MCOT128096AZ-RGBM

**Midas Components Limited Telephone** +44 (0)1493 602602 Electra House **Fax** +44 (0)1493 665111 32 Southtown Road **Email** sales@midasdisplays.com Great Yarmouth **Website** www.midasdisplays.com Norfolk NR31 0DU England 

## **S ecification p** 

Part Number: ~~oe~~ Version: ~~ee~~ Date: ~~a~~ 

## **Midas Displays OLED Part Number System** 

**MCO B 21605 A * V - E W I * 1 2 3 4 5 6** 7 8 9 10 1 = **MCO:** Midas Displays OLED 2 = **Blank: B** : COB (Chip on Board) **T** : TAB (Taped Automated Bonding) 3 = **No of dots: (** e.g. 240064 = 240 x 64 dots) (e.g. 21605 = 2 x 16 5mm C.H.) 4 = **Series** A to Z 5 = **Series Variant:** A to Z and 1 to 9 **– see addendum** 6 = **Operating Temp Range:  A:** -30+85° C **V:** -40+80° C **Y:** -40 +70° C **Z:** -30+70° C **X** : -40 +85° C 7 = **Character Set: Blank** : Not Applicable **E:** Multi European Font Set (English/Japanese – Western European (K) – Cyrillic (R)) 8 = **Colour: Y:** Yellow **W:** White **B:** Blue **R:** Red **G:** Green **RGB** : Full Colour 9 = **Interface: P:** Parallel **I:** I²C **S:** SPI **M:** Multi 10 = **Voltage Variant:** e.g. **3** = 3v 

F/Displays/Midas Brand/Midas NEW OLED Part Number System 18 June 2013 2011.doc 

## **Contents** 

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**----- Start of picture text -----**<br>
|||
|---|---|
|Contents|................................................................................................................i|
|1. Basic Specifications .................................................................................. 1~6|
|1.1 Display Specifications .................................................................................................1|
|1.2 Mechanical Specifications ...........................................................................................1|
|1.3 Active Area & Pixel Construction ...............................................................................1|
|1.4 Mechanical Drawing....................................................................................................2|
|1.5 Pin Definition...............................................................................................................3|
|1.6 Block Diagram.............................................................................................................6|
|2. Absolute Maximum Ratings|.......................................................................... 7|
|3. Optics & Electrical Characteristics......................................................... 8~12|
|3.1 Optics Characteristics ..................................................................................................8|
|3.2 DC Characteristics .......................................................................................................8|
|3.3 AC Characteristics .......................................................................................................9|
|3.3.1 68XX-Series MPU Parallel Interface Timing Characteristics...........................9|
|3.3.2 80XX-Series MPU Parallel Interface Timing Characteristics.........................10|
|3.3.3 Serial Interface Timing Characteristics (4-wire SPI).......................................11|
|3.3.4 Serial Interface Timing Characteristics (3-wire SPI).......................................12|
|4. Functional Specification ....................................................................... 13~14|
|4.1 Commands .................................................................................................................13|
|4.2 Power down and Power up Sequence........................................................................13|
|4.2.1 Power up Sequence..........................................................................................13|
|4.2.2 Power down Sequence.....................................................................................13|
|4.3 Reset Circuit...............................................................................................................13|
|4.4 Actual Application Example......................................................................................14|
|5. Reliability...................................................................................................... 15|
|5.1 Contents of Reliability Tests......................................................................................15|
|5.2 Lifetime......................................................................................................................15|
|5.3 Failure Check Standard..............................................................................................15|
|6. Outgoing Quality Control Specifications.............................................. 16~20|
|6.1 Environment Required...............................................................................................16|
|6.2 Sampling Plan............................................................................................................16|
|6.3 Criteria & Acceptable Quality Level .........................................................................16|
|6.3.1 Cosmetic Check (Display Off) in Non-Active Area........................................16|
|6.3.2 Cosmetic Check (Display Off) in Active Area.................................................19|
|6.3.3 Pattern Check (Display On) in Active Area.....................................................20|
|7. Package Specifications ................................................................................ 21|

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_**8. Precautions When Using These OEL Display Modules....................... 22~24**_ 8.1 Handling Precautions.................................................................................................22 8.2 Storage Precautions....................................................................................................23 8.3 Designing Precautions ...............................................................................................23 8.4 Precautions when disposing of the OEL display modules.........................................24 8.5 Other Precautions.......................................................................................................24 

## _**1. Basic Specifications**_ 

## **1.1 Display Specifications** 

- 1) Display Mode: Passive Matrix 2) Display Color: 262,144 Colors (Maximum) 3) Drive Duty: 1/96 Duty 

## **1.2 Mechanical Specifications** 

- 1) Outline Drawing: According to the annexed outline drawing 2) Number of Pixels: 128 (RGB) × 96 

- 3) Panel Size: 33.70 × 26.90 × 1.60 (mm) 

- 4) Active Area: 25.708 × 19.28 (mm) 

- 5) Pixel Pitch: 0.067 × 0.201 (mm) 

- 6) Pixel Size: 0.047 × 0.185 (mm) 

- 7) Weight: 2.92 (g) 

## **1.3 Active Area & Pixel Construction** 

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P0.067x(128x3)-0.02=16.067 (A/A)<br>A Lf<br>0.201<br>0.181<br>0.067<br>0.047<br>R G B<br>! “1 a |<br>Segment C127<br>(  Column 384  )<br>Segment A0<br>(  Column 1  )<br>Common 64<br>Common 0 (  Row 95  ) Detail "A"<br>(  Row 96  ) Common 111 Scale (10:1)<br>Common 47 (  Row 1  )<br>(  Row 2  )<br>0.201 0.185<br>P0.201x96-0.016=12.05 (A/A)<br>**----- End of picture text -----**<br>


1 

## **1.4 Mechanical Drawing** 

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**----- Start of picture text -----**<br>
| f<br>ri ry<br>wt ra<br>0.185<br>T 7 7 0.201<br>(28.5)<br>(1.6)<br>(24.01)<br>(16.3)<br>1<br>'<br>(35.6)<br>(8.7)<br>(5.4)<br>!<br>r<br>4±0.5 (Stiffener)<br>Glue<br>|—_ i _} ry<br>1 ji 7 1 f ry<br>Remove Tape Polarizer Protective Film Contact Side<br>t=0.15mm Max t=0.2mm 25x6.7x0.1mm<br>8<br>1<br>rT y |<br>1i,<br>\<br>i ' 1<br>it<br>;<br>| 1|<br>11 !<br>3<br>(2.8) P0.201x96-0.016=19.28 (A/A) 3.139<br>(1.8) 21.28 (V/A) 4.365<br>0.5±0.5 23.5 (Polarizer) 5.35±0.1<br>24.9±0.2 (Cap Size) 7.71<br>26.9±0.2 (Panel Size) 14.35±0.2<br>(41.25)<br>Rev. A Size<br>Symbol N.C. (GND) VCC VCOMH VDDIO VSL N.C. D7 D6 D5 D4 D3 D2 D1 D0 E/RD# R/W# BS0 BS1 CS# D/C RES# IREF GPIO1 GPIO0 N.C. VDD VCI VSS N.C. N.C. (GND)<br>Remark<br>Original Drawing Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 DFE2896CNCF13 Soda Lime / Polyimide<br> )  )  ) P.M.<br>(  Row 95 (  Row 1 Cherry Lin 20080815<br>Date (  Column 384 Common 64 Common 111<br>20080815 Segment C127<br> ) GBR Detail "A" Scale (10:1) Ivy Lo<br>Item A Segment A0 (  Column 1  )  ) 0.201 0.181 20080815<br>Common 0 (  Row 96 Common 47 (  Row 2 0.067 0.047<br>Sean Lai 20080815<br>(2.3)<br>20080815<br>Humphrey Lin<br>(1.6) (Reference Mechnical Design)<br>±1<br>1.6±0.1 0.3±0.03 0.80 Max<br>Signature<br>Customer Approval<br>5<br>2-R0.5±0.05<br>10<br>30<br> 96 Pixels<br>x 15.5±0.2 24±0.1 27.83±0.2<br>32.7 (Polarizer) 27.708 (V/A)<br>33.7±0.2 (Panel Size) 33.7±0.2 (Cap Size)<br>P0.067x(128x3)-0.02=25.708 (A/A) Active Area 1.27" 1 P0.50x(30-1)=14.5±0.05 (W0.30±0.03)<br>128(RGB)<br>"A"<br>0.5±0.5 (2.996) (3.996) (2.935)<br>Notes: 1. Driver IC: SSD1351 2. Die Size: 10700um x 1500um 3. COF Number: SSD1351U3 4. Interface:     8-bits 68XX/80XX Parallel, 3-/4-wire SPI 5. General Tolerance: ±0.30 6. The total thickness (1.70 Max) is without polarizer protective film & remove tape.     The actual assembled total thickness with above materials should be 1.95 Max.<br>N.C. (GND)N.C. (GND)VCOMHVDDIOE/RD#GPIO0GPIO1R/W#RES#VDDD/C#IREFVCCVSLN.C.N.C.N.C.VSSVCICS#BS1BS0D0D1D2D3D4D5D6D7<br>**----- End of picture text -----**<br>


2 

## **1.5 Pin Definition** 

|**Pin Number**|**Symbol**|**Type**|**Function**|
|---|---|---|---|
|**_Power Supply_**||||
|27<br>26<br>4<br>28<br>2|VCI<br>VDD<br>VDDIO<br>VSS<br>VCC|P<br>P<br>P<br>P<br>P|**_Power Supply for Operation_**<br>This is a voltage supply pin.  It must be connected to<br>external source & always be equal to or higher than VDD<br>& VDDIO.<br>**_Power Supply for Core Logic Circuit_**<br>This is a voltage supply pin which is regulated internally<br>from VCI.  A capacitor should be connected between<br>this pin & VSS under all circumstances.<br>**_Power Supply for I/O Pin_**<br>This pin is a power supply pin of I/O buffer.  It should<br>be connected to VCI or external source.  All I/O signal<br>should have VIH reference to VDDIO.  When I/O signal<br>pins (BS0~BS1, D0~D7, control signals…) pull high,<br>they should be connected to VDDIO.<br>**_Ground of OEL System_**<br>This is a ground pin.  It also acts as a reference for the<br>logic pins, the OEL driving voltages, and the analog<br>circuits.  It must be connected to external ground.<br>**_Power Supply for OEL Panel_**<br>This is the most positive voltage supply pin of the chip.<br>Itmust be connected to externalsource.|
|**_Driver_**||||
|22<br>3<br>5|IREF<br>VCOMH<br>VSL|I<br>P<br>P|**_Current Reference for Brightness Adjustment_**<br>This pin is segment current reference pin.  A resistor<br>should be connected between this pin and VSS.  Set the<br>current lower than 12.5uA.<br>**_Voltage Output High Level for COM Signal_**<br>This pin is the input pin for the voltage output high level<br>for COM signals.  A tantalum capacitor should be<br>connected between this pin and VSS.<br>**_Voltage Output Low Level for SEG Signal_**<br>This is segment voltage reference pin.<br>When external VSL is not used, this pin should be left<br>open.<br>When external VSL is used, this pin should connect with<br>resistorand diodeto ground.|
|**_External IC Control_**||||
|24<br>23|GPIO0<br>GPIO1|I/O|**_General Purpose Input/Output_**<br>These pins could be left open individually or have signal<br>inputted/outputted.  They are able to use as the external<br>DC/DC converter circuit enabled/disabled control or other<br>applications.|



3 

## **1.5 Pin Definition (Continued)** 

|**Pin Number**|**Symbol**|**I/O**|**Function**|
|---|---|---|---|
|**_Interface_**||||
|17<br>18<br>21<br>19<br>20<br>15<br>16<br>7~14|BS0<br>BS1<br>RES#<br>CS#<br>D/C#<br>E/RD#<br>R/W#<br>D7~D0|I<br>I<br>I<br>I<br>I<br>I<br>I/O|**_Communicating Protocol Select_**<br>These pins are MCU interface selection input.  See the<br>following table:<br>BS0<br>BS1<br>3-wire SPI<br>1<br>0<br>4-wire SPI<br>0<br>0<br>68XX-parallel (8-bit)<br>1<br>1<br>80XX-parallel(8-bit)<br>0<br>1<br>**_Power Reset for Controller and Driver_**<br>This pin is reset signal input.  When the pin is low,<br>initialization of the chip is executed.<br>**_Chip Select_**<br>This pin is the chip select input.  The chip is enabled for<br>MCU communication only when CS# is pulled low.<br>**_Data/Command Control_**<br>This pin is Data/Command control pin.  When the pin is<br>pulled high, the input at D7~D0 is treated as display data.<br>When the pin is pulled low, the input at D7~D0 will be<br>transferred to the command register.  For detail<br>relationship to MCU interface signals, please refer to the<br>Timing Characteristics Diagrams.<br>When 3-wire serial mode is selected, this pin must be<br>connected to VSS.<br>**_Read/Write Enable or Read_**<br>This pin is MCU interface input.  When interfacing to a<br>68XX-series microprocessor, this pin will be used as the<br>Enable (E) signal. Read/write operation is initiated when<br>this pin is pulled high and the CS# is pulled low.<br>When connecting to an 80XX-microprocessor, this pin<br>receives the Read (RD#) signal.  Data read operation is<br>initiated when this pin is pulled low and CS# is pulled<br>low.<br>When serial mode is selected, this pin must be connected<br>to VSS.<br>**_Read/Write Select or Write_**<br>This pin is MCU interface input.  When interfacing to a<br>68XX-series microprocessor, this pin will be used as<br>Read/Write (R/W#) selection input.  Pull this pin to<br>“High” for read mode and pull it to “Low” for write<br>mode.<br>When 80XX interface mode is selected, this pin will be<br>the Write (WR#) input.  Data write operation is initiated<br>when this pin is pulled low and the CS# is pulled low.<br>When serial mode is selected, this pin must be connected<br>to VSS.<br>**_Host Data Input/Output Bus_**<br>These pins are 8-bit bi-directional data bus to be<br>connected to the microprocessor’s data bus.  When serial<br>mode is selected, D1 will be the serial data input SDIN<br>and D0 will be the serial clock input SCLK.<br>Unusedpins must be connected to VSS except for D2.<br>~~D~~AS.<br>~~—~~_|



4 

## **1.5 Pin Definition (Continued)** 

|**Pin Number**|**Symbol**|**I/O**|**Function**|
|---|---|---|---|
|**_Reserve_**||||
|6, 25, 29<br>1, 30|N.C.<br>N.C. (GND)|-<br>-|**_Reserved Pin_**<br>The N.C. pins between function pins are reserved for<br>compatible and flexible design.<br>**_Reserved Pin (Supporting Pin)_**<br>The supporting pins can reduce the influences from<br>stresses on the function pins.  These pins must be<br>connected to externalground.|



5 

## **1.6 Block Diagram** 

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Active Area 1.27"<br>128(RGB)  x  96 Pixels<br>~ ~ ~ ~ ~<br>SSD1351<br>baad ~ 1 pedadautaiad aa 1<br>i<br>C4<br>C3<br>C1<br>C2<br>R1<br>R2 D1<br>C7<br>C5<br>C6<br>Common 47 Common 0 Segment A0 Segment C127 Common 64 Common 111<br>VCC VCOMH VDDIO VSL D7 D0 E/RD# R/W# BS0 BS1 CS# D/C# RES# IREF GPIO1 GPIO0 VDD VCI VSS<br>**----- End of picture text -----**<br>


MCU Interface Selection: BS0 and BS1 Pins connected to MCU interface: D7~D0, E/RD#, R/W#, CS#, D/C#, and RES# 

C1, C5: 0.1 μ F C2: 4.7 μ F C6: 10 μ F C3, C4: 1 μ F C7: 4.7uF / 25V Tantalum Capacitor R1: 560k Ω , R1 = (Voltage at IREF – VSS) / IREF R2: 50 Ω , 1/4W D1: ≤ 1.4V, 0.5W 

6 

## _**2. Absolute Maximum Ratings**_ 

|**Parameter**|**Symbol**|**Min**|**Max**|**Unit**|**Notes**|
|---|---|---|---|---|---|
|Supply Voltage for Operation<br>Supply Voltage for Logic<br>Supply Voltage for I/O Pins<br>Supply Voltage for Display<br>Operating Temperature<br>Storage Temperature|VCI<br>VDD<br>VDDIO<br>VCC<br>TOP<br>TSTG|-0.3<br>-0.5<br>-0.5<br>-0.5<br>-30<br>-40|4<br>2.75<br>VCI<br>16<br>70<br>80|V<br>V<br>V<br>V<br>°C<br>°C|1, 2<br>1, 2<br>1, 2<br>1, 2<br>-<br>-|



Note 1: All the above voltages are on the basis of “VSS = 0V”. 

Note 2: When this module is used beyond the above absolute maximum ratings, permanent breakage of the module may occur.  Also, for normal operations, it is desirable to use this module under the conditions according to Section 3. “Optics & Electrical Characteristics”.  If this module is used beyond these conditions, malfunctioning of the module can occur and the reliability of the module may deteriorate. 

7 

## _**3. Optics & Electrical Characteristics**_ 

## **3.1 Optics Characteristics** 

|**3.1 Optics Characteristics**|||||||
|---|---|---|---|---|---|---|
|**Characteristics**|**Symbol**|**Conditions**|**Min**|**Typ Max Unit**|**Max Unit**|**Max Unit**|
|Brightness (White)<br>C.I.E. (White)<br>C.I.E. (Red)<br>C.I.E. (Green)<br>C.I.E. (Blue)<br>Dark Room Contrast<br>View Angle|Lbr<br>(x)<br>(y)<br>(x)<br>(y)<br>(x)<br>(y)<br>(x)<br>(y)<br>CR|With Polarizer<br>(Note 3)<br>With Polarizer<br>With Polarizer<br>With Polarizer<br>With Polarizer|80<br>0.26<br>0.29<br>0.60<br>0.30<br>0.27<br>0.58<br>0.10<br>0.12<br>-<br>>160|100<br>0.30<br>0.33<br>0.64<br>0.34<br>0.31<br>0.62<br>0.14<br>0.16<br>>2000:1<br>-|-<br>0.34<br>0.37<br>0.68<br>0.38<br>0.35<br>0.66<br>0.18<br>0.20<br>>2000:1<br>-<br>-|cd/m2<br>degree|



* Optical measurement taken at VCI = 2.8V, VCC = 12V. Software configuration follows Section 4.4 Initialization. 

## **3.2 DC Characteristics** 

|**3.2 DC Characteristics**|||||||
|---|---|---|---|---|---|---|
|**Characteristics**|**Symbol**|**Conditions**|**Min**|**Typ Max Unit**|**Max Unit**|**Max Unit**|
|Supply Voltage for Operation<br>Supply Voltage for Logic<br>Supply Voltage for I/O Pins<br>Supply Voltage for Display<br>High Level Input<br>Low Level Input<br>High Level Output<br>Low Level Output<br>Operating Current for VCI<br>Operating Current for VCC<br>Sleep Mode Current for VCI<br>SleepMode Current for VCC|VCI<br>VDD<br>VDDIO<br>VCC<br>VIH<br>VIL<br>VOH<br>VOL<br>ICI<br>ICC<br>ICI, SLEEP<br>ICC, SLEEP|Note 3<br>Iout= 100μA, 3.3MHz <br>Iout= 100μA, 3.3MHz<br>Note 4<br>Note 5|2.4<br>2.4<br>1.65<br>11.5<br>0.8×VDDIO<br>0<br> 0.9×VDDIO<br>0<br>-<br>-<br>-<br>-<br>-|2.8<br>2.5<br>1.8<br>12<br>-<br>-<br>-<br>-<br>240<br>16.1<br>27.0<br>1<br>1|3.5<br>2.6<br>VCI<br>12.5<br>VDDIO<br>0.2×VDDIO<br>VDDIO<br>0.1×VDDIO<br>300<br>20.1<br>33.8<br>5<br>5|V<br>V<br>V<br>V<br>V<br>V<br>V<br>V<br>μA<br>mA<br>mA<br>μA<br>μA|



Note 3: Brightness (Lbr) and Supply Voltage for Display (VCC) are subject to the change of the panel characteristics and the customer’s request. 

Note 4: VCI = 2.8V, VCC = 12V, 50% Display Area Turn on. 

Note 5: VCI = 2.8V, VCC = 12V, 100% Display Area Turn on. 

* Software configuration follows Section 4.4 Initialization. 

8 

## **3.3 AC Characteristics** 

3.3.1 68XX-Series MPU Parallel Interface Timing Characteristics: 

|**Symbol Descri**|**mbol Description**|**Min**|**Max**|**Unit**|
|---|---|---|---|---|
|tcycle<br>tAS<br>tAH<br>tDSW<br>tDHW<br>tDHR<br>tOH<br>tACC<br>PWCSL<br>PWCSH<br>tR<br>tF|Clock Cycle Time<br>Address Setup Time<br>Address Hold Time<br>Write Data Setup Time<br>Write Data Hold Time<br>Read Data Hold Time<br>Output Disable Time<br>Access Time<br>Chip Select Low Pulse Width (Read)<br>Chip Select Low Pulse Width (Write)<br>Chip Select High Pulse Width (Read)<br>Chip Select High Pulse Width (Write)<br>Rise Time<br>Fall Time|300<br>10<br>0<br>40<br>7<br>20<br>-<br>-<br>120<br>60<br>60<br>60<br>-<br>-|-<br>-<br>-<br>-<br>-<br>-<br>70<br>140<br>-<br>-<br>15<br>15|ns<br>ns<br>ns<br>ns<br>ns<br>ns<br>ns<br>ns<br>ns<br>ns<br>ns<br>ns|



- (1) When 8-bit Used: D[7:0] Instead 

9 

## 3.3.2 80XX-Series MPU Parallel Interface Timing Characteristics: 

|**Symbol Descri**|**mbol Description**|**Min**|**Max**|**Unit**|
|---|---|---|---|---|
|tcycle<br>tAS<br>tAH<br>tDSW<br>tDHW<br>tDHR<br>tOH<br>tACC<br>tPWLR<br>tPWLW<br>tPWHR<br>tPWHW<br>tCS<br>tCSH<br>tCSF<br>tR<br>tF|Clock Cycle Time<br>Address Setup Time<br>Address Hold Time<br>Write Data Setup Time<br>Write Data Hold Time<br>Read Data Hold Time<br>Output Disable Time<br>Access Time<br>Read Low Time<br>Write Low Time<br>Read High Time<br>Write High Time<br>Chip Select Setup Time<br>Chip Select Hold Time to Read Signal<br>Chip Select Hold Time<br>Rise Time<br>Fall Time|300<br>10<br>0<br>40<br>7<br>20<br>-<br>-<br>150<br>60<br>60<br>60<br>0<br>0<br>20<br>-<br>-|-<br>-<br>-<br>-<br>-<br>-<br>70<br>140<br>-<br>-<br>-<br>-<br>-<br>-<br>-<br>15<br>15|ns<br>ns<br>ns<br>ns<br>ns<br>ns<br>ns<br>ns<br>ns<br>ns<br>ns<br>ns<br>ns<br>ns<br>ns<br>ns<br>ns|



- (VDD - VSS = 2.4V to 2.6V, VDDIO = 1.65V, VCI = 2.8V, Ta = 25°C) 

- (1) When 8-bit Used: D[7:0] Instead 

10 

## 3.3.3 Serial Interface Timing Characteristics: (4-wire SPI) 

|**Symbol Descri**|**mbol Description**|**Min**|**Max**|**Unit**|
|---|---|---|---|---|
|tcycle<br>tAS<br>tAH<br>tCSS<br>tCSH<br>tDSW<br>tDHW<br>tCLKL<br>tCLKH<br>tR<br>tF|Clock Cycle Time<br>Address Setup Time<br>Address Hold Time<br>Chip Select Setup Time<br>Chip Select Hold Time<br>Write Data Setup Time<br>Write Data Hold Time<br>Clock Low Time<br>Clock High Time<br>Rise Time<br>Fall Time|50<br>15<br>15<br>20<br>10<br>15<br>15<br>20<br>20<br>-<br>-|-<br>-<br>-<br>-<br>-<br>-<br>-<br>-<br>-<br>15<br>15|ns<br>ns<br>ns<br>ns<br>ns<br>ns<br>ns<br>ns<br>ns<br>ns<br>ns|



- (VDD - VSS = 2.4V to 2.6V, VDDIO = 1.65V, VCI = 2.8V, Ta = 25°C) 

11 

## 3.3.4 Serial Interface Timing Characteristics: (3-wire SPI) 

|**Symbol Descri**|**mbol Description**|**Min**|**Max**|**Unit**|
|---|---|---|---|---|
|tcycle<br>tCSS<br>tCSH<br>tDSW<br>tDHW<br>tCLKL<br>tCLKH<br>tR<br>tF|Clock Cycle Time<br>Chip Select Setup Time<br>Chip Select Hold Time<br>Write Data Setup Time<br>Write Data Hold Time<br>Clock Low Time<br>Clock High Time<br>Rise Time<br>Fall Time|50<br>20<br>10<br>15<br>15<br>20<br>20<br>-<br>-|-<br>-<br>-<br>-<br>-<br>-<br>-<br>15<br>15|ns<br>ns<br>ns<br>ns<br>ns<br>ns<br>ns<br>ns<br>ns|



* (VDD - VSS = 2.4V to 2.6V, VDDIO = 1.65V, VCI = 2.8V, Ta = 25°C) 

12 

## _**4. Functional Specification**_ 

## **4.1. Commands** 

Refer to the Technical Manual for the SSD1351 

## **4.2 Power down and Power up Sequence** 

To protect OEL panel and extend the panel life time, the driver IC power up/down routine should include a delay period between high voltage and low voltage power sources during turn on/off.  It gives the OEL panel enough time to complete the action of charge and discharge before/after the operation. 

## 4.2.1 Power up Sequence: 

**==> picture [380 x 225] intentionally omitted <==**

**----- Start of picture text -----**<br>
VCI ,VDDIO on<br>1. Power up VCI & VDDIO VCC on<br>2. Send Display off command  Display on<br>3. Initialization<br>4. Clear Screen  VCC<br>5. Power up VCC VCI/VDDIO<br>6. Delay 100ms<br>(when VCC is stable)  VSS/Ground<br>7. Send Display on command<br>Display off<br>VCC off<br>1. Send Display off command  VCI ,VDDIO off<br>2. Power down VCC<br>3. Delay 100ms  VCC<br>(when VCC is reach 0 and panel is  VCI/VDDIO<br>completely discharges)<br>VSS/Ground<br>**----- End of picture text -----**<br>


- 4.2.2 Power down Sequence: 

   4. Power down VCI & VDDIO 

## **4.3 Reset Circuit** 

When RES# input is low, the chip is initialized with the following status: 

1. Display is OFF 

2. 128(RGB) × 128 Display Mode 

3. Normal segment and display data column and row address mapping (SEG0 mapped to column address 00h and COM0 mapped to row address 00h) 

4. Display start line is set at display RAM address 0 

5. Column address counter is set at 0 

6. Normal scan direction of the COM outputs 

7. Command A2h, B1h, B3h, BBh, BEh are locked by command FDh 

13 

## **4.4 Actual Application Example** 

Command usage and explanation of an actual example 

## <Initialization> 

**==> picture [413 x 570] intentionally omitted <==**

**----- Start of picture text -----**<br>
Command Lock  Function Selection  Enhance Driving Scheme Capability<br>0xFD, 0x12 0xAB, 0x01 0xB2, 0xA4, 0x00, 0x00<br>Command Lock  Set Segment Low Voltage Set Pre-Charge Voltage<br>0xFD, 0xB1 0xB4, 0xA0, 0xB5, 0x55 0xBB, 0x17<br>Set Sleep Mode On  Set Contrast Current  Set Second Pre-Charge Period<br>0xAE 0xC1, 0xC8, 0x80, 0x8A 0xB6, 0x01<br>Set Display Clock Divide Ratio/Oscillator Frequency  Set Master Current Control Set VCOMH Voltage<br>0xB3, 0xF1 0xC7, 0x0F 0xBE, 0x05<br>Gamma Look up Table<br>Set Multiplex Ratio  Set Display Mode<br>0xB8,<br>0xCA, 0x5F 0xA6<br>0x02, 0x03, 0x04, 0x05,<br>0x06, 0x07, 0x08, 0x09,<br>0x0A, 0x0B, 0x0C, 0x0D,<br>0x0E, 0x0F, 0x10, 0x11,<br>Set Display Offset<br>0x12, 0x13, 0x15, 0x17, Clear Screen<br>0xA2, 0x00<br>0x19, 0x1B, 0x1D, 0x1F,<br>0x21, 0x23, 0x25, 0x27,<br>0x2A, 0x2D, 0x30, 0x33,<br>0x36, 0x39, 0x3C, 0x3F,<br>Set Display Start Line  Set Sleep Mode Off<br>0xA1, 0x00 0x42, 0x45, 0x48, 0x4C, 0xAF<br>0x50, 0x54, 0x58, 0x5C,<br>0x60, 0x64, 0x68, 0x6C,<br>0x70, 0x74, 0x78, 0x7D,<br>0x82, 0x87, 0x8C, 0x91,<br>Set Re-Map & Color Depth<br>0x96, 0x9B, 0xA0, 0xA5,<br>0xA0, 0xB4<br>0xAA, 0xAF, 0xB4, 0x00,<br>Set GPIO  Set Phase Length<br>0xB5, 0x00 0xB1, 0x32<br>LP<br>If the noise is accidentally occurred at the displaying window during the operation,<br>please reset the display in order to recover the display function.<br>**----- End of picture text -----**<br>


14 

## _**5. Reliability**_ 

## **5.1 Contents of Reliability Tests** 

|**5.1 Contents of Reliability Tests**|||
|---|---|---|
|**Item**|**Conditions**|**Criteria**|
|High Temperature Operation<br>Low Temperature Operation<br>High Temperature Storage<br>Low Temperature Storage<br>High Temperature/Humidity Operation <br>Thermal Shock|70°C, 240 hrs<br>-30°C, 240 hrs<br>80°C, 240 hrs<br>-40°C, 240 hrs<br> 60°C, 90% RH, 120 hrs<br>-40°C⇔85°C, 24 cycles<br>60 mins dwell|The operational<br>functions work.|



- The samples used for the above tests do not include polarizer. 

- No moisture condensation is observed during tests. 

## **5.2 Lifetime** 

End of lifetime is specified as 50% of initial brightness. 

|**Parameter**|**Min**|**Max**|**Unit**|**Condition**|**Notes**|
|---|---|---|---|---|---|
|Operating Life Time<br>Storage Life Time|10,000<br>20,000|-<br>-|hr<br>hr|100 cd/m2, 50% Checkerboard<br>Ta= 25°C,50% RH|6<br>-|



Note 6:  The average operating lifetime at room temperature is estimated by the accelerated operation at high temperature conditions. 

## **5.3 Failure Check Standard** 

After the completion of the described reliability test, the samples were left at room temperature for 2 hrs prior to conducting the failure test at 23 ± 5 ° C; 55 ± 15% RH. 

15 

## _**6. Outgoing Quality Control Specifications**_ 

## **6.1 Environment Required** 

Customer’s test & measurement are required to be conducted under the following conditions: 

|**6.1 Environment Required**<br>Customer’s test & measurement are required to be conducted under the following<br>conditions:|Customer’s test & measurement are required to be conducted under the following|
|---|---|
|Temperature:|23±5°C|
|Humidity:|55±15 %RH|
|Fluorescent Lamp:|30W|
|Distance between the Panel & Lamp:|≥50 cm|
|Distance between the Panel & Eyes of the Inspector:|≥30 cm|
|Finger glove (or finger cover) must be worn by the inspector.||
|Inspection table or jig must be anti-electrostatic.||



## **6.2 Sampling Plan** 

Level II, Normal Inspection, Single Sampling, MIL-STD-105E 

## **6.3 Criteria & Acceptable Quality Level** 

**==> picture [410 x 422] intentionally omitted <==**

**----- Start of picture text -----**<br>
Partition  AQL  Definition<br>Major  0.65  Defects in Pattern Check (Display On)<br>Minor  1.0  Defects in Cosmetic Check (Display Off)<br>6.3.1 Cosmetic Check (Display Off) in Non-Active Area<br>Check Item  Classification Criteria<br>X > 6 mm (Along with Edge)<br>Y > 1 mm (Perpendicular to edge)<br>X<br>Panel  Minor  Y<br>General Chipping<br>X<br>Y<br>A<br>ig<br>16<br>**----- End of picture text -----**<br>


## 6.3.1 Cosmetic Check (Display Off) in Non-Active Area (Continued) 

|**Check Item**|**Classification**|**Criteria**|
|---|---|---|
|Panel Crack<br>Cupper Exposed<br>(Even Pin or Film)<br>Film or Trace Damage<br>Terminal Lead Twist<br>Terminal Lead Broken<br>Terminal Lead Prober<br>Mark|Minor<br>Minor<br>Minor<br>Minor<br>Minor<br>Acceptable|Any crack is not allowable.<br>Not Allowable by Naked Eye<br>Inspection<br>Not Allowable<br>Not Allowable<br>“fj<br>iar<br>a<br>~<br>ca<br>nh<br>D. TWISTED LEAD<br>f<br>‘<br>t4<br>t4<br>il<br>||<br>1|<br>\t<br>4!<br>4<br>‘<br>%?<br>“<br>7<br>‘f<br>~<br>f<br>~<br>ae<br>~~<br>pe<br>“<br>BROKEN<br>LEAD<br>a*<br>i‘<br>i4<br>i\<br>4I<br>1jl<br>i4<br>‘t<br>4‘<br>7<br>o<br>—<br>ma<br>Se<br>a<br>|<br>B|



17 

## 6.3.1 Cosmetic Check (Display Off) in Non-Active Area (Continued) 

**==> picture [371 x 473] intentionally omitted <==**

**----- Start of picture text -----**<br>
Check Item  Classification Criteria<br>NG if any bent lead cause lead<br>shorting.<br>/¢ZooaXN\\\<br>Ne LEAD SHORTING \<br>Minor  } i<br>t \ \<br>| \ {<br>\ /<br>\ /<br>\ /<br>\ /<br>\ /<br>\ /<br>» 7<br>SA a<br>Terminal Lead Bent<br>(Not Twist or Broken)<br>NG for horizontally bent lead more<br>than 50% of its width.<br>a<br>ra o aN™y<br>/ rs<br>i \<br>/ \<br>Minor  f<br>{ [\]<br>{<br>1 [t]<br>\<br>\f<br>\<br>\/<br>\ _ "4<br>we bY”<br>be of<br>‘ae<br>(ui =; 2 (ae ps3 ue<br>Glue or Contamination<br>on Pin<br>Minor<br>(Couldn’t Be Removed  mH i iN oS Be<br>; ; eB) : ARS : ~y<br>by Alcohol)<br>| \ Su OB:<br>Ink Marking on Back<br>Side of panel  Acceptable Ignore for Any<br>(Exclude on Film)<br>**----- End of picture text -----**<br>


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## 6.3.2 Cosmetic Check (Display Off) in Active Area 

It is recommended to execute in clear room environment (class 10k) if actual in necessary. 

|It is recommended to execute in clear room environment (class 10k) if actual<br>in necessary.y..|It is recommended to execute in clear room environment (class 10k) if actual|It is recommended to execute in clear room environment (class 10k) if actual|
|---|---|---|
|**Check Item**|**Classification**|**Criteria**|
|Any Dirt & Scratch on<br>Protective Film<br>Scratches, Fiber, Line-Shape<br>Defect<br>(On Polarizer)<br>Dirt, Spot-Shape Defect<br>(On Polarizer)<br>Dent, Bubbles, White spot<br>(Any Transparent Spot on<br>Polarizer)<br>Fingerprint, Flow Mark<br>(On Polarizer)<br>~~So~~|Acceptable<br>Minor<br>Minor<br>Minor<br>Minor|Ignore for Any<br>W≤0.1<br>Ignore<br>W > 0.1, L≤2<br>n≤1<br>L > 2<br>n = 0<br>Φ ≤0.1<br>Ignore<br>0.1 <Φ ≤0.25<br>n≤1<br>0.25 <Φ<br>n = 0<br>Φ ≤0.5<br>Ignore if no Influence on<br>Display<br>0.5<Φ<br>n =0<br>Not allowable<br>>|



- Protective film should not be tear off when cosmetic check. 

**==> picture [322 x 124] intentionally omitted <==**

**----- Start of picture text -----**<br>
** Definition of W & L &  Φ  (Unit: mm):  Φ  = (a + b) / 2<br>L<br>b: Minor Axis<br>W<br>a: Major Axis<br>**----- End of picture text -----**<br>


19 

## 6.3.3 Pattern Check (Display On) in Active Area 

|6.3.3 Pattern Check (Display On) in Active Area|6.3.3 Pattern Check (Display On) in Active Area||
|---|---|---|
|**Check Item**|**Classification**|**Criteria**|
|No Display<br>Bright Line<br>Missed Line<br>Pixel Short<br>Darker Pixel<br>Wrong Display<br>Un-Uniform (Luminance<br>Variation within a Display)|Major<br>Major<br>Major<br>Major<br>Major<br>Major<br>Major|Not allowable<br>ACEaet i|



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## _**7. Package Specifications**_ 

**==> picture [387 x 422] intentionally omitted <==**

**----- Start of picture text -----**<br>
EPE COVER FOAM 351x212x1,<br>ANTISTATIC x 1 Pcs<br>x 1 pcs (Empty) B<br>16 Pcs Tray Vacuum packing<br>eS |<br>A<br>Module<br>EPE PROTECTTIVE<br>e e: e , a e a y x 15 pcs Staggered Stacking Za NA AN S S&S A j<br>S H ~<br>Tray 420x285 T=0.8mm<br>MLE EE Exsiccator x 2 pcs Primary Box C SET<br>B<br>Brimary Box 4 SET<br>Wrapped with adhesive tape<br>x 16 pcs<br>Vacuum packing bag<br>: |<br>EPE PROTECTTIVE<br>370mm x 280mm x 20mmFl<br>a | A<br>CARTON BOX<br>Label<br>C<br>Primary L450mm x W296 x H110, B wave<br>x 4Pcs<br>Part ID :<br>Lot ID :<br>Label<br>Q'ty :<br>QC :<br>(Major / Maximum)<br>Carton Box L464mm x W313mm x H472mm, AB wave<br>**----- End of picture text -----**<br>


|**Item**|**Quantity**|
|---|---|
|HoldingTrays<br>(A)|**Quantity**<br>15<br>per PrimaryBox|
|Total Trays<br>(B)<br>Primary Box<br>(C)|16<br>per Primary Box (Including 1 Empty Tray)<br>1~4<br>per Carton (4 as Major / Maximum)|



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## _**8. Precautions When Using These OEL Display Modules**_ 

## **8.1 Handling Precautions** 

- 1) Since the display panel is being made of glass, do not apply mechanical impacts such us dropping from a high position. 

- 2) If the display panel is broken by some accident and the internal organic substance leaks out, be careful not to inhale nor lick the organic substance. 

- 3) If pressure is applied to the display surface or its neighborhood of the OEL display module, the cell structure may be damaged and be careful not to apply pressure to these sections. 

- 4) The polarizer covering the surface of the OEL display module is soft and easily scratched.  Please be careful when handling the OEL display module. 

- 5) When the surface of the polarizer of the OEL display module has soil, clean the surface.  It takes advantage of by using following adhesion tape. 

   - Scotch Mending Tape No. 810 or an equivalent 

   - Never try to breathe upon the soiled surface nor wipe the surface using cloth containing solvent such as ethyl alcohol, since the surface of the polarizer will become cloudy. 

   - Also, pay attention that the following liquid and solvent may spoil the polarizer: 

   - Water 

   - Ketone 

   - Aromatic Solvents 

- 6) Hold OEL display module very carefully when placing OEL display module into the system housing. Do not apply excessive stress or pressure to OEL display module.  And, do not over bend the film with electrode pattern layouts. These stresses will influence the display performance.  Also, secure sufficient rigidity for the outer cases. 

- 7) Do not apply stress to the LSI chips and the surrounding molded sections. 

- 8) Do not disassemble nor modify the OEL display module. 

- 9) Do not apply input signals while the logic power is off. 

- 10) Pay sufficient attention to the working environments when handing OEL display modules to prevent occurrence of element breakage accidents by static electricity. 

   - Be sure to make human body grounding when handling OEL display modules. 

   - Be sure to ground tools to use or assembly such as soldering irons. 

   - To suppress generation of static electricity, avoid carrying out assembly work under dry environments. 

   - Protective film is being applied to the surface of the display panel of the OEL display module.  Be careful since static electricity may be generated when exfoliating the protective film. 

- 11) Protection film is being applied to the surface of the display panel and removes 

22 

the protection film before assembling it.  At this time, if the OEL display module has been stored for a long period of time, residue adhesive material of the protection film may remain on the surface of the display panel after removed of the film.  In such case, remove the residue material by the method introduced in the above Section 5). 

- 12) If electric current is applied when the OEL display module is being dewed or when it is placed under high humidity environments, the electrodes may be corroded and be careful to avoid the above. 

## **8.2 Storage Precautions** 

- 1) When storing OEL display modules, put them in static electricity preventive bags avoiding exposure to direct sun light nor to lights of fluorescent lamps, etc. and, also, avoiding high temperature and high humidity environments or low temperature (less than 0 ° C) environments.  (We recommend you to store these modules in the packaged state when they were shipped from Midas Displays. At that time, be careful not to let water drops adhere to the packages or bags nor let dewing occur with them. 

- 2) If electric current is applied when water drops are adhering to the surface of the OEL display module, when the OEL display module is being dewed or when it is placed under high humidity environments, the electrodes may be corroded and be careful about the above. 

## **8.3 Designing Precautions** 

- 1) The absolute maximum ratings are the ratings which cannot be exceeded for OEL display module, and if these values are exceeded, panel damage may be happen. 

- 2) To prevent occurrence of malfunctioning by noise, pay attention to satisfy the VIL and VIH specifications and, at the same time, to make the signal line cable as short as possible. 

- 3) We recommend you to install excess current preventive unit (fuses, etc.) to the power circuit (VCI).  (Recommend value: 0.5A) 

- 4) Pay sufficient attention to avoid occurrence of mutual noise interference with the neighboring devices. 

- 5) As for EMI, take necessary measures on the equipment side basically. 

- 6) When fastening the OEL display module, fasten the external plastic housing section. 

- 7) If power supply to the OEL display module is forcibly shut down by such errors as taking out the main battery while the OEL display panel is in operation, we cannot guarantee the quality of this OEL display module. 

- 8) The electric potential to be connected to the rear face of the IC chip should be as follows: SSD1351 

   - Connection (contact) to any other potential than the above may lead to rupture of the IC. 

23 

## **8.4 Precautions when disposing of the OEL display modules** 

- 1) Request the qualified companies to handle industrial wastes when disposing of the OEL display modules.  Or, when burning them, be sure to observe the environmental and hygienic laws and regulations. 

## **8.5 Other Precautions** 

- 1) When an OEL display module is operated for a long of time with fixed pattern may remain as an after image or slight contrast deviation may occur. Nonetheless, if the operation is interrupted and left unused for a while, normal state can be restored.  Also, there will be no problem in the reliability of the module. 

- 2) To protect OEL display modules from performance drops by static electricity rapture, etc., do not touch the following sections whenever possible while handling the OEL display modules. 

   - Pins and electrodes 

   - Pattern layouts such as the COF 

- 3) With this OEL display module, the OEL driver is being exposed.  Generally speaking, semiconductor elements change their characteristics when light is radiated according to the principle of the solar battery.  Consequently, if this OEL driver is exposed to light, malfunctioning may occur. 

   - Design the product and installation method so that the OEL driver may be shielded from light in actual usage. 

   - Design the product and installation method so that the OEL driver may be shielded from light during the inspection processes. 

- 4) Although this OEL display module stores the operation state data by the commands and the indication data, when excessive external noise, etc. enters into the module, the internal status may be changed.  It therefore is necessary to take appropriate measures to suppress noise generation or to protect from influences of noise on the system design. 

- 5) We recommend you to construct its software to make periodical refreshment of the operation statuses (re-setting of the commands and re-transference of the display data) to cope with catastrophic noise. 

24