MC14541BDR2G

MC14541B 

## Programmable Timer 

The MC14541B programmable timer consists of a 16−stage binary counter, an integrated oscillator for use with an external capacitor and two resistors, an automatic power−on reset circuit, and output control logic. 

Timing is initialized by turning on power, whereupon the power−on reset is enabled and initializes the counter, within the specified VDD range. With the power already on, an external reset pulse can be applied. Upon release of the initial reset command, the oscillator will oscillate with a frequency determined by the external RC network. The 16−stage counter divides the oscillator frequency (fosc) with the n[th] stage frequency being fosc/2[n] . 

## **Features** 

- Available Outputs 2[8] , 2[10] , 2[13] or 2[16] 

## **http://onsemi.com** 

**SOIC−14 SOEIAJ−14 TSSOP−14 D SUFFIX F SUFFIX DT SUFFIX CASE 751A CASE 965 CASE 948G** 

## **PIN ASSIGNMENT** 

- Increments on Positive Edge Clock Transitions 

- Built−in Low Power RC Oscillator (±2% accuracy over temperature range and ±20% supply and ±3% over processing at < 10 kHz) 

- Oscillator May Be Bypassed if External Clock Is Available (Apply external clock to Pin 3) 

- External Master Reset Totally Independent of Automatic Reset Operation 

- Operates as 2[n] Frequency Divider or Single Transition Timer 

- Q/Q Select Provides Output Logic Level Flexibility 

- Reset (auto or master) Disables Oscillator During Resetting to Provide No Active Power Dissipation 

- Clock Conditioning Circuit Permits Operation with Very Slow Clock Rise and Fall Times 

- Automatic Reset Initializes All Counters On Power Up 

• Supply Voltage Range = 3.0 Vdc to 18 Vdc with Auto Reset Supply Voltage Range = Disabled (Pin 5 = VDD) Supply Voltage Range = 8.5 Vdc to 18 Vdc with Auto Reset Supply Voltage Range = Enabled (Pin 5 = VSS) 

- NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP Capable 

- These Devices are Pb−Free and are RoHS Compliant 

|Rtc||1|14||VDD||
|---|---|---|---|---|---|---|
|Ctc||2|13||B||
|RS||3|12||A||
|NC||4|11||NC||
||||||||
|AR||5|10||MODE||
||||||||
|MR||6|9||Q/Q<br>SEL|SEL|
||||||||
|VSS||7|8||Q||



NC = NO CONNECTION 

## **MARKING DIAGRAMS** 

**==> picture [154 x 67] intentionally omitted <==**

**----- Start of picture text -----**<br>
14<br>14<br>H A H AA A E H Lit ir it ie it<br>14541BG MC14541B<br>AWLYWW ALYWG<br>1<br>1<br>SOIC−14 SOEIAJ−14<br>**----- End of picture text -----**<br>


**==> picture [111 x 130] intentionally omitted <==**

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14 Voodoothi<br>14<br>541B<br>ALYW<br>1 UUU U UDU U<br>TSSOP−14<br>A = Assembly Location<br>WL, L = Wafer Lot<br>YY, Y = Year<br>WW, W = Work Week<br>G or  = Pb−Free Package<br>**----- End of picture text -----**<br>


(Note: Microdot may be in either location) 

## **ORDERING INFORMATION** 

See detailed ordering and shipping information in the package dimensions section on page 2 of this data sheet. 

Publication Order Number: **MC14541B/D** 

**1** 

© Semiconductor Components Industries, LLC, 2014 **July, 2014 − Rev. 14** 

**MC14541B** 

**MAXIMUM RATINGS** (Voltages Referenced to VSS) 

|**MAXIMUM RA**|**TINGS**(Voltages Referenced to VSS)|||
|---|---|---|---|
|**Symbol**|**Parameter**|**Value**|**Unit**|
|VDD|DC Supply Voltage Range|−0.5 to +18.0|V|
|Vin, Vout|Input or Output Voltage Range, (DC or Transient)|−0.5 to VDD+ 0.5|V|
|Iin|Input Current (DC or Transient)|±10 (per Pin)|mA|
|Iout|Output Current (DC or Transient)|±45 (per Pin)|mA|
|PD|Power Dissipation, per Package (Note 1)|500|mW|
|TA|Ambient Temperature Range|−55 to +125|°C|
|Tstg|Storage Temperature Range|−65 to +150|°C|
|TL|Lead Temperature, (8−Second Soldering)|260|°C|



Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 

1. Temperature Derating: “D/DW” Packages: –7.0 mW/ � C From 65 � C To 125 � C 

## **ORDERING INFORMATION** 

|**ORDERING INFORMATION**|||
|---|---|---|
|**Device**|**Package**|**Shipping**†|
|MC14541BDG|SOIC−14<br>(Pb−Free)|55 Units / Rail|
|NLV14541BDG*|SOIC−14<br>(Pb−Free)|55 Units / Rail|
|MC14541BDR2G|SOIC−14<br>(Pb−Free)|2500 / Tape & Reel|
|NLV14541BDR2G*|SOIC−14<br>(Pb−Free)|2500 / Tape & Reel|
|MC14541BDTR2G|TSSOP−14<br>(Pb−Free)|2500 / Tape & Reel|
|NLV14541BDTR2G*|TSSOP−14<br>(Pb−Free)|2500 / Tape & Reel|
|MC14541BFELG|SOEIAJ−14<br>(Pb−Free)|2000 / Tape & Reel|



†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. 

*NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP Capable. 

**http://onsemi.com 2** 

## **MC14541B** 

## **ELECTRICAL CHARACTERISTICS** (Voltages Referenced to VSS) 

|**Characteristic**|**Symbol**|**VDD**<br>**Vdc**|**− 55**�**C**|**− 55**�**C**|**25**�**C**|**25**�**C**|**25**�**C**|**125**�**C**|**125**�**C**|**Unit**|
|---|---|---|---|---|---|---|---|---|---|---|
||||**Min**|**Max**|**Min**|**Typ**<br>(Note 2)|**Max**|**Min**|**Max**||
|Output Voltage<br>“0” Level<br>Vin=  VDDor 0<br>“1” Level<br>Vin= 0 or VDD|VOL|5.0<br>10<br>15|−<br>−<br>−|0.05<br>0.05<br>0.05|−<br>−<br>−|0<br>0<br>0|0.05<br>0.05<br>0.05|−<br>−<br>−|0.05<br>0.05<br>0.05|Vdc|
||VOH|5.0<br>10<br>15|4.95<br>9.95<br>14.95|−<br>−<br>−|4.95<br>9.95<br>14.95|5.0<br>10<br>15|−<br>−<br>−|4.95<br>9.95<br>14.95|−<br>−<br>−|Vdc|
|Input Voltage<br>“0” Level<br>(VO= 4.5 or 0.5 Vdc)<br>(VO= 9.0 or 1.0 Vdc)<br>(VO= 13.5 or 1.5 Vdc)<br>“1” Level<br>(VO= 0.5 or 4.5 Vdc)<br>(VO= 1.0 or 9.0 Vdc)<br>(VO= 1.5 or 13.5 Vdc)|VIL|5.0<br>10<br>15|−<br>−<br>−|1.5<br>3.0<br>4.0|−<br>−<br>−|2.25<br>4.50<br>6.75|1.5<br>3.0<br>4.0|−<br>−<br>−|1.5<br>3.0<br>4.0|Vdc|
||VIH|5.0<br>10<br>15|3.5<br>7.0<br>11|−<br>−<br>−|3.5<br>7.0<br>11|2.75<br>5.50<br>8.25|−<br>−<br>−|3.5<br>7.0<br>11|−<br>−<br>−|Vdc|
|Output Drive Current<br>(VOH= 2.5 Vdc)<br>Source<br>(VOH= 9.5 Vdc)<br>(VOH= 13.5 Vdc)<br>(VOL= 0.4 Vdc)<br>Sink<br>(VOL= 0.5 Vdc)<br>(VOL= 1.5 Vdc)|IOH|5.0<br>10<br>15|–4.19<br>–7.96<br>–16.3|−<br>−<br>−|–3.38<br>–6.42<br>–13.2|–6.75<br>–12.83<br>–26.33|−<br>−<br>−|–2.37<br>–4.49<br>−9.24|−<br>−<br>−|mAdc|
||IOL|5.0<br>10<br>15|1.93<br>4.96<br>19.3|−<br>−<br>−|1.56<br>4.0<br>15.6|3.12<br>8.0<br>31.2|−<br>−<br>−|1.09<br>2.8<br>10.9|−<br>−<br>−|mAdc|
|Input Current|Iin|15|−|±0.1|−|±0.00001|±0.1|−|±1.0|�Adc|
|Input Capacitance<br>(Vin= 0)|Cin|−|−|−|−|5.0|7.5|−|−|pF|
|Quiescent Current<br>(Pin 5 is High)<br>Auto Reset Disabled|IDD|5.0<br>10<br>15|−<br>−<br>−|5.0<br>10<br>20|−<br>−<br>−|0.005<br>0.010<br>0.015|5.0<br>10<br>20|−<br>−<br>−|150<br>300<br>600|�Adc|
|Auto Reset Quiescent Current<br>(Pin 5 is low)|IDDR|10<br>15|−<br>−|250<br>500|−<br>−|30<br>82|250<br>500|−<br>−|1500<br>2000|�Adc|
|Supply Current (Notes 3 & 4)<br>(Dynamic plus Quiescent)|ID|5.0<br>10<br>15|ID= (0.4�A/kHz) f + IDD<br>ID= (0.8�A/kHz) f + IDD<br>ID= (1.2�A/kHz) f + IDD|||||||�Adc|



Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 

2. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance. 

3. The formulas given are for the typical characteristics only at 25 � C. 

4. When using the on chip oscillator the total supply current (in � Adc) becomes: IT = ID + 2 Ctc VDD f x 10[–3] where ID is in � A, Ctc is in pF, VDD in Volts DC, and f in kHz. (see Fig. 3) Dissipation during power−on with automatic reset enabled is typically 50 � A @ VDD = 10 Vdc. 

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**3** 

## **MC14541B** 

**SWITCHING CHARACTERISTICS** (Note 5) (CL = 50 pF, TA = 25 � C) 

|**Characteristic**|**Symbol**|**VDD**|**Min**|**Typ**<br>(Note 6)|**Max**|**Unit**|
|---|---|---|---|---|---|---|
|Output Rise and Fall Time<br>tTLH, tTHL= (1.5 ns/pF) CL+ 25 ns<br>tTLH, tTHL= (0.75 ns/pF) CL+ 12.5 ns<br>tTLH, tTHL= (0.55 ns/pF) CL+ 9.5 ns|tTLH,<br>tTHL|5.0<br>10<br>15|−<br>−<br>−|100<br>50<br>40|200<br>100<br>80|ns|
|Propagation Delay, Clock to Q (28Output)<br>tPLH, tPHL= (1.7 ns/pF) CL+ 3415 ns<br>tPLH, tPHL= (0.66 ns/pF) CL+ 1217 ns<br>tPLH, tPHL= (0.5 ns/pF) CL+ 875 ns|tPLH<br>tPHL|5.0<br>10<br>15|−<br>−<br>−|3.5<br>1.25<br>0.9|10.5<br>3.8<br>2.9|�s|
|Propagation Delay, Clock to Q (216Output)<br>tPHL, tPLH= (1.7 ns/pF) CL+ 5915 ns<br>tPHL, tPLH= (0.66 ns/pF) CL+ 3467 ns<br>tPHL, tPLH= (0.5 ns/pF) CL+ 2475 ns|tPHL<br>tPLH|5.0<br>10<br>15|−<br>−<br>−|6.0<br>3.5<br>2.5|18<br>10<br>7.5|�s|
|Clock Pulse Width|tWH(cl)|5.0<br>10<br>15|900<br>300<br>225|300<br>100<br>85|−<br>−<br>−|ns|
|Clock Pulse Frequency (50% Duty Cycle)|fcl|5.0<br>10<br>15|−<br>−<br>−|1.5<br>4.0<br>6.0|0.75<br>2.0<br>3.0|MHz|
|MR Pulse Width|tWH(R)|5.0<br>10<br>15|900<br>300<br>225|300<br>100<br>85|−<br>−<br>−|ns|
|Master Reset Removal Time|trem|5.0<br>10<br>15|420<br>200<br>200|210<br>100<br>100|−<br>−<br>−|ns|



5. The formulas given are for the typical characteristics only at 25 � C. 

6. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance. 

**==> picture [453 x 275] intentionally omitted <==**

**----- Start of picture text -----**<br>
VDD VDD<br>PULSE PULSE<br>GENERATOR RS GENERATOR RS<br>AR AR<br>Q/Q SELECT Q/Q SELECT<br>MODE Q MODE Q<br>A CL A CL<br>B B<br>MR MR<br>VSS VSS<br>20 ns 20 ns<br>(Rtc AND Ctc OUTPUTS ARE LEFT OPEN)<br>90%<br>50% 50%<br>20 ns 20 ns RS 10%<br>90% tPLH tPHL<br>50%<br>10% 50% 90% 50%<br>50% Q 10%<br>DUTY CYCLE tTLH tTHL<br>Figure 1. Power Dissipation Test Circuit Figure 2. Switching Time Test Circuit<br>and Waveform and Waveforms<br>**----- End of picture text -----**<br>


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**4** 

**MC14541B** 

## **EXPANDED BLOCK DIAGRAM** 

**==> picture [450 x 261] intentionally omitted <==**

**----- Start of picture text -----**<br>
A�12<br>B�13<br>1 OF 4<br>MUX<br>8�Q<br>Rtc�1 8-STAGE 2 [10] 2 [13] 2 [16]<br>Ctc�2 OSC C COUNTER 2 [8] C 8-STAGE<br>COUNTER<br>RS�3 RESET RESET RESET<br>AUTO RESET<br>POWER-ON<br>5<br>RESET<br>6 10 9<br>MASTER RESET MODE Q/Q<br>SELECT<br>VDD = PIN 14<br>VSS = PIN 7<br>**----- End of picture text -----**<br>


## **FREQUENCY SELECTION TABLE** 

|**A**|**B**|**Number of**<br>**Counter Stages**<br>**n**|**Count**<br>**2n**|
|---|---|---|---|
|0|0|13|8192|
|0|1|10|1024|
|1|0|8|256|
|1|1|16|65536|



## **TRUTH TABLE** 

||**TRUTH TABLE**|**TRUTH TABLE**|
|---|---|---|
|**Pin**|**State**||
||**0**|**1**|
|Auto Reset,<br>5|Auto Reset<br>Operating|Auto Reset Disabled|
|Master Reset, 6|Timer Operational|Master Reset On|
|Q/Q<br>,<br>9|Output Initially Low<br>After Reset|Output Initially High<br>After Reset|
|Mode,<br>10|Single Cycle Mode|Recycle Mode|



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**----- Start of picture text -----**<br>
3<br>TO CLOCK<br>CIRCUIT<br>INTERNAL<br>RESET<br>2 1<br>Ctc<br>RS RTC<br>**----- End of picture text -----**<br>


**Figure 3. Oscillator Circuit Using RC Configuration** 

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**5** 

**MC14541B** 

## **TYPICAL RC OSCILLATOR CHARACTERISTICS** 

**==> picture [239 x 170] intentionally omitted <==**

**----- Start of picture text -----**<br>
8.0<br>VDD = 15 V<br>4.0<br>0<br>10 V<br>-�4.0<br>-�8.0<br>5.0 V<br>-�12<br>RTC = 56 k�, RS = 0, f = 10.15 kHz @ VDD = 10 V, TA = 25°C<br>C = 1000 pF RS = 120 k�, f = 7.8 kHz @ VDD = 10 V, TA = 25°C<br>-�16<br>-�55 -�25 0 25 50 75 100 125<br>TA, AMBIENT TEMPERATURE (°C)<br>FREQUENCY DEVIATION (%)<br>**----- End of picture text -----**<br>


**Figure 4. RC Oscillator Stability** 

**==> picture [237 x 192] intentionally omitted <==**

**----- Start of picture text -----**<br>
100<br>50 V DD  = 10 V<br>f AS A FUNCTION<br>20<br>OF RTC<br>10 (C = 1000 pF)<br>5.0 (RS ≈ 2RTC)<br>f AS A FUNCTION<br>2.0 OF C<br>1.0 (RTC = 56 k�)<br>(RS = 120 k�)<br>0.5<br>0.2<br>0.1<br>1.0 k 10 k 100 k 1.0 m<br>RTC, RESISTANCE (OHMS)<br>0.0001 0.001 0.01 0.1<br>C, CAPACITANCE (�F)<br>f, OSCILLATOR FREQUENCY (kHz)<br>**----- End of picture text -----**<br>


**Figure 5. RC Oscillator Frequency as a Function of Rtc and Ctc** 

## **OPERATING CHARACTERISTICS** 

With Auto Reset pin set to a “0” the counter circuit is initialized by turning on power. Or with power already on, the counter circuit is reset when the Master Reset pin is set to a “1”. Both types of reset will result in synchronously resetting all counter stages independent of counter state. Auto Reset pin when set to a “1” provides a low power operation. 

The RC oscillator as shown in Figure 3 will oscillate with a frequency determined by the external RC network i.e., 

**==> picture [203 x 37] intentionally omitted <==**

The time select inputs (A and B) provide a two−bit address to output any one of four counter stages (2[8] , 2[10] , 2[13] and 2[16] ). The 2[n] counts as shown in the Frequency Selection Table represents the Q output of the N[th] stage of the counter. When A is “1”, 2[16] is selected for both states of B. However, 

when B is “0”, normal counting is interrupted and the 9th counter stage receives its clock directly from the oscillator (i.e., effectively outputting 2[8] ). 

The Q/Q select output control pin provides for a choice of output level. When the counter is in a reset condition and Q/Q select pin is set to a “0” the Q output is a “0”, correspondingly when Q/Q select pin is set to a “1” the Q output is a “1”. 

When the mode control pin is set to a “1”, the selected count is continually transmitted to the output. But, with mode pin “0” and after a reset condition the RS flip−flop (see Expanded Block Diagram) resets, counting commences, and after 2[n−1] counts the RS flip−flop sets which causes the output to change state. Hence, after another 2[n−1] counts the output will not change. Thus, a Master Reset pulse must be applied or a change in the mode pin level is required to reset the single cycle operation. 

## **DIGITAL TIMER APPLICATION** 

**==> picture [235 x 150] intentionally omitted <==**

**----- Start of picture text -----**<br>
Rtc<br>1 14 VDD<br>Ctc 2 13 B<br>3 12 A<br>RS<br>NC 4 11 N.C.<br>AR MODE<br>5 10<br>MR Q/Q<br>6 9 VDD<br>INPUT<br>7 8<br>OUTPUT<br>tMR<br>t + tMR<br>**----- End of picture text -----**<br>


When Master Reset (MR) receives a positive pulse, the internal counters and latch are reset. The Q output goes high and remains high until the selected (via A and B) number of clock pulses are counted, the Q output then goes low and remains low until another input pulse is received. 

This “one shot” is fully retriggerable and as accurate as the input frequency. An external clock can be used (pin 3 is the clock input, pins 1 and 2 are outputs) if additional accuracy is needed. 

Notice that a setup time equal to the desired pulse width output is required immediately following initial power up, during which time Q output will be high. 

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**6** 

**MC14541B** 

## **PACKAGE DIMENSIONS** 

**SOIC−14 NB** CASE 751A−03 ISSUE K 

**==> picture [466 x 191] intentionally omitted <==**

**----- Start of picture text -----**<br>
|||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|D|A|NOTES:|
|B|1.|DIMENSIONING AND TOLERANCING PER|
|ASME Y14.5M, 1994.|
|2.|CONTROLLING DIMENSION: MILLIMETERS.|
|14|8|3.|DIMENSION b DOES NOT INCLUDE DAMBAR|
|A3|PROTRUSION. ALLOWABLE PROTRUSION|
|SHALL BE 0.13 TOTAL IN EXCESS OF AT|
|MAXIMUM MATERIAL CONDITION.|
|H|E|4.|DIMENSIONS D AND E DO NOT INCLUDE|
|MOLD PROTRUSIONS.|
|L|5.|MAXIMUM MOLD PROTRUSION 0.15 PER|
|SIDE.|
|1|7|DETAIL A|
|MILLIMETERS|INCHES|
|0.25|M|B|[M]|13X|b|DIM|MIN|MAX|MIN|MAX|
|A|1.35|1.75|0.054|0.068|
|0.25|M|C|A|S|B|[S]|A1|0.10|0.25|0.004|0.010|
|A3|0.19|0.25|0.008|0.010|
|DETAIL A|b|0.35|0.49|0.014|0.019|
|A|X 45h|�|DE|8.553.80|8.754.00|0.3370.150|0.3440.157|
|e|1.27 BSC|0.050 BSC|
|H|5.80|6.20|0.228|0.244|
|h|0.25|0.50|0.010|0.019|
|e|A1|C|PLANESEATING|M|ML|0.400|�|1.257|�|0.0160|�|0.0497|�|

**----- End of picture text -----**<br>


## **SOLDERING FOOTPRINT*** 

**==> picture [221 x 195] intentionally omitted <==**

**----- Start of picture text -----**<br>
6.50 14X<br>1.18<br>1<br>1.27<br>PITCH<br>14X<br>0.58<br>DIMENSIONS: MILLIMETERS<br>**----- End of picture text -----**<br>


*For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. 

**http://onsemi.com** 

**7** 

**MC14541B** 

## **PACKAGE DIMENSIONS** 

**TSSOP−14** CASE 948G ISSUE B 

**==> picture [485 x 266] intentionally omitted <==**

**----- Start of picture text -----**<br>
14X      REFK NOTES:<br>1. DIMENSIONING AND TOLERANCING PER<br>0.10 (0.004) M T U S V S ANSI Y14.5M, 1982.<br>2. CONTROLLING DIMENSION: MILLIMETER.<br>0.15 (0.006) T U S 3. DIMENSION A DOES NOT INCLUDE MOLD<br>FLASH,  PROTRUSIONS OR GATE BURRS.<br>N MOLD FLASH OR GATE BURRS SHALL NOT<br>14 8 0.25 (0.010) 4.EXCEED 0.15 (0.006) PER SIDE.DIMENSION B DOES NOT INCLUDE<br>2X L/2 INTERLEAD FLASH OR PROTRUSION.<br>M INTERLEAD FLASH OR PROTRUSION SHALL<br>NOT EXCEED 0.25 (0.010) PER SIDE.<br>L B 5. DIMENSION K DOES NOT INCLUDE<br>−U− N DAMBAR PROTRUSION. ALLOWABLE<br>PIN 1 DAMBAR PROTRUSION SHALL BE 0.08<br>IDENT. F (0.003) TOTAL IN EXCESS OF THE K<br>DIMENSION AT MAXIMUM MATERIAL<br>1 7 DETAIL E CONDITION.<br>6. TERMINAL NUMBERS ARE SHOWN FOR<br>REFERENCE ONLY.<br>7. DIMENSION A AND B ARE TO BE<br>0.15 (0.006) T U S A K DETERMINED AT DATUM PLANE −W−.<br>−V− K1 MILLIMETERS INCHES<br>DIM MIN MAX MIN MAX<br>J J1 ÇÇÇÉÉÉ A 4.90 5.10 0.193 0.200<br>B 4.30 4.50 0.169 0.177<br>ÇÇÇÉÉÉ C −−− 1.20 −−− 0.047<br>SECTION N−N D 0.05 0.15 0.002 0.006<br>F 0.50 0.75 0.020 0.030<br>G 0.65 BSC 0.026 BSC<br>H 0.50 0.60 0.020 0.024<br>C −W− J 0.09 0.20 0.004 0.008<br>J1 0.09 0.16 0.004 0.006<br>0.10 (0.004) K1K 0.190.19 0.300.25 0.0070.007 0.0120.010<br>−T− SEATINGPLANE D G H DETAIL E ML 0   6.40 BSC � 8    � 0.252 BSC0    � 8    �<br>**----- End of picture text -----**<br>


## **SOLDERING FOOTPRINT*** 

**==> picture [253 x 153] intentionally omitted <==**

**----- Start of picture text -----**<br>
7.06<br>1<br>0.65<br>PITCH<br>14X 14X<br>0.36<br>1.26<br>DIMENSIONS: MILLIMETERS<br>**----- End of picture text -----**<br>


*For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. 

**http://onsemi.com** 

**8** 

**MC14541B** 

## **PACKAGE DIMENSIONS** 

**SOEIAJ−14** CASE 965 ISSUE B 

NOTES: 

DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. CONTROLLING DIMENSION: MILLIMETER. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS AND ARE MEASURED AT THE PARTING LINE. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. THE LEAD WIDTH DIMENSION (b) DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE LEAD WIDTH DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE  LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSIONS AND ADJACENT LEAD TO BE 0.46 ( 0.018). 

**14 8 LE Q1** ~~ey~~ **E HE M** ~~p~~ ot **1 7 L DETAIL P Z** ~~{nny~~ **D** ~~1 ae~~ : **VIEW P e A c b A1** 0.13 (0.005)[M] 0.10 (0.004) ~~ais ™~~ 

|**DIM**|**MIN**<br>**MAX**<br>**MILLIMETERS**|**MIN**<br>**MAX**<br>**MILLIMETERS**|**MIN**<br>**MAX**<br>**INCHES**|**MIN**<br>**MAX**<br>**INCHES**|
|---|---|---|---|---|
|**DIM**<br>**A**<br>**A**|**MIN**<br>---|**MAX**<br>2.05|**MIN**<br>---|**MAX**<br>0.081|
|**A1**|0.05|0.20|0.002|0.008|
|**b**|0.35|0.50|0.014|0.020|
|**c**|0.10|0.20|0.004|0.008|
|**c**<br>**D**|0.10<br>9.90|0.20<br>10.50|0.004<br>0.390|0.008<br>0.413|
|**E**|5.10|5.45|0.201|0.215|
|**H**<br>**e**|1.27 BSC<br>7.40<br>8.20||0.050 BSC<br>0.291<br>0.323||
|**HE**<br>**L**|7.40<br>0.50|8.20<br>0.85|0.291<br>0.020|0.323<br>0.033|
|**LE**|1.10|1.50|0.043|0.059|
|**M**|0|10|0|10|
|**Q1**|0.70|0.90|0.028|0.035|
|**Z**|---|1.42|---|0.056|



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