MAX20808AFH+

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## **MAX20808** 

## **Dual-Output 4A, 3MHz, 2.7V–16V Step-Down Switching Regulator** 

## **General Description** 

The MAX20808/MAX20808T is a dual-output, fully integrated, highly efficient, step-down DC-DC switching regulator. The regulator is able to operate from 2.7V to 16V input supplies, and each output can be regulated from 0.5V to 5.8V, delivering up to 4A of load current per output. With the MAX20808, the two outputs can be connected in parallel as a single-output, dual-phase regulator that supports up to 8A load current. 

The switching frequency of the device can be configured from 500kHz to 3MHz and provides the capability of optimizing the design in terms of solution size and performance. 

The MAX20808/MAX20808T utilizes fixed-frequency, current-mode control with internal compensation. The dual-switching regulators operate 180° out-of-phase. The MAX20808/MAX20808T features a selectable advanced modulation scheme (AMS) to provide improved dynamic load transient performance. The device also features selectable discontinuous current mode (DCM) operation to improve light load efficiency. Operation settings and configurable features can be selected by connecting pin-strap resistors from the PGM_ pins to ground. 

The MAX20808/MAX20808T has an internal 1.8V lowdropout (LDO) output to power the gate drives (VCC) and internal circuitry (AVDD). The device also has an optional LDO input pin (LDOIN), allowing connection from a 2.5V to 5.5V bias input supply for optimized efficiency. 

The MAX20808/MAX20808T integrates multiple protections including positive and negative overcurrent protection, output overvoltage protection, and overtemperature protection to ensure a robust design. 

The MAX20808/MAX20808T is available in a compact 3.5mm x 4.6mm FC2QFN package that supports -40°C to +125°C junction temperature operation. The MAX20808 package has an open top, and MAX20808T package has a closed top. 

## **Applications** 

- Communications Equipment 

- Networking Equipment 

- Servers and Storage Equipment 

- Point-of-Load Voltage Regulators 

## **Benefits and Features** 

- High-Power Density with Low Component Count 

   - Dual-Output or Dual-Phase Operation 

   - Single-Supply Operation with Integrated LDO for Bias Generation 

   - Optional 2.5V to 5.5V External Bias for Higher Efficiency 

   - Compact 3.5mm x 4.6mm, 21-Pin, FC2QFN Package 

   - Internal Compensation 

- Wide Operating Range 

   - 2.7V to 16V Input Voltage Range 

   - 0.5V to 5.8V Output Voltage Range 

   - 500kHz to 3MHz Configurable Switching Frequency 

   - -40°C to +125°C Junction Temperature Range 

   - Three Pin-Strap Programming Pins to Select Different Configurations 

   - Independent Enable and Power Good for Each Output 

- Optimized Performance and Efficiency 

   - 92.5% Peak Efficiency with VDDH = 12V, VOUT = 1.8V, and fSW = 1MHz 

   - Interleaved 180° Out-of-Phase Operation 

   - Selectable AMS to Improve Load Transient 

   - Selectable DCM to Improve Light Load Efficiency 

   - Active Current Balancing for Dual-Phase Operation (MAX20808 only) 

## **Electrical and Thermal Ratings** 

|**DESCRIPTION**|**CURRENT**<br>**RATING***<br>**(DUAL-**<br>**PHASE)**<br>**(A)**|**INPUT**<br>**VOLTAGE**<br>**(V)**|**OUTPUT**<br>**VOLTAGE**<br>**(V)**|
|---|---|---|---|
|Electrical Rating|8|2.7 to 16|0.5 to 5.8|
|Thermal Rating<br>TA = 85°C, no air<br>flow|8|12|5.0|
|Thermal Rating<br>TA = 55°C,<br>200LFM|8|12|5.0|



_*Maximum TJ = 125°C. For specific operating conditions, see the Safe Operating Area (SOA) curves in the Typical Operating Characteristics section._ 

- μP Chipsets 

- Memory VDDQ 

- I/O Pins of an FPGA/DSP/MCU 

19-101082; Rev 0; 5/21 

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Dual-Output 4A, 3MHz, 2.7V–16V Step-Down Switching Regulator 

## MAX20808 

## **SIMPLIFIED APPLICATION CIRCUIT** 

## **MAX20808/MAX20808T DUAL-OUTPUT APPLICATION CIRCUIT** 

**==> picture [459 x 512] intentionally omitted <==**

**----- Start of picture text -----**<br>
> 2.7V TO 16V INPUT<br>MAX20808/<br>Il MAX20808T<br>|  VVDDH1DDH2 BST2LX2 OUTPUT2: 0.5V TO 5.8V, 4A<br>OPTIONAL 2.5V TO 5.5V LDOIN<br>SNSP2<br>VCC<br>— - eee<br>AVDD<br>BST1<br>PGOOD1<br>PGOOD2 LX1 OUTPUT1: 0.5V TO 5.8V, 4A<br>EN1 SNSP1 aieaheien ><br>EN2<br>PGM0 i Il<br>PGM1<br>PGM2<br>PGND1<br>AGND PGND2<br>MAX20808 SINGLE-OUTPUT DUAL-PHASE APPLICATION CIRCUIT<br>——> 2.7V TO 16V INPUT<br>MAX20808<br>Il<br>VDDH1 BST2<br>VDDH2 LX2 OUTPUT: 0.5V TO 5.8V, 8A<br>OPTIONAL 2.5V TO 5.5 V LDOIN AVDD<br>COUPLED<br>VCC SNSP2 INDUCTOR<br>OR<br>DISCRETE<br>INDUCTORS<br>AVDD<br>BST1<br>ra<br>PGOOD1<br>LX1<br>PGOOD2<br>EN1 SNSP1<br>EN2<br>PGM0<br>PGM1<br>PGM2<br>PGND1<br>AGND PGND2<br>iE<br>**----- End of picture text -----**<br>


_19-XXXXXX; Rev 0; MM/YY_ 

Dual-Output 4A, 3MHz, 2.7V–16V Step-Down Switching Regulator 

## MAX20808 

## **Absolute Maximum Ratings** 

VDDH1, VDDH2 to PGND (Note 1) ......................... -0.3V to +19V LX1, LX2 to PGND (DC) ..................................... -0.3V to +19V LX1, LX2 to PGND (AC) (Note 2) ........................ -10V to +23V VDDH1 to LX1 (DC) (Note 1) ................................ -0.3V to +19V VDDH1 to LX1 (AC) (Note 2) ................................. -10V to +19V VDDH2 to LX2 (DC) (Note 1) ................................ -0.3V to +19V VDDH2 to LX2 (AC) (Note 2) ................................. -10V to +19V BST1, BST2 to PGND (DC) ............................. -0.3V to +21.5V BST1, BST2 to PGND (AC) (Note 2) .................. -7V to +25.5V BST1 to LX1 ...................................................... -0.3V to +2.5V BST2 to LX2 ...................................................... -0.3V to +2.5V 

PGND to AGND ................................................ -0.3V to +0.3V VCC to PGND .................................................... -0.3V to +2.5V AVDD to AGND................................................. -0.3V to +2.5V EN1, EN2 to AGND .............................................. -0.3V to +4V PGOOD1, PGOOD2 to AGND ............................. -0.3V to +4V SNSP1, SNSP2 to AGND ....................... -0.3V to AVDD+0.3V LDOIN to AGND................................................... -0.3V to +6V PGM0, PGM1, PGM2 to AGND .............. -0.3V to AVDD+0.3V Peak LX_ Current ............................................... -12A to +19A Junction Temperature (TJ) ........................................... +150°C Storage Temperature Range ......................... -65°C to +150°C Peak Reflow Temperature Lead-Free .......................... +260°C 

**Note 1:** Input high-frequency (HF) capacitors placed not more than 40 mils away from the VDDH_ pins are required to keep inductive voltage spikes within the Absolute Maximum limits. 

## **Note 2:** AC is limited to 25ns. 

_Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability._ 

## **Package Information** 

## **21 FC2QFN** 

|Part Number|MAX20808 (Open Top)|MAX20808T (Closed Top)|
|---|---|---|
|Package Code|F213A4F+1|F213A4F+2|
|Outline Number|21-100394|21-100513|
|Land Pattern Number|90-100134|90-100184|
|Thermal Resistance, Four Layer Board:|||
|Junction-to-Ambient Thermal Resistance (θJA) JEDEC|44.96°C/W|43.9°C/W|
|Junction-to-Ambient Thermal Resistance (θJA) on<br>MAX20808EVKIT#|20°C/W|20°C/W|
|Junction-to-Case Thermal Resistance (θJC)|0.51°C/W|10.1°C/W|



For the latest package outline information and land patterns (footprints), go to _www.maximintegrated.com/packages_ . Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer board. For detailed information on package thermal considerations, refer to _www.maximintegrated.com/thermal-tutorial_ . 

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Maxim Integrated | 3 

Dual-Output 4A, 3MHz, 2.7V–16V Step-Down Switching Regulator 

## MAX20808 

## **Electrical Characteristics** 

(Refer to _Typical Application Circuits_ , VDDH1 = VDDH2 = 12V, VLDOIN = 3.3V, TA = TJ = -40°C to +125°C, unless otherwise noted. Specifications are production tested at TA = +32°C; limits within the operating temperature range are guaranteed by design and characterization.) 

|characterization.)|||||
|---|---|---|---|---|
|**PARAMETER**|**SYMBOL**|**CONDITIONS**|**MIN**<br>**TYP**<br>**MAX**|**UNITS**|
|**INPUT SUPPLY**|||||
|Input Voltage Range|VDDH||2.7<br>16|V|
|Input Supply Current|IVDDH|VLDOIN= 3.3V, EN_ = AGND|0.1|mA|
|||VLDOIN= AVDD, EN_ = AGND|2.2||
|Linear Regulator Input<br>Voltage|VLDOIN||2.5<br>5.5|V|
|Linear Regulator Input<br>Current|ILDOIN|VLDOIN= 3.3V, EN_ = AGND|2.6|mA|
|||VLDOIN= 3.3V, EN_ = 1.8V, fSW= 1MHz|22.1||
|Internal LDO Regulated<br>Output|VCC||1.71<br>1.95|V|
|Linear Regulator<br>Current Limit||VLDOIN= AVDD|80|mA|
|||VLDOIN= 3.3V|100||
|||VCC< 1.6V|20||
|AVDD Undervoltage<br>Lockout|AVDDUVLO|Rising|1.65<br>1.67<br>1.70|V|
|AVDD Undervoltage<br>Lockout Hysteresis|||55|mV|
|VDDH_Undervoltage<br>Lockout|VDDH_UVLO|Rising|2.4<br>2.5<br>2.6|V|
|VDDH_Undervoltage<br>Lockout Hysteresis|||100|mV|
|LDOIN Undervoltage<br>Lockout|VLDOIN_UVLO||2.2<br>2.3<br>2.4|V|
|LDOIN Undervoltage<br>Lockout Hysteresis|VLDOIN_UVLO||100|mV|
|**OUTPUT VOLTAGE RANGE AND ACCURACY**|||||
|Internal Reference<br>Voltage||MAX20808|0.4945<br>0.500<br>0.5055|V|
|||MAX20808T|0.496<br>0.500<br>0.504||
|||TA= TJ= 0°C to +85°C|0.497<br>0.500<br>0.503||
|Voltage Sense Leakage<br>Current|ISNSP_|TA= TJ= +25°C|1|µA|
|**SWITCHING FREQUENCY**|||||
|Switching Frequency|fSW_||500|kHz|
||||750||
||||1000||
||||1500||
||||2000||
||||3000||
|Switching Frequency<br>Accuracy|||-10<br>+10|%|



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## MAX20808 

## Dual-Output 4A, 3MHz, 2.7V–16V Step-Down Switching Regulator 

(Refer to _Typical Application Circuits_ , VDDH1 = VDDH2 = 12V, VLDOIN = 3.3V, TA = TJ = -40°C to +125°C, unless otherwise noted. Specifications are production tested at TA = +32°C; limits within the operating temperature range are guaranteed by design and characterization.) 

|characterization.)|||||
|---|---|---|---|---|
||||||
|**PARAMETER**|**SYMBOL**|**CONDITIONS**|**MIN**<br>**TYP**<br>**MAX**|**UNITS**|
|Phase Shift Between<br>Two Outputs/Phases||fSW1= fSW2|180|°|
|Minimum Controllable<br>On-Time||MAX20808, IOUT= 0A (Note 3)|40<br>47|ns|
|||MAX20808T, IOUT= 0A (Note 3)|32<br>40||
|||MAX20808T, IOUT= 1A (Note 3)|27<br>37||
|Minimum Controllable<br>Off-Time||IOUT= 0A (Note 3)|100<br>110|ns|
|**ENABLE AND STARTUP**|||||
|Initialization Time|tINIT||800|µs|
|EN_ Threshold||Rising|0.9|V|
|||Falling|0.6||
|EN_ Filtering Delay|tEN_RISING_DE<br>LAY|Rising|200|µs|
||tEN_FALLING_D<br>ELAY|Falling|2||
|Soft-Start Time|tSS||3|ms|
|**POWER GOOD AND FAULT PROTECTIONS**|||||
|PGOOD_ Output Low||IPGOOD= 4mA|0.4|V|
|Output Undervoltage<br>(UV)Threshold|||-16<br>-13<br>-10|%|
|Output UV Deglitch<br>Delay|||4|μs|
|Output Overvoltage<br>Protection (OVP)<br>Threshold|||10<br>13<br>16|%|
|Output OVP Deglitch<br>Delay|||2|μs|
|Positive Overcurrent<br>Protection (POCP)<br>Threshold|POCP|Inductor Peak Current, POCP = 5.3A|4.80<br>5.33<br>5.86|A|
|||Inductor Peak Current, POCP = 4A|3.58<br>4.00<br>4.50||
|POCP Deglitch Delay|||36|ns|
|Fast Positive<br>Overcurrent Protection<br>(FPOCP)Threshold|FPOCP||12.5<br>14.5<br>16.5|A|
|Negative Overcurrent<br>Protection (NOCP)<br>Threshold to POCP<br>Threshold Ratio|NOCP|With respect to POCP threshold (typ)|-83|%|
|NOCP Accuracy|||-20<br>+20|%|
|BST UVLO Threshold|VBST|Rising|1.47<br>1.57<br>1.62|V|
|BST UVLO Threshold<br>Hysteresis|||60|mV|



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Dual-Output 4A, 3MHz, 2.7V–16V Step-Down Switching Regulator 

## MAX20808 

(Refer to _Typical Application Circuits_ , VDDH1 = VDDH2 = 12V, VLDOIN = 3.3V, TA = TJ = -40°C to +125°C, unless otherwise noted. Specifications are production tested at TA = +32°C; limits within the operating temperature range are guaranteed by design and 

|characterization.)|characterization.)||||
|---|---|---|---|---|
|**PARAMETER**|**SYMBOL**|**CONDITIONS**|**MIN**<br>**TYP**<br>**MAX**|**UNITS**|
|Overtemperature<br>Protection (OTP) Risin<br>Threshold|g<br>OTP||155|°C|
|OTP Accuracy|||6|%|
|OTP Hysteresis|||20|°C|
|Hiccup Protection Tim|e<br>tHICCUP||20|ms|
|**DCM OPERATION MODE**|||||
|DCM Comparator<br>Threshold to Enter DC|M|POCP = 5.3A, Inductor Valley Current|-300|mA|
|||POCP = 4A, Inductor Valley Current|-215||
|DCM Comparator<br>Threshold to Exit DCM||Inductor Valley Current|100|mA|
|**PROGRAMMING PIN**|**S**||||
|PGM_ Pin Resistor<br>Range|RPGM_||0.095<br>115|kΩ|
|PGM_ Resistor<br>Accuracy|||-1<br>+1|%|



**Note 3:** Guaranteed by design. 

## **Typical Operating Characteristics** 

(VDDH = 12V, tested on MAX20808EVKIT#, TA = +25°C, unless otherwise noted.) 

**==> picture [502 x 155] intentionally omitted <==**

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## MAX20808 

## Dual-Output 4A, 3MHz, 2.7V–16V Step-Down Switching Regulator 

(VDDH = 12V, tested on MAX20808EVKIT#, TA = +25°C, unless otherwise noted.) 

**==> picture [502 x 492] intentionally omitted <==**

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Maxim Integrated | 7 

## MAX20808 

## Dual-Output 4A, 3MHz, 2.7V–16V Step-Down Switching Regulator 

(VDDH = 12V, tested on MAX20808EVKIT#, TA = +25°C, unless otherwise noted.) 

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## MAX20808 

## Dual-Output 4A, 3MHz, 2.7V–16V Step-Down Switching Regulator 

(VDDH = 12V, tested on MAX20808EVKIT#, TA = +25°C, unless otherwise noted.) 

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Dual-Output 4A, 3MHz, 2.7V–16V Step-Down Switching Regulator 

## MAX20808 

## **Pin Configurations** 

**==> picture [181 x 257] intentionally omitted <==**

**----- Start of picture text -----**<br>
21 18<br>20 19<br>VDDH2 1 17 VDDH1<br>PGND2 2 16 PGND1<br>EN2 3 MAX20808/ 15 VCC<br>MAX20808T<br>PGOOD1 4 14 PGOOD2<br>PGM2 5 13 PGM1<br>PGM0 6 12 EN1<br>7 8 9 10 11<br>(TOP VIEW)<br>AGND SNSP1<br>BST2 LX2 LX1 BST1<br>SNSP2 AVDD LDOIN<br>**----- End of picture text -----**<br>


## **Pin Descriptions** 

|**PIN**|**NAME**|**FUNCTION**|
|---|---|---|
|1|VDDH2|Regulator Input Supply for Output 2. VDDH1and VDDH2should be connected on the PCB.|
|2|PGND2|Power Ground. PGND1 and PGND2 should be connected on the PCB.|
|3|EN2|Output Enable for Output 2.|
|4|PGOOD1|Open-Drain Power-Good Output for Output 1.|
|5|PGM2|Program Input. Connect this pin to ground though a programming resistor.|
|6|PGM0|Program Input. Connect this pin to ground though a programming resistor.|
|7|SNSP2|Output 2 Voltage Sense Feedback Pin. Connect SNSP2 to VOUT2at the load. A resistive voltage-divider<br>can be inserted between the output and SNSP2 to regulate the output above the 0.5V fixed reference<br>voltage. Connect SNSP2 to AVDD to select dual-phase operation.|
|8|AVDD|1.8V Supply for Analog Circuitry. Connect a 2.2Ω to 4.7Ω resistor from AVDD to VCC. Connect a 1μF or<br>greater ceramic capacitor from AVDD to AGND.|
|9|LDOIN|Optional 2.5V to 5.5V LDO Input Supply. Connect this pin to AVDD or GND, or leave this pin floating if<br>unused.|
|10|AGND|Analog Ground.|
|11|SNSP1|Output 1 Voltage Sense Feedback Pin. Connect SNSP1 to VOUT1at the load. A resistive voltage-divider<br>can be inserted between the output and SNSP1 to regulate the output above the 0.5V fixed reference<br>voltage.|
|12|EN1|Output Enable for Output 1.|



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## MAX20808 

## Dual-Output 4A, 3MHz, 2.7V–16V Step-Down Switching Regulator 

|||Switching Regulator|
|---|---|---|
|13|PGM1|Program Input. Connect this pin to ground though a programming resistor.|
|14|PGOOD2|Open-Drain Power-Good Output for Output 2.|
|15|VCC|Internal 1.8V LDO Output. Connect a 2.2μF or greater ceramic capacitor from VCCto PGND.|
|16|PGND1|Power Ground. PGND1 and PGND2 should be connected on the PCB.|
|17|VDDH1|Regulator Input Supply for Output 1. VDDH1and VDDH2should be connected on the PCB.|
|18|BST1|Bootstrap Pin for Output 1. Connect a 0.22μF ceramic capacitor from BST1 to LX1.|
|19|LX1|Switching Node of Output 1. Connect LX1 directly to the output inductor.|
|20|LX2|Switching Node of Output 2. Connect LX2 directly to the output inductor.|
|21|BST2|Bootstrap Pin for Output 2. Connect a 0.22μF ceramic capacitor from BST2 to LX2.|



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## MAX20808 

## Dual-Output 4A, 3MHz, 2.7V–16V Step-Down 

## Switching Regulator 

## **Block Diagram** 

**==> picture [452 x 430] intentionally omitted <==**

**----- Start of picture text -----**<br>
EN1 PGOOD1 EN2 PGOOD2 AVDD VCC<br>CLOCK                            DIGITAL CORE OTP BANK LDO LDOIN<br>TO ANALOG /<br>PGM0 DIGITAL CORE<br>TO<br>PGM1 RADC<br>GATE<br>PGM2 DRIVE<br>FAULT BST BST1<br>DETECT<br>SNSP1<br>VDDH1<br>MODULATOR1<br>PWM HS<br>OVP LOGIC DRIVER<br>PGOOD<br>LX1<br>IRECON<br>LS<br>DRIVER<br>PGND1<br>ZERO<br>CROSS<br>OVP<br>PGOOD FAULT BST BST2<br>DETECT<br>SNSP2<br>CONTROLLER2 VDDH2<br>MODULATOR2<br>AGND<br>PWM HS<br>LOGIC DRIVER<br>BANGAP LX2<br>CORE<br>IRECON<br>BIAS LS<br>DRIVER<br>PGND2<br>ZERO<br>MAX20808/ CROSS<br>MAX20808T<br>**----- End of picture text -----**<br>


## **Detailed Description** 

## **Dual-Output or Dual-Phase Operation** 

The MAX20808/MAX20808T by default is configured as dual-output step-down regulators. These devices have two independent control loops for the two outputs and the loop parameters can be independently selected. 

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Dual-Output 4A, 3MHz, 2.7V–16V Step-Down Switching Regulator 

## MAX20808 

The MAX20808 only can also be configured as a single-output, dual-phase 8A converter by connecting the SNSP2 pin to AVDD. When configured to dual-phase operation, only the control loop for OUTPUT1 works, and the control loop for OUTPUT2 is bypassed. The EN1 and PGOOD1 pins are used in dual-phase operation mode to enable the device and indicate power-good status. The EN2 and PGOOD2 pins can be disconnected. 

## **Control Architecture** 

## **Fixed-Frequency, Peak Current-Mode Control Loop** 

The MAX20808/MAX20808T control loops are based on fixed-frequency, peak current-mode control architecture. A simplified control architecture is shown in _Figure 1_ . Each loop contains an error amplifier stage, internal voltage loop compensation network, current sense, internal slope compensation, and a PWM modulator that generates the pulse-width modulation (PWM) signals to drive high-side and low-side MOSFETs. The device has a fixed 0.5V reference voltage (VREF). The difference of VREF and the sensed output voltage is amplified by the first error amplifier. Its output voltage (VERR_) is used as the input of the voltage loop compensation network. The output of the compensation network (VCOMP_) is fed to a PWM comparator with the current-sense signal (VISENSE_) and slope compensation (VRAMP_). The output of the PWM comparator is the input of the PWM modulator. The turning on of the high-side MOSFET is aligned with an internal clock. It can either be a fixed-frequency clock or a phase-shifted clock if AMS is enabled. 

**==> picture [501 x 173] intentionally omitted <==**

**----- Start of picture text -----**<br>
AMS_ENABLE<br>CLOCK<br>FIXED_CLK<br>AMS _CLK<br>PWM<br>VREF MODULATOR<br>VOLTAGE LOOP<br>VERR_ VCOMP_<br>COMPENSATION<br>VSNSP_ NETWORK<br>VISENSE_<br>VRAMP_<br>**----- End of picture text -----**<br>


## _Figure 1. Simplified Control Architecture_ 

## **Advanced Modulation Scheme** 

The MAX20808/MAX20808T offers a selectable AMS to provide improved dynamic load transient response. The AMS provides a significant advantage over conventional fixed-frequency PWM schemes. Enabling the AMS feature allows for modulation at both leading and trailing edges, which results in a fast-switching response during large load transients. **Figure 2** shows the scheme to include leading-edge modulation to the traditional trailing-edge modulation when AMS is enabled in the device. The modulation scheme allows the turn on and off with minimal delay. Since the total inductor current increases very quickly, thus satisfying the load demand, the current drawn from the output capacitors is reduced. With AMS enabled, the system closed-loop bandwidth can be extended without phase-margin penalty. As a result, the output capacitance can be minimized. 

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Dual-Output 4A, 3MHz, 2.7V–16V Step-Down Switching Regulator 

## MAX20808 

**==> picture [502 x 172] intentionally omitted <==**

**----- Start of picture text -----**<br>
FIXED_CLK<br>-VERR_<br>AMS_RAMP<br>AMS_CLK<br>PWM<br>**----- End of picture text -----**<br>


_Figure 2. AMS Operation_ 

## **Discontinuous Current Mode Operation** 

The discontinuous current mode operation can be enabled to improve light-load efficiency. It is required that VDDH is at least 2V higher than the desired VOUT for the device to operate in DCM. The device has a DCM current-detection comparator to monitor the inductor valley current while operating in continuous-conduction mode (CCM). At light load, if the inductor valley current is below the DCM comparator threshold for 48 consecutive cycles, the device transitions seamlessly to DCM. Once in DCM, the switching frequency decreases as load decreases. The MAX20808/MAX20808T transitions back to CCM operation as soon as the inductor valley current is higher than 100mA. 

## **Active Current Balancing** 

When the MAX20808 is configured to dual-phase operation, the MAX20808 operates with active current balancing for enhanced dynamic-current sharing or balancing between two-phase currents. This feature maintains the current balance during load transients, even at a load-step frequency close to the switching frequency or its harmonics. The active currentbalancing circuit adjusts the individual phase-current control signal in order to minimize the phase-current imbalance. 

## **Internal Linear Regulator** 

The MAX20808/MAX20808T contains an internal 1.8V linear regulator. The 1.8V voltage on VCC is derived from the VDDH1 pin by default. To improve efficiency, it is recommended to apply an external 2.5V to 5.5V bias input supply on the LDOIN pin so that the 1.8V voltage on VCC is converted from the LDOIN pin instead. The LDOIN pin can be connected to the output voltage if the output voltage falls within the 2.5V–5.5V range. The optional LDOIN bias input supply can be applied or removed anytime during regulation without affecting the regulation. 

The 1.8V voltage on the VCC pin supplies the current to the MOSFET drivers of both outputs. A decoupling capacitor of at least 2.2μF must be connected between VCC and PGND. The AVDD pin also requires a 1.8V supply to power the device’s internal analog circuitry. A 2.2Ω to 4.7Ω resistor must be connected between AVDD and VCC. A 1μF or greater decoupling capacitor must be used between AVDD and AGND. 

## **Startup and Shutdown** 

The startup and shutdown timing is shown in **Figure 3** . When the AVDD pin voltage is above its rising UVLO threshold, the device goes through an initialization procedure. The dual-output or dual-phase operation is detected. Configuration resistors on the PGM_ pins are read. Once initialization is complete, the device detects the VDDH UVLO and EN_ status. When both are above their rising thresholds, soft-start begins and switching is enabled. The output voltage of the enabled output starts to ramp up. The soft-start ramp time is 3ms. If there are no faults, the open-drain PGOOD_ pin is released from being held low after the soft-start ramp is complete. The device supports smooth startup with the output prebiased. 

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Maxim Integrated | 14 

## MAX20808 

## Dual-Output 4A, 3MHz, 2.7V–16V Step-Down Switching Regulator 

During operation, if either VDDH UVLO or EN_ falls below its threshold, switching is stopped immediately. The PGOOD_ pin is driven low. The output voltage is discharged by the load current. 

**==> picture [408 x 281] intentionally omitted <==**

**----- Start of picture text -----**<br>
VDDH<br>VCC AND AVDD<br>tINIT<br>EN_<br>tSS<br>VOUT_  tEN_FALLING_DELAY<br>(PRE-BIASED)<br>INTERNAL<br>SOFT-START RAMP<br>tEN_RISING_DELAY<br>PGOOD_<br>LX_<br>tINIT = 800µs<br>tEN_RISING_DELAY = 200µs<br>tSS = 3ms<br>tEN_FALLING_DELAY = 2µs<br>**----- End of picture text -----**<br>


_Figure 3. Startup and Shutdown Timing_ 

## **Fault Handling** 

## **Input Undervoltage Lockout (V** DDH **UVLO)** 

The MAX20808/MAX20808T internally monitors VDDH with a UVLO circuit. When the input supply voltage is below the UVLO threshold, the device stops switching and drives the PGOOD_ pin low. The device restarts after 20ms hiccup protection time if the VDDH UVLO status is cleared. Refer to the _Startup and Shutdown_ section for the startup sequence. 

## **Output Overvoltage Protection (OVP)** 

The feedback voltage on SNSP_ is monitored for overvoltage once the soft-start ramp is complete. If the feedback voltage is above the OVP threshold beyond the OVP deglitch filtering delay, the device stops switching and drives the PGOOD_ pin low. The device restarts after 20ms hiccup protection time if the OVP status is cleared. When configured to dualoutput operation, the OVP of one output does not affect the operation of the other output. 

## **Positive Overcurrent Protection (POCP)** 

The device’s peak current mode control architecture provides inherent current limiting and short-circuit protection. The inductor current is continuously monitored while switching. The inductor peak current is limited on a cycle-by-cycle basis. In each switching cycle, once the sensed inductor current exceeds the POCP threshold, the device turns off the high-side MOSFET and turns on the low-side MOSFET to allow the inductor current to be discharged by output voltage. An updown counter is used to accumulate the number of consecutive POCP events each switching cycle. If the counter exceeds 

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Maxim Integrated | 15 

Dual-Output 4A, 3MHz, 2.7V–16V Step-Down Switching Regulator 

## MAX20808 

1024, the device stops switching and drives the PGOOD_ pin low. The device restarts after 20ms hiccup protection time. When configured to dual-output operation, the POCP of one output does not affect the operation of the other output. 

The MAX20808 offers two POCP thresholds (5.3A and 4A) for each output, which can be selected by the PGM1 and PGM2 pins (refer to _Pin-Strap Programmability_ section). Due to POCP deglitch delay, for a specific application use case, the actual POCP threshold should be higher (refer to _Output Inductor Selection_ section). 

## **Negative Overcurrent Protection (NOCP)** 

The device also has negative overcurrent protection against inductor valley current. The NOCP threshold is -83% of the POCP threshold. In each switching cycle, once the sensed inductor current exceeds the NOCP threshold, the device turns off the low-side MOSFET and turns on the high-side MOSFET for a fixed 180ns time to allow the inductor current to be charged by input voltage. Same as the POCP, an up-down counter is used to accumulate the number of consecutive NOCP events. If the counter exceeds 1024, the device stops switching and drives the PGOOD_ pin low. The device restarts after 20ms hiccup protection time. When configured to dual-output operation, the NOCP of one output does not affect the operation of the other output. 

## **Overtemperature Protection (OTP)** 

The overtemperature protection threshold is +155°C with 20°C hysteresis. If the junction temperature reaches OTP threshold during operation, the device stops switching and drives the PGOOD_ pin low. The device restarts if the OTP status is cleared. 

## **Pin-Strap Programmability** 

The MAX20808/MAX20808T has three program pins (PGM0, PGM1, and PGM2) to set some of the key configurations of the device. A pin-strap resistor is connected from the PGM_ pin to AGND, and its value is read during startup initialization. The PGM0 selects the common settings that apply to both outputs (AMS, DCM, and switching frequencies). When the device is configured to dual-output operation, the PGM1 selects the POCP and internal compensation parameters of OUTPUT1; the PGM2 selects the POCP and internal compensation parameters of OUTPUT2. When the device is configured to dual-phase operation, the POCP and internal compensation parameters are selected only by PGM1. Refer to the _Internal Compensation Selection_ section for information about how to select the compensation parameters for optimized control loop performance. 

**Table 1. PGM0 Configurations** 

|**PGM0**<br>**CODES**|**R**<br>**(Ω)**|**AMS**|**DCM**|**f**SW1<br>**(kHz)**|**f**SW2<br>**(kHz)**|
|---|---|---|---|---|---|
|0|95.3|Disable|Disable|500|500|
|1|200|||500|1000|
|2|309|||750|750|
|3|422|||750|1500|
|4|536|||1000|500|
|5|649|||1000|1000|
|6|768|||1000|2000|
|7|909|||1500|750|
|8|1050|||1500|1500|
|9|1210|||2000|1000|
|10|1400|||2000|2000|
|11|1620|||3000|3000|
|12|1870|Enable||500|500|
|13|2150|||500|1000|
|14|2490|||750|750|
|15|2870|||750|1500|
|16|3740|||1000|500|
|17|8060|||1000|1000|
|18|12400|||1000|2000|
|19|16900|||1500|750|



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Maxim Integrated | 16 

Dual-Output 4A, 3MHz, 2.7V–16V Step-Down Switching Regulator 

## MAX20808 

|20|21500|||1500|1500|
|---|---|---|---|---|---|
|21|26100|||2000|1000|
|22|30900|||2000|2000|
|23|36500|||3000|3000|
|24|42200||Enable|500|500|
|25|48700|||500|1000|
|26|56200|||750|750|
|27|64900|||1000|500|
|28|75000|||1000|1000|
|29|86600|||1500|1500|
|30|100000|||2000|2000|
|31|115000|||3000|3000|



**Table 2. PGM1 Configurations for OUTPUT1 or Dual-Phase Operation** 

|**PGM1**<br>**CODES**|**R**<br>**(Ω)**|**POCP1**<br>**(A)**|**VOLTAGE**<br>**LOOP GAIN**<br>**MULTIPLIER 1**|**SLOPE1**<br>**(μA)**|
|---|---|---|---|---|
|0|95.3|5.3|0.4|1.5|
|1|200|||2.6|
|2|309|||3.7|
|3|422|||6.0|
|4|536|||7.0|
|5|649|||8.0|
|6|768||0.7|1.5|
|7|909|||2.6|
|8|1050|||3.7|
|9|1210|||6.0|
|10|1400|||7.0|
|11|1620|||8.0|
|12|1870||1|1.5|
|13|2150|||2.6|
|14|2490|||3.7|
|15|2870|||6.0|
|16|3740|||7.0|
|17|8060|||8.0|
|18|12400||1.5|1.5|
|19|16900|||2.6|
|20|21500|||3.7|
|21|26100|||6.0|
|22|30900|||7.0|
|23|36500|4|0.4|1.5|
|24|42200|||2.6|
|25|48700|||7.0|
|26|56200||0.7|1.5|
|27|64900|||2.6|
|28|75000|||7.0|
|29|86600||1|1.5|
|30|100000|||2.6|
|31|115000|||7.0|



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Maxim Integrated | 17 

## MAX20808 

## Dual-Output 4A, 3MHz, 2.7V–16V Step-Down Switching Regulator 

**Table 3. PGM2 Configurations for OUTPUT2** 

|**PGM2**<br>**CODES**|**R**<br>**(Ω)**|**POCP2**<br>**(A)**|**VOLTAGE LOOP GAIN**<br>**MULTIPLIER 2**|**SLOPE2**<br>**(μA)**|
|---|---|---|---|---|
|0|95.3|5.3|0.4|1.5|
|1|200|||2.6|
|2|309|||3.7|
|3|422|||6.0|
|4|536|||7.0|
|5|649|||8.0|
|6|768||0.7|1.5|
|7|909|||2.6|
|8|1050|||3.7|
|9|1210|||6.0|
|10|1400|||7.0|
|11|1620|||8.0|
|12|1870||1|1.5|
|13|2150|||2.6|
|14|2490|||3.7|
|15|2870|||6.0|
|16|3740|||7.0|
|17|8060|||8.0|
|18|12400||1.5|1.5|
|19|16900|||2.6|
|20|21500|||3.7|
|21|26100|||6.0|
|22|30900|||7.0|
|23|36500|4|0.4|1.5|
|24|42200|||2.6|
|25|48700|||7.0|
|26|56200||0.7|1.5|
|27|64900|||2.6|
|28|75000|||7.0|
|29|86600||1|1.5|
|30|100000|||2.6|
|31|115000|||7.0|



## **Reference Design Procedure** 

## **Output Voltage Sensing** 

The MAX20808/MAX20808T has an internal 0.5V reference voltage. When the desired output voltage is higher than 0.5V, it is required to use resistor-dividers RFB1 and RFB2 to sense the output voltage (refer to _Typical Application Circuits_ ). It is recommended that the value RFB2 does not exceed 5kΩ. The resistor-divider ratio is given by the following equation: 

**==> picture [114 x 29] intentionally omitted <==**

where 

VOUT = Output voltage 

VREF = 0.5V fixed reference voltage 

RFB1 = Top resistor-divider 

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Maxim Integrated | 18 

Dual-Output 4A, 3MHz, 2.7V–16V Step-Down Switching Regulator 

## MAX20808 

RFB2 = Bottom resistor-divider 

## **Switching Frequency Selection** 

The MAX20808/MAX20808T offers a wide range of selectable switching frequencies from 500kHz to 3MHz. Switching frequency selection can be optimized for different applications. Higher switching frequencies are recommended for applications prioritizing solution size so that the value and size of output LC filter can be reduced. Lower switching frequencies are recommended for applications prioritizing efficiency and thermal dissipation due to reduced switching losses. The frequency must be selected so that the minimum controllable on-time and minimum controllable off-time are not violated. The maximum recommended switching frequency is calculated by the following equation: 

**==> picture [241 x 28] intentionally omitted <==**

## where 

fSWMAX = Maximum selectable switching frequency 

VDDHMAX = Maximum input voltage 

VDDHMIN = Minimum input voltage 

tONMIN = Minimum controllable on-time 

tOFFMIN = Minimum controllable off-time 

Due to system noise injection, even at steady-state operation, typically the LX rising and falling edges would have some random jittering noise. The selection of the switching frequency (fSW) should take into consideration the jittering and be lower than fSWMAX. To improve the LX jittering, it is recommended to use smaller inductor values and lower voltage loop gain to minimize the noise sensitivity. 

## **Output Inductor Selection** 

The output inductor has an important influence on the overall size, cost, and efficiency of the voltage regulator. Since the inductor is typically one of the larger components in the system, a minimum inductor value is particularly important in space-constrained applications. Smaller inductor values also permit faster transient response, reducing the amount of output capacitance needed to maintain transient tolerance. 

To improve current loop noise immunity, typically the output inductor is selected so that the inductor current ripple is at least 1A. The inductor value is calculated by the following equation: 

**==> picture [107 x 26] intentionally omitted <==**

## where 

VDDH = Input voltage 

IRIPPLE = Inductor current ripple peak-to-peak value 

The inductor should also be selected so that maximum load current delivery can be guaranteed by the selected POCP threshold. The MAX20808/MAX20808T offers two POCP thresholds (5.3A and 4A) for each output, which can be selected by the PGM1 and PGM2 pins (refer to _Pin-Strap Programmability_ section). Due to deglitch delay from the POCP comparator tripping to the high-side MOSFET turning off, for a specific application use case, the adjusted POCP threshold should take into consideration the inductor value, input voltage, and output voltage, which can be calculated by the following equation: 

**==> picture [207 x 22] intentionally omitted <==**

where 

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Maxim Integrated | 19 

Dual-Output 4A, 3MHz, 2.7V–16V Step-Down Switching Regulator 

## MAX20808 

POCPADJUST = Adjusted POCP threshold 

POCP = POCP level specified in the EC table 

tPOCP = POCP deglitch delay (36ns, typ) 

It needs to be verified that the peak inductor current in normal operation does not exceed the minimum adjusted POCP threshold: 

**==> picture [164 x 22] intentionally omitted <==**

## where 

N = Number of phases 

IOUTMAX = Maximum load current 

POCPADJUST(MIN) = Minimum adjusted POCP threshold, calculated with the minimum value of the POCP threshold. 

_Table 4_ shows some suitable inductor part numbers which are verified on the MAX20808/MAX20808T evaluation kit to offer optimal performance. 

**Table 4. Recommended Inductors** 

|**COMPANY**|**VALUE (μH)**|**I**SAT<br>**(A)**|**R**DC<br>**(mΩ)**|**FOOTPRINT**<br>**(mm)**|**HEIGHT**<br>**(mm)**|**PART NUMBER**|
|---|---|---|---|---|---|---|
|TDK|0.22|9|8|2.5 × 2.0|1.2|TFM252012ALMAR22MTAA|
|TDK|0.33|8.4|10|3.2 × 2.5|1.2|TFM322512ALMAR33MTAA|
|Pulse|0.47|26|3.75|5.5 × 5.3|2.9|PA5003.471NLT|
|Pulse|0.56|22.2|4.05|5.5 × 5.3|2.9|PA5003.561NLT|
|Pulse|1.0|16.5|6.9|5.5 × 5.3|2.9|PA5003.102NLT|
|Pulse|2.2|10|13.2|5.5 × 5.3|2.9|PA5003.222NLT|



## **Output Capacitor Selection** 

One major factor in determining the total required output capacitance is the output-voltage ripple. To meet the outputvoltage ripple requirement, the minimum output capacitance should satisfy the following equation: 

**==> picture [223 x 25] intentionally omitted <==**

## where 

VOUTRIPPLE = Maximum allowed output-voltage ripple 

ESR = ESR of output capacitors 

The other important factors in determining the total required output capacitance are the maximum allowable output-voltage overshoot and undershoot during load transients. For a given loading or unloading current step, the minimum required output capacitance should also satisfy the following equation: 

**==> picture [267 x 57] intentionally omitted <==**

## where 

COUT = Output capacitance 

△ I = Loading or unloading current step 

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Maxim Integrated | 20 

Dual-Output 4A, 3MHz, 2.7V–16V Step-Down Switching Regulator 

## MAX20808 

## △ VOUT = Maximum allowed output voltage undershoot or overshoot 

## **Input Capacitor Selection** 

The input capacitance selection is determined by the input voltage ripple requirement. The VDDH1 and VDDH2 pins of the MAX20808/MAX20808T should be connected on the PCB. When configured to dual-output operation, the input capacitance is shared between the two outputs. The minimum required input capacitance is estimated by the following equation: 

**==> picture [257 x 31] intentionally omitted <==**

where 

CIN = Input capacitance 

IOUT_(MAX) = Maximum output current of OUTPUT_ 

VOUT_ = Output voltage of OUTPUT_ 

fsw_ = Switching frequency of OUTPUT_ 

VINPP = Peak-to-peak input voltage ripple 

When configured to dual-phase operation, the minimum required input capacitance is estimated by the following equation: 

**==> picture [133 x 29] intentionally omitted <==**

Besides the minimum required input capacitance, it is also required to place 0.1μF and 1μF high-frequency decoupling capacitors next to each VDDH_ pin to suppress the high-frequency switching noises. 

## **Internal Compensation Selection** 

## **Voltage Loop Gain** 

For stability purposes, it is recommended that the voltage loop bandwidth (BW) be lower than one-fifth of the switching frequency. Consider the case of using multilayer ceramic chip (MLCC) output capacitors that have nearly ideal impedance characteristics in the frequency range of interest with negligible equivalent series resistance (ESR) and equivalent (or effective) series inductance (ESL). The voltage loop BW can be estimated with the following equation: 

**==> picture [134 x 39] intentionally omitted <==**

where 

RVGA = Voltage loop gain resistance, which is set by the switching frequency and voltage loop gain multiplier selected by PGM_ pin resistors ( _Table 5_ ) 

## **Table 5. Voltage Loop Gain Resistance** 

|**SWITCHING**<br>**FREQUENCY (kHz)**|**VOLTAGE**<br>**LOOP GAIN**<br>**MULTIPLIER**|**R**VGA<br>**(kΩ)**|
|---|---|---|
|500|0.4|15.6|
||0.7|27|
||1|37|
||1.5|52.2|
|750|0.4|22|



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Maxim Integrated | 21 

## MAX20808 

## Dual-Output 4A, 3MHz, 2.7V–16V Step-Down Switching Regulator 

||0.7|31|
|---|---|---|
||1|44.5|
||1.5|62.3|
|1000|0.4|22|
||0.7|37|
||1|52.2|
||1.5|74.5|
|1500|0.4|27|
||0.7|44.5|
||1|62.3|
||1.5|104.4|
|2000 or 3000|0.4|31|
||0.7|52.2|
||1|74.5|
||1.5|104.4|



## **Slope Compensation** 

Slope compensation is applied to guarantee current loop stability when the duty cycle is higher than 50%. For applications where the duty cycle is smaller than 50%, it is also recommended to apply slope compensation to improve current loop noise immunity. The minimum and maximum slope compensation values are calculated by the following equation: 

**==> picture [411 x 28] intentionally omitted <==**

where 

CSLOPE = 5pF 

The slope-compensation options of MAX20808/MAX20808T can be selected by resistor values on the PGM1 and PGM2 pins. A higher slope value is recommended to help reduce the duty cycle jittering and improve stability. 

## **Typical Reference Designs** 

Refer to _Typical Application Circuits_ for examples of reference schematics. Reference design examples for some common output voltages are shown in _Table 6_ . 

**Table 6. Reference Design Examples** 

|**V**OUT<br>**(V)**|**I**OUT**(A)**<br>**(PER**<br>**PHASE)**|**f**SW<br>**(kHz)**|**R**FB1<br>**(kΩ)**|**R**FB2<br>**(kΩ)**|**PGM0**<br>**(kΩ)**|**PGM1**<br>**OR**<br>**PGM2**<br>**(kΩ)**|**L**<br>**(μH)**|**C**IN**(PER EACH**<br>**V**DDH_**PIN)**|**C**OUT|
|---|---|---|---|---|---|---|---|---|---|
|0.8|4|750|1.82|3.01|2.49|1.05|0.47|10μF +1μF +0.1μF|2 × 47μF|
|0.9|4|1000|2.40|3.01|8.06|1.05|0.47|10μF +1μF +0.1μF|2 × 47μF|
|1.0|4|1000|3.01|3.01|8.06|1.05|0.47|10μF +1μF +0.1μF|2 × 47μF|
|1.2|4|1000|4.22|3.01|8.06|1.05|0.56|10μF +1μF +0.1μF|2 × 47μF|
|1.8|4|1500|7.87|3.01|21.5|2.49|0.56|10μF +1μF +0.1μF|2 × 47μF|
|3.3|4|2000|16.9|3.01|30.9|2.15|1.0|10μF +1μF +0.1μF|2 × 47μF|
|5.0|3|2000|22.6|2.49|30.9|100|2.2|10μF +1μF +0.1μF|1 × 47μF|



## **PCB Layout Guidelines** 

• For electrical and thermal reasons, the second layer from the top and bottom of the PCB should be reserved for power ground (PGND) planes. 

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Maxim Integrated | 22 

## MAX20808 

## Dual-Output 4A, 3MHz, 2.7V–16V Step-Down Switching Regulator 

- The input decoupling capacitor should be located the closest to the IC and no more than 40mils from the VDDH_ pins. 

- The VCC decoupling capacitors should be connected to PGND and placed as close as possible to VCC pin. 

- An analog ground copper polygon or island should be used to connect all analog control-signal grounds. This “quiet” 

- analog ground copper polygon or island should be connected to the PGND through a single connection close to AGND pin. The analog ground can be used as a shield and ground reference for the control signals (PGM_ and SNSP_). 

- The AVDD decoupling capacitors should be connected to AGND and placed as close as possible to AVDD pin. 

- The boost capacitors should be placed as close as possible to LX_ and BST_ pins, on the same side of the PCB with 

- the IC. 

• The feedback resistor-divider and optional external compensation network should be placed close to the IC to minimize the noise injection. 

- Voltage sense line should be shielded by ground plane and be kept away from switching node and the inductor. 

- Multiple vias are recommended for all paths that carry high currents and for heat dissipation. 

- The input capacitors and output inductors should be placed near the IC and the traces to the components should be 

- kept as short and wide as possible to minimize parasitic inductance and resistance. 

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Maxim Integrated | 23 

## MAX20808 

## Dual-Output 4A, 3MHz, 2.7V–16V Step-Down Switching Regulator 

## **Typical Application Circuits** 

## **Dual-Output Operation** 

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Maxim Integrated | 24 

Dual-Output 4A, 3MHz, 2.7V–16V Step-Down Switching Regulator 

## MAX20808 

## **Dual-Phase Operation** 

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Maxim Integrated | 25 

Dual-Output 4A, 3MHz, 2.7V–16V Step-Down Switching Regulator 

## MAX20808 

## **Ordering Information** 

|**PART NUMBER**|**TEMPERATURE**<br>**RANGE**|**PIN-PACKAGE**|**DUAL-PHASE**<br>**OPERATION**|**MINIMUM**<br>**CONTROLLABLE**<br>**ON-TIME**|
|---|---|---|---|---|
|MAX20808AFH+|-40°C to +125°C|21 FC2QFN (Open Top)|YES|47ns|
|MAX20808AFH+T|-40°C to +125°C|21 FC2QFN (Open Top)|YES|47ns|
|MAX20808TAFH+*|-40°C to +125°C|21 FC2QFN (Closed Top)|NO|40ns|
|MAX20808TAFH+T*|-40°C to +125°C|21 FC2QFN (Closed Top)|NO|40ns|



_+Denotes a lead(Pb)-free/RoHS-compliant package._ 

_T = Tape and reel._ 

_*Future product—contact factory for availability._ 

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Maxim Integrated | 26 

## MAX20808 

## Dual-Output 4A, 3MHz, 2.7V–16V Step-Down Switching Regulator 

|||Switching|Regulator|
|---|---|---|---|
|**Revision History**||||
|**REVISION**<br>**NUMBER**|**REVISION**<br>**DATE**|**DESCRIPTION**|**PAGES**<br>**CHANGED**|
|0|05/21|Initial release|—|



For pricing, delivery, and ordering information, please visit Maxim Integrated’s online storefront at https://www.maximintegrated.com/en/storefront/storefront.html. 

_Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance._ 

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Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.