M95M01-DFMN6TP SO8

**M95M01-DF M95M01-R** 

Datasheet 

## 1-Mbit serial SPI bus EEPROM 

## **Features** 

## **Interface** 

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SO8 (MN)<br>TSSOP8 (DW) 150 mil width<br>169 mil width<br>Unsawn wafer<br>WLCSP (CS and CU)<br>**----- End of picture text -----**<br>


- Compatible with the serial peripheral interface (SPI) bus 

## **Memory** 

- 1 Mbit (128 Kbytes) of EEPROM 

- Page size: 256-bytes 

- Additional 256-bytes identification page 

## **Supply voltage** 

- 1.8 V to 5.5 V for M95M01-R 

- 1.7 V to 5.5 V for M95M01-DF 

## **Temperature** 

## **Product status link** M95M01-DF M95M01-R **Product label** 

- Operating temperature range: from -40 °C up to +85 °C 

## **Fast write cycle time** 

- Byte and page write within 5 ms 

## **High speed clock frequency** 

- Clock up to 16 MHz 

## **Performance** 

- Enhanced ESD protection 

- More than 4 million write cycles 

- More than 200-year data retention 

## **Advanced features** 

- Write protect: quarter, half or whole memory array 

## **Package** 

- SO8 (ECOPACK2) 

- TSSOP8 (ECOPACK2) 

- WLCSP (ECOPACK2) 

- Unsawn wafer (each die is tested) 

**DS5137** - **Rev 16** - **July 2023** For further information contact your local STMicroelectronics sales office. 

www.st.com 

**M95M01-DF M95M01-R Description** 

## **1 Description** 

The M95M01 devices are electrically erasable programmable memories (EEPROMs) organized as 131072 x 8 bits, accessed through the SPI bus. 

The M95M01-R can operate with a supply range from 1.8 V to 5.5 V, the M95M01-DF can operate with a supply range from 1.7 V up to 5.5 V. These devices are guaranteed over the -40 °C/+85 °C temperature range. 

The M95M01-DF offers an additional page, named the identification page (256 bytes). The identification page can be used to store sensitive application parameters that can be (later) permanently locked in read-only mode. 

**Figure 1. Logic diagram** 

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VCC<br>D<br>C<br>S<br>M95xxx Q<br>W<br>HOLD<br>VSS<br>**----- End of picture text -----**<br>


The SPI bus signals are C, D and Q, as shown in Figure 1 and Table 1. The device is selected when chip select (S) is driven low. Communications with the device can be interrupted when the HOLD is driven low. 

**Table 1. Signal names** 

|**Signal name**|**Function**|**Direction**|
|---|---|---|
|C|Serial clock|Input|
|D|Serial data input|Input|
|Q|Serial data output|Output|
|S|Chip select|Input|
|W|Write protect|Input|
|HOLD|Hold|Input|
|VCC|Supply voltage|-|
|VSS|Ground|-|



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**M95M01-DF M95M01-R Description** 

**Figure 2. 8-pin package connections (top view)** 

|VSS<br>Q<br>S<br>W<br>M95xxx<br>1<br>2<br>3<br>4<br>8<br>7<br>6<br>5|VCC|
|---|---|
||D<br>C<br>HOLD|



_Note: See Package information for package dimensions, and how to identify pin 1_ 

**Figure 3. WLCSP connections (top view, marking side, with bumps on the underside)** 

|C|B|A||
|---|---|---|---|
|D||VCC|1|
||C||2|
|W||HOLD|3|
||Q||4|
|VSS||S|5|



MS38223V1 

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**M95M01-DF M95M01-R Memory organization** 

**2 Memory organization** 

The memory is organized as shown in the following figure. 

**Figure 4. Block diagram** 

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S Sense amplifiers<br>Data register and ECC<br>Q Page latches X decoder<br>W<br>Array<br>I/Os Status<br>D<br>register<br>Control  Custom area*<br>C logic<br>HV generator<br>and sequencer<br>Address<br>HOLD<br>register<br>Y decoder<br>**----- End of picture text -----**<br>


* Identification page 

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**M95M01-DF M95M01-R Signal description** 

## **3 Signal description** 

During all operations, VCC must be held stable and within the specified valid range: VCC(min) to VCC(max). All of the input and output signals must be held high or low (according to voltages of VIH, VOH, VIL or VOL, as specified in Section 9 DC and AC parameters). These signals are described next. 

## **3.1** 

## **Serial data output (Q)** 

This output signal is used to transfer data serially out of the device. Data is shifted out on the falling edge of serial clock (C). 

## **3.2 Serial data input (D)** 

This input signal is used to transfer data serially into the device. It receives instructions, addresses, and the data to be written. Values are latched on the rising edge of serial clock (C). 

## **3.3** 

## **Serial clock (C)** 

This input signal provides the timing of the serial interface. Instructions, addresses, or data present at serial data input (D) are latched on the rising edge of serial clock (C). Data on serial data output (Q) change from the falling edge of serial clock (C). 

## **3.4** 

## **Chip select (S)** 

When this input signal is high, the device is deselected and serial data output (Q) is at high impedance. The device is in the standby power mode, unless an internal write cycle is in progress. Driving chip select (S) low selects the device, placing it in the active power mode. 

After power-up, a falling edge on chip select (S) is required prior to the start of any instruction. 

## **3.5** 

## **Hold (HOLD)** 

The hold (HOLD) signal is used to pause any serial communications with the device without deselecting the device. 

During the hold condition, the serial data output (Q) is high impedance, and serial data. 

Input (D) and serial clock (C) are Don’t care. 

To start the hold condition, the device must be selected, with chip select (S) driven low. 

## **3.6** 

## **Write protect (W)** 

The main purpose of this input signal is to freeze the size of the area of memory that is protected against write instructions (as specified by the values in the BP1 and BP0 bits of the status register). 

This pin must be driven either high or low, and must be stable during all write instructions. 

## **3.7 VCC supply voltage** 

VCC is the supply voltage. 

## **3.8 VSS ground** 

VSS is the reference for all signals, including the VCC supply voltage. 

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**M95M01-DF M95M01-R Connecting to the SPI bus** 

## **4 Connecting to the SPI bus** 

All instructions, addresses and input data bytes are shifted in to the device, most significant bit first. The serial data input (D) is sampled on the first rising edge of the serial clock (C) after chip select (S) goes low. 

All output data bytes are shifted out of the device, most significant bit first. The serial data output (Q) is latched on the first falling edge of the serial clock (C) after the instruction (such as the read from memory array and read status register instructions) have been clocked into the device. 

## **Figure 5. Bus master and memory devices on the SPI bus** 

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VSS<br>VCC<br>R<br>SDO<br>SPI interface with<br>SDI<br>(CPOL, CPHA) =<br>SCK<br>(0, 0) or (1, 1)<br>C Q D VCC C Q D VCC C Q D VCC<br>SPI bus master VSS VSS VSS<br>SPI memory SPI memory SPI memory<br>R R R<br>device device device<br>CS3 CS2 CS1<br>S W HOLD S W HOLD S W HOLD<br>AI12836b<br>**----- End of picture text -----**<br>


_Note: The write protect (W) and hold (HOLD) signals should be driven, high or low as appropriate._ 

Figure 5 shows an example of three memory devices connected to an SPI bus master. Only one memory device is selected at a time, so only one memory device drives the serial data output (Q) line at a time. The other memory devices are high impedance. 

The pull-up resistor R (represented in Figure 5) ensures that a device is not selected if the bus master leaves the S line in the high impedance state. 

In applications where the bus master may leave all SPI bus lines in high impedance at the same time (for example, if the bus master is reset during the transmission of an instruction), it is recommended to connect the clock line (C) to an external pull-down resistor so that, if all inputs/outputs become high impedance, the C line is pulled low (while the S line is pulled high): this ensures that S and C do not become high at the same time, and so, that the tSHCH requirement is met. The typical value of R is 100 kΩ. 

## **4.1 SPI modes** 

These devices can be driven by a microcontroller with its SPI peripheral running in either of the following two modes: 

- CPOL = 0, CPHA = 0 

- CPOL = 1, CPHA = 1 

For these two modes, input data is latched in on the rising edge of serial clock (C), and output data is available from the falling edge of serial clock (C). 

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**M95M01-DF M95M01-R SPI modes** 

The difference between the two modes, as shown in Figure 6, is the clock polarity when the bus master is in Stand-by mode and not transferring data: 

- C remains at 0 for (CPOL = 0, CPHA = 0) 

- C remains at 1 for (CPOL = 1, CPHA = 1) 

**Figure 6. SPI modes supported** 

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CPOL CPHA<br>0 0 C<br>1 1 C<br>D MSB<br>Q MSB<br>**----- End of picture text -----**<br>


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**M95M01-DF M95M01-R Operating features** 

## **5 Operating features** 

## **5.1 Supply voltage (VCC)** 

## **5.1.1 Operating supply voltage (VCC)** 

Prior to selecting the memory and issuing instructions to it, a valid and stable VCC voltage within the specified [VCC(min), VCC(max)] range must be applied (see Operating conditions in Section 9 DC and AC parameters). This voltage must remain stable and valid until the end of the transmission of the instruction and, for a write instruction, until the completion of the internal write cycle (tW). In order to secure a stable DC supply voltage, it is recommended to decouple the VCC line with a suitable capacitor (usually of the order of 10 nF to 100 nF) close to the VCC / VSS device pins. 

## **5.1.2** 

## **Device reset** 

In order to prevent erroneous instruction decoding and inadvertent write operations during power-up, a power-onreset (POR) circuit is included. At power-up, the device does not respond to any instruction until VCC reaches the POR threshold voltage. This threshold is lower than the minimum VCC operating voltage (see: Operating conditions Section 9 DC and AC parameters). 

At power-up, when VCC passes over the POR threshold, the device is reset and is in the following state: 

- in standby power mode, 

- deselected, 

- status register values: 

   - The write enable latch (WEL) bit is reset to 0. 

   - The write in progress (WIP) bit is reset to 0. 

   - The SRWD, BP1 and BP0 bits remain unchanged (non-volatile bits). 

It is important to note that the device must not be accessed until VCC reaches a valid and stable level within the specified [VCC(min), VCC(max)] range, as defined in Section 9 DC and AC parameters. 

## **5.1.3** 

## **Power-up conditions** 

When the power supply is turned on, VCC rises continuously from VSS to VCC. During this time, the chip select (S) line is not allow ed to float but should follow the VCC voltage. It is therefore recommended to connect the S line to VCC via a suitable pull-up resistor (see Figure 5). 

In addition, the chip select (S) input offers a built-in safety feature, as the S input is edge- sensitive as well as level-sensitive: after power-up, the device does not become selected until a falling edge has first been detected on chip select (S). This ensures that chip select (S) must have been high, prior to going low to start the first operation. 

The VCC voltage has to rise continuously from 0 V up to the minimum VCC operating voltage defined under Operating conditions in Section 9. 

## **5.1.4 Power-down** 

During power-down (continuous decrease of the VCC supply voltage below the minimum VCC operating voltage defined under Operating conditions in Section 9), the device must be: 

- deselected (chip select S should be allowed to follow the voltage applied on VCC), 

- in standby power mode (there should not be any internal write cycle in progress). 

## **5.2** 

## **Active power and standby power modes** 

When chip select (S) is low, the device is selected, and in the active power mode. The device consumes ICC. 

When chip select (S) is high, the device is deselected. If a write cycle is not currently in progress, the device then goes into the standby power mode, and the device consumption drops to ICC1, as specified in DC characteristics (see Section 9). 

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**M95M01-DF M95M01-R Hold condition** 

## **5.3** 

## **Hold condition** 

The hold (HOLD) signal is used to pause any serial communications with the device without resetting the clocking sequence. 

To enter the hold condition, the device must be selected, with chip select (S) low. 

During the hold condition, the serial data output (Q) is high impedance, and the serial data Input (D) and the serial clock (C) are Don’t care. 

Normally, the device is kept selected for the whole duration of the hold condition. Deselecting the device while it is in the hold condition has the effect of resetting the state of the device: this mechanism can be used, if required, to reset the ongoing processes. 

_Note: Note:_ 

_This resets the internal logic, except the WEL and WIP bits of the status register._ 

_In the specific case where the device has moved in a write command (Inst + address + data bytes, each data byte being exactly 8 bits), deselecting the device also triggers the write cycle of this decoded command._ 

## **Figure 7. Hold condition activation** 

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C<br>HOLD<br>Hold  Hold<br>condition condition<br>**----- End of picture text -----**<br>


The hold condition starts when the hold (HOLD) signal is driven low when serial clock (C) is already low (as shown in Figure 7). 

Figure 7 also shows what happens if the rising and falling edges are not timed to coincide with serial clock (C) being low. 

## **5.4** 

## **Status register** 

The status register contains a number of status and control bits that can be read or set (as appropriate) by specific instructions. See Section 6.3 Read status register (RDSR) for a detailed description of the status register bits. 

## **5.5** 

## **Data protection and protocol control** 

The device features the following data protection mechanisms: 

- Before accepting the execution of the write and write Status register instructions, the device checks whether the number of clock pulses comprised in the instructions is a multiple of eight. 

- All instructions that modify data must be preceded by a write enable (WREN) instruction to set the write enable latch (WEL) bit. 

- The block protect (BP1, BP0) bits in the status register are used to configure part of the memory as readonly. 

- The write protect (W) signal is used to protect the block protect (BP1, BP0) bits in the status register. 

For any instruction to be accepted, and executed, chip select (S) must be driven high after the rising edge of serial clock (C) for the last bit of the instruction, and before the next rising edge of serial clock (C). Two points should be noted in the previous sentence: 

- The “last bit of the instruction” can be the eighth bit of the instruction code, or the eighth bit of a data byte, depending on the instruction (except for read status register (RDSR) and read (READ) instructions). 

- The “next rising edge of serial clock (C)” might (or might not) be the next bus transaction for some other device on the SPI bus. 

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**M95M01-DF M95M01-R Data protection and protocol control** 

**Table 2. Write-protected block size** 

|**Status register bits**|**Status register bits**|**Pttd blk**|**Pttd  dd**|
|---|---|---|---|
|**BP1**|**BP0**|**roece oc**|**roece array aresses**|
|0|0|None|None|
|0|1|Upper quarter|18000h - 1FFFFh|
|1|0|Upper half|10000h - 1FFFFh|
|1|1|Whole memory|00000h - 1FFFFh|



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**M95M01-DF M95M01-R Instructions** 

## **6 Instructions** 

Each command is composed of bytes (MSBit transmitted first), initiated with the instruction byte, as summarized in Table 3. 

If an invalid instruction is sent (one not contained in Table 3), the device automatically enters in a wait state until deselected. 

**Table 3. Instruction set** 

|**Instruction**|**Description**|**Instruction format**|
|---|---|---|
|WREN|Write enable|0000 0110|
|WRDI|Write disable|0000 0100|
|RDSR|Read status register|0000 0101|
|WRSR|Write status register|0000 0001|
|READ|Read from memory array|0000 0011|
|WRITE|Write to memory array|0000 0010|
|RDID(1)|Read identification page|1000 0011|
|WRID(1)|Write identification page|1000 0010|
|RDLS(1)|Reads the identification page lock status|1000 0011|
|LID(1)|Locks the identification page in read-only mode|1000 0010|



_1. Instruction available only for the M95M01-D device._ 

For read and write commands to memory array and Identification page the address is defined by two bytes as explained in the following table. 

**Table 4. Significant bits within the address bytes** 

||**Upper address byte**|**Upper address byte**|**Upper address byte**|**Upper address byte**|**Upper address byte**|**Upper address byte**|**Upper address byte**|**Upper address byte**|**Middle address byte**|**Middle address byte**|**Middle address byte**|**Middle address byte**|**Middle address byte**|**Middle address byte**|**Middle address byte**|**Middle address byte**|**Lower address byte**|**Lower address byte**|**Lower address byte**|**Lower address byte**|**Lower address byte**|**Lower address byte**|**Lower address byte**|**Lower address byte**|
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|**Instruction**|**b23**|**b22**|**b21**|**b20**|**b19**|**b18**|**b17**|**b16**|**b15**|**b14**|**b13**|**b12**|**b11**|**b10**|**b9**|**b8**|**b7**|**b6**|**b5**|**b4**|**b3**|**b2**|**b1**|**b0**|
|Read or<br>write|X(1)|X|X|X|X|X|X|A16(2)|A15|A14|A13|A12|A11|A10|A9|A8|A7|A6|A5|A4|A3|A2|A1|A0|
|RDID or<br>WRID|X|X|X|X|X|X|X|X|X|X|X|X|X|0|X|X|A7|A6|A5|A4|A3|A2|A1|A0|
|RDLS or LID|X|X|X|X|X|X|X|X|X|X|X|X|X|1|X|X|X|X|X|X|X|X|X|X|



_1. X: Don’t care bit_ 

_2. A: Significant address bit_ 

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**M95M01-DF M95M01-R Write enable (WREN)** 

## **6.1 Write enable (WREN)** 

The write enable latch (WEL) bit must be set prior to each WRITE and WRSR instruction. The only way to do this is to send a write enable instruction to the device. 

As shown in Figure 8, to send this instruction to the device, chip select (S) is driven low, and the bits of the instruction byte are shifted in, on serial data input (D). The device then enters a wait state. It waits for the device to be deselected by chip select (S) being driven high. 

**Figure 8. Write enable (WREN) sequence** 

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S<br>0 1 2 3 4 5 6 7<br>C<br>Instruction<br>D<br>High impedance<br>Q<br>**----- End of picture text -----**<br>


## **6.2** 

## **Write disable (WRDI)** 

One way of resetting the write enable latch (WEL) bit is to send a write disable instruction to the device. 

As shown in Figure 9, to send this instruction to the device, chip select (S) is driven low, and the bits of the instruction byte are shifted in, on serial data input (D). 

The device then enters a wait state. It waits for a the device to be deselected, by chip select (S) being driven high. The write enable latch (WEL) bit, in fact, becomes reset by any of the following events: 

- Power-up 

- WRDI instruction execution 

- WRSR instruction completion 

- Write instruction completion. 

**Figure 9. Write disable (WRDI) sequence** 

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S<br>0 1 2 3 4 5 6 7<br>C<br>Instruction<br>D<br>High Impedance<br>Q<br>**----- End of picture text -----**<br>


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**M95M01-DF M95M01-R Read status register (RDSR)** 

## **6.3 Read status register (RDSR)** 

The read status register (RDSR) instruction is used to read the status register. The status register may be read at any time, even while a write or write status register cycle is in progress. When one of these cycles is in progress, it is recommended to check the write in progress (WIP) bit before sending a new instruction to the device. It is also possible to read the status register continuously, as shown in the following figure. 

**Figure 10. Read status register (RDSR) sequence** 

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S<br>0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15<br>C<br>Instruction<br>D<br>Status Register Out Status Register Out<br>High impedance<br>Q 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7<br>MSB MSB<br>MS47548V1<br>**----- End of picture text -----**<br>


The status and control bits of the status register are detailed in the following subsections. 

## **6.3.1** 

## **WIP bit** 

The write in progress (WIP) bit indicates whether the memory is busy with a write or write status register cycle. When set to 1, such a cycle is in progress, when reset to 0, no such cycle is in progress. 

## **6.3.2** 

## **WEL bit** 

The write enable latch (WEL) bit indicates the status of the internal write enable latch. When set to 1, the internal write enable latch is set. When set to 0, the internal write enable latch is reset, and no write or write status register instruction is accepted. 

The WEL bit is returned to its reset state by the following events: 

- Power-up 

- Write disable (WRDI) instruction completion 

- Write status register (WRSR) instruction completion 

- Write (WRITE) instruction completion 

## **6.3.3** 

## **BP1, BP0 bits** 

The block protect (BP1, BP0) bits are non volatile. They define the size of the area to be software-protected against write instructions. These bits are written with the write status register (WRSR) instruction. When one or both of the block protect (BP1, BP0) bits is set to 1, the relevant memory area (as defined in Table 2) becomes protected against write (WRITE) instructions. The block protect (BP1, BP0) bits can be written provided that the hardware protected mode has not been set. 

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**M95M01-DF M95M01-R Write status register (WRSR)** 

## **6.3.4 SRWD bit** 

The status register write disable (SRWD) bit is operated in conjunction with the write protect (W) signal. The status register write disable (SRWD) bit and write protect (W) signal enable the device to be put in the hardware protected mode (when the status register write disable (SRWD) bit is set to 1, and write protect (W) is driven low). In this mode, the non-volatile bits of the status register (SRWD, BP1, BP0) become read-only bits and the write status register (WRSR) instruction is no longer accepted for execution. 

**Table 5. Status register format** 

## **6.4 Write status register (WRSR)** 

The write status register (WRSR) instruction is used to write new values to the status register. Before it can be accepted, a write enable (WREN) instruction must have been previously executed. 

The write status register (WRSR) instruction is entered by driving chip select (S) low, followed by the instruction code, the data byte on serial data input (D) and chip select (S) driven high. Chip select (S) must be driven high after the rising edge of serial clock (C) that latches in the eighth bit of the data byte, and before the next rising edge of serial clock (C). Otherwise, the write status register (WRSR) instruction is not executed. The instruction sequence is shown in Figure 11. 

**Figure 11. Write status register (WRSR) sequence** 

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S<br>0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15<br>C<br>Instruction Status Register In<br>D 7 6 5 4 3 2 1 0<br>MSB<br>High impedance<br>Q<br>**----- End of picture text -----**<br>


Driving the chip select (S) signal high at a byte boundary of the input data triggers the self-timed write cycle that takes tW to complete (as specified in AC tables in Section 9). 

While the write status register cycle is in progress, the status register may still be read to check the value of the write in progress (WIP) bit: the WIP bit is 1 during the self-timed write cycle tW, and 0 when the write cycle is complete. The WEL bit (write enable latch) is also reset at the end of the write cycle tW. 

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**M95M01-DF M95M01-R Write status register (WRSR)** 

The write status register (WRSR) instruction enables the user to change the values of the BP1, BP0 and SRWD bits: 

- The block protect (BP1, BP0) bits define the size of the area that is to be treated as read-only, as defined in Table 2. 

- The SRWD (status register write disable) bit, in accordance with the signal read on the write protect pin (W), enables the user to set or reset the write protection mode of the status register itself, as defined in Table 6. When in write-protected mode, the write status register (WRSR) instruction is not executed. 

The contents of the SRWD and BP1, BP0 bits are updated after the completion of the WRSR instruction, including the tW write cycle. 

The write status register (WRSR) instruction has no effect on the b6, b5, b4, b1, b0 bits in the status register. Bits b6, b5, b4 are always read as 0. 

**Table 6. Protection modes** 

||**SRWD**|||**Memory content**|**Memory content**|
|---|---|---|---|---|---|
|**W signal**|<br>**bit**|**Mode**|**Write protection of the status register**|**Protected**<br>**area(1)**|**Unprotected area(1)**|
|1|0|Software-<br>protected<br>(SPM)|Status register is writable (if the WREN<br>instruction has set the WEL bit).<br>The values in the BP1 and BP0 bits can be<br>changed.|Write-<br>protected|Ready to accept<br>Write instructions|
|0|0|||||
|1|1|||||
|0|1|Hardware-<br>protected<br>(HPM)|Status register is hardware write-protected.<br>The values in the BP1 and BP0 bits cannot be<br>changed.|Write-<br>protected|Ready to accept<br>Write instructions|



_1. As defined by the values in the block protect (BP1, BP0) bits of the status register. See Table 2_ 

The protection features of the device are summarized in Table 6. Protection modes. 

When the status register write disable (SRWD) bit in the status register is 0 (its initial delivery state), it is possible to write to the status register (provided that the WEL bit has previously been set by a WREN instruction), regardless of the logic level applied on the write protect (W) input pin. 

When the status register write disable (SRWD) bit in the status register is set to 1, two cases should be considered, depending on the state of the write protect (W) input pin: 

- If write protect (W) is driven high, it is possible to write to the status register (provided that the WEL bit has previously been set by a WREN instruction). 

- If write protect (W) is driven low, it is not possible to write to the status eegister even if the WEL bit has previously been set by a WREN instruction. (Attempts to write to the status register are rejected, and are not accepted for execution). As a consequence, all the data bytes in the memory area, which are softwareprotected (SPM) by the block protect (BP1, BP0) bits in the status register, are also hardware-protected against data modification. 

Regardless of the order of the two events, the hardware-protected mode (HPM) can be entered by: 

- either setting the SRWD bit after driving the write protect (W) input pin low, 

- or driving the write protect (W) input pin low after setting the SRWD bit. 

Once the hardware-protected mode (HPM) has been entered, the only way of exiting it is to pull high the write protect (W) input pin. 

If the write protect (W) input pin is permanently tied high, the hardware-protected mode (HPM) can never be activated, and only the software-protected mode (SPM), using the block protect (BP1, BP0) bits in the status register, can be used. 

**DS5137** - **Rev 16** 

**page 15/46** 

**M95M01-DF M95M01-R Read from memory array (READ)** 

## **6.5 Read from memory array (READ)** 

As shown in Figure 12, to send this instruction to the device, chip select (S) is first driven low. The bits of the instruction byte and address bytes are then shifted in, on serial data input (D). The address is loaded into an internal address register, and the byte of data at that address is shifted out, on serial data output (Q). 

**Figure 12. Read from memory array (READ) sequence** 

**==> picture [79 x 41] intentionally omitted <==**

ai13878a 

_Note: Bits A23 to A17 of the 24-bit address are Don't Care._ 

If chip select (S) continues to be driven low, the internal address register is incremented automatically, and the byte of data at the new address is shifted out. 

When the highest address is reached, the address counter rolls over to zero, allowing the read cycle to be continued indefinitely. The whole memory can, therefore, be read with a single READ instruction. 

The read cycle is terminated by driving chip select (S) high. The rising edge of the chip select (S) signal can occur at any time during the cycle. 

The instruction is not accepted, and is not executed, if a write cycle is currently in progress. 

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**page 16/46** 

**M95M01-DF M95M01-R Write to memory array (WRITE)** 

## **6.6 Write to memory array (WRITE)** 

As shown in Figure 13, to send this instruction to the device, chip select (S) is first driven low. The bits of the instruction byte, address byte, and at least one data byte are then shifted in, on serial data input (D). 

The instruction is terminated by driving chip select (S) high at a byte boundary of the input data. The self-timed write cycle, triggered by the chip select (S) rising edge, continues for a period tW (as specified in AC characteristics in Section 9), at the end of which the write in progress (WIP) bit is reset to 0. 

## **Figure 13. Byte write (WRITE) sequence** 

**==> picture [425 x 129] intentionally omitted <==**

**----- Start of picture text -----**<br>
S<br>0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39<br>C<br>Instruction 24-bit address Data byte<br>D 23 22 21 3 2 1 0 7 6 5 4 3 2 1 0<br>High impedance<br>Q<br>**----- End of picture text -----**<br>


**==> picture [38 x 6] intentionally omitted <==**

**----- Start of picture text -----**<br>
MS30905V2<br>**----- End of picture text -----**<br>


_Note: Bits A23 to A17 of the 24-bit address are Don't Care._ 

In the case of Figure 13, chip select (S) is driven high after the eighth bit of the data byte has been latched in, indicating that the instruction is being used to write a single byte. However, if chip select (S) continues to be driven low (as shown in Figure 14), the next byte of input data is shifted in, so that more than a single byte, starting from the given address towards the end of the same page, can be written in a single internal write cycle. Each time a new data byte is shifted in, the least significant bits of the internal address counter are incremented. If more bytes are sent than will fit up to the end of the page, a condition known as “roll-over” occurs. In case of rollover, the bytes exceeding the page size are overwritten from location 0 of the same page. The instruction is not accepted, and is not executed, under the following conditions: 

- if the write enable latch (WEL) bit has not been set to 1 (by executing a write enable instruction just before), 

- if a write cycle is already in progress, 

- if the device has not been deselected, by driving high chip select (S), at a byte boundary (after the eighth bit, b0, of the last data byte that has been latched in), 

- if the addressed page is in the region protected by the block protect (BP1 and BP0) bits. 

_Note:_ 

_The self-timed write cycle tW is internally executed as a sequence of two consecutive events: [erase addressed byte(s)], followed by [program addressed byte(s)]. An erased bit is read as “0” and a programmed bit is read as “1”._ 

**DS5137** - **Rev 16** 

**page 17/46** 

**M95M01-DF M95M01-R** 

**Read identification page (available only in M95M01-D devices)** 

**Figure 14. Page write (WRITE) sequence** 

**==> picture [388 x 241] intentionally omitted <==**

**----- Start of picture text -----**<br>
S<br>0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39<br>C<br>Instruction 24-bit address Data byte 1<br>D 23 22 21 3 2 1 0 7 6 5 4 3 2 1 0<br>S<br>C<br>Data byte 2 Data byte 3 Data byte N<br>D 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 6 5 4 3 2 1 0<br>**----- End of picture text -----**<br>


**==> picture [34 x 6] intentionally omitted <==**

**----- Start of picture text -----**<br>
MS30906V2<br>**----- End of picture text -----**<br>


_Note: Bits A23 to A17 of the 24-bit address are Don't Care._ 

## **6.6.1 Cycling with error correction code (ECC x 4)** 

The ECC is an internal logic function transparent for the SPI communication protocol. 

The ECC logic is implemented on each group of four EEPROM bytes (see note). Inside a group, if a single bit out of the four bytes happens to be erroneous during a read operation, the ECC detects this bit and replaces it with the correct value. The read reliability is therefore much improved. 

Even if the ECC function is performed on groups of four bytes, a single byte can be written/cycled independently. In this case, the ECC function also writes/cycles the three other bytes located in the same group (see note). As a consequence, the maximum cycling budget is defined at group level and the cycling can be distributed over the four bytes of the group: the sum of the cycles seen by byte0, byte1, byte2 and byte3 of the same group must remain below the maximum value defined in Table 11. 

_Note:_ 

_A group of four bytes is located at addresses [4*N, 4*N+1, 4*N+2, 4*N+3], where N is an integer._ 

## **6.7 Read identification page (available only in M95M01-D devices)** 

The identification page (256 bytes) is an additional page that can be written and (later) permanently locked in read-only mode. 

Reading this page is achieved with the read identification page instruction (see Table 3). The chip select signal (S) is first driven low, the bits of the instruction byte and address bytes are then shifted in, on serial data Input (D). Address bit A10 must be 0, upper address bits are Don't care, and the data byte pointed to by the lower address bits [A7:A0] is shifted out on serial data output (Q). If chip select (S) continues to be driven low, the internal address register is automatically incremented, and the byte of data at the new address is shifted out. 

The number of bytes to read in the ID page must not exceed the page boundary, otherwise unexpected data is read (e.g.: when reading the ID page from location 90d, the number of bytes should be less than or equal to 166d, as the ID page boundary is 256 bytes). 

The read cycle is terminated by driving chip select (S) high. The rising edge of the chip select (S) signal can occur at any time during the cycle. The first byte addressed can be any byte within any page. 

The instruction is not accepted, and is not executed, if a write cycle is currently in progress. 

**DS5137** - **Rev 16** 

**page 18/46** 

**M95M01-DF M95M01-R Write identification page (available only in M95M01-D devices)** 

**Figure 15. Read identification page sequence** 

**==> picture [443 x 172] intentionally omitted <==**

**----- Start of picture text -----**<br>
S<br>0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39<br>C<br>Instruction 24-bit address<br>D 23 22 21 3 2 1 0<br>MSB<br>Data Out 1 Data Out 2<br>High impedance<br>Q 7 6 5 4 3 2 1 0 7<br>MSB<br>MS30907V2<br>**----- End of picture text -----**<br>


## **6.8 Write identification page (available only in M95M01-D devices)** 

The identification page (256 bytes) is an additional page that can be written and (later) permanently locked in read-only mode. 

Writing this page is achieved with the write identification page instruction (see Table 3). The chip select signal (S) is first driven low. The bits of the instruction byte, address bytes, and at least one data byte are then shifted in on serial data input (D). Address bit A10 must be 0, upper address bits are Don't care, the lower address bits [A7:A0] address bits define the byte address inside the identification page. The instruction sequence is shown in Figure 16. 

**Figure 16. Write identification page sequence** 

**==> picture [384 x 134] intentionally omitted <==**

**----- Start of picture text -----**<br>
S<br>0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39<br>C<br>Instruction 24-bit address Data byte<br>D 23 22 21 3 2 1 0 7 6 5 4 3 2 1 0<br>High impedance<br>Q<br>**----- End of picture text -----**<br>


## **6.9 Read lock status (available only in M95M01-D devices)** 

The read lock status instruction (see Table 3) is used to check whether the identification page is locked or not in read-only mode. The read lock status sequence is defined with the chip select (S) first driven low. The bits of the instruction byte and address bytes are then shifted in on serial data input (D). Address bit A10 must be 1, all other address bits are Don't care. The lock bit is the LSB (least significant bit) of the byte read on serial data otput (Q). It is at “1” when the lock is active and at “0” when the lock is not active. If chip select (S) continues to be driven low, the same data byte is shifted out. The read cycle is terminated by driving chip select (S) high. 

The instruction sequence is shown in Figure 17. 

**DS5137** - **Rev 16** 

**page 19/46** 

**M95M01-DF M95M01-R Lock ID (available only in M95M01-D devices)** 

**Figure 17. Read lock status sequence** 

**==> picture [389 x 146] intentionally omitted <==**

**----- Start of picture text -----**<br>
S<br>0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39<br>C<br>Instruction 24-bit addres s<br>D 23 22 21 3 2 1 0<br>MSB<br>Data Out 1 Data Out 2<br>High impedance<br>Q 7 6 5 4 3 2 1 0 7<br>MSB<br>MS30910V1<br>**----- End of picture text -----**<br>


## **6.10 Lock ID (available only in M95M01-D devices)** 

The Lock ID instruction permanently locks the identification page in read-only mode. Before this instruction can be accepted, a write enable (WREN) instruction must have been executed. 

The lock ID instruction is issued by driving chip select (S) low, sending the instruction code, the address and a data byte on serial data input (D), and driving chip select (S) high. In the address sent, A10 must be equal to 1, all other address bits are Don't care. The data byte sent must be equal to the binary value xxxx xx1x, where x = Don't care. 

Chip select (S) must be driven high after the rising edge of serial clock (C) that latches in the eighth bit of the data byte, and before the next rising edge of serial clock (C). Otherwise, the lock ID instruction is not executed. Driving chip select (S) high at a byte boundary of the input data triggers the self-timed write cycle whose duration is tW (as specified in AC characteristics in Section 9). The instruction sequence is shown in Figure 18. 

The instruction is discarded, and is not executed, under the following conditions: 

- if a write cycle is already in progress, 

- if the block protect bits (BP1,BP0) = (1,1), 

- if a rising edge on chip select (S) happens outside of a byte boundary. 

## **Figure 18. Lock ID sequence** 

**==> picture [380 x 132] intentionally omitted <==**

**----- Start of picture text -----**<br>
S<br>0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39<br>C<br>Instruction 24-bit address Data byte<br>D 23 22 21 3 2 1 0 7 6 5 4 3 2 1 0<br>High impedance<br>Q<br>**----- End of picture text -----**<br>


**DS5137** - **Rev 16** 

**page 20/46** 

**M95M01-DF M95M01-R Power-up and delivery state** 

## **7 Power-up and delivery state** 

## **7.1 Power-up state** 

After power-up, the device is in the following state: 

- Standby power mode, 

- deselected (after power-up, a falling edge is required on chip select (S) before any instructions can be started), 

- not in the hold condition, 

- the write enable latch (WEL) is reset to 0, 

- write in progress (WIP) is reset to 0. 

The SRWD, BP1 and BP0 bits of the status register are unchanged from the previous power-down (they are nonvolatile bits). 

## **7.2** 

## **Initial delivery state** 

The device is delivered with the memory array bits and identification page bits set to all 1s (each byte = FFh). The status register write disable (SRWD) and block protect (BP1 and BP0) bits are initialized to 0. 

**DS5137** - **Rev 16** 

**page 21/46** 

**M95M01-DF M95M01-R Maximum ratings** 

## **8 Maximum ratings** 

Stressing the device outside the ratings listed in Table 7 may cause permanent damage to the device. These are stress ratings only, and operation of the device at these, or any other conditions outside those indicated in the operating sections of this specification, is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 

**Table 7. Absolute maximum ratings** 

|**Symbol**|**Parameter**|**Min.**|**Max.**|**Unit**|
|---|---|---|---|---|
|-|Ambient operating temperature|-40|130|°C|
|TSTG|Storage temperature|-65|150|°C|
|TLEAD|Lead temperature during soldering|See note(1)||°C|
|VO|Output voltage|-0.50|VCC+0.6|V|
|VI|Input voltage|-0.50|6.5|V|
|VCC|Supply voltage|-0.50|6.5|V|
|IOL|DC output current (Q = 0)|-|5|mA|
|IOH|DC output current (Q = 1)|-|5|mA|
|VESD|Electrostatic discharge voltage (human body model)(2)|-|4000|V|



_1. Compliant with JEDEC standard J-STD-020 (for small-body, Sn-Pb or Pb free assembly), the ST ECOPACK 7191395 specification, and the European directive on Restrictions on Hazardous Substances (RoHS directive 2011/65/EU of July 2011)._ 

_2. Positive and negative pulses applied on different combinations of pin connections, according to ANSI/ESDA/JEDEC JS-001, C1=100 pF, R1=1500 Ω, R2 = 500 Ω._ 

**DS5137** - **Rev 16** 

**page 22/46** 

**M95M01-DF M95M01-R DC and AC parameters** 

## **9** 

## **DC and AC parameters** 

This section summarizes the operating conditions and the DC/AC characteristics. 

**Table 8. Operating conditions (M95M01-R)** 

|**Symbol**|**Parameter**|**Min.**|**Max.**|**Unit**|
|---|---|---|---|---|
|VCC|Supply voltage|1.8|5.5|V|
|TA|Ambient operating temperature|–40|85|°C|



**Table 9. Operating conditions (M95M01-DF)** 

|**Symbol**|**Parameter**|**Min.**|**Max.**|**Unit**|
|---|---|---|---|---|
|VCC|Supply voltage|1.7|5.5|V|
|TA|Ambient operating temperature|–40|85|°C|



**Table 10. AC measurement conditions** 

|**Symbol**|**Parameter**|**Min.**|**Max.**|**Unit**|
|---|---|---|---|---|
|CL|Load capacitance|-|100|pF|
|-|Input rise and fall times|-|50|ns|
|-|Input pulse voltages|0.2 VCCto 0.8 VCC||V|
|-|Input and output timing reference voltages|0.3 VCCto 0.7 VCC||V|



## **Figure 19. AC measurement I/O waveform** 

**==> picture [454 x 97] intentionally omitted <==**

**----- Start of picture text -----**<br>
Input and Output<br>Input Levels<br>Timing Reference Levels<br>0.8 ₓ VCC<br>0.7 ₓ VCC<br>0.3 ₓ VCC<br>0.2 ₓ VCC<br>AI00825C<br>**----- End of picture text -----**<br>


**Table 11. Cycling performance by groups of four bytes** 

|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Max.**|**Unit**|
|---|---|---|---|---|---|
|Ncycle|Write cycle endurance(1)|TA≤ 25 °C,<br>VCC(min) < VCC< VCC(max)|-|4,000,000|Write cycle(2)|
|||TA= 85 °C,<br>VCC(min) < VCC< VCC(max)|-|1,200,000||



_1. The write cycle endurance is defined for groups of four data bytes located at addresses [4*N, 4*N+1, 4*N+2, 4*N+3], where N is an integer. The write cycle endurance is defined by characterization and qualification._ 

_2. A write cycle is executed when either a page write, a byte write, a WRSR, a WRID or an LID instruction is decoded. When using the byte write, the page write or the WRID instruction, refer also to Cycling with error correction code (ECC x 4)_ 

**DS5137** - **Rev 16** 

**page 23/46** 

**M95M01-DF M95M01-R DC and AC parameters** 

**Table 12. Memory cell data retention** 

|**Parameter**|**Test conditions**|**Min.**|**Unit**|
|---|---|---|---|
|Data retention(1)|TA= 55 °C|200|Year|



_1. The data retention behavior is checked in production, while the 200-year limit is defined from characterization and qualification results._ 

## **Table 13. Capacitance** 

|**Symbol**|**Parameter**|**Test conditions(1)**|**Min.**|**Max.**|**Unit**|
|---|---|---|---|---|---|
|COUT|Output capacitance (Q)|VOUT= 0 V|-|8|pF|
|CIN|Input capacitance (D)|VIN= 0 V|-|8|pF|
||Input capacitance (other pins)|VIN= 0 V|-|6|pF|



_1. Evaluated by characterization – not tested in production._ 

**DS5137** - **Rev 16** 

**page 24/46** 

**M95M01-DF M95M01-R DC and AC parameters** 

## **Table 14. DC characteristics** 

|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Max.**|**Unit**|
|---|---|---|---|---|---|
|ILI|Input leakage current|VIN= VSSor VCC|-|± 2|µA|
|ILO|Output leakage current|S = VCC, VOUT= VSSor VCC|-|± 2|µA|
|ICC|Supply current (read)|C = 0.1 VCC/0.9 VCCat 2 MHz, VCC= 1.8 V(1), Q = open|-|1.5|mA|
|||C = 0.1 VCC/0.9 VCCat 5 MHz, VCC= 1.8 V(1), Q = open|-|2|mA|
|||C = 0.1 VCC/0.9 VCCat 5 MHz, VCC= 2.5 V, Q = open|-|4|mA|
|||C = 0.1 VCC/0.9 VCCat 10 MHz, VCC= 2.5 V, Q = open|-|2|mA|
|||C = 0.1 VCC/0.9 VCCat 5 MHz, VCC= 5 V, Q = open|-|5|mA|
|||C = 0.1 VCC/0.9 VCCat 10 MHz, VCC= 5.5 V, Q = open|-|5|mA|
|ICC0(2)|Supply current (write)|During tW,<br>S = VCC,|-|5|mA|
|ICC1|Supply current<br>(standby power mode)|S = VCC, VIN= VSSor VCC, VCC= 1.8 V(1)|-|3|µA|
|||S = VCC, VIN= VSSor VCC,<br>VCC= 1.8 V(1), temp = 25 °C (or less)|-|1|µA|
|||S = VCC, VIN= VSSor VCC, VCC= 2.5 V|-|3|µA|
|||S = VCC, VIN= VSSor VCC,<br>VCC= 2.5 V, temp = 25 °C (or less)|-|1|µA|
|||S = VCC, VIN= VSSor VCC, VCC= 5.5 V|-|5|µA|
|||S = VCC, VIN= VSSor VCC,<br>VCC= 5.5 V, temp = 25 °C (or less)|-|1.5|µA|
|VIL|Input low voltage|1.8 V(1)≤ VCC< 2.5 V|-0.45|0.25 VCC|V|
|||2.5 V ≤ VCC≤ 5.5 V|-0.45|0.3 VCC||
|VIH|Input high voltage|1.8 V(1)≤ VCC< 2.5 V|0.75 VCC|VCC+ 1|V|
|||2.5 V ≤ VCC≤ 5.5 V|0.7 VCC|VCC+ 1||
|VOL|Output low voltage|IOL= 0.15 mA, VCC= 1.8 V(1)|-|0.3|V|
|||VCC= 2.5 V, IOL= 1.5 mA or<br>VCC= 5 V, IOL= 2 mA|-|0.4|V|
|VOH|Output high voltage|IOH= -0.1 mA, VCC= 1.8 V(1)|0.8 VCC|-|V|
|||VCC= 2.5 V, IOH= -0.4 mA or<br>VCC= 5 V, IOH= -2 mA||||



_1. Or VCC = 1.7 V for the M95M01-DF._ 

_2. Evaluated by characterization – not tested in production._ 

**DS5137** - **Rev 16** 

**page 25/46** 

**M95M01-DF M95M01-R DC and AC parameters** 

## **Table 15. AC characteristics** 

|||**Test conditions specified inTable 8, Table 9 andTable 10**|**Test conditions specified inTable 8, Table 9 andTable 10**|**Test conditions specified inTable 8, Table 9 andTable 10**|**Test conditions specified inTable 8, Table 9 andTable 10**|**Test conditions specified inTable 8, Table 9 andTable 10**|**Test conditions specified inTable 8, Table 9 andTable 10**|**Test conditions specified inTable 8, Table 9 andTable 10**|**Test conditions specified inTable 8, Table 9 andTable 10**|**Test conditions specified inTable 8, Table 9 andTable 10**||
|---|---|---|---|---|---|---|---|---|---|---|---|
|**Smbol**|**Alt**|**Parameter**|**VCC ≥1.7 V**||**VCC ≥1.8 V**||**VCC ≥2.5 V**||**VCC ≥4.5 V**||**Unit**|
|**y**|**.**||**Min.**|**Max.**|**Min.**|**Max.**|**Min.**|**Max.**|**Min.**|**Max.**||
|fC|fSCK|Clock frequency|DC|2|DC|5|DC|10|DC|16|MHz|
|tSLCH|tCSS1|S active setup time|150|-|60|-|30|-|20|-|ns|
|tSHCH|tCSS2|S not active setup time|150|-|60|-|30|-|20|-|ns|
|tSHSL|tCS|S deselect time|200|-|60|-|40|-|25|-|ns|
|tCHSH|tCSH|S active hold time|150|-|60|-|30|-|20|-|ns|
|tCHSL|-|S not active hold time|150|-|60|-|30|-|20|-|ns|
|tCH(1)|tCLH|Clock high time|200|-|90|-|40|-|25|-|ns|
|tCL(1)|tCLL|Clock low time|200|-|90|-|40|-|25|-|ns|
|tCLCH(2)|tRC|Clock rise time|-|2|-|2|-|-|-|2|µs|
|tCHCL(2)|tFC|Clock fall time|-|2|-|2|-|-|-|2|µs|
|tDVCH|tDSU|Data in setup time|50|-|20|-|10|-|10|-|ns|
|tCHDX|tDH|Data in hold time|50|-|20|-|10|-|10|-|ns|
|tHHCH|-|Clock low hold time after<br>HOLD not active|150|-|60|-|30|-|25|-|ns|
|tHLCH|-|Clock low hold time after<br>HOLD active|150|-|60|-|30|-|20|-|ns|
|tCLHL|-|Clock low set-up time before<br>HOLD active|0|-|0|-|0|-|0|-|ns|
|tCLHH|-|Clock low set-up time before<br>HOLD not active|0|-|0|-|0|-|0|-|ns|
|tSHQZ(2)|tDIS|Output disable time|-|200|-|80|-|40|-|25|ns|
|tCLQV|tV|Clock low to output valid|-|200|-|80|-|40|-|25|ns|
|tCLQX|tHO|Output hold time|0|-|0|-|0|-|0|-|ns|
|tQLQH(2)|tRO|Output rise time|-|200|-|80|-|40|-|25|ns|
|tQHQL(2)|tFO|Output fall time|-|200|-|80|-|40|-|25|ns|
|tHHQV|tLZ|HOLD high to output valid|-|200|-|80|-|40|-|25|ns|
|tHLQZ(2)|tHZ|HOLD low to output high-Z|-|200|-|80|-|40|-|25|ns|
|tW|tWC|Write time|-|5|-|5|-|5|-|5|ms|



_1. tCH + tCL must never be less than the shortest possible clock period, 1 / fC(max)_ 

_2. Evaluated by characterization - not tested in production._ 

**DS5137** - **Rev 16** 

**page 26/46** 

**M95M01-DF M95M01-R DC and AC parameters** 

**Figure 20. Serial input timing** 

**==> picture [389 x 161] intentionally omitted <==**

**----- Start of picture text -----**<br>
tSHSL<br>S<br>tCHSL tSLCH tCH tCHSH tSHCH<br>C<br>tDVCH tCHCL tCL tCLCH<br>tCHDX<br>D<br>MSB IN LSB IN<br>High impedance<br>Q<br>**----- End of picture text -----**<br>


**==> picture [30 x 6] intentionally omitted <==**

**----- Start of picture text -----**<br>
AI01447d<br>**----- End of picture text -----**<br>


**Figure 21. Hold timing** 

**==> picture [374 x 140] intentionally omitted <==**

**----- Start of picture text -----**<br>
S<br>tHLCH<br>tCLHL tHHCH<br>C<br>tCLHH<br>tHLQZ tHHQV<br>Q<br>HOLD<br>**----- End of picture text -----**<br>


**==> picture [29 x 6] intentionally omitted <==**

**----- Start of picture text -----**<br>
AI01448c<br>**----- End of picture text -----**<br>


**Figure 22. Serial output timing** 

**==> picture [377 x 135] intentionally omitted <==**

**----- Start of picture text -----**<br>
S<br>tCH tSHSL<br>C<br>tCLQV tCLCH tCHCL tCL tSHQZ<br>tCLQX<br>Q<br>tQLQH<br>tQHQL<br>ADDR<br>D LSB IN<br>**----- End of picture text -----**<br>


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**page 27/46** 

**M95M01-DF M95M01-R Package information** 

## **10 Package information** 

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark. 

## **10.1 SO8N package information** 

This SO8N is an 8-lead, 4.9 x 6 mm, plastic small outline, 150 mils body width, package. 

## **Figure 23. SO8N – Outline** 

**==> picture [309 x 165] intentionally omitted <==**

**----- Start of picture text -----**<br>
h x 45˚<br>A2 A<br>c<br>b ccc<br>e<br>0.25 mm<br>D SEATING  GAUGE PLANE<br>PLANE<br>C k<br>8<br>E1 E<br>1 A1 L<br>L1<br>**----- End of picture text -----**<br>


1. Drawing is not to scale. 

**DS5137** - **Rev 16** 

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**M95M01-DF M95M01-R** 

**SO8N package information** 

**Table 16. SO8N – Mechanical data** 

|**Symbol**<br>~~a~~|**millimeters**<br>~~ee~~ee|**millimeters**<br>~~ee~~ee|**millimeters**<br>~~ee~~ee|**inches(1)**<br>ee~~ee~~|**inches(1)**<br>ee~~ee~~|**inches(1)**<br>ee~~ee~~|
|---|---|---|---|---|---|---|
||**Min.**<br>~~e~~|**Typ.**<br>~~ee~~|**Max.**<br>ee|**Min.**<br>ee|**Typ.**<br>~~e~~|**Max.**<br>~~ee~~|
|A<br>~~a~~|-<br>~~e~~|-<br>~~ee ~~|1.750<br> ee|-<br> ee|-<br> ~~e~~|0.0689<br>~~ee~~|
|A1|0.100|-|0.250|0.0039|-|0.0098|
|A2|1.250|-|-|0.0492|-|-|
|b|0.280|-|0.480|0.0110|-|0.0189|
|c|0.170|-|0.230|0.0067|-|0.0091|
|D(2)|4.800|4.900|5.000|0.1890|0.1929|0.1969|
|E|5.800|6.000|6.200|0.2283|0.2362|0.2441|
|E1(3)|3.800|3.900|4.000|0.1496|0.1535|0.1575|
|e|-|1.270|-|-|0.0500|-|
|h|0.250|-|0.500|0.0098|-|0.0197|
|k|0°|-|8°|0°|-|8°|
|L|0.400|-|1.270|0.0157|-|0.0500|
|L1|-|1.040|-|-|0.0409|-|
|ccc|-|-|0.100|-|-|0.0039|



_1. Values in inches are converted from mm and rounded to four decimal digits._ 

_2. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusions or gate burrs shall not exceed 0.15 mm per side_ 

_3. Dimension “E1” does not include interlead flash or protrusions. Interlead flash or protrusions shall not exceed 0.25 mm per side._ 

_Note: The package top may be smaller than the package bottom. Dimensions D and E1 are determinated at the outermost extremes of the plastic body exclusive of mold flash, tie bar burrs, gate burrs and interleads flash, but including any mismatch between the top and bottom of plastic body. Measurement side for mold flash, protusions or gate burrs is bottom side._ 

**Figure 24. SO8N - Footprint example** 

**==> picture [235 x 153] intentionally omitted <==**

**----- Start of picture text -----**<br>
0.6 (x8)<br>af<br>nae<br>1.27<br>3.9 6.7<br>O7_SO8N_FP_V2<br>**----- End of picture text -----**<br>


1. Dimensions are expressed in millimeters. 

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**M95M01-DF M95M01-R TSSOP8 package information** 

## **10.2 TSSOP8 package information** 

This TSSOP is an 8-lead, 3 x 6.4 mm, 0.65 mm pitch, thin shrink small outline package. 

## **Figure 25. TSSOP8 – Outline** 

**==> picture [322 x 216] intentionally omitted <==**

**----- Start of picture text -----**<br>
D<br>8 5<br>Seating<br>plane<br>C<br>k<br>E1 E<br>A1 L<br>Pin 1 identification<br>L1<br>1 4<br>e<br>D E1<br>A2 A<br>c<br>A1<br>b<br>aaa C e<br>**----- End of picture text -----**<br>


1. Drawing is not to scale. 

**Table 17. TSSOP8 – Mechanical data** 

|**Smbol**|**millimeters**|**millimeters**|**millimeters**|**inches(1)**|**inches(1)**|**inches(1)**|
|---|---|---|---|---|---|---|
|**y**|**Min.**|**Typ.**|**Max.**|**Min.**|**Typ.**|**Max.**|
|A|-|-|1.200|-|-|0.0472|
|A1|0.050|-|0.150|0.0020|-|0.0059|
|A2|0.800|1.000|1.050|0.0315|0.0394|0.0413|
|b|0.190|-|0.300|0.0075|-|0.0118|
|c|0.090|-|0.200|0.0035|-|0.0079|
|D(2)|2.900|3.000|3.100|0.1142|0.1181|0.1220|
|e|-|0.650|-|-|0.0256|-|
|E|6.200|6.400|6.600|0.2441|0.2520|0.2598|
|E1(3)|4.300|4.400|4.500|0.1693|0.1732|0.1772|
|L|0.450|0.600|0.750|0.0177|0.0236|0.0295|
|L1|-|1.000|-|-|0.0394|-|
|k|0°|-|8°|0°|-|8°|
|aaa|-|-|0.100|-|-|0.0039|



_1. Values in inches are converted from mm and rounded to four decimal digits._ 

_2. Dimension “D” does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side._ 

_3. Dimension “E1” does not include interlead flash or protrusions. Interlead flash or protrusions shall not exceed 0.25 mm per side._ 

**DS5137** - **Rev 16** 

**page 30/46** 

**M95M01-DF M95M01-R TSSOP8 package information** 

_Note:_ 

_The package top may be smaller than the package bottom. Dimensions D and E1 are determinated at the outermost extremes of the plastic body exclusive of the mold flash, tie bar burrs, gate burrs, and interleads flash, but including any mismatch between the top and bottom of the plastic body. The measurement side for the mold flash, protrusions, or gate burrs is the bottom side._ 

**Figure 26. TSSOP8 – Footprint example** 

**==> picture [235 x 124] intentionally omitted <==**

**----- Start of picture text -----**<br>
1.55<br>5.80<br>7.35<br>0.40<br>0.65<br>2.35<br>**----- End of picture text -----**<br>


1. Dimensions are expressed in millimeters. 

**DS5137** - **Rev 16** 

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**M95M01-DF M95M01-R WLCSP8 (CS) package information** 

## **10.3 WLCSP8 (CS) package information** 

## **10.3.1 WLCSP8 without BSC package information** 

This WLCSP is a 8-ball, 2.578 x 1.716 mm, wafer level chip scale package. 

## **Figure 27. WLCSP8 without BSC - Outline** 

**==> picture [382 x 302] intentionally omitted <==**

**----- Start of picture text -----**<br>
bbb Z<br>D X Y e F<br>e2<br>DETAIL A<br>E e1<br>F<br>aaa A<br>(4X) A2 PIN1 G G<br>CORNER<br>TOP VIEW SIDE VIEW BOTTOM VIEW<br>BUMP<br>eee z A1<br>Z<br>2 b (8X)<br>ccc M Z X Y SEATING PLANE<br>ddd M Z<br>4 DETAIL A 3<br>ROTATED 90<br>e3 e3<br>**----- End of picture text -----**<br>


1. Dimension is measured at the maximum bump diameter parallel to primary datum C. 

2. Primary datum C and seating plane are defined by the spherical crowns of the bump. 

3. Drawing is not to scale. 

**DS5137** - **Rev 16** 

**page 32/46** 

**M95M01-DF M95M01-R WLCSP8 (CS) package information** 

**Table 18. WLCSP8 without BSC - Mechanical data** 

|**Smbol**|**millimeters**|**millimeters**|**millimeters**|**inches(1)**|**inches(1)**|**inches(1)**|
|---|---|---|---|---|---|---|
|**y**|**Min**|**Typ**|**Max**|**Min**|**Typ**|**Max**|
|A|0.500|0.540|0.580|0.0197|0.0213|0.0228|
|A1|-|0.190|-|-|0.0075|-|
|A2|-|0.350|-|-|0.0138|-|
|b(2)|-|0.270|-|-|0.0106|-|
|D|-|2.578|2.598|-|0.1015|0.1023|
|E|-|1.716|1.736|-|0.0676|0.0683|
|e|-|1.000|-|-|0.0394|-|
|e1|-|0.866|-|-|0.0341|-|
|e2|-|0.500|-|-|0.0197|-|
|e3|-|0.500|-|-|0.0197|-|
|F|-|0.425|-|-|0.0167|-|
|G|-|0.789|-|-|0.0311|-|
|aaa|-|0.110|-|-|0.0043|-|
|bbb|-|0.110|-|-|0.0043|-|
|ccc|-|0.110|-|-|0.0043|-|
|ddd|-|0.060|-|-|0.0024|-|
|eee|-|0.060|-|-|0.0024|-|



_1. Values in inches are converted from mm and rounded to 4 decimal digits._ 

_2. Dimension is measured at the maximum bump diameter parallel to primary datum Z._ 

**Figure 28. WLCSP8 without BSC - Footprint example** 

**==> picture [155 x 83] intentionally omitted <==**

**----- Start of picture text -----**<br>
1.0<br>0.5<br>0.5 0.5 0.866<br>**----- End of picture text -----**<br>


1. Dimensions are expressed in millimeters. 

**DS5137** - **Rev 16** 

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**M95M01-DF M95M01-R WLCSP8 (CS) package information** 

## **10.3.2 WLCSP8 with BSC package information** 

This WLCSP is a 8-ball, 2.578 x 1.716 mm, wafer level chip scale package. 

## **Figure 29. WLCSP8 with BSC - Outline** 

**==> picture [382 x 302] intentionally omitted <==**

**----- Start of picture text -----**<br>
bbb Z<br>D X Y e F<br>e2<br>DETAIL A<br>E e1<br>F<br>aaa A<br>(4X) A2 PIN1 G G<br>A3 CORNER<br>TOP VIEW SIDE VIEW BOTTOM VIEW<br>BUMP<br>eee z A1<br>Z<br>2 b (8X)<br>ccc M Z X Y SEATING PLANE<br>ddd M Z<br>4 DETAIL A 3<br>ROTATED 90<br>e3 e3<br>**----- End of picture text -----**<br>


1. Dimension is measured at the maximum bump diameter parallel to primary datum C. 

2. Primary datum C and seating plane are defined by the spherical crowns of the bump. 

3. Drawing is not to scale. 

**DS5137** - **Rev 16** 

**page 34/46** 

**M95M01-DF M95M01-R WLCSP8 (CS) package information** 

**Table 19. WLCSP8 with BSC - Mechanical data** 

|**Smbol**|**millimeters**|**millimeters**|**millimeters**|**inches(1)**|**inches(1)**|**inches(1)**|
|---|---|---|---|---|---|---|
|**y**|**Min**|**Typ**|**Max**|**Min**|**Typ**|**Max**|
|A|0.525|0.565|0.605|0.0207|0.0222|0.0238|
|A1|-|0.190|-|-|0.0075|-|
|A2|-|0.350|-|-|0.0138|-|
|A3|-|0.025|-|-|0.0010|-|
|b(2)|-|0.270|-|-|0.0106|-|
|D|-|2.578|2.598|-|0.1015|-|
|E|-|1.716|1.736|-|0.0676|0.1023|
|e|-|1.000|-|-|0.0394|0.0683|
|e1|-|0.866|-|-|0.0341|-|
|e2|-|0.500|-|-|0.0197|-|
|e3|-|0.500|-|-|0.0197|-|
|F|-|0.425|-|-|0.0167|-|
|G|-|0.789|-|-|0.0311|-|
|aaa|-|0.110|-|-|0.0043|-|
|bbb|-|0.110|-|-|0.0043|-|
|ccc|-|0.110|-|-|0.0043|-|
|ddd|-|0.060|-|-|0.0024|-|
|eee|-|0.060|-|-|0.0024|-|



_1. Values in inches are converted from mm and rounded to 4 decimal digits._ 

_2. Dimension is measured at the maximum bump diameter parallel to primary datum Z._ 

## **Figure 30. WLCSP8 with BSC- Footprint example** 

**==> picture [155 x 83] intentionally omitted <==**

**----- Start of picture text -----**<br>
1.0<br>0.5<br>0.5 0.5 0.866<br>**----- End of picture text -----**<br>


**==> picture [7 x 69] intentionally omitted <==**

**----- Start of picture text -----**<br>
E1_1M_WLCSP8_FP_V1<br>**----- End of picture text -----**<br>


1. Dimensions are expressed in millimeters. 

**DS5137** - **Rev 16** 

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**M95M01-DF M95M01-R WLCSP8 ultra thin (CU) package information** 

## **10.4 WLCSP8 ultra thin (CU) package information** 

## **10.4.1 WLCSP8 package information** 

This WLCSP8 is an 8-ball, 2.578 x 1.716 mm, 0.5 mm pitch, wafer level chip scale package. 

## **Figure 31. WLCSP8 with BSC - Outline** 

**==> picture [364 x 254] intentionally omitted <==**

**----- Start of picture text -----**<br>
aaa<br>(2x)<br>D X bbb Z e<br>DETAIL A e2<br>Y<br>G<br>F<br>E b e1<br>A1<br>aaa A<br>Orientation reference (2x) A2 Orientation reference<br>A3<br>TOP VIEW SIDE VIEW BOTTOM VIEW<br>eee Z A1<br>b(8x) Z<br>ccc M Z X Y<br>ddd M Z SEATING PLANE<br>DETAIL A<br>ROTATED 90<br>e2<br>e2<br>**----- End of picture text -----**<br>


1. Drawing is not to scale. 

2. Dimension is measured at the maximum bump diameter parallel to primary datum Z. 

3. Primary datum Z and seating plane are defined by the spherical crowns of the bump. 4. Bump position designation per JESD 95-1, SPP-010. 

**DS5137** - **Rev 16** 

**page 36/46** 

**M95M01-DF M95M01-R WLCSP8 ultra thin (CU) package information** 

**Table 20. WLCSP8 with BSC - Mechanical data** 

|**Smbol**|**millimeters**|**millimeters**|**millimeters**|**inches(1)**|**inches(1)**|**inches(1)**|
|---|---|---|---|---|---|---|
|**y**|**Min**|**Typ**|**Max**|**Min**|**Typ**|**Max**|
|A|0.255|0.295|0.335|0.01|0.0116|0.0132|
|A1|-|0.095|-|-|0.0037|-|
|A2|-|0.175|-|-|0.0069|-|
|A3|-|0.025|-|-|0.001|-|
|b|-|0.185|-|-|0.0073|-|
|D|-|2.578|2.598|-|0.1015|0.1023|
|E|-|1.716|1.736|-|0.0676|0.0683|
|e|-|1|-|-|0.0394|-|
|e1|-|0.866|-|-|0.0341|-|
|e2|-|0.5|-|-|0.0197|-|
|F|-|0.425|-|-|0.0167|-|
|G|-|0.789|-|-|0.0311|-|
|aaa|-|0.11|-|-|0.0043|-|
|bbb|-|0.11|-|-|0.0043|-|
|ccc|-|0.11|-|-|0.0043|-|
|ddd|-|0.06|-|-|0.0024|-|
|eee|-|0.06|-|-|0.0024|-|



_1. Values in inches are converted from mm and rounded to 4 decimal digits._ 

**Figure 32. WLCSP8 - Footprint example** 

**==> picture [145 x 113] intentionally omitted <==**

**----- Start of picture text -----**<br>
1.0<br>0.5<br>0.866<br>0.185<br>0.5<br>0.5<br>**----- End of picture text -----**<br>


1. Dimensions are expressed in millimeters. 

**DS5137** - **Rev 16** 

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**M95M01-DF M95M01-R Ordering information** 

**11 Ordering information** 

## **Table 21. Ordering information scheme** 

|Example:|M95|M95|M01|M01|-D|-D|R|R|MN|MN|6|6|T|T|P|P|/K|/K|F|F|
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|**Device type**|||||||||||||||||||||
|M95 = SPI serial access EEPROM|||||||||||||||||||||
|**Device function**|||||||||||||||||||||
|M01 = 1 Mbit (131072 x 8)|||||||||||||||||||||
|**Device family**|||||||||||||||||||||
|-D = with identification page|||||||||||||||||||||
|blank = Without identification page|||||||||||||||||||||
|**Operating voltage**|||||||||||||||||||||
|R = VCC= 1.8 to 5.5 V|||||||||||||||||||||
|F = VCC= 1.7 to 5.5 V|||||||||||||||||||||
|**Package**(1)|||||||||||||||||||||
|MN = SO8 (150 mil width)|||||||||||||||||||||
|DW = TSSOP8 (169 mil width)|||||||||||||||||||||
|CS = WLCSP|||||||||||||||||||||
|CU = WLCSP Ultra thin|||||||||||||||||||||
|**Device grade**|||||||||||||||||||||
|6 = Industrial temperature range, - 40 to 85 °C|||||||||||||||||||||
|Device tested with standard test flow|||||||||||||||||||||
|**Option**|||||||||||||||||||||
|T = Tape and reel packing|||||||||||||||||||||
|blank = tube packing|||||||||||||||||||||
|**Plating technology**|||||||||||||||||||||
|P or G = ECOPACK2|||||||||||||||||||||
|**Process**(2)|||||||||||||||||||||
|/K = Manufacturing technology code|||||||||||||||||||||
|**Option**|||||||||||||||||||||
|F = Back side coating|||||||||||||||||||||
|blank = no back side coating|||||||||||||||||||||



_1. All packages are ECOPACK2® (RoHS-compliant and free of brominated, chlorinated and antimony-oxide flame retardants)._ 

_2. The process letters apply to WLCSP devices only. The process letters appear on the device package (marking) and on the shipment box. Please contact your nearest ST Sales Office for further information._ 

_Note:_ 

_Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet qualified and therefore not approved for use in production. ST is not responsible for any consequences resulting from such use. In no event will ST be liable for the customer using any of these engineering samples in production. ST Quality has to be contacted prior to any decision to use these Engineering samples to run qualification activity._ 

**DS5137** - **Rev 16** 

**page 38/46** 

**M95M01-DF M95M01-R Ordering information** 

## **Table 22. Ordering information scheme (unsawn wafer)** 

|Example:|M95|M95|M01-D|M01-D|F|F|K|K|W|W|20|20|I|I|/90|/90|
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|**Device type**|||||||||||||||||
|M95 = SPI serial access EEPROM|||||||||||||||||
|**Device function and family**|||||||||||||||||
|M01-D = 1 Mbit (131072 x 8) with Identification page|||||||||||||||||
|**Operating voltage**|||||||||||||||||
|F = VCC= 1.7 to 5.5 V|||||||||||||||||
|**Process**|||||||||||||||||
|K= F8H|||||||||||||||||
|**Delivery form**|||||||||||||||||
|W= unsawn wafer|||||||||||||||||
|**Wafer thickness**|||||||||||||||||
|20= non-backlapped wafer|||||||||||||||||
|**Wafer testing**|||||||||||||||||
|I = inkless test|||||||||||||||||
|**Device grade**|||||||||||||||||
|90= -40 °C to 85 °C|||||||||||||||||



_Note:_ 

_Note:_ 

_For all information concerning the M95M01 delivered in unsawn wafer, please contact your nearest ST Sales Office._ 

_Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet qualified and therefore not approved for use in production. ST is not responsible for any consequences resulting from such use. In no event will ST be liable for the customer using any of these engineering samples in production. ST Quality has to be contacted prior to any decision to use these Engineering samples to run qualification activity._ 

**DS5137** - **Rev 16** 

**page 39/46** 

**M95M01-DF M95M01-R** 

## **Revision history** 

**Table 23. Document revision history** 

|**Date**|**Revision**|**Changes**|
|---|---|---|
|13-Mar-2007|1|Initial release.|
|15-May-2007|2|VCCconditions modified inTable 15. Small text changes.|
|21-Jun-2007|3|The device endurance is specified at more than 1 000 000 (1 million) cycles (corrected on page 1).|
|17-Jul-2007|4|•<br>_Schmitt trigger inputs for enhanced noise margin_added to Features on page 1.<br>•<br>VILand VIHvalues modified according to voltage range in_Table 12: DC characteristics_<br>_(M95M01-R6)_.|
|24-Jan-2008|5|•<br>Document status promoted from preliminary data to full datasheet.<br>•<br>ICC0 modified inTable 14(M95M01-R6).<br>•<br>InPackage information, values in inches are converted from mm and rounded to 4 decimal<br>digits.<br>•<br>Available products (package, voltage range, temperature grade) added.<br>•<br>Small text changes.|
|07-May-2009|6|•<br>WLCSP package added (see_Figure 3: WLCSP connections (bottom view, bump side)_and<br>Package information).<br>•<br>Connecting to the SPI busupdated.<br>•<br>Section 5.1updated.<br>•<br>Note added toWrite to memory array (WRITE).<br>•<br>Note added toTable 15(M95M01-R6, VCC< 2.5 V).<br>•<br>_Figure 16: Serial input timing_,_Figure 17: Hold timing_and_Figure 18: Serial output timing_<br>updated.<br>ECOPACK text updated underPackage information.|
|30-Jul-2009|7|M95M01-W device grade 3 devices added (see_Table 9: Operating conditions (M95M01-W3)_,_Table_<br>_13: DC characteristics (M95M01-W3)_,_Table 14: AC characteristics (M95M01-R6 and M95M01-W3,_<br>_VCC_≥_2.5 V)_and_Table 20: Ordering information scheme_).|
|26-Mar-2012|8|Added TSSOP package. Updated:<br>•<br>Table 12: DC characteristics (M95M01-R6)<br>•<br>Table 13: DC characteristics (M95M01-W3)<br>•<br>_Table 14: AC characteristics (M95M01-R6 and M95M01-W3, VCC_≥_2.5 V)_<br>•<br>Table 15: AC characteristics (M95M01-R6, VCC< 2.5 V)<br>•<br>Figure 15: AC measurement I/O waveform<br>•<br>“Process” in_Section 12: Part numbering_<br>•<br>Deleted_Table 20: Available products (package, voltage range, temperature grade)_|
|20-Jun-2012|9|Datasheet split into:<br>•<br>M95M01-125 datasheet for automotive products (range 3),<br>•<br>M95M01-DF, M95M01-R (this datasheet) for standard products (range6).<br>Updated:<br>•<br>WLCSP package dimensions<br>•<br>Cycling and data retention performances (4 million Write cycles, 200- year data retention)<br>•<br>Table 14updated with 1.7 V values<br>•<br>Table 15updated with 16 MHz clock<br>Added:<br>•<br>Identification page (M95M01-DF)<br>•<br>1.7 V/5.5 V device (reference M95M01-DF)<br>•<br>Deleted reference M95M01-W3|
|06-Jul-2012|10|Updated WLCSP package reference from “CT” to “CS”.|
|3-Sep-2012|11|Fixed some errors in WLCSP connections for M95M01- DFCS6TP/K and M95M01-DFCU6TP/K<br>(top view, marking side, with bumps on the underside)|
|25-May-2015|12|•<br>Replaced “ball” by “bump” in the entire document.|



**DS5137** - **Rev 16** 

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**M95M01-DF M95M01-R** 

|**Date**|**Revision**|**Changes**|
|---|---|---|
|||•<br>Updated_Features_and WLCSP package figure on cover page. Removed Caution note on UV<br>exposure in_Description_. Updated_Figure: WLCSP connections for M95M01-DFCS6TP/K and_<br>_M95M01-DFCU6TP/K (top view, marking side, with bumps on the_ _underside)_,_Block diagram_<br>and_Page Write (WRITE)_.<br>•<br>UpdatedSection 5.1.3 Power-up conditions,Section 5.3 Hold condition,<br>Section 6 Instructions, andSection 7.2 Initial delivery state. UpdatedTable 7and its<br>footnotes.<br>•<br>UpdatedPackage information.<br>•<br>UpdatedOrdering informationand added Note: on Engineering samples.<br>•<br>Updated Disclaimer.|
|30-Jun-2016|13|•<br>Updated_Figure 8: Write Enable (WREN) sequence_and Figure: Write Disable (WRDI)<br>sequence.<br>•<br>Updated footnote inTable 7.<br>•<br>Updated caption ofSection 10.2 TSSOP8 package information.<br>•<br>Updated_Section 10.8: WLCSP package information_.<br>•<br>UpdatedOrdering information.|
|21-Feb-2017|14|Updated:<br>•<br>Features<br>•<br>Package information|
|08-Nov-2017|15|•<br>Added WLCSP CU package, hence updated image on cover page and added_Section 10.4:_<br>_WLCSP8 ultra thin package information_<br>•<br>UpdatedSection 5.3 Hold condition, and titles of_Section 10.3: WLCSP8 package information_<br>and ofOrdering information.<br>•<br>UpdatedTable 10. AC measurement conditionsandTable 21. Ordering information scheme.<br>•<br>UpdatedSPI modes supported,Hold condition activation,Write disable (WRDI) sequence,<br>Figure 10. Read status register (RDSR) sequence,Write status register (WRSR) sequence,<br>Byte write (WRITE) sequenceandRead identification page sequence.<br>•<br>Updated caption of_Figure 3: WLCSP connections for M95M01- DFCS6TP/K and M95M01-_<br>_DFCU6TP/K (top view, marking side, with bumps on the underside)_.<br>•<br>Updated note: inOrdering information.|
|13-Jul-2023|16|Updated:<br>•<br>Features.<br>•<br>Memory organization.<br>•<br>Connecting to the SPI bus.<br>•<br>Instructions.<br>•<br>Read from memory array (READ).<br>•<br>Table 7.<br>•<br>DC and AC parameters<br>•<br>Package information.<br>•<br>Ordering information.|



**DS5137** - **Rev 16** 

**page 41/46** 

**M95M01-DF M95M01-R Contents** 

|**Contents**|**Contents**||
|---|---|---|
|**1**|**Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2**||
|**2**|**Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4**||
|**3**|**Signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5**||
||**3.1**|Serial data output (Q) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5|
||**3.2**|Serial data input (D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5|
||**3.3**|Serial clock (C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5|
||**3.4**|Chip select (<br>S). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5|
||**3.5**|Hold (<br>HOLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5|
||**3.6**|Write protect (<br>W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5|
||**3.7**|VCCsupply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5|
||**3.8**|VSSground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5|
|**4**|**Connecting to the SPI bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6**||
||**4.1**|SPI modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6|
|**5**|**Operating features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8**||
||**5.1**|Supply voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8|
|||**5.1.1**<br>Operating supply voltage (VCC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8|
|||**5.1.2**<br>Device reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8|
|||**5.1.3**<br>Power-up conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8|
|||**5.1.4**<br>Power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8|
||**5.2**|Active power and standby power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8|
||**5.3**|Hold condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9|
||**5.4**|Status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9|
||**5.5**|Data protection and protocol control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9|
|**6**|**Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11**||
||**6.1**|Write enable (WREN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12|
||**6.2**|Write disable (WRDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12|
||**6.3**|Read status register (RDSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13|
|||**6.3.1**<br>WIP bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13|
|||**6.3.2**<br>WEL bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13|
|||**6.3.3**<br>BP1, BP0 bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13|
|||**6.3.4**<br>SRWD bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14|
||**6.4**|Write status register (WRSR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14|
||**6.5**|Read from memory array (READ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16|
||**6.6**|Write to memory array (WRITE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17|



**DS5137** - **Rev 16** 

**page 42/46** 

**M95M01-DF M95M01-R Contents** 

||**6.6.1**<br>Cycling with error correction code (ECC x 4). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18|
|---|---|
||**6.7**<br>Read identification page (available only in M95M01-D devices) . . . . . . . . . . . . . . . . . . . . . . . 18|
||**6.8**<br>Write identification page (available only in M95M01-D devices) . . . . . . . . . . . . . . . . . . . . . . . 19|
||**6.9**<br>Read lock status (available only in M95M01-D devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19|
||**6.10**<br>Lock ID (available only in M95M01-D devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20|
|**7**|**Power-up and delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21**|
||**7.1**<br>Power-up state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21|
||**7.2**<br>Initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21|
|**8**|**Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22**|
|**9**|**DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23**|
|**10**|**Package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28**|
||**10.1**<br>SO8N package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28|
||**10.2**<br>TSSOP8 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30|
||**10.3**<br>WLCSP8 (CS) package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32|
||**10.3.1**<br>WLCSP8 without BSC package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32|
||**10.3.2**<br>WLCSP8 with BSC package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34|
||**10.4**<br>WLCSP8 ultra thin (CU) package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36|
||**10.4.1**<br>WLCSP8 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36|
|**11**|**Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38**|
|**Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40**||
|**List**|**of tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44**|
|**List**|**of figures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45**|



**DS5137** - **Rev 16** 

**page 43/46** 

**M95M01-DF M95M01-R List of tables** 

## **List of tables** 

|**Table**|**1.**|Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2|
|---|---|---|
|**Table**|**2.**|Write-protected block size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10|
|**Table**|**3.**|Instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11|
|**Table**|**4.**|Significant bits within the address bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11|
|**Table**|**5.**|Status register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14|
|**Table**|**6.**|Protection modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15|
|**Table**|**7.**|Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22|
|**Table**|**8.**|Operating conditions (M95M01-R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23|
|**Table**|**9.**|Operating conditions (M95M01-DF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23|
|**Table**|**10.**|AC measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23|
|**Table**|**11.**|Cycling performance by groups of four bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23|
|**Table**|**12.**|Memory cell data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24|
|**Table**|**13.**|Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24|
|**Table**|**14.**|DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25|
|**Table**|**15.**|AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26|
|**Table**|**16.**|SO8N – Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29|
|**Table**|**17.**|TSSOP8 – Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30|
|**Table**|**18.**|WLCSP8 without BSC - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33|
|**Table**|**19.**|WLCSP8 with BSC - Mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35|
|**Table**|**20.**|WLCSP8 with BSC - Mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37|
|**Table**|**21.**|Ordering information scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38|
|**Table**|**22.**|Ordering information scheme (unsawn wafer) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39|
|**Table**|**23.**|Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40|



**DS5137** - **Rev 16** 

**page 44/46** 

**M95M01-DF M95M01-R List of figures** 

## **List of figures** 

|**Figure**|**1.**|Logic diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2|
|---|---|---|
|**Figure**|**2.**|8-pin package connections (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3|
|**Figure**|**3.**|WLCSP connections (top view, marking side, with bumps on the underside). . . . . . . . . . . . . . . . . . . . . . . . . . 3|
|**Figure**|**4.**|Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4|
|**Figure**|**5.**|Bus master and memory devices on the SPI bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6|
|**Figure**|**6.**|SPI modes supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7|
|**Figure**|**7.**|Hold condition activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9|
|**Figure**|**8.**|Write enable (WREN) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12|
|**Figure**|**9.**|Write disable (WRDI) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12|
|**Figure**|**10.**|Read status register (RDSR) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13|
|**Figure**|**11.**|Write status register (WRSR) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14|
|**Figure**|**12.**|Read from memory array (READ) sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16|
|**Figure**|**13.**|Byte write (WRITE) sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17|
|**Figure**|**14.**|Page write (WRITE) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18|
|**Figure**|**15.**|Read identification page sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19|
|**Figure**|**16.**|Write identification page sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19|
|**Figure**|**17.**|Read lock status sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20|
|**Figure**|**18.**|Lock ID sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20|
|**Figure**|**19.**|AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23|
|**Figure**|**20.**|Serial input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27|
|**Figure**|**21.**|Hold timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27|
|**Figure**|**22.**|Serial output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27|
|**Figure**|**23.**|SO8N – Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28|
|**Figure**|**24.**|SO8N - Footprint example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29|
|**Figure**|**25.**|TSSOP8 – Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30|
|**Figure**|**26.**|TSSOP8 – Footprint example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31|
|**Figure**|**27.**|WLCSP8 without BSC - Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32|
|**Figure**|**28.**|WLCSP8 without BSC - Footprint example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33|
|**Figure**|**29.**|WLCSP8 with BSC - Outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34|
|**Figure**|**30.**|WLCSP8 with BSC- Footprint example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35|
|**Figure**|**31.**|WLCSP8 with BSC - Outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36|
|**Figure**|**32.**|WLCSP8 - Footprint example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37|



**DS5137** - **Rev 16** 

**page 45/46** 

**M95M01-DF M95M01-R** 

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**DS5137** - **Rev 16** 

**page 46/46**