LTM4710IV-1#PBF

LTM4710-1 

## Low VIN, Quad 8A Silent Switcher µModule Regulator 

## **FEATURES** 

## **DESCRIPTION** 

- n **Quad Output Step-Down µModule[®] Regulator with Configurable 8A Output Array** 

The LTM[®] 4710-1 is a quad DC/DC step-down µModule (micromodule) regulator with 8A per output. The package includes the switching controllers, the power MOSFETs, inductors and all supported components. Operating over an input voltage range of 2.5V to 5.5V. Channel 1’s output voltage can be set by only one external resistor, where the outputs for channel 2, channel 3, and channel 4 can be set by two external resistors. All output voltages are programmable up to 3.6V. 

- n **Ultralow Noise Silent Switcher[®] 2 Architecture** 

- n **CISPR32 Class B Compliant** 

- n Input Voltage Range: 2.5V to 5.5V 

- n Output Voltage Range: 0.5V to 3.6V 

- n 8A DC Output Current, Each Channel 

- n Parallelable for Higher Output Current 

- n ±1.5% Maximum Total DC Output Voltage Accuracy 

- n Selectable Switching Frequency: 1MHz to 5MHz 

The LTM4710-1 employs Silent Switcher 2 architecture with internal hot loop bypass capacitors to achieve both low Electromagnetic Interference (EMI) and high efficiency. The LTM4710-1 is packaged in a compact (6mm × 12mm × 3.54mm) LGA with presolder package and is RoHS compliant. 

- n Power Good Indicator 

- n Die Temperature Monitoring 

- n 6mm × 12mm × 3.54mm Land Grid Array (LGA) with Presolder Package 

## **APPLICATIONS** 

## **Configurable Output Array** 

- n Optical Communications 

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n 8A<br>16A 16A<br>n Multi-Rail Point-of-Load Regulation 8A 24A<br>32A<br>n Field Programmable Gate Arrays (FPGAs), Digital  8A 8A<br>16A<br>signal processing (DSPs) and Application Specific  8A 8A 8A<br>Integrated Circuits (ASICs) Applications<br>All registered trademarks and trademarks are the property of their respective owners.<br>n Telecom, Datacom, Networking System<br>TYPICAL APPLICATION<br>Paralleled Single Output, 32A DC/DC μModule Regulator Efficiency at 1.2VOUT<br>95<br>PGOOD PG1,2,3,4 FB1 VOUT<br>VIN 100kΩ VOSNS1 68pF 7.15kΩ 1.2V,32A 90<br>2.5V TO VIN1,2,3,4 VOUT1,2,3,4 1.2V<br>5.5V 22μF 100μF<br>× 4 FB2,3,4 × 4 85<br>RUN1,2,3,4<br>MODE1 LTM4710-1 RT1<br>(90° PHASE SHIFT) 3MΩ 80<br>MODE2,3,4 RT 2 VIN 536kΩ<br>(180° PHASE SHIFT)<br>OPT OPT 0Ω COMP1a,2a,3a,4a RT3 (270° PHASE SHIFT) 332kΩ (1.5MHz) 75<br>COMP1b RT4 VIN VIN = 5V<br>OPT AGND1,2,3,4 GND 70 VIN = 3.3V<br>47101 TA01a 0 4 8 12 16 20 24 28 32<br>LOAD CURRENT (A)<br>47101 TA01b<br>EFFICIENCY (%)<br>**----- End of picture text -----**<br>


PINS NOT SHOWN IN THIS CIRCUIT: SSTT, SW 

Rev. 0 

1 

For more information www.analog.com 

Document Feedback 

## - LTM4710 1 

## **ABSOLUTE MAXIMUM RATINGS** 

## **(Note 1)** 

All Pins Except GND and AGND _n_ ................. –0.3V to 6V Operating Junction Temperature (Note 2) ............................. –40°C to 125°C 

Storage Temperature Range .................. –55°C to 125°C Peak Solder Reflow Body Temperature .................250°C 

## **PIN CONFIGURATION** 

## **(See Pin Functions, Package Pinout Description table)** 

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TOP VIEW<br>GND NC NC VIN1<br>9<br>BANK10 BANK11 BANK12<br>NC NC NC AGND1 BANK6 GND BANK7 GND BANK8 BANK9 GND<br>8<br>NC NC NC VOSNS1 VOUT1 AGND2 VOUT2 AGND3 VOUT3 VOUT4 AGND4<br>7<br>FB1 COMP1b COMP1a RT1 FB2 COMP2b COMP2a RT2 FB3 COMP3b COMP3a RT3 FB4 COMP4b COMP4a RT4<br>6<br>RUN1 SSTT1 PG1 MODE1 RUN2 SSTT2 PG2 MODE2 RUN3 SSTT3 PG3 MODE3 RUN4 SSTT4 PG4 MODE4<br>5<br>BANK2 BANK3 BANK4 BANK5<br>4 VIN1 VIN2 VIN3 VIN4<br>3<br>BANK1<br>SW1 SW2 SW3 SW4<br>GND<br>2<br>GND GND GND GND<br>1<br>A B C D E F G H J K L M N P R T U V<br>LGA WITH PRESOLDER PACKAGE<br>162-PIN (12mm × 6mm × 3.54mm)<br>TJMAX = 125°C, θJA =  12.2°C/W, θJCTOP = 6.2°C/W, θJCBOT = 2.7°C/W<br>WEIGHT = 0.58g<br>NOTES:<br>1. θ VALUES ARE DETERMINED BY SIMULATION PER JESD-51 CONDITIONS.<br>2. θJA VALUE IS OBTAINED WITH DEMO BOARD.<br>3. REFER TO APPLICATIONS INFORMATION SECTION FOR LAB MEASURMENT AND DE-RATING INFORMATION.<br>**----- End of picture text -----**<br>


## **ORDER INFORMATION** 

|**PART NUMBER**|**PAD OR BALL FINISH**|**PART MARKING**|**PART MARKING**|**PACKAGE TYPE**|**MSL RATING**|**TEMPERATURE RANGE**<br>**(SEE NOTE 2)**|
|---|---|---|---|---|---|---|
|||**DEVICE**|**FINISH CODE**||||
|LTM4710EV-1#PBF|SAC305(RoHS)|4710-1|e1|LGA with Presolder|4|–40°C to 125°C|
|LTM4710IV-1#PBF|SAC305(RoHS)|4710-1|e1|LGA with Presolder|4|–40°C to 125°C|



- Contact the factory for parts specified with wider operating temperature ranges. Pad or ball finish code is per IPC/JEDEC J-STD-609. 

- Recommended LGA and BGA PCB Assembly and Manufacturing Procedures 

- LGA and BGA Package and Tray Drawings 

Rev. 0 

2 

For more information www.analog.com 

- LTM4710 1 

**ELECTRICAL CHARACTERISTICS The** l **denotes the specifications which apply over specified internal operating junction temperature range (Note 2), otherwise specifications are at TA = 25°C, VIN = 3.3V, per the typical application.** 

|**SYMBOL**|**PARAMETER**|**CONDITIONS**|**CONDITIONS**|**MIN**<br>**TYP**<br>**MAX**|**UNITS**|
|---|---|---|---|---|---|
|VIN|Input DC Voltage||l|2.5<br>5.5|V|
|VOUT(RANGE)|Output Voltage Range||l|0.5<br>3.6|V|
|VIN_UVLO|VINUndervoltage Lockout|VINRising||2.0<br>2.1<br>2.2|V|
|VIN_UVLO_HYS|VINUndervoltage Lockout Hysteresis|||150|mV|
|VRUN|RUN Pin On-Threshold|VRUNRising||0.375<br>0.4<br>0.425|V|
|VRUN_HYS|RUN Pin Hysteresis|||75|mV|
|IRUN|RUN Pin Leakage Current|RUN = 0.4V||±20|nA|
|IQ(VIN)|Input Supply Current|VOUT= 0.5V, MODE = FLOAT, FCM<br>Shutdown, RUN = 0V(Note 5)||50<br>2|mA<br>µA|
|IOUT(DC)|Output Continuous Current Range|VOUT= 0.5V(Note 3)||8|A|
|ΔVOUT(LINE)/VOUT|Line Regulation Accuracy|VOUT= 0.5V, VIN= 2.5V to 5.5V, IOUT= 0A||0.2|%/V|
|ΔVOUT(LOAD)/VOUT|Load Regulation Accuracy|VOUT= 0.5V, IOUT= 0A to 8A|l|0.5<br>1.5|%|
|VOUT(AC)|Output Ripple Voltage|IOUT= 0A, VOUT= 0.5V||12|mV|
|ISSTT|Track Pin Soft-Start Pull-Up Current|VSSTT= 0.5V||7<br>10<br>13|μA|
|VFB|Voltage at VFBPin||l|0.495<br>0.50<br>0.505|V|
|IFB|Current at VFBPin|(Note 4)||±20|nA|
|tON(MIN)|Minimum On-Time|||40|ns|
|VPG|Power Good Rising Threshold<br>Power Good Overvoltage Threshold|VFBas a Percentage of Regulated VOUT<br>VFBas a Percentage of Regulated VOUT||98<br>110|%<br>%|
|IPG|Power Good Leakage|VPG= 5.5V||50|nA|
|fOSC|Oscillator Frequency Range|||1<br>5|MHz|
|SYNC_RANGE|Synchronization Frequency Range|RT= VIN||1.2<br>2.6|MHz|
|SYNC_LEVEL Input|Clock Level High<br>Clock Level Low|RT= VIN||1.2<br>0.4|V<br>V|



**Note 1:** Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. 

**Note 2:** The LTM4710-1 is tested under pulsed load conditions such that TJ ≈ TA. The LTM4710E-1 is guaranteed to meet performance specifications over the 0°C to 125°C internal operating temperature range. Specifications over the full –40°C to 125°C internal operating temperature range are assured by design, characterization and correlation with statistical process controls. The LTM4710I-1 is guaranteed to meet 

specifications over the full –40°C to 125°C internal operating temperature range. Note that the maximum ambient temperature consistent with these specifications is determined by specific operating conditions in conjunction with board layout, the rated package thermal resistance and other environmental factors. 

**Note 3:** See output current thermal derating curves for different VIN, VOUT and TA. 

**Note 4:** Wafer sort tested. 

**Note 5:** Guaranteed by design. 

Rev. 0 

3 

For more information www.analog.com 

## - LTM4710 1 

## **TYPICAL PERFORMANCE CHARACTERISTICS** 

## **TA = 25°C, unless otherwise noted.** 

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Efficiency, 4-Channel Paralleled  Efficiency, 4-Channel Paralleled  Efficiency, 4-Channel Paralleled<br>VIN = 2.5V VIN = 3.3V VIN = 5.5V<br>95 95 95<br>90 90 90<br>85 85 85<br>80 80 80<br>75 75 75<br>0.5VOUT, 1.0MHz<br>70 70 0.5VOUT, 1.0MHz 70 0.8VOUT, 1.2MHz<br>0.8VOUT, 1.2MHz 1.0VOUT, 1.4MHz<br>65 0.5VOUT, 1.0MHz 65 1.0V OUT , 1.4MHz 65 1.2V OUT , 1.6MHz<br>0.8VOUT, 1.2MHz 1.2VOUT, 1.6MHz 1.5VOUT, 1.6MHz<br>1.0VOUT, 1.4MHz 1.5VOUT, 1.6MHz 1.8VOUT, 1.6MHz<br>60 60 60<br>0 4 8 12 16 20 24 28 32 0 4 8 12 16 20 24 28 32 0 4 8 12 16 20 24 28 32<br>LOAD CURRENT (A) LOAD CURRENT (A) LOAD CURRENT (A)<br>47101 G01 47101 G02 47101 G03<br>Power Loss, 4-Channel Paralleled  Power Loss, 4-Channel Paralleled  Power Loss, 4-Channel Paralleled<br>VIN = 2.5V VIN = 3.3V VIN = 5.5V<br>7 7 7<br>0.5VOUT, 1.0MHz 0.5VOUT, 1.0MHz 0.5VOUT, 1.0MHz<br>6 0.8V OUT , 1.2MHz 6 0.8V OUT , 1.2MHz 6 0.8V OUT , 1.2MHz<br>1.0VOUT, 1.4MHz 1.0VOUT, 1.4MHz 1.0VOUT, 1.4MHz<br>1.2VOUT, 1.6MHz 1.2VOUT, 1.6MHz<br>5 5 1.5V OUT , 1.6MHz 5 1.5V OUT , 1.6MHz<br>1.8VOUT, 1.6MHz<br>4 4 4<br>3 3 3<br>2 2 2<br>1 1 1<br>0 0 0<br>0 4 8 12 16 20 24 28 32 0 4 8 12 16 20 24 28 32 0 4 8 12 16 20 24 28 32<br>LOAD CURRENT (A) LOAD CURRENT (A) LOAD CURRENT (A)<br>47101 G04 47101 G05 47101 G06<br>Input vs Load Current Input vs Load Current   Input vs Load Current<br>VIN = 2.5V, 4-Channel Paralleled VIN  = 3.3V, 4-Channel Paralleled VIN  = 5.5V, 4-Channel Paralleled<br>16 18 12<br>0.5VOUT, 1.0MHz 0.5VOUT, 1.0MHz 0.5VOUT, 1.0MHz<br>14 0.8VOUT, 1.2MHz 16 0.8V OUT , 1.2MHz 0.8VOUT, 1.2MHz<br>1.0VOUT, 1.4MHz 1.0VOUT, 1.4MHz 10 1.0V OUT , 1.4MHz<br>12 14 1.2V OUT , 1.6MHz 1.2VOUT, 1.6MHz<br>12 1.5VOUT, 1.6MHz 8 1.5VOUT, 1.6MHz<br>10 1.8VOUT, 1.6MHz<br>10<br>8 6<br>8<br>6<br>6 4<br>4<br>4<br>2<br>2 2<br>0 0 0<br>0 4 8 12 16 20 24 28 32 0 4 8 12 16 20 24 28 32 0 4 8 12 16 20 24 28 32<br>LOAD CURRENT (A) LOAD CURRENT (A) LOAD CURRENT (A)<br>47101 G07 47101 G08 47101 G09<br>Rev. 0<br>4 For more information www.analog.com<br>EFFICIENCY (%) EFFICIENCY (%) EFFICIENCY (%)<br>POWER LOSS (W) POWER LOSS (W) POWER LOSS (W)<br>INPUT CURRENT (A) INPUT CURRENT (A) INPUT CURRENT (A)<br>**----- End of picture text -----**<br>


- LTM4710 1 

## **TYPICAL PERFORMANCE CHARACTERISTICS** 

## **TA = 25°C, unless otherwise noted.** 

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Efficiency, Single Channel   Efficiency, Single Channel   Efficiency, Single Channel<br>VIN  = 2.5V VIN  = 3.3V VIN  = 5.5V<br>100 100 100<br>95 95 95<br>90 90 90<br>85 85 85<br>80 80 80<br>0.5VOUT, 1.0MHz<br>75 75 0.5V 0.8V OUTOUT, 1.0MHz , 1.4MHz 75 0.8V1.0V OUT OUT, 1.2MHz, 1.4MHz<br>70 0.5V0.8VOUTOUT,, 1.2MHz 1.0MHz 70 1.0V 1.2V OUTOUT, 1.6MHz , 1.6MHz 70 1.2V1.5VOUTOUT,, 1.6MHz 1.4MHz<br>65 1.0V1.2VOUTOUT,, 1.2MHz 1.2MHz 65 1.5V 1.8V OUTOUT, 1.6MHz , 1.6MHz 65 1.8V2.5VOUTOUT,, 1.8MHz 1.6MHz<br>1.5VOUT, 1.2MHz 2.5VOUT, 1.6MHz 3.3VOUT, 2.2MHz<br>60 60 60<br>0 1 2 3 4 5 6 7 8 0 1 2 3 4 5 6 7 8 0 1 2 3 4 5 6 7 8<br>LOAD CURRENT (A) LOAD CURRENT (A) LOAD CURRENT (A)<br>47101 G10 47101 G11 47101 G12<br>Power Loss, Single Channel   Power Loss, Single Channel   Power Loss, Single Channel<br>VIN  = 2.5V VIN  = 3.3V VIN  = 5.5V<br>2.00 2.00 2.00<br>0.5VOUT, 1.0MHz 0.5VOUT, 1.0MHz 0.5VOUT, 1.0MHz<br>1.75 0.8V OUT , 1.2MHz 1.75 0.8V OUT , 1.4MHz 1.75 0.8V OUT , 1.2MHz<br>1.0VOUT, 1.2MHz 1.0VOUT, 1.6MHz 1.0VOUT, 1.4MHz<br>1.50 1.2V OUT , 1.2MHz 1.50 1.2V OUT , 1.6MHz 1.50 1.2V OUT , 1.4MHz<br>1.5VOUT, 1.2MHz 1.5VOUT, 1.6MHz 1.5VOUT, 1.6MHz<br>1.25 1.25 1.8V OUT , 1.6MHz 1.25 1.8V OUT , 1.6MHz<br>2.5VOUT, 1.6MHz 2.5VOUT, 1.8MHz<br>1.00 1.00 1.00 3.3VOUT, 2.2MHz<br>0.75 0.75 0.75<br>0.50 0.50 0.50<br>0.25 0.25 0.25<br>0 0 0<br>0 1 2 3 4 5 6 7 8 0 1 2 3 4 5 6 7 8 0 1 2 3 4 5 6 7 8<br>LOAD CURRENT (A) LOAD CURRENT (A) LOAD CURRENT (A)<br>47101 G13 47101 G14 47101 G15<br>Input vs Load Current   Input vs Load Current   Input vs Load Current<br>VIN = 2.5V, Single Channel VIN  = 3.3V, Single Channel VIN  = 5.5V, Single Channel<br>8 8 6<br>0.5VOUT, 1.0MHz 0.5VOUT, 1.0MHz 0.5VOUT, 1.0MHz<br>7 0.8V OUT , 1.2MHz 7 0.8V OUT , 1.4MHz 0.8VOUT, 1.2MHz<br>1.0VOUT, 1.2MHz 1.0VOUT, 1.6MHz 5 1.0VOUT, 1.4MHz<br>6 1.2V1.5V OUT OUT, 1.2MHz, 1.2MHz 6 1.2V1.5V OUT OUT, 1.6MHz, 1.6MHz 1.2V1.5VOUTOUT, 1.4MHz, 1.6MHz<br>5 5 1.8V2.5V OUT OUT, 1.6MHz, 1.6MHz 4 1.8V 2.5V O OUTUT , 1.6MHz , 1.8MHz<br>3.3VOUT, 2.2MHz<br>4 4 3<br>3 3<br>2<br>2 2<br>1<br>1 1<br>0 0 0<br>0 1 2 3 4 5 6 7 8 0 1 2 3 4 5 6 7 8 0 1 2 3 4 5 6 7 8<br>LOAD CURRENT (A) LOAD CURRENT (A) LOAD CURRENT (A)<br>47101 G16 47101 G17 47101 G18<br>Rev. 0<br>For more information www.analog.com 5<br>EFFICIENCY (%) EFFICIENCY (%) EFFICIENCY (%)<br>POWER LOSS (W) POWER LOSS (W) POWER LOSS (W)<br>INPUT CURRENT (A) INPUT CURRENT (A) INPUT CURRENT (A)<br>**----- End of picture text -----**<br>


## - LTM4710 1 

## **TYPICAL PERFORMANCE CHARACTERISTICS** 

**TA = 25°C, unless otherwise noted.** 

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Steady State VSW with<br>Persistence On Steady State Voltage Ripple Load Transient Response<br>VSW1<br>2V/DIV<br>VSW2<br>2V/DIV VOUT VOUT<br>AC-COUPLED AC-COUPLED<br>VSW3 10mV/DIV 50mV/DIV<br>2V/DIV<br>VSW4 IOUT<br>2V/DIV 5A/DIV<br>200ns/DIV 47101  G19 1μs/DIV 47101  G20 100μs/DIV 47101  G21<br>VfSWIN = 3.3V,  V = 1.5MHz, COUTOUT = 0.6V, I = 100μF × 4OUT = 30A,  fVSWIN = 3.3V,  V = 1.5MHz, COUTOUT = 0.6V, I = 100μF × 4OUT = 30A,  CVINOUT = 3.3V,  V = 100μF × 4, COUT = 0.6V, fFF = 20pF, SW = 1.5MHz,<br>0A ~ 7.5A (25%) LOAD STEP, 4-PHASE<br>Radiated Emissions<br>Load Regulation, 1V  8A Load on Each Channel<br>Start-Up DC3164A-B Demo Board DC3164A-B, without Ferrite Bead<br>0.5 60<br>2V/DIVVRUNVRUNRUN | 0.4 | | | 4-CHANNEL PARALLELED V IN  = 3.3V 52 PITT<br>VPGPG ! 0.3 VfSWOUT = 1.4MHz = 1V 44 CISPR32 CLASS B 10m tt TTT<br>2V/DIV | 0.2 || | | fT| fttt 36 AHereEEE<br>VOUTOUT | | | 0.1 | | | tT | tT | 28 eell<br>VSSTTSSTT 0.0 20<br>1V/DIV . –0.1 P PA Tt 12 NTL ||aia<br>é 10ms/DIV 47101  G22 –0.2 pF | | RET 4 ah oh. ol<br>VIN = 3.3V,  VOUT = 0.6V, IN = 3.3V,  VOUT = 0.6V,  = 3.3V,  VOUT = 0.6V, OUT = 0.6V,  = 0.6V,  –0.3 pF | | | | AE –4 PT LUT VIN = 3.3V<br>fSW = 1.5MHz, COUT = 100μF × 4SW = 1.5MHz, COUT = 100μF × 4 = 1.5MHz, COUT = 100μF × 4OUT = 100μF × 4 = 100μF × 4 –0.4 P| | | tt | US –12 eal VOUT1 = 0.8V, VOUT2 = 1V,<br>VOUT3 = 1.2V, VOUT4 = 1.5V<br>–0.5 | | | dP dE | tt –20 PLATT<br>0 4 8 12 16 20 24 28 32 30 100 1000<br>LOAD CURRENT (A) FREQUENCY (MHz)<br>47101 G23 47101 G24<br>LOAD REGULATION (%)<br>EMISSION LEVEL (dBμV/m)<br>**----- End of picture text -----**<br>


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2V/DIVVRUNVRUNRUN<br>VPGPG<br>2V/DIV<br>|<br>VOUTOUT | | |<br>500mV/DIV<br>VSSTTSSTT<br>1V/DIV<br>.<br>é 10ms/DIV 47101  G22<br>VIN = 3.3V,  VOUT = 0.6V, IN = 3.3V,  VOUT = 0.6V,  = 3.3V,  VOUT = 0.6V, OUT = 0.6V,  = 0.6V,<br>fSW = 1.5MHz, COUT = 100μF × 4SW = 1.5MHz, COUT = 100μF × 4 = 1.5MHz, COUT = 100μF × 4OUT = 100μF × 4 = 100μF × 4<br>**----- End of picture text -----**<br>


Rev. 0 

6 

For more information www.analog.com 

- LTM4710 1 

## **PIN FUNCTIONS** 

## **PACKAGE ROW AND COLUMN LABELING MAY VARY AMONG µModule PRODUCTS. REVIEW EACH PACKAGE LAYOUT CAREFULLY.** 

**GND (Bank 1, Banks 10 – 12, Pin A9):** Power Ground Pins for All Input and Output Returns. 

**VIN1, VIN2, VIN3, VIN4 (Banks 2 – 5, Pin D9):** Power Input Pins. Apply input voltage between these pins and GND pins. Recommend placing input decoupling capacitance directly between VIN pins and GND pins. 

**VOUT1, VOUT2, VOUT3, VOUT4 (Banks 6 – 9):** Power Output Pins of Each Switching Mode Regulator. Apply output load between these pins and GND pins. Recommend placing output decoupling capacitance directly between these pins and GND pins. 

**RUN1, RUN2, RUN3, RUN4 (Pins A5, F5, K5, R5):** Enables chip operation by connecting RUN above 0.4V. Connecting it to GND shuts down the device. 

**FB1, FB2, FB3, FB4 (Pins A6, F6, K6, R6):** The negative input of the error amplifier for the switching mode regulator channel. The LTM4710-1 regulates the voltage between FB and AGND to 500mV. For FB1, this pin is internally connected to VOSNS1 with a 10k 0.5% precision resistor. Different output voltages can be programmed with an additional resistor between VOSNS1 and AGND. For FB2, FB3 and FB4, a resistor divider connecting to VOUT sets the output voltage. In PolyPhase[®] operation, tie the FB pins to VIN to disable the internal error amplifier. See the Applications Information section for details. 

**SSTT1, SSTT2, SSTT3, SSTT4 (Pins B5, G5, L5, T5):** Soft-Start, Tracking and Temperature Monitor Pins. An internal 10μA current into an external capacitor on the soft-start pin programs the output voltage ramp rate during start-up. When SSTT is below 0.5V, the VFB pin voltage will track the SSTT pin voltage. When SSTT is above 0.5V, the tracking function is disabled, the internal reference resumes control of the error amplifier and the SSTT pin servos to a voltage representative of a junction temperature. During shutdown and fault conditions, the SSTT pin is pulled to ground. 

**COMP1b, COMP2b, COMP3b, COMP4b (Pins B6, G6, L6, T6):** Internal Compensation Network. These pins are to be connected to their respective COMPa pins. When utilizing specific external compensation, float these pins. 

**PG1, PG2, PG3, PG4 (Pins C5, H5, M5, U5):** Output power good with open-drain logic of the switching mode regulator channel. PG is pulled to ground when the voltage on the FB pin is not within –2% and +10% of the internal 0.5V reference. 

**COMP1a, COMP2a, COMP3a, COMP4a (Pins C6, H6, M6, U6):** Current control threshold and error amplifier compensation point of the switching mode regulator channel. 

**MODE1, MODE2, MODE3, MODE4 (Pins D5, J5, N5, V5):** MODE pin facilitates multiphase operation and synchronization to an external clock. Depending on the mode of operation, the MODE either accepts a clock pulse or outputs a clock pulse at its operating frequency. See the Applications Information section for details. 

**RT1, RT2, RT3, RT4 (Pins D6, J6, N6, V6):** The frequency pin sets the oscillator frequency with an external resistor to AGND or sets the phasing for multiphase operation. See the Applications Information of section for frequency adjustment. 

**VOSNS1 (Pin D7):** Output Voltage Sense Pin of Channel 1. Internally, this pin is connected to the FB1 pin with a 10k, 0.5% precision resistor. It is very important to connect this pin to the VOUT1 since this is the feedback path and cannot be left open. See the Applications Information section for details. 

**AGND1, AGND2, AGND3, AGND4 (Pins D8, H7, L7, U7):** The AGND pin is the output voltage remote ground sense. Connect the AGND pin directly to the negative terminal of the output capacitor at the load and to the feedback divider resistor. 

**SW1, SW2, SW3, SW4 (Pins G2, K2, N2, T2):** Switching node waveform monitoring. 

**NC (Pins A7, A8, B7, B8, B9, C7, C8, C9):** No Connection. Leave these pins open. 

Rev. 0 

7 

For more information www.analog.com 

- LTM4710 1 

## **BLOCK DIAGRAM** 

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PG1 VIN1<br>VIN1<br>MODE1 1µF × 2 22µF 2.5V TO 5.5V<br>RUN1 SW1<br>CURRENT MODE<br>SSTT1 CONTROLLER 70nH VOUT1 VOUT1<br>RT1 0.1µF 68pF 0.5V, 8A<br>COMP1a FB1<br>0.1μF 1.13M Ω<br>COMP1b<br>10k Ω 100µF<br>4.02k Ω 1M Ω 10nF VOSNS1<br>AGND1 3.3nF GND<br>PG2<br>VIN2<br>MODE2 VIN2<br>1µF × 2 22µF 2.5V TO 5.5V<br>RUN2 SW2<br>CURRENT MODE<br>SSTT2 CONTROLLER 70nH VOUT2<br>VOUT2<br>VIN RT2 0.1µF 68pF 10k Ω 1V, 8A<br>0.1μF COMP2a FB2<br>COMP2b<br>10k Ω<br>1M Ω<br>4.02k Ω<br>100µF<br>AGND2 3.3nF GND<br>PG3<br>VIN3<br>MODE3 VIN3<br>1µF × 2 22µF 2.5V TO 5.5V<br>RUN3 SW3<br>CURRENT MODE<br>SSTT3 CONTROLLER 70nH VOUT3<br>VOUT3<br>VIN RT3 0.1µF 68pF 10k Ω 1.2V, 8A<br>0.1μF COMP3a FB3<br>COMP3b 7.15k Ω<br>1M Ω<br>4.02k Ω 100µF<br>3.3nF<br>AGND3 GND<br>PG4<br>VIN4<br>MODE4 VIN4<br>1µF × 2 22µF 2.5V TO 5.5V<br>RUN4<br>SW4<br>CURRENT MODE<br>VIN SSTT4 CONTROLLER 70nH VOUT4 VOUT4<br>0.1μF RT4 1.5V, 8A<br>0.1µF 68pF 10k Ω<br>COMP4a FB4<br>COMP4b<br>5k Ω<br>1M Ω<br>4.02k Ω<br>100µF<br>3.3nF<br>AGND4 GND<br>47101 BD<br>DECOUPLING REQUIREMENTS (Per Channel)<br>SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS<br>CIN External Input Capacitor Requirement (VIN = 2.5V to 5.5V, VOUT = 0.5V) IOUT = 8A 22 µF<br>COUT External Output Capacitor Requirement (VIN = 2.5V to 5.5V, VOUT = 0.5V) IOUT = 8A 100 µF<br>Rev. 0<br>**----- End of picture text -----**<br>


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- LTM4710 1 

## **OPERATION** 

The LTM4710-1 is a quad output step-down switch mode DC/DC power supply. It integrates four separate regulators, each capable of delivering up to 8A continuous output current with few external input and output capacitors. Each regulator provides precisely regulated output voltage programmable from 0.5V to 3.6V over a 2.5V to 5.5V input voltage range. See typical application schematic (Figure 1). 

The LTM4710-1 integrates four separate constant-frequency peak current mode control regulators, power MOSFETs, inductors, and other supporting discrete components. It employs Silent Switcher 2 technology, which allows fast switching edges for high efficiency at high switching frequencies, while simultaneously achieving good EMI performance. Ceramic Capacitors on VIN keep all the fast AC current loops small, improving EMI performance. 

With current mode control and internal feedback loop compensation, the LTM4710-1 has sufficient stability margins and fast transient performance with a wide range of output capacitors, even with all ceramic output capacitors. 

The switching frequency for LTM4710-1 can be adjusted by an external resistor from RT to AGND, or the LTM4710-1 can be externally synchronized to a clock. See the Applications Information section. 

Current mode control provides cycle-by-cycle fast current limiting. Peak current limiting is provided in an overcurrent condition. The internal overvoltage and undervoltage comparators pull the open-drain PG output low if the output feedback voltage exits a –2% and +10% window around the regulation point. Furthermore, in an overvoltage condition, the internal top MOSFET is turned off, and the bottom MOSFET is turned on and held on until the overvoltage condition clears. 

The multiphase operation can be easily configurable with synchronization and phase mode controls. 

Pulling the RUN pin to GND forces the controller into its shutdown state, turning off both power MOSFETs and most of the internal control circuitry. 

The SSTT pin is used for power supply tracking, soft-start programming and, and monitoring die temperature. See the Applications Information section. 

Forced continuous mode (FCM) is the only operation mode recommended for low ripple and low noise consideration. The switching frequency of the four channels should always be synchronized regardless the output(s) are paralleled or independent. For multiphase paralleled output, phase-shift interleaving is recommended. For independent outputs, an aligned main-switch turn-on transition is recommended. See the Applications Information section and Typical Applications for more information. 

## **APPLICATIONS INFORMATION** 

The typical LTM4710-1 application circuit is shown in Figure 1. External component selection is primarily determined by the input voltage, the output voltage and the maximum load current. See Table 10 for specific external capacitor requirements for a particular application. 

## **VIN to VOUT Step-Down Ratios** 

There are restrictions in the minimum VOUT step-down ratio that can be achieved for a given input voltage due to the minimum on-time limits of the regulator. 

The minimum on-time limit imposes a minimum duty cycle of the converter, which can be calculated with Equation 1. 

**==> picture [240 x 18] intentionally omitted <==**

where tON(MIN) is the minimum on-time, 40ns typical for LTM4710-1. In the rare cases where the minimum duty cycle is surpassed, the output voltage will remain in regulation, but the switching frequency will decrease from its programmed value. 

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- LTM4710 1 

## **APPLICATIONS INFORMATION** 

## **Output Voltage Programming** 

The PWM controller has an internal 0.5V reference voltage. As shown in the Block Diagram, a 10k (0.5% tolerance) internal feedback resistor is included in channel 1 only. The 10k resistor connects FB1 to VOSNS1, which should be directly connected to the VOUT1 sense point. 10k external top feedback resistor is recommended for VOUT2,3,4 if operating independently. Adding a resistor RBOT from FB pin to the AGND pin programs the output voltage (Equation 2). 

**==> picture [239 x 31] intentionally omitted <==**

## **Input Decoupling Capacitors** 

Each channel of the LTM4710-1 module should be connected to a low AC-impedance DC source. For the regulator, at least 22µF input ceramic capacitor is recommended for RMS ripple current decoupling. Bulk input capacitors are needed when the input source impedance is compromised by long inductive leads, traces or not enough source capacitance. The bulk capacitor can be an electrolytic aluminum capacitor or polymer capacitor. 

Without considering the inductor current ripple, the RMS current of the input capacitor can be estimated with Equation 3. 

**==> picture [241 x 32] intentionally omitted <==**

where η is the estimated efficiency of the power module. 

## **Output Decoupling Capacitors** 

With an optimized high frequency, high bandwidth design, only a 100μF low ESR output ceramic capacitor is required for each channel to achieve low output voltage ripple and a very good transient response. Additional output filtering may be required by the system designer, if further reduction of output ripples or dynamic transient spikes is required. Table 10 shows a matrix of different output voltages and output capacitors to minimize the voltage droop and overshoot during a 2A (25%) load step transient. 

The multiphase operation will reduce effective output ripple as a function of the number of phases. Application Note 77 

discusses this noise reduction versus output ripple current cancellation, but the output capacitance will be more a function of stability and transient response. The LTpowerCAD[®] design tool is available to download on-line for output ripple, stability and transient response analysis and calculating the output ripple reduction as the number of phases implemented increases by N times. 

## **Mode of Operation** 

The MODE pin is either a clock input or a clock output. When configured as clock input, it synchronizes the switching frequency to an external clock (see Table 1). 

The LTM4710-1 should operate in forced continuous mode (FCM) for low-noise applications. 

**Table 1. LTM4710-1 Single Phase Configuration** 

|**RT PIN**<br>**CONNECTION**|**MODE**<br>**PIN CONNECTION**|**MODE OF**<br>**OPERATION**|**SWITCHING**<br>**FREQUENCY**|
|---|---|---|---|
|VIN|Clock Input|Forced<br>Continuous|External<br>Clock|
|Float/Resistor<br>to AGND|Clock Output|Forced<br>Continuous|RT<br>Programmed|



## **Setting the Operating Frequency** 

The frequency can be programmed by tying a resistor from RT to AGND pins (Equation 4). 

**==> picture [240 x 19] intentionally omitted <==**

where RT is in kΩ and fSW is the desired switching frequency in MHz. 

The frequency can be programmed to switch from 1MHz to 5MHz. Table 2 shows the necessary RT value for a desired switching frequency. 

**Table 2. SW Frequency vs RFREQ Value** 

|**Table 2. SW Frequency vs RFREQ **|**Value**|
|---|---|
|**fSW(MHz)**|**RT (kΩ)**|
|1|1130|
|1.5|536|
|2|340|
|2.2|301|
|3|196|
|4|140|
|5|105|



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## **APPLICATIONS INFORMATION** 

## **Frequency Synchronization and Clock Input** 

The LTM4710-1 switching frequency can be adjusted by synchronizing the internal PLL circuit to an external square wave clock applied at the MODE pin. The synchronization frequency range is 1.2MHz to 2.6MHz. The external clock amplitude must be greater than 1.2V and less than 0.4V. 

The internal PLL starts up at the 2MHz default frequency. After detecting an external clock on the first rising edge of the MODE pin, the internal PLL gradually adjusts its operating frequency to match the frequency and phase of the MODE signal. 

## **Multiphase Operation** 

For output loads that demand more than 8A of current, multiple LTM4710-1 channels can be paralleled to run out of phase to provide more output current without increasing input and output voltage ripples. Table 3 shows the configuration for multiphase operation. 

**Table 3. LTM4710-1 Multiphase Configuration** 

|**PHASE**|**RT**<br>**PIN**|**FB**<br>**PIN**|**MODE**<br>**PIN**|**SWITCHING**<br>**FREQUENCY**|
|---|---|---|---|---|
|Main|VIN|VOUT<br>Divider|Clock<br>Input|External Clock|
|Main|Resistor to<br>AGND|VOUT<br>Divider|Clock<br>Output|RTProgrammed|
|Subordinary|VINDivider|VIN|Clock Input|External Clock|



To parallel multiple LTM4710-1 channels to achieve the same switching frequency, perfect interleaved phase shift and accurate current sharing between different channels, one of the LTM4710-1 channels will become the main channel, and the rest of the LTM4710-1 channels need to be programmed as the subordinary channels. 

Connecting the RT pin of the main phase to a resistor to AGND programs the frequency and configures the MODE pin to become the clock output used to drive the MODE pin of the subordinary phase(s). 

Connecting the RT pin of the main phase to VIN configures the MODE pin to become an input capable of accepting an external clock. 

Connecting the VFB pin to VIN configures a phase as a subordinary phase. The MODE becomes a clock input, and the voltage control loop is disabled. The subordinary phase current control loop is still active, and the peak current is controlled via the shared COMP node. 

The phasing of a subordinary phase relative to the main phase is programmed with a resistor divider on the RT pin. The use of 1% resistors is recommended. See Table 4 for more information. Figure 17 shows an example. 

**Table 4.  Subordinary Phase Shift Related to MODE Input** 

|**PHASE ANGLE BETWEENSUBORDINARY**<br>**MODULE AND MODE INPUT (°)**|**RT RESISTOR TO VIN**<br>**(**Ω**)**|
|---|---|
|0|0|
|90|3M|
|120|1.4M|
|180|(RT= GND)|
|240|715k|
|270|332k|



Application Note 77 provides a detailed explanation of multiphase operation. The input RMS ripple current cancellation mathematical derivation are presented, and a graph is displayed representing the RMS ripple current reduction as a function of the number of interleaved phases (see Figure 1). 

**==> picture [246 x 232] intentionally omitted <==**

**----- Start of picture text -----**<br>
0.60<br>1-PHASE<br>0.55 2-PHASE<br>3-PHASE<br>4-PHASE<br>0.50 6-PHASE<br>0.45<br>0.40<br>0.35<br>0.30<br>0.25<br>0.20<br>0.15<br>0.10<br>0.05<br>0<br>0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 0.6 0.65 0.7 0.75 0.8 0.85 0.9<br>DUTY CYCLE (VOUT/VIN) 47101 F01<br>DC LOAD CURRENT<br>RMS INPUT RIPPLE CURRENT<br>**----- End of picture text -----**<br>


**Figure 1. Input RMS Current Ratios to DC Load Current as a Function of Duty Cycle** 

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## **APPLICATIONS INFORMATION** 

The LTM4710-1 device is an inherently current modecontrolled device, so that parallel modules will have very good current sharing. This will balance the thermals on all channels. Connect the RUN, COMP and PG pin of each paralleling channel together and connect FB to VIN for subordinary channels. Figure 17 shows an example of parallel operation and pin connection. 

## **Soft-Start/Output Voltage Tracking/ Temperature Monitoring** 

The SSTT pin function facilitates supply sequencing, limits VIN inrush current and reduces start-up output overshoot. An internal 10µA charge up a capacitor on the SSTT pin hence program the ramp rate of the output voltage. SSTT pin can also be externally driven by another voltage source. During the soft-start ramp, when the SSTT voltage is below 0.5V, the output voltage will proportionally track the SSTT pin voltage. When the SSTT voltage is above 0.5V, the SSTT pin will servo to a voltage proportional to the LTM4710-1 die junction temperature (see Figure 2). The SSTT capacitor is reset during shutdown, VIN UVLO and over thermal shutdown. 

**==> picture [191 x 143] intentionally omitted <==**

**----- Start of picture text -----**<br>
150<br>125<br>DIE TEMP 100 SSTT PIN VOLTAGE<br> (°C) 75 OPERATING RANGE<br>50 TEMP<br>MONITOR<br>25 ~4mV/°C<br>0.6<br>0.5<br>0.4<br>FB<br>0.3<br> (V)<br>0.2<br>SOFT-START<br>0.1 AND TRACKING<br>0<br>0 0.1 0.2 0.3 0.4 0.5 0.6 1.2 1.3 1.4 1.5 1.6 1.7 SSTT (V)<br>47101 F02<br>**----- End of picture text -----**<br>


**Figure 2. Soft-Start and Temperature Monitor Operation** 

The total soft-start time can be calculated with Equation 5. 

**==> picture [239 x 29] intentionally omitted <==**

where CSS is the capacitance on the SSTT pin. FCM is disabled during the soft-start process to prevent the current from reversing. 

A default 10nF soft-start cap is connected to SSTT1 inside the module, resulting in a 0.5ms default start-up time on channel 1. The presence of this cap is to simplify customers’ design in most cases. 

## **Output Power Good** 

When the LTM4710-1’s output voltage is within the –2% and +10%  window of the nominal regulation voltage, the output is considered good, and the open-drain PG pin goes high impedance and is typically pulled high with an external resistor. Otherwise, the internal pull-down device will pull the PG pin low. To prevent glitching both the upper and lower thresholds, include 1% of hysteresis as well as a built-in time delay, typically 100μs. The PG pin is also actively pulled low during fault conditions: RUN pin is low, VIN is too low or in thermal shutdown. 

For multiphase applications, the PG pin is used for communication between the main and sub-ordinary phases. Connect the PG pins together and pull-up to VIN or VOUT with an external resistor. PG pins MUST be pulled higher than 490mV. 

## **Stability Compensation** 

The LTM4710-1 has already been internally optimized and compensated for all output voltages and capacitor combinations including all ceramic capacitor applications when COMPb is tied to COMPa. 

Table 10 is provided for most application requirements using the optimized internal compensation. For applications that need to achieve high bandwidth control loop compensation with enough phase margin, a 68pF feed-forward capacitor is recommended from VOUT to VFB pin. For specific optimized requirement, disconnect COMPb from COMPa and apply a Type II C-R-C compensation network from COMPa to AGND to achieve external compensation. The LTpowerCAD design tool can be downloaded online to perform specific control loop optimization and analyze the control stability and load transient performance. 

## **RUN Enable** 

The LTM4710-1 has a precision threshold RUN pin to enable or disable the switching. When forced low, the RUN pin puts the LTM4710-1 into a low current shutdown 

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## **APPLICATIONS INFORMATION** 

mode. The rising threshold of the RUN comparator is 400mV, with 75mV of hysteresis. It can be tied to VIN if the shutdown feature is not used. Adding a resistor divider from VIN to RUN programs the LTM4710-1 to regulate the output only when VIN is above a desired voltage. Typically, this threshold, VIN(EN), is used in situations where the input supply is current limited or has a relatively high source resistance. A switching regulator draws constant power from the source, so the source current increases as the source voltage drops. This looks like a negative resistance load to the source and can cause the source to current limit or latch low under low source voltage conditions. The VIN(EN) threshold prevents the regulator from operating at source voltages where problems may occur. This threshold can be adjusted by setting the values R1 and R2 such that they satisfy Equation 6. 

**==> picture [239 x 30] intentionally omitted <==**

where the LTM4710-1 will remain off until VIN is above VIN(EN). Due to the comparator’s hysteresis, switching will not stop until the input falls slightly below VIN(EN). 

Alternatively, a resistor divider from an output of another channel to the RUN pin of the LTM4710-1 provides eventbased power-up sequencing, enabling the LTM4710-1 when the output of the other regulator reaches a predetermined level. 

## **Thermal Considerations and Output Current Derating** 

The thermal resistances reported in the Pin Configuration section of this data sheet are consistent with those parameters defined by JESD51-12 and are intended for use with finite element analysis (FEA) software modeling tools that leverage the outcome of thermal modeling, simulation, and correlation to hardware evaluation performed on a µModule package mounted to a hardware test board. The motivation for providing these thermal coefficients in found in JESD51-12 (“Guidelines for Reporting and Using Electronic Package Thermal Information”). 

Many designers may use laboratory equipment and a test vehicle, such as the demo board, to anticipate the µModule regulator’s thermal performance in their application at various electrical and environmental operating 

conditions to compliment any FEA activities. Without FEA software, the thermal resistances reported in the Pin Configuration section are, in-and-of themselves, not relevant to providing guidance on thermal performance; instead, the derating curves provided in the data sheet can be used in a manner that yields insight and guidance pertaining to one’s application-usage and can be adapted to correlate thermal performance to one’s own application. 

The Pin Configuration section typically gives three thermal coefficients explicitly defined in JESD 51-12; these coefficients are quoted or paraphrased below. 

1. θ JA, the thermal resistance from junction to ambient, is the natural convection junction-to-ambient air thermal resistance measured in a one cubic foot sealed enclosure. This environment is sometimes referred to as “still air”, although natural convection causes the air to move. This value is determined with the part mounted to the demo board DC3164A-B. 

2. θ JCbottom, the thermal resistance from junction to bottom of the product case, is determined with all the component power dissipation flowing through the bottom of the package. In the typical module regulator, the bulk of the heat flows out the bottom of the package, but there is always heat flow out into the ambient environment. As a result, this thermal resistance value maybe useful for comparing packages, but the test conditions don’t generally match the user’s application. 

3. θ JCtop, the thermal resistance from the junction to the top of the product case, is determined with nearly all of the component power dissipation flowing through the top of the package. As the electrical connections of the typical µModule are on the bottom of the package, it is rare for an application to operate such that most of the heat flows from the junction to the top of the part. As in the case of θ JCbottom, this value may be useful for comparing packages, but the test conditions don’t generally match the user’s application. 

A graphical representation of the aforementioned thermal resistances is shown in Figure 3; blue resistances are contained within the μModule regulator, whereas green resistances are external to the µModule. 

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## - LTM4710 1 

## **APPLICATIONS INFORMATION** 

**==> picture [328 x 119] intentionally omitted <==**

**----- Start of picture text -----**<br>
µModule DEVICE θJA JUNCTION-TO-AMBIENT RESISTANCE<br>θJCtop JUNCTION-TO-CASE CASE (TOP)-TO-AMBIENT<br>(TOP) RESISTANCE RESISTANCE<br>JUNCTION AMBIENT<br>θJCbot JUNCTION-TO-CASE CASE (BOTTOM)-TO-BOARD BOARD-TO-AMBIENT<br>(BOTTOM) RESISTANCE RESISTANCE RESISTANCE<br>47101 F03<br>**----- End of picture text -----**<br>


**Figure 3. Graphical Representation of JESD51-12 Thermal Coefficients** 

Within the LTM4710-1 module, be aware that there are multiple power devices and components dissipating power, with the consequence that the thermal resistances relative to different junctions of components or die are not exactly linear to total package power loss. To reconcile this complication without sacrificing modeling simplicity—but also, not ignoring practical realities—an approach has been taken using FEA software modeling along with laboratory testing in a controlled-environment chamber to reasonably define and correlate the thermal resistance values supplied in this data sheet: (1) Initially, FEA software is used to accurately build the mechanical geometry of the µModule and the specified PCB with all of the correct material coefficients along with accurate power loss source definitions; (2) this model simulates a software-defined JEDEC environment consistent with JSED51-12 to predict power loss heat flow and temperature readings at different interfaces that enable the calculation of the JEDEC-defined thermal resistance values; (3) the model and FEA software is used to evaluate the LTM4710-1 with heat sink and airflow; (4) having solved for and analyzed these thermal resistance values and simulated various operating conditions in the software model, a thorough laboratory evaluation replicates the simulated conditions with thermocouples within a controlled-environment chamber while operating the device at the same power loss as that which was simulated. An outcome of this process and due diligence yields a set of derating curves, as shown in this datasheet. 

After these laboratory tests have been performed and correlated to the LTM4710-1 model, then the θ JB and θ BA are 

summed together to provide a value that should closely equal the θ JA value because approximately 100% of the power loss flows from the junction through the board into ambient with no airflow or top mounted heat sink. 

Figure 5 and Figure 6 (3.3V and 5V) power loss curves can be used in coordination with Figure 7 through Figure 15 load current derating curves for calculating an approximate θ JA thermal resistance for the LTM4710-1 with various heat sinking and airflow conditions. The power loss curves are taken at room temperature and are increased with multiplicative factors according to the junction temperature. This approximate factor is 1.2 for 120°C at junction temperature. The maximum load current is achievable while increasing ambient temperature as long as the junction temperature is less than 120°C, which is 5°C guard band from The maximum junction temperature of 125°C. When the ambient temperature reaches a point where the junction temperature is 120°C, then the load current is lowered to maintain the junction at 120°C while increasing the ambient temperature up to 120°C. The derating curves are plotted with the output current starting at 36A and the ambient temperature at 30°C. The output voltages are 0.5V, 0.8V, 1V, 1.2V, and 1.5V. Thermal models are derived from several temperature measurements in a controlled temperature chamber along with thermal modeling analysis. The junction temperatures are monitored while ambient temperature is increased with and without airflow. The power loss increase with ambient temperature change is factored into the derating curves. The junctions are maintained at 120°C maximum while lowering output current or power 

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## **APPLICATIONS INFORMATION** 

with increasing the ambient temperature. The decreased output current will decrease the internal module loss as ambient temperature is increased. The monitored junction temperature of 120°C minus the ambient operating temperature specifies how much module temperature rise can be allowed. As an example, in Figure 13, the load current is derated to be 19.2A at 86.4°C with no air or heat sink, and the total power loss for 3.3VIN to 1.2VOUT at 19.2A is 2.6W (Figure 5), then multiply by the 1.2 coefficient for 120°C junction temperature, the total power loss for 4 channels is 3.2W, if 86.4°C ambient temperature is subtracted from 120°C junction temperature, the difference of the 33.6°C divided by 3.2W equals 10.5°C/W. Table 5 specifies an 11°C/W value which is very close. Table 5 to Table 9 provide equivalent thermal resistances for 0.5V, 0.8V, 1V, 1.2V and 1.5V outputs with and without airflow. The derived thermal resistances in Table 5 to Table 9 for the various conditions can be multiplied by the calculated power loss as a function of ambient temperature to derive temperature rise above ambient, thus maximum junction temperature. Room temperature power loss 

**==> picture [155 x 161] intentionally omitted <==**

**----- Start of picture text -----**<br>
7<br>0.5VOUT, 1.0MHz<br>6 0.8V1.0V OUT OUT, 1.2MHz, 1.4MHz TT<br>1.2VOUT, 1.6MHz<br>5 1.5V OUT , 1.6MHz any<br>4<br>3 SERREEW<br>2 | ee 74|<br>1<br>ose<br>0<br>Pry tt dtd| | |<br>0 4 8 12 16 20 24 28 32<br>LOAD CURRENT (A)<br>47101 F05<br>POWER LOSS (W)<br>**----- End of picture text -----**<br>


**Figure 5. Power Loss, 4-Channel Paralleled VIN = 3.3V** 

can be derived from the efficiency curves in the Typical Performance Characteristics section and adjusted with the above ambient temperature multiplicative factors. The printed circuit board is a 1.6mm thick six-layer board with two-ounce copper on all six layers. The PCB dimensions are 4.25-inch × 4.48-inch. 

**==> picture [251 x 218] intentionally omitted <==**

**----- Start of picture text -----**<br>
47101 F04<br>Figure 4. Thermal Image, LTM4710-1 Running from 3.3V Input<br>to 0.5V, Paralleled 32A Output with No Airflow, No Heat Sink<br>7<br>0.5VOUT, 1.0MHz<br>6 0.8V1.0V OUT OUT, 1.2MHz, 1.4MHz TE<br>1.2VOUT, 1.6MHz<br>5 1.5V OUT , 1.6MHz ae<br>1.8VOUT, 1.6MHz<br>4<br>3<br>2 |mpeee<br>1<br>|_|<br>0 i PEE  eyae<br>0 4 8 12 16 20 24 28 32<br>LOAD CURRENT (A)<br>47101 F06<br>POWER LOSS (W)<br>**----- End of picture text -----**<br>


**Figure 6. Power Loss, 4-Channel Paralleled VIN = 5.5V** 

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## **APPLICATIONS INFORMATION** 

**==> picture [515 x 632] intentionally omitted <==**

**----- Start of picture text -----**<br>
35 35 35<br>30 30 30<br>25 25 25<br>20 20 20<br>15 15 15<br>10 10 10<br>0LFM 0LFM 0LFM<br>5 5 5<br>200LFM 200LFM 200LFM<br>400LFM 400LFM 400LFM<br>0 0 0<br>25 35 45 55 65 75 85 95 105 115 125 25 35 45 55 65 75 85 95 105 115 125 25 35 45 55 65 75 85 95 105 115 125<br>TEMPERATURE (°C) TEMPERATURE (°C) TEMPERATURE (°C)<br>47101 F07 47101 F08 47101 F09<br>Figure 7. Derating, 4-Channel  Figure 8. Derating, 4-Channel  Figure 9. Derating, 4-Channel<br>Paralleled VIN = 3.3V, VOUT = 0.5V  Paralleled VIN = 5V, VOUT = 0.5V  Paralleled VIN = 3.3V, VOUT = 0.8V<br>DC3164A-B Demo Board DC3164A-B Demo Board DC3164A-B Demo Board<br>35 35 35<br>30 30 30<br>25 25 25<br>20 20 20<br>15 15 15<br>10 10 10<br>5 0LFM 5 0LFM 5 0LFM<br>200LFM 200LFM 200LFM<br>400LFM 400LFM 400LFM<br>0 0 0<br>25 35 45 55 65 75 85 95 105 115 125 25 35 45 55 65 75 85 95 105 115 125 25 35 45 55 65 75 85 95 105 115 125<br>TEMPERATURE (°C) TEMPERATURE (°C) TEMPERATURE (°C)<br>47101 F10 47101 F0x 47101 F12<br>Figure 10. Derating, 4-Channel  Figure 11. Derating, 4-Channel  Figure 12. Derating, 4-Channel<br>Paralleled VIN = 5V, VOUT = 0.8V  Paralleled VIN = 3.3V, VOUT = 1V  Paralleled VIN = 5V, VOUT = 1V<br>DC3164A-B Demo Board DC3164A-B Demo Board DC3164A-B Demo Board<br>35 35 35<br>30 30 30<br>25 25 25<br>20 20 20<br>15 15 15<br>10 10 10<br>0LFM 0LFM 0LFM<br>5 5 5<br>200LFM 200LFM 200LFM<br>400LFM 400LFM 400LFM<br>0 0 0<br>25 35 45 55 65 75 85 95 105 115 125 25 35 45 55 65 75 85 95 105 115 125 25 35 45 55 65 75 85 95 105 115 125<br>TEMPERATURE (°C) TEMPERATURE (°C) TEMPERATURE (°C)<br>47101 F13 47101 F14 47101 F15<br>Figure 13. Derating, 4-Channel  Figure 14. Derating, 4-Channel  Figure 15. Derating, 4-Channel<br>Paralleled VIN = 3.3V, VOUT = 1.2V  Paralleled VIN = 5V, VOUT = 1.2V  Paralleled VIN = 5V, VOUT = 1.5V<br>DC3164A-B Demo Board DC3164A-B Demo Board DC3164A-B Demo Board<br>Rev. 0<br> (A)  (A)  (A)<br>IOUT IOUT IOUT<br> (A)  (A)  (A)<br>IOUT IOUT IOUT<br> (A)  (A)  (A)<br>IOUT IOUT IOUT<br>**----- End of picture text -----**<br>


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## **APPLICATIONS INFORMATION** 

## **Table 5. 0.5V Output** 

|**Table 5. 0.5V Output**||||||
|---|---|---|---|---|---|
|**DERATING CURVE**|**VIN (V)**|**POWER LOSS CURVE**|**AIRFLOW (LFM)**|**HEAT SINK**|θ**JA(°C/W)**|
|Figure 7, Figure 8|3.3, 5|Figure 5, Figure 6|0|None|11|
|Figure 7, Figure 8|3.3, 5|Figure 5, Figure 6|200|None|9|
|Figure 7, Figure 8|3.3, 5|Figure 5, Figure 6|400|None|10|



## **Table 6. 0.8V Output** 

|**Table 6. 0.8V Output**||||||
|---|---|---|---|---|---|
|**DERATING CURVE**|**VIN (V)**|**POWER LOSS CURVE**|**AIRFLOW (LFM)**|**HEAT SINK**|θ**JA(°C/W)**|
|Figure 9, Figure 10|3.3, 5|Figure 5, Figure 6|0|None|14|
|Figure 9, Figure 10|3.3, 5|Figure 5, Figure 6|200|None|10|
|Figure 9, Figure 10|3.3, 5|Figure 5, Figure 6|400|None|11|



## **Table 7. 1.0V Output** 

|**Table 7. 1.0V Output**||||||
|---|---|---|---|---|---|
|**DERATING CURVE**|**VIN (V)**|**POWER LOSS CURVE**|**AIRFLOW (LFM)**|**HEAT SINK**|θ**JA(°C/W)**|
|Figure 11, Figure 12|3.3, 5|Figure 5, Figure 6|0|None|12|
|Figure 11, Figure 12|3.3, 5|Figure 5, Figure 6|200|None|9|
|Figure 11, Figure 12|3.3, 5|Figure 5, Figure 6|400|None|9|
|**Table 8. 1.2V Output**||||||
|**DERATING CURVE**|**VIN (V)**|**POWER LOSS CURVE**|**AIRFLOW (LFM)**|**HEAT SINK**|θ**JA(°C/W)**|
|Figure 13, Figure 14|3.3, 5|Figure 5, Figure 6|0|None|12|
|Figure 13, Figure 14|3.3, 5|Figure 5, Figure 6|200|None|9|
|Figure 13, Figure 14|3.3, 5|Figure 5, Figure 6|400|None|9|



## **Table 9. 1.5V Output** 

|**Table 9. 1.5V Output**||||||
|---|---|---|---|---|---|
|**DERATING CURVE**|**VIN (V)**|**POWER LOSS CURVE**|**AIRFLOW (LFM)**|**HEAT SINK**|θ**JA(°C/W)**|
|Figure 15|5|Figure 5, Figure 6|0|None|12|
|Figure 15|5|Figure 5, Figure 6|200|None|11|
|Figure 15|5|Figure 5, Figure 6|400|None|10|



## **Table 10. Output Voltage Response vs Component Matrix, 6A to 8A Load Step Typical Measured Values, Freq = 1.5MHz** 

|**VIN**<br>**(V)**|**VOUT**<br>**(V)**|**CIN**<br>**CERAMIC**<br>**(μF) **|**COUT1,2,3,4**<br>**CERAMIC**<br>**(μF)**|**CFF**<br>**(pF)**|**PEAK-PEAK**<br>**DERIVATION**<br>**(mV)**|**LOAD**<br>**STEP**<br>**(A)**|**LOAD STEP**<br>**SLEW RATE**<br>**(A/μs)**|**RFB**<br>**(kΩ)**|**COMPENSATION**|
|---|---|---|---|---|---|---|---|---|---|
|2.5|0.5|22 ×2 + 47|22 + 47 + 100|68|42.2|2|2|Open|Module Internal Compensation|
|3.3|0.5|22 ×2 + 47|22 + 47 + 100|68|44.9|2|2|Open|Module Internal Compensation|
|5|0.5|22 ×2 + 47|22 + 47 + 100|68|48.9|2|2|Open|Module Internal Compensation|
|5.5|0.5|22 ×2 + 47|22 + 47 + 100|68|49.5|2|2|Open|Module Internal Compensation|
|2.5|0.8|22 ×2 + 47|22 + 47 + 100|68|54.9|2|2|16.5|Module Internal Compensation|
|3.3|0.8|22 ×2 + 47|22 + 47 + 100|68|56.9|2|2|16.5|Module Internal Compensation|
|5|0.8|22 ×2 + 47|22 + 47 + 100|68|60.3|2|2|16.5|Module Internal Compensation|
|5.5|0.8|22 ×2 + 47|22 + 47 + 100|68|60.3|2|2|16.5|Module Internal Compensation|
|2.5|1|22 ×2 + 47|22 + 47 + 100|68|58.2|2|2|10|Module Internal Compensation|
|3.3|1|22 ×2 + 47|22 + 47 + 100|68|59.6|2|2|10|Module Internal Compensation|



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## **APPLICATIONS INFORMATION** 

**Table 10. Output Voltage Response vs Component Matrix, 6A to 8A Load Step Typical Measured Values, Freq = 1.5MHz** 

|**VIN**<br>**(V)**|**VOUT**<br>**(V)**|**CIN**<br>**CERAMIC**<br>**(μF) **|**COUT1,2,3,4**<br>**CERAMIC**<br>**(μF)**|**CFF**<br>**(pF)**|**PEAK-PEAK**<br>**DERIVATION**<br>**(mV)**|**LOAD**<br>**STEP**<br>**(A)**|**LOAD STEP**<br>**SLEW RATE**<br>**(A/μs)**|**RFB**<br>**(kΩ)**|**COMPENSATION**|
|---|---|---|---|---|---|---|---|---|---|
|5|1|22 ×2 + 47|22 + 47 + 100|68|62.9|2|2|10|Module Internal Compensation|
|5.5|1|22 ×2 + 47|22 + 47 + 100|68|61.6|2|2|10|Module Internal Compensation|
|2.5|1.2|22 ×2 + 47|22 + 47 + 100|68|71.6|2|2|7.15|Module Internal Compensation|
|3.3|1.2|22 ×2 + 47|22 + 47 + 100|68|73|2|2|7.15|Module Internal Compensation|
|5|1.2|22 ×2 + 47|22 + 47 + 100|68|79|2|2|7.15|Module Internal Compensation|
|5.5|1.2|22 ×2 + 47|22 + 47 + 100|68|82|2|2|7.15|Module Internal Compensation|
|2.5|1.5|22 ×2 + 47|22 + 47 + 100|68|78|2|2|4.99|Module Internal Compensation|
|3.3|1.5|22 ×2 + 47|22 + 47 + 100|68|80|2|2|4.99|Module Internal Compensation|
|5|1.5|22 ×2 + 47|22 + 47 + 100|68|90|2|2|4.99|Module Internal Compensation|
|5.5|1.5|22 ×2 + 47|22 + 47 + 100|68|90|2|2|4.99|Module Internal Compensation|



## **Safety Considerations** 

The LTM4710-1 modules do not provide galvanic isolation from VIN to VOUT. There is no internal fuse. If required, a slow blow fuse with a rating twice the maximum input current must be provided to protect each unit from catastrophic failure. The device does support thermal shutdown and overcurrent protection. 

## **Layout Checklist/Example** 

The high integration of LTM4710-1 makes the PCB board layout very simple and easy. However, to optimize its electrical and thermal performance, some layout considerations are still necessary. 

- Use large PCB copper areas for high current paths, including VIN, GND and VOUT. It helps to minimize the PCB conduction loss and thermal stress. 

- Place high-frequency ceramic input and output capacitors next to the VIN, GND and VOUT pins to minimize high-frequency noise. 

- Place a dedicated power ground layer underneath the unit. 

- To minimize the via conduction loss and reduce module thermal stress, use multiple vias for interconnection between top layer and other power layers. 

- Do not put via directly on the pad, unless they are capped or plated over. 

- Use a separated AGND ground copper area for components connected to signal pins. See AGND in Figure 17. 

- For parallel modules, tie the VOUT, FB, and COMP pins together. Use an internal layer to closely connect these pins together. The SSTT pin should NOT be tied together for temperature monitoring of each silicon independently. 

- Bring out test points on the signal pins for monitoring. 

- Solder mask-defined pin pads are recommended. 

Figure 16 gives a good example of the recommended layout. 

**==> picture [253 x 152] intentionally omitted <==**

**----- Start of picture text -----**<br>
GND VOUT2 VOUT3 GND<br>VOUT1 VOUT4<br>GND GND<br>VIN VIN<br>GND<br>47101 F16<br>**----- End of picture text -----**<br>


**Figure 16. Recommended PCB Layout** 

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- LTM4710 1 

## **TYPICAL APPLICATIONS** 

**==> picture [375 x 483] intentionally omitted <==**

**----- Start of picture text -----**<br>
PGOOD PG1,2,3,4 FB1<br>2.5V TO5.5VVIN 22μF 100kΩ VIN1,2,3,4 VOUT1,2,3,4VOSNS1 100μF 68pF V0.5V, 32AOUT<br>× 4 FB2,3,4 × 4<br>RUN1,2,3,4<br>MODE1 LTM4710-1 RT1<br>(90° PHASE SHIFT) 3MΩ<br>MODE2,3,4 RT 2 VIN 536kΩ<br>(180° PHASE SHIFT)<br>COMP1a,2a,3a,4a RT3 (1.5MHz)<br>OPT OPT 0Ω (270° PHASE SHIFT) 332kΩ<br>COMP1b RT4 VIN<br>OPT<br>AGND1,2,3,4 GND<br>47101 F17<br>PINS NOT SHOWN IN THIS CIRCUIT: SSTT, SW<br>Figure 17. Paralleled Single Output, 32A DC/DC μModule Regulator<br>4V TO 5.5VVIN VIN1,2,3,4 VOSNS1<br>C22μF× 4IN RT2,3,4 VOUT1 68pF COUT1 V0.5V, 8AOUT1<br>RUN1,2,3,4 FB1 100μF<br>× 2<br>RT1 VOUT2 VOUT2<br>1.13M Ω R29 COUT2 1V, 8A<br>(1MHz) MODE2,3,4 FB2 68pF 10k Ω 100μF× 2<br>MODE1 R30<br>10k Ω<br>COMP1aCOMP1b LTM4710-1 VOUT3 68pF R3110k Ω C100μFOUT3 V2V, 8AOUT3<br>COMP2a FB3<br>COMP2b R32<br>3.32k Ω<br>COMP3aCOMP3b VOUT4 68pF R3310k Ω C100μFOUT4 V3.3V, 8AOUT4<br>COMP4a FB4<br>R34<br>COMP4b<br>1.78k Ω<br>PINS NOT SHOWN IN THIS CIRCUIT: SSTT1,2,3,4 AGND1,2,3,4 GND 47101 F18<br>PG, SW CSS<br>0.1μF<br>× 4<br>**----- End of picture text -----**<br>


## **Figure 18. 0.5V, 8A; 1V, 8A; 2V, 8A; and 3.3V, 8A Outputs from 4V to 5.5V Input, Switching Frequency Synchronized** 

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## **TYPICAL APPLICATION** 

**==> picture [348 x 299] intentionally omitted <==**

**----- Start of picture text -----**<br>
PGOOD1,2,3 PG1,2,3 VOSNS1 VOUT1<br>1V, 24A<br>2.5V TOVIN 100kΩ VIN1,2,3 VOUT1,2,3 100μF× 4<br>5.5V 22μF× 4 FB2,3 68pF<br>RUN1,2,3 FB1<br>MODE1 10kΩ<br>MODE2,3<br>COMP1a,2a,3a RT1<br>OPT OPT 0Ω (120° PHASE SHIFT) 1.4MΩ VIN<br>COMP1b RT2 536kΩ<br>OPT (240° PHASE SHIFT) 715kΩ<br>RT3 (1.5MHz)<br>LTM4710-1<br>PGOOD4 PG4 FB4<br>2.5V TO5.5VVIN 22μF 100k VIN4 VOUT4 V0.5V, 8AOUT2<br>× 4 100μF<br>RUN4 × 4<br>MODE1<br>MODE4 RT4 VIN<br>COMP4a<br>OPT OPT 0Ω<br>COMP4b<br>OPT<br>AGND1,2,3,4 GND<br>47101 F19<br>PINS NOT SHOWN IN THIS CIRCUIT: SSTT, SW<br>**----- End of picture text -----**<br>


**Figure 19. 1V, 24A; 0.5V, 8A; Outputs from 2.5V to 5.5V Input** 

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## **PACKAGE PINOUT DESCRIPTION** 

## **PACKAGE ROW AND COLUMN LABELING MAY VARY AMONG µModule PRODUCTS. REVIEW EACH PACKAGE LAYOUT CAREFULLY.** 

|**PIN**|**PIN NAME**|**PIN**|**PIN NAME**|**PIN**|**PIN NAME**|**PIN**|**PIN NAME**|**PIN**|**PIN NAME**|**PIN**|**PIN NAME**|
|---|---|---|---|---|---|---|---|---|---|---|---|
|A9|GND|B9|NC|C9|NC|D9|VIN1|E9|GND|F9|VOUT1|
|A8|NC|B8|NC|C8|NC|D8|AGND1|E8|GND|F8|VOUT1|
|A7|NC|B7|NC|C7|NC|D7|VOSNS1|E7|GND|F7|VOUT1|
|A6|FB1|B6|COMP1b|C6|COMP1a|D6|RT1|E6|GND|F6|FB2|
|A5|RUN1|B5|SSTT1|C5|PG1|D5|MODE1|E5|GND|F5|RUN2|
|A4|VIN1|B4|VIN1|C4|VIN1|D4|VIN1|E4|GND|F4|VIN2|
|A3|GND|B3|GND|C3|GND|D3|GND|E3|GND|F3|GND|
|A2|GND|B2|GND|C2|GND|D2|GND|E2|GND|F2|GND|
|A1|GND|B1|GND|C1|GND|D1|GND|E1|GND|F1|GND|
|G9|VOUT1|H9|GND|J9|VOUT2|K9|VOUT2|L9|GND|M9|VOUT3|
|G8|VOUT1|H8|GND|J8|VOUT2|K8|VOUT2|L8|GND|M8|VOUT3|
|G7|VOUT1|H7|AGND2|J7|VOUT2|K7|VOUT2|L7|AGND3|M7|VOUT3|
|G6|COMP2b|H6|COMP2a|J6|RT2|K6|FB3|L6|COMP3b|M6|COMP3a|
|G5|SSTT2|H5|PG2|J5|MODE2|K5|RUN3|L5|SSTT3|M5|PG3|
|G4|VIN2|H4|VIN2|J4|VIN2|K4|VIN3|L4|VIN3|M4|VIN3|
|G3|GND|H3|GND|J3|GND|K3|GND|L3|GND|M3|GND|
|G2|SW1|H2|GND|J2|GND|K2|SW2|L2|GND|M2|GND|
|G1|GND|H1|GND|J1|GND|K1|GND|L1|GND|M1|GND|
|N9|VOUT3|P9|GND|R9|VOUT4|T9|VOUT4|U9|GND|V9|GND|
|N8|VOUT3|P8|GND|R8|VOUT4|T8|VOUT4|U8|GND|V8|GND|
|N7|VOUT3|P7|GND|R7|VOUT4|T7|VOUT4|U7|AGND4|V7|GND|
|N6|RT3|P6|GND|R6|FB4|T6|COMP4b|U6|COMP4a|V6|RT4|
|N5|MODE3|P5|GND|R5|RUN4|T5|SSTT4|U5|PG4|V5|MODE4|
|N4|VIN3|P4|GND|R4|VIN4|T4|VIN4|U4|VIN4|V4|VIN4|
|N3|GND|P3|GND|R3|GND|T3|GND|U3|GND|V3|GND|
|N2|SW3|P2|GND|R2|GND|T2|SW4|U2|GND|V2|GND|
|N1|GND|P1|GND|R1|GND|T1|GND|U1|GND|V1|GND|



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## **PACKAGE DESCRIPTION** 

**==> picture [497 x 540] intentionally omitted <==**

**----- Start of picture text -----**<br>
7<br>SEE NOTES PIN 1<br>A B C D E F G H J K L M N P R T U V<br>1<br>2<br>DETAIL A<br>3 b<br>4<br>5 G<br>6<br>LTMXXXX µModule<br>7<br>8 PACKAGE BOTTOM VIEW<br>e<br>9 PACKAGE IN TRAY LOADING ORIENTATION<br>PACKAGE ROW AND COLUMN LABELING MAY VARY  AMONG µModule PRODUCTS. REVIEW EACH PACKAGE LAYOUT CAREFULLY<br>e !<br>3 F DETAILS OF PIN 1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE PIN 1 IDENTIFIER MAY BE EITHER A MOLD OR  MARKED FEATURE<br>b<br>SEE NOTES NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994 2. ALL DIMENSIONS ARE IN MILLIMETERS 3        LAND DESIGNATION PER JEP95 4 5. PRIMARY DATUM -Z- IS SEATING PLANE 6 PIN 1 BEVEL<br>COMPONENT TRAY PIN 1<br>A2<br>DETAIL B<br>A<br>PACKAGE SIDE VIEW<br>NOTES PAD HT PAD DIMENSION SUBSTRATE THK MOLD CAP HT INDUCTOR HT<br>H1 MAX 3.87 0.08 1.04 0.38 2.75 0.15 0.10 0.20 0.25 0.10<br>SUBSTRATE Y<br>X<br>Z Z<br>LGA Package 1 A Zccc  MOLD CAP H2 Mddd Meee DIMENSIONS NOM 3.54  0.95 0.35 12.00 6.00 0.65 11.05 5.20 0.25 REF 0.70 REF 2.525<br>MIN 3.21   0.86 0.32 2.30<br>DETAIL B DETAIL A<br>(Reference DWG# 05-08-7101 Rev A)<br>162-Lead (6mm × 12mm × 3.54mm)<br>H3<br>INDUCTOR Øb (162 PLACES) A A1 A2 b D E e F G H1 H2 H3 aaa bbb ccc ddd eee<br>SYMBOL<br>aaa Z<br>2×<br>X D<br>0.000<br>Y 0.35 TYP 5.525 4.875 4.225 3.575 2.925 2.275 1.625 0.975 0.325 0.325 0.975 1.625 2.275 2.925 3.575 4.225 4.875 5.525<br>2.90 TYP<br>1.20 TYP 1.20 TYP<br>E<br>5.30 MAX 0.35 TYP TOP VIEW<br>2.00 TYP 2.00 TYP 2.00 TYP<br>PACKAGE TOP VIEW<br>SUGGESTED PCB LAYOUT<br>Zaaa  PIN 1 4 0.35 TYP<br>2× CORNER 0.35 REF Ø 162x<br>8.70 MAX<br>BGA 162 0921 REV A<br>Z<br>Z<br>Z// bbb<br>2.600<br>1.950<br>1.300<br>0.650<br>0.000<br>0.650<br>1.300<br>1.950<br>2.600<br>**----- End of picture text -----**<br>


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## **REVISION HISTORY** 

|**REV**|**DATE**|**DESCRIPTION**|**PAGE NUMBER**|
|---|---|---|---|
|0|07/23|Initial Release.|—|



Rev. 0 

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Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implicatiFor more informati **on** or otherwise under any patent or patent rights of Analog Devices.www.analog.com 

## - LTM4710 1 

## **PACKAGE PHOTOS** 

**Part marking is either ink mark or laser mark** 

## **DESIGN RESOURCES** 

|**DESIGN RESOURCES**|||
|---|---|---|
|**SUBJECT**|**DESCRIPTION**||
|µModule Design and Manufacturing Resources|Design:<br>• Selector Guides<br>• Demo Boards and Gerber Files<br>• Free Simulation Tools|Manufacturing:<br>• Quick Start Guide<br>• PCB Design, Assembly and Manufacturing Guidelines<br>• Package and Board Level Reliability|
|µModule Regulator Products Search|1.  Sort table of products by parameters and download the result as a spread sheet.<br>2. Search using the Quick Power Search parametric table.<br>Quick Power Search<br>INPUT<br>|<br>Vin(Min)<br>Vv<br>Vin(Max)<br>Vv<br>OUTPUT |<br>Vout<br>v<br>lout<br>A<br>FEATURES |<br>LowEMI<br>Ultrathin<br>Internal Heat Sink<br>Multiple Outputs||
|Digital Power System Management|Analog Devices’ family of digital power supply management ICs are highly integrated solutions that<br>offer essential functions, including power supply monitoring, supervision, margining and sequencing,<br>and feature EEPROM for storing user configurations and fault logging.||



## **RELATED PARTS** 

|**RELATED PARTS**|**RELATED PARTS**||
|---|---|---|
|**PART NUMBER**|**DESCRIPTION**|**COMMENTS**|
|LTM4691|Low VIN, Ultrathin, Dual 2A μModule Regulator|2.25V ≤ VIN≤ 3.6V, 0.5V ≤ VOUT≤ 2.5V, 3mm × 4mm × 1.18mm LGA,<br>3mm × 4mm × 1.48mm BGA|
|LTM4693|Low VIN, Ultrathin, 2A Buck-Boost μModule Regulator|2.6V ≤ VIN≤ 5.5V, 1.8V ≤ VOUT≤ 5.5V, 3.5mm × 4mm × 1.25mm LGA|
|LTM4663|Ultrathin, 1.5A μModule TEC Controller|2.7V ≤ VIN≤ 5.5V, 3.5mm × 4mm × 1.3mm LGA|
|LTM4658|Low VIN, 10A μModule Regulator|2.25V ≤ VIN≤ 5.5V, 0.5V ≤ VOUT≤ VIN, 4mm × 4mm × 4.32mm LGA|
|LTM4670|Low VIN, Quad 10A μModule Regulator|2.25V ≤ VIN≤ 5.5V, 0.5V ≤ VOUT≤ VIN, 7.5mm × 15mm × 4.65mm BGA|
|LTM4611|Ultralow VIN, 15A μModule Regulator|1.5V ≤ VIN≤ 5.5V, 0.8V ≤ VOUT≤ 5V, 15mm × 15mm × 4.32mm LGA|
|LTM4643|Low VINwith External Bias Voltage, Quad 3A<br>μModule Regulator|2.375V ≤ VIN≤ 20V, 0.6V ≤ VOUT≤ 3.3V, 9mm × 15mm × 1.82mm BGA,<br>9mm × 15mm × 2.42mm BGA|
|LTM4702|16VIN, 8A Ultralow Noise Silent Switcher<br>μModule Regulator|3V ≤ VIN≤ 16V, 0.3V ≤ VOUT≤ 5.7V, 6.25mm × 6.25mm × 5.07mm BGA|
|LTM8060|Quad 40VIN, Silent Switcher μModule Regulator<br>with Configurable 3A Output Array|3V ≤ VIN≤ 40V, 0.8V ≤ VOUT≤ 8V, 11.9mm × 16mm × 3.32mm BGA|
|LTM8051|Quad 40VINSilent Switcher μModule Regulator<br>with Configurable 1.2A Output Array|3V ≤ VIN≤ 40V, 0.8V ≤ VOUT≤ 8V, 6.25mm × 11.25mm × 2.22mm BGA|



Rev. 0 

07/23 www.analog.com 

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