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LTM4682IY#PBF
Non Isolated POL DC/DC Converter, BGA-330, Micro Module, 700 mV, 1.35 V, 31.25 A
⚠️ Reference pricing provided. In case of supply shortages, we will connect you with our trusted procurement partners to ensure your project's continuity.
- Manufacturer: ANALOG DEVICES
- Product type: DC / DC Non Isolated Board Mount Converters - Adjustable Output
- SVHC: Lead (04-Feb-2026)
- Depth: 22mm
- Width: 15mm
- Height: 5.71mm
- Product Range: LTM4682 Series
- Output Power Max: -
- Output Current Max: 31.25A
- Output Voltage Max: 1.35V
- Output Voltage Min: 700mV
- Input Voltage DC Max: 16V
- Input Voltage DC Min: 4.5V
- DC / DC Converter Type: BGA-330, Micro Module
- Power Supply Applications: -
- DC / DC Converter Output Type: Adjustable
| Delivery and price | |
|---|---|
| Units per pack | 60 |
| Price | 168.1 € |
| Current stock | 10+ |
| Lead time | 30 days |
Datasheet
LTM4682
Low Profile Quad 31.25A or Single 125A μModule Regulator with Digital Power System Management
## **FEATURES**
- n **Quad Digitally Adjustable Analog Loops with Digital Interface for Control and Monitoring**
- n **Wide Input Voltage Range: 4.5V to 16V**
- n **Output Voltage Range: 0.7V to 1.35V**
- n **±0.5% DC Output Accuracy at 0.75V**
- n **±4.5% Current Readback Accuracy: 0°C to 125°C**
- n **Optimized for Low Output Voltage Ranges**
- n **400kHz PMBus-Compliant I[2] C Serial Interface**
- n **Supports Telemetry Polling Rates Up to 125Hz**
- n **Integrated 16-Bit** ∆Σ **ADC**
- n **Parallel and Current Share Multiple Modules**
- n 15mm × 22mm × 5.71mm BGA Package **Readable Data**
- n Input and Output Voltages, Currents, and Temperatures
- n Running Peak Values, Uptime, Faults and Warnings
- n Onboard EEPROM Fault Log Record
- **Writable Data and Configurable Parameters**
- n Output Voltage, Voltage Sequencing and Margining
- n Digital Soft-Start/Stop Ramp, Program Analog Loop
- n OV/UV/OT, UVLO, Frequency and Phasing
## **APPLICATIONS**
## **DESCRIPTION**
The LTM[®] 4682 is a quad 31.25A or single 125A step-down power µModule[®] (power micromodule) DC/DC regulator featuring remote configurability and telemetry monitoring of power management parameters over PMBus. The LTM4682 is comprised of digitally programmable analog control loops, and is optimized for higher bandwidth and transient response.
The LTM4682’s 2-wire serial interface allows outputs to be margined, tuned, and ramped up and down at programmable slew rates with sequencing delay times. True input current sense, output currents, output voltages, output power, temperatures, uptime, and peak values are readable. Custom configuration of the EEPROM contents is not required. At start-up, output voltages, switching frequency, and channel phase angle assignments can be set by pin-strapping resistors. The LTpowerPlay[®] graphical user interface (GUI), the DC1613A USB-to-PMBus converter, and evaluation kits are available.
The LTM4682 is offered in a 15mm × 22mm × 5.71mm BGA package available with an SnPb or a RoHS-compliant terminal finish.
All registered trademarks and trademarks are the property of their respective owners.
- n Multi-Rail Processor Power, Configurable Core Power
## **TYPICAL APPLICATION**
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Single Channel Efficiency<br>Quad 31.25A µModule Regulator with Digital Interface for Control and Monitoring vs Load Current<br>4.5V TO 16V 100<br>0.75V AT 31.25A<br>22µF×6 RSENSE1 IN_01 [+] VOSNS0VOUT0 [+] CER+ 95<br>IN_01 [–] LOAD CBULK 90<br>VIN01 VOSNS0 [–] 85<br>22µF SVIN_23IN_01 [+] VOSNS1VOUT1 [+] 0.9V AT 31.25ACER+ 80<br>×6 RSENSE2 LOAD CBULK 75<br>IN_23VSVVRUNPIN23IN_VBIASIN_23 [–] LTM4682 VVOSNS1OSNS2VOUT2 [–][+] LOAD 1.0V AT 31.25ACER+ CBULK 706560 12V 12V12V 12V 12VINININININ, 0.75V , 0.9V , 1.0V , 1.2V , 1.35VOUTOUTOUTOUTOUT , 650kHz , 650kHz , 650kHz , 575kHz, 750kHz<br>ON/OFF CONTROL RUN0,1,2,3 VOSNS2 [–] 0 5 10 15 20 25 30 35<br>POWER GOOD MONITORSFAULT INTERRUPTS FAULTPGOOD0,1,2,30,1,2,3 VOSNS3VOUT3 [+] 1.2V AT 31.25ACER+ LOAD CURRENT (A) 4682 TA01b<br>LOAD CBULK<br>(FROM 4.5V TO 5.5VCONNECT VIN, SVIN, VOSNS3 [–] Configurable Output Array<br>AND INTVCC TOGETHER) 4682 TA01a 31.25A<br>62.5A 62.5A<br>31.25A 93.75A<br>125A<br>FOR COMPLETE CIRCUIT SYNCHRONIZATION TIME I [2] C/SMBus I/F WITH PMBus COMMAND 31.25A 31.25A<br>SEE FIGURE 48 BASE REGISTER WRITEPROTECTION SET TO/FROM IPMI OR OTHERBOARD MANAGEMENT CONTROLLER 31.25A 31.25A 31.25A 62.5A<br>EFFICIENCY (%)<br>_23 _01<br>WP_01 WP_23 SYNC_23 SYNC_01 SHARE_CLK_23 SHARE_CLK_01 ALERT ALERT SDA_23 SDA_01 SCL_23 SCL_01 SGND_01 SGND_23 GND<br>**----- End of picture text -----**<br>
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## LTM4682
## **TABLE OF CONTENTS**
**Features ..................................................... 1 Applications ................................................ 1 Typical Application ........................................ 1 Description.................................................. 1 Absolute Maximum Ratings .............................. 4 Order Information .......................................... 4 Pin Configuration .......................................... 4 Electrical Characteristics ................................. 5 Typical Performance Characteristics ..................12 Pin Functions ..............................................15 Simplified Block Diagram ...............................23 Decoupling Requirements ...............................23 Functional Diagram ......................................24 Test Circuits ...............................................25 Operation...................................................27** Power Module Introduction ....................................27 Power Module Overview, Major Features ................27 EEPROM with ECC ..................................................28 Power-Up and Initialization .....................................29 Soft-Start ................................................................30 Time-Based Sequencing .........................................30 Voltage-Based Sequencing .....................................31 Shutdown ...............................................................31 Light-Load Current Operation .................................31 Switching Frequency and Phase .............................32 PWM Loop Compensation ......................................32 Output Voltage Sensing ..........................................32 INTVCC/VBIAS Power ...............................................32 Output Current Sensing and Sub Milliohm DCR Current Sensing ......................................................33 Input Current Sensing .............................................33 PolyPhase Load Sharing .........................................33 Internal Temperature Sense ....................................34 RCONFIG (Resistor Configuration) Pins ..................34 Table 1. VOUT _n_ _CFG Pin Strapping Look-Up Table for the LTM4682’s Output Voltage, Coarse Setting (Not Applicable if MFR_CONFIG_ALL[6] = 1b) Top Resistor = 14.3k ......................................................35 Table 2. VTRIMn_CFG Pin Strapping Look-Up Table for the LTM4682’s Output Voltage, Fine Adjustment Setting (Not Applicable if MFR_CONFIG_ALL[6] = 1b) Top Resistor = 14.3k .........................................35 Table 3. FSWPH nn_ _CFG Pin Strapping Look-Up Table to Set the LTM4682’s Switching Frequency and
Channel Phase-Interleaving Angle (Not Applicable if MFR_CONFIG_ALL[6] = 1b), _nn_ = 01 or 23 Channels, Set Top Resistor to 14.3k ........................................36 Table 4. ASEL nn_ Pin Strapping Look-Up Table to Set the LTM4682’s Subordinate Address (Applicable Regardless of MFR_CONFIG_ALL[6] Setting) ........37 Table 5. LTM4682 MFR_ADDRESS Command Examples Expressed in 7- and 8-Bit Addressing .....37 Fault Detection and Handling ..................................37 Status Registers and ALERT Masking .......................38 Figure 5. LTM4682 Status Register Summary per Controller ................................................................39 Mapping Faults to FAULT _n_ Pins .................................40 Power Good Pins ......................................................40 CRC Protection .........................................................40 Serial Interface .......................................................40 Communication Protection .......................................40 Device Addressing ..................................................40 Responses to VOUT and IIN/IOUT Faults ...................41 Output Overvoltage Fault Response ..........................41 Output Undervoltage Response ................................42 Peak Output Overcurrent Fault Response .................42 Responses to Timing Faults ....................................42 Responses to VIN OV Faults ....................................42 Responses to OT/UT Faults .....................................42 Internal Overtemperature Fault Response .................42 Overtemperature and Undertemperature Fault Response .......................................................43 Responses to Input Overcurrent and Output Undercurrent Faults ................................................43 Responses to External Faults ..................................43 Fault Logging ..........................................................43 Bus Timeout Protection ..........................................43 Similarity Between PMBus, SMBus and I[2] C 2-Wire Interface .................................................................44 PMBus Serial Digital Interface ................................44 Table 6. Abbreviations of Supported Data Formats ...45 Figure 6. PMBus Timing Diagram .............................45 Figure 7 to Figure 24 PMBus Protocols ..................46 **PMBus Command Summary ............................49** PMBus Commands .................................................49 Table 7. PMBus Commands Summary (Note: The Data Format Abbreviations Are Detailed in Table 8) ........49 Table 8. Data Format Abbreviations ..........................54
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LTM4682
## **TABLE OF CONTENTS**
**Applications Information ................................55** VIN to VOUT Step-Down Ratios ................................55 Input Capacitors .....................................................55 Output Capacitors ...................................................55 Light Load Current Operation .................................55 Switching Frequency and Phase .............................56 Output Current Limit Programming ........................57 Minimum On-Time Considerations..........................58 Variable Delay Time, Soft-Start and Output Voltage Ramping .................................................................58 Digital Servo Mode .................................................58 Soft Off (Sequenced Off) ........................................59 Undervoltage Lockout .............................................60 Fault Detection and Handling ..................................60 Open-Drain Pins .....................................................60 Phase-Locked Loop and Frequency Synchronization .. 61 Input Current Sense Amplifier .................................62 Programmable Loop Compensation .......................62 Checking Transient Response .................................63 PolyPhase Configuration...........................................64 Connecting The USB to I[2] C/SMBus/PMBus Controller to the LTM4682 In System .....................................64 LTpowerPlay: An Interactive GUI for Digital Power .65 PMBus Communication and Command Processing 65 Thermal Considerations and Output Current Derating . 67 Table 10 through Table 12: Output Current Derating ........71 Table 13. Single Channel Output Voltage vs Capacitor Selection, 10A to 20A Load Step with 10A/µs Slew Rate ................................................................72 Table 14. Single Channel Output Voltage vs Capacitor Selection, All Ceramic Configuration, 10A to 20A Load Step with 10A/µs Slew Rate ...........................72 Table 15. Dual Connected Channels Output Voltage vs Capacitor Selection, Bulk and Ceramic Cap Configuration, 10A to 30A Load Step with 20A/µs Slew Rate ................................................................73 Table 16. Quad Connected Channels Output Voltage vs Capacitor Selection, Bulk and Ceramic Cap Configuration, 10A to 40A Load Step with 15A/µs Slew Rate ................................................................73 EMI Performance .................................................... 74 Safety Considerations ............................................. 74 Layout Checklist/Example ......................................75
**Typical Application .......................................76 PMBus Command Details ...............................81** Addressing and Write Protect .................................81 General Configuration Commands ..........................83 On/Off/Margin ........................................................84 PWM Configuration ................................................86 Voltage ....................................................................89 Input Voltage and Limits ...........................................89 Output Voltage and Limits ........................................90 Output Current and Limits ......................................93 Input Current and Limits ...........................................95 Temperature ............................................................96 Power Stage DCR Temperature Calibration ...............96 Power Stage Temperature Limits ..............................96 Timing ....................................................................97 Timing—On Sequence/Ramp ...................................97 Timing—Off Sequence/Ramp...................................98 Precondition for Restart ...........................................99 Fault Response .......................................................99 Fault Responses All Faults ........................................99 Fault Responses Input Voltage ................................100 Fault Responses Output Voltage .............................100 Fault Responses Output Current .............................103 Fault Responses IC Temperature.............................104 Fault Responses External Temperature ...................105 Fault Sharing .........................................................106 Fault Sharing Propagation.......................................106 Fault Sharing Response ..........................................108 Scratchpad ...........................................................108 Identification .........................................................109 Fault Warning and Status ...................................... 110 Telemetry .............................................................. 116 NVM Memory Commands .................................... 120 Store/Restore ......................................................... 120 Fault Logging .......................................................... 121 Block Memory Write/Read ...................................... 125 **Package Description ................................... 126** Table 25. LTM4682 BGA Pinout .............................. 126 **Package Description ................................... 127 Revision History ........................................ 129 Package Photos ......................................... 130 Design Resources ...................................... 130 Related Parts ............................................ 130**
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## LTM4682
## **ABSOLUTE MAXIMUM RATINGS**
## **PIN CONFIGURATION**
## **(Note 1)**
**Terminal Voltages** VIN _nn_ (Note 4), SVIN nn_ , IIN nn_[+] , IIN nn_[−] , VIN_VBIAS, RUNP ........................................ –0.3V to 18V (SVIN nn_ – IIN nn_[+] ), (IIN nn_[+] – IIN nn_[−] ) ....... –0.3V to 0.3V SW _n_ ............................ −1V to 18V, −5V to 18V Transient INTVCC nn_ , VBIAS ......................................... –0.3V to 6V VOUT _n_ ........................................................ –0.3V to 2.0V VOSNS _n_[+] ..................................................... –0.3V to 2.0V VOSNS _n_[−] ..................................................... –0.3V to 0.3V RUN _n_ , SDA nn_ , SCL nn_ , ALERT nn_ ......... –0.3V to 5.5V FSWPH nn_ _CFG, VOUT _n__ CFG, VTRIM _n__ CFG, ASEL nn_ .......................... –0.3V to 2.75V FAULT _n_ , SYNC nn_ , SHARE_CLK nn_ , WP nn_ , PGOOD _n_ ...................................... −0.3V to 3.6V COMP _n_ a, COMP _n_ b .................................... –0.3V to 2.7V TSNS _n_ ....................................................... –0.3V to 0.8V _n_ = 0, 1, 2, 3 and _nn_ = 01, 23 VDD33 nn_ and VDD25 nn_ Are Outputs Not to Be Driven. **Temperatures** Internal Operating Temperature Range (Notes 2, 15, 16) .................................... –40°C to 125°C Storage Temperature Range .................. –55°C to 125°C Peak Solder Reflow Package Body Temperature ... 245°C
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TOP VIEW<br>1 2 3 4 5 6 7 8 9 10 11 12 13 14 15<br>A<br>GND VOUT0<br>VDD25_01 VTRIM1_CFG SDA_01 BC ALERT_01<br>SW0 VIN01 SCL_01 SYNC_01<br>VTRIM0_CFG SHARE_CLK_01VDD33_01 WP_01 DE TSNS1SGND_01TSNS0<br>COMP1b VOSNS1 [–] VOUT1 F<br>COMP1a VOSNS1 [+] G COMP0b COMP0a<br>PGOOD0INTVCC_01 PGOOD1SVIN_01 SW1 HJK IN_01IN_01 [+][–] VVOSNS0OSNS0 [–][+]<br>GND<br>L<br>GND<br>VIN_VBIAS VBIAS RUNP M<br>VOSNS2 [+] SW2 VIN23 IN_23IN_23 [–][+] VOUT2 NP SVIN_23 INTVCC_23<br>VOSNS2 [–] R PGOOD2 VOSNS3 [+]<br>COMP2b COMP2a TSNS3 T PGOOD3 VOSNS3 [–]<br>SCL_23SYNC_23 ALERTSDA_23TSNS2RUN3_23 SW3 GND RUN2 VOUT3 UVWYAA SGND_23FAULTFAULTVDD33_2323 COMP3aCOMP3bWP_23<br>AB<br>BGA PACKAGE<br>330-PIN (15mm × 22mm × 5.71mm)<br>TJMAX = 125°C, θJCtop = 2.8°C/W, θJCbottom = 1.4°C/W, θJA = 4.4°C/W<br>θ VALUES ARE DETERMINED BY SIMULATION PER JESD51 CONDITIONS, WEIGHT = 6.4g (TYP.).<br>θJA VALUE IS OBTAINED WITH DEMO BOARD.<br>SEE THE APPLICATIONS INFORMATION SECTION FOR LAB MEASUREMENT AND DERATING INFORMATION.<br>VOUT1_CFG ASEL_01 RUN0 RUN1<br>VOUT0_CFG FSWPH_01_CFG FAULT1 FAULT0<br>VDD25_23<br>VOUT3_CFG VTRIM3_CFG VTRIM2_CFG<br>VOUT2_CFG FSWPH_23_CFG ASEL_23 SHARE_CLK_23<br>**----- End of picture text -----**<br>
## **ORDER INFORMATION**
|**PART NUMBER**|**PAD OR BALL**<br>**FINISH***|**PART MARKING**|**PART MARKING**|**PACKAGE**<br>**TYPE**|**MSL**<br>**RATING**|**TEMPERATURE RANGE**<br>**(SEE NOTE 2)**|
|---|---|---|---|---|---|---|
|||**DEVICE**|**FINISH CODE**||||
|LTM4682EY#PBF|SAC305(RoHS)|LTM4682Y|e1|BGA|4|–40°C to 125°C|
|LTM4682IY#PBF|SAC305(RoHS)|LTM4682Y|e1|BGA|4|–40°C to 125°C|
|LTM4682IY|SnPb(63/37)|LTM4682Y|e0|BGA|4|–40°C to 125°C|
- Contact the factory for parts specified with wider operating temperature ranges. *Pad or ball finish code is per IPC/JEDEC J-STD-609.
- Recommended LGA and BGA PCB Assembly and Manufacturing Procedures
- LGA and BGA Package and Tray Drawings
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LTM4682
## **ELECTRICAL CHARACTERISTICS**
**The** l **denotes the specifications which apply over the specified internal operating temperature range (Note 2). Specified as each individual output channel (Note 4). TA = 25°C, VIN = 12V, RUN** _**n**_ **= 3.3V, RUNP = 12V, FREQUENCY_SWITCH = 575kHz and VOUT** _**n**_ **commanded to 0.75V unless otherwise noted. Configured with factory-default EEPROM settings and per Test Circuit 1, unless otherwise noted.**
|**SYMBOL**|**PARAMETER**|**CONDITIONS**|**CONDITIONS**|**MIN**<br>**TYP**<br>**MAX**|**UNITS**|
|---|---|---|---|---|---|
|VIN_nn_|Input DC Voltage|Test Circuit 1<br>Test Circuit 2, VIN_OFF < VIN_ON = 4V|l<br>l|<br>5.75<br>4.5<br>16<br>5.75|V<br>V|
|VOUT_n_|Range of Output Voltage Regulation<br>for Each Channel|VOUT_n_Differentially Sensed on VOSNS_n_+/VOSNS_n_–Pin-Pair,<br>Commanded by Serial Bus or with Resistors Present at<br>Start-Up on VOUT_n__CFG|l|<br>0.7<br>1.35|V<br>V|
|VOUT_n_(DC)|Output Voltage, Total Variation with<br>Line and Load for Each Channel|Digital Servo Engaged (MFR_PWM_MODE_n_[6] = 1b)<br>Digital Servo Disengaged (MFR_PWM_MODE_n_[6] = 0b)<br>VOUT_n_Commanded to 0.75V, VOUT_n_Low Range (MFR_<br>PWM_MODE_n_[1]= 1b) (Notes 5, 6)|l|0.745<br>0.742<br>0.750<br>0.750<br>0.755<br>0.758|V<br>V|
|VUVLO|Undervoltage Lockout Threshold,<br>When VIN< 4.3V|VINTVCCnn_Falling<br>VINTVCCnn_Rising||3.55<br>3.90|V<br>V|
|**Input Specifications**||||||
|IINRUSH(VIN_nn_)|Input Inrush Current at Start-Up|Test Circuit 1, VOUT_n_ = 0.75V, VIN= 12V; No Load Besides<br>Capacitors; TON_RISE_n_ = 3ms||200|mA|
|IQ(SVIN_nn_)|Input Supply Bias Current|Forced Continuous Mode, MFR_PWM_MODE_n_[0] = 1b<br>RUN_n_= RUNP = 3.3V<br>Shutdown, RUN_n_ = RUNP = 0V||40<br>25|mA<br>mA|
|IS(VIN_nn_,PSM)|Input Supply Current in Pulse-<br>Skipping Mode Operation|Pulse-Skipping Mode, MFR_PWM_MODE_n_[0] = 0b,<br>IOUT_n_= 100mA||10|mA|
|IS(VIN_nn_,FCM)|Input Supply Current in Forced-<br>Continuous Mode Operation|Forced Continuous Mode, MFR_PWM_MODE_n_[0] = 1b<br>12V to 0.75V, IOUT_n_= 31.25A, VBIAS= Off||2.3|A|
|IS(VIN_nn_,SHUTDOWN)|Input Supply Current in Shutdown|Shutdown, RUN_n_= 0V, RUNP = 0V, VBIAS= Off||300|µA|
|**Output Specifications**||||||
|IOUT_n_|Output Continuous Current Range<br>Each Channel|(Note 6) Utilizing MFR_PWM_MODE[7] = 1 and Using<br>~IOUT= 42A for IOUT_OC_FAULT_LIMIT, See the IOUT_<br>OC_FAULT_LIMIT in the PMBus Command Details Section||0<br>31.25|A|
|∆VOUT_n_(LINE)<br>VOUT_n_|Line Regulation Accuracy Each<br>Channel|Digital Servo Engaged (MFR_PWM_MODE_n_[6] = 1b)<br>Digital Servo Disengaged (MFR_PWM_MODE_n_[6] = 0b)<br>SVINand VIN_n_Electrically Shorted Together and INTVCC<br>Open Circuit, IOUT_n_ = 0A, 5.75V ≤ VIN≤ 16V, VOUTLow Range<br>(MFR_PWM_MODE_n_[1] = 1b), FREQUENCY_SWITCH =<br>575kHz(Note 5)|l|0.03<br>0.03<br>±0.2|%/V<br>%/V|
|∆VOUT_n_(LOAD)<br> VOUT_n_|Load Regulation Accuracy Each<br>Channel|Digital Servo Engaged (MFR_PWM_MODE_n_[6] = 1b)<br>Digital Servo Disengaged (MFR_PWM_MODE_n_[6] = 0b)<br>0A ≤ IOUT_n_≤ 31.25A, VOUTLow Range, (MFR_PWM_<br>MODE_n_[1]= 1b) (Notes 5, 6)|l|0.03<br>0.2<br>0.5|%<br>%|
|VOUT_n_(AC)|Output Voltage Ripple|||10|mVP-P|
|fS (Each Channel)|VOUT_n_Ripple Frequency|FREQUENCY_SWITCH Set to 575kHz(0x023F)|l|535<br>575<br>605|kHz|
|∆VOUT_n_(START)|Turn-On Overshoot|TON_RISE_n_= 3ms(Note 12)||8|mV|
|tSTART|Turn-On Start-Up Time|Time from VINToggling from 0V to 12V to Rising Edge<br>PGOOD_n_. TON_DELAY_n_= 0ms, TON_RISE_n_ = 3ms|l|35|ms|
|tDELAY(0ms)|Turn-On Delay Time|Time from First Rising Edge of RUN_n_to Rising Edge of<br>PGOOD_n _. TON_DELAY_n _= 0ms, TON_RISE_n _= 3ms,<br>VINHaving Been Established for at Least 70ms||2.75<br>3.3<br>3.8|ms|
|∆VOUT_n_(LS)|Peak Output Voltage Deviation for<br>Dynamic Load Step|Load: 0A to 10A and 10A to 0A at 10A/µs,<br>VOUT_n_= 0.75V, VIN= 12V(Note 12)See Transient Graph||35|mV|
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## LTM4682
## **ELECTRICAL CHARACTERISTICS**
**The** l **denotes the specifications which apply over the specified internal operating temperature range (Note 2). Specified as each individual output channel (Note 4). TA = 25°C, VIN = 12V, RUN** _**n**_ **= 3.3V, RUNP = 12V, FREQUENCY_SWITCH = 575kHz and VOUT** _**n**_ **commanded to 0.75V unless otherwise noted. Configured with factory-default EEPROM settings and per Test Circuit 1, unless otherwise noted.**
|**SYMBOL**|**PARAMETER**|**CONDITIONS**|**CONDITIONS**|**MIN**<br>**TYP**<br>**MAX**|**UNITS**|
|---|---|---|---|---|---|
|tSETTLE|Settling Time for Dynamic Load Step<br>per Channel|Load: 0A to 10A and 10A to 0A at 10A/µs,<br>VOUT_n_ = 0.75V, VIN= 12V (Note 12) See the Transient<br>Graphs in the Typical Performance Characteristics section.||30|µs|
|IOUT_n_(OCL_PK)|Output Current Limit, Peak High<br>Range per Channel|Cycle-by-Cycle Inductor Peak Current Limit Inception,<br>Utilizing MFR_PWM_MODE[7] = 1, Using ~IOUT= 42A<br>for IOUT_OC_FAULT_LIMIT, See the IOUT_OC_FAULT_<br>LIMIT in the PMBus Command Details Section||45|A|
|IOUT_n_(OCL_AVG)|Output Current Limit, Time Averaged<br>per Channel|Time-Averaged Output Inductor Current Limit Inception<br>Threshold, Commanded by IOUT_OC_FAULT_LIMIT_n_<br>(Note 12) Utilizing MFR_PWM_MODE[7] = 1, Using ~IOUT<br>= 42A, See the IOUT_OC_FAULT_LIMIT in the PMBus<br>Command Details Section||40<br>See the IOUT-RB-ACC<br>Specification (Output<br>Current Readback<br>Accuracy)|A|
|**Control Section**||||||
|VFBCM_n_|Channel 0 to Channel 3 Feedback<br>Input Common Mode Range|VOSNS_n_–Valid Input Range (Referred to SGND)<br>VOSNS_n_+Valid Input Range(Referred to SGND)|l<br>l|<br>–0.1<br>0.3<br>2.0|V<br>V|
|VOUT-RNGL|Full-Scale Command Voltage, Range<br>Low (0.7V to 2.75V) per Channel<br>(Note 14)|VOUT_n_Commanded to 2.750V, MFR_PWM_MODE_n_[1] = 1b<br>Set Point Accuracy<br>Resolution<br>LSB Step Size||−0.5<br>2.75<br>12<br>0.688<br>+0.5|V<br>%<br>Bits<br>mV|
|RVSNS_n_+|VOSNS_n_+Impedance to SGND|0.5V ≤ VVOSNS_n_+– VSGND≤ 1.5V||50|kΩ|
|tON(MIN)|Minimum On-Time|(Note 8)per Channel||85|ns|
|RCOMP_n_|Resolution<br>Compensation Resistor RTH(MAX)<br>Compensation Resistor RTH(MIN)|MFR_PWM_CONFIG[4:0] = 0 to 31 (See Figure 1, in the<br>Note Section)||5<br>62<br>0|Bits<br>kΩ<br>kΩ|
|gm_n_|Resolution<br>Error Amplifier gm(MAX)<br>Error Amplifier gm(MIN)<br>LSB Step Size|VCOMP_n_= 1.35V, MFR_PWM_CONFIG[7:5] = 0 to 7||3<br>5.76<br>1<br>0.68|Bits<br>mmho<br>mmho<br>mmho|
|**Analog OV/UV (Overvoltage/Undervoltage) Output Voltage Supervisor Comparators (VOUT_OV/UV_FAULT_LIMIT and VOUT_OV/UV_WARN_LIMIT Monitors)**||||||
|NOV/UV_COMP|Resolution, Output Voltage<br>Supervisors|(Notes 13, 14)||9|Bits|
|VOV-RNG|Output OV Comparator Threshold<br>Detection Range|High Range Scale, Not Needed, Output Limited to 1.35V<br>Low Range Scale, MFR_PWM_MODE_n_[1]= 1b(Note 14)||0.7<br>2.7|V|
|VOUSTP|Output OV and UV Comparator<br>Threshold Programming LSB Step Size|(Note 14)<br>Low Range Scale, MFR_PWM_MODE_n_[1]= 1b||5.6|mV|
|VOV-ACC-_n_|Output OV Comparator Threshold<br>Accuracy Channel 0 to Channel 3<br>(Note 13)|0.7V ≤ VVOSNS_n_+– VVOSNS_n_–≤ 1.35V, MFR_PWM_MODE[1] = 1b|l|±3|%|
|VUV-RNG_n_|Output UV Comparator Threshold<br>Detection Range|High Range Scale, Not Needed, Output Limited to 1.35V<br>Low Range Scale, MFR_PWM_MODE_n_[1]= 1b||0.7<br>2.7|V<br>V|
|VUV-ACC_n_|Output UV Comparator Threshold<br>Accuracy Channel 0 to Channel 3<br>(Note 13)|0.7V ≤ VVOSNS_n_+– VVOSNS_n_–≤ 1.35V, MFR_PWM_MODE[1] = 1b|l|±3|%|
|tPROP-OV|Output OV Comparator<br>Response Times|Overdrive to 10% Above Programmed Threshold||100|µs|
|tPROP-UV|Output UV Comparator<br>Response Times|Underdrive to 10% Below Programmed Threshold||100|µs|
Rev. 0
6
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LTM4682
## **ELECTRICAL CHARACTERISTICS**
**The** l **denotes the specifications which apply over the specified internal operating temperature range (Note 2). Specified as each individual output channel (Note 4). TA = 25°C, VIN = 12V, RUN** _**n**_ **= 3.3V, RUNP = 12V, FREQUENCY_SWITCH = 575kHz and VOUT** _**n**_ **commanded to 0.75V unless otherwise noted. Configured with factory-default EEPROM settings and per Test Circuit 1, unless otherwise noted.**
|**SYMBOL**|**PARAMETER**|**CONDITIONS**|**CONDITIONS**|**MIN**<br>**TYP**<br>**MAX**|**UNITS**|
|---|---|---|---|---|---|
|**Analog OV/UV SVINnn_ Input Voltage Supervisor Comparators (Threshold Detectors for VIN_ON and VIN_OFF)**||||||
|NSVIN-OV/UV-COMP|SVINnn_OV/UV Comparator<br>Threshold-Programming Resolution|(Note 14)||9|Bits|
|SVIN-OU-RANGE|SVINnn_OV/UV Comparator<br>Threshold-Programming Range|Limited to Abs Max = 18V|l|4.5<br>18|V|
|SVIN-OU-STP|SVINnn_OV/UV Comparator Threshold-<br>Programming LSB Step Size|(Note 14)||76|mV|
|SVIN-OU-ACC|SVINnn_OV/UV Comparator<br>Threshold Accuracy|9V < SVIN≤ 16V<br>4.5V ≤ SVIN≤ 9V|l<br>l|<br>±3<br>±270|%<br>mV|
|tPROP-SVIN-HIGH-VIN|SVINnn_OV/UV Comparator<br>Response Time, High VINOperating<br>Configuration|Test Circuit 1, and:<br>VIN_ON = 9V, SVINDriven from 8.775V to 9.225V<br>VIN_OFF = 9V, SVINDriven from 9.225V to 8.775V|l<br>l|<br>100<br>100|µs<br>µs|
|tPROP-SVIN-LOW-VIN|SVINnn_OV/UV Comparator<br>Response Time, Low VINOperating<br>Configuration|Test Circuit 2, and:<br>VIN_ON = 4.5V, SVINDriven from 4.225V to 4.725V<br>VIN_OFF = 4.5V, SVINDriven from 4.725V to 4.225V|l<br>l|<br>100<br>100|µs<br>µs|
|**Channel****_n_ Output Voltage Readback (READ_VOUT****_n_)**||||||
|NVO-RB|Output Voltage Readback Resolution<br>and LSB Step Size|(Note 14)||16<br>244|Bits<br>µV|
|VO-F/S|Output Voltage Full-Scale<br>Digitizable Range|VRUN_n_= 0V (Note 14), Limited to 1.35V Max Operating||8|V|
|VO-RB-ACC|Output Voltage Readback Accuracy|Channel_n_: 0.7V ≤ VVOSNS+ – VVOSNS–< 1.35V|l|–7<br>7|mV|
|tCONVERT-VO-RB|Output Voltage Readback<br>Update Rate|MFR_ADC_CONTROL = 0x00 (Notes 9, 14)<br>MFR_ADC_CONTROL = 0x01 through 0x0C (Notes 9, 14)<br>MFR_ADC_CONTROL Section||90<br>8|ms<br>ms<br>ms|
|**Input Voltage (SVINnn_ ) Readback (READ_VIN)**||||||
|NSVIN-RB|Input Voltage Readback Resolution<br>and LSB Step Size|(Notes 10, 14) Limited to Abs Max = 18V||10<br>15.625|Bits<br>mV|
|SVIN-F/S|Input Voltage Full-Scale<br>Digitizable Range|(Notes 11, 14) Limited to 16V Operating||43|V|
|SVIN-RB-ACC|Input Voltage Readback Accuracy|READ_VIN, 4.5V ≤ SVIN≤ 16V|l|Within ±2% of Reading||
|tCONVERT-SVIN-RB|Input Voltage Readback Update Rate|MFR_ADC_CONTROL = 0x00 (Notes 9, 14)<br>MFR_ADC_CONTROL = 0x01(Notes 9, 14)||90<br>8|ms<br>ms|
|**Channel****_n_ Output Current (READ_IOUT****_n_), Duty Cycle (READ_DUTY_CYCLE****_n_), and Computed Input Current (MFR_READ_IIN**_n_**) Readback**||||||
|NIO-RB|Output Current Readback Resolution<br>and LSB Step Size|(Notes 10, 14)||10<br>34.1|Bits<br>mA|
|IOUT-F/S|Output Current Full-Scale<br>Digitizable Range|(Note 14) Utilizing MFR_PWM_MODE[7] = 1, Using<br>IOUT_OC_FAULT_LIMIT = 61A, See the IOUT_OC_<br>FAULT_LIMIT in the PMBus Command Details Section||54|A|
|IOUT-RB-ACC|Output Current, Readback Accuracy|READ_IOUT_n_, Channel 0 to Channel 3, 0 ≤ IOUT_n_≤ 25A,<br>Forced Continuous Mode, MFR_PWM_MODE_n_[0] = 1b<br>See Histograms in Typical Performance Characteristics<br>Section,(Note 12)|l|Within 1.5A of Reading||
|IOUT-RB(31.25A)|Full Load Output Current Readback|(Note 12), See Histograms in Typical Performance<br>Characteristics||31.25|A|
|tCONVERT-IO-RB|Output Current Readback Update<br>Rate|MFR_ADC_CONTROL = 0x00 (Notes 9, 14)<br>MFR_ADC_CONTROL = 0x06 (CH0,2 IOUT) or 0x0A (CH1,3 IOUT)<br>(Notes 9, 14)See MFR_ADC_CONTROL SECTION||90<br>8|ms<br>ms|
Rev. 0
7
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## LTM4682
## **ELECTRICAL CHARACTERISTICS**
**The** l **denotes the specifications which apply over the specified internal operating temperature range (Note 2). Specified as each individual output channel (Note 4). TA = 25°C, VIN = 12V, RUN** _**n**_ **= 3.3V, RUNP = 12V, FREQUENCY_SWITCH = 575kHz and VOUT** _**n**_ **commanded to 0.75V unless otherwise noted. Configured with factory-default EEPROM settings and per Test Circuit 1, unless otherwise noted.**
|**SYMBOL**|**PARAMETER**|**CONDITIONS**|**CONDITIONS**|**MIN**<br>**TYP**<br>**MAX**|**UNITS**|
|---|---|---|---|---|---|
|**Input Current Readback**||||||
|N|Resolution|(Note 10)||10|Bits|
|VIINSTP|LSB Step Size Full-Scale Range = 16mV<br>LSB Step Size Full-Scale Range = 32mV<br>LSB Step Size Full-Scale Range = 64mV|Gain = 8, 0V ≤ |VIIN+– VIIN–| ≤ 5mV<br>Gain = 4, 0V ≤ |VIIN+– VIIN–| ≤ 20mV<br>Gain = 2, 0V ≤|VIIN+– VIIN–|≤ 50mV||15.26<br>30.52<br>61|µV<br>µV<br>µV|
|IIN_TUE|Total Unadjusted Error|Gain = 8, 2.5mV ≤ |VIIN+– VIIN–| (Note 7)<br>Gain = 4, 4mV ≤ |VIIN+– VIIN–| (Note 7)<br>Gain = 2, 6mV ≤|VIIN+– VIIN–| (Note 7)||2<br>1.3<br>1.2|%<br>%<br>%|
|VOS|Zero-Code Offset Voltage|(Note 14)||±50|µV|
|tCONVERT|Update Rate|(Notes 9,15), See MFR_ADC_CONTROL Section for<br>Faster Update Rates||90|ms|
|**Supply Current Readback (Note 15)**||||||
|N|Resolution|(Note 10)||10|Bits|
|VICHIPSTP|LSB Step Size Full-Scale Range =<br>256mV|Onboard 1Ω Resistor||244|µV|
|ICHIP_RB|ICHIPReadback|SVINnn_Current||50|mA|
|tCONVERT|Update Rate|(Notes 9,14), See MFR_ADC_CONTROL Section for<br>Faster Update Rates||90|ms|
|**Temperature Readback (T0, T1)**||||||
|TRES-RB|Temperature Readback Resolution|Channel_n_, and Controller(Note 14)||0.25|°C|
|T0_TUE|External Temperature Total<br>Unadjusted Readback Error|Supporting Only ∆VBESensing||2.5|°C|
|T1_TUE|Internal TSNS TUE|VRUN_n_= 0.0, fSYNC= 0kHz(Note 7)||±1|°C|
|tCONVERT|Update Rate|(Note 9)<br>MFR_ADC_CONTROL = 0x04, 0x0c, or 0x08(Notes 9, 14)||90<br>8|ms<br>ms|
|**INTVCCnn_ Regulator/VBIAS**||||||
|VINTVCCnn_|Internal VCCVoltage No Load|6V ≤ SVINnn_≤ 16V|l|5.25<br>5.5<br>5.75|V|
|VLDO_INT|INTVCCLoad Regulation|ICC= 0mA to 20mA, 6V ≤ SVINnn_≤ 16V||0.5<br>±2|%|
|VIN_VBIAS|Input Range for VIN_VBIAS|||4.5<br>16|V|
|RUNP|VBIASEnable|RUNP Rising||0.8<br>0.85|V|
|VBIAS|5.5V Internal Regulator|7V ≤ VIN_VBIAS≤ 16V, VSVINnn_> 7V||5.25<br>5.5<br>5.75|V|
|SVIN_THR|VSVINnn_Threshold to Enable VBIAS<br>Switchover|SVINnn_Rising||7<br>7.5|V|
|SVIN_THF|VSVINnn_Threshold to Disable VBIAS<br>Switchover|SVINnn_Falling||6.5|V|
|**VDD33****__nn_ Regulator**||||||
|VVDD33_nn_|Internal VDD33Voltage|VINTVCC__nn_> 4.5V||3.2<br>3.3<br>3.4|V|
|ILIM|VDD33Current Limit|VDD33__nn_= GND, VIN__nn_= INTVCC__nn_= 4.5V||100|mA|
|VVDD33_OV|VDD33Overvoltage Threshold|(Note 14)||3.5|V|
|VVDD33_UV|VDD33Undervoltage Threshold|(Note 14)||3.1|V|
Rev. 0
8
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LTM4682
## **ELECTRICAL CHARACTERISTICS**
**The** l **denotes the specifications which apply over the specified internal operating temperature range (Note 2). Specified as each individual output channel (Note 4). TA = 25°C, VIN = 12V, RUN** _**n**_ **= 3.3V, RUNP = 12V, FREQUENCY_SWITCH = 575kHz and VOUT** _**n**_ **commanded to 0.75V unless otherwise noted. Configured with factory-default EEPROM settings and per Test Circuit 1, unless otherwise noted.**
|**SYMBOL**|**PARAMETER**|**CONDITIONS**||**MIN**|**TYP**|**MAX**|**UNITS**|
|---|---|---|---|---|---|---|---|
|**VDD25nn_ Regulator**||||||||
|VVDD25_nn_|Internal VDD25Voltage||||2.5||V|
|ILIM|VDD25Current Limit|VDD25__nn_= GND, VIN__nn_= INTVCC__nn_= 4.5V|||80||mA|
|**Oscillator and Phase-Locked Loop (PLL)**||||||||
|fRANGE|PLL SYNC Range|Synchronized with Falling Edge of SYNC||250||1000|kHz|
|fOSC|Oscillator Frequency Accuracy|Frequency Switch = 250kHz to 1000kHz(Note 14)|l|||±7.5|%|
|VTH(SYNCnn_)|SYNC Input Threshold (Note 14)|VSYNCFalling<br>VSYNCRising|||1<br>1.5||V<br>V|
|VOL(SYNCnn_)|SYNC Low Output Voltage|ILOAD= 3mA(Note 14)|||0.2|0.4|V|
|ILEAK(SYNCnn_)|SYNC Leakage Current in Subordinate<br>Mode|0V ≤ VSYNCnn_≤ 3.6V||||±5|µA|
|θSYNC-θ0, -θ2|SYNC to Ch0, Ch2 Phase|MFR_PWM_CONFIG[2:0] = 0,2,3|||0||Deg|
||Relationship Based on the Falling|MFR_PWM_CONFIG[2:0] = 5|||60||Deg|
||Edge of Sync and Rising Edge of|MFR_PWM_CONFIG[2:0] = 1|||90||Deg|
||SW0, SW2|MFR_PWM_CONFIG[2:0]= 4,6|||120||Deg|
|θSYNC-θ1, -θ3|SYNC to Ch1, Ch3 Phase|MFR_PWM_CONFIG[2:0] = 3|||120||Deg|
||Relationship Based on the Falling|MFR_PWM_CONFIG[2:0] = 0|||180||Deg|
||Edge of Sync and Rising Edge of|MFR_PWM_CONFIG[2:0] = 2,4,5|||240||Deg|
||SW1, SW3|MFR_PWM_CONFIG[2:0] = 1|||270||Deg|
|||MFR_PWM_CONFIG[2:0]= 6|||300||Deg|
|**EEPROM Characteristics**||||||||
|Endurance|(Note 15)|0°C ≤ TJ≤ 85°C During EEPROM Write Operations|l|10,000|||Cycles|
|Retention|(Note 15)|TJ< 125°C|l|10|||Years|
|Mass_Write|Mass Write Operation Time|STORE_USER_ALL, 0°C < TJ< 85°C|||440|4100|ms|
|||During EEPROM Write Operation||||||
|**Leakage Current SDAnn_, SCLnn_, ALERTnn_, RUN****_n_**||||||||
|IOL|Input Leakage Current|OV ≤ VPIN≤ 5.5V|l|||±5|µA|
|**Leakage CurrentFAULT****_n_, PGOOD****_n_**||||||||
|IGL|Input Leakage Current|OV ≤ VPIN≤ 3.6V|l|||±2|µA|
|**Digital Inputs SCLnn_, SDAnn_, RUN****_n_**||||||||
|VIH|Input High Threshold Voltage||l|||1.35|V|
|VIL|Input Low Threshold Voltage||l|0.8|||V|
|VHYST|Input Hysteresis|SCL, SDA|||0.08||V|
|CPIN|Input Capacitance|||||10|pF|
|**Digital Input WPnn_(Note 14) (Note 14)**||||||||
|IPUWP|Input Pull-Up Current|WP|||10||µA|
|**Open-Drain Outputs SCLnn_, SDAnn_, FAULT****_n_, ALERTnn_, RUN****_n_, SHARE_CLKnn_, PGOOD****_n_**||||||||
|VOL|Output Low Voltage|ISINK= 3mA||||0.4|V|
|**Digital Inputs SHARE_CLKnn_, WPnn_(Note 14)**||||||||
|VIH|Input High Threshold Voltage||l||1.5|1.8|V|
|VIL|Input Low Threshold Voltage||l|0.6|1||V|
Rev. 0
9
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## LTM4682
## **ELECTRICAL CHARACTERISTICS**
**The** l **denotes the specifications which apply over the specified internal operating temperature range (Note 2). Specified as each individual output channel (Note 4). TA = 25°C, VIN = 12V, RUN** _**n**_ **= 3.3V, RUNP = 12V, FREQUENCY_SWITCH = 575kHz and VOUT** _**n**_ **commanded to 0.75V unless otherwise noted. Configured with factory-default EEPROM settings and per Test Circuit 1, unless otherwise noted.**
|**SYMBOL**|**PARAMETER**|**CONDITIONS**|**CONDITIONS**|**MIN**<br>**TYP**<br>**MAX**|**UNITS**|
|---|---|---|---|---|---|
|**Digital Filtering ofFAULT****_n_(Note 14)**||||||
|IFLTG|Input Digital FilteringFAULT_n_|||3|µs|
|**Digital Filtering of PGOOD****_n_(Note 14)**||||||
|IFLTG|Output Digital Filtering PGOOD_n_|||100|µs|
|**Digital Filtering of RUN****_n_(Note 14)**||||||
|IFLTG|Input Digital Filtering RUN|||10|µs|
|**PMBus Interface Timing Characteristics (Note 14)**||||||
|fSCL|Serial Bus Operating Frequency||l|10<br>400|kHz|
|tBUF|Bus Free Time Between Stop and<br>Start||l|1.3|µs|
|tHD(STA)|Hold Time After Repeated Start<br>Condition After This Period, the First<br>Clock is Generated||l|0.6|µs|
|tSU(STA)|Repeated Start Condition Setup Time||l|0.6<br>10000|µs|
|tSU(ST0)|Stop Condition Setup Time||l|0.6|µs|
|tHD(DAT)|Date Hold Time<br>Receiving Data<br>Transmitting Data||l<br>l|0<br>0.3<br>0.9|µs<br>µs|
|tSU(DAT)|Data Setup Time<br>Receiving Data|||0.1|µs|
|tTIMEOUT_SMB|Stuck PMBus Timer Non-Block Reads<br>Stuck PMBus Timer Block Reads|Measured from the Last PMBus Start Event||32<br>255|ms|
|tLOW|Serial Clock Low Period||l|1.3<br>10000|µs|
|tHIGH|Serial Clock High Period||l|0.6|µs|
**Note 1:** Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime.
**Note 2:** The LTM4682 is tested under pulsed-load conditions such that TJ ≈ TA. The LTM4682E is guaranteed to meet performance specifications over the 0°C to 125°C internal operating temperature range. Specifications over the –40°C to 125°C internal operating temperature range are assured by design, characterization and correlation with statistical process controls. The LTM4682I is guaranteed to meet specifications over the full –40°C to 125°C internal operating temperature range. The TJ is calculated from the ambient temperature TA and the power dissipation PD according to the formula:
TJ **=** TA + (PD **•** θ JA)
Note that the maximum ambient temperature consistent with these specifications is determined by specific operating conditions in conjunction with the board layout, the rated package thermal resistance, and other environmental factors.
**Note 3:** All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to ground unless otherwise specified.
**Note 4:** The two power inputs—VIN01 and VIN23—and their respective power outputs—VOUT0,1 and VOUT2,3—are tested independently in production. A shorthand notation is used in this document that allows these parameters to be referred to by VIN _nn_ and VOUT _n_ , where _n_ is permitted to take on a value of 0 to 3. This italicized _n_ notation and convention is extended to encompass all such pin names, as well as register names with channel-specific, i.e., paged data. For example, VOUT_COMMAND _n_ refers to the VOUT_COMMAND command code data located in Pages 0 and 1, which in turn relate to Channel 0,2 (VOUT0,2) and Channel 1,3 (VOUT1,3). Registers containing non-page-specific data, i.e., whose data is global to the module, or applies to all of the module’s channels lack the italicized _n_ , e.g., FREQUENCY_SWITCH.
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LTM4682
## **ELECTRICAL CHARACTERISTICS**
**Note 5:** VOUT _n_ (DC) and line and load regulation tests are performed in production with digital servo disengaged (MFR_PWM_MODE _n_ [6] = 0b), and low VOUT _n_ range selected MFR_PWM_MODE _n_ [1] = 1b. The digital servo control loop is exercised in production (setting MFR_PWM_ MODE _n_ [6] = 1b). However, the convergence of the output voltage to its final settling value is not necessarily observed in the final test—due to potentially long-time constants involved—and is instead guaranteed by the output voltage readback accuracy specification. Evaluation in application demonstrates capability; see the Typical Performance Characteristics section.
**Note 6:** See the Thermal Considerations and Output Current Derating section for VIN, VOUT, and TA, located in the Applications Information section.
**Note 7:** Part tested with PWM disabled. Evaluation in application demonstrates capability. The TUE(%) = ADC Gain Error (%) + 100 (zerocode offset + ADC Linearity Error)/Actual Value.
**Note 8:** Minimum on-time is tested at wafer sort.
**Note 9:** The data conversion is done by default in a round-robin fashion. All input signals are continuously converted for a typical latency of 90ms. Setting MFR_ADC_CONTRL value to be 0 to 12, LTM4682 can do fast data conversion with only 8ms to 10ms. See the PMBus Command Summary section for details.
**Note 10:** The following telemetry parameters are formatted in PMBusdefined Linear Data Format, in which each register contains a word comprised of 5 most significant bits—representing a signed exponent, to be raised to the power of 2—and 11 least significant bits—representing a signed mantissa: input voltage (on SVIN nn_ ), accessed through the READ_VIN command code; output currents (IOUT _n_ ), accessed through the READ_IOUT _n_ command codes; module input current (IVIN nn_ + IVIN nn_ + ISVIN nn_ ), accessed through the READ_IIN command code; channel input currents (IVIN nn_ + 1/2 • ISVIN nn_ ), accessed through the MFR_READ_IIN _n_ command codes; and duty cycles of Channel 0 and Channel 1 switching power stages, accessed through the READ_DUTY_CYCLE _n_ command codes. This data format limits the resolution of telemetry readback data to 10 bits even though the internal ADC is 16 bits and the LTM4682’s internal calculations use 32-bit words.
**Note 11:** The absolute maximum rating for the SVIN nn_ pin is 18V. The input voltage telemetry (READ_VIN) is obtained by digitizing a voltage scaled down from the SVIN nn_ pin.
**Note 13:** Channel 0 to Channel 3 OV/UV comparator threshold accuracy for 0.7V to 1.35V are 3%.
**Note 14:** Tested at IC-level ATE.
**Note 15:** The LTM4682’s EEPROM temperature range for valid write commands is 0°C to 85°C. To achieve guaranteed EEPROM data retention, execution of the STORE_USER_ALL command—i.e., uploading RAM contents to NVM—outside this temperature range is not recommended. However, as long as the LTM4682’s EEPROM temperature is less than 130°C, the LTM4682 will obey the STORE_USER_ALL command. Only when EEPROM temperature exceeds 130°C, the LTM4682 will not act on any STORE_USER_ALL transactions; instead, the LTM4682 NACKs the serial command and asserts its relevant CML (communications, memory, logic) fault bits. The EEPROM temperature can be queried before commanding STORE_USER_ALL; see the Applications Information section.
**Note 16:** The LTM4682 includes overtemperature protection that is intended to protect the device during momentary overload conditions. The junction temperature will exceed 125°C when overtemperature protection is active. Continuous operation above the specified maximum operating junction temperature may impair device reliability.
**==> picture [162 x 162] intentionally omitted <==**
**----- Start of picture text -----**<br>
62<br>56<br>50<br>43<br>37<br>31<br>25<br>19<br>12<br>6<br>0<br>0 5 10 15 20 25 30 35<br>CODE<br>4682 F01<br> (kΩ)<br>n<br>COMP<br>R<br>**----- End of picture text -----**<br>
**Figure 1. Programmable RCOMP** _**n**_
**Note 12:** These typical parameters are based on bench measurements and are not production tested.
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LTM4682
## **TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, unless otherwise noted.**
**Single Channel Efficiency, 5VIN, VIN = SVIN = INTVCC = 5V, RUNP = 0V, Continuous-Conduction Mode**
**==> picture [161 x 399] intentionally omitted <==**
**----- Start of picture text -----**<br>
100<br>95<br>90<br>85<br>80<br>75<br>5VIN, 0.75VOUT, 575kHz<br>70 5V IN , 0.9V OUT , 650kHz<br>5VIN, 1.0VOUT, 650kHz<br>65 5V IN , 1.2V OUT , 650kHz<br>5VIN, 1.35VOUT, 750kHz<br>60<br>0 5 10 15 20 25 30 35<br>LOAD CURRENT (A)<br>4682 G01<br>Single Channel Efficiency, 12VIN, IN, ,<br>VIN = SVIN = VIN_VBIAS = RUNP = 12V, IN = SVIN = VIN_VBIAS = RUNP = 12V, = SVIN = VIN_VBIAS = RUNP = 12V, IN = VIN_VBIAS = RUNP = 12V, = VIN_VBIAS = RUNP = 12V, IN_VBIAS = RUNP = 12V, = RUNP = 12V,<br>Continuous-Conduction Mode<br>100<br>95<br>90<br>85<br>80<br>75<br>12VIN, 0.75VOUT, 575kHz<br>70 12V IN , 0.9V OUT , 650kHz<br>12VIN, 1.0VOUT, 650kHz<br>65 12V IN , 1.2V OUT , 650kHz<br>12VIN, 1.35VOUT, 750kHz<br>60<br>0 5 10 15 20 25 30 35<br>LOAD CURRENT (A)<br>4682 G03<br>EFFICIENCY (%)<br>EFFICIENCY (%)<br>**----- End of picture text -----**<br>
**Single Channel Efficiency, 12VIN, IN, , VIN = SVIN = VIN_VBIAS = RUNP = 12V, IN = SVIN = VIN_VBIAS = RUNP = 12V, = SVIN = VIN_VBIAS = RUNP = 12V, IN = VIN_VBIAS = RUNP = 12V, = VIN_VBIAS = RUNP = 12V, IN_VBIAS = RUNP = 12V, = RUNP = 12V, Continuous-Conduction Mode**
**Single Channel Efficiency, 8VIN, VIN = SVIN = VIN_VBIAS = 8V, RUNP = 8V, Continuous-Conduction Mode**
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**----- Start of picture text -----**<br>
100<br>95<br>90<br>85<br>80<br>75<br>8VIN, 0.75VOUT, 575kHz<br>70 8V IN , 0.9V OUT , 650kHz<br>8VIN, 1.0VOUT, 650kHz<br>65 8V IN , 1.2V OUT , 650kHz<br>8VIN, 1.35VOUT, 750kHz<br>60<br>0 5 10 15 20 25 30 35<br>LOAD CURRENT (A)<br>4682 G03<br>EFFICIENCY (%)<br>**----- End of picture text -----**<br>
**Quad Channel Single Output Efficiency VIN = SVIN = VIN_VBIAS = RUNP = 12V, Continuous-Conduction Mode**
**==> picture [162 x 160] intentionally omitted <==**
**----- Start of picture text -----**<br>
100<br>95<br>90<br>85<br>80<br>75<br>12VIN, 0.75VOUT, 575kHz<br>70 12V IN , 0.9V OUT , 650kHz<br>12VIN, 1.0VOUT, 650kHz<br>65 12V IN , 1.2V OUT , 650kHz<br>12VIN, 1.35VOUT, 750kHz<br>60<br>0 20 40 60 80 100 120<br>LOAD CURRENT (A)<br>4682 G04<br>EFFICIENCY (%)<br>**----- End of picture text -----**<br>
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LTM4682
## **TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, unless otherwise noted.**
**Single Channel Load Transient Response (0A) to (10A) Load Step, 10A/µs, 12VIN to 0.7VOUT, fSW = 575kHz**
**Single Channel Load Transient Response (0A) to (10A) Load Step, 10A/µs, 12VIN to 0.85VOUT, fSW = 650kHz**
**Single Channel Load Transient Response (0A) to (10A) Load Step, 10A/µs, 12VIN to 1VOUT, fSW = 650kHz**
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VOUT VOUT VOUT<br>20mV/DIV 20mV/DIV 20mV/DIV<br>IOUT IOUT IOUT<br>5A/DIV 5A/DIV 5A/DIV<br>100µs/DIV 4682 G05 100µs/DIV 4682 G06 100µs/DIV 4682 G07<br>FIGURE 48 CIRCUIT FIGURE 48 CIRCUIT<br>CROUTCOMP = 470µF ×3 POSCAP, 100µF ×4 CERAMIC = 15k, EA-gm = 3.02mS FIGURE 48 CIRCUITCOUT = 470µF ×3 POSCAP, 100µF ×4 CERAMIC CROUTCOMP = 470µF ×3 POSCAP, 100µF ×4 CERAMIC = 15k, EA-gm = 3.02mS<br>COMPna = 2.2nF, COMPnb = 150pF RCOMP = 15k, EA-gm = 3.02mS COMPna = 2.2nF, COMPnb = 150pF<br>ILIM RANGE HIGH, VOUT RANGE LOW COMPna = 2.2nF, COMPnb = 150pF ILIM RANGE HIGH, VOUT RANGE LOW<br>ILIM RANGE HIGH, VOUT RANGE LOW<br>**----- End of picture text -----**<br>
**Single Channel Load Transient Response (0A) to (10A) Load Step, 10A/µs, 12VIN to 1.2VOUT, fSW = 650kHz**
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VOUT<br>20mV/DIV<br>IOUT<br>5A/DIV<br>100µs/DIV 4682 G08<br>FIGURE 48 CIRCUIT<br>COUT = 470µF ×3 POSCAP, 100µF ×4 CERAMIC<br>RCOMP = 15k, EA-gm = 3.02mS<br>COMPna = 2.2nF, COMPnb = 150pF<br>ILIM RANGE HIGH, VOUT RANGE LOW<br>**----- End of picture text -----**<br>
**Single Channel Load Transient Response (0A) to (10A) Load Step, 10A/µs, 12VIN to 1.35VOUT, fSW = 750kHz**
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VOUT<br>20mV/DIV<br>IOUT<br>5A/DIV<br>100µs/DIV 4682 G09<br>FIGURE 48 CIRCUIT<br>COUT = 470µF ×3 POSCAP, 100µF ×4 CERAMIC<br>RCOMP = 15k, EA-gm = 3.02mS<br>COMPna = 2.2nF, COMPnb = 150pF<br>ILIM RANGE HIGH, VOUT RANGE LOW<br>**----- End of picture text -----**<br>
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LTM4682
## **TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, unless otherwise noted.**
## **Quad Output Concurrent Rail, Start-Up, Prebias**
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VOUT3 = 1.35V<br>V OUT2 = 1V<br>V OUT1 = 0.85V<br>VOUT0 = 0.7V<br>250mV/DIV<br>5ms/DIV 4682 G10<br>FIGURE 48 CIRCUIT, 12VIN, 30A ON VOUT0<br>NO LOAD ON OTHER OUTPUTS AND 400mV<br>PREBIAS ON VOUT1<br>Single Phase Single Output<br>12V to 0.75V, No Load Short-<br>Circuit Protection<br>VOUT, 0.75V<br>500mV/DIV<br>IIN<br>2A/DIV<br>200µs/DIV 4682 G12<br>FIGURE 48 CIRCUIT, 12VIN, NO LOAD ON<br>VOUT0 PRIOR TO APPLICATION OF SHORT-<br>CIRCUIT USE OF HIGH RANGE OF ILIMIT<br>SYSTEM SHORT-CIRCUIT USING LOW<br>IMPEDANCE COPPER ACROSS OUTPUT<br>(HARD SHORT)<br>**----- End of picture text -----**<br>
**Quad Output Concurrent Rail, Shutdown, Prebias**
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**----- Start of picture text -----**<br>
VOUT3 = 1.35V<br>V OUT2 = 1V<br>V OUT1 = 0.85V<br>VOUT0 = 0.7V<br>250mV/DIV<br>5ms/DIV 4682 G11<br>FIGURE 48 CIRCUIT, 12VIN, 30A ON VOUT0<br>NO LOAD ON OTHER OUTPUTS AND 400mV<br>PREBIAS ON VOUT1<br>Single Phase Single Output<br>12V to 0.75V, 31.25A Load Short-<br>Circuit Protection<br>VOUT0, 0.75V<br>500mV/DIV<br>IIN<br>2A/DIV<br>200µs/DIV 4682 G13<br>FIGURE 48 CIRCUIT, 12VIN, 31.25A LOAD ON<br>VOUT0 PRIOR TO APPLICATION OF SHORT-<br>CIRCUIT USE OF HIGH RANGE OF ILIMIT<br>SYSTEM SHORT-CIRCUIT USING LOW<br>IMPEDANCE COPPER ACROSS OUTPUT<br>(HARD SHORT)<br>**----- End of picture text -----**<br>
## **VIN = SVIN = 12V, VOUT = 0.75V, FREQ = 575kHz, IOUT = 31.25A**
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Rev. 0<br>**----- End of picture text -----**<br>
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LTM4682
## **PIN FUNCTIONS**
**PACKAGE ROW AND COLUMN LABELING MAY VARY AMONG µModule PRODUCTS. REVIEW EACH PACKAGE LAYOUT CAREFULLY.**
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**GND (A1-A4, A7, A12, B1-B4, B7, B12, C3-C4, C7, C12, D3-D4, D7, D12, E3-E4, E7, E12, F1-F4, F7, F12, G3-G4, G7, G12, H3-H4, H7, H12, J3-J4, J7, J12, K1-K4, K7-K12, L1-L15, M1-M15, N1-N4, N7-N8, N12, P3-P4, P7, P12, R3-R4, R7, R12, T3-T4, T7, T12, U1-U4, U7, U12, V3-V4, V7, V12, W3-W4, W7, W12, Y3-Y4, Y7, Y12, AA1-AA4, AA7, AA12, AB1-AB4, AB7, AB12):** Power Ground of the LTM4682. Power return for VIN01 VIN23 VOUT0,1 and VOUT2,3. Return input and output capacitors to this point.
**VIN01 (A5-A6, B5-B6, C5-C6, D5-D6, E5-E6, F5-F6, G5-G6, H5-H6, J5-J6, K5-K6):** Positive Power Input to Channels 0 and 1 Switching Stages. Provide sufficient decoupling capacitance in the form of multilayer ceramic capacitors (MLCCs) and low ESR electrolytic (or equivalent) to handle reflected input current ripple from the stepdown switching stage. The MLCCs capacitors should be placed as close to the LTM4682 as physically possible. See the Layout Checklist/Example section in the Applications Information section.
**VOUT0_CFG (A8):** Output Voltage Select Pin for VOUT0, Coarse Setting. If the VOUT0_CFG and VTRIM0_CFG pins are both left open—or, if the LTM4682 is configured to ignore pin-strap (RCONFIG) resistors, i.e., MFR_CONFIG_ ALL[6] = 1b—then the LTM4682s target VOUT0 output voltage setting (VOUT_COMMAND0) and associated power-good and OV/UV warning and fault thresholds are dictated at SVIN_01 power-up according to the LTM4682’s nonvolatile (NVM) contents. A resistor divider connected to 2.5V and to SGND (see Table 1)—in combination with resistor pin settings on VTRIM0_CFG, and using the factory-default NVM setting of MFR_CONFIG_ALL[6] = 0b—can be used to configure the LTM4682’s Channel 0 output to power-up to a VOUT_COMMAND value (and associated output voltage monitoring and protection/ fault-detection thresholds) different from those of NVM contents. (See the Applications Information section.) Connecting resistor(s) from VOUT0_CFG to SGND and, or VTRIM0_CFG to SGND allows a convenient way to
configure multiple LTM4682s with identical NVM contents for different output voltage settings all without graphical user interface (GUI) intervention or the need to custom-preprogram module NVM contents. Minimize capacitance especially when the pin is left open, to ensure accurate detection of the pin state. Note that the use of RCONFIGs on VOUT0_CFG/VTRIM0_CFG can affect the VOUT0 range setting (MFR_PWM_MODE0[1]) and loop gain. For addressed ASEL_01, Page 0x00 corresponds to Channel 0 and Page 0x01 corresponds to Channel 1. See PAGE description section.
**FSWPH_01_CFG (A9):** Switching Frequency, Channel Phase-Interleaving Angle and Phase Relationship to SYNC Configuration Pin for Channels 0 and 1. If this pin is left open—or, if the LTM4682 is configured to ignore pinstrap (RCONFIG) resistors, i.e., MFR_CONFIG_ALL[6] = 1b—then LTM4682’s switching frequency (FREQUENCY_ SWITCH) and channel phase relationships (with respect to the SYNC clock; MFR_PWM_CONFIG[2:0]) are dictated at SVIN_01 power-up according to the LTM4682’s NVM contents for Channels 0 and 1. Default factory values are: 575kHz operation; Channel 0 at 0°; and Channel 1 at 180°C (convention throughout this document: a phase angle of 0° means the channel’s switch node rises coincident with the falling edge of the SYNC pulse). Connecting a resistor divider from 2.5V to SGND (and using the factorydefault NVM setting of MFR_CONFIG_ALL[6] = 0b) allows a convenient way to configure multiple LTM4682s with identical NVM contents for different switching frequencies of operation and phase interleaving angle settings of intra- and extra-module-paralleled channels—all, without GUI intervention or the need to custom pre-program module NVM contents. See the Applications Information section. Minimize capacitance—especially when the pin is left open—to ensure accurate detection of the pin state.
**FAULT0, FAULT1, FAULT2, FAULT3 (A11, A10, V10, W10):** Digital Programmable FAULT Inputs and Outputs. Open-drain output. A pull-up resistor to 3.3V is required in the application.
**VOUT0 (A13-A15, B13-B15, C13-C15, D13-D15, E13E15):** Channel 0 Output Voltage. Place the recommended
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LTM4682
## **PIN FUNCTIONS**
output capacitors from this shape to GND. See the Layout Checklist/Example section.
**VOUT2_CFG (AA8):** Output Voltage Select Pin for VOUT2, Coarse Setting. If the VOUT2_CFG and VTRIM2_CFG pins are both left open—or, if the LTM4682 is configured to ignore pin-strap (RCONFIG) resistors, i.e., MFR_CONFIG_ ALL[6] = 1b—then the LTM4682s target VOUT2 output voltage setting (VOUT_COMMAND2) and associated power-good and OV/UV warning and fault thresholds are dictated at SVIN_23 power-up according to the LTM4682’s NVM contents. A resistor divider connected to 2.5V and to SGND to this pin—in combination with resistor pin settings on VTRIM2_CFG, and using the factory-default NVM setting of MFR_CONFIG_ALL[6] = 0b—can be used to configure the LTM4682’s Channel 2 output to power-up to a VOUT_COMMAND value (and associated output voltage monitoring and protection/fault-detection thresholds) different from those of NVM contents. See the Applications Information section. Connecting resistor(s) from VOUT2_CFG to SGND and/or VTRIM2_CFG to SGND in this manner allows a convenient way to configure multiple LTM4682s with identical NVM contents for different output voltage settings all without GUI intervention or the need to custom-preprogram module NVM contents. Minimize capacitance especially when the pin is left open to ensure accurate detection of the pin state. Note that the use of RCONFIGs on VOUT2_CFG/VTRIM2_CFG can affect the VOUT2 range setting (MFR_PWM_MODE0[1]) and loop gain. For addressed ASEL_23, Page 0x00 corresponds to Channel 2 and Page 0x01 corresponds to Channel 3. See PAGE description section.
**FSWPH_23_CFG (AA9):** Switching Frequency, Channel Phase-Interleaving Angle and Phase Relationship to SYNC Configuration Pin for Channels 2 and 3. If this pin is left open—or, if the LTM4682 is configured to ignore pinstrap (RCONFIG) resistors, i.e., MFR_CONFIG_ALL[6] = 1b—then LTM4682’s switching frequency (FREQUENCY_ SWITCH) and channel phase relationships (with respect to the SYNC clock; MFR_PWM_CONFIG[2:0]) are dictated at SVIN_23 power-up according to the LTM4682’s NVM contents for Channels 2 and 3. Default factory values are 575kHz operation; Channel 2 at 0°; and Channel 3 at
180°C (convention throughout this document: a phase angle of 0° means the channel’s switch node rises coincident with the falling edge of the SYNC pulse). Connecting a resistor divider from 2.5V to SGND (and using the factorydefault NVM setting of MFR_CONFIG_ALL[6] = 0b) allows a convenient way to configure multiple LTM4682s with identical NVM contents for different switching frequencies of operation and phase interleaving angle settings of intra- and extra-module-paralleled channels—all, without GUI intervention or the need to custom pre-program module NVM contents. See the Applications Information section. Minimize capacitance, especially, when the pin is left open, to ensure accurate detection of the pin state.
**ASEL_23 (AA10):** Serial Bus Address Configuration Pin for Channels 2 and 3 Controller. On any given I[2] C/SMBus serial bus segment, every device must have its unique subordinate address. If this pin is left open, the LTM4682 powers up to its default subordinate address of 0x4F (hexadecimal), i.e., 1001111b (industry-standard convention is used throughout this document: 7-bit subordinate addressing). The lower 4 bits of the LTM4682’s subordinate address can be altered from this default value by connecting a resistor from this pin to SGND. Minimize capacitance—especially when the pin is left open—to ensure accurate detection of the pin state. It is recommended to use a resistor to set the address. The ASEL_23 address will be used to address Channels 2 and 3, and a different ASEL_01 address will be used to address Channels 0 and 1. For addressed ASEL_23, Page 0x00 corresponds to Channel 2 and Page 0x01 corresponds to Channel 3. See PAGE description section. The GUI will represent Channel 2 as U1:B0 and Channel 3 as U1:B1. See the LTpowerPlay Screen Shot (Figure 31).
**VOUT3_CFG (AB8):** Output Voltage Select Pin for VOUT3, Coarse Setting. If the VOUT3_CFG and VTRIM3_CFG pins are both left open—or, if the LTM4682 is configured to ignore pin-strap (RCONFIG) resistors, i.e., MFR_CONFIG_ ALL[6] = 1b, then the LTM4682s target VOUT3 output voltage setting (VOUT_COMMAND3) and associated power-good and OV/UV warning and fault thresholds are dictated at SVIN_23 power-up according to the LTM4682’s NVM contents. A resistor divider connected to 2.5V and
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LTM4682
## **PIN FUNCTIONS**
to SGND to this pin—in combination with resistor pin settings on VTRIM3_CFG, and using the factory-default NVM setting of MFR_CONFIG_ALL[6] = 0b—can be used to configure the LTM4682’s Channel 3 output to power-up to a VOUT_COMMAND value (and associated output voltage monitoring and protection/fault-detection thresholds) different from those of NVM contents. See the Applications Information section. Connecting resistor(s) from VOUT3_CFG to SGND and/or VTRIM3_CFG to SGND in this manner allows a convenient way to configure multiple LTM4682s with identical NVM contents for different output voltage settings all without GUI intervention or the need to custom-preprogram module NVM contents. Minimize capacitance especially when the pin is left open to ensure accurate detection of the pin state. Note that the use of RCONFIGs on VOUT3_CFG/VTRIM3_CFG can affect the VOUT3 range setting (MFR_PWM_MODE1[1]) and loop gain. For addressed ASEL_23, Page 0x00 corresponds to Channel 2 and Page 0x01 corresponds to Channel 3. See PAGE description section.
**VTRIM3_CFG (AB9):** Output Voltage Select Pin for VOUT3, Fine Setting. Works in combination with VOUT3_CFG to affect the VOUT_COMMAND (and associated output voltage monitoring and protection/fault-detection thresholds) of Channel 3, at SVIN_23 power-up. See VOUT3_CFG and the Applications Information section. A resistor divider from 2.5V to SGND connected to the pin will set the TRIM value (see Table 2). Minimize capacitance especially when the pin is left open to ensure accurate detection of the pin state. Note that the use of RCONFIGs on VOUT3_CFG/ VTRIM3_CFG can affect the VOUT3 range setting (MFR_ PWM_MODE0[1]) and loop gain. For addressed ASEL_23, Page 0x00 corresponds to Channel 2 and Page 0x01 corresponds to Channel 3. See PAGE description section.
**VTRIM2_CFG (AB10):** Output Voltage Select Pin for VOUT2, Fine Setting. Works in combination with VOUT2_CFG to affect the VOUT_COMMAND (and associated output voltage monitoring and protection/fault-detection thresholds) of Channel 2, at SVIN_23 power-up. See VOUT2_CFG and the Applications Information section. A resistor divider from 2.5V to SGND connected to the pin will set the TRIM value. See Table 2. Minimize capacitance especially when
the pin is left open to ensure accurate detection of the pin state. Note that the use of RCONFIGs on VOUT2_CFG/ VTRIM2_CFG can affect the VOUT2 range setting (MFR_ PWM_MODE0[1]) and loop gain. For addressed ASEL_23, Page 0x00 corresponds to Channel 2 and Page 0x01 corresponds to Channel 3. See PAGE description section.
**VDD25_23 (AB11):** Internally Generated 2.5V Power Supply Output Pin for Channels 2 and 3 Circuits. Do not load this pin with external current. This pin is used strictly to bias internal logic and provides current for the internal pull-up resistors connected to the configuration-programming pins. No external decoupling is required.
**VOUT1_CFG (B8):** Output Voltage Select Pin for VOUT1, Coarse Setting. If the VOUT1_CFG and VTRIM1_CFG pins are both left open—or, if the LTM4682 is configured to ignore pin-strap (RCONFIG) resistors, i.e., MFR_CONFIG_ALL[6] = 1b—then the LTM4682s target VOUT1 output voltage setting (VOUT_COMMAND1) and associated power-good and OV/UV warning and fault thresholds are dictated at SVIN_01 power-up according to the LTM4682’s NVM contents. A resistor divider connected to 2.5V and to SGND to this pin— in combination with resistor pin settings on VTRIM1_CFG, and using the factory-default NVM setting of MFR_CONFIG_ ALL[6] = 0b—can be used to configure the LTM4682’s Channel 1 output to power-up to a VOUT_COMMAND value (and associated output voltage monitoring and protection/ fault-detection thresholds) different from those of NVM contents. See the Applications Information section. Connecting resistor(s) from VOUT1_CFG to SGND and/or VTRIM1_CFG to SGND in this manner allows a convenient way to configure multiple LTM4682s with identical NVM contents for different output voltage settings all without GUI intervention or the need to custom-preprogram module NVM contents. Minimize capacitance especially when the pin is left open to ensure accurate detection of the pin state. Note that the use of RCONFIGs on VOUT1_CFG/VTRIM1_CFG can affect the VOUT1 range setting (MFR_PWM_MODE1[1]) and loop gain. For addressed ASEL_01, Page 0x00 corresponds to Channel 0 and Page 0x01 corresponds to Channel 1. See PAGE description section.
**ASEL_01 (B9):** Serial Bus Address Configuration Pin for Channels 0 and 1 Controller. On any given I[2] C/SMBus
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LTM4682
## **PIN FUNCTIONS**
serial bus segment, every device must have its unique subordinate address. If this pin is left open, the LTM4682 powers up to its default subordinate address of 0x4E (hexadecimal), i.e., 1001110b (industry-standard convention is used throughout this document: 7-bit subordinate addressing). The lower 4 bits of the LTM4682’s subordinate address can be altered from this default value by connecting a resistor from this pin to SGND. Minimize capacitance—especially when the pin is left open—to ensure accurate detection of the pin state. It is recommended to use a resistor to set the address. The ASEL_01 address will be used to address Channels 0 and 1, and a different ASEL_23 address will be used to address Channels 2 and 3. For addressed ASEL_01, Page 0x00 corresponds to Channel 0 and Page 0x01 corresponds to Channel 1. See PAGE description section. The GUI will represent Channel 0 as U0:A0 and Channel 1 as U0:A1. See the LTpowerPlay Screen Shot (Figure 31).
**RUN0, RUN1 (B10, B11 Respectively):** Enable Run Input for Channels 0 and 1, Respectively. Open-drain input and output. The logic high on these pins enables the respective outputs of the LTM4682. These open-drain output pins hold the pin low until the LTM4682 is out of reset and SVIN_01 is detected to exceed VIN_ON. A pull-up resistor to 3.3V is required in the application. The LTM4682 pulls RUN0 and/or RUN1 low, as appropriate, when a global fault and/or channel-specific fault occurs whose fault response is configured to latch off and cease regulation; issuing a CLEAR_FAULTS command through I[2] C or power-cycling SVIN_01 is necessary to restart the module, in such cases. Do not pull RUN logic high with a low impedance source. The INTVCC is active when SVIN_01 is above UVLO. This provides power to the VDD33 and VDD25 to allow programming the EEPROM.
**SW0 (C1-C2, D1-D2, E1-E2):** Switching Node of Channel 0 Step-Down Converter Stage. Used for test purposes or EMI-snubbing. It may be routed a short distance to a local test point to monitor the switching action of Channel 0, if desired, but do not route near any sensitive signals. Otherwise, leave electrically isolated (open).
**VDD25_01 (C8):** Internally Generated 2.5V Power Supply Output Pin for Channels 0 and 1 Circuits. Do not load this
pin with external current; it is used strictly to bias internal logic and provides current for the internal pull-up resistors connected to the configuration-programming pins. No external decoupling is required.
**VTRIM1_CFG (C9):** Output Voltage Select Pin for VOUT1, Fine Setting. Works in combination with VOUT1_CFG to affect the VOUT_COMMAND (and associated output voltage monitoring and protection/fault-detection thresholds) of Channel 1, at SVIN_01 power-up. See VOUT1_CFG and the Applications Information section. A resistor divider from 2.5V to SGND connected to the pin will set the TRIM value. See Table 2. Minimize capacitance especially when the pin is left open to ensure accurate detection of the pin state. Note that the use of RCONFIGs on VOUT1_CFG/ VTRIM1_CFG can affect the VOUT1 range setting (MFR_ PWM_MODE1[1]) and loop gain. For addressed ASEL_01, Page 0x00 corresponds to Channel 0 and Page 0x01 corresponds to Channel 1. See PAGE description section.
**SDA_01, SDA_23 (C10, V8):** Serial Bus Data Open-Drain Input and Output. A pull-up resistor to 3.3V is required in the application. The SDA_01 is for Channels 0 and 1, and SDA_23 is for Channels 2 and 3.
**ALERT_01, ALERT_23 (C11, W8):** Open-Drain Digital Output. A pull-up resistor to 3.3V is required in the application only if SMBALERT interrupt detection is implemented in one’s SMBus system.
**SHARE_CLK_01, SHARE_CLK_23 (D8, AA11):** Share Clock, Bidirectional Open-Drain Clock Sharing Pin. Nominally 100kHz. Used for synchronizing the time base between multiple LTM4682s (and any other Analog Devices ICs with a SHARE_CLK pin)—to realize welldefined rail sequencing and rail tracking. Connect the SHARE_CLK pins of all such devices together. All devices with a SHARE_CLK pin will synchronize to the fastest clock. A pull-up resistor to 3.3V is only required when synchronizing the time base between devices.
**VTRIM0_CFG (D9):** Output Voltage Select Pin for VOUT0, Fine Setting. Works in combination with VOUT0_CFG to affect the VOUT_COMMAND (and associated output voltage monitoring and protection/fault-detection thresholds) of Channel 0, at SVIN_01 power-up. See VOUT0_CFG and
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LTM4682
## **PIN FUNCTIONS**
the Applications Information section. A resistor divider from 2.5V to SGND connected to the pin will set the TRIM value. See Table 2. Minimize capacitance especially when the pin is left open to ensure accurate detection of the pin state. Note that the use of RCONFIGs on VOUT0_ CFG/VTRIM0_CFG can affect the VOUT0 range setting (MFR_PWM_MODE0[1]) and loop gain. For addressed ASEL_01, Page 0x00 corresponds to Channel 0 and Page 0x01 corresponds to Channel 1. See PAGE command description section.
**SCL_01, SCL_23 (D10, W9):** Serial Bus Clock Open-Drain Input (Can Be an Input and Output, if Clock Stretching is Enabled). A pull-up resistor to 3.3V is required in the application for digital communication to the SMBus main device(s) that nominally drive this clock. The LTM4682 will never encounter scenarios where it would need to engage clock stretching unless SCL communication speeds exceed 100kHz—and even then, LTM4682 will not clock stretch unless clock stretching is enabled using setting MFR_CONFIG_ALL[1] = 1b. The factory-default NVM configuration setting has MFR_CONFIG_ALL[1] = 0b: clock stretching disabled. If communication on the bus at clock speeds above 100kHz is required, the user’s SMBus main device(s) need to implement clock stretching support to ensure solid serial bus communications, and only then should MFR_CONFIG_ALL[1] be set to 1b. When clock stretching is enabled, SCL becomes a bidirectional, open-drain output pin on the LTM4682.
**SYNC_01, SYNC_23 (D11,V9):** External Clock Synchronization Input and Open-Drain Output Pin. If an external clock is present at this pin, the switching frequency will be synchronized to the external clock. If the main clock mode is enabled, this pin will pull low at the switching frequency with a 500ns pulse to the ground. A resistor pull-up to 3.3V is required in the application if the LTM4682 is the main device.
**VDD33_01 (E8):** Internally Generated 3.3V Power Supply Output Pin for Channels 0 and 1 Circuits. This pin should only be used to provide external current for the pull-up resistors required for FAULT _n_ , SHARE_CLK nn_ , and SYNC nn_ , and may be used to provide external current for
pull-up resistors on RUN _n_ , SDA nn_ , SCL nn_ , ALERT nn_ and PGOOD _n_ . Where _nn_ is either 0,1 or 2,3 channels, and _n_ is the actual channel. No external decoupling is required. VDD33_01 is powered from VBIAS and programming RUN _n_ improves efficiency.
**WP_01, WP_23 (E9, Y11):** Write Protect Pin, Active High. An internal 10µA current source pulls this pin to VDD33. If WP is open circuit or logic high, only I[2] C writes to PAGE, OPERATION, CLEAR_FAULTS, MFR_CLEAR_PEAKS and MFR_EE_UNLOCK are supported. Additionally, Individual faults can be cleared by writing 1b’s to bits of interest in registers prefixed with STATUS. If WP is low, I[2] C writes are unrestricted. VOSNS0[–] (H11): Channel 0 negative differential voltage sense input. See VOSNS0[+] .
**TSNS0, TSNS1, TSNS2, TSNS3 (E11, E10, U8, U9):** Power Stage Temperature Monitors for the 4 Channels. See the Applications Information section.
**VOSNS1[–] (F8):** Channel 1 Negative Differential Voltage Sense Input. See VOSNS1[+] .
**SGND01, SGND23 (F10-F11, U10-U11):** SGND is the signal ground return path of the LTM4682 internal controllers. SGND is not internally connected to GND. Connect SGND to GND local to the LTM4682. See the Layout Checklist/Example section.
**VOUT1 (F13-F15, G13-G15, H13-H15, J13-J15, K13K15):** Channel 1 Output Voltage. Place the recommended output capacitors from this shape to GND. See the Layout Checklist/Example section.
**SW1 (G1-G2, H1-H2, J1-J2):** Switching Node of Channel 1 Step-Down Converter Stage. Used for test purposes or EMI-snubbing. It may be routed a short distance to a local test point to monitor the switching action of Channel 1, if desired, but do not route near any sensitive signals. Otherwise, leave it open.
**VOSNS1[+] (G8):** Channel 1 Positive Differential Voltage Sense Input. Together, VOSNS1[+] and VOSNS1[–] serve to Kelvin-sense the VOUT1 output voltage at VOUT1’s point of load (POL) and provide the differential feedback signal directly to Channel 1’s feedback loop. Command VOUT1’s
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LTM4682
## **PIN FUNCTIONS**
target regulation voltage by serial bus. Its initial command value at SVIN_01 power-up is dictated by NVM contents (factory default: 0.75V)—or, optionally, may be set by configuration resistors; see VOUT1_CFG, VTRIM1_CFG and the Applications Information section.
**COMP0b, COMP1b, COMP2b, COMP3b (G10, F9, T9, W11):** Current Control Threshold and Error Amplifier Compensation Nodes. Each associated channel’s current comparator tripping threshold increases with its compensation voltage. Each channel has a 22pF to SGND.
**COMP0a, COMP1a, COMP2a, COMP3a (G11, G9, T8, V11):** Loop Compensation Nodes. The internal PWM loop compensation resistors RCOMP _n_ of the LTM4682 can be adjusted using bit[4:0] of the MFR_PWM_COMP command. The transconductance of the LTM4682 PWM error amplifier can be adjusted using bit[7:5] of the MFR_ PWM_COMP command. These two loop compensation parameters can be programmed when the device is in operation. See the Programmable Loop Compensation subsection in the Applications Information section for further details. See Figure 1.
**PGOOD0, PGOOD1, PGOOD2, PGOOD3 (H9, H8, R10, T10):** Power Good Indicator Outputs. The open-drain logic output is pulled to the ground when the output exceeds the UV and OV regulation window. The output is deglitched by an internal 100µs filter. A pull-up resistor to 3.3V is required in the application.
**IIN_01[+] (H10):** Positive Current Sense Amplifier Input. If the input current sense amplifier is not used, this pin must be shorted to the IIN_01[–] and SVIN_01 pin. See the Applications Information section for more details about the input current sensing.
**VOSNS0[–] (H11):** Channel 0 Negative Differential Voltage Sense Input. See VOSNS0[+] .
**SVIN_01 (J8):** Input Supply for LTM4682’s Internal Control IC for Channels 0 and 1. In most applications, SVIN_01 connects to VIN01. SVIN_01 can be operated from an auxiliary supply separate from VIN01 for powering the VIN01 from a lower supply like 6V. The SVIN_01 pin requires 1Ω and 1µF decoupling capacitor to measure the actual control chip current. The 1Ω resistor is used to measure
the actual control chip current. See MFR_READ_ICHIP and MFR_ADC_CONTROL COMMAND section. When operating from 4.5V to 5.75V with no auxiliary bias supply, then the main input supply should connect to SVIN_01 and INTVCC_01. See Test Circuit 2 for an example. In this configuration, the ICHIP current will not be relevant since INTV is connected to SV . CC_01 IN_01
**INTVCC_01 (J9):** Internal Regulator, 5.5V Output. When operating the LTM4682 from 5.75V ≤ SVIN_01 ≤ 16V, an internal LDO generates INTVCC_01 from SVIN_01 to bias internal control circuits and the MOSFET drivers of the LTM4682’s Channels 0 and 1. An external 4.7µF ceramic decoupling capacitor is required. The INTVCC_01 is on regulated regardless of the RUN _n_ pin state. When operating the LTM4682 with 4.5V ≤ SVIN_01 < 5.75V, INTVCC_01 must be electrically shorted to SVIN_01, and the RUNP pin must be pulled to GND. The VBIAS takes over after startup when the input voltage is greater than 7V.
**IIN_01[–] (J10):** Negative Current Sense Amplifier Input. If the input current sense amplifier is not used, this pin must be shorted to the IIN_01[+] and SVIN_01 pin. See the Applications Information section for more details about the input current sensing.
**VOSNS0[+] (J11):** Channel 0 Positive Differential Voltage Sense Input. Together, VOSNS0[+] and VOSNS0[–] serve to Kelvin-sense the VOUT0 output voltage at VOUT0’s point of load (POL) and provide the differential feedback signal directly to Channel 0’s feedback loop. Command VOUT0’s target regulation voltage by serial bus. Its initial command value at SVIN_01 power-up is dictated by NVM contents (factory default: 0.75V)—or, optionally, may be set by configuration resistors; see VOUT0_CFG, VTRIM0_CFG and the Applications Information section.
**VIN23 (N5-N6, P5-P6, R5-R6, T5-T6, U5-U6, V5-V6, W5-W6, Y5-Y6, AA5-AA6, AB5-AB6):** Positive Power Input to Channels 2 and 3 Switching Stages. Provide sufficient decoupling capacitance in the form of MLCCs and low ESR electrolytic (or equivalent) to handle reflected input current ripple from the step-down switching stage. The MLCCs should be placed as close to the LTM4682 as physically possible. See the Layout Checklist/Example section in the Applications Information section.
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LTM4682
## **PIN FUNCTIONS**
**VIN_VBIAS (N9):** Input pin to the internal step down regulator that produces 5.5V (VBIAS pin) to power both internal controllers to reduce power dissipation after power up. Each internal controller has an INTV or INTV CC_01 CC_23 regulator that is powered from SVIN_01 or SVIN_23. To eliminate this power loss through these linear regulators, the VBIAS powers both at very high efficiency.
**VBIAS (N10):** A 5.5V step down output that powers both internal controllers to reduce power loss. It provides a 22µF ceramic bypass capacitor on this pin to GND. SVIN_01 and SVIN_23 must be higher than 7V for this VBIAS to supply the controllers. When the input voltage is between 4.5V to 5.75V, pull the RUNP pin to GND, and connect SVIN_01 and SVIN_23 to INTVCC_01 and INTVCC_23, respectively. Powering up the VBIAS regulator with the SVIN_01 and SVIN_23 greater than 7V will power the INTVCC_01, INTVCC_02, the VDD33_01, VDD33_23, VDD25_01, and VDD25_23 from VBIAS. Otherwise, these sources will get their power from SVIN_01 and SVIN_23. This will allow the programming each internal controller’s EEPROM with the power regulator channels in the off position.
**RUNP (N11):** This pin enables the Internal 5.5V VBIAS step down regulator. Pulling this pin above 0.85V will enable the Internal regulator. The pin is rated to VIN, so connect to VIN to enable, and connect to GND to disable. When the input voltage is between 4.5V to 5.75V, pull the RUNP pin to GND, and connect SVIN_01 and SVIN_23 to INTVCC_01 and INTVCC_23, respectively.
**VOUT2 (N13-N15, P13-P15, R13-R15, T13-T15, U13U15):** Channel 2 Output Voltage. Place the recommended output capacitors from this shape to GND. See the Layout Checklist/Example section.
**SW2 (P1-P2, R1-R2, T1-T2):** Switching Node of Channel 2 Step-Down Converter Stage. Used for test purposes or EMI-snubbing. It may be routed a short distance to a local test point to monitor switching action of Channel 2, if desired, but do not route near any sensitive signals. Otherwise, leave it open.
**VOSNS2[+] (P8):** Channel 2 Positive Differential Voltage Sense Input. Together, VOSNS2[+] and VOSNS2[–] serve to Kelvin-sense the VOUT2 output voltage at VOUT2’s POL and provide the differential feedback signal directly to Channel 2’s feedback loop. Command VOUT2’s target regulation voltage by serial bus. Its initial command value at SVIN_23 power-up is dictated by NVM contents (factory default: 0.75V)—or, optionally, may be set by configuration resistors; see VOUT2_CFG, VTRIM2_CFG and the Applications Information section.
**IIN_23[–] (P9):** Negative Current Sense Amplifier Input. If the input current sense amplifier is not used, this pin must be shorted to the IIN_23[+] and SVIN_23 pin. See the Applications Information section for more details about the input current sensing.
**INTVCC_23 (P10):** Internal Regulator, 5.5V Output. When operating the LTM4682 from 5.75V ≤ SVIN_23 ≤ 16V, an internal LDO generates INTVCC_23 from SVIN_23 to bias internal control circuits and the MOSFET drivers of the LTM4682’s Channels 2 and 3. An external 4.7µF ceramic decoupling i capacitor s required. INTVCC_23 is on regulated regardless of the RUN _n_ pin state. When operating the LTM4682 with 4.5V ≤ SVIN_23 < 5.75V, INTVCC_23 must be electrically shorted to SVIN_23, and the RUNP pin must be pulled to GND. VBIAS takes over after startup when the input voltage is greater than 7V.
**SVIN_23 (P11):** Input Supply for LTM4682’s Internal Control IC for Channels 2 and 3. In most applications, SVIN_23 connects to VIN_23. SVIN_23 can be operated from an auxiliary supply separate from VIN23 for powering the VIN23 from a lower supply like 6V. The SVIN_23 pin requires 1Ω and 1µF decoupling capacitor to measure the actual control chip current. The 1Ω resistor is used to measure the actual control chip current. See MFR_ READ_ICHIP and MFR_ADC_CONTROL COMMAND section. When operating from 4.5V to 5.75V with no auxiliary bias supply, then the main input supply should connect to SVIN_23 and INTVCC_23. See Test Circuit 2 for an example. In this configuration, the ICHIP current will not be relevant since INTV is connected to SV . CC_23 IN_23
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LTM4682
## **PIN FUNCTIONS**
**VOSNS2[–] (R8):** Channel 2 Negative Differential Voltage Sense Input. See VOSNS2[+] .
**IIN_23[+] (R9):** Positive Current Sense Amplifier Input. If the input current sense amplifier is not used, this pin must be shorted to the IIN_23[–] and SVIN_23 pin. See the Applications Information section for more details about the input current sensing.
**VOSNS3[+] (R11):** Channel 3 Positive Differential Voltage Sense Input. Together, VOSNS3[+] and VOSNS3[–] serve to Kelvin-sense the VOUT3 output voltage at VOUT3’s POL and provide the differential feedback signal directly to Channel 3’s feedback loop. Command VOUT3’s target regulation voltage by serial bus. Its initial command value at SVIN_23 power-up is dictated by NVM contents (factory default: 0.75V)—or, optionally, may be set by configuration resistors; see VOUT3_CFG, VTRIM3_CFG and the Applications Information section.
**VOSNS3[–] (T11):** Channel 3 Negative Differential Voltage Sense Input. See VOSNS3[+] .
**SW3 (V1-V2, W1-W2, Y1-Y2):** Switching Node of Channel 3 Step-Down Converter Stage. Used for test purposes or EMI-snubbing. It may be routed a short distance to a local test point to monitor switching action of Channel 3, if desired, but do not route near any sensitive signals. Otherwise, leave it open.
**RUN2, RUN3 (Y9, Y8):** Enable Run Input for Channels 2 and 3, respectively. Open-drain input and output. The logic high on these pins enables the respective outputs of the LTM4682. These open-drain output pins hold the pin low until the LTM4682 is out of reset and SV is detected IN_23 to exceed VIN_ON. A pull-up resistor to 3.3V is required in the application. The LTM4682 pulls RUN2 and/or RUN3 low, as appropriate, when a global fault and/or channelspecific fault occurs whose fault response is configured to latch off and cease regulation; issuing a CLEAR_FAULTS command through I[2] C or power-cycling SVIN_23 is necessary to restart the module, in such cases. Do not pull RUN logic high with a low impedance source. INTVCC is active when SVIN_23 is above UVLO. This provides power to the VDD33 and VDD25 to allow programming the EEPROM.
**VDD33_23 (Y10):** Internally Generated 3.3V Power Supply Output Pin for Channels 2 and 3 Circuits. This pin should only be used to provide external current for the pull-up resistors required for FAULT nn_ , SHARE_CLK nn_ , and SYNC nn_ , and may be used to provide external current for pull-up resistors on RUN _n_ , SDA nn_ , SCL nn_ , ALERT nn_ and PGOOD _n_ . Where _nn_ is either 0,1 or 2,3 channels, and _n_ is the actual channel. No external decoupling is required. VDD33_23 can be powered from VBIAS, such that this controller 2 can be programmed with RUN _n_ low.
**VOUT3 (V13-V15, W13-W15, Y13-Y15, AA13-AA15, AB13-AB15):** Channel 3 Output Voltage. Place the recommended output capacitors from this shape to GND See the Layout Checklist/Example section.
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LTM4682
## **SIMPLIFIED BLOCK DIAGRAM**
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1Ω GUI<br>1µF<br>+ CIN1VIN CIN2 RSENSE 4.7µF 22µF ALL PINS SHOWN IS FUNCTION ×2TO SUPPORT CHANNELS 0 AND 1,AND CHANNELS 2 AND 3. CHANNEL# 0 IDENTITY U0:A0<br>1 U0:A1<br>IN_01 [+] , IN_01 [–] , SVIN_01, VIN01, INTVCC_01, VBIAS VDD33_01, VIN01, 2 U0:B0<br>IN_23 [+] IN_23 [–] SVIN_23 VIN23 INTVCC_23 VDD33_23 VIN23 3 U0:B1<br>0.22µF 0.1µF 2.2µF 0.22µF<br>A = N VBIAS 5.5V VIN_VBIAS VIN<br>INPUT CURRENT/ICHIP (READ_IIN, RUNP<br>MFR_READ_IIN_PEAK TO ANALOG<br>SW0, SW2 READBACK) SW1, SW3<br>VOUT0, VOUT2 ADJ MT MT VOUT1, VOUT3 ADJ<br>TO 1.35V TO 1.35V<br>UP TO 31.25A VOUT0 120nH SVIN_01, SVIN_23 > 7V 120nH VOUT1 UP TO 31.25A<br>COUT2COUT1 GND 2.2µF MB POWER CONTROL ANALOG SECTION MB 2.2µFGND COUT3 COUT4<br>0.01µF DIE TEMP SENSE 0.01µF SGND_01, SGND_23<br>TSNS0 TSNS1<br>IOUT CURRENT SENSE TO ANALOGREADBACK TO ANALOGREADBACK IOUT CURRENT SENSE<br>TSNS0, TSNS2 TEMP MUX TSNS1, TSNS3<br>VOSNS0 [+] , VOSNS2 [+] VOSNS1 [+] , VOSNS3 [+]<br>LOAD CLOAD REMOTE SENSE X1 ALL ANALOG X1 REMOTE SENSE CLOAD LOAD<br>VOSNS0 [–] , VOSNS2 [–] READBACK SIGNALS VOSNS1 [–] , VOSNS3 [–]<br>PROG GM 10:1 MUX + PROG GM<br>COMP0b, COMP2b22pF EA0,2 – EA1,3 22pFCOMP1b, COMP3b<br>CCOMPH COMP0a, COMP2a PROG RCOMP ADC PROG RCOMP COMP1a, COMP3a CCOMPH<br>CCOMPL PGOOD0, PGOOD2 PGOOD1, PGOOD3 CCOMPL<br>SPI SUBORDINATE SYNC_01, SYNC_23 3.3V TOLERANT PULL-UP<br>POWER CONTROL DIGITAL SECTION NOT SHOWN<br>2.5V VDD25_01, VDD25_23<br>SCL_01, SCL_23<br>PULL-UP RESISTORS5V-TOLERANT,NOT SHOWN SDA_01, SDAALERT_01, ALERT_23 _23 ROM SPI MAIN SYNC DRIVER 14.3kEACH PIN 2.2µF<br>ASEL_01, ASEL_23<br>3.3V-TOLERANT, PULL-UP RESISTORS NOT SHOWN WP_01, WP_23 RAM DIGITAL ENGINE 32MHz OSC FSWPH_01_CFG, FSWPH_23_CFGVTRIM0_CFG<br>EXTERNAL RESISTIVE<br>5V-TOLERANT, RUN0, RUN1 EEPROM VTRIM1_CFG DIVIDERS BETWEEN<br>PULL-UP RESISTORSNOT SHOWN RUN2, RUN3 VTRIM2_CFG, VTRIM3_CFG SGND_VDD25_ nnnn ARE AND<br>PULL-UP RESISTORS3.3V-TOLERANT,NOT SHOWN FAULTFAULTSHARE_CLK_01, SHARE_CLK_230,2, FAULT FAULT13 TWO DIFFERENT PSM CONTROLLERS1ST CONTROLLER(PAGE 0X00) = CHANNEL 0(PAGE 0X01) = CHANNEL 1 2ND CONTROLLER(PAGE 0X00) = CHANNEL 2(PAGE 0X01) = CHANNEL 3 VOUT2_CFG, VOUT3_CFGVOUT0_CFGVOUT1_CFG NOT SHOWN. REFER TO TABLES 1, 2 AND 3.<br>4682 F02<br>Figure 2. Simplified LTM4682 Block Diagram of the 1/2 Function<br>DECOUPLING REQUIREMENTS TA = 25°C. Using Figure 2 configuration.<br>SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS<br>CINH External High Frequency Input Capacitor Requirement IOUT0 = 31.25A 100 µF<br>(5.75V ≤ VIN ≤ 16V, VOUT n Commanded to 0.75V). IOUT1 = 31.25A 100 µF<br>COUT n External High Frequency Output Capacitor Requirement IOUT0 = 31.25A 800 µF<br>(5.75V ≤ VIN ≤ 16V, VOUT n Commanded to 0.75V). IOUT1 = 31.25A 800 µF<br>+ –<br>+<br>–<br>+<br>–<br>**----- End of picture text -----**<br>
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## LTM4682
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FUNCTIONAL DIAGRAM<br>GUI<br>CHANNEL# IDENTITY<br>0 U0:A0<br>1 U0:A1<br>2 U0:B0<br>3 U0:B1<br>Figure 3. Functional LTM4682 Block Diagram<br>Rev. 0<br>RSNUB CSNUB VOUT1, VOUT3COUT4ADJ TO 1.35V UP TO 31.25A LOAD CCOMPH<br>VIN OPTIONAL SNUBBER COUT3 TELEMETRY:OUT CLOAD CCOMPL AND nn _ ARE nn<br>(V READ_VOUT, MFR_VOUT_PEAK, READ_POUT) 3.3V TOLERANT PULL-UP NOT SHOWN EXTERNAL RESISTIVE DIVIDERS BETWEEN VDD25 SGND_ NOT SHOWN. REFER TO TABLES 1, 2 AND 3.<br>VIN_VBIAS5.5V RUNP SW3SW1, , VVOUT3OUT1 2.2µF GND SGNDSGND2301,__ TSNS3TSNS1, OSNS3+OSNS1+, VV , VVOSNS3–OSNS1– COMP3bCOMP1b, COMP3aCOMP1a, PGOOD1, PGOOD3 SYNC_01, SYNC_23 , VVDD25_23DD25_01 2.2µF ASELASEL2301,__ FSWPH_01_CFG, CFGFSWPH23__ CFGVTRIM0_ CFGVTRIM1_ CFGVTRIM2_ CFGVTRIM3_ CFGVOUT0_ VOUT1_CFG CFGVOUT2_ VOUT3_CFG 4682 F03<br>22pF<br>VBIAS TELEMETRY: REMOTE SENSE VDD33 14.3k EACH PIN<br>0.01µF COMP<br>(IOUT1 READ_IOUT1, MFR_IOUT_PEAK) READ_TEMPERATURE1 CHANNEL TEMP + –<br>X1 PROG R<br>120nH 2.5V<br>ALL PINS SHOWN IS FUNCTION ×2 TO SUPPORT CHANNELS 0 AND 1, AND CHANNELS 2 AND 3. (MFR_PWM_MODE, MFR_PWM_CONFIG, FREQUENCY_SWITCH)<br>IN23 DCR SENSE Z PROG GM<br>, V 0.22µF MFR_PWM_COMP<br>VIN01 MT MB + – EA1,3 CONFIG DETECT<br>, SENSE SENSE + –<br>2.2µF IOUT IOUT<br>VDD33_01 VDD33_23<br>22µF LIM SYNC DRIVER<br>VBIAS MUX SETPOINT, UV, OV, I DACs SINC3 32MHz OSC<br>, TEMP<br>4.7µF CC_01 CC_23 0.1µF 32µA READ_TEMPERATURE2 DIE TEMP SENSE 10:1 MUX ADC SUBORDINATE SPI MAIN<br>INTV INTV 2µA SPI EEPROM<br>(CURRENT MODE PWM CNTL LOOPS, POWER CONTROL ANALOG SECTION LINEAR REGULATORS, DACs, ADC, UV/OV MONITORS, VCO/PLL, MOSFET DRIVERS AND POWER CNTL LOGIC) VBE SENSING ROM<br>VIN01, VIN23 + – PROGRAM RAM<br> SENSE SENSE + –<br>UVLO<br>MT MB IOUT IOUT<br>EA0,2<br>COMP<br>CIN2 0.22µF DCR SENSE Z PROG GM PROG R VDD33 COMPARE DIGITAL ENGINE, MAIN CONTROL<br>1µF , 120nH MFR_PWM_COMP<br> TELEMETRY:<br>IN_01 IN_23 IN X1<br>SV SV SV (MFR_READ_ICHIP, READ_VIN, READ_VIN_PEAK)<br>DD33_23<br>, V<br>1Ω IN_01– , IN_23– – INPUT CURRENT/ICHIP READ_IIN, MFR_READ_IIN_PEAK TO ANALOG READBACK) TELEMETRY:(IOUT0 READ_IOUT0, MFR_IOUT_PEAK) CHANNEL TEMP 0.01µF 22pF POWER MANAGEMENT DIGITAL SECTION 2C-BASED I SMBus INTERFACE WITH PMBus COMMANDS (10kHz TO 400kHz COMPATIBLE) VDD33_01 CHANNEL TIMING MANAGEMENT<br>RSENSEVIN CIN1 +IN_01, +IN_23 + A = N (MFR_PWM_MODE, MFR_PWM_CONFIG, FREQUENCY_SWITCH)SW0, SW1 , VVOUT2OUT0 2.2µFGND READ_TEMPERATURE1 TSNS2TSNS0, OSNS2+OSNS0+, VV REMOTE SENSE , VVOSNS2–OSNS0– COMP0b, COMP2b COMP0a, COMP2a PGOOD0, PGOOD2 SCLSCL2301,__ SDA_01, SDA_23 ALERTALERT_23_01, WP_01, WP_23 10µA RUN1RUN0, RUN3RUN2, FAULTFAULT10, FAULTFAULT32, SHARE_CLK_01, CLKSHARE23__<br>+<br>CLOAD CCOMPL<br>COUT1<br>OPTIONAL SNUBBER RSNUB CSNUB COUT2 TELEMETRY:(VOUT READ_VOUT, MFR_VOUT_PEAK, READ_POUT) CCOMPH _01, SHARE_CLK_01 5V-TOLERANT, NOT SHOWN 5V-TOLERANT, NOT SHOWN 3.3V-TOLERANT, NOT SHOWN<br>, LOAD PULL-UP RESISTORS PULL-UP RESISTORS PULL-UP RESISTORS<br>VOUT0 VOUT2 ADJ TO 1.35V UP TO 31.25A ALERT _23, SHARE_CLK_23 FOR 3.3V-TOLERANT, PULL-UP RESISTORS NOT SHOWN TWO DIFFERENT CONTROLLERS 1ST CONTROLLER (PAGE 0X00) = CHANNEL 0 (PAGE 0X01) = CHANNEL 1 2ND CONTROLLER (PAGE 0X00) = CHANNEL 2 (PAGE 0X01) = CHANNEL 3<br>SCL_01, SDA_01, ASEL_01, WP_01, FOR CHANNEL 0 AND 1 SCL_23, SDA_23, ASEL_23, WP_23, ALERT CHANNEL 2 AND 3<br>PWM1,3<br>PWM0,2<br>TEMP<br>OUT1,3I<br>OUT0,2I<br>OUT1,3V<br>OUT0,2V<br>INV<br>CHIPI<br>INI<br>**----- End of picture text -----**<br>
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LTM4682
## **TEST CIRCUITS**
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VDD33_01<br>I [2] C/SMBus I/F WITH PMBus COMMAND 4.7µF 22µF<br>SET TO/FROM IPMI OR OTHER BOARD<br>MANAGEMENT CONTROLLER 10k 4.99k 4.99k 4.99k 4.99k 4.7µF<br>*RUNP CAN BE CONNECTED TO GND<br>FOR ALL VIN, BUT EFFICIENCY WILL BE<br>IMPROVED BY CONNECTING RUNP TO SW0 0.75V AT 31.25A<br>VIN FOR VIN > 7V. ADJUSTABLE TO 1.35V<br>VIN, 5.75V TO 16V VOSNS0VOUT0 [+] 100µF×5<br>+ IN_01 [+] LOAD<br>150µF 22µF 1mΩ VOSNS0 [–]<br>×6<br>1Ω IN_01 [–]<br>VIN01 SW1 0.75V AT 31.25A<br>SVIN_01 ADJUSTABLE TO 1.35V<br>1µF VOSNS1VOUT1 [+] 100µF×5<br>VIN LOAD<br>IN_23 [+] VOSNS1 [–]<br>1mΩ<br>1Ω IN_23 [–] SW2 0.75V AT 31.25A<br>VIN23 ADJUSTABLE TO 1.35V<br>1µF VIN SVVIN_VBIASIN_23 LTM4682 VOSNS2VOUT2 [+] 100µF×5<br>VDD33_01 RUNP*RUN0 VOSNS2 [–] LOAD<br>10k RUN1<br>RUN2 SW3 0.75V AT 31.25A<br>10k ON_OFF_CONFIG RUN3FAULT0 VOSNS3VOUT3 [+] ADJUSTABLE TO 1.35V100µF×5<br>FAULT1 LOAD<br>FAULT2 VOSNS3 [–]<br>FAULT INTERRUPTS<br>FAULT3<br>10k PGOOD0 GND<br>PGOOD1 SGND_23<br>PGOOD2<br>POWER GOOD SGND_01<br>PGOOD3<br>4682 TC01<br>4700pF 4700pF 4700pF 4700pF 32.4k<br>22.6k<br>100pF 100pF 100pF 100pF<br>CONFIG RESISTORS ARE<br>TO BE 1%, 50PPM<br>MFR_CONFIG_ALL BIT[4] =1<br>DEVICE 0,1 ADDRESS: 100_1111_R/W<br>DEVICE 2,3 ADDRESS: 100_1110_R/W<br>DD33_01 DD33_23 DD25_01 DD25_23<br>V V V V<br>_23 _01 BIAS<br>ALERT ALERT SYNC_23 SYNC_01 SDA_23 SDA_01 SCL_23 SCL_01 WP_01 WP_23 VDD33_01 VDD33_23 VDD25_01 VDD25_23 INTVCC_01 INTVCC_23 V TSNS0 TSNS1 TSNS2 TSNS3<br>SHARE_CLK_23 SHARE_CLK_01<br>COMP0a COMP0b COMP1a COMP1b COMP2a COMP2b COMP3a COMP3b VOUT0_CFG VTRIM0_CFG VOUT1_CFG VTRIM1_CFG VOUT2_CFG VTRIM2_CFG VOUT3_CFG VTRIM3_CFG FSWPH_23_CFG FSWPH_01_CFG ASEL_01 ASEL_23<br>**----- End of picture text -----**<br>
## **Test Circuit 1.**
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LTM4682
## **TEST CIRCUITS**
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SVIN_01<br>VDD33_01 4.7µF<br>SVIN_23 22µF<br>I [2] C/SMBus I/F WITH PMBus COMMAND 10k 4.99k 4.99k 4.99k 4.99k<br>SET TO/FROM IPMI OR OTHER BOARD 4.7µF<br>MANAGEMENT CONTROLLER<br>VIN_ON, VIN_OFF, VIN_OV, VIN_UV<br>ARE ADJUSTED FOR LOW VIN OPERATION SW0 0.75V AT 31.25A<br>ADJUSTABLE TO 1.35V<br>VIN, 4.5V TO 5.75V VOSNS0VOUT0 [+] 100µF×5<br>+ IN_01 [+] LOAD<br>150µF 22µF×6 1mΩ VOSNS0 [–]<br>1Ω IN_01 [–]<br>1µF SVIN_01 VSVIN01IN_01 VOSNS1VOUT1SW1 [+] ADJUSTABLE TO 1.35V0.75V AT 31.25A100µF×5<br>VIN LOAD<br>IN_23 [+] VOSNS1 [–]<br>1mΩ<br>1Ω IN_23 [–] SW2 0.75V AT 31.25A<br>VIN23 ADJUSTABLE TO 1.35V<br>1µF SVIN_23 SVVIN_VBIASIN_23 LTM4682 VOSNS2VOUT2 [+] 100µF×5<br>VDD33_01 RUNP VOSNS2 [–] LOAD<br>RUN0<br>10k RUN1<br>RUN2 SW3 0.75V AT 31.25A<br>10k ON_OFF_CONFIG RUN3FAULT0 VOSNS3VOUT3 [+] ADJUSTABLE TO 1.35V100µF×5<br>FAULT1 LOAD<br>FAULT2 VOSNS3 [–]<br>FAULT INTERRUPTS<br>FAULT3<br>10k PGOOD0 GND<br>PGOOD1 SGND_23<br>POWER GOOD PGOOD2 SGND_01<br>PGOOD3<br>4682TC02<br>32.4k<br>4700pF 4700pF 4700pF 4700pF<br>22.6k<br>1 00pF 100pF 100pF 100pF<br>CONFIG RESISTORS ARE<br>TO BE 1%, 50PPM<br>MFR_CONFIG_ALL[4] = 0<br>FOR 0,1 DEVICE<br>SUBORDINATE ADDRESS: 100_1111_R/W<br>FOR 2,3 DEVICE<br>SUBORDINATE ADDRESS: 100_1110_R/W<br>DD33_01 DD33_23 DD25_01 DD25_23<br>V V V V<br>_23 _01 BIAS<br>ALERT ALERT SYNC_23 SYNC_01 SDA_23 SDA_01 SCL_23 SCL_01 WP_01 WP_23 VDD33_01 VDD33_23 VDD25_01 VDD25_23 INTVCC_01 INTVCC_23 V TSNS0 TSNS1 TSNS2 TSNS3<br>SHARE_CLK_23 SHARE_CLK_01<br>COMP0a COMP0b COMP1a COMP1b COMP2a COMP2b COMP3a COMP3b VOUT0_CFG VTRIM0_CFG VOUT1_CFG VTRIM1_CFG VOUT2_CFG VTRIM2_CFG VOUT3_CFG VTRIM3_CFG FSWPH_23_CFG FSWPH_01_CFG ASEL_01 ASEL_23<br>**----- End of picture text -----**<br>
## **Test Circuit 2.**
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LTM4682
## **OPERATION**
## **POWER MODULE INTRODUCTION**
The LTM4682 is a highly configurable quad 31.25A output standalone nonisolated switching mode step-down DC/ DC power supply with built-in EEPROM NVM with error correction coding (ECC) and I[2] C-based PMBus/SMBus 2-wire serial communication interface capable of 400kHz SCL bus speed. Four output voltages can be regulated (VOUT0, VOUT1, VOUT2, and VOUT3) with a few external input and output capacitors and pull-up resistors. Readback telemetry data of input and output voltages and input and output currents, and module temperatures are continually digitized cyclically by an integrated 16-bit analog-to-digital converter (ADC). Many fault thresholds and responses are customizable. Data can be autonomously saved to EEPROM when a fault occurs, and the resulting fault log can be retrieved over I[2] C later, for analysis. See Figure 2 and Figure 3 for the Block Diagrams. One controller for Channels 0 and 1, and second controller for Channels 2 and 3.
## **POWER MODULE OVERVIEW, MAJOR FEATURES**
Major Features Include:
- n Dedicated Power Good Indicators
- n Direct Input and Chip Current Sensing
- n Programmable Loop Compensation Parameters
- n TINIT Start-Up Time: 30ms
- n PWM Synchronization Circuit, (See the Switching Frequency and Phase Section for More Details)
- n MFR_ADC_CONTROL for Fast ADC Sampling of One Parameter (as Fast as 8ms) (See the PMBus Command Details Section)
- n Fully Differential Output Sensing for All Four Channels; VOUT0, VOUT1, VOUT2, and VOUT3. All Programmable Up to 1.2V
- n Power-Up and Program EEPROM with VBIAS
- n Input Voltage Up to 16V
- n ∆VBE Temperature Sensing
- n SYNC Contention Circuit (See the Switching Frequency and Phase Section for More Details)
- n Fault Logging
- n Programmable Output Voltage
- n Programmable Input Voltage On and Off Threshold Voltage
- n Programmable Current Limit
- n Programmable Switching Frequency
- n Programmable OV and UV Threshold Voltage
- n Programmable ON and Off Delay Times
- n Programmable Output Rise/Fall Times
- n Phase-Locked Loop for Synchronous PolyPhase[®] Operation (2, 3, 4 or 6 Phases)
- n Nonvolatile Memory Configuration with ECC
- n Optional External Configuration Resistors for Key Operating Parameters
- n Optional Time Base Interconnect for Synchronization Between Multiple Controllers
- n WP Pin to Protect Internal Configuration
- n Stand Along Operation After User Factory Configuration
- n PMBus, Version 1.2, 400kHz-Compliant Interface
The PMBus interface provides access to important power management data during system operation including:
- n Internal Controller Temperature
- n Internal Power Channel Temperature
- n Average Output Current
- n Average Output Voltage
- n Average Input Voltage
- n Average Input Current
- n Average Chip Input Current from VIN
- n Configurable, Latched and Unlatched Individual Fault and Warning Status
Individual channels are accessed through the PMBus using the PAGE command, i.e., PAGE 0 or 1.
Fault reporting and shutdown behavior are fully configurable. Four individual FAULT0, FAULT1, FAULT2,
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LTM4682
## **OPERATION**
and FAULT3, outputs are provided. Each FAULT _n_ can be masked independently.
Six dedicated pins for ALERT_01, ALERT_23, PGOOD0, PGOOD1, PGOOD2, and PGOOD3 functions are provided. The shutdown operation also allows all faults to be individually masked and can be operated in either unlatched (hiccup) or latched modes.
Individual status commands enable fault reporting over the serial bus to identify the specific fault event. Fault or warning detection includes the following:
- n Output Undervoltage/Overvoltage
- n Input Undervoltage/Overvoltage
- n Input and Output Overcurrent
- n Internal Overtemperature
- n Communication, Memory or Logic (CML) Fault
## **EEPROM WITH ECC**
The LTM4682 contains internal EEPROM with ECC to store user configuration settings and fault log information for Channels 0 and 1, and Channels 2 and 3. The EEPROM endurance retention and mass write operation time are specified in the Electrical Characteristics and Absolute Maximum Ratings sections. Write operations above TJ = 85°C are possible although the Electrical Characteristics are not guaranteed and the EEPROM will be degraded. Read operations performed at temperatures between –40°C and 125°C will not degrade the EEPROM. Writing to the EEPROM above 85°C will result in degrading retention characteristics. The fault logging function, which is useful in debugging system problems that may occur at high temperatures, only writes to fault log EEPROM locations. If occasional writes to these registers occur above 85°C, the slight degradation in the data retention characteristics of the fault log will not take away from the usefulness of the function.
It is recommended that the EEPROM not be written when the die temperature is greater than 85°C. If the die temperature exceeds 130°C, the LTM4682 will disable all EEPROM write operations. All EEPROM write operations will be re-enabled when the die temperature drops below
125°C. The controller will also disable all the switching when the die temperature exceeds the internal overtemperature fault limit 160°C with a 10°C hysteresis.
The degradation in EEPROM retention for temperatures >125°C can be approximated by calculating the dimensionless acceleration factor using the following equation:
**==> picture [162 x 32] intentionally omitted <==**
where:
AF = acceleration factor
Ea = activation energy = 1.4eV
k = 8.617 • 10[–5] eV/K
TUSE = 125°C specified junction temperature
TSTRESS = actual junction temperature in °C
Example: Calculate the effect on retention when operating at a junction temperature of 130°C for 10 hours.
TSTRESS = 130°C
TUSE = 125°C, AF = e[([(1.4/8.617 • 10–5) • (1/398 – 1/403)] ) ] = 1.66
The equivalent operating time at 125°C = 16.6 hours.
Thus the overall retention of the EEPROM was degraded by 6.6 hours as a result of operating at a junction temperature of 130°C for 10 hours. The effect of the overstress is negligible when compared to the overall EEPROM retention rating of 87,600 hours at a maximum junction temperature of 125°C.
The integrity of the entire onboard EEPROM is checked with a CRC calculation each time its data is to be read, such as after a power-on reset or execution of a RESTORE_USER_ ALL command. If a CRC error occurs, the CML bit is set in the STATUS_BYTE and STATUS_WORD commands, the EEPROM CRC Error bit in the STATUS_MFR_SPECIFIC command is set, and the ALERT and RUN pins pulled low (PWM channels off). At that point the device will only respond at a special address 0x7C, which is activated only after an invalid CRC has been detected. The chip will also respond at the global addresses 0x5A and 0x5B, but using these addresses when attempting to recover
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LTM4682
## **OPERATION**
from a CRC issue is not recommended. All power supply rails associated with either PWM channel of a device reporting an invalid CRC should remain disabled until the issue is resolved. See the Applications Information section or contact the factory for more details on efficient insystem EEPROM programming, including bulk EEPROM Programming, which the LTM4682 also supports.
The LTM4682 contains two dual internal constant frequency current mode control buck regulators (Channel 0 and Channel 1, and Channel 2 and Channel 3) and whose power MOSFETs are capable of fast switching speed. Reference to the signal pins will be Name nn_ , where _n_ is either 01 or 23, or with name _n_ when referring to signal pins that are related to the actual channel. The factory NVMdefault switching frequency clocks SYNC nn_ at 575kHz, to which the regulators synchronize their switching frequency. The default phase-interleaving angle between the channels is 180°. A pin-strapping resistor on FSWPH nn_ _CFG configures the frequency of the SYNC nn_ clock (switching frequency) and the channel phase relationship of the channels to each other and for the falling edge of the SYNC nn_ signal. (Most possible combinations of the switching frequency and the phase-angle assignments are settleable by the resistor pin programming; see Table 3. Configure the LTM4682’s NVM to implement settings unavailable by resistor-pin strapping.) When a FSWPH nn_ _CFG pinstrap resistor sets the channel phase relationship of the LTM4682’s channels, the SYNC nn_ clock is not driven by the module. Instead, SYNC nn_ becomes strictly a high impedance input, and the channel switching frequency is then synchronized to SYNC nn_ provided by an externallygenerated clock or sibling LTM4682 with a pull-up resistor to VDD33 nn_ . Switching frequency and phase relationship can be altered through the I[2] C interface, but only when the switching action is off, i.e., when the module is not regulating the outputs. See the Applications Information section for more details.
Programmable analog feedback loop compensation for Channel 0 to Channel 3 is accomplished with a capacitor connection from COMP _n_ a to SGND, and a capacitor from COMP _n_ b to SGND.) The COMP _n_ b pin is for the high frequency gain roll-off and is the gm amplifier output that has a programmable range, and the COMP _n_ a pin has the programmable resistor range, along with a
capacitor to SGND that sets the frequency compensation. See the Programmable Loop Compensation section. The LTM4682 module has sufficient stability margins and good transient performance with a wide range of output capacitors—even all-ceramic MLCCs. Table 13 provides guidance on input and output capacitors recommended for many common operating conditions, along with the programmable compensation settings. The Analog Devices LTpowerCAD[®] tool is available for transient and stability analysis, and experienced users who prefer to adjust the module’s feedback loop compensation parameters can use this tool.
## **POWER-UP AND INITIALIZATION**
The LTM4682 is designed to provide standalone supply sequencing and controlled turn-on and turn-off operation. It operates from a single input supply (4.5V to 16V) while three on-chip linear regulators generate internal 2.5V, 3.3V, and 5.5V per controller. If the VIN _nn_ does not exceed 5.75V, and the VBIAS pin is turned off, the INTVCC, VIN _nn_ and SVIN nn_ pins must be connected together. The controller configuration is initialized by an internal thresholdbased UVLO where VIN _nn_ must be approximately 4V, and the 5.5V, 3.3V, and 2.5V linear regulators must be within approximately 20% of the regulated values. In addition to the power supply, a PMBus RESTORE_USER_ALL or MFR_RESET command can initialize the part, too.
- The VBIAS pin is the output of an internal 5.5V buck regula tor to improve the efficiency of the circuit and minimize power loss on the LTM4682. The VBIAS pin must exceed approximately 4.8V, and VIN must exceed 7V before the INTVCC LDO operates from the VBIAS pin. The VBIAS regulator is powered from VIN_VBIAS and enabled with RUNP.
During initialization, the external configuration resistors are identified and/or contents of the NVM are read into the controller’s commands, and the power train is held off. The RUN _n_ , FAULT _n_ , and PGOOD _n_ are held low. The LTM4682 will use the contents of Table 1 through Table 5 to determine the resistor-defined parameters. See the RCONFIG (Resistor Configuration) Pins section for more details. The resistor configuration pins only control some of the preset values of the controller. The remaining values are programmed in NVM either at the factory or by the user.
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LTM4682
## **OPERATION**
If the configuration resistors are not inserted or if the ignore RCONFIG bit is asserted (bit 6 of the MFR_ CONFIG_ALL configuration command), the LTM4682 will use only the contents of NVM to determine the DC/DC characteristics. The ASEL nn_ value read at power-up or reset is always respected unless the pin is open. The ASEL nn_ will set the bottom 4LSBs, and the MSBs are set by NVM. See the Applications Information section for more details.
After the part has initialized, an additional comparator monitors VIN through the SVIN nn_ pins. The VIN_ON threshold must be exceeded before the output power sequencing can begin. After VIN is initially applied, the part will typically require 30ms to initialize and begin the TON_DELAY timer. The readback of voltages and currents may require an additional 0ms to 90ms.
## **SOFT-START**
The method of start-up sequencing described in this section is time-based. The part must enter the run state before soft-start. The RUN pins are released by the LTM4682 after the part is initialized and SVIN nn_ exceeds the VIN_ON threshold. If multiple LTM4682s are used in an application, they all hold their respective RUN pins low until all devices are initialized, and SVIN nn_ exceeds the VIN_ON threshold for every device. The SHARE_CLK nn_ pin assures all the devices connected to the signal use the same time base. The SHARE_CLK nn_ pin is held low until the part has been initialized after VIN is applied. The LTM4682 can be set to turn-off (or remain off) if SHARE_ CLK nn_ is low (set bit 2 of MFR_CHAN_CONFIG to 1). This allows the user to ensure synchronization across numerous Analog Devices ICs even if the RUN _n_ pins cannot be connected together due to board constraints. In general, if the user cares about synchronization between chips, it is best not only to connect all the respective RUN _n_ pins together but also to connect all the respective SHARE_CLK nn_ pins together and pulled up to VDD33 nn_ with a 10k resistor. This assures all chips begin sequencing simultaneously and use the same time base.
After the RUN _n_ pins release and before entering a constant output voltage regulation state, the LTM4682 performs a monotonic initial ramp or soft-start. Soft-start is performed
by actively regulating the load voltage while digitally ramping the target voltage from 0V to the commanded voltage set-point. Once the LTM4682 is commanded to turn on (after power up and initialization), the controller waits for the user specified turn-on delay (TON_DELAY) before initiating this output voltage ramp. The rise time of the voltage ramp can be programmed using the TON_RISE command to minimize inrush currents associated with the start-up voltage ramp. The soft-start feature is disabled by setting the value of TON_RISE to any value less than 0.25ms. The LTM4682 PWM always uses discontinuous mode during the TON_RISE operation. In discontinuous mode, the bottom MOSFET is turned off as soon as reverse current is detected in the inductor. This will allow the regulator to start up into a pre-biased load. When the TON_MAX_FAULT_ LIMIT is reached, the part transitions to continuous mode, if so programmed. If TON_MAX_FAULT_LIMIT is set to zero, there is no time limit, and the part transitions to the desired conduction mode after TON_RISE completes and VOUT _n_ has exceeded the VOUT_UV_FAULT_LIMIT and IOUT_OC is not present. However, setting TON_MAX_FAULT_LIMIT to a value of 0 is not recommended.
## **TIME-BASED SEQUENCING**
The default mode for sequencing the outputs on and off is time-based. Each output is enabled after waiting a TON_ DELAY amount of time following either a RUN pin going high, a PMBus command to turn on or the VIN rising above a preprogrammed voltage. Off-sequencing is handled similarly. To ensure proper sequencing, make sure all ICs connect the SHARE_CLK nn_ pin together and RUN _n_ pins together. If the RUN _n_ pins cannot be connected together for some reasons, set bit 2 of MFR_CHAN_CONFIG to 1. This bit requires the SHARE_CLK nn_ pin to be clocking before the power supply output can start. When the RUN _n_ pin is pulled low, the LTM4682 will hold the pin low for the MFR_RESTART_DELAY. The minimum MFR_RESTART_ DELAY is TOFF_DELAY + TOFF_FALL + 136ms. This delay assures proper sequencing of all rails. The LTM4682 calculates this delay internally and will not process a shorter delay. However, a longer commanded MFR_RESTART_ DELAY can be used by the part. The maximum allowed value is 65.52 seconds.
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LTM4682
## **OPERATION**
## **VOLTAGE-BASED SEQUENCING**
The sequence can also be voltage-based. As shown in Figure 4, The PGOOD _n_ pin is asserted when the UV threshold is exceeded for each output. It is possible to feed the PGOOD _n_ pin from one LTM4682 channel into the RUN _n_ pin of the next LTM4682 channel in the sequence, especially across multiple LTM4682s. The PGOOD _n_ has a 100µs filter. If the VOUT _n_ voltage bounces around the UV threshold for a long period of time, it is possible for the PGOOD _n_ output to toggle more than once. To minimize this problem, set the TON_RISE time under 100ms.
If a fault in the string of rails is detected, only the faulted rail and downstream rails will fault off. The rails in the string of devices in front of the faulted rail will remain on unless commanded off.
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RUN0 PGOOD0<br>START<br>LTM4682<br>1/2<br>RUN1 PGOOD1<br>RUN2 PGOOD2<br>LTM4682<br>1/2<br>RUN3 PGOOD3<br>4682 F04<br>TO NEXT CHANNEL<br>IN THE SEQUENCE<br>**----- End of picture text -----**<br>
**Figure 4. Event (Voltage) Based Sequencing**
## **SHUTDOWN**
The LTM4682 supports two shutdown modes. The first mode is a closed-loop shutdown response, with a userdefined turn-off delay (TOFF_DELAY) and ramp down rate (TOFF_FALL). The controller will maintain the mode of operation for TOFF_FALL. The second mode is the discontinuous conduction mode, the controller will not draw current from the load and the fall time will be set by the output capacitance, and load current, instead of TOFF_FALL.
The shutdown occurs in response to a fault condition or loss of SHARE_CLK nn_ (if bit 2 of MFR_CHAN_CONFIG is set to a 1), or VIN _nn_ falling below the VIN_OFF threshold, or FAULT pulled low externally (if the MFR_FAULT_ RESPONSE is set to inhibit). Under these conditions, the
power stage is disabled in order to stop the transfer of energy to the load as quickly as possible. The shutdown state can be entered from the soft-start or active regulation states or through user intervention.
There are two ways to respond to faults; retry mode and latched-off mode. In retry mode, the controller responds to a fault by shutting down and entering the inactive state for a programmable delay time (MFR_RETRY_DELAY). This delay minimizes the duty cycle associated with autonomous retries if the fault that causes the shutdown disappears once the output is disabled. The retry delay time is determined by the longer of the MFR_RETRY_ DELAY command or the time required for the regulated output to decay below 12.5% of the programmed value. If multiple outputs are controlled by the same FAULT _n_ pin, the decay time of the faulted output determines the retry delay. If the natural decay time of the output is too long, it is possible to remove the voltage requirement of the MFR_RETRY_DELAY command by asserting bit 0 of MFR_CHAN_CONFIG. Alternatively, latched-off mode means the controller remains latched-off following a fault, and clearing requires user intervention, such as toggling RUN _n_ or commanding the part OFF and then ON.
## **LIGHT-LOAD CURRENT OPERATION**
The LTM4682 has two modes of operation: high efficiency discontinuous conduction mode or forced continuous conduction mode. Mode selection is done using the MFR_PWM_MODE command (discontinuous conduction is always the start-up mode, and forced continuous is the default running mode).
If a controller is enabled for discontinuous operation, the inductor current is not allowed to reverse. The reverse current comparator’s output turns off the bottom MOSFET just before the inductor current reaches zero, preventing it from reversing and going negative.
In forced continuous operation, the inductor current is allowed to reverse at light loads or under large transient conditions. The peak inductor current is determined solely by the voltage on the COMP _n_ pins. In this mode, the efficiency at light loads is lower than in discontinuous mode operation. However, continuous mode exhibits
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LTM4682
## **OPERATION**
lower output ripple and less interference with audio circuitry, but may result in a reverse inductor current, which can cause the input supply to boost. The VIN_OV_FAULT_ LIMIT can detect this and turn off the offending channel. However, this fault is based on an ADC read and can take up to tCONVERT to detect. If there is a concern about the input supply boosting, keep the part in discontinuous conduction mode.
If the part is set to discontinuous mode operation, as the inductor average current increases, the controller will automatically modify the operation from discontinuous mode to continuous mode.
## **SWITCHING FREQUENCY AND PHASE**
The switching frequency of the PWM can be established with an internal oscillator or an external time base. The internal phase-locked loop (PLL) synchronizes the PWM control to this timing reference with proper phase relation, whether the clock is provided internally or externally. The device can also be configured to provide the main device clock to other devices through the PMBus command, NVM setting, or external configuration resistors, as outlined in Table 3.
As a main clock, the LTM4682 will drive its open-drain SYNC nn_ pin at the selected rate with a pulse width of 500ns. An external pull-up resistor between SYNC nn_ and VDD33 nn_ is required in this case. Only one device connected to SYNC nn_ should be designated to drive the pin. The LTM4682 will automatically revert to an external SYNC nn_ input, disabling its SYNC nn_ , as long as the external SYNC nn_ frequency is greater than 80% of the programmed SYNC nn_ frequency. The external SYNC input shall have a duty cycle between 20% and 80%.
Whether configured to drive SYNC nn_ or not, the LTM4682 can continue PWM operation using its internal oscillator if an external clock signal is subsequently lost.
The device can also be programmed to always require an external oscillator for PWM operation by setting bit 4 of MFR_CONFIG_ALL. The status of the SYNC driver circuit is indicated by bit 10 of MFR_PADS.
The MFR_PWM_CONFIG command can be used to configure the phase of each channel. The desired phase can
also be set from EEPROM or external configuration resistors, as outlined in Table 3. The designated phase is the relationship between the falling edge of SYNC and the internal clock edge that sets the PWM latch to turn on the top power switch. Additional small propagation delays to the PWM control pins will also apply. Both channels must be off before the FREQUENCY_SWITCH and MFR_PWM_ CONFIG commands can be written to the LTM4682.
The phase relationships and frequency options provide for numerous application options. Multiple LTM4682 modules can be synchronized to realize a PolyPhase array. In this case, the phases should be separated by 360/ _n_ degrees, where _n_ is the number of phases driving the output voltage rail.
## **PWM LOOP COMPENSATION**
The internal PWM loop compensation resistors RCOMP _n_ a of the LTM4682 can be adjusted using bit[4:0] of the MFR_PWM_COMP command for each controller.
The transconductance (gm) of the LTM4682 PWM error amplifier can be adjusted using bit[7:5] of the MFR_ PWM_COMP command. These two loop compensation parameters can be programmed when the device is in operation. See the Programmable Loop Compensation subsection in the Applications Information section for further details.
## **OUTPUT VOLTAGE SENSING**
All four channels in LTM4682 have differential amplifiers, which allow the remote sensing of the load voltage between V[+] and V[–] pins. The telemetry ADC is also fully differential and makes measurements between VOSNS _n_[+ ] and VOSNS _n_[–] voltages for both channels at the V[+] and V[– ] pins, respectively. The maximum allowed is 1.5V, but the LTM4682 design is limited to 1.35V.
## **INTVCC/VBIAS POWER**
Power for the internal top and bottom MOSFET drivers and most other internal circuitry is derived from the INTVCC pin. When the RUNP pin is shorted to GND and the VBIAS is off, an internal 5.5V linear regulator supplies INTVCC
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LTM4682
## **OPERATION**
power from SVIN nn_ . When enabling VBIAS at 5.5V output and SVIN exceeds 7.0V, an internal switch turned on to source power from VBIAS instead of INTVCC regulator. Using the VBIAS allows the INTVCC power to be derived from a high efficiency internal source. VBIAS can provide power to the internal 3.3V linear regulators when VIN is present, which allows the LTM4682 controllers to be initialized and programmed even with channels off.
The INTVCC nn_ regulator is powered from the SVIN nn_ pin; the power through the IC is equal to SVIN nn_ • IINTVCC _nn_ . The gate charge current is dependent on the operating frequency. The typical INTVCC nn_ current for the LTM4682 is ~50mA. A 12V input voltage would equate to a difference of 7V per controller drop across the internal controller, when multiplied by 50mA equals a 350mW power loss. This loss can be eliminated by utilizing the VBIAS regulator.
Do not connect INTVCC nn_ on the LTM4682 to an external supply because INTVCC nn_ will attempt to pull the external supply high and hit the current limit, significantly increasing the die temperature.
For applications where VIN is 5V, connect the SVIN nn_ and INTVCC nn_ pins together to the 5V input through a 1Ω resistor, as shown in Test Circuit 2.
## **OUTPUT CURRENT SENSING AND SUB MILLIOHM DCR CURRENT SENSING**
The LTM4682 uses a unique sub-milliohm inductor current sensing technique that provides a high level signalto-noise ratio while sensing very low signals in current mode operation. This enables higher conversion efficiencies using the internal sub-milliohm inductors in heavy load applications. The current limit threshold can be accurately set with the MFR_PWM_MODE[7] for the high and low range (see IOUT_OC_FAULT_LIMIT).
The internal DCR sensing network, thus, the current limit is calculated based on the DCR of the inductor at room temperature. The DCR of the inductor has a large temperature coefficient, approximately 3900ppm/°C. The temperature coefficient of the inductor is written to the MFR_IOUT_ CAL_GAIN_TC register. The external temperature is sensed near the inductor and used to modify the internal current limit circuit to maintain an essentially constant current
limit with temperature. The current sensed is then digitized by the LTM4682’s telemetry ADC with an input range of ±128mV, a noise floor of 7µVRMS, and a peak-peak noise of approximately 46.5µV. The LTM4682 computes the inductor current using the DCR value stored in the IOUT_CAL_ GAIN command and the temperature coefficient stored in the MFR_IOUT_CAL_GAIN_TC command. The resulting current value is returned by the READ_IOUT command.
## **INPUT CURRENT SENSING**
To sense the total input current consumed by the LTM4682’s power stages, a sense resistor is placed between the supply voltage and the drain of the top N-channel MOSFET. The IIN nn_[+] and IIN nn_[– ] pins are connected to the sense resistor. The filtered voltage is amplified by the internal high-side current sense amplifier and digitized by the LTM4682’s telemetry ADC. The input current sense amplifier has three gain settings of 2×, 4×, and 8× set by the bit[6:5] of the MFR_PWM_CONFIG command. The maximum input sense voltage for the three gain settings is 50mV, 25mV, and 10mV, respectively. The LTM4682 computes the input current using the internal RSENSE value stored in the IIN_CAL_GAIN command. The resulting measured power stage current is returned by the READ_IIN command. IIN_01[+] , IIN_01[–] for controller 1 (Channels 0 and 1), and IIN_23[+] , IIN_23[–] for controller 2 (Channels 2 and 3).
The LTM4682 uses a 1Ω resistor to measure the SVIN nn_ pin supply current being consumed by each LTM4682 internal controller. This value is returned by the MFR_ READ_ICHIP command. The chip current is calculated by using the 1Ω value stored in the MFR_ICHIP_CAL_GAIN command. See the subsection titled Input Current Sense Amplifier in the Applications Information section for further details.
## **PolyPhase LOAD SHARING**
Multiple LTM4682s can be arrayed to provide a balanced load-share solution by bussing the necessary pins. Figure 50 illustrates an 8-phase design sharing connections required for load sharing.
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LTM4682
## **OPERATION**
If an external oscillator is not provided, the SYNC nn_ pins should only be enabled on one of the LTM4682s controllers. The other(s) should be programmed to disable SYNC nn_ controllers using bit 4 of MFR_CONFIG_ALL. If an external oscillator is present, the chip with the SYNC nn_ pin enabled will detect the presence of the external clock and disable its output.
Multiple channels need to connect all the VOSNSn[+] pins together, and all the VOSNSn[–] pins together, COMP _n_ a and COMP _n_ b pins together as well. Do not assert bit[4] of MFR_ CONFIG_ALL except in a PolyPhase application.
The user must share the SYNC nn_ , SHARE_CLK nn_ , FAULT _n_ , and ALERT _n_ pins of these parts. Use the pullup resistors on SYNC nn_ , FAULT _n_ , SHARE_CLK nn_ and ALERT _n_ . See the Typical Application section.
## **INTERNAL TEMPERATURE SENSE**
Temperature is measured using the internal diode-connected PNP transistors, and the outputs are connected to TSNS0 to TSNS3 pins corresponding to Channels 0 to 3. These outputs are used for testing. Two different currents are applied to the diode (nominally 2µA and 32µA), and the temperature is calculated from a ∆VBE measurement made with the internal 16-bit monitor ADC (see Figure 2 Block Diagram).
The LTM4682 will only implement ∆VBE temperature sensing. Therefore the MFR_PWM_MODE bit[5] is reserved.
## **RCONFIG (RESISTOR CONFIGURATION) PINS**
There are twelve input pins utilizing 1% resistors between these pins to select key operating parameters. The pins are ASEL_01, ASEL_23, FSWPH_01_CFG, FSWPH_23_ CFG, VOUT0_CFG, VOUT1_CFG, VOUT2_CFG, VOUT3_ CFG, VTRIM0_CFG, VTRIM1_CFG, VTRIM2_CFG, and VTRIM3_CFG. If pins are floated, the value stored in the corresponding NVM command is used. If bit 6 of the MFR_CONFIG_ALL configuration command is asserted in NVM, the resistor input is ignored upon power-up except for ASEL, which is always respected. The resistor configuration pins are only measured during a power-up reset or after a MFR_RESET, or after an RESTORE_USER_ALL command is executed.
The VOUT _n_ _CFG pin settings are described in Table 1. These pins set the LTM4682 VOUT0 to VOUT3 output voltage coarse settings. If the pin is open, the VOUT_COMMAND command is loaded from NVM to determine the output voltage. The default setting is to have the switcher off unless the voltage configuration pins are installed. The VTRIM _n_ _CFG pins in Table 2 are used to set the output voltage fine adjustment setting. Both combine to offer several distinct output voltages.
The following parameters are set as a percentage of the output voltage if the RCONFIG pins are used to determine the output voltage:
n VOUT_OV_FAULT_LIMIT ....................................+10% n VOUT_OV_WARN_LIMIT ....................................+7.5% n VOUT_MAX .........................................................+7.5% n VOUT_MARGIN_HIGH ........................................+5% n VOUT_MARGIN_LOW .........................................–5% n VOUT_UV_FAULT_LIMIT ....................................–7%
The FSWPH_CFG nn_ pin settings are described in Table 3. This pin selects the switching frequency and phase of each channel. The phase relationships between the two channels and the SYNC nn_ pin are determined in Table 3. To synchronize to an external clock, the part should be put into external clock mode (SYNC nn_ output disabled but frequency set to the nominal value). If no external clock is supplied, the part will clock at the programmed frequency. If the application is multiphase and the SYNC nn_ signal between chips is lost, the parts will not operate at the designed phase, even if they are programmed and trimmed to the same frequency.
This may increase the ripple voltage on the output, possibly producing undesirable operation. If the external SYNC nn_ signal is being generated internally and external SYNC nn_ is not selected, bit 10 of MFR_PADS will be asserted. If no frequency is selected and the external SYNC nn_ frequency is not present, a PLL_FAULT will occur. If the user does not wish to see the ALERT from a PLL_FAULT, even if there is not a valid synchronization signal at power-up, the ALERT mask for PLL_FAULT must be written. See the description on SMBALERT_MASK for more details. If the SYNC nn_ pin is connected between multiple ICs, only one of the ICs should have the SYNC nn_ pin enabled using the
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LTM4682
## **OPERATION**
MFR_CONFIG_ALL[4] = 1, and all other ICs should be configured to have the SYNC pin disabled with MFR_CONFIG_ ALL[4] = 0.
The ASEL nn_ pin settings are described in Table 4. ASEL nn_ selects the subordinate address for the LTM4682 internal controller. See Table 5.
Note: Per the PMBus specification, pin-programmed parameters can be overridden by commands from the digital interface, with the exception of ASEL nn_ , which is always honored. Do not set any part address to 0x5A or 0x5B because these are global addresses, and all parts will respond to them.
**Table 1. VOUT** _**n**_ **_CFG Pin Strapping Look-Up Table for the LTM4682’s Output Voltage, Coarse Setting (Not Applicable if MFR_CONFIG_ALL[6] = 1b) Top Resistor = 14.3k**
|**RVOUT****_n__CFG* **<br>**(kΩ)**|**VOUT****_n_ (V)**<br>**SETTING COARSE**|**MFR_PWM_MODE****_n_[1]**<br>**BIT**|
|---|---|---|
|Open|NVM|NVM|
|32.4|NVM|NVM|
|3.24|1.3|1|
|2.43|1.1|1|
|1.65|0.9|1|
|0.787|0.7|1|
|0|0.5|1|
*RVOUT _n_ _CFG value indicated is nominal. Select RVOUT _n_ _CFG from a resistor vendor such that its value is always within 3% of the value indicated in the table. Consider resistor initial tolerance, T.C.R. and resistor operating temperatures, soldering heat/IR reflow, and endurance of the resistor over its lifetime. Thermal shock/cycling, moisture (humidity), and other effects (depending on one’s specific application) could also affect RVOUT _n_ _CFG’s value over time. All such effects must be considered for resistor pin strapping to yield the expected result at every SVIN power-up and/or every execution of MFR_RESET or RESTORE_USER_ALL, over the lifetime of one’s product. RTOP = 14.3k is external to the part. Example:
**==> picture [52 x 66] intentionally omitted <==**
**----- Start of picture text -----**<br>
VDD25_ nn<br>RTOP<br>14.3k<br>VOUT n _CFG<br>RVOUT n _CFG<br>SGND_ nn<br>**----- End of picture text -----**<br>
**Table 2. VTRIMn_CFG Pin Strapping Look-Up Table for the LTM4682’s Output Voltage, Fine Adjustment Setting (Not Applicable if MFR_CONFIG_ALL[6] = 1b) Top Resistor = 14.3k**
|**RVTRIMn_CFG* **<br>**(kΩ)**|**VTRIM (mV) FINE ADJUSTMENT TO VOUT****_n_ SETTING**<br>**WHEN RESPECTIVE**|
|---|---|
|Open|0|
|32.4|99|
|22.6|86.625|
|18.0|74.25|
|15.4|61.875|
|12.7|49.5|
|10.7|37.125|
|9.09|24.75|
|7.68|12.375|
|6.34|–12.375|
|5.23|–24.75|
|4.22|–37.125|
|3.24|–49.5|
|2.43|–61.875|
|1.65|–74.25|
|0.787|–86.625|
|0|–99|
*RVTRIM _n_ _CFG value indicated is nominal. Select RVTRIM _n_ _CFG from a resistor vendor such that its value is always within 3% of the value indicated in the table. Consider resistor initial tolerance, T.C.R. and resistor operating temperatures, soldering heat/IR reflow, and endurance of the resistor over its lifetime. Thermal shock/cycling, moisture (humidity) and other effects (depending on one’s specific application) could also affect RVTRIM _n_ _CFG’s value over time. All such effects must be considered for resistor pin strapping to yield the expected result at every SVIN nn_ power-up and/or every execution of MFR_RESET, or RESTORE_USER_ALL over the lifetime of one’s product. RTOP = 14.3k is external to the part. Example:
**==> picture [59 x 71] intentionally omitted <==**
**----- Start of picture text -----**<br>
VDD25_ nn<br>14.3k<br>VTRIM n _CFG<br>RTRIM_CFG BOT<br>SGND_ nn<br>**----- End of picture text -----**<br>
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LTM4682
## **OPERATION**
**Table 3. FSWPH_** _**nn**_ **_CFG Pin Strapping Look-Up Table to Set the LTM4682’s Switching Frequency and Channel Phase-Interleaving Angle (Not Applicable if MFR_CONFIG_ALL[6] = 1b),** _**nn**_ **= 01 or 23 Channels, Set Top Resistor to 14.3k**
|**RFSWPH_CFG* **<br>**(kΩ)**|**SWITCHING**<br>**FREQUENCY (kHz)**|θ**SYNC TO**θ**0,2**|θ**SYNC TO**θ**1,3**|**BITS [2:0] of**<br>**MFR_PWM_CONFIG**|**BIT [4] of**<br>**MFR_CONFIG_ALL**|
|---|---|---|---|---|---|
|Open|NVM; LTM4682<br>Default = 575|NVM; LTM4682<br>Default = 0°|NVM; LTM4682<br>Default = 180°|NVM; LTM4682<br>Default = 000b|NVM; LTM4682<br>Default = 0b|
|32.4|250|0°|180°|000b|0b|
|22.6|350|0°|180°|000b|0b|
|18.0|425|0°|180°|000b|0b|
|15.4|575|0°|180°|000b|0b|
|12.7|650|0°|180°|000b|0b|
|10.7|750|0°|180°|000b|0b|
|7.68|500|120°|240°|100b|0b|
|6.34|500|90°|270°|001b|0b|
|5.23|External**|0°|240°|010b|1b|
|4.22|External**|0°|120°|011b|1b|
|3.24|External**|60°|240°|101b|1b|
|2.43|External**|120°|300°|110b|1b|
|1.65|External**|90°|270°|001b|1b|
|0.787|External**|0°|180°|000b|1b|
|0|External**|120°|240°|100b|1b|
*RFSWPH nn_ _CFG value indicated is nominal. Select RFSWPH nn_ _CFG from a resistor vendor such that its value is always within 3% of the value indicated in the table. Consider resistor initial tolerance, T.C.R. and resistor operating temperatures, soldering heat/IR reflow, and endurance of the resistor over its lifetime. Thermal shock/cycling, moisture (humidity), and other effects (depending on one’s specific application) could also affect RFSWPH nn_ _CFG’s value over time. All such effects must be considered for resistor pin-strapping to yield the expected result at every SVIN power-up and/or every execution of MFR_RESET or RESTORE_USER_ALL, over the lifetime of one’s product.
**External setting corresponds to FREQUENCY_SWITCH (Register 0x33) value set to 0x0000; the device synchronizes its switching frequency to that of the clock provided on the SYNC nn_ pin, provided MFR_CONFIG_ALL[4] = 1b. RTOP = 14.3k is external to the part. Example:
**==> picture [80 x 70] intentionally omitted <==**
**----- Start of picture text -----**<br>
VDD25_ nn<br>14.3k<br>FSWPH_ nn _CFG PIN<br>RFSWPH_CFG BOT<br>**----- End of picture text -----**<br>
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LTM4682
## **OPERATION**
**Table 4. ASEL_** _**nn**_ **Pin Strapping Look-Up Table to Set the LTM4682’s Subordinate Address (Applicable Regardless of MFR_CONFIG_ALL[6] Setting)**
|<br>**LTM4682’s Subordinate Address**<br>**MFR_CONFIG_ALL[6] Setting)**|<br>**(Applicable Regardless of**|
|---|---|
|**RASEL* (kΩ)**|**SUBORDINATE ADDRESS**|
|Open|100_1111_R/W|
|32.4|100_1111_R/W|
|22.6|100_1110_R/W|
|18.0|100_1101_R/W|
|15.4|100_1100_R/W|
|12.7|100_1011_R/W|
|10.7|100_1010_R/W|
|9.09|100_1001_R/W|
|7.68|100_1000_R/W|
|6.34|100_0111_R/W|
|5.23|100_0110_R/W|
|4.22|100_0101_R/W|
|3.24|100_0100_R/W|
|2.43|100_0011_R/W|
|1.65|100_0010_R/W|
|0.787|100_0001_R/W|
|0|100_0000_R/W|
## Where:
R/W = Read/Write bit in the control byte
All PMBus device addresses listed in the specification are 7 bits wide unless otherwise noted.
Note: The LTM4682 will always respond to subordinate addresses 0x5A and 0x5B regardless of the NVM or ASEL resistor configuration values.
*RCFG value indicated is nominal. Select RCFG from a resistor vendor such that its value is always within 3% of the value indicated in the table. Consider resistor initial tolerance, T.C.R. and resistor operating temperatures, soldering heat/IR reflow, and endurance of the resistor over its lifetime. Thermal shock cycling, moisture (humidity), and other effects (depending on one’s specific application) could also affect RCFG’s value over time. All such effects must be considered for resistor pin-strapping to yield the expected result at every SVIN power-up and/or every execution of MFR_RESET or RESTORE_USER_ALL, over the lifetime of one’s product.
Example:
**==> picture [49 x 42] intentionally omitted <==**
**----- Start of picture text -----**<br>
ASEL_ nn PIN<br>RASEL<br>SGND_ nn<br>**----- End of picture text -----**<br>
**Table 5. LTM4682 MFR_ADDRESS Command Examples Expressed in 7- and 8-Bit Addressing**
|**DESCRIPTION**|**HEX DEVICE**<br>**ADDRESS**|**HEX DEVICE**<br>**ADDRESS**|**BIT**|**BIT**|**BIT**|**BIT**|**BIT**|**BIT**|**BIT**|**BIT**|**BIT**|
|---|---|---|---|---|---|---|---|---|---|---|---|
||**7-BIT**|**8-BIT**|**7**|**6**|**5**|**4**|**3**|**2**|**1**|**0**|**R/W**|
|Rail4|0x5A|0xB4|0|1|0|1|1|0|1|0|0|
|Global4|0x5B|0xB6|0|1|0|1|1|0|1|1|0|
|Default|0x4F|0x9E|0|1|0|0|1|1|1|1|0|
|Example 1|0x40|0x80|0|1|0|0|0|0|0|0|0|
|Example 2|0x41|0x82|0|1|0|0|0|0|0|1|0|
|Disabled2,3|||1|0|0|0|0|0|0|0|0|
1 This table can be applied to the MFR_RAIL_ADDRESS _n_ commands, but not the MFR_ADDRESS command.
2A disabled value in one command does not disable the device, nor does it disable the global address.
3A disabled value in one command does not inhibit the device from responding to device addresses specified in other commands.
4It is not recommended to write the value 0x00, 0x0C (7-bit), 0x5A (7-bit), 0x5B (7-bit) or 0x7C(7-bit) to the MFR_CHANNEL_ADDRESS _n_ or the MFR_RAIL_ADDRESSn commands.
## **FAULT DETECTION AND HANDLING**
A variety of fault and warning reporting and handling mechanisms are available. Fault and warning detection capabilities include:
- n Input OV FAULT Protection and UV Warning
- n Average Input OC Warn
- n Output OV/UV Fault and Warn Protection
- n Output OC Fault and Warn Protection
- n Internal control Die and Internal Module Overtemperature Fault and Warn Protection
- n Internal Undertemperature Fault and Warn Protection
- n CML Fault (Communication, Memory or Logic)
- n External Fault Detection through the Bidirectional FAULT _n_ Pins
In addition, the LTM4682 can map any combination of fault indicators to their respective FAULT _n_ pin using the propagate FAULT _n_ response commands, MFR_FAULT_ PROPAGATE. Typical usage of a FAULT _n_ pin is as a driver for an external crowbar device, overtemperature alert,
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LTM4682
## **OPERATION**
overvoltage alert or as an interrupt to cause a microcontroller to poll the fault commands. Alternatively, the FAULT _n_ pins can be used as inputs to detect external faults downstream of the controller that requires an immediate response.
Any fault or warning event will always cause the ALERT nn_ pin to assert low unless the fault or warning is masked by the SMBALERT_MASK. The pin will remain asserted low until the CLEAR_FAULTS command is issued, the fault bit is written to a 1 or, bias power is cycled, or an MFR_RESET command is issued, or the RUN _n_ pins are toggled OFF/ ON, or the part is commanded OFF/ON through PMBus, or an alert response address (ARA) command operation is performed. The MFR_FAULT_PROPAGATE command determines if the FAULT _n_ pins are pulled low when a fault is detected.
Output and input fault event handling is controlled by the corresponding fault response byte as specified in Table 17 through Table 21. Shutdown recovery from these types of faults can either be autonomous or latched. For autonomous recovery, the faults are not latched, so if the fault conditions not present after the retry interval has elapsed, a new soft-start is attempted.
If the fault persists, the controller will continue to retry. The retry interval is specified by the MFR_RETRY_DELAY command and prevents damage to the regulator components by repetitive power cycling, assuming the fault condition itself is not immediately destructive. The MFR_ RETRY_DELAY must be greater than 120ms. It can not exceed 83.88 seconds.
## **Status Registers and ALERT Masking**
Figure 5 summarizes the internal LTM4682 status registers accessible by the PMBus command. These contain indications of various faults, warnings and other important operating conditions. As shown, the STATUS_BYTE and STATUS_WORD commands also summarize the contents of other status registers. See the PMBus Command Details section for specific information.
NONE OF THE ABOVE in the STATUS_BYTE indicates that one or more of the bits in the most-significant nibble of STATUS_WORD are also set.
In general, any asserted bit in a STATUS_x register also pulls the ALERT nn_ pin low. Once set, ALERT nn_ pin will remain low until one of the following occurs.
- n A CLEAR_FAULTS or MFR_RESET Command Is Issued
- n The Related Status Bit Is Written to a One
- n The Faulted Channel Is Properly Commanded Off and Back On
- n The LTM4682 Successfully Transmits Its Address During a PMBus ARA
- n Bias Power Is Cycled
With some exceptions, the SMBALERT_MASK command can be used to prevent the LTM4682 from asserting ALERT nn_ for bits in these registers on a bit-by-bit basis. These mask settings are promoted to STATUS_WORD and STATUS_BYTE in the same fashion as the status bits themselves. For example, if ALERT nn_ is masked for all bits in channel _n_ STATUS_VOUT, then ALERT nn_ is effectively masked for the VOUT bit in STATUS_WORD for PAGE _n_ . The BUSY bit in STATUS_BYTE also asserts ALERT nn_ low and cannot be masked. This bit can be set as a result of various internal interactions with PMBus communication. This fault occurs when a command is received that cannot be safely executed with one or both channels enabled. As discussed in the Application Information, BUSY faults can be avoided by polling MFR_ COMMON before executing some commands.
If masked faults occur immediately after power up, ALERT nn_ may still be pulled low because there has not been time to retrieve all of the programmed masking information from EEPROM.
Status information contained in MFR_COMMON and MFR_PADS can be used to further debug or clarify the contents of STATUS_BYTE or STATUS_WORD as shown, but the contents of these registers do not affect the state of the ALERT nn_ pin and may not directly influence bits in STATUS_BYTE or STATUS_WORD.
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LTM4682
## **OPERATION**
|**OPERATION**|**OPERATION**|**OPERATION**||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|||||||**STATUS_WORD**|||||||**STATUSMFRSPECIFIC**<br>**STATUS_INPUT**<br>7<br>6<br>5<br>4<br>3<br>2<br>1<br>0<br>VIN_OV Fault<br>(reads 0)<br>VIN_UV Warning<br>(reads 0)<br>Unit Off for Insuffcient VIN<br>(reads 0)<br>IIN_OC Warning<br>(reads 0)|||
|**STATUS_VOUT***<br><br>||||||1<br>1|5<br>|VOUT<br>I||||||||
|6||VOUT_OV Fault<br>VOUT_OV Warning||||1|3|OUT<br>INPUT||||||||
|||||||||||||||||
|5||VOUT_UV Warning||||1|2|MFR_SPECIFIC||||||||
|4||VOUT_UV Fault||||1|1|POWER_GOOD#||||||||
|3||VOUT_MAX Warning||||1|0|(reads 0)||||||||
|2||TON_MAX Fault||||9||(reads 0)||||||||
|1||TOFF_MAX Warning||||8||(reads 0)||||||||
|0||(reads 0)|||||**STATUS_BYTE**|||||||||
|||||||7||BUSY||||||||
|||||||6||OFF||||||||
|||||||5||VOUT_OV||||||||
|||||||4<br>||IOUT_OC<br>||||||||
|||||||2||(reads 0)<br>TEMPERATURE|||||**__**<br>7<br>Internal Temperature Fault|||
|||||||1||CML|||||6||Internal Temperature Warning|
|||||||0||NONE OF THE ABOVE|||||5||EEPROM CRC Error|
||||||||||||||4||Internal PLL Unlocked|
||||||||||||||3||Fault Log Present|
||||||||||||||2||VDD33UV or OV Fault|
||||||||||||||1||VOUTShort Cycled|
||||||||||||||0||FAULTPulled Low By External Device|
|||||||**MFR_INFO**||||||||||
|||||||15||Reserved||||||||
|||||||14||Reserved||||||||
|||||||13||Reserved||||||||
|||||||12||Reserved||||||||
|||||||11||Reserved||||||||
|||||||10||Reserved||||||||
|||||||9||Reserved||||||||
|||||||8||Reserved||||||||
|||||||7<br>||Reserved<br>||||||||
|||||||6||Reserved||||||||
|||||||5||Reserved||||||||
|||||||4||EEPROM ECC Status||||||||
|||||||3||Reserved||||||||
|||||||2||Reserved||||||||
|||||||1||Reserved||||||||
|||||||0||Reserved||||||||
|||||||||||||||||
|||||**DESCRIPTION**|||||**MASKABLE**|**GENERATESALERT**||**BIT CLEARABLE**||||
|||||General Fault or Warning Event|||||Yes|Yes||Yes||||
|||||General Non-Maskable Event|||||No|Yes||Yes||||
|||||Dynamic|||||No|No||No||||
|||||Status Derived from Other Bits|||||No|Not Directly||No||||
**Figure 5. LTM4682 Status Register Summary per Controller**
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LTM4682
## **OPERATION**
## **Mapping Faults to FAULT** _**n**_ **Pins**
Channel-to-channel fault (including channels from multiple LTM4682s) dependencies can be created by connecting FAULT _n_ pins together. In the event of an internal fault, one or more of the channels is configured to pull the bussed FAULT _n_ pins low. The other channels are then configured to shut down when the FAULT _n_ pins are pulled low. For autonomous group retry, the faulted channel is configured to let go of the FAULT _n_ pin(s) after a retry interval, assuming the original fault has cleared. All the channels in the group then begin a soft-start sequence. If the fault response is LATCH_OFF, the FAULT _n_ pin remains asserted low until either the RUN _n_ pin is toggled OFF/ON or the part is commanded OFF/ON. The toggling of the RUN _n_ either by the pin or OFF/ON command will clear faults associated with the channel. If it is desired to have all faults cleared when either the RUN _n_ , pin is toggled or, set bit 0 of MFR_CONFIG_ALL to a 1.
The status of all faults and warnings is summarized in the STATUS_WORD and STATUS_BYTE commands.
Additional fault detection and handling capabilities including power good pins and CRC protection.
## **Power Good Pins**
The PGOOD _n_ pins of the LTM4682 are connected to the open drains of internal MOSFETs. The MOSFETs turn on and pull the PGOOD _n_ pins low when the channel output voltage is not within the channel’s UV and OV voltage thresholds. During TON_DELAY and TON_RISE sequencing, the PGOOD _n_ pin is held low. The PGOOD _n_ pin is also pulled low when the respective RUN _n_ pin is low. The PGOOD _n_ pin response is deglitched by an internal 100µs digital filter. The PGOOD _n_ pin and PGOOD status may be different at times due to communication latency of up to 10µs.
## **CRC Protection**
The integrity of the NVM memory is checked after a power on reset. A CRC error will prevent the controller from leaving the inactive state. If a CRC error occurs, the CML bit is set in the STATUS_BYTE and STATUS_WORD commands, the appropriate bit is set in the STATUS_ MFR_SPECIFIC command, and the ALERT nn_ pin will be pulled low. NVM repair can be attempted by writing
the desired configuration to the controller and executing a STORE_USER_ALL command followed by a CLEAR_ FAULTS command.
The LTM4682 manufacturing section of the NVM is mirrored. If both copies are corrupted, the NVM CRC Fault in the STATUS_MFR_SPECIFIC command is set. If this bit remains set after being cleared by issuing a CLEAR_ FAULTS or writing a 1 to this bit, an irrecoverable internal fault has occurred. The user is cautioned to disable both output power supply rails associated with this specific part. There are no provisions for field repair of NVM faults in the manufacturing section.
## **SERIAL INTERFACE**
The LTM4682 serial interface is a PMBus-compliant subordinate device and can operate at any frequency between 10kHz and 400kHz. The address is configurable using either the NVM or an external resistor. In addition, the LTM4682 always responds to the global broadcast address of 0x5A (7-bit) or 0x5B (7-bit).
The serial interface supports the following protocols defined in the PMBus specifications: 1) send command, 2) write byte, 3) write word, 4) group, 5) read byte, 6) read word, 7) read block and 8) write block. All read operations will return a valid PEC if the PMBus main device requests it. If the PEC_REQUIRED bit is set in the MFR_ CONFIG_ALL command, the PMBus write operations will not be acted upon until a valid PEC has been received by the LTM4682.
## **Communication Protection**
PEC write errors (if PEC_REQUIRED is active), attempts to access unsupported commands, or writing invalid data to supported commands will result in a CML fault. The CML bit is set in the STATUS_BYTE and STATUS_WORD commands, the appropriate bit is set in the STATUS_CML command, and the ALERT pin is pulled low.
## **DEVICE ADDRESSING**
The LTM4682 offers four different types of addressing over the PMBus interface, specifically: 1) global, 2) device, 3) rail addressing and 4) alert response address (ARA).
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LTM4682
## **OPERATION**
Global addressing provides a means for the PMBus main device to address all LTM4682 devices on the bus. The LTM4682 global address is fixed 0x5A (7-bit) or 0xB4 (8-bit) and cannot be disabled. Commands sent to the global address act the same as if PAGE is set to a value of 0xFF. Commands sent are written to both channels simultaneously. Global command 0x5B (7-bit) or 0xB6 (8-bit) is paged and allows channel-specific command of all LTM4682 devices on the bus. Other Analog Devices IC types may respond at one or both of these global addresses. Reading from global addresses is strongly discouraged.
Device addressing provides the standard means of the PMBus main device communicating with a single instance of an LTM4682. The value of the device address is set by a combination of the ASEL nn_ configuration pin and the MFR_ADDRESS command. When this addressing means is used, the PAGE command determines the channel being acted upon. Device addressing can be disabled by writing a value of 0x80 to the MFR_ADDRESS.
Rail addressing provides a means for the bus main device to communicate simultaneously with all channels connected together to produce a single output voltage (PolyPhase). While similar to global addressing, the rail address can be dynamically assigned with the paged MFR_RAIL_ADDRESS command, allowing for any logical grouping of channels that might be required for reliable system control. Reading from rail addresses is also strongly discouraged.
All four means of PMBus addressing require the user to employ disciplined planning to avoid addressing conflicts. Communication to LTM4682 devices at global and rail addresses should be limited to command write operations.
## **RESPONSES TO VOUT AND IIN/IOUT FAULTS**
VOUT OV and UV conditions are monitored by comparators. The OV and UV limits are set in the following three ways.
- n As a Percentage of the VOUT if Using the Resistor Configuration Pins
## n By PMBus Command
The IIN and IOUT overcurrent monitors are performed by ADC readings and calculations. Thus, these values are based on average currents and can have a time latency of up to tCONVERT. The IOUT calculation accounts for the DCR and their temperature coefficient. The input current equals to the voltage measured across the RSENSE _n_ resistor divided by the resistor value as set with the MFR_ IIN_CAL_GAIN command. If this calculated input current exceeds the IN_OC_WARN_LIMIT, the ALERT nn_ pin is pulled low, and the IIN_OC_WARN bit is asserted in the STATUS_INPUT command.
The digital processor within the LTM4682 provides the ability to ignore the fault, shut down and latch off or shut down and retry indefinitely (hiccup). The retry interval is set in MFR_RETRY_DELAY and can be from 120ms to 83.88 seconds in 10µs increments. The shutdown for OV/UV and OC can be done immediately or after a userselectable deglitch time.
## **Output Overvoltage Fault Response**
A programmable overvoltage comparator (OV) guards against transient overshoots and long-term overvoltages at the output. In such cases, the top MOSFET is turned off, and the bottom MOSFET is turned on. However, the reverse output current is monitored while the device is in OV fault. When it reaches the limit, both top and bottom MOSFETs are turned off. The top and bottom MOSFETs will keep their state until the overvoltage condition is cleared, regardless of the PMBus VOUT_OV_FAULT_RESPONSE command byte value. This hardware-level fault response delay is typically 2µs from the overvoltage condition to BG asserted high. Using the VOUT_OV_FAULT_RESPONSE command, the user can select any of the following behaviors.
- n OV Pull-Down Only (OV Cannot Be Ignored)
- n Shut Down (Stop Switching) Immediately—Latch Off
- n Shut Down Immediately—Retry Indefinitely at the Time Interval Specified in MFR_RETRY_DELAY
Either the Latch Off or Retry fault responses can be deglitched in increments of (0-7) • 10µs. See Table 17.
- n In NVM, if Either Programmed at the Factory or Through the GUI
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LTM4682
## **OPERATION**
## **Output Undervoltage Response**
The response to an undervoltage comparator output can be the following:
- n Ignore
- n Shut Down Immediately—Latch Off
- n Shut Down Immediately—Retry Indefinitely at the Time Interval Specified in MFR_RETRY_DELAY.
The UV responses can be deglitched. See Table 18.
## **Peak Output Overcurrent Fault Response**
Due to the current mode control algorithm, peak output current across the inductor is always limited on a cycle-by-cycle basis. The value of the peak current limit is specified in the Electrical Characteristics table. The current limit circuit operates by limiting the COMP _n_ maximum voltage. Since internal DCR sensing is used, the COMP _n_ maximum voltage has a temperature dependency directly proportional to the TC of the DCR of the inductor. The LTM4682 automatically monitors the external temperature sensors and modifies the maximum allowed COMP _n_ to compensate for this term. The IOUT_OC_ FAULT_LIMIT section provides data points for IOUT Limiting, see IOUT_OC_FAULT_LIMIT.
The overcurrent fault processing circuitry can execute the following behaviors.
- n Current Limit Indefinitely
- n Shut Down Immediately—Latch Off
- n Shut Down Immediately—Retry Indefinitely at the Time Interval Specified in MFR_RETRY_DELAY.
The overcurrent responses can be deglitched in increments of (0-7) • 16ms. See Table 19.
## **RESPONSES TO TIMING FAULTS**
TON_MAX_FAULT_LIMIT is the time allowed for VOUT to rise and settle at start-up. The TON_MAX_FAULT_ LIMIT condition is predicated upon detecting the VOUT_UV_FAULT_LIMIT as the output is undergoing a SOFT_START sequence. The TON_MAX_FAULT_LIMIT time is started after TON_DELAY has been reached and a SOFT_START sequence is started. The resolution
of the TON_MAX_FAULT_LIMIT is 10µs. If the VOUT_ UV_FAULT_LIMIT is not reached within the TON_MAX_ FAULT_LIMIT time, the response of this fault is determined by the value of the TON_MAX_FAULT_RESPONSE command value. This response may be one of the following.
- n Ignore
- n Shut Down (Stop Switching) Immediately—Latch Off
- n Shut Down Immediately—Retry Indefinitely at the Time Interval Specified in MFR_RETRY_DELAY.
This fault response is not deglitched. A value of 0 in TON_MAX_FAULT_LIMIT means the fault is ignored. The TON_MAX_FAULT_LIMIT should be set longer than the TON_RISE time. It is recommended that TON_MAX_ FAULT_LIMIT always be set to a non-zero value, otherwise the output may never come up, and no flag will be set to the user. See Table 21.
## **RESPONSES TO VIN OV FAULTS**
VIN overvoltage is measured with the ADC. The response is naturally deglitched by the 100ms typical response time of the ADC. The fault responses include the following.
- n Ignore
- n Shut Down Immediately—Latch Off
- n Shut Down Immediately—Retry Indefinitely at the Time Interval Specified in MFR_RETRY_DELAY. See Table 21.
## **RESPONSES TO OT/UT FAULTS**
## **Internal Overtemperature Fault Response**
An internal temperature sensor protects against NVM damage. Above 85°C, no writes to NVM are recommended. Above 130°C, the internal overtemperature warns threshold is exceeded and the part disables the NVM, and does not re-enable until the temperature has dropped to 125°C. When the die temperature exceeds 160°C, the internal temperature fault response is enabled, and the PWM is disabled until the die temperature drops below 150°C. Temperature is measured by the ADC. Internal temperature faults cannot be ignored. Internal temperature limits cannot be adjusted by the user. See Table 20.
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LTM4682
## **OPERATION**
## **Overtemperature and Undertemperature Fault Response**
Four internal temperature sensors are used to sense the temperature of critical circuit elements like inductors and power MOSFETs on each channel. The OT_FAULT_RESPONSE and UT_FAULT_RESPONSE commands are used to determine the appropriate response to an overtemperature and under temperature conditions, respectively. If no external sense elements are used (not recommended), set the UT_FAULT_ RESPONSE to ignore—and set the UT_FAULT_LIMIT to 275°C. The fault responses are:
- n Ignore
- n Shut Down Immediately—Latch Off
- n Shut Down Immediately—Retry Indefinitely at the Time
Interval Specified in MFR_RETRY_DELAY. See Table 21.
## **RESPONSES TO INPUT OVERCURRENT AND OUTPUT UNDERCURRENT FAULTS**
Input overcurrent and output undercurrent are measured with the ADC. The fault responses are:
- n Ignore
- n Shut Down Immediately—Latch Off
- n Shut Down Immediately—Retry Indefinitely at the Time Interval Specified in MFR_RETRY_DELAY.
## **RESPONSES TO EXTERNAL FAULTS**
When either FAULT _n_ pin is pulled low, the OTHER bit is set in the STATUS_WORD command, the appropriate bit is set in the STATUS_MFR_SPECIFIC command, and the ALERT nn_ pin is pulled low. Responses are not deglitched. Each channel can be configured to ignore or shut down then retry in response to its FAULT _n_ pin going low by modifying the MFR_FAULT_RESPONSE command. To avoid the ALERT nn_ pin asserting low when FAULT _n_ is pulled low, assert bit 1 of MFR_CHAN_CONFIG, or mask the ALERT using the SMBALERT_MASK command.
## **FAULT LOGGING**
The LTM4682 has the fault logging capability. Data is logged into memory in the order shown in Table 23. The data is stored in a continuously updated buffer in RAM. When a fault event occurs, the fault log buffer is copied from the RAM buffer into the NVM. Fault logging is allowed at temperatures above 85°C; however, retention of 10 years is not guaranteed. When the die temperature exceeds 130°C, the fault logging is delayed until the die temperature drops below 125°C. The fault log data remains in NVM until a MFR_FAULT_LOG_CLEAR command is issued. Issuing this command re-enables the fault log feature. Before reenabling the fault log, be sure no faults are present, and a CLEAR_FAULTS command has been issued.
When the LTM4682 powers-up or exits its reset state, it checks the NVM for a valid fault log. If a valid fault log exists in NVM, the Valid Fault Log bit in the STATUS_ MFR_SPECIFIC command will be set, and an ALERT event will be generated. Also, fault logging will be blocked until the LTM4682 has received a MFR_FAULT_LOG_CLEAR command before fault logging will be re-enabled.
The information is stored in EEPROM in the event of any fault that disables the controller on either channel. A FAULT _n_ being externally pulled low will not trigger a fault logging event.
## **BUS TIMEOUT PROTECTION**
The LTM4682 implements a timeout feature to avoid persistent faults on the serial interface. The data packet timer begins at the first START event before the device address write byte. Data packet information must be completed within 30ms, or the LTM4682 will three-state the bus and ignore the given data packet. If more time is required, assert bit 3 of MFR_ CONFIG_ALL to allow typical bus timeouts of 255ms. Data packet information includes the device address byte write, command byte, repeat start event (if a read operation), device address byte read (if a read operation), all data bytes and the PEC byte if applicable.
The LTM4682 allows longer PMBus timeouts for blockread data packets. This timeout is proportional to the length of the block read. The additional block read timeout
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## **OPERATION**
applies primarily to the MFR_FAULT_LOG command. The timeout period defaults to 32ms.
The user is encouraged to use as high a clock rate as possible to maintain efficient data packet transfer between all devices sharing the serial bus interface. The LTM4682 supports the full PMBus frequency range from 10kHz to 400kHz.
## **SIMILARITY BETWEEN PMBus, SMBus AND I[2] C 2-WIRE INTERFACE**
The PMBus 2-wire interface is an incremental extension of the SMBus. The SMBus is built upon I[2] C with some minor differences in timing, DC parameters, and protocol. The PMBus/SMBus protocols are more robust than simple I[2] C byte commands because PMBus/SMBus provide timeouts to prevent persistent bus errors and optional packet error checking (PEC) to ensure data integrity. In general, a main device that can be configured for I[2] C communication can be used for PMBus communication with little or no change to hardware or firmware. Repeat start (restart) is not supported by all I[2] C controllers but is required for SMBus/PMBus reads. If a general-purpose I[2] C controller is used, check that repeat start is supported.
The LTM4682 supports the maximum SMBus clock speed of 100kHz and is compatible with the higher speed PMBus specification (between 100kHz and 400kHz) if MFR_COMMON polling or clock stretching is enabled. For robust communication and operation see the Note section in the PMBus Command Summary section. Clock stretching is enabled by asserting bit 1 of MFR_CONFIG_ALL.
For a description of the minor extensions and exceptions PMBus makes to SMBus, refer to PMBus Specification Part 1 Revision 1.2: Paragraph 5: Transport. To describe the differences between SMBus and I[2] C, refer to System Management Bus (SMBus) Specification Version 2.0: Appendix B—Differences Between SMBus and I[2] C.
## **PMBus SERIAL DIGITAL INTERFACE**
The LTM4682 communicates with a host (main device) using the standard PMBus serial bus interface. The PMBus Timing Diagram, Figure 6, shows the timing relationship of the signals on the bus. The two-bus lines,
SDA and SCL, must be high when the bus is not in use. External pull-up resistors or current sources are required on these lines. The LTM4682 is a subordinate device. The main device can communicate with the LTM4682 using the following formats.
- n Main Transmitter, Subordinate Receiver
- n Main Receiver, Subordinate Transmitter
The following PMBus protocols are supported.
- n Write Byte, Write Word, Send Byte
- n Read Byte, Read Word, Block Read, Block Write
- n Alert Response Address
Figure 7 to Figure 24 illustrate the aforementioned PMBus protocols. All transactions support PEC and GCP (group command protocol). The Block Read supports 255 bytes of returned data. For this reason, the PMBus timeout may be extended when reading the fault log.
Figure 7 is the key to the protocol diagrams in this section. PEC is optional. A value shown below a field in Figure 7 to Figure 24 is a mandatory value for that field.
The data formats implemented by PMBus are:
- n Main transmitter transmits to an subordinate receiver. The transfer direction, in this case, has not been changed.
- n Main device reads the subordinate immediately after the first byte. At the moment of the first acknowledgement (provided by the subordinate receiver), the main transmitter becomes a main receiver, and the subordinate receiver becomes the subordinate transmitter.
- n Combined format. During a change of direction within a transfer, the main device repeats both a start condition and the subordinate address but with the R/W bit reversed. In this case, the main receiver terminates the transfer by generating a NACK on the last byte of the transfer and a STOP condition.
See Figure 7 for a legend.
Handshaking features are included to ensure robust system communication. See the PMBus Communication and Command Processing subsection of the Applications Information section for further details.
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## **OPERATION**
**==> picture [442 x 117] intentionally omitted <==**
**----- Start of picture text -----**<br>
SDA<br>tf tLOW tr tSU(DAT) tf tHD(SDA) tSP tr tBUF<br>SCL<br>tHD(STA) tSU(STA) tSU(STO)<br>tHD(DAT) tHIGH 4682 F06<br>START REPEATED START STOP START<br>CONDITION CONDITION CONDITION CONDITION<br>**----- End of picture text -----**<br>
**Figure 6. PMBus Timing Diagram**
**Table 6. Abbreviations of Supported Data Formats**
||**PMBus**|**PMBus**|**ADI**<br>**TERMINOLOGY **|**DEFINITION**|**EXAMPLE**|
|---|---|---|---|---|---|
||**TERMINOLOGY**|**SPECIFICATION**<br>**REFERENCE**||||
|L11|Linear|Part II ¶7.1|Linear_5s_11s|Floating point 16-bit data: value = Y • 2N,<br>where N = b[15:11] and Y = b[10:0], both<br>two’s compliment binary integers.|b[15:0] = 0x9807 = 10011_000_0000_0111<br>value = 7 • 2–13= 854E-6|
|L16|Linear<br>VOUT_MODE|Part II ¶8.2|Linear_16u|Floating point 16-bit data: value = Y • 2–12,<br>where Y = b[15:0], an unsigned integer.|b[15:0] = 0x4C00 = 0100_1100_0000_0000<br>value = 19456 • 2–12= 4.75|
|CF|DIRECT|Part II ¶7.2|Varies|16-bit data with a custom format defined in<br>the PMBus Command Details section.|Often an unsigned or two’s compliment integer.|
|Reg|Register Bits|Part II ¶10.3|Reg|Per-bit meaning defined in the PMBus<br>Command Details section.|PMBus STATUS_BYTE command.|
|ASC|Text Characters|Part II ¶22.2.1|ASCII|ISO/IEC 8859-1[A05]|LTC(0x4C5443)|
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## **OPERATION**
## **FIGURE 7 TO FIGURE 24 PMBus PROTOCOLS**
S START CONDITION Sr REPEATED START CONDITION
- Rd READ (BIT VALUE OF 1)
- Wr WRITE (BIT VALUE OF 0)
- A ACKNOWLEDGE (THIS BIT POSITION MAY BE 0 FOR AN ACK OR 1 FOR A NACK)
- P STOP CONDITION
- PEC PACKET ERROR CODE
- MAIN TO SUBORDINATE
- SUBORDINATE TO MAIN
- ... CONTINUATION OF PROTOCOL 4682 F07
**Figure 7. PMBus Packet Protocol Diagram Element Key**
**==> picture [392 x 429] intentionally omitted <==**
**----- Start of picture text -----**<br>
1 7 1 1 1<br>S SUBORDINATE ADDRESS Rd/Wr A P<br>4682 F08<br>Figure 8. Quick Command Protocol<br>1 7 1 1 8 1 1<br>S SUBORDINATE ADDRESS Wr A COMMAND CODE A P<br>4682 F09<br>Figure 9. Send Byte Protocol<br>1 7 1 1 8 1 8 1 1<br>S SUBORDINATE ADDRESS Wr A COMMAND CODE A PEC A P<br>4682 F10<br>Figure 10. Send Byte Protocol with PEC<br>1 7 1 1 8 1 8 1 1<br>S SUBORDINATE ADDRESS Wr A COMMAND CODE A DATA BYTE A P<br> 4682 F11<br>Figure 11. Write Byte Protocol<br>1 7 1 1 8 1 8 1 8 1 1<br>S SUBORDINATE ADDRESS Wr A COMMAND CODE A DATA BYTE A PEC A P<br>4682 F12<br>Figure 12. Write Byte Protocol with PEC<br>1 7 1 1 8 1 8 1 8 1 1<br>S SUBORDINATE ADDRESS Wr A COMMAND CODE A DATA BYTE LOW A DATA BYTE HIGH A P<br>4682 F13<br>Figure 13. Write Word Protocol<br>1 7 1 1 8 1 8 1 8 1 8 1 1<br>S SUBORDINATE ADDRESS Wr A COMMAND CODE A DATA BYTE LOW A DATA BYTE HIGH A PEC A P<br>4682 F14<br>**----- End of picture text -----**<br>
## **Figure 14. Write Word Protocol with PEC**
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## **OPERATION**
**==> picture [507 x 237] intentionally omitted <==**
**----- Start of picture text -----**<br>
1 7 1 1 8 1 1 7 1 1 8 1 1<br>S SUBORDINATE ADDRESS Wr A COMMAND CODE A Sr SUBORDINATE ADDRESS Rd A DATA BYTE A P<br>4682 F15<br>Figure 15. Read Byte Protocol<br>1 7 1 1 8 1 1 7 1 1 8 1 1 1<br>S SUBORDINATE ADDRESS Wr A COMMAND CODE A Sr SUBORDINATE ADDRESS Rd A DATA BYTE A PEC A P<br>4682 F16<br>Figure 16. Read Byte Protocol with PEC<br>1 7 1 1 8 1 1 7 1 1 8 1 8 1 1<br>S SUBORDINATE ADDRESS Wr A COMMAND CODE A Sr SUBORDINATE ADDRESS Rd A DATA BYTE LOW A DATA BYTE HIGH A P<br>4682 F17<br>Figure 17. Read Word Protocol<br>1 7 1 1 8 1 1 7 1 1 8 1 8 1 8 1 1<br>S SUBORDINATE ADDRESS Wr A COMMAND CODE A Sr SUBORDINATE ADDRESS Rd A DATA BYTE LOW A DATA BYTE HIGH A PEC A P<br>4682 F18<br>**----- End of picture text -----**<br>
**Figure 18. Read Word Protocol with PEC**
|1||7|||1|1||||8|||1|1||||7||||1||1||||8||1||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|S|SUBORDINATEADDRESS||||Wr|A||COMMAND CODE|||||A|Sr||SUBORDINATEADDRESS||||||Rd||A||BYTE||COUNT = N||A|…|
||||||8||||1|||8||||1|…||8|||1||1||||||||
|||||DATA BYTE|||1||A||DATA BYTE 2|||||A|…|DATA BYTE N||||A||P||||||||
|||||||||||||||||||||||4682 F19||||||||||
||||||||||**Figure 19. Block**||||||**Read**|||**Protocol**||||||||||||||
|1||7|||1|1||||8|||1|1||||7||||1||1||||8||1||
|S|SUBORDINATEADDRESS||||Wr|A||COMMAND CODE|||||A|Sr||SUBORDINATEADDRESS||||||Rd||A||BYTE COUNT = N||||A|…|
|||8|||1||||8|||1|…||||8||1|||8|||||1|1||||
|||DATA BYTE||1|A||DATA BYTE||||2|A|…||DATA BYTE N||||A|||PEC|||||A|P||||
||||||||||||||||||||||||||||4682 F20|||||
**Figure 20. Block Read Protocol with PEC**
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## **OPERATION**
**==> picture [325 x 127] intentionally omitted <==**
**----- Start of picture text -----**<br>
1 7 1 1 8 1 8 1 8 1<br>S SUBORDINATE ADDRESS Wr A COMMAND CODE A BYTE COUNT = M A DATA BYTE 1 A …<br>8 1 8 1<br>DATA BYTE 2 A … DATA BYTE M A …<br>1 7 1 1 8 1 8 1 1<br>Sr SUBORDINATEADDRESS Rd A BYTE COUNT = N A DATA BYTE 1 A …<br>8 1 … 8 1 1<br>DATA BYTE 2 A … DATA BYTE N A P<br>4682 F21<br>**----- End of picture text -----**<br>
**Figure 21. Block Write – Block Read Process Call**
**==> picture [326 x 126] intentionally omitted <==**
**----- Start of picture text -----**<br>
1 7 1 1 8 1 8 1 8 1<br>S SUBORDINATE ADDRESS Wr A COMMAND CODE A BYTE COUNT = M A DATA BYTE 1 A …<br>8 1 8 1<br>DATA BYTE 2 A … DATA BYTE M A …<br>1 7 1 1 8 1 8 1 1<br>Sr SUBORDINATE ADDRESS Rd A BYTE COUNT = N A DATA BYTE 1 A …<br>8 1 … 8 1 8 1 1<br>DATA BYTE 2 A … DATA BYTE N A PEC A P<br>4682 F22<br>**----- End of picture text -----**<br>
**Figure 22. Block Write – Block Read Process Call with PEC**
**==> picture [170 x 35] intentionally omitted <==**
**----- Start of picture text -----**<br>
1 7 1 1 8 1 1<br>ALERT RESPONSE<br>S Rd A DEVICE ADDRESS A P<br>ADDRESS<br>4682 F23<br>**----- End of picture text -----**<br>
**Figure 23. Alert Response Address Protocol**
**==> picture [236 x 35] intentionally omitted <==**
**----- Start of picture text -----**<br>
1 7 1 1 8 1 8 1 1<br>ALERT RESPONSE<br>S Rd A DEVICE ADDRESS A PEC A P<br>ADDRESS<br>4682 F24<br>**----- End of picture text -----**<br>
**Figure 24. Alert Response Address Protocol with PEC**
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## **PMBus COMMAND SUMMARY**
## **PMBus COMMANDS**
Table 7 lists supported PMBus commands and manufacturer-specific commands. A complete description of these commands can be found in the PMBus Power System Management Protocol Specification – Part II – Revision 1.2. Users are encouraged to reference this specification. Exceptions or manufacturer-specific implementations are listed in Table 7. Floating point values listed in the DEFAULT VALUE column are either Linear 16-bit Signed (PMBus Section 8.3.1) or Linear_5s_11s (PMBus Section 7.1) format, whichever is appropriate for the command. All commands from 0xD0 through 0xFF not listed in Table 7 are implicitly reserved by the manufacturer. Users should avoid blind writes within this range of commands to avoid the undesired operation of the part. All commands from 0x00 through 0xCF not listed in Table 7 are implicitly not
supported by the manufacturer. Attempting to access nonsupported or reserved commands may result in a CML command fault event. All output voltage settings and measurements are based on the VOUT_MODE setting of 0x14. This translates to an exponent of 2[–12] .
If PMBus commands are received faster than they are being processed, the part may become too busy to handle new commands. In these circumstances, the part follows the protocols defined in the PMBus Specification v1.2, Part II, Section 10.8.7, to communicate that it is busy. The part includes handshaking features to eliminate busy errors and simplify error-handling software while ensuring robust communication and system behavior. See the subsection titled PMBus Communication and Command Processing in the Applications Information section for further details.
**Table 7. PMBus Commands Summary (Note: The Data Format Abbreviations Are Detailed in Table 8)**
|**COMMAND NAME**|**CMD**<br>**CODE**|**DESCRIPTION**|**TYPE**|**PAGED**|**DATA**<br>**FORMAT**|**UNITS**|**NVM**|**DEFAULT**<br>**VALUE**|PAGE|
|---|---|---|---|---|---|---|---|---|---|
|PAGE|0x00|Provides integration with multi-page<br>PMBus devices.|R/W Byte|N|Reg|||0x00|81|
|OPERATION|0x01|Operating mode control. On/off, margin<br>high and margin low.|R/W Byte|Y|Reg||Y|0x80|85|
|ON_OFF_CONFIG|0x02|RUN pin and PMBus bus on/off command<br>configuration.|R/W Byte|Y|Reg||Y|0x1E|85|
|CLEAR_FAULTS|0x03|Clear any fault bits that have been set.|Send Byte|N||||NA|110|
|PAGE_PLUS_WRITE|0x05|Write a command directly to a<br>specified page.|W Block|N|||||81|
|PAGE_PLUS_READ|0x06|Read a command directly from a<br>specified page.|Block R/W|N|||||81|
|WRITE_PROTECT|0x10|Level of protection provided by the device<br>against accidental changes.|R/W Byte|N|Reg||Y|0x00|82|
|STORE_USER_ALL|0x15|Store user operating memory to EEPROM.|Send Byte|N||||NA|120|
|RESTORE_USER_ALL|0x16|Restore user operating memory from<br>EEPROM.|Send Byte|N||||NA|120|
|CAPABILITY|0x19|Summary of PMBus optional communication<br>protocols supported by this device.|R Byte|N|Reg|||0xB0|109|
|SMBALERT_MASK|0x1B|MaskALERTactivity.|Block R/W|Y|Reg||Y|See CMD|110|
|VOUT_MODE|0x20|Output voltage format and exponent (2–12).|R Byte|Y|Reg|||2–12<br>0x14|91|
|VOUT_COMMAND|0x21|Nominal output voltage set point.|R/W Word|Y|L16|V|Y|0.75<br>0x0C00|92|
|VOUT_MAX|0x24|The upper limit on the commanded output<br>voltage, including VOUT_MARGIN_HI.|R/W Word|Y|L16|V|Y|1.5<br>0x1800|91|
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## **PMBus COMMAND SUMMARY**
|**COMMAND NAME**|**CMD**<br>**CODE**|**DESCRIPTION**|**TYPE**|**PAGED**|**DATA**<br>**FORMAT**|**UNITS**|**NVM**|**DEFAULT**<br>**VALUE**|PAGE|
|---|---|---|---|---|---|---|---|---|---|
|VOUT_MARGIN_HIGH|0x25|Margin high output voltage set point. It<br>must be greater than VOUT_COMMAND.|R/W Word|Y|L16|V|Y|0.80<br>0x0CCD|92|
|VOUT_MARGIN_LOW|0x26|Margin low output voltage set point. It<br>must be less than VOUT_COMMAND.|R/W Word|Y|L16|V|Y|0.70<br>0x0B33|92|
|VOUT_TRANSITION_RATE|0x27|Rate the output changes when VOUT is<br>commanded to a new value.|R/W Word|Y|L11|V/ms|Y|0.25<br>0xD010|98|
|FREQUENCY_SWITCH|0x33|Switching frequency of the controller.|R/W Word|N|L11|kHz|Y|575kHz<br>0x023F|89|
|VIN_ON (SVIN_XX)|0x35|Input voltage at which the unit should start<br>power conversion.|R/W Word|N|L11|V|Y|4.75<br>0xD130|90|
|VIN_OFF (SVIN_XX)|0x36|Input voltage at which the unit should stop<br>power conversion.|R/W Word|N|L11|V|Y|4.5<br>0xD120|90|
|VOUT_OV_FAULT_LIMIT|0x40|Output overvoltage fault limit.|R/W Word|Y|L16|V|Y|0.85<br>0x0D9A|91|
|VOUT_OV_FAULT_<br>RESPONSE|0x41|Action is to be taken by the device when an<br>output overvoltage fault is detected.|R/W Byte|Y|Reg||Y|0xB8|100|
|VOUT_OV_WARN_LIMIT|0x42|Output overvoltage warning limit.|R/W Word|Y|L16|V|Y|0.825<br>0xD33|91|
|VOUT_UV_WARN_LIMIT|0x43|Output undervoltage warning limit.|R/W Word|Y|L16|V|Y|0.675<br>0x0ACD|92|
|VOUT_UV_FAULT_LIMIT|0x44|Output undervoltage fault limit.|R/W Word|Y|L16|V|Y|0.65<br>0x0A66|92|
|VOUT_UV_FAULT_<br>RESPONSE|0x45|Action is to be taken by the device when an<br>output undervoltage fault is detected.|R/W Byte|Y|Reg||Y|0xB8|101|
|IOUT_OC_FAULT_LIMIT|0x46|Output overcurrent fault limit.|R/W Word|Y|L11|A|Y|42.00<br>0xE2A0|94|
|IOUT_OC_FAULT_RESPONSE|0x47|Action is to be taken by the device when an<br>output overcurrent fault is detected.|R/W Byte|Y|Reg||Y|0x00|103|
|IOUT_OC_WARN_LIMIT|0x4A|Output overcurrent warning limit.|R/W Word|Y|L11|A|Y|35.0<br>0xE918|95|
|OT_FAULT_LIMIT|0x4F|External overtemperature fault limit.|R/W Word|Y|L11|C|Y|128.0<br>0xF200|96|
|OT_FAULT_RESPONSE|0x50|Action is to be taken by the device when an<br>external overtemperature fault is detected.|R/W Byte|Y|Reg||Y|0xB8|105|
|OT_WARN_LIMIT|0x51|External overtemperature warning limit.|R/W Word|Y|L11|C|Y|125.0<br>0xEBE8|96|
|UT_FAULT_LIMIT|0x53|External undertemperature fault limit.|R/W Word|Y|L11|C|Y|–45.0<br>0xE530|97|
|UT_FAULT_RESPONSE|0x54|Action is to be taken by the device when<br>an external undertemperature fault is<br>detected.|R/W Byte|Y|Reg||Y|0xB8|105|
|VIN_OV_FAULT_LIMIT|0x55|Input supply overvoltage fault limit.|R/W Word|N|L11|V|Y|16.8<br>0xDA1A|89|
|VIN_OV_FAULT_RESPONSE|0x56|Action is to be taken by the device when an<br>input overvoltage fault is detected.|R/W Byte|Y|Reg||Y|0x80|100|
|VIN_UV_WARN_LIMIT|0x58|Input supply undervoltage warning limit.|R/W Word|N|L11|V|Y|4.65<br>0xD12A|90|
|IIN_OC_WARN_LIMIT|0x5D|Input supply overcurrent warning limit.|R/W Word|N|L11|A|Y|10.0<br>0xD280|95|
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LTM4682
## **PMBus COMMAND SUMMARY**
|**COMMAND NAME**|**CMD**<br>**CODE**|**DESCRIPTION**|**TYPE**|**PAGED**|**DATA**<br>**FORMAT**|**UNITS**|**NVM**|**DEFAULT**<br>**VALUE**|PAGE|
|---|---|---|---|---|---|---|---|---|---|
|TON_DELAY|0x60|Time from RUN and/or Operation on to<br>output rail turn-on.|R/W Word|Y|L11|ms|Y|0.0<br>0x8000|97|
|TON_RISE|0x61|Time from when the output starts to rise<br>until the output voltage reaches the VOUT<br>commanded value.|R/W Word|Y|L11|ms|Y|3.0<br>0xC300|97|
|TON_MAX_FAULT_LIMIT|0x62|Maximum time from the start of<br>TON_RISE for VOUTto cross the<br>VOUT_UV_FAULT_LIMIT.|R/W Word|Y|L11|ms|Y|5.0<br>0xCA80|98|
|TON_MAX_FAULT_<br>RESPONSE|0x63|Action is to be taken by the device when a<br>TON_MAX_FAULT event is detected.|R/W Byte|Y|Reg||Y|0xB8|103|
|TOFF_DELAY|0x64|Time from RUN and/or Operation off to the<br>start of TOFF_FALL ramp.|R/W Word|Y|L11|ms|Y|0.0<br>0x8000|98|
|TOFF_FALL|0x65|Time from when the output starts to fall<br>until the output reaches zero volts.|R/W Word|Y|L11|ms|Y|3.0<br>0xC300|98|
|TOFF_MAX_WARN_LIMIT|0x66|Maximum allowed time, after TOFF_FALL<br>is completed, for the unit to decay below<br>12.5%.|R/W Word|Y|L11|ms|Y|0<br>0x8000|99|
|STATUS_BYTE|0x78|One byte summary of the unit’s fault<br>condition.|R/W Byte|Y|Reg|||NA|111|
|STATUS_WORD|0x79|Two byte summary of the unit’s fault<br>condition.|R/W Word|Y|Reg|||NA|112|
|STATUS_VOUT|0x7A|Output voltage fault and warning status.|R/W Byte|Y|Reg|||NA|112|
|STATUS_IOUT|0x7B|Output current fault and warning status.|R/W Byte|Y|Reg|||NA|113|
|STATUS_INPUT|0x7C|Input supply fault and warning status.|R/W Byte|N|Reg|||NA|113|
|STATUS_TEMPERATURE|0x7D|External temperature fault and warning<br>status for READ_TEMERATURE_1.|R/W Byte|Y|Reg|||NA|114|
|STATUS_CML|0x7E|Communication and memory fault and<br>warning status.|R/W Byte|N|Reg|||NA|114|
|STATUS_MFR_SPECIFIC|0x80|Manufacturer-specific fault and state<br>information.|R/W Byte|Y|Reg|||NA|115|
|READ_VIN|0x88|Measured input supply voltage.|R Word|N|L11|V||NA|117|
|READ_IIN|0x89|Measured input supply current.|R Word|N|L11|A||NA|117|
|READ_VOUT|0x8B|Measured output voltage.|R Word|Y|L16|V||NA|117|
|READ_IOUT|0x8C|Measured output current.|R Word|Y|L11|A||NA|117|
|READ_TEMPERATURE_1|0x8D|External temperature sensor temperature.<br>This is the value used for all temperature-<br>related processing, including<br>IOUT_CAL_GAIN.|R Word|Y|L11|C||NA|117|
|READ_TEMPERATURE_2|0x8E|Internal die junction temperature. Does not<br>affect any other commands.|R Word|N|L11|C||NA|117|
|READ_FREQUENCY|0x95|Measured PWM switching frequency.|R Word|Y|L11|Hz||NA|117|
|READ_POUT|0x96|Measured output power|R Word|Y|L11|W||N/A|117|
|READ_PIN|0x97|Calculated input power|R Word|Y|L11|W||N/A|118|
|PMBus_REVISION|0x98|PMBus revision is supported by this<br>device. The current revision is 1.2.|R Byte|N|Reg|||0x22|109|
|MFR_ID|0x99|The manufacturer ID of the LTM4682 in<br>ASCII.|R String|N|ASC|||LTC|109|
|MFR_MODEL|0x9A|Manufacturer part number is in ASCII.|R String|N|ASC||||109|
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## LTM4682
## **PMBus COMMAND SUMMARY**
|**COMMAND NAME**|**CMD**<br>**CODE**|**DESCRIPTION**|**TYPE**|**PAGED**|**DATA**<br>**FORMAT**|**UNITS**|**NVM**|**DEFAULT**<br>**VALUE**|PAGE|
|---|---|---|---|---|---|---|---|---|---|
|MFR_VOUT_MAX|0xA5|Maximum allowed output voltage including<br>VOUT_OV_FAULT_LIMIT.|R Word|Y|L16|V||1.5<br>0x1800|93|
|MFR_PIN_ACCURACY|0xAC|Returns the accuracy of the READ_PIN<br>command.|R Byte|N|%|||5.0%|118|
|USER_DATA_00|0xB0|OEM RESERVED. Typically used for part<br>serialization.|R/W Word|N|Reg||Y|NA|109|
|USER_DATA_01|0xB1|Manufacturer reserved for LTpowerPlay.|R/W Word|Y|Reg||Y|NA|109|
|USER_DATA_02|0xB2|OEM RESERVED. Typically used for part<br>serialization|R/W Word|N|Reg||Y|NA|109|
|USER_DATA_03|0xB3|An NVM word is available for the user.|R/W Word|Y|Reg||Y|0x0000|109|
|USER_DATA_04|0xB4|An NVM word is available for the user.|R/W Word|N|Reg||Y|0x0000|109|
|MFR_EE_UNLOCK|0xBD|Contact factory.|||||||125|
|MFR_EE_ERASE|0xBE|Contact factory.|||||||125|
|MFR_EE_DATA|0xBF|Contact factory.|||||||125|
|MFR_CHAN_CONFIG|0xD0|Configuration bits that are channel-specific.|R/W Byte|Y|Reg||Y|0x1D|83|
|MFR_CONFIG_ALL|0xD1|General configuration bits.|R/W Byte|N|Reg||Y|0x21|84|
|MFR_FAULT_PROPAGATE|0xD2|Configuration that determines which faults<br>are propagated to theFAULTpin.|R/W Word|Y|Reg||Y|0x6993|106|
|MFR_PWM_COMP|0xD3|PWM loop compensation configuration|R/W Byte|Y|Reg||Y|0x76|87|
|MFR_PWM_MODE|0xD4|Configuration for the PWM engine.|R/W Byte|Y|Reg||Y|0xC7|86|
|MFR_FAULT_RESPONSE|0xD5|Action is to be taken by the device when<br>theFAULTpin is externally asserted low.|R/W Byte|Y|Reg||Y|0xC0|108|
|MFR_OT_FAULT_RESPONSE|0xD6|Action is to be taken by the device when an<br>internal overtemperature fault is detected.|R Byte|N|Reg|||0xC0|104|
|MFR_IOUT_PEAK|0xD7|Report the maximum measured<br>value of READ_IOUT since the last<br>MFR_CLEAR_PEAKS.|R Word|Y|L11|A||NA|118|
|MFR_ADC_CONTROL|0xD8|ADC telemetry parameter selected for<br>repeated fast ADC read back.|R/W Byte|N|Reg|||0x00|119|
|MFR_RETRY_DELAY|0xDB|Retry interval duringFAULTretry mode.|R/W Word|Y|L11|ms|Y|250.0<br>0xF3E8|99|
|MFR_RESTART_DELAY|0xDC|The minimum time the RUN pin is held low<br>by the LTM4682.|R/W Word|Y|L11|ms|Y|150.0<br>0xF258|99|
|MFR_VOUT_PEAK|0xDD|The maximum measured value of READ_<br>VOUT since the last MFR_CLEAR_PEAKS.|R Word|Y|L16|V||NA|118|
|MFR_VIN_PEAK|0xDE|The maximum measured value of READ_<br>VIN since the last MFR_CLEAR_PEAKS.|R Word|N|L11|V||NA|118|
|MFR_TEMPERATURE_1_PEAK|0xDF|The maximum measured value of external<br>Temperature (READ_TEMPERATURE_1)<br>since the last MFR_CLEAR_PEAKS.|R Word|Y|L11|C||NA|118|
|MFR_READ_IIN_PEAK|0xE1|The maximum measured value of<br>READ_IIN command since the last<br>MFR_CLEAR_PEAKS.|R Word|N|L11|A||NA|118|
|MFR_CLEAR_PEAKS|0xE3|Clears all peak values.|Send Byte|N||||NA|111|
|MFR_READ_ICHIP|0xE4|Measured supply current of the SVINpin.|R Word|N|L11|A||NA|119|
|MFR_PADS|0xE5|Digital status of the I/O pads.|R Word|N|Reg|||NA|115|
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LTM4682
## **PMBus COMMAND SUMMARY**
|**COMMAND NAME**|**CMD**<br>**CODE**|**DESCRIPTION**|**TYPE**|**PAGED**|**DATA**<br>**FORMAT**|**UNITS**|**NVM**|**DEFAULT**<br>**VALUE**|PAGE|
|---|---|---|---|---|---|---|---|---|---|
|MFR_ADDRESS|0xE6|Sets the 7-bit I2C address byte, Ch 0 and 1.|R/W Byte|N|Reg||Y|0x4F|83|
|MFR_ADDRESS|0xE6|Sets the 7-bit I2C address byte, Ch 2 and 3.|R/W Byte|N|Reg||Y|0x4E|83|
|MFR_SPECIAL_ID|0xE7|Manufacturer code representing the<br>LTM4682 and revision.|R Word|N|Reg|||0x418X|109|
|MFR_IIN_CAL_GAIN|0xE8|The resistance value of the input current<br>sense element in mΩ.|R/W Word|N|L11|mΩ|Y|2.0<br>0xC200|95|
|MFR_FAULT_LOG_STORE|0xEA|Command a transfer of the fault log from<br>RAM to EEPROM.|Send Byte|N||||NA|121|
|MFR_INFO|0x|Contact factory.|||||||125|
|MFR_IOUT_CAL_GAIN|0xDA|SET AT FACTORY. Typical 0.36mΩ.|R Word|Y|L11|mΩ||0.360<br>Typical<br>0xD017|93|
|MFR_FAULT_LOG_CLEAR|0xEC|Initialize the EEPROM block reserved for<br>fault logging.|Send Byte|N||||NA|125|
|MFR_FAULT_LOG|0xEE|Fault log data bytes.|R Block|N|Reg||Y|NA|121|
|MFR_COMMON|0xEF|Manufacturer status bits that are common<br>across multiple ADI chips.|R Byte|N|Reg|||NA|116|
|MFR_COMPARE_USER_ALL|0xF0|Compares current command contents<br>with NVM.|Send Byte|N||||NA|120|
|MFR_TEMPERATURE_2_PEAK|0xF4|Peak internal die temperature since the last<br>MFR_CLEAR_PEAKS.|R Word|N|L11|C||NA|119|
|MFR_PWM_CONFIG|0xF5|Set numerous parameters for the DC/DC<br>controller, including phasing.|R/W Byte|N|Reg||Y|0x10|88|
|MFR_IOUT_CAL_GAIN_TC|0xF6|Temperature coefficient of the current<br>sensing element.|R/W Word|Y|CF|ppm/<br>˚C|Y|3900<br>0x0F3C|93|
|MFR_RVIN_CAL_GAIN|0xF7|The resistance value of the VINpin filter<br>element in mΩ.|R/W Word|N|L11|mΩ|Y|1000<br>0x03E8|90|
|MFR_TEMP_1_GAIN|0xF8|Sets the slope of the external temperature<br>sensor.|R/W Word|Y|CF||Y|0.995<br>0x3FAE|96|
|MFR_TEMP_1_OFFSET|0xF9|Sets the offset of the external temperature<br>sensor with respect to –273.1°C|R/W Word|Y|L11|C|Y|0.0<br>0x8000|96|
|MFR_RAIL_ADDRESS|0xFA|Common address for PolyPhase outputs to<br>adjust common parameters.|R/W Byte|Y|Reg||Y|0x80|83|
|MFR_REAL_TIME|0xFB|48-bit share-clock counter value.|R Block|N|CF|||NA|122|
|MFR_RESET|0xFD|Commanded reset without requiring a<br>power down.|Send Byte|N||||NA|85|
Note 1: Commands indicated with Y in the NVM column indicate that these commands are stored and restored using the STORE_USER_ALL and RESTORE_USER_ALL commands, respectively.
Note 2: Commands with a default value of NA indicate not applicable. Commands with a default value of FS indicate factory set on a per part basis.
Note 3: The LTM4682 contains additional commands not listed in Table 7. Reading these commands is harmless to the operation of the IC; however, the contents and meaning of these commands can change without notice.
Note 4: Some of the unpublished commands are read-only and will generate a CML bit 6 fault if written.
Note 5: Writing to commands not published in Table 7 is not permitted.
Note 6: The user should not assume compatibility of commands between different parts based upon command names. Always refer to the manufacturer’s data sheet for each part for a complete definition of a command’s function. Analog Devices strives to keep command functionality compatible between all Analog Devices devices. Differences may occur to address specific product requirements.
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LTM4682
## **PMBus COMMAND SUMMARY**
## **Table 8. Data Format Abbreviations**
|L11|Linear_5s_11s|PMBus data field b[15:0]<br>Value = Y • 2N<br>where N = b[15:11] is a 5-bit two’s complement integer and Y = b[10:0] is an 11-bit two’s complement integer.<br>Example:<br>For b[15:0] = 0x9807 = ‘b10011_000_0000_0111<br>Value = 7 • 2–13= 854 • 10–6<br>From PMBus Spec Part II: Paragraph 7.1|
|---|---|---|
|L16|Linear_16u|PMBus data field b[15:0]<br>Value = Y • 2N<br>where Y = b[15:0] is an unsigned integer and N = VOUT_MODE_PARAMETER is a 5-bit two’s complement exponent that is<br>hardwired to –12 decimal<br>Example:<br>For b[15:0] = 0x4C00 = ‘b0100_1100_0000_0000<br>Value = 19456 • 2–12= 4.75 From PMBus Spec Part II: Paragraph 8.2|
|Reg|Register|PMBus data field b[15:0] or b[7:0].<br>Bit field meaning is defined in the PMBus Command Details section.|
|L16|Integer Word|PMBus data field b[15:0]<br>Value = Y<br>where Y = b[15:0] is a 16-bit unsigned integer<br>Example:<br>For b[15:0] = 0x9807 = ‘b1001_1000_0000_0111<br>Value = 38919(decimal)|
|CF|Custom Format|Value is defined in the PMBus Command Details section.<br>This is often an unsigned or two’s complement integer scaled by an MFR specific constant.|
|ASC|ASCII Format|A variable length string of text characters conforming to ISO/IEC 8859-1 standard.|
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LTM4682
## **APPLICATIONS INFORMATION**
## **VIN TO VOUT STEP-DOWN RATIOS**
There are restrictions in the maximum VIN and VOUT stepdown ratio that can be achieved for a given input voltage. Each output of the LTM4682 is capable of the 95% duty cycle at 500kHz, but the VIN to VOUT minimum dropout is still a function of its load current and will limit output current capability related to the high duty cycle on the topside switch.
Minimum on-time t is another consideration in ON(MIN) operating at a specified duty cycle while operating at a certain frequency due to the fact that tON(MIN) < D/fSW, where D is the duty cycle and fSW is the switching frequency. tON(MIN) is specified in the electrical parameters as 85ns. See Note 6 in the Electrical Characteristics section for output current guidelines.
## **INPUT CAPACITORS**
The LTM4682 module should be connected to a low AC impedance DC source. For the regulator input, four 22µF input ceramic capacitors are used to handle the RMS ripple current. A 47µF to 150µF surface mount aluminum electrolytic bulk capacitor can be used for more input bulk capacitance. This bulk input capacitor is only needed if the input source impedance is compromised by long inductive leads, traces or not enough source capacitance. If low impedance power planes are used, then this bulk capacitor is not needed.
For a buck converter, the switching duty-cycle can be estimated as:
**==> picture [56 x 30] intentionally omitted <==**
Without considering the inductor current ripple, for each output, the RMS current of the input capacitor can be estimated as:
**==> picture [183 x 31] intentionally omitted <==**
In the above equation, η % is the estimated efficiency of the power module. The bulk capacitor can be a switcher-rated electrolytic aluminum capacitor, or a polymer capacitor.
Application Note 77 can be utilized to help calculate ripple current cancellation for multiphase applications.
## **OUTPUT CAPACITORS**
The LTM4682 is designed for low output voltage ripple noise and good transient response. The bulk output capacitors defined as COUT are chosen with low enough effective series resistance (ESR) to meet the output voltage ripple and transient requirements. The COUT can be a low ESR tantalum capacitor, a low ESR polymer or a ceramic capacitor. The typical output capacitance range for each output is from 400µF to 1000µF. Additional output filtering may be required by the system designer, if further reduction of output ripple or dynamic transient spikes is required. Table 13 shows a matrix of different output voltages and output capacitors to minimize the voltage droop and overshoot during a 10A to 20A step, with 10A/µs transient on each channel. Table 13 optimizes total equivalent ESR and total bulk capacitance to optimize the transient performance. Stability criteria are considered in the Table 13 matrix, and the LTpowerCAD design tool will be provided for stability analysis. Multiphase operation reduces effective output ripple as a function of the number of phases. Application Note 77 discusses this noise reduction versus output ripple current cancellation, but the output capacitance should be considered carefully as a function of stability and transient response. The LTpowerCAD design tool can calculate the output ripple reduction as the number of implemented phases increases by N times. A small value 10Ω resistor can be placed in series from VOUT _n_ to the VOSNS0[+] pin to allow for a bode plot analyzer to inject a signal into the control loop and validate the regulator stability. The LTM4682’s stability compensation can be adjusted using two external capacitors (COMP _n_ a, COMP _n_ b), and the MFR_PWM_COMP commands.
## **LIGHT LOAD CURRENT OPERATION**
The LTM4682 has two modes of operation including high efficiency, discontinuous conduction mode or forced continuous conduction mode. The mode of operation is configured by bit 0 of the MFR_PWM_MODE _n_ command (discontinuous conduction is always the start-up mode, forced continuous is the default running mode).
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## **APPLICATIONS INFORMATION**
If a channel is enabled for discontinuous mode operation, the inductor current is not allowed to reverse. The reverse current comparator, IREV, turns off the bottom MOSFET (MB _n_ ) just before the inductor current reaches zero, preventing it from reversing and going negative. Thus, the controller can operate in discontinuous (pulseskipping) operation. In forced continuous operation, the inductor current is allowed to reverse at light loads or under large transient conditions. The peak inductor current is determined solely by the voltage on the COMP _n_ pin. In this mode, the efficiency at light loads is lower than in discontinuous mode operation. However, continuous mode exhibits lower output ripple and less interference with audio circuitry. Forced continuous conduction mode may result in reverse inductor current, which can cause the input supply to boost. The VIN_OV_FAULT_LIMIT can detect this (if SVIN nn_ is connected to VIN01 and/or VIN23) and turn off the offending channel. However, this fault is based on an ADC read and can nominally take up to 100ms to detect. If there is a concern about the input supply boosting, keep the part in discontinuous conduction operation.
## **SWITCHING FREQUENCY AND PHASE**
The switching frequency of the LTM4682’s channels is established by its analog phase-locked-loop (PLL) locking on to the clock present at the module’s SYNC nn_ pin. The clock waveform on the SYNC nn_ pin can be generated by the LTM4682’s internal circuitry when an external pull-up resistor to 3.3V (e.g., VDD33) is provided, in combination with the LTM4682 control IC’s FREQUENCY_SWITCH command being set to one of the following supported values: 250kHz, 350kHz, 425kHz, 500kHz, 575kHz, 650kHz, and 750kHz. In this configuration, the module is called a sync main device: (using the factory-default setting of MFR_CONFIG_ALL[4] = 0b), SYNC nn_ becomes a bidirectional open-drain pin, and the LTM4682 pulls SYNC logic low for nominally 500ns at a time, at the prescribed clock rate. The SYNC signal can be bused to other LTM4682 modules (configured as sync subordinates), for purposes of synchronizing switching frequencies of multiple modules within a system—but only one LTM4682 internal controllers should be configured as a sync main
device the other LTM4682(s) should be configured as sync subordinates.
The most straightforward way is to set its FREQUENCY_ SWITCH command to 0x0000 and MFR_CONFIG_ ALL[4] = 1b. This can be easily implemented with resistor pin-strap settings on the FSWPH nn_ _CFG pin (see Table 3). Using the MFR_CONFIG_ALL[4] = 1b, the LTM4682s SYNC pin becomes a high impedance input only—i.e., it does not drive SYNC low. The module synchronizes its frequency to the clock applied to its SYNC pin. The only shortcoming of this approach is without an externally applied clock, the switching frequency of the module will default to the low end of its frequencysynchronization capture range (~225kHz).
If fault-tolerance to the loss of an externally applied SYNC clock is desired, the FREQUENCY_SWITCH command of a sync subordinate can be left at the nominal target switching frequency of the application and not 0x0000 However, it is still necessary to configure MFR_CONFIG_ ALL[4] = 1b. With this combination of configurations, the LTM4682’s SYNC nn_ pins becomes a high impedance input and the module synchronizes its frequency to that of the externally applied clock, provided that the frequency of the externally applied clock exceeds ~½. of the target frequency (FREQUENCY_SWITCH). If the SYNC clock is absent, the module responds by operating at its target frequency, indefinitely. If and when the SYNC clock is restored, the module automatically phase-locks to the SYNC clock as normal. The only shortcoming of this approach is that the EEPROM must be configured per above guidance; resistor pin-strapping options on the FSWPH nn_ _CFG pin alone cannot provide fault-tolerance to the absence of the SYNC clock.
The FREQUENCY_SWITCH register can be altered through I[2] C commands, but only when the switching action is disengaged, i.e., the module’s outputs are turned off. The FREQUENCY_SWITCH command takes on the value stored in NVM at SVIN power-up, but is overridden according to a resistor pin-strap applied between the FSWPH nn_ _CFG pin and SGND only if the module is configured to respect resistor pin-strap settings (MFR_CONFIG_ALL[6] = 0b).
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LTM4682
## **APPLICATIONS INFORMATION**
Table 3 highlights the available resistor pin-strap and corresponding FREQUENCY_SWITCH settings.
The relative phasing of all active channels in a PolyPhase rail should be optimally phased. The relative phasing of each rail is 360°/ _n_ , where _n_ is the number of phases in the rail. MFR_PWM_CONFIG[2:0] configures channel relative phasing to the SYNC nn_ pin. Phase relationship values are indicated with 0° corresponding to the falling edge of SYNC being coincident with the turn-on of the top MOSFETs.
The MFR_PWM_CONFIG command can be altered through I[2] C commands, but only when the switching action is disengaged, i.e., the module’s outputs are turned off. The MFR_PWM_CONFIG command takes on the value stored in NVM at SVIN nn_ power-up, but is overridden according to a resistor pin-strap applied between the FSWPH nn_ _ CFG pin and SGND only if the module is configured to respect resistor pin-strap settings (MFR_CONFIG_ALL[6] = 0b). Table 3 highlights the available resistor pin-strap and corresponding MFR_PWM_CONFIG[2:0] settings.
Some combinations of FREQUENCY_SWITCH and MFR_PWM_CONFIG[2:0] are unavailable by resistor pinstrapping the FSWPH nn_ _CFG pin. All combinations of supported values for FREQUENCY_SWITCH and MFR_ PWM_CONFIG[2:0] can be configured by NVM programming—or, I[2] C transactions, provided switching action is disengaged, i.e., the module’s outputs are turned off.
Care must be taken to minimize capacitance on SYNC to ensure that the pull-up resistor versus the capacitor load has a low enough time constant for the application to form a clean clock. See Open-Drain Pins, later in this section.
When an LTM4682 is configured as a sync subordinate, it is permissible for external circuitry to drive the SYNC nn_ pin from a current-limited source (less than 10mA), rather than using a pull-up resistor. Any external circuitry must not drive high with arbitrarily low impedance at SVIN nn_ power-up, because the SYNC nn_ output can be low impedance until NVM contents have been downloaded to RAM.
The recommended LTM4682 switching frequencies for operation of many common VIN-to-VOUT applications are indicated Table 9. When the two channels of an LTM4682
are stepping input voltage(s) down to output voltages whose recommended switching frequencies in Table 9 are significantly different, operation at the higher of the two recommended switching frequencies is preferable, but minimum on-time must be considered. See the Minimum On-Time Considerations section.
**Table 9. Recommended Switching Frequency for Various VIN-toVOUT Step-Down Scenarios**
||**5VIN**|**8VIN**|**12VIN**|
|---|---|---|---|
|0.7VOUT|575kHz|575kHz|575kHz|
|0.8VOUT|650kHz|650kHz|650kHz|
|0.9VOUT|650kHz|650kHz|650kHz|
|1.0VOUT|650kHz|650kHz|650kHz|
|1.2VOUT|650kHz|650kHz|650kHz|
|1.35VOUT|750kHz|750kHz|750kHz|
## **OUTPUT CURRENT LIMIT PROGRAMMING**
The cycle-by-cycle current limit (= VISENSE/DCR) is proportional to COMP _n_ b, which can be programmed from 1.45V to 2.2V using the PMBus command IOUT_OC_FAULT_ LIMIT. The LTM4682 uses only the sub-milliohm sensing to detect current levels. See IOUT_OC_FAULT_LIMIT. The LTM4682 has two ranges of current limit programming. The value of MFR_PWM_MODE[2] is reserved, and the MFR_PWM_MODE[7], and IOUT_OC_FAULT_LIMIT are used to set the current limit level, see the section of the PMBus commands, the device can regulate output voltage with the peak current under the value of IOUT_OC_ FAULT_LIMIT in normal operation. In case output current exceeds the current limit, a OC fault will be issued. Each of the IOUT_OC_FAULT_LIMIT ranges will affect the loop gain, and subsequently affect the loop stability, so setting the range of current limiting is a part of loop design.
The LTpowerCAD design tool can be used to look at the loop stability changes if the current limit range is adjusted. The LTM4682 will automatically update the current limit as the inductor temperature changes. Keep in mind this operation is on a cycle-by-cycle basis and is only a function of the peak inductor current. The average inductor current is monitored by the ADC converter, and can provide a warning if too much average output current is detected. The overcurrent fault is detected when the
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## **APPLICATIONS INFORMATION**
COMP _nb_ voltage hits the maximum value. The digital processor within the LTM4682 provides the ability to either ignore the fault, shut down and latch off or shut down and retry indefinitely (hiccup). See the Peak Output Overcurrent Fault Response in the Operation section for more details. The Read_POUT can be used to readback calculated output power.
## **MINIMUM ON-TIME CONSIDERATIONS**
Minimum on-time, tON(MIN), is the smallest time duration that the LTM4682 is capable of turning on the top MOSFET. It is determined by internal timing delays and the gate charge required to turn on the top MOSFET. Low duty cycle applications may approach this minimum on-time limit, and care should be taken to ensure that:
**==> picture [96 x 30] intentionally omitted <==**
If the duty cycle falls below what can be accommodated by the minimum on-time, the controller will begin to skip cycles. The output voltage will continue to be regulated, but the ripple voltage and current will increase.
The minimum on-time for the LTM4682 is 85ns.
## **VARIABLE DELAY TIME, SOFT-START AND OUTPUT VOLTAGE RAMPING**
The LTM4682 must enter its run state before soft-start. The RUN _n_ pins are released after the part initializes and SVIN nn_ exceeds the VIN_ON threshold. If multiple LTM4682s are used in an application, they should be configured to share the same RUN _n_ pins. They all hold their respective RUN _n_ pins low until all devices initialize and SVIN exceeds the VIN_ON threshold for all devices. The SHARE_CLK nn_ pin assures all the devices connected to the signal use the same time base.
After the RUN _n_ pin is released, the controller waits for the user-specified turn-on delay (TON_DELAY _n_ ) before initiating an output voltage ramp. Multiple LTM4682s and other Analog Devices parts can be configured to start with variable delay times. To work correctly, all devices use the same timing clock (SHARE_CLK), and all devices must share the RUN _n_ pin.
This allows the relative delay of all parts to be synchronized. The actual variation in the delay will be dependent on the highest clock rate of the devices connected to the SHARE_CLK pin (all Analog Devices ICs are configured to allow the fastest SHARE_CLK signal to control the timing of all devices). The SHARE_CLK signal can be ±10% in frequency, thus the actual time delays will have some variance.
Soft-start is performed by actively regulating the load voltage while digitally ramping the target voltage from 0V to the commanded voltage set point. The rise time of the voltage ramp can be programmed using the TON_ RISE _n_ command to minimize inrush currents associated with the start-up voltage ramp. The soft-start feature is disabled by setting TON_RISE _n_ to any value less than 0.250ms. The LTM4682 performs the necessary math internally to ensure the voltage ramp are controlled to the desired slope. However, the voltage slope can not be any faster than the VOUT _n_ fundamental limits of the power stage. The number of tON(MIN) steps in the ramp is equal to TON_RISE/0.1ms.Therefore, the shorter the TON_RISE _n_ time setting, the more discrete steps in the soft-start ramp appear.
The LTM4682 PWM always operates in discontinuous mode during the TON_RISE _n_ operation. In discontinuous mode, the bottom MOSFET (MB _n_ ) is turned off as soon as reverse current is detected in the inductor. This allows the regulator to start up into a pre-biased load.
- There is no analog tracking feature in the LTM4682; how ever, two outputs can be given the same TON_RISE _n_ and TON_DELAY _n_ times to achieve ratiometric rail tracking. Because the RUN _n_ pins are released simultaneously and both units use the same time base (SHARE_CLK), the outputs track very closely. If the circuit is in a PolyPhase configuration, all timing parameters must be the same.
## **DIGITAL SERVO MODE**
For maximum accuracy in the regulated output voltage, enable the digital servo loop by asserting bit 6 of the MFR_PWM_MODE command. In digital servo mode, the LTM4682 will adjust the regulated output voltage based
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## **APPLICATIONS INFORMATION**
on the ADC voltage reading. Every 90ms, the digital servo loop will step the LSB of the DAC (nominally 1.375mV or 0.6875mV depending on the voltage range bit) until the output is at the correct ADC reading. At power-up, this mode engages after TON_MAX_FAULT_LIMIT unless the limit is set to 0 (infinite). If the TON_MAX_FAULT_LIMIT is set to 0 (infinite), the servo begins after TON_RISE is complete and VOUT has exceeded the VOUT_UV_FAULT_ LIMIT. This same point in time is when the output changes from discontinuous to the programmed mode, as indicated in MFR_PWM_MODE bit 0. See Figure 25 for more details on the VOUT waveform under time-based sequencing. If the TON_MAX_FAULT_LIMIT is set to a value greater than 0 and the TON_MAX_FAULT_RESPONSE is set to ignore 0x00, the servo begins:
1. After the TON_RISE sequence is complete
2. After the TON_MAX_FAULT_LIMIT time is reached; and
3. After the VOUT_UV_FAULT_LIMIT has been exceeded or the IOUT_OC_FAULT_LIMIT is no longer active.
If the TON_MAX_FAULT_LIMIT is set to a value greater than 0 and the TON_MAX_FAULT_RESPONSE is not set to ignore 0x00, the servo begins:
1. After the TON_RISE sequence is complete
2. After the TON_MAX_FAULT_LIMIT time has expired and both VOUT_UV_FAULT and IOUT_OC_FAULT are not present.
**==> picture [238 x 145] intentionally omitted <==**
**----- Start of picture text -----**<br>
DIGITAL SERVO<br>MODE ENABLED FINAL OUTPUT<br>T ON_MAX_FAULT_LIMIT VOLTAGE REACHED<br>DAC VOLTAGE TIME DELAY OF<br>VOUT ERROR (NOT 200-400ms<br>TO SCALE)<br>TON_RISE TIME 4682 F25<br>TON_DELAY<br>**----- End of picture text -----**<br>
**Figure 25. Timing Controlled VOUT Rise**
The maximum rise time is limited to 1.3 seconds.
In a PolyPhase configuration it is recommended that only one of the control loops have the digital servo mode enabled. This will insure the various loops do not work against each other due to slight differences in the reference circuits.
## **SOFT OFF (SEQUENCED OFF)**
In addition to a controlled start-up, the LTM4682 also supports controlled turn-off. The TOFF_DELAY and TOFF_ FALL functions are shown in Figure 26. TOFF_FALL is processed when the RUN _n_ pin goes low, or when the part is commanded off. If the part faults off or FAULT _n_ is pulled low externally and the part is programmed to respond to this, the output will be three-state rather than exhibiting a controlled ramp. The output will decay as a function of the load. The output voltage will operate as shown in Figure 26 as long as the part is in forced continuous mode and the TOFF_FALL time is sufficiently slow that the power stage can achieve the desired slope. The TOFF_FALL time can only be met if the power stage and controller can sink sufficient current to ensure the output is at zero volts by the end of the fall time interval. If the TOFF_FALL time is set shorter than the time required to discharge the load capacitance, the output will not reach the desired zero-volt state. At the end of TOFF_FALL, the controller will cease to sink current, and VOUT will decay at the natural rate determined by the load impedance. If the controller is in discontinuous mode, the controller will
**==> picture [204 x 72] intentionally omitted <==**
**----- Start of picture text -----**<br>
VOUT<br>TOFF_DELAY TOFF_FALL TIME 4682 F26<br>**----- End of picture text -----**<br>
**Figure 26. TOFF_DELAY and TOFF_FALL**
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## **APPLICATIONS INFORMATION**
not pull a negative current, and the output will be pulled low by the load, not the power stage. The maximum fall time is limited to 1.3 seconds. The shorter the TOFF_FALL time is set, the larger the discrete steps in the TOFF_FALL ramp will appear. The number of steps in the ramp is equal to TOFF_FALL/0.1ms.
## **UNDERVOLTAGE LOCKOUT**
The LTM4682 is initialized by an internal threshold-based UVLO where VIN must be approximately 4V and INTVCC nn_ , VDD33 nn_ , and VDD25 nn_ must be within approximately 20% of their regulated values. In addition, VDD33 nn_ must be within approximately 7% of the targeted value before the RUN _n_ pin is released. After the part has initialized, an additional comparator monitors VIN. The VIN_ON threshold must be exceeded before the power sequencing can begin. When the VIN drops below the VIN_ OFF threshold, the SHARE_CLK nn_ pin will be pulled low, and the VIN must increase above the VIN_ON threshold before the controller will restart. The normal start-up sequence will be allowed after the VIN_ON threshold is crossed. If FAULT _n_ is held low when VIN is applied, ALERT _nn_ will be asserted low even if the part is programmed not to assert ALERT _nn_ when FAULT _n_ is held low. If I[2] C communication occurs before the LTM4682 is out of reset and only a portion of the command is seen by the part, this can be interpreted as a CML fault. If a CML fault is detected, ALERT _nn_ is asserted low.
It is possible to program the contents of the NVM in the application if the VDD33 nn_ supply is externally driven directly to VDD33 nn_ or through VBIAS. This will activate the digital portion of the LTM4682 without engaging the high-voltage sections. PMBus communications are valid in this supply configuration. If the VIN has not been applied to the LTM4682, bit 3 (NVM Not Initialized) in MFR_COMMON will be asserted low. If this condition is detected, the part will only respond to addresses 5A and 5B. To initialize the part, the following set of commands are used: global address 0x5B command 0xBD data 0x2B followed by global address 5B command 0xBD and data 0xC4. The part will now respond to the correct address. Configure the part as desired, then issue a STORE_USER_ ALL. When VIN is applied, an MFR_RESET command must
be issued to allow the PWM to be enabled and valid ADC conversions to be read.
## **FAULT DETECTION AND HANDLING**
The LTM4682 FAULT _n_ pins are configurable to indicate a variety of faults including, OV, UV, OC, OT, timing faults, and peak overcurrent faults. In addition, the FAULT _n_ pins can be pulled low by external sources, indicating a fault in some other portion of the system. The fault response is configurable and allows the following options:
- n Ignore
- n Shut Down Immediately—Latch Off
- n Shut Down Immediately—Retry Indefinitely at the Time Interval Specified in MFR_RETRY_DELAY
See the PMBus PMBus Command Details, and the PMBus Command Summary sections of this data sheet and the PMBus specification for more details.
The OV response is automatic. If an OV condition is detected, TG _n_ goes low, and BG _n_ is asserted.
Fault logging is available on the LTM4682. The fault logging is configurable to automatically store data when a fault occurs that causes the unit to fault off. The header portion of the fault logging table contains peak values. It is possible to read these values at any time. This data will be useful while troubleshooting the fault.
If the LTM4682 internal temperature is in excess of 85°C, writes into the NVM (other than fault logging) is not recommended. The data will still be held in RAM, unless the 3.3V supply UVLO threshold is reached. If the die temperature exceeds 130°C, all NVM communication is disabled until the die temperature drops below 120°C.
## **OPEN-DRAIN PINS**
The LTM4682 has the following open-drain pins:
3.3V Pins
1. FAULT _n_
2. SYNC nn_
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## **APPLICATIONS INFORMATION**
3. SHARE_CLK nn_
4. PGOODn
- 5V Pins (5V pins operate correctly when pulled to 3.3V.)
1. RUN _n_
2. ALERT nn_
3. SCL nn_
4. SDA nn_
All the open-drain pins have on-chip pull-down transistors that can sink 3mA at 0.4V. The low threshold on the pins is 0.8V; thus, there is plenty of margin on the digital signals with 3mA of current. For 3.3V pins, 3mA of current is a 1.1k resistor. Unless transient speed issues are associated with the RC time constant of the resistor pullup and parasitic capacitance to the ground, a 10k resistor or larger is generally recommended.
For high-speed signals such as the SDA, SCL, and SYNC, a lower-value resistor may be required. The RC time constant should be set to 1/3 to 1/5 of the required rise time to avoid timing issues. For a 100pF load and a 400kHz PMBus communication rate, the rise time must be less than 300ns. The resistor pull-up on the SDA nn_ and SCL nn_ pins with the time constant set to 1/3 of the rise time is:
**==> picture [115 x 28] intentionally omitted <==**
The closest 1% resistor value is 1k. Be careful to minimize parasitic capacitance on the SDA and SCL pins to avoid communication problems. To estimate the loading capacitance, monitor the signal in question and measure how long it takes for the desired signal to reach approximately 63% of the output value. This is a one-time constant. The SYNC nn_ pin has an on-chip pull-down transistor with the output held low for nominally 500ns. If the internal oscillator is set for 500kHz and, the load is 100pF, and a 3x time constant is required, the resistor calculation is as follows:
**==> picture [128 x 29] intentionally omitted <==**
The closest 1% resistor is 4.99k.
If timing errors occur or the SYNC frequency is not as fast as desired, monitor the waveform and determine if the RC time constant is too long for the application. If possible, reduce the parasitic capacitance. If not, reduce the pull-up resistor sufficiently to ensure proper timing. The SHARE_CLK nn_ pull-up resistor has a similar equation with a period of 10µs and a pull-down time of 1µs. The RC time constant should be approximately 3µs or faster.
## **PHASE-LOCKED LOOP AND FREQUENCY SYNCHRONIZATION**
The LTM4682 has a phase-locked loop (PLL) comprised of an internal voltage-controlled oscillator (VCO) and a phase detector. The PLL is locked to the falling edge of the SYNC nn_ pin. The phase relationship between the PWM controller and the falling edge of SYNC is controlled by the lower 3 bits of the MFR_PWM_CONFIG command. For PolyPhase applications, it is recommended that all the phases be spaced evenly. Thus, for a 2-phase system, the signals should be 180° out of phase, and a 4-phase system should be spaced 90°.
The phase detector is an edge-sensitive digital type that provides a known phase shift between the external and internal oscillators. This type of phase detector does not exhibit a false lock to the harmonics of the external clock.
The output of the phase detector is a pair of complementary current sources that charge or discharge the internal filter network. The PLL lock range is guaranteed between 250kHz and 1MHz. Nominal parts will have a range beyond this; however, the operation to a wider frequency range is not guaranteed.
The PLL has a lock detection circuit. If the PLL should lose lock during operation, bit 4 of the STATUS_MFR_ SPECIFIC command is asserted, and the ALERT nn_ pin is pulled low. The fault can be cleared by writing a 1 to the bit. If the user does not wish to see the ALERT nn_ pin assert if a PLL_FAULT occurs, the SMBALERT_MASK command can be used to prevent the alert.
If the SYNC signal is not clocking in the application, the nominal programmed frequency will control the PWM circuitry. However, if multiple parts share the SYNC nn_
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## **APPLICATIONS INFORMATION**
pins and the signal is not clocking, the parts will not be synchronized, and excess voltage ripple on the output may be present. Bit 10 of MFR_PADS will be asserted low if this condition exists.
If the PWM signal appears to be running at too high a frequency, monitor the SYNC nn_ pin. Extra transitions on the falling edge will result in the PLL trying to lock on to noise versus the intended signal. Review the routing of digital control signals and minimize crosstalk to the SYNC signal to avoid this problem. Multiple LTM4682s are required to share one SYNC nn_ pin in PolyPhase configurations. For other configurations, connecting the SYNC nn_ pins to form a single SYNC signal is optional. If the SYNC nn_ pin is shared between LTM4682s, only one LTM4682 controller can be programmed with frequency output. All the other LTM4682s should be programmed to disable the SYNC nn_ output. However, their frequency should be programmed to the nominal desired value.
## **INPUT CURRENT SENSE AMPLIFIER**
The LTM4682 input current sense amplifier can sense the supply current into the VIN01 and VIN23 power stage pins using an external sense resistor, as shown in Figure 2 Block Diagram. The RSENSE _n_ value can be programmed using the MFR_IIN_CAL_GAIN command. Kelvin sensing is recommended across the RSENSE resistor to eliminate errors. The MFR_PWM_CONFIG [6:5] sets the input current sense amplifier gain. See the MFR_PWM_CONFIG section. The IIN_OC_WARN_LIMIT command sets the value of the input current measured by the ADC, in amperes, which causes a warning indicating the input current is high. The READ_IIN value will determine if this limit has been exceeded. The READ_IIN command returns the input current, in Amperes, as measured across the input current sense resistor.
There is an IR voltage drop from the supply to the SVIN nn_ pin due to the current flowing into the SVIN nn_ pin. To compensate for this voltage drop, the MFR_RVIN will be automatically set to the 1Ω internal sense resistor in the Figure 2 Block Diagram. The LTM4682 will multiply the MFR_READ_ICHIP measurement value by this 1Ω resistor and add this voltage to the measured voltage at
the SVIN nn_ pin. Therefore, READ_VIN = VSVIN_PIN + (MFR_READ_ICHIP • 1Ω). The MFR_READ_ICHIP command is used to measure the internal controller current. Using the READ_PIN command allows for reading calculated input power.
## **PROGRAMMABLE LOOP COMPENSATION**
The LTM4682 offers programmable loop compensation to optimize the transient response without hardware change. The error amplifier gain gm varies from 1.0mS to 5.76mS, and the compensation resistor RCOMP _n_ varies from 0kΩ to 62kΩ inside the controller. Two compensation capacitors, COMP _n_ a and COMP _n_ b, are required in the design, and the typical ratio between COMP _n_ a and COMP _n_ b is 10. Also, see Figure 2 Block Diagram and Figure 27.
By adjusting the gm and RCOMP _n_ only, the LTM4682 can provide a flexible Type II compensation network to optimize the loop over a wide range of output capacitors. Adjusting the gm will change the compensation’s gain over the whole frequency range without moving the pole and zero location, as shown in Figure 28.
**==> picture [199 x 278] intentionally omitted <==**
**----- Start of picture text -----**<br>
gm VREF<br>FB<br>RCOMP n<br>COMP na COMP nb<br>4682 F27<br>CCOMP L CCOMP H<br>Figure 27. Programmable Loop Compensation<br>TYPE II COMPENSATION<br>GAIN<br>INCREASE gm<br>FREQUENCY<br>4682 F28<br>+<br>–<br>**----- End of picture text -----**<br>
**Figure 28. Error Amp gm Adjust**
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## **APPLICATIONS INFORMATION**
Adjusting the RCOMP will change the pole and zero location, as shown in Figure 29. It is recommended that the user determines the appropriate value for the gm and RCOMP _n_ using the LTpowerCAD tool.
**==> picture [219 x 138] intentionally omitted <==**
**----- Start of picture text -----**<br>
TYPE II COMPENSATION<br>GAIN<br>INCREASE RCOMP n<br>FREQUENCY<br>4682 F29<br>**----- End of picture text -----**<br>
**Figure 29. RCOMP Adjust**
## **CHECKING TRANSIENT RESPONSE**
The regulator loop response can be checked by looking at the load current transient response. Switching regulators take several cycles to respond to a step in DC (resistive) load current. When a load step occurs, VOUT shifts by an amount equal to ∆ILOAD • ESR, where ESR is the effective series resistance of COUT. ∆ILOAD also begins to charge or discharge COUT, generating the feedback error signal that forces the regulator to adapt to the current change and return VOUT to its steady-state value. During this recovery time, VOUT can be monitored for excessive overshoot or ringing, indicating a stability problem. The availability of the COMP pin not only allows optimization of control loop behavior but also provides a DC-coupled and AC-filtered closed-loop response test point. The DC step, rise time, and settling at this test point truly reflect the closed-loop response. Assuming a predominantly second-order system, phase margin and/or damping factor can be estimated using the percentage of overshoot seen at this pin. The bandwidth can also be estimated by examining the rise time at the pin. The COMP _n_ a external capacitor shown in the Typical Application circuit section will provide an adequate starting point for most applications. The programmable parameters that affect loop gain are the voltage range, bit[1] of the MFR_PWM_MODE command, the current range bit[7] of the MFR_PWM_MODE
command, the gm of the PWM channel amplifier bits [7:5] of MFR_PWM_COMP, and the internal RCOMP compensation resistor, bits[4:0] of MFR_PWM_COMP. Be sure to establish these settings before compensation calculation.
The COMP _n_ a series internal RCOMP _n_ and external CCOMP _n_ a filter sets the dominant pole-zero loop compensation. The internal RCOMP _n_ value can be modified (from 0Ω to 62k) using bits[4:0] of the MFR_PWM_COMP command. Adjust the value of RCOMP _n_ to optimize transient response once the final PCB layout is done and the particular CCOMPbn filter capacitor and output capacitor type and value have been determined. The output capacitors must be selected because the various types and values determine the loop gain and phase. An output current pulse of 20% to 80% of full-load current having a rise time of 1µs to 10µs will produce output voltage and COMP pin waveforms that will give a sense of the overall loop stability without breaking the feedback loop. Placing a power MOSFET with a resistor to the ground directly across the output capacitor and driving the gate with an appropriate signal generator is a practical way to produce a load step. The MOSFET + RSERIES will produce output currents approximately equal to VOUT/RSERIES. RSERIES values from 0.1Ω to 2Ω are valid depending on the current limit settings and the programmed output voltage. The initial output voltage step resulting from the step change in output current may not be within the bandwidth of the feedback loop, so this signal cannot be used to determine the phase margin. This is why it is better to look at the COMP pin signal, which is in the feedback loop and is the filtered and compensated control loop response. The gain of the loop will be increased by increasing RCOMP, and the bandwidth of the loop will be increased by decreasing CCOMP _n_ a. If RCOMP is increased by the same factor that CCOMP is decreased, the zero frequency will be kept the same, thereby keeping the phase shift the same in the most critical frequency range of the feedback loop. The gain of the loop will be proportional to the transconductance of the error amplifier, gm, which is set using bits[7:5] of the MFR_PWM_COMP command. The output voltage settling behavior is related to the stability of the closed-loop system and will demonstrate the actual overall supply performance. A second, more severe transient is caused by switching in loads with large (>1µF)
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## **APPLICATIONS INFORMATION**
supply bypass capacitors. The discharged bypass capacitors are effectively put in parallel with COUT, causing a rapid drop in VOUT. No regulator can alter its delivery of current quickly enough to prevent this sudden step change in output voltage if the load switch resistance is low and it is driven quickly. If the ratio of CLOAD to COUT is greater than 1:50, the switch rise time should be controlled so that the load rise time is limited to approximately 25 • CLOAD. Thus, a 10µF capacitor would require a 250µs rise time, limiting the charging current to about 200mA.
## **PolyPhase Configuration**
When configuring a PolyPhase rail with multiple LTM4682s, the user must share the SYNC, COMP, SHARE_CLK, FAULT, and ALERT pins of these parts. Be sure to use pull-up resistors on FAULT, SHARE_CLK, and ALERT. One of the part’s SYNC pins must be set to the desired switching frequency, and all other FREQUENCY_SWITCH commands must be set to External Clock. If an external oscillator is provided, set the FREQUENCY_SWITCH command to an external clock for all parts. The relative phasing of all the channels should be spaced equally. The MFR_RAIL_ADDRESS of all the devices should be set to the same value.
Multiple channels need to connect all the VSENSE _n_[+] pins together, and all the VSENSE _n_[–] pins together, COMP _n_ a and COMP _n_ b pins together as well. Do not assert bit[4] of MFR_CONFIG_ALL except in a PolyPhase application. See the typical application example, Figure 50.
## **CONNECTING THE USB TO I[2] C/SMBUS/PMBUS CONTROLLER TO THE LTM4682 IN SYSTEM**
The Analog Devices USB-to-I[2] C/SMBus/PMBus adapter (DC1613A or equivalent) can be interfaced to the LTM4682 on the user’s board for programming, telemetry, and system debug. The adapter, when used in conjunction with LTpowerPlay, provides a powerful way to debug an entire power system. Faults are quickly diagnosed using the telemetry, fault status commands, and the fault log. The final configuration can be quickly developed and stored in the LTM4682 EEPROM. Figure 30 illustrates the application schematic for powering, programming, and communication with one or more LTM4682s through the Analog Devices I[2] C/SMBus/PMBus adapter, regardless of whether or not system power is present. If system power is not present, the dongle will power the LTM4682 through the VDD33 nn_ supply pin. To initialize the part when VIN _nn_ is
**==> picture [310 x 241] intentionally omitted <==**
**----- Start of picture text -----**<br>
VIN<br>ADI 100k 100k<br>CONTROLLERHEADER VIN nn<br>ISOLATED<br>3.3V<br>SDA TP0101K VDD33 _ nn VDD25 _ nn<br>1µF LTM4682<br>SCL 10k 1/2<br>SDA_ nn<br>10k<br>SCL_ nn<br>WP_ nn PGND/SGND_ nn<br>TO ADI DC1613<br>USB TO I [2] C/SMBus/PMBus<br>CONTROLLER<br>VIN nn<br>VDD33_ nn VDD25_ nn<br>TP0101K 1µF LTM4682<br>1/2<br>SDA_ nn<br>SCL_ nn<br>VGS MAX ON THE TP0101K IS 8V IF VIN > 16V<br>CHANGE THE RESISTOR DIVIDER ON THE PFET GATE WP_ nn PGND/SGND_ nn 4682 F30<br>LTM4682 HAS TWO INTERNAL CONTROLLERS<br>**----- End of picture text -----**<br>
**Figure 30. Controller Connection**
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## **APPLICATIONS INFORMATION**
not applied, and the VDD33 nn_ pin is powered, use global address 0x5B command 0xBD data 0x2B followed by address 0x5B command 0xBD data 0xC4. The LTM4682 can now communicate with the internal EEPROM and read the project file. To write the updated project file to the NVM, issue a STORE_USER_ALL command. When VIN is applied, an MFR_RESET must be issued to allow the PWM POWER to be enabled and valid ADCs to be read.
Because of the adapter’s limited current sourcing capability, only the LTM4682s, their associated pull-up resistors, and the I[2] C pull-up resistors should be powered from the VDD33 3.3V supply. In addition, any device sharing the I[2] C bus connections with the LTM4682 should not have body diodes between the SDA/SCL pins and their respective VDD node because this will interfere with bus communication without system power. If the VIN is applied, the DC1613A will not supply the power to the LTM4682s on the board. It is recommended that the RUN _n_ pins be held low, or no voltage configuration resistors be inserted to avoid providing power to the load until the part is fully configured.
The LTM4682 is fully isolated from the host PC’s ground by the DC1613A. The 3.3V from the adapter and the LTM4682 VDD33 nn_ pin must be driven to each LTM4682 internal controller with a separate PFET. If both VIN and VBIAS are not on, the VDD33 nn_ pins can be in parallel because the on-chip LDO is off. The controller’s 3.3V current limit is 100mA, but typical VDD33 nn_ currents are under 15mA. The VDD33 nn_ does backdrive the INTVCC/ VBIAS pin. Normally, this is not an issue if the VIN is open.
## **LTpowerPlay: AN INTERACTIVE GUI FOR DIGITAL POWER**
The LTpowerPlay (see Figure 31) is a powerful Windowsbased development environment supporting Analog Devices, digital power system management ICs, and the LTM4682. The software supports a variety of different tasks. The LTpowerPlay can evaluate Analog Devices ICs by connecting to a demo board or the user application. The LTpowerPlay can also be used in an offline mode (with no hardware present) to build multiple IC configuration files that can be saved and reloaded later. The LTpowerPlay
provides unprecedented diagnostic and debug features. It becomes a valuable diagnostic tool during board bringup to program or tweak the power system or to diagnose power issues when bringing up rails. LTpowerPlay utilizes Analog Devices’s USB-to-I[2] C/SMBus/PMBus adapter to communicate with one of the many potential targets, including the DC2924A, DC3082A demo boards, or a customer target system. The software also provides an automatic update feature to keep the revisions current with the latest set of device drivers and documentation.
A great deal of context-sensitive help is available with LTpowerPlay, along with several tutorial demos.
## **PMBus COMMUNICATION AND COMMAND PROCESSING**
The LTM4682 internal controllers have a one-deep buffer to hold the last data written for each supported command before processing, as shown in Figure 32, Write Command Data Processing. When the part receives a new command from the bus, it copies the data into the Write Command Data Buffer, indicates to the internal processor that this command data needs to be fetched, and converts the command to its internal format to be executed. Two distinct parallel blocks manage command buffering and command processing (fetch, convert, and execute) to ensure the last data written to any command is never lost. Command data buffering handles incoming PMBus writes by storing the command data to the Write Command Data Buffer and marking these commands for future processing. The internal processor runs in parallel and handles the sometimes slower task of fetching, converting and executing commands marked for processing. Some computationally intensive commands (e.g., timing parameters, temperatures, voltages, and currents) have internal processor execution times that may be long relative to PMBus timing. If the part is busy processing a command, and new command(s) arrive, execution may be delayed or processed in a different order than received. The part indicates when internal calculations are in the process through bit 5 of MFR_COMMON (calculations not pending). When the part is busy calculating, bit 5 is cleared. When this bit is set, the part is ready for another
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## LTM4682
## **APPLICATIONS INFORMATION**
## **Figure 31. LTpowerPlay Screen Shot**
**==> picture [345 x 114] intentionally omitted <==**
**----- Start of picture text -----**<br>
CMD WRITE COMMAND<br>PMBusWRITE DECODER DATA BUFFERPAGE 0x00 PROCESSORINTERNAL Channel # IdentitGUI y<br>CMDS ••• FETCH, 0 U0:A0<br>0x21 CONVERT 1 U0:A1<br>DATA VOUT_COMMAND DATA 2 U0:B0<br>MUX AND<br>••• EXECUTE 3 U0:B1<br>MFR_RESET 0xFD<br>CALCULATIONS S x1<br>PENDING R 4682 F32<br>**----- End of picture text -----**<br>
**Figure 32. Write Command Data Processing**
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LTM4682
## **APPLICATIONS INFORMATION**
command. An example polling loop is shown in Figure 33, which ensures that commands are processed in order while simplifying error-handling routines.
When the part receives a new command while it is busy, it will communicate this condition using standard PMBus protocol. Depending on the part configuration it may either NACK the command or return all ones (0xFF) for reads. It may also generate a BUSY fault and ALERT notification, or stretch the SCL clock low. For more information, refer to PMBus Specification v1.1, Part II, Section 10.8.7, and SMBus v2.0, section 4.3.3. Clock stretching can be enabled by asserting bit 1 of MFR_CONFIG_ALL. Clock stretching will only occur if enabled, and the bus communication speed exceeds 100kHz.
```
// wait until chip is not busy
do
{
mfrCommonValue = PMBUS_READ_BYTE(0xEF);
partReady = (mfrCommonValue & 0x68) == 0x68;
}while(!partReady)
```
```
// now the part is ready to receive the next
command
PMBUS_WRITE_WORD(0x21, 0x2000); //write VOUT_
COMMAND to 2V
```
## **Figure 33. Example of a Command Write of VOUT_COMMAND**
The PMBus busy protocols are well-accepted standards, but can make writing system-level software somewhat complex. The part provides three hand-shaking status bits, which reduce complexity while enabling robust system-level communication.
The three hand-shaking status bits are in the MFR_ COMMON register. When the part is busy executing an internal operation, it will clear bit 6 of MFR_COMMON (chip not busy). When the part is busy specifically because it is in a transitional VOUT state (margining hi/lo, power off/on, moving to a new output voltage set point, etc.), it will clear bit 4 of MFR_COMMON (output not in transition). When internal calculations are in process, the part will clear bit 5 of MFR_COMMON (calculations not pending). These three status bits can be polled with a PMBus read byte of the MFR_COMMON register until all three bits are set. A command immediately following the status bits being set will be accepted without NACKing or generating a BUSY fault/ALERT notification. The part can NACK
commands for other reasons, however, as required by the PMBus spec (for instance, an invalid command or data). An example of a robust command write algorithm for the VOUT_COMMAND register is provided in Figure 33.
It is recommended that all command writes (write byte, write word, etc.) be preceded with a polling loop to avoid the extra complexity of dealing with busy behavior and unwanted ALERT notifications. A simple way to achieve this is to create a SAFE_WRITE_BYTE() and SAFE_ - WRITE_WORD() subroutine. The above polling mecha nism allows your software to remain clean and simple while robustly communicating with the part. For a detailed discussion of these topics and other special cases, refer to the Application Note search section feature at Analog.com.
When communicating using bus speeds at or below 100kHz, the polling mechanism shown here provides a simple solution that ensures robust communication without clock stretching. At bus speeds in excess of 100kHz, it is strongly recommended that the part be configured to enable clock stretching. This requires a PMBus main device that supports clock stretching. System software that detects and properly recovers from the standard PMBus NACK/BUSY faults as described in the PMBus Specification v1.1, Par II, Section 10.8.7 is required to communicate. The LTM4682 is not recommended in applications with bus speeds in excess of 400kHz.
## **THERMAL CONSIDERATIONS AND OUTPUT CURRENT DERATING**
The thermal resistances reported in the Pin Configuration section of this data sheet are consistent with those parameters defined by JESD51-12. They are intended for use with finite element analysis (FEA) software modeling tools that leverage the outcome of thermal modeling, simulation, and correlation to hardware evaluation performed on a µModule package mounted to a hardware test board defined by JESD51-9 (Test Boards for Area Array Surface Mount Package Thermal Measurements). The motivation for providing these thermal coefficients is found in JESD51-12 (Guidelines for Reporting and Using Electronic Package Thermal Information).
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## **APPLICATIONS INFORMATION**
Many designers may use laboratory equipment and a test vehicle, such as the demo board, to predict the - µModule regulator’s thermal performance in their appli cation at various electrical and environmental operating conditions to compliment any FEA activities. Without FEA software, the thermal resistances reported in the Pin Configuration section are in-and-of themselves not relevant to providing guidance on thermal performance; instead, the derating curves provided later in this data sheet can be used in a manner that yields insight and guidance pertaining to one’s application-usage, and can be adapted to correlate thermal performance to one’s own application.
The Pin Configuration section gives four thermal coefficients explicitly defined in JESD51-12; these coefficients are quoted or paraphrased below:
1. θ JA, the thermal resistance from junction to ambient, is the natural convection junction-to-ambient air thermal resistance measured in one cubic foot sealed enclosure. This environment is sometimes referred to as still air, although natural convection causes the air to move. This value is determined with the part mounted to a JESD51-9 defined test board, which does not reflect an actual application or viable operating condition.
2. θ JCbottom, the thermal resistance from the junction to the bottom of the product case, is determined with all of the component power dissipation flowing through the bottom of the package. In the typical µModule regulator, the bulk of the heat flows out the bottom of the package, but there is always heat flow out into the ambient
environment. As a result, this thermal resistance value may be useful for comparing packages, but the test conditions don’t generally match the user’s application.
3. θ JCtop, the thermal resistance from the junction to the top of the product case, is determined with nearly all of the component power dissipation flowing through the top of the package. As the electrical connections of the typical µModule regulator are on the bottom of the package, it is rare for an application to operate such that most of the heat flows from the junction to the top of the part. As in the case of θ JCbottom, this value may be useful for comparing packages, but the test conditions don’t generally match the user’s application.
4. θ JB, the thermal resistance from the junction to the printed circuit board, is the junction-to-board thermal resistance where almost all of the heat flows through the bottom of the µModule regulator and into the board, and is really the sum of the θ JCbottom and the thermal resistance of the bottom of the part through the solder joints and through a portion of the board. The board temperature is measured at a specified distance from the package, using a two-sided, two-layer board. This board is described in JESD51-9.
A graphical representation of the aforementioned thermal resistances is shown in Figure 34; blue resistances are contained within the µModule regulator, whereas green resistances are external to the µModule package.
As a practical matter, it should be clear to the reader that no individual or sub-group of the four thermal resistance
**==> picture [357 x 148] intentionally omitted <==**
**----- Start of picture text -----**<br>
JUNCTION-TO-AMBIENT THERMAL RESISTANCE COMPONENTS<br>JUNCTION-TO-CASE (TOP) CASE (TOP)-TO-AMBIENT<br>RESISTANCE RESISTANCE<br>JUNCTION-TO-BOARD RESISTANCE<br>JUNCTION AMBIENT<br>JUNCTION-TO-CASE CASE (BOTTOM)-TO-BOARD BOARD-TO-AMBIENT<br>(BOTTOM) RESISTANCE RESISTANCE RESISTANCE<br>4682 F33<br>µModule DEVICE<br>**----- End of picture text -----**<br>
**Figure 34. Graphical Representation of JESD51-12 Thermal Coefficients**
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## **APPLICATIONS INFORMATION**
parameters defined by JESD51-12 or provided in the Pin Configuration section replicates or conveys normal operating conditions of a µModule regulator. For example, in normal board-mounted applications, never does 100% of the device’s total power loss (heat) thermally conduct exclusively through the top or exclusively through the bottom of the µModule package—as the standard defines for θ JCtop and θ JCbottom, respectively. In practice, power loss is thermally dissipated in both directions away from the package—granted, in the absence of a heat sink and airflow, a majority of the heat flow is into the board.
Within the LTM4682, be aware that there are multiple power devices and components dissipating power, with the consequence that the thermal resistances relative to different junctions of components or die are not exactly linear to total package power loss. To reconcile this complication without sacrificing modeling simplicity—but also, not ignoring practical realities—an approach has been taken using FEA software modeling along with laboratory testing in a controlled-environment chamber to reasonably define and correlate the thermal resistance values supplied in this data sheet: (1) Initially, FEA software is used to accurately build the mechanical geometry of the LTM4682 and the specified PCB with all of the correct material coefficients along with accurate power loss source definitions; (2) this model simulates a softwaredefined JEDEC environment consistent with JESD51-9 and JESD51-12 to predict power loss heat flow and temperature readings at different interfaces that enable the calculation of the JEDEC-defined thermal resistance values; (3) the model and FEA software is used to evaluate the LTM4682 with heat sink, and airflow; (4) having solved for and analyzed these thermal resistance values and simulated various operating conditions in the software model, a thorough laboratory evaluation replicates the simulated conditions with thermocouples within a controlled environment chamber while operating the device at the same power loss as that which was simulated. The outcome of this process and due diligence yields the set of derating curves provided in later sections of this data sheet, along with well-correlated JESD51-12defined θ values provided in the Pin Configuration section of this data sheet.
The 5V, 8V, and 12V power loss curves in Figure 35, Figure 36, and Figure 37, respectively, can be used in coordination with the load current derating curves in Figure 41 to Figure 46 for calculating an approximate θ JA thermal resistance for the LTM4682 with various airflow conditions and without heat sinks. These thermal resistances represent the demonstrated performance of the LTM4682 on hardware, an 8-layer FR4 PCB measuring 215mm × 160mm × 1.6mm using 2oz copper on all layers. The power loss curves are taken at room temperature, and are increased with multiplicative factors of 1.35 when the junction temperature reaches 125°C. The derating curves are plotted with the LTM4682’s paralleled outputs initially sourcing up to 120A and the ambient temperature at 25°C. The output voltages are 0.75V, 1V and 1.35V. These are chosen to include the lower and higher output voltage ranges to correlate the thermal resistance. Thermal models are derived from several temperature measurements in a controlled temperature chamber, along with thermal modeling analysis. The junction temperatures are monitored while the ambient temperature is increased with and without airflow.
The power loss increase with ambient temperature change is factored into the derating curves. The junctions are maintained at 125°C maximum while lowering output current or power while increasing ambient temperature. The decreased output current decreases the internal module loss as the ambient temperature is increased. The monitored junction temperature of 125°C minus the ambient operating temperature specifies how much module temperature rise can be allowed. As an example in Figure 43, the load current is derated to ~80A at ~67°C ambient with no air or heat sink, and the room temperature (25°C) power loss for this 12VIN to 1VOUT at 80AOUT condition is ~9.7W. A 13.1W loss is calculated by multiplying the ~9.7W room temperature loss from the 12VIN to 1VOUT power loss curve at 80A (Figure 37), with the 1.35 multiplying factor. If the 67°C ambient temperature is subtracted from the 125°C junction temperature, then the difference of 58°C divided by 13.1W yields a thermal resistance, θ JA, of 4.4°C/W—in good agreement with the value derived from thermal simulation shown
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## LTM4682
## **APPLICATIONS INFORMATION-DERATING CURVES**
**==> picture [531 x 624] intentionally omitted <==**
**----- Start of picture text -----**<br>
22 22 22<br>0LFM 0LFM 0LFM<br>20 200LFM 20 200LFM 20 200LFM<br>18 400LFM 18 400LFM 18 400LFM<br>16 16 16<br>14 14 14<br>12 12 12<br>10 10 10<br>8 8 8<br>6 6 6<br>4 4 4<br>2 2 2<br>0 0 0<br>0 20 40 60 80 100 120 140 0 20 40 60 80 100 120 140 0 20 40 60 80 100 120 140<br>TEMPERATURE (°C) TEMPERATURE (°C) TEMPERATURE (°C)<br>4682 F35 4682 F36 4682 F37<br>Figure 35. 5VIN Power Loss Curve Figure 36. 8VIN Power Loss Curve Figure 37. 12VIN Power Loss Curve<br>140 140 140<br>120 120 120<br>100 100 100<br>80 80 80<br>60 60 60<br>40 40 40<br>0LFM 0LFM 0LFM<br>20 200LFM 20 200LFM 20 200LFM<br>400LFM 400LFM 400LFM<br>0 0 0<br>0 20 40 60 80 100 120 0 20 40 60 80 100 120 0 20 40 60 80 100 120<br>TEMPERATURE (°C) TEMPERATURE (°C) TEMPERATURE (°C)<br>4682 F38 4682 F39 4682 F40<br>Figure 38. 5VIN to 0.75VOUT Figure 39. 8VIN to 0.75VOUT Derating Figure 40. 12VIN to 0.75VOUT Derating<br>Derating Curve, No Heatsink Curve, No Heatsink Curve, No Heatsink<br>140 140 140<br>120 120 120<br>100 100 100<br>80 80 80<br>60 60 60<br>40 40 40<br>0LFM 0LFM 0LFM<br>20 20 20<br>200LFM 200LFM 200LFM<br>400LFM 400LFM 400LFM<br>0 0 0<br>0 20 40 60 80 100 120 0 20 40 60 80 100 120 0 20 40 60 80 100 120<br>TEMPERATURE (°C) TEMPERATURE (°C) TEMPERATURE (°C)<br>4682 F41 4682 F42 4682 F43<br>Figure 41. 5VIN to 1VOUT Figure 42. 8VIN to 1VOUT Derating Figure 43. 12VIN to 1VOUT Derating<br>Derating Curve, No Heat Sink Curve, No Heat Sink Curve, No Heat Sink<br>Rev. 0<br>LOAD CURRENT (A) LOAD CURRENT (A) LOAD CURRENT (A)<br>LOAD CURRENT (A) LOAD CURRENT (A) LOAD CURRENT (A)<br>LOAD CURRENT (A) LOAD CURRENT (A) LOAD CURRENT (A)<br>**----- End of picture text -----**<br>
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## **APPLICATIONS INFORMATION**
**==> picture [523 x 189] intentionally omitted <==**
**----- Start of picture text -----**<br>
140 140 140<br>120 120 120<br>100 100 100<br>80 80 80<br>60 60 60<br>40 40 40<br>0LFM 0LFM 0LFM<br>20 200LFM 20 200LFM 20 200LFM<br>400LFM 400LFM 400LFM<br>0 0 0<br>0 20 40 60 80 100 120 0 20 40 60 80 100 120 0 20 40 60 80 100 120<br>TEMPERATURE (°C) TEMPERATURE (°C) TEMPERATURE (°C)<br>4682 F44 4682 F45 4682 F38<br>Figure 44. 5VIN to 1.35VOUT Figure 45. 8VIN to 1.35VOUTIN to 1.35VOUT to 1.35VOUTOUT Figure 46. 12VIN to 1.35VOUT<br>Derating Curve, No Heat Sink Derating Curve, No Heat Sink Derating Curve, No Heat Sink<br>LOAD CURRENT (A) LOAD CURRENT (A) LOAD CURRENT (A)<br>**----- End of picture text -----**<br>
**Figure 45. 8VIN to 1.35VOUTIN to 1.35VOUT to 1.35VOUTOUT Derating Curve, No Heat Sink**
in the Pin Configuration section. Table 10, Table 11, and Table 12 provide equivalent thermal resistances for 0.75V, 1V, and 1.35V outputs with and without airflow. The derived thermal resistances in Table 10 through Table 12 for the various conditions can be multiplied by the calculated power loss as a function of ambient temperature to derive temperature rise above ambient, thus maximum
junction temperature. Room temperature power loss can be derived from the efficiency curves in the Typical Performance Characteristics section and adjusted with the above ambient temperature multiplicative factors.
**Table 10 through Table 12: Output Current Derating**
**Table 10. 0.75V Output**
|**DERATING CURVE**|**VIN (V)**|**POWER LOSS CURVE**|**AIRFLOW(LFM)**|**HEAT SINK**|θ**JA (°C/W)**|
|---|---|---|---|---|---|
|Figure 38 to Figure 40|5,8,12|Figure 35 to Figure 37|0|None|4.4|
|Figure 38 to Figure 40|5,8,12|Figure 35 to Figure 37|200|None|4|
|Figure 38 to Figure 40|5,8,12|Figure 35 to Figure 37|400|None|3|
|**Table 11. 1V Output**||||||
|**DERATING CURVE**|**VIN (V)**|**POWER LOSS CURVE**|**AIRFLOW(LFM)**|**HEAT SINK**|θ**JA (°C/W)**|
|Figure 41 to Figure 43|5,8,12|Figure 35 to Figure 37|0|None|4.4|
|Figure 41 to Figure 43|5,8,12|Figure 35 to Figure 37|200|None|4|
|Figure 41 to Figure 43|5,8,12|Figure 35 to Figure 37|400|None|3|
|**Table 12. 1.35V Output**||||||
|**DERATING CURVE**|**VIN (V)**|**POWER LOSS CURVE**|**AIRFLOW(LFM)**|**HEAT SINK**|θ**JA (°C/W)**|
|Figure 44 to Figure 46|5,8,12|Figure 35 to Figure 37|0|None|4.4|
|Figure 44 to Figure 46|5,8,12|Figure 35 to Figure 37|200|None|4|
|Figure 44 to Figure 46|5,8,12|Figure 35 to Figure 37|400|None|3|
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LTM4682
## **APPLICATIONS INFORMATION**
|**GAIN**<br>**MARGIN**<br>**CROSS**<br>**OVER FREQ**<br>**(kHz)**|128|136|132|121|141|129|144|130|154|137|*TDK C3225X5R0J107M, 100μF, 6.3V, X5R.<br>**Panasonic ETPF470M5H, 470μF, 2.5V, 5mΩ<br>These Values Should Be Check with a BODE Analyzer.|
|---|---|---|---|---|---|---|---|---|---|---|---|
|**GAIN**<br>**MARGIN**<br>**(dB)**|–14|–13|–14|–13|–14|–14|–14|–14|–14|–14||
|**PHASE**<br>**MARGIN**<br>**(DEG)**|65|66|65|64|66|64|66|64|67|65||
|<br>**PHASE**<br>**MARGIN**<br>**CROSS**<br>**OVER FREQ**<br>**(kHz)**|29|29|30|29|30|30|31|30|31|31||
|**RECOVERY**<br>**TIME (μs)**|33|33|29|28|27|26|24|23|21|21||
|**PK–PK**<br>**DEVIATION**<br>**(mV)**|60|58|59|61|57|58|56|60|56|59||
|**VOUT**<br>**DROOP**<br>**(mV)**|30|29|30|31|29|29|28|30|28|30||
|**LOAD**<br>**STEP (A)**|10 to 20|10 to 20|10 to 20|10 to 20|10 to 20|10 to 20|10 to 20|10 to 20|10 to 20|10 to 20||
|**fSW**<br>**(kHz)**|575|575|575|575|650|650|650|650|750|750||
|**EA–**<br>**gm**<br>**(mS)**|3.02|3.02|3.02|3.02|3.02|3.02|3.02|3.02|3.02|3.02||
|**RCOMP**<br>**(kΩ)**|15|15|15|15|15|15|15|15|15|15||
|**CCOMPa**<br>**(nF)**|2.2|2.2|2.2|2.2|2.2|2.2|2.2|2.2|2.2|2.2||
|**CCOMPb**<br>**(pF)**|150|150|150|150|150|150|150|150|150|150||
|**COUT**<br>**(BULK CAP)**|**470µF ×3|**470µF ×3|**470µF ×3|**470µF ×3|**470µF ×3|**470µF ×3|**470µF ×3|**470µF ×3|**470µF ×3|**470µF ×3||
|**COUT**<br>**(CER CAP)**|*100µF ×4|*100µF ×4|*100µF ×4|*100µF ×4|*100µF ×4|*100µF ×4|*100µF ×4|*100µF ×4|*100µF ×4|*100µF ×4||
|**VOUT**<br>**RANGE**|Low|Low|Low|Low|Low|Low|Low|Low|Low|Low||
|**ILIM**<br>**RANGE**|High|High|High|High|High|High|High|High|High|High||
|**VOUT**<br>**(V)**|0.7|0.7|0.9|0.9|1.0|1.0|1.2|1.2|1.35|1.35||
|**VIN**<br>**(V)**|5|12|5|12|5|12|5|12|5|12||
|**Table 14. Single Channel Output Voltage vs Capacitor Selection, All Ceramic Configuration, 10A to 20A Load Step with 10A/µs Slew Rate**|<br>**GAIN**<br>**MARGIN**<br>**CROSS**<br>**OVER FREQ**<br>**(kHz)**|73|75|76|69|80|73|82|73|87|76|*Murata GRM32EC80E227ME05L, 220μF, 2.5V, X6S.<br>These values should be check with a BODE Analyzer.|
|---|---|---|---|---|---|---|---|---|---|---|---|---|
||**GAIN**<br>**MARGIN**<br>**(dB)**|–13|–14|–13|–12|–14|–13|–14|–12|–15|–13||
||**PHASE**<br>**MARGIN**<br>**(DEG)**|38|40|38|37|38|38|39|38|39|38||
||**PHASE**<br>**MARGIN**<br>**CROSS**<br>**OVER FREQ**<br>**(kHz)**|30|28|30|29|31|29|31|30|32|30||
||**RECOVERY**<br>**TIME (μs)**|28|24|23|22|22|22|21|20|19|21||
||**PK–PK**<br>**DEVIATION**<br>**(mV)**|77|77|75|76|75|77|76|78|74|76||
||**VOUT**<br>**DROOP**<br>**(mV)**|39|39|38|38|38|39|38|39|37|38||
||**LOAD**<br>**STEP (A)**|10 to 20|10 to 20|10 to 20|10 to 20|10 to 20|10 to 20|10 to 20|10 to 20|10 to 20|10 to 20||
||**fSW**<br>**(kHz)**|575|575|575|575|650|650|650|650|750|750||
||**EA–**<br>**gm**<br>**(mS)**|3.02|3.02|3.02|3.02|3.02|3.02|3.02|3.02|3.02|3.02||
||**RCOMP**<br>**(kΩ)**|15|15|15|15|15|15|15|15|15|15||
||**CCOMPa**<br>**(nF)**|2.2|2.2|2.2|2.2|2.2|2.2|2.2|2.2|2.2|2.2||
||**CCOMPb**<br>**(pF)**|150|150|150|150|150|150|150|150|150|150||
||**COUT**<br>**(BULK**<br>**CAP)**|none|none|none|none|none|none|none|none|none|none||
||**COUT**<br>**(CER CAP)**|*220µF ×10|*220µF ×10|*220µF ×10|*220µF ×10|*220µF ×10|*220µF ×10|*220µF ×10|*220µF ×10|*220µF ×10|*220µF ×10||
||**VOUT**<br>**RANGE**|Low|Low|Low|Low|Low|Low|Low|Low|Low|Low||
||**ILIM**<br>**RANGE**|High|High|High|High|High|High|High|High|High|High||
||**VOUT**<br>**(V)**|0.7|0.7|0.9|0.9|1.0|1.0|1.2|1.2|1.35|1.35||
||**VIN**<br>**(V)**|5|12|5|12|5|12|5|12|5|12||
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## **APPLICATIONS INFORMATION**
|**Table 15. Dual Connected Channels Output Voltage vs Capacitor Selection, Bulk and Ceramic Cap Configuration, 10A to 30A Load Step with 20A/µs Slew Rate**|<br>**GAIN**<br>**MARGIN**<br>**CROSS**<br>**OVER FREQ**<br>**(kHz)**|166|150|159|159|166|*TDK C3225X5R0J107M, 100μF, 6.3V, X5R.<br>**Panasonic EEFGX0D561R, 560μF, 2.0V, 3mΩ.<br>These Values Should Be Check with a BODE Analyzer.|
|---|---|---|---|---|---|---|---|
||**GAIN**<br>**MARGIN**<br>**(dB)**|–14|–14|–14|–14|–14||
||**PHASE**<br>**MARGIN**<br>**(DEG)**|55|53|54|53|54||
||<br>**PHASE**<br>**MARGIN**<br>**CROSS**<br>**OVER**<br>**FREQ**<br>**(kHz)**|33|33|33|34|34||
||**RECOVERY**<br>**TIME (μs)**|48|42|39|32|30||
||**PK–PK**<br>**DEVIATION**<br>**(mV)**|74|75|74|73|73||
||**VOUT**<br>**DROOP**<br>**(mV)**|37|37|37|37|37||
||**LOAD**<br>**STEP (A)**|10 to 30|10 to 30|10 to 30|10 to 30|10 to 30||
||**fSW**<br>**(kHz)**|575|575|650|650|750||
||**EA–**<br>**gm**<br>**(mS)**|3.02|3.02|3.02|3.02|3.02||
||**RCOMP**<br>**(kΩ)**|15|15|15|15|15||
||**CCOMPa**<br>**(nF)**|3.3|3.3|3.3|3.3|3.3||
||**CCOMPb**<br>**(pF)**|150|150|150|150|150||
||**COUT**<br>**(BULK CAP)**|**560µF ×4|**560µF ×4|**560µF ×4|**560µF ×4|**560µF ×4||
||**COUT**<br>**(CER CAP)**|*100µF ×8|*100µF ×8|*100µF ×8|*100µF ×8|*100µF ×8||
||**VOUT**<br>**RANGE**|Low|Low|Low|Low|Low||
||**ILIM**<br>**RANGE**|High|High|High|High|High||
||**VOUT**<br>**(V)**|0.7|0.9|1.0|1.2|1.35||
||**VIN**<br>**(V)**|12|12|12|12|12||
|**Table 16. Quad Connected Channels Output Voltage vs Capacitor Selection, Bulk and Ceramic Cap Configuration, 10A to 40A Load Step with 15A/µs Slew Rate**|<br>**GAIN**<br>**MARGIN**<br>**CROSS**<br>**OVER**<br>**FREQ (kHz)**|145|137|144|146|153|*TDK C3225X5R0J107M, 100μF, 6.3V, X5R.<br>**Panasonic EEFGX0D561R, 560μF, 2.0V, 3mΩ.<br>These Values Should Be Check with a BODE Analyzer.|
|---|---|---|---|---|---|---|---|
||**GAIN**<br>**MARGIN**<br>**(dB)**|–7|–7|–7|–7|–8||
||**PHASE**<br>**MARGIN**<br>**(DEG)**|43|40|42|42|45||
||<br>**PHASE**<br>**MARGIN**<br>**CROSS**<br>**OVER**<br>**FREQ**<br>**(kHz)**|62|63|63|64|62||
||**RECOVERY**<br>**TIME (μs)**|24|20|20|17|13||
||**PK–PK**<br>**DEVIATION**<br>**(mV)**|62|63|60|63|64||
||**VOUT**<br>**DROOP**<br>**(mV)**|31|32|30|32|32||
||**LOAD**<br>**STEP (A)**|10 to 40|10 to 40|10 to 40|10 to 40|10 to 40||
||**fSW**<br>**(kHz)**|575|575|650|650|750||
||**EA–gm**<br>**(mS)**|3.02|3.02|3.02|3.02|3.02||
||**RCOMP**<br>**(kΩ)**|15|15|15|15|15||
||**CCOMPa**<br>**(nF)**|6.8|6.8|6.8|6.8|6.8||
||**CCOMPb**<br>**(pF)**|150|150|150|150|150||
||**COUT**<br>**(BULK**<br>**CAP)**|**560µF ×4|**560µF ×4|**560µF ×4|**560µF ×4|**560µF ×4||
||**COUT**<br>**(CER CAP)**|*100µF ×12|*100µF ×12|*100µF ×12|*100µF ×12|*100µF ×12||
||**VOUT**<br>**RANGE**|Low|Low|Low|Low|Low||
||**ILIM**<br>**RANGE**|High|High|High|High|High||
||**VOUT**<br>**(V)**|0.7|0.9|1.0|1.20|1.35||
||**VIN**<br>**(V)**|12|12|12|12|12||
Rev. 0
73
For more information www.analog.com
LTM4682
## **APPLICATIONS INFORMATION**
## **EMI PERFORMANCE**
The SW _n_ pin provides access to the midpoint of the power MOSFETs in LTM4682’s power stages.
Connecting an optional series RC network from SW _n_ to GND can dampen high-frequency (~30MHz+) switch node ringing caused by parasitic inductances and capacitances in the switched-current paths. The RC network is called a snubber circuit because it dampens (or snubs) the resonance of the parasitics, at the expense of higher power loss. To use a snubber, choose first how much power to allocate to the task and how much PCB real estate is available to implement the snubber. For example, if PCB space allows a low inductance 0.5W resistor to be used, then the capacitor in the snubber network (CSW) is computed by:
**==> picture [107 x 34] intentionally omitted <==**
where VIN _n_ (MAX) is the maximum input voltage that the input to the power stage (VIN _n_ ) will see in the application, and fSW is the DC/DC converter’s switching frequency of operation. CSW should be NPO, C0G, or X7R-type (or better) material.
The snubber resistor (RSW) value is then given by:
**==> picture [65 x 33] intentionally omitted <==**
The snubber resistor should be low ESL and capable of withstanding the pulsed currents present in snubber circuits. A value between 0.7Ω and 4.2Ω is normal.
A 2.2nF snubber capacitor is a good value to start with in series with the snubber resistor to the ground. The no-load input quiescent current can be monitored while selecting different RC series snubber components to get an increased power loss versus switch node ringing attenuation.
## **SAFETY CONSIDERATIONS**
The LTM4682 modules do not provide galvanic isolation from VIN to VOUT. There is no internal fuse. If required, a slow blow fuse with a rating twice the maximum input current must be provided to protect each unit from catastrophic failure.
The fuse or circuit breaker should be selected to limit the current to the regulator during overvoltage in case of an internal top MOSFET fault. If the internal top MOSFET fails, then turning it off will not resolve the overvoltage. Thus, the internal bottom MOSFET will turn on indefinitely, trying to protect the load. Under this fault condition, the input voltage will source very large currents to the ground - through the failed internal top MOSFET and enabled inter nal bottom MOSFET. This can cause excessive heat and board damage depending on how much power the input voltage can deliver to this system. A fuse or circuit breaker can be used as a secondary fault protector in this situation. The device supports overcurrent and overtemperature protection.
Rev. 0
74
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LTM4682
## **APPLICATIONS INFORMATION**
## **LAYOUT CHECKLIST/EXAMPLE**
The high integration of LTM4682 makes the PCB board layout very simple and easy. However, to optimize its electrical and thermal performance, some layout considerations are still necessary.
- n Use large PCB copper areas for high current paths, including VIN _n_ , GND, and VOUT _n_ . It helps to minimize the PCB conduction loss and thermal stress.
- n Place high-frequency ceramic input and output capacitors next to the VINn, GND, and VOUT _n_ pins to minimize high-frequency noise.
- n Place a dedicated power ground layer underneath the module.
- n To minimize the via conduction loss and reduce module thermal stress, use multiple vias for interconnection between the top layer and other power layers.
- n Do not put vias directly on pads, unless they are capped or plated over.
- n Use a separate SGND copper plane for components connected to signal pins. Connect SGND to GND local to the LTM4682.
- n Use Kelvin sense connections across the input RSENSE resistor if input current monitoring is used.
For parallel modules, connect the VOUT _n_ , VOSNS _n_[+] /VOSNS _n_[–] voltage-sense differential pair lines, RUN _n_ , COMP _n_ a, and COMP _n_ b pins together.
- n The user must share the SYNC nn_ , SHARE_CLK nn_ , FAULT _n_ , and ALERT nn_ pins of these parts. Be sure to use pull-up resistors on FAULT _n_ , SHARE_CLK nn_ , and ALERT nn_ .
- n Bring out test points on the signal pins for monitoring.
Figure 47 gives a good example of the recommended layout.
**==> picture [255 x 188] intentionally omitted <==**
**----- Start of picture text -----**<br>
VOUT0 VOUT1 GND VOUT2 VOUT3<br>GND GND<br>VIN VIN<br>GND<br>4682 F47a<br>**----- End of picture text -----**<br>
- **(a) LTM4682 Top Layer**
**==> picture [255 x 188] intentionally omitted <==**
**----- Start of picture text -----**<br>
VOUT0 VOUT1 GND VOUT2 VOUT3<br>GND GND<br>VIN VIN<br>GND<br>4682 F47b<br>**----- End of picture text -----**<br>
**==> picture [109 x 11] intentionally omitted <==**
**----- Start of picture text -----**<br>
(b) LTM4682 Bottom Layer<br>**----- End of picture text -----**<br>
**Figure 47. Recommended PCB Layout Package Top View**
Rev. 0
75
For more information www.analog.com
LTM4682
## **TYPICAL APPLICATION**
**==> picture [522 x 447] intentionally omitted <==**
**----- Start of picture text -----**<br>
VDD33_01<br>4.7µF 22µF<br>I [2] C/SMBus I/F WITH PMBus COMMAND 10k 10k 4.99k 4.99k 4.99k 4.99k 4.99k<br>SET TO/FROM IPMI OR OTHER BOARD 4.7µF<br>MANAGEMENT CONTROLLER<br>SW0<br>0.70V AT 31.25A<br>+ VIN, 6V TO 16V IN_01 [+] VOSNS0VOUT0 [+] LOAD 100µF×4 + 470µF×3<br>150µF 22µF×6 1mΩ VOSNS0 [–]<br>1Ω IN_01 [–]<br>VIN01 SW1<br>SVIN_01 0.75V AT 31.25A<br>1µF IN_23 [+] VOSNS1VOUT1 [+] LOAD 100µF×4 + 470µF×3<br>1mΩ VOSNS1 [–]<br>1Ω IN_23 [–]<br>VIN23 SW2<br>1µF SVVRUNPIN_VBIASIN_23 LTM4682 VOSNS2VOUT2 [+] LOAD 100µF×41.0V AT 31.25A+ 470µF×3<br>VDD33_01 10k VOSNS2 [–]<br>RUN0<br>10k<br>10k 10k RUN1 SW3<br>10k ON_OFF_CONFIG RUN2RUN3FAULT0 VOSNS3VOUT3 [+] LOAD 100µF×41.2V AT 31.25A+ 470µF×3<br>FAULT1 VOSNS3 [–]<br>FAULT2<br>FAULT INTERRUPTS<br>FAULT3<br>10k<br>PGOOD0 GND<br>10k<br>10k PGOOD1 SGND_23<br>POWER GOOD 10k PGOOD2 SGND_01 SGND<br>PGOOD3<br>4682 F48<br>2200pF 2200pF 2200pF 2200pF 32.4k 22.6k<br>150pF 150pF 150pF 150pF<br>14.3k 14.3k<br>14.3k 14.3k 14.3k 14.3k 14.3k<br>12.7k 15.4k<br>787Ω 787Ω 12.7k 2.43k 3.24k<br>CHANNEL 0: gm = 3.02mS, RCOMP = 15k, FREQ = 575kHz CONFIG RESISTORS ARE TO BE 1%, 50PPM<br>CHANNEL 1: gm = 3.02mS, RCOMP = 15k, FREQ = 575kHz MFR_CONFIG_ALL[4] = 0 (ENABLE SYNC)<br>CHANNEL 2: gm = 3.02mS, RCOMP = 15k, FREQ = 650kHz MFR_CONFIG_ALL[6] = 0 (RESPECT ALL RESISTOR CONFIGURATION PINS)<br>CHANNEL 3: gm = 3.02mS, RCOMP = 15k, FREQ = 650kHz DEVICE 0,1 ADDRESS: 100_1111_R/W<br>DEVICE 2,3 ADDRESS: 100_1110_R/W<br>DD33_01 DD33_23 DD25_01 DD25_23<br>V V V V<br>_23 _01 BIAS<br>ALERT ALERT SYNC_23 SYNC_01 SDA_23 SDA_01 SCL_23 SCL_01 WP_01 WP_23 VDD33_01 VDD33_23 VDD25_01 VDD25_23 INTVCC_01 INTVCC_23 V TSNS0 TSNS1 TSNS2 TSNS3<br>SHARE_CLK_23 SHARE_CLK_01<br>COMP0a COMP0b COMP1a COMP1b COMP2a COMP2b COMP3a COMP3b VOUT0_CFG VTRIM0_CFG VOUT1_CFG VTRIM1_CFG VOUT2_CFG VTRIM2_CFG VOUT3_CFG VTRIM3_CFG FSWPH_23_CFG FSWPH_01_CFG ASEL_01 ASEL_23<br>DD25_23 DD25_01<br>V V<br>DD25_01 DD25_01 DD25_01 DD25_23 DD25_23<br>V V V V V<br>**----- End of picture text -----**<br>
**Figure 48. Quad 31.25A DC/DC µModule Regulator with I[2] C/SMBus/PMBus Serial Interface**
Rev. 0
76
For more information www.analog.com
LTM4682
## **TYPICAL APPLICATION**
**==> picture [524 x 437] intentionally omitted <==**
**----- Start of picture text -----**<br>
VDD33_01<br>4.7µF 22µF<br>I [2] C/SMBus I/F WITH PMBus COMMAND 10k 10k 4.99k 4.99k 4.99k 4.99k 4.99k<br>SET TO/FROM IPMI OR OTHER BOARD 4.7µF<br>MANAGEMENT CONTROLLER<br>SW0<br>0.75V AT 60A<br>VIN, 6V TO 16V VOUT0 220µF<br>+ IN_01 [+] ×4<br>150µF 22µF×6 1Ω 1mΩ IN_01VSVIN01IN_01 [–] VVOSNS0OSNS0 [+][–] VVOSNS0OSNS0 [+] [–] LOAD + 560µF×2<br>1µF SW1<br>IN_23 [+] VOUT1<br>220µF<br>1mΩ ×4<br>1Ω IN_23 [–] VOSNS1 [+] VOSNS0 [+]<br>VIN23 VOSNS1 [–] VOSNS0 [–]<br>SVIN_23 SW2<br>1µF 1V AT 60A<br>VOUT2 220µF<br>VDD33_01 VIN_VBIAS LTM4682 ×4<br>RUNP VOSNS2 [+] VOSNS2 [+]<br>10k RUN0 LOAD + 560µF<br>10k RUN1RUN2 VOSNS2 [–] VOSNS2 [–] ×2<br>10k ON_OFF_CONFIG RUN3 SW3<br>10k FAULTFAULT01 VOUT3 220µF×4<br>FAULT INTERRUPTS FAULT2 VOSNS3 [+] VOSNS2 [+]<br>10k FAULT3 VOSNS3 [–] VOSNS2 [–]<br>PGOOD0<br>GND<br>PGOOD1<br>10k PGOOD_0.75V PGOOD2 SGND_23<br>PGOOD3 SGND_01 SGND<br>PGOOD_1V<br>4682 F49<br>32.4k 22.6k<br>3300pF 3300pF 3300pF 3300pF<br>150pF 150pF 150pF 150pF 14.3k 14.3k<br>14.3k 14.3k 14.3k<br>787Ω 12.7k 2.43k 12.7k 15.4k CONFIG RESISTORS ARE TO BE 1%, 50PPM<br>MFR_CONFIG_ALL[4] = 0 (ENABLE SYNC)<br>CHANNEL 0: gm = 3.02ms, RCOMP = 9k, FREQ = 575kHz MFR_CONFIG_ALL[6] = 0 (RESPECT ALL RESISTOR<br>CHANNEL 1: gm = 3.02ms, RCOMP = 9k, FREQ = 575kHz CONFIGURATION PINS)<br>CHANNEL 2: gm = 3.02ms, RCOMP = 11k, FREQ = 650kHz DEVICE 0,1 ADDRESS: 100_1111_R/W<br>CHANNEL 3: gm = 3.02ms, RCOMP = 11k, FREQ = 650kHz DEVICE 2,3 ADDRESS: 100_1110_R/W<br>DD33_01 DD33_23 DD25_01 DD25_23<br>V V V V<br>_23 _01 BIAS<br>ALERT ALERT SYNC_23 SYNC_01 SDA_23 SDA_01 SCL_23 SCL_01 WP_01 WP_23 VDD33_01 VDD33_23 VDD25_01 VDD25_23 INTVCC_01 INTVCC_23 V TSNS0 TSNS1 TSNS2 TSNS3<br>SHARE_CLK_23 SHARE_CLK_01<br>COMP0a COMP0b COMP1a COMP1b COMP2a COMP2b COMP3a COMP3b VOUT0_CFG VOUT1_CFG VTRIM0_CFG VTRIM1_CFG VOUT2_CFG VOUT3_CFG VTRIM2_CFG VTRIM3_CFG FSWPH_23_CFG FSWPH_01_CFG ASEL_01 ASEL_23<br>DD25_23 DD25_01<br>V V<br>DD25_01 DD25_01 DD25_23<br>V V V<br>**----- End of picture text -----**<br>
**Figure 49. 0.75V and 1V Outputs at 60A with Providing I[2] C/SMBus/PMBus Serial Interface**
Rev. 0
77
For more information www.analog.com
LTM4682
## **TYPICAL APPLICATION**
**==> picture [485 x 587] intentionally omitted <==**
**----- Start of picture text -----**<br>
I [2] C/SMBus I/F WITH PMBus COMMAND VDD33A_01<br>SET TO/FROM IPMI OR OTHER BOARD<br>MANAGEMENT CONTROLLER 4.99k 4.99k 4.99k 4.99k 4.99k 4.7µF 22µF<br>ALERT SHARE_CLK SYNC SDA SCL 4.7µF<br>150µF + VIN, 6V TO 16V22µF×6 1Ω 1mΩ IN_01IN_01 [+][–] VOUT0SW0 220µF×2 + 560µF<br>VIN01 ×2<br>SVIN_01 VOSNS0 [+] VOSNS [+]<br>1µF VOSNS0 [–] VOSNS [–]<br>SW1<br>1mΩ IN_23 [+] VOUT1 220µF×2<br>1Ω IN_23 [–]<br>VIN23 VOSNS1 [+] VOSNS [+]<br>SVIN_23 VOSNS1 [–] VOSNS [–]<br>1µF SW2<br>VDD33A_01 VRUNPIN_VBIAS MODULE ALTM4682 VOUT2 220µF×2 + 560µF<br>RUN0 VOSNS2 [+] VOSNS [+] ×2<br>4.99k RUN RUN1 VOSNS2 [–] VOSNS [–]<br>4.99kON_OFF_CONFIG RUN2RUN3FAULT0 VOUT3SW3 220µF×2<br>FAULTB FAULT1<br>FAULT2 VOSNS3 [+] VOSNS [+]<br>FAULT INTERRUPTS FAULT3 VOSNS3 [–] VOSNS [–]<br>4.99k PGOOD0 GND<br>PGOOD1<br>PGOOD2 SGND_23<br>PGOOD_0.9V PGOOD3 SGND_01 SGND<br>COMPb 32.4k<br>COMPa 22.6k<br>0.015μF 330pF 14.3k 14.3k 14.3k 14.3k CONFIG RESISTORS ARE TO BE 1%, 50PPM<br>CHANNEL 1: gCHANNEL 0: gmm = 3.02mS, R = 3.02mS, RCOMPCOMP = 2k, FREQ = = 2k, FREQ = 575kHz575kHz, 0°, 180°, EXT, 0°, 180° 1.65k 1.65k 1.65k 15.4k MFR_CONFIG_ALL BIT[6] = 0MFR_CONFIG_ALL BIT[4] = 0MAIN DEVICE 0,1 ADDRESS: 100_1111_R/W<br>CHANNEL 2: gCHANNEL 3: gmm = 3.02mS, R = 3.02mS, RCOMPCOMP = 2k, FREQ = 575kHz, 90°, 270°= 2k, FREQ = 575kHz, EXT, 90°, 270° MFR_CONFIG_ALL BIT[4] = 1SUBORDINATE DEVICE 2,3 ADDRESS:1 00_1110_R/W<br>SET TO/FROM IPMI OR OTHER BOARDI [2] C/SMBus I/F WITH PMBus COMMAND VOSNS [+]<br>MANAGEMENT CONTROLLER 4.7µF 22µF<br>ALERT SHARE_CLK SYNC SDA SCL 4.7µF 0.9V AT 250ALOAD<br>150µF + VIN, 6V TO 16V22µF×6 1Ω 1mΩ IN_01IN_01 [+][–] VOUT0SW0 220µF×2 V+OSNS [–]<br>VSVIN01IN_01 VOSNS0 [+] VOSNS [+] 560µF×2<br>1µF VOSNS0 [–] VOSNS [–]<br>SW1<br>1mΩ IN_23 [+] VOUT1 220µF×2<br>1Ω IN_23 [–]<br>VIN23 VOSNS1 [+] VOSNS [+]<br>SVIN_23 VOSNS1 [–] VOSNS [–]<br>1µF SW2<br>VRUNPIN_VBIAS MODULE BLTM4682 VOUT2 220µF×2 + 560µF<br>RUN0 VOSNS2 [+] VOSNS [+] ×2<br>ON_OFF_CONFIGRUN RUN1RUN2RUN3FAULT0 VOSNS2VOUT3SW3 [–] VOSNS [–] 220µF×2<br>FAULT1<br>FAULTB<br>FAULT2 VOSNS3 [+] VOSNS [+]<br>FAULT INTERRUPTS FAULT3 VOSNS3 [–] VOSNS [–]<br>PGOOD0 GND<br>PGOOD1<br>PGOOD2 SGND_23<br>PGOOD_0.9V PGOOD3 SGND_01<br>4682 F50<br>COMPb 18k<br>COMPa 15.4k<br>14.3k 14.3k 14.3k 14.3k<br>CHANNEL 0: gm = 3.02mS, RCOMP = 2k, FREQ = 575kHz, 0°, 180° CONFIG RESISTORS ARE TO BE 1%, 50PPM<br>CHANNEL 1: gm = 3.02mS, RCOMP = 2k, FREQ = 575kHz, EXT, 0°, 180° MFR_CONFIG_ALL BIT[6] = 0<br>CHANNEL 2: gm = 3.02mS, RCOMP = 2k, FREQ = 575kHz, 90°, 270° 1.65k 1.65k 1.65k 15.4k MFR_CONFIG_ALL BIT[4] = 1<br>CHANNEL 3: gm = 3.02mS, RCOMP = 2k, FREQ = 575kHz, EXT, 90°, 270° SUBORDINATE DEVICE 0,1 ADDRESS: 100_1101_R/W<br>SUBORDINATE DEVICE 2,3 ADDRESS: 100_1100_R/W<br>VDD33A_01 VDD33A_23 VDD25A_01 VDD25A_23<br>ALERT_23 ALERT_01 SYNC_23 SYNC_01 SDA_23 SDA_01 SCL_23 SCL_01 WP_01 WP_23 VDD33_01 VDD33_23 VDD25_01 VDD25_23 INTVCC_01 INTVCC_23 VBIAS TSNS0 TSNS1 TSNS2 TSNS3<br>SHARE_CLK_23 SHARE_CLK_01<br>COMP0a COMP0b COMP1a COMP1b COMP2a COMP2b COMP3a COMP3b VOUT0_CFG VTRIM0_CFG VOUT1_CFG VTRIM1_CFG VOUT2_CFG VTRIM2_CFG VOUT3_CFG VTRIM3_CFG FSWPH_23_CFG FSWPH_01_CFG ASEL_01 ASEL_23<br>VDD25A_01 VDD25A_23 VDD25A_23 VDD25A_01<br>VDD33B_01 VDD33B_23 VDD25B_01 VDD25B_23<br>ALERT_23 ALERT_01 SYNC_23 SYNC_01 SDA_23 SDA_01 SCL_23 SCL_01 WP_01 WP_23 VDD33_01 VDD33_23 VDD25_01 VDD25_23 INTVCC_01 INTVCC_23 VBIAS TSNS0 TSNS1 TSNS2 TSNS3<br>SHARE_CLK_23 SHARE_CLK_01<br>COMP0a COMP0b COMP1a COMP1b COMP2a COMP2b COMP3a COMP3b VOUT0_CFG VTRIM0_CFG VOUT1_CFG VTRIM1_CFG VOUT2_CFG VTRIM2_CFG VOUT3_CFG VTRIM3_CFG FSWPH_23_CFG FSWPH_01_CFG ASEL_01 ASEL_23<br>VDD25B_01 VDD25B_23 VDD25B_23 VDD25B_01<br>**----- End of picture text -----**<br>
**Figure 50. Two Paralleled LTM4682 Producing 0.9VOUT at 250A, Integrated Power System Management Features Accessible Over 2-Wire I[2] C/SMBus/PMBus Serial Interface**
Rev. 0
78
For more information www.analog.com
LTM4682
## **TYPICAL APPLICATION**
**==> picture [516 x 437] intentionally omitted <==**
**----- Start of picture text -----**<br>
VDD33_01<br>SVIN_01 SVIN_23<br>I [2] C/SMBus I/F WITH PMBus COMMAND 10k 10k 4.99k 4.99k 4.99k 4.99k<br>SET TO/FROM IPMI OR OTHER BOARD 4.7µF 4.7µF<br>MANAGEMENT CONTROLLER<br>VIN_ON, VIN_OFF, VIN_OV, VIN_UV ARE<br>ADJUSTED FOR LOW VIN OPERATION<br>SW0<br>5V 0.75V AT 60A<br>+ 150µF×2 22µF×6 1Ω 1mΩ IN_01IN_01 [+][–] VOUT0 VOSNS0 [+] 220µF×4<br>SV1µFIN_01 VSVIN01IN_01 VVOSNS0OSNS0 [+][–] VOSNS0 [–] LOAD + 560µF×2<br>SW1<br>5V IN_23 [+]<br>22µF×6 5V 1mΩ VOUT1 220µF<br>IN_23 [–] 23<br>SV1ΩIN_23 VSVIN23IN_23 VVOSNS1OSNS1 [+][–] VVOSNS0OSNS0 [+][–]<br>1µF SW2<br>1V AT 60A<br>VDD33_01 VRUNPIN_VBIAS LTM4682 VOUT2 220µF×4<br>10kENABLE10k RUN0RUN1RUN2 VVOSNS2OSNS2 [+][–] VVOSNS2OSNS2 [+][–] LOAD + 560µF×2<br>RUN3<br>10k SW3<br>FAULT0<br>10k FAULT1 VOUT3 220µF<br>FAULT INTERRUPTS FAULT2 VOSNS3 [+] VOSNS2 [+] ×4<br>10k FAULT3 VOSNS3 [–] VOSNS2 [–]<br>PGOOD0<br>PGOOD1 GND<br>10k PGOOD_0.75V PGOOD2 SGND_23<br>PGOOD_1V PGOOD3 SGND_01 SGND<br>4682 F51<br>32.4k 22.6k<br>3300pF 3300pF 3300pF 3300pF<br>14.3k<br>100pF 100pF 100pF 100pF 14.3k 14.3k 14.3k<br>787Ω 12.7k 2.43k 15.4k CONFIG RESISTORS ARE TO BE 1%, 50PPM<br>CHANNEL 0: gCHANNEL 1: gCHANNEL 2: gCHANNEL 3: gmmmm = 3.02mS, R = 3.02mS, R = 3.02mS, R = 3.02mS, RCOMPCOMPCOMPCOMP = 9k, FREQ = 575kHz = 9k, FREQ = 575kHz = 11k, FREQ = 575kHz= 11k, FREQ = 575kHz MFR_CONFIG_ALL BIT[6] = 0MFR_CONFIG_ALL BIT[4] = 0MAIN DEVICE 0,1 ADDRESS: 100_1111_R/WMFR_CONFIG_ALL BIT[4] = 1SUBORDINATE DEVICE 2,3 ADDRESS:100_1110_R/W<br>DD33_01 DD33_23 DD25_01 DD25_23<br>V V V V<br>_23 _01 BIAS<br>ALERT ALERT SYNC_23 SYNC_01 SDA_23 SDA_01 SCL_23 SCL_01 WP_01 WP_23 VDD33_01 VDD33_23 VDD25_01 VDD25_23 INTVCC_01 INTVCC_23 V TSNS0 TSNS1 TSNS2 TSNS3<br>SHARE_CLK_23 SHARE_CLK_01<br>COMP0a COMP0b COMP1a COMP1b COMP2a COMP2b COMP3a COMP3b VOUT0_CFG VOUT1_CFG VTRIM0_CFG VTRIM1_CFG VOUT2_CFG VOUT3_CFG VTRIM2_CFG VTRIM3_CFG FSWPH_23_CFG FSWPH_01_CFG ASEL_01 ASEL_23<br>DD25_23<br>V<br>DD25_01 DD25_01 DD25_23<br>V V V<br>**----- End of picture text -----**<br>
## **Figure 51. 0.75V/60A and 1V/60A Outputs Generated from 5V Power Input and Providing I[2] C/SMBus/PMBus Serial Interface**
Rev. 0
79
For more information www.analog.com
LTM4682
## **TYPICAL APPLICATION**
**==> picture [486 x 589] intentionally omitted <==**
**----- Start of picture text -----**<br>
I [2] C/SMBus I/F WITH PMBus COMMAND VDD33A_01<br>SET TO/FROM IPMI OR OTHER BOARD<br>MANAGEMENT CONTROLLER 4.99k 4.99k 4.99k 4.99k 4.99k 4.7µF 22µF<br>ALERT SHARE_CLK SYNC SDA SCL 4.7µF<br>150µF×2 + VIN, 6V TO 16V22µF×6 1Ω 1mΩ IN_01IN_01 [+][–] VOUT0SW0 100µF×2 + 560µF<br>VIN01 ×1<br>SVIN_01 VOSNS0 [+] VOSNS [+]<br>1µF VOSNS0 [–] VOSNS [–]<br>SW1<br>1mΩ IN_23 [+] VOUT1 100µF×2<br>1Ω IN_23 [–]<br>VIN23 VOSNS1 [+] VOSNS [+]<br>SVIN_23 VOSNS1 [–] VOSNS [–]<br>1µF SW2<br>VDD33A_01 VRUNPIN_VBIAS MODULE ALTM4682 VOUT2 100µF×2 + 560µF<br>RUN0 VOSNS2 [+] VOSNS [+] ×1<br>4.99k RUN RUN1 VOSNS2 [–] VOSNS [–]<br>4.99kON_OFF_CONFIG RUN2RUN3FAULT0 VOUT3SW3 100µF×2<br>FAULTB FAULT1<br>FAULT2 VOSNS3 [+] VOSNS [+]<br>FAULT INTERRUPTS FAULT3 VOSNS3 [–] VOSNS [–]<br>4.99k PGOOD0 GND<br>PGOOD1<br>PGOOD2 SGND_23<br>PGOOD_0.9V PGOOD3 SGND_01 SGND<br>COMPb 32.4k<br>COMPa 22.6k<br>MODULE A 6800pF 150pF 14.3k 14.3k 14.3k 14.3k<br> CHANNEL 0: gm = 3.02mS, RCOMP = 4k, FREQ = 650kHz, 0 CONFIG RESISTORS ARE TO BE 1%, 50PPM<br> CHANNEL 1: gm = 3.02mS, RCOMP = 4k, FREQ = 650kHz, 180 MFR_CONFIG_ALL BIT[6] = 0<br> CHANNEL 2: gm = 3.02mS, RCOMP = 4k, FREQ = 650kHz, EXT 90 1.65k 1.65k 1.65k 12.7k MFR_CONFIG_ALL BIT[4] = 0 (ENABLE SYNC)<br> CHANNEL 3: gm = 3.02mS, RCOMP = 4k, FREQ = 650kHz, EXT 270 MAIN DEVICE 0,1 ADDRESS: 100_1111_R/W<br>MFR_CONFIG_ALL BIT[4] = 1 (DISABLE SYNC)<br>SUBORDINATE DEVICE 2,3 ADDRESS: 100_1110_R/W<br>SET TO/FROM IPMI OR OTHER BOARDI [2] C/SMBus I/F WITH PMBus COMMAND VOSNS [+]<br>MANAGEMENT CONTROLLER 4.7µF 22µF<br>ALERT SHARE_CLK SYNC SDA SCL 4.7µF 0.9V AT 187ALOAD<br>150µF×2 + VIN, 6V TO 16V22µF×6 1Ω 1mΩ IN_01IN_01 [+][–] VOUT0SW0 100µF×2 V+OSNS [–] 560µF<br>VIN01 ×1<br>SVIN_01 VOSNS0 [+] VOSNS [+]<br>1µF VOSNS0 [–] VOSNS [–]<br>SW1<br>1mΩ IN_23 [+] VOUT1 100µF×2<br>1Ω IN_23 [–]<br>VIN23 VOSNS1 [+] VOSNS [+]<br>SVIN_23 VOSNS1 [–] VOSNS [–]<br>1µF<br>VDD33B_23 4.99k 4.99k RUN VRUNPRUN0RUN1IN_VBIAS MODULE BLTM4682 VVOSNS2OSNS2VOUT2SW2 [+][–] VVOSNS1VOSNS1V [+][–] 100µF×4 1V AT 30A+ 560µF×2<br>RUN2<br>4.99k 4.99k FAULT INTERRUPTSON_OFF_CONFIGFAULTB RUN3FAULTFAULTFAULT012 VVOSNS3OSNS3VOUT3SW3 [+][–] VVOSNS1V2OSNS1V2 [+][–] 100µF×4 1.2V AT 30A+ 560µF×2<br>FAULT3<br>4.99k PGOOD_0.9V PGOOD0PGOOD1 GND<br>4.99k PGOOD_1.2VPGOOD_1V PGOOD2PGOOD3 SGND_23SGND_01 SGND<br>4682 F52<br>COMPb 100pF 100pF 18k 15.4k<br>COMPa 3300pF 3300pF<br>14.3k 14.3k 14.3k 14.3k 14.3k 14.3k<br> CHANNEL 1: g CHANNEL 2: g CHANNEL 3: gMODULE B CHANNEL 0: gmmmm = 3.02mS, R = 3.02mS, R = 3.02mS, R = 3.02ms, RCOMP COMPCOMPCOMP = 4k, FREQ = 650kHz, 0° = 4k, FREQ = 650kHz, 180° = 15k, FREQ = 650kHz, EXT 90°= 15k, FREQ = 650kHz, EXT 270° 1.65k 2.43k 12.7k 32.4k 1.65k 12.7k CONFIG RESISTORS ARE TO BE 1%, 50PPMMFR_CONFIG_ALL BIT[6] = 0MFR_CONFIG_ALL BIT[4] = 0 (ENABLE SYNC)MAIN DEVICE 0,1 ADDRESS: 100_1111_R/WMFR_CONFIG_ALL BIT[4] = 1 (DISABLE SYNC)SUBORDINATE DEVICE 2,3 ADDRESS: 100_1110_R/W<br>VDD33A_01 VDD33A_23 VDD25A_01 VDD25A_23<br>ALERT_23 ALERT_01 SYNC_23 SYNC_01 SDA_23 SDA_01 SCL_23 SCL_01 WP_01 WP_23 VDD33_01 VDD33_23 VDD25_01 VDD25_23 INTVCC_01 INTVCC_23 VBIAS TSNS0 TSNS1 TSNS2 TSNS3<br>SHARE_CLK_23 SHARE_CLK_01<br>COMP0a COMP0b COMP1a COMP1b COMP2a COMP2b COMP3a COMP3b VOUT0_CFG VTRIM0_CFG VOUT1_CFG VTRIM1_CFG VOUT2_CFG VTRIM2_CFG VOUT3_CFG VTRIM3_CFG FSWPH_23_CFG FSWPH_01_CFG ASEL_01 ASEL_23<br>VDD25A_01 VDD25A_23 VDD25A_23 VDD25A_01<br>VDD33B_01 VDD33B_23 VDD25B_01 VDD25B_23<br>ALERT_23 ALERT_01 SYNC_23 SYNC_01 SDA_23 SDA_01 SCL_23 SCL_01 WP_01 WP_23 VDD33_01 VDD33_23 VDD25_01 VDD25_23 INTVCC_01 INTVCC_23 VBIAS TSNS0 TSNS1 TSNS2 TSNS3<br>SHARE_CLK_23 SHARE_CLK_01<br>COMP0a COMP0b COMP1a COMP1b COMP2a COMP2b COMP3a COMP3b VOUT0_CFG VTRIM0_CFG VOUT1_CFG VTRIM1_CFG VOUT2_CFG VOUT3_CFG VTRIM2_CFG VTRIM3_CFG FSWPH_23_CFG FSWPH_01_CFG ASEL_01 ASEL_23<br>VDD25B_01 VDD25B_23 VDD25B_23 VDD25B_23 VDD25B_23 VDD25B_01<br>**----- End of picture text -----**<br>
**Figure 52. Six-Phase Operation Producing 0.9V at 187A, One-Phase for 1V at 30A, and 1.2V at 30A, Power System Management Features Accessible Through LTM4682 Over 2-Wire I[2] C/SMBus/PMBus Serial Interface**
Rev. 0
80
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LTM4682
## **PMBus COMMAND DETAILS**
## **ADDRESSING AND WRITE PROTECT**
|**COMMAND NAME**|**CMD**<br>**CODE**|**DESCRIPTION**|**TYPE**|**PAGED**|**DATA**<br>**FORMAT**|**UNITS**|**NVM**|**DEFAULT**<br>**VALUE**|
|---|---|---|---|---|---|---|---|---|
|PAGE|0x00|Provides integration with multi-page PMBus devices.|R/W Byte|N|Reg|||0x00|
|PAGE_PLUS_WRITE|0x05|Write a supported command directlyto a PWM channel.|W Block|N|||||
|PAGE_PLUS_READ|0x06|Read a supported command directly from a PWM<br>channel.|Block<br>R/W|N|||||
|WRITE_PROTECT|0x10|Level of protection provided by the device against<br>accidental changes.|R/W Byte|N|Reg||Y|0x00|
|MFR_ADDRESS|0xE6|Sets the 7-bit I2C address byte.|R/W Byte|N|Reg||Y|0x4F|
|MFR_RAIL_ADDRESS|0xFA|Common address for PolyPhase outputs to adjust<br>commonparameters.|R/W Byte|Y|Reg||Y|0x80|
## _**PAGE**_
The PAGE command provides the ability to configure, control and monitor both PWM channels through only one physical address, either the MFR_ADDRESS or GLOBAL device address. Each PAGE contains the operating commands for one PWM channel.
Pages 0x00 and 0x01 correspond to Channel 0 and Channel 1, respectively, in this device.
ASEL_01 sets the address for Channels 0 and 1, and ASEL_23 sets the address for Channels 2 and 3. Each of the ASEL pins will have a different programmed address.
Setting PAGE to 0xFF applies any following paged commands to both outputs. With PAGE set to 0xFF, the LTM4682 will respond to read commands as if PAGE were set to 0x00 (Channel 0 results).
This command has one data byte.
## _**PAGE_PLUS_WRITE**_
The PAGE_PLUS_WRITE command provides a way to set the page within a device, send a command, and then send the data for the command, all in one communication packet. Commands allowed by the present write protection level may be sent with PAGE_PLUS_WRITE.
The value stored in the PAGE command is not affected by PAGE_PLUS_WRITE. If PAGE_PLUS_WRITE is used to send a non-paged command, the Page Number byte is ignored.
This command uses the Write Block protocol. An example of the PAGE_PLUS_WRITE command with PEC sending a command that has two data bytes is shown in Figure 53.
**==> picture [367 x 76] intentionally omitted <==**
**----- Start of picture text -----**<br>
1 7 1 1 8 1 8 1 8 1 8 1<br>S SUBORDINATE W A PAGE_PLUS A BLOCK COUNT A PAGE A COMMAND A …<br>ADDRESS COMMAND CODE (= 4) NUMBER CODE<br>8 1 8 1 8 1 1<br>LOWER DATA UPPER DATA<br>A A PEC BYTE A P<br>BYTE BYTE<br>4682 F53<br>**----- End of picture text -----**<br>
**Figure 53. Example of PAGE_PLUS_WRITE**
## _**PAGE_PLUS_READ**_
The PAGE_PLUS_READ command provides the ability to set the page within a device, send a command, and then read the data returned by the command, all in one communication packet.
Rev. 0
81
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LTM4682
## **PMBus COMMAND DETAILS**
The value stored in the PAGE command is not affected by PAGE_PLUS_READ. If PAGE_PLUS_READ is used to access data from a non-paged command, the Page Number byte is ignored.
This command uses the Process Call protocol. An example of the PAGE_PLUS_READ command with PEC is shown in Figure 54.
|||1|1|7||||1|1|||1|1|8|||1|1|8||||1|1|8|||1|1|8||1|1|||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|||S||SUBORDINATE<br>ADDRESS||||W||||A||PAGE_PLUS<br>COMMAND CODE|||A||BLOCK COUNT<br>(= 2)||||A||PAGE<br>NUMBER|||A||COMMAND<br>CODE||A||…||
|1||||7||1||||1||||8|1||||8||1||||8|1||||8|1||1|||
|Sr||||SUBORDINATE<br>ADDRESS||R||||A||||BLOCK COUNT<br>(= 2)|A||||LOWER DATA<br>BYTE||A||||UPPER DATA<br>BYTE|A||||PEC BYTE|NA||P|||
|||||||||||||||||||||||||||||||||4682 F54||||
**Figure 54. Example of PAGE_PLUS_READ**
Note: PAGE_PLUS commands cannot be nested. A PAGE_PLUS command cannot be used to read or write another PAGE_PLUS command. If this is attempted, the LTM4682 will NACK the entire PAGE_PLUS packet and issue a CML fault for Invalid/Unsupported Data.
## _**WRITE_PROTECT**_
The WRITE_PROTECT command is used to control writing to the LTM4682 device. This command does not indicate the status of the WP pin, which is defined in the MFR_COMMON command. The WP pin takes precedence over the value of this command.
|**BYTE**|**MEANING**|
|---|---|
|0x80|Disable all writes except to the WRITE_PROTECT, PAGE, MFR_<br>EE_UNLOCK, and STORE_USER_ALL commands.|
|0x40|Disable all writes except to the WRITE_PROTECT, PAGE,<br>MFR_EE_UNLOCK, MFR_CLEAR_PEAKS, STORE_USER_ALL,<br>OPERATION, and CLEAR_FAULTS command. Individual fault<br>bits can be cleared by writing a 1 to the respective bits in the<br>STATUS commands.|
|0x20|Disable all writes except to the WRITE_PROTECT, OPERATION,<br>MFR_EE_UNLOCK, MFR_CLEAR_PEAKS, CLEAR_FAULTS,<br>PAGE, ON_OFF_CONFIG, VOUT_COMMAND and STORE_USER_<br>ALL. Individual fault bits can be cleared by writing a 1 to the<br>respective bits in the STATUS commands.|
|0x10|Reserved, must be 0.|
|0x08|Reserved, must be 0.|
|0x04|Reserved, must be 0.|
|0x02|Reserved, must be 0.|
|0x01|Reserved, must be 0.|
Enable writes to all commands when WRITE_PROTECT is set to 0x00.
If the WP pin is high, PAGE, OPERATION, MFR_CLEAR_PEAKS, MFR_EE_UNLOCK, WRITE_PROTECT, and CLEAR_ FAULTS commands are supported. Individual fault bits can be cleared by writing a 1 to the respective bits in the STATUS commands.
Rev. 0
82
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LTM4682
## **PMBus COMMAND DETAILS**
## _**MFR_ADDRESS**_
The MFR_ADDRESS command byte sets the 7 bits of the PMBus subordinate address for this device.
Setting this command to a value of 0x80 disables device addressing. The GLOBAL device address, 0x5A and 0x5B, cannot be deactivated. If RCONFIG is set to ignore, the ASEL nn_ pins are still used to determine the LSB of the channel address. If the ASEL_01 and ASEL_23 pins are both open, the LTM4682 will use the address value stored in NVM. If the ASEL nn_ pins are open, the LTM4682 will use the lower 4 bits of the MFR_ADDRESS value stored in NVM to construct the effective address of the part.
This command has one data byte.
## _**MFR_RAIL_ADDRESS**_
The MFR_RAIL_ADDRESS command enables direct device address access to the PAGE-activated channel. The value of this command should be common to all devices attached to a single power supply rail.
The user should only perform command writes to this address. If a read is performed from this address and the rail devices do not respond with EXACTLY the same value, the LTM4682 will detect bus contention and may set a CML communications fault.
Setting this command to a value of 0x80 disables rail device addressing for the channel.
This command has one data byte.
## **GENERAL CONFIGURATION COMMANDS**
|**COMMAND NAME**|**CMD CODE **|**DESCRIPTION**|**TYPE**|**PAGED**|**DATA**<br>**FORMAT**|**UNITS**|**NVM**|**DEFAULT**<br>**VALUE**|
|---|---|---|---|---|---|---|---|---|
|MFR_CHAN_CONFIG|0xD0|Configuration bits that are channel specific.|R/W Byte|Y|Reg||Y|0x1D|
|MFR_CONFIG_ALL|0xD1|General configuration bits.|R/W Byte|N|Reg||Y|0x21|
## _**MFR_CHAN_CONFIG**_
General purpose configuration command common to multiple Analog Devices’ products.
|**BIT**|**MEANING**|
|---|---|
|7|Reserved|
|6|Reserved|
|5|Reserved|
|4|Disable RUN Low. When asserted, the RUN pin is not pulsed low if commanded OFF.|
|3|Enable Short Cycle recognition if this bit is set to a 1.|
|2|SHARE_CLOCK control. If SHARE_CLOCK is held low, the output is disabled.|
|1|NoFAULT ALERT,ALERTis not pulled low ifFAULTis pulled low externally. Assert this bit if either POWER_GOOD or VOUT_UVUF are<br>propagated onFAULT.|
|0|Disables the VOUTdecay value requirement for MFR_RETRY_TIME and tOFF(MIN)processing. When this bit is set to a 0, the output must decay to<br>less than 12.5% of the programmed value for any action that turns off the rail, including a fault, an OFF/ON command, or a toggle of RUN from<br>high to low to high.|
This command has one data byte.
Rev. 0
83
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LTM4682
## **PMBus COMMAND DETAILS**
A ShortCycle event occurs whenever the PWM channel is commanded back ON, or reactivated, after the part has been commanded OFF and is processing either the TOFF_DELAY or the TOFF_FALL states. The PWM channel can be turned ON and OFF through either the RUN pin, and or the PMBus OPERATION command.
If the PWM channel is reactivated during the TOFF_DELAY, the part will perform the following:
1. Immediately tri-state the PWM channel output;
2. Start the retry delay timer as specified by the tOFF(MIN).
3. After the tOFF(MIN) value has expired, the PWM channel will proceed to the TON_DELAY state and the STATUS_ MFR_SPECIFIC bit #1 will assert.
If the PWM channel is reactivated during the TOFF_FALL, the part will perform the following:
1. Stop ramping down the PWM channel output;
2. Immediately tri-state the PWM channel output;
3. Start the retry delay timer as specified by the tOFF(MIN).
4. After the tOFF(MIN) value has expired, the PWM channel will proceed to the TON_DELAY state, and the STATUS_ MFR_SPEFIFIC bit #1 will assert.
If the ShortCycle event occurs and the ShortCycle MFR_CHAN_CONFIG bit is not set, the PWM channel state machine will complete its TOFF_DELAY and TOFF_FALL operations as previously commanded by the user.
## _**MFR_CONFIG_ALL**_
General purpose configuration command common to multiple Analog Devices’ products.
|**BIT**|**MEANING**|
|---|---|
|7|Enable fault logging.|
|6|Ignore resistor configuration pins.|
|5|Mask PMBus, Part II, Section 10.9.1 Violations.|
|4|Disable SYNC output.|
|3|Enable 255ms PMBus timeout.|
|2|A valid PEC is required for PMBus writes to be accepted. If this bit is not<br>set, the part will accept commands with invalid PEC.|
|1|Enable the use of PMBus clock stretching.|
|0|Execute CLEAR_FAULTS on the rising edge of either RUN pin.|
This command has one data byte.
## **ON/OFF/MARGIN**
|**COMMAND NAME**|**CMD**<br>**CODE**|**DESCRIPTION**|**TYPE**|**PAGED**|**DATA**<br>**FORMAT**|**UNITS**|**NVM**|**DEFAULT**<br>**VALUE**|
|---|---|---|---|---|---|---|---|---|
|ON_OFF_CONFIG|0x02|RUN pin and PMBus bus on/off command configuration.|R/W Byte|Y|Reg||Y|0x1E|
|OPERATION|0x01|Operating mode control. On/off, margin high, and<br>margin low.|R/W Byte|Y|Reg||Y|0x80|
|MFR_RESET|0xFD|Commanded reset without requiring a power-down.|Send Byte|N||||NA|
Rev. 0
84
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LTM4682
## **PMBus COMMAND DETAILS**
## _**ON_OFF_CONFIG**_
The ON_OFF_CONFIG command specifies the combination of the RUN _n_ pin input state and PMBus commands needed to turn the PWM channel on and off.
## Supported Values:
|Supported|Values:|
|---|---|
|**VALUE**|**MEANING**|
|0x1F|The OPERATION value and RUN_n_pin must both command the device to start/run. The device executes immediate off when commanded<br>off.|
|0x1E|The OPERATION value and RUN_n_pin must both command the device to start/run. The device uses TOFF_ command values when<br>commanded off.|
|0x17|RUN_n_pin control with immediate off when commanded off. OPERATION on/off control ignored.|
|0x16|RUN_n_pin control using TOFF_ command values when commanded off. OPERATION on/off control ignored.|
Programming an unsupported ON_OFF_CONFIG value will generate a CML fault, and the command will be ignored. This command has one data byte.
## _**OPERATION**_
The OPERATION command is used to turn the unit on and off in conjunction with the input from the RUN _n_ pins. It is also used to cause the unit to set the output voltage to the upper or lower MARGIN VOLTAGEs. The unit stays in the commanded operating mode until a subsequent OPERATION command or change in the state of the RUN _n_ pin instructs the device to change to another mode. If the part is stored in the MARGIN_LOW/HIGH state, the next RESET or POWER_ON cycle will ramp to that state. If the OPERATION command is modified, for example, ON is changed to MARGIN_LOW, the output will move at a fixed slope set by the VOUT_TRANSITION_RATE. The default operation command is Sequence Off. If the VIN is applied to a part with factory default programming and the VOUT_CONFIG resistor configuration pins are not installed, the outputs will be commanded off. The part defaults to the Sequence Off state. This command has one data byte.
Supported Values:
|Supported|Values:|
|---|---|
|**VALUE**|**MEANING**|
|0xA8|Margin high.|
|0x98|Margin low.|
|0x80|On(VOUTback to nominal even if bit 3 of ON_OFF_CONFIG is not set).|
|0x40*|Soft off(with sequencing).|
|0x00*|Immediate off(no sequencing).|
*Device does not respond to these commands if bit 3 of ON_OFF_CONFIG is not set.
Programming an unsupported OPERATION value will generate a CML fault, and the command will be ignored. This command has one data byte.
## _**MFR_RESET**_
This command provides a means to reset the LTM4682 from the serial bus. This forces the LTM4682 to turn off both PWM channels, load the operating memory from internal EEPROM, clear all faults and then perform a soft-start of both PWM channels if enabled.
This write-only command has no data bytes.
Rev. 0
85
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LTM4682
## **PMBus COMMAND DETAILS**
## **PWM CONFIGURATION**
|**COMMAND NAME**|**CMD CODE **|**DESCRIPTION**|**TYPE**|**PAGED**|**DATA**<br>**FORMAT**|**UNITS**|**NVM**|**DEFAULT**<br>**VALUE**|
|---|---|---|---|---|---|---|---|---|
|MFR_PWM_COMP|0xD3|PWM loop compensation configuration.|R/W Byte|Y|Reg||Y|0x76|
|MFR_PWM_MODE|0xD4|Configuration for the PWM engine.|R/W Byte|Y|Reg||Y|0xC7|
|MFR_PWM_CONFIG|0xF5|Set numerous parameters for the DC/DC controller,<br>including phasing.|R/W Byte|N|Reg||Y|0x10|
|FREQUENCY_SWITCH|0x33|Switching frequency of the controller.|R/W<br>Word|N|L11|kHz|Y|575<br>0x023F|
## _**MFR_PWM_MODE**_
The MFR_PWM_MODE command sets important PWM controls for each channel.
The MFR_PWM_MODE command allows the user to program the PWM controller to use discontinuous (pulse-skipping mode), or forced continuous conduction mode.
|<br>mode),|<br>or forced continuous conduction mode.|
|---|---|
|**BIT**|**MEANING**|
|7<br>0b<br>1b|Use a high range of ILIMIT.<br>Low current range.<br>High current range.|
|6|Enable servo mode|
|5|External temperature sense:<br>0: ∆VBEmeasurement.<br>Now reserved,∆VBEonlysupported.|
|4|Page 0 Only: Use of TSNS1a-Sensed Temperature Telemetry.<br>0 – Temperature sensed through TSNS1a is used to temperature-correct the current-sense information digitized by Channel 1’s current-sense<br>input, ISNS1a+/ISNS1a–.<br>1 – Temperature sensed through TSNS0a is used to temperature-correct the current-sense information digitized by Channel 1’s current-sense<br>input,ISNS1a+/ISNS1a–. Telemetryobtained from the thermal sensor connected to TSNS1a can be external to the module,if desired.|
|3|Reserved|
|2|Reserved|
|1<br>1b<br>0b|VOUTrange.<br>The maximum output voltage is 2.75V.<br>The maximum output voltage is 3.6V,which is not needed.|
|Bit[0]<br>0b<br>1b|Mode.<br>Discontinuous.<br>Forced continuous.|
Bit [7] of this command determines if the part is in a high range or low range of the IOUT_OC_FAULT_LIMIT command. Changing this bit value changes the PWM loop gain and compensation. This bit value should not be changed when the channel output is active. Writing this bit when the channel is active will generate a CML fault.
Bit [6] The LTM4682 will not servo while the part is OFF, ramping on or ramping off. When set to one, the output servo is enabled. The output set point DAC will be slowly adjusted to minimize the difference between the READ_VOUT_ADC and the VOUT_COMMAND (or the appropriate margined value).
The LTM4682 computes temperature in °C from ∆ VBE measured by the ADC at the TSNS _n_ pin as
T = (G • ∆VBE • q/(K • ln(16))) – 273.15 + O
Rev. 0
86
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LTM4682
## **PMBus COMMAND DETAILS**
For both equations,
G = MFR_TEMP_1_GAIN • 2[–14] , and
O = MFR_TEMP_1_OFFSET
Bit[1] of this command determines if the part is in a high range or low voltage range. Changing this bit value changes the PWM loop gain and compensation. This bit value should not be changed when the channel output is active. Writing this bit when the channel is active will generate a CML fault.
Bit[0] determines if the PWM mode of operation is discontinuous (pulse-skipping mode), or forced continuous conduction mode. Whenever the channel is ramping on, the PWM mode will be discontinuous, regardless of the value of this bit. This command has one data byte.
## _**MFR_PWM_COMP**_
The MFR_PWM_COMP command sets the gm of the PWM channel error amplifiers and the value of the internal RITHn compensation resistors. This command affects the loop gain of the PWM output, which may require modifications to the external compensation network.
|**BIT**|**MEANING**|
|---|---|
|**BIT [7:5]**|**Error Amplifier GM Adjust(mS)**|
|000b|1.00|
|001b|1.68|
|010b|2.35|
|011b|3.02|
|100b|3.69|
|101b|4.36|
|110b|5.04|
|111b|5.76|
|**BIT [4:0]**|**RCOMP (k**Ω**)**|
|00000b|0|
|00001b|0.25|
|00010b|0.5|
|00011b|0.75|
|00100b|1|
|00101b|1.25|
|00110b|1.5|
|00111b|1.75|
|01000b|2|
|01001b|2.5|
|01010b|3|
|01011b|3.5|
|01100b|4|
|01101b|4.5|
|01110b|5|
|01111b|5.5|
|10000b|6|
Rev. 0
87
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LTM4682
## **PMBus COMMAND DETAILS**
|**BIT**|**MEANING**|
|---|---|
|10001b|7|
|10010b|8|
|10011b|9|
|10100b|11|
|10101b|13|
|10110b|15|
|10111b|17|
|11000b|20|
|11001b|24|
|11010b|28|
|11011b|32|
|11100b|38|
|11101b|46|
|11110b|54|
|11111b|62|
This command has one data byte.
## _**MFR_PWM_CONFIG**_
The MFR_PWM_CONFIG command sets the switching frequency phase offset to the falling edge of the SYNC signal. The part must be in the OFF state to process this command. Either the RUN pins must be low, or the channels must be commanded off. If either channel is in the RUN state and this command is written, the command will be NACK’d, and a BUSY fault will be asserted.
|**BIT**|**MEANING**|**MEANING**|
|---|---|---|
|7|Reserved||
|[6:5]<br>00b<br>01b<br>10b<br>11b|Input current sense gain.<br>2x gain. 0mV to 50mV range.<br>4x gain. 0mV to 25mV range.<br>8x gain. 0mV to 10mV range.<br>Reserved||
|4|Share Clock Enable: If this bit is 1, the<br>SHARE_CLK pin will not be released until<br>VIN> VIN_ON. The SHARE_CLK pin will be<br>pulled low when VIN< VIN_OFF. If this bit is 0, the SHARE_<br>CLK pin will not be pulled low when VIN < VIN_OFF except<br>for the initial application of VIN.||
|3|Reserved||
|**BIT [2:0]**|**CHANNEL 0 (DEGREES)**|**CHANNEL 1 (DEGREES)**|
|000b|0|180|
|001b|90|270|
|010b|0|240|
|011b|0|120|
|100b|120|240|
|101b|60|240|
|110b|120|300|
Rev. 0
88
For more information www.analog.com
LTM4682
## **PMBus COMMAND DETAILS**
## _**FREQUENCY_SWITCH**_
The FREQUENCY_SWITCH command sets the switching frequency, in kHz, of the LTM4682.
## Supported Frequencies:
|**VALUE [15:0]**|**RESULTING FREQUENCY(TYP)**|
|---|---|
|0x0000|External oscillator|
|0xF3E8|250kHz|
|0xFABC|350kHz|
|0xFB52|425kHz|
|0xFBE8|500kHz|
|0x023F|575kHz|
|0x028A|650kHz|
|0x02EE|750kHz|
|0x03E8|1000kHz|
The part must be in the OFF state to process this command. The RUN pin must be low, or both channels must be commanded off. If the part is in a RUN state and this command is written, the command will be NACK'd, and a BUSY fault will be asserted. When the part is commanded off, and the frequency is changed, a PLL_UNLOCK status may be detected as the PLL locks onto the new frequency.
This command has two data bytes and is formatted in Linear_5s_11s format.
## **VOLTAGE**
## **Input Voltage and Limits**
|**COMMAND NAME**|**CMD CODE **|**DESCRIPTION**|**TYPE**|**PAGED**|**DATA**<br>**FORMAT**|**UNITS**|**NVM**|**DEFAULT**<br>**VALUE**|
|---|---|---|---|---|---|---|---|---|
|VIN_OV_FAULT_LIMIT|0x55|Input supply overvoltage fault limit.|R/W<br>Word|N|L11|V|Y|16.8<br>0xDA1A|
|VIN_UV_WARN_LIMIT|0x58|Input supply undervoltage warning limit.|R/W<br>Word|N|L11|V|Y|4.65<br>0xD12A|
|VIN_ON|0x35|Input voltage at which the unit should start<br>power conversion.|R/W<br>Word|N|L11|V|Y|4.75<br>0xD130|
|VIN_OFF|0x36|Input voltage at which the unit should stop<br>power conversion.|R/W<br>Word|N|L11|V|Y|4.5<br>0xD120|
|MFR_ICHIP_CAL_GAIN|0xF7|The resistance value of the VINpin filter<br>element in mΩ.|R/W<br>Word|N|L11|mΩ|Y|1000<br>0x03E8|
## _**VIN_OV_FAULT_LIMIT**_
The VIN_OV_FAULT_LIMIT command sets the value of the input voltage measured by the ADC, in volts, that causes an input overvoltage fault.
This command has two data bytes in Linear_5s_11s format.
Rev. 0
89
For more information www.analog.com
LTM4682
## **PMBus COMMAND DETAILS**
## _**VIN_UV_WARN_LIMIT**_
- The VIN_UV_WARN_LIMIT command sets the value of input voltage measured by the ADC that causes an input under voltage warning. This warning is disabled until the input exceeds the input startup threshold value set by the VIN_ON command and the unit has been enabled. If the VIN Voltage drops below the VIN_UV_WARN_LIMIT, the device:
- Sets the INPUT bit in the STATUS_WORD
- Sets the VIN undervoltage warning bit in the STATUS_INPUT command
- Notifies the host by asserting ALERT, unless masked
## _**VIN_ON**_
The VIN_ON command sets the input voltage, in Volts, at which the unit starts power conversion.
This command has two data bytes and is formatted in Linear_5s_11s format.
## _**VIN_OFF**_
The VIN_OFF command sets the input voltage, in Volts, at which the unit stops power conversion.
This command has two data bytes and is formatted in Linear_5s_11s format.
## _**MFR_ICHIP_CAL_GAIN**_
The MFR_ICHIP_CAL_GAIN command is used to set the resistance value of the VIN pin filter element in milliohms. (See also READ_VIN). Set MFR_RVIN equal to 0 if no filter element is used.
This command has two data bytes and is formatted in Linear_5s_11s format.
## **Output Voltage and Limits**
|**COMMAND NAME**|**CMD CODE**|**DESCRIPTION**|**TYPE**|**PAGED**|**DATA**<br>**FORMAT**|**UNITS**|**NVM**|**DEFAULT**<br>**VALUE**|
|---|---|---|---|---|---|---|---|---|
|VOUT_MODE|0x20|The output voltage format and<br>exponent(2–12).|R Byte|Y|Reg|||2–12<br>0x14|
|VOUT_MAX|0x24|The upper limit on the output<br>voltage the unit can command<br>regardless of anyother commands.|R/W<br>Word|Y|L16|V|Y|1.5V<br>0x1800|
|VOUT_OV_FAULT_LIMIT|0x40|Output overvoltage fault limit.|R/W<br>Word|Y|L16|V|Y|0.85<br>0x0D9A|
|VOUT_OV_WARN_LIMIT|0x42|Output overvoltage warning limit.|R/W<br>Word|Y|L16|V|Y|0.825<br>0x0D33|
|VOUT_MARGIN_HIGH|0x25|Margin high output voltage set<br>point. It must be greater than<br>VOUT_COMMAND.|R/W<br>Word|Y|L16|V|Y|0.80<br>0x0CCD|
|VOUT_COMMAND|0x21|Nominal output voltage set point.|R/W<br>Word|Y|L16|V|Y|0.75<br>0x0C00|
|VOUT_MARGIN_LOW|0x26|Margin low output voltage<br>set point. It must be less than<br>VOUT_COMMAND.|R/W<br>Word|Y|L16|V|Y|0.70<br>0x0B33|
|VOUT_UV_WARN_LIMIT|0x43|Output undervoltage warning limit.|R/W<br>Word|Y|L16|V|Y|0.675<br>0x0ACD|
|VOUT_UV_FAULT_LIMIT|0x44|Output undervoltage fault limit.|R/W<br>Word|Y|L16|V|Y|0.65<br>0x0A66|
|MFR_VOUT_MAX|0xA5|Maximum allowed output voltage.|R Word|Y|L16|V||1.5<br>0x1800|
|Rev. 0|||||||||
90
For more information www.analog.com
LTM4682
## **PMBus COMMAND DETAILS**
## _**VOUT_MODE**_
The data byte for the VOUT_MODE command, used for commanding and reading output voltage, consists of a 3-bit mode (only linear format is supported) and a 5-bit parameter representing the exponent used in output voltage Read/ Write commands.
This read-only command has one data byte.
## _**VOUT_MAX**_
The VOUT_MAX command sets an upper limit on any voltage, including VOUT_MARGIN_HIGH. The unit can command regardless of any other commands or combinations. The maximum allowed value of this command is 1.5V. The maximum output voltage the LTM4682 can produce is 1.35V, including VOUT_MARGIN_HIGH. However, the VOUT_OV_FAULT_LIMIT can be commanded as high as 1.5V.
This command has two data bytes and is formatted in Linear_16u format.
## _**VOUT_OV_FAULT_LIMIT**_
The VOUT_OV_FAULT_LIMIT command sets the value of the output voltage measured by the OV supervisor comparator at the sense pins, in volts, which causes an output overvoltage fault.
If the VOUT_OV_FAULT_LIMIT is modified and the part is in the RUN state, allow 10ms after the command is modified to ensure the new value is being honored. The part indicates if it is busy making a calculation. Monitor bits 5 and 6 of MFR_COMMON. Either bit is low if the part is busy. If this wait time is not honored and the VOUT_COMMAND is modified above the old overvoltage limit, an OV condition might temporarily be detected, resulting in undesirable behavior and possible damage to the switcher.
If the VOUT_OV_FAULT_RESPONSE is set to OV_PULLDOWN or 0x00, the FAULT pin will not assert if the VOUT_OV_ FAULT is propagated. The LTM4682 will pull the TG low and assert the BG bit when the overvoltage condition is detected.
This command has two data bytes and is formatted in Linear_16u format.
## _**VOUT_OV_WARN_LIMIT**_
The VOUT_OV_WARN_LIMIT command sets the value of the output voltage measured by the ADC at the sense pins, in volts, which causes an output voltage high warning. The MFR_VOUT_PEAK value can be used to determine if this limit has been exceeded.
In response to the VOUT_OV_WARN_LIMIT being exceeded, the device:
- Sets the NONE_OF_THE_ABOVE bit in the STATUS_BYTE
- Sets the VOUT bit in the STATUS_WORD
- Sets the VOUT overvoltage warning bit in the STATUS_VOUT command
- Notifies the host by asserting ALERT pin, unless masked
This condition is detected by the ADC, so that the response time may be up to tCONVERT.
Rev. 0
91
For more information www.analog.com
LTM4682
## **PMBus COMMAND DETAILS**
This command has two data bytes and is formatted in Linear_16u format.
## _**VOUT_MARGIN_HIGH**_
The VOUT_MARGIN_HIGH command loads the unit with the voltage to which the output is to be changed, in Volts, when the OPERATION command is set to Margin High. The value should be greater than VOUT_COMMAND. The maximum guaranteed value on VOUT_MARGIN_HIGH is 1.5V.
This command will not be acted on during TON_RISE and TOFF_FALL output sequencing. The VOUT_TRANSITION_ RATE will be used if this command is modified while the output is active and in a steady-state condition.
This command has two data bytes and is formatted in Linear_16u format.
## _**VOUT_COMMAND**_
The VOUT_COMMAND consists of two bytes and is used to set the output voltage, in volts. The maximum guaranteed value on VOUT is 1.5V.
This command will not be acted on during TON_RISE and TOFF_FALL output sequencing. The VOUT_TRANSITION_ RATE will be used if this command is modified while the output is active and in a steady-state condition.
This command has two data bytes and is formatted in Linear_16u format.
## _**VOUT_MARGIN_LOW**_
The VOUT_MARGIN_LOW command loads the unit with the voltage to which the output is to be changed, in volts, when the OPERATION command is set to Margin Low. The value must be less than VOUT_COMMAND.
This command will not be acted on during TON_RISE and TOFF_FALL output sequencing. The VOUT_TRANSITION_ RATE will be used if this command is modified while the output is active and in a steady-state condition.
This command has two data bytes and is formatted in Linear_16u format.
## _**VOUT_UV_WARN_LIMIT**_
The VOUT_UV_WARN_LIMIT command reads the value of the output voltage measured by the ADC at the sense pins, in volts, which causes an output voltage low warning.
In response to the VOUT_UV_WARN_LIMIT being exceeded, the device:
- Sets the NONE_OF_THE_ABOVE bit in the STATUS_BYTE
- Sets the VOUT bit in the STATUS_WORD
- Sets the VOUT undervoltage warning bit in the STATUS_VOUT command
- Notifies the host by asserting ALERT pin, unless masked
This command has two data bytes and is formatted in Linear_16u format.
## _**VOUT_UV_FAULT_LIMIT**_
The VOUT_UV_FAULT_LIMIT command reads the value of the output voltage measured by the UV supervisor comparator at the sense pins, in volts, which causes an output undervoltage fault.
This command has two data bytes and is formatted in Linear_16u format.
Rev. 0
92
For more information www.analog.com
LTM4682
## **PMBus COMMAND DETAILS**
## _**MFR_VOUT_MAX**_
The MFR_VOUT_MAX command is the maximum output voltage in volts for each channel, including VOUT_OV_FAULT_ LIMIT. If the output voltages are set to a high range (Bit 1 of MFR_PWM_MODE set to 0) MFR_VOUT_MAX is 3.6V. The (Bit 6 of MFR_PWM_CONFIG set to a 0), MFR_VOUT_MAX is 3.6V is not used since the outputs are limited to 1.5V. If the output voltage is set to a low range (Bit 1 of MFR_PWM_MODE set to a 1), the MFR_VOUT_MAX is 2.75V. Entering a VOUT_COMMAND value greater than this will result in a CML fault, and the output voltage setting will be clamped to the maximum level. This will also result in Bit 3 VOUT_MAX_Warning in the STATUS_VOUT command being set.
This read only command has 2 data bytes and is formatted in Linear_16u format.
## **OUTPUT CURRENT AND LIMITS**
|**COMMAND NAME**|**CMD CODE**|**DESCRIPTION**|**TYPE**|**PAGED**|**DATA**<br>**FORMAT**|**UNITS**|**NVM**|**DEFAULT**<br>**VALUE**|
|---|---|---|---|---|---|---|---|---|
|MFR_IOUT_CAL_GAIN|0xDA|The ratio of the voltage at the current<br>sense pins to the sensed current. For<br>devices using a fixed current sense<br>resistor, it is the resistance value<br>in mΩ.|R Word|Y|L11|mΩ|Factory<br>Only<br>NVM|0.360<br>0xD017|
|MFR_IOUT_CAL_GAIN_TC|0xF6|Temperature coefficient of the current<br>sensing element.|R/W Word|Y|CF||Y|3900<br>0x0F3C|
|IOUT_OC_FAULT_LIMIT|0x46|Output overcurrent fault limit.|R/W Word|Y|L11|A|Y|42.0<br>0xE940|
|IOUT_OC_WARN_LIMIT|0x4A|Output overcurrent warning limit.|R/W Word|Y|L11|A|Y|35.0<br>0xE918|
## _**MFR_IOUT_CAL_GAIN**_
The MFR_IOUT_CAL_GAIN command sets the resistance value of the current sense resistor in milliohms. (see also MFR_IOUT_CAL_GAIN_TC).
This command has two data bytes and is formatted in Linear_5s_11s format.
## _**MFR_IOUT_CAL_GAIN_TC**_
The MFR_IOUT_CAL_GAIN_TC command is used to program the temperature coefficient of the IOUT_CAL_GAIN sense resistor or inductor DCR in ppm/°C in manufacturing.
This command has two data bytes and is formatted in 16-bit 2’s complement integer ppm. N = –32768 to 32767 • 10[–6] . The nominal temperature is 27°C. The IOUT_CAL_GAIN is multiplied by:
[1.0 + MFR_IOUT_CAL_GAIN_TC • (READ_TEMPERATURE_1-27)].
DCR sensing will have a typical value of 3900.
The IOUT_CAL_GAIN and MFR_IOUT_CAL_GAIN_TC impact all current parameters, including: READ_IOUT, MFR_IOUT_PEAK, IOUT_OC_FAULT_LIMIT, and IOUT_OC_WARN_LIMIT.
Rev. 0
93
For more information www.analog.com
LTM4682
## **PMBus COMMAND DETAILS**
## _**IOUT_OC_FAULT_LIMIT**_
The IOUT_OC_FAULT_LIMIT command sets the value of the peak output current limit, in Amperes. When the controller is in the current limit, the overcurrent detector will indicate an overcurrent fault condition. The following table lists the programmable peak output current limit value in mV between ISENSE[+] and ISENSE[–] . The actual value of the current limit is (ISENSE[+ ] – ISENSE[–] )/IOUT_CAL_GAIN in Amperes.
**BASED ON PEAK-TO-PEAK INDUCTOR CURRENT = 50% OF 30A FOR WORSE CASE, THESE ARE APPROXIMATES, SO USE GUARDBAND AND CHECK**
|**MFR_PWM_MODE[7] = 1**<br>**HIGH CURRENT RANGE (mV)**|**~IL PEAK (A)**|**~IOUT (A)**|**MFR_PWM_MODE[7] = 0**<br>**LOW CURRENT RANGE (mV)**|**~ IL PEAK (A)**|**~ IOUT (A)**|
|---|---|---|---|---|---|
|17.73|49.25|41.75|9.85|27.36|19.86|
|18.86|52.38|44.88|10.48|29.11|21.61|
|20.42|NA|NA|11.34|31.5|24|
|21.14|NA|NA|11.74|32.61|25.11|
|22.27|NA|NA|12.37|34.36|26.86|
|23.41|NA|NA|13.01|36.13|28.63|
|24.55|NA|NA|13.64|37.88|30.38|
Note: This is the peak of the current waveform. The READ_IOUT command returns the average current. The peak output current limits are adjusted with temperature based on the MFR_IOUT_CAL_GAIN_TC using the equation:
Peak Current Limit = IOUT_CAL_GAIN • (1 + MFR_IOUT_CAL_GAIN_TC • (READ_TEMPERTURE_1-27.0)).
The LTM4682 automatically converts currents to the appropriate internal bit value.
The IOUT range is set with bit 7 of the MFR_PWM_MODE command.
The IOUT_OC_FAULT_LIMIT is ignored during TON_RISE and TOFF_FALL.
If the IOUT_OC_FAULT_LIMIT is exceeded, the device:
- Sets the IOUT bit in the STATUS word
- Sets the IOUT Overcurrent fault bit in the STATUS_IOUT
- Notifies the host by asserting ALERT, unless masked
This command has two data bytes and is formatted in Linear_5s_11s format.
Rev. 0
94
For more information www.analog.com
LTM4682
## **PMBus COMMAND DETAILS**
## _**IOUT_OC_WARN_LIMIT**_
This command sets the value of the output current measured by the ADC that causes an output overcurrent warning in Amperes. The READ_IOUT value will be used to determine if this limit has been exceeded.
In response to the IOUT_OC_WARN_LIMIT being exceeded, the device:
- Sets the NONE_OF_THE_ABOVE bit in the STATUS_BYTE
- Sets the IOUT bit in the STATUS_WORD
- Sets the IOUT Overcurrent Warning bit in the STATUS_IOUT command, and
- Notifies the host by asserting ALERT pin, unless masked
The IOUT_OC_FAULT_LIMIT is ignored during TON_RISE and TOFF_FALL.
This command has two data bytes and is formatted in Linear_5s_11s format.
## **Input Current and Limits**
|**COMMAND NAME**|**CMD**<br>**CODE**|**DESCRIPTION**|**TYPE**|**DATA**<br>**FORMAT**|**UNITS**|**NVM**|**DEFAULT**<br>**VALUE**|
|---|---|---|---|---|---|---|---|
|MFR_IIN_CAL_GAIN|0xE8|The resistance value of the input current sense<br>element in mΩ.|R/W Word|L11|mΩ|Y|1.000<br>0x03E8|
## _**MFR_IIN_CAL_GAIN**_
The MFR_IIN_CAL_GAIN command sets the resistance value of the input current sense resistor in milliohms. (see also READ_IIN).
This command has two data bytes and is formatted in Linear_5s_11s format.
|**COMMAND NAME**|**CMD CODE **|**DESCRIPTION**|**TYPE**|**PAGED**|**DATA**<br>**FORMAT**|**UNITS**|**NVM**|**DEFAULT**<br>**VALUE**|
|---|---|---|---|---|---|---|---|---|
|IIN_OC_WARN_LIMIT|0x5D|Input overcurrent warning<br>limit.|R/W Word|N|L11|A|Y|10.0<br>0xD280|
## _**IIN_OC_WARN_LIMIT**_
The IIN_OC_WARN_LIMIT command sets the value of the input current measured by the ADC, in amperes, which causes a warning indicating the input current is high. The READ_IIN value will be used to determine if this limit has been exceeded.
In response to the IIN_OC_WARN_LIMIT being exceeded, the device:
- Sets the OTHER bit in the STATUS_BYTE
- Sets the INPUT bit in the upper byte of the STATUS_WORD
- Sets the IIN Overcurrent Warning bit[1] in the STATUS_INPUT command
- Notifies the host by asserting the ALERT pin
This command has two data bytes and is formatted in Linear_5s_11s format.
Rev. 0
95
For more information www.analog.com
LTM4682
## **PMBus COMMAND DETAILS**
## **TEMPERATURE**
## **Power Stage DCR Temperature Calibration**
|**COMMAND NAME**|**CMD CODE **|**DESCRIPTION**|**TYPE**|**PAGED**|**DATA**<br>**FORMAT **|**UNITS**|**NVM**|**DEFAULT**<br>**VALUE**|
|---|---|---|---|---|---|---|---|---|
|MFR_TEMP_1_GAIN|0xF8|Sets the slope of the external<br>temperature sensor.|R/W Word|Y|CF||Y|0.995<br>0x3FAE|
|MFR_TEMP_1_OFFSET|0xF9|Sets the offset of the external<br>temperature sensor.|R/W Word|Y|L11|C|Y|0.0<br>0x8000|
## _**MFR_TEMP_1_GAIN**_
The MFR_TEMP_1_GAIN command will modify the slope of the power stage sensor to account for non-idealities in the element and errors associated with the remote sensing of the temperature in the inductor.
This command has two data bytes and is formatted in 16-bit 2’s complement integer. The effective gain adjustment is N • 2[–14] . The nominal value is 1. N = 8192 to 32767
## _**MFR_TEMP_1_OFFSET**_
The MFR_TEMP_1_OFFSET command will modify the offset of the power stage temperature sensor to account for non-idealities in the element and errors associated with the remote sensing of the temperature in the inductor.
This command has two data bytes and is formatted in Linear_5s_11s format. The part starts the calibration with a –273.15, so the default adjustment is zero.
## **Power Stage Temperature Limits**
|**COMMAND NAME**|**CMD CODE **|**DESCRIPTION**|**TYPE**|**PAGED**|**DATA**<br>**FORMAT**|**UNITS**|**NVM**|**DEFAULT**<br>**VALUE**|
|---|---|---|---|---|---|---|---|---|
|OT_FAULT_LIMIT|0x4F|Power stage overtemperature<br>fault limit.|R/W Word|Y|L11|C|Y|128.0<br>0xF200|
|OT_WARN_LIMIT|0x51|Power stage overtemperature<br>warning limit.|R/W Word|Y|L11|C|Y|125.0<br>0xEBE8|
|UT_FAULT_LIMIT|0x53|Power stage undertemperature<br>fault limit.|R/W Word|Y|L11|C|Y|–45.0<br>0xE530|
## _**OT_FAULT_LIMIT**_
The OT_FAULT_LIMIT command sets the value of the power stage temperature measured by the ADC, in degrees Celsius, which causes an overtemperature fault. The READ_TEMPERATURE_1 value will be used to determine if this limit has been exceeded.
This command has two data bytes and is formatted in Linear_5s_11s format.
## _**OT_WARN_LIMIT**_
The OT_WARN_LIMIT command sets the value of the power stage temperature measured by the ADC, in degrees Celsius, which causes an overtemperature warning. The READ_TEMPERATURE_1 value will be used to determine if this limit has been exceeded.
Rev. 0
96
For more information www.analog.com
LTM4682
## **PMBus COMMAND DETAILS**
In response to the OT_WARN_LIMIT being exceeded, the device:
- Sets the TEMPERATURE bit in the STATUS_BYTE
- Sets the Overtemperature Warning bit in the STATUS_TEMPERATURE command, and
- Notifies the host by asserting ALERT pin, unless masked
This command has two data bytes and is formatted in Linear_5s_11s format.
## _**UT_FAULT_LIMIT**_
The UT_FAULT_LIMIT command sets the value of the power stage temperature measured by the ADC, in degrees Celsius, which causes an undertemperature fault. The READ_TEMPERATURE_1 value will be used to determine if this limit has been exceeded.
Note: If the temperature sensors are not installed, the UT_FAULT_LIMIT can be set to –275°C and the UT_FAULT_LIMIT response set to ignore to avoid ALERT being asserted.
This command has two data bytes and is formatted in Linear_5s_11s format.
## **TIMING**
**Timing—On Sequence/Ramp**
|**COMMAND NAME**|**CMD CODE **|**DESCRIPTION**|**TYPE**|**PAGED**|**DATA**<br>**FORMAT**|**UNITS**|**NVM**|**DEFAULT**<br>**VALUE**|
|---|---|---|---|---|---|---|---|---|
|TON_DELAY|0x60|Time from RUN and/or Operation on to<br>output rail turn-on.|R/W Word|Y|L11|ms|Y|0.0<br>0x8000|
|TON_RISE|0x61|Time from when the output rises until<br>the output voltage reaches the VOUT<br>commanded value.|R/W Word|Y|L11|ms|Y|3.0<br>0xC300|
|TON_MAX_FAULT_LIMIT|0x62|Maximum time from the start of<br>TON_RISE for VOUT to cross the<br>VOUT_UV_FAULT_LIMIT.|R/W Word|Y|L11|ms|Y|5.0<br>0xCA80|
|VOUT_TRANSITION_RATE|0x27|Rate the output changes when VOUTis<br>commanded to a new value.|R/W Word|Y|L11|V/ms|Y|0.25<br>0xD010|
## _**TON_DELAY**_
The TON_DELAY command sets the time, in milliseconds, from when a start condition is received until the output voltage rises. Values from 0ms to 83 seconds are valid. The resulting turn-on delay will have a typical delay of 270µs for TON_DELAY = 0 and an uncertainty of ±50µs for all values of TON_DELAY.
This command has two data bytes and is formatted in Linear_5s_11s format.
## _**TON_RISE**_
The TON_RISE command sets the time, in milliseconds, from the time the output starts to rise to the time the output enters the regulation band. Values from 0 to 1.3 seconds are valid. The part will be in discontinuous mode during TON_RISE events. If TON_RISE is less than 0.25ms, the LTM4682 digital slope will be bypassed, and the output voltage transition will only be controlled by the analog performance of the PWM switcher. The number of steps in TON_RISE is equal to TON_RISE (in ms)/0.1ms with an uncertainty of ±0.1ms.
This command has two data bytes and is formatted in Linear_5s_11s format.
Rev. 0
97
For more information www.analog.com
LTM4682
## **PMBus COMMAND DETAILS**
## _**TON_MAX_FAULT_LIMIT**_
The TON_MAX_FAULT_LIMIT command sets the value, in milliseconds, on how long the unit can attempt to power up the output without reaching the output undervoltage fault limit.
A data value of 0ms means there is no limit, and the unit can attempt to bring up the output voltage indefinitely. The maximum limit is 83 seconds.
This command has two data bytes and is formatted in Linear_5s_11s format.
## _**VOUT_TRANSITION_RATE**_
When a PMBus device receives either a VOUT_COMMAND or OPERATION (Margin High, Margin Low) that causes the output voltage to change, this command sets the rate in V/ms at which the output voltage changes. The commanded rate of change does not apply when the unit is commanded on or off. The maximum allowed slope is 4V/ms.
This command has two data bytes and is formatted in Linear_5s_11s format.
## **Timing—Off Sequence/Ramp**
|**COMMAND NAME**|**CMD**<br>**CODE **|**DESCRIPTION**|**TYPE**|**PAGED**|**DATA**<br>**FORMAT**|**UNITS**|**NVM**|**DEFAULT**<br>**VALUE**|
|---|---|---|---|---|---|---|---|---|
|TOFF_DELAY|0x64|Time from RUN and/or Operation off to the<br>start of TOFF_FALL ramp.|R/W Word|Y|L11|ms|Y|0.0<br>0x8000|
|TOFF_FALL|0x65|Time from when the output starts to fall until<br>the output reaches zero volts.|R/W Word|Y|L11|ms|Y|3.0<br>0xC300|
|TOFF_MAX_WARN_LIMIT|0x66|Maximum allowed time, after TOFF_FALL is<br>completed,for the unit to decaybelow 12.5%.|R/W Word|Y|L11|ms|Y|0<br>0x8000|
## _**TOFF_DELAY**_
The TOFF_DELAY command sets the time, in milliseconds, from when a stop condition is received until the output voltage starts to fall. Values from 0 to 83 seconds are valid. The resulting turn-off delay will have a typical delay of 270µs for TOFF_DELAY = 0 and an uncertainty of ±50µs for all values of TOFF_DELAY. TOFF_DELAY is not applied when a fault event occurs
This command has two data bytes and is formatted in Linear_5s_11s format.
## _**TOFF_FALL**_
The TOFF_FALL command sets the time, in milliseconds, from the end of the turn-off delay time until the output voltage is commanded to zero. It is the ramp time of the VOUT DAC. When the VOUT DAC is zero, the PWM output will be set to a high impedance state.
The part will maintain the mode of operation programmed. For defined TOFF_FALL times, the user should set the part to continuous conduction mode. Loading the max value indicates that the part will ramp down at the slowest possible rate. The minimum supported fall time is 0.25ms. A value less than 0.25ms will result in a 0.25ms ramp. The maximum fall time is 1.3 seconds. The number of steps in TOFF_FALL is equal to TOFF_FALL (in ms)/0.1ms with an uncertainty of ±0.1ms.
In discontinuous conduction mode, the controller will not draw current from the load, and the fall time will be set by the output capacitance and load current.
This command has two data bytes and is formatted in Linear_5s_11s format.
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LTM4682
## **PMBus COMMAND DETAILS**
## _**TOFF_MAX_WARN_LIMIT**_
The TOFF_MAX_WARN_LIMIT command sets the value, in milliseconds, on how long the output voltage exceeds 12.5% of the programmed voltage before a warning is asserted. The output is considered off when the VOUT voltage is less than 12.5% of the programmed VOUT_COMMAND value. The calculation begins after TOFF_FALL is complete.
A data value of 0ms means there is no limit, and the output voltage exceeds 12.5% of the programmed voltage indefinitely. Other than 0, values from 120ms to 524 seconds are valid.
This command has two data bytes and is formatted in Linear_5s_11s format.
## **Precondition for Restart**
|**COMMAND NAME**|**CMD CODE **|**DESCRIPTION**|**TYPE**|**PAGED**|**DATA**<br>**FORMAT**|**UNITS**|**NVM**|**DEFAULT**<br>**VALUE**|
|---|---|---|---|---|---|---|---|---|
|MFR_RESTART_DELAY|0xDC|Minimum time the RUN pin is held<br>low by the LTM4682.|R/W Word|Y|L11|ms|Y|150<br>0xF258|
## _**MFR_RESTART_DELAY**_
This command specifies the minimum RUN off time in milliseconds. This device will pull the RUN pin low for this length of time once a falling edge of RUN has been detected. The minimum recommended value is 136ms.
Note: The restart delay is different from the retry delay. The restart delay pulls RUN low for the specified time, after which a standard start-up sequence is initiated. The minimum restart delay should be equal to TOFF_DELAY + TOFF_ FALL + 136ms. Valid values are from 136ms to 65.52 seconds in 16ms increments. To ensure a minimum off time, set the MFR_RESTART_DELAY 16ms longer than the desired time. The output rail can be off longer than the MFR_ RESTART_DELAY after the RUN pin is pulled high if the output decay bit 0 is enabled in MFR_CHAN_CONFIG and the output takes a long time to decay below 12.5% of the programmed value.
This command has two data bytes and is formatted in Linear_5s_11s format.
## **FAULT RESPONSE**
## **Fault Responses All Faults**
|**COMMAND NAME**|**CMD CODE**|**DESCRIPTION**|**TYPE**|**PAGED**|**DATA**<br>**FORMAT**|**UNITS**|**NVM**|**DEFAULT**<br>**VALUE**|
|---|---|---|---|---|---|---|---|---|
|MFR_RETRY_DELAY|0xDB|Retry interval during FAULT<br>retry mode.|R/W Word|Y|L11|ms|Y|250<br>0xF3E8|
## _**MFR_RETRY_DELAY**_
This command sets the time in milliseconds between retries if the fault response is to retry the controller at specified intervals. This command value is used for all fault responses that require retry. The retry time starts once the fault has been detected by the offending channel. Valid values are from 120ms to 83.88 seconds in 10µs increments.
Note: The retry delay time is determined by the length of the MFR_RETRY_DELAY command or the time required for the regulated output to decay below 12.5% of the programmed value. If the natural decay time of the output is too long, it is possible to remove the voltage requirement of the MFR_RETRY_DELAY command by asserting bit 0 of MFR_CHAN_CONFIG.
This command has two data bytes and is formatted in Linear_5s_11s format.
Rev. 0
99
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## LTM4682
## **PMBus COMMAND DETAILS**
## **Fault Responses Input Voltage**
|**COMMAND NAME**|**CMD CODE**|**DESCRIPTION**|**TYPE**|**PAGED**|**DATA**<br>**FORMAT**|**UNITS**|**NVM**|**DEFAULT**<br>**VALUE**|
|---|---|---|---|---|---|---|---|---|
|VIN_OV_FAULT_RESPONSE|0x56|Action is to be taken by the device<br>when an input supply overvoltage fault<br>is detected.|R/W Byte|Y|Reg||Y|0x80|
## _**VIN_OV_FAULT_RESPONSE**_
The VIN_OV_FAULT_RESPONSE command instructs the device on what action is to be taken in response to an input overvoltage fault. The data byte is in the format given in Table 21.
The device also:
- Sets the NONE_OF_THE_ABOVE bit in the STATUS_BYTE
- Set the INPUT bit in the upper byte of the STATUS_WORD
- Sets the VIN overvoltage fault bit in the STATUS_INPUT command
- Notifies the host by asserting ALERT pin, unless masked
This command has one data byte.
## **Fault Responses Output Voltage**
|**COMMAND NAME**|**CMD**<br>**CODE**|**DESCRIPTION**|**TYPE**|**PAGED**|**DATA**<br>**FORMAT**|**UNITS**|**NVM**|**DEFAULT**<br>**VALUE**|
|---|---|---|---|---|---|---|---|---|
|VOUT_OV_FAULT_RESPONSE|0x41|Action is to be taken by the device when<br>an output overvoltage fault is detected.|R/W Byte|Y|Reg||Y|0xB8|
|VOUT_UV_FAULT_RESPONSE|0x45|Action is to be taken by the device when<br>an output undervoltage fault is detected.|R/W Byte|Y|Reg||Y|0xB8|
|TON_MAX_FAULT_RESPONSE|0x63|Action is to be taken by the device when a<br>TON_MAX_FAULT event is detected.|R/W Byte|Y|Reg||Y|0xB8|
## _**VOUT_OV_FAULT_RESPONSE**_
The VOUT_OV_FAULT_RESPONSE command instructs the device on what action is to be taken in response to an output overvoltage fault. The data byte is in the format as shown in Table 17.
The device also:
- Sets the VOUT_OV bit in the STATUS_BYTE
- Sets the VOUT bit in the STATUS_WORD
- Sets the VOUT overvoltage fault bit in the STATUS_VOUT command
- Notifies the host by asserting ALERT pin, unless masked
The only values recognized for this command are:
- 0x00 Part performs OV pull down only, or OV_PULLDOWN.
- 0x80 The device shuts down (disables the output), and the unit does not attempt to retry. (PMBus, Part II, Section 10.7).
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LTM4682
## **PMBus COMMAND DETAILS**
- 0xB8 The device shuts down (disables the output), and the device attempts to retry continuously, without limitation, until it is commanded OFF (by the RUN pin, or OPERATION command, or both), bias power is removed, or another fault condition causes the unit to shut down.
- 0x4 _n_ The device shuts down, and the unit does not attempt to retry. The output remains disabled until the part is commanded OFF, then ON, or the RUN pin is asserted low, then high or RESET through the command or removal of VIN. The OV fault must remain active for a period of n • 10µs, where n is a value from 0 to 7.
- 0x78 _n_ The device shuts down, and the unit attempts to retry continuously until either the fault condition is cleared or the part is commanded OFF, then ON, or the RUN pin is asserted low, then high or RESET through the command or removal of VIN. The OV fault must remain active for a period of n • 10µs, where n is a value from 0 to 7.
Any other value will result in a CML fault, and the write will be ignored.
This command has one data byte.
## **Table 17. VOUT_OV_FAULT_RESPONSE Data Byte Contents**
|**BITS**|**DESCRIPTION**|**VALUE**|**MEANING**|
|---|---|---|---|
|7:6|Response<br>For all values of bits [7:6], the LTM4682:<br>• Sets the corresponding fault bit in the status commands and<br>• Notifies the host by assertingALERTpin, unless masked.<br>The fault bit, once set, is cleared only when one or more of the<br>following events occurs:<br>• The device receives a CLEAR_FAULTS command.<br>• The output is commanded through the RUN pin, the OPERATION<br>command, or the combined action of the RUN pin and<br>OPERATION command to turn off and then to turn back on, or<br>• Biaspower is removed and reapplied to the LTM4682.|00|Part performs OV pull down only or OV_PULLDOWN<br>(i.e., turns off the top MOSFET and turns on lower MOSFET<br>while VOUTis > VOUT_OV_FAULT).|
|||01|The PMBus device continues operation for the delay time<br>specified by bits [2:0] and the delay time unit specified for that<br>particular fault. If the fault condition is still present at the end of<br>the delay time, the unit responds as programmed in the Retry<br>Setting (bits[5:3]).|
|||10|The device shuts down immediately (disables the output) and<br>responds accordingto the retrysettingin bits[5:3].|
|||11|Not supported. Writing this value will generate a CML fault.|
|5:3|Retry Setting|000|The unit does not attempt to restart. The output remains<br>disabled until the fault is cleared until the device is commanded<br>OFF biaspower is removed.|
|||111|The PMBus device attempts to restart continuously, without<br>limitation, until it is commanded OFF (by the RUN pin or<br>OPERATION command or both), bias power is removed, or another<br>fault condition causes the unit to shut down without retry. Note: The<br>retryinterval is set bythe MFR_RETRY_DELAY command.|
|2:0|Delay Time|000-111|The delay time is in 10µs increments. This delay time<br>determines how long the controller continues operating after a<br>fault is detected. It is onlyvalid for the deglitched off state.|
## _**VOUT_UV_FAULT_RESPONSE**_
The VOUT_UV_FAULT_RESPONSE command instructs the device on what action is to be taken in response to an output undervoltage fault. The data byte is in the format as shown in Table 18.
The device also:
- Sets the NONE_OF_THE_ABOVE bit in the STATUS_BYTE
- Sets the VOUT bit in the STATUS_WORD
- Sets the VOUT undervoltage fault bit in the STATUS_VOUT command
- Notifies the host by asserting ALERT pin, unless masked
Rev. 0
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LTM4682
## **PMBus COMMAND DETAILS**
The UV fault and warn are masked until the following criteria are achieved:
- 1) The TON_MAX_FAULT_LIMIT has been reached
- 2) The TON_DELAY sequence has been completed
- 3) The TON_RISE sequence has been completed
- 4) The VOUT_UV_FAULT_LIMIT threshold has been reached
- 5) The IOUT_OC_FAULT_LIMIT is not present
The UV fault and warn are masked whenever the channel is not active.
The UV fault and warn are masked during TON_RISE and TOFF_FALL sequencing.
This command has one data byte.
**Table 18. VOUT_UV_FAULT_RESPONSE Data Byte Contents**
|**BITS**|**DESCRIPTION**|**VALUE**|**MEANING**|
|---|---|---|---|
|7:6|Response<br>For all values of bits [7:6], the LTM4682:<br>• Sets the corresponding fault bit in the status commands and<br>• Notifies the host by assertingALERTpin, unless masked.<br>The fault bit, once set, is cleared only when one or more of the<br>following events occurs:<br>• The device receives a CLEAR_FAULTS command.<br>• The output is commanded through the RUN pin, the OPERATION<br>command, or the combined action of the RUN pin and<br>OPERATION command, to turn off and then to turn back on, or<br>• The device receives a RESTORE_USER_ALL command.<br>• The device receives a MFR_RESET command.<br>• The device supply power is cycled.|00|The PMBus device continues operation without interruption.<br>(Ignores the fault functionally).|
|||01|The PMBus device continues operation for the delay time<br>specified by bits [2:0] and the delay time unit specified for<br>that particular fault. If the fault condition is still present at the<br>end of the delay time, the unit responds as programmed in the<br>Retry Setting(bits[5:3]).|
|||10|The device shuts down (disables the output) and responds<br>according to the retry setting in bits[5:3].|
|||11|Not supported. Writing this value will generate a CML fault.|
|5:3|Retry Setting|000|The unit does not attempt to restart. The output remains<br>disabled until the fault is cleared until the device is commanded<br>OFF bias power is removed.|
|||111|The PMBus device attempts to restart continuously, without<br>limitation, until it is commanded OFF (by the RUN pin or<br>OPERATION command or both), bias power is removed, or<br>another fault condition causes the unit to shut down without<br>retry. Note: The retry interval is set by the MFR_RETRY_DELAY<br>command.|
|2:0|Delay Time|000-111|The delay time is in 10µs increments. This delay time<br>determines how long the controller continues operating after a<br>fault is detected. It is only valid for the deglitched off state.|
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LTM4682
## **PMBus COMMAND DETAILS**
## _**TON_MAX_FAULT_RESPONSE**_
The TON_MAX_FAULT_RESPONSE command instructs the device on what action is to be taken in response to a TON_MAX fault. The data byte is in the format as shown in Table 21.
The device also:
- Sets the NONE_OF_THE_ABOVE bit in the STATUS_BYTE
- Sets the VOUT bit in the STATUS_WORD
- Sets the TON_MAX_FAULT bit in the STATUS_VOUT command
- Notifies the host by asserting ALERT pin, unless masked
A value of 0 disables the TON_MAX_FAULT_RESPONSE. It is not recommended to use 0.
Note: The PWM channel remains in discontinues mode until the TON_MAX_FAULT_LIMIT has been exceeded.
This command has one data byte.
## **Fault Responses Output Current**
|**COMMAND NAME**|**CMD CODE**|**DESCRIPTION**|**TYPE**|**PAGED**|**DATA**<br>**FORMAT**|**UNITS**|**NVM**|**DEFAULT**<br>**VALUE**|
|---|---|---|---|---|---|---|---|---|
|IOUT_OC_FAULT_RESPONSE|0x47|Action is to be taken by the device when<br>an output overcurrent fault is detected.|R/W Byte|Y|Reg||Y|0x00|
## _**IOUT_OC_FAULT_RESPONSE**_
The IOUT_OC_FAULT_RESPONSE command instructs the device on what action is to be taken in response to an output overcurrent fault. The data byte is in the format given in Table 19.
The device also:
- Sets the NONE_OF_THE_ABOVE bit in the STATUS_BYTE
- Sets the IOUT_OC bit in the STATUS_BYTE
- Sets the IOUT bit in the STATUS_WORD
- Sets the IOUT Overcurrent Fault bit in the STATUS_IOUT command
- Notifies the host by asserting ALERT pin, unless masked
This command has one data byte.
Rev. 0
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LTM4682
## **PMBus COMMAND DETAILS**
## **Table 19. IOUT_OC_FAULT_RESPONSE Data Byte Contents**
|**BITS**|**DESCRIPTION**|**VALUE**|**MEANING**|
|---|---|---|---|
|7:6|Response<br>For all values of bits [7:6], the LTM4682:<br>• Sets the corresponding fault bit in the status commands and<br>• Notifies the host by assertingALERTpin, unless masked.<br>The fault bit, once set, is cleared only when one or more of the<br>following events occurs:<br>• The device receives a CLEAR_FAULTS command.<br>• The output is commanded through the RUN pin, the OPERATION<br>command, or the combined action of the RUN pin and<br>OPERATION command, to turn off and then to turn back on, or<br>• The device receives a RESTORE_USER_ALL command.<br>• The device receives a MFR_RESET command.<br>• The device supply power is cycled.|00|The LTM4682 continues to operate indefinitely while<br>maintaining the output current at the value set by<br>IOUT_OC_FAULT_LIMIT without regard to the output<br>voltage(known as constant-current or brick-wall limiting).|
|||01|Not supported.|
|||10|The LTM4682 continues to operate, maintaining the output<br>current at the value set by IOUT_OC_FAULT_LIMIT without<br>regard to the output voltage, for the delay time set by bits [2:0].<br>If the device is still operating in the current limit at the end of<br>the delay time, the device responds as programmed by the<br>Retry Setting in bits[5:3].|
|||11|The LTM4682 shuts down immediately and responds as<br>programmed by the Retry Setting in bits [5:3].|
|5:3|Retry Setting|000|The unit does not attempt to restart. The output remains<br>disabled until the fault is cleared by cycling the RUN pin or<br>removing bias power.|
|||111|The device attempts to restart continuously, without limitation,<br>until it is commanded OFF (by the RUN pin or OPERATION<br>command or both), bias power is removed, or another fault<br>condition causes the unit to shut down. Note: The retry interval<br>is set by the MFR_RETRY_DELAY command.|
|2:0|Delay Time|000-111|The number of delay time units in 16ms increments. This<br>delay time is used to determine the amount of time a unit is<br>to continue operating after a fault is detected before shutting<br>down. It is only valid for the deglitched off response.|
## **Fault Responses IC Temperature**
|**COMMAND NAME**|**CMD CODE **|**DESCRIPTION**|**TYPE**|**PAGED**|**DATA**<br>**FORMAT**|**UNITS**|**NVM**|**DEFAULT**<br>**VALUE**|
|---|---|---|---|---|---|---|---|---|
|MFR_OT_FAULT_RESPONSE|0xD6|Action is to be taken by the device when<br>an internal overtemperature fault is<br>detected.|R Byte|N|Reg|||0xC0|
## _**MFR_OT_FAULT_RESPONSE**_
The MFR_OT_FAULT_RESPONSE command byte instructs the device on what action should be taken in response to an internal overtemperature fault. The data byte is in the format given in Table 20.
## The LTM4682 also:
- Sets the NONE_OF_THE_ABOVE bit in the STATUS_BYTE
- Sets the MFR bit in the STATUS_WORD
- Sets the overtemperature fault bit in the STATUS_MFR_SPECIFIC command
- Notifies the host by asserting ALERT pin, unless masked
Rev. 0
104
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LTM4682
## **PMBus COMMAND DETAILS**
This command has one data byte.
## **Table 20. Data Byte Contents MFR_OT_FAULT_RESPONSE**
|**BITS**|**DESCRIPTION**|**VALUE**|**MEANING**|
|---|---|---|---|
|7:6|Response<br>For all values of bits [7:6], the LTM4682:<br>• Sets the corresponding fault bit in the status commands and<br>• Notifies the host by assertingALERTpin, unless masked.<br>The fault bit, once set, is cleared only when one or more of the<br>following events occurs:<br>• The device receives a CLEAR_FAULTS command.<br>• The output is commanded through the RUN pin, the OPERATION<br>command, or the combined action of the RUN pin and<br>OPERATION command, to turn off and then to turn back on, or<br>• Bias power is removed and reapplied to the LTM4682.|00|Not supported. Writing this value will generate a CML fault.|
|||01|Not supported. Writing this value will generate a CML fault.|
|||10|The device shuts down immediately (disables the output) and<br>responds according to the retry setting in bits[5:3].|
|||11|The device’s output is disabled while the fault is present.<br>Operation resumes, and the output is enabled when the fault<br>condition no longer exists.|
|5:3|Retry Setting|000|The unit does not attempt to restart. The output remains<br>disabled until the fault is cleared.|
|||001-111|Not supported. Writing this value will generate a CML fault.|
|2:0|Delay Time|XXX|Not supported. Value ignored.|
## **Fault Responses External Temperature**
|**COMMAND NAME**|**CMD CODE **|**DESCRIPTION**|**TYPE**|**PAGED**|**DATA**<br>**FORMAT**|**UNITS**|**NVM**|**DEFAULT**<br>**VALUE**|
|---|---|---|---|---|---|---|---|---|
|OT_FAULT_RESPONSE|0x50|Action is to be taken by the device when an<br>external overtemperature fault is detected,|R/W Byte|Y|Reg||Y|0xB8|
|UT_FAULT_RESPONSE|0x54|Action is to be taken by the device when an<br>external undertemperature fault is detected.|R/W Byte|Y|Reg||Y|0xB8|
## _**OT_FAULT_RESPONSE**_
The OT_FAULT_RESPONSE command instructs the device on what action is to be taken in response to an external overtemperature fault on the external temperature sensors. The data byte is in the format given in Table 21.
The device also:
- Sets the TEMPERATURE bit in the STATUS_BYTE
- Sets the overtemperature fault bit in the STATUS_TEMPERATURE command
- Notifies the host by asserting ALERT pin, unless masked
This command has one data byte.
## _**UT_FAULT_RESPONSE**_
The UT_FAULT_RESPONSE command instructs the device on what action is to be taken in response to an external undertemperature fault on the external temp sensors. The data byte is in the format given in Table 15.
The device also:
- Sets the TEMPERATURE bit in the STATUS_BYTE
- Sets the undertemperature fault bit in the STATUS_TEMPERATURE command
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LTM4682
## **PMBus COMMAND DETAILS**
## • Notifies the host by asserting ALERT pin, unless masked
This condition is detected by the ADC so that the response time may be up to tCONVERT.
This command has one data byte.
## **Table 21. Data Byte Contents: TON_MAX_FAULT_RESPONSE, VIN_OV_FAULT_RESPONSE, OT_FAULT_RESPONSE, UT_FAULT_RESPONSE**
|**BITS**|**DESCRIPTION**|**VALUE**|**MEANING**|
|---|---|---|---|
|7:6|Response<br>For all values of bits [7:6], the LTM4682:<br>• Sets the corresponding fault bit in the status commands, and<br>• Notifies the host by assertingALERTpin, unless masked.<br>The fault bit, once set, is cleared only when one or more of the<br>following events occurs:<br>• The device receives a CLEAR_FAULTS command.<br>• The output is commanded through the RUN pin, the OPERATION<br>command, or the combined action of the RUN pin and<br>OPERATION command, to turn off and then to turn back on, or<br>• The device receives a RESTORE_USER_ALL command.<br>• The device receives a MFR_RESET command.<br>• The device supply power is cycled.|00|The PMBus device continues operation without interruption.|
|||01|Not supported. Writing this value will generate a CML fault.|
|||10|The device shuts down immediately (disables the output) and<br>responds according to the retry setting in bits[5:3].|
|||11|Not supported. Writing this value will generate a CML fault.|
|5:3|Retry Setting|000|The unit does not attempt to restart. The output remains<br>disabled until the fault is cleared until the device is commanded<br>OFF bias power is removed.|
|||111|The PMBus device attempts to restart continuously, without<br>limitation, until it is commanded OFF (by the RUN pin, or<br>OPERATION command, or both), bias power is removed, or<br>another fault condition causes the unit to shut down without<br>retry. Note: The retry interval is set by the MFR_RETRY_DELAY<br>command.|
|2:0|Delay Time|XXX|Not supported. Values ignored.|
## **FAULT SHARING**
## **Fault Sharing Propagation**
|**COMMAND NAME**|**CMD CODE**|**DESCRIPTION**|**TYPE**|**PAGED**|**DATA**<br>**FORMAT**|**UNITS**|**NVM**|**DEFAULT**<br>**VALUE**|
|---|---|---|---|---|---|---|---|---|
|MFR_FAULT_PROPAGATE|0xD2|Configuration that determines which faults<br>are propagated to the FAULT pins.|R/W Word|Y|Reg||Y|0x6993|
## _**MFR_FAULT_PROPAGATE**_
The MFR_FAULT_PROPAGATE command enables the faults that can cause the FAULT _n_ pin to assert low. The command is formatted as shown in Table 22. Faults can only be propagated to the FAULT _n_ pin if they are programmed to respond to faults.
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LTM4682
## **PMBus COMMAND DETAILS**
This command has two data bytes.
## **Table 22. FAULT** _**n**_ **Propagate Fault Configuration**
The FAULT0 and FAULT1 pins are designed to provide electrical notification of selected events to the user. Some of these events are common to both output channels. Others are specific to an output channel. They can also be used to share faults between channels.
|**BIT(S)**|**SYMBOL**|**OPERATION**|
|---|---|---|
|B[15]|VOUT disabled while not decayed.|This is used in a PolyPhase configuration when bit 0 of the MFR_CHAN_CONFIG_LTM4682 is<br>zero. If the channel is turned off, by toggling the RUN pin, or commanding the part OFF, and then<br>the RUN is reasserted, or the part is commanded back on before the output has decayed, VOUT<br>will not restart until the 12.5% decay is honored. TheFAULTpin is asserted during this condition<br>if bit 15 is asserted.|
|B[14]|Mfr_fault_propagate_short_CMD_cycle|0: No action.<br>1: Asserts low if commanded off then on before the output has sequenced off. Re-asserts high<br>tOFF(MIN)after sequence off.|
|b[13]|Mfr_fault_propagate_ton_max_fault|0: No action if a TON_MAX_FAULT fault is asserted.<br>1: Associated output will be asserted low if a TON_MAX_FAULT fault is asserted.<br>FAULT0is associated with page 0 TON_MAX_FAULT faults.<br>FAULT1is associated withpage 1 TON_MAX_FAULT faults.|
|b[12]|Reserved||
|b[11]|Mfr_fault0_propagate_int_ot,<br>Mfr_fault1_propagate_int_ot|0: No action if the MFR_OT_FAULT_LIMIT fault is asserted.<br>1: Associated output will be asserted low if the MFR_OT_FAULT_LIMIT fault is asserted.|
|b[10]|Reserved||
|b[9]|Reserved||
|b[8]|Mfr_fault0_propagate_ut,<br>Mfr_fault1_propagate_ut|0: No action if the UT_FAULT_LIMIT fault is asserted.<br>1: Associated output will be asserted low if the UT_FAULT_LIMIT fault is asserted.<br>FAULT0is associated with page 0 UT faults.<br>FAULT1is associated withpage 1 UT faults.|
|b[7]|Mfr_fault0_propagate_ot,<br>Mfr_fault1_propagate_ot|0: No action if the OT_FAULT_LIMIT fault is asserted.<br>1: Associated output will be asserted low if the OT_FAULT_LIMIT fault is asserted.<br>FAULT0is associated with page 0 OT faults.<br>FAULT1is associated withpage 1 OT faults.|
|b[6]|Reserved||
|b[5]|Reserved||
|b[4]|Mfr_fault0_propagate_input_ov,<br>Mfr_fault1_propagate_input_ov|0: No action if the VIN_OV_FAULT_LIMIT fault is asserted.<br>1: Associated output will be asserted low if the VIN_OV_FAULT_LIMIT fault is asserted.|
|b[3]|Reserved||
|b[2]|Mfr_fault0_propagate_iout_oc,<br>Mfr_fault1_propagate_iout_oc|0: No action if the IOUT_OC_FAULT_LIMIT fault is asserted.<br>1: Associated output will be asserted low if the IOUT_OC_FAULT_LIMIT fault is asserted.<br>FAULT0is associated with page 0 OC faults.<br>FAULT1is associated withpage 1 OC faults.|
|b[1]|Mfr_fault0_propagate_vout_uv,<br>Mfr_fault1_propagate_vout_uv|0: No action if the VOUT_UV_FAULT_LIMIT fault is asserted.<br>1: Associated output will be asserted low if the VOUT_UV_FAULT_LIMIT fault is asserted.<br>FAULT0is associated with page 0 UV faults.<br>FAULT1is associated withpage 1 UV faults.|
|b[0]|Mfr_fault0_propagate_vout_ov,<br>Mfr_fault1_propagate_vout_ov|0: No action if the VOUT_OV_FAULT_LIMIT fault is asserted.<br>1: Associated output will be asserted low if the VOUT_OV_FAULT_LIMIT fault is asserted.<br>FAULT0is associated with page 0 OV faults.<br>FAULT1is associated withpage 1 OV faults.|
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## LTM4682
## **PMBus COMMAND DETAILS**
## **Fault Sharing Response**
|**COMMAND NAME**|**CMD CODE **|**DESCRIPTION**|**TYPE**|**PAGED**|**DATA**<br>**FORMAT**|**UNITS**|**NVM**|**DEFAULT**<br>**VALUE**|
|---|---|---|---|---|---|---|---|---|
|MFR_FAULT_RESPONSE|0xD5|Action is to be taken by the device when the<br>FAULTpin is asserted low.|R/W Byte|Y|Reg||Y|0xC0|
## _**MFR_FAULT_RESPONSE**_
The MFR_FAULT_RESPONSE command instructs the device on what action is to be taken in response to the FAULT _n_ pin being pulled low by an external source.
## Supported Values:
|Supported|Values:|
|---|---|
|**VALUE**|**MEANING**|
|0xC0|FAULT_INHIBIT. The LTM4682 will three-state the output in response to theFAULTpin pulled low.|
|0x00|FAULT_IGNORE. The LTM4682 continues operation without interruption.|
## The device also:
- Sets the MFR bit in the STATUS_WORD
- Sets bit 0 in the STATUS_MFR_SPECIFIC command to indicate FAULT _n_ is being pulled low
- Notifies the host by asserting ALERT, unless masked
This command has one data byte.
## **SCRATCHPAD**
|**SCRATCHPAD**|||||||||
|---|---|---|---|---|---|---|---|---|
|**COMMAND NAME**|**CMD CODE**|**DESCRIPTION**|**TYPE**|**PAGED**|**DATA**<br>**FORMAT**|**UNITS**|**NVM**|**DEFAULT**<br>**VALUE**|
|USER_DATA_00|0xB0|OEM reserved. Typically used for part<br>serialization.|R/W Word|N|Reg||Y|NA|
|USER_DATA_01|0xB1|Manufacturer reserved for LTpowerPlay.|R/W Word|Y|Reg||Y|NA|
|USER_DATA_02|0xB2|OEM reserved. Typically used for part<br>serialization.|R/W Word|N|Reg||Y|NA|
|USER_DATA_03|0xB3|A NVM word available for the user.|R/W Word|Y|Reg||Y|0x0000|
|USER_DATA_04|0xB4|A NVM word available for the user.|R/W Word|N|Reg||Y|0x0000|
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LTM4682
## **PMBus COMMAND DETAILS**
## _**USER_DATA_00 through USER_DATA_04**_
These commands are nonvolatile memory locations for customer storage. The customer has the option to write any value to the USER_DATA_nn at any time. However, the LTpowerPlay software and contract manufacturers use some of these commands for inventory control. Modifying the reserved USER_DATA_nn commands may lead to undesirable inventory control and incompatibility with these products.
These commands have 2 data bytes and are in a register format.
## **IDENTIFICATION**
|**COMMAND NAME**|**CMD CODE **|**DESCRIPTION**|**TYPE**|**PAGED**|**DATA**<br>**FORMAT**|**UNITS**|**NVM**|**DEFAULT**<br>**VALUE**|
|---|---|---|---|---|---|---|---|---|
|PMBus_REVISION|0x98|PMBus revision, supported by this device. The<br>current revision is 1.2.|R Byte|N|Reg||FS|0x22|
|CAPABILITY|0x19|Summary of PMBus optional communication<br>protocols supported bythis device.|R Byte|N|Reg|||0xB0|
|MFR_ID|0x99|The manufacturer ID of the LTM4682 is in ASCII.|R String|N|ASC|||LTC|
|MFR_MODEL|0x9A|Manufacturerpart number in ASCII.|R String|N|ASC|||LTM4682|
|MFR_SPECIAL_ID|0xE7|Manufacturer code representingthe LTM4682.|R Word|N|Reg|||0x418X|
## _**PMBus_REVISION**_
The PMBUS_REVISION command indicates the revision of the PMBus to which the device is compliant. The LTM4682 is PMBus Version 1.2 compliant in both Part I and Part II.
This read-only command has one data byte.
## _**CAPABILITY**_
This command provides a way for a host system to determine some key capabilities of a PMBus device.
The LTM4682 supports packet error checking, 400kHz bus speeds, and an ALERT pin.
This read-only command has one data byte.
## _**MFR_ID**_
The MFR_ID command indicates the manufacturer ID of the LTM4682 using ASCII characters.
This read-only command is in block format.
## _**MFR_MODEL**_
The MFR_MODEL command indicates the manufacturer’s part number of the LTM4682 using ASCII characters. This read-only command is in block format.
## _**MFR_SPECIAL_ID**_
The 16-bit word represents the part name and revision. 0x418X denotes that the part is an LTM4682, and X is adjustable by the manufacturer.
This read-only command has two data bytes.
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LTM4682
## **PMBus COMMAND DETAILS**
## **FAULT WARNING AND STATUS**
|**COMMAND NAME**|**CMD CODE**|**DESCRIPTION**|**TYPE**|**PAGED**|**FORMAT**|**UNITS**|**NVM**|**DEFAULT**<br>**VALUE**|
|---|---|---|---|---|---|---|---|---|
|CLEAR_FAULTS|0x03|Clear anyfault bits that have been set.|Send Byte|N||||NA|
|SMBALERT_MASK|0x1B|Mask activity.|Block R/W|Y|Reg||Y|See CMD<br>Details|
|MFR_CLEAR_PEAKS|0xE3|Clears allpeak values.|Send Byte|Y||||NA|
|STATUS_BYTE|0x78|One-byte summary of the unit’s fault<br>condition.|R/W Byte|Y|Reg|||NA|
|STATUS_WORD|0x79|Two-byte summary of the unit’s fault<br>condition.|R/W Word|Y|Reg|||NA|
|STATUS_VOUT|0x7A|Output voltage fault and warning<br>status.|R/W Byte|Y|Reg|||NA|
|STATUS_IOUT|0x7B|Output current fault and warning<br>status.|R/W Byte|Y|Reg|||NA|
|STATUS_INPUT|0x7C|Input supplyfault and warningstatus.|R/W Byte|N|Reg|||NA|
|STATUS_TEMPERATURE|0x7D|External temperature fault and warning<br>status for READ_TEMERATURE_1.|R/W Byte|Y|Reg|||NA|
|STATUS_CML|0x7E|Communication and memory fault and<br>warningstatus.|R/W Byte|N|Reg|||NA|
|STATUS_MFR_SPECIFIC|0x80|Manufacturer-specific fault and state<br>information.|R/W Byte|Y|Reg|||NA|
|MFR_PADS|0xE5|Digital status of the I/Opads.|R Word|N|Reg|||NA|
|MFR_COMMON|0xEF|Manufacturer status bits that are<br>common across multiple ADI chips.|R Byte|N|Reg|||NA|
## _**CLEAR_FAULTS**_
The CLEAR_FAULTS command is used to clear any fault bits that have been set. This command clears all bits in all status commands simultaneously. At the same time, the device negates (clears, releases) its ALERT pin signal output if the device is asserting the ALERT pin signal. If the fault is still present when the bit is cleared, the fault bit will remain set, and the host will be notified by asserting the ALERT pin low. CLEAR_FAULTS can take up to 10µs to process. If a fault occurs within that time frame, it may be cleared before the status register is set.
This write-only command has no data bytes.
The CLEAR_FAULTS does not cause a unit that has latched off for a fault condition to restart. Units that have shut down for a fault condition are restarted when:
- The output is commanded through the RUN pin, the OPERATION command, or the combined action of the RUN pin and OPERATION command, to turn off and then to turn back on, or
- MFR_RESET command is issued.
- Bias power is removed and reapplied to the integrated circuit
## _**SMBALERT_MASK**_
The SMBALERT_MASK command can be used to prevent a particular status bit or bits from asserting ALERT as they are asserted.
Figure 55 shows an example of the Write Word format used to set an ALERT mask, in this case, without PEC. The bits in the mask byte align with bits in the specified status register. For example, if the STATUS_TEMPERATURE command code is sent in the first data byte, and the mask byte contains 0x40, then a subsequent External Overtemperature Warning
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LTM4682
## **PMBus COMMAND DETAILS**
would still set bit 6 of STATUS_TEMPERATURE but not assert ALERT. All other supported STATUS_TEMPERATURE bits would continue to assert ALERT if set.
Figure 55 and Figure 56 show an example of the Block Write – Block Read Process Call protocol used to read back the present state of any supported status register, again without PEC.
SMBALERT_MASK cannot be applied to STATUS_BYTE, STATUS_WORD, MFR_COMMON, or MFR_PADS_LTM4682. Factory default masking for applicable status registers is shown below. Providing an unsupported command code to SMBALERT_MASK will generate a CML for Invalid/Unsupported Data.
SMBALERT_MASK Default Setting: (See Figure 2)
|**STATUS RESISTER**|**ALERT MASK VALUE **|**MASKED BITS**|
|---|---|---|
|STATUS_VOUT|0x00|None|
|STATUS_IOUT|0x00|None|
|STATUS_TEMPERATURE|0x00|None|
|STATUS_CML|0x00|None|
|STATUS_INPUT|0x00|None|
|STATUS_MFR_SPECIFIC|0x11|Bit 4(internal PLL unlocked),bit 0(FAULT pulled low byexternal device).|
**==> picture [306 x 145] intentionally omitted <==**
**----- Start of picture text -----**<br>
1 7 1 1 8 1 8 1 8 1 1<br>S SUBORDINATE W A SMBALERT_MASK A STATUS_x A MASK BYTE A P<br>ADDRESS COMMAND CODE COMMAND CODE<br>4682 F55<br>Figure 55. Example of Writing SMBALERT_MASK<br>1 7 1 1 8 1 8 1 8 1<br>S SUBORDINATE W A SMBALERT_MASK A BLOCK COUNT A STATUS_x A …<br>ADDRESS COMMAND CODE (= 1) COMMAND CODE<br>1 7 1 1 8 1 8 1 1<br>SUBORDINATE BLOCK COUNT<br>Sr R A A MASK BYTE NA P<br>ADDRESS (= 1)<br>4682 F56<br>**----- End of picture text -----**<br>
**Figure 56. Example of Reading SMBALERT_MASK**
## _**MFR_CLEAR_PEAKS**_
The MFR_CLEAR_PEAKS command clears the MFR_*_PEAK data values. A MFR_RESET command will also clear the MFR_*_PEAK data values.
This write-only command has no data bytes.
## _**STATUS_BYTE**_
The STATUS_BYTE command returns one byte of information with a summary of the most critical faults. This is the lower byte of the status word.
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LTM4682
## **PMBus COMMAND DETAILS**
STATUS_BYTE Message Contents:
|**BIT**|**STATUS BIT NAME**|**MEANING**|
|---|---|---|
|7*|BUSY|A fault was declared because the LTM4682 was unable to respond.|
|6|OFF|This bit is set if the channel is not providing power to its output, regardless of the reason, including not being<br>enabled.|
|5|VOUT_OV|An output overvoltage fault has occurred.|
|4|IOUT_OC|An output overcurrent fault has occurred.|
|3|VIN_UV|Not supported(LTM4682 returns 0).|
|2|TEMPERATURE|A temperature fault or warninghas occurred.|
|1|CML|A communications,memory,or logic fault has occurred.|
|0*|NONE OF THE ABOVE|A fault Not listed in bits[7:1]has occurred.|
*ALERT can be asserted if either of these bits is set. They may be cleared by writing a 1 to their bit position in the STATUS_BYTE instead of a CLEAR_FAULTS command.
This command has one data byte.
## _**STATUS_WORD**_
The STATUS_WORD command returns a two-byte summary of the channel's fault condition. The low byte of the STATUS_WORD is the same as the STATUS_BYTE command.
STATUS_WORD High Byte Message Contents:
|**BIT**|**STATUS BIT NAME**|**MEANING**|
|---|---|---|
|15|VOUT|An output voltage fault or warninghas occurred.|
|14|IOUT|An output current fault or warninghas occurred.|
|13|INPUT|An input voltage fault or warninghas occurred.|
|12|MFR_SPECIFIC|A fault or warningspecific to the LTM4682 has occurred.|
|11|POWER_GOOD#|The POWER_GOOD state is false if this bit is set.|
|10|FANS|Not supported(LTM4682 returns 0).|
|9|OTHER|Not supported(LTM4682 returns 0).|
|8|UNKNOWN|Not supported(LTM4682 returns 0).|
If any of the bits in the upper byte are set, NONE_OF_THE_ABOVE is asserted. This command has two data bytes.
## _**STATUS_VOUT**_
The STATUS_VOUT command returns one byte of VOUT status information.
## STATUS_VOUT Message Contents:
|**BIT**|**MEANING**|
|---|---|
|7|VOUTovervoltage fault.|
|6|VOUTovervoltage warning.|
|5|VOUTundervoltage warning.|
|4|VOUTundervoltage fault.|
|3|VOUTmax warning.|
|2|TON max fault.|
|1|TOFF max fault.|
|0|Not supported(LTM4682 returns 0).|
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LTM4682
## **PMBus COMMAND DETAILS**
The user is permitted to write a 1 to any bit in this command to clear a specific fault. This permits the user to clear status by means other than using the CLEAR_FAULTS command.
Any supported fault bit in this command will initiate an ALERT event.
This command has one data byte.
## _**STATUS_IOUT**_
The STATUS_IOUT command returns one byte of IOUT status information.
## STATUS_IOUT Message Contents:
|**BIT**|**MEANING**|
|---|---|
|7|IOUTovercurrent fault.|
|6|Not supported(LTM4682 returns 0).|
|5|IOUTovercurrent warning.|
|4:0|Not supported(LTM4682 returns 0).|
The user is permitted to write a 1 to any bit in this command to clear a specific fault. This permits the user to clear status by means other than using the CLEAR_FAULTS command.
Any supported fault bit in this command will initiate an ALERT event. This command has one data byte.
## _**STATUS_INPUT**_
The STATUS_INPUT command returns one byte of VIN (VINSNS) status information.
STATUS_INPUT Message Contents:
|**BIT**|**MEANING**|
|---|---|
|7|VINovervoltage fault.|
|6|Not supported(LTM4682 returns 0).|
|5|VINundervoltage warning.|
|4|Not supported(LTM4682 returns 0).|
|3|Unit off for insufficient VIN.|
|2|Not supported(LTM4682 returns 0).|
|1|IINovercurrent warning.|
|0|Not supported(LTM4682 returns 0).|
The user is permitted to write a 1 to any bit in this command to clear a specific fault. This permits the user to clear status by means other than using the CLEAR_FAULTS command.
Any supported fault bit in this command will initiate an ALERT event. Bit 3 of this command is not latched and will not generate an ALERT even if it is set. This command has one data byte.
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LTM4682
## **PMBus COMMAND DETAILS**
## _**STATUS_TEMPERATURE**_
The STATUS_TEMPERATURE command returns one byte with status information on temperature. This is a paged command and is related to the respective READ_TEMPERATURE_1 value.
STATUS_TEMPERATURE Message Contents:
|**BIT**|**MEANING**|
|---|---|
|7|External overtemperature fault|
|6|External overtemperature warning|
|5|Not supported(LTM4682 returns 0)|
|4|External undertemperature fault|
|3:0|Not supported(LTM4682 returns 0)|
The user is permitted to write a 1 to any bit in this command to clear a specific fault. This permits the user to clear status by means other than using the CLEAR_FAULTS command.
This command has one data byte.
## _**STATUS_CML**_
The STATUS_CML command returns one byte of status information on received commands, internal memory, and logic.
STATUS_CML Message Contents:
|**BIT**|**MEANING**|
|---|---|
|7|Invalid or unsupported command received.|
|6|Invalid or unsupported data received.|
|5|The packet error check failed.|
|4|Memory fault detected.|
|3|Processor fault detected.|
|2|Reserved(LTM4682 returns 0).|
|1|Other communication faults.|
|0|Other memory or logic faults.|
If either bit 3 or bit 4 of this command is set, a serious and significant internal error has been detected. Continued operation of the part is not recommended if these bits are continuously set.
The user is permitted to write a 1 to any bit in this command to clear a specific fault. This permits the user to clear status by means other than using the CLEAR_FAULTS command.
Any supported fault bit in this command will initiate an ALERT event.
This command has one data byte.
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LTM4682
## **PMBus COMMAND DETAILS**
## _**STATUS_MFR_SPECIFIC**_
The STATUS_MFR_SPECIFIC commands return one byte with the manufacturer-specific status information. The format for this byte is:
|**BIT**|**MEANING**|
|---|---|
|7|Internal temperature fault limit exceeded.|
|6|Internal temperature warn limit exceeded.|
|5|Factory trim area NVM CRC fault.|
|4|PLL is unlocked.|
|3|Fault log present.|
|2|VDD33UV or OV fault.|
|1|ShortCycle event detected.|
|0|FAULTpin asserted low by external device.|
If any of these bits are set, the MFR bit in the STATUS_WORD will be set, and ALERT may be asserted.
The user is permitted to write a 1 to any bit in this command to clear a specific fault. This permits the user to clear status by means other than using the CLEAR_FAULTS command. However, the fault log present bit can only be cleared by issuing the MFR_FAULT_LOG_CLEAR command.
Any supported fault bit in this command will initiate an ALERT event.
This command has one data byte.
## _**MFR_PADS**_
This command provides the user with a means of directly reading the digital status of the I/O pins of the device. The bit assignments of this command are as follows:
|**BIT**|**ASSIGNED DIGITAL PIN**|
|---|---|
|15|VDD33OV fault.|
|14|VDD33UV fault.|
|13|Reserved.|
|12|Reserved.|
|11|ADC values invalid,occurs duringstart-up. mayoccur brieflyon current measurement channels duringnormal operation.|
|10|SYNC clocked byan external device(when LTM4682 configured to drive SYNCpin).|
|9|Channel 1powergood.|
|8|Channel 0powergood.|
|7|LTM4682 drivingRUN1 low.|
|6|LTM4682 drivingRUN0 low.|
|5|RUN1pin state.|
|4|RUN0pin state.|
|3|LTM4682 driving FAULT1 low.|
|2|LTM4682 driving FAULT0 low.|
|1|FAULT1pin state.|
|0|FAULT0pin state.|
## A 1 indicates the condition is true.
This read-only command has two data bytes.
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LTM4682
## **PMBus COMMAND DETAILS**
## _**MFR_COMMON**_
The MFR_COMMON command contains bits that are common to all Analog Devices digital power and telemetry products.
|**BIT**|**MEANING**|
|---|---|
|7|Module not drivingALERTlow.|
|6|LTM4682 not busy.|
|5|Calculations not pending.|
|4|LTM4682 outputs not in transition.|
|3|NVM Initialized.|
|2|Reserved.|
|1|SHARE_CLK timeout.|
|0|WP pin status.|
## This read-only command has one data byte.
## **TELEMETRY**
|**TELEMETRY**|||||||||
|---|---|---|---|---|---|---|---|---|
|**COMMAND NAME**|**CMD**<br>**CODE**|**DESCRIPTION**|**TYPE**|**PAGED**|**FORMAT**|**UNITS**|**NVM**|**DEFAULT**<br>**VALUE**|
|READ_VIN|0x88|Measured input supplyvoltage.|R Word|N|L11|V||NA|
|READ_IIN|0x89|Measured input supplycurrent.|R Word|N|L11|A||NA|
|READ_VOUT|0x8B|Measured output voltage.|R Word|Y|L16|V||NA|
|READ_IOUT|0x8C|Measured output current.|R Word|Y|L11|A||NA|
|READ_TEMPERATURE_1|0x8D|Power stage temperature sensor. This is<br>the value used for all temperature-related<br>processing,includingIOUT_CAL_GAIN.|R Word|Y|L11|C||NA|
|READ_TEMPERATURE_2|0x8E|Internal junction temperature. Does not affect<br>anyother controller commands.|R Word|N|L11|C||NA|
|READ_FREQUENCY|0x95|Measured PWM switchingfrequency.|R Word|Y|L11|Hz||NA|
|READ_POUT|0x96|Calculated outputpower.|R Word|Y|L11|W||NA|
|READ_PIN|0x97|Calculated inputpower.|R Word|N|L11|W||NA|
|MFR_PIN_ACCURACY|0xAC|Returns the accuracyof the READ_PIN command|R Byte|N||%||5.0%|
|MFR_IOUT_PEAK|0xD7|Report the maximum measured value of READ_<br>IOUT since the last MFR_CLEAR_PEAKS.|R Word|Y|L11|A||NA|
|MFR_VOUT_PEAK|0xDD|The maximum measured value of READ_VOUT<br>since the last MFR_CLEAR_PEAKS.|R Word|Y|L16|V||NA|
|MFR_VIN_PEAK|0xDE|The maximum measured value of READ_VIN<br>since the last MFR_CLEAR_PEAKS.|R Word|N|L11|V||NA|
|MFR_TEMPERATURE_1_PEAK|0xDF|The maximum measured value of external<br>Temperature (READ_TEMPERATURE_1) since<br>the last MFR_CLEAR_PEAKS.|R Word|Y|L11|C||NA|
|MFR_READ_IIN_PEAK|0xE1|The maximum measured value of the READ_IIN<br>command since the last MFR_CLEAR_PEAKS.|R Word|N|L11|A||NA|
|MFR_READ_ICHIP|0xE4|Measured current used bythe LTM4682.|R Word|N|L11|A||NA|
|MFR_TEMPERATURE_2_PEAK|0xF4|Peak internal die temperature since the last<br>MFR_CLEAR_PEAKS.|R Word|N|L11|C||NA|
|MFR_ADC_CONTROL|0xD8|The ADC telemetry parameter selected for<br>repeated fast ADC read back.|R/W Byte|N|N|Reg||NA|
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LTM4682
## **PMBus COMMAND DETAILS**
## _**READ_VIN**_
The READ_VIN command returns the measured VIN pin voltage, in volts added to READ_ICHIP • MFR_RVIN. This compensates for the IR voltage drop across the VIN filter element due to the supply current of the LTM4682.
This read-only command has two data bytes and is formatted in Linear_5s_11s format.
## _**READ_VOUT**_
The READ_VOUT command returns the measured output voltage by the VOUT_MODE command.
This read-only command has two data bytes and is formatted in Linear_16u format.
## _**READ_IIN**_
The READ_IIN command returns the input current, in Amperes, as measured across the input current sense resistor (see also MFR_IIN_CAL_GAIN).
This read-only command has two data bytes and is formatted in Linear_5s_11s format.
## _**READ_IOUT**_
The READ_IOUT command returns the average output current in amperes. The IOUT value is a function of:
a) the differential voltage measured across the ISENSE pins
b) the IOUT_CAL_GAIN value
c) the MFR_IOUT_CAL_GAIN_TC value, and
- d) READ_TEMPERATURE_1 value
- e) The MFR_TEMP_1_GAIN and the MFR_TEMP_1_OFFSET
This read-only command has two data bytes and is formatted in Linear_5s_11s format.
## _**READ_TEMPERATURE_1**_
The READ_TEMPERATURE_1 command returns the temperature, in degrees Celsius, of the power stage sense element.
This read-only command has two data bytes and is formatted in Linear_5s_11s format.
## _**READ_TEMPERATURE_2**_
The READ_TEMPERATURE_2 command returns the LTM4682’s die temperature, in degrees Celsius, of the internal sense element.
This read-only command has two data bytes and is formatted in Linear_5s_11s format.
## _**READ_FREQUENCY**_
The READ_FREQUENCY command is a reading of the PWM switching frequency in kHz.
This read-only command has 2 data bytes and is formatted in Linear_5s_11s format.
## _**READ_POUT**_
The READ_POUT command is a reading of the DC/DC converter output power in Watts. POUT is calculated based on the most recent correlated output voltage and current reading.
This read-only command has 2 data bytes and is formatted in Linear_5s_11s format.
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LTM4682
## **PMBus COMMAND DETAILS**
## _**READ_PIN**_
The READ_PIN command is a reading of the DC/DC converter input power in Watts. The PIN is calculated based on the most recent input voltage and current reading.
This read-only command has 2 data bytes and is formatted in Linear_5s_11s format.
## _**MFR_PIN_ACCURACY**_
The MFR_PIN_ACCURACY command returns the accuracy, in percent, of the value returned by the READ_PIN command. There is one data byte. The value is 0.1% per bit, which gives a range of ±0.0% to ±25.5%.
This read-only command has one data byte and is formatted as an unsigned integer.
## _**MFR_IOUT_PEAK**_
The MFR_IOUT_PEAK command reports the highest current, in amperes, reported by the READ_IOUT measurement. This command is cleared using the MFR_CLEAR_PEAKS command.
This read-only command has two data bytes and is formatted in Linear_5s_11s format.
## _**MFR_VOUT_PEAK**_
The MFR_VOUT_PEAK command reports the highest voltage, in volts, reported by the READ_VOUT measurement. This command is cleared using the MFR_CLEAR_PEAKS command.
This read-only command has two data bytes and is formatted in Linear_16u format.
## _**MFR_VIN_PEAK**_
The MFR_VIN_PEAK command reports the highest voltage, in volts, reported by the READ_VIN measurement.
This command is cleared using the MFR_CLEAR_PEAKS command.
This read-only command has two data bytes and is formatted in Linear_5s_11s format.
## _**MFR_TEMPERATURE_1_PEAK**_
The MFR_TEMPERATURE_1_PEAK command reports the highest temperature, in degrees Celsius, reported by the READ_TEMPERATURE_1 measurement.
This command is cleared using the MFR_CLEAR_PEAKS command.
This read-only command has two data bytes and is formatted in Linear_5s_11s format.
## _**MFR_READ_IIN_PEAK**_
The MFR_READ_IIN_PEAK command reports the highest current, in Amperes, reported by the READ_IIN measurement. This command is cleared using the MFR_CLEAR_PEAKS command.
This command has two data bytes and is formatted in Linear_5s_11s format.
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LTM4682
## **PMBus COMMAND DETAILS**
## _**MFR_READ_ICHIP**_
The MFR_READ_ICHIP command returns the measured input current, in Amperes, used by the LTM4682. This command has two data bytes and is formatted in Linear_5s_11s format.
## _**MFR_TEMPERATURE_2_PEAK**_
The MFR_TEMPERATURE_2_PEAK command reports the highest temperature, in degrees Celsius, reported by the READ_TEMPERATURE_2 measurement.
This command is cleared using the MFR_CLEAR_PEAKS command.
This read-only command has two data bytes and is formatted in Linear_5s_11s format.
## _**MFR_ADC_CONTROL**_
The MFR_ADC_CONTROL command determines the ADC read back selection. A default value of 0 in the command runs the standard telemetry loop with all parameters updated in a round-robin fashion with a typical latency of tCONVERT. The user can command a non-zero value to monitor a single parameter with an approximate update rate of 8ms. This command has a latency of up to 2 ADC conversions or approximately 16ms (external temperature conversions may have a latency of up to 3 ADC conversions or approximately 24ms). It is recommended that the part remain in standard telemetry mode except for special cases where fast ADC updates of a single parameter is required. The part should be commanded to monitor the desired parameter for a limited period of time (less than 1 second), then set the command back to standard round-robin mode. If this command is set to any value except standard round-robin telemetry (0), all warnings and faults associated with telemetry other than the selected parameter are effectively disabled, and voltage servoing is disabled. When a round-robin is reasserted, all warnings and faults and servo mode are re-enabled.
|**COMMANDED VALUE**|**TELEMETRY COMMAND NAME**|**DESCRIPTION**|
|---|---|---|
|0x0F||Reserved|
|0x0E||Reserved|
|0x0D||Reserved|
|0x0C|READ_TEMPERATURE_1|Channel 1 external temperature.|
|0x0B||Reserved|
|0x0A|READ_IOUT|Channel 1 measured output current.|
|0x09|READ_VOUT|Channel 1 measured output voltage.|
|0x08|READ_TEMPERATURE_1|Channel 0 external temperature.|
|0x07||Reserved|
|0x06|READ_IOUT|Channel 0 measured output current.|
|0x05|READ_VOUT|Channel 0 measured output voltage.|
|0x04|READ_TEMPERATURE_2|Internaljunction temperature.|
|0x03|READ_IIN|Measured input supplycurrent.|
|0x02|MFR_READ_ICHIP|Measured supplycurrent of the LTM4682.|
|0x01|READ_VIN|Measured input supplyvoltage.|
|0x00||Standard ADC round-robin telemetry.|
If a reserved command value is entered, the telemetry will default to Internal IC temperature and issue a CML fault. The CML faults will continue to be issued by the LTM4682 until a valid command value is entered. The accuracy of the measured input supply voltage is only guaranteed if the MFR_ADC_CONTROL command is set to standard roundrobin telemetry.
This write-only command has 1 data byte and is formatted in a register format.
Rev. 0
119
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LTM4682
## **PMBus COMMAND DETAILS**
## **NVM MEMORY COMMANDS**
## **Store/Restore**
|**COMMAND NAME**|**CMD**<br>**CODE**|**DESCRIPTION**|**TYPE**|**PAGED**|**FORMAT**|**UNITS**|**NVM**|**DEFAULT**<br>**VALUE**|
|---|---|---|---|---|---|---|---|---|
|STORE_USER_ALL|0x15|Store user operating memory to<br>EEPROM.|Send Byte|N||||NA|
|RESTORE_USER_ALL|0x16|Restore user operating memory<br>from EEPROM.|Send Byte|N||||NA|
|MFR_COMPARE_USER_ALL|0xF0|Compares current command contents<br>with NVM.|Send Byte|N||||NA|
## _**STORE_USER_ALL**_
The STORE_USER_ALL command instructs the PMBus device to copy the nonvolatile user contents of the operating memory to the matching locations in the nonvolatile User NVM memory.
Executing this command if the die temperature exceeds 85°C or is below 0°C is not recommended, and the data retention of 10 years cannot be guaranteed. If the die temperature exceeds 130°C, the STORE_USER_ALL command is disabled. The command is re-enabled when the IC temperature drops below 125°C.
Communication with the LTM4682 and programming of the NVM can be initiated when EXTVCC or VDD33 is available, and VIN is not applied. To enable the part in this state, using global address 0x5B, write MFR_EE_UNLOCK to 0x2B followed by 0xC4. The LTM4682 will now communicate normally, and the project file can be updated. To write the updated project file to the NVM issue, a STORE_USER_ALL command. When VIN is applied, an MFR_RESET must be issued to allow the PWM to be enabled and valid ADCs to be read.
This write-only command has no data bytes.
## _**RESTORE_USER_ALL**_
The RESTORE_USER_ALL command instructs the LTM4682 to copy the contents of the nonvolatile user memory to the matching locations in the operating memory. The values in the operating memory are overwritten by the value retrieved from the user commands. The LTM4682 ensures both channels are off, loads the operating memory from the internal EEPROM, clears all faults, reads the resistor configuration pins, and then performs a soft-start of both PWM channels if applicable.
STORE_USER_ALL, MFR_COMPARE_USER_ALL and RESTORE_USER_ALL commands are disabled if the die exceeds 130°C and are not re-enabled until the die temperature drops below 125°C.
This write-only command has no data bytes.
## _**MFR_COMPARE_USER_ALL**_
The MFR_COMPARE_USER_ALL command instructs the PMBus device to compare current command contents with what is stored in nonvolatile memory. If the compare operation detects differences, a CML bit 0 fault will be generated. This write-only command has no data bytes.
Rev. 0
120
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LTM4682
## **PMBus COMMAND DETAILS**
## **Fault Logging**
|**Fault Logging**|||||||||
|---|---|---|---|---|---|---|---|---|
|**COMMAND NAME**|**CMD CODE**|**DESCRIPTION**|**TYPE**|**PAGED**|**DATA**<br>**FORMAT**|**UNITS**|**NVM**|**DEFAULT**<br>**VALUE**|
|MFR_FAULT_LOG|0xEE|Fault logdata bytes.|R Block|N|CF||Y|NA|
|MFR_FAULT_LOG_STORE|0xEA|Command a transfer of the fault log from RAM<br>to EEPROM.|Send Byte|N||||NA|
|MFR_FAULT_LOG_CLEAR|0xEC|Initialize the EEPROM block reserved for fault<br>logging.|Send Byte|N||||NA|
## _**MFR_FAULT_LOG**_
The MFR_FAULT_LOG command allows the user to read the contents of the FAULT_LOG after the first fault occurrence since the last MFR_FAULT_LOG_CLEAR command was written. The contents of this command are stored in nonvolatile memory, and are cleared by the MFR_FAULT_LOG_CLEAR command. The length and content of this command are listed in Table 15. If the user accesses the MFR_FAULT_LOG command and a no-fault log is present, the command will return a data length of 0. If a fault log is present, the MFR_FAULT_LOG will return a block of data 147 bytes long. If a fault occurs within the first second of applying power, some of the earlier pages in the fault log may not contain valid data.
NOTE: The approximate transfer time for this command is 3.4ms using a 400kHz clock.
This read-only command is in block format.
## _**MFR_FAULT_LOG_STORE**_
The MFR_FAULT_LOG_STORE command forces the fault log operation to be written to NVM just as if a fault event occurred. This command will set bit 3 of the STATUS_MFR_SPECIFIC fault if bit 7, Enable Fault Logging, is set in the MFR_CONFIG_ALL command.
If the die temperature exceeds 130°C, the MFR_FAULT_LOG_STORE command is disabled until the IC temperature drops below 125°C.
This write-only command has no data bytes.
Rev. 0
121
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LTM4682
## **PMBus COMMAND DETAILS**
## **Table 23. Fault Logging**
This table outlines the format of the block data from a read block data of the MFR_FAULT_LOG command.
|**Data Format Definitions**||||LIN 11 = PMBus = Rev 1.2,Part 2,section 7.1|
|---|---|---|---|---|
|||||LIN 16 = PMBus Rev 1.2,Part 2,section 8. Mantissaportion only.|
|||||BYTE = 8 bits interpretedper definition of this command.|
|**DATA**|**BITS**|**DATA**<br>**FORMAT**|**BYTE NUM **|**BLOCK READ COMMAND**|
|Block Length||Byte|147|The MFR_FAULT_LOG command is a fixed length of 147 bytes.<br>The block length will be zero if a data logevent has not been captured.|
|**HEADER INFORMATION**|||||
|Fault Log Preface|[7:0]|ASC|0|Returns LTxx beginning at byte 0 if a partial or complete fault log exists.<br>Word xx is a factory identifier that may vary from part to part.|
||[7:0]||1||
||[15:8]|Reg|2||
||[7:0]||3||
|Fault Source|[7:0]|Reg|4|See Table 19.|
|MFR_REAL_TIME|[7:0]|Reg|5|48-bit share-clock counter value when the fault occurred (200µs<br>resolution).|
||[15:8]||6||
||[23:16]||7||
||[31:24]||8||
||[39:32]||9||
||[47:40]||10||
|MFR_VOUT_PEAK (PAGE 0)|[15:8]|L16|11|Peak READ_VOUT on Channel 0 since the last power-on or CLEAR_<br>PEAKS command.|
||[7:0]||12||
|MFR_VOUT_PEAK (PAGE 1)|[15:8]|L16|13|Peak READ_VOUT on Channel 1 since the last power-on or CLEAR_<br>PEAKS command.|
||[7:0]||14||
|MFR_IOUT_PEAK (PAGE 0)|[15:8]|L11|15|Peak READ_IOUT on Channel 0 since the last power-on or CLEAR_<br>PEAKS command.|
||[7:0]||16||
|MFR_IOUT_PEAK (PAGE 1)|[15:8]|L11|17|Peak READ_IOUT on Channel 1 since the last power-on or CLEAR_<br>PEAKS command.|
||[7:0]||18||
|MFR_VIN_PEAK|[15:8]|L11|19|Peak READ_VIN since the last power-on or CLEAR_PEAKS command.|
||[7:0]||20||
|READ_TEMPERATURE1 (PAGE 0)|[15:8]|L11|21|Power stage temperature sensor 0 during the last event.|
||[7:0]||22||
|READ_TEMPERATURE1 (PAGE 1)|[15:8]|L11|23|Power stage temperature sensor 1 during the last event.|
||[7:0]||24||
|READ_TEMPERATURE2|[15:8]|L11|25|LTM4682 die temperature sensor duringthe last event.|
||[7:0]||26||
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LTM4682
## **PMBus COMMAND DETAILS**
## **CYCLICAL DATA**
|**CYCLICAL DATA**|**CYCLICAL DATA**|**CYCLICAL DATA**|**CYCLICAL DATA**||
|---|---|---|---|---|
|**EVENT n**<br>**(Data at Which Fault Occurred; Most Recent Data)**||||Event n represents one complete cycle of ADC reads through the MUX at<br>the time of fault. Example: If the fault occurs when the ADC is processing<br>step 15, it will continue to take readings through step 25 and then store<br>the header and all six eventpages to EEPROM.|
|READ_VOUT (PAGE 0)|[15:8]|LIN 16|27||
||[7:0]|LIN 16|28||
|READ_VOUT (PAGE 1)|[15:8]|LIN 16|29||
||[7:0]|LIN 16|30||
|READ_IOUT (PAGE 0)|[15:8]|LIN 11|31||
||[7:0]|LIN 11|32||
|READ_IOUT (PAGE 1)|[15:8]|LIN 11|33||
||[7:0]|LIN 11|34||
|READ_VIN|[15:8]|LIN 11|35||
||[7:0]|LIN 11|36||
|READ_IIN|[15:8]|LIN 11|37||
||[7:0]|LIN 11|38||
|STATUS_VOUT(PAGE 0)||Byte|39||
|STATUS_VOUT(PAGE 1)||Byte|40||
|STATUS_WORD (PAGE 0)|[15:8]|Word|41||
||[7:0]|Word|42||
|STATUS_WORD (PAGE 1)|[15:8]|Word|43||
||[7:0]|Word|44||
|STATUS_MFR_SPECIFIC(PAGE 0)||Byte|45||
|STATUS_MFR_SPECIFIC(PAGE 1)||Byte|46||
|**EVENT n-1**<br>**(data measured before fault was detected)**|||||
|READ_VOUT (PAGE 0)|[15:8]|LIN 16|47||
||[7:0]|LIN 16|48||
|READ_VOUT (PAGE 1)|[15:8]|LIN 16|49||
||[7:0]|LIN 16|50||
|READ_IOUT (PAGE 0)|[15:8]|LIN 11|51||
||[7:0]|LIN 11|52||
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LTM4682
## **PMBus COMMAND DETAILS**
|READ_IOUT (PAGE 1)|[15:8]|LIN 11|53||
|---|---|---|---|---|
||[7:0]|LIN 11|54||
|READ_VIN|[15:8]|LIN 11|55||
||[7:0]|LIN 11|56||
|READ_IIN|[15:8]|LIN 11|57||
||[7:0]|LIN 11|58||
|STATUS_VOUT(PAGE 0)||BYTE|59||
|STATUS_VOUT(PAGE 1)||BYTE|60||
|STATUS_WORD (PAGE 0)|[15:8]|WORD|61||
||[7:0]|WORD|62||
|STATUS_WORD (PAGE 1)|[15:8]|WORD|63||
||[7:0]|WORD|64||
|STATUS_MFR_SPECIFIC(PAGE 0)||BYTE|65||
|STATUS_MFR_SPECIFIC(PAGE 1)||BYTE|66||
|**EVENT n-5**<br>**(Oldest Recorded Data)**|||||
|READ_VOUT (PAGE 0)|[15:8]|LIN 16|127||
||[7:0]|LIN 16|128||
|READ_VOUT (PAGE 1)|[15:8]|LIN 16|129||
||[7:0]|LIN 16|130||
|READ_IOUT (PAGE 0)|[15:8]|LIN 11|131||
||[7:0]|LIN 11|132||
|READ_IOUT (PAGE 1)|[15:8]|LIN 11|133||
||[7:0]|LIN 11|134||
|READ_VIN|[15:8]|LIN 11|135||
||[7:0]|LIN 11|136||
|READ_IIN|[15:8]|LIN 11|137||
||[7:0]|LIN 11|138||
|STATUS_VOUT(PAGE 0)||BYTE|139||
|STATUS_VOUT(PAGE 1)||BYTE|140||
|STATUS_WORD (PAGE 0)|[15:8]|WORD|141||
||[7:0]|WORD|142||
|STATUS_WORD (PAGE 1)|[15:8]|WORD|143||
||[7:0]|WORD|144||
|STATUS_MFR_SPECIFIC(PAGE 0)||BYTE|145||
|STATUS_MFR_SPECIFIC(PAGE 1)||BYTE|146||
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124
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LTM4682
## **PMBus COMMAND DETAILS**
**Table 24. Explanation of Position_Fault Values**
|**POSITION_FAULT VALUE**|**SOURCE OF FAULT LOG**|
|---|---|
|0xFF|MFR_FAULT_LOG_STORE|
|0x00|TON_MAX_FAULT|
|0x01|VOUT_OV_FAULT|
|0x02|VOUT_UV_FAULT|
|0x03|IOUT_OC_FAULT|
|0x05|TEMP_OT_FAULT|
|0x06|TEMP_UT_FAULT|
|0x07|VIN_OV_FAULT|
|0x0A|MFR_TEMP_2_OT_FAULT|
## _**MFR_INFO**_
Contact the factory for more details.
## _**MFR_IOUT_CAL_GAIN**_
Contact the factory for more details.
## _**MFR_FAULT_LOG_CLEAR**_
The MFR_FAULT_LOG_CLEAR command will erase the fault log file stored values. It will also clear bit 3 in the STATUS_MFR_SPECIFIC command. After a clear is issued, the status can take up to 8ms to clear.
This write-only command is to send bytes.
## **Block Memory Write/Read**
|**COMMAND NAME**|**CMD CODE **|**DESCRIPTION**|**TYPE**|**PAGED**|**DATA**<br>**FORMAT**|**UNITS**|**NVM**|**DEFAULT**<br>**VALUE**|
|---|---|---|---|---|---|---|---|---|
|MFR_EE_UNLOCK|0xBD|Unlock user EEPROM for access by MFR_EE_ERASE<br>and MFR_EE_DATA commands.|R/W Byte|N|Reg|||NA|
|MFR_EE_ERASE|0xBE|Initialize user EEPROM for bulk programming<br>by MFR_EE_DATA.|R/W Byte|N|Reg|||NA|
|MFR_EE_DATA|0xBF|Data transferred to and from EEPROM using<br>sequential PMBus word reads or writes. Supports<br>bulk programming.|R/W<br>Word|N|Reg|||NA|
All the NVM commands are disabled if the die temperature exceeds 130°C. The NVM commands are re-enabled when the die temperature drops below 125°C.
## _**MFR_EE_xxxx**_
The MFR_EE_xxxx commands facilitate bulk programming of the LTM4682 internal EEPROM. Contact the factory for more details.
Rev. 0
125
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LTM4682
## **PACKAGE DESCRIPTION**
## **PACKAGE ROW AND COLUMN LABELING MAY VARY AMONG µModule PRODUCTS. REVIEW EACH PACKAGE LAYOUT CAREFULLY.**
## **Table 25. LTM4682 BGA Pinout**
|**PIN ID**|**FUNCTION**|**PIN ID**|**FUNCTION**|**PIN ID**|**FUNCTION**|**PIN ID**|**FUNCTION**|**PIN ID**|**FUNCTION**|**PIN ID**|**FUNCTION**|
|---|---|---|---|---|---|---|---|---|---|---|---|
|A1|GND|B1|GND|C1|SW0|D1|SW0|E1|SW0|F1|GND|
|A2|GND|B2|GND|C2|SW0|D2|SW0|E2|SW0|F2|GND|
|A3|GND|B3|GND|C3|GND|D3|GND|E3|GND|F3|GND|
|A4|GND|B4|GND|C4|GND|D4|GND|E4|GND|F4|GND|
|A5|VIN01|B5|VIN01|C5|VIN01|D5|VIN01|E5|VIN01|F5|VIN01|
|A6|VIN01|B6|VIN01|C6|VIN01|D6|VIN01|E6|VIN01|F6|VIN01|
|A7|GND|B7|GND|C7|GND|D7|GND|E7|GND|F7|GND|
|A8|VOUT0_CFG|B8|VOUT1_CFG|C8|VDD25_01|D8|SHARE_CLK_01|E8|VDD33_01|F8|VOSNS1–|
|A9|FSWPH_01_CFG|B9|ASEL_01|C9|VTRIM1_CFG|D9|VTRIM0_CFG|E9|WP_01|F9|COMP1b|
|A10|FAULT1|B10|RUN0|C10|SDA_01|D10|SCL_01|E10|TSNS1|F10|SGND_01|
|A11|FAULT0|B11|RUN1|C11|ALERT_01|D11|SYNC_01|E11|TSNS0|F11|SGND_01|
|A12|GND|B12|GND|C12|GND|D12|GND|E12|GND|F12|GND|
|A13|VOUT0|B13|VOUT0|C13|VOUT0|D13|VOUT0|E13|VOUT0|F13|VOUT1|
|A14|VOUT0|B14|VOUT0|C14|VOUT0|D14|VOUT0|E14|VOUT0|F14|VOUT1|
|A15|VOUT0|B15|VOUT0|C15|VOUT0|D15|VOUT0|E15|VOUT0|F15|VOUT1|
|||||||||||||
|**PIN ID**|**FUNCTION**|**PIN ID**|**FUNCTION**|**PIN ID**|**FUNCTION**|**PIN ID**|**FUNCTION**|**PIN ID**|**FUNCTION**|**PIN ID**|**FUNCTION**|
|G1|SW1|H1|SW1|J1|SW1|K1|GND|L1|GND|M1|GND|
|G2|SW1|H2|SW1|J2|SW1|K2|GND|L2|GND|M2|GND|
|G3|GND|H3|GND|J3|GND|K3|GND|L3|GND|M3|GND|
|G4|GND|H4|GND|J4|GND|K4|GND|L4|GND|M4|GND|
|G5|VIN01|H5|VIN01|J5|VIN01|K5|VIN01|L5|GND|M5|GND|
|G6|VIN01|H6|VIN01|J6|VIN01|K6|VIN01|L6|GND|M6|GND|
|G7|GND|H7|GND|J7|GND|K7|GND|L7|GND|M7|GND|
|G8|VOSNS1+|H8|PGOOD1|J8|SVIN_01|K8|GND|L8|GND|M8|GND|
|G9|COMP1a|H9|PGOOD0|J9|INTVCC_01|K9|GND|L9|GND|M9|GND|
|G10|COMP0b|H10|IIN_01+|J10|IIN_01–|K10|GND|L10|GND|M10|GND|
|G11|COMP0a|H11|VOSNS0–|J11|VOSNS0+|K11|GND|L11|GND|M11|GND|
|G12|GND|H12|GND|J12|GND|K12|GND|L12|GND|M12|GND|
|G13|VOUT1|H13|VOUT1|J13|VOUT1|K13|VOUT1|L13|GND|M13|GND|
|G14|VOUT1|H14|VOUT1|J14|VOUT1|K14|VOUT1|L14|GND|M14|GND|
|G15|VOUT1|H15|VOUT1|J15|VOUT1|K15|VOUT1|L15|GND|M15|GND|
Rev. 0
126
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LTM4682
## **PACKAGE DESCRIPTION**
|**PIN ID**|**FUNCTION**|**PIN ID**|**FUNCTION**|**PIN ID**|**FUNCTION**|**PIN ID**|**FUNCTION**|**PIN ID**|**FUNCTION**|**PIN ID**|**FUNCTION**|
|---|---|---|---|---|---|---|---|---|---|---|---|
|N1|GND|P1|SW2|R1|SW2|T1|SW2|U1|GND|V1|SW3|
|N2|GND|P2|SW2|R2|SW2|T2|SW2|U2|GND|V2|SW3|
|N3|GND|P3|GND|R3|GND|T3|GND|U3|GND|V3|GND|
|N4|GND|P4|GND|R4|GND|T4|GND|U4|GND|V4|GND|
|N5|VIN23|P5|VIN23|R5|VIN23|T5|VIN23|U5|VIN23|V5|VIN23|
|N6|VIN23|P6|VIN23|R6|VIN23|T6|VIN23|U6|VIN23|V6|VIN23|
|N7|GND|P7|GND|R7|GND|T7|GND|U7|GND|V7|GND|
|N8|GND|P8|VOSNS2+|R8|VOSNS2–|T8|COMP2a|U8|TSNS2|V8|SDA_23|
|N9|VIN_VBIAS|P9|IIN_23–|R9|IIN_23+|T9|COMP2b|U9|TSNS3|V9|SYNC_23|
|N10|VBIAS|P10|INTVCC_23|R10|PGOOD2|T10|PGOOD3|U10|SGND_23|V10|FAULT2|
|N11|RUNP|P11|SVIN_23|R11|VOSNS3+|T11|VOSNS3–|U11|SGND_23|V11|COMP3a|
|N12|GND|P12|GND|R12|GND|T12|GND|U12|GND|V12|GND|
|N13|VOUT2|P13|VOUT2|R13|VOUT2|T13|VOUT2|U13|VOUT2|V13|VOUT3|
|N14|VOUT2|P14|VOUT2|R14|VOUT2|T14|VOUT2|U14|VOUT2|V14|VOUT3|
|N15|VOUT2|P15|VOUT2|R15|VOUT2|T15|VOUT2|U15|VOUT2|V15|VOUT3|
|||**PIN ID**<br>**FUNCTION**<br>**PIN ID**<br>**FUNCTION**<br>**PIN ID**<br>**FUNCTION**<br>**PIN ID**<br>**FUNCTION**<br>W1<br>SW3<br>Y1<br>SW3<br>AA1<br>GND<br>AB1<br>GND<br>W2<br>SW3<br>Y2<br>SW3<br>AA2<br>GND<br>AB2<br>GND<br>W3<br>GND<br>Y3<br>GND<br>AA3<br>GND<br>AB3<br>GND<br>W4<br>GND<br>Y4<br>GND<br>AA4<br>GND<br>AB4<br>GND<br>W5<br>VIN23<br>Y5<br>VIN23<br>AA5<br>VIN23<br>AB5<br>VIN23<br>W6<br>VIN23<br>Y6<br>VIN23<br>AA6<br>VIN23<br>AB6<br>VIN23<br>W7<br>GND<br>Y7<br>GND<br>AA7<br>GND<br>AB7<br>GND<br>W8<br>ALERT_23<br>Y8<br>RUN3<br>AA8<br>VOUT2_CFG<br>AB8<br>VOUT3_CFG<br>W9<br>SCL_23<br>Y9<br>RUN2<br>AA9<br>FSWPH_23_CFG<br>AB9<br>VTRIM3_CFG<br>W10<br>FAULT3<br>Y10<br>VDD33_23<br>AA10<br>ASEL_23<br>AB10<br>VTRIM2_CFG<br>W11<br>COMP3b<br>Y11<br>WP_23<br>AA11 SHARE_CLK_23 AB11<br>VDD25_23<br>W12<br>GND<br>Y12<br>GND<br>AA12<br>GND<br>AB12<br>GND<br>W13<br>VOUT3<br>Y13<br>VOUT3<br>AA13<br>VOUT3<br>AB13<br>VOUT3<br>W14<br>VOUT3<br>Y14<br>VOUT3<br>AA14<br>VOUT3<br>AB14<br>VOUT3<br>W15<br>VOUT3<br>Y15<br>VOUT3<br>AA15<br>VOUT3<br>AB15<br>VOUT3||||||||||
|||**PIN ID**|**FUNCTION**|**PIN ID**|**FUNCTION**|**PIN ID**|**FUNCTION**|**PIN ID**|**FUNCTION**|||
|||W1|SW3|Y1|SW3|AA1|GND|AB1|GND|||
|||W2|SW3|Y2|SW3|AA2|GND|AB2|GND|||
|||W3|GND|Y3|GND|AA3|GND|AB3|GND|||
|||W4|GND|Y4|GND|AA4|GND|AB4|GND|||
|||W5|VIN23|Y5|VIN23|AA5|VIN23|AB5|VIN23|||
|||W6|VIN23|Y6|VIN23|AA6|VIN23|AB6|VIN23|||
|||W7|GND|Y7|GND|AA7|GND|AB7|GND|||
|||W8|ALERT_23|Y8|RUN3|AA8|VOUT2_CFG|AB8|VOUT3_CFG|||
|||W9|SCL_23|Y9|RUN2|AA9|FSWPH_23_CFG|AB9|VTRIM3_CFG|||
|||W10|FAULT3|Y10|VDD33_23|AA10|ASEL_23|AB10|VTRIM2_CFG|||
|||W11|COMP3b|Y11|WP_23|AA11|SHARE_CLK_23|AB11|VDD25_23|||
|||W12|GND|Y12|GND|AA12|GND|AB12|GND|||
|||W13|VOUT3|Y13|VOUT3|AA13|VOUT3|AB13|VOUT3|||
|||W14|VOUT3|Y14|VOUT3|AA14|VOUT3|AB14|VOUT3|||
|||W15|VOUT3|Y15|VOUT3|AA15|VOUT3|AB15|VOUT3|||
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For more information www.analog.com
LTM4682
## **PACKAGE DESCRIPTION**
**==> picture [467 x 604] intentionally omitted <==**
**----- Start of picture text -----**<br>
aaa Z<br>PACKAGE TOP VIEW<br>6<br>3<br>SEE NOTES PIN 1 SEE NOTES<br>A B C D E F G H J K L M N P R T U V W Y AA AB<br>1<br>2<br>3<br>4<br>e<br>5<br>Øb (330 PLACES) 6<br>Y 7<br>XZ Z 8 G<br>M M 9<br>ddd eee 1011 b<br>12<br>13 PACKAGE BOTTOM VIEW<br>14<br>15 PACKAGE ROW AND COLUMN LABELING MAY VARY AMONG µModule PRODUCTS. REVIEW EACH PACKAGE LAYOUT CAREFULLY<br>b e !<br>DETAILS OF PIN #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE PIN #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE<br>F<br>NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994 2. ALL DIMENSIONS ARE IN MILLIMETERS 3 BALL DESIGNATION PER JESD MS-028 AND JEP95 4 5. PRIMARY DATUM -Z- IS SEATING PLANE 6<br>A2<br>A<br>PACKAGE SIDE VIEW<br>NOTES BALL HT BALL DIMENSION PAD DIMENSION SUBSTRATE THK MOLD CAP HT INDUCTOR HT<br>DETAIL A MAX 6.00 0.60 1.92 0.70 0.53 0.37 1.55 3.50 0.15 0.10 0.20 0.25 0.10 0.35<br>H1<br>A1 SUBSTRATE<br>BGA Package b1 DIMENSIONS NOM 5.71 0.50 1.82 0.60 0.50 15.00 22.00 1.00 21.00 14.00 0.32 1.50<br>ccc Z MOLD CAP H2<br>MIN 5.58 0.40 1.72 0.50 0.47 0.27 1.45<br>TOTAL NUMBER OF BALLS: 330<br>(Reference DWG # BC-330-2 Rev Ø)<br>330-Lead (15mm × 22mm × 5.71mm) DETAIL A<br>H3 A A1 A2 b b1 D E e F G H1 H2 H3 aaa bbb ccc ddd eee fff<br>SYMBOL<br>INDUCTOR<br>0.00<br>10.50 9.50 8.50 7.50 6.50 5.50 4.50 3.50 2.50 1.50 0.50 0.50 1.50 2.50 3.50 4.50 5.50 6.50 7.50 8.50 9.50 10.50<br>D<br>14.30<br>TOP VIEW<br>SUGGESTED PCB LAYOUT<br>21.40 X<br>4 E Y<br>PIN “A1” CORNER<br>aaa Z<br>0.500 ±0.025 Ø 330x<br>03-22-2022-A<br>Z<br>Z<br>Z// bbb<br>Z // fff<br>7.00<br>6.00<br>5.00<br>4.00<br>3.00<br>2.00<br>1.00<br>0.00<br>1.00<br>2.00<br>3.00<br>4.00<br>5.00<br>6.00<br>7.00<br>**----- End of picture text -----**<br>
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For more information www.analog.com
LTM4682
## **REVISION HISTORY**
|**REV**|**DATE**|**DESCRIPTION**|**PAGE NUMBER**|
|---|---|---|---|
|0|07/24|Initial Release.|—|
Rev. 0
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Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implicatiFor more informati **on** or otherwise under any patent or patent rights of Analog Devices.www.analog.com
## LTM4682
## **PACKAGE PHOTOS**
## **Part marking is either ink mark or laser mark**
## **DESIGN RESOURCES**
|**DESIGN RESOURCES**|||
|---|---|---|
|**SUBJECT**|**DESCRIPTION**||
|µModule Design and Manufacturing Resources|Design:<br>• Selector Guides<br>• Demo Boards and Gerber Files<br>• Free Simulation Tools|Manufacturing:<br>• Quick Start Guide<br>• PCB Design, Assembly and Manufacturing Guidelines<br>• Package and Board Level Reliability|
|µModule Regulator Products Search|1. Sort table of products by parameters and download the result as a spread sheet.<br>2. Search using the Quick Power Search parametric table.<br>Quick Power Search<br>INPUT<br>|<br>Vin(Min)<br>Vv<br>Vin(Max)<br>Vv<br>OUTPUT |<br>Vout<br>Vv<br>lout<br>A<br>FEATURES |<br>LowEMI<br>Ultrathin<br>InternalHeat Sink<br>Multiple Outputs||
|Digital Power System Management|Analog Devices’ family of digital power supply management ICs are highly integrated solutions that<br>offer essential functions, including power supply monitoring, supervision, margining and sequencing,<br>and feature EEPROM for storing user configurations and fault logging.||
## **RELATED PARTS**
|**PART NUMBER **|**DESCRIPTION**|**COMMENTS**|
|---|---|---|
|LTP8800-2|135A DC/DCμModule Regulator with PMBus Interface|45V ≤ VIN≤ 65V,0.5V ≤ VOUT≤ 1.0V,22mm × 24mm × 6.7mm Surface Mount Package|
|LTP8800-1A|150A DC/DCμModule Regulator with PMBus Interface|45V ≤ VIN≤ 65V,0.5V ≤ VOUT≤ 1.1V,22mm × 24mm × 6.7mm Surface Mount Package|
|LTP8803-1A|160A DC/DCμModule Regulator with PMBus Interface|45V ≤ VIN≤ 65V,0.5V ≤ VOUT≤ 1.5V,22mm × 24mm × 22mm Surface Mount Package|
|LTP8800-4A|200A DC/DCμModule Regulator with PMBus Interface|45V ≤ VIN≤ 65V,0.5V ≤ VOUT≤ 1.1V,22mm × 24mm × 22mm Surface Mount Package|
|LTM4683|Low VOUT, Quad 31.25A or Single 125A µModule Regulator<br>with Digital Power System Management (PSM)|4.5V ≤ VIN≤ 14V, 0.3V ≤ VOUT≤ 0.7V, 15mm × 22mm × 5.71mm BGA|
|LTM4675|Dual 9A or Single 18A Step-Down μModule Regulator,<br>Digital PSM|4.5V ≤ VIN≤ 17V, 0.5V ≤ VOUT≤ 5.5V, 11.9mm × 16mm × 3.51mm BGA|
|LTM4673|Dual 12A and Dual 5A,QuadμModule Regulator,Digital PSM|4.5V ≤ VIN≤ 16V,0.6V ≤ VOUT≤ 3.3V or 5.5V,16mm × 16mm × 4.72mm BGA|
|LTM4686/<br>LTM4686-1|Ultrathin Dual 10A or Single 20A μModule Regulator, Digital PSM|4.5V ≤ VIN≤ 17V, 0.5V ≤ VOUT≤ 3.6V (LTM4686), 2.375V ≤ VIN≤ 17V (LTM4686-1)<br>11.9mm × 16mm × 1.82mm LGA|
|LTM4686B|Ultrathin Dual 14A or Single 28A µModule Regulator, Digital PSM,<br>Low VOUT,Higher IOUTVersion of LTM4686/LTM4686-1|4.5V ≤ VIN≤ 5.75, 0.5V ≤ VOUT≤ 3.6V, 11.9mm × 16mm × 1.82mm LGA|
|LTM4676A|Dual 13A or Single 26A Step-DownμModule Regulator,Digital PSM|4.5V ≤ VIN≤ 26.5V,0.5V ≤ VOUT≤ 5.5V,16mm × 16mm × 5.01mm BGA|
|LTM4677|Dual 18A or Single 36A Step-DownμModule Regulator,Digital PSM|4.5V ≤ VIN≤ 16V,0.5V ≤ VOUT≤ 1.8V,16mm × 16mm × 5.01mm BGA|
|LTM4678|Dual 25A or Single 50AμModule Regulator with Digital PSM|4.5V ≤ VIN≤ 16V,0.5V ≤ VOUT≤ 3.4V,16mm × 16mm × 5.86mm BGA|
|LTM4664|54VIN,Dual 25A or Single 50AμModule Regulator with Digital PSM|30V ≤ VIN≤ 58V,0.5V ≤ VOUT≤ 1.5V,16mm × 16mm × 7.72mm BGA|
|LTM4680|Dual 30A or Single 60A μModule Regulator with Digital PSM|4.5V ≤ VIN≤ 16V, 0.5V ≤ VOUT≤ 3.3V, 16mm × 16mm × 7.82mm BGA|
|LTM4681|Quad 31.25A or Single 125A, μModule Regulator with<br>Digital PSM, Higher VOUTVersion of LTM4683|4.5V ≤ VIN≤ 16V, 0.5V ≤ VOUT≤ 3.3V, 15mm × 22mm × 8.17mm BGA|
|LTM4700|Dual 50A or Single 100A μModule Regulator with Digital PSM|4.5V ≤ VIN≤ 16V, 0.5V ≤ VOUT≤ 1.8V, 15mm × 22mm × 7.87mm BGA|
Rev. 0
07/24 www.analog.com
130
ANALOG DEVICES, INC. 2024
For more information www.analog.com
Updated at April 10, 2026
Since its inception in 1965, Analog Devices has established itself as a global leader in the design and manufacturing of high-performance analog, mixed-signal, and digital signal processing (DSP) integrated circuits. The company is renowned for solving complex engineering challenges by providing critical technologies that seamlessly convert real-world phenomena into precise electrical signals for the industrial, automotive, communications, and consumer markets. Within its extensive portfolio, Analog Devices provides highly reliable clock, timing, and frequency management solutions, featuring a comprehensive array of precision timers, oscillators, and pulse generators. Complementing this core lineup is a robust offering of driver and interface ICs, particularly high-performance I/O expanders that enable seamless connectivity and streamline complex electronic system architectures. Beyond these foundational integrated circuits, Analog Devices leads the industry in sensor innovation, delivering advanced MEMS accelerometers and integrated MEMS modules designed for exceptional precision in motion sensing. To support complete hardware designs, the company's specialized offerings also encompass discrete bipolar transistors, sub-2.4GHz RF transceivers, temperature-compensated oscillators, and dedicated power management components such as DC/DC converters and LED driver ICs.
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