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LTM4675IY
DC/DC POL Converter, Adjustable, Buck, 4.5 to 17V in, 0.5 to 5.5V / 9A Out, BGA-108
⚠️ Reference pricing provided. In case of supply shortages, we will connect you with our trusted procurement partners to ensure your project's continuity.
- Manufacturer: ANALOG DEVICES
- Product type: DC / DC Non Isolated Board Mount Converters - Adjustable Output
- SVHC: No SVHC (07-Jul-2017)
- Depth: 16mm
- Width: 11.9mm
- Height: 3.51mm
- Topology: Buck (Step Down)
- No. of Pins: 108Pins
- Product Range: LTM4675 Series
- No. of Outputs: 2 Output
- Output Current: 9A
- Output Power Max: -
- Input Voltage Max: 17V
- Input Voltage Min: 4.5V
- Output Current Max: 9A
- Output Voltage Max: 5.5V
- Output Voltage Min: 500mV
- Switching Frequency: 500kHz
- Input Voltage DC Max: 17V
- Input Voltage DC Min: 4.5V
- DC / DC Converter Type: BGA-108, Micro Module
- DC / DC Converter IC Case: BGA
- Operating Temperature Max: 125°C
- Power Supply Applications: -
- DC / DC Converter Output Type: Adjustable
| Delivery and price | |
|---|---|
| Units per pack | 112 |
| Price | 53.64 € |
| Current stock | 100+ |
| Lead time | 30 days |
Datasheet
LTM4675
## Dual 9A or Single 18A µModule Regulator with Digital Power System Management
## **FEATURES**
- n **Dual, Fast, Analog Loops with Digital Interface for Control and Monitoring**
- n **Wide Input Voltage Range: 4.5V to 17V**
- n **Output Voltage Range: 0.5V to 5.5V**
- n **±0.5% Maximum DC Output Error Over Temperature**
- n **±2.5% Current Readback Accuracy at 9A Load**
- n **400kHz PMBus-Compliant I[2] C Serial Interface**
- n **Integrated 16-Bit** ∆Σ **ADC**
- n **Supports Telemetry Polling Rates Up to 125Hz**
- n **Constant Frequency Current Mode Control**
- n **Parallel and Current Share Multiple Modules**
- n All 7-Bit Slave Addresses Supported
- n Drop-In Pin-Compatible to Dual 13A LTM4676A and Dual 18A LTM4677
- n 16mm × 11.9mm × 3.51mm BGA Package
## **Readable Data:**
- n Input and Output Voltages, Currents, and Temperatures
- n Running Peak Values, Uptime, Faults and Warnings
- n Onboard EEPROM Fault Log Record with ECC
## **Writable Data and Configurable Parameters:**
- n Output Voltage, Voltage Sequencing and Margining
- n Digital Soft-Start/Stop Ramp
- n OV/UV/OT, UVLO, Frequency and Phasing
## **APPLICATIONS**
## **DESCRIPTION**
The LTM[®] 4675 is a dual 9A or single 18A step-down µModule[®] (micromodule) DC/DC regulator with 40ms turn-on time. It features remote configurability and telemetry-monitoring of power management parameters over PMBus— an open standard I[2] C-based digital interface protocol . The LTM4675 is comprised of fast analog control loops, precision mixed-signal circuitry, EEPROM, power MOSFETs, inductors and supporting components.
The LTM4675’s 2-wire serial interface allows outputs to be margined, tuned and ramped up and down at programmable slew rates with sequencing delay times. Input and output currents and voltages, output power, temperatures, uptime and peak values are readable. Custom configuration of the EEPROM contents is not required. At start-up, output voltages, switching frequency, and channel phase angle assignments can be set by pin-strapping resistors. The LTpowerPlay[®] GUI and DC1613 USB-to-PMBus converter and demo kits are available.
The LTM4675 is offered in a 16mm × 11.9mm × 3.51mm BGA package available with SnPb or RoHS compliant terminal finish.
All registered trademarks and trademarks are the property of their respective owners. Protected by U.S. Patents including 5408150, 5481178, 5705919, 5929620, 6144194, 6177787, 6580258, 7420359, 8163643. Licensed under U.S. Patent 7000125 and other related patents worldwide.
**Click to view associated Video Design Idea.**
- n System Optimization in Prototype and Production
## **TYPICAL APPLICATION**
**Using PMBus and LTpowerPlay to Monitor Telemetry and Margin VOUT0/VOUT1 During Load Pattern Tests. 10Hz Polling Rate. 12VIN**
**Dual 9A µModule Regulator with Digital Interface for Control and Monitoring***
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Interface for Control and Monitoring* Output Voltage Readback, V 1.1 OUT Margined 7.5% Low 1.9 1.0 Input Current Readback 2.0<br>5.75V TO 17VVIN VIN0 V OUT0 ADJUSTABLEVOUT0, 1.0 1.8<br>22µF×2 VSVIN1IN VOSNS0+ LOAD0 100µF×UP TO 9A4 0.9 1.7 0.5 1.0<br>ON/OFF CONTROL RUNRUN01 LTM4675VOSNS0VOUT1 [–] ADJUSTABLEVOUT1, 0.80 3 TIME (s)6 9 4675 TA01b121.6 00 3 TIME (s)6 9 4675 TA01d120<br>FAULT INTERRUPTS, GPIO0 UP TO 9A<br>POWER SEQUENCING GPIO1 VOSNS1 Output Current Readback, Varying Load Pattern Power Stage Temperature Readback<br>LOAD1 100µF 10 10 60 60<br>PWM CLOCK AND SYNC SGND ×4<br>TIME-BASE SHARE_CLK 57 57<br>SYNCHRONIZATION 5 5<br>SCL I [2] C/SMBus I/F WITH 54 54<br>REGISTER WRITE SDA PMBus COMMAND SET<br>PROTECTION WP GND ALERT TO/FROM IPMI OR OTHER 0 0 51 51<br>4675 TA01a BOARD MANAGEMENT 0 3 6 9 12 0 3 6 9 12<br>*FOR COMPLETE CIRCUIT, SEE FIGURE 61 CONTROLLER TIME (s) 4675 TA01c TIME (SEC) 4675 TA01e<br>Rev. D<br> (V) OUT1V (A) IN1I<br>VOUT0 (V) IIN0 (A)<br> (A) OUT1I<br>IOUT0 (A)<br>CHANNEL 0 TEMP (°C) CHANNEL 1 TEMP (°C)<br>**----- End of picture text -----**<br>
1
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LTM4675
## **TABLE OF CONTENTS**
**Features ..................................................... 1 Applications ................................................ 1 Typical Application ........................................ 1 Description.................................................. 1 Absolute Maximum Ratings .............................. 3 Order Information .......................................... 3 Pin Configuration .......................................... 3 Electrical Characteristics ................................. 4 Typical Performance Characteristics ..................11 Pin Functions ..............................................13 Simplified Block Diagram ...............................18 Decoupling Requirements ...............................18 Functional Diagram ......................................19 Test Circuits ...............................................20 Operation...................................................21** Power Module Introduction .........................................21 Power Module Configurability and Readback Data ......23 Time-Averaged and Peak Readback Data ....................25 Power Module Overview .............................................28 EEPROM .....................................................................32 Serial Interface ............................................................33 Device Addressing ......................................................33 Fault Detection and Handling ......................................34 Responses to VOUT and IOUT Faults.............................35 Responses to Timing Faults ........................................36 Responses to SVIN OV Faults ......................................36 Responses to OT/UT Faults .........................................36 Responses to External Faults .....................................36 Fault Logging ..............................................................37 Bus Timeout Protection ..............................................37 **PMBus Command Summary ............................38** PMBus Commands ....................................................38 **Applications Information ................................45** VIN to VOUT Step-Down Ratios ....................................48 Input Capacitors ..........................................................48 Output Capacitors .......................................................48 Light Load Current Operation ......................................48 Switching Frequency and Phase .................................49 Minimum On-Time Considerations ..............................51 Variable Delay Time, Soft-Start and Output Voltage Ramping .................................................................51 Digital Servo Mode .....................................................52 Soft Off (Sequenced Off) ............................................53 Undervoltage Lockout .................................................53 Fault Detection and Handling ......................................54
Open-Drain Pins ..........................................................54 Phase-Locked Loop and Frequency Synchronization ..55 RCONFIG Pin-Straps (External Resistor Configuration Pins) ....................56 Voltage Selection ........................................................56 Connecting the USB to the I[2] C/SMBus/PMBus Controller to the LTM4675 In System .....................56 LTpowerPlay: An Interactive GUI for Digital Power System Management ..............................................60 PMBus Communication and Command Processing ....61 Thermal Considerations and Output Current Derating..... 62 EMI Performance ........................................................69 Safety Considerations .................................................69 Layout Checklist/Example ...........................................69 **Typical Applications ......................................71 Appendix A .................................................77** Similarity Between PMBus, SMBus and I[2] C 2-Wire Interface ................................................77 **Appendix B .................................................78** PMBus Serial Digital Interface ....................................78 **Appendix C: PMBus Command Details ................82** Addressing and Write Protect .....................................82 General Configuration Registers .................................84 On/Off/Margin .............................................................85 PWM Config ...............................................................87 Voltage ........................................................................89 Current ........................................................................92 Temperature ................................................................95 Timing .........................................................................97 Fault Response ...........................................................99 Fault Sharing .............................................................106 Scratchpad ................................................................108 Identification .............................................................108 Fault Warning and Status ..........................................109 Telemetry .................................................................. 116 NVM (EEPROM) Memory Commands ....................... 120 **Package Description ................................... 127 Package Photograph ................................... 129 Package Description ................................... 130 Revision History ........................................ 131 Typical Application ..................................... 132 Design Resources ...................................... 132 Related Parts ............................................ 132**
Rev. D
2
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LTM4675
## **ABSOLUTE MAXIMUM RATINGS**
## **PIN CONFIGURATION**
## **(Note 1)**
## **Terminal Voltages:**
VIN _n_ (Note 4), SVIN ..................................... –0.3V to 20V VOUT _n_ ........................................................... –0.3V to 6V VOSNS0[+] , VORB0[+] , VOSNS1, VORB1, INTVCC .... –0.3V to 6V RUN _n_ , SDA, SCL, ALERT ........................... –0.3V to 5.5V FSWPHCFG, VOUT _n_ CFG, VTRIM _n_ CFG, ASEL .. –0.3V to 2.75V VDD33, GPIO _n_ , SYNC, SHARE_CLK, WP, COMP _n_ a, VOSNS0[–] , VORB0[–] ........................ –0.3V to 3.6V SGND ........................................................ –0.3V to 0.3V
## **Temperatures**
Internal Operating Temperature Range (Notes 2, 3) ............................................ –40°C to 125°C Storage Temperature Range .................. –55°C to 125°C Peak Solder Reflow Package Body Temperature ... 245°C
**==> picture [189 x 250] intentionally omitted <==**
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TOP VIEW<br>1 2 3 4 5 6 7 8 9<br>A<br>B<br>VOUT0 VIN0<br>C<br>D<br>E<br>F<br>GND SGND<br>G<br>H<br>J<br>K<br>VOUT1 VIN1<br>L<br>M<br>BGA PACKAGE<br>108-LEAD (16mm × 11.9mm × 3.51mm)<br>TJMAX = 125°C, θJCtop = 5.9°C/W, θJCbottom = 2.1°C/W, θJB = 2.7°C/W,<br>θJA = 16°C/W<br>θ VALUES DETERMINED PER JESD51-12<br>WEIGHT = 1.7 GRAMS<br>**----- End of picture text -----**<br>
## **ORDER INFORMATION**
|**PART NUMBER**|**PAD OR BALL FINISH**|**PART MARKING***|**PART MARKING***|**PACKAGE**<br>**TYPE**|**MSL**<br>**RATING**|**TEMPERATURE RANGE**<br>**(SEE NOTE 2)**|
|---|---|---|---|---|---|---|
|||**DEVICE**|**FINISH CODE**||||
|LTM4675EY#PBF|SAC305(RoHS)|LTM4675Y|e1|BGA|4|–40°C to 125°C|
|LTM4675IY#PBF|SAC305(RoHS)|LTM4675Y|e1|BGA|4|–40°C to 125°C|
|LTM4675IY|SnPb(63/37)|LTM4675Y|e0|BGA|4|–40°C to 125°C|
- Contact the factory for parts specified with wider operating temperature ranges. *Pad or ball finish code is per IPC/JEDEC J-STD-609.
- Device temperature grade is indicated by a label on the shipping container.
- Recommended LGA and BGA PCB Assembly and Manufacturing Procedures
- LGA and BGA Package and Tray Drawings
Rev. D
3
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## LTM4675
## **ELECTRICAL CHARACTERISTICS**
**The** l **denotes the specifications which apply over the specified internal operating temperature range (Note 2). Specified as each individual output channel (Note 4). TA = 25°C, VIN = 12V, RUN** _**n**_ **= 5V, FREQUENCY_SWITCH = 500kHz and VOUT** _**n**_ **commanded to 1.000V unless otherwise noted. Configured with factory-default EEPROM settings and per Test Circuit 1, unless otherwise noted.**
|**SYMBOL**|**PARAMETER**|**CONDITIONS**|**CONDITIONS**|**MIN**<br>**TYP**<br>**MAX**|**UNITS**|
|---|---|---|---|---|---|
|VIN|Input DC Voltage|Test Circuit 1<br>Test Circuit 2; VIN_OFF < VIN_ON = 4.25V|l<br>l|<br>5.75<br>4.5<br>17<br>5.75|V<br>V|
|VOUT_n_|Range of Output Voltage<br>Regulation|VOUT0Differentially Sensed on VOSNS0+/VOSNS0–Pin-Pair;<br>VOUT1Differentially Sensed on VOSNS1/SGND Pin-Pair;<br>Commanded by Serial Bus or with Resistors Present at Start-Up on<br>VOUT_n_CFGand/or VTRIM_n_CFG|l<br>l|<br>0.5<br>0.5<br>5.5<br>5.5|V<br>V|
|VOUT_n_(DC)|Output Voltage, Total<br>Variation with Line and<br>Load|(Note 5<br>VOUT_n_Low Range (MFR_PWM_MODE_n_[1] = 1b),<br>FREQUENCY_SWITCH = 425kHz )<br>Digital Servo Engaged (MFR_PWM_MODE_n_[6] = 1b)<br>Digital Servo Disengaged(MFR_PWM_MODE_n_[6]= 0b)|l|<br>0.995<br>0.985<br>1.000<br>1.000<br>1.005<br>1.015|V<br>V|
|**Input Specifications**||||||
|IINRUSH(VIN)|Input Inrush Current at<br>Start-Up|Test Circuit 1, VOUT_n_ =1V, VIN= 12V; No Load Besides Capacitors;<br>TON_RISE_n_ = 3ms||400|mA|
|IQ(SVIN)|Input Supply Bias Current|Forced Continuous Mode, MFR_PWM_MODE_n_[0] = 1b<br>RUN_n_= 5V, RUN1-_n_= 0V<br>Shutdown, RUN0= RUN1= 0V||40<br>20|mA<br>mA|
|IS(VIN_n_,PSM)|Input Supply Current in<br>Pulse-Skipping Mode<br>Operation|Pulse-Skipping Mode, MFR_PWM_MODE_n_[0] = 0b,<br>IOUT_n_= 100mA||20|mA|
|IS(VIN_n_,FCM)|Input Supply Current in<br>Forced-Continuous Mode<br>Operation|Forced Continuous Mode, MFR_PWM_MODE_n_[0] = 1b<br>IOUT_n_= 100mA<br>IOUT_n_= 9A||40<br>927|mA<br>mA|
|IS(VIN_n_,SHUTDOWN)|Input Supply Current in<br>Shutdown|Shutdown, RUN_n_= 0V||50|µA|
|**Output Specifications**||||||
|IOUT_n_|Output Continuous<br>Current Range|(Note 6)||0<br>9|A|
|∆VOUT_n_(LINE)<br>VOUT_n_|Line Regulation Accuracy|Digital Servo Engaged (MFR_PWM_MODE_n_[6] = 1b)<br>Digital Servo Disengaged (MFR_PWM_MODE_n_[6] = 0b)<br>SVINand VIN_n_Electrically Shorted Together and INTVCCOpen Circuit;<br>IOUT_n_ = 0A, 5.75V ≤ VIN≤ 17V, VOUTLow Range<br>(MFR_PWM_MODE_n_[1] = 1b) FREQUENCY_SWITCH = 425kHz<br>(Referenced to 12VIN) (Note 5)|l|0.03<br>0.03<br>±0.2|%<br>%/V|
|∆VOUT_n_(LOAD)<br> VOUT_n_|Load Regulation<br>Accuracy|Digital Servo Engaged (MFR_PWM_MODE_n_[6] = 1b)<br>Digital Servo Disengaged (MFR_PWM_MODE_n_[6] = 0b)<br>0A ≤ IOUT_n_≤ 9A, VOUTLow Range, (MFR_PWM_MODE_n_[1] = 1b)<br>FREQUENCY_SWITCH = 425kHz(Note 5)|l|0.03<br>0.2<br>0.5|%<br>%|
|VOUT_n_(AC)|Output Voltage Ripple|||10|mVP-P|
|fS (Each Channel)|VOUT_n_Ripple Frequency|FREQUENCY_SWITCH Set to 500kHz(0xFBE8)|l|462.5<br>500<br>537.5|kHz|
|∆VOUT_n_(START)|Turn-On Overshoot|TON_RISE_n_= 3ms(Note 12)||8|mV|
|tSTART|Turn-On Start-Up Time|Time from VINToggling from 0V to 12V to Rising Edge ofGPIO_n_.<br>TON_DELAY_n_= 0ms, TON_RISE_n_ = 3ms,<br>MFR_GPIO_PROPAGATE_n_= 0x0100,<br>MFR_GPIO_RESPONSE_n_= 0x0000|l|35<br>40|ms|
Rev. D
4
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LTM4675
## **ELECTRICAL CHARACTERISTICS**
**The** l **denotes the specifications which apply over the specified internal operating temperature range (Note 2). Specified as each individual output channel (Note 4). TA = 25°C, VIN = 12V, RUN** _**n**_ **= 5V, FREQUENCY_SWITCH = 500kHz and VOUT** _**n**_ **commanded to 1.000V unless otherwise noted. Configured with factory-default EEPROM settings and per Test Circuit 1, unless otherwise noted.**
|**SYMBOL**|**PARAMETER**|**CONDITIONS**|**CONDITIONS**|**MIN**<br>**TYP**<br>**MAX**|**UNITS**|
|---|---|---|---|---|---|
|tDELAY(0ms)|Turn-On Delay Time|Time from First Rising Edge of RUN_n_to Rising Edge ofGPIO_n_.<br>TON_DELAY_n_= 0ms, TON_RISE_n_= 3ms,<br>MFR_GPIO_PROPAGATE_n_= 0x0100,<br>MFR_GPIO_RESPONSE_n_= 0x0000.<br>VINHaving Been Established for at Least 40ms|l|2.75<br>3.1<br>3.5|ms|
|∆VOUT_n_(LS)|Peak Output Voltage<br>Deviation for Dynamic<br>Load Step|Load: 0A to 4.5A and 4.5A to 0A at 4.5A/µs, Figure 61 Circuit,<br>VOUT_n_= 1V, VIN= 12V (Note 12)||50|mV|
|tSETTLE|Settling Time for<br>Dynamic Load Step|Load: 0A to 4.5A and 4.5A to 0A at 4.5A/µs, Figure 61 Circuit,<br>VOUT_n_ = 1V, VIN= 12V(Note 12)||35|µs|
|IOUT_n_(OCL_PK)|Output Current Limit,<br>Peak|Cycle-by-Cycle Inductor Peak Current Limit Inception||15.8|A|
|IOUT_n_(OCL_AVG)|Output Current Limit,<br>Time Averaged|Time-Averaged Output Inductor Current Limit Inception Threshold,<br>Commanded by IOUT_OC_FAULT_LIMIT_n_(Note 12)||10.8A; See IO-RB-ACC<br>Specification (Output Current<br>Readback Accuracy)||
|**Control Section**||||||
|VFBCM0|Channel 0 Feedback Input<br>Common Mode Range|VOSNS0–Valid Input Range (Referred to SGND)<br>VOSNS0+Valid Input Range(Referred to SGND)|l<br>l|<br>–0.1<br>0.3<br>5.7|V<br>V|
|VFBCM1|Channel 1 Feedback Input<br>Common Mode Range|SGND Valid Input Range (Referred to GND)<br>VOSNS1Valid Input Range(Referred to SGND)|l<br>l|<br>–0.3<br>0.3<br>5.7|V<br>V|
|VOUT-RNG0|Full-Scale Command<br>Voltage, Range 0|(Notes 7, 15)<br>VOUT_n_Commanded to 5.500V, MFR_PWM_MODE_n_[1] = 0b<br>Resolution<br>LSB Step Size||5.422<br>12<br>1.375<br>5.576|V<br>Bits<br>mV|
|VOUT-RNG1|Full-Scale Command<br>Voltage, Range 1|(Notes 7, 15)<br>VOUT_n_Commanded to 2.750V, MFR_PWM_MODE_n_[1] = 1b<br>Resolution<br>LSB Step Size||2.711<br>12<br>0.6875<br>2.788|V<br>Bits<br>mV|
|RVOSNS0+|VOSNS0+Impedance to<br>SGND|0.05V ≤ VVOSNS0+– VSGND≤ 5.5V||41|kΩ|
|RVOSNS1|VOSNS1Impedance to<br>SGND|0.05V ≤ VVOSNS1– VSGND≤ 5.5V||37|kΩ|
|tON(MIN)|Minimum On-Time|(Note 8)||45|ns|
|**Analog OV/UV (Overvoltage/Undervoltage) Output Voltage Supervisor Comparators (VOUT_OV/UV_FAULT_LIMIT and VOUT_OV/UV_WARN_LIMIT Monitors)**||||||
|NOV/UV_COMP|Resolution, Output<br>Voltage Supervisors|(Note 15)||8|Bits|
|VOV-RNG|Output OV Comparator<br>Threshold Detection<br>Range|(Note 15)<br>High Range Scale, MFR_PWM_MODE_n_[1] = 0b<br>Low Range Scale, MFR_PWM_MODE_n_[1]= 1b||1<br>0.5<br>5.6<br>2.7|V<br>V|
|VOU-STP|Output OV and UV<br>Comparator Threshold<br>Programming LSB Step<br>Size|(Note 15)<br>High Range Scale, MFR_PWM_MODE_n_[1] = 0b<br>Low Range Scale, MFR_PWM_MODE_n_[1] = 1b||22<br>11|mV<br>mV|
Rev. D
5
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## LTM4675
## **ELECTRICAL CHARACTERISTICS**
**The** l **denotes the specifications which apply over the specified internal operating temperature range (Note 2). Specified as each individual output channel (Note 4). TA = 25°C, VIN = 12V, RUN** _**n**_ **= 5V, FREQUENCY_SWITCH = 500kHz and VOUT** _**n**_ **commanded to 1.000V unless otherwise noted. Configured with factory-default EEPROM settings and per Test Circuit 1, unless otherwise noted.**
|**SYMBOL**|**PARAMETER**|**CONDITIONS**|**CONDITIONS**|**MIN**<br>**TYP**<br>**MAX**|**UNITS**|
|---|---|---|---|---|---|
|VOV-ACC|Output OV Comparator<br>Threshold Accuracy|(See Note 14)<br>2V ≤ VVOSNS0+– VVOSNS0–≤ 5.6V, MFR_PWM_MODE0[1] = 0b<br>1V ≤ VVOSNS0+– VVOSNS0–≤ 2.7V, MFR_PWM_MODE0[1] = 1b<br>0.5V ≤ VVOSNS0+– VVOSNS0–< 1V, MFR_PWM_MODE0[1] = 1b<br>2V ≤ VVOSNS1– VSGND≤ 5.6V, MFR_PWM_MODE1[1] = 0b<br>1.5V ≤ VVOSNS1– VSGND≤ 2.7V, MFR_PWM_MODE1[1] = 1b<br>0.5V ≤ VVOSNS1– VSGND< 1.5V, MFR_PWM_MODE1[1]= 1b|l<br>l<br>l<br>l<br>l<br>l|<br> <br> <br> <br> <br>±2<br>±2<br>±20<br>±2<br>±2<br>±30|%<br>%<br>mV<br>%<br>%<br>mV|
|VUV-RNG|Output UV Comparator<br>Threshold Detection<br>Range|(Note 15)<br>High Range Scale, MFR_PWM_MODE_n_[1] = 0b<br>Low Range Scale, MFR_PWM_MODE_n_[1]= 1b||1<br>0.5<br>5.4<br>2.7|V<br>V|
|VUV-ACC|Output UV Comparator<br>Threshold Accuracy|(See Note 14)<br>2V ≤ VVOSNS0+– VVOSNS0–≤ 5.4V, MFR_PWM_MODE0[1] = 0b<br>1V ≤ VVOSNS0+– VVOSNS0–≤ 2.7V, MFR_PWM_MODE0[1] = 1b<br>0.5V ≤ VVOSNS0+– VVOSNS0–< 1V, MFR_PWM_MODE0[1] = 1b<br>2V ≤ VVOSNS1– VSGND≤ 5.4V, MFR_PWM_MODE1[1] = 0b<br>1.5V ≤ VVOSNS1– VSGND≤ 2.7V, MFR_PWM_MODE1[1] = 1b<br>0.5V ≤ VVOSNS1– VSGND< 1.5V, MFR_PWM_MODE1[1]= 1b|l<br>l<br>l<br>l<br>l<br>l|<br> <br> <br> <br> <br>±2<br>±2<br>±20<br>±2<br>±2<br>±30|%<br>%<br>mV<br>%<br>%<br>mV|
|tPROP-OV|Output OV Comparator<br>Response Times|Overdrive to 10% Above Programmed Threshold||35|µs|
|tPROP-UV|Output UV Comparator<br>Response Times|Underdrive to 10% Below Programmed Threshold||50|µs|
|**Analog OV/UV SVIN Input Voltage Supervisor Comparators (Threshold Detectors for VIN_ON and VIN_OFF)**||||||
|NSVIN-OV/UV-COMP|SVINOV/UV Comparator<br>Threshold-Programming<br>Resolution|(Note 15)||8|Bits|
|SVIN-OU-RANGE|SVINOV/UV Comparator<br>Threshold-Programming<br>Range||l|4.5<br>20|V|
|SVIN-OU-STP|SVINOV/UV Comparator<br>Threshold-Programming<br>LSB Step Size|(Note 15)||82|mV|
|SVIN-OU-ACC|SVINOV/UV Comparator<br>Threshold Accuracy|9V < SVIN≤ 20V<br>4.5V ≤ SVIN≤ 9V|l<br>l|<br>±2.5<br>±225|%<br>mV|
|tPROP-SVIN-HIGH-VIN|SVINOV/UV Comparator<br>Response Time, High VIN<br>Operating Configuration|Test Circuit 1, and:<br>VIN_ON = 9V; SVINDriven from 8.775V to 9.225V<br>VIN_OFF = 9V; SVINDriven from 9.225V to 8.775V|l<br>l|<br>35<br>35|µs<br>µs|
|tPROP-SVIN-LOW-VIN|SVINOV/UV Comparator<br>Response Time, Low VIN<br>Operating Configuration|Test Circuit 2, and:<br>VIN_ON = 4.5V; SVINDriven from 4.225V to 4.725V<br>VIN_OFF = 4.5V; SVINDriven from 4.725V to 4.225V|l<br>l|<br>35<br>35|µs<br>µs|
|**Channels 0 and 1 Output Voltage Readback (READ_VOUT****_n_)**||||||
|NVO-RB|Output Voltage Readback<br>Resolution and LSB Step<br>Size|(Note 15)||16<br>244|Bits<br>µV|
|VO-F/S|Output Voltage Full-Scale<br>Digitizable Range|VRUN_n_= 0V (Notes 7, 15)||8|V|
|VO-RB-ACC|Output Voltage Readback<br>Accuracy|Channel 0: 1V ≤ VVOSNS0+– VVOSNS0–≤ 5.5V<br>Channel 0: 0.6V ≤ VVOSNS0+ – VVOSNS0–< 1V<br>Channel 1: 1V ≤ VVOSNS1 – VSGND≤ 5.5V<br>Channel 1: 0.6V ≤ VVOSNS1– VSGND< 1V|l<br>l<br>l<br>l|<br> <br> <br>Within ±0.5% of Reading<br>Within ±5mV of Reading<br>Within ±0.5% of Reading<br>Within ±5mV of Reading||
Rev. D
6
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LTM4675
**ELECTRICAL CHARACTERISTICS The** l **denotes the specifications which apply over the specified internal operating temperature range (Note 2). Specified as each individual output channel (Note 4). TA = 25°C, VIN = 12V, RUN** _**n**_ **= 5V, FREQUENCY_SWITCH = 500kHz and VOUT** _**n**_ **commanded to 1.000V unless otherwise noted. Configured with factory-default EEPROM settings and per Test Circuit 1, unless otherwise noted.**
|**SYMBOL**|**PARAMETER**|**CONDITIONS**|**CONDITIONS**|**MIN**<br>**TYP**<br>**MAX**|**UNITS**|
|---|---|---|---|---|---|
|tCONVERT-VO-RB|Output Voltage Readback<br>Update Rate|MFR_ADC_CONTROL=0x00 (Notes 9, 15)<br>MFR_ADC_CONTROL=0x0D (Notes 9, 15)<br>MFR_ADC_CONTROL=0x05 or 0x09(Notes 9, 15)||90<br>27<br>8|ms<br>ms<br>ms|
|**Input Voltage (SVIN) Readback (READ_VIN)**||||||
|NSVIN-RB|Input Voltage Readback<br>Resolution and LSB Step<br>Size|(Notes 10, 15)||10<br>15.625|Bits<br>mV|
|SVIN-F/S|Input Voltage Full-Scale<br>Digitizable Range|(Notes 11, 15)||38.91|V|
|SVIN-RB-ACC|Input Voltage Readback<br>Accuracy|READ_VIN, 4.5V ≤ SVIN≤ 17V|l|Within ±2% of Reading||
|tCONVERT-SVIN-RB|Input Voltage Readback<br>Update Rate|MFR_ADC_CONTROL=0x00 (Notes 9, 15)<br>MFR_ADC_CONTROL=0x01(Notes 9, 15)||90<br>8|ms<br>ms|
|**Channels 0 and 1 Output Current (READ_IOUT****_n_), Duty Cycle (READ_DUTY_CYCLE****_n_), and Computed Input Current (MFR_READ_IIN****_n_) Readback**||||||
|NIO-RB|Output Current Readback<br>Resolution and LSB Step<br>Size|(Notes 10, 12)||10<br>15.6|Bits<br>mA|
|IO-F/S, II-F/S|Output Current Full-Scale<br>Digitizable Range and<br>Input Current Range of<br>Calculation|(Note 12)||±40|A|
|IO-RB-ACC|Output Current, Readback<br>Accuracy|READ_IOUT_n_, Channels 0 and 1, 0 ≤ IOUT_n_≤ 9A,<br>Forced-Continuous Mode, MFR_PWM_MODE_n_[0]=1b|l|Within 225mA of Reading||
|IO-RB(9A)|Full Load Output Current<br>Readback|IOUT_n_= 9A (Note 12). See Histograms in Typical Performance<br>Characteristics||9|A|
|NII-RB|Computed Input Current,<br>Readback Resolution and<br>LSB Step Size|(Notes 10, 12)||10<br>1.95|Bits<br>mA|
|II-RB-ACC|Computed Input Current,<br>Readback Accuracy,<br>Neglecting ISVIN|MFR_READ_IIN_n_, Channels 0 and 1, 0 ≤ IOUT_n_≤ 9A,<br>Forced-Continuous Mode, MFR_PWM_MODE_n_[0]=1b,<br>MFR_IIN_OFFSET_n_= 0mA|l|Within 140mA of Reading||
|tCONVERT-IO-RB|Output Current Readback<br>Update Rate|MFR_ADC_CONTROL=0x00 (Notes 9, 15)<br>MFR_ADC_CONTROL=0x0D (Notes 9, 15)<br>MFR_ADC_CONTROL=0x06 or 0x0A(Notes 9, 15)||90<br>27<br>8|ms<br>ms<br>ms|
|tCONVERT-II-RB|Computed Input Current,<br>Readback Update Rate|MFR_ADC_CONTROL=0x00 (Notes 9, 15)||90|ms|
|NDUTY-RB|Resolution, Duty Cycle<br>Readback|(Notes 10, 15)||10|Bits|
|DRB-ACC|Duty Cycle TUE|READ_DUTY_CYCLE_n_, 16.3% Duty Cycle(Note 15)||±3|%|
|tCONVERT-DUTY-RB|Duty Cycle Readback<br>Update Rate|MFR_ADC_CONTROL=0x00 (Notes 9, 15)||90|ms|
|**Temperature Readback for Channel 0, Channel 1, and Controller (Respectively: READ_TEMPERATURE_10, READ_TEMPERATURE_11,**<br>**and READ_TEMPERATURE_2)**||||||
|TRES-RB|Temperature Readback<br>Resolution|Channel 0, Channel 1, and Controller (Note 15)||0.0625|°C|
|TRB-CH-ACC(72mV)|Channel Temperature<br>TUE, Switching Action Off|Channels 0 and 1, PWM Inactive, RUN_n_= 0V,<br>∆VTSNS_n_a= 72mV|l|Within ±3°C of Reading||
Rev. D
7
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## LTM4675
## **ELECTRICAL CHARACTERISTICS**
**The** l **denotes the specifications which apply over the specified internal operating temperature range (Note 2). Specified as each individual output channel (Note 4). TA = 25°C, VIN = 12V, RUN** _**n**_ **= 5V, FREQUENCY_SWITCH = 500kHz and VOUT** _**n**_ **commanded to 1.000V unless otherwise noted. Configured with factory-default EEPROM settings and per Test Circuit 1, unless otherwise noted.**
|**SYMBOL**|**PARAMETER**|**CONDITIONS**||**MIN**|**TYP**|**MAX**|**UNITS**|
|---|---|---|---|---|---|---|---|
|TRB-CH-ACC(ON)|Channel Temperature<br>TUE, Switching Action On|READ_TEMPERATURE_1_n_, Channels 0 and 1,<br>PWM Active, RUN_n_= 5V(Note 12)||Within ±3°C||of Reading||
|TRB-CTRL-ACC(ON)|Control IC Die<br>Temperature TUE,|READ_TEMPERATURE_2, PWM Active, RUN0= RUN1= 5V<br>(Note 12)||Within ±1°C||of Reading||
||Switching Action On|||||||
|tCONVERT-TEMP-RB|Temperature Readback|MFR_ADC_CONTROL=0x00 (Notes 9, 15)|||90||ms|
||Update Rate|MFR_ADC_CONTROL=0x06 or 0x0A(Notes 9, 15)|||8||ms|
|**INTVCC Regulator**||||||||
|VINTVCC|Internal VCCVoltage No|6V ≤ VIN≤ 17V||4.8|5|5.2|V|
||Load|||||||
|∆VINTVCC(LOAD)|INTVCCLoad Regulation|0mA ≤ IINTVCC≤ 50mA|||0.5|±2|%|
|VINTVCC||||||||
|**VDD33 Regulator**||||||||
|VVDD33|Internal VDD33Voltage|||3.2|3.3|3.4|V|
|ILIM(VDD33)|VDD33Current Limit|VDD33Electrically Short-Circuited to GND|||70||mA|
|VVDD33_OV|VDD33Overvoltage|(Note 15)|||3.5||V|
||Threshold|||||||
|VVDD33_UV|VDD33Undervoltage|(Note 15)|||3.1||V|
||Threshold|||||||
|**VDD25 Regulator**||||||||
|VVDD25|Internal VDD25Voltage||||2.5||V|
|ILIM(VDD25)|VDD25Current Limit|VDD25Electrically Short-Circuited to GND|||50||mA|
|**Oscillator and Phase-Locked Loop (PLL)**||||||||
|fOSC|Oscillator Frequency|FREQUENCY_SWITCH = 500kHz (0xFBE8)|l|||±7.5|%|
||Accuracy|250kHz ≤ FREQUENCY_SWITCH ≤ 1MHz(Note 15)||||±7.5|%|
|fSYNC|PLL SYNC Capture Range|(Note 16)|l|225||1100|kHz|
|VTH,SYNC|SYNC Input Threshold|VSYNCRising (Note 15)|||1.5||V|
|||VSYNCFalling(Note 15)|||1||V|
|VOL,SYNC|SYNC Low Output|ISYNC= 3mA|l||0.3|0.4|V|
||Voltage|||||||
|ISYNC|SYNC Leakage Current in|0V ≤ VSYNC≤ 3.6V|l|||±5|µA|
||Frequency Slave Mode|MFR_CONFIG_ALL[4]=1b||||||
|θSYNC-θ0|SYNC-to-Channel 0|(Note 15)||||||
||Phase Relationship, Lag|MFR_PWM_CONFIG[2:0] = 000b, 01Xb|||0||Deg|
||from Falling Edge of Sync|MFR_PWM_CONFIG[2:0] = 101b|||60||Deg|
||to Rising Edge of Top|MFR_PWM_CONFIG[2:0] = 001b|||90||Deg|
||MOSFET(MT0)Gate|MFR_PWM_CONFIG[2:0]= 1X0b|||120||Deg|
|θSYNC-θ1|SYNC-to-Channel 1|(Note 15)||||||
||Phase Relationship, Lag|MFR_PWM_CONFIG[2:0] = 011b|||120||Deg|
||from Falling Edge of Sync|MFR_PWM_CONFIG[2:0] = 000b|||180||Deg|
||to Rising Edge of Top|MFR_PWM_CONFIG[2:0] = 010b, 10Xb|||240||Deg|
||MOSFET (MT1) Gate|MFR_PWM_CONFIG[2:0] = 001b|||270||Deg|
|||MFR_PWM_CONFIG[2:0]= 110b|||300||Deg|
Rev. D
8
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LTM4675
## **ELECTRICAL CHARACTERISTICS**
**The** l **denotes the specifications which apply over the specified internal operating temperature range (Note 2). Specified as each individual output channel (Note 4). TA = 25°C, VIN = 12V, RUN** _**n**_ **= 5V, FREQUENCY_SWITCH = 500kHz and VOUT** _**n**_ **commanded to 1.000V unless otherwise noted. Configured with factory-default EEPROM settings and per Test Circuit 1, unless otherwise noted.**
|**SYMBOL**|**PARAMETER**|**CONDITIONS**|**CONDITIONS**|**MIN**<br>**TYP**<br>**MAX**|**UNITS**|
|---|---|---|---|---|---|
|**EEPROM Characteristics**||||||
|Endurance|(Note 13)|0°C ≤ TJ≤ 85°C During EEPROM Write Operations(Note 3)|l|10,000|Cycles|
|Retention|(Note 13)|TJ< TJ(MAX), with Most Recent EEPROM Write Operation Having<br>Occurred at 0°C ≤ TJ≤ 85°C(Note 3)|l|10|Years|
|Mass_Write|Mass Write Operation<br>Time|Execution of STORE_USER_ALL Command, 0°C ≤ TJ≤ 85°C<br>(ATE-Tested at TJ= 25°C) (Notes 3, 13)||440<br>4100|ms|
|**Digital I/Os**||||||
|VIH|Input High Threshold<br>Voltage|SCL, SDA, RUN_n_,GPIO_n_(Note 15)<br>SHARE_CLK, WP(Note 15)||1.35<br>1.8|V<br>V|
|VIL|Input Low Threshold<br>Voltage|SCL, SDA, RUN_n_,GPIO_n_(Note 15)<br>SHARE_CLK, WP(Note 15)||0.8<br>0.6|V<br>V|
|VHYST|Input Hysteresis|SCL, SDA(Note 15)||80|mV|
|VOL|Output Low Voltage|SCL, SDA,ALERT, RUN_n_,GPIO_n_, SHARE_CLK:<br>ISINK= 3mA|l|0.3<br>0.4|V|
|IOL|Input Leakage Current|SDA, SCL,ALERT, RUN_n_: 0V ≤ VPIN≤ 5.5V<br>GPIO_n_and SHARE_CLK: 0V ≤ VPIN≤ 3.6V|l<br>l|<br>±5<br>±2|µA<br>µA|
|tFILTER|Input Digital Filtering|RUN_n_(Note 15)<br>GPIO_n_ (Note 15)||10<br>3|µs<br>µs|
|CPIN|Input Capacitance|SCL, SDA, RUN_n_,GPIO_n_, SHARE_CLK, WP(Note 15)||10|pF|
|**PMBus Interface Timing Characteristics**||||||
|fSMB|Serial Bus Operating<br>Frequency|(Note 15)||10<br>400|kHz|
|tBUF|Bus Free Time Between<br>Stop and Start|(Note 15)||1.3|μs|
|tHD,STA|Hold Time After Repeated<br>Start Condition|Time Period After Which First Clock Is Generated (Note 15)||0.6|µs|
|tSU,STA|Repeated Start Condition<br>Setup Time|(Note 15)||0.6|μs|
|tSU,STO|Stop Condition Setup<br>Time|(Note 15)||0.6|μs|
|tHD,DAT|Data Hold Time|Receiving Data (Note 15)<br>Transmitting Data(Note 15)||0<br>0.3<br>0.9|µs<br>µs|
|tSU,DAT|Data Setup Time|Receiving Data(Note 15)||0.1|μs|
|tTIMEOUT_SMB|Stuck PMBus Timer<br>Timeout|Measured from the Last PMBus Start Event:<br>Block Reads, MFR_CONFIG_ALL[3]=0b(Note 15)<br>Non-Block Reads, MFR_CONFIG_ALL[3]=0b(Note 15)<br>MFR_CONFIG_ALL[3]=1b (Note 15)||150<br>32<br>250|ms<br>ms<br>ms|
|tLOW|Serial Clock Low Period|(Note 15)||1.3<br>10000|μs|
|tHIGH|Serial Clock High Period|(Note 15)||0.6|μs|
Rev. D
9
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LTM4675
## **ELECTRICAL CHARACTERISTICS**
**Note 1:** Stresses beyond those listing under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating conditions for extended periods may affect device reliability and lifetime.
**Note 2:** The LTM4675 is tested under pulsed-load conditions such that TJ ≈ TA. The LTM4675E is guaranteed to meet performance specifications over the 0°C to 125°C internal operating temperature range. Specifications over the –40°C to 125°C internal operating temperature range are assured by design, characterization and correlation with statistical process controls. The LTM4675I is guaranteed to meet specifications over the full –40°C to 125°C internal operating temperature range. Note that the maximum ambient temperature consistent with these specifications is determined by specific operating conditions in conjunction with board layout, the rated package thermal resistance and other environmental factors.
**Note 3:** The LTM4675’s EEPROM temperature range for valid write commands is 0°C to 85°C. To achieve guaranteed EEPROM data retention, execution of the “STORE_USER_ALL” command—i.e., uploading RAM contents to NVM—outside this temperature range is not recommended. However, as long as the LTM4675’s EEPROM temperature is less than 130°C, the LTM4675 _will_ obey the STORE_USER_ALL command. Only when EEPROM temperature exceeds 130°C, the LTM4675 will not act on any STORE_USER_ALL transactions: instead, the LTM4675 NACKs the serial command and asserts its relevant CML (communications, memory, logic) fault bits. EEPROM temperature can be queried prior to commanding STORE_USER_ALL; see the Applications Information section.
**Note 4:** The two power inputs—VIN0 and VIN1—and their respective power outputs—VOUT0 and VOUT1—are tested independently in production. A shorthand notation is used in this document that allows these parameters to be referred to by “VIN _n_ ” and “VOUT _n_ ”, where _n_ is permitted to take on a value of 0 or 1. This italicized, subscripted “ _n_ ” notation and convention is extended to encompass all such pin names, as well as register names with channel-specific, i.e., paged data. For example, VOUT_COMMAND _n_ refers to the VOUT_COMMAND command code data located in Pages 0 and 1, which in turn relate to Channels 0 (VOUT0) and Channel 1 (VOUT1). Registers containing non-page-specific data, i.e., whose data is “global” to the module or applies to both of the module's Channels lack the italicized, subscripted “ _n_ ”, e.g., FREQUENCY_SWITCH.
**Note 5:** VOUT _n_ (DC) and line and load regulation tests are performed in production with digital servo disengaged (MFR_PWM_MODE _n_ [6] = 0b) and low VOUT _n_ range selected (MFR_PWM_MODE _n_ [1]) = 1b. The digital servo control loop is exercised in production (setting MFR_PWM_ MODE _n_ [6] = 1b), but convergence of the output voltage to its final settling value is not necessarily observed in final test—due to potentially long time constants involved—and is instead guaranteed by the output voltage readback accuracy specification. Evaluation in application demonstrates capability; see the Typical Performance Characteristics section.
**Note 6:** See output current derating curves for different VIN, VOUT, and TA, located in the Applications Information section.
**Note 7:** Even though VOUT0 and VOUT1 are specified for 6V absolute maximum, the maximum recommended regulation-command voltage is: 5.5V for a high-VOUT range setting of MFR_PWM_MODE _n_ [1]=0b; 2.5V for a low-VOUT range setting of MFR_PWM_MODE _n_ [1]=1b.
**Note 8:** Minimum on-time is tested at wafer sort.
**Note 9:** Data conversion is performed in round-robin (cyclic) fashion. All telemetry signals are continuously digitized, and reported data is based on measurements not older than 90ms, typical. Some telemetry parameters can be digitized at a faster update rate by configuring MFR_ ADC_CONTROL.
**Note 10:** The following telemetry parameters are formatted in PMBusdefined “Linear Data Format”, in which each register contains a word comprised of 5 most significant bits—representing a signed exponent, to be raised to the power of 2—and 11 least significant bits—representing a signed mantissa: input voltage (on SVIN), accessed via the READ_VIN command code; output currents (IOUT _n_ ), accessed via the READ_IOUT _n_ command codes; module input current (IVIN0 + IVIN1 + ISVIN), accessed via the READ_IIN command code; channel input currents (IVIN _n_ + 1/2 • ISVIN), accessed via the MFR_READ_IIN _n_ command codes;and duty cycles of channel 0 and channel 1 switching power stages, accessed via the READ_DUTY_CYCLE _n_ command codes. This data format limits the resolution of telemetry readback data to 10 bits even though the internal ADC is 16 bits and the LTM4675’s internal calculations use 32-bit words. **Note 11:** The absolute maximum rating for the SVIN pin is 20V. Input voltage telemetry (READ_VIN) is obtained by digitizing a voltage scaled down from the SVIN pin.
**Note 12:** These typical parameters are based on bench measurements and are not production tested.
**Note 13:** EEPROM endurance and retention are guaranteed by wafer-level testing for data retention. The minimum retention specification applies for devices whose EEPROM has been cycled less than the minimum endurance specification, and whose EEPROM data was written to at 0°C ≤ TJ ≤ 85°C. Downloading NVM contents to RAM by executing the RESTORE_USER_ALL or MFR_RESET commands is valid over the entire operating temperature range and does not influence EEPROM characteristics.
**Note 14:** Channel 0 OV/UV comparator threshold accuracy for MFR_PWM_MODE0[1] = 1b tested in ATE at VVOSNS0[+ ] – VVOSNS0[–] = 0.5V and 2.7V. 1V condition tested at IC-Level, only. Channel 1 OV/UV comparator threshold accuracy for MFR_PWM_MODE1[1] = 1b tested in ATE with VVOSNS1-VSGND = 0.5V and 2.7V. 1.5V condition tested at IC-level, only.
**Note 15:** Tested at IC-level ATE.
**Note 16:** PLL SYNC capture range tested with FREQUENCY_SWITCH set to frequency slave mode (0x0000), with MFR_CONFIG_ALL[4] = 1b, and with SYNC driven by external clock. Low end of SYNC capture range (225kHz) verified at VIN = 5.75V and VOUT _n_ = 2.5V. High end of SYNC capture range (1.1MHz) verified at VIN = 12V and VOUT _n_ = 3.3V.
Rev. D
10
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LTM4675
## **TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, 12VIN to 1VOUT, unless otherwise noted.**
**==> picture [524 x 603] intentionally omitted <==**
**----- Start of picture text -----**<br>
Efficiency vs Load Current at 5VIN Efficiency vs Load Current at 8VIN Efficiency vs Load Current at 12VIN<br>100 100 100<br>95 a 95 95<br>9085 ert)aseresee ey o 9085 l]| p(becpspeeeedSSSeer || 9085 LOCoccer]| a<br>5.0VOUT, 1MHz<br>80 2.5V 3.3V OUTOUT , 650kHz , 650kHz 80 3.3V2.5VOUTOUT, 1MHz, 1MHz 80 5.0VOUT, 1MHz3.3VOUT, 1MHz<br>75 1.8VOUT, 650kHz 75 1.8V OUT , 750kHz 75 2.5VOUT, 1MHz<br>70 for 1.5V1.2V1.0V0.9VOUTOUTOUTOUT, 575kHz, 500kHz, 500kHz, 425kHz 70 fo= 1.5V 1.2V 1.0V0.9VOUT OUT OUTOUT, 650kHz , 575kHz , 500kHz, 525kHz 70 ey = 1.8VOUT, 750kHz1.5V 1.2VOUT, 575kHz 1.0VOUT, 500kHz0.9VOUT, 525kHzOUT, 650kHz<br>65 65 65<br>0 2 4 6 8 10 12 14 16 18 0 2 4 6 8 10 12 14 16 18 0 2 4 6 8 10 12 14 16 18<br>OUTPUT CURRENT (A) OUTPUT CURRENT (A) OUTPUT CURRENT (A)<br>4675 G01 4675 G02 4675 G03<br>Single Phase Single Output<br>Pulse-Skipping (Discontinuous)<br>Mode Efficiency,<br>VIN = SVIN = VIN n , INTVCC Open, Dual Phase Single Output Load Single Phase Single Output Load<br>MFR_PWM_MODE n [0] = 0b Transient Response,12VIN to 1VOUT Transient Response,12VIN to 1VOUT<br>90<br>80 PF} ] | LP ett 20mV/DIVVOUT eeeeee 50mV/DIV [ee] VOUT0 ee<br>AC-COUPLED shee penmaed mman AC-COUPLED Ho PPR<br>va [aa]<br>70<br>IOUT IOUT<br>10A/DIV 5A/DIV<br>60 PALE Per peep<br>50µs/DIV 4675 G05 40µs/DIV 4675 G06<br>FIGURE 27 CIRCUIT AT 12VIN, INTVCC PIN FIGURE 61 CIRCUIT AT 12VIN<br>ATE a<br>50 OPEN CIRCUIT AND VOUT_COMMAND n SET 0A TO 5A LOAD STEP AT 5A/µs<br>TO 1.000V. 8A TO 18A LOAD STEP AT 10A/µs<br>12VIN TO 1.5VOUT, 650kHz<br>40<br>0 1 2 3 4 5 6 7 8 9<br>OUTPUT CURRENT (A)<br>4675 G04<br>Dual Phase Single Output Load Dual Output Concurrent Rail Dual Output Start-Up/Shutdown<br>Transient Response, 5VIN to 1VOUT Start-Up/Shutdown with a Pre-Biased Load<br>VOUT VVOUT0OUT1, VOUT0500mV/DIV, VOUT1<br>20mV/DIV 500mV/DIV<br>AC-COUPLED<br>IOUT0 IDIODE<br>5A/DIV 1mA/DIV<br>IOUT<br>10A/DIV RUN0, RUN1 RUN0, RUN1<br>5V/DIV 5V/DIV<br>50µs/DIV 4675 G07 2ms/DIV 4675 G08 2ms/DIV 4675 G09<br>FIGURE 27 CIRCUIT AT 5VIN, FIGURE 61 CIRCUIT AT 12VIN, 112mΩ LOAD FIGURE 61 CIRCUIT AT 12VIN, 112mΩ LOAD ON<br>VOUT_COMMAND n SET TO 1.000V. ON VOUT0, NO LOAD ON VOUT1. VOUT0, 500Ω ON VOUT1. VOUT1 PRE-BIASED<br>8A TO 18A LOAD STEP AT 10A/µs TON_RISE0 = 3ms, TON_RISE1 = 5.297ms, THROUGH A DIODE. TON_RISE0 = 3ms,<br>TOFF_DELAY1 = 0ms, TOFF_DELAY0 = 2.43ms, TON_RISE1 = 5.297ms, TOFF_DELAY1 = 0ms,<br>TOFF_FALL1 = 5.328ms, TOFF_FALL0 = 3ms, TOFF_DELAY0 = 2.43ms, TOFF_FALL1 = 5.328ms,<br>ON_OFF_CONFIG n = 0x1E TOFF_FALL0 = 3ms, ON_OFF_CONFIG1 = 0x1F,<br>ON_OFF_CONFIG0 = 0x1E<br>EFFICIENCY (%) EFFICIENCY (%) EFFICIENCY (%)<br>EFFICIENCY (%)<br>**----- End of picture text -----**<br>
Rev. D
11
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LTM4675
## **TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, 12VIN to 1VOUT, unless otherwise noted.**
## **Single Phase Single Output Short-Circuit Protection at No Load**
**Single Phase Single Output ShortCircuit Protection at Full Load**
**==> picture [167 x 97] intentionally omitted <==**
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VOUT0<br>200mV/DIV<br>IIN0<br>1A/DIV<br>Kad<br>10µs/DIV 4675 G10<br>FIGURE 61 CIRCUIT AT 12VIN,<br>NO LOAD ON VOUT0 PRIOR TO APPLICATION<br>OF SHORT CIRCUIT<br>**----- End of picture text -----**<br>
**==> picture [167 x 97] intentionally omitted <==**
**----- Start of picture text -----**<br>
VOUT0<br>200mV/DIV<br>IIN0<br>1A/DIV<br>10µs/DIV 4675 G11<br>FIGURE 61 CIRCUIT AT 12VIN,<br>112mΩ LOAD ON VOUT0 PRIOR TO<br>APPLICATION OF SHORT CIRCUIT<br>**----- End of picture text -----**<br>
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READ_VOUT n (Output Voltage READ_TEMPERATURE_2<br>Readback) Error vs VOUT n READ_IOUT n (Output Current (Control IC Temperature Error) vs<br>IOUT n = No Load, RUN1- n = 0V Readback) Error vs IOUT n Junction Temperature, RUN n = 0V<br>30 300 1.0<br>SPECIFIED UPPER LIMIT SPECIFIED UPPER LIMIT 0.8<br>20 p y > 200 LEE 0.6 EE EH<br>10 e e 100 0.4 Pt | | ey<br>CHANNEL 0 0.2<br>0 cow CHANNEL 1 s ee= L 0 eeP ee 0 NT<br>CHANNEL 0 –0.2<br>–10 ew –100 fo –0.4 MIN AE<br>= So ie eee<br>–20 sf –200 Lee CHANNEL 1 –0.6 PEP Aee<br>SPECIFIED LOWER LIMIT<br>~ SPECIFIED LOWER LIMIT –0.8 Pt | | ey ty<br>–30 –300 –1.0 Pitt} Tet | i<br>0.5 1.5 2.5 3.5 4.5 5.5 0 3 6 9 –45 –25 –5 15 35 55 75 95 115<br>VOUT (V) IOUT (A) ACTUAL TEMPERATURE (°C)<br>4675 G12 4675 G13 4675 G14<br>MFR_READ_IIN n (Input Current<br>Readback) Error vs (IVIN n + ISVIN),<br>READ_VIN (Input Voltage MFR_PWM_MODE n [0]=1b,<br>Readback Telemetry) Error vs IOUT n Swept from 0A to 9A, One<br>SVIN, RUN n = 0V Channel at a Time, RUN1- n = 0V<br>400 160<br>SPECIFIED UPPER LIMIT ——E SPECIFIED UPPER LIMIT<br>120<br>200 80 — -<br>40 C HANNEL 0<br>0 ieee 0 Pay<br><T Le es<br>–40<br>CHANNEL 1<br>–200 wae –80 ES<br>Sa ff _<br>–120<br>SPECIFIED LOWER LIMIT SPECIFIED LOWER LIMIT<br>–400 a e : –160 a= —<br>4 8 12 16 20 0 0.2 0.4 0.6 0.8 1.0<br>SVIN (V) IIN n + ISVIN (A)<br>4675 G15 4675 G16<br>MEASUREMENT ERROR (mV) MEASUREMENT ERROR (mA) MEASUREMENT ERROR (°C)<br>MEASUREMENT ERROR (mV) MEASUREMENT ERROR (mA)<br>**----- End of picture text -----**<br>
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LTM4675
## **TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, 12VIN to 1VOUT, unless otherwise noted.**
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READ_IOUT of 26 LTM4675s READ_IOUT of 26 LTM4675s READ_IOUT of 26 LTM4675s<br>(DC2053) 12VIN, 1VOUT, (DC2053) 12VIN, 1VOUT, (DC2053) 12VIN, 1VOUT,<br>TJ = –40°C, IOUT n = 9A, System TJ = 25°C, IOUT n = 9A, System TJ = 125°C, IOUT n = 9A, System<br>Having Reached Thermally Having Reached Thermally Having Reached Thermally<br>Steady-State Condition, No Airflow Steady-State Condition, No Airflow Steady-State Condition, No Airflow<br>14 14 14<br>12 12 12<br>10 10 10<br>8 8 8<br>6 6 6<br>4 4 4<br>2 2 2<br>0 0 0<br>READ_IOUT CHANNEL READBACK (A) READ_IOUT CHANNEL READBACK (A) READ_IOUT CHANNEL READBACK (A)<br>4675 G17 4675 G18 4675 G19<br>NUMBER OF CHANNELS NUMBER OF CHANNELS NUMBER OF CHANNELS<br>9.00000 9.03125 9.06250 9.09375 9.12500 9.15625 9.18750 9.21875 9.25000 8.87500 8.90625 8.93750 8.96875 9.00000 9.03125 9.06250 9.09375 9.12500 8.81250 8.84375 8.87500 8.90625 8.93750 8.96875 9.00000 9.03125 9.06250<br>**----- End of picture text -----**<br>
## **PIN FUNCTIONS**
## **PACKAGE ROW AND COLUMN LABELING MAY VARY AMONG µModule PRODUCTS. REVIEW EACH PACKAGE LAYOUT CAREFULLY.**
**GND (A2-8, B2-7, C2, C4-8, D2, D5, E1, E9, F1, F8, G1, G8-9, H1, H8-9, J2, J8, K2, K5-8, L2-7, M2-8):** Power Ground of the LTM4675. Power return for VOUT0 and VOUT1.
**VOUT0 (A1, B1, C1, D1):** Channel 0 Output Voltage.
**VOSNS0[+] (D7):** Channel 0 Positive Differential Voltage Sense Input. Together, VOSNS0[+] and VOSNS0[–] serve to kelvin-sense the VOUT0 output voltage at VOUT0’s point of load (POL) and provide the differential feedback signal directly to Channel 0’s control loop and voltage supervisor circuits. VOUT0 can regulate up to 5.5V output. Command VOUT0’s target regulation voltage by serial bus. Its initial command value at SVIN power-up is dictated by NVM (non-volatile memory) contents (factory default: 1.000V)—or, optionally, may be set by configuration resistors; see VOUT0CFG, VTRIM0CFG and the Applications Information section.
**VOSNS0[–] (E7):** Channel 0 Negative Differential Voltage Sense Input. See VOSNS0[+] .
**VORB0[+] (D8):** Channel 0 Positive Readback Pin. Shorted to VOSNS0[+] internal to the LTM4675. If desired, place a test point on this node and measure its impedance to VOUT0 on one’s hardware (e.g., motherboard, during in circuit test (ICT) post-assembly process) to provide a means of verifying the integrity of the feedback signal connection between VOSNS0[+] and VOUT0.
**VORB0[–] (E8):** Channel 0 Negative Readback Pin. Shorted to VOSNS0[–] internal to the LTM4675. If desired, place a test point on this node and measure its impedance to GND on one’s hardware (e.g., motherboard, during ICT post-assembly process) to provide a means of verifying the integrity of the feedback signal connection between VOSNS0[–] and GND (VOUT0 power return).
**VOUT1 (J1, K1, L1, M1):** Channel 1 Output Voltage.
**VOSNS1 (H7):** Channel 1 Positive Voltage Sense Input. Connect VOSNS1 to VOUT1 at the POL. This provides the feedback signal for Channel 1’s control loop and voltage supervisor circuits. VOUT1 can regulate up to 5.5V output. Command VOUT1’s target regulation voltage by serial bus. Its initial command value at SVIN power-up is dictated by
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LTM4675
## **PIN FUNCTIONS**
NVM (non-volatile memory) contents (factory default: 1.000V)—or, optionally, may be set by configuration resistors; see VOUT1CFG, VTRIM1CFG and the Applications Information section.
**SGND (F5-6, G5-6):** Channel 1 Negative Voltage Sense Input. See VOSNS1. Additionally, SGND is the signal ground return path of the LTM4675. If desired, one may place a test point on one of the four SGND pins and measure its impedance to GND on one’s hardware (e.g., motherboard, during ICT post-assembly process) to provide a means of verifying the integrity of the feedback signal connection between the other three SGND pins and GND (VOUT1 power return). SGND is not electrically connected to GND internal to the LTM4675. Connect SGND to GND local to the LTM4675.
**VORB1 (J7):** Channel 1 Positive Readback Pin. Shorted to VOSNS1 internal to the LTM4675. At one’s option, place a test point on this node and measure its impedance to VOUT1 on one’s hardware (e.g., motherboard, during ICT post-assembly process) to provide a means of verifying the integrity of the feedback signal connection between VOUT1 and VOSNS1.
**VIN0 (A9, B9, C9, D9):** Positive Power Input to Channel 0 Switching Stage. Provide sufficient decoupling capacitance in the form of multilayer ceramic capacitors (MLCCs) and low ESR electrolytic (or equivalent) to handle reflected input current ripple from the step-down switching stage. MLCCs should be placed as close to the LTM4675 as physically possible. See Layout Recommendations in the Applications Information section.
**VIN1 (J9, K9, L9, M9):** Positive Power Input to Channel 1 Switching Stage. Provide sufficient decoupling capacitance in the form of MLCCs and low ESR electrolytic (or equivalent) to handle reflected input current ripple from the step-down switching stage. MLCCs should be placed as close to the LTM4675 as physically possible. See Layout Recommendations in the Applications Information section.
**SW0 (B8):** Switching Node of Channel 0 Step-Down Converter Stage. Used for test purposes or EMI-snubbing. May be routed a short distance to a local test point to monitor switching action of Channel 0, if desired, but do not route near any sensitive signals; otherwise, leave electrically isolated (open).
**SW1 (L8):** Switching Node of Channel 1 Step-Down Converter Stage. Used for test purposes or EMI-snubbing. May be routed a short distance to a local test point to monitor switching action of Channel 1, if desired, but do not route near any sensitive signals; otherwise, leave open.
**SVIN (F9):** Input Supply for LTM4675’s Internal Control IC. In most applications, SVIN connects to VIN0 and/or VIN1, in which case no external decoupling beyond that already allocated for VIN0/VIN1 is required. If SVIN is operated from an auxiliary supply separate from VIN0/VIN1, decouple this pin to GND with a capacitor (0.1μF to 1μF).
**INTVCC (F7, G7):** Internal Regulator, 5V Output. When operating the LTM4675 from 5.75V ≤ SVIN ≤ 17V, an LDO generates INTVCC from SVIN to bias internal control circuits and the MOSFET drivers of the LTM4675. No external decoupling is required. INTVCC is regulated regardless of the RUN _n_ pin state. When operating the LTM4675 with 4.5V ≤ SVIN < 5.75V, INTVCC _must_ be electrically shorted to SVIN.
**VDD33 (J5):** Internally Generated 3.3V Power Supply Output Pin. This pin should only be used to provide external current for the pull-up resistors required for GPIO _n_ , SHARE_CLK, and SYNC, and may be used to provide external current for pull-up resistors on RUN _n_ , SDA, SCL and ALERT. No external decoupling is required.
**VDD25 (J4):** Internally Generated 2.5V Power Supply Output Pin. Do not load this pin with external current; it is used strictly to bias internal logic and provides current for the internal pull-up resistors connected to the configurationprogramming pins. No external decoupling is required.
**ASEL (G2):** Serial Bus Address Configuration Pin. On any given I[2] C/SMBus serial bus segment, every device must have its own unique slave address. If this pin is left open, the LTM4675 powers up to a slave address set by MFR_ADDRESS[6:0] (see Table 5). The factorydefault setting is 0x4F (hexadecimal), i.e., 1001111b (industry standard convention is used throughout this document: 7-bit slave addressing). The lower four bits of the LTM4675’s slave address can be altered from the NVM-set value by connecting a resistor from this pin to SGND. Minimize capacitance—especially when the pin is left open—to assure accurate detection of the pin state.
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LTM4675
## **PIN FUNCTIONS**
**FSWPHCFG (H2):** Switching Frequency, Channel PhaseInterleaving Angle and Phase Relationship to SYNC Configuration Pin. If this pin is left open—or, if the LTM4675 is configured to ignore pin-strap (RCONFIG) resistors, i.e., MFR_CONFIG_ALL[6] = 1b—then the LTM4675’s switching frequency (FREQUENCY_SWITCH) and channel phase relationships (with respect to the SYNC clock; MFR_PWM_CONFIG[2:0]) are dictated at SVIN powerup according to the LTM4675’s NVM contents. Default factory values are: 500kHz operation; Channel 0 at 0°; and Channel 1 at 180°C (convention throughout this document: a phase angle of 0° means the channel’s switch node rises coincident with the falling edge of the SYNC pulse). Connecting a resistor from this pin to SGND (and using the factory-default NVM setting of MFR_CONFIG_ALL[6] = 0b) allows a convenient way to configure multiple LTM4675s with identical NVM contents for different switching frequencies of operation and phase interleaving angle settings of intra- and extra-module-paralleled channels—all, without GUI intervention or the need to “custom pre-program” module NVM contents. (See the Applications Information section.) Minimize capacitance—especially when the pin is left open—to assure accurate detection of the pin state.
**VOUT0CFG (G3):** Output Voltage Select Pin for VOUT0, Coarse Setting. If the VOUT0CFG and VTRIM0CFG pins are both left open—or, if the LTM4675 is configured to ignore pin-strap (RCONFIG) resistors, i.e., MFR_CONFIG_ALL[6] = 1b—then the LTM4675’s target VOUT0 output voltage setting (VOUT_COMMAND0) and associated powergood and OV/UV warning and fault thresholds are dictated at SVIN power-up according to the LTM4675’s NVM contents. A resistor* connected from this pin to SGND—in combination with resistor pin settings on VTRIM0CFG, and using the factory-default NVM setting of MFR_CONFIG_ALL[6] = 0b—can be used to configure the LTM4675’s Channel 0 output to power-up to a VOUT_COMMAND value (and associated output voltage monitoring and protection/fault-detection thresholds) different from those of NVM contents. (See the Applications Information section.) Connecting resistor(s) from VOUT0CFG to SGND and/or VTRIM0CFG to SGND in this manner allows a convenient way to configure multiple LTM4675s with identical NVM contents for different output voltage settings—all without GUI intervention or the need to
“custom-pre-program” module NVM contents. Minimize capacitance—especially when the pin is left open—to assure accurate detection of the pin state. Note that use of RCONFIGs* on VOUT0CFG/VTRIM0CFG can affect the VOUT0 range setting (MFR_PWM_MODE0[1]) and loop gain.
**VTRIM0CFG (H3):** Output Voltage Select Pin for VOUT0, Fine Setting. Works in combination with VOUT0CFG to affect the VOUT_COMMAND (and associated output voltage monitoring and protection/fault-detection thresholds) of Channel 0, at SVIN power-up. (See VOUT0CFG and the Applications Information section.) Minimize capacitance— especially when the pin is left open—to assure accurate detection of the pin state. Note that use of RCONFIGs* on VOUT0CFG/VTRIM0CFG can affect the VOUT0 range setting (MFR_PWM_MODE0[1]) and loop gain.
**VOUT1CFG (G4):** Output Voltage Select Pin for VOUT1, Coarse Setting. If the VOUT1CFG and VTRIM1CFG pins are both left open—or, if the LTM4675 is configured to ignore pin-strap (RCONFIG) resistors, i.e., MFR_CONFIG_ALL[6] = 1b—then the LTM4675’s target VOUT1 output voltage setting (VOUT_COMMAND1) and associated OV/UV warning and fault thresholds are dictated at SVIN power-up according to the LTM4675’s NVM contents, in precisely the same fashion that the VOUT0CFG and VTRIM0CFG pins affect the respective settings of VOUT0 /Channel 0. (See VOUT0CFG, VTRIM0CFG and the Applications Information section.) Minimize capacitance—especially when the pin is left open—to assure accurate detection of the pin state. Note that use of RCONFIGs* on VOUT1CFG/VTRIM1CFG can affect the VOUT1 range setting (MFR_PWM_MODE1[1]) and loop gain.
**VTRIM1CFG (H4):** Output Voltage Select Pin for VOUT1, Fine Setting. Works in combination with VOUT1CFG to affect the VOUT_COMMAND (and associated output voltage monitoring and protection/fault-detection thresholds) of Channel 1, at SVIN power-up. (See VOUT1CFG and the Applications Information section.) Minimize capacitance— especially when the pin is left open—to assure accurate detection of the pin state. Note that use of RCONFIGs* on VOUT1CFG/VTRIM1CFG can affect the VOUT1 range setting (MFR_PWM_MODE1[1]) and loop gain.
> *In applications where VOUT0 and VOUT1 are paralleled, the respective VOUT _n_ CFG and VTRIM _n_ CFG pin-pairs can be electrically connected together; common RCONFIG resistors can be applied, whose values are half of what is prescribed in Table 2 and Table 3. See Figure 34, for example.
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LTM4675
## **PIN FUNCTIONS**
**SYNC (E5):** PWM Clock Synchronization Input and OpenDrain Output Pin. The setting of the FREQUENCY_SWITCH command dictates whether the LTM4675 is a “sync master” or “sync slave” module. When the LTM4675 is a sync master, FREQUENCY_SWITCH contains the commanded switching frequency of Channels 0 and 1—in PMBus linear data format—and it drives its SYNC pin low for 500ns at a time, at this commanded rate. In contrast, a sync slave uses MFR_CONFIG_ALL[4]=1b and does not pull its SYNC pin low. The LTM4675’s PLL synchronizes the LTM4675’s PWM clock to the waveform present on the SYNC pin—and therefore, a resistor pull-up to 3.3V is required in the application, regardless of whether the LTM4675 is a sync master or slave. EXCEPTION: driving the SYNC pin with an external clock is permissible; see the Applications Information section for details.
**SCL (E4):** Serial Bus Clock Open-Drain Input (Can Be an Input and Output, if Clock Stretching is Enabled). A pull-up resistor to 3.3V is required in the application for digital communication to the SMBus master(s) that nominally drive this clock. The LTM4675 will never encounter scenarios where it would need to engage clock stretching unless SCL communication speeds exceed 100kHz—and even then, LTM4675 will not clock stretch unless clock stretching is enabled by means of setting MFR_CONFIG_ALL[1] = 1b. The factory-default NVM configuration setting has MFR_CONFIG_ALL[1] = 0b: clock stretching disabled. If communication on the bus at clock speeds above 100kHz is required, the user’s SMBus master(s) need to implement clock stretching support to assure solid serial bus communications, and only then should MFR_CONFIG_ALL[1] be set to 1b. When clock stretching is enabled, SCL becomes a bidirectional, opendrain output pin on LTM4675.
**SDA (D4):** Serial Bus Data Open-Drain Input and Output. A pull-up resistor to 3.3V is required in the application.
**ALERT (E3):** Open-Drain Digital Output. A pull-up resistor to 3.3V is required in the application only if SMBALERT interrupt detection is implemented in one’s SMBus system.
**SHARE_CLK (H5):** Share Clock, Bidirectional OpenDrain Clock Sharing Pin. Nominally 100kHz. Used for synchronizing the time base between multiple LTM4675s (and any other ADI devices with a SHARE_CLK pin)—to realize well-defined rail sequencing and rail tracking. Tie the SHARE_CLK pins of all such devices together; all devices with a SHARE_CLK pin will synchronize to the fastest clock. A pull-up resistor to 3.3V is required when synchronizing the time base between multiple devices. If synchronizing the time base between multiple devices is not needed and MFR_CHAN_CONFIGn[2] = 0b, only then is a pull-up resistor not required.
**GPIO0, GPIO1 (E2 and F2, Respectively):** Digital, Programmable General Purpose Inputs and Outputs. Open-drain outputs and/or high impedance inputs. The LTM4675’s factory-default NVM configurations for MFR_GPIO_PROPAGATE _n_ —0x6893—and MFR_GPIO_ RESPONSE _n_ —0xC0—are such that: (1) when a channelspecific fault condition is detected—such as channel OT (overtemperature) or output UV/OV—the respective GPIO _n_ pin pulls logic low; (2) when a non-channel specific fault condition is detected—such as input OV or control IC OT—both GPIO _n_ pins pull logic low; (3) the LTM4675 ceases switching action on Channel 0 and 1 when its respective GPIO _n_ pin is logic low. Most significantly, this default configuration provides for graceful integration and inter-operation of LTM4675 with paralleled channel(s) of other LTM4675(s)—in terms of properly coordinating efforts in starting, ceasing, and resuming switching action and output voltage regulation, in unison—all without GUI intervention or the need to “custompreprogram” module NVM contents. Pull-up resistors from GPIO _n_ to 3.3V are required for proper operation in the vast majority of applications. (Only if the LTM4675’s MFR_GPIO_RESPONSE _n_ value were set to 0x00 might pull-ups be unnecessary. See the Applications Information section for details.)
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LTM4675
## **PIN FUNCTIONS**
**WP (K4):** Write Protect Pin, Active High. An internal 10μA current source pulls this pin to VDD33. If WP is open circuit or logic high, only I[2] C writes to PAGE, OPERATION, CLEAR_FAULTS, MFR_CLEAR_PEAKS and MFR_EE_UNLOCK are supported. Additionally, individual faults can be cleared by writing 1b’s to bits of interest in registers prefixed with “STATUS”. If WP is low, I[2] C writes are unrestricted.
**RUN0, RUN1 (F3 and F4, Respectively):** Enable Run Input for Channels 0 and 1, Respectively. Open-drain input and output. Logic high on these pins enables the respective outputs of the LTM4675. These open-drain output pins hold the pin low until the LTM4675 is out of reset and SVIN is detected to exceed VIN_ON. A pull-up resistor to 3.3V is required in the application. Do not pull RUN logic high with a low impedance source.
**TSNS0 (C3 and D3):** Temperature Sensor Node for Channel 0. Pads C3 and D3 are connected to each other internal to the module. It is permissible to leave these pads electrically open circuit and to only solder these pins to mounting pads on the PC board for mechanical integrity purposes. However, it is acceptable to electrically connect C3 to D3 on the PC board.
**TSNS1a, TSNS1b (J3 and K3, Respectively):** Channel 1 Temperature Excitation/Measurement and Thermal Sensor Pins, Respectively. In most applications, connect TSNS1a to TSNS1b. This allows the LTM4675 to monitor the Power Stage Temperature of Channel 1. See the Applications Information section for information on how to use TSNS1a to monitor a temperature sensor external to the module, e.g., a PN junction on the die of a microprocessor.
**COMP0a, COMP1a (E6 and H6, Respectively):** Current Control Threshold and Error Amplifier Compensation Nodes for Channels 0 and 1, Respectively. The trip threshold of each channel’s current comparator increases with a respective rise in COMP _n_ a voltage. Small filter capacitors (22pF) internal to the LTM4675 on these COMP pins (terminated to SGND) introduce high frequency roll off of the error-amplifier response, yielding good noise rejection in the control loop. See COMP0b/COMP1b.
**COMP0b, COMP1b (D6 and J6, Respectively):** Internal Loop Compensation Networks for Channels 0 and 1, Respectively. For the vast majority of applications, the internal, default loop compensation of the LTM4675 is suitable to apply “as is”, and yields very satisfactory results: apply the default loop compensation to the control loops of Channels 0 and 1 by simply connecting COMP0a to COMP0b and COMP1a to COMP1b, respectively. In contrast, when more specialized applications require a personal touch the optimization of control loop response, this can be easily accomplished by connecting (an) R-C network(s) from COMP0a and/or COMP1a—terminated to SGND—and leaving COMP0b and/or COMP1b open, as desired.
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LTM4675
## **SIMPLIFIED BLOCK DIAGRAM**
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VIN<br>5.75V TO 17V +<br>CINL CINH<br>VIN0 SVIN INTVCC VDD33 VIN1<br>1µF 1µF<br>VOUT0 VOUT1<br>ADJUSTABLE ADJUSTABLE<br>UP TO 5.5V SW0 MT0 POWER CONTROL MT1 SW1 UP TO 5.5V<br>UP TO 9A UP TO 9A<br>ANALOG SECTION<br>VOUT0 360nH 360nH VOUT1<br>+<br>COUT0HF COUT0LF GND 2.2µF THERMALSENSOR MB0 MB1 THERMALSENSOR 2.2µF GND COUT1LF COUT1HF<br>THERMAL TSNS1b<br>SENSOR<br>TSNS0 TSNS1a<br>VORB0 [+] VORB1 [[+]]<br>LOCAL VOSNS0 [+] ANALOG VOSNS1 [[+]] LOCAL<br>LOAD0 HIGHFREQ VOSNS0 [–] +–x1 TO ERRORAMPLIFIER READBACKSIGNALS SGND [VOSNS1 [–] ] FREQHIGH LOAD1<br>MLCCs MLCCs<br>VORB0 [–] CONTROLLER SIGNAL GND<br>COMP0a COMP1a<br>COMP0b INTERNAL INTERNAL COMP1b<br>COMP ADC COMP<br>SCL<br>SYNC 3.3V TOLERANT; PULL-UP<br>5V TOLERANT; PULL-UP SDA VDD25 RESISTOR NOT SHOWN<br>RESISTORS NOT SHOWN SPI<br>ALERT SLAVE<br>3.3V TOLERANT; PULL-UP WP ASEL<br>RESISTOR NOT NEEDED RUN0 POWER MANAGEMENTDIGITAL SECTION SPI SYNC FSWPHCFG<br>5V TOLERANT; PULL-UP MASTER DRIVER<br>RESISTORS NOT SHOWN RUN1 VOUT0CFG CONFIGURATION<br>GPIO0 ROM DIGITAL ENGINE VTRIM0CFG RESISTORS TERMINATINGTO SGND NOT SHOWN<br>OSC<br>3.3V TOLERANT; PULL-UP GPIO1 RAM EEPROM (32MHz) VOUT1CFG<br>RESISTORS NOT SHOWN SHARE_CLK VTRIM1CFG<br>4675 F01<br>+<br>**----- End of picture text -----**<br>
**Figure 1. Simplified LTM4675 Block Diagram**
## **DECOUPLING REQUIREMENTS TA = 25°C. Using Figure 1 configuration.**
|**SYMBOL**|**PARAMETER**|**CONDITIONS**|**MIN**<br>**TYP**<br>**MAX**|**UNITS**|
|---|---|---|---|---|
|CINH|External High Frequency Input Capacitor Requirement<br>(5.75V ≤ VIN≤ 17V, VOUT_n_Commanded to 1.000V)|IOUT0= 9A, 2×22μF, or 3×10μF<br>IOUT1= 9A, 2×22μF, or 3×10μF|30<br>44|µF|
|COUT_n_HF|External High Frequency Output Capacitor Requirement<br>(5.75V ≤ VIN≤ 17V, VOUT_n_Commanded to 1.000V)|IOUT0= 9A<br>IOUT1= 9A|400<br>400|µF<br>µF|
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LTM4675
## **FUNCTIONAL DIAGRAM**
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Rev. D<br>VOUT1 LOAD1 )1<br>ADJUSTABLE UP TO 5.5V UP TO 9A OUT1HF )1<br>C Telemetry: and1 LOCAL HIGH FREQ MLCCs<br>OUT1 Not Shown Not Shown<br>OUT1LF (V READ_VOUT<br>C MFR_VOUT_PEAK Telemetry: READ_POUT<br>(LOAD1 Power Consumption 3.3V Tolerant; Pull-Up Resistor Configuration Resistors Terminating to SGND<br>+ 4675 FD<br>1 ] 1a 1b<br>)1 SW VOUT1– GND TSNS1b TSNS1a ORB1[+]V OSNS1[+]V OSNS1– COMP COMP SYNC VDD25 ASEL FSWPHCFG VOUT0CFG VTRIM0CFG VOUT1CFG VTRIM1CFG<br>+ ZISNS1b– ISNS1b+Z ZISNS1a as Shown)1 SGND [V<br>: MFR_READ_IIN 1 )1 14.3k 6×<br>SVIN 1 )1 SNS1<br>) Voltage Feedback Signal READ_FREQUENCY)<br> + 1/2 • I OUT1<br>VIN1 Channel 1 Current Demand Signal<br>(Switching Frequency Telemetry:<br> Telemetry: READ_IOUT and MFR_IOUT_PEAK<br>Channel 1 (V<br>)1 OUT1<br>(I Channel 1 Internal Loop Compensation<br>Channel 1 Thermal Sensor<br>(Telemetry: READ_TEMPERATURE_1 and MFR_TEMPERATURE_1_PEAK Channel 1 Current Sense Signal, ∆I (Differential when Terminating SGND at LOAD SYNC DRIVER CONFIG DETECT<br>ZCOMP1b<br>(PWM1 Telemetry: READ_DUTY_CYCLE Controller Signal GND 1nF + 20kΩ<br>IN1 (Computed Channel 1 Input Current, I MT1 MB1 3 OSC (32MHz)<br>V<br>22pF SINC<br>DD33 SPI<br>V 30µA VTSNS SPI MASTER EEPROM<br>CC Other SLAVE<br>INTVIN TMUX 8:1 MUX DACs, OV/UV Comparators, RAM<br>SV INT FILTER POWER CONTROL ANALOG SECTION CURRENT MODE PWM CTRL. LOOPS, LIN. REGULATORS, DACs ADC, UV/OV COMPARATORS, VCO AND PLL, MOSFET DRIVERS AND POWER SWITCH LOGIC 2µA 16-BIT ADC ROM PROGRAM<br>IN0<br>V TO E/A 22pF<br>CINH )0 + – MT0 MB0 UVLO<br>R R<br>+ CINL : MFR_READ_IINSVIN : READ_IIN) + ISVINVIN1 (SV Telemetry: IN Telemetry: 0 )0 0 0 )0 Power Controller Thermal Sensor R + RA = 1 – ZCOMP0b 1nF + 20kΩ VDD33 10µA VDD33 COMPARE DIGITAL ENGINE, MAIN CONTROL POWER MANAGEMENT DIGITAL SECTION DIGITAL ENGINE, INCLUDING: ROM, RAM, NVM AND OSCILLATOR<br>VIN + 1/2 • I + IVINO (PWM )0 (Telemetry: READ_TEMPERATURE_2) ) Voltage Feedback SignalOUT0<br>READ_DUTY_CYCLE<br>VIN0<br>5.75V TO 17V READ_VIN and MFR_VIN_PEAK) VDD33<br>Channel 0 Thermal Sensor<br> Telemetry: READ_IOUT(IOUT0 and MFR_IOUT_PEAK (Telemetry: READ_TEMPERATURE_1 and MFR_TEMPERATURE_1_PEAK , Channel 0 Current Sense Signal∆ISNS0 , Differential Feedback Signal Channel 0 (V 2C-BASED SMBusI INTERFACE WITH PMBus COMMAND SET (10kHz TO 400kHz COMPATIBLE) CHANNEL TIMING MANAGEMENT<br>OSNS0<br>+ ∆V Channel 0 Internal Loop Compensation<br>(Computed Total Input Current, I – ZISNS0b– ISNS0b+Z ZISNS0a<br>0 0 Channel 0 Current Demand Signal 0a 0b 0 1 0 1<br>(Computed Channel 0 Input Current, I SW VOUT0 GND TSNS ORB0+V OSNS0+V VOSNS0– VORB0– COMP COMP SCL SDA ALERT WP RUN RUN GPIO GPIO SHARE_CLK<br>+ COUT0LF and0 )0 )0 Not Shown Not Needed Not Shown Not Shown<br> Telemetry:<br>COUT0HF (VOUT0 READ_VOUT MFR_VOUT_PEAK LOCAL HIGH FREQ MLCCs Power Consumption0 5V Tolerant; Pull-Up Resistors 3.3V Tolerant; Pull-Up Resistor 5V Tolerant; Pull-Up Resistors 3.3V Tolerant; Pull-Up Resistors<br>0 (LOAD Telemetry: READ_POUT<br>OUT0<br>V LOAD<br>ADJUSTABLE UP TO 5.5V UP TO 9A<br>PWM1<br>PWM0<br>÷39INSV<br>SNS1a∆I<br>SNS0a∆I<br>OSNS1V<br>OSNS0∆V<br>**----- End of picture text -----**<br>
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LTM4675
## **TEST CIRCUITS**
## **Test Circuit 1. LTM4675 ATE High VIN Operating Range Configuration, 5.75V ≤ VIN ≤ 17V**
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5.75V TO 17VVIN + C150µFINL C10µF×6INH V VSV IN0 IN1IN TSNSVOUT00 + COPT*OUTL0 C100µF×4OUTH0 1V ADJUSTABLEUP TO 9AVOUT0<br>VDD33<br>SCL<br>SMBus INTERFACE WITH<br>SDA<br>PMBus COMMAND SET<br>ALERTRUN0 VVOSNS0ORB0 [+][+] LOAD0<br>ON/OFF CONTROL,<br>FAULT MANAGEMENT AND RUN1 LTM4675 VOSNS0 [–]<br>POWER SEQUENCING GPIO0 VORB0 [–]<br>GPIO1 VORB1<br>PWM CLOCK SYNCH SYNC VOUT1<br>TIME BASE SYNCH SHARE_CLKWP TSNSTSNS1b1a + COPT*OUTL1 C100µFOUTH1 1V ADJUSTABLEUP TO 9AVOUT1<br>×4<br>(PULL-UP RESISTORS ON DIGITAL<br>I/O PINS NOT SHOWN)<br>VOSNS1 LOAD1<br>SGND<br>4675 TC01<br>RTH0 RTH1<br>30.1k 30.1k *COUTL0, COUTL1 NOT USED IN ATE TESTING<br>CTH0 CTH1<br>470pF 470pF<br>CC 0 1<br>DD25 SW SW<br>INTV V<br>0a 0b 1a 1b<br>P P<br>SWPHCFG OUT0CFG TRIM0CFG OUT1CFG TRIM1CFG<br>COM COMP COM COMP ASEL F V V V V GND<br>**----- End of picture text -----**<br>
## **Test Circuit 2. LTM4675 ATE Low VIN Operating Range Configuration, 4.5V ≤ VIN ≤ 5.75V**
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4.5V TO 5.75VVIN + C150µFINL C10µF×6INH V VSV IN0 IN1IN TSNSVOUT00 + COPT*OUTL0 C100µF×4OUTH0 1V ADJUSTABLEUP TO 9AVOUT0<br>VDD33<br>SCL<br>SMBus INTERFACE WITH<br>SDA<br>PMBus COMMAND SET<br>ALERT VORB0 [+]<br>RUN0 VOSNS0 [+] LOAD0<br>ON/OFF CONTROL,<br>FAULT MANAGEMENT AND RUN1 LTM4675 VOSNS0 [–]<br>POWER SEQUENCING GPIO0 VORB0 [–]<br>GPIO1 VORB1<br>PWM CLOCK SYNCH SYNC VOUT1<br>TIME BASE SYNCH SHARE_CLKWP TSNSTSNS1b1a + COPT*OUTL1 C100µFOUTH1 V1V ADJUSTABLEUP TO 9AOUT1<br>×4<br>(PULL-UP RESISTORS ON DIGITAL<br>I/O PINS NOT SHOWN)<br>VOSNS1 LOAD1<br>SGND<br>4675 TC02<br>RTH0 RTH1<br>30.1k 30.1k *COUTL0, COUTL1 NOT USED IN ATE TESTING<br>CTH0 CTH1<br>470pF 470pF<br>CC 0 1<br>DD25 SW SW<br>INTV V<br>0a 0b 1a 1b<br>P P<br>SWPHCFG OUT0CFG TRIM0CFG OUT1CFG TRIM1CFG<br>COM COMP COM COMP ASEL F V V V V GND<br>**----- End of picture text -----**<br>
Rev. D
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LTM4675
## **OPERATION**
## **POWER MODULE INTRODUCTION**
The LTM4675 is a highly configurable dual 9A output standalone nonisolated switching mode step-down DC/DC power supply with built-in EEPROM NVM (nonvolatile memory) with ECC and I[2] C-based PMBus/SMBus 2-wire serial communication interface capable of 400kHz SCL bus speed. Two output voltages can be regulated (VOUT0, VOUT1—collectively, VOUT _n_ ) with a few external input and output capacitors and pull-up resistors. Readback telemetry data of average input and output voltages and currents, Channel PWM duty cycles, and module temperatures are continually digitized cyclically by an integrated 16-bit ADC (analog-to-digital converter). Many fault thresholds and responses are customizable. Data can be autonomously saved to EEPROM when a fault occurs, and the resulting fault log can be retrieved over I[2] C at a later time, for analysis.
The LTM4675 provides precisely regulated output voltages between 0.6VDC to 5.5VDC (±0.5% above 1VDC, ±5mV below 1VDC). The target output voltage can be set according to pinstrapping resistors (VOUT _n_ CFG and VTRIM _n_ CFG pins), NVM/ register settings, and altered on the fly via the I[2] C interface. The output voltage can be modified by the user at any time with a write to PMBus VOUT_COMMAND. Executing this command has a typical latency less than 10ms. Writes to PMBus OPERATION have a typical latency less than 1ms. The NVM factory-default switching frequency is 500kHz and the phase-interleaving angle between its two channels is 180°. Channel switching frequency, phase angle, and phase relationship with respect to the falling edge of the SYNC pin waveform can be configured according to a pin-strap resistor (FSWPHCFG pin) and NVM/register settings—though, not on the fly during regulation. The 7-bit I[2] C slave address of the module defaults to the value retrieved from MFR_ADDRESS[6:0] at power-up (factory default: 0x4F), but the least significant four bits of the address are set by resistor pin-strapping the ASEL pin. Bits[6:4] of MFR_ADDRESS can be written and stored to EEPROM. Between the ASEL resistor pin-strap and user-configurable MFS_ADDRESS[6:4], the LTM4675 can take on any 7-bit slave address desired. With the exception of the ASEL pin, the module can be configured to ignore all pin-strap resistors, if desired (see MFR_CONFIG_ALL[6]).
Table 1 provides a summary of LTM4675’s supported PMBus commands. For details on the supported commands, payloads and data formats see Appendix C: PMBus Command Details.
For introductory information about the PMBus Specification, see Appendix A: Similarity Between PMBus, SMBus and I[2] C 2-Wire Interface. For information about the data communication link layer and timing diagrams, see Appendix B: PMBus Serial Digital Interface.
Major features of the LTM4675 strictly from a DC/DC converter power delivery point of view are as follows:
- n Up to 9A Output Current Delivery from Each of Two Integrated Power Stages (See Front Page Figure)— or Up to 18A Output, Combined (See Figure 27 and Figure 34).
- n Wide Input Voltage Range: DC/DC Step-Down Conversion from 5.75V to 17V Input (See Figure 61).
- n DC/DC Step-Down Conversion from 4.5V to 5.75V Input, Connecting SVIN to INTVCC (See Figure 27).
- n DC/DC Step-Down Conversion Possible from Less Than 4.5V Input When an Auxiliary 5V Bias Supply Powers SVIN and INTVCC (See Figure 29).
- n Output Voltage Range: 0.5V to 5.5V on both VOUT0 and VOUT1.
- n Differential Remote Sensing of VOUT0 (VOSNS0[+] / VOSNS0[–] ). For paralleled outputs, the VOSNS0[+] /VOSNS0[–] pin-pair can be configured as the feedback path for both VOUT0 and VOUT1 (see Figure 34 and, optionally, MFR_PWM_CONFIG[7]).
- n Start-Up Into a Pre-Biased Load Without Sinking Current.
- n Four LTM4675s Can Be Paralleled to Deliver Up to ~70A (See Figure 31).
- n One LTM4675 Can Be Paralleled with Three LTM4620A or LTM4630 Modules to Deliver Up to 122A; Infer Rail Status and Telemetry of Paralleled LTM4620A or LTM4630 via the Sole LTM4675 (See Figure 32).
- n Discontinuous Mode Operation Available for Higher Light-Load Efficiency (MFR_PWM_MODE _n_ [0]).
- n Output Current Limit and Overvoltage Protection.
- n Three Integrated Temperature Sensors, Over/Undertemperature Protection.
- n Constant Frequency Peak Current Mode Control.
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LTM4675
## **OPERATION**
- n Configurable Switching Frequency, 250kHz to 1MHz; Synchronizable to External Clock; Seven Configurable Channel Phase Interleaving Settings.
- n Internal Loop Compensation Provided; External Loop Compensation Can Be Applied, if Preferred.
- n Low Profile (16mm × 11.9mm × 3.51mm) BGA Package Power Solution Requires Only Input and Output Capacitors; at Most, Nine Pull-Up Resistors for OpenDrain Digital Signals; at Most, Six Pull-Down Resistors to Configure All Possible Pin-Strapping Options.
Features of the LTM4675 that enable power system management, rail sequencing, and fault monitoring and reporting are as follows:
- n I[2] C-based PMBus/SMBus 2-Wire Serial Communication Interface (SDA, SCL) with ALERT Interrupt Pin, SCL Clock Capable of 400kHz Bus Communication Speeds with Clock Low Extending—or 100kHz, Otherwise.
- n Configurable Output Voltage.
- n Configurable Input Undervoltage Comparators (UVLO Rising, UVLO Falling).
- n Configurable Switching Frequency.
- n Configurable Current Limit.
- n Configurable Output Over/Undervoltage Comparators.
- n Configurable Turn-On and Turn-Off Delay Times.
- n Configurable Output Ramp Rise and Fall Times.
- n Non-Volatile Configuration Memory (NVM EEPROM) with ECC to Configure Aforementioned Settings, and More—Yielding Standalone Operation, if Desired, and Also Enabling In-Situ Changes to the LTM4675’s Configuration in Embedded Designs.
- n Monitoring and Reporting of Telemetry Data: Average Output and Input Currents and Voltages, Internal Temperatures, and Power Stage Duty Cycles—Continuously Digitized Cyclically by a 16-Bit ADC.
- Peak Observed Output Current and Voltage, Input Voltage, and Module Temperatures Can Be Polled and Cleared/Reset.
- ADC Latency Not Greater Than 90ms, Nominal.
- Option to Monitor One External Temperature in Lieu of Channel 1 (VOUT1) Module Power Stage Temperature.
- n Monitoring, Reporting, and Configurable Response to Latching and Non-Latching Individual Fault and/or Warning Status, Including but Not Limited to:
- Output Over/Undervoltages.
- Input (SVIN) Over/Undervoltages.
- Module Input and Power Stage Output Overcurrents.
- Module Power Stage Over/Under Temperatures.
- Internal Control IC Overtemperature.
- Communication, Memory and Logic (CML) Faults.
- n Fault Logging Upon Detection of a Fault Condition. The LTM4675 Can Be Configured to Automatically Upload a Fault Log to Its NVM, Consisting of: an Uptime Counter, Peak Observed Telemetry, Telemetry Gathered from the Six Most Recent Rounds of Cyclical ADC Data Leading Up to the Detection of the Fault That Triggered Fault Log Writing, and Fault Status Associated with That ADC History.
- n Two Configurable Open-Drain General Purpose Input/ Output Pins (GPIO0, GPIO1), Which Can Be Used for:
- Fault Reporting, e.g., as a System Interrupt Signal.
- Coordinating Turn-On/Off of the LTM4675 in Multiphase/Multirail Systems.
- Propagating an Unfiltered Power Good Signal (Output of a VOUT _n_ Undervoltage Comparator) to Command Turn-On/Off of a Downstream Rail.
- n A Write Protect (WP) Pin and Configurable WRITE_ PROTECT Register to Protect the Internal Configuration of RAM and NVM Against Unintended Changes via I[2] C.
- n Time-Base Interconnect (SHARE_CLK, 100kHz Heartbeat) for Synchronization in the Time Domain Between Multiple LTM4675s.
- n Optional External Configuration Resistors (RCONFIGs) for Setting Start-Up Output Voltages, Switching Frequency and Channel-to-Channel Phase Interleaving Angle.
- n Any 7-Bit Slave Address Can Be Assigned to the LTM4675 (0x4F Default), Configured by Resistor Pin Strapping the ASEL Pin and User-Editable Bits [6:4] of MFR_ADDRESS.
Rev. D
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LTM4675
## **OPERATION**
## **POWER MODULE CONFIGURABILITY AND READBACK DATA**
This section of the data sheet describes all the configurable features and readable data of the LTM4675 accessible via I[2] C. The relevant command code name(s) are indicated by use of all capital letters, e.g., “VIN_ON”. Refer to Table 1 and Appendix C: PMBus Command Details of this data sheet for details of the command code, payload size, data format and factory-default value. Specific register bits of some registers are indicated with the use of brackets, i.e., “[” and “]”. The least significant bit (LSB) of a register is bit number zero, indicated by “[0]”. The most significant bit of a byte-long (8-bit-long) register is bit number seven, indicated by “[7]”. The most significant bit (MSB) of a word-long (16-bit-long) register is bit number fifteen, indicated by “[15]”. Multiple bits of a register can be alluded to with the use of a colon, e.g., bits 2, 1 and 0 of the MFR_PWM_CONFIG register are indicated by “MFR_PWM_CONFIG[2:0]”. Bits can take on values of 0b or 1b. The subscripted “b” suffix indicates the number’s value is in binary. Values in hexadecimal are indicated with a “0x” prefix. For example, decimal value “89” is indicated by 0x59 and 01011001b (8-bit-long values), as well as 0x0059 and 0000000001011001b (16-bit-long values).
One further shorthand notion the reader will notice is the italicized “ _n_ ” or “ _n_ ”. “ _n_ ” can take on a value of 0 or 1—and provides an easy way to refer to registers which are paged commands, i.e., register names which have the same command code value but can be configured independently (or yield channel-specific telemetry) for Channel 0 (Page 0, or 0x00) vs Channel 1 (Page 1, or 0x01). Registers lacking an “ _n_ ” are therefore easily identified as being global in nature, i.e., common to both Channels/Outputs. For example, the switching frequency setting commanded by register FREQUENCY_SWITCH is common to both channels, and lacks “ _n_ ”. Another example: the READ_VIN register contains the digitized input voltage as seen at the SVIN pin, and SVIN is unique, i.e., common to both Channels. In contrast, the nominal commanded output voltage is indicated by the register VOUT_COMMAND _n_ . The “ _n_ ” indicates that VOUT_COMMAND can be set differently for Channel 0 vs Channel 1. Executing the PAGE Command (Command Code 0x00) with payload 0x00 sets
the LTM4675 to write/read data pertaining to Channel 0 in all subsequent I[2] C transactions until the Page is changed. Executing the PAGE Command with payload 0x01 sets the LTM4675 to write/read data pertaining to Channel 1 in all subsequent I[2] C transactions until the Page is changed. Executing the PAGE Command with payload 0xFF sets the LTM4675 to write data pertaining to Channels 0 and 1 in all subsequent I[2] C write transactions until the Page is changed. Reads from and writes to global registers do not require setting the Page to 0xFF. Reads from channelspecific (i.e., non-global) registers when the Page is set to 0xFF result in the LTM4675 reporting the value on Page 0x00 (i.e., Channel 0-specific data).
The list below itemizes aspects of the LTM4675 relating to power supply functions that are configurable by I[2] C communications—provided the state of the WP (write protect) pin and the WRITE_PROTECT register value permit the I[2] C writes—and by EEPROM settings:
- n Output start-up voltages (VOUT_COMMAND _n_ ), the maximum commandable output voltages (VOUT_MAX _n_ ), output margin high (VOUT_MARGIN_HIGH _n_ ) and margin low (VOUT_MARGIN_LOW _n_ ) command voltages, and output over/undervoltage warning and fault thresholds (VOUT_OV_WARN_LIMIT _n_ , VOUT_OV_FAULT_LIMIT _n_ , VOUT_UV_WARN_LIMIT _n_ , and VOUT_UV_FAULT_ LIMIT _n_ ). Additionally, these values can be configured at SVIN power-up according to resistor-pin strapping of the VOUT0CFG, VTRIM0CFG, VOUT1CFG and/or VTRIM1CFG pins, provided MFR_CONFIG_ALL[6] = 0b.
- n Output voltages, on the fly, including transition rate (∆V/∆t), VOUT_TRANSITION_RATE _n_ —either by I[2] C writes to the VOUT_COMMAND _n_ , VOUT_MARGIN_ HIGH _n_ , or VOUT_MARGIN_LOW _n_ registers, and/or to the OPERATION _n_ register.
- n Input undervoltage-lockout, rising (VIN_ON) and input undervoltage lockout, falling (VIN_OFF), based on the SVIN pin voltage.
- n Switching frequency (FREQUENCY_SWITCH) and channel phase-interleaving angle (MFR_PWM_CONFIG[2:0]). However, these parameters can be changed via I[2] C communications only when the LTM4675’s channels are off, i.e., not switching. The LTM4675 synchronizes
Rev. D
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LTM4675
## **OPERATION**
its switching frequency to a clock signal supplied to its SYNC pin when MFR_CONFIG_ALL[4]=1b. These parameters can be configured at SVIN power-up according to resistor-pin strapping of the FSWPHCFG pin, provided MFR_CONFIG_ALL[6] = 0b.
- n Output voltage turn-on and turn-off sequencing and associated watchdog timers, namely:
- Output voltage turn-on delay time (the time delay from the LTM4675 being commanded to turn on, e.g., by the RUN _n_ pin toggling from logic low to high, before switching action commences. TON_DELAY _n_ ).
- Output voltage soft-start ramp-up time (TON_RISE _n_ ).
- The amount of time (TON_MAX_FAULT_LIMIT _n_ ) permitted to elapse after the LTM4675 is commanded to turn on, e.g., by the RUN _n_ pin toggling from logic low to high, after which, if the output voltage fails to exceed the output undervoltage fault threshold (VOUT_UV_FAULT_LIMIT _n_ ), the LTM4675’s output (VOUT _n_ ) is declared to have not come up in a timely manner.
- The LTM4675’s response to any such aforementioned TON_MAX_FAULT_LIMIT _n_ event (TON_MAX_FAULT_RESPONSE _n_ ).
- Output voltage soft-stop ramp-down time (TOFF_FALL _n_ ).
- Output voltage turn-off delay time (the time delay from the LTM4675 being commanded to turn off, e.g., by the RUN _n_ pin toggling from logic high to low, before switching action ceases. TOFF_DELAY _n_ ).
- When commanded to turn off its output—or, when turning off its output in response to a fault— configuring whether the LTM4675's output (VOUT _n_ ) becomes high impedance (“High-Z” or “three state”—turning off both MT _n_ and MB _n_ in the power stage). (“Immediate Off”, ON_OFF_CONFIG _n_ [0] = 1b vs configuring the output voltage to be ramped down according to TOFF_FALL _n_ and/or TOFF_DELAY _n_ settings, ON_OFF_CONFIG _n_ [0] = 0b).
- The amount of time (TOFF_MAX_WARN_LIMIT _n_ ) permitted to elapse after the LTM4675 is supposed to have turned off its output, i.e., at the end of the
period dictated by TOFF_FALL _n_ , after which, If the output voltage has not fallen below 12.5% of the former target voltage of regulation, the LTM4675’s output (VOUT _n_ ) is declared to have not powered down in a timely manner.
- n Configurable output voltage restart time. Subsequent to the RUN _n_ pin being pulled low, the LTM4675 pulls RUN _n_ logic low, itself, and the output cannot be restarted until a minimum time has elapsed—the restart delay time. This delay assures proper sequencing of all system rails. The minimum restart delay processed by the LTM4675 is the longer of (TOFF_DELAY _n_ + TOFF_FALL _n_ + 136ms) vs the commanded MFR_RESTART_DELAY _n_ register value. At the end of this delay, the LTM4675 releases its RUN _n_ pin.
- n Configurable fault-hiccup retry delay time. When a fault occurs in which the LTM4675’s fault response behavior to that fault is to reattempt power-up of its output voltage after said fault ceases to be present (e.g., “Infinite Retry”), the delay time for the LTM4675 to re-engage switching action is the longer of the MFR_RETRY_DELAY _n_ time vs the time required for the output to decay below 12.5% of the formerly commanded output voltage value (unless this lattermost criteria, i.e., requiring the output to decay below 12.5% is negated by the setting of MFR_CHAN_CONFIG _n_ [0] to “1b”—which is the LTM4675’s factory-NVM default setting).
- n Output over/undervoltage fault responses (VOUT_OV_ FAULT_RESPONSE _n_ , VOUT_UV_FAULT_RESPONSE _n_ ).
- n Time-averaged current limit warning and instantaneous peak (cycle-by-cycle) fault thresholds, and fault response (IOUT_OC_WARN_LIMIT _n_ , IOUT_OC_FAULT_LIMIT _n_ , IOUT_OC_FAULT_RESPONSE _n_ ).
- n Channel (VOUT0, VOUT1) overtemperature warning and fault thresholds, and fault response (OT_WARN_LIMIT _n_ , OT_FAULT_LIMIT _n_ , OT_FAULT_RESPONSE _n_ ).
- n Channel (VOUT0, VOUT1) undertemperature fault thresholds and fault response (UT_FAULT_LIMIT _n_ , UT_FAULT_RESPONSE _n_ ).
- n Input overvoltage fault threshold and response (VIN_OV_FAULT_LIMIT, VIN_OV_FAULT_RESPONSE), based on the SVIN pin voltage.
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LTM4675
## **OPERATION**
- n Input undervoltage warning threshold (VIN_UV_WARN_ LIMIT) based on the SVIN pin voltage.
- n Module input overcurrent warning threshold (IIN_OC_WARN_LIMIT)
The control IC within the LTM4675 module ceases switching action if control IC temperature exceeds 160°C (Note 12). The control IC resumes operation after a 10°C cool-down hysteresis. Note that these typical parameters are based on measurements in a lab oven and are not production tested. This overtemperature protection is intended to protect the device during momentary overload conditions. The maximum rated junction temperature will be exceeded when this protection is active. Continuous operation above the specified absolute maximum operating junction temperature may impair device reliability or permanently damage the device.
## **TIME-AVERAGED AND PEAK READBACK DATA**
Time-averaged telemetry readback data accessible via I[2] C communications follow:
- n Channel output current (READ_IOUT _n_ ) and peak observed value of READ_IOUT _n_ (MFR_IOUT_PEAK _n_ ).
- n Channel output voltage (READ_VOUT _n_ ) and peak observed value of READ_VOUT _n_ (MFR_VOUT_PEAK _n_ ).
- n Channel output power (READ_POUT _n_ ).
- n Channel input current (MFR_READ_IIN _n_ ) and module input current (READ_IIN).
- n Channel temperatures (READ_TEMPERATURE_1 _n_ ) and peak observed values of READ_TEMPERATURE_1 _n_ (MFR_TEMPERATURE_1_PEAK _n_ ).
- n Control IC temperature (READ_TEMPERATURE_2) and peak observed value (MFR_TEMPERATURE_2_PEAK).
- n Input voltage (READ_VIN), based on the voltage of the SVIN pin, and peak observed value of READ_VIN (MFR_VIN_PEAK).
Digitized cyclical telemetry is available at a 10Hz update rate, typical. Through the use of the MFR_ADC_CONTROL command, some signals of interest can be digitized more frequently—up to a 125Hz update rate, typical. Availability of newly digitized telemetry data can be made known via the MFR_ADC_TELEMETRY_STATUS command.
Peak observed values of telemetry readback data can be cleared with the MFR_CLEAR_PEAKS I[2] C command, provided the WRITE_PROTECT register value permits it. (Executing MFR_CLEAR_PEAKS can be performed regardless of the state of the WP pin.)
Details on the LTM4675’s Fault Log Feature follow:
- n Fault logging is enabled when MFR_CONFIG_ALL[7] = 1b.
- n A fault log is present in NVM when STATUS_MFR_ SPECIFIC _n_ [3]Reports “1b”, which is propagated to the MFR Bit (Bit 12) of the STATUS_WORD register.
- n Retrieving fault log data, if present, is performed with the MFR_FAULT_LOG command. 147 bytes of data are retrieved using the PMBus-defined variant to the SMBus block read protocol.
- n The fault log contents in NVM, if present, are cleared by executing the MFR_FAULT_LOG_CLEAR command.
- n The fault log will not be written if a fault log is already present in NVM.
- n The LTM4675 can be forced to write a fault log to its NVM by executing the MFR_FAULT_LOG_STORE command; the LTM4675 will behave as if a channel faulted off. Note the command is NACKed and a CML fault is reported if a fault log is already present at the time of executing MFR_FAULT_LOG_STORE.
When an external stimulus pulls the LTM4675’s GPIO _n_ pin(s) logic low, the respective channel (VOUT _n_ ) either: takes no action on it, i.e., ignores it completely— if MFR_GPIO_RESPONSE _n_ = 0x00; or, turns off immediately, i.e., the power stage(s) become high impedance (“inhibited”)— if MFR_GPIO_RESPONSE _n_ = 0xC0.
- n Channel topside power MOSFET (MT _n_ ) duty cycle (READ_DUTY_CYCLE _n_ )
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LTM4675
## **OPERATION**
The MFR_GPIO_PROPAGATE _n_ register contents configure which fault(s) cause the LTM4675 to pull its GPIO _n_ pin(s) logic low.
I[2] C communications are originated by the user’s (system’s) I[2] C master device. Writes/reads to/from Channel 0 of the LTM4675 (VOUT0: PAGE 0x00), to/from Channel 1 of the LTM4675 (VOUT1: PAGE 0x01), or writes to both Channels 0 and 1 of the LTM4675 (VOUT0 and VOUT1: PAGE 0xFF) are possible. The target channel(s) of interest are selected by the I[2] C master by executing the PAGE command and sending the appropriate argument (0x00, 0x01, 0xFF) in the payload. The PAGE command is unrestricted, i.e., not affected by the WP pin or WRITE_PROTECT register settings.
The LTM4675 always responds to its global slave addresses, 0x5A and 0x5B. Commands sent to the global address 0x5A act the same as if the PAGE command were set to 0xFF, i.e., received commands are written to both channels simultaneously. Commands sent to the global address 0x5B are applied to the PAGE active at the time of the global address transaction, i.e., allows channel-specific command of all LTM4675 devices on the bus.
I[2] C commands not listed above that relate to Fault Status and EEPROM NVM Operations follow. Writing of the following is possible provided the state of the WP (write protect) pin and the WRITE_PROTECT register value permits the I[2] C writes:
- n Soliciting (reading) module fault status and clearing (writing) module fault status (CLEAR_FAULTS, STATUS_ BYTE _n_ , STATUS_WORD _n_ , STATUS_VOUT _n_ , STATUS_ IOUT _n_ , STATUS_INPUT, STATUS_TEMPERATURE _n_ , STATUS_CML [communications, memory, and/or logic], and STATUS_MFR_SPECIFIC _n_ [miscellaneous]).
- n Storing the LTM4675’s user-writable RAM register data to the EEPROM NVM (STORE_USER_ALL).
- n An alternate means to the STORE_USER_ALL command to directly erase and write the LTM4675’s EEPROM contents, protected by unlock keys, to facilitate programming of the LTM4675 EEPROM in environments such as ICT (in-circuit test) and bulk programming by, e.g., embedded hardware or by the LTpowerPlay GUI. Also, a means to directly read the LTM4675 EEPROM contents (MFR_EE_UNLOCK, MFR_EE_ERASE, MFR_EE_DATA).
- n Instigating a soft reset of the LTM4675 without powercycling SVIN power (MFR_RESET). The MFR_RESET command triggers the download of EEPROM NVM data to RAM registers, as if SVIN power had been cycled.
- n Forcing a download of EEPROM NVM data to RAM registers (RESTORE_USER_ALL). This is indistinguishable from executing MFR_RESET.
Other data that can be obtained from the LTM4675 via I[2] C communications are as follows:
- n Soliciting the LTM4675 for its PMBus capabilities, as defined by PMBus (CAPABILITY):
- PEC (packet error checking). Note, the LTM4675 requires valid PEC in I[2] C communications when MFR_CONFIG_ALL[2] = 1b. The NVM factory-default configuration is MFR_CONFIG_ALL[2] = 0b, i.e., PEC not required.
- I[2] C communications can be supported at up to 400kHz SCL bus speed. Note, clock low extending (clock stretching) must be enabled on the LTM4675 to ensure robust communications above 100kHz SCL bus speeds, i.e., MFR_CONFIG_ALL[1] = 1b. The NVM factory-default configuration is MFR_CONFIG_ ALL[1] = 0b, i.e. Clock stretching is disabled.
- The LTM4675 has an SMBALERT (ALERT) pin and does support the SMBus ARA (alert response address) protocol.
- n Soliciting the module for the maximum output voltage it can be commanded to produce (MFR_VOUT_MAX _n_ ).
- n Soliciting the device for the data format of its output voltage-related registers (VOUT_MODE _n_ ).
- n Soliciting the device for the revisions of PMBus specifications that it supports (Part I: Rev. 1.2; Part II: Rev 1.2).
- n Soliciting the device for the identification of the manufacturer of the LTM4675, “LTC” (MFR_ID) and the manufacturer code representing the LTM4675 and revision, 0x47AX (MFR_SPECIAL_ID).
- n Soliciting the device for its part number, “LTM4675 ” (MFR_MODEL).*
- n Soliciting the module for its serial number (MFR_SERIAL).
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LTM4675
## **OPERATION**
- n The digital status of the LTM4675’s I/O pads and validity of the ADC (MFR_PADS) and WP pin status (MFR_COMMON[0]).
The following list indicates other aspects of the LTM4675 relating to power system management and power sequencing that are configurable by I[2] C communications— provided the state of the WP (write protect) pin and the WRITE_PROTECT register value permit the I[2] C writes—and by EEPROM settings:
- n Providing multiple means to read/write data directly to a particular channel of the LTM4675 by assigning additional slave address for channels 0 and 1 (MFR_ RAIL_ADDRESS _n_ ), the benefit of which is that it reduces page command usage and associated I[2] C traffic. It also facilitates altering the same register of multiple LTM4675 in unison without invoking the PMBus group command protocol. See also PAGE_PLUS_READ and PAGE_PLUS_WRITE.
- n Configuring the output voltage to be on or off by means other than the RUN _n_ pin (ON_OFF_CONFIG _n_ [3], OPERATION commands).
- n Configuring whether the LTM4675 performs a CLEAR_FAULTS command upon itself when either RUN _n_ pin toggles from logic low to logic high. (MFR_CONFIG_ALL[0]).
- n Configuring whether the LTM4675 pulls RUN _n_ logic low when the LTM4675 is commanded off by other means (MFR_CHAN_CONFIG _n_ [4]).
- n Configuring the response of the LTM4675 when it is commanded to turn on its output prior to the completion of processing TOFF_DELAY _n_ and TOFF_FALL _n_ powerdown sequencing (MFR_CHAN_CONFIG _n_ [3]).
- n Configuring whether the LTM4675’s output is disabled when SHARE_CLK is held low (MFR_CHAN_ CONFIG _n_ [2]).
- n Configuring whether the ALERT pin is pulled low when GPIO _n_ is pulled low by external stimulus (MFR_CHAN_ CONFIG _n_ [1]).
> * The MFR_MODEL value is “LTM4675 ". The value consists of 8 ASCII characters and the last character is a blank space punctuation character (" "), i.e., ASCII code 0x20 or 32d.
- n Setting the value of the MFR_IIN_OFFSET _n_ registers, representing an estimate of the current drawn by the SVIN pin. The SVIN pin current is not measured by the LTM4675 but the MFR_IIN_OFFSET _n_ is used in computing and reporting channel and total module input currents (MFR_READ_IIN _n_ , READ_IIN).
- n Three words (six bytes) of the LTM4675’s EEPROM that are available for storing user data. (USER_DATA_03 _n_ , USER_DATA_04).
- n Invoking or releasing several levels of I[2] C write protection (WRITE_PROTECT).
- n Configuring the bus timeout for 255ms (MFR_CONFIG_ ALL[3]=1b) if the host needs more time to complete I[2] C transactions.
- n Determining whether the user-editable RAM register values are identical to the contents of the user NVM (MFR_COMPARE_USER_ALL).
- n Setting the programmable output voltage range of VOUT to a narrower range (0.5V to 2.75V) in order to achieve a higher resolution of VOUT adjustment than is available by default (MFR_PWM_MODE _n_ [1]). MFR_PWM_MODE cannot be changed on the fly; switching action must be off. Note that altering the VOUT range alters the gain of the control loop and may therefore require loop compensation to be adjusted.
- n Altering the temperature coefficient of the LTM4675’s current sensing elements, if needed (MFR_IOUT_CAL_ GAIN_TC _n_ ) (uncommon to alter this parameter from its NVM-Factory default setting).
- n Altering the gain or offset of the power stage sensors (MFR_TEMP_1_GAIN _n_ and MFR_TEMP_1_OFFSET _n_ )— or that of the external temperature sensor, when an external temperature sensor is used on the TSNS1a pin. (Uncommon to alter this parameter from its NVMfactory default setting).
- n Configuring whether the LTM4675 Pulls SHARE_CLK logic low when SVIN has fallen outside Its UVLO thresholds (MFR_PWM_CONFIG[4]). MFR_PWM_ CONFIG cannot be changed on the fly; switching action must be off (uncommon to alter this parameter from its NVM-factory default setting).
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LTM4675
## **OPERATION**
- n Configuring whether the LTM4675’s output voltage digital servos are active vs disengaged (MFR_PWM_ MODE _n_ [6]. Uncommon to alter this parameter from its NVM-factory default settings).
- n Configuring whether the LTM4675’s current limit range is set to high range vs low range. (MFR_PWM_ MODE _n_ [7]. Not recommended to alter this parameter from its NVM-factory default settings).
Remaining LTM4675 status that can be queried over I[2] C communications follow:
- n Access to three “hand-shaking” status bits (MFR_COMMON[6:4]) to ease implementation of PMBus busy protocols, i.e., enabling fast and robust system level communication through polling of these bits to infer LTM4675’s readiness to act on subsequent I[2] C writes. (See PMBus communication and command processing, in the Applications Information section.)
- n Providing a means to determine whether the LTM4675 NVM download to RAM has occurred (“NVM Initialized,” MFR_COMMON[3]).
- n Providing a means other than ARA protocol to determine whether the LTM4675 is pulling ALERT low (MFR_COMMON[7]).
- n Detecting a SHARE_CLK timeout event (MFR_COMMON[1]).
- n Verifying or Altering the Slave Address of the LTM4675 (MFR_ADDRESS).
## **POWER MODULE OVERVIEW**
A dedicated remote-sense amplifier precisely kelvin-senses VOUT0’s load via the differential pin-pair formed by VOSNS0[+] and VOSNS0[–] . VOUT0 can be commanded to between 0.5VDC and 5.5VDC. VOUT1 is sensed via the pin-pair formed by VOSNS1 and signal ground of the module’s SGND. VOUT1 can be commanded to between 0.5VDC and 5.5VDC. Output voltage readback telemetry is available over I[2] C (READ_VOUT _n_ registers). Peak output voltage readback telemetry is accessible in the MFR_READ_VOUT_PEAK _n_ registers. If VOSNS0[–] exceeds VOSNS0[+] , no phase reversal of the differentially-sensed output voltage feedback signal
occurs (Note 12). Similarly, no phase reversal occurs when SGND exceeds VOSNS1(Note 12). For added flexibility, the VOSNSO[+] /VOSNSO[–] feedback pins can be configured as the control loop feedback path for both VOUT0 and VOUT1 by setting MFR_PWM_CONFIG[7]=1b. (See Figure 34).
The typical application schematic is shown in Figure 61 on the back page of this data sheet.
The LTM4675 can operate from input voltages between 5.75V and 17V (see front page figure). In this configuration, INTVCC MOSFET driver and control IC bias is generated internally by an LDO fed from SVIN to produce 5V at up to 100mA peak output current. Additional internal LDOs—3.3V (VDD33), derived from INTVCC, and 2.5V (VDD25), derived from VDD33—bias the LTM4675’s digital circuitry. When INTVCC is connected to SVIN, the LTM4675 can operate from input voltages between 4.5V and 5.75V (see Figure 27). Control IC bias (SVIN) is routed independent of the inputs to the power stages (VIN0, VIN1); this enables step-down DC/DC conversion from less than 4.5V input (see Figure 29), so long as auxiliary power (4.5V ~ 17V) is available to bias the control IC appropriately. Furthermore, the inputs of the two power stages are not connected together internal to the module; therefore, DC/ DC step-down conversion from two different source power supplies can be performed.
Per Note 6 of the Electrical Characteristics section, the output current may require derating for some operating scenarios. Detailed derating guidance is provided in the Applications Information section.
The LTM4675 contains dual integrated constant frequency current mode control buck regulators (Channel 0 and Channel 1) whose built-in power MOSFETs are capable of fast switching speed. The factory NVM-default switching frequency clocks SYNC at 500kHz, to which the regulators synchronize their switching frequency. The default phase-interleaving angle between the channels is 180°. A pin-strapping resistor on FSWPHCFG[ configures the frequency of the SYNC clock (switching ] frequency) and the channel phase relationship of the channels to each other and with respect to the falling edge of the SYNC signal. (Not all possible combinations of switching frequency and phase-angle assignments are settable by resistor pin programming; see Table 4. Configure the LTM4675’s NVM
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LTM4675
## **OPERATION**
to implement settings not available by resistor-pin strapping.) When a FSWPHCFG pin-strap resistor sets the channel phase relationship of the LTM4675’s channels, the SYNC clock is not driven by the module; instead, SYNC becomes strictly a high impedance input and channel switching frequency is then synchronized to SYNC provided by an externally-generated clock or sibling LTM4675 with pull-up resistor to VDD33. Switching frequency and phase relationship can be altered via the I[2] C interface, but only when switching action is off, i.e., when the module is not regulating either output. See the Applications Information section for details.
Internal feedback loop compensation for Regulator 0 is available by connecting COMP0a to COMP0b. (For Regulator 1, the connection is from COMP1a to COMP1b.) With current mode control and internal feedback loop compensation, the LTM4675 module has sufficient stability margins and good transient performance with a wide range of output capacitors—even all-ceramic MLCCs. Table 20 provides guidance on input and output capacitors recommended for many common operating conditions. The Analog Devices μModule Power Design Tool is available for transient and stability analysis. Furthermore, expert users who prefer to not make use of the module’s internal feedback loop compensation—but instead, tailor the feedback loop compensation specifically for his/her application—may do so by not connecting COMP _n_ a to COMP _n_ b: the personalized loop compensation network can be applied externally, i.e., from COMP _n_ a to SGND, and leaving COMP _n_ b open circuit.
The LTM4675 has two general purpose input/output pins, named GPIO0 and GPIO1. The behavior of these pins is configurable via registers MFR_GPIO_PROPAGATE _n_ and MFR_GPIO_RESPONSE _n_ . The GPIO _n_ pins are high impedance during NVM-download-to-RAM initialization. These pins are intended to perform one of two primary functions, or a hybrid of the two: behave as open- drain, active low fault/ warning indicators; and/or, behave as auxiliary RUN pins for their respective VOUTs. In the former case, the pins can be configured as interrupt pins, pulling active low when output under/overvoltage, input under/overvoltage, input/ output overcurrent, overtemperature, and/or communication, memory or logic (CML) fault or warning events are detected by the LTM4675. Factory NVM-default settings configure the LTM4675 for the latter case, enabling the GPIO _n_ to be bussed
to paralleled siblings (paralleled LTM4675 channels and/or modules), for purposes of coordinating orderly power-up and power-down, i.e., in unison. The LTM4675 DC/DC regulator does not feature a traditional “power good” (PGOOD) indicator pin to indicate when the output voltage is within a few percent of the target regulation point. However, the GPIO _n_ pin can be configured as a PGOOD indicator. If used for event-based sequencing of downstream rails, configure GPIO _n_ as the unfiltered output of the VOUT_UV_FAULT_LIMIT _n_ comparator, setting Bit 12 of MFR_GPIO_PROPAGATE _n_ to “1b”; do not set Bits 9 and 10 of MFR_GPIO_PROPAGATE _n_ for this purpose, since the propagation of power good in those latter instances is subject to supervisor filtering and comparator latency. If it is necessary to have the desired PGOOD polarity appear on the GPIO _n_ pin immediately upon SVIN power-up—given that the pin will initially be high impedance, until NVM contents have downloaded to RAM—a pull-down Schottky diode is needed between the RUN _n_ pin of the LTM4675 and the respective GPIO _n_ pin. (see Figure 2). If the GPIO _n_ pin is configured as a PGOOD indicator, the MFR_GPIO_RESPONSE _n_ must be set to “ignore” (0x00), or else the LTM4675 cannot start up due to the latch-off conditions imposed.
The RUN _n_ pin is a bidirectional open-drain pin. This means it should never be driven logic high from a low impedance source. Instead, simply provide a 10k pull-up resistor from the RUN _n_ pins to VDD33. The LTM4675 pulls its RUN _n_ pin logic low during NVM-download-to-RAM initialization, when SVIN is below the commanded undervoltage lockout voltage (VIN_ON, rising and VIN_OFF, falling), and subsequent to external stimulus pulling RUN low—for a minimum time dictated by MFR_RESTART_DELAY _n_ . Bussing the respective RUN _n_ and GPIO _n_ pins to sibling LTM4675 modules enables coordinated power-up/powerdown to be well orchestrated, i.e., performing turn-on and turn-off in a unified fashion.
When RUN _n_ exceeds 1.35V, the LTM4675 initially idles for a time dictated by the TON_DELAY _n_ register. After the TON_DELAY _n_ time expires, the module begins ramping up the respective control loop’s internal reference, starting from 0V. In the absence of a pre-biased VOUT _n_ condition, the output voltage is ramped linearly from 0V to the commanded target voltage, with a ramp-up time dictated by the TON_RISE _n_ register. In the presence of a
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LTM4675
## **OPERATION**
**==> picture [234 x 206] intentionally omitted <==**
**----- Start of picture text -----**<br>
Voltage Based Sequencing by Cascading GPIO n Pins Into RUN n Pins<br>(MFR_GPIO_PROPAGATE = XXX1X00XX00XXXXXb and MFR_GPIO_RESPONSE = 0x00)<br>*<br>START RUN0 GPIO0 = VOUT0_UVUF<br>LTM4675<br>RUN1 GPIO1 = VOUT1_UVUF<br>*<br>*<br>RUN0 GPIO0 = VOUT0_UVUF<br>LTM4675<br>RUN1 GPIO1 = VOUT1_UVUF<br>*<br>4675 F02<br>TO NEXT CHANNEL<br>IN THE SEQUENCE<br>**----- End of picture text -----**<br>
NOTE: RESISTOR OR RC PULL-UPS ON RUN _n_ AND GPIO _n_ PINS NOT SHOWN *OPTIONAL SIGNAL SCHOTTKY DIODE. ONLY NEEDED WHEN ACCURATE PGOOD (POWER GOOD) INDICATION IS REQURED BY THE SYSTEM/USER IMMEDIATELY AT SVIN POWER UP
## **Figure 2. Event (Voltage) Based Sequencing**
pre-biased VOUT _n_ condition, the output voltage is brought into regulation in the same manner as aforementioned, with the exception that inductor current is prevented from going negative (the module’s controller is operated in discontinuous mode operation during start-up). In both cases, the output voltage reaches regulation in a consistent time, as measured with respect to RUN _n_ toggling high. See start-up oscilloscope shots in the Typical Performance Characteristics section.
Pulling the RUN _n_ pin below 0.8V turns off the DC/DC converter, i.e., forces the respective regulator into a shutdown state. Factory NVM-default settings configure the LTM4675 to turn off its power stage MOSFETs immediately, thereby becoming high impedance. The output voltage then decays according to whatever output capacitance and load impedance is present. Alternatively, NVM/register settings can configure the LTM4675 to actively discharge VOUT _n_ when RUN _n_ is pulled logic low, according to prescribed TOFF_DELAY _n_ delay and TOFF_FALL _n_ ramp-down times. See the Applications Information section for details. The LTM4675 does not feature an explicit, analog TRACK pin. Rail-to-rail tracking and sequencing is handled digitally, as explained previously.
Bussing the open-drain SHARE_CLK pins of all LTM4675s (and providing a pull-up resistor to VDD33) provides a means for all LTM4675s in the system to synchronize their time-base (or “heartbeat”) to the fastest SHARE_CLK clock. Sharing the heartbeat amongst all LTM4675 ensures that all rails are sequenced according to expectations; it negates timing errors that could otherwise materialize due to SHARE_CLK (time-base) tolerance and part-topart variation.
Current sense information is derived from across the power inductors internal to the LTM4675 and made available to the internal control IC’s current control loops and ADC sensors. Output current readback telemetry is available over I[2] C (READ_IOUT _n_ registers). Peak output current readback telemetry is available in the MFR_READ_IOUT_PEAK _n_ registers.
Output power readback is computed by the LTM4675 according to:
READ_POUT _n_ = READ_VOUT _n_ • READ_IOUT _n_
Alternating excitation currents of 2µA and 30µA are sourced from the TSNS1a pin. Connecting TSNS1a to TSNS1b, temperature sensing of the Channel 1 power stage is realized by the LTM4675 digitizing the voltages that appear at the PNP transistor temperature sensor that resides at the TSNS1b pin. Analogous activity occurs on the TSNS0 node, from which Channel 0 power stage temperature is derived. The LTM4675 performs what is known in the industry as delta VBE (∆VBE) computations and makes channel (power stage) temperature telemetry available over I[2] C (READ_TEMPERATURE_1 _n_ ). The junction temperature of the control IC within the LTM4675 is also available over I[2] C (READ_TEMPERATURE_2). Observed peak Channel temperatures can be read back in registers READ_MFR_TEMPERATURE_1_PEAK _n_ . Observed peak temperature of the control IC can be read back in register MFR_READ_TEMPERATURE_2_PEAK.
For a fixed load current, the amplitude of the current sense information changes over temperature due to the temperature coefficient of copper (inductor DCR), which is approximately 3900ppm/°C. This would introduce significant current readback error over the operating range of the module if not for the fact that the LTM4675’s temperature
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LTM4675
## **OPERATION**
readback information is used in conjunction with the perceived current sense signal to yield temperature-corrected current readback data.
If desired, it is possible to use only the temperature readback information derived by the TSNS0 pin to yield temperature-corrected current readback data for both Channels 0 and 1. This frees up the Channel 1 temperature sensor to monitor a temperature sensor external to the LTM4675. This is achieved by setting MFR_PWM_MODE0[4] = 1b (the NVM-factory default value is 0b). This degrades the current readback accuracy of Channel 1—more so when Channel 0 and Channel 1 are not paralleled outputs. However, the TSNS1a pin becomes available to be connected to an external diodeconnected small-signal PNP transistor (such as 2N3906) and 10nF X7R capacitor, i.e., an external temperature sensor, whose temperature readback data and peak value are available over I[2] C (READ_TEMPERATURE_11, MFR_ READ_TEMPERATURE_1_PEAK1). Implementation of the aforementioned is as follows: (1) local to the LTM4675, electrically connect a 10nF X7R capacitor directly from TSNS1a to SGND; (2) differentially route a pair of traces from the LTM4675's TSNS1a and SGND pins to the target PNP transistor; (3) electrically connect the emitter of the PNP transistor to TSNS1a; (4) electrically connect the collector and base of the PNP transistor to SGND.
Power stage duty cycle readback telemetry is available over I[2] C (READ_DUTY_CYCLE _n_ registers). Computed channel input current readback is computed by the LTM4675 as:
MFR_READ_IIN _n_ = READ_DUTY_CYCLE _n_ • READ_IOUT _n_ + MFR_IIN_OFFSET _n_
Computed module input current readback is computed by the LTM4675 as:
READ_IIN=MFR_READ_IIN0 +MFR_READ_IIN1
where MFR_IIN_OFFSET _n_ is a register value representing the SVIN input bias current. The SVIN current is not digitized by the module. The factory NVM-default value of MFR_IIN_OFFSET _n_ is 29.56mA, representing the contribution of current drawn by each of the module’s channels on the SVIN pin, when the power stages are operating in forced continuous mode at the factory-
default switching frequency of 500kHz. See Table 8 in the Applications Information section for recommended MFR_IIN_OFFSET _n_ setting vs Switching Frequency. The aforementioned method by which input current is calculated yields an accurate current readback value even at light load currents, but only as long as the module is configured for forced continuous operation (NVM-factory default). SVIN and peak SVIN readback telemetry is accessible via I[2] C in the READ_VIN and MFR_VIN_PEAK registers, respectively.
The power stage switch nodes are brought out on the SW _n_ pin for functional operation monitoring and for optional installation of a resistor-capacitor snubber circuit (terminated to GND) for reduced EMI.
The LTM4675 features a write protect (WP) pin. If WP is open circuit or logic high, I[2] C writes are severely restricted: only I[2] C writes to the PAGE, OPERATION, CLEAR_FAULTS, MFR_CLEAR_PEAKS, and MFR_EE_UNLOCK commands are supported, with the exception that individual fault bits can be cleared by writing a “1b” to the respective bits in the STATUS_* registers. Register reads are never restricted. Not to be confused with the WP pin, the LTM4675 features a WRITE_PROTECT register, which is also used to restrict I[2] C writes to register contents. Refer to Appendix C: PMBus Command Details for details. The WP pin and the WRITE_PROTECT register provide a level of protection against accidental changes to RAM and EEPROM contents.
The LTM4675 supports all possible 7-bit slave addresses. The factory NVM-default slave address is 0x4F. The lower four bits of the LTM4675’s slave address can be altered from this default value by connecting a resistor from the ASEL pin to SGND. See Table 5 in the Applications Information section for details. Bits[6:4] can be altered by writing to the SLAVE_ADDRESS command. The value of the SLAVE_ADDRESS command can be stored to NVM, however, the lower four bits of the SLAVE_ADDRESS is always dictated by the ASEL resistor pin-strap setting.
Up to four LTM4675 modules (8 channels) can be paralleled, suitable for powering ~70A loads such as CPUs and GPUs. (See Figure 31) The LTM4675 can be paralleled with LTM4620A or LTM4630 modules, as well (see Figure 32 and Figure 33).
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LTM4675
## **OPERATION**
## **EEPROM**
The LTM4675’s control IC contains an internal EEPROM (non-volatile memory, NVM) with Error Correction Coding (ECC) to store configuration settings and fault log information. EEPROM endurance retention and mass write operation time are specified in the Electrical Characteristics and Absolute Maximum Ratings sections. Write operations at TJ < 0°C or at TJ > 85°C are possible although the Electrical Characteristics are not guaranteed and the EEPROM retention characteristics may be degraded. Read operations performed at junction temperatures between –40°C and 125°C do not degrade the EEPROM. The fault logging function, which is useful in debugging system problems that may occur at high temperatures, only writes to fault log-specific EEPROM locations (partitions). If occasional writes to these registers occur above 85°C junction, the slight degradation in the data retention characteristics of the fault log does not undermine the usefulness of the function.
It is recommended that the EEPROM not be written when the control IC die temperature is greater than 85°C. If the die temperature exceeds 130°C, the LTM4675’s control IC disables all EEPROM write operations. EEPROM write operations are subsequently re-enabled when the die temperature drops below 125°C.
The degradation in EEPROM retention for temperatures >125°C can be approximated by calculating the dimensionless acceleration factor using the following equation:
**==> picture [166 x 30] intentionally omitted <==**
where:
AF = acceleration factor
Ea = activation energy = 1.4eV k = 8.617 • 10[–5] eV/°K
TUSE = 125°C specified junction temperature
TSTRESS = actual junction temperature in °C
Example: Calculate the effect on retention when operating at a junction temperature of 135°C for 10 hours.
TSTRESS = 130°C
TUSE = 125°C
AF= e[[(1.4/8.617 • 10][–5][) • (1/398 – 1/403)]] = 1.66
The equivalent operating time at 125°C = 16.6 hours.
Thus the overall retention of the EEPROM was degraded by 6.6 hours as a result of operating at a junction temperature of 130°C for 10 hours. The effect of the overstress is negligible when compared to the overall EEPROM retention rating of 87,600 hours at a maximum junction temperature of 125°C.
The integrity of the EEPROM is checked with a CRC calculation each time its data is read, such as after a power-on reset or execution of a RESTORE_USER_ALL or MFR_RESET command. If CRC error occurs, the MFR bit is set in the STATUS_BYTE and STATUS_WORD commands. The NVM CRC error bit in the STATUS_MFR_SPECIFIC command is set and the ALERT and RUN pins are pulled low disabling the output as a safety measure. The device will only respond at special address 0x7C or global addresses 0x5A and 0x5B.
## **Internal EEPROM with CRC Protection and ECC**
The LTM4675 contains internal EEPROM with Error Correction Coding (ECC) to store user configuration settings and fault log information. EEPROM endurance and retention for user space and fault log pages are specified in the Absolute Maximum Ratings and Electrical Characteristics table.
The integrity of the EEPROM memory is checked with a CRC calculation each time its data is to be read, such as after a power-on reset. A CRC error will prevent the controller from leaving the OFF state. If a CRC error occurs, the CML bit is set in the STATUS_BYTE and STATUS_WORD commands, the appropriate bit is set in the STATUS_MFR_SPECIFIC command, and the ALERT and RUN pins will be pulled low. At that point the device will respond at special address 0x7C, which is only activated after an invalid CRC has been detected. The module will also respond to global
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LTM4675
## **OPERATION**
addresses 0x5A and 0x5B, but all ADI PSM modules and ICs will respond to these addresses so users must be careful when using global addresses. EEPROM repair can be attempted by writing the desired configuration to the controller and executing a STORE_USER_ALL command followed by a CLEAR_FAULTS command. Contact the factory if EEPROM repair is unsuccessful.
See the Applications Information section and Analog Devices Application Note 145, or contact the factory for details on efficient in-system EEPROM programming, including bulk EEPROM programming, which the LTM4675 also supports.
## **SERIAL INTERFACE**
The LTM4675 serial interface is a PMBus compliant slave device and can operate at any frequency between 10kHz and 400kHz. The address is configurable using either the EEPROM or an external resistor. In addition the LTM4675 always responds to the global broadcast address of 0x5A (7 bit) or 0x5B (7 bit). Address 0x5A is not paged and is performed on both channels. 0x5B respects the page command. Because address 0x5A does not support page, it can not be used for any paged reading commands.
The serial interface supports the following protocols defined in the PMBus specifications: 1) send command, 2) write byte, 3) write word, 4) group, 5) read byte, 6) read word and 7) read block 8) PAGE_PLUS_READ, 9) PAGE_PLUS_WRITE 10) SMBALERT_MASK read, 11) SMBALERT_MASK write. All read operations will return a valid PEC if the PMBus master requests it. If the PEC_REQUIRED bit is set in the MFR_CONFIG_ALL command, the PMBus write operations will not be acted upon until a valid PEC has been received by the LTM4675.
## **Communication Protection**
PEC write errors (if PEC_REQUIRED is active), attempts to access unsupported commands, or writing invalid data to supported commands will result in a CML fault. The CML bit is set in the STATUS_BYTE and STATUS_WORD commands, the appropriate bit is set in the STATUS_CML command, and the ALERT pin is pulled low.
## **DEVICE ADDRESSING**
The LTM4675 offers four different types of addressing over the PMBus interface, specifically: 1) global, 2) device, 3) rail addressing and 4) alert response address (ARA).
Global addressing provides a means of the PMBus master to address all LTM4675 devices on the bus. The LTM4675 global address is fixed 0x5A (7 bit) or 0xB4 (8 bit) and cannot be disabled. Commands sent to the global address act the same as if PAGE is set to a value of 0xFF. Commands sent are written to both channels simultaneously. Global command 0x5B (7 bit) or 0xB6 (8 bit) is paged and allows channel specific command of all LTM4675 devices on the bus. Other ADI device types may respond at one or both of these global addresses; therefore do not read from global addresses.
Rail addressing provides a means for the bus master to simultaneously communicate with all channels connected together to produce a single output voltage (PolyPhase[®] ). While similar to global addressing, the rail address can be dynamically assigned with the paged MFR_RAIL_ADDRESS command, allowing for any logical grouping of channels that might be required for reliable system control. Do not read from rail addresses because multiple ADI devices may respond.
Device addressing provides the standard means of the PMBus master communicating with a single instance of an LTM4675. The value of the device address is set by a combination of the ASEL configuration pin and the MFR_ADDRESS command. When this addressing means is used, the PAGE command determines the channel being acted upon. Device addressing can be disabled by writing a value of 0x80 to the MFR_ADDRESS.
All four means of PMBus addressing require the user to employ disciplined planning to avoid addressing conflicts. Communication to LTM4675 devices at global and rail addresses should be limited to command write operations.
## **FAULT DETECTION AND HANDLING**
A variety of fault and warning reporting and handling mechanisms are available. Fault and warning detection capabilities include:
n Input OV/FAULT Protection and UV Warning
- n Average Input OC Warn
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## **OPERATION**
- n Output OV/UV Fault and Warn Protection
- n Output OC Fault and Warn Protection
- n Internal and External Overtemperature Fault and Warn Protection
- n External Undertemperature Fault Protection
- n CML Fault (Communication, Memory or Logic)
- n External Fault Detection via the Bidirectional GPIO _n_ Pins.
In addition, the LTM4675 can map any combination of fault indicators to their respective GPIO _n_ pin using the propagate GPIO _n_ response commands, MFR_GPIO_PROPAGATE _n_ . Typical usage of a GPIO pin is as a driver for an external crowbar device, overtemperature alert, overvoltage alert or as an interrupt to cause a microcontroller to poll the fault commands. Alternatively, the GPIO _n_ pins can be used as inputs to detect external faults downstream of the controller that require an immediate response. The GPIO0 and/or GPIO1 pins can also be configured as power good outputs. Power good indicates the controller output is within the OV/UV fault thresholds. At power-up the pin will initially be three-state. If it is necessary to have the desired polarity on the pin at powerup in this configuration, attach a Schottky diode between the RUN pin of the propagated power good signal and the GPIO pin. The Cathode must be attached to RUN and the Anode to the GPIO pin (see Figure 2). If the GPIO pin is set to a power good status, the MFR_GPIO_RESPONSE must be ignore otherwise a latched off condition exists.
As described in the Soft-Start section, it is possible to control start-up through concatenated events. If GPIO _n_ is used to drive the RUN pin of another controller, the unfiltered VOUT_UV fault limit should be mapped to the GPIO pin.
Any fault or warning event will cause the ALERT pin to assert low unless the ALERT is masked by the SMBALERT_MASK command. The pin will remain asserted low until the CLEAR_FAULTS command is issued, the fault bit is written to a 1, the PMBus master successfully reads the device ARA register, bias power is cycled or a MFR_RESET or RESTORE_USER_ALL command is issued. Channel specific faults are cleared if the RUN pins are toggled OFF/ON or the part is commanded OFF/ON via PMBus. If bit 0 of MFR_ CONFIG_ALL is set to a 1, toggling the RUN pins OFF/ON or commanding the part OFF/ON via PMBus clears all faults.
The MFR_GPIO_PROPAGATE _n_ command determines if the GPIO pins are pulled low when a fault is detected; however, the ALERT pin is always pulled low if a fault or warning is detected and the status bits are updated unless the ALERT pin is masked using the SMBALERT_MASK command.
Output and input fault event handling is controlled by the corresponding fault response byte as specified in Table 24 to Table 28. Shutdown recovery from these types of faults can either be autonomous or latched. For autonomous recovery, the faults are not latched, so if the fault condition is not present after the retry interval has elapsed, a new soft-start is attempted. If the fault persists, the controller will continue to retry. The retry interval is specified by the MFR_RETRY_DELAY command and prevents damage to the regulator components by repetitive power cycling. The MFR_RETRY_DELAY must be greater than 120ms. It can not exceed 83.88 seconds.
Channel-to-channel fault dependencies can be created by connecting GPIO _n_ pins together. In the event of an internal fault, one or more of the channels is configured to pull the bussed GPIO _n_ pins low. The other channels are then configured to shut down when the GPIO _n_ pins are pulled low. For autonomous group retry, the faulted channel is configured to release the GPIO _n_ pin(s) after a retry interval, assuming the original fault has cleared. All the channels in the group then begin a soft-start sequence. If the fault response is LATCH_OFF, the GPIO pin remains asserted low until either the RUN pin is toggled OFF/ON or the part is commanded OFF/ON. The toggling of the RUN either by the pin or OFF/ON command will clear faults associated with the channel. If it is desired to have all faults cleared when either RUN pin is toggled, set bit 0 of MFR_CONFIG_ALL to a 1.
The status of all faults and warnings is summarized in the STATUS_WORD and STATUS_BYTE commands.
## **RESPONSES TO VOUT AND IOUT FAULTS**
VOUT OV and UV conditions are monitored by comparators. The OV and UV limits are set in three ways.
- n As a Percentage of the VOUT if Using the Resistor Configuration Pins
- n In EEPROM if Either Programmed at the Factory or Through the GUI
- n By PMBus Command
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## **OPERATION**
The IIN and IOUT overcurrent monitors are performed by ADC readings and calculations. Thus these values are based on average currents and can have a nominal time latency of up to 90ms. The IOUT calculation accounts for the power inductor DCR and the temperature coefficient of the inductor's copper winding. The input current is equal to the sum of output current times the respective channel duty cycle plus the input offset current for each channel. If this calculated input current exceeds the IIN_OC_WARN_LIMIT the ALERT pin is pulled low and the IIN_OC_WARN bit is asserted in the STATUS_INPUT register.
The LTM4675 provides the ability to ignore the fault, shut down and latch off or shut down and retry indefinitely (hiccup). The retry interval is set in MFR_RETRY_DELAY _n_ and can be from 120ms to 83.88 seconds in 1ms increments. The shutdown for OV/UV and OC can be done immediately or after a user selectable deglitch time.
## **Output Overvoltage Fault Response**
A programmable overvoltage comparator (OV) guards against transient overshoots as well as long-term overvoltages at the output. In such cases, the top MOSFET is turned off and the bottom MOSFET is turned on until the overvoltage condition is cleared _regardless of the PMBus VOUT_OV_FAULT_RESPONSEn command byte value._ This hardware level fault response delay is typically 2µs from the overvoltage condition to BG asserted high. Using the VOUT_OV_FAULT_RESPONSE _n_ command, the user can select any of the following behaviors:
- n OV Pull-Down Only (OV cannot be ignored)
- n Shut Down (Stop Switching) Immediately—Latch Off
- n Shut Down Immediately—Retry Indefinitely using the Time Interval Specified in MFR_RETRY_DELAY _n_
Either the Latch Off or Retry fault responses can be deglitched in increments of (0 to 7) • 10µs. See Table 24.
## **Output Undervoltage Response**
The response to an undervoltage comparator output can be either:
- n Ignore
- n Shut Down Immediately—Retry Indefinitely using the Time Interval Specified in MFR_RETRY_DELAY _n_
Either the Latch Off or Retry fault responses can be deglitched in increments of (0 to 7) • 10µs. See Table 25.
## **Peak Output Overcurrent Fault Response**
Due to the current mode control algorithm, peak inductor current is always limited on a cycle by cycle basis. The value of the peak current limit is specified in the Electrical Characteristics table. The current limit circuit operates by limiting the COMP _n_ a maximum voltage. DCR sensing is used so the COMP _n_ a maximum voltage has a temperature dependency directly proportional to the TC of the DCR of the inductor. The LTM4675 automatically monitors the power stage temperature sensors and modifies the maximum allowed COMP _n_ a to compensate for this term.
The overcurrent fault processing circuitry can execute the following behaviors:
- n Current Limit Indefinitely
- n Shut Down Immediately—Latch Off
- n Shut Down Immediately—Retry Indefinitely using the Time Interval Specified in MFR_RETRY_DELAY _n_
The overcurrent responses can be deglitched in increments of (0 to 7) • 16ms. See Table 26.
## **RESPONSES TO TIMING FAULTS**
TON_MAX_FAULT_LIMIT _n_ is the time allowed for VOUT to rise and settle at start-up. The TON_MAX_FAULT_LIMIT _n_ condition is predicated upon detection of the VOUT_UV_ FAULT_LIMIT _n_ as the output is undergoing a SOFT_START sequence. The TON_MAX_FAULT_LIMIT _n_ time is started after TON_DELAY _n_ has been reached and a SOFT_START sequence is started. The resolution of the TON_MAX_ FAULT_LIMIT _n_ is 10µs. If the VOUT_UV_FAULT_LIMIT _n_ is not reached within the TON_MAX_FAULT_LIMIT _n_ time, the response of this fault is determined by the value of the TON_MAX_FAULT_RESPONSE _n_ command value. This response may be one of the following:
## n Ignore
- n Shut Down (Stop Switching) Immediately—Latch Off
- n Shut Down Immediately—Latch Off
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## **OPERATION**
- n Shut Down Immediately—Retry Indefinitely using the Time Interval Specified in MFR_RETRY_DELAY _n_
This fault response is not deglitched. A value of 0 in TON_MAX_FAULT_LIMIT _n_ means the fault is ignored. The TON_MAX_FAULT_LIMIT _n_ should be set longer than the TON_RISE _n_ time. It is recommended TON_MAX_FAULT_ LIMIT _n_ always be set to a non-zero value, otherwise the output may never come up and no flag will be set to the user.
See Table 28.
## **External Overtemperature and Undertemperature Fault Response**
Two temperature sensors within the LTM4675 are used to sense power stage temperature. The OT_FAULT_ RESPONSE _n_ and UT_FAULT_RESPONSE _n_ commands are used to determine the appropriate response to an overtemperature and undertemperature condition, respectively.
The fault responses are:
- n Ignore
- n Shut Down Immediately—Latch Off
## **RESPONSES TO SVIN OV FAULTS**
SVIN overvoltage is measured with the ADC; therefore, the response is naturally deglitched by up to the 90ms typical response time of the ADC. The fault responses are:
- n Ignore
- n Shut Down Immediately—Latch Off
- n Shut Down Immediately—Retry Indefinitely using the Time Interval Specified in MFR_RETRY_DELAY _n_
See Table 28.
## **RESPONSES TO OT/UT FAULTS**
## **Internal Overtemperature Fault/Warn Response**
An internal temperature sensor protects against EEPROM damage. Above 85°C, no writes to EEPROM are recommended. Above 130°C, the internal over temperature warn threshold is exceeded and the part disables EEPROM writes and does not re-enable until the temperature has dropped to 125°C. When the die temperature exceed 160°C the internal over temperature fault response is enabled and the PWM is disabled until the die temperature drops below 150°C. Temperature is measured by the ADC. Internal temperature faults cannot be ignored. Internal temperature limits cannot be adjusted by the user.
See Table 27.
- n Shut Down Immediately—Retry Indefinitely using the Time Interval Specified in MFR_RETRY_DELAY _n_
See Table 28.
## **RESPONSES TO EXTERNAL FAULTS**
When either GPIO _n_ pin is pulled low, the OTHER bit is set in the STATUS_WORD command, the appropriate bit is set in the STATUS_MFR_SPECIFC command, and the ALERT pin is pulled low. Responses are not deglitched. Each channel can be configured to ignore or shut down then retry in response to its GPIO _n_ pin going low by modifying the MFR_GPIO_RESPONSE _n_ command. To avoid the ALERT pin asserting low when GPIO is pulled low, assert bit 1 of MFR_CHAN_CONFIG _n_ , or mask the ALERT using the SMBALERT_MASK command.
## **FAULT LOGGING**
The LTM4675 has fault logging capability. Data is logged into memory in the order shown in Table 30. The data to be stored in the fault log is being continuously stored in internal volatile memory. When a fault event occurs, the recording into internal volatile memory is halted, the fault log information is available from the MFR_FAULT_LOG command, and the contents of the internal memory are copied into EEPROM. Fault logging is allowed at temperatures above 85°C; however, retention of 10 years is
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LTM4675
## **OPERATION**
not guaranteed. When the die temperature exceeds 130°C the fault logging is delayed until the die temperature drops below 125°C. After the fault condition that created the fault log event has been removed, clear the fault before the fault log data is erased, or else the part will immediately issue another fault log.
When the LTM4675 powers-up, it checks the EEPROM for a valid fault log. If a valid fault log exists in EEPROM, the “Valid Fault Log” bit in the STATUS_MFR_SPECIFIC command will be set and an ALERT event will be generated. Also, fault logging will be blocked until the LTM4675 has received a MFR_FAULT_LOG_CLEAR command before fault logging will be re-enabled.
The information is stored in EEPROM in the event of any fault that disables the controller on either channel. An external GPIO _n_ pulling low will not trigger a fault logging event.
## **BUS TIMEOUT PROTECTION**
The LTM4675 implements a timeout feature to avoid hanging the serial interface. The data packet timer begins at the first START event before the device address write byte. Data packet information must be completed within 25ms or the LTM4675 will three-state the bus and ignore the given data packet. If more time is required, assert bit 3 of MFR_CONFIG_ALL to allow typical bus timeouts of 255ms. Data packet information includes the device address byte write, command byte, repeat start event (if a read operation), device address byte read (if a read operation), all data bytes and the PEC byte if applicable.
The LTM4675 allows longer PMBus timeouts for block read data packets. This timeout is proportional to the length of the block read. The additional block read timeout applies primarily to the MFR_FAULT_LOG command. In no circumstances will the timeout period be less than the tTIMEOUT_SMB specification of 32ms (typical).
The user is encouraged to use as high a clock rate as possible to maintain efficient data packet transfer between all devices sharing the serial bus interface. The LTM4675 supports the full PMBus frequency range from 10kHz to 400kHz.
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LTM4675
## **PMBUS COMMAND SUMMARY**
## **PMBUS COMMANDS**
Table 1 lists supported PMBus commands and manufacturer specific commands. A complete description of these commands can be found in the “PMBus Power System Management Protocol Specification – Part II – Revision 1.2." Users are encouraged to reference this specification. Exceptions or manufacturer specific implementations are listed in Table 1.
All commands from 0xD0 through 0xFF not listed in this table are implicitly reserved by the manufacturer. Users should avoid blind writes within this range of commands to avoid undesired operation of the part. All commands from 0x00 through 0xCF not listed in this table are implicitly not supported by the manufacturer. Attempting to access
non-supported or reserved commands may result in a CML
command fault event. All output voltage settings and measurements are based on the VOUT_MODE setting of 0x14. This translates to an exponent of 2–12.
If PMBus commands are received faster than they are being processed, the part may become too busy to handle new commands. In these circumstances the part follows the protocols defined in the PMBus Specification v1.2, Part II, Section 10.8.7, to communicate that it is busy.
The part includes handshaking features to eliminate busy errors and simplify error handling software while ensuring robust communication and system behavior. Please refer to the PMBus Communication and Command Processing subsection in the Applications Information section for details.
**Table 1. Summary of Supported Commands**
|**PMBus COMMAND**<br>**NAME, OR FEATURE**|**CMD CODE**<br>**(REGISTER)**|**COMMAND OR FEATURE**<br>**DESCRIPTION**|**LTM4675 NVM FACTORY-DEFAULT VALUE AND/OR ATTRIBUTES**|**PAGE**|
|---|---|---|---|---|
|PAGE|0x00|Channel or page currently targeted<br>for paged communications.|0x00, read/write, non-paged, not stored in NVM.|82|
|OPERATION_n_|0x01|Operating mode control. On/off,<br>margin high and margin low.|0x80, read/write, paged, stored in user-editable NVM.|86|
|ON_OFF_CONFIG_n_|0x02|RUN_n_pin and On/Off<br>Configuration.|0x1F, read/write, paged, stored in user-editable NVM.|85|
|CLEAR_FAULTS|0x03|Clear any fault bits that have been<br>set.|Default value not applicable, send byte only, non-paged, not stored in<br>NVM.|109|
|PAGE_PLUS_WRITE|0x05|Write a command directly to a<br>specified page.|Default value not applicable, write-only, non-paged, not stored in NVM.|82|
|PAGE_PLUS_READ|0x06|Read a command directly from a<br>specified page.|Default value not applicable, read/write, non-paged, not stored in NVM.|83|
|WRITE_PROTECT|0x10|Level of protection provided by the<br>device against accidental changes.|0x00, read/write, non-paged, stored in user-editable NVM.|83|
|STORE_USER_ALL|0x15|Store user operating memory to<br>EEPROM(user-editable NVM).|Default value not applicable, send byte only, non-paged, not stored in<br>NVM.|120|
|RESTORE_USER_<br>ALL|0x16|Restore user operating memory<br>from EEPROM.|Default value not applicable, send byte only, non-paged, not stored in NVM.<br>Identical to MFR_RESET command(0xFD).|121|
|CAPABILITY|0x19|Summary of PMBus optional<br>communication protocols<br>supported by this device.|0xB0, read-only, non-paged, not stored in NVM.|108|
|SMBALERT_MASK_n_|0x1B|MaskALERTactivity.|Default mask values: STATUS_VOUT_n_=0x00, STATUS_IOUT_n_=0x00,<br>STATUS_INPUT=0x00, STATUS_TEMPERATURE_n_=0x00, STATUS_<br>CML=0x00, STATUS_MFR_SPECIFIC_n_=0x11.<br>Read/write, paged as indicated, 10 bytes total, stored in NVM|110|
|VOUT_MODE_n_|0x20|Output voltage format/exponent.|0x14(2–12), read-only, paged, not stored in NVM.|90|
|VOUT_COMMAND_n_|0x21|Nominal output voltage set point.|0x1000(1.000V), read/write, paged, stored in user-editable NVM.|91|
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## **PMBUS COMMAND SUMMARY**
**Table 1. Summary of Supported Commands**
|**PMBus COMMAND**<br>**NAME, OR FEATURE**|**CMD CODE**<br>**(REGISTER)**|**COMMAND OR FEATURE**<br>**DESCRIPTION**|**LTM4675 NVM FACTORY-DEFAULT VALUE AND/OR ATTRIBUTES**|**PAGE**|
|---|---|---|---|---|
|VOUT_MAX_n_|0x24|The upper limit on the<br>commandable output voltage.|Page 0x00: 0x599A (5.600V)<br>Page 0x01: 0x599A (5.600V)<br>Read/write, paged, stored in user-editable NVM.|90|
|VOUT_MARGIN_<br>HIGH_n_|0x25|Margin high output voltage set<br>point. Must be greater than<br>VOUT_COMMAND_n_.|0x10CD (1.050V), read/write, paged, stored in user-editable NVM.|91|
|VOUT_MARGIN_<br>LOW_n_|0x26|Margin low output voltage set<br>point. Must be less than<br>VOUT_COMMAND_n_.|0x0F33 (0.950V), read/write, paged, stored in user-editable NVM.|92|
|VOUT_TRANSITION_<br>RATE_n_|0x27|The rate at which the output<br>voltage changes when VOUT_n_is<br>commanded to a new value via<br>I2C.|0x8042 (0.001V/ms), read/write, paged, stored in user-editable NVM.|97|
|FREQUENCY_<br>SWITCH|0x33|The switching frequency setting.|0xFBE8 (500kHz), read/write, non-paged, stored in user-editable NVM.|89|
|VIN_ON|0x35|The undervoltage lockout (UVLO)-<br>rising threshold.|0xCAC0 (5.500V), as monitored on the “SVIN” pin, read/write, non-paged,<br>stored in user-editable NVM.|90|
|VIN_OFF|0x36|The undervoltage lockout (UVLO)-<br>falling threshold.|0xCAA0 (5.250V) , as monitored on the “SVIN” pin, read/write, non-paged,<br>stored in user-editable NVM.|90|
|IOUT_CAL_GAIN_n_|0x38|The ratio of the voltage at the<br>control IC’s current-sense pins<br>to the sensed current, in mΩ, at<br>25°C.|Trimmed at ATE, read/write, paged, stored in factory-only NVM. Writes to<br>this register not recommended.|93|
|VOUT_OV_FAULT_<br>LIMIT_n_|0x40|Output overvoltage fault limit.|0x119A (1.100V), read/write, paged, stored in user-editable NVM.|91|
|VOUT_OV_FAULT_<br>RESPONSE_n_|0x41|Action to be taken by the device<br>when an output overvoltage fault<br>is detected.|0x7A (20µs glitch filter; non-latching shutdown; autonomous restart upon<br>fault removal), read/write, paged, stored in user-editable NVM.|100|
|VOUT_OV_WARN_<br>LIMIT_n_|0x42|Output overvoltage warning<br>threshold.|0x1133 (1.075V), read/write, paged, stored in user-editable NVM.|91|
|VOUT_UV_WARN_<br>LIMIT_n_|0x43|Output undervoltage warning<br>threshold.|0x0ECD (0.925V), read/write, paged, stored in user-editable NVM.|92|
|VOUT_UV_FAULT_<br>LIMIT_n_|0x44|Output undervoltage fault limit.|0x0E66 (0.900V), read/write, paged, stored in user-editable NVM.|92|
|VOUT_UV_FAULT_<br>RESPONSE_n_|0x45|Action to be taken by the device<br>when an output undervoltage fault<br>is detected.|0xB8 (non-latching shutdown; autonomous restart upon fault removal),<br>read/write, paged, stored in user-editable NVM.|101|
|IOUT_OC_FAULT_<br>LIMIT_n_|0x46|Output overcurrent fault threshold<br>(cycle-by-cycle inductor peak<br>current).|0xD3F3 (15.80A), read/write, paged, stored in user-editable NVM.|94|
|IOUT_OC_FAULT_<br>RESPONSE_n_|0x47|Action to be taken by the device<br>when an output overcurrent fault<br>is detected.|0x00 (try to regulate through the fault condition/event; limit the cycle-by-<br>cycle peak of the inductor current to not exceed the commanded IOUT_<br>OC_FAULT_LIMIT), read/write, paged, stored in user-editable NVM.|103|
|IOUT_OC_WARN_<br>LIMIT_n_|0x4A|Output overcurrent warning<br>threshold (time-averaged inductor<br>current).|0xD2B3 (10.80A), read/write, paged, stored in user-editable NVM.|95|
|OT_FAULT_LIMIT_n_|0x4F|Overtemperature fault threshold.|0xF200(128°C), read/write, paged, stored in user-editable NVM.|96|
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## **PMBUS COMMAND SUMMARY**
## **Table 1. Summary of Supported Commands**
|**PMBus COMMAND**<br>**NAME, OR FEATURE**|**CMD CODE**<br>**(REGISTER)**|**COMMAND OR FEATURE**<br>**DESCRIPTION**|**LTM4675 NVM FACTORY-DEFAULT VALUE AND/OR ATTRIBUTES**|**PAGE**|
|---|---|---|---|---|
|OT_FAULT_<br>RESPONSE_n_|0x50|Action to be taken by the device<br>when an overtemperature fault is<br>detected via TSNS_n_a.|0xB8 (non-latching shutdown; autonomous restart upon fault removal),<br>read/write, paged, stored in user-editable NVM.|105|
|OT_WARN_LIMIT_n_|0x51|Overtemperature warning<br>threshold.|0xEBE8 (125°C), read/write, paged, stored in user-editable NVM.|96|
|UT_FAULT_LIMIT_n_|0x53|Undertemperature fault threshold.|0xE530(–45°C), read/write, paged, stored in user-editable NVM.|96|
|UT_FAULT_<br>RESPONSE_n_|0x54|Response to undertemperature<br>fault events.|0x00 (ignore; continue without interruption), read/write, paged, stored in<br>user-editable NVM, read/write, paged, stored in user-editable NVM.|105|
|VIN_OV_FAULT_<br>LIMIT|0x55|Input supply (SVIN) overvoltage<br>fault limit.|0xDA2E (17.44V), read/write, non-paged, stored in user-editable NVM.|89|
|VIN_OV_FAULT_<br>RESPONSE_n_|0x56|Response to input overvoltage<br>fault events.|0xB8 (non-latching shutdown; autonomous restart upon fault removal),<br>read/write, paged, stored in user-editable NVM.|99|
|VIN_UV_WARN_<br>LIMIT|0x58|Input undervoltage warning<br>threshold.|0xCAA6 (5.297V), read/write, non-paged, stored in user-editable NVM.|89|
|IIN_OC_WARN_<br>LIMIT|0x5D|Input supply overcurrent warning<br>threshold.|0xD220 (8.5A), read/write, non-paged, stored in user-editable NVM.|93|
|TON_DELAY_n_|0x60|Time from RUN_n_and/or<br>OPERATION_n_on to output rail<br>turn-on.|0x8000 (0ms), read/write, paged, stored in user-editable NVM.|97|
|TON_RISE_n_|0x61|Time from when the output<br>voltage reference starts to rise<br>until it reaches its commanded<br>setting.|0xC300 (3ms), read/write, paged, stored in user-editable NVM.|97|
|TON_MAX_FAULT_<br>LIMIT_n_|0x62|Turn-on watchdog timeout fault<br>threshold (time permitted for<br>VOUT_n_to reach or exceed VOUT_<br>UV_FAULT_LIMIT_n_after turn-on<br>command is received).|0xCA80 (5ms), read/write, paged, stored in user-editable NVM.|97|
|TON_MAX_FAULT_<br>RESPONSE_n_|0x63|Action to be taken by the device<br>when a TON_MAX_FAULT_n_event<br>is detected.|0xB8 (non-latching shutdown; autonomous restart upon fault removal),<br>read/write, paged, stored in user-editable NVM.|102|
|TOFF_DELAY_n_|0x64|Time from RUN and/or Operation<br>off to the start of TOFF_FALL_n_<br>ramp.|0x8000 (0ms), read/write, paged, stored in user-editable NVM.|98|
|TOFF_FALL_n_|0x65|Time from when the output<br>voltage reference starts to fall until<br>it reaches 0V.|0xC300 (3ms), read/write, paged, stored in user-editable NVM.|98|
|TOFF_MAX_WARN_<br>LIMIT_n_|0x66|Turn-off watchdog timeout fault<br>threshold (time permitted for<br>VOUT_n_to decay to or below<br>12.5% of the commanded VOUT_n_<br>value at the time of receiving a<br>turn-off command).|0x8000 (no limit; warning is disabled), read/write, paged, stored in user-<br>editable NVM.|98|
|STATUS_BYTE_n_|0x78|One byte summary of the unit’s<br>fault condition.|Default value not applicable, read/write, paged, not stored in NVM.|111|
|STATUS_WORD_n_|0x79|Two byte summary of the unit’s<br>fault condition.|Default value not applicable, read/write, paged, not stored in NVM.|111|
|STATUS_VOUT_n_|0x7A|Output voltage fault and warning<br>status.|Default value not applicable, read/write, paged, not stored in NVM.|112|
Rev. D
40
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LTM4675
## **PMBUS COMMAND SUMMARY**
**Table 1. Summary of Supported Commands**
|**PMBus COMMAND**<br>**NAME, OR FEATURE**|**CMD CODE**<br>**(REGISTER)**|**COMMAND OR FEATURE**<br>**DESCRIPTION**|**LTM4675 NVM FACTORY-DEFAULT VALUE AND/OR ATTRIBUTES**|**PAGE**|
|---|---|---|---|---|
|STATUS_IOUT_n_|0x7B|Output current fault and warning<br>status.|Default value not applicable, read/write, paged, not stored in NVM.|112|
|STATUS_INPUT|0x7C|Input supply (SVIN) fault and<br>warning status.|Default value not applicable, read/write, non-paged, not stored in NVM.|112|
|STATUS_<br>TEMPERATURE_n_|0x7D|TSNS_n_a-sensed temperature fault<br>and warning status for READ_<br>TEMERATURE_1_n_.|Default value not applicable, read/write, paged, not stored in NVM.|113|
|STATUS_CML|0x7E|Communication and memory fault<br>and warning status.|Default value not applicable, read/write, non-paged, not stored in NVM.|113|
|STATUS_MFR_<br>SPECIFIC_n_|0x80|Manufacturer specific fault and<br>state information.|Default value not applicable, read/write, paged, not stored in NVM.|113|
|READ_VIN|0x88|Measured input supply (SVIN)<br>voltage.|Default value not applicable, read-only, non-paged, not stored in NVM.|117|
|READ_IIN|0x89|Calculated total input supply<br>current.|Default value not applicable, read-only, non-paged, not stored in NVM.|117|
|READ_VOUT_n_|0x8B|Measured output voltage.|Default value not applicable, read-only, paged, not stored in NVM.|117|
|READ_IOUT_n_|0x8C|Measured output current.|Default value not applicable, read-only, paged, not stored in NVM.|117|
|READ_<br>TEMPERATURE_1_n_|0x8D|Measurement of TSNS_n_a-sensed<br>temperature.|Default value not applicable, read-only, paged, not stored in NVM.|117|
|READ_<br>TEMPERATURE_2|0x8E|Measured control IC junction<br>temperature.|Default value not applicable, read-only, non-paged, not stored in NVM.|118|
|READ_DUTY_<br>CYCLE_n_|0x94|Measured duty cycle of MT_n_.|Default value not applicable, read-only, paged, not stored in NVM.|118|
|READ_POUT_n_|0x96|Calculated output power.|Default value not applicable, read-only, paged, not stored in NVM.|118|
|PMBUS_REVISION|0x98|PMBus revision supported by this<br>device.|0x22 (Revision 1.2 of Part I and Revision 1.2 of Part II of PMBus<br>Specification documents), read-only, non-paged, not stored in NVM.|108|
|MFR_ID|0x99|Manufacturer identification, in<br>ASCII|“LTC”, read-only, non-paged.|108|
|MFR_MODEL|0x9A|Manufacturer’s part number, in<br>ASCII|LTM4675, read-only, non-paged.|109|
|MFR_SERIAL|0x9E|Serial number of this specific unit.|Up to nine bytes of custom-formatted data that identify the unit’s<br>configuration, read-only, non-paged.|109|
|MFR_VOUT_MAX_n_|0xA5|Maximum allowed output voltage.|0x5B34 (5.700V) on both channels. Read-only, paged, not stored in user-<br>editable NVM.|92|
|USER_DATA_00|0xB0|OEM reserved data.|Read/write, non-paged, stored in user-editable NVM. Recommended<br>against altering.|108|
|USER_DATA_01_n_|0xB1|OEM reserved data.|Read/write, paged, stored in user-editable NVM. Recommended against<br>altering.|108|
|USER_DATA_02|0xB2|OEM reserved data.|Read/write, non-paged, stored in user-editable NVM. Recommended<br>against altering.|108|
|USER_DATA_03_n_|0xB3|User-editable words available for<br>the user.|0x0000, read/write, paged, stored in user-editable NVM.|108|
|USER_DATA_04|0xB4|A user-editable word available for<br>the user.|0x0000, read/write, non-paged, stored in user-editable NVM.|108|
|MFR_INFO|0xB6|Manufacturing specific<br>information|Default value not applicable, read only, non-paged, not stored in NVM.<br>Bit 5 is 0bwhen ECC has made a correction to data derived from the<br>EEPROM user space.|116|
Rev. D
41
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LTM4675
## **PMBUS COMMAND SUMMARY**
## **Table 1. Summary of Supported Commands**
|**PMBus COMMAND**<br>**NAME, OR FEATURE**|**CMD CODE**<br>**(REGISTER)**|**COMMAND OR FEATURE**<br>**DESCRIPTION**|**LTM4675 NVM FACTORY-DEFAULT VALUE AND/OR ATTRIBUTES**|**PAGE**|
|---|---|---|---|---|
|MFR_EE_UNLOCK|0xBD|Unlock user EEPROM for access<br>by MFR_EE_ERASE and MFR_EE_<br>DATA commands.|Default value not applicable, read/write, non-paged, not stored in NVM.|126|
|MFR_EE_ERASE|0xBE|Initialize user EEPROM for bulk<br>programming by MFR_EE_DATA.|Default value not applicable, read/write, non-paged, not stored in NVM.|126|
|MFR_EE_DATA|0xBF|Data transferred to and from<br>EEPROM using sequential PMBus<br>word reads or writes. Supports<br>bulk programming.|Default value not applicable, read/write, non-paged, not stored in NVM.|126|
|MFR_CHAN_<br>CONFIG_*_n_|0xD0|Channel-specific configuration<br>bits.|0x1F, read/write, paged, stored in user-editable NVM. Register is named<br>“MFR_CHAN_CONFIG” and referred to as “MFR_CHAN_CONFIG_<br>LTM467X” in LTpowerPlay.|84|
|MFR_CONFIG_ALL_*|0xD1|Global configuration bits, i.e.,<br>common to both VOUTchannels<br>0 and 1.|0x09, read/write, non-paged, stored in user-editable NVM. Bit 4<br>configures whether the SYNC drive circuit is active (0b) or inactive (1b);<br>Bit 3 configures whether the Stuck PMBus Timer Timeout is 150ms for<br>Block Reads and 32ms for Non-Block Reads (0b) or 250ms for all<br>Reads (1b).<br>Register is named "MFR_CONFIG_ALL_LTM467X” in LTpowerPlay.|85|
|MFR_GPIO_<br>PROPAGATE_*_n_|0xD2|Configuration bits for propagating<br>faults to the GPIO_n_pins.|0x6893, read/write, paged, stored in user-editable NVM. Register is<br>named “MFR_GPIO_PROPAGATE” and referred to as “MFR_GPIO_<br>PROPAGATE_LTM467X” in LTpowerPlay.|106|
|MFR_PWM_<br>MODE_*_n_|0xD4|Configuration for the PWM engine<br>of each VOUTchannel.|0xC1, read/write, paged, stored in user-editable NVM. Bit 1 commands<br>whether the output is in high range (0b) or low range (1b). Bit 0<br>commands whether the output is operating in Forced Continuous<br>Conduction Mode (1b) or Discontinuous Mode (0b).<br>Command is named MFR_PWM_MODE and referred to as MFR_PWM_<br>MODE_LTM467X in LTpowerPlay.|87|
|MFR_GPIO_<br>RESPONSE_n_|0xD5|Action to be taken by the device<br>when the GPIO_n_pin is asserted<br>low by circuitry external to the<br>unit.|0xC0 (make the respective output’s power stage high impedance, i.e.,<br>three-stated; autonomous restart upon fault removal),<br>read/write, paged, stored in user-editable NVM.|107|
|MFR_OT_FAULT_<br>RESPONSE|0xD6|Action to be taken by the device<br>when a control IC junction<br>overtemperature fault is detected.|0xC0 (make the respective output’s power stage high impedance, i.e.,<br>three-stated; autonomous restart upon fault removal), read-only, non-<br>paged, not stored in user-editable NVM.|104|
|MFR_IOUT_PEAK_n_|0xD7|Maximum measured value of<br>READ_IOUT_n_since the last MFR_<br>CLEAR_PEAKS.|Default value not applicable, read-only, paged, not stored in NVM.|119|
|MFR_ADC_<br>CONTROL|0xD8|ADC telemetry parameter for<br>repeated fast ADC readback.|0x00, read/write, not paged, not stored in NVM. Allows telemetry<br>readback rates up to 125Hz instead of 10Hz, nominal.|119|
|MFR_ADC_<br>TELEMETRY_<br>STATUS|0xDA|ADC status during short-loop.|Default value not applicable, read/write, not paged, not stored in NVM.<br>ADC status indicating most recently digitized telemetry when engaged in<br>short round-robin loop(MFR_ADC_CONTROL=0x0D)|120|
|MFR_RETRY_<br>DELAY_n_|0xDB|Retry interval during fault-retry<br>mode.|0xF3E8 (250ms), read/write, paged, stored in user-editable NVM.|99|
|MFR_RESTART_<br>DELAY_n_|0xDC|Minimum interval (nominal) the<br>RUN_n_pin is pulled logic low by<br>internal circuitry.|0xFA58 (300ms), read/write, paged, stored in user-editable NVM.|99|
|MFR_VOUT_PEAK_n_|0xDD|Maximum measured value of<br>READ_VOUT_n_since the last<br>MFR_CLEAR_PEAKS.|Default value not applicable, read-only, paged, not stored in NVM.|118|
Rev. D
42
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LTM4675
## **PMBUS COMMAND SUMMARY**
**Table 1. Summary of Supported Commands**
|**PMBus COMMAND**<br>**NAME, OR FEATURE**|**CMD CODE**<br>**(REGISTER)**|**COMMAND OR FEATURE**<br>**DESCRIPTION**|**LTM4675 NVM FACTORY-DEFAULT VALUE AND/OR ATTRIBUTES**|**PAGE**|
|---|---|---|---|---|
|MFR_VIN_PEAK|0xDE|Maximum measured value of<br>READ_VIN since the last MFR_<br>CLEAR_PEAKS.|Default value not applicable, read-only, non-paged, not stored in NVM.|118|
|MFR_<br>TEMPERATURE_1_<br>PEAK_n_|0xDF|Maximum value of TSNS_n_a<br>measured temperature since the<br>last MFR_CLEAR_PEAKS.|Default value not applicable, read-only, paged, not stored in NVM.|118|
|MFR_CLEAR_PEAKS|0xE3|Clears all peak values.|Default value not applicable, send byte only, non-paged, not stored in<br>NVM.|110|
|MFR_PADS|0xE5|Digital status of the I/O pads.|Default value not applicable, read-only, non-paged, not stored in NVM.|114|
|MFR_ADDRESS|0xE6|LTM4675's I2C slave address,<br>right-justified.|0x4F, read/write, non-paged, stored in user-editable NVM. Bits[6:4]<br>represent the user-configurable upper 3 bits of the 7-bit slave address of<br>the device. Bits[3:0] are dictated by the ASEL resistor pin-strap setting.<br>Setting this command to 0x80 disables device-specific addressing.|84|
|MFR_SPECIAL_ID|0xE7|Manufacturer code representing IC<br>silicon and revision|0x47AX, read-only, non-paged.|109|
|MFR_IIN_OFFSET_n_|0xE9|Coefficient used in calculations of<br>READ_IIN and MFR_READ_IIN_n_,<br>representing the contribution of<br>input current drawn by the control<br>IC, including the MOSFET drivers.|0x8BC9 (0.02956A), read/write, paged, stored in user-editable NVM.|93|
|MFR_FAULT_LOG_<br>STORE|0xEA|Commands a transfer of the fault<br>log from RAM to EEPROM. This<br>causes the part to behave as if a<br>channel has faulted off.|Default value not applicable, send byte only, non-paged, not stored in<br>NVM.|126|
|MFR_FAULT_LOG_<br>CLEAR|0xEC|Initialize the EEPROM block<br>reserved for fault logging and<br>clear any previous fault logging<br>locks.|Default value not applicable, send byte only, non-paged, not stored in<br>NVM.|126|
|MFR_READ_IIN_n_|0xED|Calculated input current, by<br>channel.|Default value not applicable, read-only, paged, not stored in NVM.|117|
|MFR_FAULT_LOG|0xEE|Fault log data bytes. This<br>sequentially retrieved data is used<br>to assemble a complete fault log.|Default value not applicable, read-only, non-paged, stored in fault-log<br>NVM.|125|
|MFR_COMMON|0xEF|Manufacturer status bits that are<br>common across multiple ADI ICs/<br>modules.|Default value not applicable, read-only, non-paged, not stored in NVM.|114|
|MFR_COMPARE_<br>USER_ALL|0xF0|Compares current command<br>contents(RAM)with NVM.|Default value not applicable, send byte only, non-paged, not stored in<br>NVM.|121|
|MFR_<br>TEMPERATURE_2_<br>PEAK|0xF4|Maximum measured control IC<br>junction temperature since last<br>MFR_CLEAR_PEAKS.|Default value not applicable, read-only, non-paged, not stored in NVM.|118|
|MFR_PWM_<br>CONFIG_*|0xF5|Configuration bits for setting<br>the phase interleaving angles of<br>Channels 0 and 1, SHARE_CLK<br>behavior in UVLO, and using<br>the fully differential amplifier<br>to regulate paralleled output<br>channels.|0x10, read/write, non-paged, stored in user-editable NVM. When bit 7 is<br>0b, Channel 1's output is regulated by the VOSNS1and SGND feedback<br>signals. When bit 7 is 1b, Channel 1's output is regulated by the VOSNS0+<br>and VOSNS0– feedback signals. Only set bit 7 to 1bfor PolyPhase rail<br>applications. The command is named MFR_PWM_CONFIG and referred to<br>as MFR_PWM_CONFIG_LTM467X in LTpowerPlay.|88|
|MFR_IOUT_CAL_<br>GAIN_TC_n_|0xF6|Temperature coefficient of the<br>current sensing element.|0x0F14 (3860ppm/°C), read/write, paged, stored in user-editable NVM.|93|
Rev. D
43
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LTM4675
## **PMBUS COMMAND SUMMARY**
## **Table 1. Summary of Supported Commands**
|**PMBus COMMAND**<br>**NAME, OR FEATURE**|**CMD CODE**<br>**(REGISTER)**|**COMMAND OR FEATURE**<br>**DESCRIPTION**|**LTM4675 NVM FACTORY-DEFAULT VALUE AND/OR ATTRIBUTES**|**PAGE**|
|---|---|---|---|---|
|MFR_TEMP_1_<br>GAIN_n_|0xF8|Sets the slope of the temperature<br>sensors that interface to TSNS_na_.|0x3FAE (0.995, in custom units), read/write, paged, stored in user-<br>editable NVM.|95|
|MFR_TEMP_1_<br>OFFSET_n_|0xF9|Sets the offset of the TSNS_na_<br>temperature sensor with respect<br>to –273.1°C.|0x8000 (0.0), read/write, paged, stored in NVM.|95|
|MFR_RAIL_<br>ADDRESS_n_|0xFA|Common address for PolyPhase<br>outputs to adjust common<br>parameters.|0x80, read/write, paged, stored in NVM.|84|
|MFR_RESET|0xFD|Commanded reset without<br>requiring a power down.|Default value not applicable, send byte only, non-paged, not stored in<br>NVM. Identical to RESTORE_USER_ALL.|87|
Rev. D
44
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LTM4675
## **APPLICATIONS INFORMATION**
**Table 2. VOUT** _**n**_ **CFG Pin Strapping Look-Up Table for the LTM4675's Output Voltage, Coarse Setting (Not Applicable if MFR_CONFIG_ALL[6] = 1b)**
|**RVOUT****_n_ CFG*,****<br>**(kΩ)**|**VOUT****_n_ (V) SETTING**<br>**COARSE**|**MFR_PWM_MODE****_n_[1] BIT**|
|---|---|---|
|Open|NVM|NVM|
|32.4|See Table 3|See Table 3|
|22.6|3.3|0|
|18.0|3.1|0|
|15.4|2.9|0|
|12.7|2.7|0|
|10.7|2.5|0, if VTRIM_n_> 0mV<br>1, if VTRIM_n_≤ 0mV|
|9.09|2.3|1|
|7.68|2.1|1|
|6.34|1.9|1|
|5.23|1.7|1|
|4.22|1.5|1|
|3.24|1.3|1|
|2.43|1.1|1|
|1.65|0.9|1|
|0.787|0.7|1|
|0|0.5|1|
*RVOUT _n_ CFG value indicated is nominal. Select RVOUT _n_ CFG from a resistor vendor such that its value is always within 3% of the value indicated in the table. Take into account resistor initial tolerance, T.C.R. and resistor operating temperatures, soldering heat/IR reflow, and endurance of the resistor over its lifetime. Thermal shock/cycling, moisture (humidity) and other effects (depending on one’s specific application) could also affect RVOUT _n_ CFG’s value over time. All such effects must be taken into account in order for resistor pin strapping to yield the expected result at every SVIN power-up and/or every execution of MFR_RESET or RESTORE_ USER_ALL, over the lifetime of one’s product.
**In applications where VOUT0 and VOUT1 are paralleled, the respective VOUT _n_ CFG and VTRIM _n_ CFG pin-pairs can be electrically connected together; common RCONFIG resistors can be applied, whose values are half of what is prescribed in Table 2 and Table 3. See Figure 34, for example.
**Table 3. VTRIM** _**n**_ **CFG Pin Strapping Look-Up Table for the LTM4675's Output Voltage, Fine Adjustment Setting (Not Applicable if MFR_CONFIG_ALL[6] = 1b)**
|**RVTRIM****_n_CFG*,****<br>**(kΩ)**|**VTRIM (mV) FINE**<br>**ADJUSTMENT**<br>**TO VOUT****_n_**<br>**SETTING WHEN**<br>**RESPECTIVE**<br>**RVOUT****_n_CFG ≠**<br>**32.4kΩ**|**VOUT****_n_ OUTPUT**<br>**VOLTAGE**<br>**SETTING**<br>**(V) WHEN**<br>**VOUT****_n_CFG PIN**<br>**USES RCFG =**<br>**32.4kΩ**|**MFR_PWM_**<br>**MODE****_n_[1] BIT**|
|---|---|---|---|
|Open|0|NVM|0, if VOUT_OV_<br>FAULT_LIMIT_n_<br>> 2.75V<br>1, if VOUT_OV_<br>FAULT_LIMIT_n_<br>≤ 2.75V|
|32.4|99|||
|22.6|86.625|||
|18.0|74.25|||
|15.4|61.875|||
|12.7|49.5|||
|10.7|37.125|5.50|0|
|9.09|24.75|5.25|0|
|7.68|12.375|5.00|0|
|6.34|–12.375|4.75|0|
|5.23|–24.75|4.50|0|
|4.22|–37.125|4.25|0|
|3.24|–49.5|4.00|0|
|2.43|–61.875|3.75|0|
|1.65|–74.25|3.63|0|
|0.787|–86.625|3.50|0|
|0|–99|3.46|0|
*RVTRIM _n_ CFG value indicated is nominal. Select RVTRIM _n_ CFG from a resistor vendor such that its value is always within 3% of the value indicated in the table. Take into account resistor initial tolerance, T.C.R. and resistor operating temperatures, soldering heat/IR reflow, and endurance of the resistor over its lifetime. Thermal shock/cycling, moisture (humidity) and other effects (depending on one’s specific application) could also affect RVTRIM _n_ CFG’s value over time. All such effects must be taken into account in order for resistor pin strapping to yield the expected result at every SVIN power-up and/or every execution of MFR_RESET or RESTORE_USER_ALL, over the lifetime of one’s product.
**In applications where VOUT0 and VOUT1 are paralleled, the respective VOUT _n_ CFG and VTRIM _n_ CFG pin-pairs can be electrically connected together; common RCONFIG resistors can be applied, whose values are half of what is prescribed in Table 2 and Table 3. See Figure 34, for example.
Rev. D
45
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LTM4675
## **APPLICATIONS INFORMATION**
**Table 4. FSWPHCFG Pin Strapping Look-Up Table to Set the LTM4675's Switching Frequency and Channel Phase-Interleaving Angle (Not Applicable if MFR_CONFIG_ALL[6] = 1b)**
|**RFSWPHCFG* **<br>**(kΩ)**|**SWITCHING**<br>**FREQUENCY(kHz)**|θ**SYNC TO**θ**0**|θ**SYNC TO**θ**1**|**BITS [2:0] OF**<br>**MFR_PWM_CONFIG**|**BIT [4] OF**<br>**MFR_CONFIG_ALL**|
|---|---|---|---|---|---|
|Open|NVM; LTM4675<br>Default = 500|NVM; LTM4675<br>Default = 0°|NVM; LTM4675<br>Default = 180°|NVM; LTM4675<br>Default = 000b|NVM; LTM4675<br>Default = 0b|
|32.4|250|0°|180°|000b|0b|
|22.6|350|0°|180°|000b|0b|
|18.0|425|0°|180°|000b|0b|
|15.4|575|0°|180°|000b|0b|
|12.7|650|0°|180°|000b|0b|
|10.7|750|0°|180°|000b|0b|
|9.09|1000|0°|180°|000b|0b|
|7.68|500|120°|240°|100b|0b|
|6.34|500|90°|270°|001b|0b|
|5.23|Sync Slave**|0°|240°|010b|1b|
|4.22|Sync Slave**|0°|120°|011b|1b|
|3.24|Sync Slave**|60°|240°|101b|1b|
|2.43|Sync Slave**|120°|300°|110b|1b|
|1.65|Sync Slave**|90°|270°|001b|1b|
|0.787|Sync Slave**|0°|180°|000b|1b|
|0|Sync Slave**|120°|240°|100b|1b|
* RFSWPHCFG value indicated is nominal. Select RFSWPHCFG from a resistor vendor such that its value is always within 3% of the value indicated in the table. Take into account resistor initial tolerance, T.C.R. and resistor operating temperatures, soldering heat/IR reflow, and endurance of the resistor over its lifetime. Thermal shock/cycling, moisture (humidity) and other effects (depending on one’s specific application) could also affect RFSWPHCFG’s value over time. All such effects must be taken into account in order for resistor pin-strapping to yield the expected result at every SVIN power-up and/or every execution of MFR_RESET or RESTORE_USER_ALL, over the lifetime of one’s product.
** The "Sync Slave" setting results in MFR_CONFIG_ALL[4] being set to 1b and FREQUENCY_SWITCH being set according to user-configurable EEPROM contents corresponding to Command 0x33 (factory default: 500kHz). In this configuration, the module's switching frequency synchronizes to the SYNC signal, provided that the SYNC pin is driven in a manner consistent with specifications (see Switching Frequency and Phase subsection of the Applications Information section for details).
Rev. D
46
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LTM4675
## **APPLICATIONS INFORMATION**
## **Table 5. ASEL Pin Strapping Look-Up Table to Set the LTM4675's MFR_ADDRESS (Applicable Regardless of MFR_CONFIG_ALL[6] Setting)**
|**RASEL* (kΩ)**|**SLAVE ADDRESS**|
|---|---|
|Open|MFR_ADDRESS[6:0]_R/W|
|32.4|MFR_ADDRESS[6:4]_1111_R/W|
|22.6|MFR_ADDRESS[6:4]_1110_R/W|
|18.0|MFR_ADDRESS[6:4]_1101_R/W|
|15.4|MFR_ADDRESS[6:4]_1100_R/W|
|12.7|MFR_ADDRESS[6:4]_1011_R/W|
|10.7|MFR_ADDRESS[6:4]_1010_R/W|
|9.09|MFR_ADDRESS[6:4]_1001_R/W|
|7.68|MFR_ADDRESS[6:4]_1000_R/W|
|6.34|MFR_ADDRESS[6:4]_0111_R/W|
|5.23|MFR_ADDRESS[6:4]_0110_R/W|
|4.22|MFR_ADDRESS[6:4]_0101_R/W|
|3.24|MFR_ADDRESS[6:4]_0100_R/W|
|2.43|MFR_ADDRESS[6:4]_0011_R/W|
|1.65|MFR_ADDRESS[6:4]_0010_R/W|
|0.787|MFR_ADDRESS[6:4]_0001_R/W|
|0|MFR_ADDRESS[6:4]_0000_R/W|
## **Table 6. LTM4675 MFR_ADDRESS Command Examples Expressed in 7- and 8-Bit Addressing**
|**DESCRIPTION**|**HEX DEVICE**<br>**ADDRESS**<br>**7 BIT 8 BIT**|**BIT**<br>**7**|**BIT**<br>**6**|**BIT**<br>**5**|**BIT**<br>**4**|**BIT**<br>**3**|**BIT**<br>**2**|**BIT**<br>**1**|**BIT**<br>**0**|**R/W**|
|---|---|---|---|---|---|---|---|---|---|---|
|Rail4|0x5A 0xB4|0|1|0|1|1|0|1|0|0|
|Global4|0x5B 0xB6|0|1|0|1|1|0|1|1|0|
|Default|0x4F<br>0x9E|0|1|0|0|1|1|1|1|0|
|Example 1|0x40<br>0x80|0|1|0|0|0|0|0|0|0|
|Example 2|0x41<br>0x82|0|1|0|0|0|0|0|1|0|
|Disabled2,3||1|0|0|0|0|0|0|0|0|
Note 1: This table can be applied to the MFR_RAIL_ADDRESS _n_ command, but not the MFR_ADDRESS command.
Note 2: A disabled value in one command does not disable the device, nor does it disable the Global address.
Note 3: A disabled value in one command does not inhibit the device from responding to device addresses specified in other commands.
Note 4: It is not recommended to write the value 0x00, 0x0C (7 bit), 0x5A (7 bit), 0x5B (7 bit), or 0x7C (7 bit) to the MFR_RAIL_ ADDRESS _n_ or MFR_ADDRESS commands.
where:
R/W = Read/Write bit in control byte.
All PMBus device addresses listed in the specification are 7 bits wide unless otherwise noted.
Note: The LTM4675 will always respond to slave address 0x5A and 0x5B regardless of the NVM or ASEL resistor configuration values.
*RASEL value indicated is nominal. Select RASEL from a resistor vendor such that its value is always within 3% of the value indicated in the table. Take into account resistor initial tolerance, T.C.R. and resistor operating temperatures, soldering heat/IR reflow, and endurance of the resistor over its lifetime. Thermal shock cycling, moisture (humidity) and other effects (depending on one’s specific application) could also affect RASEL’s value over time. All such effects must be taken into account in order for resistor pin-strapping to yield the expected result at every SVIN power-up and/or every execution of MFR_RESET or RESTORE_USER_ALL, over the lifetime of one’s product.
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LTM4675
## **APPLICATIONS INFORMATION**
## **VIN TO VOUT STEP-DOWN RATIOS**
There are restrictions in the maximum VIN and VOUT stepdown ratio that can be achieved for a given input voltage. Each output of the LTM4675 is capable of 95% duty cycle at 500kHz, but the VIN to VOUT minimum dropout is still a function of its load current and will limit output current capability related to high duty cycle on the topside switch. Minimum on-time t is another consideration in ON(MIN) operating at a specified duty cycle while operating at a certain frequency due to the fact that tON(MIN) < D/fSW, where D is duty cycle and fSW is the switching frequency. tON(MIN) is specified in the electrical parameters as 45ns. See Note 6 in the Electrical Characteristics section for output current guideline.
## **INPUT CAPACITORS**
The LTM4675 module should be connected to a low ACimpedance DC source. For the regulator input four 22µF input ceramic capacitors are used to handle the RMS ripple current. A 47µF to 100µF surface mount aluminum electrolytic bulk capacitor can be used for more input bulk capacitance. This bulk input capacitor is only needed if the input source impedance is compromised by long inductive leads, traces or not enough source capacitance. If low impedance power planes are used, then this bulk capacitor is not needed.
For a buck converter, the switching duty-cycle can be estimated as:
**==> picture [53 x 35] intentionally omitted <==**
## **OUTPUT CAPACITORS**
The LTM4675 is designed for low output voltage ripple noise and good transient response. The bulk output capacitors defined as COUT are chosen with low enough effective series resistance (ESR) to meet the output voltage ripple and transient requirements. COUT can be a low ESR tantalum capacitor, a low ESR polymer capacitor or ceramic capacitor. The typical output capacitance range for each output is from 400µF to 700µF. Additional output filtering may be required by the system designer, if further reduction of output ripple or dynamic transient spikes is required. Table 20 shows a matrix of different output voltages and output capacitors to minimize the voltage droop and overshoot during a 4.5A/µs transient. The table optimizes total equivalent ESR and total bulk capacitance to optimize the transient performance. Stability criteria are considered in the Table 20 matrix, and the Analog Devices µModule Power Design Tool will be provided for stability analysis. Multiphase operation reduces effective output ripple as a function of the number of phases. Analog Devices Application Note 77 discusses this noise reduction versus output ripple current cancellation, but the output capacitance should be considered carefully as a function of stability and transient response. The Analog Devices µModule Power Design Tool can calculate the output ripple reduction as the number of implemented phases increases by N times. A small value 10Ω resistor can be placed in series from VOUT _n_ to the VOSNS0[+] or VOSNS1 pin to allow for a bode plot analyzer to inject a signal into the control loop and validate the regulator stability.
## **LIGHT LOAD CURRENT OPERATION**
Without considering the inductor current ripple, for each output, the RMS current of the input capacitor can be estimated as:
**==> picture [179 x 31] intentionally omitted <==**
The LTM4675 has two modes of operation: high efficiency, discontinuous conduction mode or forced continuous conduction mode. The mode of operation is configured by bit 0 of the MFR_PWM_MODE _n_ command (discontinuous conduction is always the start-up mode, forced continuous is the default running mode).
In the above equation, η% is the estimated efficiency of the power module. The bulk capacitor can be a switcher-rated electrolytic aluminum capacitor, or a Polymer capacitor.
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LTM4675
## **APPLICATIONS INFORMATION**
If a channel is enabled for discontinuous mode operation, the inductor current is not allowed to reverse. The reverse current comparator, IREV , turns off the bottom MOSFET (MB _n_ ) just before the inductor current reaches zero, preventing it from reversing and going negative. Thus, the controller can operate in discontinuous (pulse-skippng) operation. In forced continuous operation, the inductor current is allowed to reverse at light loads or under large transient conditions. The peak inductor current is determined solely by the voltage on the COMP _n_ a pin. In this mode, the efficiency at light loads is lower than discontinuous mode operation. However, continuous mode exhibits lower output ripple and less interference with audio circuitry. Forced continuous conduction mode may result in reverse inductor current, which can cause the input supply to boost. The VIN_OV_FAULT_LIMIT can detect this (if SVIN is connected to VIN0 and/or VIN1) and turn off the offending channel. However, this fault is based on an ADC read and can nominally take up to 90ms to detect. If there is a concern about the input supply boosting, keep the part in discontinuous conduction operation.
## **SWITCHING FREQUENCY AND PHASE**
The switching frequency of the LTM4675’s channels is established by its analog phase-locked-loop (PLL) locking on to the clock present at the module’s SYNC pin. The clock waveform on the SYNC pin can be generated by the LTM4675’s internal circuitry when an external pull-up resistor to 3.3V (e.g., VDD33) is provided, in combination with the LTM4675 control IC’s FREQUENCY_SWITCH command being set to one of the following supported values: 250kHz, 350kHz, 425kHz, 500kHz, 575kHz, 650kHz, 750kHz, 1MHz (see Table 8 for hexadecimal values). In this configuration, the module is called a “sync master”: using the factory-default setting of MFR_CONFIG_ALL[4]=0b, SYNC becomes a bidirectional open-drain pin, and the LTM4675 pulls SYNC logic low for nominally 500ns at a time, at the prescribed clock rate. The SYNC signal can be bused to other LTM4675 modules (configured as “sync slaves”), for purposes of synchronizing switching frequencies of multiple modules
within a system—but only one LTM4675 should be configured as a “sync master”; the other LTM4675(s) should be configured as “sync slaves”.
There are two recommended ways to configure an LTM4675 as a “sync slave”:
- Apply an appropriate pin-strap resistor setting on the FSWPHCFG pin (see Table 4), and use the factory-default setting MFR_CONFIG_ALL[6] = 0b. This configures MFR_CONFIG_ALL[4] = 1b and FREQUENCY_SWITCH according to EEPROM settings (0xFBE8 factory default, corresponding to 500kHz). The LTM4675’s SYNC pin thus becomes a high impedance input and the module synchronizes its frequency to that of the externally applied clock, provided that the frequency of the externally applied clock exceeds ~45% of the target frequency (FREQUENCY_SWITCH). If the SYNC clock is absent, the module responds by operating at its target frequency, indefinitely. If and when the SYNC clock is restored, the module automatically phase-locks to the SYNC clock as normal.
- Set FREQUENCY_SWITCH to 0x0000 and MFR_ CONFIG_ALL[4]=1b. Using MFR_CONFIG_ALL[4]=1b, the LTM4675’s SYNC pin becomes a high impedance input, only—i.e., it does not drive SYNC low. The module synchronizes its frequency to that of the clock applied to its SYNC pin. The only shortcoming of this approach is: in the absence of an externally applied clock, the switching frequency of the module will default to the low end of its frequency-synchronization capture range (~225kHz).
The FREQUENCY_SWITCH command can be altered via I[2] C commands, but only when switching action is disengaged, i.e., the module’s outputs are turned off. The FREQUENCY_SWITCH command takes on the value stored in NVM at SVIN power-up, but is overridden according to a resistor pin-strap applied between the FSWPHCFG pin and SGND only if the module is configured to respect resistor pin-strap settings (MFR_CONFIG_ALL[6] = 0b). Table 4 highlights available resistor pin-strap and corresponding FREQUENCY_SWITCH settings.
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LTM4675
## **APPLICATIONS INFORMATION**
The relative phasing of all active channels in a PolyPhase rail should be optimally phased. The relative phasing of each rail is 360°/n, where n is the number of phases in the rail. MFR_PWM_CONFIG[2:0] configures channel relative phasing with respect to the SYNC pin. Phase relationship values are indicated with 0° corresponding to the falling edge of SYNC being coincident with the turn-on of the top MOSFETs, MT _n_ .
The MFR_PWM_CONFIG command can be altered via I[2] C commands, but only when switching action is disengaged, i.e., the module’s outputs are turned off. The MFR_PWM_CONFIG command takes on the value stored in NVM at SVIN power-up, but is overridden according to a resistor pin-strap applied between the FSWPHCFG pin and SGND only if the module is configured to respect resistor pin-strap settings (MFR_CONFIG_ALL[6] = 0b). Table 4 highlights available resistor pin-strap and corresponding MFR_PWM_CONFIG[2:0] settings.
Some combinations of FREQUENCY_SWITCH and MFR_PWM_CONFIG[2:0] are not available by resistor pin-strapping the FSWPHCFG pin. All combinations of supported values for FREQUENCY_SWITCH and MFR_PWM_CONFIG[2:0] can be configured by NVM programming—or, I[2] C transactions, provided switching action is disengaged, i.e., the module’s outputs are turned off.
Care must be taken to minimize capacitance on SYNC to assure that the pull-up resistor versus the capacitor load has a low enough time constant for the application to form a “clean” clock. (See “Open-Drain Pins”, later in this section.)
When an LTM4675 is configured as a sync slave, it is permissible for external circuitry to drive the SYNC pin from a current-limited source (less than 10mA), rather than using a pull-up resistor. Any external circuitry must not drive high with arbitrarily low impedance at SVIN power-up, because the SYNC output can be low impedance until NVM contents have been downloaded to RAM.
Recommended LTM4675 switching frequencies of operation for many common VIN-to-VOUT applications
are indicated in Table 7. When the two channels of an LTM4675 are stepping input voltage(s) down to output voltages whose recommended switching frequencies in Table 7 are significantly different, operation at the higher of the two recommended switching frequencies is preferable, but minimum on-time must be considered. (See Minimum On-Time Considerations section.) For example, consider an application in which it is desired for an LTM4675 to step-down 12VIN to 1VOUT on Channel 0, and 12VIN to 3.3VOUT on Channel 1: according to Table 7, the recommended switching frequency is 500kHz and 1MHz, respectively. However, the switching frequency setting of the LTM4675 is common to both channels. Based on the aforementioned guidance, operation at 1MHz would be preferred—in order to keep inductor ripple currents reasonable—however, it is then realized that the on-time for a 12VIN-to-1VOUT condition at 1MHz is only 83ns, shy of the 90ns guardband recommendation. Therefore, for this particular example, the recommended switching frequency becomes 750kHz.
**Table 7. Recommended Switching Frequency for Various VIN-to-VOUT Step-Down Scenarios**
||**5VIN**|**8VIN~ 12VIN**|
|---|---|---|
|0.9VOUT|425kHz|425kHz|
|1.0VOUT|500kHz|500kHz|
|1.2VOUT|500kHz|575kHz|
|1.5VOUT|575kHz|650kHz|
|1.8VOUT|650kHz|750kHz|
|2.5VOUT|650kHz|1MHz|
|3.3VOUT|650kHz|1MHz|
|5.0VOUT|N/A|1MHz|
The current drawn by the SVIN pin of the LTM4675 is not digitized or computed. A value representing the estimated SVIN current is located in the MFR_IIN_OFFSET _n_ command, and is used in the computations of input current readback telemetry, namely READ_IIN and and MFR_READ_IIN _n_ . The recommended setting of MFR_IIN_OFFSET _n_ is found in Table 8. The same value should be used for MFR_IIN_OFFSET0 and MFR_IIN_OFFSET1 (i.e., Pages 0x00 and 0x01).
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LTM4675
## **APPLICATIONS INFORMATION**
**Table 8. Recommended MFR_IIN_OFFSET** _**n**_ **Setting vs Switching Frequency Setting**
|**SWITCHING**<br>**FREQUENCY**<br>**(kHz)**|**FREQUENCY_**<br>**SWITCH**<br>**COMMAND**<br>**VALUE (HEX.)**|**RECOMMENDED**<br>**MFR_IIN_**<br>**OFFSET****_n_**<br>**SETTING (mA)**|**RECOMMENDED**<br>**MFR_IIN_**<br>**OFFSET****_n_**<br>**SETTING (HEX.)**|
|---|---|---|---|
|250|0xF3E8|20.26|0x8A98|
|350|0xFABC|23.98|0x8B12|
|425|0xFB52|26.77|0x8B6D|
|500|0xFBE8|29.56|0x8BC9|
|575|0x023F|32.35|0x9212|
|650|0x028A|35.14|0x9240|
|750|0x02EE|38.86|0x927D|
|1000|0x03E8|48.16|0x9315|
|Sync. to<br>External Clock,<br>fSYNC|N/A|0.372 • fSYNC+<br>10.96|*|
*See Appendix C: PMBus Command Details, L11 data format.
## **MINIMUM ON-TIME CONSIDERATIONS**
Minimum on-time, tON(MIN), is the smallest time duration that the LTM4675 is capable of turning on the top MOSFET. It is determined by internal timing delays and the gate charge required to turn on the top MOSFET. Low duty cycle applications may approach this minimum on-time limit and care should be taken to ensure that:
**==> picture [96 x 30] intentionally omitted <==**
If the duty cycle falls below what can be accommodated by the minimum on-time, the controller will begin to skip cycles. The output voltage will continue to be regulated, but the ripple voltage and current will increase.
The minimum on-time for the LTM4675 is 45ns, nominal, guardband to 90ns.
## **VARIABLE DELAY TIME, SOFT-START AND OUTPUT VOLTAGE RAMPING**
The LTM4675 must enter its run state prior to soft-start. The RUN _n_ pins are released after the part initializes and SVIN is greater than the VIN_ON threshold. If multiple LTM4675s are used in an application, they should be configured to share the same RUN _n_ pins. They all hold their respective RUN _n_ pins low until all devices initialize
and SVIN exceeds the VIN_ON threshold for all devices. The SHARE_CLK pin assures all the devices connected to the signal use the same time base.
After the RUN _n_ pin releases, the controller waits for the user-specified turn-on delay (TON_DELAY _n_ ) prior to initiating an output voltage ramp. Multiple LTM4675s and other ADI parts can be configured to start with variable delay times. To work correctly, all devices use the same timing clock (SHARE_CLK) and all devices must share the RUN _n_ pin. This allows the relative delay of all parts to be synchronized. The actual variation in the delay will be dependent on the highest clock rate of the devices connected to the SHARE_CLK pin (all Analog Devices ICs are configured to allow the fastest SHARE_CLK signal to control the timing of all devices). The SHARE_CLK signal can be ±7.5% in frequency, thus the actual time delays will have some variance.
Soft-start is performed by actively regulating the load voltage while digitally ramping the target voltage from 0V to the commanded voltage set point. The rise time of the voltage ramp can be programmed using the TON_RISE _n_ command to minimize inrush currents associated with the start-up voltage ramp. The soft-start feature is disabled by setting TON_RISE _n_ to any value less than 0.250ms. The LTM4675 performs the necessary math internally to assure the voltage ramp is controlled to the desired slope. However, the voltage slope can not be any faster than the fundamental limits of the power stage. The number of steps in the ramp is equal to TON_RISE/0.1ms. Therefore, the shorter the TON_RISE _n_ time setting, the more jagged the soft-start ramp appears.
The LTM4675 PWM always operates in discontinuous mode during the TON_RISE _n_ operation. In discontinuous mode, the bottom MOSFET (MB _n_ ) is turned off as soon as reverse current is detected in the inductor. This allows the regulator to start up into a pre-biased load.
There is no analog tracking feature in the LTM4675; however, two outputs can be given the same TON_RISE _n_ and TON_DELAY _n_ times to achieve ratiometric rail tracking. Because the RUN _n_ pins are released at the same time and both units use the same time base (SHARE_CLK), the outputs track very closely. If the circuit is in a PolyPhase configuration, all timing parameters must be the same.
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LTM4675
## **APPLICATIONS INFORMATION**
Coincident rail tracking can be achieved by setting two outputs to have the same turn-on/off slew rates, identical turn-on delays, and appropriately chosen turn-off delays:
**==> picture [239 x 30] intentionally omitted <==**
**==> picture [18 x 11] intentionally omitted <==**
**==> picture [239 x 30] intentionally omitted <==**
and
TON_DELAYRAIL1 = TON_DELAYRAIL2
and (if VOUT_COMMANDRAIL2 ≥ VOUT_COMMANDRAIL1)
**==> picture [97 x 13] intentionally omitted <==**
**==> picture [238 x 52] intentionally omitted <==**
or else (VOUT_COMMANDRAIL2 < VOUT_COMMANDRAIL1)
**==> picture [98 x 13] intentionally omitted <==**
**==> picture [236 x 51] intentionally omitted <==**
The described method of start-up sequencing is time based. For concatenated events it is possible to control the RUN pin based on the GPIO _n_ pin of a different controller (see Figure 2). The GPIO _n_ pin can be configured to release when the output voltage of the converter is greater than the VOUT_UV_FAULT_LIMIT _n_ . It is recommended to use the unfiltered VOUT UV fault limit because there is little appreciable time delay between the converter crossing the UV threshold and the GPIO _n_ pin releasing. The unfiltered output can be enabled by the MFR_GPIO_PROPAGATE _n_ [12] setting. (Refer to the MFR section of the PMBus commands in Appendix C: PMBus Command Details). The unfiltered signal may have some glitching as the VOUT signal transitions through the comparator threshold. A small digital filter of 250µs internally deglitches the GPIO _n_ pins. If the TON_RISE time is greater than 100ms, the deglitch
filter should be complimented with an externally applied capacitor between GPIO _n_ and ground—to further filter the waveform. The RC time-constant of the filter should be set sufficiently fast to assure no appreciable delay is incurred. For most applications, a value of 300µs to 500µs will provide sufficient filtering without significantly delaying the trigger event.
## **DIGITAL SERVO MODE**
For maximum accuracy in the regulated output voltage, enable the digital servo loop by asserting bit 6 of the MFR_PWM_MODE _n_ command. In digital servo mode, the LTM4675 adjusts the regulated output voltage based on the ADC voltage reading. Every 90ms the digital servo loop steps the LSB of the DAC (nominally 1.375mV or 0.6875mV depending on the voltage range bit, MFR_PWM_MODE _n_ [1]) until the output is at the correct ADC reading. At power-up this mode engages after TON_ MAX_FAULT_LIMIT _n_ unless the limit is set to 0 (infinite). If the TON_MAX_FAULT_LIMIT _n_ is set to 0 (infinite), the servo begins after TON_RISE _n_ is complete and VOUT _n_ has exceeded VOUT_UV_FAULT_LIMIT _n_ and IOUT_OC _n_ is not present. This same point in time is when the output changes from discontinuous to the mode commanded by MFR_PWM_MODE _n_ [0]. Refer to Figure 3 for details on the VOUT _n_ waveform under time based sequencing.
**==> picture [240 x 162] intentionally omitted <==**
**----- Start of picture text -----**<br>
RUN n<br>DIGITAL SERVO<br>MODE ENABLED FINAL OUTPUT<br>VOLTAGE REACHED<br>TON_MAX_FAULT_LIMIT n<br>VOUT_UV_FAULT_LIMIT n<br>DAC VOLTAGE TIME DELAY OF<br>VOUT n ERROR (NOT MANY SECONDS<br>TO SCALE)<br>TON_RISE n TIME 4675 F03<br>TON_DELAY n<br>**----- End of picture text -----**<br>
**Figure 3. Timing Controlled VOUT Rise**
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LTM4675
## **APPLICATIONS INFORMATION**
If the TON_MAX_FAULT_LIMIT _n_ is set to a value greater than 0 and the TON_MAX_FAULT_RESPONSE _n_ is set to ignore (0x00), the servo begins:
1. After the TON_RISE _n_ sequence is complete
2. After the TON_MAX_FAULT_LIMIT _n_ time is reached;
- and
3. After the VOUT_UV_FAULT_LIMIT _n_ has been exceed or the IOUT_OC_FAULT_LIMIT _n_ is no longer active.
If the TON_MAX_FAULT_LIMIT _n_ is set to a value greater than 0 and the TON_MAX_FAULT_RESPONSE _n_ is not set to ignore (0X00), the servo begins:
1. After the TON_RISE _n_ sequence is complete;
2. After the TON_MAX_FAULT_LIMIT _n_ time has expired and both VOUT_UV_FAULT _n_ and IOUT_OC_FAULT _n_ are not present.
The maximum rise time is limited to 1.3 seconds.
In a PolyPhase configuration it is recommended only one of the control loops have the digital servo mode enabled. This will assure the various loops do not work against each other due to slight differences in the reference circuits.
## **SOFT OFF (SEQUENCED OFF)**
In addition to a controlled start-up, the LTM4675 also supports controlled turn-off. The TOFF_DELAY _n_ and TOFF_FALL _n_ functions are shown in Figure 4. TOFF_FALL _n_ is processed when the RUN _n_ pin goes low or if the module is commanded off. If the module faults off or GPIO _n_ is pulled low externally and the module is programmed to respond to this (MFR_GPIO_RESPONSE _n_ = 0xC0), the
**==> picture [200 x 110] intentionally omitted <==**
**----- Start of picture text -----**<br>
RUN n<br>VOUT n<br>TOFF_DELAY n TOFF_FALL n TIME 4675 F04<br>**----- End of picture text -----**<br>
output three-states (becomes high impedance) rather than exhibiting a controlled ramp. The output then decays as a function of the load.
The output voltage operates as shown in Figure 4 so long as the part is in forced continuous mode and the TOFF_FALL _n_ time is sufficiently slow that the power stage can achieve the desired slope. The TOFF_FALL _n_ time can only be met if the power stage and controller can sink sufficient current to assure the output is at zero volts by the end of the fall time interval. If the TOFF_FALL _n_ time is set shorter than the time required to discharge the load capacitance, the output will not reach the desired zero volt state. At the end of TOFF_FALL _n_ , the controller ceases to sink current and VOUT _n_ decays at the natural rate determined by the load impedance. If the controller is in discontinuous mode, the controller does not pull negative current and the output becomes pulled low by the load, not the power stage. The maximum fail time is limited to 1.3 seconds. The number of steps in the ramp is equal to TOFF_FALL/0.1ms.Therefore, the shorter the TOFF_FALL _n_ setting, the more jagged the TOFF_FALL _n_ ramp appears.
## **UNDERVOLTAGE LOCKOUT**
The LTM4675 is initialized by an internal thresholdbased UVLO where SVIN must be approximately 4V and INTVCC, VDD33, VDD25 must be within approximately 20% of the regulated values. In addition, VDD33 must be within approximately 7% of the targeted value before the LTM4675 releases its RUN _n_ pins. After the part has initialized, an additional comparator monitors SVIN. The VIN_ON threshold must be exceeded before the power sequencing can begin. When SVIN drops below the VIN_OFF threshold, the LTM4675 ceases PWM action and SVIN must increase above the VIN_ON threshold before the controller will restart. The normal start-up sequence will be allowed after the VIN_ON threshold is crossed.
It is possible to program the contents of the NVM in the application if the VDD33 supply is externally driven. This activates the digital portion of the LTM4675 without engaging the high voltage sections. PMBus communications are valid in this supply configuration. If SVIN has not been applied to the LTM4675,
**Figure 4. TOFF_DELAY** _**n**_ **and TOFF_FALL** _**n**_
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LTM4675
## **APPLICATIONS INFORMATION**
MFR_COMMON[3] will be asserted low, indicating that NVM has not initialized. If this condition is detected, the part will only respond to addresses 0x5A and 0x5B. To initialize the part issue the following set of commands: global address 0x5B command 0xBD data 0x2B followed by global address 0x5B command 0xBD and data 0xC4. The part will now respond to the correct address. Configure the part as desired then issue a STORE_USER_ALL. When SVIN is applied a MFR_RESET or RESTORE_USER_ALL, command must be issued to allow the PWM to be enabled and valid ADC conversions to be read.
## **FAULT DETECTION AND HANDLING**
The LTM4675 GPIO _n_ pins are configurable to indicate a variety of faults including OV/UV, OC, OT, timing faults, peak overcurrent faults. In addition the GPIO _n_ pins can be pulled low by external sources to indicate to the LTM4675 the presence of a fault in some other portion of the system. The fault response is configurable via PMBus Command Code names with a _RESPONSE suffix and allows the following options:
- n Ignore
- n Shut Down Immediately—Latch Off
- n Shut Down Immediately—Retry Indefinitely at the Time Interval Specified in MFR_RETRY_DELAY _n_
Refer to Appendix C and the PMBus specification for more details.
The OV response is automatic and rapid. If an OV is detected, MT _n_ is turned off and BG _n_ is turned on, until the OV condition clears.
Fault logging is available on the LTM4675. The fault logging is configurable to automatically store data when a fault occurs that causes the unit to fault off. The header portion of the fault logging table contains peak values. It is possible to read these values at any time. This data will be useful while troubleshooting the fault.
If the LTM4675 internal temperature is in excess of 85°C or below 0°C, the write into the NVM is not recommended. The data will still be held in RAM, unless the 3.3V supply UVLO threshold is reached. If the die temperature exceeds 130°C all NVM communication is disabled until the die
temperature drops below 125°C, with the exception of the RESTORE_USER_ALL command, which is valid at any temperature.
## **OPEN-DRAIN PINS**
Note that up to nine pull-up resistors are required for proper operation of the LTM4675:
- Three for the SMBus/I[2] C interface (the SCL, SDA, and ALERT pins); two, only if the system SMBus host does not make use of the ALERT interrupt. (These are 5V tolerant).
- One each for the RUN0 and RUN1 pins (or, just one to RUN0 and RUN1, if RUN0 and RUN1 are electrically connected together). (These are 5V tolerant).
- One each for GPIO0 and GPIO1 (or, just one to GPIO0 and GPIO1, if GPIO0 and GPIO1 are electrically connected together). (These are 3.3V tolerant).
- One on SHARE_CLK, required, for the LTM4675 to establish a heartbeat time base for timing-related operations and functions (output voltage ramp-up timing, voltage margining transition timing, SYNC open-drain drive frequency). (SHARE CLK is 3.3V tolerant).
- One on SYNC, in order for the LTM4675 to phase lock to the frequency generated by the open-drain output of its digital engine. EXCEPTION: in some applications, it is desirable to drive the LTM4675’s SYNC pin with a hard-driven (low impedance) external clock. This is the only scenario where the LTM4675 does not require a pull-up resistor on SYNC. However, be aware that the SYNC pin can be low impedance during NVM initialization, i.e., during download of EEPROM contents to RAM (for ~50ms [Note 12] after SVIN power is applied). Therefore, the hard-driven clock signal should only be applied to the LTM4675 SYNC pin through a series resistor whose impedance limits current into the SYNC pin during NVM initialization to less than 10mA. If FREQUENCY_SWITCH=0x0000, any clock signal should be provided prior to the RUN _n_ pins toggle from logic low to logic high, or else the switching frequency of the LTM4675 will start off at the low end of its PLLcapture range (~225kHz) until the SYNC clock becomes established. (SYNC is 3.3V tolerant).
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LTM4675
## **APPLICATIONS INFORMATION**
All the above pins interface to pull-down transistors within the module that can sink 3mA at 0.4V. The low threshold on the pins is 0.8V; thus, plenty of margin on the digital signals with 3mA of current. For 3.3V pins, 3mA of current is a 1.1k resistor. Unless there are transient speed issues associated with the RC time constant of the resistor pullup and parasitic capacitance to ground, a 10k resistor or larger is generally recommended.
For high speed signals such as the SDA, SCL and SYNC, a lower value resistor may be required. The RC time constant should be set to 1/3 to 1/5 the required rise time to avoid timing issues. For a 100pF load and a 400kHz PMBus communication rate, the rise time must be less than 300ns. The resistor pull-up on the SDA and SCL pins with the time constant set to 1/3 the rise time:
**==> picture [113 x 28] intentionally omitted <==**
Be careful to minimize parasitic capacitance on the SDA and SCL pins to avoid communication problems. To estimate the loading capacitance, monitor the signal in question and measure how long it takes for the desired signal to reach approximately 63% of the output value. This is one time constant.
The SYNC pin interfaces to a pull-down transistor within the module whose output is held low for nominally 500ns per switching period. If the internal oscillator is set for 500kHz and the load is 100pF and a 3x time constant is required, the resistor calculation is as follows:
**==> picture [127 x 29] intentionally omitted <==**
The closest 1% resistor is 4.99k.
If timing errors are occurring or if the SYNC frequency is not as fast as desired, monitor the waveform and determine if the RC time constant is too long for the application. If possible reduce the parasitic capacitance. If not reduce the pull up resistor sufficiently to assure proper timing.
## **PHASE-LOCKED LOOP AND FREQUENCY SYNCHRONIZATION**
The LTM4675 has a phase-locked loop (PLL) comprised of an internal voltage-controlled oscillator (VCO) and a phase detector. The PLL is locked to the falling edge of the SYNC pin. The phase relationship between channel 0, channel 1 and the falling edge of SYNC is controlled by the lower 3 bits of the MFR_PWM_CONFIG command. For PolyPhase applications, it is recommended all the phases be spaced evenly. Thus for a 2-phase system the signals should be 180° out of phase and a 4-phase system should be spaced 90°.
The phase detector is an edge-sensitive digital type that provides a known phase shift between the external and internal oscillators. This type of phase detector does not exhibit false lock to harmonics of the external clock.
The output of the phase detector is a pair of complementary current sources that charge or discharge the internal filter network. The PLL lock range is guaranteed between 225kHz and 1.1MHz.
The PLL has a lock detection circuit. If the PLL should lose lock during operation, bit 4 of the STATUS_MFR_SPECIFIC command is asserted and the ALERT pin is pulled low. The fault can be cleared by writing a 1 to the bit. If the user does not wish to see the PLL_FAULT, even if a synchronization clock is not available at power up, bit 3 of the MFR_CONFIG_ALL command must be asserted.
If the SYNC signal is not clocking in the application, the PLL runs at the lowest free running frequency of the VCO. This will be well below the intended PWM frequency of the application and may cause undesirable operation of the converter.
If the PWM (SW _n_ ) signal appears to be running at too high a frequency, monitor the SYNC pin. Extra transitions on the falling edge will result in the PLL trying to lock on to noise instead of the intended signal. Review routing of digital control signals and minimize crosstalk to the SYNC signal to avoid this problem. Multiple LTM4675s are required to share the SYNC pin in PolyPhase
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LTM4675
## **APPLICATIONS INFORMATION**
configurations; for other configurations, it is optional. If the SYNC pin is shared between LTM4675s, only one LTM4675 can be programmed with a frequency output. All the other LTM4675s must be configured for external clock (MFR_CONFIG_ALL[4]=1b, and/or see Table 4).
## **RCONFIG PIN-STRAPS (EXTERNAL RESISTOR CONFIGURATION PINS)**
The LTM4675 default NVM is programmed to respect the RCONFIG pins. If a user wishes the output voltage, PWM frequency and phasing and the address to be set without programming the part or purchasing specially programmed parts, the RCONFIG pins can be used to establish these parameters—provided MFR_CONFIG_ ALL[6] = 0b. The RCONFIG pins only require a resistor terminating to SGND of the LTM4675. The RCONFIG pins are only monitored at initial power up and during a reset (MFR_RESET or RESTORE_USER_ALL) so modifying their values perhaps using a DAC after the part is powered will have no effect. To assure proper operation, the value of RCONFIG resistors applied to the LTM4675 pin-strapping pins must not deviate more than ±3% away from the target nominal values indicated in lookup Table 2 to Table 5, over the lifetime of the product. Thin film, 1% tolerance (or better), ±50ppm/°C-T.C.R. rated (or better) resistors from vendors such as KOA Speer, Panasonic, Vishay and Yageo are good candidates. Noisy clock signals should not be routed near these pins. Note that bits [3:0] of MFR_ADDRESS are dictated by the ASEL pin-strap resistor regardless of the setting of MFR_CONFIG_ALL[6].
## **VOLTAGE SELECTION**
When an output voltage is set using the RCONFIG pins on VOUT _n_ _CFG and VTRIM _n_ _CFG (MFR_CONFIG_ALL[6] = 0b), the following parameters are set as a percentage of the output voltage:
|•|VOUT_OV_FAULT_LIMIT|+10%|
|---|---|---|
|•|VOUT_OV_WARN|+7.5%|
|•|VOUT_MAX|+7.5%|
|•|VOUT_MARGIN_HI|+5%|
|•|VOUT_MARGIN_LO|–5%|
|•<br>•|VOUT_UV_WARN<br>VOUT_UV_FAULT_LIMIT|–6.5%<br>–7%|
## **CONNECTING THE USB TO THE I[2] C/SMBus/PMBus CONTROLLER TO THE LTM4675 IN SYSTEM**
The ADI USB to I[2] C/SMBus/PMBus controller can be interfaced to the LTM4675 on the user’s board for programming, telemetry and system debug. The controller, when used in conjunction with LTpowerPlay, provides a powerful way to debug an entire power system. Faults are quickly diagnosed using telemetry, fault status registers and the fault log. The final configuration can be quickly developed and stored to the LTM4675 EEPROM.
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LTM4675
## **APPLICATIONS INFORMATION**
Figure 5 and Figure 6 illustrate the application schematics for powering, programming and communicating with one or more LTM4675s via the ADI I[2] C/SMBus/PMBus controller regardless of whether or not system power is present. If system power is not present the dongle will power the LTM4675 through the VDD33 supply pin. To initialize the part when SVIN is not applied and the VDD33 pin is powered use global address 0x5B command 0xBD data 0x2B followed by address 0x5B command 0xBD data 0xC4. The part can now be communicated with, and the project file updated. To write the updated project file to the NVM issue a STORE_USER_ALL command. When SVIN is applied, a MFR_RESET or RESTORE_USER_ALL must be issued to allow the PWM to be enabled and valid ADCs to be read.
Because of the controllers limited current sourcing capability, only the LTM4675s, their associated pull-up resistors and the I[2] C pull-up resistors should be powered from the ORed 3.3V/3.4V supply. In addition, any device sharing the I[2] C bus connections with the LTM4675 must not have body diodes between the SDA/SCL pins and their respective VDD node because this will interfere with bus communication in the absence of system power. In Figure 5, the dongle will not bias the LTM4675s when SVIN is present. It is recommended the RUN _n_ pins be held low to avoid providing power to the load until the part is fully configured.
The ADI controller/adapter I[2] C connections are optoisolated from the PC USB. The 3.3V/3/4V from the controller/adapter and the LTM4675 VDD33 pin must be driven to each LTM4675 with a separate PFET or diode, according to Figure 5 and Figure 6. Only when SVIN is not applied is it permissible for the VDD33 pins to be electrically in parallel because the INTVCC LDO is off. The DC1613’s 3.3V current limit is 100mA but typical VDD33 currents are under 15mA. The VDD33 does back drive the INTVCC pin. Normally this is not an issue if SVIN is open. The DC2086 is capable of delivering 3.4V at 2A.
Using a 4-pin header in Figure 5 or Figure 6 maximizes flexibility to alter the LTM4675’s NVM contents at any stage of the user’s product development and production cycles. If the LTM4675’s NVM is “pre-programmed”, i.e., contains its finalized configuration, prior to being soldered to the user’s PCB/motherboard—or, if other means have been provided for altering the LTM4675's NVM contents in the user’s system—then the 3.3V/3.4V pin on the header is not needed, and a 3-pin header is sufficient to establish GUI communications. The LTM4675 can be purchased with customized NVM contents; consult factory for details. Alternatively, the NVM contents of the LTM4675 can be configured in a mass production environment by designing for it in ICT (in-circuit test), or by providing a means of applying SVIN while holding the LTM4675’s RUN pins low. Communication to the module must be made possible via the SCL and SDA pins/nets in all NVM programming scenarios. Recommended headers are found in Table 9 and Table 10.
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LTM4675
## **APPLICATIONS INFORMATION**
**==> picture [333 x 252] intentionally omitted <==**
**----- Start of picture text -----**<br>
MODULE PROGRAMMING VIN<br>AND COMMUNICATION 100k 100k<br>INTERFACE HEADER SVIN<br>ISOLATED 3.4V<br>(USUALLY NEEDED)<br>SEE TABLES 9-13 FOR VDD33 VDD25<br>CONNECTOR AND SCL TP0101K<br>PINOUT OPTIONS SOT-23 LTM4675<br>10k<br>SCL<br>SDA<br>10k<br>SDA<br>TO LTC DC2086 DIGITAL WP SGND<br>POWER PROGRAMMING<br>ADAPTER (REQUIRES LTC<br>DC1613 USB TO I [2] C/SMBus/<br>PMBus CONTROLLER)<br>SVIN<br>VGS MAX ON THE TP0101K IS 8V. IF VIN > 16V,<br>CHANGE THE RESISTOR DIVIDER ON THE PFET GATE VDD33 VDD25<br>ALTERNATE PFETS/PACKAGES: TP0101K<br>SOT-723: GOOD-ARK SEMI SSF2319GE SOT-23 LTM4675<br>ON SEMI NTK3139PT1G<br>ROHM RZM002P02T2L ••• SCL<br>SOT-523: DIODES INC. DMG1013T-7<br>SDA<br>GOOD-ARK SEMI SSF2319GD<br>SOT-563: DIODES INC. DMP2104V-7 WP SGND<br>ON SEMI NTZS3151PT1G 4675 F05<br>SOT-323: DIODES INC. DMG1013UW-7ON SEMI NTS2101PT1G •••<br>VISHAY Si1303DL-T1-E3<br>**----- End of picture text -----**<br>
**Figure 5. Circuit Suitable for Programming EEPROM/NVM of LTM4675 and Other ADI PSM Modules/ICs in Vast Systems, Even When VIN Power is Absent, 0°C < TJ ≤ 85°C**
**==> picture [288 x 240] intentionally omitted <==**
**----- Start of picture text -----**<br>
MODULE PROGRAMMING VIN<br>AND COMMUNICATION<br>INTERFACE HEADER SVIN<br>ISOLATED 3.4V<br>(USUALLY NEEDED)<br>SEE TABLES 9-13 FOR VDD33 VDD25<br>CONNECTOR AND SCL<br>PINOUT OPTIONS D1 LTM4675<br>SOD882 10k<br>SCL<br>SDA<br>10k<br>SDA<br>TO LTC DC2086 DIGITAL WP SGND<br>POWER PROGRAMMING<br>ADAPTER (REQUIRES LTC<br>DC1613 USB TO I [2] C/SMBus/<br>PMBus CONTROLLER) D2 SVIN<br>SOD882<br>VDD33 VDD25<br>LTM4675<br>•••<br>SCL<br>D1, D2: NXP PMEG2005AEL OR PMEG2005AELD.<br>DIODE SELECTION IS NOT ARBITRARY.<br>SDA<br>USE VF < 210mV AT IF = 20mA WP SGND<br>••• 4675 F06<br>**----- End of picture text -----**<br>
**Figure 6. Circuit Suitable for Programming EEPROM/NVM of LTM4675 and Other ADI PSM Modules/ICs in Vast Systems, Even When VIN Power is Absent, TA > 20°C and TJ < 85°C**
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LTM4675
## **APPLICATIONS INFORMATION**
**Table 9. 4-Pin Headers, 2mm Pin-to-Pin Spacing, Gold Flash or Plating, Compatible with DC2086 Cables**
|**MOUNTING**<br>**STYLE**|**INSERTION**<br>**ANGLE**|**INTERFACE STYLE**|**VENDOR**|**PART NUMBER**|**PINOUT STYLE(SEE TABLE 11)**|
|---|---|---|---|---|---|
|Surface Mount|Vertical|Shrouded and Keyed Header|Hirose|DF3DZ-4P-2V(51)<br>DF3DZ-4P-2V(50)<br>DF3Z-4P-2V(50)|Type A|
|||Non Shrouded,Non-Keyed Header|3M|951104-2530-AR-PR|Type A and B Supported. Reversible/Not Keyed|
||Right Angle|Shrouded and Keyed Header|Hirose|DF3DZ-4P-2H(51)<br>DF3DZ-4P-2H(50)|Type A|
|||Non Shrouded. Cable-to-Header/PCB<br>Mechanics Yield KeyingEffect|FCI|10112684-G03-04ULF|Type B. Keying Achieved by PCB Surface|
|Through-Hole|Vertical|Shrouded and Keyed Header|Hirose|DF3-4P-2DSA(01)|Type A|
|||Non Shrouded, Non-Keyed Header|Harwin|M22-2010405|Type A and B Supported. Reversible/Not Keyed|
||||Samtec|TMM-104-01-LS||
||||Sullins|NRPN041PAEN-RC||
||Right Angle|Shrouded and Keyed Header|Hirose|DF3-4P-2DS(01)|Type A|
|||Non Shrouded. Cable-to-Header/PCB<br>Mechanics Yield Keying Effect|Norcomp|27630402RP2|Type B. Keying Achieved by Intentional PCB<br>Interference|
||||Harwin|M22-2030405||
||||Samtec|TMM-104-01-L-S-RA||
**Table 10. 3-Pin Headers, 2mm Pin-to-Pin Spacing, Gold Flash or Plating, Compatible with DC2086 Cables**
|**MOUNTING**<br>**STYLE**|**INSERTION**<br>**ANGLE**|**INTERFACE STYLE**|**VENDOR**|**PART NUMBER**|**PINOUT STYLE(SEE TABLE 12)**|
|---|---|---|---|---|---|
|Surface Mount|Vertical|Shrouded and Keyed Header|Hirose|DF3DZ-3P-2V(51)<br>DF3DZ-3P-2V(50)<br>DF3Z-3P-2V(50)|Type A|
|||Non Shrouded,Non-Keyed Header|3M|951103-2530-AR-PR|Type A and B Supported. Reversible/Not Keyed|
||Right Angle|Shrouded and Keyed Header|Hirose|DF3DZ-3P-2H(51)<br>DF3DZ-3P-2H(50)|Type A|
|||Non Shrouded. Cable-to-Header/PCB<br>Mechanics Yield KeyingEffect|FCI|10112684-G03-03LF|Type B. Keying Achieved by PCB Surface|
|Through-Hole|Vertical|Shrouded and Keyed Header|Hirose|DF3-3P-2DSA(01)|Type A|
|||Non Shrouded, Non-Keyed Header|Harwin|M22-2010305|Type A and B Supported. Reversible/Not Keyed|
||||Samtec|TMM-103-01-LS||
||||Sullins|NRPN031PAEN-RC||
||Right Angle|Shrouded and Keyed Header|Hirose|DF3-3P-2DS(01)|Type A|
|||Non Shrouded. Cable-to-Header/PCB<br>Mechanics Yield Keying Effect|Norcomp|27630302RP2|Type B. Keying Achieved by Intentional PCB<br>Interference|
||||Harwin|M22-2030305||
||||Samtec|TMM-103-01-L-S-RA||
**Table 11. Recommended 4-Pin Header Pinout (Pin Numbering Scheme Adheres to Hirose Conventions). Interfaces to DC2086 Cables**
**Table 12. Recommended 3-Pin Header Pinout (Pin Numbering Scheme Adheres to Hirose Conventions). Interfaces to DC2086 Cables**
|<br>**Cables**||||<br>**Cables**|||
|---|---|---|---|---|---|---|
|**PIN NUMBER**|**PINOUT STYLE “A”**<br>**(SEE TABLE 9)**|**PINOUT STYLE “B”**<br>**(SEE TABLE 9)**||**PIN NUMBER**|**PINOUT STYLE “A”**<br>**(SEE TABLE 10)**|**PINOUT STYLE “B”**<br>**(SEE TABLE 10)**|
|1|SDA|Isolated 3.3V/3.4V||1|SDA|SCL|
|2|GND|SCL||2|GND|GND|
|3|SCL|GND||3|SCL|SDA|
|4|Isolated 3.3V/3.4V|SDA|||||
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LTM4675
## **APPLICATIONS INFORMATION**
**Table 13. 4-Pin Male-to-Male Shrouded and Keyed Adapter (Optional. Eases Creation of Adapter Cables, if Deviating from Recommended Connectors/Connector Pinouts). Interfaces to DC2086 Cables**
|**VENDOR**|**PART NUMBER**|**WEBSITE**|
|---|---|---|
|Hirose|DF3-4EP-2A|www.hirose.com, www.hirose.co.jp|
## **LTpowerPlay: AN INTERACTIVE GUI FOR DIGITAL POWER SYSTEM MANAGEMENT**
LTpowerPlay is a powerful Windows-based development environment that supports Analog Devices digital power ICs including the LTM4675. The software supports a variety of different tasks. LTpowerPlay can be used to evaluate Analog Devices ICs by connecting to a demo board or the user application. LTpowerPlay can also be used in an offline mode (with no hardware present) in order to build multiple
IC configuration files that can be saved and reloaded at a later time. LTpowerPlay provides unprecedented diagnostic and debug features. It becomes a valuable diagnostic tool during board bring-up to program or tweak the power system or to diagnose power issues when bringing up rails. LTpowerPlay utilizes Analog Devices’s USB-to-I[2] C/ SMBus/PMBus controller to communication with one of the many potential targets including the DC2053 (single LTM4675), DC1811 (single LTM4676A) or DC1989B (dual, triple, quad LTM4676A) demo boards, or a customer target system. The software also provides an automatic update feature to keep the revisions current with the latest set of device drivers and documentation. A great deal of context sensitive help is available with LTpowerPlay along with several tutorial demos. Complete information is available at LTpowerPlay.
**Figure 7. LTPowerPlay**
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LTM4675
## **APPLICATIONS INFORMATION**
**==> picture [253 x 125] intentionally omitted <==**
**----- Start of picture text -----**<br>
CMD WRITE COMMAND<br>PMBus DATA BUFFER<br>DECODER<br>WRITE INTERNAL<br>PAGE 0x00<br>PROCESSOR<br>CMDS ••• FETCH,<br>CONVERT<br>0x21<br>DATA VOUT_COMMAND DATA<br>MUX AND<br>••• EXECUTE<br>MFR_RESET 0xFD<br>CALCULATIONS S x1<br>PENDING R 4675 F08<br>**----- End of picture text -----**<br>
**Figure 8. Write Command Data Processing**
## **PMBus COMMUNICATION AND COMMAND PROCESSING**
The LTM4675 has one deep buffer to hold the last data written for each supported command prior to processing as shown in Figure 8; Write Command Data Processing. When the part receives a new command from the bus, it copies the data into the Write Command Data Buffer, indicates to the internal processor that this command data needs to be fetched, and converts the command to its internal format so that it can be executed.
Two distinct parallel blocks manage command buffering and command processing (fetch, convert, and execute) to ensure the last data written to any command is never lost. Command data buffering handles incoming PMBus writes by storing the command data to the Write Command Data Buffer and marking these commands for future processing. The internal processor runs in parallel and handles the sometimes slower task of fetching, converting and executing commands marked for processing.
Some computationally intensive commands (e.g., timing parameters, temperatures, voltages and currents) have internal processor execution times that may be long relative to PMBus timing. If the part is busy processing a command, and new command(s) arrive, execution may be delayed or processed in a different order than received. The part indicates when internal calculations are in process via bit 5 of MFR_COMMON (‘calculations not pending’). When the part is busy calculating, bit 5 is cleared. When this bit is set, the part is ready for another command. An example polling loop is provided in Figure 8 which ensures that commands are processed in order while simplifying error handling routines.
When the part receives a new command while it is busy, it will communicate this condition using standard PMBus protocol. Depending on part configuration it may either NACK the command or return all ones (0xFF) for reads. It may also generate a BUSY fault and ALERT notification, or stretch the SCL clock low. For more information refer to PMBus Specification v1.2, Part II, Section 10.8.7 and SMBus v2.0 section 4.3.3. Clock stretching can be enabled by asserting bit 1 of MFR_CONFIG_ALL. Clock stretching will only occur if enabled and the bus communication speed exceeds 100kHz.
PMBus busy protocols are well accepted standards, but can make writing system level software somewhat complex. The part provides three ‘hand shaking’ status bits which reduce complexity while enabling robust system level communication.
The three hand shaking status bits are in the MFR_ COMMON register. When the part is busy executing an internal operation, it will clear bit 6 of MFR_COMMON (‘module not busy’). When the part is busy specifically because it is in a transitional VOUT state (margining hi/lo, power off/on, moving to a new output voltage set point, etc.) it will clear bit 4 of MFR_COMMON (‘output not in transition’). When internal calculations are in process, the part will clear bit 5 of MFR_COMMON (‘calculations not pending’). These three status bits can be polled with a PMBus read byte of the MFR_COMMON register until all three bits are set. A command immediately following the status bits being set will be accepted without NACKing or generating a BUSY fault/ALERT notification. The part can NACK commands for other reasons, however, as required by the PMBus spec (for instance, an invalid command or data). An example of a robust command write algorithm for the VOUT_COMMAND _n_ register is provided in Figure 9.
- `// wait until bits 6, 5, and 4 of MFR_COMMON are all set do { mfrCommonValue = PMBUS_READ_BYTE(0xEF); partReady = (mfrCommonValue & 0x68) == 0x68;`
- `}while (!partReady)`
```
// now the part is ready to receive the next command
PMBUS_WRITE_WORD(0x21, 0x2000); //write VOUT_COMMAND to 2V
```
**Figure 9. Example of a Command Write of VOUT_COMMAND**
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LTM4675
## **APPLICATIONS INFORMATION**
It is recommended that all command writes (write byte, write word, etc.) be preceded with a polling loop to avoid the extra complexity of dealing with busy behavior and unwanted ALERT notification. A simple way to achieve this is by creating SAFE_WRITE_BYTE() and SAFE_WRITE_ WORD() subroutines. The above polling mechanism allows one’s software to remain clean and simple while robustly communicating with the part. For a detailed discussion of these topics and other special cases please refer to Analog Devices Application Notes section.
When communicating using bus speeds at or below 100kHz, the polling mechanism shown here provides a simple solution that ensures robust communication without clock stretching. At bus speeds in excess of 100kHz, it is strongly recommended that the part be configured to enable clock stretching. This requires a PMBus master that supports clock stretching. System software that detects and properly recovers from the standard PMBus NACK/ BUSY faults as described in the PMBus Specification v1.2, Part II, Section 10.8.7 is required to communicate above 100kHz without clock stretching. Clock stretching will not extend the PMBus speed beyond the specified 400kHz.
## **THERMAL CONSIDERATIONS AND OUTPUT CURRENT DERATING**
The thermal resistances reported in the Pin Configuration section of this data sheet are consistent with those parameters defined by JESD51-12 and are intended for use with finite element analysis (FEA) software modeling tools that leverage the outcome of thermal modeling, simulation, and correlation to hardware evaluation performed on a µModule package mounted to a hardware test board. The motivation for providing these thermal coefficients is found in JESD51-12 (“Guidelines for Reporting and Using Electronic Package Thermal Information”).
Many designers may opt to use laboratory equipment and a test vehicle such as the demo board to predict the µModule regulator’s thermal performance in their application at various electrical and environmental operating conditions to compliment any FEA activities. Without FEA software, the thermal resistances reported in the Pin Configuration section are, in and of themselves, not relevant to
providing guidance of thermal performance; instead, the derating curves provided in this data sheet can be used in a manner that yields insight and guidance pertaining to one’s application-usage, and can be adapted to correlate thermal performance to one’s own application.
The Pin Configuration section gives four thermal coefficients explicitly defined in JESD51-12; these coefficients are quoted or paraphrased below:
1. θJA, the thermal resistance from junction to ambient, is the natural convection junction-to-ambient air thermal resistance measured in a one cubic foot sealed enclosure. This environment is sometimes referred to as “still air” although natural convection causes the air to move. This value is determined with the part mounted to a JESD51-9 defined test board, which does not reflect an actual application or viable operating condition.
2. θJCbottom, the thermal resistance from junction to the bottom of the product case, is determined with all of the component power dissipation flowing through the bottom of the package. In the typical µModule regulator, the bulk of the heat flows out the bottom of the package, but there is always heat flow out into the ambient environment. As a result, this thermal resistance value may be useful for comparing packages but the test conditions don’t generally match the user’s application.
3. θJCtop, the thermal resistance from junction to top of the product case, is determined with nearly all of the component power dissipation flowing through the top of the package. As the electrical connections of the typical µModule regulator are on the bottom of the package, it is rare for an application to operate such that most of the heat flows from the junction to the top of the part. As in the case of θJCbottom, this value may be useful for comparing packages but the test conditions don’t generally match the user’s application.
4. θJB, the thermal resistance from junction to the printed circuit board, is the junction-to-board thermal resistance where almost all of the heat flows through the bottom of the µModule regulator and into the board, and is really the sum of the θJCbottom and the thermal resistance of the bottom of the part through the solder joints and through a portion of the board. The board
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LTM4675
## **APPLICATIONS INFORMATION**
temperature is measured a specified distance from the package, using a two sided, two layer board. This board is described in JESD51-9.
A graphical representation of the aforementioned thermal resistances is given in Figure 10; blue resistances are contained within the µModule regulator, whereas green resistances are external to the µModule package.
As a practical matter, it should be clear to the reader that no individual or sub-group of the four thermal resistance parameters defined by JESD51-12 or provided in the Pin Configuration section replicates or conveys normal operating conditions of a µModule regulator. For example, in normal board-mounted applications, never does 100% of the device’s total power loss (heat) thermally conduct exclusively through the top or exclusively through bottom of the µModule package—as the standard defines for θJCtop and θJCbottom, respectively. In practice, power loss is thermally dissipated in both directions away from the package—granted, in the absence of a heat sink and airflow, a majority of the heat flow is into the board.
Within the LTM4675, be aware there are multiple power devices and components dissipating power, with a consequence that the thermal resistances relative to different junctions of components or die are not exactly linear with respect to total package power loss. To reconcile this complication without sacrificing modeling simplicity—but also not ignoring practical realities—an approach has been taken using FEA software modeling along with laboratory testing in a controlled-environment chamber to reason-
ably define and correlate the thermal resistance values supplied in this data sheet: (1) Initially, FEA software is used to accurately build the mechanical geometry of the LTM4675 and the specified PCB with all of the correct material coefficients along with accurate power loss source definitions; (2) this model simulates a softwaredefined JEDEC environment consistent with JESD51-9 and JESD51-12 to predict power loss heat flow and temperature readings at different interfaces that enable the calculation of the JEDEC-defined thermal resistance values; (3) the model and FEA software is used to evaluate the LTM4675 with heat sink and airflow; (4) having solved for and analyzed these thermal resistance values and simulated various operating conditions in the software model, a thorough laboratory evaluation replicates the simulated conditions with thermocouples within a controlled environment chamber while operating the device at the same power loss as that which was simulated. The outcome of this process and due diligence yields the set of derating curves provided in later sections of this data sheet, along with well-correlated JESD51-12-defined θ values provided in the Pin Configuration section of this data sheet.
The 1V, 1.8V and 3.3V power loss curves in Figure 11, Figure 12 and Figure 13 respectively can be used in coordination with the load current derating curves in Figures 14 to 25 for calculating an approximate θJA thermal resistance for the LTM4675 with various heat sinking and air flow conditions. These thermal resistances represent demonstrated performance of the LTM4675 on DC2053A hardware; a 4-layer FR4 PCB measuring
**==> picture [396 x 164] intentionally omitted <==**
**----- Start of picture text -----**<br>
JUNCTION-TO-AMBIENT THERMAL RESISTANCE COMPONENTS<br>JUNCTION-TO-CASE (TOP) CASE (TOP)-TO-AMBIENT<br>RESISTANCE RESISTANCE<br>JUNCTION-TO-BOARD RESISTANCE<br>JUNCTION AMBIENT<br>JUNCTION-TO-CASE CASE (BOTTOM)-TO-BOARD BOARD-TO-AMBIENT<br>(BOTTOM) RESISTANCE RESISTANCE RESISTANCE<br>4675 F10<br>µMODULE DEVICE<br>**----- End of picture text -----**<br>
**Figure 10. Graphical Representation of JESD51-12 Thermal Coefficients**
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LTM4675
## **APPLICATIONS INFORMATION**
99mm × 133mm × 1.6mm using outer and inner copper weights of 2oz and 1oz, respectively. The power loss curves are taken at room temperature, and are increased with multiplicative factors with ambient temperature. These approximate factors are listed in Table 14. (Compute the factor by interpolation, for intermediate temperatures.) The derating curves are plotted with the LTM4675’s paralleled outputs initially sourcing up to 18A and the ambient temperature at 30°C. The output voltages are 1V, 1.8V and 3.3V. These are chosen to include the lower and higher output voltage ranges for correlating the thermal resistance. Thermal models are derived from several temperature measurements in a controlled temperature chamber along with thermal modeling analysis. The junction temperatures are monitored while ambient temperature is increased with and without air flow, and with and without a heat sink attached with thermally conductive adhesive tape. The power loss increase with ambient temperature change is factored into the derating curves. The junctions are maintained at 120°C maximum while lowering output current or power while increasing ambient temperature. The decreased output current decreases the internal module loss as ambient temperature is increased. The monitored junction temperature of 120°C minus the ambient operating temperature specifies how much module temperature rise can be allowed. As an example in Figure 19, the load current is derated to ~12A at ~65°C ambient with 200LFM airflow and no heat sink and the room temperature (25°C) power loss for this 12VIN to 1VOUT at 12AOUT condition is ~3.6W. A 4.05W loss is calculated by multiplying the ~3.6W room temperature loss from the 12VIN to 1.8VOUT power loss curve at 12A (Figure 12), with the 1.125
multiplying factor at 65°C ambient (from Table 14). If the 65°C ambient temperature is subtracted from the 120°C junction temperature, then the difference of 55°C divided by 4.05W yields a thermal resistance, θJA, of 13.6°C/W— in good agreement with Table 16. Table 15, Table 16 and Table 17 provide equivalent thermal resistances for 1V, 1.8V and 3.3V outputs with and without air flow and heat sinking. The derived thermal resistances in Table 15, Table 16 and Table 17 for the various conditions can be multiplied by the calculated power loss as a function of ambient temperature to derive temperature rise above ambient, thus maximum junction temperature. Room temperature power loss can be derived from the efficiency curves in the Typical Performance Characteristics section and adjusted with ambient temperature multiplicative factors from Table 14.
**Table 14. Power Loss Multiplicative Factors vs Ambient Temperature**
|<br>**Temperature**||
|---|---|
|**AMBIENT TEMPERATURE**|**POWER LOSS MULTIPLICATIVE**<br>**FACTOR**|
|Up to 40°C|1.00|
|50°C|1.05|
|60°C|1.10|
|70°C|1.15|
|80°C|1.20|
|90°C|1.25|
|100°C|1.30|
|110°C|1.35|
|120°C|1.40|
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LTM4675
## **APPLICATIONS INFORMATION**
## **Table 15. 1.0V Output**
|**Table 15. 1.0V Output**||||||
|---|---|---|---|---|---|
|**DERATING CURVE**|**VIN (V)**|**POWER LOSS CURVE**|**AIRFLOW(LFM)**|**HEAT SINK**|θ**JA (°C/W)**|
|Figures 14,15|5,12|Figure 11|0|None|16.1|
|Figures 14,15|5,12|Figure 11|200|None|12.3|
|Figures 14,15|5,12|Figure 11|400|None|11.2|
|Figures 16,17|5,12|Figure 11|0|BGA Heat Sink|14.8|
|Figures 16,17|5,12|Figure 11|200|BGA Heat Sink|11.4|
|Figures 16,17|5,12|Figure 11|400|BGA Heat Sink|10.3|
## **Table 16. 1.8V Output**
|**Table 16. 1.8V Output**||||||
|---|---|---|---|---|---|
|**DERATING CURVE**|**VIN (V)**|**POWER LOSS CURVE**|**AIRFLOW(LFM)**|**HEAT SINK**|θ**JA (°C/W)**|
|Figures 18,19|5,12|Figure 12|0|None|16.4|
|Figures 18,19|5,12|Figure 12|200|None|13.4|
|Figures 18,19|5,12|Figure 12|400|None|12.3|
|Figures 20,21|5,12|Figure 12|0|BGA Heat Sink|15.4|
|Figures 20,21|5,12|Figure 12|200|BGA Heat Sink|12.6|
|Figures 20,21|5,12|Figure 12|400|BGA Heat Sink|11.4|
## **Table 17. 3.3V Output**
|**Table 17. 3.3V Output**||||||
|---|---|---|---|---|---|
|**DERATING CURVE**|**VIN (V)**|**POWER LOSS CURVE**|**AIRFLOW(LFM)**|**HEAT SINK**|θ**JA (°C/W)**|
|Figure 22,23|5,12|Figure 13|0|None|15.9|
|Figure 22,23|5,12|Figure 13|200|None|13.1|
|Figure 22,23|5,12|Figure 13|400|None|11.8|
|Figure 24,25|5,12|Figure 13|0|BGA Heat Sink|15.0|
|Figure 24,25|5,12|Figure 13|200|BGA Heat Sink|12.2|
|Figure 24,25|5,12|Figure 13|400|BGA Heat Sink|11.1|
**Table 18. Heat Sink Manufacturer (Thermally Conductive Adhesive Tape Pre-Attached)**
|**HEAT SINK MANUFACTURER**|**PART NUMBER**|**WEBSITE**|
|---|---|---|
|Cool Innovations|3-0504035UT411|www.coolinnovations.com|
## **Table 19. Thermally Conductive Adhesive Tape Vendor**
|**THERMALLY CONDUCTIVE ADHESIVE**<br>**TAPE MANUFACTURER**|**PART NUMBER**|**WEBSITE**|
|---|---|---|
|Chomerics|T411|www.chomerics.com|
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## **APPLICATIONS INFORMATION**
## **Table 20. LTM4675 Channel Output Voltage Response vs Component Matrix. 4.5A Load-Stepping at 4.5A/µs. Typical Measured Values**
|**COUTH VENDORS **|**COUTH VENDORS **|**COUTH VENDORS **|**PART NUMBER**<br><br>|**PART NUMBER**<br><br>|**PART NUMBER**<br><br>|**PART NUMBER**<br><br>|**PART NUMBER**<br><br>|**COUTL**<br>**VENDORS**|**COUTL**<br>**VENDORS**|**PART NUMBER**|**PART NUMBER**|**PART NUMBER**|**PART NUMBER**|**PART NUMBER**|**PART NUMBER**|
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|AVX|||12106D107MAT2A(100μF, 6.3V, 1210 Case Size)<br>|||||Sanyo POSCAP||6TPF330M9L(330μF, 6.3V, 9mΩ ESR, D3L Case Size)||||||
|Murata|||GRM32ER60J107ME20L(100μF, 6.3V, 1210 Case Size)|||||Sanyo POSCAP||6TPD470M(470μF, 6.3V, 10mΩ ESR, D4D Case Size)||||||
|Taiyo Yuden|||JMK325BJ107MM-T(100μF, 6.3V, 1210 Case Size)<br>|||||Sanyo POSCAP||2R5TPE470M9(470μF, 2.5V, 9mΩ ESR, D2E Case Size)||||||
|TDK|||C3225X5R0J107MT(100μF, 6.3V, 1210 Case Size)<br>|||||Sanyo POSCAP||6TPF470MAH(470μF, 6.3V, 10mΩ ESR, D4 Case Size)||||||
|||||||||||||||||
|**VOUT****_n_**<br>**(V)**|**VIN****_n_**<br>**(V)**|**REF.**<br>**CIRCUIT***||**COUTH****_n_**<br>**(CERAMIC**<br>**OUTPUT**<br>**CAP)**|**COUTL****_n_**<br>**(BULK**<br>**OUTPUT**<br>**CAP)**|**CONNECT**<br>**COMP****_n_a TO**<br>**COMP****_n_b? **<br>**(INTERNAL LOOP**<br>**COMP)**|**RTH****_n_**<br>**(EXT**<br>**LOOP**<br>**COMP)**<br>**(kΩ)**|<br>**CTH****_n_**<br>**(EXT**<br>**LOOP**<br>**COMP)**<br>**(nF)**|<br>**fSW**<br>**(kHz)**|**FSWPHCFG**<br>**PIN-**<br>**STRAP,**<br>**RESISTOR**<br>**TO SGND**<br>**(Table 4)**<br>**(kΩ)**|**VOUT****_n_ CFG**<br>**PIN-**<br>**STRAP**<br>**RESISTOR**<br>**TO SGND**<br>**(Table 2)**<br>**(kΩ)**|**VTRIM****_n_CFG**<br>**PIN-**<br>**STRAP,**<br>**RESISTOR**<br>**TO SGND**<br>**(Table 3)**<br>**(kΩ)**|<br>**TRANS-**<br>**IENT**<br>**DROOP**<br>**(0A TO**<br>**4.5A)**<br>**(mV)**|**PK-PK**<br>**DEVI-**<br>**ATION**<br>**(0A TO**<br>**4.5A**<br>**TO 0A)**<br>**(mV)**|**RECOV-**<br>**ERY**<br>**TIME**<br>**(µs)**|
|0.9|5|Test Ckt. 2||100µF×4|None|Yes, cf. Figure 61|N/A|N/A|425|18.0|1.65|None|37|76|45|
|0.9|5|Test Ckt. 2||100µF×3|470µF|Yes, cf. Figure 61|N/A|N/A|425|18.0|1.65|None|30|63|50|
|0.9|12|Test Ckt. 1||100µF×4|None|Yes, cf. Figure 61|N/A|N/A|425|18.0|1.65|None|37|76|45|
|0.9|12|Test Ckt. 1||100µF×3|470µF|Yes, cf. Figure 61|N/A|N/A|425|18.0|1.65|None|30|63|50|
|1|5|Test Ckt. 2||100µF×4|None|Yes, cf. Figure 61|N/A|N/A|500|None|2.43|0|39|79|45|
|1|5|Test Ckt. 2||100µF×3|470µF|Yes, cf. Figure 61|N/A|N/A|500|None|2.43|0|31|63|50|
|1|12|Test Ckt. 1||100µF×4|None|Yes, cf. Figure 61|N/A|N/A|500|None|2.43|0|39|79|45|
|1|12|Test Ckt. 1||100µF×3|470µF|Yes, cf. Figure 61|N/A|N/A|500|None|2.43|0|31|63|50|
|1.2|5|Test Ckt. 2||100µF×4|None|Yes, cf. Figure 61|N/A|N/A|500|None|3.24|0|40|80|45|
|1.2|5|Test Ckt. 2||100µF×3|470µF|Yes, cf. Figure 61|N/A|N/A|500|None|3.24|0|32|64|50|
|1.2|12|Test Ckt. 1||100µF×4|None|Yes, cf. Figure 61|N/A|N/A|575|15.4|3.24|0|40|80|45|
|1.2|12|Test Ckt. 1||100µF×3|470µF|Yes, cf. Figure 61|N/A|N/A|575|15.4|3.24|0|32|64|50|
|1.5|5|Test Ckt. 2||100µF×4|None|Yes, cf. Figure 61|N/A|N/A|575|15.4|4.22|None|41|81|45|
|1.5|5|Test Ckt. 2||100µF×3|470µF|Yes, cf. Figure 61|N/A|N/A|575|15.4|4.22|None|32|65|50|
|1.5|12|Test Ckt. 1||100µF×4|None|Yes, cf. Figure 61|N/A|N/A|650|12.7|4.22|None|41|81|45|
|1.5|12|Test Ckt. 1||100µF×3|470µF|Yes, cf. Figure 61|N/A|N/A|650|12.7|4.22|None|32|65|50|
|1.8|5|Test Ckt. 2||100µF×4|None|Yes, cf. Figure 61|N/A|N/A|650|12.7|6.34|0|41|82|45|
|1.8|5|Test Ckt. 2||100µF×3|470µF|Yes, cf. Figure 61|N/A|N/A|650|12.7|6.34|0|32|65|50|
|1.8|12|Test Ckt. 1||100µF×4|None|Yes, cf. Figure 61|N/A|N/A|750|10.7|6.34|0|41|82|45|
|1.8|12|Test Ckt. 1||100µF×3|470µF|Yes, cf. Figure 61|N/A|N/A|750|10.7|6.34|0|32|65|50|
|2.5|5|Test Ckt. 2||100µF×4|None|Yes, cf. Figure 61|N/A|N/A|650|12.7|10.7|None|42|87|45|
|2.5|5|Test Ckt. 2||100µF×3|470µF|Yes, cf. Figure 61|N/A|N/A|650|12.7|10.7|None|32|65|50|
|2.5|12|Test Ckt. 1||100µF×4|None|Yes, cf. Figure 61|N/A|N/A|1000|9.09|10.7|None|42|87|45|
|2.5|12|Test Ckt. 1||100µF×3|470µF|Yes, cf. Figure 61|N/A|N/A|1000|9.09|10.7|None|32|65|50|
|3.3|5|Test Ckt. 2||100µF×4|None|Yes, cf. Figure 61|N/A|N/A|650|12.7|22.6|None|70|147|50|
|3.3|5|Test Ckt. 2||100µF×3|470µF|Yes, cf. Figure 61|N/A|N/A|650|12.7|22.6|None|54|104|60|
|3.3|12|Test Ckt. 1||100µF×4|None|Yes, cf. Figure 61|N/A|N/A|1000|9.09|22.6|None|70|147|50|
|3.3|12|Test Ckt. 1||100µF×3|470µF|Yes, cf. Figure 61|N/A|N/A|1000|9.09|22.6|None|54|105|60|
|5|12|Test Ckt. 1||100µF×3|470µF|Yes, cf. Figure 61|N/A|N/A|1000|9.09|32.4|7.68|56|113|60|
*For all conditions: CINH input capacitance is 10µF × 2, per channel (VIN0, VIN1). CINL bulk input capacitance of 150µF is optional if VIN has very low input impedance.
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LTM4675
## **APPLICATIONS INFORMATION-DERATING CURVES**
## **See also Figure 35, 12VIN to 5VOUT Derating Curves.**
**==> picture [516 x 576] intentionally omitted <==**
**----- Start of picture text -----**<br>
7 7 7<br>6 6 6<br>5 5 5 12V IN<br>4 4 12VIN 4<br>3 8V IN 12VIN 3 8VIN 3 8V IN<br>2 2 5V IN 2 5VIN<br>5VIN<br>1 1 1<br>0 0 0<br>0 2 4 6 8 10 12 14 16 18 0 2 4 6 8 10 12 14 16 18 0 2 4 6 8 10 12 14 16 18<br>OUTPUT CURRENT (A) OUTPUT CURRENT (A) OUTPUT CURRENT (A)<br>4675 F11 4675 F12 4675 F13<br>Figure 11. 1VOUT Power Loss Curve Figure 12. 1.8VOUT Power Loss Curve Figure 13. 3.3VOUT Power Loss CurveOUT Power Loss Curve Power Loss Curve<br>18 18 18<br>16 16 16<br>14 14 14<br>12 12 12<br>10 10 10<br>8 8 8<br>6 6 6<br>4 4 4<br>400LFM 400LFM 400LFM<br>2 200LFM 2 200LFM 2 200LFM<br>0LFM 0LFM 0LFM<br>0 0 0<br>30 40 50 60 70 80 90 100 110 120 30 40 50 60 70 80 90 100 110 120 30 40 50 60 70 80 90 100 110 120<br>AMBIENT TEMPERATURE (°C) AMBIENT TEMPERATURE (°C) AMBIENT TEMPERATURE (°C)<br>4675 F14 4675 F15 4675 F16<br>Figure 14. 5V to 1V Derating Figure 15. 12V to 1V Derating Curve, Figure 16. 5V to 1V Derating<br>Curve, No Heat Sink No Heat Sink Curve, with Heat Sink<br>18 18 18<br>16 16 16<br>14 14 14<br>12 12 12<br>10 10 10<br>8 8 8<br>6 6 6<br>4 4 4<br>400LFM 400LFM 400LFM<br>2 200LFM 2 200LFM 2 200LFM<br>0LFM 0LFM 0LFM<br>0 0 0<br>30 40 50 60 70 80 90 100 110 120 30 40 50 60 70 80 90 100 110 120 30 40 50 60 70 80 90 100 110 120<br>AMBIENT TEMPERATURE (°C) AMBIENT TEMPERATURE (°C) AMBIENT TEMPERATURE (°C)<br>4675 F17 4675 F18 4675 F19<br>POWER LOSS (W) POWER LOSS (W) POWER LOSS (W)<br>MAXIMUM LOAD CURRENT (A) MAXIMUM LOAD CURRENT (A) MAXIMUM LOAD CURRENT (A)<br>MAXIMUM LOAD CURRENT (A) MAXIMUM LOAD CURRENT (A) MAXIMUM LOAD CURRENT (A)<br>**----- End of picture text -----**<br>
**Figure 13. 3.3VOUT Power Loss CurveOUT Power Loss Curve Power Loss Curve**
**Figure 17. 12V to 1V Derating Curve, with Heat Sink**
**Figure 19. 12V to 1.8V Derating Curve, No Heat Sink**
**Figure 18. 5V to 1.8V Derating Curve, No Heat Sink**
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LTM4675
## **APPLICATIONS INFORMATION-DERATING CURVES**
**==> picture [516 x 385] intentionally omitted <==**
**----- Start of picture text -----**<br>
18 18 18<br>16 16 16<br>14 14 14<br>12 12 12<br>10 10 10<br>8 8 8<br>6 6 6<br>4 4 4<br>400LFM 400LFM 400LFM<br>2 200LFM 2 200LFM 2 200LFM<br>0LFM 0LFM 0LFM<br>0 0 0<br>30 40 50 60 70 80 90 100 110 120 30 40 50 60 70 80 90 100 110 120 30 40 50 60 70 80 90 100 110 120<br>AMBIENT TEMPERATURE (°C) AMBIENT TEMPERATURE (°C) AMBIENT TEMPERATURE (°C)<br>4675 F20 4675 F21 4675 F22<br>Figure 20. 5V to 1.8V Derating Figure 21. 12V to 1.8V Derating Figure 22. 5V to 3.3V Derating<br>Curve, with Heat Sink Curve, with Heat Sink Curve, No Heat Sink<br>18 18 18<br>16 16 16<br>14 14 14<br>12 12 12<br>10 10 10<br>8 8 8<br>6 6 6<br>4 4 4<br>400LFM 400LFM 400LFM<br>2 200LFM 2 200LFM 2 200LFM<br>0LFM 0LFM 0LFM<br>0 0 0<br>30 40 50 60 70 80 90 100 110 120 30 40 50 60 70 80 90 100 110 120 30 40 50 60 70 80 90 100 110 120<br>AMBIENT TEMPERATURE (°C) AMBIENT TEMPERATURE (°C) AMBIENT TEMPERATURE (°C)<br>4675 F23 4675 F24 4675 F25<br>MAXIMUM LOAD CURRENT (A) MAXIMUM LOAD CURRENT (A) MAXIMUM LOAD CURRENT (A)<br>MAXIMUM LOAD CURRENT (A) MAXIMUM LOAD CURRENT (A) MAXIMUM LOAD CURRENT (A)<br>**----- End of picture text -----**<br>
**Figure 23. 12V to 3.3V Derating Curve, No Heat Sink**
**Figure 24. 5V to 3.3V Derating Curve, with Heat Sink**
**Figure 25. 12V to 3.3V Derating Curve, with Heat Sink**
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LTM4675
## **APPLICATIONS INFORMATION**
## **EMI PERFORMANCE**
The SW _n_ pin provides access to the midpoint of the power MOSFETs in LTM4675’s power stages.
Connecting an optional series RC network from SW _n_ to GND can dampen high frequency (~30MHz+) switch node ringing caused by parasitic inductances and capacitances in the switched-current paths. The RC network is called a snubber circuit because it dampens (or “snubs”) the resonance of the parasitics, at the expense of higher power loss.
To use a snubber, choose first how much power to allocate to the task and how much PCB real estate is available to implement the snubber. For example, if PCB space allows a low inductance 1W resistor to be used—derated conservatively to 600mW (PSNUB)—then the capacitor in the snubber network (CSW) is computed by:
**==> picture [107 x 34] intentionally omitted <==**
where VIN _n_ (MAX) is the maximum input voltage that the input to the power stage (VIN _n_ ) will see in the application, and fSW is the DC/DC converter’s switching frequency of operation. CSW should be NPO, C0G or X7R-type (or better) material.
The snubber resistor (RSW) value is then given by:
**==> picture [65 x 34] intentionally omitted <==**
The snubber resistor should be low ESL and capable of withstanding the pulsed currents present in snubber circuits. A value between 0.7Ω and 4.2Ω is normal.
## **SAFETY CONSIDERATIONS**
The LTM4675 modules do not provide galvanic isolation from VIN to VOUT. There is no internal fuse. If required, a slow blow fuse with a rating twice the maximum input current needs to be provided to protect each unit from catastrophic failure.
The fuse or circuit breaker should be selected to limit the current to the regulator during overvoltage in case of an internal top MOSFET fault. If the internal top MOSFET fails, then turning it off will not resolve the overvoltage, thus the internal bottom MOSFET will turn on indefinitely trying to protect the load. Under this fault condition, the input voltage will source very large currents to ground through the failed internal top MOSFET and enabled internal bottom MOSFET. This can cause excessive heat and board damage depending on how much power the input voltage can deliver to this system. A fuse or circuit breaker can be used as a secondary fault protector in this situation. The device does support over current and overtemperature protection.
## **LAYOUT CHECKLIST/EXAMPLE**
The high integration of LTM4675 makes the PCB board layout very simple and easy. However, to optimize its electrical and thermal performance, some layout considerations are still necessary.
- Use large PCB copper areas for high current paths, including VIN _n_ , GND and VOUT _n_ . It helps to minimize the PCB conduction loss and thermal stress.
- Place high frequency ceramic input and output capacitors next to the VIN _n_ , GND and VOUT _n_ pins to minimize high frequency noise.
- Place a dedicated power ground layer underneath the module.
- To minimize the via conduction loss and reduce module thermal stress, use multiple vias for interconnection between top layer and other power layers.
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LTM4675
## **APPLICATIONS INFORMATION**
RUN _n_ , GPIO _n_ , COMP _n_ a, SYNC and SHARE_CLK pins together—as shown in Figure 31.
- Do not put vias directly on pads, unless they are capped or plated over.
- Use a separate SGND copper plane for components connected to signal pins. Connect SGND to GND local to the LTM4675.
- Bring out test points on the signal pins for monitoring.
Figure 26 (a) shows a good example of the LTM4675’s recommended layout. For flexibility, the LTM4675 is dropin pin-compatible to its taller, larger dual 13A LTM4676A and dual 18A LTM4677 sibling modules—as seen in the layout recommended by Figure 26 (b).
- For parallel modules, tie the VOUT _n_ , VOSNS0[+] /VOSNS[–] and/ or VOSNS1/SGND voltage-sense differential pair lines,
**==> picture [253 x 185] intentionally omitted <==**
**----- Start of picture text -----**<br>
CIN0 VIN0 GND VIN1 CIN1<br>9<br>8<br>7<br>6<br>GND SGND GND<br>5<br>4<br>COUT0 COUT1<br>3<br>2<br>1<br>A B C D E F G H J K L M<br>VOUT0 GND VOUT1<br>**----- End of picture text -----**<br>
**==> picture [180 x 140] intentionally omitted <==**
**----- Start of picture text -----**<br>
VIN0 VIN1<br>9<br>GND<br>8<br>7<br>GND GND<br>6<br>SGND<br>5<br>GND GND<br>4<br>3<br>GND GND<br>2<br>VOUT0 VOUT1<br>1<br>A B C D E F G H J K L M<br>GND<br>**----- End of picture text -----**<br>
- **(a) PCB Layout for LTM4675, Package Top View**
**==> picture [462 x 217] intentionally omitted <==**
**----- Start of picture text -----**<br>
VIN0 GND VIN1<br>CIN0 CIN1<br>9 9 VIN0 VIN1<br>GND<br>8 8<br>7 7<br>GND GND<br>6 6<br>GND SGND GND<br>5 5<br>COUT0 4 COUT1 4<br>3 3<br>GND GND<br>2 2<br>1 1<br>VOUT0 VOUT1<br>A B C D E F G H J K L M A B C D E F G H J K L M<br>VOUT0 CNTRL VOUT1<br>**----- End of picture text -----**<br>
- **(b) PCB Layout to Accommodate Any of LTM4675 or LTM4676A or LTM4677 Modules**
**Figure 26. Recommended PCB Layout Package Top View**
4675 F26ab
Rev. D
70
For more information www.analog.com
LTM4675
## **TYPICAL APPLICATIONS**
**==> picture [468 x 267] intentionally omitted <==**
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4.5V to 5.75VVIN + CINL C22µFINH VVIN0IN1 TSNSVOUT00 + 470µF10mΩ C100µFOUT VADJUSTABLEOUT, 1.5V<br>220µF ×3 SVIN ESR ×6 UP TO 18A<br>×2<br>VDD33<br>10k<br>×7<br>SCL VORB0 [+] LOAD<br>SMBus INTERFACE WITH SDA VOSNS0 [+]<br>ON/OFF CONTROL, FAULTMANAGEMENT, POWERPMBus COMMAND SETSEQUENCING ALERTRUNRUNGPIOGPIO0101 LTM4675 VTSNSVOSNS0VVORB0ORB1OUT11a [–][–]<br>PWM CLOCK SYNCH. SYNC TSNS1b<br>TIME BASE SYNCH. SHARE_CLK<br>WP<br>• SLAVE ADDRESS = 1001010_R/W (0X4A) VOSNS1<br>• 575kHz SWITCHING FREQUENCY SGND<br>• NO GUI CONFIGURATION AND<br> NO PART-SPECIFIC PROGRAMMING REQUIRED EXCEPT: 4675 F27<br> VIN_OFF < VIN_UV_WARN_LIMIT < VIN_ON < 4.3V<br> IN MULTI-MODULE SYSTEMS, CONFIGURING RAIL_ADDRESS<br>10.7k 15.4k 2.1k<br> IS RECOMMENDED<br>1% 1% 1%<br>• SETTING MFR_PWM_CONFIG[7]=1b, ±50ppm/°C ±50ppm/°C ±50ppm/°C<br> CONFIGURES THE VOUT1 CONTROL LOOP<br> TO USE THE VOSNS0 [+] /VOSNS0 [–] DIFFERENTIAL-<br> SENSE PIN-PAIR AS THE FEEDBACK SIGNAL<br> FOR REGULATING VOUT1.<br>CC 0 1<br>DD25 SW SW<br>INTV V<br>0a 0b 1a 1b<br>SWPHCFG OUT0CFG TRIM0CFG OUT1CFG TRIM1CFG<br>COMP COMP COMP COMP ASEL F V V V V GND<br>**----- End of picture text -----**<br>
**Figure 27. 18A, 1.5V Output DC/DC µModule Regulator with I[2] C/SMBus/PMBus Serial Interface**
**==> picture [160 x 166] intentionally omitted <==**
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10<br>8<br>6 I OUT1<br>4<br>2 I OUT0<br>0<br>–2<br>0 2 4 6 8 10 12 14 18<br>TOTAL OUTPUT CURRENT (A)<br>4675 F28a<br>CHANNEL OUTPUT CURRENT (A)<br>**----- End of picture text -----**<br>
**(28a) 5VIN, Figure 27 Circuit**
**==> picture [173 x 196] intentionally omitted <==**
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10<br>8<br>6 IOUT1<br>4<br>2 IOUT0<br>0<br>–2<br>0 2 4 6 8 10 12 14 18<br>TOTAL OUTPUT CURRENT (A)<br>4675 F28b<br>(28b) 12VIN, Figure 27 Circuit with INTVCC<br>Open and VOUT Commanded to 1V<br>CHANNEL OUTPUT CURRENT (A)<br>**----- End of picture text -----**<br>
**Figure 28. Current Sharing Performance of the LTM4675's Channels**
Rev. D
71
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LTM4675
## **TYPICAL APPLICATIONS**
**==> picture [447 x 253] intentionally omitted <==**
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5V<br>LOW POWER BIAS<br><100mA<br>NOMINAL3.3VIN + C220µFINL C22µF×3INH + VVSVIN0IN1IN TSNSVOUT00 C100µF×5OUT0 ADJUSTABLEUP TO 9AVOUT0, 1.2V<br>VDD33<br>10k<br>×9<br>SMBus INTERFACE WITH SCLSDA VVOSNS0ORB0 [+][+] LOAD0<br>PMBus COMMAND SET ALERT LTM4675 VOSNS0 [–]<br>ON/OFF CONTROL, FAULTMANAGEMENT, POWERPWM CLOCK SYNCH.SEQUENCING RUNRUNGPIOGPIOSYNC0101 TSNSTSNSVVVORB0ORB1OUT11b1a [–] C100µF×5OUT1 ADJUSTABLEUP TO 9AVOUT1, 2.5V<br>TIME BASE SYNCH. SHARE_CLK<br>WP<br>VOSNS1 LOAD1<br>SGND<br>• SLAVE ADDRESS = 1001111_R/W (0X4F)• 500kHz SWITCHING FREQUENCY 4675 F29<br>• NO GUI CONFIGURATION AND<br> NO PART-SPECIFIC PROGRAMMING REQUIRED EXCEPT:<br> VIN_OFF < VIN_UV_WARN_LIMIT < VIN_ON < 4.5V 3.24k 10.7k<br> IN MULTI-MODULE SYSTEMS, CONFIGURING RAIL_ADDRESS 1% 1%<br> IS RECOMMENDED ±50ppm/°C ±50ppm/°C<br>CC 0 1<br>DD25 SW SW<br>INTV V<br>0a 0b 1a 1b<br>SWPHCFG OUT0CFG TRIM0CFG OUT1CFG TRIM1CFG<br>COMP COMP COMP COMP ASEL F V V V V GND<br>**----- End of picture text -----**<br>
**Figure 29. 9A, 1.2V and 2.5V Outputs Generated from 3.3V Power Input and Providing I[2] C/SMBus/PMBus Serial Interface**
**==> picture [255 x 121] intentionally omitted <==**
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VOUT1<br>50mV/DIV<br>VOUT0<br>50mV/DIV<br>SCL<br>5V/DIV<br>SDA<br>5V/DIV<br>ioe<br>4ms/DIV 4675 F30a<br>(30a) PMBus Operation (Reg. 0x01): 0x80 → 0xA8 (Margin High)<br>**----- End of picture text -----**<br>
**==> picture [186 x 99] intentionally omitted <==**
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VOUT1<br>50mV/DIV<br>VOUT0<br>50mV/DIV<br>SCL<br>5V/DIV<br>SDA<br>5V/DIV<br>4ms/DIV 4675 F30b<br>**----- End of picture text -----**<br>
## **(30b) PMBus Operation (Reg. 0x01): 0xA8** → **0x80 (Margin Off)**
**==> picture [456 x 88] intentionally omitted <==**
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VOUT1<br>50mV/DIV VOUT1<br>50mV/DIV<br>VOUT0<br>50mV/DIV VOUT0<br>50mV/DIV<br>SCL SCL<br>5V/DIV 5V/DIV<br>SDA SDA<br>5V/DIV 5V/DIV<br>4ms/DIV 4675 F30c 4ms/DIV 4675 F30d<br>**----- End of picture text -----**<br>
**(30c) PMBus Operation (Reg. 0x01): 0x80** → **0x98 (Margin Low)**
**(30d) PMBus Operation (Reg. 0x01): 0x98** → **0x80 (Margin Off)**
**Figure 30. Output Voltage Margining, Figure 29 Circuit**
Rev. D
72
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LTM4675
## **TYPICAL APPLICATIONS**
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5.75V TO 16VVIN + C150µFIN5 C10µF×4IN1 VVSVINOIN1IN TSNSVOUT00 C330µF×10OUT(BULK) C100µF×10OUT(MLCC) ADJUSTABLEUP TO 70AVOUT, 1V<br>VDD33<br>10k<br>×7<br>SCL LOAD<br>SDA VOSNS0 [+]<br>ALERT U1 VOSNS0 [–]<br>RUN0 LTM4675 VO UT1<br>RUN1 TSNS1a<br>GPIO0 TSNS1b<br>GPIO1<br>SYNC<br>SHARE_CLK<br>WP<br>VOSNS1<br>SGND<br>C10µFIN2 V V INO IN1 TSNS VOUT0 0<br>×4 SVIN<br>VDD33<br>SCL<br>SDA VOSNS0 [+]<br>ALERT U2 VOSNS0 [–]<br>RUNRUNGPIO010 LTM4675 TSNSTSNSVO UT1 1b1a<br>GPIO1<br>SYNC<br>SHARE_CLK<br>WP<br>VOSNS1<br>SGND<br>C10µFIN3 V V INO IN1 TSNS VOUT0 0 787Ω1%±50ppm/°C 1.65k1%±50ppm/°C<br>×4 SVIN<br>VDD33<br>SCL<br>SDA VOSNS0 [+]<br>ALERT U3 VOSNS0 [–]<br>RUNRUNGPIO010 LTM4675 TSNSTSNSVO UT1 1b1a<br>GPIO1<br>SYNC<br>SHARE_CLK<br>WP<br>VOSNS1<br>SGND<br>3.24k<br>1.65k 1%<br>1% ±50ppm/°C<br>C10µFIN4 VVINOIN1 TSNSVOUT00 ±50ppm/°C<br>×4 SVIN<br>VDD33 U1: SLAVE ADDRESS = 1000000_R/W (0X40)U2: SLAVE ADDRESS = 1000001_R/W (0X41)<br>SMBus INTERFACE WITHPMBus COMMAND SET SCLSDAALERT U4 VVOSNS0OSNS0 [+][–] U3: SLAVE ADDRESS = 1000010_R/W (0X42)U4: SLAVE ADDRESS = 1000011_R/W (0X43)500kHz SWITCHING FREQUENCY WITH<br>ON/OFF CONTROL, FAULTMANAGEMENT, POWERSEQUENCING RUNRUNGPIOGPIO0101 LTM4675 TSNSTSNSVOUT11b1a INTERLEAVINGNO GUI CONFIGURATION AND NO PART-SPECIFIC PROGRAMMING REQUIRED<br>PWM CLOCK SYNCH. SYNC IN MULTI-MODULE SYSTEMS, CONFIGURING<br>TIME BASE SYNCH. SHARE_CLK RAIL_ADDRESS IS RECOMMENDED<br>WP<br>VOSNS1 ELECTRICALLY UNCONNECTED PINS<br>SGND VORB0 [+] , VORB0 [–] AND VORB1 NOT SHOWN<br>1.65kRTH 4675 F31 SETTING MFR_PWM_CONFIG[7] = 1b,<br>CONFIGURES THE VOUT1 CONTROL LOOP<br>C3.3nFTH C220pFTHP 1.21k1% TO USE THE VSENSE PIN-PAIR AS THE FEEDBACK SIGNAL OSNS0 [+] /VOSNS0 [–] DIFFERENTIAL-<br>±50ppm/°C FOR REGULATING VOUT1.<br>INTVCC VDD25 SW0 SW1<br>COMP0a COMP0b COMP1a COMP1b ASEL FSWPHCFG VOUT0CFG VTRIM0CFG VOUT1CFG VTRIM1CFG GND<br>INTVCC VDD25 SW0 SW1<br>COMP0a COMP0b COMP1a COMP1b ASEL FSWPHCFG VOUT0CFG VTRIM0CFG VOUT1CFG VTRIM1CFG GND<br>INTVCC VDD25 SW0 SW1<br>COMP0a COMP0b COMP1a COMP1b ASEL FSWPHCFG VOUT0CFG VTRIM0CFG VOUT1CFG VTRIM1CFG GND<br>INTVCC VDD25 SW0 SW1<br>COMP0a COMP0b COMP1a COMP1b ASEL FSWPHCFG VOUT0CFG VTRIM0CFG VOUT1CFG VTRIM1CFG GND<br>**----- End of picture text -----**<br>
**Figure 31. Four Paralleled LTM4675 Producing 1VOUT at Up to 70A. Integrated Power System Management Features Accessible Over 2-Wire I[2] C/SMBus/PMBus Serial Interface. Evaluated on DC1989B-C, Custom-Stuffed with LTM4675 Modules**
Rev. D
73
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LTM4675
## **TYPICAL APPLICATIONS**
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12VIN ±20% + C150µFIN5 C10µF×4IN1 VVSVINOIN1IN TSNSVOUT00 C470µF×10OUT(BULK) C100µF×20OUT(MLCC) VADJUSTABLEUP TO 92A~122AOUT, 1V<br>VDD33<br>10k<br>×6<br>SMBus INTERFACE WITHPMBus COMMAND SET SCLSDAALERT U1 VVOSNS0OSNS0 [+][–] LOAD<br>ON/OFF CONTROL, FAULTMANAGEMENT, POWERSEQUENCING RUNRUNGPIOGPIO0101 LTM4675 TSNSTSNSVO UT1 1b1a<br>PWM CLOCK SYNCH. SYNC<br>TIME BASE SYNCH. SHARE_CLK<br>WP<br>VOSNS1<br>SGND<br>RTH* U1: SLAVE ADDRESS = 1000000_R/W (0x40)500kHz SWITCHING FREQUENCY WITH INTERLEAVING<br>NO GUI CONFIGURATION AND NO PART-SPECIFIC<br>CTH* 6.34k PROGRAMMING REQUIRED EXCEPT:<br>RCLK 1% 1.2k IOUT_OC_WARN_LIMIT n =18A<br>U5A 200Ω ±50ppm/°C 1%±50ppm/°C IN MULTI-MODULE SYSTEMS, CONFIGURING MFR_GPIO_RESPONSE n = 0x00<br>1/2 LT1801 M1 RAIL_ADDRESS IS RECOMMENDED<br>2N7002A<br>ELECTRICALLY UNCONNECTED PINS<br>CINTVCC2 VORB0 [+] , VORB0 [–] AND VORB1 NOT SHOWN<br>4.7µF<br>C10µF×4IN2 R121kTEMP2 V TEMP IN PGOOD1 VVOUTS1OUT1VFB1 TO USE THE VSETTING MFR_PWM_CONFIG[7] = 1CONFIGURES THE VOSNS0OUT1 [+] /VOSNS0 CONTROL LOOP [–] DIFFERENTIAL-b,<br>EXTVPHASMDCC DIFFP R8.25kVFB SENSE PIN-PAIR AS THE FEEDBACK SIGNAL FOR REGULATING VOUT1.<br>DIFFN<br>RDIV1* RUN1RUN2TRACK1 U2* DIFFOUTVVOUTS2OUT2<br>+ TRACK2 VFB2<br>RDIV2* 1/2 LT1801U5B COMP1 PGOOD2<br>– COMP2fSET<br>RFSET2<br>121k<br>CINTVCC3<br>4.7µF<br>PGOOD1<br>C10µF×4IN3 R121kTEMP3 TEMP VVOUTS1OUT1VFB1<br>EXTVPHASMDCC DIFFP<br>DIFFN<br>RUN1RUN2 U3* DIFFOUTVOUT2<br>TRACK1 VOUTS2<br>TRACK2 VFB2<br>COMP1 PGOOD2<br>COMP2<br>fSET<br>RFSET3<br>121k<br>CINTVCC4<br>4.7µF<br>PGOOD1<br>C10µF×4IN4 R121kTEMP4 TEMP VVOUTS1OUT1VFB1<br>EXTVPHASMDCC DIFFP<br>DIFFN<br>RUN1RUN2 U4* DIFFOUTVOUT2<br>TRACK1 VOUTS2<br>TRACK2 VFB2 4675 F32<br>COMP1 PGOOD2<br>COMP2<br>fSET<br>RFSET4<br>121k<br>*STUFFING OPTIONS<br>DEMO BOARD OUTPUT CURRENT U1 U2, U3, U4 RDIV1 RDIV2 RTH CTH<br>DC2106A-A UP TO 92A LTM4675 LTM4620A 28k 90.9k 13.3k 4.7nF<br>DC2106A-B UP TO 122A LTM4675 LTM4630 23.2k 95.3k 8.87k 4.7nF<br>INTVCC VDD25 SW0 SW1<br>COMP0a COMP0b COMP1a COMP1b ASEL FSWPHCFG VOUT0CFG VTRIM0CFG VOUT1CFG VTRIM1CFG GND<br>SW 1 SW 2 INTVCC<br>MODE_PLLIN<br>CLKOUT SGND GND<br>SW 1 SW 2 INTVCC<br>MODE_PLLIN<br>CLKOUT SGND GND<br>SW 1 SW 2 INTVCC<br>MODE_PLLIN<br>CLKOUT SGND GND<br>+<br>–<br>**----- End of picture text -----**<br>
**Figure 32. One LTM4675 Operating In Parallel with 3xLTM4620A or 3xLTM4630 (See Demo Boards DC2106A-A, DC2106A-B, Custom-Stuffed with LTM4675 Modules for U1) Producing 1VOUT at up to 92A ~ 122A. Power System Management Features Accessible Through LTM4675. See Figure 33**
Rev. D
74
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LTM4675
## **TYPICAL APPLICATIONS**
**==> picture [252 x 378] intentionally omitted <==**
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14<br>12<br>10<br>U1-LTM4675-IOUT0<br>8 U1-LTM4675-IOUT1<br>U2-LTM4620A-IOUT1<br>6 U2-LTM4620A-IOUT2<br>U3-LTM4620A-IOUT1<br>4 U3-LTM4620A-IOUT2<br>U4-LTM4620A-IOUT1<br>2 U4-LTM4620A-IOUT2<br>0<br>–2<br>0 10 20 30 40 50 60 70 80 90 100<br>TOTAL OUTPUT CURRENT (A)<br>4675 F33a<br>(33a) LTM4675 Paralleled with 3x LTM4620A (Up to 92A Output)<br>21<br>18<br>15<br>U1-LTM4675-IOUT0<br>12 U1-LTM4675-IOUT1<br>U2-LTM4630-IOUT1<br>9 U2-LTM4630-IOUT2<br>U3-LTM4630-IOUT1<br>6 U3-LTM4630-IOUT2<br>U4-LTM4630-IOUT1<br>3 U4-LTM4630-IOUT2<br>0<br>–3<br>0 20 40 60 80 100 120 140<br>TOTAL OUTPUT CURRENT (A)<br>4675 F33b<br>CHANNEL OUTPUT CURRENT (A)<br>CHANNEL OUTPUT CURRENT (A)<br>**----- End of picture text -----**<br>
**(33b) LTM4675 Paralleled with 3x LTM4630 (Up to 122A Output)**
**Figure 33. Current Sharing Performance of Figure 32 Circuit at 12VIN**
Rev. D
75
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LTM4675
## **TYPICAL APPLICATIONS**
**==> picture [401 x 559] intentionally omitted <==**
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IN OUT OPTIONAL: INSTALLING U2 AWAY FROM HEAT SOURCES<br>U2 RSET1 ALLOWS INTVCC LDO LOSSES NORMALLY INCURRED BY<br>LT3060 13.3k THE LTM4675 TO BE DISSIPATED INSTEAD BY THE LT3060.<br>SHDN ADJ THERMAL-DERATING CAN THUS BE IMPROVED<br>GND REF/BYP RSET2<br>1.62k<br>5.75V to 17VVIN + CINL C22µFINH VVIN0IN1 TSNSVOUT00 C100µFOUT VADJUSTABLEOUT, 5V<br>220µF ×3 SVIN ×10 UP TO 18A<br>VDD33<br>10k<br>×7<br>SCL VORB0 [+] LOAD<br>SMBus INTERFACE WITH SDA VOSNS0 [+]<br>PMBus COMMAND SET ALERT U1 VOSNS0 [–]<br>ON/OFF CONTROL, FAULTMANAGEMENT, POWERSEQUENCING RUNRUNGPIOGPIO0101 LTM4675 TSNSVVVORB0ORB1OUT11a [–]<br>PWM CLOCK SYNCH. SYNC TSNS1b<br>TIME BASE SYNCH. SHARE_CLK<br>WP<br>• SLAVE ADDRESS = 1000101_R/W (0X45)<br>VOSNS1<br>SGND<br>• 1MHz SWITCHING FREQUENCY<br>• NO GUI CONFIGURATION AND NO 4675 F34<br> PART-SPECIFIC PROGRAMMING REQUIRED<br> IN MULTI-MODULE SYSTEMS, CONFIGURING<br> RAIL_ADDRESS IS RECOMMENDED. 4.22k 9.09k 16.2k 3.83k<br>1% 1% 1% 1%<br>±50ppm/°C ±50ppm/°C ±50ppm/°C ±50ppm/°C<br>• SETTING MFR_PWM_CONFIG[7]=1b,<br> CONFIGURES THE VOUT1 CONTROL LOOP<br> TO USE THE VOSNS0 [+] /VOSNS0 [–] DIFFERENTIAL-<br> SENSE PIN-PAIR AS THE FEEDBACK SIGNAL<br> FOR REGULATING VOUT1.<br>Figure 34. 18A, 5V Output DC/DC µModule Regulator with Serial Interface<br>18<br>16<br>14<br>12<br>10 400LFM, WITH U2, R0LFM, WITH U2, RSET1SET1 AND R AND RSET2SET2 INSTALLED: INSTALLED: θJAθ = 9.2°C/WJA = 7.9°C/W<br>8 400LFM, WITH U2, RSET1 AND RSET2 NOT USED: θJA = 9.5°C/W<br>0LFM, WITH U2, RSET1 AND RSET2 NOT USED: θJA = 13°C/W<br>6<br>4<br>2<br>0<br>20 30 40 50 60 70 80 90 100<br>AMBIENT TEMPERATURE (°C)<br>4675 F35<br>CC DD25 SW0 SW1<br>INTV V<br>0a 0b 1a 1b<br>COMP COMP COMP COMP ASEL FSWPHCFG VOUT0CFG VTRIM0CFG VOUT1CFG VTRIM1CFG GND<br>MAXIMUM LOAD CURRENT (A)<br>**----- End of picture text -----**<br>
**Figure 35. Output Derating Curve of Figure 34 Circuit Tested on DC2053, 12VIN, No Heat Sink**
Rev. D
76
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LTM4675
## **APPENDIX A**
## **SIMILARITY BETWEEN PMBUS, SMBUS AND I[2] C 2-WIRE INTERFACE**
The PMBus 2-wire interface is an incremental extension of the SMBus. SMBus is built upon I[2] C with some minor differences in timing, DC parameters and protocol. The PMBus/SMBus protocols are more robust than simple I[2] C byte commands because PMBus/SMBus provide time-outs to prevent bus errors and optional packet error checking (PEC) to ensure data integrity. In general, a master device that can be configured for I[2] C communication can be used for PMBus communication with little or no change to hardware or firmware. Repeat start (restart) is not supported by all I[2] C controllers but is required for SMBus/
PMBus reads. If a general purpose I[2] C controller is used, check that repeat start is supported.
For a description of the minor extensions and exceptions PMBus makes to SMBus, refer to PMBus Specification Part 1 Revision 1.2: Paragraph 5: Transport.
For a description of the differences between SMBus and I[2] C, refer to System Management Bus (SMBus) Specification Version 2.0: Appendix B—Differences Between SMBus and I[2] C.
PMBus data format terminology and abbreviations used in ADI data sheets (see Appendix C, for example), application notes, and the LTpowerPlay GUI are indicated in Table 21.
**Table 21. Data Format Terminology**
|**PMBus TERMINOLOGY**|**MEANING**|**TERMINOLOGY FOR: SPECS, GUI,**<br>**APPLICATION NOTES**|**ABBREVIATIONS FOR SUMMARY**<br>**COMMAND TABLE**|
|---|---|---|---|
|Linear|Linear|Linear_5s_11s|L11|
|Linear (for Voltage Related<br>Commands)|Linear|Linear_16u|L16|
|Direct|Direct-Manufacturer Customized|DirectMfr|CF|
|Hex||Hex|I16|
|ASCII||ASCII|ASC|
||Register Fields|Reg|Reg|
Handshaking features are included to ensure robust system communication. Please refer to the PMBus Communication and Command Processing subsection of the Applications Information section for further details.
Rev. D
77
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LTM4675
## **APPENDIX B**
## **PMBUS SERIAL DIGITAL INTERFACE**
The LTM4675 communicates with a host (master) using the standard PMBus serial bus interface. The Timing Diagram, Figure 36, shows the timing relationship of the signals on the bus. The two bus lines, SDA and SCL, must be high when the bus is not in use. External pull-up resistors or current sources are required on these lines.
The LTM4675 is a slave device. The master can communicate with the LTM4675 using the following formats:
- n Master transmitter, slave receiver
- n Master receiver, slave transmitter
The following PMBus protocols are supported:
- n Write Byte, Write Word, Send Byte, Block Write
- n Read Byte, Read Word, Block Read
- n Block Write -- Block Read Process Call
- n Alert Response Address
Figure 38 to Figure 54 illustrate the aforementioned PMBus protocols. All transactions support PEC (parity error check) and GCP (group command protocol). The Block Read
supports 255 bytes of returned data. For this reason, the PMBus timeout may be extended when reading the fault log.
Figure 37 is a key to the protocol diagrams in this section. PEC is optional.
A value shown below a field in the following figures is a mandatory value for that field.
The data formats implemented by PMBus are:
- n Master transmitter transmits to slave receiver. The transfer direction in this case is not changed.
- n Master reads slave immediately after the first byte. At the moment of the first acknowledgment (provided by the slave receiver) the master transmitter becomes a master receiver and the slave receiver becomes a slave transmitter.
- n Combined format. During a change of direction within a transfer, the master repeats both a start condition and the slave address but with the R/W bit reversed. In this case, the master receiver terminates the transfer by generating a NACK on the last byte of the transfer and a STOP condition.
**==> picture [444 x 116] intentionally omitted <==**
**----- Start of picture text -----**<br>
SDA<br>tf tLOW tr tSU(DAT) tf tHD(SDA) tSP tr tBUF<br>SCL<br>tHD(STA) tSU(STA) tSU(STO)<br>tHD(DAT) tHIGH 4675 F36<br>START REPEATED START STOP START<br>CONDITION CONDITION CONDITION CONDITION<br>**----- End of picture text -----**<br>
**Figure 36. Timing Diagram**
Rev. D
78
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LTM4675
## **APPENDIX B**
|7<br>8<br>1<br>1<br>1<br>1<br>1|7<br>8<br>1<br>1<br>1<br>1<br>1|7<br>8<br>1<br>1<br>1<br>1<br>1|7<br>8<br>1<br>1<br>1<br>1<br>1|7<br>8<br>1<br>1<br>1<br>1<br>1|7<br>8<br>1<br>1<br>1<br>1<br>1|7<br>8<br>1<br>1<br>1<br>1<br>1|
|---|---|---|---|---|---|---|
|S|SLAVE ADDRESS|Wr|A|DATA BYTE|A|P|
|S<br>START CONDITION<br>Sr<br>REPEATED START CONDITION<br>Rd<br>READ (BIT VALUE OF 1)<br>Wr<br>WRITE (BIT VALUE OF 0)<br>x<br>SHOWN UNDER A FIELD INDICATES THAT THAT<br>FIELD IS REQUIRED TO HAVE THE VALUE OF x<br>A<br>ACKNOWLEDGE (THIS BIT POSITION MAY BE 0<br>FOR AN ACK OR 1 FOR A NACK)<br>x<br>x|||||||
- P STOP CONDITION PEC PACKET ERROR CODE MASTER TO SLAVE SLAVE TO MASTER
- ... CONTINUATION OF PROTOCOL 4675 F37
**Figure 37. PMBus Packet Protocol Diagram Element Key**
**==> picture [116 x 28] intentionally omitted <==**
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1 7 1 1 1<br>S SLAVE ADDRESS Rd/Wr A P<br>4675 F38<br>**----- End of picture text -----**<br>
**Figure 38. Quick Command Protocol**
**==> picture [170 x 28] intentionally omitted <==**
**----- Start of picture text -----**<br>
1 7 1 1 8 1 1<br>S SLAVE ADDRESS Wr A COMMAND CODE A P<br>4675 F39<br>**----- End of picture text -----**<br>
**Figure 39. Send Byte Protocol**
**==> picture [237 x 99] intentionally omitted <==**
**----- Start of picture text -----**<br>
1 7 1 1 8 1 8 1 1<br>S SLAVE ADDRESS Wr A COMMAND CODE A PEC A P<br>4675 F40<br>Figure 40. Send Byte Protocol with PEC<br>1 7 1 1 8 1 8 1 1<br>S SLAVE ADDRESS Wr A COMMAND CODE A DATA BYTE A P<br>4675 F41<br>**----- End of picture text -----**<br>
**Figure 41. Write Byte Protocol**
**==> picture [302 x 28] intentionally omitted <==**
**----- Start of picture text -----**<br>
1 7 1 1 8 1 8 1 8 1 1<br>S SLAVE ADDRESS Wr A COMMAND CODE A DATA BYTE A PEC A P<br>4675 F42<br>**----- End of picture text -----**<br>
**Figure 42. Write Byte Protocol with PEC**
**==> picture [19 x 6] intentionally omitted <==**
**----- Start of picture text -----**<br>
Rev. D<br>**----- End of picture text -----**<br>
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LTM4675
## **APPENDIX B**
|**X B**|**X B**|**X B**|**X B**|**X B**|**X B**|**X B**|**X B**|**X B**|**X B**|**X B**|**X B**|**X B**|**X B**|**X B**|
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|SLAVE ADDRESS<br>COMMAND CODE<br>DATA BYTE LOW<br>Wr<br>A<br>A<br>A<br>P<br>4675 F43<br>S<br>7<br>8<br>8<br>1<br>DATA BYTE HIGH<br>8<br>1<br>1<br>1<br>1<br>1<br>1<br>A<br>SLAVE ADDRESS<br>COMMAND CODE<br>DATA BYTE LOW<br>Wr<br>A<br>A<br>A<br>P<br>4675 F44<br>S<br>7<br>8<br>8<br>1<br>DATA BYTE HIGH<br>8<br>PEC<br>8<br>1<br>1<br>1<br>1<br>1<br>1<br>1<br>A<br>A<br>SLAVE ADDRESS<br>COMMAND CODE<br>SLAVE ADDRESS<br>Wr<br>A<br>A<br>Sr<br>P<br>4675 F45<br>S<br>7<br>8<br>7<br>1<br>1<br>DATA BYTE<br>8<br>1<br>1<br>1<br>1<br>1<br>1<br>1<br>A<br>Rd<br>NA<br>7<br>8<br>7<br>1<br>1<br>8<br>8<br>1<br>1<br>1<br>1<br>1<br>1<br>1<br>1<br>**Figure 43. Write Word Protocol**<br>**Figure 44. Write Word Protocol with PEC**<br>**Figure 45. Read Byte Protocol**|||||||||||||||
|S|SLAVE ADDRESS|Wr|A|COMMAND CODE|A|Sr|SLAVE ADDRESS|Rd|A|DATA BYTE|A|PEC|A|P|
|4675 F46<br>7<br>8<br>7<br>1<br>8<br>8<br>1<br>1<br>1<br>1<br>1<br>1<br>1<br>1<br>1<br>**Figure 46. Read Byte Protocol with PEC**|||||||||||||||
|S|SLAVE ADDRESS|Wr|A|COMMAND CODE|A|Sr|SLAVE ADDRESS|Rd|A|DATA BYTE LOW|A|DATA BYTE HIGH|NA|P|
|4675 F47|||||||||||||||
**Figure 47. Read Word Protocol**
**==> picture [459 x 27] intentionally omitted <==**
**----- Start of picture text -----**<br>
1 7 1 1 8 1 1 7 1 1 8 1 8 1 8 1 1<br>S SLAVE ADDRESS Wr A COMMAND CODE A Sr SLAVE ADDRESS Rd A DATA BYTE LOW A DATA BYTE HIGH A PEC A P<br>4675 F48<br>**----- End of picture text -----**<br>
**Figure 48. Read Word Protocol with PEC**
||1|7||||1|1|||8||||1||1|||||7||1||1|||||8||||1|||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
||S|SLAVE ADDRESS|||Wr||A||COMMAND CODE|||||A||Sr|||SLAVE ADDRESS||||Rd||A|||BYTE COUNT = N||||||A||…|
|||||||8|||1|||8||||||1||||8|||||1||1||||||||
|||||DATA BYTE 1|||||A||DATA BYTE 2|||||||A||…|DATA BYTE N|||||NA|||P||||||||
|||||||||||||||||||||||||||||4675 F49|||||||||
||||||||||**Figure 49. Block**||||||||**Read**||||**Protocol**||||||||||||||||
||1|7||||1|1|||8||||1||1|||||7||1||1|||||8||||1|||
||S|SLAVE ADDRESS||||Wr|A||COMMAND CODE|||||A||Sr|||SLAVE ADDRESS||||Rd||A|||BYTE||COUNT = N||||A||…|
|||8||||1|||8|||1||||||||8||1||||||8|||1|1|||||
|||DATA BYTE||1||A|DATA BYTE||||2|A||…|||DATA BYTE N|||||A||||PEC|||||NA|P|||||
||||||||||||||||||||||||||||||||4675 F50||||||
**Figure 50. Block Read Protocol with PEC**
Rev. D
80
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LTM4675
## **APPENDIX B**
**==> picture [302 x 127] intentionally omitted <==**
**----- Start of picture text -----**<br>
1 7 1 1 8 1 8 1 8 1<br>S SLAVE ADDRESS Wr A COMMAND CODE A BYTE COUNT = M A DATA BYTE 1 A …<br>8 1 8 1<br>DATA BYTE 2 A … DATA BYTE M A …<br>1 7 1 1 8 1 8 1<br>Sr SLAVE ADDRESS Rd A BYTE COUNT = N A DATA BYTE 1 A …<br>8 1 8 1 1<br>DATA BYTE 2 A … DATA BYTE N NA P<br>4675 F51<br>**----- End of picture text -----**<br>
**Figure 51. Block Write – Block Read Process Call**
**==> picture [302 x 127] intentionally omitted <==**
**----- Start of picture text -----**<br>
1 7 1 1 8 1 8 1 8 1<br>S SLAVE ADDRESS Wr A COMMAND CODE A BYTE COUNT = M A DATA BYTE 1 A …<br>8 1 8 1<br>DATA BYTE 2 A … DATA BYTE M A …<br>1 7 1 1 8 1 8 1<br>Sr SLAVE ADDRESS Rd A BYTE COUNT = N A DATA BYTE 1 A …<br>8 1 8 1 8 1 1<br>DATA BYTE 2 A … DATA BYTE N A PEC NA P<br>4675 F52<br>**----- End of picture text -----**<br>
**Figure 52. Block Write – Block Read Process Call with PEC**
**==> picture [171 x 35] intentionally omitted <==**
**----- Start of picture text -----**<br>
1 7 1 1 7 1 1<br>ALERT RESPONSE<br>S Rd A DEVICE ADDRESS NA P<br>ADDRESS<br>4675 F53<br>**----- End of picture text -----**<br>
**Figure 53. Alert Response Address Protocol**
**==> picture [237 x 35] intentionally omitted <==**
**----- Start of picture text -----**<br>
1 7 1 1 7 1 8 1 1<br>ALERT RESPONSE<br>S Rd A DEVICE ADDRESS A PEC NA P<br>ADDRESS<br>4675 F54<br>**----- End of picture text -----**<br>
**Figure 54. Alert Response Address Protocol with PEC**
Rev. D
81
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LTM4675
## **APPENDIX C: PMBUS COMMAND DETAILS**
## **ADDRESSING AND WRITE PROTECT**
|**COMMAND NAME**|**CMD**<br>**CODE**|**DESCRIPTION**|**TYPE**|**PAGED**|**DATA**<br>**FORMAT**|**UNITS**|**NVM**|**DEFAULT**<br>**VALUE**|
|---|---|---|---|---|---|---|---|---|
|PAGE|0x00|Channel (page) presently selected for any<br>paged command.|R/W Byte|N|Reg|||0x00|
|PAGE_PLUS_WRITE|0x05|Write a command directly to a specified page.|W Block|N|||||
|PAGE_PLUS_READ|0x06|Read a command directly from a specified<br>page.|Block R/W<br>Process|N|||||
|WRITE_PROTECT|0x10|Protect the device against unintended PMBus<br>modifications.|R/W Byte|N|Reg||Y|0x00|
|MFR_ADDRESS|0xE6|Specify right-justified 7-bit device address.|R/W Byte|N|Reg||Y|0x4F|
|MFR_RAIL_ADDRESS|0xFA|Specify unique right-justified 7-bit address<br>for channels comprising a PolyPhase output.|R/W Byte|Y|Reg||Y|0x80|
Related commands: MFR_COMMON.
## _**PAGE**_
The PAGE command provides the ability to configure, control and monitor both PWM channels through only one physical address, either the MFR_ADDRESS or GLOBAL device address. Each PAGE contains the operating memory for one PWM channel.
Pages 0x00 and 0x01 correspond to channel 0 and channel 1, respectively, in this device.
Setting PAGE to 0xFF applies any following paged commands to both outputs. With PAGE set to 0xFF the LTM4675 will respond to read commands as if PAGE were set to 0x00 (channel 0 results).
This command has one data byte.
## _**PAGE_PLUS_WRITE**_
The PAGE_PLUS_WRITE command provides a way to set the page within a device, send a command and then send the data for the command, all in one communication packet. Commands allowed by the present write protection level may be sent with PAGE_PLUS_WRITE.
The value stored in the PAGE command is not affected by PAGE_PLUS_WRITE. If PAGE_PLUS_WRITE is used to send a non-paged command, the Page Number byte is ignored.
This command uses Write Block protocol. An example of the PAGE_PLUS_WRITE command with PEC sending a command that has two data bytes is shown in Figure 55.
**==> picture [367 x 76] intentionally omitted <==**
**----- Start of picture text -----**<br>
1 7 1 1 8 1 8 1 8 1 8 1<br>S SLAVE W A PAGE_PLUS A BLOCK COUNT A PAGE A COMMAND A …<br>ADDRESS COMMAND CODE (= 4) NUMBER CODE<br>8 1 8 1 8 1 1<br>LOWER DATA UPPER DATA<br>A A PEC BYTE A P<br>BYTE BYTE<br>4675 F55<br>**----- End of picture text -----**<br>
**Figure 55. Example of PAGE_PLUS_WRITE**
Rev. D
82
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LTM4675
## **APPENDIX C: PMBUS COMMAND DETAILS**
## _**PAGE_PLUS_READ**_
The PAGE_PLUS_READ command provides the ability to set the page within a device, send a command and then read the data returned by the command, all in one communication packet .
The value stored in the PAGE command is not affected by PAGE_PLUS_READ. If PAGE_PLUS_READ is used to access data from a non-paged command, the Page Number byte is ignored.
This command uses Block Write – Block Read Process Call protocol. An example of the PAGE_PLUS_READ command with PEC is shown in Figure 56.
NOTE: PAGE_PLUS commands cannot be nested. A PAGE_PLUS command cannot be used to read or write another PAGE_PLUS command. If this is attempted, the LTM4675 will NACK the entire PAGE_PLUS packet and issue a CML fault for Invalid/Unsupported Data.
|||1|1|7|||1|1|||1|1|8|||1|1|8||||1|1|8|||1|1|8||1|1|||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|||S||SLAVE<br>ADDRESS|||W||||A||PAGE_PLUS<br>COMMAND CODE|||A||BLOCK COUNT<br>(= 2)||||A||PAGE<br>NUMBER|||A||COMMAND<br>CODE||A||…||
|1||||7|1||||1||||8|1||||8||1||||8|1||||8|1||1|||
|Sr||||SLAVE<br>ADDRESS|R||||A||||BLOCK COUNT<br>(= 2)|A||||LOWER DATA<br>BYTE||A||||UPPER DATA<br>BYTE|A||||PEC BYTE|NA||P|||
||||||||||||||||||||||||||||||||4676A F56||||
**Figure 56. Example of PAGE_PLUS_READ**
## _**WRITE_PROTECT**_
The WRITE_PROTECT command is used to control writing to the LTM4675 device. This command does not indicate the status of the WP pin which is defined in the MFR_COMMON command. The WP pin takes precedence over the value of this command unless the WRITE_PROTECT command is more stringent.
|**BYTE**|**MEANING**|
|---|---|
|0x80|Disable all writes except to the WRITE_PROTECT, PAGE, MFR_<br>EE_UNLOCK and STORE_USER_ALL command|
|0x40|Disable all writes except to the WRITE_PROTECT, PAGE,<br>MFR_EE_UNLOCK, MFR_CLEAR_PEAKS, STORE_USER_ALL,<br>OPERATION and CLEAR_FAULTS command. individual fault<br>bits can be cleared by writing a 1 to the respective bits in the<br>STATUS registers.|
|0x20|Disable all writes except to the WRITE_PROTECT, OPERATION,<br>MFR_EE_UNLOCK, MFR_CLEAR_PEAKS, CLEAR_FAULTS,<br>PAGE, ON_OFF_CONFIG, VOUT_COMMAND and STORE_USER_<br>ALL. Individual fault bits can be cleared by writing a 1 to the<br>respective bits in the STATUS registers.|
|0x10|Reserved, must be 0|
|0x08|Reserved, must be 0|
|0x04|Reserved, must be 0|
|0x02|Reserved, must be 0|
|0x01|Reserved, must be 0|
Enable writes to all commands when WRITE_PROTECT is set to 0x00.
This command has one data byte.
Rev. D
83
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LTM4675
## **APPENDIX C: PMBUS COMMAND DETAILS**
If WP pin is high, PAGE, OPERATION, MFR_CLEAR_PEAKS, MFR_EE_UNLOCK and CLEAR_FAULTS commands are supported. Individual fault bits can be cleared by writing a 1 to the respective bits in the STATUS registers.
## _**MFR_ADDRESS**_
The MFR_ADDRESS command byte sets the 7 bits of the PMBus slave address for this device.
Setting this command to a value of 0x80 disables device addressing. The GLOBAL device address, 0x5A and 0x5B, cannot be deactivated. If RCONFIG is set to ignore (MFR_CONFIG_ALL[6]=1b), the ASEL pin is still used to determine the LSB of the channel address. If the ASEL pin is open, the LTM4675 will use the MFR_ADDRESS stored in EEPROM. Values of 0x5A, 0x5B, 0x0C, and 0x7C are not recommended.
This command has one data byte.
## _**MFR_RAIL_ADDRESS**_
The MFR_RAIL_ADDRESS command enables direct device address access to the PAGE activated channel. The value of this command should be common to all devices attached to a single power supply rail.
The user should only perform command writes to this address. If a read is performed from this address and the rail devices do not respond with EXACTLY the same value, the LTM4675 will detect bus contention and set a CML communications fault.
Setting this command to a value of 0x80 disables rail device addressing for the channel.
This command has one data byte.
## **GENERAL CONFIGURATION REGISTERS**
|**GENERAL CONFIGURATI**|**ON REGIS**|**TERS**|||||||
|---|---|---|---|---|---|---|---|---|
|**COMMAND NAME**|**CMD CODE **|**DESCRIPTION**|**TYPE**|**PAGED**|**DATA**<br>**FORMAT**|**UNITS**|**NVM**|**DEFAULT**<br>**VALUE**|
|MFR_CHAN_CONFIG|0xD0|Configuration bits that are channel specific.|R/W Byte|Y|Reg||Y|0x1F|
|MFR_CONFIG_ALL|0xD1|Configuration bits that are common to all<br>pages.|R/W Byte|N|Reg||Y|0x09|
## _**MFR_CHAN_CONFIG**_
General purpose configuration command common to multiple ADI products.
|**BIT**|**MEANING**|
|---|---|
|7|Reserved|
|6|Reserved|
|5|Reserved|
|4|Disable RUN Low. When asserted the RUNpin is notpulsed low if commanded OFF|
|3|Short Cycle. When asserted the output will immediate off if commanded ON while waiting for TOFF_DELAY or TOFF_FALL. TOFF_MIN of 120ms<br>is honored then thepart will command ON.|
|2|SHARE_CLOCK control, if SHARE_CLOCK is held low, the output is disabled|
|1|NoGPIO ALERT,ALERTis not pulled low ifGPIOis pulled low externally. Assert this bit if either POWER_GOOD or VOUT_UVUF are propagated<br>onGPIO|
|0|Disables the VOUT decay value requirement for MFR_RETRY_TIME processing. When this bit is set to a 0, the output must decay to less than 12.5% of<br>theprogrammed value for anyaction that turns off the rail includinga fault, an OFF/ON command, or a toggle of RUN from high to low to high.|
This command has one data byte.
Rev. D
84
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LTM4675
## **APPENDIX C: PMBUS COMMAND DETAILS**
## _**MFR_CONFIG_ALL**_
General purpose configuration command common to multiple ADI products
|**BIT**|**MEANING**|
|---|---|
|7|Enable Fault Logging|
|6|Ignore Resistor Configuration Pins|
|5|Disable CML fault for Quick Command message|
|4|Disable SYNC out|
|3|Enable 255ms Time Out|
|2|A valid PEC required for PMBus writes to be accepted. If this bit is not set,<br>the part will accept commands with invalid PEC.|
|1|Enable the use of PMBus clock stretching|
|0|Enables a low to high transition on either RUN pin to issue a<br>CLEAR_FAULTS command|
This command has one data byte.
## **ON/OFF/MARGIN**
|**COMMAND NAME**|**CMD**<br>**CODE**|**DESCRIPTION**|**TYPE**|**PAGED**|**DATA**<br>**FORMAT**|**UNITS**|**NVM**|**DEFAULT**<br>**VALUE**|
|---|---|---|---|---|---|---|---|---|
|ON_OFF_CONFIG|0x02|RUN pin and PMBus bus on/off command configuration.|R/W Byte|Y|Reg||Y|0x1F|
|OPERATION|0x01|Operating mode control. On/off, margin high and margin<br>low.|R/W Byte|Y|Reg||Y|0x80|
|MFR_RESET|0xFD|Commanded reset without requiring a power-down.<br>Identical to RESTORE_USER_ALL.|Send Byte|N||||NA|
## _**ON_OFF_CONFIG**_
The ON_OFF_CONFIG command configures the combination of RUN _n_ pin input and serial bus commands needed to turn the unit on and off. This includes how the unit responds when power is applied.
**Table 22. Supported Values**
|**VALUE**|**MEANING**|
|---|---|
|0x1F|OPERATION value and RUN_n_pin must both command the device to start/run. Device executes immediate off when commanded off.|
|0x1E|OPERATION value and RUN_n_pin must both command the device to start/run. Device uses TOFF_ command values when<br>commanded off.|
|0x17|RUN_n_pin control with immediate off when commanded off. OPERATION on/off control ignored.|
|0x16|RUN_n_pin control using TOFF_ command values when commanded off. OPERATION on/off control ignored.|
Note: A high on the RUN _n_ pin is always required to start power conversion. Power conversion will always stop with a low on RUN _n_ .
Programming an unsupported ON_OFF_CONFIG value will generate a CML fault and the command will be ignored. This command has one data byte.
Rev. D
85
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LTM4675
## **APPENDIX C: PMBUS COMMAND DETAILS**
## _**OPERATION**_
The OPERATION command is used to turn the unit on and off in conjunction with the input from the RUN _n_ pins. It is also used to cause the unit to set the output voltage to the upper or lower MARGIN VOLTAGEs. The unit stays in the commanded operating mode until a subsequent OPERATION command or change in the state of the RUN _n_ pin instructs the device to change to another mode. If the part is stored in the MARGIN_LOW/HIGH state, the next MFR_RESET or RESTORE_USER_ALL or SVIN power cycle will ramp to that state. If the OPERATION command is modified, for example ON is changed to MARGIN_LOW, the output will move at a fixed slope set by the VOUT_TRANSITION_RATE. The default operation command is sequence off.
Margin High (Ignore Faults) and Margin Low (Ignore Faults) operations are not supported by the LTM4675. The part defaults to the Sequence Off state.
This command has one data byte.
**Table 23. OPERATION Command Detail Register OPERATION Data Contents When On_Off_Config_Use_PMBus Enables Operation_Control**
|**SYMBOL**|**ACTION**|**VALUE**|
|---|---|---|
|**BITS**|||
|**FUNCTION**|Turn off immediately|0x00|
||Turn on|0x80|
||Margin Low|0x98|
||Margin High|0xA8|
||Sequence off|0x40|
## **OPERATION Data Contents When On_Off_Config is Configured Such That OPERATION Command Is Not Used to Command Channel On or Off**
|**SYMBOL**|**ACTION**|**VALUE**|
|---|---|---|
|**BITS**|||
|**FUNCTION**|Output at Nominal|0x80|
||Margin Low|0x98|
||Margin High|0xA8|
Note: Attempts to write a reserved value will cause a CML fault.
Rev. D
86
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LTM4675
## **APPENDIX C: PMBUS COMMAND DETAILS**
## _**MFR_RESET**_
This command provides a means by which the user can perform a reset of the LTM4675. Identical to RESTORE_USER_ALL. This write-only command has no data bytes.
## **PWM CONFIG**
|**PWM CONFIG**|||||||||
|---|---|---|---|---|---|---|---|---|
|**COMMAND NAME**|**CMD CODE **|**DESCRIPTION**|**TYPE**|**PAGED**|**DATA**<br>**FORMAT**|**UNITS**|**NVM**|**DEFAULT**<br>**VALUE**|
|MFR_PWM_MODE|0xD4|Configuration for the PWM engine of each channel.|R/W Byte|Y|Reg||Y|0xC1|
|MFR_PWM_CONFIG|0xF5|Set numerous parameters for the DC/DC controller<br>including phasing.|R/W Byte|N|Reg||Y|0x10|
|FREQUENCY_SWITCH|0x33|Switching frequency of the controller.|R/W Word|N|L11|kHz|Y|500<br>0xFBE8|
## _**MFR_PWM_MODE**_
The MFR_PWM_MODE command allows the user to program the PWM controller to use, discontinuous (pulse-skipping mode), or forced continuous conduction mode.
|<br>mode),|<br>or forced continuous conduction mode.|
|---|---|
|**BIT**|**MEANING**|
|7|Range of ILIMIT<br>0 – Low Current Range<br>1 – High Current Range|
|6|Enable Servo Mode|
|5|Reserved|
|4|Page 0 Only: Use of TSNS1a-Sensed Temperature Telemetry<br>0 - Temperature sensed via TSNS1ais used to temperature-correct the current-sense information digitized by Channel 1.<br>1 - Temperature sensed via TSNS0is used to temperature-correct the current-sense information digitized by Channel 1. Telemetry obtained<br>from the thermal sensor connected to TSNS1acan be external to the module, if desired.|
|3|Reserved|
|2|Reserved|
|1|Voltage Range<br>0 - Hi Voltage Range 5.5 volts max<br>1 - Lo Voltage Range 2.75 volts max|
|0|PWM Mode<br>0 - Discontinuous Mode<br>1 - Continuous Mode|
Whenever the channel is ramping on, the PWM mode will be discontinuous, regardless of the value of this command.
Bit [7] of this command determines if the part is in high range or low range of the IOUT_OC_FAULT_LIMIT command. Changing this bit value changes the PWM loop gain and compensation. Changing this bit value whenever an output is active may have detrimental system results.
Rev. D
87
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LTM4675
## **APPENDIX C: PMBUS COMMAND DETAILS**
Bit [6] The LTM4675 will not servo while the part is OFF, ramping on or ramping off. When set to a one, the output servo is enabled. The output set point DAC will be slowly adjusted to minimize the difference between the READ_VOUT_ADC and the VOUT_COMMAND (or the appropriate margined value).
Bit [1] of this command determines if the part is in high range or low voltage range. Changing this bit value changes the PWM loop gain and compensation. This bit value cannot be changed when an output is active.
This command has one data byte.
## _**MFR_PWM_CONFIG**_
The MFR_PWM_CONFIG command sets the switching frequency phase offset with respect to the falling edge of the SYNC signal. The part must be in the OFF state to process this command. Either the RUN pins must be low or the part must be commanded off. If the part is in the RUN state and this command is written, the command will be ignored and a BUSY fault will be asserted. Bit 7 allows remote differential voltage sensing for PolyPhase rail applications.
|**BIT**|**MEANING**|**MEANING**|
|---|---|---|
|7|EA Connection<br>0 – Independent EA and Channel Outputs<br>1 – EA1 uses EA0 input for PolyPhase operation||
|6|Reserved.||
|5|Reserved||
|4|Share Clock Enable : If this bit is 1, the<br>SHARE_CLK pin will not be released until<br>SVIN> VIN_ON. The SHARE_CLK pin will be<br>pulled low when SVIN< VIN_OFF. If this bit is 0, the SHARE_CLK<br>pin will not be pulled low when SVIN< VIN_OFF except for the<br>initial application of SVIN.||
|3|Reserved||
|**BIT [2:0]**|**CHANNEL 0 (DEGREES)**|**CHANNEL 1 (DEGREES)**|
|000b|0|180|
|001b|90|270|
|010b|0|240|
|011b|0|120|
|100b|120|240|
|101b|60|240|
|110b|120|300|
Do not assert Bit [7] unless it is a PolyPhase application and both VOUT pins are tied together and both COMP _n_ a pins are tied together.
This command has one data byte.
Rev. D
88
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LTM4675
## **APPENDIX C: PMBUS COMMAND DETAILS**
## _**FREQUENCY_SWITCH**_
The FREQUENCY_SWITCH command sets the switching frequency, in kHz, of a PMBus device. See Table 7 for recommended values.
## Supported Frequencies:
|Supported Frequencies|:|
|---|---|
|**VALUE [15:0]**|**RESULTING FREQUENCY(TYP)**|
|0x0000|External Oscillator|
|0xF3E8|250kHz|
|0xFABC|350kHz|
|0xFB52|425kHz|
|0xFBE8|500kHz|
|0x023F|575kHz|
|0x028A|650kHz|
|0x02EE|750kHz|
|0x03E8|1000kHz|
The part must be in the OFF state to process this command. Either the RUN pins must be low or the part must be commanded off. If the part is in the RUN state and this command is written, the command will be ignored and a BUSY fault will be asserted. When the part is commanded off and the frequency is changed, a PLL_UNLOCK status may be detected as the PLL locks onto the new frequency.
This command has two data bytes and is formatted in Linear_5s_11s format.
## **VOLTAGE**
## **Input Voltage (SVIN) and Limits**
|**Input Voltage (SVIN)**|**and Limi**|**ts**|||||||
|---|---|---|---|---|---|---|---|---|
|**COMMAND NAME**|**CMD CODE **|**DESCRIPTION**|**TYPE**|**PAGED**|**DATA**<br>**FORMAT **|**UNITS**|**NVM**|**DEFAULT**<br>**VALUE**|
|VIN_OV_FAULT_ LIMIT|0x55|Input supply (SVIN) overvoltage fault limit.|R/W Word|N|L11|V|Y|17.44<br>0xDA2E|
|VIN_UV_WARN_LIMIT|0x58|Input supply (SVIN) undervoltage warning limit.|R/W Word|N|L11|V|Y|5.297<br>0xCAA6|
|VIN_ON|0x35|Input voltage (SVIN) at which the unit should start<br>power conversion.|R/W Word|N|L11|V|Y|5.500<br>0xCAC0|
|VIN_OFF|0x36|Input voltage (SVIN) at which the unit should stop<br>power conversion.|R/W Word|N|L11|V|Y|5.250<br>0xCAA0|
## _**VIN_OV_FAULT_LIMIT**_
The VIN_OV_FAULT_LIMIT command sets the value of the measured (SVIN) input voltage, in volts, that causes an input overvoltage fault. The fault is detected with the A/D converter resulting in latency up to 90ms, typical.
This command has two data bytes and is formatted in Linear_5s_11s format.
## _**VIN_UV_WARN_LIMIT**_
The VIN_UV_WARN_LIMIT command sets the value of the SVIN input voltage that causes an SVIN input undervoltage warning. The warning is detected with the A/D converter resulting in latency up to 90ms, typical.
This command has two data bytes and is formatted in Linear_5s_11s format.
Rev. D
89
For more information www.analog.com
LTM4675
## **APPENDIX C: PMBUS COMMAND DETAILS**
## _**VIN_ON**_
The VIN_ON command sets the SVIN input voltage, in volts, at which the unit should start power conversion. This command has two data bytes and is formatted in Linear_5s_11s format.
## _**VIN_OFF**_
The VIN_OFF command sets the SVIN input voltage, in volts, at which the unit should stop power conversion. This command has two data bytes and is formatted in Linear_5s_11s format.
## **Output Voltage and Limits**
|**COMMAND NAME**|**CMD CODE**|**DESCRIPTION**|**TYPE**|**PAGED**|**DATA**<br>**FORMAT**|**UNITS**|**NVM**|**DEFAULT**<br>**VALUE**|
|---|---|---|---|---|---|---|---|---|
|VOUT_MODE|0x20|Output voltage format and exponent (2–12).|R Byte|Y|Reg|||2–12<br>0x14|
|VOUT_MAX|0x24|Upper limit on the commanded output voltage<br>includingVOUT_MARGIN_HIGH.|R/W Word|Y|L16|V|Y|5.6<br>0x599A|
|VOUT_OV_FAULT_ LIMIT|0x40|Output overvoltage fault limit.|R/W Word|Y|L16|V|Y|1.1<br>0x119A|
|VOUT_OV_WARN_ LIMIT|0x42|Output overvoltage warning limit.|R/W Word|Y|L16|V|Y|1.075<br>0x1133|
|VOUT_MARGIN_HIGH|0x25|Margin high output voltage set point. Must be<br>greater than VOUT_COMMAND.|R/W Word|Y|L16|V|Y|1.05<br>0x10CD|
|VOUT_COMMAND|0x21|Nominal output voltage set point.|R/W Word|Y|L16|V|Y|1.0<br>0x1000|
|VOUT_MARGIN_LOW|0x26|Margin low output voltage set point. Must be<br>less than VOUT_COMMAND.|R/W Word|Y|L16|V|Y|0.95<br>0x0F33|
|VOUT_UV_WARN_ LIMIT|0x43|Output undervoltage warning limit.|R/W Word|Y|L16|V|Y|0.925<br>0x0ECD|
|VOUT_UV_FAULT_ LIMIT|0x44|Output undervoltage fault limit.|R/W Word|Y|L16|V|Y|0.9<br>0x0E66|
|MFR_VOUT_MAX|0xA5|Maximum allowed output voltage including<br>VOUT_OV_FAULT_LIMIT.|R Word|Y|L16|V||5.7<br>0x5B34|
## _**VOUT_MODE**_
The data byte for VOUT_MODE command, used for commanding and reading output voltage, consists of a 3-bit mode (only linear format is supported) and a 5-bit parameter representing the exponent used in output voltage Read/Write commands.
This read-only command has one data byte.
## _**VOUT_MAX**_
The VOUT_MAX command sets an upper limit on any voltage, including VOUT_MARGIN_HIGH, the unit can command regardless of any other commands or combinations. The maximum allowed value of this command is 5.7 volts. The maximum output voltage the LTM4675 can produce is 5.5 volts including VOUT_MARGIN_HIGH. However, the VOUT_OV_FAULT_LIMIT can be commanded as high as 5.7 volts.
This command has two data bytes and is formatted in Linear_16u format.
Rev. D
90
For more information www.analog.com
LTM4675
## **APPENDIX C: PMBUS COMMAND DETAILS**
## _**VOUT_OV_FAULT_LIMIT**_
The VOUT_OV_FAULT_LIMIT command sets the value of the output voltage measured at the sense pins, in volts, which causes an output overvoltage fault.
If the VOUT_OV_FAULT_LIMIT is modified and the switcher is active, allow 10ms after the command is modified to assure the new value is being honored. The part indicates if it is busy making a calculation. Monitor bits 5 and 6 of MFR_COMMON. Either bit is low if the part is busy. If this wait time is not met, and the VOUT_COMMAND is modified above the old overvoltage limit, an OV condition might temporarily be detected resulting in undesirable behavior and possible damage to the switcher.
If VOUT_OV_FAULT_RESPONSE is set to OV_PULLDOWN, the GPIO pin will not assert if VOUT_OV_FAULT is propagated. The LTM4675 will pull the TG low and assert the BG bit as soon as the overvoltage condition is detected.
This command has two data bytes and is formatted in Linear_16u format.
## _**VOUT_OV_WARN_LIMIT**_
The VOUT_OV_WARN_LIMIT command sets the value of the output voltage measured at the sense pins, in volts, which causes an output voltage high warning. The READ_VOUT value will be used to determine if this limit has been exceeded.
In response to the VOUT_OV_WARN_LIMIT being exceeded, the device:
- Sets the NONE_OF_THE_ABOVE bit in the STATUS_BYTE
- Sets the VOUT bit in the STATUS_WORD
- Sets the VOUT Overvoltage Warning bit in the STATUS_VOUT command
- Notifies the host by asserting ALERT pin, unless masked.
This condition is detected by the ADC so the response time may be up to 90ms, typical.
This command has two data bytes and is formatted in Linear_16u format.
## _**VOUT_MARGIN_HIGH**_
The VOUT_MARGIN_HIGH command loads the unit with the voltage to which the output is to be changed, in volts, when the OPERATION command is set to “Margin High”. The value must be greater than VOUT_COMMAND. The maximum guaranteed value on VOUT_MARGIN_HIGH is 5.5 volts.
This command will not be acted on during TON_RISE and TOFF_FALL output sequencing. The VOUT_TRANSITION_RATE will be used if this command is modified while the output is active and in a steady-state condition.
This command has two data bytes and is formatted in Linear_16u format.
## _**VOUT_COMMAND**_
The VOUT_COMMAND consists of two bytes and is used to set the output voltage, in volts. The maximum guaranteed value on VOUT is 5.5 volts.
This command will not be acted on during TON_RISE and TOFF_FALL output sequencing. The VOUT_TRANSITION_RATE will be used if this command is modified while the output is active and in a steady-state condition.
This command has two data bytes and is formatted in Linear_16u format.
Rev. D
91
For more information www.analog.com
LTM4675
## **APPENDIX C: PMBUS COMMAND DETAILS**
## _**VOUT_MARGIN_LOW**_
The VOUT_MARGIN_LOW command loads the unit with the voltage to which the output is to be changed, in volts, when the OPERATION command is set to “Margin Low”. The value must be less than VOUT_COMMAND.
This command will not be acted on during TON_RISE and TOFF_FALL output sequencing. The VOUT_TRANSITION_RATE will be used if this command is modified while the output is active and in a steady-state condition.
This command has two data bytes and is formatted in Linear_16u format.
## _**VOUT_UV_WARN_LIMIT**_
The VOUT_UV_ WARN_LIMIT command reads the value of the output voltage measured at the sense pins, in volts, which causes an output voltage low warning.
In response to the VOUT_UV_WARN_LIMIT being exceeded, the device:
- Sets the NONE_OF_THE_ABOVE bit in the STATUS_BYTE
- Sets the VOUT bit in the STATUS_WORD
- Sets the VOUT Undervoltage Warning bit in the STATUS_VOUT command
- Notifies the host by asserting ALERT pin, unless masked.
This condition is detected by the ADC so the response time may be up to 90ms, typical.
This command has two data bytes and is formatted in Linear_16u format.
## _**VOUT_UV_FAULT_LIMIT**_
The VOUT_UV_FAULT_LIMIT command reads the value of the output voltage measured at the sense pins, in volts, which causes an output undervoltage fault.
This command has two data bytes and is formatted in Linear_16u format.
## _**MFR_VOUT_MAX**_
The MFR_VOUT_MAX command is the maximum output voltage in volts for each channel including VOUT_OV_FAULT_ LIMIT. If the output voltages are set to high range (Bit 1 of MFR_PWM_MODE set to a 0) MFR_VOUT_MAX for channel 0 and 1 is 5.7V. If the output voltages are set to low range (Bit 1 of MFR_PWM_MODE set to a 1) the MFR_VOUT_MAX for both channels is 2.75V. Entering VOUT_COMMAND values greater than this will result in a CML fault and the output voltage setting will be clamped to the maximum level.
This read-only command has 2 data bytes and is formatted in Linear_16u format.
## **CURRENT**
## **Input Current Calibration**
|**COMMAND NAME**|**CMD CODE**|**DESCRIPTION**|**TYPE**|**PAGED**|**DATA**<br>**FORMAT**|**UNITS**|**NVM**|**DEFAULT**<br>**VALUE**|
|---|---|---|---|---|---|---|---|---|
|MFR_IIN_OFFSET|0xE9|Coefficient used to add to the input current to<br>account for the IQ of thepart.|R/W<br>Word|Y|L11|A|Y|0.02956<br>0x8BC9|
Rev. D
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LTM4675
## **APPENDIX C: PMBUS COMMAND DETAILS**
## _**MFR_IIN_OFFSET**_
The MFR_IIN_OFFSET command allows the user to set an input current representing the quiescent current of each channel. For accurate results at low output current, the part should be in continuous conduction mode. (MFR_PWM_ MODE[0]=1b). See Table 8 for recommended values.
This command has 2 data bytes and is formatted in Linear_5s_11s format.
## **Output Current Calibration**
|**COMMAND NAME**|**CMD**<br>**CODE**|**DESCRIPTION**|**TYPE**|**PAGED**|**DATA**<br>**FORMAT**|**UNITS**|**NVM**|**DEFAULT**<br>**VALUE**|
|---|---|---|---|---|---|---|---|---|
|IOUT_CAL_GAIN|0x38|The ratio of the voltage at the current<br>sensepins to the sensed current.|R/W Word|Y|L11|mΩ|Factory-<br>OnlyNVM|Trimmed,<br>4.46mΩ typical|
|MFR_IOUT_CAL_GAIN_TC|0xF6|Temperature coefficient of the current<br>sensingelement.|R/W Word|Y|CF||Y|3860<br>0x0F14|
## _**IOUT_CAL_GAIN**_
The IOUT_CAL_GAIN command is nominally used to set the resistance value of the current sense element, in milliohms. (see also MFR_IOUT_CAL_GAIN_TC). Writes to this register result in a NACK and do not impact output current readback telemetry.
This command has two data bytes and is formatted in Linear_5s_11s format.
## _**MFR_IOUT_CAL_GAIN_TC**_
The MFR_IOUT_CAL_GAIN_TC command allows the user to program the temperature coefficient of the IOUT_CAL_GAIN inductor DCR in ppm/°C.
This command has two data bytes and is formatted in 16-bit 2’s complement integer ppm. N = –32768 to 32767 • 10[–6] . Nominal temperature is 27°C. The IOUT_CAL_GAIN is multiplied by:
[1.0 + MFR_IOUT_CAL_GAIN_TC • (READ_TEMPERATURE_1-27)]. DCR sensing will have a typical value of 3900.
The IOUT_CAL_GAIN and MFR_IOUT_CAL_GAIN_TC impact all current parameters including: READ_IOUT, READ_IIN, IOUT_OC_FAULT_LIMIT and IOUT_OC_WARN_LIMIT. Writes to this register are not recommended; use the factorydefault value.
## **Input Current**
|**COMMAND NAME**|**CMD CODE **|**DESCRIPTION**|**TYPE**|**PAGED**|**DATA**<br>**FORMAT**|**UNITS**|**NVM**|**DEFAULT**<br>**VALUE**|
|---|---|---|---|---|---|---|---|---|
|IIN_OC_WARN_LIMIT|0x5D|Input overcurrent warning limit.|R/W Word|N|L11|A|Y|8.5<br>0xD220|
## _**IIN_OC_WARN_LIMIT**_
The IIN_OC_WARN_LIMIT command sets the value of the input current, in amperes, that causes a warning indicating the input current is high. The READ_IIN value will be used to determine if this limit has been exceeded.
In response to the IIN_OC_WARN_LIMIT being exceeded, the device:
- Sets the OTHER bit in the STATUS_BYTE
- Sets the INPUT bit in the upper byte of the STATUS_WORD
Rev. D
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LTM4675
## **APPENDIX C: PMBUS COMMAND DETAILS**
- Sets the IIN Overcurrent Warning bit in the STATUS_INPUT command, and
- Notifies the host by asserting ALERT pin, unless masked
This condition is detected by the ADC so the response time may be up to 90ms, typical.
This command has two data bytes and is formatted in Linear_5s_11s format.
## **Output Current**
|**Output Current**|||||||||
|---|---|---|---|---|---|---|---|---|
|**COMMAND NAME**|**CMD CODE**|**DESCRIPTION**|**TYPE**|**PAGED**|**DATA**<br>**FORMAT**|**UNITS**|**NVM**|**DEFAULT**<br>**VALUE**|
|IOUT_OC_FAULT_LIMIT|0x46|Output overcurrent fault limit.|R/W Word|Y|L11|A|Y|15.80<br>0xD3F3|
|IOUT_OC_WARN_LIMIT|0x4A|Output overcurrent warning limit.|R/W Word|Y|L11|A|Y|10.80<br>0xD2B3|
## _**IOUT_OC_FAULT_LIMIT**_
The IOUT_OC_FAULT_LIMIT command sets the value of the peak output current limit, in amperes. When the controller is in current limit, the overcurrent detector will indicate an overcurrent fault condition. The programmed overcurrent fault limit value is rounded up to the nearest one of the following set of discrete values:
|25mV/IOUT_CAL_GAIN|Low Range (1.5x Nominal Loop Gain)<br>MFR_PWM_MODE [7]=0|
|---|---|
|28.6mV/IOUT_CAL_GAIN||
|32.1mV/IOUT_CAL_GAIN||
|35.7mV/IOUT_CAL_GAIN||
|39.3mV/IOUT_CAL_GAIN||
|42.9mV/IOUT_CAL_GAIN||
|46.4mV/IOUT_CAL_GAIN||
|50mV/IOUT_CAL_GAIN||
|37.5mV/IOUT_CAL_GAIN|High Range (Nominal Loop Gain)<br>MFR_PWM_MODE [7]=1|
|42.9mV/IOUT_CAL_GAIN||
|48.2mV/IOUT_CAL_GAIN||
|53.6mV/IOUT_CAL_GAIN||
|58.9mV/IOUT_CAL_GAIN||
|64.3mV/IOUT_CAL_GAIN||
|69.6mV/IOUT_CAL_GAIN||
|75mV/IOUT_CAL_GAIN||
Note: This is the peak of the current waveform. The READ_IOUT command returns the average current. The peak output current limits are adjusted with temperature based on the MFR_IOUT_CAL_GAIN_TC using the equation:
IOUT_OC_FAULT_LIMIT = IOUT_CAL_GAIN • (1 + MFR_IOUT_CAL_GAIN_TC • (READ_TEMPERTURE_1-27.0)).
The LTpowerPlay GUI automatically convert the voltages to currents.
The IOUT range is set with bit 7 of the MFR_PWM_MODE command.
The IOUT_OC_FAULT_LIMIT is ignored during TON_RISE and TOFF_FALL.
This command has two data bytes and is formatted in Linear_5s_11s format.
Rev. D
94
For more information www.analog.com
LTM4675
## **APPENDIX C: PMBUS COMMAND DETAILS**
## _**IOUT_OC_WARN_LIMIT**_
This command sets the value of the output current that causes an output overcurrent warning in amperes. The READ_IOUT value will be used to determine if this limit has been exceeded.
In response to the IOUT_OC_WARN_LIMIT being exceeded, the device:
- Sets the NONE_OF_THE_ABOVE bit in the STATUS_BYTE
- Sets the IOUT bit in the STATUS_WORD
- Sets the IOUT Overcurrent Warning bit in the STATUS_IOUT command, and
- Notifies the host by asserting ALERT pin, unless masked.
This condition is detected by the ADC so the response time may be up to 90ms, typical.
The IOUT_OC_FAULT_LIMIT is ignored during TON_RISE and TOFF_FALL.
This command has two data bytes and is formatted in Linear_5s_11s format
## **TEMPERATURE**
## **Power Stage DCR Temperature Calibration**
|**COMMAND NAME**|**CMD CODE **|**DESCRIPTION**|**TYPE**|**PAGED**|**DATA**<br>**FORMAT **|**UNITS**|**NVM**|**DEFAULT**<br>**VALUE**|
|---|---|---|---|---|---|---|---|---|
|MFR_TEMP_1_GAIN|0xF8|Sets the slope of the power stage temperature<br>sensor.|R/W Word|Y|CF||Y|0.995<br>0x3FAE|
|MFR_TEMP_1_OFFSET|0xF9|Sets the offset of the power stage temperature<br>sensor with respect to –273.1°C.|R/W Word|Y|L11|C|Y|0<br>0x8000|
## _**MFR_TEMP_1_GAIN**_
The MFR_TEMP_1_GAIN command will modify the slope of the power stage temperature sensor to account for nonidealities in the element and errors associated with the remote sensing of the temperature in the inductor.
This command has two data bytes and is formatted in 16-bit 2’s complement integer. N = 8192 to 32767. The effective adjustment is N • 2[–14] . The nominal value is 1.
## _**MFR_TEMP_1_OFFSET**_
The MFR_TEMP_1_OFFSET command will modify the offset of the power stage temperature sensor to account for non-idealities in the element and errors associated with the remote sensing of the temperature in the inductor.
This command has two data bytes and is formatted in Linear_5s_11s format. The part starts the calculation with a value of –273.15 so the default adjustment value is zero.
Rev. D
95
For more information www.analog.com
LTM4675
## **APPENDIX C: PMBUS COMMAND DETAILS**
## **Power Stage Temperature Limits**
|**COMMAND NAME**|**CMD CODE **|**DESCRIPTION**|**TYPE**|**PAGED**|**DATA**<br>**FORMAT**|**UNITS**|**NVM**|**DEFAULT**<br>**VALUE**|
|---|---|---|---|---|---|---|---|---|
|OT_FAULT_LIMIT|0x4F|Power stage overtemperature fault limit.|R/W Word|Y|L11|C|Y|128<br>0xF200|
|OT_WARN_LIMIT|0x51|Power stage overtemperature warning limit.|R/W Word|Y|L11|C|Y|125<br>0xEBE8|
|UT_FAULT_LIMIT|0x53|Power stage undertemperature fault limit.|R/W Word|Y|L11|C|Y|–45<br>0xE530|
## _**OT_FAULT_LIMIT**_
The OT_FAULT_LIMIT command sets the value of the power stage temperature, in degrees Celsius, which causes an overtemperature fault. The READ_TEMPERATURE_1 value will be used to determine if this limit has been exceeded.
This condition is detected by the ADC so the response time may be up to 90ms, typical.
This command has two data bytes and is formatted in Linear_5s_11s format.
## _**OT_WARN_LIMIT**_
The OT_WARN_LIMIT command sets the value of the power stage temperature, in degrees Celsius, which causes an overtemperature warning. The READ_TEMPERATURE_1 value will be used to determine if this limit has been exceeded.
In response to the OT_WARN_LIMIT being exceeded, the device:
- Sets the TEMPERATURE bit in the STATUS_BYTE
- Sets the Overtemperature Warning bit in the STATUS_TEMPERATURE command, and
- Notifies the host by asserting ALERT pin, unless masked.
This condition is detected by the ADC so the response time may be up to 90ms, typical.
This command has two data bytes and is formatted in Linear_5s_11s format.
## _**UT_FAULT_LIMIT**_
The UT_FAULT_LIMIT command sets the value of the power stage temperature, in degrees Celsius, which causes an undertemperature fault. The READ_TEMPERATURE_1 value will be used to determine if this limit has been exceeded.
This condition is detected by the ADC so the response time may be up to 90ms, typical.
This command has two data bytes and is formatted in Linear_5s_11s format.
Rev. D
96
For more information www.analog.com
LTM4675
## **APPENDIX C: PMBUS COMMAND DETAILS**
## **TIMING**
## **Timing—On Sequence/Ramp**
|**COMMAND NAME**|**CMD CODE **|**DESCRIPTION**|**TYPE**|**PAGED**|**DATA**<br>**FORMAT**|**UNITS**|**NVM**|**DEFAULT**<br>**VALUE**|
|---|---|---|---|---|---|---|---|---|
|TON_DELAY|0x60|Time from RUN and/or Operation on to output<br>rail turn-on.|R/W Word|Y|L11|ms|Y|0.0<br>0x8000|
|TON_RISE|0x61|Time from when the output starts to rise<br>until the output voltage reaches the VOUT<br>commanded value.|R/W Word|Y|L11|ms|Y|3.0<br>0xC300|
|TON_MAX_FAULT_LIMIT|0x62|Maximum time from the start of TON_RISE for<br>VOUT to cross the VOUT_UV_FAULT_LIMIT.|R/W Word|Y|L11|ms|Y|5.0<br>0xCA80|
|VOUT_TRANSITION_RATE|0x27|Rate the output changes when VOUT<br>commanded to a new value.|R/W Word|Y|L11|V/ms|Y|0.001<br>0x8042|
## _**TON_DELAY**_
The TON_DELAY command sets the time, in milliseconds, from when a start condition is received until the output voltage starts to rise. Values from 0ms to 83 seconds are valid.
This command has two data bytes and is formatted in Linear_5s_11s format.
## _**TON_RISE**_
The TON_RISE command sets the time, in milliseconds, from the time the output starts to rise to the time the output enters the regulation band. Values from 0 to 1.3 seconds are valid. The part will be in discontinuous mode during TON_RISE events. If TON_RISE is less than 0.25ms, the LTM4675 digital slope will be bypassed. The output voltage transition will be controlled by the analog performance of the PWM switcher. The maximum allowed slope is 4V/ms.
This command has two data bytes and is formatted in Linear_5s_11s format.
## _**TON_MAX_FAULT_LIMIT**_
The TON_MAX_FAULT_LIMIT command sets the value, in milliseconds, on how long the unit can attempt to power up the output without reaching the output undervoltage fault limit.
A data value of 0ms means that there is no limit and that the unit can attempt to bring up the output voltage indefinitely. The maximum limit is 83 seconds.
This command has two data bytes and is formatted in Linear_5s_11s format.
## _**VOUT_TRANSITION_RATE**_
When a PMBus device receives either a VOUT_COMMAND or OPERATION (Margin High, Margin Low) that causes the output voltage to change this command set the rate in V/ms at which the output voltage changes. This commanded rate of change does not apply when the unit is commanded on or off.
This command has two data bytes and is formatted in Linear_5s_11s format.
Rev. D
97
For more information www.analog.com
LTM4675
## **APPENDIX C: PMBUS COMMAND DETAILS**
## **Timing—Off Sequence/Ramp**
|**COMMAND NAME**|**CMD CODE **|**DESCRIPTION**|**TYPE**|**PAGED**|**DATA**<br>**FORMAT**|**UNITS**|**NVM**|**DEFAULT**<br>**VALUE**|
|---|---|---|---|---|---|---|---|---|
|TOFF_DELAY|0x64|Time from RUN and/or Operation off to the start<br>of TOFF_FALL ramp.|R/W Word|Y|L11|ms|Y|0.0<br>0x8000|
|TOFF_FALL|0x65|Time from when the output starts to fall until the<br>output reaches zero volts.|R/W Word|Y|L11|ms|Y|3.0<br>0xC300|
|TOFF_MAX_WARN_LIMIT|0x66|Maximum allowed time, after TOFF_FALL<br>completed,for the unit to decaybelow 12.5%.|R/W Word|Y|L11|ms|Y|0.0<br>0x8000|
## _**TOFF_DELAY**_
The TOFF_DELAY command sets the time, in milliseconds, from when a stop condition is received until the output voltage starts to fall. Values from 0 to 83 seconds are valid.
This command is excluded from fault events.
This command has two data bytes and is formatted in Linear_5s_11s format.
## _**TOFF_FALL**_
The TOFF_FALL command sets the time, in milliseconds, from the end of the turn-off delay time until the output voltage is commanded to zero. It is the ramp time of the VOUT DAC. When the VOUT DAC is zero, the part will three-state.
The part will maintain the mode of operation programmed. For defined TOFF_FALL times, the user should set the part to continuous conduction mode. Loading the max value indicates the part will ramp down at the slowest possible rate. The minimum supported fall time is 0.25ms. A value less than 0.25ms will result in a 0.25ms ramp. The maximum fall time is 1.3 seconds. The maximum allowed slope is 4V/ms.
In discontinuous conduction mode, the controller will not draw current from the load and the fall time will be set by the output capacitance and load current.
This command has two data bytes and is formatted in Linear_5s_11s format.
## _**TOFF_MAX_WARN_LIMIT**_
The TOFF_MAX_WARN_LIMIT command sets the value, in milliseconds, on how long the unit can attempt to turn off the output until a warning is asserted. The output is considered off when the VOUT voltage is less than 12.5% of the programmed VOUT_COMMAND value. The calculation begins after TOFF_FALL is complete. TOFF_MAX_WARN is not enabled in VOUT_DECAY is disabled.
A data value of 0ms means that there is no limit and that the unit can attempt to turn off the output voltage indefinitely. Other than 0, values from 120ms to 524 seconds are valid.
This command has two data bytes and is formatted in Linear_5s_11s format.
## **Precondition for Restart**
|**COMMAND NAME**|**CMD CODE **|**DESCRIPTION**|**TYPE**|**PAGED**|**DATA**<br>**FORMAT**|**UNITS**|**NVM**|**DEFAULT**<br>**VALUE**|
|---|---|---|---|---|---|---|---|---|
|MFR_RESTART_ DELAY|0xDC|Delay from actual RUN active edge to virtual<br>RUN active edge.|R/W Word|Y|L11|ms|Y|300<br>0xFA58|
Rev. D
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LTM4675
## **APPENDIX C: PMBUS COMMAND DETAILS**
## _**MFR_RESTART_DELAY**_
This command specifies the minimum RUN off time in milliseconds. This device will pull the RUN pin low for this length of time once a falling edge of RUN has been detected. The minimum recommended value is 136ms.
Note: The restart delay is different than the retry delay. The restart delay pulls run low for the specified time, after which a standard start-up sequence is initiated. The minimum restart delay should be equal to TOFF_DELAY + TOFF_FALL + 136ms. Valid values are from 136ms to 65.52 seconds in 16ms increments. To assure a minimum off time, set the MFR_RESTART_DELAY 16ms longer than the desired time. The output rail can be off longer than the MFR_ RESTART_DELAY after the RUN pin is pulled high if the output decay bit 1 is enabled in MFR_CHAN_CONFIG and the output takes a long time to decay below 12.5% of the programmed value.
This command has two data bytes and is formatted in Linear_5s_11s format.
## **FAULT RESPONSE**
## **Fault Responses All Faults**
|**COMMAND NAME**|**CMD CODE**|**DESCRIPTION**|**TYPE**|**PAGED**|**DATA**<br>**FORMAT**|**UNITS**|**NVM**|**DEFAULT**<br>**VALUE**|
|---|---|---|---|---|---|---|---|---|
|MFR_RETRY_ DELAY|0xDB|Retry interval during FAULT retry mode.|R/W Word|Y|L11|ms|Y|250<br>0xF3E8|
## _**MFR_RETRY_DELAY**_
This command sets the time in milliseconds between restarts if the fault response is to retry the controller at specified intervals. This command value is used for all fault responses that require retry. The retry time starts once the fault has been detected by the offending channel. Valid values are from 120ms to 83.88 seconds in 1ms increments.
Note: The retry delay time is determined by the longer of the MFR_RETRY_DELAY command or the time required for the regulated output to decay below 12.5% of the programmed value. If the natural decay time of the output is too long, it is possible to remove the voltage requirement of the MFR_RETRY_DELAY command by asserting bit 0 of MFR_CHAN_CONFIG.
This command has two data bytes and is formatted in Linear_5s_11s format.
## **Fault Responses Input Voltage (SVIN)**
|**COMMAND NAME**|**CMD CODE **|**DESCRIPTION**|**TYPE**|**PAGED**|**DATA**<br>**FORMAT**|**UNITS**|**NVM**|**DEFAULT**<br>**VALUE**|
|---|---|---|---|---|---|---|---|---|
|VIN_OV_FAULT_RESPONSE|0x56|Action to be taken by the device when an SVIN<br>input supply overvoltage fault is detected.|R/W Byte|Y|Reg||Y|0xB8|
## _**VIN_OV_FAULT_RESPONSE**_
The VIN_OV_FAULT_RESPONSE command instructs the device on what action to take in response to an (SVIN) input overvoltage fault. The data byte is in the format given in Table 28.
The device also:
- Sets the NONE_OF_THE_ABOVE bit in the STATUS_BYTE
- Set the INPUT bit in the upper byte of the STATUS_WORD
Rev. D
99
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LTM4675
## **APPENDIX C: PMBUS COMMAND DETAILS**
- Sets the SVIN Overvoltage Fault bit in the STATUS_INPUT command, and
- Notifies the host by asserting ALERT pin, unless masked.
This command has one data byte.
## **Fault Responses Output Voltage**
|**COMMAND NAME**|**CMD CODE **|**DESCRIPTION**|**TYPE**|**PAGED**|**DATA**<br>**FORMAT**|**UNITS**|**NVM**|**DEFAULT**<br>**VALUE**|
|---|---|---|---|---|---|---|---|---|
|VOUT_OV_FAULT_RESPONSE|0x41|Action to be taken by the device when an<br>output overvoltage fault is detected.|R/W Byte|Y|Reg||Y|0x7A|
|VOUT_UV_FAULT_RESPONSE|0x45|Action to be taken by the device when an<br>output undervoltage fault is detected.|R/W Byte|Y|Reg||Y|0xB8|
|TON_MAX_FAULT_<br>RESPONSE|0x63|Action to be taken by the device when a<br>TON_MAX_FAULT event is detected.|R/W Byte|Y|Reg||Y|0xB8|
## _**VOUT_OV_FAULT_RESPONSE**_
The VOUT_OV_FAULT_RESPONSE command instructs the device on what action to take in response to an output overvoltage fault. The data byte is in the format given in Table 24.
The device also:
- Sets the VOUT_OV bit in the STATUS_BYTE
- Sets the VOUT bit in the STATUS_WORD
- Sets the VOUT Overvoltage Fault bit in the STATUS_VOUT command
- Notifies the host by asserting ALERT pin, unless masked.
The only value recognized for this command are:
0x80–The device shuts down (disables the output) and the unit does not attempt to retry. The output remains disabled until the fault is cleared (PMBus, Part II, Section 10.7).
0xB8–The device shuts down (disables the output) and device attempts retry continuously, without limitation, until it is commanded OFF (by the RUN pin or OPERATION command or both), bias power is removed, or another fault condition causes the unit to shut down.
0x4n The device shuts down and the unit does not attempt to retry. The output remains disabled until the part is commanded OFF then ON or the RUN pin is asserted low then high or MFR_RESET or RESTORE_USER_ALL through the command or removal of SVIN. The OV fault must remain active for a period of n • 10µs, where n is a value from 0 to 7.
0x78+n The device shuts down and the unit attempts to retry continuously until either the fault condition is cleared or the part is commanded OFF then ON or the RUN pin is asserted low then high or MFR_RESET or RESTORE_USER_ALL through the command or removal of SVIN. The OV fault must remain active for a period of n • 10µs, where n is a value from 0 to 7.
Any other value will result in a CML fault and the write will be ignored.
This command has one data byte.
Rev. D
100
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LTM4675
## **APPENDIX C: PMBUS COMMAND DETAILS**
## **Table 24. VOUT_OV_FAULT_RESPONSE Data Byte Contents**
|**BITS**|**DESCRIPTION**|**VALUE**|**MEANING**|
|---|---|---|---|
|7:6|Response<br>For all values of bits [7:6], the LTM4675:<br>• Sets the corresponding fault bit in the status commands and<br>• Notifies the host by assertingALERTpin, unless masked.<br>The fault bit, once set, is cleared only when one or more of the<br>following events occurs:<br>• The device receives a CLEAR_FAULTS command.<br>• The output is commanded through the RUN_n_pin, the OPERATION<br>command, or the combined action of the RUN_n_pin and<br>OPERATION command, to turn off and then to turn back on, or<br>• Biaspower is removed and reapplied to the LTM4675.|00|Part performs OV pull down only (i.e., turns off the top<br>MOSFET and turns on lower MOSFET while VOUTis ><br>VOUT_OV_FAULT)|
|||01|The PMBus device continues operation for the delay time<br>specified by bits [2:0] and the delay time unit specified for that<br>particular fault. If the fault condition is still present at the end of<br>the delay time, the unit responds as programmed in the Retry<br>Setting (bits[5:3]).|
|||10|The device shuts down immediately (disables the output) and<br>responds accordingto the retrysettingin bits[5:3].|
|||11|Not supported. Writing this value will generate a CML fault.|
|5:3|Retry Setting|000-110|The unit does not attempt to restart. The output remains<br>disabled until the fault is cleared until the device is commanded<br>OFF biaspower is removed.|
|||111|The PMBus device attempts to restart continuously, without<br>limitation, until it is commanded OFF (by the RUN_n_pin or<br>OPERATION command or both), bias power is removed, or<br>another fault condition causes the unit to shut down without<br>retry. Note: The retry interval is set by the MFR_RETRY_DELAY<br>command.|
|2:0|Delay Time|XXX|The delay time in 10µs increments. This delay time determines<br>how long the controller continues operating after a fault is<br>detected. Onlyvalid for deglitched off state|
## _**VOUT_UV_FAULT_RESPONSE**_
The VOUT_UV_FAULT_RESPONSE command instructs the device on what action to take in response to an output undervoltage fault. The data byte is in the format given in Table 25.
The device also:
- Sets the VOUT bit in the STATUS_WORD
- Sets the VOUT undervoltage fault bit in the STATUS_VOUT command
- Notifies the host by asserting ALERT pin, unless masked.
The UV fault and warn are masked until the following criteria are achieved:
- 1) The TON_MAX_FAULT_LIMIT has been reached
- 2) The TON_DELAY sequence has completed
- 3) The TON_RISE sequence has completed
- 4) The VOUT_UV_FAULT_LIMIT threshold has been reached
- 5) The IOUT_OC_FAULT_LIMIT is not present
The UV fault and warn are masked whenever the channel is not active.
The UV fault and warn are masked during TON_RISE and TOFF_FALL sequencing.
This command has one data byte.
Rev. D
101
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LTM4675
## **APPENDIX C: PMBUS COMMAND DETAILS**
## **Table 25. VOUT_UV_FAULT_RESPONSE Data Byte Contents**
|**BITS**|**DESCRIPTION**|**VALUE**|**MEANING**|
|---|---|---|---|
|7:6|Response<br>For all values of bits [7:6], the LTM4675:<br>• Sets the corresponding fault bit in the status commands and<br>• Notifies the host by assertingALERTpin, unless masked.<br>The fault bit, once set, is cleared only when one or more of the<br>following events occurs:<br>• The device receives a CLEAR_FAULTS command<br>• The output is commanded through the RUN_n_pin, the OPERATION<br>command, or the combined action of the RUN_n_pin and<br>OPERATION command, to turn off and then to turn back on, or<br>• Bias power is removed and reapplied to the LTM4675|00|The PMBus device continues operation without interruption.<br>(Ignores the fault functionally)|
|||01|The PMBus device continues operation for the delay time<br>specified by bits [2:0] and the delay time unit specified for<br>that particular fault. If the fault condition is still present at the<br>end of the delay time, the unit responds as programmed in the<br>Retry Setting(bits[5:3]).|
|||10|The device shuts down (disables the output) and responds<br>according to the retry setting in bits[5:3].|
|||11|Not supported. Writing this value will generate a CML fault.|
|5:3|Retry Setting|000-110|The unit does not attempt to restart. The output remains<br>disabled until the fault is cleared until the device is commanded<br>OFF bias power is removed.|
|||111|The PMBus device attempts to restart continuously, without<br>limitation, until it is commanded OFF (by the RUN_n_pin or<br>OPERATION command or both), bias power is removed, or<br>another fault condition causes the unit to shut down without<br>retry. Note: The retry interval is set by the MFR_RETRY_DELAY<br>command.|
|2:0|Delay Time|XXX|The delay time in 10µs increments. This delay time determines<br>how long the controller continues operating after a fault is<br>detected. Only valid for deglitched off state.|
## _**TON_MAX_FAULT_RESPONSE**_
The TON_MAX_FAULT_RESPONSE command instructs the device on what action to take in response to a TON_MAX fault. The data byte is in the format given in Table 28.
The device also:
- Sets the NONE_OF_THE_ABOVE bit in the STATUS_BYTE
- Sets the VOUT bit in the STATUS_WORD
- Sets the TON_MAX_FAULT bit in the STATUS_VOUT command, and
- Notifies the host by asserting ALERT pin, unless masked.
- A value of 0 disables the TON_MAX_FAULT_RESPONSE. It is not recommended to use 0.
This command has one data byte.
Rev. D
102
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LTM4675
## **APPENDIX C: PMBUS COMMAND DETAILS**
## **Fault Responses Output Current**
|**COMMAND NAME**|**CMD CODE**|**DESCRIPTION**|**TYPE**|**PAGED**|**DATA**<br>**FORMAT**|**UNITS**|**NVM**|**DEFAULT**<br>**VALUE**|
|---|---|---|---|---|---|---|---|---|
|IOUT_OC_FAULT_RESPONSE|0x47|Action to be taken by the device when an<br>output overcurrent fault is detected.|R/W Byte|Y|Reg||Y|0x00|
## _**IOUT_OC_FAULT_RESPONSE**_
The IOUT_OC_FAULT_RESPONSE command instructs the device on what action to take in response to an output overcurrent fault. The data byte is in the format given in Table 26.
## The device also:
- Sets the IOUT_OC bit in the STATUS_BYTE
- Sets the IOUT bit in the STATUS_WORD
- Sets the IOUT Overcurrent Fault bit in the STATUS_IOUT command, and
- Notifies the host by asserting ALERT pin, unless masked.
This command has one data byte.
## **Table 26. IOUT_OC_FAULT_RESPONSE Data Byte Contents**
|**BITS**|**DESCRIPTION**|**VALUE**|**MEANING**|
|---|---|---|---|
|7:6|Response<br>For all values of bits [7:6], the LTM4675:<br>• Sets the corresponding fault bit in the status commands and<br>• Notifies the host by assertingALERTpin, unless masked.<br>The fault bit, once set, is cleared only when one or more of the<br>following events occurs:<br>• The device receives a CLEAR_FAULTS command<br>• The output is commanded through the RUN_n_pin, the OPERATION<br>command, or the combined action of the RUN_n_pin and<br>OPERATION command, to turn off and then to turn back on, or<br>• Bias power is removed and reapplied to the LTM4675.|00|The LTM4675 continues to operate indefinitely while<br>maintaining the output current at the value set by IOUT_OC_<br>FAULT_LIMIT without regard to the output voltage (known as<br>constant-current or brick-wall limiting).|
|||01|Not supported.|
|||10|The LTM4675 continues to operate, maintaining the output<br>current at the value set by IOUT_OC_FAULT_LIMIT without<br>regard to the output voltage, for the delay time set by bits [2:0].<br>If the device is still operating in current limit at the end of the<br>delay time, the device responds as programmed by the Retry<br>Setting in bits[5:3].|
|||11|The LTM4675 shuts down immediately and responds as<br>programmed by the Retry Setting in bits [5:3].|
|5:3|Retry Setting|000-110|The unit does not attempt to restart. The output remains<br>disabled until the fault is cleared by cycling the RUN_n_pin or<br>removing bias power.|
|||111|The device attempts to restart continuously, without limitation,<br>until it is commanded OFF (by the RUN_n_pin or OPERATION<br>command or both), bias power is removed, or another fault<br>condition causes the unit to shut down. Note: The retry interval<br>is set by the MFR_RETRY_DELAY command.|
|2:0|Delay Time|XXX|The number of delay time units in 16ms increments. This<br>delay time is used to determine the amount of time a unit is<br>to continue operating after a fault is detected before shutting<br>down. Only valid for deglitched off state.|
Rev. D
103
For more information www.analog.com
LTM4675
## **APPENDIX C: PMBUS COMMAND DETAILS**
## **Fault Responses IC Temperature**
|**COMMAND NAME**|**CMD CODE **|**DESCRIPTION**|**TYPE**|**PAGED**|**DATA**<br>**FORMAT **|**UNITS**|**NVM**|**DEFAULT**<br>**VALUE**|
|---|---|---|---|---|---|---|---|---|
|MFR_OT_FAULT_<br>RESPONSE|0xD6|Action to be taken by the device when an<br>internal overtemperature fault is detected.|R Byte|N|Reg|||0xC0|
## _**MFR_OT_FAULT_RESPONSE**_
The MFR_OT_FAULT_RESPONSE command byte instructs the device on what action to take in response to an internal overtemperature fault. The data byte is in the format given in Table 27.
The LTM4675 also:
- Sets the MFR bit in the STATUS_WORD, and
- Sets the Overtemperature Fault bit in the STATUS_MFR_SPECIFIC command
- Notifies the host by asserting ALERT pin, unless masked.
This command has one data byte.
**Table 27. Data Byte Contents MFR_OT_FAULT_RESPONSE**
|**BITS**|**DESCRIPTION**|**VALUE**|**MEANING**|
|---|---|---|---|
|7:6|Response<br>For all values of bits [7:6], the LTM4675:<br>• Sets the corresponding fault bit in the status commands and<br>• Notifies the host by assertingALERTpin, unless masked.<br>The fault bit, once set, is cleared only when one or more of the<br>following events occurs:<br>• The device receives a CLEAR_FAULTS command<br>• The output is commanded through the RUN_n_pin, the OPERATION<br>command, or the combined action of the RUN_n_pin and<br>OPERATION command, to turn off and then to turn back on, or<br>• Bias power is removed and reapplied to the LTM4675|00|Not supported. Writing this value will generate a CML fault.|
|||01|Not supported. Writing this value will generate a CML fault|
|||10|The device shuts down immediately (disables the output) and<br>responds according to the retry setting in bits[5:3].|
|||11|The device’s output is disabled while the fault is present.<br>Operation resumes and the output is enabled when the fault<br>condition no longer exists.|
|5:3|Retry Setting|000|The unit does not attempt to restart. The output remains<br>disabled until the fault is cleared.|
|||001-111|Not supported. Writing this value will generate CML fault.|
|2:0|Delay Time|XXX|Not supported. Value ignored|
## **Fault Responses Power Stage Temperature**
|**COMMAND NAME**|**CMD CODE **|**DESCRIPTION**|**TYPE**|**PAGED**|**DATA**<br>**FORMAT**|**UNITS**|**NVM**|**DEFAULT**<br>**VALUE**|
|---|---|---|---|---|---|---|---|---|
|OT_FAULT_ RESPONSE|0x50|Action to be taken by the device when a power<br>stage overtemperature fault is detected,|R/W Byte|Y|Reg||Y|0xB8|
|UT_FAULT_ RESPONSE|0x54|Action to be taken by the device when a power<br>stage undertemperature fault is detected.|R/W Byte|Y|Reg||Y|0x00|
Rev. D
104
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LTM4675
## **APPENDIX C: PMBUS COMMAND DETAILS**
## _**OT_FAULT_RESPONSE**_
The OT_FAULT_RESPONSE command instructs the device on what action to take in response to a power stage overtemperature fault. The data byte is in the format given in Table 28.
The device also:
- Sets the TEMPERATURE bit in the STATUS_BYTE
- Sets the Overtemperature Fault bit in the STATUS_TEMPERATURE command, and
- Notifies the host by asserting ALERT pin, unless masked.
This condition is detected by the ADC so the response time may be up to 90ms, typical.
This command has one data byte.
## _**UT_FAULT_RESPONSE**_
The UT_FAULT_RESPONSE command instructs the device on what action to take in response to a power stage undertemperature fault. The data byte is in the format given in Table 28.
The device also:
- Sets the TEMPERATURE bit in the STATUS_BYTE
- Sets the Undertemperature Fault bit in the STATUS_TEMPERATURE command, and
- Notifies the host by asserting ALERT pin, unless masked.
This condition is detected by the ADC so the response time may be up to 90ms, typical.
This command has one data byte.
## **Table 28. Data Byte Contents: TON_MAX_FAULT_RESPONSE, VIN_OV_FAULT_RESPONSE, OT_FAULT_RESPONSE, UT_FAULT_RESPONSE**
|**BITS **|**DESCRIPTION**|**VALUE**|**MEANING**|
|---|---|---|---|
|7:6|Response<br>For all values of bits [7:6], the LTM4675:<br>• Sets the corresponding fault bit in the status commands, and<br>• Notifies the host by assertingALERTpin, unless masked.<br>The fault bit, once set, is cleared only when one or more of the<br>following events occurs:<br>• The device receives a CLEAR_FAULTS command<br>• The output is commanded through the RUN_n_pin, the OPERATION<br>command, or the combined action of the RUN_n_pin and<br>OPERATION command, to turn off and then to turn back on, or<br>• Biaspower is removed and reapplied to the LTM4675|00|The PMBus device continues operation without interruption.|
|||01|Not supported. Writingthis value willgenerate a CML fault.|
|||10|The device shuts down immediately (disables the output) and<br>responds accordingto the retrysettingin bits[5:3].|
|||11|Not supported. Writing this value will generate a CML fault.|
|5:3|Retry Setting|000-110|The unit does not attempt to restart. The output remains disabled<br>until the fault is cleared until the device is commanded OFF bias<br>power is removed.|
|||111|The PMBus device attempts to restart continuously, without<br>limitation, until it is commanded OFF (by the RUN_n_pin or<br>OPERATION command or both), bias power is removed, or another<br>fault condition causes the unit to shut down without retry. Note:<br>The retryinterval is set bythe MFR_RETRY_DELAY command.|
|2:0|DelayTime|XXX|Not supported. Values ignored|
Rev. D
105
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LTM4675
## **APPENDIX C: PMBUS COMMAND DETAILS**
## **FAULT SHARING**
## **Fault Sharing Propagation**
|**COMMAND NAME**|**CMD CODE**|**DESCRIPTION**|**TYPE**|**PAGED**|**DATA**<br>**FORMAT**|**UNITS**|**NVM**|**DEFAULT**<br>**VALUE**|
|---|---|---|---|---|---|---|---|---|
|MFR_GPIO_ PROPAGATE_n_|0xD2|Configuration that determines which faults are<br>propagated to theGPIOpins.|R/W Word|Y|Reg||Y|0x6893|
## _**MFR_GPIO_PROPAGATE**_
The MFR_GPIO_PROPAGATE command enables the faults that can cause the GPIO _n_ pin to assert low. The command is formatted as shown in Table 29. Faults can only be propagated to the GPIO if they are programmed to respond to faults. This command has two data bytes.
**Table 29. GPIO** _**n**_ **Propagate Fault Configuration. The GPIO0 and GPIO1 pins are designed to provide electrical notification of selected events to the user. Some of these events are common to both output channels. Others are specific to an output channel. They can also be used to share faults between channels.**
|**BIT(S)**|**SYMBOL**|**OPERATION**|
|---|---|---|
|B[15]|VOUT disabled while not decayed.|This is used in a PolyPhase configuration when bit 0 of the MFR_CHAN_CONFIG is a zero. If the<br>channel is turned off, by toggling the RUN pin or commanding the part OFF, and then the RUN<br>is reasserted or the part is commanded back on before the output has decayed, VOUT will not<br>restart until the 12.5% decay is honored. TheGPIOpin is asserted during this condition if bit 15<br>is asserted.|
|B[14]|Mfr_gpio_propagate_short_CMD_cycle|0: No action<br>1: Asserts low if commanded off then on before the output has sequenced off. Re-asserts high<br>120ms after sequence off.|
|b[13]|Mfr_gpio_propagate_ton_max_fault|0: No action if a TON_MAX_FAULT fault is asserted<br>1: Associated output will be asserted low if a TON_MAX_FAULT fault is asserted<br>GPIO0is associated with page 0 TON_MAX_FAULT faults<br>GPIO1is associated withpage 1 TON_MAX_FAULT faults|
|b[12]|Mfr_gpio0_propagate_vout_uvuf,<br>Mfr_gpio1_propagate_vout_uvuf|Unfiltered VOUT_UV_FAULT_LIMIT comparator output<br>GPIO0is associated with channel 0<br>GPIO1is associated with channel 1|
|b[11]|Mfr_gpio0_propagate_int_ot,<br>Mfr_gpio1_propagate_int_ot|0: No action if the MFR_OT_FAULT_LIMIT fault is asserted<br>1: Associated output will be asserted low if the MFR_OT_FAULT_LIMIT fault is asserted|
|b[10]|Mfr_pwrgd1_en*|0: No action if channel 1 POWER_GOOD is not true<br>1: Associated output will be asserted low if channel 1 POWER_GOOD is not true<br>If this bit is asserted, the GPIO_FAULT_RESPONSE must be ignore. If the GPIO_FAULT_<br>RESPONSE is not set to ignore,thepart will latch off and never be able to start.|
|b[9]|Mfr_pwrgd0_en*|0: No action if channel 0 POWER_GOOD is not true<br>1: Associated output will be asserted low if channel 0 POWER_GOOD is not true<br>If this bit is asserted, the GPIO_FAULT_RESPONSE must be ignore. If the GPIO_FAULT_<br>RESPONSE is not set to ignore,thepart will latch off and never be able to start.|
|b[8]|Mfr_gpio0_propagate_ut,<br>Mfr_gpio1_propagate_ut|0: No action if the UT_FAULT_LIMIT fault is asserted<br>1: Associated output will be asserted low if the UT_FAULT_LIMIT fault is asserted<br>GPIO0is associated with page 0 UT faults<br>GPIO1is associated withpage 1 UT faults|
Rev. D
106
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LTM4675
## **APPENDIX C: PMBUS COMMAND DETAILS**
**Table 29. GPIO** _**n**_ **Propagate Fault Configuration. The GPIO0 and GPIO1 pins are designed to provide electrical notification of selected events to the user. Some of these events are common to both output channels. Others are specific to an output channel. They can also be used to share faults between channels.**
|**BIT(S)**|**SYMBOL**|**OPERATION**|
|---|---|---|
|b[7]|Mfr_gpio0_propagate_ot,<br>Mfr_gpio1_propagate_ot|0: No action if the OT_FAULT_LIMIT fault is asserted<br>1: Associated output will be asserted low if the OT_FAULT_LIMIT fault is asserted<br>GPIO0is associated with page 0 OT faults<br>GPIO1is associated withpage 1 OT faults|
|b[6]|Reserved||
|b[5]|Reserved||
|b[4]|Mfr_gpio0_propagate_input_ov,<br>Mfr_gpio1_propagate_input_ov|0: No action if the VIN_OV_FAULT_LIMIT fault is asserted<br>1: Associated output will be asserted low if the VIN_OV_FAULT_LIMIT fault is asserted|
|b[3]|Reserved||
|b[2]|Mfr_gpio0_propagate_iout_oc,<br>Mfr_gpio1_propagate_iout_oc|0: No action if the IOUT_OC_FAULT_LIMIT fault is asserted<br>1: Associated output will be asserted low if the IOUT_OC_FAULT_LIMIT fault is asserted<br>GPIO0is associated with page 0 OC faults<br>GPIO1is associated withpage 1 OC faults|
|b[1]|Mfr_gpio0_propagate_vout_uv,<br>Mfr_gpio1_propagate_vout_uv|0: No action if the VOUT_UV_FAULT_LIMIT fault is asserted<br>1: Associated output will be asserted low if the VOUT_UV_FAULT_LIMIT fault is asserted<br>GPIO0is associated with page 0 UV faults<br>GPIO1is associated withpage 1 UV faults|
|b[0]|Mfr_gpio0_propagate_vout_ov,<br>Mfr_gpio1_propagate_vout_ov|0: No action if the VOUT_OV_FAULT_LIMIT fault is asserted<br>1: Associated output will be asserted low if the VOUT_OV_FAULT_LIMIT fault is asserted<br>GPIO0is associated with page 0 OV faults<br>GPIO1is associated withpage 1 OV faults|
*The PWRGD status is designed as an indicator and not to be used for power supply sequencing.
## **Fault Sharing Response**
|**COMMAND NAME**|**CMD CODE **|**DESCRIPTION**|**TYPE**|**PAGED**|**DATA**<br>**FORMAT**|**UNITS**|**NVM**|**DEFAULT**<br>**VALUE**|
|---|---|---|---|---|---|---|---|---|
|MFR_GPIO_RESPONSE|0xD5|Action to be taken by the device when theGPIOpin<br>is asserted low.|R/W Byte|Y|Reg||Y|0xC0|
## _**MFR_GPIO_RESPONSE**_
This command determines the controller’s response to the GPIO _n_ pin being pulled low by an external source.
|**VALUE**|**MEANING**|
|---|---|
|0xC0|GPIO_INHIBIT The LTM4675 will three-state the output in response to theGPIO pinpulled low.|
|0x00|GPIO_IGNORE The LTM4675 continues operation without interruption.|
## The device also:
- Sets the NONE_OF_THE_ABOVE bit in the STATUS_BYTE
- Sets the MFR bit in the STATUS_WORD
- Sets the GPIOB bit in the STATUS_MFR_SPECIFIC command, and
- Notifies the host by asserting ALERT pin, unless masked. The ALERT pin pulled low can be disabled by setting bit[1] of MFR_CHAN_CFG.
This command has one data byte.
Rev. D
107
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LTM4675
## **APPENDIX C: PMBUS COMMAND DETAILS**
## **SCRATCHPAD**
|**SCRATCHPAD**|||||||||
|---|---|---|---|---|---|---|---|---|
|**COMMAND NAME**|**CMD CODE**|**DESCRIPTION**|**TYPE**|**PAGED**|**DATA**<br>**FORMAT **|**UNITS**|**NVM**|**DEFAULT**<br>**VALUE**|
|USER_DATA_00|0xB0|OEM reserved. Typicallyused forpart serialization.|R/W Word|N|Reg||Y|NA|
|USER_DATA_01|0xB1|Manufacturer reserved for LTpowerPlay.|R/W Word|Y|Reg||Y|NA|
|USER_DATA_02|0xB2|OEM reserved. Typicallyused forpart serialization.|R/W Word|N|Reg||Y|NA|
|USER_DATA_03|0xB3|A NVM word available for the user.|R/W Word|Y|Reg||Y|0x0000|
|USER_DATA_04|0xB4|A NVM word available for the user.|R/W Word|N|Reg||Y|0x0000|
## _**USER_DATA_00**_ **through** _**USER_DATA_04**_
These commands are non-volatile memory locations for customer storage. The customer has the option to write any value to the USER_DATA_nn at any time. However, the LTpowerPlay software and contract manufacturers use some of these commands for inventory control. Modifying the reserved USER_DATA_nn commands may lead to undesirable inventory control and incompatibility with these products.
These commands have 2 data bytes and are in register format.
## **IDENTIFICATION**
|**COMMAND NAME**|**CMD CODE **|**DESCRIPTION**|**TYPE**|**PAGED**|**DATA**<br>**FORMAT **|**UNITS**|**NVM**|**DEFAULT**<br>**VALUE**|
|---|---|---|---|---|---|---|---|---|
|PMBUS_REVISION|0x98|PMBus revision supported by this device. Current<br>revision is 1.2.|R Byte|N|Reg|||0x22|
|CAPABILITY|0x19|Summary of PMBus optional communication protocols<br>supported bythis device.|R Byte|N|Reg|||0xB0|
|MFR_ID|0x99|The manufacturer ID of the LTM4675 in ASCII.|R String|N|ASC|||LTC|
|MFR_MODEL|0x9A|Manufacturerpart number in ASCII.|R String|N|ASC|||LTM4675*|
|MFR_SERIAL|0x9E|Serial number of this specific unit in ASCII.|R Block|N|CF|||NA|
|MFR_SPECIAL_ID|0xE7|Manufacturer code representingthe LTM4675.|R Word|N|Reg|||0x47AX|
* The MFR_MODEL value is "LTM4675 ". The value consists of 8 ASCII characters and the last character is a blank space punctuation character (" "), i.e., ASCII code 0x20 or 32d.
## _**PMBus_REVISION**_
The PMBUS_REVISION command indicates the revision of the PMBus to which the device is compliant. The LTM4675 is PMBus Version 1.2 compliant in both Part I and Part II.
This read-only command has one data byte.
## _**CAPABILITY**_
This command provides a way for a host system to determine some key capabilities of a PMBus device. The LTM4675 supports packet error checking, 400kHz bus speeds, and ALERT pin.
This read-only command has one data byte.
## _**MFR_ID**_
The MFR_ID command indicates the manufacturer ID of the LTM4675 using ASCII characters.
This read-only command is in block format.
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## **APPENDIX C: PMBUS COMMAND DETAILS**
## _**MFR_MODEL**_
The MFR_MODEL command indicates the manufacturer’s part number of the LTM4675 using ASCII characters. The MFR_MODEL value is “LTM4675 ”. The value consists of 8 ASCII characters and the last character is a blank space punctuation character (“ ”), i.e., ASCII code 0x20 or 32d.
This read-only command is in block format.
## _**MFR_SERIAL**_
The MFR_SERIAL command contains up to 9 bytes of custom formatted data used to uniquely identify the LTM4675 configuration.
This read-only command is in block format.
## _**MFR_SPECIAL_ID**_
The 16-bit word representing the part name. The 0x47A prefix denotes the part is an LTM4675, X is adjustable by the manufacturer.
This read-only command has 2 data bytes.
## **FAULT WARNING AND STATUS**
|**COMMAND NAME**|**CMD CODE**|**DESCRIPTION**|**TYPE**|**PAGED**|**FORMAT**|**UNITS**|**NVM**|**DEFAULT**<br>**VALUE**|
|---|---|---|---|---|---|---|---|---|
|CLEAR_FAULTS|0x03|Clear anyfault bits that have been set.|Send Byte|N||||NA|
|SMBALERT_MASK|0x1B|MaskALERTActivity.|Block R/W|Y|Reg||Y|See CMD<br>Details|
|MFR_CLEAR_PEAKS|0xE3|Clears allpeaks values.|Send Byte|N||||NA|
|STATUS_BYTE|0x78|One byte summary of the unit’s fault<br>condition.|R/W Byte|Y|Reg|||NA|
|STATUS_WORD|0x79|Two byte summaryof the unit’s fault condition.|R/W Word|Y|Reg|||NA|
|STATUS_VOUT|0x7A|Output voltage fault and warningstatus.|R/W Byte|Y|Reg|||NA|
|STATUS_IOUT|0x7B|Output current fault and warningstatus.|R/W Byte|Y|Reg|||NA|
|STATUS_INPUT|0x7C|Input supply (SVIN)fault and warningstatus.|R/W Byte|N|Reg|||NA|
|STATUS_ TEMPERATURE|0x7D|TSNS_n_a-sensed fault and warning status for<br>READ_TEMERATURE_1.|R/W Byte|Y|Reg|||NA|
|STATUS_CML|0x7E|Communication and memory fault and<br>warningstatus.|R/W Byte|N|Reg|||NA|
|STATUS_MFR_ SPECIFIC|0x80|Manufacturer specific fault and state<br>information.|R/W Byte|Y|Reg|||NA|
|MFR_PADS|0xE5|Digital status of the I/Opads.|R Word|N|Reg|||NA|
|MFR_COMMON|0xEF|Manufacturer status bits that are common<br>across multiple ADI ICs/modules.|R Byte|N|Reg|||NA|
|MFR_INFO|0xB6|ManufacturingSpecific Information|R Word|N|Reg|||NA|
## _**CLEAR_FAULTS**_
The CLEAR_FAULTS command is used to clear any fault bits that have been set. This command clears all bits in all status commands simultaneously. At the same time, the device negates (clears, releases) its ALERT pin signal output if the device is asserting the ALERT pin signal. If the fault is still present when the bit is cleared, the fault bit will remain
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LTM4675
## **APPENDIX C: PMBUS COMMAND DETAILS**
set and the host notified by asserting the ALERT pin low. CLEAR_FAULTS can take up to 10µs to process. If a fault occurs within that time frame it may be cleared before the status register is set.
This write-only command has no data bytes.
The CLEAR_FAULTS does not cause a unit that has latched off for a fault condition to restart. Units that have shut down for a fault condition are restarted when:
- The output is commanded through the RUN pin, the OPERATION command, or the combined action of the RUN pin and OPERATION command, to turn off and then to turn back on, or
- MFR_RESET or RESTORE_USER_ALL command is issued.
- Bias power is removed and reapplied to the integrated circuit
## _**MFR_CLEAR_PEAKS**_
The MFR_CLEAR_PEAKS command clears the MFR_*_PEAK data values. A MFR_RESET or RESTORE_USER_ALL will initiate this command.
This write-only command has no data bytes.
## _**SMBALERT_MASK**_
The SMBALERT_MASK command can be used to prevent a particular status bit or bits from asserting ALERT as they are asserted.
Figure 57 shows an example of the Write Word format used to set an ALERT mask, in this case without PEC. The bits in the mask byte align with bits in the specified status register. For example, if the STATUS_TEMPERATURE command code is sent in the first data byte, and the mask byte contains 0x40, then a subsequent External Overtemperature Warning would still set bit 6 of STATUS_TEMPERATURE but not assert ALERT. All other supported STATUS_TEMPERATURE bits would continue to assert ALERT if set.
Figure 58 shows an example of the Block Write – Block Read Process Call protocol used to read back the present state of any supported status register, again without PEC.
SMBALERT_MASK cannot be applied to STATUS_BYTE, STATUS_WORD, MFR_COMMON or MFR_PADS. Factory default masking for applicable status registers is shown below. Providing an unsupported command code to SMBALERT_MASK will generate a CML for Invalid/Unsupported Data.
|<br>nvalid/Unsupported Data.|<br>nvalid/Unsupported Data.|<br>nvalid/Unsupported Data.|<br>nvalid/Unsupported Data.|<br>nvalid/Unsupported Data.|<br>nvalid/Unsupported Data.|<br>nvalid/Unsupported Data.|<br>nvalid/Unsupported Data.|<br>nvalid/Unsupported Data.|<br>nvalid/Unsupported Data.|<br>nvalid/Unsupported Data.|
|---|---|---|---|---|---|---|---|---|---|---|
|1<br>7<br>8<br>8<br>1<br>8<br>1<br>1<br>1<br>1<br>1|||||||||||
|S|SLAVE<br>ADDRESS|W|A|SMBALERT_MASK<br>COMMAND CODE|A|STATUS_x<br>COMMAND CODE|A|MASK BYTE|A|P|
|4675 F57|||||||||||
**Figure 57. Example of Setting SMBALERT_MASK**
**==> picture [306 x 70] intentionally omitted <==**
**----- Start of picture text -----**<br>
1 7 1 1 8 1 8 1 8 1<br>S SLAVE W A SMBALERT_MASK A BLOCK COUNT A STATUS_x A …<br>ADDRESS COMMAND CODE (= 1) COMMAND CODE<br>1 7 1 1 8 1 8 1 1<br>SLAVE BLOCK COUNT<br>Sr R A A MASK BYTE NA P<br>ADDRESS (= 1)<br>**----- End of picture text -----**<br>
**Figure 58. Example of Reading SMBALERT_MASK**
4675 F58
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## **APPENDIX C: PMBUS COMMAND DETAILS**
**SMBALERT_MASK Default Setting: (Refer Also to Summary of the Status Registers, Figure 59)**
|**STATUS RESISTER**|**ALERT Mask Value **|**MASKED BITS**|
|---|---|---|
|STATUS_VOUT_n_|0x00|None|
|STATUS_IOUT_n_|0x00|None|
|STATUS_TEMPERATURE_n_|0x00|None|
|STATUS_CML|0x00|None|
|STATUS_INPUT|0x00|None|
|STATUS_MFR_SPECIFIC_n_|0x11|Bit 4(internal PLL unlocked), bit 0(GPIO_n_pulled low by external device)|
## _**STATUS_BYTE**_
The STATUS_BYTE command returns a one-byte summary of the most critical faults.
## **STATUS_BYTE Message Contents:**
|**BIT**|**STATUS BIT NAME**|**MEANING**|
|---|---|---|
|7|BUSY|A fault was declared because the LTM4675 was unable to respond.|
|6|OFF|This bit is set if the channel is not providing power to its output, regardless of the reason, including simply not<br>beingenabled.|
|5|VOUT_OV|An output overvoltage fault has occurred.|
|4|IOUT_OC|An output overcurrent fault has occurred.|
|3|VIN_UV|Not supported(LTM4675 returns 0).|
|2|TEMPERATURE|A temperature fault or warninghas occurred.|
|1|CML|A communications, memoryor logic fault has occurred.|
|0|NONE OF THE ABOVE|A fault Not listed in bits[7:1]has occurred.|
This command has one data byte
Any supported fault bit in this command will initiate an ALERT event.
## _**STATUS_WORD**_
The STATUS_WORD command returns a two-byte summary of the channel’s fault condition. The low byte of the STATUS_WORD is the same as the STATUS_BYTE command.
## **STATUS_WORD High Byte Message Contents:**
|**BIT**|**STATUS BIT NAME**|**MEANING**|
|---|---|---|
|15|VOUT|An output voltage fault or warninghas occurred.|
|14|IOUT|An output current fault or warninghas occurred.|
|13|INPUT|An SVINinput voltage fault or warninghas occurred.|
|12|MFR_SPECIFIC|A fault or warningspecific to the LTM4675 has occurred.|
|11|POWER_GOOD#|The POWER_GOOD state is false if this bit is set.|
|10|FANS|Not supported(LTM4675 returns 0).|
|9|OTHER|Not supported(LTM4675 returns 0).|
|8|UNKNOWN|Not supported(LTM4675 returns 0).|
Any supported fault bit in this command will initiate an ALERT event.
This command has two data bytes.
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## **APPENDIX C: PMBUS COMMAND DETAILS**
## _**STATUS_VOUT**_
The STATUS_VOUT command returns one byte of VOUT status information.
## **STATUS_VOUT Message Contents:**
|**BIT**|**MEANING**|
|---|---|
|7|VOUTovervoltage fault.|
|6|VOUTovervoltage warning.|
|5|VOUTundervoltage warning.|
|4|VOUTundervoltage fault.|
|3|VOUT_MAX warning.|
|2|TON_MAX fault.|
|1|TOFF_MAX warning.|
|0|Not supported bythe LTM4675(returns 0).|
ALERT can be asserted if any of bits[7:1] are set. These may be cleared by writing a 1 to their bit position in STATUS_VOUT, in lieu of a CLEAR_FAULTS command.
This command has one data byte.
## _**STATUS_IOUT**_
The STATUS_IOUT command returns one byte of IOUT status information.
## **STATUS_IOUT Message Contents:**
|**BIT**|**MEANING**|
|---|---|
|7|IOUTovercurrent fault.|
|6|Not supported(LTM4675 returns 0).|
|5|IOUTovercurrent warning.|
|4:0|Not supported(LTM4675 returns 0).|
ALERT can be asserted if any supported bits are set. Any supported bit may be cleared by writing a 1 to that bit position in STATUS_IOUT, in lieu of a CLEAR_FAULTS command.
This command has one data byte.
## _**STATUS_INPUT**_
The STATUS_INPUT command returns one byte of VIN (SVIN) status information.
## **STATUS_INPUT Message Contents:**
|**BIT**|**MEANING**|
|---|---|
|7|SVINovervoltage fault.|
|6|Not supported(LTM4675 returns 0).|
|5|SVINundervoltage warning.|
|4|Not supported(LTM4675 returns 0).|
|3|Unit off for insufficient SVINvoltage.|
|2|Not supported(LTM4675 returns 0).|
|1|Input over current warning.|
|0|Not supported(LTM4675 returns 0)|
ALERT can be asserted if bit 7 is set. Bit 7 may be cleared by writing it to a 1, in lieu of a CLEAR_FAULTS command.
This command has one data byte.
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LTM4675
## **APPENDIX C: PMBUS COMMAND DETAILS**
## _**STATUS_TEMPERATURE**_
The STATUS_TEMPERATURE command returns one byte of sensed power stage temperature status information.
## **STATUS_TEMPERATURE Message Contents:**
|**BIT**|**MEANING**|
|---|---|
|7|External overtemperature fault.|
|6|External overtemperature warning.|
|5|Not supported(LTM4675 returns 0).|
|4|External undertemperature fault.|
|3:0|Not supported(LTM4675 returns 0).|
ALERT can be asserted if any supported bits are set. Any supported bit may be cleared by writing a 1 to that bit position in STATUS_TEMPERATURE, in lieu of a CLEAR_FAULTS command.
This command has one data byte.
## _**STATUS_CML**_
The STATUS_CML command returns one byte of status information on received commands, internal memory and logic.
## **STATUS_CML Message Contents:**
|**BIT**|**MEANING**|
|---|---|
|7|Invalid or unsupported command received.|
|6|Invalid or unsupported data received.|
|5|Packet error check failed.|
|4|Memoryfault detected.|
|3|Processor fault detected.|
|2|Reserved(LTM4675 returns 0).|
|1|Other communication fault.|
|0|Other memoryor logic fault.|
ALERT can be asserted if any supported bits are set. Any supported bit may be cleared by writing a 1 to that bit position in STATUS_CML, in lieu of a CLEAR_FAULTS command.
This command has one data byte.
## _**STATUS_MFR_SPECIFIC**_
The STATUS_MFR_SPECIFIC commands returns one byte with the manufacturer specific status information. Each channel has a copy of the same information. Only bit 0 is page specific.
The format for this byte is:
|**BIT**|**MEANING**|
|---|---|
|7|Internal Temperature Fault Limit Exceeded.|
|6|Internal Temperature Warn Limit Exceeded.|
|5|NVM CRC Fault.|
|4|PLL is Unlocked|
|3|Fault LogPresent|
|2|VDD33UV or OV Fault|
|0|GPIOPin Asserted Low byExternal Device(paged)|
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## **APPENDIX C: PMBUS COMMAND DETAILS**
If any of these bits are set, the MFR bit in the STATUS_WORD will be set.
The user is permitted to write a 1 to any bit in this command to clear a specific fault. This permits the user to clear status by means other than using the CLEAR_FAULTS command. Exception: The fault log present bit can only be cleared by issuing the MFR_FAULT_LOG_CLEAR command.
Any supported fault bit in this command will initiate an ALERT event.
This command has one data byte.
## _**MFR_PADS**_
This command provides the user a means of directly reading the digital status of the I/O pins of the device. The bit assignments of this command are as follows:
|**BIT**|**ASSIGNED DIGITAL PIN**|
|---|---|
|15|VDD33OV Fault|
|14|VDD33UV Fault|
|13|Reserved|
|12|Reserved|
|11|ADC Values Invalid,Occurs DuringStart-Up|
|10|SYNC Output Disabled Due to External Clock|
|9|PowerGood1|
|8|PowerGood0|
|7|Device DrivingRUN1Low|
|6|Device DrivingRUN0Low|
|5|RUN1|
|4|RUN0|
|3|Device Driving GPIO1Low|
|2|Device Driving GPIO0Low|
|1|GPIO1|
|0|GPIO0|
A 1 indicates the condition is true.
This read-only command has two data bytes.
## _**MFR_COMMON**_
The MFR_COMMON command contains bits that are common to all ADI digital power and telemetry products.
|**BIT**|**MEANING**|
|---|---|
|7|MODULE NOT DRIVINGALERTLOW|
|6|MODULE NOT BUSY|
|5|CALCULATIONS NOT PENDING|
|4|OUTPUT NOT IN TRANSITION|
|3|NVM Initialized|
|2|Reserved|
|1|SHARE_CLK Timeout|
|0|WP Pin Status|
This read-only command has one data byte.
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## **APPENDIX C: PMBUS COMMAND DETAILS**
||||||**STATUS_WORD**|**STATUS_WORD**|**STATUS_WORD**|||**STATUS_INPUT**<br>7<br>6<br>5<br>4<br>3<br>2<br>1<br>0<br>VIN_OV Fault SVIN<br>(reads 0)<br>VIN_UV Warning SVIN<br>(reads 0)<br>Unit Off for Insuffcient SVINVoltage<br>(reads 0)<br>IIN_OC Warning<br>(reads 0)|**STATUS_INPUT**<br>7<br>6<br>5<br>4<br>3<br>2<br>1<br>0<br>VIN_OV Fault SVIN<br>(reads 0)<br>VIN_UV Warning SVIN<br>(reads 0)<br>Unit Off for Insuffcient SVINVoltage<br>(reads 0)<br>IIN_OC Warning<br>(reads 0)|**STATUS_INPUT**<br>7<br>6<br>5<br>4<br>3<br>2<br>1<br>0<br>VIN_OV Fault SVIN<br>(reads 0)<br>VIN_UV Warning SVIN<br>(reads 0)<br>Unit Off for Insuffcient SVINVoltage<br>(reads 0)<br>IIN_OC Warning<br>(reads 0)|**STATUS_INPUT**<br>7<br>6<br>5<br>4<br>3<br>2<br>1<br>0<br>VIN_OV Fault SVIN<br>(reads 0)<br>VIN_UV Warning SVIN<br>(reads 0)<br>Unit Off for Insuffcient SVINVoltage<br>(reads 0)<br>IIN_OC Warning<br>(reads 0)|
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|**STATUS_VOUT***|||||1|5|VOUT|||||||
|7||VOUTOV Fault|||1|4|IOUT|||||||
|6||_<br>VOUT_OV Warning|||1|3|INPUT|||||||
|||||||||||||||
|5||VOUT_UV Warning|||1|2|MFR_SPECIFIC|||||||
|||||||||||||||
|4||VOUT_UV Fault|||1|1|POWER_GOOD#|||||||
|3||VOUT_MAX Warning|||1|0|(reads 0)|||||||
|2||TON_MAX Fault|||9||(reads 0)|||||||
|1||TOFF_MAX Warning|||8||(reads 0)|||||||
|0||(reads 0)||||**STATUS_BYTE**||||||||
||||||7||BUSY|||||||
||||||6||OFF|||||||
||||||5||VOUT_OV|||||||
||||||4||IOUT_OC|||||||
||||||3||(reads 0)|||**STATUS_MFR_SPECIFIC**||||
||||||2||TEMPERATURE|||7||Internal Temperature Fault||
||||||1||CML|||6||Internal Temperature Warning||
||||||0||NONE OF THE ABOVE|||5||EEPROM CRC Error||
|||||||||||4||Internal PLL Unlocked||
|||||||||||3||Fault Log Present||
|||||||||||2||(reads 0)||
|||||||||||1||VOUT Short Cycled||
|||||||||||0||GPIOPulled Low By External Device||
|||||||||||||||
|||||||||||**MFR_PADS**<br>15<br>14<br>13<br>12<br>11<br>10<br>9<br>8<br>7<br>6<br>5<br>4<br>3<br>2<br>1<br>0<br>VDD33 0V<br>VDD33 UV<br>(reads 0)<br>(reads 0)<br>Invalid ADC Result(s)<br>SYNC Output Disabled Externally<br>Channel 1 is POWER_GOOD<br>Channel 0 is POWER_GOOD<br>LTM4675 Forcing RUN1 Low<br>LTM4675 Forcing RUN0 Low<br>RUN1 Pin State<br>RUN0 Pin State<br>LTM4675 ForcingGPIO1Low<br>LTM4675 ForcingGPIO0Low<br>GPIO1Pin State<br>GPIO0Pin State<br>4675 F59||||
|**DESCRIPTION**|**MASKABLE**|**GENERATESALERT**|**BIT CLEARABLE**|
|---|---|---|---|
|General Fault or Warning Event|Yes|Yes|Yes|
|Dynamic|No|No|No|
|Status Derived from Other Bits|No|Not Directly|No|
**Figure 59. Summary of the Status Registers**
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## **APPENDIX C: PMBUS COMMAND DETAILS**
## _**MFR_INFO**_
The MFR_INFO command contains additional status bits that are LTM4675-specific and may be common to multiple ADI PSM products.
## **MFR_INFO Data Contents:**
|**BIT**|**MEANING**|
|---|---|
|15:6|Reserved.|
|5|EEPROM ECC status.<br>0: Corrections have been made in the EEPROM user space.<br>1: No corrections have been made in the EEPROM user space.|
|4:0|Reserved|
EEPROM ECC status is updated after each RESTORE_USER_ALL or RESET command, a power-on reset or an EEPROM bulk read operation. This read-only command has two data bytes.
## **TELEMETRY**
|**TELEMETRY**|||||||||
|---|---|---|---|---|---|---|---|---|
|**COMMAND NAME**|**CMD**<br>**CODE**|**DESCRIPTION**|**TYPE**|**PAGED**|**FORMAT**|**UNITS**|**NVM**|**DEFAULT**<br>**VALUE**|
|READ_VIN|0x88|Measured input supply (SVIN)voltage.|R Word|N|L11|V||NA|
|READ_VOUT|0x8B|Measured output voltage.|R Word|Y|L16|V||NA|
|READ_IIN|0x89|Calculated input supplycurrent.|R Word|N|L11|A||NA|
|MFR_READ_IIN|0xED|Calculated input currentper channel.|R Word|Y|L11|A||NA|
|READ_IOUT|0x8C|Measured output current.|R Word|Y|L11|A||NA|
|READ_TEMPERATURE_1|0x8D|Power stage temperature sensor. This is the value<br>used for all temperature related processing, including<br>IOUT_CAL_GAIN.|R Word|Y|L11|C||NA|
|READ_TEMPERATURE_2|0x8E|Control IC die temperature. Does not affect any other<br>registers.|R Word|N|L11|C||NA|
|READ_DUTY_CYCLE|0x94|Dutycycle of the top gate control signal.|R Word|Y|L11|%||NA|
|READ_POUT|0x96|Calculated outputpower.|R Word|Y|L11|W||NA|
|MFR_VOUT_PEAK|0xDD|Maximum measured value of READ_VOUT since last<br>MFR_CLEAR_PEAKS.|R Word|Y|L16|V||NA|
|MFR_VIN_PEAK|0xDE|Maximum measured value of READ_VIN since last<br>MFR_CLEAR_PEAKS.|R Word|N|L11|V||NA|
|MFR_TEMPERATURE_1_PEAK|0xDF|Maximum measured value of power stage<br>temperature (READ_TEMPERATURE_1) since last<br>MFR_CLEAR_PEAKS.|R Word|Y|L11|C||NA|
|MFR_TEMPERATURE_2_PEAK|0xF4|Maximum measured value of control IC die<br>temperature (READ_TEMPERATURE_2) since last<br>MFR_CLEAR_PEAKS.|R Word|N|L11|C||NA|
|MFR_IOUT_PEAK|0xD7|Report the maximum measured value of READ_IOUT<br>since last MFR_CLEAR_PEAKS.|R Word|Y|L11|A||NA|
|MFR_ADC_CONTROL|0xD8|ADC telemetry parameter selected for repeated fast<br>ADC read back.|R/W<br>Byte|N|Reg|||0x00|
|MFR_ADC_TELEMETRY_<br>STATUS|0xDA|ADC telemetry status indicating which parameter is<br>most recently converted when the short round robin<br>ADC loopis enabled|R/W<br>Byte|N|Reg|||NA|
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LTM4675
## **APPENDIX C: PMBUS COMMAND DETAILS**
## _**READ_VIN**_
The READ_VIN command returns the measured SVIN input voltage, in volts.
This read-only command has two data bytes and is formatted in Linear_5s_11s format.
## _**READ_VOUT**_
The READ_VOUT command returns the measured output voltage in the same format as set by the VOUT_MODE command.
This read-only command has two data bytes and is formatted in Linear_16u format.
## _**READ_IIN**_
The READ_IIN command returns the input current in Amperes. Note: Input current is calculated from READ_IOUT current and the READ_DUTY_CYCLE value from both outputs plus the MFR_IIN_OFFSET. For accurate values at low currents the part must be in continuous conduction mode. The greatest source of error if DCR sensing is used, is the accuracy of the inductor parasitic DC resistance (DCR) at room temperature IOUT_CAL_GAIN.
READ_IIN = MFR_READ_IIN_PAGE0 + MFR_READ_IIN_PAGE1
This read-only command has two data bytes and is formatted in Linear_5s_11s format.
## _**MFR_READ_IIN**_
The MFR_READ_IIN command is a paged reading of the input current that applies the paged MFR_IIN_OFFSET parameter. This calculation is similar to READ_IIN except the paged values are used.
MFR_READ_IIN = MFR_IIN_OFFSET + (IOUT • DUTY_CYCLE)
This command has 2 data bytes and is formatted in Linear_5s_11s format.
## _**READ_IOUT**_
The READ_IOUT command returns the average output current in amperes. The IOUT value is a function of:
a) the differential voltage derived from the power inductor ∆ISNS _n_
b) the IOUT_CAL_GAIN value
- c) the MFR_IOUT_CAL_GAIN_TC value, and
- d) READ_TEMPERATURE_1 value
- e) The MFR_TEMP_1_GAIN and the MFR_TEMP_1_OFFSET
This read-only command has two data bytes and is formatted in Linear_5s_11s format.
## _**READ_TEMPERATURE_1**_
The READ_TEMPERATURE_1 command returns the temperature, in degrees Celsius, of the external sense element. This read-only command has two data bytes and is formatted in Linear_5s_11s format.
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LTM4675
## **APPENDIX C: PMBUS COMMAND DETAILS**
## _**READ_TEMPERATURE_2**_
The READ_TEMPERATURE_2 command returns the temperature, in degrees Celsius, of the internal sense element.
This read-only command has two data bytes and is formatted in Linear_5s_11s format.
## _**READ_DUTY_CYCLE**_
The READ_DUTY_CYCLE command returns the duty cycle of controller, in percent.
This read-only command has two data bytes and is formatted in Linear_5s_11s format.
## _**READ_POUT**_
The READ_POUT command is a paged reading of the DC/DC converter output power in Watts. The POUT is calculated based on the most recent correlated output voltage and current readings.
This command has 2 data bytes and is formatted in Linear_5s_11s format.
## _**MFR_VOUT_PEAK**_
The MFR_VOUT_PEAK command reports the highest voltage, in volts, reported by the READ_VOUT measurement. This command is cleared using the MFR_CLEAR_PEAKS command.
This read-only command has two data bytes and is formatted in Linear_16u format.
## _**MFR_VIN_PEAK**_
The MFR_VIN_PEAK command reports the highest voltage, in volts, reported by the READ_VIN measurement.
This command is cleared using the MFR_CLEAR_PEAKS command.
This read-only command has two data bytes and is formatted in Linear_5s_11s format.
## _**MFR_TEMPERATURE_1_PEAK**_
The MFR_TEMPERATURE_1_PEAK command reports the highest temperature, in degrees Celsius, reported by the READ_TEMPERATURE_1 measurement.
This command is cleared using the MFR_CLEAR_PEAKS command.
This read-only command has two data bytes and is formatted in Linear_5s_11s format.
## _**MFR_TEMPERATURE_2_PEAK**_
The MFR_TEMPERATURE_2_PEAK command reports the highest temperature, in degrees Celsius, reported by the READ_TEMPERATURE_2 measurement.
This command is cleared using the MFR_CLEAR_PEAKS command.
This read-only command has two data bytes and is formatted in Linear_5s_11s format.
Rev. D
118
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LTM4675
## **APPENDIX C: PMBUS COMMAND DETAILS**
## _**MFR_IOUT_PEAK**_
The MFR_IOUT_PEAK command reports the highest current, in amperes, reported by the READ_IOUT measurement. This command is cleared using the MFR_CLEAR_PEAKS command.
This read-only command has two data bytes and is formatted in Linear_5s_11s format.
## _**MFR_ADC_CONTROL**_
The MFR_ADC_CONTROL command determines the ADC read back selection. A default value of 0 in the command runs the standard telemetry loop with all parameters updated in a round robin fashion with a typical latency of 90ms. The user can command a non-zero value to monitored a single parameter with an approximate update rate of 8ms. This command has a latency of up to two ADC conversions or approximately 16ms (power stage temperature conversions may have a latency of up to three ADC conversion or approximately 24ms). Selecting a value of 0x0D will enable a short round robin loop. This commanded value runs a short telemetry loop only selecting VOUT0, IOUT0, VOUT1 and IOUT1 in a round robin manner. The round robin typical latency is 27ms. It is recommended the part remain in standard telemetry mode except for special cases where fast ADC updates of a single parameter is required. The part should be commanded to monitor the desired parameter for a limited period of time (say, less than a second) then set the command back to standard round robin mode. If this command is set to any value except standard round robin telemetry (0) all warnings and faults associated with telemetry other than the selected parameter are effectively disabled and voltage servoing is disabled. When round robin is reasserted, all warnings and faults and servo mode are re-enabled.
|**COMMANDED VALUE**|**TELEMETRY SELECTED**|
|---|---|
|0x00|Standard ADC Round Robin Telemetry|
|0x01|SVIN|
|0x02|Reserved|
|0x03|Reserved|
|0x04|Internal IC Temperature|
|0x05|Channel 0 VOUT|
|0x06|Channel 0 IOUT|
|0x07|Reserved|
|0x08|Channel 0 Power Stage-Sensed Temperature|
|0x09|Channel 1 VOUT|
|0x0A|Channel 1 IOUT|
|0x0B|Reserved|
|0x0C|Channel 1 Power Stage or TSNS1a-Sensed Temperature|
|0x0D|ADC Short Round Robin|
|0x0E-0xFF|Reserved|
If a reserved command value is entered, the part will default to Internal IC Temperature and issue a CML[6] fault. CML[6] faults will continue to be issued by the LTM4675 until a valid command value is entered.
This read/write command has 1 data byte and is formatted in register format.
Rev. D
119
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LTM4675
## **APPENDIX C: PMBUS COMMAND DETAILS**
## _**MFR_ADC_TELEMETRY_STATUS**_
The MFR_ADC_TELEMETRY_STATUS command provides the user the means to determine the most recent ADC conversion when the MFR_ADC_CONTROL short round robin loop is enabled using command 0xD8 value 0x0D. The bit assignments of this command are as follows:
|**BIT**|**TELEMETRY DATA AVAILABLE**|
|---|---|
|7|Reserved returns 0|
|6|Reserved returns 0|
|5|Reserved returns 0|
|4|Reserved returns 0|
|3|Channel 1 IOUTreadback(IOUT1)|
|2|Channel 1 VOUTreadback(VOUT1)|
|1|Channel 0 IOUTreadback(IOUT0)|
|0|Channel 0 VOUTreadback(VOUT0)|
Write to MFR_ADC_TELEMETRY_STATUS with data bits set to 1 clear the respective bits.
This read/write command has 1 data byte and is formatted in register format.
## **NVM (EEPROM) MEMORY COMMANDS**
## **Store/Restore**
|**Store/Restore**|||||||||
|---|---|---|---|---|---|---|---|---|
|**COMMAND NAME**|**CMD**<br>**CODE**|**DESCRIPTION**|**TYPE**|**PAGED**|**FORMAT **|**UNITS**|**NVM**|**DEFAULT**<br>**VALUE**|
|STORE_USER_ALL|0x15|Store user operatingmemoryto EEPROM.|Send Byte|N||||NA|
|RESTORE_USER_ALL|0x16|Restore user operating memory from EEPROM.<br>Identical to MFR_RESET.|Send Byte|N||||NA|
|MFR_COMPARE_USER_ALL|0xF0|Compares current command contents with NVM.|Send Byte|N||||NA|
## _**STORE_USER_ALL**_
The STORE_USER_ALL command instructs the PMBus device to copy the non-volatile user contents of the Operating Memory to the matching locations in the non-volatile User NVM memory (EEPROM).
The 10 year data retention can only be guaranteed when STORE_USER_ALL is executed at 0°C ≤ TJ ≤ 85°C. Executing this command at junction temperatures above 85°C or below 0°C is not recommended because data retention cannot be guaranteed for that condition. If the die temperature exceeds 130°C, the STORE_USER_ALL command is disabled. The command is re-enabled when the IC temperature drops below 125°C.
Communication with the LTM4675 and programming of the EEPROM can be initiated when VDD33 is available and SVIN is not applied. To enable the part in this state, using global address 0x5B write 0x2B followed by 0xC4. The part can now be communicated with, and the project file updated. To write the updated project file to the EEPROM issue a STORE_USER_ALL command. When SVIN is applied, a MFR_RESET or RESTORE_USER_ALL must be issued to allow the PWM to be enabled and valid ADCs to be read.
This write-only command has no data bytes.
Rev. D
120
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LTM4675
## **APPENDIX C: PMBUS COMMAND DETAILS**
## _**RESTORE_USER_ALL**_
The RESTORE_USER_ALL command provides an alternate means by which the user can perform a MFR_RESET of the LTM4675.
This write-only command has no data bytes.
## _**MFR_COMPARE_USER_ALL**_
The MFR_COMPARE_USER_ALL command instructs the PMBus device to compare current command contents with what is stored in non-volatile memory. If the compare operation detects differences, a CML bit 0 fault will be generated.
MFR_COMPARE_USER_ALL commands are disabled if the die exceeds 130°C and are not re-enabled until the die temperature drops below 125°C.
This write-only command has no data bytes.
## _**Fault Log Operation**_
A conceptual diagram of the fault log is shown in Figure 60. The fault log provides telemetry recording capability to the LTM4675. During normal operation the contents of the status registers, the output voltage readings, temperature readings as well as peak values of these quantities are stored in a continuously updated buffer in RAM. The operation is similar to a strip chart recorder. When a fault occurs, the contents are written into EEPROM for nonvolatile storage. The EEPROM fault log is then locked. The part can be powered down with the fault log available for reading at a later time. As a consequence of adding ECC, the area in the EEPROM available for fault log is reduced. When reading the fault log from RAM all 6 events of cyclical data remain. However, when the fault log is read from EEPROM (after a reset), the last 2 events are lost. The read length of 147 bytes remains the same, but the fifth and sixth events are a repeat of the fourth event.
**==> picture [204 x 156] intentionally omitted <==**
**----- Start of picture text -----**<br>
RAM BYTES EEPROM BYTES<br>8<br>ADC READINGS<br>CONTINUOUSLY<br>FILL BUFFER TIME OF FAULT<br>TRANSFER TO<br>EEPROM AND<br>LOCK<br>• •<br>• •<br>• •<br>AFTER FAULT<br>READ FROM<br>EEPROM AND<br>LOCK BUFFER<br>4675 F60<br>**----- End of picture text -----**<br>
**Figure 60. Fault Log Conceptual Diagram**
Rev. D
121
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LTM4675
## **APPENDIX C: PMBUS COMMAND DETAILS**
**Table 30. Fault Logging. This table outlines the format of the block data from a read block data of the MFR_FAULT_LOG command.**
|**Data Format Definitions**||||LIN 11 = PMBus = Rev 1.2,Part 2,section 7.1|
|---|---|---|---|---|
|||||LIN 16 = PMBus Rev 1.2,Part 2,section 8. Mantissaportion only|
|||||BYTE = 8 bits interpretedper definition of this command|
|**DATA**|**BITS**|**DATA**<br>**FORMAT**|**BYTE NUM **|**BLOCK READ COMMAND**|
|Block Length||BYTE|147|The MFR_FAULT_LOG command is a fixed length of 147 bytes<br>The block length will be zero if a data logevent has not been captured|
|**HEADER INFORMATION**|||||
|Fault Log Preface|[7:0]|ASC|0|Returns LTxx beginning at byte 0 if a partial or complete fault log exists.<br>Word xx is a factory identifier that may vary part to part.|
||[7:0]||1||
||[15:8]|Reg|2||
||[7:0]||3||
|Fault Source|[7:0]|Reg|4|Refer to Table 31.|
|MFR_REAL_TIME|[7:0]|Reg|5|48 bit share-clock counter value when fault occurred (200µs resolution).|
||[15:8]||6||
||[23:16]||7||
||[31:24]||8||
||[39:32]||9||
||[47:40]||10||
|MFR_VOUT_PEAK (PAGE 0)|[15:8]|L16|11|Peak READ_VOUT on Channel 0 since last power-on or CLEAR_PEAKS<br>command.|
||[7:0]||12||
|MFR_VOUT_PEAK (PAGE 1)|[15:8]|L16|13|Peak READ_VOUT on Channel 1 since last power-on or CLEAR_PEAKS<br>command.|
||[7:0]||14||
|MFR_IOUT_PEAK (PAGE 0)|[15:8]|L11|15|Peak READ_IOUT on Channel 0 since last power-on or CLEAR_PEAKS<br>command.|
||[7:0]||16||
|MFR_IOUT_PEAK (PAGE 1)|[15:8]|L11|17|Peak READ_IOUT on Channel 1 since last power-on or CLEAR_PEAKS<br>command.|
||[7:0]||18||
|MFR_VIN_PEAK|[15:8]|L11|19|Peak READ_VIN since last power-on or CLEAR_PEAKS command.|
||[7:0]||20||
|READ_TEMPERATURE1 (PAGE 0)|[15:8]|L11|21|Channel 0 power stage during last event.|
||[7:0]||22||
|READ_TEMPERATURE1 (PAGE 1)|[15:8]|L11|23|Channel 1 power stage or TSNS1a-sensed temperature 1 during last<br>event.|
||[7:0]||24||
|READ_TEMPERATURE2|[15:8]|L11|25|Internal temperature sensor during last event.|
||[7:0]||26||
|**CYCLICAL DATA**|||||
|**EVENT n**<br>**(Data at Which Fault Occurred; Most Recent Data)**||||Event “n” represents one complete cycle of ADC reads through the MUX<br>at time of fault. Example: If the fault occurs when the ADC is processing<br>step 15, it will continue to take readings through step 25 and then store<br>the header and all 6 event pages to EEPROM|
Rev. D
122
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LTM4675
## **APPENDIX C: PMBUS COMMAND DETAILS**
**Table 30. Fault Logging. This table outlines the format of the block data from a read block data of the MFR_FAULT_LOG command.**
|READ_VOUT (PAGE 0)|[15:8]|LIN 16|27||
|---|---|---|---|---|
||[7:0]|LIN 16|28||
|READ_VOUT (PAGE 1)|[15:8]|LIN 16|29||
||[7:0]|LIN 16|30||
|READ_IOUT (PAGE 0)|[15:8]|LIN 11|31||
||[7:0]|LIN 11|32||
|READ_IOUT (PAGE 1)|[15:8]|LIN 11|33||
||[7:0]|LIN 11|34||
|READ_VIN|[15:8]|LIN 11|35||
||[7:0]|LIN 11|36||
|READ_IIN|[15:8]|LIN 11|37||
||[7:0]|LIN 11|38||
|STATUS_VOUT(PAGE 0)||BYTE|39||
|STATUS_VOUT(PAGE 1)||BYTE|40||
|STATUS_WORD (PAGE 0)|[15:8]|WORD|41||
||[7:0]|WORD|42||
|STATUS_WORD (PAGE 1)|[15:8]|WORD|43||
||[7:0]|WORD|44||
|STATUS_MFR_SPECIFIC(PAGE 0)||BYTE|45||
|STATUS_MFR_SPECIFIC(PAGE 1)||BYTE|46||
|**EVENT n-1**<br>**(data measured before fault was detected)**|||||
|READ_VOUT (PAGE 0)|[15:8]|LIN 16|47||
||[7:0]|LIN 16|48||
|READ_VOUT (PAGE 1)|[15:8]|LIN 16|49||
||[7:0]|LIN 16|50||
|READ_IOUT (PAGE 0)|[15:8]|LIN 11|51||
||[7:0]|LIN 11|52||
|READ_IOUT (PAGE 1)|[15:8]|LIN 11|53||
||[7:0]|LIN 11|54||
|READ_VIN|[15:8]|LIN 11|55||
||[7:0]|LIN 11|56||
|READ_IIN|[15:8]|LIN 11|57||
||[7:0]|LIN 11|58||
|STATUS_VOUT(PAGE 0)||BYTE|59||
|STATUS_VOUT(PAGE 1)||BYTE|60||
|STATUS_WORD (PAGE 0)|[15:8]|WORD|61||
||[7:0]|WORD|62||
|STATUS_WORD (PAGE 1)|[15:8]|WORD|63||
||[7:0]|WORD|64||
|STATUS_MFR_SPECIFIC(PAGE 0)||BYTE|65||
|STATUS_MFR_SPECIFIC(PAGE 1)||BYTE|66||
Rev. D
123
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LTM4675
## **APPENDIX C: PMBUS COMMAND DETAILS**
**Table 30. Fault Logging. This table outlines the format of the block data from a read block data of the MFR_FAULT_LOG command.**
|*|||||
|---|---|---|---|---|
|*|||||
|*|||||
|**EVENT n-5**<br>**(Oldest Recorded Data)**|||||
|READ_VOUT (PAGE 0)|[15:8]|LIN 16|127||
||[7:0]|LIN 16|128||
|READ_VOUT (PAGE 1)|[15:8]|LIN 16|129||
||[7:0]|LIN 16|130||
|READ_IOUT (PAGE 0)|[15:8]|LIN 11|131||
||[7:0]|LIN 11|132||
|READ_IOUT (PAGE 1)|[15:8]|LIN 11|133||
||[7:0]|LIN 11|134||
|READ_VIN|[15:8]|LIN 11|135||
||[7:0]|LIN 11|136||
|READ_IIN|[15:8]|LIN 11|137||
||[7:0]|LIN 11|138||
|STATUS_VOUT(PAGE 0)||BYTE|139||
|STATUS_VOUT(PAGE 1)||BYTE|140||
|STATUS_WORD (PAGE 0)|[15:8]|WORD|141||
||[7:0]|WORD|142||
|STATUS_WORD (PAGE 1)|[15:8]|WORD|143||
||[7:0]|WORD|144||
|STATUS_MFR_SPECIFIC(PAGE 0)||BYTE|145||
|STATUS_MFR_SPECIFIC(PAGE 1)||BYTE|146||
Rev. D
124
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LTM4675
## **APPENDIX C: PMBUS COMMAND DETAILS**
## **Table 31. Explanation of Position_Fault Values**
|**POSITION_FAULT VALUE**|**SOURCE OF FAULT LOG**|
|---|---|
|0xFF|MFR_FAULT_LOG_STORE|
|0x00|TON_MAX_FAULT Channel 0|
|0x01|VOUT_OV_FAULT Channel 0|
|0x02|VOUT_UV_FAULT Channel 0|
|0x03|IOUT_OC_FAULT Channel 0|
|0x05|OT_FAULT Channel 0|
|0x06|UT_FAULT Channel 0|
|0x07|VIN_OV_FAULT Channel 0|
|0x0A|MFR_OT_FAULT Channel 0|
|0x10|TON_MAX_FAULT Channel 1|
|0x11|VOUT_OV_FAULT Channel 1|
|0x12|VOUT_UV_FAULT Channel 1|
|0x13|IOUT_OC_FAULT Channel 1|
|0x15|OT_FAULT Channel 1|
|0x16|UT_FAULT Channel 1|
|0x17|VIN_OV_FAULT Channel 1|
|0x1A|MFR_OT_FAULT Channel 1|
## **Fault Logging**
|**Fault Logging**|||||||||
|---|---|---|---|---|---|---|---|---|
|**COMMAND NAME**|**CMD**<br>**CODE**|**DESCRIPTION**|**TYPE**|**PAGED**|**DATA**<br>**FORMAT**|**UNITS**|**NVM**|**DEFAULT**<br>**VALUE**|
|MFR_FAULT_LOG|0xEE|Fault log data bytes. This sequentially retrieved data is<br>used to assemble a complete fault log.|R Block|N|CF||Y|NA|
|MFR_FAULT_LOG_ STORE|0xEA|Command a transfer of the fault log from RAM to<br>EEPROM.|Send Byte|N||||NA|
|MFR_FAULT_LOG_CLEAR|0xEC|Initialize the EEPROM block reserved for fault logging.|Send Byte|N||||NA|
## _**MFR_FAULT_LOG**_
The MFR_FAULT_LOG command allows the user to read the contents of the FAULT_LOG after the first fault occurrence since the last MFR_FAULT_LOG_CLEAR command was last written. The contents of this command are stored in non-volatile memory, and are cleared by the MFR_FAULT_LOG_CLEAR command. The length and content of this command are listed in Table 30. If the user accesses the MFR_FAULT_LOG command and no fault log is present, the command will return a data length of 0. If a fault log is present, the MFR_FAULT_LOG will always return a block of data 147 bytes long. If a fault occurs within the first second of applying power, some of the earlier pages in the fault log may not contain valid data.
NOTE: The approximate transfer time for this command is 3.4ms using a 400kHz clock.
This read-only command is in block format.
Rev. D
125
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LTM4675
## **APPENDIX C: PMBUS COMMAND DETAILS**
## _**MFR_FAULT_LOG_STORE**_
The MFR_FAULT_LOG_STORE command forces the fault log operation to be written to EEPROM just as if a fault event occurred. This command will generate a MFR_SPECIFIC fault if the “Enable Fault Logging” bit is set in the MFR_ CONFIG_ALL command.
If the die temperature exceeds 130°C, the MFR_FAULT_LOG_STORE command is disabled until the IC temperature drops below 125°C.
Up-Time Counter is in the Fault Log header. The counter is the time since the last module reset (MFR_RESET, RESTORE_USER_ALL, or SVIN - power cycle) in 200µs increments. This is a 48-bit binary counter.
This write-only command has no data bytes.
## _**MFR_FAULT_LOG_CLEAR**_
The MFR_FAULT_LOG_CLEAR command will erase the fault log file stored values. It will also clear bit 3 in the STATUS_MFR_SPECIFIC command. After a clear is issued, the status can take up to 8ms to clear.
This write-only command is send bytes.
## **Block Memory Write/Read**
|**COMMAND NAME**|**CMD CODE **|**DESCRIPTION**|**TYPE**|**PAGED**|**DATA**<br>**FORMAT**|**UNITS**|**NVM**|**DEFAULT**<br>**VALUE**|
|---|---|---|---|---|---|---|---|---|
|MFR_EE_UNLOCK|0xBD|Unlock user EEPROM for access by MFR_EE_ERASE and<br>MFR_EE_DATA commands.|R/W Byte|N|Reg|||NA|
|MFR_EE_ERASE|0xBE|Initialize user EEPROM for bulk programming by MFR_EE_<br>DATA.|R/W Byte|N|Reg|||NA|
|MFR_EE_DATA|0xBF|Data transferred to and from EEPROM using sequential<br>PMBus word reads or writes. Supports bulkprogramming.|R/W<br>Word|N|Reg|||NA|
All the (EEPROM) commands are disabled if the die temperature exceeds 130°C. (EEPROM) commands are re-enabled when the die temperature drops below 125°C.
## _**MFR_EE_xxxx**_
MFR_EE_XXXX commands are used to facilitate bulk programming of the internal EEPROM. Contact the factory for more details.
Rev. D
126
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LTM4675
## **PACKAGE DESCRIPTION**
## **PACKAGE ROW AND COLUMN LABELING MAY VARY AMONG µModule PRODUCTS. REVIEW EACH PACKAGE LAYOUT CAREFULLY.**
**Table 32. LTM4675 BGA Pinout**
|**PIN ID**|**FUNCTION**|**PIN ID**|**FUNCTION**|**PIN ID**|**FUNCTION**|**PIN ID**|**FUNCTION**|**PIN ID**|**FUNCTION**|**PIN ID**|**FUNCTION**|
|---|---|---|---|---|---|---|---|---|---|---|---|
|A1|VOUT0|B1|VOUT0|C1|VOUT0|D1|VOUT0|E1|GND|F1|GND|
|A2|GND|B2|GND|C2|GND|D2|GND|E2|GPIO0|F2|GPIO1|
|A3|GND|B3|GND|C3|TSNS0|D3|TSNS0|E3|ALERT|F3|RUN0|
|A4|GND|B4|GND|C4|GND|D4|SDA|E4|SCL|F4|RUN1|
|A5|GND|B5|GND|C5|GND|D5|GND|E5|SYNC|F5|SGND|
|A6|GND|B6|GND|C6|GND|D6|COMP0b|E6|COMP0a|F6|SGND|
|A7|GND|B7|GND|C7|GND|D7|VOSNS0+|E7|VOSNS0-|F7|INTVCC|
|A8|GND|B8|SW0|C8|GND|D8|VORB0+|E8|VORB0-|F8|GND|
|A9|VIN0|B9|VIN0|C9|VIN0|D9|VIN0|E9|GND|F9|SVIN|
|||||||||||||
|**PIN ID**|**FUNCTION**|**PIN ID**|**FUNCTION**|**PIN ID**|**FUNCTION**|**PIN ID**|**FUNCTION**|**PIN ID**|**FUNCTION**|**PIN ID**|**FUNCTION**|
|G1|GND|H1|GND|J1|VOUT1|K1|VOUT1|L1|VOUT1|M1|VOUT1|
|G2|ASEL|H2|FSWPHCFG|J2|GND|K2|GND|L2|GND|M2|GND|
|G3|VOUT0CFG|H3|VTRIM0CFG|J3|TSNS1a|K3|TSNS1b|L3|GND|M3|GND|
|G4|VOUT1CFG|H4|VTRIM1CFG|J4|VDD25|K4|WP|L4|GND|M4|GND|
|G5|SGND|H5|SHARE_CLK|J5|VDD33|K5|GND|L5|GND|M5|GND|
|G6|SGND|H6|COMP1a|J6|COMP1b|K6|GND|L6|GND|M6|GND|
|G7|INTVCC|H7|VOSNS1|J7|VORB1|K7|GND|L7|GND|M7|GND|
|G8|GND|H8|GND|J8|GND|K8|GND|L8|SW1|M8|GND|
|G9|GND|H9|GND|J9|VIN1|K9|VIN1|L9|VIN1|M9|VIN1|
Rev. D
127
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LTM4675
## **PACKAGE DESCRIPTION**
**==> picture [273 x 376] intentionally omitted <==**
**----- Start of picture text -----**<br>
TOP VIEW<br>1 2 3 4 5 6 7 8 9<br>A<br>VOUT0 GND GND SW0 VIN0<br>B<br>TSNS0 GND GND<br>C<br>VOUT0 TSNS0 SDA GND COMP0b VOSNS0 [+] VORB0 [+] VIN0<br>D<br>GPIO0 ALERT SCL SYNC COMP0a VOSNS0 [–] VORB0 [–]<br>E<br>GPIO1 RUN0 RUN1 SVIN<br>F<br>GND ASEL VOUT0CFG VOUT1CFG SGND INTVCC<br>G<br>FSWPHCFG VTRIM0CFG VTRIM1CFG SHARE_CLK COMP1a VOSNS1 GND<br>H<br>TSNS1a VDD25 VDD33 COMP1b VORB1<br>J<br>VOUT1 TSNS1b WP VIN1<br>K<br>GND GND SW1<br>L<br>VOUT1 GND GND VIN1<br>M<br>**----- End of picture text -----**<br>
Rev. D
128
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LTM4675
## **PACKAGE PHOTOGRAPH**
Rev. D
129
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LTM4675
## **PACKAGE DESCRIPTION**
**==> picture [506 x 597] intentionally omitted <==**
**----- Start of picture text -----**<br>
6<br>3<br>SEE NOTES<br>PIN 1 SEE NOTES BGA 108 0517 REV B<br>A B C D E F G H J K L M<br>1<br>2<br>DETAIL A<br>3<br>e<br>4<br>5 G<br>6<br>7 b PACKAGE BOTTOM VIEW LTMXXXXXX µModule<br>8<br>PACKAGE IN TRAY LOADING ORIENTATION<br>9 PACKAGE ROW AND COLUMN LABELING MAY VARY AMONG µModule PRODUCTS. REVIEW EACH PACKAGE LAYOUT CAREFULLY<br>!<br>b e DETAILS OF PIN #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE PIN #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE<br>F NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994 2. ALL DIMENSIONS ARE IN MILLIMETERS 3 BALL DESIGNATION PER JESD MS-028 AND JEP95 4 5. PRIMARY DATUM -Z- IS SEATING PLANE 6 COMPONENT PIN “A1” TRAY PIN 1 BEVEL<br> 3.51mm) A<br>× A2 NOTES BALL HT BALL DIMENSION PAD DIMENSION SUBSTRATE THK MOLD CAP HT<br>DETAIL B<br>PACKAGE SIDE VIEW<br>MAX 3.71 0.70 3.01 0.90 0.66 0.46 2.55 0.15 0.10 0.20 0.30 0.15<br> 11.9mm<br>× Y<br>X<br>H1 Z Z DIMENSIONS NOM 3.51 0.60 2.91 0.75 0.63 16.00 11.90 1.27 13.97 10.16 0.41 2.50<br>BGA Package A1 SUBSTRATE M M<br>ddd eee<br>b1 MIN 3.31 0.50 2.81 0.60 0.60 0.36 2.45 TOTAL NUMBER OF BALLS: 108<br>H2 DETAIL A<br>ccc Z MOLD CAP DETAIL B<br>(Reference LTC DWG # 05-08-1931 Rev B)<br>108-Lead (16mm Øb (108 PLACES) A A1 A2 b b1 D E e F G H1 H2 aaa bbb ccc ddd eee<br>SYMBOL<br>aaa Z<br>0.0000<br>D X Y 6.9850 5.7150 4.4450 3.1750 1.9050 0.6350 0.6350 1.9050 3.1750 4.4450 5.7150 6.9850<br>E<br>TOP VIEW<br>PACKAGE TOP VIEW<br>SUGGESTED PCB LAYOUT<br>4<br>PIN “A1” CORNER<br>0.630 ±0.025 Ø 108x<br>Z<br>Z<br>Z// bbb<br>5.080<br>3.810<br>2.540<br>1.270<br>0.000<br>1.270<br>2.540<br>3.810<br>5.080<br>aaa Z<br>**----- End of picture text -----**<br>
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For more information www.analog.com
LTM4675
## **REVISION HISTORY**
|**REV**|**DATE**|**DESCRIPTION**|**PAGE NUMBER**|
|---|---|---|---|
|A|10/16|Added LTM4677 to Features.<br>Added explicit guidance in Pin Descriptions on RCONFIGs for parallel-VOUTapplications.<br>Removed erroneous mention of ISENSEPins.<br>Called out ASEL Pin.<br>Table 4: Switching Frequency: from External to Sync Slave.<br>Table 5: Included term "MFR_ADDRESS" In table title.<br>Table 8: Frequency Command from 0x0000 to N/A.<br>Table 18: Corrected typo in heat sink manufacturer part number.<br>Corrected typo in MFR_SPECIAL_ID prefix, 0x47A.|1<br>15<br>30 and 117<br>33<br>46<br>47<br>51<br>65<br>109|
|B|06/17|Added "with ECC”.<br>Faster turn-on time from 70ms to 40ms tSTART.<br>Changed update rate from 100ms to 90ms.|1<br>1, 4<br>7, 8|
|C|03/20|Added Application Information<br>Changed RVSENSO+to RVOSNSO+<br>Changed VVSENSO+to VVOSNSO+<br>Changed VVSENSO–to VVOSNSO–<br>Changed VVSENS1to VVOSNS1<br>Changed MFR_PWM_MODEn[1:0]=10b to MFR_PWM_MODEn[0]=1b<br>Corrected User-Editable bits [7:4] to [6:4]<br>Changed RCFGto RASEL<br>Changed MFR_RETRY_DELAY 10µs increments to 1mS|2<br>5<br>6<br>7<br>22<br>47<br>99|
|D|07/21|Updated text.<br>Updated Table 5. ASEL Pin Strapping Look-up table with Correct Slave Address.|14, 33, 84<br>47|
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Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implicatioFor more informatio **n** or otherwise under any patent or patent rights of Analog Devices.www.analog.com
## LTM4675
## **TYPICAL APPLICATION**
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5.75V TO 17VVIN =z + C220µFINL =z C22µF×3INH aiH VVSVIN0IN1IN TSNSVOUT00 C100µF×4OUT0 ADJUSTABLEUP TO 9AVOUT0, 1.0V<br>VDD33<br>10k<br>×9<br>ON/OFF CONTROL, FAULTSMBus INTERFACE WITHMANAGEMENT, POWERPMBus COMMAND SETPWM CLOCK SYNCH.TIME BASE SYNCH.SEQUENCING EEREEEEcopittyH+itLo_ Eee Eee SCLSDAALERTRUNRUNGPIOGPIOSYNCSHARE_CLK0101 LTM4675 VVTSNSTSNSVVOSNS0OSNS0VVORB0ORB0ORB1OUT11b1a [+][–][+][–] o a _ C100µF×4OUT1 o LOAD = ADJUSTABLEUP TO 9AV0OUT1, 1.8V<br>WP<br>VOSNS1 LOAD1<br>• SLAVE ADDRESS = 1001111_R/W (0X4F) SGND<br>• SWITCHING FREQUENCY: 500kHz 4676A F61<br>• NO GUI CONFIGURATION AND LJ LJ<br> NO PART SPECIFIC PROGRAMMING REQUIRED<br> IN MULTI-MODULE SYSTEMS, CONFIGURING 6.34k<br> RAIL_ADDRESS IS RECOMMENDED 1%<br>±50ppm/°C<br>Figure 61. 9A, 1V and 9A, 1.8V Output DC/DC µModule Regulator with Serial Interface<br>|<br>DESIGN RESOURCES<br>SUBJECT DESCRIPTION<br>µModule Design and Manufacturing Resources Design: Manufacturing:<br>• Selector Guides • Quick Start Guide<br>• Demo Boards and Gerber Files • PCB Design, Assembly and Manufacturing Guidelines<br>• Free Simulation Tools • Package and Board Level Reliability<br>µModule Regulator Products Search 1. Sort table of products by parameters and download the result as a spread sheet.<br>2. Search using the Quick Power Search parametric table.<br>INPUT | Vin(Min) Vv Vin(Max) Vv<br>OUTPUT | Vout Vv lout A<br>FEATURES | Low EMI Ultrathin Internal Heat Sink<br>Digital Power System Management Analog Devices’ family of digital power supply management ICs are highly integrated solutions that<br>offer essential functions, including power supply monitoring, supervision, margining and sequencing,<br>and feature EEPROM for storing user configurations and fault logging.<br>CC DD25 SW0 SW1<br>INTV V<br>COMP0a COMP0b COMP1a COMP1b ASEL FSWPHCFG VOUT0CFG VTRIM0CFG VOUT1CFG VTRIM1CFG GND<br>**----- End of picture text -----**<br>
## **DESIGN RESOURCES**
## **RELATED PARTS**
|**RELATED PARTS**|**RELATED PARTS**||
|---|---|---|
|**PART NUMBER**|**DESCRIPTION**|**COMMENTS**|
|LTM4650|Dual 25A or Single 50A Step-DownµModule Regulator|4.5V ≤ VIN≤ 15V,0.6V ≤ VOUT≤ 1.8V,16mm×16mm×5.01mm BGA|
|LTM4677|Dual 18A or Single 36A Step-Down µModule Regulator<br>with Digital Power System Management|4.5V ≤ VIN≤ 16V, 0.6V ≤ VOUT≤ 1.8V, 16mm×16mm×5.01mm BGA|
|LTM4676A|Dual 13A or Single 26A Step-Down µModule Regulator<br>with Digital Power System Management|4.5V ≤ VIN≤ 17V, 0.5V ≤ VOUT≤ 5.5V, 16mm×16mm × 5.01mm BGA|
|LTC3887/LTC3883|Dual and Single Output DC/DC Controllers with Power<br>System Management|0.5% TUE 16-Bit ADC, Voltage/Current/Temperature Monitoring and<br>Supervision|
|LTC2977/LTC2974|8- and 4-Channel PMBus Power System Managers|0.25% TUE 16-Bit ADC,Voltage/Temperature Monitoringand Supervision|
Licensed under U.S. Patent 7000125 and other related patents worldwide. TUE is total unadjusted error.
Rev. D
07/21 www.analog.com
132
ANALOG DEVICES, INC. 2015-2021
For more information www.analog.com
Updated at April 10, 2026
Since its inception in 1965, Analog Devices has established itself as a global leader in the design and manufacturing of high-performance analog, mixed-signal, and digital signal processing (DSP) integrated circuits. The company is renowned for solving complex engineering challenges by providing critical technologies that seamlessly convert real-world phenomena into precise electrical signals for the industrial, automotive, communications, and consumer markets. Within its extensive portfolio, Analog Devices provides highly reliable clock, timing, and frequency management solutions, featuring a comprehensive array of precision timers, oscillators, and pulse generators. Complementing this core lineup is a robust offering of driver and interface ICs, particularly high-performance I/O expanders that enable seamless connectivity and streamline complex electronic system architectures. Beyond these foundational integrated circuits, Analog Devices leads the industry in sensor innovation, delivering advanced MEMS accelerometers and integrated MEMS modules designed for exceptional precision in motion sensing. To support complete hardware designs, the company's specialized offerings also encompass discrete bipolar transistors, sub-2.4GHz RF transceivers, temperature-compensated oscillators, and dedicated power management components such as DC/DC converters and LED driver ICs.
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