LTM4658EY#PBF

LTM4658 

## Low V IN, High Efficiency 10A Step-Down DC/DC µModule Regulator 

## **FEATURES** 

- n **Tiny Surface Mount, 4mm × 4mm × 4.32mm LGA and 4mm × 4mm × 4.62mm BGA Packages** 

- n **Silent Switcher[®] 2 Architecture** 

- n **Ultralow EMI Noise** 

- n Input Voltage Range: 2.25V to 5.5V 

- n Output Voltage Range: 0.5V to VIN 

- n 10A DC Output Current 

- n Current Mode Control, Fast Transient Response 

- n Multiphase Parallel Current Sharing with Multiple LTM4658s 

- n Output Soft-Start with Voltage Tracking 

- n External Frequency Synchronization 

- n Selectable Pulse-Skipping Mode 

- n Power Good Indicator 

- n Die Temperature Monitoring Output 

- n Overvoltage, Overcurrent and Overtemperature Protection 

## **APPLICATIONS** 

- n Telecom, Datacom, Networking System 

- n Optical Module 

- n Industrial Equipment 

- n Point-of-Load Regulation 

## **DESCRIPTION** 

The LTM[®] 4658 is a complete 10A step-down switching mode μModule[®] regulator in a tiny 4mm × 4mm × 4.32mm LGA and 4mm × 4mm × 4.62mm BGA packages. Included in the package are the switching controller, power MOSFETs, inductor and all support components. Operating over an input voltage range of 2.25V to 5.5V, the LTM4658 supports an output voltage range of 0.5V to VIN set by external resistors. Its high efficiency design delivers 10A continuous output current. Only ceramic input and output capacitors are needed. 

The LTM4658 employs a Silent Switcher 2 architecture with internal hot loop bypass capacitors to achieve both low EMI and high efficiency at high switching frequencies. 

The LTM4658 also supports frequency synchronization, multiphase operation, selectable pulse-skipping mode operation, output voltage tracking for supply rail sequencing. Its high switching frequency and a current mode architecture enables a very fast transient response to line and load changes without sacrificing stability. 

Fault protection features include overvoltage, overcurrent and overtemperature protection. The LTM4658 is Pb-Free and RoHS compliant. 

All registered trademarks and trademarks are the property of their respective owners. 

## **TYPICAL APPLICATION** 

**Single 10A, 1V Output DC/DC μModule Regulator** 

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MODE/SYNC PGOOD<br>VIN VOUT<br>2.5V TO 5.5V VIN VOUT 100µF 1V10A<br>22µF RUN 6.3V<br>6.3V FREQ LTM4658 GND 60.4k<br>COMP<br>SSTT FB<br>AGND<br>60.4k<br>0.1µF 4658 TA01a<br>**----- End of picture text -----**<br>


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Efficiency vs Load Current<br>100 3.0<br>90<br>EFFICIENCY 2.5<br>80<br>70<br>2.0<br>60<br>50 1.5<br>40<br>1.0<br>30<br>20<br>POWER LOSS VIN = 3.3V 0.5<br>10 VOUT = 1V<br>FREQ = 2MHz<br>0 0<br>0 1 2 3 4 5 6 7 8 9 10<br>LOAD CURRENT (A)<br>4658 TA01b<br>EFFICIENCY (%)<br>POWER LOSS (W)<br>**----- End of picture text -----**<br>


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Rev. B<br>**----- End of picture text -----**<br>


1 

For more information www.analog.com 

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## LTM4658 

## **ABSOLUTE MAXIMUM RATINGS** 

## **(Note 1)** 

VIN ............................................................... –0.3V to 6V Operating Junction Temperature VOUT ............................................................ –0.3V to VIN (Note 2) .................................................. –40°C to 125°C PGOOD ......................................................... –0.3V to 6V Storage Temperature Range .................. –55°C to 125°C RUN, SSTT, MODE/SYNC, Peak Solder Reflow Body Temperature .................250°C FB, COMP, FREQ ......................................... –0.3V to VIN Note that the peak reflow temperature must not exceed 250°C, including reworking process. 

## **PIN CONFIGURATION (See Pin Functions and Table 9)** 

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TOP VIEW TOP VIEW<br>RUN VOUT RUN VOUT<br>5 5<br>FB AGND FB AGND<br>COMP SSTT COMP SSTT<br>4 FREQ 4 FREQ<br>VIN MODE/SYNC VIN MODE/SYNC<br>3 PGOOD 3 PGOOD<br>2 GND 2 GND<br>SW SW<br>1 1<br>A B C D E A B C D E<br>LGA PACKAGE BGA PACKAGE<br>25-PIN (4mm × 4mm × 4.32mm) 25-PIN (4mm × 4mm × 4.62mm)<br>TJMAX = 125°C, θJA = 25.8°C/W,  TJMAX = 125°C, θJA = 25.8°C/W,<br>θJCtop = 60.7°C/W, θJCbot = 6.8°C/W θJCtop = 60.7°C/W, θJCbot = 6.8°C/W<br>WEIGHT = 0.22g WEIGHT = 0.22g<br>**----- End of picture text -----**<br>


## **ORDER INFORMATION** 

|**PART NUMBER**|**PAD OR BALL FINISH**|**PART MARKING***|**PART MARKING***|**PACKAGE**<br>**TYPE**|**MSL**<br>**RATING**|**TEMPERATURE RANGE**<br>**(SEE NOTE 2)**|
|---|---|---|---|---|---|---|
|||**DEVICE**|**FINISH CODE**||||
|LTM4658EV#PBF|Au(RoHS)|4658<br>4LTV|4|LGA|4|–40°C to 125°C|
|LTM4658IV#PBF|Au(RoHS)|||LGA|4|–40°C to 125°C|
|LTM4658EY#PBF|SAC305(RoHS)|4658<br>1LTY|1|BGA|4|–40°C to 125°C|
|LTM4658IY#PBF|SAC305(RoHS)|||BGA|4|–40°C to 125°C|



- Contact the factory for parts specified with wider operating temperature ranges. *Pad or ball finish code is per IPC/JEDEC J-STD-609. 

- Recommended LGA and BGA PCB Assembly and Manufacturing Procedures 

- LGA and BGA Package and Tray Drawings 

Rev. B 

2 

For more information www.analog.com 

LTM4658 

**ELECTRICAL CHARACTERISTICS The** l **denotes the specifications which apply over the specified operating temperature range, otherwise specifications are at TA = 25°C, (Note 2). VIN = 3.3V per the typical application.** 

|**SYMBOL**|**PARAMETER**|**CONDITIONS**|**CONDITIONS**|**MIN**<br>**TYP**<br>**MAX**|**UNITS**|
|---|---|---|---|---|---|
|VIN|Input DC Voltage||l|2.25<br>5.5|V|
|VOUT(RANGE)|Output Voltage Range|MODE/SYNC = 1MHz, FREQ = VIN|l|0.5<br>VIN|V|
|VOUT(DC)|Output Voltage|MODE/SYNC = 1MHz, FREQ = VIN, VOUT= 0.5V|l|0.4925<br>0.5<br>0.5075|V|
|VIN_UVLO|VINUndervoltage Lockout|VINRising||2.0<br>2.1<br>2.2|V|
|VIN_UVLO_HYS|VINUndervoltage Lockout Hysteresis|||150|mV|
|VRUN|RUN Pin On Threshold|VRUNRising||0.375<br>0.4<br>0.425|V|
|VRUN_HYS|RUN Pin Hysteresis|||60|mV|
|IRUN|RUN Pin Leakage Current|RUN = 0.4V||±200|nA|
|IQ(VIN)|Input Supply Bias Current<br>Pulse-Skipping Mode<br>Forced Continuous Mode<br>Shutdown|MODE/SYNC = FREQ = VIN, VOUT= 1.5V<br>MODE/SYNC = 0V, FREQ = VIN, VOUT= 1.5V<br>RUN = 0V||1.6<br>70<br>1|mA<br>mA<br>μA|
|IS(VIN)|Input Supply Current|VOUT= 1.5V, IOUT= 10A||5.5|A|
|IOUT(DC)|Output Continuous Current Range|VOUT= 1.5V(Note 4)||10|A|
|∆VOUT(Line)/VOUT|Line Regulation Accuracy|FREQ = VIN, VOUT= 1.5V, VIN= 2.25V to 5.5V,<br>IOUT= 0A|l|0.001<br>0.30|%/V|
|∆VOUT(Load)/VOUT|Load Regulation Accuracy|VIN= FREQ = 3.3V, MODE/SYNC = 1.0MHz,<br>VOUT= 0.5V<br>IOUT= 0A to 8A<br>IOUT= 0A to 10A(Notes 3 and 4)|l|0.2<br>1.5<br>1.5|%<br>%|
|VOUT(AC)|Output Ripple Voltage|IOUT= 0A, COUT= 100μF + 22μF ×2 Ceramic,<br>(Notes 4)||100|mV|
|∆VOUT(START)|Turn-On Overshoot|IOUT= 0A, COUT= 100μF + 22μF ×2 Ceramic,<br>(Notes 4)||5|mV|
|tSTART|Turn-On Time|COUT= 100μF + 22μF ×2 Ceramic, No Load,<br>SSTT = 0.1μF(Note 4)||5|ms|
|ISSTT|Track Pin Soft-Start Pull-Up Current|SSTT = 0.5V||7<br>10<br>13|μA|
|∆VOUTLS|Peak Deviation for Dynamic Load|Load: 0% to 50% to 0% of Full Load<br>COUT= 100μF + 2× 22μF Ceramic<br>(Note 4)||157|mV|
|tSETTLE|Settling Time for Dynamic Load Step|Load: 0% to 50% to 0% of Full Load,<br>COUT= 100μF + 2× 22μF Ceramic,<br>(Note 4)||15|μs|
|IOUTPK|Output Current Limit|VIN= 3.3V, VOUT= 0.5V||16|A|
|VFB|Voltage at VFBPin|IOUT= 0A, VOUT= 1.5V|l|0.495<br>0.50<br>0.505|V|
|IFB|Current at VFBPin|||±20|nA|
|VPGOOD|PGOOD Trip Level<br>Undervoltage Falling Threshold<br>Overvoltage Rising Threshold|As a Percentage of Regulated VOUT<br>VFBRamping Negative<br>VFBRamping Positive||–4<br>7<br>–3<br>10<br>–2<br>13|%<br>%|



Rev. B 

3 

For more information www.analog.com 

## LTM4658 

**ELECTRICAL CHARACTERISTICS The** l **denotes the specifications which apply over the specified operating temperature range, otherwise specifications are at TA = 25°C, (Note 2). VIN = 3.3V per the typical application.** 

|**SYMBOL**|**PARAMETER**|**CONDITIONS**|**CONDITIONS**|**MIN**<br>**TYP**<br>**MAX**|**UNITS**|
|---|---|---|---|---|---|
|IPGOOD|PGOOD Leakage|VPGOOD= 5.5V||50|nA|
|fOSC|Oscillator Frequency|||2|MHz|
|SYNC_RANGE|Sync Frequency Range|FREQ = VIN||1.0<br>2.6|MHz|
|SYNC_LEVEL|Clock Level High on SYNC<br>Clock Level Low on SYNC|||1.2<br>0.4|V<br>V|



**Note 1:** Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. 

**Note 2:** The LTM4658 is tested under pulsed load conditions such that TJ ≈ TA. The LTM4658E is guaranteed to meet performance specifications over the 0°C to 125°C internal operating temperature range. Specifications over the full –40°C to 125°C internal operating temperature range are assured by design, characterization and correlation 

with statistical process controls. The LTM4658I is guaranteed to meet specifications over the full –40°C to 125°C internal operating temperature range. Note that the maximum ambient temperature consistent with these specifications is determined by specific operating conditions in conjunction with board layout, the rated package thermal resistance and other environmental factors. 

**Note 3:** See output current derating curves for different VIN, VOUT and TA. **Note 4:** Guaranteed by design. 

Rev. B 

4 

For more information www.analog.com 

LTM4658 

## **TYPICAL PERFORMANCE CHARACTERISTICS** 

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Efficiency vs Load Current at 2.5VIN Efficiency vs Load Current at 3.3VIN Efficiency vs Load Current at 5VIN<br>10095 P| | | ttt ty yl 10095 | | deed | | | | ft | 10095 P| tt |i ft yf<br>90 90 90<br>P esbe itl | || | fLecbececkee be Pott] || ac ESTE<br>85 85 85<br>|W Aa Baie Ef oS Sct | Peete<br>80 We | || ERR E4 80 BY ESS 80 iee<br>75 ie 75 eo 75 PrW7| | | | tt td<br>70 qi | | i tt tf | 70 Wi | | EEE EL 70 HAGE<br>VOUT = 0.5V (1MHz)<br>65 qi | ol VOUT = 0.5V (1MHz) 65 HW) | VOUT = 0.5V (1MHz) 65 ef VOUT = 0.8V (2MHz)<br>60 ime VVOUTOUT  = 0.8V (2MHz)= 1V    (2MHz) 60 VVOUTOUT  = 0.8V (2MHz)= 1V    (2MHz) 60 | VVOUT OUT = 1.5V (2MHz)= 1V    (2MHz)<br>55 ia VOUT = 1.5V (2MHz) 55 Ht | ft VOUT = 1.5V (2MHz) 55 a | VOUT = 2.5V (2MHz)<br>50 Ri | VOUT = 1.8V (2MHz) 50 i( i ia VOUT = 1.8V (2MHz) 50 i if n VOUT = 3.3V (2MHz)<br>0 1 2 3 4 5 6 7 8 9 10 0 1 2 3 4 5 6 7 8 9 10 0 1 2 3 4 5 6 7 8 9 10<br>LOAD CURRENT (A) LOAD CURRENT (A) LOAD CURRENT (A)<br>4658 G01 4658 G02 4658 G03<br>Efficiency vs Load Current at  1.0V Output Transient Response,  1.5V Output Transient Response,<br>Different Mode of Operation VIN = 3.3V VIN = 3.3V<br>100<br>VIN = 3.3V PULSE-SKIP<br>9080 VVVINININ = 3.3V FCM = 5V PULSE-SKIP  = 5V FCM 200mV/DIVVOUT 200mV/DIVVOUT<br>70 hf<br>ILOAD ILOAD<br>60 P | OIfi 5A/DIV 5A/DIV<br>50<br>pete |<br>40 Pf<br>30 Pf ff VIN = 3.3V  20μs/DIV 4658 G05 VIN = 3.3V  20μs/DIV 4658 G06<br>20 Le pf IOUT = 2.5A TO 7.5A  IOUT = 2.5A TO 7.5A<br>10 nV ff)AT OUTPUT  CAPACITOR = 100μF + 22μF ×2   OUTPUT  CAPACITOR = 100μF + 22μF ×2<br>0 Pies<br>0.001 0.010 0.100 1.000 10.000<br>LOAD CURRENT (A)<br>4658 G04<br>1.0V Output Transient Response,  1.5V Output Transient Response,<br>VIN = 5V VIN = 5V Start-Up with No Load<br>200mV/DIVVOUT 200mV/DIVVOUT VOUT<br>ILOAD ILOAD RUN<br>5A/DIV 5A/DIV<br>IIN<br>1A/DIV<br>4658 G07 4658 G08 4658 G09<br>20μs/DIV 20μs/DIV 10ms/DIV<br>VIN = 5V  VIN = 5V  VIN = 3.3V<br>IOUT = 2.5A TO 7.5A  IOUT = 2.5A TO 7.5A  VOUT = 1.5V<br>OUTPUT  CAPACITOR = 100μF + 22μF ×2   OUTPUT  CAPACITOR = 100μF + 22μF ×2    NO LOAD<br>EFFICIENCY (%) EFFICIENCY (%) EFFICIENCY (%)<br>EFFICIENCY (%)<br>**----- End of picture text -----**<br>


Rev. B 

5 

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LTM4658 

## **TYPICAL PERFORMANCE CHARACTERISTICS** 

## **Start-Up with 10A Load** 

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VOUT<br>RUN<br>IIN<br>5A/DIV<br>4658 G10<br>10ms/DIV<br>VIN = 3.3V<br>VOUT = 1.5V<br>RLOAD= 0.15Ω<br>Short-Circuit with 10A Load<br>VOUT<br>1V/DIV<br>IIN<br>2A/DIV<br>fe<br>4658 G12<br>200μs/DIV<br>**----- End of picture text -----**<br>


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Short-Circuit with No Load<br>**----- End of picture text -----**<br>


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VOUT<br>1V/DIV<br>IIN<br>2A/DIV<br>se 4658 G11<br>100μs/DIV<br>**----- End of picture text -----**<br>


**Start-Up with Prebiased Output** 

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RUN: 2V/DIV<br>VOUT: 500mV/DIV<br>PREBIASED TO 1V<br>PGOOD: 2V/DIV<br>IIN: 1A/DIV<br>**----- End of picture text -----**<br>


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4658 G13<br>2ms/DIV<br>**----- End of picture text -----**<br>


Rev. B 

6 

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LTM4658 

## **PIN FUNCTIONS** 

**GND (Pins A1, A2, B2, C2, D2, E1, E2):** Power Ground Pins for Both Input and Output Returns. 

**VIN (Pins A3, B3, C3):** The VIN pins supply current to the internal circuitry and topside power switch. All of the VIN pins must be connected together with short, wide traces and bypassed to PGND with low ESR capacitors located as close as possible to the pins. 

**COMP (Pin A4):** Current Control Threshold and Error Amplifier Compensation Point of the Switching Mode Regulator Channel. The current comparator’s trip threshold is linearly proportional to this voltage. Tie the COMP pins together for parallel operation. The device is internal compensated. 

**RUN (Pin A5):** Run Control Input of Each Switching Mode Regulator Channel. Enables chip operation by tying RUN above 0.4V. Tying it to GND shuts down the part. 

**SW (Pins B1, C1, D1):** Switching Node Internal High Current Path from MOSFET to Inductor. Connect with solid cooper area or leave it floating. 

**FB (Pin B4):** The negative input of the error amplifier for the switching mode regulator. The LTM4658 regulates the voltage between FB and AGND to 500mV. A resistor divider connecting to VOUT sets the output voltage. In PolyPhase[®] operation, tying the FB pins of the subordinate channels to VIN to disable the internal error amplifier. See the Applications Information of Switching Regulator section for details. 

**VOUT (Pins B5, C5, D5, E5):** Power Output Pins of Each Switching Mode Regulator. Apply output load between these pins and GND pins. Recommend placing output decoupling capacitance directly between these pins and GND pins. 

**AGND (Pin C4):** The AGND pin is the ground reference for the internal analog circuitry, including the bandgap voltage reference. To achieve good load regulation, connect 

the AGND pin to the negative terminal of the output capacitor (COUT) at the load. A drop in the high current power ground return path will be compensated. All of the signal components, such as the FB resistor dividers and softstart capacitor, should be referenced to the AGND node. The AGND node carries very little current and, therefore, can be a minimal size trace. 

**MODE/SYNC (Pin D3):** The MODE/SYNC pin facilitates multiphase operation and synchronization to an external clock. Depending on the mode of operation, the MODE/ SYNC pin either accepts an input clock pulse or outputs a clock pulse at its operating frequency. (see Multiphase Operation in Applications Information). The MODE/SYNC pin also programs the mode of operation: pulse-skipping or forced continuous. 

**SSTT (Pin D4):** Soft-Start, Tracking and Temperature Monitor Pin. An internal 10μA current into an external capacitor on the soft-start pin programs the output voltage ramp rate during start-up. When SSTT is below 0.5V, the VFB pin voltage will track the SSTT pin voltage. When SSTT is above 0.5V, the tracking function is disabled, the internal reference resumes control of the error amplifier and the SSTT pin servos to a voltage representative of junction temperature. For a clean recovery from an output short circuit condition, the SSTT pin is pulled down to approximately 140mV above the VFB voltage and a new soft-start cycle is initiated. During shutdown and fault conditions, the SSTT pin is pulled to ground. 

**PGOOD (Pin E3):** Output Power Good with Open-Drain Logic of the Switching Mode Regulator Channel. PGOOD is pulled to ground when the voltage on the FB pin is not within −3%/10% of the internal 0.5V reference. 

**FREQ (Pin E4):** The FREQ pin sets the oscillator frequency with an external resistor to AGND or sets the phasing for multiphase operation. (See Multiphase Operation in Applications Information section). 

Rev. B 

7 

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LTM4658 

## **BLOCK DIAGRAM** 

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VIN<br>R1<br>RUN<br>+ INTERNAL 0.55V VIN<br>R2 0.4V – REFERENCE 0.5V0.49V + VIN<br>CIN<br>SW<br>FREQ<br>OSCILLATOR S Q SWITCH LOGIC  82nH<br>RFREQ R ANTI-SHOOT THROUGHAND  VIN VOUT VOUT<br>COUT<br>SENSE [+]<br>MODE/SYNC GND<br>SENSE [–]<br>SLOPE COM P<br>ERROR RA CFF<br>COMP AMP FB<br>+ 0.5V<br>RB<br>RC<br>AGND<br>CC CCOMP<br>10µA<br>– PGOOD<br>SSTT VTEMP 0.49V +<br>FAULT<br>CSS FAULT<br>+<br>0.55V –<br>4658 F01<br>+<br>–<br>–<br>+<br>+<br>–<br>**----- End of picture text -----**<br>


**Figure 1. Simplified LTM4658 Block Diagram** 

## **DECOUPLING REQUIREMENTS** 

|**SYMBOL**|**PARAMETER**|**CONDITIONS**|**MIN**<br>**TYP**<br>**MAX**|**UNITS**|
|---|---|---|---|---|
|CIN|External Input Capacitor Requirement<br>(VIN= 2.25V to 5.5V, VOUT= 1.5V)|IOUT= 10A|22|µF|
|COUT|External Output Capacitor Requirement<br>(VIN= 2.25V to 5.5V, VOUT= 1.5V)|IOUT= 10A|100|µF|



Rev. B 

8 

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LTM4658 

## **OPERATION** 

The LTM4658 is a standalone nonisolated step-down μModule regulator. It can deliver up to 10A of DC output current with a few external input and output capacitors. This module provides precisely regulated output voltage from 0.5V to 5.5V over 2.25V to 5.5V input voltage range. The typical application schematic is shown on page 1. 

The LTM4658 has an integrated constant frequency peak current mode step-down regulator with power MOSFETs, inductor, and other supporting discrete components. The default switching frequency is 2MHz. It can be externally synchronized to a clock from 1MHz to 2.60MHz. See the Applications Information section. 

Current mode control provides cycle-by-cycle fast current limiting, overcurrent protection. Internal feedback loop compensation provides sufficient stability margins and good transient performance with wide range of output capacitors, even with all ceramic output capacitors. 

Internal undervoltage and overvoltage comparators pull the open-drain PGOOD output low if the feedback voltage exits a −3%/10% window around the regulation point. Furthermore, in an overvoltage condition, internal top MOSFET is turned off and bottom MOSFET is turned on and held on until the overvoltage condition clears. 

For systems with higher power requirements, multiphase operation can be easily employed with the synchronization and phase mode controls. 

Pulling the RUN pin to GND forces the controller into its shutdown state, turning off both power MOSFETs and most of the internal control circuitry. At light load currents, pulse-skipping mode operation can be enabled to achieve higher efficiency compared to forced continuous mode by setting MODE/SYNC pin to VIN. The SSTT pin is used for power supply tracking, soft-start programming and die temperature monitoring. See the Applications Information section. 

Rev. B 

9 

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LTM4658 

## **APPLICATIONS INFORMATION** 

The typical LTM4658 application circuit is shown on page 1. External component selection is primarily determined by the input voltage, the output voltage and the maximum load current. Refer to Table 8 for specific external capacitor requirements for a particular application. 

## **VIN to VOUT Step-Down Ratios** 

The minimum VOUT step-down ratio that can be achieved for a given input voltage is limited by minimum on-time of the regulator. 

The minimum on-time limit imposes a minimum duty cycle of the converter which can be calculated with Equation 1. 

**==> picture [240 x 18] intentionally omitted <==**

where TON(MIN) is the minimum on-time, 45ns typical for the LTM4658. In the rare cases where the minimum duty cycle is surpassed, output will overvoltage and a slower switching frequency is needed to accommodate the high VIN/VOUT ratio. 

The LTM4658 is capable of a maximum duty cycle of 100%, therefore, the VIN-to-VOUT dropout is limited by the RDS(ON) of the top switch, the inductor DCR and the load current. 

It should be noted that the practical transconductance amplifier has a limited output voltage range, to stay in regulation, COMP voltage in the compensation loop must reflect the peak current value. If the output is set to below 0.7V and the switching frequency is 2MHz or above, due to the small ripple current, the output voltage may not be regulated at no load since the transconductance amplifier is running to its low output voltage limit. To avoid this issue, reduce to a lower frequency or change the operation mode to pulse-skipping mode. 

## **Output Voltage Programming and Output Voltage Sensing** 

The PWM controller has an internal 0.5V reference voltage. Resistor divider from VOUT remote sensing point to FB pin and from FB pin to AGND pin programs the output voltage (Equation 2). Refer to the Block Diagram. 

**==> picture [239 x 30] intentionally omitted <==**

In high current operation, a ground offset may be present between the LTM4658 local ground and ground at the load. To overcome this offset, AGND should have a Kelvin connection to the load ground, and the lowest potential node of the resistor divider should be connected to AGND. The internal error amplifier senses the difference between this feedback voltage and a 0.5V AGND referenced voltage. This scheme overcomes any ground offsets between local ground and remote output ground, resulting in a more accurate output voltage. The LTM4658 allows for remote output ground deviations as much as ±100mV with respect to the local ground. 

## **Input Decoupling Capacitors** 

The LTM4658 module should be connected to a low AC-impedance DC source. All of the VIN pins must be connected together with short, wide traces and bypassed to PGND with low ESR capacitors located as close as possible to the pins. For the regulator, one-piece 22µF input ceramic capacitor is recommended for RMS ripple current decoupling. Bulk input capacitor is only needed when the input source impedance is compromised by long inductive leads, traces or not enough source capacitance. The bulk capacitor can be an electrolytic aluminum capacitor and polymer capacitor. 

Without considering the inductor current ripple, the RMS current of the input capacitor can be estimated with Equation 3. 

**==> picture [241 x 31] intentionally omitted <==**

where η % is the estimated efficiency of the power module. 

## **Output Decoupling Capacitors** 

With an optimized high frequency, high bandwidth design, only two pieces of 47μF low ESR output ceramic capacitor is required for LTM4658 to achieve low output voltage ripple and very good transient response. Additional output filtering may be required by the system designer, if further reduction of output ripples or dynamic transient spikes is required. Table 8 shows a matrix of different output voltages and output 

Rev. B 

10 

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LTM4658 

## **APPLICATIONS INFORMATION** 

capacitors to minimize the voltage droop and overshoot during a 2.5A (25%) load-step transient. 

Multiphase operation will reduce effective output ripple as a function of the number of phases. Application Note 77 discusses this noise reduction versus output ripple current cancellation, but the output capacitance will be more a function of stability and transient response. The Analog Devices LTpowerCAD[®] design tool is available to download online for output ripple, stability and transient response analysis and calculating the output ripple reduction as the number of phases implemented increases by N times. 

## **Modes of Operation** 

The MODE/SYNC pin either synchronizes the external switching frequency, or a clock output, to set the PWM mode. The PWM modes of operation are either pulseskipping or forced continuous. See Table 1. 

**Table 1. LTM4658 Single Phase Configuration** 

|**FREQ PIN**<br>**CONNECTION**|**MODE/SYNC**<br>**PIN CONNECTION**|**MODE OF**<br>**OPERATION**|**SWITCHING**<br>**FREQUENCY**|
|---|---|---|---|
|VIN|Clock Input|Forced<br>Continuous|External<br>Clock|
|VIN|AGND|Forced<br>Continuous|2MHz Default|
|VIN|VIN|Pulse-Skip|2MHz Default|
|Resistor<br>to AGND|Clock Output|Forced<br>Continuous|RFREQ<br>Programmed|



The LTM4658 operates in forced continuous mode for low noise or pulse-skipping mode for high efficiency at light load. The LTM4658 operates in pulse-skipping mode when both FREQ and MODE/SYNC pins are connected to VIN. In pulse-skipping mode, switching cycles are skipped at light load to regulate the output voltage. The LTM4658 defaults to forced continuous in regulation and during synchronization. During forced continuous mode, the top switch turns on every cycle and light load regulation is achieved by allowing negative inductor current. 

## **Setting the Operating Frequency** 

The operating frequency defaults to 2MHz when the FREQ pin is tied to VIN. If any frequency higher than the default 

frequency is required, the frequency can be programmed by tying a resistor from FREQ pin to AGND with Equation 4. 

(–1.08) RFREQ = 568 •  f(SW) (4) where RFREQ is in kΩ and fSW is the desired switching frequency in MHz. 

The frequency can be programmed to switch from 1MHz to 3MHz. Table 2 shows the necessary RFREQ value for a desired switching frequency. 

**Table 2. SW Frequency vs RFREQ Value** 

|**Table 2. SW Frequency vs RFREQ **|**Value**|
|---|---|
|**fSW(MHz)**|**RFREQ (kΩ)**|
|1|549|
|2|274|
|2.2|243|
|3|178|



## **Synchronizing the Oscillator to an External Clock** 

The LTM4658 switching frequency can also be adjusted by synchronizing the internal PLL circuit to an external clock to the MODE/SYNC pin. The synchronization frequency range is 1MHz to 2.6MHz. The LTM4658 operates in forced continuous mode when synchronized to an external clock. 

Tie the FREQ pin to VIN configures the MODE/SYNC pin as a clock input. During synchronization, the top power switch turn-on is locked to the rising edge of the external frequency source. The slope compensation is automatically adapted to the external clock frequency. 

At start-up, before the LTM4658 recognizes the external clock applied to MODE/SYNC, the LTM4658 will switch at its default frequency of 2MHz. Once the externally applied clock is recognized, the switching frequency will gradually transition from the default frequency to the applied frequency. If the external clock is removed, the LTM4658 will slowly transition back to the default frequency. 

The synchronizing clock amplitude should be greater than 1.2V and less than 0.4V with a pulse width greater than 40ns. An internal 200k resistor on MODE/SYNC pin to AGND allows the MODE/SYNC to be floating. Please note 

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## **APPLICATIONS INFORMATION** 

that low switching frequency will increase the inductor peak current and the output voltage ripple. 

## **Multiphase Operation** 

For output loads that demand more than 10A of current, multiple LTM4658s can be paralleled to run out of phase to provide more output current without increasing input and output voltage ripples. See Table 3. 

To parallel multiple LTM4658 modules to achieve the same switching frequency, a perfect interleaved phase shift and an accurate current sharing between different modules, one of the LTM4658 will become the main module and the rest of LTM4658s need to be programmed to be subordinate modules. Refer to multiphase application circuits. 

1. Connect a resistor from FREQ pin to AGND of the main phase will programs the frequency and configures the MODE/SYNC pin to become a clock output used to drive the MODE/SYNC pins of the subordinate phase(s). 

Connecting the FREQ pin of the main phase to VIN configures the MODE/SYNC pin to become an input capable of accepting an external clock. The switching frequency defaults to the nominal 2MHz internal 

frequency when the external clock is unavailable, such as during start-up. 

Connecting the FB pin to VIN configures a phase as a subordinate. The MODE/SYNC becomes an input and the voltage control loop is disabled. The subordinate phase current control loop is still active and the peak current is controlled via the shared COMP node. Careful consideration should be taken when routing the COMP node between phases. Routing the COMP and AGND nodes together is recommended to create a low inductance path. 

Connecting the PGOOD pins together and adding an external pull-up resistor allows the main phase to communicate with the subordinate phases on when startup has been completed. 

The pull-up voltage should be greater than 0.49V for subordinate channels on multiphase operations. 

2. The phasing of a subordinate phase relative to the main phase is programmed with a resistor divider on the FREQ pin (see Figure 2). Use of 1% resistors is recommended. See Table 4 for more information. 

**Table 3. Multiphase Configuration** 

|**MAIN/SUBORDINATE**|**FREQ PIN**|**FB PIN**|**MODE/SYNC PIN**|**SWITCHING FREQUENCY (fSW)**|
|---|---|---|---|---|
|Main|VIN|VOUTDivider|Clock Input|External Clock/2MHz Default|
|Main|Resistor to AGND|VOUTDivider|Clock Output|FREQ Programmed|
|Subordinate|VINDivider|VIN|Clock Input|External Clock|



**Table 4. Programming Subordinate Phase Angle** 

|**SYNC PHASE ANGLE**|**R3**<br>**RATIO**|**R4**<br>**RATIO**|**R3**<br>**EXAMPLE**|**R4**<br>**EXAMPLE**|
|---|---|---|---|---|
|0°|0Ω|NA|0Ω|NA|
|90°|3 • R|R|301k|100k|
|120°|7 • R|5 • R|243k|174k|
|180°|NA|0Ω|NA|0Ω|
|240°|5 • R|7 • R|174k|243k|
|270°|R|3 • R|100k|300k|



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When configured for main/subordinate operation, the subordinate phases operate in forced continuous modes. 

**==> picture [74 x 72] intentionally omitted <==**

**----- Start of picture text -----**<br>
VIN<br>FB<br>R3<br>LTM4658<br>FREQ<br>R4<br>4658 F02<br>AGND<br>**----- End of picture text -----**<br>


**Figure 2. Phase Programming** 

The LTM4658 device is an inherently current mode controlled device, so parallel modules will have very good current sharing. This will balance the thermals on the design. Tie RUN, SSTT, FB and COMP pins of each paralleling channel together. Figure 17 through Figure 19 show examples of parallel operation and pin connections. 

## **INPUT RMS Ripple Current Cancellation** 

Application Note 77 provides a detailed explanation of multiphase operation. The input RMS ripple current cancellation mathematical derivations are presented, and a graph is displayed representing the RMS ripple current reduction as a function of the number of interleaved phases. Figure 3 shows this graph. 

**==> picture [247 x 232] intentionally omitted <==**

**----- Start of picture text -----**<br>
0.60<br>1-PHASE<br>2-PHASE<br>0.55 3-PHASE<br>4-PHASE<br>6-PHASE<br>0.50<br>0.45<br>0.40<br>0.35<br>0.30<br>0.25<br>0.20<br>0.15<br>0.10<br>0.05<br>0<br>0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 0.6 0.65 0.7 0.75 0.8 0.85 0.9<br>DUTY CYCLE (VOUT/VIN) 4658 F03<br>DC LOAD CURRENT<br>RMS INPUT RIPPLE CURRENT<br>**----- End of picture text -----**<br>


**Figure 3. Input RMS Current Ratios to DC Load Current as a Function of Duty Cycle** 

## **Soft-Start /Tracking/Temperature Monitor** 

The LTM4658 allows the user to program its output voltage ramp rate by means of the SSTT pin. 

An internal 10μA pulls up the SSTT pin. Putting an external capacitor on SSTT enables soft-starting the output to prevent current surge on the input supply and output voltage overshoot. During the soft-start ramp, the output voltage will proportionally track the SSTT pin voltage. When the soft-start is complete, the pin will servo to a voltage proportional to the LTM4658 junction temperature. See Figure 4 showing the SSTT pin operating range. 

**==> picture [191 x 143] intentionally omitted <==**

**----- Start of picture text -----**<br>
150<br>125<br>DIE TEMP 100 SSTT PIN VOLTAGE<br> (°C) 75 OPERATING RANGE<br>50 TEMP<br>MONITOR<br>25 ~4mV/°C<br>0.6<br>0.5<br>0.4<br>FB<br>0.3<br> (V)<br>0.2<br>SOFT-START<br>0.1 AND TRACKING<br>0<br>0 0.1 0.2 0.3 0.4 0.5 0.6 1.2 1.3 1.4 1.5 1.6 1.7 SSTT (V)<br>4658 F04<br>**----- End of picture text -----**<br>


**Figure 4. Soft-Start and Temperature Monitor Operation** 

The soft-start time is calculated with Equation 5. 

**==> picture [240 x 29] intentionally omitted <==**

For output tracking applications, SSTT can be externally driven by another voltage source. From 0V to 0.5V, the SSTT voltage will override the internal 0.5V reference input to the error amplifier, thus regulating the FB pin voltage to that of SSTT pin. When SSTT is above 0.5V, tracking is disabled and the feedback voltage will regulate to the internal reference voltage. 

An active pull-down circuit is connected to the SSTT pin to discharge the external soft-start capacitor in the case of fault conditions. The ramp will restart when the fault is cleared. Fault conditions that clear the soft-start capacitor are the RUN/UV pin transitioning low, VIN voltage falling too low or thermal shutdown. 

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Once the soft-start cycle has completed and the output power good flag thrown, the SSTT pin reports the die junction temperature. The LTM4658 regulates the SSTT pin to a voltage proportional to the junction temperature. While reporting the temperature, the SSTT voltage is not valid below 1V. The junction temperature is calculated with Equation 6. 

**==> picture [239 x 27] intentionally omitted <==**

The following procedure is used for a more accurate measurement of the junction temperature: 

1. Measure the ambient temperature TA. 

2. Measure the SSTT voltage while in pulse-skipping mode with the VOUT pulled up slightly higher than the regulated VOUT. 

3. Calculate the slope of the temperature sensing circuit using Equation 7. 

**==> picture [240 x 31] intentionally omitted <==**

4. Calculate the junction temperature with the new calibrated slope. 

When the output voltage goes out of regulation and the power good pin is pulled low, the soft-start pin no longer reports the temperature. 

## **Power Good** 

The PGOOD pins are open drain pins that can be used to monitor valid output voltage regulation. This pin monitors a −3/+10% window around the regulation point. A resistor can be pulled up to a particular supply voltage for monitoring. To prevent unwanted PGOOD glitches during transients or dynamic VOUT changes, the LTM4658’s PGOOD falling edge includes a blanking delay of approximately 100µs. The PGOOD is also actively pulled low during fault conditions: RUN pin is low, VIN is too low or in thermal shutdown. 

## **Stability Compensation** 

The LTM4658 module’s internal compensation loop is designed and optimized for low ESR ceramic output capacitors only application. A 10pF to 15pF phase boost cap between VOUT and FB pins may be required to help maintaining a high phase margin. The LTpowerCAD design tool is available to download for control loop optimization. 

## **RUN Threshold Programming** 

The LTM4658 has a precision threshold RUN pin to enable or disable switching. Pulling the RUN pin to ground forces the LTM4658 into its shutdown state, turning off both power MOSFETs and most of its internal control circuitry. Bringing the RUN pin above 0.4V will turn on the entire chip. 

The rising threshold of the RUN comparator is 400mV with 60mV of hysteresis. Connect the RUN pin to VIN if the shutdown feature is not used. Adding a resistor divider from VIN to RUN programs the LTM4658 to regulate the output only when VIN is above a desired voltage (see the Block Diagram). Typically, this threshold, VIN(RUN), is used in situations where the input supply is current limited or has a relatively high source resistance. A switching regulator draws constant power from the source, so source current increases as source voltage drops. This looks like a negative resistance load to the source and can cause the source to current limit or latch low under low source voltage conditions. The VIN(RUN) threshold prevents the regulator from operating at source voltages where problems may occur. This threshold can be adjusted by setting the values R1 and R2 such that they satisfy Equation 8. 

**==> picture [239 x 33] intentionally omitted <==**

where the LTM4658 will remain off until VIN is above VIN(RUN). Due to the comparator’s hysteresis, switching will not stop until the input falls slightly below VIN(RUN). 

Alternatively, a resistor divider from an output of another regulator to the enable RUN pin of the LTM4658 provides event-based power up sequencing, enabling the LTM4658 when the output of the other regulator reaches a predetermined level. 

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## **APPLICATIONS INFORMATION** 

## **Output Overvoltage Protection** 

During an output overvoltage event, when the FB pin voltage is greater than 110% of nominal, the LTM4658 top power switch will be turned off. If the output remains out of regulation for more than 100μs, the PGOOD pin will be pulled low. An output overvoltage event should not happen under normal operating conditions. 

## **Output Short-Circuit Protection and Recovery** 

The peak inductor current at which the current comparator shuts off the top power switch is controlled by the voltage on the COMP pin. If the output current increases, the error amplifier raises the COMP pin voltage until the average inductor current matches the new load current. In normal operation, the LTM4658 clamps at the maximum COMP pin voltage. 

When the output is shorted to ground, the inductor current decays very slowly during the switch off time because of the low voltage across the inductor. To keep the current in control, a secondary limit is also imposed on the valley inductor current. If the inductor current measured through the bottom power switch increases beyond IVALLEY(MAX), the top power switch will be held off and switching cycles will be skipped until the inductor current is reduced. 

Recovery from a short circuit can be abrupt and because the output is shorted and below regulation the regulator is requesting the maximum current to charge the output. When the short circuit condition is removed, the inductor current could cause an extreme voltage overshoot in the output. The LTM4658 addresses this potential issue by regulating the SSTT voltage just above the FB voltage anytime the output is out of regulation. Therefore, a recovery from an output short circuit goes through a soft-start cycle. The output ramp is controlled and the overshoot is minimized. 

## **Thermal Considerations and Output Current Derating** 

The thermal resistances reported in the Pin Configuration section are consistent with those parameters defined by JESD51-9 and are intended for use with finite element analysis (FEA) software modeling tools that leverage the 

outcome of thermal modeling, simulation, and correlation to hardware evaluation performed on a µModule package mounted to a hardware test board—also defined by JESD51-9 (“Test Boards for Area Array Surface Mount Package Thermal Measurements”). The motivation for providing these thermal coefficients in found in JESD51-12 (“Guidelines for Reporting and Using Electronic Package Thermal Information”). 

Many designers may opt to use laboratory equipment and a test vehicle such as the demo board to anticipate the µModule regulator’s thermal performance in their application at various electrical and environmental operating conditions to compliment any FEA activities. Without FEA software, the thermal resistances reported in the Pin Configuration section are in-and-of themselves not relevant to providing guidance of thermal performance; instead, the derating curves provided in the data sheet can be used in a manner that yields insight and guidance pertaining to one’s application-usage, and can be adapted to correlate thermal performance to one’s own application. 

The Pin Configuration section typically gives four thermal coefficients explicitly defined in JESD51-12; these coefficients are quoted or paraphrased below: 

1. θ JA, the thermal resistance from junction to ambient, is the natural convection junction-to-ambient air thermal resistance measured in a one cubic foot sealed enclosure. This environment is sometimes referred to as “still air” although natural convection causes the air to move. This value is determined with the part mounted to a JESD51-9 defined test board, which does not reflect an actual application or viable operating condition. 

2. θ JCbot, the thermal resistance from junction to bottom of the product case, is determined with all of the component power dissipation flowing through the bottom of the package. In the typical module regulator, the bulk of the heat flows out the bottom of the package, but there is always heat flow out into the ambient environment. As a result, this thermal resistance value maybe useful for comparing packages but the test conditions don’t generally match the user’s application. 

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3. θ JCtop, the thermal resistance from junction to top of the product case, is determined with nearly all of the component power dissipation flowing through the top of the package. As the electrical connections of the typical µModule are on the bottom of the package, it is rare for an application to operate such that most of the heat flows from the junction to the top of the part. As in the case of θ JCbot, this value may be useful for comparing packages but the test conditions don’t generally match the user’s application. 

A graphical representation of the aforementioned thermal resistances is given in Figure 5; blue resistances are contained within the µModule regulator, whereas green resistances are external to the µModule. 

As a practical matter, it should be clear to the reader that no individual or sub-group of the four thermal resistance parameters defined by JESD51-12 or provided in the Pin Configuration section replicates or conveys normal operating conditions of a μModule. For example, in normal board-mounted applications, never does 100% of the device’s total power loss (heat) thermally conduct exclusively through the top or exclusively through bottom of the µModule—as the standard defines for θ JCtop and θ JCbot, respectively. In practice, power loss is thermally dissipated in both directions away from the package—granted, in the absence of a heat sink and airflow, a majority of the heat flow is into the board. 

Within a SIP (system-in-package) module, be aware there are multiple power devices and components dissipating power, with a consequence that the thermal resistances relative to different junctions of components or die are not exactly linear with respect to total package power loss. To reconcile this complication without sacrificing modeling simplicity—but also, not ignoring practical realities—an approach has been taken using FEA software modeling along with laboratory testing in a controlled-environment chamber to reasonably define and correlate the thermal resistance values supplied in this data sheet: (1) Initially, FEA software is used to accurately build the mechanical geometry of the µModule and the specified PCB with all of the correct material coefficients along with accurate power loss source definitions; (2) this model simulates a software-defined JEDEC environment consistent with JESD51-9 to predict power loss heat flow and temperature readings at different interfaces that enable the calculation of the JEDEC-defined thermal resistance values; (3) the model and FEA software is used to evaluate the µModule with heat sink and airflow; (4) having solved for and analyzed these thermal resistance values and simulated various operating conditions in the software model, a thorough laboratory evaluation replicates the simulated conditions with thermocouples within a controlled-environment chamber while operating the device at the same power loss as that which was simulated. An outcome of this process and due-diligence yields a set of derating curves provided in other sections of this data sheet. 

**==> picture [402 x 146] intentionally omitted <==**

**----- Start of picture text -----**<br>
µModule DEVICE θJA JUNCTION-TO-AMBIENT RESISTANCE<br>θJCtop JUNCTION-TO-CASE CASE (TOP)-TO-AMBIENT<br>(TOP) RESISTANCE RESISTANCE<br>JUNCTION AMBIENT<br>θJCbot JUNCTION-TO-CASE CASE (BOTTOM)-TO-BOARD BOARD-TO-AMBIENT<br>(BOTTOM) RESISTANCE RESISTANCE RESISTANCE<br>4658 F05<br>**----- End of picture text -----**<br>


**Figure 5. Graphical Representation of JESD51-12 Thermal Coefficients** 

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The 2.5VIN, 3.3VIN and 5VIN power loss curves in Figure 6, Figure 7 and Figure 8 can be used in coordination with the load current derating curves in Figure 9 to Figure 14 for calculating an approximate θ JA thermal resistance for the LTM4658 with various heat sinking and airflow conditions. The power loss curves are taken at room temperature, and are increased with multiplicative factors according to the junction temperature. This approximate factor is ~1.2 assuming the junction temperature is reaching 120°C. Maximum load current is achievable while increasing ambient temperature as long as the junction temperature is less than 120°C, which is 5°C guardband from maximum junction temperature of 125°C. When the ambient temperature reaches a point where the junction temperature is 120°C, then the load current is lowered to maintain the junction at 120°C while increasing ambient temperature up to 120°C. The derating curves are plotted with the output current starting at 10A and the ambient temperature at 30°C. The output voltages are 1.0V, 1.5V and 2.5V. These are chosen to include the lower and higher output voltage ranges for correlating the thermal resistance. Thermal models are derived from several temperature measurements in a controlled temperature chamber along with thermal modeling analysis. The junction temperatures are monitored while ambient temperature is increased with and without airflow. The power loss increase with ambient temperature change is factored into the derating curves. The junctions are maintained at 120°C maximum while lowering output current or power with increasing ambient temperature. The decreased output current will 

decrease the internal module loss as ambient temperature is increased. The monitored junction temperature of 120°C minus the ambient operating temperature specifies how much module temperature rise can be allowed. For example, to determine the maximum ambient temperature allowable when VIN = 5V, VOUT = 1V and 10A load current without a heat sink and airflow, simply find out the power loss from Figure 7 which equals to 1.54W in this case, then multiply by the 1.2 coefficient for 120°C junction temperature, If the 81.6°C ambient temperature is subtracted from the 120°C junction temperature, then the difference of 43°C divided by 1.85W equals a 21°C/W for θ JA the system equivalent thermal resistance. Table 5 specifies 20.8°C/W value which is very close. Table 6 and Table 7 provide equivalent thermal resistances for 1.5V and 2.5V outputs with and without airflow. **The Pin Configuration section shows the simulation data for the worst case scenario.** Table 5 through Table 7 provide equivalent thermal resistances for 1.0V, 1.5V and 2.5V outputs with and without airflow. The derived thermal resistances in Table 5 through Table 7 for the various conditions can be multiplied by the calculated power loss as a function of ambient temperature to derive temperature rise above ambient, thus maximum junction temperature. Room temperature power loss can be derived from the efficiency curves in the Typical Performance Characteristics section and adjusted with the above ambient temperature multiplicative factors. The printed circuit board is a 1.6mm thick four-layer board with two ounce copper for the two outer layers and one ounce copper for the two inner layers. The PCB dimensions are 95mm × 76mm. 

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**==> picture [523 x 622] intentionally omitted <==**

**----- Start of picture text -----**<br>
3 3 3<br>1.8VOUT 0.8VOUT 1.8VOUT 0.8VOUT 3.3VOUT 1.0VOUT<br>1.5VOUT 0.5VOUT 1.5VOUT 0.5VOUT 2.5VOUT 0.8VOUT<br>1.0VOUT 1.0VOUT 1.5VOUT 0.5VOUT<br>2 2 2<br>1 1 1<br>0 0 0<br>0 1 2 3 4 5 6 7 8 9 10 0 1 2 3 4 5 6 7 8 9 10 0 1 2 3 4 5 6 7 8 9 10<br>LOAD CURRENT (A) LOAD CURRENT (A) LOAD CURRENT (A)<br>4658 F06 4658 F07 4658 F08<br>Figure 6. Power Loss vs  Figure 7. Power Loss vs Load  Figure 8. Power Loss vs Load<br>Load Current at 2.5VIN Current at 3.3VIN Current at 5VIN<br>12 12 12<br>10 10 10<br>8 8 8<br>6 6 6<br>4 4 4<br>2 0LFM 2 0LFM 2 0LFM<br>200LFM 200LFM 200LFM<br>400LFM 400LFM 400LFM<br>0 0 0<br>0 20 40 60 80 100 120 0 20 40 60 80 100 120 0 20 40 60 80 100 120<br>TAMB (°C) TAMB (°C) TAMB (°C)<br>4658 F09 4658 F10 4658 F11<br>Figure 9. 3.3V to 1V Derating  Figure 10. 3.3V to 1.5V  Figure 11. 3.3V to 2.5V<br>Curve, No Heat Sink Derating Curve, No Heat Sink Derating Curve, No Heat Sink<br>12 12 12<br>10 10 10<br>8 8 8<br>6 6 6<br>4 4 4<br>2 0LFM 2 0LFM 2 0LFM<br>200LFM 200LFM 200LFM<br>400LFM 400LFM 400LFM<br>0 0 0<br>0 20 40 60 80 100 120 0 20 40 60 80 100 120 0 20 40 60 80 100 120<br>TAMB (°C) TAMB (°C) TAMB (°C)<br>4658 F12 4658 F13 4658 F14<br>Figure 12. 5V to 1V Derating  Figure 13. 5V to 1.5V Derating  Figure 14. 5V to 2.5V Derating<br>Curve, No Heat Sink Curve, No Heat Sink Curve, No Heat Sink<br>Rev. B<br>POWER LOSS (W) POWER LOSS (W) POWER LOSS (W)<br>LOAD CURRENT (A) LOAD CURRENT (A) LOAD CURRENT (A)<br>LOAD CURRENT (A) LOAD CURRENT (A) LOAD CURRENT (A)<br>**----- End of picture text -----**<br>


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**Table 5. 1.0V Output** 

|**Table 5. 1.0V Output**||||||
|---|---|---|---|---|---|
|**DERATING CURVE**|**VIN (V)**|**POWER LOSS CURVE**|**AIRFLOW (LFM)**|**HEAT SINK**|θ**JA (°C/W)**|
|Figure 9, Figure 12|3.3, 5|Figure 7, Figure 8|0|None|20.6|
|Figure 9, Figure 12|3.3, 5|Figure 7, Figure 8|200|None|18.5|
|Figure 9, Figure 12|3.3, 5|Figure 7, Figure 8|400|None|17.4|



## **Table 6. 1.5V Output** 

|**Table 6. 1.5V Output**||||||
|---|---|---|---|---|---|
|**DERATING CURVE**|**VIN (V)**|**POWER LOSS CURVE**|**AIRFLOW (LFM)**|**HEAT SINK**|θ**JA (°C/W)**|
|Figure 10, Figure 13|3.3, 5|Figure 7, Figure 8|0|None|20.5|
|Figure 10, Figure 13|3.3, 5|Figure 7, Figure 8|200|None|18.3|
|Figure 10, Figure 13|3.3, 5|Figure 7, Figure 8|400|None|17.5|



**Table 7. 2.5V Output** 

|**Table 7. 2.5V Output**||||||
|---|---|---|---|---|---|
|**DERATING CURVE**|**VIN (V)**|**POWER LOSS CURVE**|**AIRFLOW (LFM)**|**HEAT SINK**|θ**JA (°C/W)**|
|Figure 11, Figure 14|3.3, 5|Figure 7, Figure 8|0|None|21.2|
|Figure 11, Figure 14|3.3, 5|Figure 7, Figure 8|200|None|18.3|
|Figure 11, Figure 14|3.3, 5|Figure 7, Figure 8|400|None|17.5|



**Table 8. Output Voltage Response vs Component Matrix (Refer to Front Page Figure) 0A to 5A Load Step Typical Measured Values** 

|**CIN CERAMIC**<br>**VENDORS**|**CIN CERAMIC**<br>**VENDORS**|**CIN CERAMIC**<br>**VENDORS**|**VALUE**<br>**(μF)**|**VALUE**<br>**(μF)**|**PART NUMBER**|**PART NUMBER**|**PART NUMBER**|**PART NUMBER**|**COUT VENDORS**|**COUT VENDORS**|**COUT VENDORS**|**VALUE**<br>**(μF)**|**VALUE**<br>**(μF)**|**PART**<br>**NUMBER**|**PART**<br>**NUMBER**|**PART**<br>**NUMBER**|
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|Taiyo Yuden|||10||EMK212BB7106MG-T||||Murata|||22||GRM188R60J226MEA0D|||
|Murata|||22||GRM188R61A226ME15D||||Murata|||100||GRM21BR60J107ME15K|||
||||||||||||||||||
|**VOUT**<br>**(V)**|**CIN**<br>**(CERAMIC)**<br>**(μF)**|**CIN**<br>**(BULK)**||**COUT**<br>**(CERAMIC)**<br>**(μF)**||**COUT**<br>**(BULK)**<br>**(μF)**|**CFF**<br>**(pF)**|**VIN**<br>**(V)**||**DROOP**<br>**(mV)**|**P-P**<br>**Deviation**<br>**(mV)**|**RECOVERY**<br>**TIME**<br>**(µs)**|**LOAD**<br>**STEP**<br>**(A/µs)**||**LOAD STEP**<br>**SLEW RATE**<br>**(A/µs)**|**FREQ.**<br>**(kHz)**|
|0.5|2 ×10|150||100 + 2 ×22||Open|Open|3.3||40|78|5|5||5|1000|
|0.8|2 ×10|150||100 + 2 ×22||Open|Open|3.3||45|92|10|5||5|2000|
|0.8|2 ×10|150||100 + 2 ×22||Open|Open|5||45|90|10|5||5|2000|
|1|2 ×10|150||100 + 2 ×22||Open|Open|3.3||55|109|10|5||5|2000|
|1|2 ×10|150||100 + 2 ×22||Open|Open|5||55|105|10|5||5|2000|
|1.5|2 ×10|150||100 + 2 ×22||Open|Open|3.3||80|157|10|5||5|2000|
|1.5|2 ×10|150||100 + 2 ×22||Open|Open|5||80|156|10|5||5|2000|
|2.5|2 ×10|150||100 + 2 ×22||Open|Open|3.3||120|239|15|5||5|2000|
|2.5|2 ×10|150||100 + 2 ×22||Open|Open|5||120|241|15|5||5|2000|
|3.3|2 ×10|150||100 + 2 ×22||Open|Open|5||120|291|15|5||5|2000|



Rev. B 

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For more information www.analog.com 

LTM4658 

## **APPLICATIONS INFORMATION** 

## **Safety Considerations** 

The LTM4658 modules do not provide galvanic isolation from VIN to VOUT. There is no internal fuse. If required, a slow blow fuse with a rating twice the maximum input current needs to be provided to protect each unit from catastrophic failure. The device does support thermal shutdown and over current protection. 

## **Layout Checklist/Example** 

The high integration of LTM4658 makes the PCB board layout very simple and easy. However, to optimize its electrical and thermal performance, some layout considerations are still necessary. 

- Use large PCB copper areas for high current paths, including VIN, GND and VOUT. It helps to minimize the PCB conduction loss and thermal stress. 

- Place high frequency ceramic input and output capacitors next to the VIN, GND and VOUT pins as close as possible to minimize high frequency noise. 

- Place a dedicated power ground layer underneath the unit. 

- To minimize the via conduction loss and reduce module thermal stress, use multiple vias for interconnection between top layer and other power layers. 

- Do not put via directly on the pad, unless they are capped or plated over. 

- Use a separated GND ground copper area for components connected to signal pins. Connect the AGND to GND underneath the unit. 

- For parallel modules, tie the VOUT, VFB, and COMP pins together. Use an internal layer to closely connect these pins together. The SSTT pin can be tied a common capacitor for regulator soft-start. 

- Bring out test points on the signal pins for monitoring. 

- Figure 15 gives a good example of the recommended layout. 

**==> picture [252 x 227] intentionally omitted <==**

**----- Start of picture text -----**<br>
COUT<br>CIN 5<br>4<br>3<br>2<br>1<br>A B C D E<br>GND<br>**----- End of picture text -----**<br>


**==> picture [21 x 5] intentionally omitted <==**

**----- Start of picture text -----**<br>
4658 F15<br>**----- End of picture text -----**<br>


**Figure 15. Recommended PCB Layout** 

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LTM4658 

## **TYPICAL APPLICATIONS** 

**==> picture [235 x 122] intentionally omitted <==**

**----- Start of picture text -----**<br>
VIN<br>2.5V TO 5V<br>22µF 22µF<br>RUN VIN PGOOD<br>VOUT<br>MODE/SYNC VOUT 0.5V<br>10A<br>60.4k<br>LTM4658 47µF<br>SSTT FB ×4<br>0.1µF<br>COMP FREQ<br>AGND GND 549k<br>4658 F16<br>**----- End of picture text -----**<br>


**Figure 16. High Efficiency, 1MHz, 0.5V, 10A Forced Continuous Mode, Low Part Count** 

**==> picture [282 x 218] intentionally omitted <==**

**----- Start of picture text -----**<br>
PGOOD<br>VIN 100k<br>2.5V TO 5.5V 22µF VIN PGOOD VIN<br>6.3V RUN VOUT VOUT<br>LTM4658 RA 100µF 1V<br>COMP 60.4k 6.3V 20A<br>FB<br>MODE/SYNC RB<br>60.4k<br>SSTT FREQ<br>0.1µF AGND GND RFREQ<br>274k<br>VIN<br>22µF VIN PGOOD PGOOD<br>6.3V RUN VOUT<br>LTM4658 100µF<br>SSTT 6.3V<br>MODE/SYNC FB VIN<br>COMP FREQ<br>AGND GND 180°<br>4658 F17<br>**----- End of picture text -----**<br>


**Figure 17. Dual-Phase Application with 180° Phase** 

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LTM4658 

## **TYPICAL APPLICATIONS** 

**==> picture [282 x 316] intentionally omitted <==**

**----- Start of picture text -----**<br>
PGOOD<br>VIN 100k<br>3.5V TO 4.5V 22µF VIN PGOOD VIN<br>6.3V RUN VOUT VOUT<br>RA 100µF 0.6V<br>COMP LTM4658 86.6k 6.3V 30A<br>FB<br>MODE/SYNC RB<br>432k<br>SSTT FREQ<br>0.1µF AGND GND RFREQ<br>274k<br>VIN<br>22µF VIN PGOOD PGOOD<br>6.3V RUN VOUT<br>100µF<br>COMP LTM4658 FB VIN 6.3V<br>MODE/SYNC 243k<br>SSTT FREQ<br>AGND GND 174k<br>120˚<br>VIN<br>22µF VIN PGOOD PGOOD<br>6.3V RUN VOUT<br>100µF<br>COMP LTM4658 FB VIN 6.3V<br>MODE/SYNC 174k<br>SSTT FREQ<br>AGND GND 243k<br>4658 F18<br>240˚<br>**----- End of picture text -----**<br>


**Figure 18. Three-Phase Application** 

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LTM4658 

## **TYPICAL APPLICATIONS** 

**==> picture [288 x 421] intentionally omitted <==**

**----- Start of picture text -----**<br>
PGOOD<br>VIN 100k<br>3.0V TO 5.5V 22µF6.3V RUNVIN PGOODVOUT VIN V1.2VOUT<br>FREQ LTM4658 RA 100µF 40A<br>COMP 140k 6.3V<br>FB<br>MODE/SYNC RB<br>100k<br>SSTT<br>0.1µF AGND GND<br>VIN<br>22µF VIN PGOOD PGOOD<br>6.3V RUN VOUT<br>LTM4658 100µF<br>COMP FB VIN 6.3V<br>MODE/SYNC 301k<br>SSTT FREQ<br>AGND GND 100k<br>90˚<br>VIN<br>22µF VIN PGOOD PGOOD<br>6.3V RUN VOUT<br>LTM4658 100µF<br>COMP 6.3V<br>FB VIN<br>MODE/SYNC<br>SSTT FREQ<br>AGND GND<br>180˚<br>VIN<br>22µF VIN PGOOD PGOOD<br>6.3V RUN VOUT<br>LTM4658 100µF<br>COMP FB VIN 6.3V<br>MODE/SYNC 100k<br>SSTT FREQ<br>AGND GND 301k<br>4658 F19<br>270˚<br>**----- End of picture text -----**<br>


**Figure 19. Four-Phase Application** 

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LTM4658 

## **PACKAGE DESCRIPTION** 

## **PACKAGE ROW AND COLUMN LABELING MAY VARY AMONG µModule PRODUCTS. REVIEW EACH PACKAGE LAYOUT CAREFULLY.** 

## **Table 9. LTM4658 Component Pinout** 

|**PIN ID**|**FUNCTION**|**PIN ID**|**FUNCTION**|**PIN ID**|**FUNCTION**|**PIN ID**|**FUNCTION**|**PIN ID**|**FUNCTION**|
|---|---|---|---|---|---|---|---|---|---|
|A1|GND|A2|GND|A3|VIN|A4|COMP|A5|RUN|
|B1|SW|B2|GND|B3|VIN|B4|FB|B5|VOUT|
|C1|SW|C2|GND|C3|VIN|C4|AGND|C5|VOUT|
|D1|SW|D2|GND|D3|MODE/SYNC|D4|SSTT|D5|VOUT|
|E1|GND|E2|GND|E3|PGOOD|E4|FREQ|E5|VOUT|



Rev. B 

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LTM4658 

## **PACKAGE DESCRIPTION** 

**==> picture [471 x 574] intentionally omitted <==**

**----- Start of picture text -----**<br>
6<br>SEE NOTES<br>PIN 1<br>A B C D E<br>1 LGA 25 0619 REV Ø<br>e<br>DETAIL A 2<br>3 G<br>4 b<br>5 PACKAGE BOTTOM VIEW LTMXXXX<br>3 b e PACKAGE IN TRAY LOADING ORIENTATION<br>SEE NOTES F PACKAGE ROW AND COLUMN LABELING MAY VARY  AMONG µModule PRODUCTS. REVIEW EACH PACKAGE  LAYOUT CAREFULLY<br>!<br>DETAILS OF PIN 1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE PIN 1 IDENTIFIER MAY BE EITHER A MOLD OR  MARKED FEATURE<br>PIN 1 BEVEL<br>NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994 2. ALL DIMENSIONS ARE IN MILLIMETERS 3        LAND DESIGNATION PER JEP95 4 5. PRIMARY DATUM -Z- IS SEATING PLANE 6<br>COMPONENT TRAY PIN 1<br>Y<br>X<br>Z Z<br>M M<br>ddd eee<br> 4.32mm) × A<br>DETAIL B<br>DETAIL A<br>NOTES PAD DIMENSION SUBSTRATE THK MOLD CAP HT<br> 4mm  PACKAGE SIDE VIEW<br>×<br>Øb (25 PLACES)<br>MAX 4.41 0.03 0.38 0.15 0.10 0.10 0.15 0.08<br>LGA Package<br>DETAIL C H1<br>SUBSTRATE DIMENSIONS NOM 4.32 0.35 4.00 4.00 0.65 2.60 2.60<br>0.32 REF 4.00 REF<br>b<br>25-Lead (4mm<br>(Reference LTC DWG# 05-08-1830 Rev Ø)<br>MIN 4.23 0.32<br>A1 DETAIL C<br>MOLD CAP H2 DETAIL B A A1 b D E e F G H1 H2 aaa bbb ccc ddd eee<br>SYMBOL<br>aaa  Z<br>2× D X<br>Y 1.30 0.65 0.000 0.65 1.30<br>E<br>TOP VIEW<br>PACKAGE TOP VIEW<br>SUGGESTED PCB LAYOUT<br>PIN 1 CORNER 4<br>0.35 REF Ø 25x<br>Z<br>  ZIccc<br>Z//  bbb<br>1.30<br>0.65<br>0.000<br>0.65<br>1.30<br>aaa  Z 2×<br>**----- End of picture text -----**<br>


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For more information www.analog.com 

LTM4658 

## **PACKAGE DESCRIPTION** 

**==> picture [434 x 555] intentionally omitted <==**

**----- Start of picture text -----**<br>
6<br>SEE NOTES<br>PIN 1<br>A B C D E<br>1 BGA 25 0721 REV Ø<br>e<br>DETAIL A 2<br>3 G<br>4 b<br>5 PACKAGE BOTTOM VIEW<br>3 b e PACKAGE IN TRAY LOADING ORIENTATION<br>SEE NOTES F PACKAGE ROW AND COLUMN LABELING MAY VARY  AMONG µModule PRODUCTS. REVIEW EACH PACKAGE  LAYOUT CAREFULLY<br>!<br>DETAILS OF PIN 1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE PIN 1 IDENTIFIER MAY BE EITHER A MOLD OR  MARKED FEATURE<br>PIN 1 BEVEL<br>NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994 2. ALL DIMENSIONS ARE IN MILLIMETERS 3        LAND DESIGNATION PER JEP95 4 5. PRIMARY DATUM -Z- IS SEATING PLANE 6<br>COMPONENT TRAY PIN 1<br>A A2<br>DETAIL B<br>PACKAGE SIDE VIEW<br> 4.62mm × YX NOTES BALL HT BALL DIMENSION PAD DIMENSION SUBSTRATE THK MOLD CAP HT<br>Z Z<br>M M<br> 4mm  × (BC-25-2) ddd eee MAX 4.78 0.37 4.41 0.45 0.38 0.15 0.10 0.10 0.15 0.08<br>H1<br>A1 SUBSTRATE<br>DETAIL A<br> 4mm  DIMENSIONS NOM 4.62 0.30 4.32 0.40 0.35 4.00 4.00 0.65 2.60 2.60<br>b1 Øb (25 PLACES) 0.32 REF 4.00 REF<br>ccc  Z<br>DETAIL B TOTAL NUMBER OF BALLS: 25<br>MIN 4.46 0.23 4.23 0.35 0.32<br>MOLD CAP H2<br>25-Ball Chip Scale Package Ball Grid Array [CSP_BGA] A A1 A2 b b1 D E e F G H1 H2 aaa bbb ccc ddd eee<br>SYMBOL<br>aaa  Z<br>2× D X<br>Y 1.30 0.65 0.000 0.65 1.30<br>E<br>TOP VIEW<br>PACKAGE TOP VIEW<br>SUGGESTED PCB LAYOUT<br>PIN 1 CORNER 4<br>0.35 REF Ø 25x<br>Z<br>Z<br>Z//  bbb<br>1.30<br>0.65<br>0.000<br>0.65<br>1.30<br>aaa  Z 2×<br>**----- End of picture text -----**<br>


Rev. B 

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LTM4658 

## **REVISION HISTORY** 

|**REV**|**DATE**|**DESCRIPTION**|**PAGE NUMBER**|
|---|---|---|---|
|A|10/22|Changed master to main and slave to subordinate.<br>Added BGA package option, updated peak reflow temperature.<br>Added label on G11.<br>Added pull-up voltage comment in Multiphase Operation section.<br>Corrected Pin D4 to read SSTT.<br>Updated Package Description.<br>Added ink marking statement to package photos.|All<br>2<br>6<br>12<br>24<br>26, 28<br>28|
|B|9/23|Updated Order Information<br>Updated in Electrical Characteristics (VRUNparameter)<br>Updated Setting the Oerating Frequeny section<br>Updated Package Description|2<br>3<br>11<br>26|



Rev. B 

27 

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implicatiFor more informati **on** or otherwise under any patent or patent rights of Analog Devices.www.analog.com 

LTM4658 

## **PACKAGE PHOTOS** 

## **Part marking is either ink mark or laser mark** 

**(a) LGA Package** 

**(b) BGA Package** 

## **DESIGN RESOURCES** 

|**DESIGN RESOURCES**|||
|---|---|---|
|**SUBJECT**|**DESCRIPTION**||
|µModule Design and Manufacturing Resources|Design:<br>• Selector Guides<br>• Demo Boards and Gerber Files<br>• Free Simulation Tools|Manufacturing:<br>• Quick Start Guide<br>• PCB Design, Assembly and Manufacturing Guidelines<br>• Package and Board Level Reliability|
|µModule Regulator Products Search|1.  Sort table of products by parameters and download the result as a spread sheet.<br>2. Search using the Quick Power Search parametric table.<br>INPUT |<br>Vin(Min)<br>Vv<br>Vin(Max)<br>Vv<br>OUTPUT |<br>Vout<br>Vv<br>lout<br>A<br>FEATURES |<br>Low EMI<br>Ultrathin<br>Internal Heat Sink<br>{search)||
|Digital Power System Management|Analog Devices’ family of digital power supply management ICs are highly integrated solutions that<br>offer essential functions, including power supply monitoring, supervision, margining and sequencing,<br>and feature EEPROM for storing user configurations and fault logging.||



## **RELATED PARTS** 

|**PART NUMBER**|**DESCRIPTION**|**COMMENTS**|
|---|---|---|
|LTM4670|Quad 10A Step-Down µModule Regulator|2.25V ≤ VIN≤ 5.5V, 0.5V ≤ VOUT≤ 5.5V, 15mm × 7.50mm × 4.65mm BGA|
|LTM4691|Low VIN, Ultrathin, Dual 2A Step-Down µModule Regulator|2.25V ≤ VIN≤ 3.6V, 0.5V ≤ VOUT≤ 2.5V, 3mm × 4mm × 1.18mm LGA/BGA|
|LTM4668/<br>LTM4668A|Quad 1.2A Step-Down µModule Regulator|2.7V ≤ VIN≤ 17V, 0.6V ≤ VOUT≤ 1.8V (LTM4668A: 0.6V ≤ VOUT≤ 5.5V,<br>2.25MHz)6.25mm × 6.25mm × 2.1mm BGA|
|LTM4622|Ultrathin, Dual 2.5A or Single 5A Step-Down µModule Regulator|3.6V ≤ VIN≤ 20V, 0.6V ≤ VOUT≤ 5.5V, 6.25mm × 6.25mm × 1.82mm<br>LGA, 6.25mm × 6.25mm × 2.42mm BGA|
|LTM4626|12A μModule Regulator. Pin Compatible with LTM4657, LTM4638|3.1V ≤ VIN≤ 20V. 0.6V ≤ VOUT≤ 5.5V, 6.25mm × 6.25mm × 3.87mm BGA|
|LTM4657|8A μModule Regulator. Pin Compatible with LTM4626, LTM4638|3.1V ≤ VIN≤ 20V, 0.5V ≤ VOUT≤ 5.5V, 6.25mm × 6.25mm × 3.87mm BGA|
|LTM4638|15A μModule Regulator. Pin Compatible with LTM4657, LTM4626|3.1V ≤ VIN≤ 20V, 0.6V ≤ VOUT≤ 5.5V, 6.25mm × 6.25mm × 5.02mm BGA|
|LTM4663|Ultrathin 1.5A μModule Thermoelectric Cooler(TEC)Regulator|2.7V ≤ VIN≤ 5.5V, 3.5mm × 4mm × 1.3mm LGA|
|LTM4693|Low VIN, Ultrathin, 2A Buck-Boost μModule Regulator|2.6V ≤ VIN≤ 5.5V, 1.8V ≤ VOUT≤ 5.5V, 3.5mm × 4mm × 1.25mm LGA|



Rev. B 

9/23 www.analog.com 

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