LTM4653IY#PBF

LTM4653 

## EN55022B Compliant 58V, 4A Step‑Down DC/DC μModule Regulator 

## **FEATURES** 

## **DESCRIPTION** 

- n **Complete Low EMI Switch Mode Power Supply** 

- n **EN55022 Class B Compliant** 

- n **Wide Input Voltage Range: 3.1V to 58V** 

- n **Up to 4A Output Current** 

- n **Output Voltage Range: 0.5V ≤ VOUT ≤ 0.94** • **VIN** 

- n **±1.67% Total DC Output Voltage Error Over Line, Load and Temperature (–40°C to 125°C)** 

- n **Parallel and Current Share with Multiple LTM4653s** 

- n **Analog Output Current Indicator** 

- n **Programmable Input Voltage Limiting** 

- n Constant-Frequency Current Mode Control 

- n Power Good Indicator and Programmable Soft-Start 

- n Overcurrent/Overvoltage/Overtemperature Protection 

- n 15mm × 9mm × 5.01mm BGA Package 

## **APPLICATIONS** 

- n Avionics, Industrial Control and Test Equipment 

- n Video, Imaging and Instrumentation 

- n 48V Telecom and Network Power Supplies 

The LTM[®] 4653 is an ultralow noise 58V, 4A DC/DC stepdown μModule[®] regulator designed to meet the radiated emissions requirements of EN55022. Conducted emission requirements can be met by adding standard filter components. Included in the package are the switching controller, power MOSFETs, inductor, filters and support components. 

Operating over an input voltage range of 3.1V to 58V, the LTM4653 supports an output voltage range of 0.5V to 94% of VIN, and a switching frequency range of 250kHz to 3MHz (400kHz default), each set by a single resistor. For high load currents, the LTM4653 can be paralleled in PolyPhase[®] operation and synchronized to an external clock. Only the bulk input and output filter capacitors are needed to finish the design. 

The LTM4653 is offered in a 15mm × 9mm × 5.01mm BGA package with SnPb or RoHS compliant terminal finish. 

All registered trademarks and trademarks are the property of their respective owners. Protected by U.S. Patents, including 5481178, 5705919, 5847554, 6580258. 

- n RF Systems 

## **TYPICAL APPLICATION** 

**4A, 24V Output Low EMI DC/DC μModule Regulator with Analog Output Current Indicator** 

**Radiated Emission Scan in a 10m Chamber LTM4653 Delivering 24VOUT at 3.5A, from 48VIN** 

**==> picture [522 x 173] intentionally omitted <==**

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IOUT 70<br>28V TO 58VVIN VIN VOUT _ UP TO 4A24VOUT 60 MEAS DIST 10m SPEC DIST 10m P| ft | ft | yl<br>4.7μF SVIN VOSNS 10µF 50<br>×2<br>VD LOAD 40<br>= Po Ree<br>RUN SGND<br>4.7μF PGND 30<br>INTVCC<br>z LTM4653 20 A<br>VINREG<br>ANALOG OUTPUT 10 QPK LIMIT<br>10nF COMPa IMONbIMONa CURRENT INDICATORVIMON = 0.25Ω • IOUT 0 [1] HORIZONTAL [2] VERTICAL<br>499Ω + FORMAL<br>Ff fSET PINS NOT USED IN  –1030 P| 130 230 | 330 [| 430 | 530 ft 630 ft, 730 830 930 1000<br>124k GND ISETa ISETb THIS CIRCUIT: FREQUENCY (MHz) 4653 TA01b<br>4653 TA01a CLKIN, PGOOD, COMPbPGDFB, SW, EXTVCC<br>TEMP [+] , TEMP [–] , NC<br>481k<br>AMPLITUDE (dBµV/m)<br>**----- End of picture text -----**<br>


Rev. B 

1 

For more information LTM4653 

Document Feedback 

## LTM4653 

## **ABSOLUTE MAXIMUM RATINGS** 

## **PIN CONFIGURATION** 

## **(Note 1)** 

## **All Voltages Relative to VOUT[–] , Unless Otherwise Indicated** 

## **Terminal Voltages** 

VIN, VD, SVIN, SW, ISETa, VOUT, VOSNS .........–0.3V to 60V GND, ISETb, EXTVCC .................................. –0.3V to 28V RUN ........................................ GND –0.3V to PGND 60V INTVCC, PGDFB, VINREG, COMPa, COMPb, IMONa, IMONb  ............................................ –0.3V to 4V fSET .......................................................–0.3V to INTVCC CLKIN, PGOOD (Relative to GND)  ............... –0.3V to 6V **Terminal Currents** INTVCC Peak Output Current (Note 8) ....................30mA TEMP[+] ......................................................–1mA to 10mA TEMP[–] .....................................................–10mA to 1mA 

## **Temperatures** 

Internal Operating Temperature Range (Note 2) .................................................. –40°C to 125°C Storage Temperature Range .................. –55°C to 125°C Peak Solder Reflow Package Body Temperature  ................................................ 245°C 

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TOP VIEW<br>1 2 3 4 5 6 7<br>VIN<br>A<br>CLKIN NC VD<br>B<br>PGND<br>IMONb IMONa SVIN<br>C<br>PGOOD PGDFB VINREG GND<br>D<br>COMPb COMPa fSET SGND NC<br>E<br>ISETb ISETa EXTVCC RUN<br>F<br>INTVCC<br>G<br>VOSNS SGND SW<br>H<br>TEMP [+] TEMP [–] TEMP [+] TEMP [–]<br>J<br>PGND<br>K<br>VOUT NC<br>L<br>BGA PACKAGE<br>77-PIN (15mm × 9mm × 5.01mm)<br>TJ(MAX) = 125°C; θJA = 15.5°C/W;<br>θJCtop = 20.6°C/W; θJCbot = 5.1°C/W;<br>WEIGHT = 1.8 GRAMS<br>**----- End of picture text -----**<br>


NOTES: 

- 1) θ VALUES ARE DETERMINED BY SIMULATION PER JESD51 CONDITIONS. 2) θJA  VALUE IS OBTAINED WITH DEMO BOARD. 

3) REFER TO APPLICATION INFORMATION SECTION FOR LAB MEASUREMENT AND DERATING INFORMATION. 

## **ORDER INFORMATION** 

|**PART NUMBER**|**PAD OR BALL FINISH**|**PART MARKING***|**PART MARKING***|**PACKAGE**<br>**TYPE**|**MSL**<br>**RATING**|**TEMPERATURE RANGE**<br>**(SEE NOTE 2)**|
|---|---|---|---|---|---|---|
|||**DEVICE**|**FINISH CODE**||||
|LTM4653EY#PBF|SAC305(RoHS)|LTM4653Y|e1|BGA|3|–40°C to 125°C|
|LTM4653IY#PBF|SAC305(RoHS)|LTM4653Y|e1|BGA|3|–40°C to 125°C|
|LTM4653IY|SnPb(63/37)|LTM4653Y|e0|BGA|3|–40°C to 125°C|



- Contact the factory for parts specified with wider operating temperature ranges. *Pad or ball finish code is per IPC/JEDEC J-STD-609. 

- Recommended LGA and BGA PCB Assembly and Manufacturing Procedures 

- LGA and BGA Package and Tray Drawings 

For more information on lead free part marking, go to: http://www.adi.com/ leadfree/ 

- For more information on tape and reel specifications, go to: http://www.adi. com/tapeandreel/ 

Rev. B 

2 

For more information LTM4653 

LTM4653 

## **ELECTRICAL CHARACTERISTICS** 

**The** l **denotes the specifications which apply over the specified internal operating temperature range (Note 2). TA = 25°C, Test Circuit, VIN = SVIN = 48V, EXTVCC = 24V, RUN = 3.3V, RISET = 480k, RfSET = 57.6k, fSW = 1.5MHz (CLKIN driven with 1.2MHz clock signal), unless otherwise noted.** 

|**SYMBOL**|**PARAMETER**|**CONDITIONS**||**MIN**|**TYP**|**MAX**|**UNITS**|
|---|---|---|---|---|---|---|---|
|SVIN(DC), VIN(DC)|Input DC Voltage||l|3.1||58|V|
|VOUT(RANGE)|Range of Output Voltage Regulation|0.5V ≤ ISETa to SGND ≤ 0.94VIN, IOUT= 0A(See Note 6)|l|0.5||0.94VIN|V|
|VOUT(24VDC)|Output Voltage Total Variation with<br>Line and Load at VOUT= 24V|28V ≤ VIN≤ 58V, 0A ≤ IOUT≤ 4A, CINH= 4.7μF,<br>CD= 4.7μF, COUTH= 47μF ×2, CLKIN driven with|l|23.6|24|24.4|V|
|||1.5MHz Clock||||||
|VOUT(0.5VDC)|Output Voltage Total Variation with<br>Line and Load at VOUT= 0.5V|Measuring VOSNSto ISETa<br>3.1V ≤ VIN≤ 13.2V, 0A ≤ IOUT≤ 4A, CINH= 4.7μF,|l|–15|0|15|mV|
|||CD= 4.7μF, COUTH= 47μF ×2, ISETa = 500mV,||||||
|||RfSET= N/U(Note 5)||||||
|**Input Specifications**||||||||
|VIN(UVLO)|SVINUndervoltage Lockout Threshold|SVINRising<br>SVINFalling|l<br>l|2.4|2.85<br>2.6|<br>3.1<br>2.9|V<br>V|
|||Hysteresis|l|150|250||mV|
|VIN(OVLO)|SVINOvervoltage Lockout Rising|(Note 4)||64|68||V|
|VIN(HYS)|SVINOvervoltage Lockout Hysteresis|(Note 4)|||2|4|V|
|IINRUSH(VIN)|Input Inrush Current at Start-Up|CINH= 4.7μF, CD= 4.7μF, COUTH= 47μF ×2; IOUT= 0A,<br>ISETa Electrically Connected to ISETb|||300||mA|
|IQ(SVIN)|Input Supply Bias Current|Shutdown, RUN = GND<br>RUN = VIN|||16<br>450|30|μA<br>μA|
|IS(VIN,FCM)|Input Supply Current|CLKIN Open Circuit, IOUT= 4A|||2.1||A|
|IS(VIN,SHUTDOWN)|Input Supply Current in Shutdown|Shutdown, RUN = GND|||4||µA|
|**Output Specifications**||||||||
|IOUT|VOUTOutput Continuous Current Range|(Note 3)||0||4|A|
|∆VOUT(LINE)/VOUT|Line Regulation Accuracy|IOUT= 0A, 28V ≤ VIN≤58V|l||0.05|0.1|%|
|∆VOUT(LOAD)/VOUT|Load Regulation Accuracy|VIN= 48V, 0A ≤ IOUT≤ 4A|l||0.05|0.75|%|
|VOUT(AC)|Output Voltage Ripple, VOUT|VIN= 12V, ISETa = 5V|||2||mVP-P|
|fs|VOUTRipple Frequency|ISETa = 5V, RfSET= 57.6k, CLKIN Open Circuit|l|1.7|1.95|2.2|MHz|
|∆VOUT(START)|Turn-On Overshoot||||8||mV|
|tSTART|Turn-On Start-Up Time|Delay Measured from VINToggling from 0V to 48V to|l||4|9|ms|
|||PGOOD Exceeding 3V; PGOOD Having a 100k Pull-Up||||||
|||to 3.3V, VPGFB Resistor-Divider Network as Shown in||||||
|||Test Circuit, RISETa= 480k, ISETa Electrically Connected||||||
|||to ISETb and CLKIN Driven with 1.5MHz Clock||||||
|∆VOUT(LS)|Peak Output Voltage Deviation for<br>Dynamic Load Step|IOUT: 0A to 2A and 2A to 0A Load Steps in 1μs,<br>COUTH= 47µF ×2|||400||mV|
|tSETTLE|Settling Time for Dynamic Load Step|IOUT: 0A to 2A and 2A to 0A Load Steps in 1μs,|||50||µs|
|||COUTH= 47µF ×2||||||
|IOUT(OCL)|IOUTOutput Current Limit||||5.5||A|
|**Control Section**||||||||
|IISETa|Reference Current of ISETa Pin|VISETa= 0.5V, 3.1V ≤ VIN≤ 13.2V|l|49.3|50|50.7|µA|
|||VISETa= 24V, 28V ≤ VIN≤ 58V|l|49|50|51|µA|
|IVOSNS|VOSNSLeakage Current|VIN= SVIN= RUN = ISETa = 58V|||600||µA|
|tON(MIN)|Minimum On-Time|(Note 4)|||60||ns|



Rev. B 

3 

For more information LTM4653 

## LTM4653 

## **ELECTRICAL CHARACTERISTICS** 

**The** l **denotes the specifications which apply over the specified internal operating temperature range (Note 2). TA = 25°C, Test Circuit, VIN = SVIN = 48V, EXTVCC = 24V, RUN = 3.3V, RISET = 480k, RfSET = 57.6k, fSW = 1.5MHz (CLKIN driven with 1.2MHz clock signal), unless otherwise noted.** 

|**SYMBOL**|**PARAMETER**|**CONDITIONS**||**MIN**|**TYP**|**MAX**|**UNITS**|
|---|---|---|---|---|---|---|---|
|VRUN|RUN Turn-On/-Off Thresholds|RUN Input Turn-On Threshold, RUN Rising|l|1.08|1.2|1.32|V|
|||RUN Hysteresis|||130||mV|
|IRUN|RUN Leakage Current|RUN = 3.3V|l||0.1|50|nA|
|**Oscillator and Phase-Locked Loop (PLL)**||||||||
|fOSC|Oscillator Frequency Accuracy|VIN= 12V, ISETa = 5V, and:||||||
|||fSETOpen Circuit|l|360|400|440|kHz|
|||RfSET= 57.6k(See fsSpecification)|||1.95||MHz|
|fSYNC|PLL Synchronization Capture Range|VIN= 12V, ISETa = 5V, CLKIN Driven with a GND-||||||
|||Referred Clock Toggling from 0.4V to 1.2V and Having||||||
|||a Clock Duty Cycle:||||||
|||From 10% to 90%; fSETOpen Circuit||250||550|kHz|
|||From 40% to 60%; RfSET= 57.6k||1.3||3|MHz|
|VCLKIN|CLKIN Input Threshold|VCLKINRising||1.2|||V|
|||VCLKINFalling||||0.4|V|
|ICLKIN|CLKIN Input Current|VCLKIN= 5V|||230|500|μA|
|||VCLKIN= 0V||–20|–5||μA|
|**Power Good Feedback Input and Power Good Output**||||||||
|OVPGDFB|Output Overvoltage PGOOD Upper|PGDFB Rising|l|620|645|675|mV|
||Threshold|||||||
|UVPGDFB|Output Undervoltage PGOOD Lower|PGDFB Falling|l|525|555|580|mV|
||Threshold|||||||
|∆VPGDFB|PGOOD Hysteresis|PGDFB Returning|||8||mV|
|RPGDFB|Resistor Between PGDFB and SGND|||4.94|4.99|5.04|kΩ|
|RPGOOD|PGOOD Pull-Down Resistance|VPGOOD= 0.1V, VPGDFB< UVPGDFBor|||700|1500|Ω|
|||VPGDFB> OVPGDFB||||||
|IPGOOD(LEAK)|PGOOD Leakage Current|VPGOOD= 3.3V, UVPGDFB< VPGDFB< OVPGDFB|||0.1|1|μA|
|tPGOOD(DELAY)|PGOOD Delay|PGOOD Low to High (Note 4)<br>PGOOD High to Low(Note 4)|||16/fSW(Hz)<br>64/fSW(Hz)||s<br>s|
|**Current Monitor and Input Voltage Regulation Pins**||||||||
|hIMONa|IOUT/IIMONa|Ratio of VOUTOutput Current to IIMONaCurrent, IOUT= 4A|l|36|40|44|k|
|IOS(IMON)|IMONaOffset Current|IIMONaat IOUT= 0A||–5||5|µA|
|IMONbResistor|Resistor Between IMONband SGND|||9.8|10|10.2|kΩ|
|VIMONa|IMONaServo Voltage|IMONa Voltage During Output Current Regulation|l|1.9|2.0|2.1|V|
|VVINREG|VINREG Servo Voltage|VINREG Voltage During Output Current Regulation|l|1.8|2.0|2.2|V|
|IVINREG|VINREG Leakage Current|VINREG = 2V|||1||nA|
|**INTV**CC**Regulator**||||||||
|VINTVCC|Channel Internal VCCVoltage, No|3.6V ≤ SVIN≤ 58V, EXTVCC= Open Circuit||3.15|<br>3.4|3.65|V|
||INTVCCLoading(IINTVCC= 0mA)|5V ≤ SVIN≤ 58V, 3.2V ≤ EXTVCC≤ 26.5V||2.85|3.0|3.15|V|
|VEXTVCC(TH)|EXTVCCSwitchover Voltage|(Note 4)|||3.15||V|
|∆VINTVCC(LOAD)/<br>VINTVCC|INTVCCLoad Regulation|0mA ≤ IINTVCC≤ 30mA||–2|0.5|2|%|



Rev. B 

4 

For more information LTM4653 

LTM4653 

## **ELECTRICAL CHARACTERISTICS** 

**The** l **denotes the specifications which apply over the specified internal operating temperature range (Note 2). TA = 25°C, Test Circuit, VIN = SVIN = 48V, EXTVCC = 24V, RUN = 3.3V, RISET = 480k, RfSET = 57.6k, fSW = 1.5MHz (CLKIN driven with 1.2MHz clock signal), unless otherwise noted.** 

|**SYMBOL**|**PARAMETER**|**CONDITIONS**|**CONDITIONS**|**MIN**<br>**TYP**<br>**MAX**|**UNITS**|
|---|---|---|---|---|---|
|**Temperature Sensor**||||||
|∆VTEMP|Temperature Sensor Forward Voltage,<br>VTEMP+to VTEMP–|ITEMP+= 100µA and ITEMP–= –100μA at TA= 25°C||0.6|V|
|TC∆V(TEMP)|∆VTEMPTemperature Coefficient|||–2.0|mV/°C|



**Note 1:** Stresses beyond those listing under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating conditions for extended periods may affect device reliability and lifetime. 

**Note 2:** The LTM4653 is tested under pulsed load conditions such that TJ ≈ TA. The LTM4653E is guaranteed to meet performance specifications over the 0°C to 125°C internal operating temperature range. Specifications over the full –40°C to 125°C internal operating temperature range are assured by design, characterization and correlation with statistical process controls. The LTM4653I is guaranteed to meet specifications over the full internal operating temperature range. Note that the maximum ambient temperature consistent with these specifications is determined by specific operating conditions in conjunction with board layout, the rated package thermal resistance and other environmental factors. 

**Note 3:** See output current derating curves for different VIN, VOUT, and TA, located in the Applications Information section. 

**Note 4:** Minimum on-time, VIN Overvoltage Lockout and Overvoltage Lockout Hysteresis, and EXTVCC Switchover Threshold are tested at wafer sort. 

**Note 5:** To ensure minimum on time criteria is met, VOUT(0.5VDC) high-line regulation is tested at 13.2VIN with fSET and CLKIN open circuit. See the Applications Information section. 

**Note 6:** See Applications Information Section for Dropout Criteria. 

**Note 7:** This IC includes overtemperature protection that is intended to protect the device during momentary overload conditions. Junction temperature will exceed 125°C when overtemperature protection is active. Continuous operation above the specified maximum operating junction temperature may impair device reliability. 

**Note 8:** The INTVCC Abs Max peak output current is specified as the sum of current drawn by circuits internal to the module biased off of INTVCC and current drawn by external circuits biased off of INTVCC. See the Applications Information section. 

Rev. B 

5 

For more information LTM4653 

## LTM4653 

## **TYPICAL PERFORMANCE CHARACTERISTICS** 

## **TA = 25°C, unless otherwise noted.** 

**==> picture [526 x 607] intentionally omitted <==**

**----- Start of picture text -----**<br>
Efficiency vs Load Current at Efficiency vs Load Current at Efficiency vs Load Current at<br>5VIN, Forced Continuous Mode 12VIN, Forced Continuous Mode 15VIN, Forced Continuous Mode<br>95  95  100<br>> 95  To<br>90  90<br>BoA 23a —<br>a Z: ie 90  ieee ee<br>85  oRosNS 85  a == eff<br>er ma sss NX ~“\ a - + ee: . ~ sO 85  V 407 1 ~<br>80  80  80<br>\<br>75  3.3VOUT, 400kHz i} ma _ . 75  75  12VOUT, 500kHz _<br>———= 2.5V1.8VOUTOUT, 400kHz, 400kHz ff —— 5V3.3VOUTOU, 400kHzT, 400kHz : 70  5V3.3V OUT OUT, 450kHz, 400kHz<br>70  1.5V 1.2V OUT OUT , 400kHz , 400kHz 70  2.5V 1.8VOUTOUT , 400kHz , 400kHz 1.2VOUT, 400kHz 65  2.5V 1.8V OUTOUT, 400kHz , 400kHz 1.2V OUT , 400kHz<br>65  1VOUT, 400kHz 65  1.5VOUT, 400kHz 1VOUT, 400kHz 60  1.5VOUT, 400kHz 1VOUT, 400kHz<br>0.5  1.0  1.5  2.0  2.5  3.0  3.5  4.0  0.5  1.0  1.5  2.0  2.5  3.0  3.5  4.0  0.5  1.0  1.5  2.0  2.5  3.0  3.5  4.0<br>LOAD CURRENT (A)  4653 G01 LOAD CURRENT (A)  4653 G02 LOAD CURRENT (A)  4653 G03<br>Efficiency vs Load Current at Efficiency vs Load Current at Efficiency vs Load Current at<br>24VIN, Forced Continuous Mode 36VIN, Forced Continuous Mode 48VIN, Forced Continuous Mode<br>100  100  95<br>95  PTTttTT 95  PT| TT tT TT 90  == =<br>jt} |<br>90  p~{--t--|-- 90  et<br>85<br>85  Se ee es eeejfee OT 85  YeeVoce aia nia i Zee inne oe<br>80  7 aa 80  80  (Aee ee<br>ec ol i<br>75  75  75<br>70  I] | 70  EAL | Ps am 24VOUT, 1.5MHz<br>15VOUT, 750kHz 70  15V OUT , 1.4MHz<br>65  vam 12V OUT , 800kHz 1.8V r= OUT , 400kHz 65  24VOUT, 1.2MHz 3.3VOUT, 400kHz | | 12VOUT, 1.2MHz<br>5VOUT, 550kHz 1.5VOUT, 400kHz 15VOUT, 1.2MHz 2.5VOUT, 400kHz 65  5VOUT, 600kHz<br>60  3.3V OUT , 400kHz 1.2V OUT , 400kHz 60  12V OUT , 1.1MHz 1.8V OUT , 400kHz 3.3V OUT , 400kHz<br>2.5VOUT, 400kHz 1VOUT, 400kHz 5VOUT, 575kHz 1.5VOUT, 400kHz 2.5VOUT, 400kHz<br>55  55  60<br>0.5  1.0  1.5  2.0  2.5  3.0  3.5  4.0  0.5  1.0  1.5  2.0  2.5  3.0  3.5  4.0  0.5  1.0  1.5  2.0  2.5  3.0  3.5  4.0<br>LOAD CURRENT (A)  4653 G04 LOAD CURRENT (A)  4653 G05 LOAD CURRENT (A)  4653 G06<br>3.3V Transient Response, 48VIN 12V Transient Response, 48VIN 1V Transient Response, 24VIN<br>VOUT VOUT VOUT<br>50mV/DIV 100mV/DIV 50mV/DIV<br>AC-COUPLED AC-COUPLED AC-COUPLED<br>IOUT IOUT IOUT<br>2A/DIV 2A/DIV 2A/DIV<br>a<br>4653 G07 4653 G08 4653 G09<br>40µs/DIV 40µs/DIV 40µs/DIV<br>FIGURE 32 CIRCUIT, 48VIN, FIGURE 32 CIRCUIT, 48VIN, FIGURE 32 CIRCUIT, 24VIN,<br>CINH = CD = 4.7µF, COUT = 100µF ×2, CINH = CD = 4.7µF, COUT = 22µF ×2, CINH = CD = 4.7µF, COUT = 100µF ×3,<br>RfSET = N/A, RISET = 66.5k, RfSET = 124k, RISET = 240k, RfSET = N/A, RISET = 20k,<br>CTH = 10nF, RTH = 604Ω, CTH = 10nF, RTH = 562Ω, CTH = 6.8nF, RTH = 681Ω,<br>REXTVCC = N/A, CEXTVCC = N/A, REXTVCC = 49.9Ω, CEXTVCC = 1µF, REXTVCC = N/A, CEXTVCC = N/A,<br>2A TO 4A LOAD STEP AT 2A/µs 2A TO 4A LOAD STEP AT 2A/µs 2A TO 4A LOAD STEP AT 2A/µs<br>EFFICIENCY (%)  EFFICIENCY (%)<br>EFFICIENCY (%)<br>EFFICIENCY (%)  EFFICIENCY (%)<br>EFFICIENCY (%)<br>**----- End of picture text -----**<br>


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Rev. B<br>**----- End of picture text -----**<br>


6 

For more information LTM4653 

LTM4653 

## **TYPICAL PERFORMANCE CHARACTERISTICS** 

**TA = 25°C, unless otherwise noted.** 

## **Start-Up, No Load** 

## **Start-Up, 4A Load** 

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RUN RUN<br>2V/DIV 2V/DIV<br>VOUT VOUT<br>5V/DIV 5V/DIV<br>PGOOD PGOOD<br>2V/DIV 2V/DIV<br>4653 G10 4653 G11<br>2ms/DIV 2ms/DIV<br>FIGURE 32 CIRCUIT, 48VIN, FIGURE 32 CIRCUIT, 48VIN,<br>CINH = CD = 4.7µF, COUT = 22µF ×2, CINH = CD = 4.7µF, COUT = 22µF ×2,<br>RfSET = 124k, RISET = 240k, RfSET = 124k, RISET = 240k,<br>RPGDFB = 95.3k, RPGDFB = 95.3k,<br>CTH = 10nF, RTH = 562Ω, CTH = 10nF, RTH = 562Ω,<br>REXTVCC = 49.9Ω, CEXTVCC = 1µF, REXTVCC = 49.9Ω, CEXTVCC = 1µF,<br>NO LOAD 3Ω RESISTIVE LOAD<br>**----- End of picture text -----**<br>


## **Start-Up, Pre-Bias** 

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RUN<br>2V/DIV<br>VOUT<br>5V/DIV<br>IDIODE<br>1mA/DIV<br>PGOOD<br>2V/DIV<br>4653 G12<br>2ms/DIV<br>FIGURE 32 CIRCUIT, 48VIN,<br>CINH = CD = 4.7µF, COUT = 22µF ×2,<br>RfSET = 124k, RISET = 240k,<br>RPGDFB = 95.3k,<br>CTH = 10nF, RTH = 562Ω,<br>REXTVCC = 49.9Ω, CEXTVCC = 1µF,<br>VOUT PRE-BIASED TO 5V<br>THROUGH 1N4148 DIODE<br>**----- End of picture text -----**<br>


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VOUT<br>5V/DIV<br>IIN<br>1A/DIV<br>**----- End of picture text -----**<br>


## **Short-Circuit, No Load** 

**==> picture [352 x 208] intentionally omitted <==**

**----- Start of picture text -----**<br>
Short-Circuit, No Load Short-Circuit, 4A Load<br>VOUT<br>5V/DIV<br>IIN<br>1A/DIV<br><=<br>4653 G13 4653 G14<br>10µs/DIV 10µs/DIV<br>FIGURE 32 CIRCUIT, 48VIN, FIGURE 32 CIRCUIT, 48VIN,<br>CINH = CD = 4.7µF, COUT = 22µF ×2, CINH = CD = 4.7µF, COUT = 22µF ×2,<br>RfSET = 124k, RISET = 240k, RfSET = 124k, RISET = 240k,<br>RPGDFB = 95.3k, RPGDFB = 95.3k,<br>CTH = 10nF, RTH = 562Ω, CTH = 10nF, RTH = 562Ω,<br>REXTVCC = 49.9Ω, CEXTVCC = 1µF, REXTVCC = 49.9Ω, CEXTVCC = 1µF,<br>NO LOAD PRIOR TO APPLICATION 3Ω RESISTIVE LOAD PRIOR TO<br>OF OUTPUT SHORT-CIRCUIT APPLICATION OF OUTPUT<br>SHORT-CIRCUIT<br>**----- End of picture text -----**<br>


Rev. B 

7 

For more information LTM4653 

LTM4653 

## **PIN FUNCTIONS** 

## **PACKAGE ROW AND COLUMN LABELING MAY VARY AMONG µModule PRODUCTS. REVIEW EACH PACKAGE LAYOUT CAREFULLY.** 

**VIN (A1–A3, B3):** Power Input Pins. Apply input voltage and input decoupling capacitance directly between VIN and a ground (PGND) plane. 

**VD (A4, B4, C4):** Drain of the Converter’s Primary Switching MOSFET. Apply at minimum one 4.7µF high frequency ceramic decoupling capacitor directly from VD to PGND. Give this capacitor higher layout priority (closer proximity to the module) than any VIN decoupling capacitors. 

**PGND (A5, B5, C5, D5, E5, F5, G4-5, H3, H5, J3-J5, K4-K5, L4-L5):** Power Ground Pins of the LTM4653. Connect all pins to the application’s PGND plane. 

**NC (A6-A7, B2, B6-B7, C6-C7, D6-D7, E6-E7, F6-F7, G6-G7, H6-H7, K6-K7, L6-L7):** No connect pins, i.e., pins with no internal connection. The NC pins predominantly serve to provide improved mounting of the module to the board. In one’s layout, NC pins are permitted to remain electrically unconnected or can be connected as desired, e.g., connected to a GND plane for heat-spreading purposes and/or to facilitate routing. 

**CLKIN (B1):** Mode Select and Oscillator Synchronization Input. Leave CLKIN open circuit for forced continuous mode operation. Alternatively, this pin can be driven to synchronize the switching frequency of the LTM4653 to a clock signal. In this condition, the LTM4653 operates in forced continuous mode and the cycle-by-cycle turnon of the primary power MOSFET MT is coincident with the rising edge of the clock applied to CLKIN. Note the synchronization range of CLKIN is approximately ±40% of the oscillator frequency programmed by the fSET pin. (See the Applications Information section.) 

**IMONb (C1):** Power Inductor Analog Indicator Current Default Termination R-C Network. A 10k resistor in parallel with a 10nF capacitor and terminating to SGND connect to this pin. Connect IMONb to IMONa to achieve default power inductor analog indicator current characteristics: 1V at full-scale (4A) load current. (See IMONa.) 

**IMONa (C2):** Power Inductor Current Analog Indicator Pin and Current Limit Programming Pin. The current flowing out of this pin is equal to 1/40,000 of the average power inductor current. To construct a voltage (VIMONa) that is proportional to the power inductor current, optionally apply a parallel resistor-capacitor network to this pin and terminate it to SGND. 

IMONa can be connected to IMONb if the default resistor-capacitor termination network provided by IMONb is desired: 1V at full-scale (4A) load current. (See IMONb.) If this analog indicator feature is not desired, connect IMONa to SGND. 

If IMONa ever exceeds a trip threshold of approximately 2V, an IMON control loop servos VOUT to decrease power inductor current and thus regulate IMONa at 2V. In this manner, the average current limit inception threshold of the LTM4653 can be configured. (See the Applications Information section.) 

**SVIN (C3):** Input Voltage Supply for Small-Signal Circuits. SVIN is the input to the INTVCC LDO. Connect SVIN directly to VIN. No decoupling capacitor is needed on this pin. 

**PGOOD (D1):** Power Good Indicator, Open-Drain Output Pin. PGOOD is high impedance when PGDFB is within approximately ±7.5% of 0.6V. PGOOD is pulled to GND when PGDFB is outside this range. 

**PGDFB (D2):** Power Good Feedback Programming Pin. Connect PGDFB to VOSNS through a resistor, RPGDFB. RPGDFB configures the voltage threshold of VOUT for which PGOOD toggles its state. If the PGOOD feature is used, set RPGDFB to: 

**==> picture [137 x 28] intentionally omitted <==**

otherwise, leave PGDFB open circuit. 

A small filter capacitor (220pF) internal to the LTM4653 on this pin provides high frequency noise immunity for the PGOOD output indicator. 

Rev. B 

8 

For more information LTM4653 

LTM4653 

## **PIN FUNCTIONS** 

**VINREG (D3):** Input Voltage Regulation Programming Pin. Optionally connect this pin to the midpoint node formed by a resistor-divider between VD and SGND. When the voltage on VINREG falls below approximately 2V, a VINREG control loop servos VOUT to decrease the power inductor current and thus regulate VINREG at 2V. (See the Applications Information section.) 

If this input voltage regulation feature is not desired, connect VINREG to INTVCC. 

**GND (D4):** Ground Pin of the LTM4653. Electrically connect to the application’s PGND plane. 

**COMPb (E1):** Internal Loop Compensation Network. For most applications, the internal, default loop compensation of the LTM4653 is suitable to apply “as is”, and yields very satisfactory results: apply the default loop compensation to the control loop by simply connecting COMPa to COMPb. When more specialized applications require a personal touch to the optimization of control loop response, this can be accomplished by connecting a series resistor-capacitor network from COMPa to SGND— and leaving COMPb open circuit. 

**COMPa (E2):** Current Control Threshold and Error Amplifier Compensation Node. The trip threshold of LTM4653’s current comparator increases with a corresponding rise in COMPa voltage. A small filter cap (10pF) internal to the LTM4653 on this pin introduces a highfrequency roll-off of the error-amplifier response, yielding good noise rejection in the control-loop. COMPa is often electrically connected to COMPb in one’s application, thus applying default loop compensation. Loop compensation (a series resistor-capacitor) can be applied externally to COMPa if desired or needed, instead. (See COMPb.) 

**fSET (E3):** Oscillator Frequency Programming Pin. The default switching frequency of the LTM4653 is 400kHz. Often, it is necessary to increase the programmed frequency by connecting a resistor between fSET and SGND. (See the Applications Information section.) Note that the synchronization range of CLKIN is approximately ±40% of the oscillator frequency programmed by the fSET pin. 

**SGND (E4, G2, H2):** Signal Ground Pins of the LTM4653. Connect Pin H2 to PGND directly under the LTM4653. The SGND pins at locations E4 and G2 are electrically connected to each other internal to the module, and thus it is only necessary to connect one SGND pin to PGND under the module. The remaining SGND pins can be used for redundant connectivity or routed to an ICT test point for design-for-test considerations, as desired. 

**ISETb (F1):** 1.5nF Soft-Start Capacitor. Connect ISETb to ISETa to achieve default soft-start characteristics, if desired. See ISETa. 

**ISETa (F2):** Accurate 50μA Current Source. Positive input to the error amplifier. Connect a resistor (RISET) from this pin to SGND to program the desired LTM4653 output voltage, VOUT = RISET • 50μA. A capacitor can be connected from ISETa to SGND to soft-start the output voltage and reduce start-up inrush current. Connect ISETa to ISETb in order to achieve default soft-start, if desired. (See ISETb.) 

In addition, the output of the LTM4653 can track a voltage applied between the ISETa pin and the SGND pins. (See the Applications Information section.) 

**EXTVCC (F3):** External Bias, Auxiliary Input to the INTVCC Regulator. When EXTVCC exceeds 3.2V and SVIN exceeds 5V, the INTVCC LDO derives power from EXTVCC bias instead of the SVIN path. This technique can reduce LDO losses considerably, resulting in a corresponding reduction in module junction temperature. For applications in which 4V ≤ VOUT ≤ 26.5V, connect EXTVCC to VOUT through a resistor. (See the Applications Information section for resistor value.) When taking advantage of this EXTVCC feature, locally decouple EXTVCC to PGND with a 1µF ceramic—otherwise, leave EXTVCC open circuit. 

**RUN (F4):** Run Control Pin. A voltage above 1.2V commands the Module to regulate its output voltage. Undervoltage lockout (UVLO) can be implemented by connecting RUN to the midpoint node formed by a resistor-divider between VIN and GND. RUN features 130mV of hysteresis. See the Applications Information section. 

Rev. B 

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For more information LTM4653 

LTM4653 

## **PIN FUNCTIONS** 

**VOSNS (G1, H1):** Output Voltage Sense and Feedback Signal. Connect VOSNS to VOUT at the point of load (POL). Pins G1 and H1 are electrically connected to each other internal to the module, and thus it is only necessary to connect one VOSNS pin to VOUT at the POL. The remaining VOSNS pin can be used for redundant connectivity or routed to an ICT test point for design-for-test considerations, as desired. 

**INTVCC (G3):** Internal Regulator, 3.3V Nominal Output. Internal control circuits and MOSFET-drivers derive power from INTVCC bias. When operating 3.1V < SVIN ≤ 58V, an LDO generates INTVCC from SVIN when RUN is logic high (RUN > 1.2V). No external decoupling is required. When RUN is logic low (RUN to GND < 1.2V), the INTVCC LDO is off, i.e., INTVCC is unregulated. (Also see EXTVCC.) 

**SW (H4):** Switching Node of Switching Converter Stage. Used for test purposes. May be routed a short distance with a thin trace to a local test point to monitor switching action of the converter, if desired, but do not route near any sensitive signals; otherwise, leave electrically open circuit. 

**TEMP[+] (J1, J6):** Temperature Sensor, Positive Input. Emitter of a 2N3906-genre PNP bipolar junction transistor (BJT). Optionally interface to temperature monitoring circuitry such as LTC[®] 2997, LTC2990, LTC2974 or LTC2975. Otherwise leave electrically open. Pins J1 and J6 are electrically connected together internal to the LTM4653, and thus it is only necessary to connect one TEMP[+] pin to monitoring circuitry. The remaining TEMP[+] pin can be used for redundant connectivity or routed to an ICT test point for design-for-test considerations, as desired. 

**TEMP[–] (J2, J7):** Temperature Sensor, Negative Input. Collector and base of a 2N3906-genre PNP bipolar junction transistor (BJT). Optionally interface to temperature monitoring circuitry such as LTC2997, LTC2990, LTC2974 or LTC2975. Otherwise leave electrically open. Pins J2 and J7 are electrically connected together internal to the LTM4653, and thus it is only necessary to connect one TEMP[–] pin to monitoring circuitry. The remaining TEMP[–] pin can be used for redundant connectivity or routed to an ICT test point for design-for-test considerations, as desired. 

**VOUT (K1–K3, L1–L3):** Power Output Pins of the LTM4653. Connect all pins to the application’s power VOUT plane. Apply the output filter capacitors and the output load between a power VOUT plane and the application’s PGND plane. 

Rev. B 

10 

For more information LTM4653 

LTM4653 

## **SIMPLIFIED BLOCK DIAGRAM** 

**==> picture [340 x 599] intentionally omitted <==**

**----- Start of picture text -----**<br>
*<br>IN<br>OUT LOAD-LOCAL MLCCs (HIGH-FREQUENCY  DECOUPLING)<br>IN V DOWN TO 0.5V UP TO 0.94 • V UP TO 4A<br>V 3.1V TO 58V<br>INL<br>C LOAD<br>+<br>OUTH<br>INH C<br>C -SGND<br>CD 4.7µF COUT Hi-Z WHEN VPGDFB IS WITHIN 0.6V±7.5% RPGDFB<br>+<br>SVIN VIN VD PGND SW VOUT 0.1µF VOSNS PGND SGND PGOOD PGDFB +TEMP –TEMP 4653 BD<br>4µH<br>400nH BEAD (CENTRALLY- LOCATED PNP TEMPERATURE SENSOR)<br>0.1µF<br>T B<br>M M<br>220pF<br>4.99k<br>50µA + –<br>1Ω ERROR PGOOD LOGIC<br>AMPLIFIER<br>GND<br>AND<br>0.1µF TO CURRENT  PWM, AND FET DRIVERS<br>POWER CONTROL ANAOLG CIRCUITS COMPARATORS, 100Ω<br>÷ 40000 – + – + 2V<br>IL  +–<br>COMP  BUFFER<br>10pF 249k<br>10k<br>1.5nF<br>10nF<br>10nF 10k 1µF<br>CC CC<br>RUN CLKIN EXTV ISETa ISETb COMPa COMPb INTV VINREG fSET IMONa IMONb SGND<br>A<br>OUT µ<br> = OFF V 50<br> = ONTYP TYP = ISET 400kHz DEFAULT<br>ISET  R<br>RUN TO GND: >1.2V <1.07V R<br>**----- End of picture text -----**<br>


Rev. B 

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For more information LTM4653 

LTM4653 

## **TEST CIRCUIT** 

**==> picture [341 x 197] intentionally omitted <==**

**----- Start of picture text -----**<br>
28V TO 58VVIN C4.7μFINH VSVININ NC SW VVOSNSOUT RPGDFB COUTH + 24VUP TO 4ACOUTLOUT<br>RUN 196k LOAD 27µF 68µF<br>PGDFB<br>GND<br>SGND<br>CLKIN LTM4653 PGND<br>VD<br>CD INTVCC PGOOD<br>4.7μF×2 VINREG EXTVCC<br>TEMP [+]<br>COMPa<br>CTH TEMP [–]<br>0.1μF COMPb IMONa<br>RTH fSET IMONb<br>499Ω ISETa ISETb<br>4653 TC01<br>RfSET RISET<br>57.6k 480k<br>**----- End of picture text -----**<br>


## **DECOUPLING REQUIREMENTS TA = 25°C. Refer to Test Circuit.** 

|**APPLICATION**|**SYMBOL**|**PARAMETER**|**CONDITIONS**|**MIN**<br>**TYP**<br>**MAX**|**UNITS**|
|---|---|---|---|---|---|
|Test Circuit|CINH, CD|External High Frequency Input Capacitor Requirement,<br>28V ≤ VIN≤ 58V, VOUT = 24V|IOUT= 4A|9.4|µF|
||COUTH|External High Frequency Output Capacitor Requirement,<br>28V ≤ VIN≤ 58V, VOUT= 24V|IOUT= 4A|22|µF|



Rev. B 

12 

For more information LTM4653 

LTM4653 

## **OPERATION** 

## **Power Module Description** 

The LTM4653 is a nonisolated switch mode DC/DC stepdown power supply. It can provide up to 4A output current with a few external input and output capacitors. Set by a single resistor, RISET, the LTM4653 regulates a positive output voltage, VOUT. VOUT can be set to as low as 0.5V to as high as 0.94VIN. The LTM4653 operates from a positive input supply rail, VIN, between 3.1V and 58V. The typical application schematic is shown in Figure 32. 

The LTM4653 contains an integrated constant-frequency current mode regulator, power MOSFETs, power inductor, EMI filter and other supporting discrete components. The nominal switching frequency range is from 400kHz to 3MHz, and the default operating frequency is 400kHz. It can be externally synchronized to a clock, from 250kHz to 3MHz. See the Applications Information section. The LTM4653 supports internal and external control loop compensation. Internal loop compensation is selected by connecting the COMPa and COMPb pins. Using internal loop compensation, the LTM4653 has sufficient stability margins and good transient performance with a wide range of output capacitors—even ceramic-only output capacitors. For external loop compensation, see the Applications Information section. LTpowerCAD[®] is available for transient load step and stability analysis. Input filter and noise cancellation circuitry reduces noise-coupling to the module’s inputs and outputs, ensuring the module’s electromagnetic interference (EMI) meets the limits of EN55022 Class B (see Figure 6 to Figure 8). 

Pulling the RUN pin below 1.2V forces the LTM4653 into a shutdown state. A capacitor can be applied from ISETa to SGND to program the output voltage ramp-rate; or, the default LTM4653 ramp-rate can be set by connecting ISETa to ISETb; or, voltage tracking can be implemented by interfacing rail voltages to the ISETa pin. See the Applications Information section. 

Multiphase operation can be employed by applying an external clock source to the LTM4653’s synchronization input, the CLKIN pin. See the Typical Application section. 

LDO losses within the module are reduced by connecting EXTVCC to VOUT through an RC-filter or by connecting EXTVCC to a suitable voltage source. 

IMONa is an analog output current indicator pin. It sources a current proportional to the LTM4653’s load current. When IMONa is electrically connected to IMONb, the voltage on the IMONa/IMONb node is proportional to load current—with 1V corresponding to 4A load. IMONa can be interfaced to an external parallel-RC network instead of the one provided by IMONb. If IMONa ever exceeds 2V, a servo loop reduces the LTM4653’s output current in order to keep IMONa at or below 2V. Through this servo mechanism, a parallel RC network can be connected to IMONa to implement an average current limit function—if desired. When the feature is not needed, connect IMONa to SGND. 

The LTM4653 also features a spare control pin called VINREG with a 2V servo threshold, which can be used to reduce the input current draw during input line sag (“brownout”) conditions. Connect VINREG to INTVCC when this feature is not needed. 

TEMP[+] and TEMP[–] pins give access to a diode-connected PNP transistor, making it possible to monitor the LTM4653’s internal temperature—if desired. 

External component selection is primarily determined by the maximum load current and output voltage. Refer to Table 7 and the Test Circuit for recommended external component values. 

## **VIN to VOUT Step-Down Ratios** 

There are restrictions on the VIN to VOUT step-down ratio that the LTM4653 can achieve. The maximum duty cycle of the LTM4653 is 96% typical. The VIN to VOUT minimum dropout voltage is a function of load current when operating in high duty cycle applications. As an example, VOUT(24VDC) from the Electrical Characteristics table highlights the LTM4653’s ability to regulate 24VOUT at up to 4A from 28VIN, when running at a switching frequency, fSW, of 1.5MHz. 

At very low duty cycles, the LTM4653’s on-time of MT each switching cycle should be designed to exceed the LTM4653 control loop’s specified minimum on-time of 60ns, tON(MIN), (guardband to 90ns), i.e.: 

**==> picture [71 x 32] intentionally omitted <==**

Rev. B 

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LTM4653 

## **OPERATION** 

where D (unitless) is the duty cycle of MT, given by: 

**==> picture [46 x 31] intentionally omitted <==**

In rare cases where the minimum on-time restriction is violated, the frequency of the LTM4653 automatically and gradually folds back down to approximately one-fifth of its programmed switching frequency to allow VOUT to remain in regulation. See the Frequency Adjustment section. Be reminded of Notes 2, 3 and 5 in the Electrical Characteristics section regarding output current guidelines. 

## **Input Capacitors** 

The LTM4653 achieves low input conducted EMI noise due to tight layout and high-frequency bypassing of MOSFETs MT and MB within the module itself. A small filter inductor (400nH) is integrated in the input line (from VIN to VD), providing further noise attenuation—again, local to the switching MOSFETs. The VD and VIN pins are available for external input capacitors—CD and CINH—to form a high-frequency π filter. As shown in the Simplified Block Diagram, the ceramic capacitor CD on the LTM4653’s VD pins handles the majority of the RMS current into the DC/ DC converter power stage and requires careful selection, for that reason. 

See Figure 6 to Figure 8 for demonstration of LTM4653’s EMI performance, meeting the radiated emissions requirements of EN55022B. 

The input capacitance, CD, is needed to filter the pulsed current drawn by MT. To prevent excessive voltage sag on VD, a low-effective series resistance (low-ESR, such as an X7R ceramic) input capacitor should be used, sized appropriately for the maximum CD RMS ripple current: 

**==> picture [165 x 33] intentionally omitted <==**

where η % is the estimated efficiency of the power module. (See Typical Performance Characteristics graphs.) 

Several capacitors may be paralleled to meet the application’s target size, height, and CD RMS ripple current rating. For lower input voltage applications, sufficient bulk input capacitance is needed to counteract line sag and 

transient effects during output load changes. The bulk capacitor can be a switcher-rated aluminum electrolytic capacitor or a Polymer capacitor. Suggested values for CD and CINH are found in Table 7. 

A final precaution regarding ceramic capacitors concerns the maximum input voltage rating of the LTM4653’s VIN, SVIN, and VD pins. A ceramic input capacitor combined with trace or cable inductance forms a high Q (underdamped) tank circuit. If the LTM4653 circuit is plugged into a live supply, the input voltage can ring to twice its nominal value, possibly exceeding the device’s rating. This situation is easily avoided; see the Hot-Plugging Safely section. 

## **Output Capacitors** 

Output capacitors COUTH and COUTL are applied to VOUT of the LTM4653. Sufficient capacitance and low ESR are called for, to meet the output voltage ripple, loop stability, and transient requirements. COUTL can be a low ESR tantalum or polymer capacitor. COUTH is a ceramic capacitor. The typical output capacitance is 22μF (type X5R material, or better), if ceramic-only output capacitors are used. 

Table 7 shows a matrix of suggested output capacitors optimized for 2A transient step-loads applied at 2A/μs. Additional output filtering may be required by the system designer, if further reduction of output ripple or dynamic transient spike is required. The LTpowerCAD design tool is available for transient and stability analysis. Stability criteria are considered in the Table 7 matrix, and LTpowerCAD is available for stability analysis. Multiphase operation will reduce effective output ripple as a function of the number of phases. ADI Application Note 77 discusses this noise reduction versus output ripple current cancellation, but the output capacitance should be considered carefully as a function of stability and transient response. LTpowerCAD can be used to calculate the output ripple reduction as the number of implemented phases increases by N times. External loop compensation can be applied to COMPa if needed, for transient response optimization. 

## **Forced Continuous Operation** 

Leave the CLKIN pin open circuit to command the LTM4653 for forced continuous operation. In this mode, the control loop is allowed to command the inductor peak current to approximately –1A, allowing for significant 

Rev. B 

14 

For more information LTM4653 

LTM4653 

## **OPERATION** 

negative average current. Clocking the CLKIN pin at a frequency within ±40% of the target switching frequency commanded by the fSET pin synchronizes MT’s turn-on to the rising edge of the CLKIN pin. 

## **Output Voltage Programming, Tracking and Soft-Start** 

The LTM4653 regulates its output voltage, VOUT, according to the differential voltage present across ISETa and SGND. In most applications, the output voltage is set by simply connecting a resistor, RISET, from ISETa to SGND, according to: 

**==> picture [68 x 30] intentionally omitted <==**

Since the LTM4653 control loop servos its output voltage according to the voltage between ISETa and SGND: placing a capacitor, CSS, parallel to RSET configures the ramp-up rate of ISETa and thus VOUT. In the time domain, the output voltage ramp-up after the RUN pin is toggled from low to high (t = 0s) is given by: 

**==> picture [193 x 36] intentionally omitted <==**

The soft-start time, tSS, is defined as the time it takes for VOUT to ramp from 0V to 90% of its final value: 

**==> picture [147 x 13] intentionally omitted <==**

or 

**==> picture [107 x 14] intentionally omitted <==**

A default value of CSS = 1.5nF can be implemented by connecting ISETa to ISETb. For other ramp-up rates, connect an external CSS capacitor parallel to RISET. When starting up into a pre-biased VOUT, the LTM4653 stays in a sleep mode, keeping MT and MB off until VISETa equals VOSNS—after which, the DC/DC converter commences switching action and VOUT is ramped according to the voltage commanded by ISETa. 

Since the LTM4653 control loop servos its VOSNS voltage to match that of ISETa’s, the LTM4653’s output can be configured to track any voltage applied to ISETa, referenced to SGND. 

## **Frequency Adjustment** 

The default switching frequency (fSW) of the LTM4653 is 400kHz. This is suitable for low-VIN (VIN ≤ 5V) applications and low-VOUT (VOUT ≤ 3.3V) applications. For a practical design, the LTM4653’s inductor ripple current (∆IPK-PK) is suggested to be less than ~2APK-PK. Choose fSW according to: 

**==> picture [92 x 30] intentionally omitted <==**

where the value of LTM4653’s power inductor, L, is 4μH. 

To avoid cycle-skipping, impose restrictions on fSW, to ensure minimum on time criteria is met: 

**==> picture [73 x 34] intentionally omitted <==**

The LTM4653’s minimum on-time, tON(MIN), is specified as 60ns. For a practical design, it is recommended to guardband to 90ns. 

To configure the LTM4653 for a higher switching frequency than its default of 400kHz, apply a resistor, RfSET, between the fSET pin and SGND. RfSET is given (in MΩ) by: 

**==> picture [218 x 33] intentionally omitted <==**

The relationship of RfSET to programmed fSW is shown in Figure 1. See Table 7 for recommended fSW and corresponding RfSET values for various combinations of VIN and VOUT. 

**==> picture [161 x 160] intentionally omitted <==**

**----- Start of picture text -----**<br>
10<br>1 RfSET NOT USED<br>0.1<br>10 100 1k 10k<br>RfSET (kΩ)<br>4653 F01<br>PROGRAMMED SWITCHING FREQUENCY (MHz)<br>**----- End of picture text -----**<br>


**Figure 1. Relationship Between RfSET and Target fSW** 

Rev. B 

15 

For more information LTM4653 

LTM4653 

## **APPLICATIONS INFORMATION** 

## **Power Module Protection** 

The LTM4653’s current mode control architecture provides fast cycle-by-cycle current limit in an overcurrent condition, as shown in the Typical Performance Characteristics section. If the output voltage collapses sufficiently due to an overload or short-circuit condition, minimum on-time will be violated and the internal oscillator will then fold-back automatically to one-fifth of the LTM4653’s programmed switching frequency—thereby reducing the output current and affording the load a chance to recover. 

The LTM4653 features input overvoltage shutdown protection: when VIN > 68V, switching action ceases (with 4V of hysteresis)—however, be advised that this protection is only active outside the LTM4653’s safe operating area (see Note 1 and Note 4 of the Electrical Characteristics table). 

The LTM4653 ceases switching action if internal temperatures exceed 165°C. The control IC resumes operation after a 10°C cool-down hysteresis. Note that these typical parameters are based on measurements in a lab oven and are not production tested. This overtemperature protection is intended to protect the device during momentary overload conditions. The maximum rated junction temperature will be exceeded when this overtemperature protection is active. Continuous operation above the specified absolute maximum operating junction temperature may impair device reliability or permanently damage the device. 

The LTM4653 does not feature any specialized output overvoltage protection beyond what is inherent to the control loop’s servo mechanism. 

## **RUN Pin Enable** 

The RUN pin is used to enable the power module or sequence the power module. The threshold is 1.2V. The RUN pin can be used to provide an undervoltage lockout (UVLO) function by connecting a resistor divider from the input supply to the RUN pin, as shown in Figure 2. Undervoltage lockout keeps the LTM4653 in shutdown until the supply input voltage is above a certain voltage 

**==> picture [99 x 83] intentionally omitted <==**

**----- Start of picture text -----**<br>
VSUPPLY<br>RA<br>RUN PIN<br>RB<br>4653 F02<br>**----- End of picture text -----**<br>


**Figure 2. Undervoltage Lockout Resistive Divider** 

programmed by the user. The RUN pin hysteresis voltage prevents noise from falsely tripping UVLO. Resistors are chosen by first selecting RB (refer to Figure 2). Then: 

**==> picture [108 x 30] intentionally omitted <==**

where VIN(ON) is the input voltage at which the undervoltage lockout is overcome and the supply turns on. RA may be replaced with a hardwired connection from VD to RUN. The VIN turn-off voltage, VIN(OFF) is given by: 

**==> picture [256 x 71] intentionally omitted <==**

When RUN is below its threshold, UVLO is engaged, MT and MB are turned off, INTVCC ceases to be regulated, and ISETa is discharged to SGND by internal circuitry. 

## **Loop Compensation** 

External loop compensation may be preferred for some applications and can be implemented easily, as follows: leave COMPb open circuit; connect a series-RC network (RTH and CTH) from COMPa to SGND; in some instances, connect a capacitor (CTHP) from COMPa to SGND (paralleling the RTH-CTH series-RC network). See Table 7 for suggested input and output capacitances for a variety of operating conditions. Additionally, the LTpowerCAD design tool is available for transient and stability analysis. 

Rev. B 

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LTM4653 

## **APPLICATIONS INFORMATION** 

## **Hot-Plugging Safely** 

The small size, robustness and low impedance of ceramic capacitors make them an attractive option for the input bypass capacitors (CD and CINH) of the LTM4653. However, these capacitors can cause problems if the LTM4653 is plugged into a live supply (see Analog Devices Application Note 88 for a complete discussion). The low loss ceramic capacitor combined with stray inductance in series with the power source forms an under damped tank circuit, and the voltage at the VIN pin of the LTM4653 can ring to twice the nominal input voltage, possibly exceeding the LTM4653’s rating and damaging the part. If the input supply is poorly controlled or the user will be plugging the LTM4653 into an energized supply, the input network should be designed to prevent this overshoot by introducing a damping element into the path of current flow. This is often done by adding an inexpensive electrolytic bulk capacitor (CINL) across the input terminals of the LTM4653. The selection criteria for CINL calls for: an ESR high enough to damp the ringing; a capacitance value several times larger than CINH. CINL does not need to be located physically close to the LTM4653; it should be located close to the application board’s input connector, instead. 

or other mechanisms that invoke reverse energy flow in the Figure 3 circuit may need a suitably-rated Zener diode protection clamp, to limit the resulting transient voltage rise on SVIN/VIN and CIN. 

**==> picture [158 x 75] intentionally omitted <==**

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VIN VIN<br>SVIN<br>OPT LTM4653<br>CIN<br>4.7µF<br>4653 F03<br>**----- End of picture text -----**<br>


**Figure 3. Schottky Diode in Series with the Supply** 

**==> picture [165 x 77] intentionally omitted <==**

**----- Start of picture text -----**<br>
VIN VIN VOUT VOUT<br>SVIN<br>CIN LTM4653 COUT<br>4.7µF 47µF<br>4653 F04<br>**----- End of picture text -----**<br>


**Figure 4. Schottky Diode from VOUT to VIN** 

## **INTVCC and EXTVCC Connection** 

## **Input Disconnect/Input Short Considerations** 

If at any point the input supply is removed with the output voltage still held high through its capacitor, power will be drawn from the output capacitor to power the module, until the output voltage drops below the minimum SVIN/ VIN requirements of the module. 

However, if the SVIN/VIN pins are grounded while the output is held high, regardless of the RUN state, parasitic body diodes inside the LTM4653 will pull current from the output through the VOUT pins. Depending on the size of the output capacitor and the resistivity of the short, high currents may flow through the internal body diode, and cause damage to the part. If discharge of SVIN/VIN by the input source is possible, preventative measures should be taken to prevent current flow through the internal body diode. Simple solutions would be placing a Schottky diode in series with the supply (Figure 3), or placing a Schottky diode from VOUT to SVIN/VIN (Figure 4). Applications with loads that experience large load-step release, load dump 

When RUN is logic high, an internal low dropout regulator regulates an internal supply, INTVCC, that powers the control circuitry for driving LTM4653’s internal MOSFETs. INTVCC is regulated at 3.3V. In this manner, the LTM4653’s INTVCC is directly powered from SVIN, by default. The gate driver current through the LDO is about 20mA for a typical 1MHz application. The internal LDO power dissipation can be calculated as: 

**==> picture [199 x 16] intentionally omitted <==**

The LDO draws current off of EXTVCC instead of SVIN when EXTVCC is higher than 3.2V and SVIN is above 5V. For output voltages of 4V and higher, EXTVCC can be connected to VOUT through an RC-filter. When the internal LDO derives power from EXTVCC instead of SVIN, the internal LDO power dissipation is: 

**==> picture [202 x 16] intentionally omitted <==**

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LTM4653 

## **APPLICATIONS INFORMATION** 

The recommended value of the resistor between VOUT and EXTVCC is roughly VOUT • 4Ω/V. This resistor, REXTVCC, must be rated to continually dissipate (0.02A)[²] • REXTVCC. The primary purpose of this resistor is to prevent EXTVCC overstress under a fault condition. For example, when an inductive short-circuit is applied to the module’s output, VOUT may be briefly dragged below PGND—forward biasing the PGND-to-EXTVCC body diode. This resistor limits the magnitude of current flow in EXTVCC. Bypass EXTVCC with 1μF of X5R (or better) MLCC. 

## **Multiphase Operation** 

Multiple LTM4653 devices can be paralleled for higher output current applications. For lowest input and output voltage and current ripples, it is advisable to synchronize paralleled LTM4653s to an external clock (within ±40% of the target switching frequency set by fSET—see Test Circuit 1). See Figure 34 for an example of a synchronizing circuit. 

LTM4653 modules can be paralleled without synchronizing circuits: just be aware that some beat-frequency ripple will be present in the output voltage and reflected input current by virtue of the fact that such modules are not operating at identical, synchronized switching frequencies. 

The LTM4653 device is an inherently current mode controlled device, so parallel modules will have good current sharing’s shown in Figure 35. This helps balance the thermals on the design. 

To parallel LTM4653s, connect the respective COMPa, ISETa, and VOSNS pins of each LTM4653 together to share the current evenly. In addition, tie the respective RUN pins of paralleled LTM4653 devices together, to ensure proper start-up and shutdown behavior. Figure 34 shows a schematic of LTM4653 devices operating in parallel. 

Note that for parallel applications, VOUT can be set by a single, common resistor on the ISETa net: 

**==> picture [82 x 31] intentionally omitted <==**

where N is the number of LTM4653 modules in parallel configuration. 

Depending on the duty cycle of operation, the output voltage ripple achieved by paralleled, synchronized LTM4653 modules may be considerably smaller than what is yielded by a single-phase solution. Application Note 77 provides a detailed explanation of multiphase operation (relevant to parallel LTM4653 applications) pertaining to noise reduction and output and input ripple current cancellation. Regardless of ripple current cancellation, it remains important for the output capacitance of paralleled LTM4653 applications to be designed for loop stability and transient response. LTpowerCAD is available for such analysis. 

Figure 5 illustrates the RMS ripple current reduction as a function of the number of interleaved (paralleled and synchronized) LTM4653 modules—derived from Application Note 77. 

## **Radiated EMI Noise** 

The generation of radiated EMI noise is an inherent disadvantage of switching regulators. Fast switching turnon and turn-off of the power MOSFETs—necessary for achieving high efficiency—create high-frequency (~30MHz+) ∆l/∆t changes within DC/DC converters. This activity tends to be the dominant source of high-frequency EMI radiation in such systems. The high level of device integration within LTM4653—including optimized gatedriver and critical front-end � filter inductor—delivers low radiated EMI noise performance. Figure 6 to Figure 8 show typical examples of LTM4653 meeting the radiated emission limits established by EN55022 Class B. 

## **Thermal Considerations and Output Current Derating** 

The thermal resistances reported in the Pin Configuration section of this data sheet are consistent with those parameters defined by JESD51-12 and are intended for use with finite element analysis (FEA) software modeling tools that leverage the outcome of thermal modeling, simulation, and correlation to hardware evaluation performed on a µModule package mounted to a hardware test board. The motivation for providing these thermal coefficients is found in JESD51-12 (“Guidelines for Reporting and Using Electronic Package Thermal Information”). 

Rev. B 

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LTM4653 

## **APPLICATIONS INFORMATION** 

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**----- Start of picture text -----**<br>
0.60<br>1-PHASE<br>0.55 2-PHASE PEt TTT TT yy yy<br>3-PHASE<br>4-PHASE<br>0.50 6-PHASE PT tT TET Ty Ty TT<br>0.45<br>bet | PN LT<br>0.40 Pie EEN<br>0.35 PALIT<br>0.30 YET iit [tiie] TEE TTT NT<br>0.25 PE iN<br>0.20 Pr T T TPETTLEyeyPac<br>0.15 ttt | | NARI TT et<br>0.10 pis tN |eee<br>0.05 ps BUPAgermany[ets<br>0 PREP [Te] FL FL feos, |<br>0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 0.6 0.65 0.7 0.75 0.8 0.85 0.9<br>DUTY CYCLE 4653 F05<br>DC LOAD CURRENT<br>RMS INPUT RIPPLE CURRENT<br>**----- End of picture text -----**<br>


**Figure 5. Normalized Input RMS Ripple Current vs Duty Cycle for One to Six LTM4653s (Phases)** 

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70 70<br>MEAS DIST 10m MEAS DIST 10m<br>60 SPEC DIST 10m 60 SPEC DIST 10m<br>50 eel 50 eel<br>40 40<br>30 |ee | | ee|| | | {||e|| dT|e hd[| 30 |ee | | eeft|| | tt| |ttht dt<br>20 20<br>ee ce We<br>10 QPK LIMIT 10 QPK LIMIT<br>[1] HORIZONTAL [1] HORIZONTAL<br>0 [2] VERTICAL 0 [2] VERTICAL<br>+ FORMAL + FORMAL<br>–10 pe)ee –10 eeane cen<br>30 130 230 330 430 530 630 730 830 930 1000 30 130 230 330 430 530 630 730 830 930 1000<br>FREQUENCY (MHz) 4653 F06 FREQUENCY (MHz) 4653 F07<br>AMPLITUDE (dBµV/m) AMPLITUDE (dBµV/m)<br>**----- End of picture text -----**<br>


**Figure 6. Radiated Emissions Scan of the LTM4653 Producing 24VOUT at 4A, from 29.5VIN, DC2327A Hardware, fSW = 1.2MHz, Measured in a 10m Chamber, Peak Detect Method** 

**Figure 7. Radiated Emissions Scan of the LTM4653 Producing 24VOUT at 3.5A, from 48VIN, DC2327A Hardware, fSW = 1.2MHz, Measured in a 10m Chamber, Peak Detect Method** 

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70<br>MEAS DIST 10m<br>60 SPEC DIST 10m<br>50 PL TTY pe<br>40<br>pf PT] | | dT |<br>30 a ft ft |<br>20<br>Lf hamneredhantndert<br>10 QPK LIMIT<br>[1] HORIZONTAL<br>0 [2] VERTICAL<br>+ FORMAL<br>–10 PRPS<br>30 130 230 330 430 530 630 730 830 930 1000<br>FREQUENCY (MHz) 4653 F08<br>AMPLITUDE (dBµV/m)<br>**----- End of picture text -----**<br>


**Figure 8. Radiated Emissions Scan of the LTM4653 Producing 12VOUT at 3A, from 58VIN, DC2327A Hardware, fSW = 1.2MHz, Measured in a 10m Chamber, Peak Detect Method** 

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## **APPLICATIONS INFORMATION** 

Many designers may opt to use laboratory equipment and a test vehicle such as the demo board to predict the µModule regulator’s thermal performance in their application at various electrical and environmental operating conditions to compliment any FEA activities. Without FEA software, the thermal resistances reported in the Pin Configuration  section are, in and of themselves, not relevant to providing guidance of thermal performance; instead, the derating curves provided in this data sheet can be used in a manner that yields insight and guidance pertaining to one’s application-usage, and can be adapted to correlate thermal performance to one’s own application. 

The Pin Configuration section gives four thermal coefficients explicitly defined in JESD51-12; these coefficients are quoted or paraphrased below: 

1. θ JA, the thermal resistance from junction to ambient, is the natural convection junction-to-ambient air thermal resistance measured in a one cubic foot sealed enclosure. This environment is sometimes referred to as “still air” although natural convection causes the air to move. This value is determined with the part mounted to a JESD51-9 defined test board, which does not reflect an actual application or viable operating condition. 

2. θ JCbottom, the thermal resistance from junction to the bottom of the product case, is determined with all of the component power dissipation flowing through the bottom of the package. In the typical µModule regulator, 

the bulk of the heat flows out the bottom of the package, but there is always heat flow out into the ambient environment. As a result, this thermal resistance value may be useful for comparing packages but the test conditions don’t generally match the user’s application. 

3. θ JCtop, the thermal resistance from junction to top of the product case, is determined with nearly all of the component power dissipation flowing through the top of the package. As the electrical connections of the typical µModule regulator are on the bottom of the package, it is rare for an application to operate such that most of the heat flows from the junction to the top of the part.  As in the case of θ JCbottom, this value may be useful for comparing packages but the test conditions don’t generally match the user’s application. 

4. θ JB, the thermal resistance from junction to the printed circuit board, is the junction-to-board thermal resistance where almost all of the heat flows through the bottom of the µModule regulator and into the board, and is really the sum of the θ JCbottom and the thermal resistance of the bottom of the part through the solder joints and through a portion of the board. The board temperature is measured a specified distance from the package, using a two sided, two layer board. This board is described in JESD51-9. 

A graphical representation of the aforementioned thermal resistances is given in Figure 9; blue resistances are contained within the µModule regulator, whereas green resistances are external to the µModule package. 

**==> picture [403 x 146] intentionally omitted <==**

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µModule DEVICE θJA JUNCTION-TO-AMBIENT RESISTANCE<br>θJCtop JUNCTION-TO-CASE CASE (TOP)-TO-AMBIENT<br>(TOP) RESISTANCE RESISTANCE<br>JUNCTION AMBIENT<br>θJCbot JUNCTION-TO-CASE CASE (BOTTOM)-TO-BOARD BOARD-TO-AMBIENT<br>(BOTTOM) RESISTANCE RESISTANCE RESISTANCE<br>4653 F09<br>**----- End of picture text -----**<br>


**Figure 9. Graphical Representation of JESD51-12 Thermal Coefficients** 

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LTM4653 

## **APPLICATIONS INFORMATION** 

As a practical matter, it should be clear to the reader that no individual or sub-group of the four thermal resistance parameters defined by JESD51-12 or provided in the Pin Configuration section replicates or conveys normal operating conditions of a µModule regulator. For example, in normal board-mounted applications, never does 100% of the device’s total power loss (heat) thermally conduct exclusively through the top or exclusively through bottom of the µModule package—as the standard defines for θ JCtop and θ JCbottom, respectively. In practice, power loss is thermally dissipated in both directions away from the package—granted, in the absence of a heat sink and airflow, a majority of the heat flow is into the board. 

Within the LTM4653, be aware there are multiple power devices and components dissipating power with a consequence that the thermal resistances relative to different junctions of components or die are not exactly linear with respect to total package power loss. To reconcile this complication without sacrificing modeling simplicity—but also not ignoring practical realities—an approach has been taken using FEA software modeling along with laboratory testing in a controlled-environment chamber to reasonably define and correlate the thermal resistance values supplied in this data sheet: (1) Initially, FEA software is used to accurately build the mechanical geometry of the LTM4653 and the specified PCB with all of the correct material coefficients along with accurate power loss source definitions; (2) this model simulates a softwaredefined JEDEC environment consistent with JESD51-9 and JESD51-12 to predict power loss heat flow and temperature readings at different interfaces that enable the calculation of the JEDEC-defined thermal resistance values; (3) the model and FEA software is used to evaluate the LTM4653 with heat sink and airflow; (4) having solved for and analyzed these thermal resistance values and simulated various operating conditions in the software model, a thorough laboratory evaluation replicates the simulated conditions with thermocouples within a controlled environment chamber while operating the device at the same power loss as that which was simulated. The outcome of this process and due diligence yields the set of derating curves provided in later sections of this data sheet, along with wellcorrelated JESD51-12-defined θ values provided in the Pin Configuration section of this data sheet. 

The 1V, 5V, and 15V and 24V power loss curves in Figure 10, Figure 11 and Figure 12 respectively can be used in coordination with the load current derating curves in Figure 13 to Figure 30 for calculating an approximate θ JA thermal resistance for the LTM4653 with various heat sinking and air flow conditions. These thermal resistances represent demonstrated performance of the LTM4653 on DC2327A hardware; a 4-layer FR4 PCB measuring 99mm × 133mm × 1.6mm using outer and inner copper weights of 2oz and 1oz, respectively. The power loss curves are taken at room temperature, and are increased with multiplicative factors with ambient temperature. These approximate factors are listed in Table 1. (Compute the factor by interpolation, for intermediate temperatures.) The derating curves are plotted with the LTM4653’s output initially sourcing 4A and the ambient temperature at 20°C. The output voltages are 1V, 5V, 15V and 24V. These are chosen to include the lower and higher output voltage ranges for correlating the thermal resistance. In all derating curves, the switching frequency of operation follows guidance provided by Table 7. Thermal models are derived from several temperature measurements in a controlled temperature chamber along with thermal modeling analysis. The junction temperatures are monitored while ambient temperature is increased with and without air flow, and with and without a heat sink attached with thermally conductive adhesive tape. The power loss increase with ambient temperature change is factored into the derating curves. The junctions are maintained at 120°C maximum while lowering output current or power while increasing ambient temperature. The decreased output current decreases the internal module loss as ambient temperature is increased. The monitored junction temperature of 120°C minus the ambient operating temperature specifies how much module temperature rise can be allowed. As an example in Figure 27, the load current is derated to 2.5A at 70°C ambient with 200LFM airflow and no heat sink and the room temperature (25°C) power loss for this 48VIN to 24VOUT at 2.5AOUT condition is 3.9W. A 4.5W loss is calculated by multiplying the 3.9W room temperature loss from the 48VIN to 24VOUT power loss curve at 2.5A (Figure 12) with the 1.15 multiplying factor at 70°C ambient (from Table 1). If the 70°C ambient temperature 

Rev. B 

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LTM4653 

## **APPLICATIONS INFORMATION See Table 1 for fSW and REXTVCC.** 

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3.0 4.0 7.0<br>5.0VOUT, 400kHz 15VOUT, 750kHz 24VOUT, 1.5MHz<br>3.3VOUT, 400kHz 3.5 12VOUT, 800kHz 6.0 15V OUT , 1.4MHz<br>2.5 2.5VOUT, 400kHz 5.0VOUT, 550kHz 12VOUT, 1.2MHz<br>1.8VOUT, 400kHz 3.0 3.3VOUT, 400kHz 5.0VOUT, 600kHz<br>2.0 1.5V 1.2V OUTOUT, 400kHz , 400kHz 2.5 2.5V 1.8V OUT OUT , 400kHz , 400kHz 5.0 3.3V 2.5VOUTOUT , 400kHz , 400kHz<br>1.0VOUT, 400kHz 1.5VOUT, 400kHz 4.0<br>1.5 2.0 1.2VOUT, 400kHz<br>1 . 0V OUT,  400kH z<br>3.0<br>1.5<br>1.0<br>2.0<br>1.0<br>0.5<br>0.5 1.0<br>0.0 0.0 0.0<br>0.0  0.5  1.0  1.5  2.0  2.5  3.0  3.5  4.0  0.0  0.5  1.0  1.5  2.0  2.5  3.0  3.5  4.0  0.0  0.5  1.0  1.5  2.0  2.5  3.0  3.5  4.0<br>OUTPUT CURRENT (A)  4653 F10 OUTPUT CURRENT (A)  4653 F11 OUTPUT CURRENT (A)  4653 F12<br>Figure 10. 12VIN Power Loss Curve Figure 11. 24VIN Power Loss Curve Figure 12. 48VIN Power Loss Curve<br>4.0  4.0  4.0<br>3.5  3.5  3.5<br>3.0  3.0  3.0<br>2.5  2.5  2.5<br>2.0  2.0  2.0<br>1.5  1.5  1.5<br>1.0  1.0  1.0<br>OLFM OLFM OLFM<br>0.5  200LFM 0.5  200LFM 0.5  200LFM<br>400LFM 400LFM 400LFM<br>0.0  0.0  0.0<br>20  40 60 80  100 120 20  40 60 80  100 120 20  40 60 80  100 120<br>AMBIENT TEMPERATURE (°C)  4653 F13 AMBIENT TEMPERATURE (°C)  4653 F14 AMBIENT TEMPERATURE (°C)  4653 F15<br>Figure 13. 5V to 1VOUT Derating  Figure 14. 12V to 1VOUT Figure 15. 24V to 1VOUT<br>Curve, No Heat Sink Derating Curve, No Heat Sink  Derating Curve, No Heat Sink<br>4.0  4.0  4.0<br>3.5  3.5  3.5<br>3.0  3.0  3.0<br>2.5  2.5  2.5<br>2.0  2.0  2.0<br>1.5  1.5  1.5<br>1.0  1.0  1.0<br>OLFM OLFM OLFM<br>0.5  200LFM 0.5  200LFM 0.5  200LFM<br>400LFM 400LFM 400LFM<br>0.0  0.0  0.0<br>20  40 60 80  100 120 20  40 60 80  100 120 20  40 60 80  100 120<br>AMBIENT TEMPERATURE (°C)  4653 F16 AMBIENT TEMPERATURE (°C)  4653 F17 AMBIENT TEMPERATURE (°C)  4653 F18<br>POWER LOSS (W)  POWER LOSS (W)  POWER LOSS (W)<br>MAXIMUM LOAD CURRENT (A)  MAXIMUM LOAD CURRENT (A)  MAXIMUM LOAD CURRENT (A)<br>MAXIMUM LOAD CURRENT (A)  MAXIMUM LOAD CURRENT (A)  MAXIMUM LOAD CURRENT (A)<br>**----- End of picture text -----**<br>


**Figure 16. 5V to 1VOUT Derating Curve with BGA Heat Sink** 

**Figure 17. 12V to 1VOUT Derating Curve with BGA Heat Sink** 

**Figure 18. 24V to 1VOUT Derating Curve with BGA Heat Sink** 

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## **APPLICATIONS INFORMATION See Table 1 for fSW and REXTVCC.** 

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4.0  4.0  4.0<br>3.5  3.5  3.5<br>3.0  3.0  3.0<br>2.5  2.5  2.5<br>2.0  2.0  2.0<br>1.5  1.5  1.5<br>1.0  1.0  1.0<br>OLFM OLFM OLFM<br>0.5  200LFM 0.5  200LFM 0.5  200LFM<br>400LFM 400LFM 400LFM<br>0.0  0.0  0.0<br>20  40 60 80  100 120 20  40 60 80  100 120 20  40 60 80  100 120<br>AMBIENT TEMPERATURE (°C)  4653 F19 AMBIENT TEMPERATURE (°C)  4653 F20 AMBIENT TEMPERATURE (°C)  4653 F21<br>Figure 19. 12V to 5VOUT Figure 20. 24V to 5VOUT Derating  Figure 21. 48V to 5VOUT Derating<br>Derating Curve, No Heat Sink Curve, No Heat Sink Curve, No Heat Sink<br>4.0  4.0  4.0<br>3.5  3.5  3.5<br>3.0  3.0  3.0<br>2.5  2.5  2.5<br>2.0  2.0  2.0<br>1.5  1.5  1.5<br>1.0  1.0  1.0<br>OLFM OLFM OLFM<br>0.5  200LFM 0.5  200LFM 0.5  200LFM<br>400LFM 400LFM 400LFM<br>0.0  0.0  0.0<br>20  40 60 80  100 120 20  40 60 80  100 120 20  40 60 80  100 120<br>AMBIENT TEMPERATURE (°C)  4653 F22 AMBIENT TEMPERATURE (°C)  4653 F23 AMBIENT TEMPERATURE (°C)  4653 F24<br>Figure 22. 12V to 5VOUT Derating  Figure 23. 24V to 5VOUT Derating  Figure 24. 48V to 5VOUT Derating<br>Curve with BGA Heat Sink Curve with BGA Heat Sink  Curve with BGA Heat Sink<br>4.0  4.0  4.0<br>3.5  3.5  3.5<br>3.0  3.0  3.0<br>2.5  2.5  2.5<br>2.0  2.0  2.0<br>1.5  1.5  1.5<br>1.0  1.0  1.0<br>OLFM OLFM OLFM<br>0.5  200LFM 0.5  200LFM 0.5  200LFM<br>400LFM 400LFM 400LFM<br>0.0  0.0  0.0<br>20  40 60 80  100 120 20  40 60 80  100 120 20  40 60 80  100 120<br>AMBIENT TEMPERATURE (°C)  4653 F25 AMBIENT TEMPERATURE (°C)  4653 F26 AMBIENT TEMPERATURE (°C)  4653 F27<br>Figure 25. 24V to 15VOUT Derating  Figure 26. 48V to 15VOUT Derating  Figure 27. 48V to 24VOUT Derating<br>Curve, No Heat Sink Curve, No Heat Sink Curve, No Heat Sink<br>MAXIMUM LOAD CURRENT (A)  MAXIMUM LOAD CURRENT (A)  MAXIMUM LOAD CURRENT (A)<br>MAXIMUM LOAD CURRENT (A)  MAXIMUM LOAD CURRENT (A)  MAXIMUM LOAD CURRENT (A)<br>MAXIMUM LOAD CURRENT (A)  MAXIMUM LOAD CURRENT (A)  MAXIMUM LOAD CURRENT (A)<br>**----- End of picture text -----**<br>


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## **APPLICATIONS INFORMATION See Table 1 for fSW and REXTVCC.** 

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**----- Start of picture text -----**<br>
4.0  4.0  4.0<br>3.5  3.5  3.5<br>3.0  3.0  3.0<br>2.5  2.5  2.5<br>2.0  2.0  2.0<br>1.5  1.5  1.5<br>1.0  1.0  1.0<br>OLFM OLFM OLFM<br>0.5  200LFM 0.5  200LFM 0.5  200LFM<br>400LFM 400LFM 400LFM<br>0.0  0.0  0.0<br>20  40 60 80  100 120 20  40 60 80  100 120 20  40 60 80  100 120<br>AMBIENT TEMPERATURE (°C)  4653 F28 AMBIENT TEMPERATURE (°C)  4653 F29 AMBIENT TEMPERATURE (°C)  4653 F30<br>Figure 28. 24V to 15VOUT Derating OUT Derating  Derating  Figure 29. 48V to 15VOUT Derating  Figure 30. 48V to 24VOUT Derating<br>Curve with BGA Heat Sink Curve with BGA Heat Sink Curve with BGA Heat Sink<br>MAXIMUM LOAD CURRENT (A)  MAXIMUM LOAD CURRENT (A)  MAXIMUM LOAD CURRENT (A)<br>**----- End of picture text -----**<br>


**Figure 28. 24V to 15VOUT Derating OUT Derating  Derating Curve with BGA Heat Sink** 

is subtracted from the 120°C junction temperature, then the difference of 50°C divided by 4.5W yields a thermal resistance, θ JA, of 11.1°C/W—in good agreement with Table 4. Table 2, Table 3 and Table 4 provide equivalent thermal resistances for 1V, 5V and 15V and 24V outputs with and without air flow and heat sinking. The derived thermal resistances in Table 2, Table 3 and Table 4 for the various conditions can be multiplied by the calculated power loss as a function of ambient temperature to derive temperature rise above ambient, thus maximum junction temperature. Room temperature power loss can be derived from the efficiency curves in the Typical Performance Characteristics section and adjusted with ambient temperature multiplicative factors from Table 1. 

**Table 1. Power Loss Multiplicative Factors vs Ambient Temperature** 

|<br>**Temperature**||
|---|---|
|**AMBIENT TEMPERATURE**|**POWER LOSS MULTIPLICATIVE**<br>**FACTOR**|
|Up to 40°C|1.00|
|50°C|1.05|
|60°C|1.10|
|70°C|1.15|
|80°C|1.20|
|90°C|1.25|
|100°C|1.30|
|110°C|1.35|
|120°C|1.40|



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LTM4653 

## **APPLICATIONS INFORMATION** 

## **Table 2. 1V Output** 

|**Table 2. 1V Output**||||||
|---|---|---|---|---|---|
|**DERATING CURVE**|**VIN (V)**|**POWER LOSS CURVE**|**AIRFLOW(LFM)**|**HEAT SINK**|θ**JA (°C/W)**|
|Figure 13,Figure 14,Figure 15|5,12,24|Figure 10,Figure 11|0|None|13.9|
|Figure 13,Figure 14,Figure 15|5,12,24|Figure 10,Figure 11|200|None|11.4|
|Figure 13,Figure 14,Figure 15|5,12,24|Figure 10,Figure 11|400|None|10.7|
|Figure 16,Figure 17,Figure 18|5,12,24|Figure 10,Figure 11|0|BGA Heat Sink|13.3|
|Figure 16,Figure 17,Figure 18|5,12,24|Figure 10,Figure 11|200|BGA Heat Sink|11.0|
|Figure 16,Figure 17,Figure 18|5,12,24|Figure 10,Figure 11|400|BGA Heat Sink|10.3|



**Table 3. 5V Output** 

|**Table 3. 5V Output**||||||
|---|---|---|---|---|---|
|**DERATING CURVE**|**VIN (V)**|**POWER LOSS CURVE**|**AIRFLOW(LFM)**|**HEAT SINK**|θ**JA (°C/W)**|
|Figure 19,Figure 20,Figure 21|12,24,48|Figure 10,Figure 11,Figure 12|0|None|13.9|
|Figure 19,Figure 20,Figure 21|12,24,48|Figure 10,Figure 11,Figure 12|200|None|11.4|
|Figure 19,Figure 20,Figure 21|12,24,48|Figure 10,Figure 11,Figure 12|400|None|10.7|
|Figure 22,Figure 23,Figure 24|12,24,48|Figure 10,Figure 11,Figure 12|0|BGA Heat Sink|13.3|
|Figure 22,Figure 23,Figure 24|12,24,48|Figure 10,Figure 11,Figure 12|200|BGA Heat Sink|11.0|
|Figure 22,Figure 23,Figure 24|12,24,48|Figure 10,Figure 11,Figure 12|400|BGA Heat Sink|10.3|



**Table 4. 15V and 24V Output** 

|**Table 4. 15V and 24V Output**||||||
|---|---|---|---|---|---|
|**DERATING CURVE**|**VIN (V)**|**POWER LOSS CURVE**|**AIRFLOW(LFM)**|**HEAT SINK**|θ**JA (°C/W)**|
|Figure 25,Figure 26,Figure 27|24,48|Figure 11,Figure 12|0|None|13.9|
|Figure 25,Figure 26,Figure 27|24,48|Figure 11,Figure 12|200|None|11.4|
|Figure 25,Figure 26,Figure 27|24,48|Figure 11,Figure 12|400|None|10.7|
|Figure 28,Figure 29,Figure 30|24,48|Figure 11,Figure 12|0|BGA Heat Sink|13.3|
|Figure 28,Figure 29,Figure 30|24,48|Figure 11,Figure 12|200|BGA Heat Sink|11.0|
|Figure 28,Figure 29,Figure 30|24,48|Figure 11,Figure 12|400|BGA Heat Sink|10.3|



**Table 5. Heat Sink Manufacturer (Thermally Conductive Adhesive Tape Pre-Attached)** 

|**HEAT SINK MANUFACTURER**|**PART NUMBER**|**WEBSITE**|
|---|---|---|
|Cool Innovations|3-0504035UT411|www.coolinnovations.com|



**Table 6. Thermally Conductive Adhesive Tape Vendor** 

|**Table 6. Thermally Conductive Adhesive**|**Tape Vendor**||
|---|---|---|
|**THERMALLY CONDUCTIVE ADHESIVE**<br>**TAPE MANUFACTURER**|**PART NUMBER**|**WEBSITE**|
|Chomerics|T411|www.chomerics.com|



Rev. B 

25 

For more information LTM4653 

LTM4653 

## **APPLICATIONS INFORMATION** 

## **Table 7. LTM4653 Output Voltage Response vs Component Matrix. Performance of Figure 32 Circuit with Values Here Indicated. Load-Stepping from 2A to 4A Load Current, at 2A/μs. Typical Measured Values** 

|**COUTH VENDOR **|**PART NUMBER**|**CINH/CD VENDOR**|**PART NUMBER**|
|---|---|---|---|
|AVX|12066D107MAT2A (100μF, 6.3V, 1206 Case Size)<br>1210YD476MAT2A (47μF, 16V, 1210 Case Size)<br>12103D226MAT2A (22μF, 25V, 1210 Case Size)<br>12105D106MAT2A(10μF, 50V, 1210 Case Size)|AVX|12065C475MAT2A (4.7μF, 50V, 1206 Case Size)|
|Murata|GRM31CR60J107M (100μF, 6.3V, 1206 Case Size)<br>GRM32ER61C476M (47μF, 16V, 1210 Case Size)<br>GRM32ER61H106M(10μF, 50V, 1210 Case Size)|Murata|GRM31CR71H475M (4.7μF, 50V, 1206 Case Size)|
|Taiyo Yuden|JMK316BBJ107MLHT (100μF, 6.3V, 1206 Case Size)<br>EMK325BJ476MM (47μF, 16V, 1210 Case Size)<br>TMK325BJ226MM (22μF, 25V, 1210 Case Size)<br>UMK325BJ106M(10μF, 50V, 1210 Case Size)|Taiyo Yuden|UMK316AB7475ML (4.7μF, 50V, 1206 Case Size)|
|TDK|C3216X5R0J107M (100μF, 6.3V, 1206 Case Size)<br>C3225X5R1E226M (22μF, 25V, 1210 Case Size)<br>C3225X5R1H106M(10μF, 50V, 1210 Case Size)|TDK|C3216X5R1H475M (4.7μF, 50V, 1206 Case Size)|



|**VOUT**<br>**(V)**|**VIN**<br>**(V)**|**CINH**<br>**(μF)**|**CD **<br>**(μF)**|**COUTH**<br>**(μF)**|**RTH**<br>**(Ω)**|**CTH**<br>**(nF)**|**RISET**<br>**(kΩ)**|**RPGDFB**<br>**(kΩ)**|**fSW**<br>**(kHz)**|**RfSET**<br>**(kΩ)**|**REXTVCC**<br>**(Ω)**|**LOAD STEP**<br>**TRANSIENT**<br>**DROOP**<br>**(mV)**|**LOAD STEP**<br>**PK-PK**<br>**DEVIATION**<br>**(mV)**|**RECOVERY**<br>**TIME**<br>**(μs)**|
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|1|5|4.7|4.7|100 ×3|681|6.8|20|3.32|400|N/A|N/A|70|145|55|
|1|12|4.7|4.7|100 ×3|681|6.8|20|3.32|400|N/A|N/A|70|145|50|
|1|24|4.7|4.7|100 ×3|681|6.8|20|3.32|400|N/A|N/A|70|145|50|
|1.2|5|4.7|4.7|100 ×3|665|6.8|24|4.99|400|N/A|N/A|70|145|50|
|1.2|12|4.7|4.7|100 ×3|665|6.8|24|4.99|400|N/A|N/A|70|145|50|
|1.2|24|4.7|4.7|100 ×3|665|6.8|24|4.99|400|N/A|N/A|70|145|50|
|1.5|5|4.7|4.7|100 ×3|665|6.8|30.1|7.5|400|N/A|N/A|70|145|50|
|1.5|12|4.7|4.7|100 ×3|665|6.8|30.1|7.5|400|N/A|N/A|70|145|50|
|1.5|24|4.7|4.7|100 ×3|665|6.8|30.1|7.5|400|N/A|N/A|70|145|50|
|1.5|36|4.7|4.7|100 ×3|665|6.8|30.1|7.5|400|N/A|N/A|70|145|50|
|1.8|5|4.7|4.7|100 ×3|665|8.2|36|10|400|N/A|N/A|70|145|50|
|1.8|12|4.7|4.7|100 ×3|665|8.2|36|10|400|N/A|N/A|70|145|50|
|1.8|24|4.7|4.7|100 ×3|665|8.2|36|10|400|N/A|N/A|70|145|50|
|1.8|36|4.7|4.7|100 ×3|665|8.2|36|10|400|N/A|N/A|70|145|50|
|2.5|5|4.7|4.7|100 ×3|649|8.2|50|15.8|400|N/A|N/A|70|145|50|
|2.5|12|4.7|4.7|100 ×3|649|8.2|50|15.8|400|N/A|N/A|70|145|50|
|2.5|24|4.7|4.7|100 ×3|649|8.2|50|15.8|400|N/A|N/A|70|145|50|
|2.5|36|4.7|4.7|100 ×3|649|8.2|50|15.8|400|N/A|N/A|70|145|50|
|2.5|48|4.7|4.7|100 ×3|649|8.2|50|15.8|400|N/A|N/A|70|145|50|
|3.3|5|4.7|4.7|100 ×2|604|10|66.5|22.6|400|N/A|N/A|90|190|50|
|3.3|12|4.7|4.7|100 ×2|604|10|66.5|22.6|400|N/A|N/A|90|190|50|
|3.3|24|4.7|4.7|100 ×2|604|10|66.5|22.6|400|N/A|N/A|90|185|50|
|3.3|36|4.7|4.7|100 ×2|604|10|66.5|22.6|400|N/A|N/A|90|180|50|
|3.3|48|4.7|4.7|100 ×2|604|10|66.5|22.6|400|N/A|N/A|90|180|50|



Rev. B 

26 

For more information LTM4653 

LTM4653 

## **APPLICATIONS INFORMATION** 

**Table 7. LTM4653 Output Voltage Response vs Component Matrix. Performance of Figure 32 Circuit with Values Here Indicated. Load-Stepping from 2A to 4A Load Current, at 2A/μs. Typical Measured Values** 

|**VOUT**<br>**(V)**|**VIN**<br>**(V)**|**CINH**<br>**(μF)**|**CD **<br>**(μF)**|**COUTH**<br>**(μF)**|**RTH**<br>**(Ω)**|**CTH**<br>**(nF)**|**RISET**<br>**(kΩ)**|**RPGDFB**<br>**(kΩ)**|**fSW**<br>**(kHz)**|**RfSET**<br>**(kΩ)**|**REXTVCC**<br>**(Ω)**|**LOAD STEP**<br>**TRANSIENT**<br>**DROOP**<br>**(mV)**|**LOAD STEP**<br>**PK-PK**<br>**DEVIATION**<br>**(mV)**|**RECOVERY**<br>**TIME**<br>**(μs)**|
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|5|12|4.7|4.7|47 ×2|499|10|100|36.5|400|N/A|20|130|260|45|
|5|24|4.7|4.7|47 ×2|499|10|100|36.5|550|665|20|130|260|45|
|5|36|4.7|4.7|47 ×2|499|10|100|36.5|575|576|20|130|260|45|
|5|48|4.7|4.7|47 ×2|499|10|100|36.5|600|499|20|130|260|45|
|12|15|4.7|4.7|22 ×2|499|10|240|95.3|500|1000|49.9|170|350|40|
|12|24|4.7|4.7|22 ×2|499|10|240|95.3|800|249|49.9|170|350|40|
|12|36|4.7|4.7|22 ×2|499|10|240|95.3|1100|143|49.9|170|350|40|
|12|48|4.7|4.7|22 ×2|499|10|240|95.3|1200|124|49.9|170|350|40|
|15|24|4.7|4.7|22 ×2|499|10|301|121|750|287|60.4|170|350|40|
|15|36|4.7|4.7|22 ×2|499|10|301|121|1200|124|60.4|170|350|40|
|15|48|4.7|4.7|22 ×2|499|10|301|121|1400|100|60.4|170|350|40|
|24|36|4.7|4.7|10 ×2|499|10|481|196|1200|124|100|220|430|35|
|24|48|4.7|4.7|10 ×2|499|10|481|196|1500|90.9|100|220|440|35|



## **Safety Considerations** 

The LTM4653 does not provide galvanic isolation from VIN to VOUT. There is no internal fuse. If required, a slow blow fuse with a rating twice the maximum input current needs to be provided to protect the unit from catastrophic failure. 

The fuse or circuit breaker, if used, should be selected to limit the current to the regulator in case of a MT MOSFET fault. If MT fails, the system’s input supply will source very large currents to VOUT through MT. This can cause excessive heat and board damage depending on how much power the input voltage can deliver to this system. A fuse or circuit breaker can be used as a secondary fault protector in this situation. The LTM4653 does feature overcurrent and overtemperature protection. 

## **Layout Checklist/Example** 

The high integration of LTM4653 makes the PCB board layout straightforward. However, to optimize its electrical and thermal performance, some layout considerations are still necessary. 

- Use large PCB copper areas for high current paths, including VIN, PGND and VOUT. Doing so helps to minimize the PCB conduction loss and thermal stress. 

- Place high frequency ceramic input and output capacitors next to the VIN, VD, PGND and VOUT pins to minimize high frequency noise. 

- Place a dedicated power ground layer underneath the LTM4653. 

- To minimize the via conduction loss and reduce module thermal stress, use multiple vias for interconnection between top layer and other power layers. 

- Do not put vias directly on pads, unless they are capped or plated over. 

- Use a separate SGND copper plane for components connected to signal pins. Connect SGND to PGND directly under the module. 

- For parallel module applications, connect the VOUT, VOSNS, RUN, ISETa, COMPa and PGOOD pins together as shown in Figure 34. 

- Bring out test points on the signal pins for monitoring. 

- Figure 31 gives a good example of the recommended LTM4653 layout. 

Rev. B 

27 

For more information LTM4653 

LTM4653 

## **APPLICATIONS INFORMATION** 

**==> picture [277 x 146] intentionally omitted <==**

**----- Start of picture text -----**<br>
GND<br>VIN GND VOUT<br>4653 F31<br>**----- End of picture text -----**<br>


**Figure 31. Recommend PCB Layout, Package Top View** 

## **TYPICAL APPLICATION** 

**==> picture [414 x 187] intentionally omitted <==**

**----- Start of picture text -----**<br>
48VVIN 4.7μFCINH VSVININ NC SW VVOSNSOUT RPGDFB C10µFOUTH UP TO 4A24VOUT,<br>196k LOAD ×2<br>VD PGDFB<br>C4.7μFD RUN SGND INTVCC<br>GND LTM4653 PGND REXTVCC<br>CLKIN RPGDPUP 100Ω 0.1µF<br>100k<br>INTVCC INTVCC PGOOD<br>VINREG TEMP [+] D [+] VCC VREF<br>TEMP [–] 470pF LTC2997<br>C10nFTH COMPaCOMPb EXTVIMONaCC CEXTVCC D [–] GND VPTAT 4mV/K<br>RTH fSET IMONb 1µF<br>499Ω ISETa ISETb<br>4653 F32<br>RfSET RISET OPTIONAL ANALOG OUTPUT<br>90.9k 481k<br>TEMPERATURE INDICATOR<br>**----- End of picture text -----**<br>


**Figure 32. 4A, 24V Output DC/DC μModule Regulator** 

Rev. B 

28 

For more information LTM4653 

LTM4653 

## **TYPICAL APPLICATIONS** 

**==> picture [160 x 89] intentionally omitted <==**

**----- Start of picture text -----**<br>
RUN<br>5V/DIV<br>VOUT<br>10V/DIV<br>PGOOD<br>5V/DIV<br>1ms/DIV 4653 F33<br>**----- End of picture text -----**<br>


**Figure 33. Start-Up Waveforms at 48VIN, Figure 32 Circuit** 

**==> picture [520 x 459] intentionally omitted <==**

**----- Start of picture text -----**<br>
IOUT1<br>48VVIN C4.7μFINH VSVININ NC SW VVOSNSOUT RPGDFB1 C22µF×2OUT UP TO 8A24VOUT<br>VD 196k LOAD<br>CD PGDFB<br>4.7μF RUN SGND<br>GND<br>PGND<br>INTVCC1 CLKIN LTM4653U1 INTVCC1<br>RPGDPUP<br>INTVCC 100k<br>ch<br>VINREG PGOOD PGOOD<br>EXTVCC<br>COMPa TEMP [+] REXTVCC<br>100Ω<br>COMPb TEMP [–] CEXTVCC<br>LTC6908-1 fSET IMONa 1µF ANALOG OUTPUT<br>ISETa ISETb IMONb CURRENT INDICATOR<br>V [+] OUT1<br>RSET R90.9kfSET1 VIMON = 0.125Ω • (IOUT1 + IOUT2)<br>66.5k<br>SET OUT2<br>0.1µF IOUT2<br>GND MOD VIN NC SW VOUT<br>C4.7μFINH SVIN VOSNS RPGDFB2<br>196k<br>VD PGDFB<br>CD RUN SGND<br>4.7μF<br>GND PGND<br>U2<br>LTM4653<br>CLKIN<br>REXTVCC<br>INTVCC 100Ω<br>VINREG PGOOD<br>EXTVCC<br>COMPa<br>CTH TEMP [+] CEXTVCC<br>10nF COMPb TEMP [–] 1µF<br>RTH IMONa<br>499Ω fSET IMONb<br>al ISETa ISETb<br>4653 F34<br>RfSET RISET<br>90.9k 240k<br>Figure 34. 24V Output at Up to 8A from 48V Input, 2-Phase Parallel with Analog Output Current Indicator<br>**----- End of picture text -----**<br>


Rev. B 

29 

For more information LTM4653 

LTM4653 

## **TYPICAL APPLICATIONS** 

**==> picture [161 x 166] intentionally omitted <==**

**----- Start of picture text -----**<br>
5<br>4<br>TOT<br>3<br>A<br>2<br>SEnn7 200<br>1<br>ao7 20000<br>0 Painnnen<br>U1<br>U2<br>–1 i<br>0  1  2  3  4  5  6  7  8<br>TOTAL OUTPUT CURRENT (A)  4653 F35<br>MODULE OUTPUT CURRENT (A)<br>**----- End of picture text -----**<br>


**Figure 35. Current Sharing Performance of LTM4653s in Figure 34 Circuit** 

**==> picture [158 x 94] intentionally omitted <==**

**----- Start of picture text -----**<br>
RUN<br>5V/DIV<br>VOUT<br>5V/DIV<br>FEE<br>VOUT [–]<br>5V/DIV<br>PGOOD<br>5V/DIV eat<br>2ms/DIV 4653 F36<br>**----- End of picture text -----**<br>


**Figure 36. Concurrent ±12V Supply, Output Voltage Start-Up Waveforms, Figure 37 Circuit** 

Rev. B 

30 

For more information LTM4653 

LTM4653 

## **PACKAGE PHOTOS** 

**Part marking is either ink mark or laser mark** 

## **PACKAGE DESCRIPTION** 

**Please refer to http://www.adi.com/designtools/packaging/ for the most recent package drawings.** 

**Table 8. LTM4653 Component BGA Pinout** 

**==> picture [506 x 250] intentionally omitted <==**

**----- Start of picture text -----**<br>
|||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|
|PIN ID|FUNCTION|PIN ID|FUNCTION|PIN ID|FUNCTION|PIN ID|FUNCTION|PIN ID|FUNCTION|PIN ID|FUNCTION|
|es|ee|Ge|rsGQ|GO|
|A1|VIN|B1|CLKIN|C1|IMONb|D1|PGOOD|E1|COMPb|F1|ISETb|
|es|es ee|ee|rs|Qs es|
|A2|VIN|B2|NC|C2|IMONa|D2|PGDFB|E2|COMPa|F2|ISETa|
|es|re es|re es|Gd|es|
|A3|VIN|B3|VIN|C3|SVIN|D3|VINREG|E3|fSET|F3|EXTVCC|
|es|es|eG|GG|GO|
|A4|VD|B4|VD|C4|VD|D4|GND|E4|SGND|F4|RUN|
|es|es|eG|reGQ|GO|
|A5|PGND|B5|PGND|C5|PGND|D5|PGND|E5|PGND|F5|PGND|
|es|es ees|ee|rs|rs|rs|
|A6|NC|B6|NC|C6|NC|D6|NC|E6|NC|F6|NC|
|PTE|lm|
|A7|NC|B7|NC|C7|NC|D7|NC|E7|NC|F7|NC|
|PF|CUT|UE|
|PIN ID|FUNCTION|PIN ID|FUNCTION|PIN ID|FUNCTION|PIN ID|FUNCTION|PIN ID|FUNCTION|
|es|es es ee|
|G1|VOSNS|H1|VOSNS|J1|TEMP|[+]|K1|VOUT|L1|VOUT|
|a|ee|es|
|G2|SGND|H2|SGND|J2|TEMP|[–]|K2|VOUT|L2|VOUT|
|es|es ee|Ge|es|
|G3|INTVCC|H3|PGND|J3|PGND|K3|VOUT|L3|VOUT|
|es|es|es|ee|
|G4|PGND|H4|SW|J4|PGND|K4|PGND|L4|PGND|
|es|es ee|ee|es|
|G5|PGND|H5|PGND|J5|PGND|K5|PGND|L5|PGND|
|a|es es|Ge|
|G6|NC|H6|NC|J6|TEMP|[+]|K6|NC|L6|NC|
|esee|
|G7|NC|H7|NC|J7|TEMP|[–]|K7|NC|L7|NC|
|es|es ee|ee|esse|

**----- End of picture text -----**<br>


Rev. B 

31 

For more information LTM4653 

LTM4653 

## **PACKAGE DESCRIPTION** 

## **Please refer to http://www.adi.com/designtools/packaging/ for the most recent package drawings.** 

**==> picture [487 x 562] intentionally omitted <==**

**----- Start of picture text -----**<br>
6<br>SEE NOTES<br>PIN 1<br>A B C D E F G H J K L BGA 77 0417 REV Ø<br>DETAIL A 12<br>3<br>G 4<br>5<br>6 PACKAGE BOTTOM VIEW LTMXXXXXX µModule<br>7 PACKAGE IN TRAY LOADING ORIENTATION<br>e<br>PACKAGE ROW AND COLUMN LABELING MAY VARY  AMONG µModule PRODUCTS. REVIEW EACH PACKAGE  LAYOUT CAREFULLY<br>F<br>3<br>SEE NOTES b DETAILS OF PIN #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE PIN #1 IDENTIFIER MAY BE EITHER A MOLD OR  MARKED FEATURE !<br>NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994 2. ALL DIMENSIONS ARE IN MILLIMETERS 3        BALL DESIGNATION PER JESD MS-028 AND JEP95 4 5. PRIMARY DATUM -Z- IS SEATING PLANE 6<br>COMPONENT PIN “A1” TRAY PIN 1 BEVEL<br>5.01mm)<br>× A A2<br>DETAIL B PACKAGE SIDE VIEW NOTES BALL HT BALL DIMENSION PAD DIMENSION SUBSTRATE THK MOLD CAP HT<br>9.00mm<br>× MAX 5.21 0.70 4.51 0.90 0.66 0.46 4.05 0.15 0.10 0.20 0.30 0.15<br>Y<br>H1 X<br>BGA Package A1 SUBSTRATE MZ MZ DIMENSIONS NOM 5.01 0.60 4.41 0.75 0.63 15.00 9.00 1.27 12.70 7.62 0.41 4.00<br>ddd eee<br>b1<br>H2 TOTAL NUMBER OF BALLS: 77<br>ccc  Z MOLD CAP DETAIL B DETAIL A MIN 4.81 0.50 4.31 0.60 0.60 0.36 3.95<br>(Reference LTC DWG# 05-08-1826 Rev Ø)<br>77-Lead (15.00mm<br>Øb (77 PLACES)<br>A A1 A2 b b1 D E e F G H1 H2 aaa bbb ccc ddd eee<br>SYMBOL<br>aaa  Z<br>X D<br>6.350 5.080 3.810 2.540 1.270 0.000 1.270 2.540 3.810 5.080 6.350<br>Y<br>E<br>TOP VIEW<br>PACKAGE TOP VIEW<br>SUGGESTED PCB LAYOUT<br>aaa  Z 4<br>PIN “A1” CORNER<br>0.630 ±0.025 Ø 77x<br>Z<br>Z<br>Z//  bbb<br>3.810<br>2.540<br>1.270<br>0.3175<br>0.000<br>0.3175<br>1.270<br>2.540<br>3.810<br>**----- End of picture text -----**<br>


Rev. B 

32 

For more information LTM4653 

LTM4653 

## **REVISION HISTORY** 

|**REV**|**DATE**|**DESCRIPTION**|**PAGE NUMBER**|
|---|---|---|---|
|A|02/20|Added Input Disconnect/Input Short Considerations section.<br>Corrected resistor value to 100k from 100Ω.|17<br>29, 34|
|B|10/22|Removed errant negative sign.<br>Fixed major formatting issues.<br>Added ink marking statement to package photos.|3<br>All<br>31|



Rev. B 

33 

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.For more information LTM4653 

LTM4653 

## **TYPICAL APPLICATION** 

**==> picture [441 x 395] intentionally omitted <==**

**----- Start of picture text -----**<br>
IOUT<br>15V TO 46VVIN R105kA C4.7μFINH1 VSVVINDIN NC SW VVOSNSOUT RPGDFB195.3k LOAD C22µFOUTH V12VUP TO 4AOUT<br>CD1 PGDFB ×2<br>4.7μF GND SGND<br>RUN PGND<br>U1<br>CLKIN LTM4653 INTVCC1<br>RPGDPUP<br>INTVCC1 INTVCC 100k<br>VINREG PGOOD PGOOD<br>EXTVCC<br>COMPa TEMP [+] REXTVCC1<br>C10nFTH COMPb TEMP [–] CEXTVCC1 49.9Ω<br>R499ΩTH fSET ISETa ISETb IMONbIMONa 1µF ANALOG OUTPUTCURRENT INDICATOR,<br>VIMON = 0.25Ω • IOUT<br>RfSET1 CSS RISET1<br>124k 10nF 240k<br>VIN NC SW<br>CINH2 PGOOD<br>CINOUT 4.7µF SVIN GNDSNS<br>4.7µF GND<br>CDGND VD PGND<br>4.7µF LOAD COUT2<br>U2 D1* 22µF<br>LTM4651 VOUT [–]<br>CD2 VOUT [–] –12V<br>4.7µF SVOUT [–] UP TO 3.25A<br>RUN RPGDFB2<br>10kRB INTVCLKINCC PGDFB 95.3k<br>REXTVCC2<br>VINREG 49.9Ω<br>COMPa EXTVCC<br>TEMP [+]<br>COMPb TEMP [–] RTRACK<br>fSET ISETa ISETb 10k<br>RfSET2 RISET2 CEXTVCC2 *D1: CENTRAL SEMI<br>124k 240k||10k 1µF P/N CMMSH1-40L<br>4653 F37<br>**----- End of picture text -----**<br>


**Figure 37. Concurrent ±12V Supply. See Figure 36 for Output Voltage Start-Up Waveforms** 

## **RELATED PARTS** 

|**PART NUMBER**|**DESCRIPTION**|**COMMENTS**|
|---|---|---|
|LTM4651|EN55022B Compliant, 58VIN, 24W Inverting-Output<br>μModule Regulator|3.6V ≤ VIN≤ 58V, –26.5V ≤ VOUT≤ –0.5V, IOUT≤ 4A,<br>15mm × 9mm × 5.01mm BGA|
|LTM8045|SEPIC or Inverting µModule DC/DC Converter|2.8V ≤ VIN≤ 18V, ±2.5V ≤ VOUT≤ ±15V. IOUT(DC)≤ 700mA,<br>6.25mm × 11.25mm × 4.92mm BGA|
|LTM8049|Dual, SEPIC and/or Inverting µModule DC/DC Converter|2.6V ≤ VIN≤ 20V, ±2.5V ≤ VOUT≤ ±24V. IOUT(DC)≤ 1A/Channel,<br>9mm × 15mm × 2.42mm BGA|
|LTM8071|60V, 5A Step-Down µModule Regulator|3.6V ≤ VIN≤ 60V, 0.97V ≤ VOUT≤ 15V, 9mm ×11.25mm × 3.32mm BGA|
|LTM8073|60V, 3A Step-Down µModule Regulator|3.4V ≤ VIN≤ 60V, 0.8V ≤ VOUT≤ 15V. 6.25mm × 9mm × 3.32mm BGA|
|LTM8064|58V, ±6A CVCCStep-Down µModule Regulator|6V ≤ VIN≤ 58V, 1.2V ≤ VOUT≤ 36V, 11.9mm × 16mm × 4.92mm BGA|
|LTM4613|EN55022B Compliant, 36V, 8A µModule Regulator|5V ≤ VIN≤ 36V, 3.3V ≤ VOUT≤ 15V, 15mm × 15mm × 4.32mm LGA, and<br>15mm × 15mm × 4.92mm BGA|



Rev. B 

10/22 www.analog.com 

34 

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