LTM4620IY

LTM4620 

## Dual 13A or Single 26A DC/DC µModule Regulator 

## **FEATURES** 

- n **Complete Standalone Dual Output Power Supply** 

- n **Dual 13A or Single 26A Output** 

- n **Wide Input Voltage Range: 4.5V to 16V** 

- n **Output Voltage Range: 0.6V to 2.5V** 

- n **±1.5% Maximum Total DC Output Error** 

- n **Multiphase Current Sharing with Multiple LTM4620s Up to 100A** 

- n Differential Remote Sense Amplifier 

- n Current Mode Control/Fast Transient Response 

- n Adjustable Switching Frequency 

- n Overcurrent Foldback Protection 

- n Frequency Synchronization 

- n Internal Temperature Monitor 

- n Output Overvoltage Protection 

- n SnPb or RoHS Compliant Finish 

- n Thermally Enhanced (15mm × 15mm × 4.41mm) LGA Package and (15mm × 15mm × 5.01mm) BGA Package 

## **APPLICATIONS** 

- n Telecom and Networking Equipment 

- n Storage and ATCA Cards 

- n Industrial Equipment 

## **DESCRIPTION** 

The LTM[®] 4620 is a complete dual 13A output switching mode DC/DC power supply. Included in the package are the switching controller, power FETs, inductors, and all supporting components. Operating from an input voltage range of 4.5V to 16V, the LTM4620 supports two outputs each with an output voltage range of 0.6V to 2.5V, set by a single external resistor. Its high efficiency design delivers up to 13A continuous current for each output. Only a few input and output capacitors are needed. 

The device supports frequency synchronization, multiphase operation, Burst Mode operation and output voltage tracking for supply rail sequencing and has an onboard temperature diode for device temperature monitoring. High switching frequency and a current mode architecture enable a very fast transient response to line and load changes without sacrificing stability. 

Fault protection features include overvoltage and overcurrent protection. The power module is offered in a proprietary space saving and thermally enhanced 15mm × 15mm × 4.41mm LGA package and 15mm × 15mm × 5.01mm BGA package, with integrated top-side heat sink. The LTM4620 is available with SnPb (BGA) or RoHS compliant terminal finish. 

L, LT, LTC, LTM, Linear Technology, the Linear logo, µModule, Burst Mode, LTpowerCAD and PolyPhase are registered trademarks of Analog Devices, Inc. All other trademarks are the property of their respective owners. 

> **[Click to view associated TechClip Videos.]** 

## **TYPICAL APPLICATION** 

**26A, 1.2V Output DC/DC µModule**[®] **Regulator** 

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INTVCC<br>4.7µF 5k 1.2V Efficiency vs IOUT<br>PGOOD<br>MODE_PLLIN CLKOUT INTVCC EXTVCC PGOOD1 90<br>VIN 4.5V TO 16V 10k* 22µF× 4 120k VIN VVOUTS1OUT1 100µF6.3V + 470µF6.3V 80<br>25V T EMP DIFFOUT<br>SW1<br>RUN1 70<br>RUN2 LTM4620 VFB1<br>TRACK1 VFB2 60.4k 60<br>5.1V* TR ACK2 COMP1<br>* PULL-UP RESISTOR AND 0.1µF 121k PHASMDfSETSGND GND DIFFP DIFFN PGOOD2COMP2VVOUTS2OS UT2W2 100µF6.3V + 470µF6.3V V1.2V AT 26AOUT 5040 0 2 4 6 OUTPUT CURRENT (A)8 10 12 14 16 1812V5VIN20IN/500kHz/500kHz224620 TA01b24 26<br>PGOOD<br> ZENER ARE OPTIONAL<br>4620 TA01a<br>EFFICIENCY (%)<br>**----- End of picture text -----**<br>


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## LTM4620 

## **ABSOLUTE MAXIMUM RATINGS** 

## **(Note 1)** 

VIN (Note 8) .................................................–0.3V to 18V VSW1, VSW2 ....................................................–1V to 18V PGOOD1, PGOOD2, RUN1, RUN2, INTVCC, EXTVCC .......................................... –0.3V to 6V MODE_PLLIN, fSET, TRACK1, TRACK2, DIFFOUT, PHASMD ...............................–0.3V to INTVCC VOUT1, VOUT2, VOUTS1, VOUTS2 ..................... –0.3V to 6V 

DIFFP, DIFFN .........................................–0.3V to INTVCC COMP1, COMP2, VFB1, VFB2 (Note 6) ........ –0.3V to 2.7V INTVCC Peak Output Current ................................100mA Internal Operating Temperature Range (Note 2) E- and I-Grade ................................... –40°C to 125°C MP-Grade .......................................... –55°C to 125°C Storage Temperature Range .................. –55°C to 125°C Peak Package Body Temperature .......................... 245°C 

## **PIN CONFIGURATION** 

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TOP VIEW TOP VIEW<br>TEMP EXTVCC TEMP EXTVCC<br>M M<br>L L<br>VIN VIN<br>K K<br>J J<br>CLKOUTSW1 H INTVSW2CC CLKOUTSW1 H INTVSW2CC<br>G PGOOD1 G PGOOD1<br>PHASMD RUN1 SGND PGOOD2 PHASMD RUN1 SGND PGOOD2<br>MODE_PLLIN F GND COMP1 COMP2 RUN2DIFFOUT MODE_PLLIN F GND COMP1 COMP2 RUN2DIFFOUT<br>TRACK1VFB1 DE SGND VFB2 TRACK2 GND DIFFPDIFFN TRACK1VFB1 DE SGND VFB2 TRACK2 GND DIFFPDIFFN<br>fSET SGND VOUTS2 fSET SGND VOUTS2<br>C C<br>VOUTS1 VOUTS1<br>B B<br>VOUT1 GND VOUT2 VOUT1 GND VOUT2<br>A A<br>1 2 3 4 5 6 7 8 9 10 11 12 1 2 3 4 5 6 7 8 9 10 11 12<br>LGA PACKAGE BGA PACKAGE<br>144-LEAD (15mm × 15mm × 4.41mm) 144-LEAD (15mm × 15mm × 5.01mm)<br>TJMAX = 125°C,  θ JA = 7°C/W,  θ JCbottom = 1.5°C/W,   TJMAX = 125°C,  θ JA = 7°C/W,  θ JCbottom = 1.5°C/W,<br>θ JCtop = 3.7°C/W,  θ JB +  θ BA ≅  7°C/W  θ JCtop = 3.7°C/W,  θ JB +  θ BA ≅  7°C/W<br>θ  VALUES DEFINED PER JESD 51-12 θ  VALUES DEFINED PER JESD 51-12<br>WEIGHT = 3.037g WEIGHT = 3.232g<br>**----- End of picture text -----**<br>


## **ORDER INFORMATION** 

## **http://www.linear.com/product/LTM4620#orderinfo** 

|**PART NUMBER**|**PAD OR BALL FINISH**|**PART MARKING***<br>**DEVICE**<br>**FINISH CODE**|**PART MARKING***<br>**DEVICE**<br>**FINISH CODE**|**PACKAGE**<br>**TYPE**|**MSL**<br>**RATING**|**TEMPERATURE RANGE**<br>**(Note 2)**|
|---|---|---|---|---|---|---|
||||**FINISH CODE**||||
|LTM4620EV#PBF|Au(RoHS)|LTM4620V|e4|LGA|3|–40°C to 125°C|
|LTM4620IV#PBF|Au(RoHS)|LTM4620V|e4|LGA|3|–40°C to 125°C|
|LTM4620EY#PBF|SAC305(RoHS)|LTM4620Y|e1|BGA|3|–40°C to 125°C|
|LTM4620IY#PBF|SAC305(RoHS)|LTM4620Y|e1|BGA|3|–40°C to 125°C|
|LTM4620IY|SnPb(63/37)|LTM4620Y|e0|BGA|3|–40°C to 125°C|
|LTM4620MPY#PBF|SAC305(RoHS)|LTM4620Y|e1|BGA|3|–55°C to 125°C|
|LTM4620MPY|SnPb(63/37)|LTM4620Y|e0|BGA|3|–55°C to 125°C|



Consult Marketing for parts specified with wider operating temperature ranges. *Device temperature grade is indicated by a label on the shipping container. Pad or ball finish code is per IPC/JEDEC J-STD-609. 

- Terminal Finish Part Marking: www.linear.com/leadfree 

• Recommended LGA and BGA PCB Assembly and Manufacturing Procedures: www.linear.com/umodule/pcbassembly 

- LGA and BGA Package and Tray Drawings: www.linear.com/packaging 

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LTM4620 

## **ELECTRICAL CHARACTERISTICS** 

**The** l **denotes the specifications which apply over the specified internal operating temperature range (Note 2). Specified as each individual output channel. TA = 25°C, VIN = 12V and VRUN1, VRUN2 at 5V unless otherwise noted. Per the typical application in Figure 23.** 

|**SYMBOL**|**PARAMETER**|**CONDITIONS**|**CONDITIONS**|**MIN**<br>**TYP**<br>**MAX**|**UNITS**|
|---|---|---|---|---|---|
|VIN|Input DC Voltage||l|4.5<br>16|V|
|VOUT|Output Voltage|(Note 8)|l|0.6<br>2.5|V|
|VOUT1(DC),<br>VOUT2(DC)|Output Voltage, Total Variation with<br>Line and Load|CIN= 22µF×3, COUT= 100µF×1 Ceramic,<br>470µF POSCAP, VOUT= 1.5V|l|1.477<br>1.5<br>1.523|V|
|**Input Specifications**||||||
|VRUN1, VRUN2|RUN Pin On/Off Threshold|RUN Rising||1.1<br>1.25<br>1.40|V|
|VRUN1HYS, VRUN2HYS|RUN Pin On Hysteresis|||150|mV|
|IINRUSH(VIN)|Input Inrush Current at Start-Up|IOUT= 0A, CIN= 22µF ×3, CSS= 0.01µF,<br>COUT= 100µF ×3, VOUT1= 1.5V, VOUT2= 1.5V,<br>VIN= 12V||1|A|
|IQ(VIN)|Input Supply Bias Current|VIN= 12V, VOUT= 1.5V, Burst Mode Operation<br>VIN= 12V, VOUT= 1.5V, Pulse-Skipping Mode<br>VIN= 12V, VOUT= 1.5V, Switching Continuous<br>Shutdown, RUN = 0, VIN= 12V||5<br>15<br>65<br>50|mA<br>mA<br>mA<br>µA|
|IS(VIN)|Input Supply Current|VIN= 5V, VOUT= 1.5V, IOUT= 13A<br>VIN= 12V, VOUT= 1.5V, IOUT= 13A||4.6<br>1.853|A<br>A|
|**Output Specifications**||||||
|IOUT1(DC), IOUT2(DC)|Output Continuous Current Range|VIN= 12V, VOUT= 1.5V(Notes 7, 8)||0<br>13|A|
|ΔVOUT1(LINE)/VOUT1<br>ΔVOUT2(LINE)/VOUT2|Line Regulation Accuracy|VOUT= 1.5V, VINfrom 4.5V to 16V<br>IOUT= 0A for Each Output,|l|0.01<br>0.025|%/V|
|ΔVOUT1/VOUT1<br>ΔVOUT2/VOUT2|Load Regulation Accuracy|For Each Output, VOUT= 1.5V, 0A to 13A<br>VIN= 12V(Note 7)|l|0.5<br>0.75|%|
|VOUT1(AC), VOUT2(AC)|Output Ripple Voltage|For Each Output, IOUT= 0A, COUT= 100µF ×3/<br>X7R/Ceramic, 470µF POSCAP, VIN= 12V,<br>VOUT= 1.5V, Frequency= 400kHz||15|mVP-P|
|fS (Each Channel)|Output Ripple Voltage Frequency|VIN= 12V, VOUT= 1.5V, fSET= 1.25V(Note 4)||500|kHz|
|fSYNC<br>(Each Channel)|SYNC Capture Range|||400<br>780|kHz|
|ΔVOUTSTART<br>(Each Channel)|Turn-On Overshoot|COUT= 100µF/X5R/Ceramic, 470µF POSCAP,<br>VOUT= 1.5V, IOUT= 0A VIN= 12V||10|mV|
|tSTART<br>(Each Channel)|Turn-On Time|COUT= 100µF/X5R/Ceramic, 470µF POSCAP,<br>No Load, TRACK/SS with 0.01µF to GND,<br>VIN= 12V||5|ms|
|ΔVOUT(LS)<br>(Each Channel)|Peak Deviation for Dynamic Load|Load: 0% to 50% to 0% of Full Load<br>COUT= 22µF ×3/X5R/Ceramic, 470µF POSCAP<br>VIN= 12V, VOUT= 1.5V||30|mV|
|tSETTLE<br>(Each Channel)|Settling Time for Dynamic Load<br>Step|Load: 0% to 50% to 0% of Full Load,<br>VIN= 12V, COUT= 100µF, 470µF POSCAP||20|µs|
|IOUT(PK)<br>(Each Channel)|Output Current Limit|VIN= 12V, VOUT= 1.5V||20|A|
|**Control Section**||||||
|VFB1, VFB2|Voltage at VFBPins|IOUT= 0A, VOUT= 1.5V|l|0.592<br>0.600<br>0.606|V|
|IFB1, IFB2||(Note 6)||–5<br>–20|nA|
|VOVL|Feedback Overvoltage Lockout||l|0.64<br>0.66<br>0.68|V|



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## LTM4620 

## **ELECTRICAL CHARACTERISTICS** 

**The** l **denotes the specifications which apply over the specified internal operating temperature range (Note 2). Specified as each individual output channel. TA = 25°C, VIN = 12V and VRUN1, VRUN2 at 5V unless otherwise noted. Per the typical application in Figure 23.** 

|**SYMBOL**|**PARAMETER**|**CONDITIONS**|**CONDITIONS**|**MIN**<br>**TYP**<br>**MAX**|**UNITS**|
|---|---|---|---|---|---|
|TRACK1 (I),<br>TRACK2(I)|Track Pin Soft-Start Pull-Up Current|TRACK1 (I),TRACK2 (I) Start at 0V||1<br>1.25<br>1.5|µA|
|UVLO|Undervoltage Lockout|VINFalling<br>VINRising||3.3<br>3.9|V<br>V|
|UVLO Hysteresis||||0.6|V|
|tON(MIN)|Minimum On-Time|(Note 6)||90|ns|
|RFBHI1, RFBHI2|Resistor Between VOUTS1, VOUTS2<br>and VFB1, VFB2Pins for Each Output|||60.05<br>60.4<br>60.75|kΩ|
|VPGOOD1, VPGOOD2<br>Low|PGOOD Voltage Low|IPGOOD= 2mA||0.1<br>0.3|V|
|IPGOOD|PGOOD Leakage Current|VPGOOD= 5V||±5|µA|
|VPGOOD|PGOOD Trip Level|VFBwith Respect to Set Output Voltage<br>VFBRamping Negative<br>VFBRampingPositive||–10<br>10|%<br>%|
|**INTVCC Linear Regulator**||||||
|VINTVCC|Internal VCCVoltage|6V < VIN< 16V||4.8<br>5<br>5.2|V|
|VINTVCC<br>Load Regulation|INTVCCLoad Regulation|ICC= 0mA to 50mA||0.5<br>2|%|
|VEXTVCC|EXTVCCSwitchover Voltage|EXTVCCRampingPositive||4.5<br>4.7|V|
|VEXTVCC(DROP)|EXTVCCDropout|ICC= 20mA, VEXTVCC= 5V||50<br>100|mV|
|VEXTVCC(HYST)|EXTVCCHysteresis|||200|mV|
|**Oscillator and Phase-Locked Loop**||||||
|FrequencyNominal|Nominal Frequency|fSET= 1.2V||450<br>500<br>550|kHz|
|FrequencyLow|Lowest Frequency|fSET= 0V(Note 5)||210<br>250<br>290|kHz|
|FrequencyHigh|Highest Frequency|fSET> 2.4V, Upto INTVCC||700<br>780<br>860|kHz|
|fSET|FrequencySet Current|||9<br>10<br>11|µA|
|RMODE_PLLIN|MODE_PLLIN Input Resistance|||250|kΩ|
|CLKOUT|Phase (Relative to VOUT1)|PHASMD = GND<br>PHASMD = Float<br>PHASMD = INTVCC||60<br>90<br>120|Deg<br>Deg<br>Deg|
|CLK High<br>CLK Low|Clock High Output Voltage<br>Clock Low Output Voltage|||2<br>0.2|V<br>V|
|**Differential Amplifier**||||||
|AVDifferential<br>Amplifier|Gain|||1|V/V|
|RIN|Input Resistance|Measured at DIFFP Input||80|kΩ|
|VOS|Input Offset Voltage|VDIFFP= VDIFFOUT= 1.5V, IDIFFOUT= 100µA||3|mV|
|PSRR Differential<br>Amplifier|Power Supply Rejection Ratio|5V < VIN< 16V||90|dB|
|ICL|Maximum Output Current|||2|mA|
|VOUT(MAX)|Maximum Output Voltage|IDIFFOUT= 300µA||INTVCC– 1.4|V|



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LTM4620 

## **ELECTRICAL CHARACTERISTICS** 

|||||||
|---|---|---|---|---|---|
|**The**l**denotes the specifications which apply over the specified internal**<br>**operating temperature range (Note 2). Specified as each individual output channel. TA = 25°C, VIN = 12V and VRUN1, VRUN2 at 5V**<br>**unless otherwise noted. Per the typical application in Figure 23.**<br>**ELECTRICAL CHARACTERISTICS**||||||
|**SYMBOL**|**PARAMETER**|**CONDITIONS**||**MIN**<br>**TYP**<br>**MAX**|**UNITS**|
|GBW|Gain Bandwidth Product|||3|MHz|
|VTEMPTempDiode|Diode Connected PNP|I = 100µA||0.598|V|
|TC|Temperature Coefficient|||–2.0|mV/°C|



**Note 1:** Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. 

**Note 3:** Two outputs are tested separately and the same testing condition is applied to each output. 

**Note 4:** The switching frequency is programmable from 400kHz to 750kHz. **Note 5:** LTM4620 device is designed to operate from 400kHz to 750kHz **Note 6:** These parameters are tested at wafer sort. 

**Note 2:** The LTM4620 is tested under pulsed load conditions such that TJ ≈ TA. The LTM4620E is guaranteed to meet specifications from 0°C to 125°C internal temperature. Specifications over the –40°C to 125°C internal operating temperature range are assured by design, characterization and correlation with statistical process controls. The LTM4620I is guaranteed over the full –40°C to 125°C internal operating temperature range. The LTM4620MP is tested and guaranteed over the –55°C to 125°C operating temperature range. For output current derating at high temperature, please refer to thermal conditions and output current derating discussion. Note that the maximum ambient temperature consistent with these specifications is determined by specific operating conditions in conjunction with board layout, the rated package thermal impedance and other environmental factors. 

**Note 7:** See output current derating curves for different VIN, VOUT and TA. **Note 8:** Output current limitations. For 10V ≤ VIN ≤ 16V, the 2.5V output current needs to be limited to 10A/channel, switching frequency = 750kHz. Derating curves apply. For 5V ≤ VIN ≤ 9V, the 2.5V output current needs to be limited to 12A/channel, switching frequency = 750kHz. Derating curves apply. All other input and output combinations are 13A/channel with recommended switching frequency included in the efficiency graphs. Derating curves apply. 

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LTM4620 

## **TYPICAL PERFORMANCE CHARACTERISTICS** 

**Efficiency vs Output Current, VIN = 5V** 

**Efficiency vs Output Current, VIN = 12V** 

**Dual Phase Single Output Efficiency vs Output Current, VIN = 12V** 

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10095 Ton 9590 «=o 9590 Me<br>90<br>85 85<br>-epeeeecieery ||GREER) [|Lee<br>85<br>80 80<br>fos (aS 6ELPe<br>80<br>75 75<br>Hy)<br>75<br>70 qo| 1.2V1VOUTOUT, f = 400kHz, f = 500kHz 70 Fille 1.2V1VOUTOUT, f = 400kHz, f = 500kHz 70 rine7 1.2V1VOUTOUT, f = 400kHz, f = 500kHz<br>65 qd 1.5V1.8VOUTOUT, f = 550kHz, f = 600kHz 65 HLL 1.5V1.8VOUTOUT, f = 550kHz, f = 600kHz 65 Fai 1.5V1.8VOUTOUT, f = 550kHz, f = 600kHz<br>60 (tte 2.5VOUT, f = 750kHz 60 ian 2.5VOUT, f = 750kHz 60 Ae 2.5VOUT, f = 750kHz<br>0 1 2 3 4 5 6 7 8 9 10 11 12 13 0 1 2 3 4 5 6 7 8 9 10 11 12 13 0 2 4 6 8 10 12 14 16 18 20 22 24 26<br>OUTPUT CURRENT (A) OUTPUT CURRENT (A) OUTPUT CURRENT (A)<br>4620 G01 4620 G02 4620 G03<br>Dual Phase Single Output   Single Phase Single Output   Single Phase Single Output<br>Load Transient Response Load Transient Response Load Transient Response<br>VOUT VOUT VOUT<br>100mV/DIV 100mV/DIV 100mV/DIV<br>ILOAD ILOAD ILOAD i<br>10A/DIV PT TTT 50µs/DIV ET Ty 4620 G04 5A/DIV 50µs/DIV || 4620 G05 5A/DIV PETTyETE 50µs/DIV 4620 G06<br>Hesrre PEPER<br>12VIN, 1.5VOUT AT 26A/µs LOAD STEP 12VIN, 1VOUT AT 13A/µs LOAD STEP 12VIN, 1.2VOUT AT 13A/µs LOAD STEP<br>COUT = 4× 470µF, 4V POSCAP AND  COUT = 2× 470µF, 4V POSCAP AND  COUT = 2× 470µF, 4V POSCAP AND<br>2× 100µF, 6.3V CERAMIC 1× 100µF, 6.3V CERAMIC 1× 100µF, 6.3V CERAMIC<br>EFFICIENCY (%) EFFICIENCY (%) EFFICIENCY (%)<br>**----- End of picture text -----**<br>


## **Single Phase Single Output Load Transient Response** 

**Single Phase Single Output Load Transient Response** 

**Single Phase Single Output Load Transient Response** 

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VOUT VOUT<br>100mV/DIV 100mV/DIV<br>ILOAD ILOAD<br>5A/DIV 50µs/DIV 4620 G07 5A/DIV PT TTT 50µs/DIV et Ty 4620 G08<br>12VIN, 1.5VOUT AT 13A/µs LOAD STEP 12VIN, 1.8VOUT AT 13A/µs LOAD STEP<br>COUT = 2× 470µF, 4V POSCAP AND  COUT = 2× 470µF, 4V POSCAP AND<br>1× 100µF, 6.3V CERAMIC 1× 100µF, 6.3V CERAMIC<br>**----- End of picture text -----**<br>


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VOUT<br>100mV/DIV<br>ILOAD<br>5A/DIV PT TT tT et tty<br>50µs/DIV 4620 G09<br>12VIN, 2.5VOUT AT 13A/µs LOAD STEP<br>COUT = 2× 470µF, 4V POSCAP AND<br>1× 100µF, 6.3V CERAMIC<br>**----- End of picture text -----**<br>


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LTM4620 

## **TYPICAL PERFORMANCE CHARACTERISTICS** 

**Single Phase Single Output Single Phase Single Output Start-Up Start-Up** 

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VOUT<br>0.5V/DIV<br>IOUT<br>5A/DIV<br>ae 2ms/DIV 4620 G10 a 2ms/DIV 4620 G11<br>12VIN, 1.5VOUT AT NO LOAD 12VIN, 1.5VOUT AT 10A LOAD<br>COUT = 2× 470µF, 4V SANYO POSCAP,  COUT = 2× 470µF, 4V SANYO POSCAP,<br>1× 100µF, 6.3V CERAMIC 1× 100µF, 6.3V X5R CERAMIC<br>SOFT-START CAPACITOR = 0.01µF SOFT-START CAPACITOR = 0.01µF<br>USE RUN PIN TO CONTROL START-UP USE RUN PIN TO CONTROL START-UP<br>**----- End of picture text -----**<br>


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VOUT<br>0.5V/DIV<br>IOUT<br>1A/DIV<br>2ms/DIV 4620 G10<br>**----- End of picture text -----**<br>


**Current Limit and Current Foldback** 

**Load Regulation vs Current** 

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1.8<br>VIN = 12V VIN = 12V<br>1.6 VOUT = 1.5V TT 1.0 VOUT = 1.5V TooToo<br>1.4<br>0.8<br>1.2 S S S<br>1.0 PE TT 0.6 LEAL<br>0.8<br>0.6 +f 0.4 LYALL LLL<br>0.4 A 0.2 MALLET<br>0.2 en c<br>0 fe 0 ALLL<br>0 5 10 15 20 25 0 5 10 15<br>OUTPUT CURRENT (A) OUTPUT CURRENT (A)<br>4620 G12 4620 G13<br>Short-Circuit Protection Short-Circuit Protection<br>VOUT<br>VOUTOUT 500mV/DIV<br>IIN<br>IININ 2A/DIV<br>2A/DIV<br>50µs/DIV 4620 G14 50µs/DIV 4620 G15<br>VIN = 12VIN = 12V = 12V VIN = 12V<br>VOUT = 1.5VOUT = 1.5V= 1.5V VOUT = 1.5V<br>IOUT = NO LOADOUT = NO LOAD = NO LOAD IOUT = 13A<br>OUTPUT VOLTAGE (V)<br>LOAD REGULATION (mV)<br>**----- End of picture text -----**<br>


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VOUTOUT<br>500mV/DIV<br>IININ<br>2A/DIV<br>50µs/DIV 4620 G14<br>VIN = 12VIN = 12V = 12V<br>VOUT = 1.5VOUT = 1.5V= 1.5V<br>IOUT = NO LOADOUT = NO LOAD = NO LOAD<br>**----- End of picture text -----**<br>


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LTM4620 

## **PIN FUNCTIONS** 

## **(Recommended to Use Test Points to Monitor Signal Pin Connections.)** 

**VFB1, VFB2 (D5, D7):** The Negative Input of the Error Amplifier for Each Channel. Internally, this pin is connected to VOUTS1 or VOUTS2 with a 60.4kΩ precision resistor. Different output voltages can be programmed with an additional resistor between VFB and GND pins. In PolyPhase[®] operation, tying the VFB pins together allows for parallel operation. See the Applications Information section for details. 

## **PACKAGE ROW AND COLUMN LABELING MAY VARY AMONG µModule PRODUCTS. REVIEW EACH PACKAGE LAYOUT CAREFULLY.** 

**==> picture [35 x 31] intentionally omitted <==**

**VOUT1 (A1-A5, B1-B5, C1-C4):** Power Output Pins. Apply output load between these pins and GND pins. Recommend placing output decoupling capacitance directly between these pins and GND pins. Review Table 4. See Note 8 in the Electrical Characteristics section for output current guideline. 

**TRACK1, TRACK2 (E5, D8):** Output Voltage Tracking Pin and Soft-Start Inputs. Each channel has a 1.3µA pull-up current source. When one channel is configured to be master of the two channels, then a capacitor from this pin to ground will set a soft-start ramp rate. The remaining channel can be set up as the slave, and have the master’s output applied through a voltage divider to the slave output’s track pin. This voltage divider is equal to the slave output’s feedback divider for coincidental tracking. See the Applications Information section. 

**GND (A6-A7, B6-B7, D1-D4, D9-D12, E1-E4, E10-E12, F1-F3, F10-F12, G1, G3, G10, G12, H1-H7, H9-H12, J1, J5, J8, J12, K1, K5-K8, K12, L1, L12, M1 , M12):** Power Ground Pins for Both Input and Output Returns. 

**VOUT2 (A8-A12, B8-B12, C9-C12):** Power Output Pins. Apply output load between these pins and GND pins. Recommend placing output decoupling capacitance directly between these pins and GND pins. Review Table 4. See Note 8 in the Electrical Characteristics section for output current guideline. 

**COMP1, COMP2 (E6, E7):** Current control threshold and error amplifier compensation point for each channel. The current comparator threshold increases with this control voltage. Tie the COMP pins together for parallel operation. The device is internal compensated. 

**VOUTS1, VOUTS2 (C5, C8):** This pin is connected to the top of the internal top feedback resistor for each output. The pin can be directly connected to its specific output, or connected to DIFFOUT when the remote sense amplifier is used. In paralleling modules, one of the VOUTS pins is connected to the DIFFOUT pin in remote sensing or directly to VOUT with no remote sensing. It is very important to connect these pins to either the DIFFOUT or VOUT since this is the feedback path, and cannot be left open. See the Applications Information section. 

**DIFFP (E8):** Positive input of the remote sense amplifier. This pin is connected to the remote sense point of the output voltage. See the Applications Information section. 

**DIFFN (E9):** Negative input of the remote sense amplifier. This pin is connected to the remote sense point of the output GND. See the Applications Information section. 

**fSET (C6):** Frequency Set Pin. A 10µA current is sourced from this pin. A resistor from this pin to ground sets a voltage that in turn programs the operating frequency. Alternatively, this pin can be driven with a DC voltage that can set the operating frequency. See the Applications Information section. 

**MODE_PLLIN (F4):** Force Continuous Mode, Burst Mode Operation, or Pulse-Skipping Mode Selection Pin and External Synchronization Input to Phase Detector Pin. Connect this pin to SGND to force both channels into force continuous mode of operation. Connect to INTVCC to enable pulse-skipping mode of operation. Leaving the pin floating will enable Burst Mode operation. A clock on the pin will force both channels into continuous mode of operation and synchronized to the external clock applied to this pin. 

**SGND (C7, D6, G6-G7, F6-F7):** Signal Ground Pin. Return ground path for all analog and low power circuitry. Tie a single connection to the output capacitor GND in the application. See layout guidelines in Figure 22. 

**Heat Sink (Top Exposed Metal):** The top exposed metal is at ground potential. 

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LTM4620 

## **PIN FUNCTIONS (Recommended to Use Test Points to Monitor Signal Pin Connections.)** 

**RUN1, RUN2 (F5, F9):** Run Control Pin. A voltage above 1.25V will turn on each channel in the module. A voltage below 1.25V on the RUN pin will turn off the related channel. Each RUN pin has a 1µA pull-up current, once the RUN pin reaches 1.2V an additional 4.5µA pull-up current is added to this pin. 

**DIFFOUT (F8):** Internal Remote Sense Amplifier Output. Connect this pin to VOUTS1 or VOUTS2 depending on which output is using remote sense. In parallel operation connect one of the VOUTS pin to DIFFOUT for remote sensing. 

**SW1, SW2 (G2, G11):** Switching node of each channel that is used for testing purposes. Also an R-C snubber network can be applied to reduce or eliminate switch node ringing, or otherwise leave floating. See the Applications Information section. 

**PHASMD (G4):** Connect this pin to SGND, INTVCC, or floating this pin to select the phase of CLKOUT to 60 degrees, 120 degrees, and 90 degrees respectively. 

**CLKOUT (G5):** Clock output with phase control using the PHASMD pin to enable multiphase operation between devices. See the Applications Information section. 

**PGOOD1, PGOOD2 (G9, G8):** Output Voltage Power Good Indicator. Open drain logic output that is pulled to ground when the output voltage is not within ±10% of the regulation point. 

**INTVCC (H8):** Internal 5V Regulator Output. The control circuits and internal gate drivers are powered from this voltage. Decouple this pin to PGND with a 4.7µF low ESR tantalum or ceramic. INTVCC is activated when either RUN1 or RUN2 is activated. 

**TEMP (J6):** Onboard Temperature Diode for Monitoring the VBE Junction Voltage Change with Temperature. See the Applications Information section. 

**EXTVCC (J7):** External power input that is enabled through a switch to INTVCC whenever EXTVCC is greater than 4.7V. Do not exceed 6V on this input, and connect this pin to VIN when operating VIN on 5V. An efficiency increase will occur that is a function of the (VIN – INTVCC) multiplied by power MOSFET driver current. Typical current requirement is 30mA. VIN must be applied before EXTVCC, and EXTVCC must be removed before VIN. 

**VIN (M2-M11, L2-L11, J2-J4, J9-J11, K2-K4, K9-K11):** Power Input Pins. Apply input voltage between these pins and GND pins. Recommend placing input decoupling capacitance directly between VIN pins and GND pins. 

**Top Heat Sink:** Top heat sink is at ground potential. 

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LTM4620 

## **SIMPLIFIED BLOCK DIAGRAM** 

**==> picture [500 x 465] intentionally omitted <==**

**----- Start of picture text -----**<br>
PGOOD1<br>TRACK1 VIN<br>SS CAP 1µF C22µFIN1 C22µFIN2<br>25V 25V<br>GND<br>VRINT = 100µA VIN RT CLKOUTTEMP MTOP1 SW1<br>RUN1 0.33µH VOUT1 VOUT1<br>MODE_PLLIN + 1.5V/13A<br>MBOT1 2.2µF COUT1<br>PHASMD GND<br>VOUTS1<br>COMP1 60.4k<br>VFB1<br>INTERNAL<br>COMP RFB1<br>40.2k<br>SGND POWER<br>CONTROL PGOOD2<br>TRACK2 VIN<br>SS CAP INTVCC 1µF C22µFIN3 C22µFIN4<br>4.7µF GND 25V 25V<br>EXTVCC<br>MTOP2<br>SW2<br>0.33µH VOUT2 VOUT2<br>RUN2 + 1.2V/13A<br>MBOT2 2.2µF COUT2<br>GND<br>VOUTS2<br>60.4k<br>COMP2 VFB2<br>+ –<br>INTERNAL RFB2<br>COMP 60.4k<br>fSET<br>RfSET INTERNAL<br>121k FILTER<br>SGND<br>DIFFOUT<br>DIFFN<br>DIFFP<br>**----- End of picture text -----**<br>


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**----- Start of picture text -----**<br>
4620 BD<br>**----- End of picture text -----**<br>


**Figure 1. Simplified LTM4620 Block Diagram** 

## **DECOUPLING REQUIREMENTS TA = 25°C. Use Figure 1 configuration.** 

|**DECO**|**UPLING REQUIREMENTS**|<br>**TA = 25°C. Use Figure 1 configuration.**|<br>**TA = 25°C. Use Figure 1 configuration.**|||
|---|---|---|---|---|---|
|**SYMBOL**|**PARAMETER**|**CONDITIONS**||**MIN**<br>**TYP**<br>**MAX**|**UNITS**|
|CIN1,CIN2<br>CIN3, CIN4|External Input Capacitor Requirement<br>(VIN= 4.5V to 16V, VOUT1= 1.5V)<br>(VIN= 4.5V to 16V, VOUT2= 1.2V)|IOUT1= 13A<br>IOUT2= 13A(Note 8)||22<br>22|µF<br>µF|
|COUT1<br>COUT2|External Output Capacitor Requirement<br>(VIN= 4.5V to 16V, VOUT1= 1.5V)<br>(VIN= 4.5V to 16V, VOUT2= 1.2V)|IOUT1= 13A<br>IOUT2= 13A(Note 8)||300<br>300|µF<br>µF|
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LTM4620 

## **OPERATION** 

## **Power Module Description** 

The LTM4620 is a dual-output standalone nonisolated switching mode DC/DC power supply. It can provide two 13A outputs with few external input and output capacitors and setup components. This module provides precisely regulated output voltages programmable via external resistors from 0.6VDC to 2.5VDC over 4.5V to 16V input voltages. The typical application schematic is shown in Figure 23. See Note 8 in the Electrical Characteristics section for output current guideline. 

The LTM4620 has dual integrated constant-frequency current mode regulators and built-in power MOSFET devices with fast switching speed. The typical switching frequency is 500kHz. For switching-noise sensitive applications, it can be externally synchronized from 400kHz to 780kHz. A resistor can be used to program a free run frequency on the fSET pin. See the Applications Information section. 

With current mode control and internal feedback loop compensation, the LTM4620 module has sufficient stability margins and good transient performance with a wide range of output capacitors, even with all ceramic output capacitors. 

Current mode control provides cycle-by-cycle fast current limit and foldback current limit in an overcurrent condition. Internal overvoltage and undervoltage comparators pull the open-drain PGOOD outputs low if the output feedback voltage exits a ±10% window around the regulation point. As the output voltage exceeds 10% above regulation, the bottom MOSFET will turn on to clamp the output voltage. The top MOSFET will be turned off. This overvoltage protect is feedback voltage referred. 

Pulling the RUN pins below 1.1V forces the regulators into a shutdown state, by turning off both MOSFETs. The TRACK pins are used for programming the output 

voltage ramp and voltage tracking during start-up or used for soft-starting the regulator. See the Applications Information section. 

The LTM4620 is internally compensated to be stable over all operating conditions. Table 4 provides a guide line for input and output capacitances for several operating conditions. The LTpowerCAD[®] will be provided for transient and stability analysis. The VFB pin is used to program the output voltage with a single external resistor to ground. A differential remote sense amplifier is available for sensing the output voltage accurately on one of the outputs at the load point, or in parallel operation sensing the output voltage at the load point. 

Multiphase operation can be easily employed with the MODE_PLLIN, PHASMD, and CLKOUT pins. Up to 12 phases can be cascaded to run simultaneously with respect to each other by programming the PHASMD pin to different levels. See the Applications Information section. 

High efficiency at light loads can be accomplished with selectable Burst Mode operation or pulse-skipping operation using the MODE_PLLIN pin. These light load features will accommodate battery operation. Efficiency graphs are provided for light load operation in the Typical Performance Characteristics  section. See the Applications Information section for details. 

A temperature diode is included inside the module to monitor the temperature of the module. See the Applications Information section for details. 

A TEMP pin is provided to allow the internal device temperature to be monitored using an onboard diode connected PNP transistor. This diode connected PNP transistor is grounded in the module and can be used as a general temperature monitor using a device that is designed to monitor the single-ended connection. 

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LTM4620 

## **APPLICATIONS INFORMATION** 

The typical LTM4620 application circuit is shown in Figure 23. External component selection is primarily determined by the maximum load current and output voltage. Refer to Table 4 for specific external capacitor requirements for particular applications. 

## **VIN to VOUT Step-Down Ratios** 

There are restrictions in the maximum VIN and VOUT stepdown ratio that can be achieved for a given input voltage. Each output of the LTM4620 is capable of 98% duty cycle, but the VIN to VOUT minimum dropout is still shown as a function of its load current and will limit output current capability related to high duty cycle on the top side switch. Minimum on-time t is another consideration in ON(MIN) operating at a specified duty cycle while operating at a certain frequency due to the fact that tON(MIN) < D/fSW, where D is duty cycle and fSW is the switching frequency. tON(MIN) is specified in the electrical parameters as 90ns. See Note 8 in the Electrical Characteristics section for output current guideline. 

## **Output Voltage Programming** 

The PWM controller has an internal 0.6V reference voltage. As shown in the Block Diagram, a 60.4kΩ internal feedback resistor connects between the VOUTS1 to VFB1 and VOUTS2 to VFB2. It is very important that these pins be connected to their respective outputs for proper feedback regulation. Overvoltage can occur if these VOUTS1 and VOUTS2 pins are left floating when used as individual regulators, or at least one of them is used in paralleled regulators. The output voltage will default to 0.6V with no feedback resistor on either VFB1 or VFB2. Adding a resistor RFB from VFB pin to GND programs the output voltage: 

**==> picture [119 x 29] intentionally omitted <==**

**Table 1. VFB Resistor Table vs Various Output Voltages** 

|**VOUT**|0.6V|1.0V|1.2V|1.5V|1.8V|2.5V|
|---|---|---|---|---|---|---|
|**RFB**|Open|90.9k|60.4k|40.2k|30.2k|19.1k|



For parallel operation of multiple channels the same feedback setting resistor can be used for the parallel design. This is done by connecting the VOUTS1 to the output as shown in Figure 2, thus tying one of the internal 60.4k 

resistors to the output.  All of the VFB pins tie together with one programming resistor as shown in Figure 2. 

In parallel operation, the VFB pins have an IFB current of 20nA maximum each channel. To reduce output voltage error due to this current, an additional VOUTS pin can be tied to VOUT, and an additional RFB resistor can be used to lower the total Thevenin equivalent resistance seen by this current. For example in Figure 2, the total Thevenin equivalent resistance of the VFB pin is (60.4k//RFB), which is 30.2k where RFB is equal to 60.4k for a 1.2V output. Four phases connected in parallel equates to a worse case feedback current of 4 • IFB = 80nA maximum. The voltage error is 80nA • 30.2k = 2.4mV. If VOUTS2 is connected, as shown in Figure 2, to VOUT, and another 60.4k resistor is connected from VFB2 to ground, then the voltage error is reduced to 1.2mV. If the voltage error is acceptable then no additional connections are necessary. The onboard 60.4k resistor is 0.5% accurate and the VFB resistor can be chosen by the user to be as accurate as needed. All COMP pins are tied together for current sharing between the phases. The TRACK pins can be tied together and a single soft-start capacitor can be used to soft-start the regulator. The soft-start equation will need to have the soft-start current parameter increased by the number of paralleled channels. See the Output Voltage Tracking section. 

**==> picture [246 x 245] intentionally omitted <==**

**----- Start of picture text -----**<br>
4 PARALLELED OUTPUTS<br>COMP1 LTM4620 VOUT1 FOR 1.2V AT 50A<br>COMP2 VOUT2<br>60.4k VOUTS1<br>VOUTS2<br>OPTIONAL CONNECTION<br>VFB1<br>60.4k<br>TRACK1<br>VFB2<br>TR ACK2<br>OPTIONAL<br>RFB<br>COMP1 LTM4620 VOUT1 60.4k<br>COMP2 VOUT2<br>60.4k VOUTS1 USE TO LOWERTOTAL EQUIVALENT<br>VOUTS2 RESISTANCE TO LOWER<br>IFB VOLTAGE ERROR<br>VFB1<br>60.4k<br>TRACK1<br>VFB2<br>0.1µF TRACK2<br>RFB<br>4620 F02 60.4k<br>**----- End of picture text -----**<br>


**Figure 2. 4-Phase Parallel Configurations** 

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LTM4620 

## **APPLICATIONS INFORMATION** 

## **Input Capacitors** 

The LTM4620 module should be connected to a low AC-impedance DC source. For the regulator input four 22µF input ceramic capacitors are used for RMS ripple current.  A 47µF to 100µF surface mount aluminum electrolytic bulk capacitor can be used for more input bulk capacitance.  This bulk input capacitor is only needed if the input source impedance is compromised by long inductive leads, traces or not enough source capacitance. If low impedance power planes are used, then this bulk capacitor is not needed. 

For a buck converter, the switching duty-cycle can be estimated as: 

**==> picture [43 x 29] intentionally omitted <==**

Without considering the inductor current ripple, for each output, the RMS current of the input capacitor can be estimated as: 

**==> picture [159 x 31] intentionally omitted <==**

In the above equation, η % is the estimated efficiency of the power module. The bulk capacitor can be a switcherrated electrolytic aluminum capacitor, Polymer capacitor. 

## **Output Capacitors** 

The LTM4620 is designed for low output voltage ripple noise and good transient response. The bulk output capacitors defined as COUT are chosen with low enough effective series resistance (ESR) to meet the output voltage ripple and transient requirements. COUT can be a low ESR tantalum capacitor, the low ESR polymer capacitor or ceramic capacitor. The typical output capacitance range for each output is from 200µF to 470µF. Additional output filtering may be required by the system designer, if further reduction of output ripples or dynamic transient spikes is required. Table 4 shows a matrix of different output voltages and output capacitors to minimize the voltage droop and overshoot during a 7A/µs transient. The table optimizes total equivalent ESR and total bulk capacitance to optimize the transient performance. Stability criteria are considered in the Table 4 matrix, and LTpowerCAD will be provided for stability analysis. Multiphase operation will reduce effective output ripple as a function of the number of phases. Application Note 77 discusses this noise reduction versus output ripple current cancellation, but the output capacitance should be considered carefully as a function of stability and transient response. LTpowerCAD can calculate the output ripple reduction as the number of implemented phases increases by N times. A small value 10Ω to 50Ω resistor can be placed in series from VOUT to the VOUTS pin to allow for a bode plot analyzer to inject a signal into the control loop and validate the regulator stability. The same resistor could be placed in series from VOUT to DIFFP and a bode plot analyzer could inject a signal into the control loop and validate the regulator stability. 

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LTM4620 

## **APPLICATIONS INFORMATION** 

## **Burst Mode Operation** 

The LTM4620 is capable of Burst Mode operation on each regulator in which the power MOSFETs operate intermittently based on load demand, thus saving quiescent current. For applications where maximizing the efficiency at very light loads is a high priority, Burst Mode operation should be applied. Burst Mode operation is enabled with the MODE_PLLIN pin floating. During this operation, the peak current of the inductor is set to approximately one third of the maximum peak current value in normal operation even though the voltage at the COMP pin indicates a lower value. The voltage at the COMP pin drops when the inductor’s average current is greater than the load requirement. As the COMP voltage drops below 0.5V, the burst comparator trips, causing the internal sleep line to go high and turn off both power MOSFETs. 

In sleep mode, the internal circuitry is partially turned off, reducing the quiescent current to about 450µA for each output. The load current is now being supplied from the output capacitors. When the output voltage drops, causing COMP to rise above 0.5V, the internal sleep line goes low, and the LTM4620 resumes normal operation. The next oscillator cycle will turn on the top power MOSFET and the switching cycle repeats. Either regulator can be configured for Burst Mode operation. 

## **Pulse-Skipping Mode Operation** 

In applications where low output ripple and high efficiency at intermediate currents are desired, pulse-skipping mode should be used. Pulse-skipping operation allows the LTM4620 to skip cycles at low output loads, thus increasing efficiency by reducing switching loss. Tying the MODE_PLLIN pin to INTVCC enables pulseskipping operation. At light loads the internal current comparator may remain tripped for several cycles and force the top MOSFET to stay off for several cycles, thus skipping cycles. The inductor current does not reverse in this mode. This mode will maintain higher effective 

frequencies thus lower output ripple and lower noise than Burst Mode operation. Either regulator can be configured for pulse-skipping mode. 

## **Forced Continuous Operation** 

In applications where fixed frequency operation is more critical than low current efficiency, and where the lowest output ripple is desired, forced continuous operation should be used. Forced continuous operation can be enabled by tying the MODE_PLLIN pin to GND. In this mode, inductor current is allowed to reverse during low output loads, the COMP voltage is in control of the current comparator threshold throughout, and the top MOSFET always turns on with each oscillator pulse. During startup, forced continuous mode is disabled and inductor current is prevented from reversing until the LTM4620’s output voltage is in regulation. Either regulator can be configured for forced continuous mode. 

## **Multiphase Operation** 

For output loads that demand more than 13A of current, two outputs in LTM4620 or even multiple LTM4620s can be paralleled to run out of phase to provide more output current without increasing input and output voltage ripple. The MODE_PLLIN pin allows the LTM4620 to synchronize to an external clock (between 400kHz and 780kHz) and the internal phase-locked loop allows the LTM4620 to lock onto an incoming clock phase as well. The CLKOUT signal can be connected to the MODE_PLLIN pin of the following stage to line up both the frequency and the phase of the entire system. Tying the PHASMD pin to INTVCC, SGND, or (floating) generates a phase difference (between MODE_PLLIN and CLKOUT) of 120 degrees, 60 degrees, or 90 degrees respectively. A total of 12 phases can be cascaded to run simultaneously with respect to each other by programming the PHASMD pin of each LTM4620 channel to different levels. Figure 3 shows a 2-phase design, 4-phase design and a 6-phase design example for clock phasing with the PHASMD table. 

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LTM4620 

## **APPLICATIONS INFORMATION** 

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**----- Start of picture text -----**<br>
2-PHASE DESIGN<br>PHASMD SGND FLOAT INTVCC<br>FLOAT<br>CONTROLLER1 0 0 0<br>CLKOUT<br>CONTROLLER2 180 180 240<br>MODE_PLLIN<br>0 PHASE 180 PHASE CLKOUT 60 90 120<br>VOUT1 VO UT2<br>PHA SMD<br>4-PHASE DESIGN<br>90 DEGREE<br>CLKOUT CLKOUT<br>MODE_PLLIN MODE_PLLIN<br>0 PHASE 180 PHASE 90 PHASE 270 PHASE<br>VOUT1 VO UT2 VOUT1 VO UT2<br>FLOAT FLOAT<br>PHA SMD PHA SMD<br>6-PHASE DESIGN<br>60 DEGREE 60 DEGREE<br>CLKOUT CLKOUT CLKOUT<br>MODE_PLLIN MODE_PLLIN MODE_PLLIN<br>0 PHASE 180 PHASE 60 PHASE 240 PHASE 120 PHASE 300 PHASE<br>VOUT1 VO UT2 VOUT1 VO UT2 VOUT1 VO UT2<br>SGND SGND FLOAT<br>PHA SMD PHA SMD PHA SMD<br>4620 F03<br>**----- End of picture text -----**<br>


**Figure 3. Examples of 2-Phase, 4-Phase, and 6-Phase Operation with PHASMD Table** 

A multiphase power supply significantly reduces the amount of ripple current in both the input and output capacitors. The RMS input ripple current is reduced by, and the effective ripple frequency is multiplied by, the number of phases used (assuming that the input voltage is greater than the number of phases used times the output voltage). The output ripple amplitude is also reduced by the number of phases used when all of the outputs 

are tied together to achieve a single high output current design. 

The LTM4620 device is an inherently current mode controlled device, so parallel modules will have very good current sharing. This will balance the thermals on the design. Figure 26 shows an example of parallel operation and pin connection. 

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LTM4620 

## **APPLICATIONS INFORMATION** 

## **Input RMS Ripple Current Cancellation** 

Application Note 77 provides a detailed explanation of multiphase operation. The input RMS ripple current cancellation mathematical derivations are presented, and a graph is displayed representing the RMS ripple current reduction as a function of the number of interleaved phases. Figure 4 shows this graph. 

## **Frequency Selection and Phase-Locked Loop (MODE_PLLIN and fSET Pins)** 

The LTM4620 device is operated over a range of frequencies to improve power conversion efficiency. It is recommended to operate the lower output voltages or lower duty cycle conversions at lower frequencies to improve efficiency by lowering power MOSFET switching losses. Higher output voltages or higher duty cycle conversions can be operated at higher frequencies to limit inductor ripple current. The efficiency graphs will show an operating frequency chosen for that condition. 

**==> picture [307 x 290] intentionally omitted <==**

**----- Start of picture text -----**<br>
0.60<br>1-PHASE<br>0.55 2-PHASE<br>3-PHASE<br>4-PHASE<br>0.50 6-PHASE<br>0.45<br>0.40<br>0.35<br>0.30<br>0.25<br>0.20<br>0.15<br>0.10<br>0.05<br>0<br>0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 0.6 0.65 0.7 0.75 0.8 0.85 0.9<br>DUTY CYCLE (VOUT/VIN) 4620 F04<br>DC LOAD CURRENT<br>RMS INPUT RIPPLE CURRENT<br>**----- End of picture text -----**<br>


**Figure 4. Input RMS Current Ratios to DC Load Current as a Function of Duty Cycle** 

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LTM4620 

## **APPLICATIONS INFORMATION** 

**==> picture [161 x 160] intentionally omitted <==**

**----- Start of picture text -----**<br>
900<br>800<br>700<br>600<br>500<br>400<br>300<br>200<br>100<br>0<br>0 0.5 1 1.5 2 2.5<br>fSET PIN VOLTAGE (V)<br>4620 F05<br>FREQUENCY (kHz)<br>**----- End of picture text -----**<br>


**Figure 5. Operating Frequency vs fSET Pin Voltage** 

The LTM4620 switching frequency can be set with an external resistor from the fSET pin to SGND. An accurate 10µA current source into the resistor will set a voltage that programs the frequency or a DC voltage can be applied. Figure 5 shows a graph of frequency setting verses programming voltage. An external clock can be applied to the MODE_PLLIN pin from 0V to INTVCC over a frequency range of 400kHz to 780kHz. The clock input high threshold is 1.6V and the clock input low threshold is 1V. The LTM4620 has the PLL loop filter components on board. The frequency setting resistor should always be present to set the initial switching frequency before locking to an external clock.  Both regulators will operate in continuous mode while being externally clocked. 

The output of the PLL phase detector has a pair of complementary current sources that charge and discharge the internal filter network. When the external clock is applied, the fSET frequency resistor is disconnected with an internal switch, and the current sources control the frequency adjustment to lock to the incoming external clock. When no external clock is applied, then the internal switch is on, thus connecting the external fSET frequency set resistor for free run operation. 

## **Minimum On-Time** 

Minimum on-time tON is the smallest time duration that the LTM4620 is capable of turning on the top MOSFET on either channel. It is determined by internal timing delays, and the gate charge required to turn on the top MOSFET. Low duty cycle applications may approach this minimum on-time limit and care should be taken to ensure that: 

**==> picture [98 x 29] intentionally omitted <==**

If the duty cycle falls below what can be accommodated by the minimum on-time, the controller will begin to skip cycles. The output voltage will continue to be regulated, but the output ripple will increase. The on-time can be increased by lowering the switching frequency. A good rule of thumb is to keep on-time longer than 110ns. 

## **Output Voltage Tracking** 

Output voltage tracking can be programmed externally using the TRACK pins. The output can be tracked up and down with another regulator. The master regulator’s output is divided down with an external resistor divider that is the same as the slave regulator’s feedback divider to implement coincident tracking. The LTM4620 uses an accurate 60.4k resistor internally for the top feedback resistor for each channel. Figure 6 shows an example of coincident tracking. 

**==> picture [138 x 33] intentionally omitted <==**

VTRACK is the track ramp applied to the slave’s track pin. VTRACK has a control range of 0V to 0.6V, or the internal reference voltage. When the master’s output is divided down with the same resistor values used to set the slave’s output, then the slave will coincident track with the master until it reaches its final value. The master will continue to its final value from the slave’s regulation point. Voltage tracking is disabled when VTRACK is more than 0.6V. RTA in Figure 6 will be equal to the RFB for coincident tracking. Figure 7 shows the coincident tracking waveforms. 

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LTM4620 

## **APPLICATIONS INFORMATION** 

**==> picture [523 x 251] intentionally omitted <==**

**----- Start of picture text -----**<br>
INTVCC<br>C10 R2<br>4.7µF 10k<br>PGOOD<br>7V TO 16V INTERMEDIATE BUS MODE_PLLIN CLKOUT INTVCC EXTVCC PGOOD1<br>C422µF R1*10k C322µF C222µF C122µF R610k VIN VVOUTS1OUT1 C6100µF C8470µF V1.5V AT 13AOUT1<br>25V 25V 25V 25V SW1 6.3V 6.3V<br>TEMP<br>RU N 1 VFB1<br>RU N2 LTM4620 COMP1VFB2 RFB 40.2k<br>D1* TRACK1 60.4k<br>5.1V ZENER MASTER TRACK2 COMP2<br>C0.1µFSS R60.4kTB R60.4kTA fSET VVOUTS2OUT2 SLAVE C5 C7 V1.2V AT 13AOUT2<br>PHASMD SW2 PGOOD 100µF 470µF<br>1.5V R4 PGOO D2 6.3V 6.3V<br>121k<br>SGND GND DIFFP DIFFN DIFFOUT INTVCC<br>R9<br>10k<br>RAMP TIME<br>tSOFTSTART = (CSS/1.3µA) • 0.6V<br>* PULL-UP RESISTOR AND ZENER ARE OPTIONAL.<br>4620 F06<br>**----- End of picture text -----**<br>


**Figure 6. Example of Output Tracking Application Circuit** 

**==> picture [148 x 132] intentionally omitted <==**

**----- Start of picture text -----**<br>
MASTER OUTPUT<br>SLAVE OUTPUT<br>TIME<br>4620 F07<br>OUTPUT VOLTAGE<br>**----- End of picture text -----**<br>


**Figure 7. Output Coincident Tracking Waveform** 

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LTM4620 

## **APPLICATIONS INFORMATION** 

The TRACK pin can be controlled by a capacitor placed on the regulator TRACK pin to ground. A 1.3µA current source will charge the TRACK pin up to the reference voltage and then proceed up to INTVCC. After the 0.6V ramp, the TRACK pin will no longer be in control, and the internal voltage reference will control output regulation from the feedback divider. Foldback current limit is disabled during this sequence of turn-on during tracking or soft-starting. The TRACK pins are pulled low when the RUN pin is below 1.2V. The total soft-start time can be calculated as: 

**==> picture [137 x 31] intentionally omitted <==**

Regardless of the mode selected by the MODE_PLLIN pin, the regulator channels will always start in pulseskipping mode up to TRACK = 0.5V. Between TRACK = 0.5V and 0.54V, it will operate in forced continuous mode and revert to the selected mode once TRACK > 0.54V. In order to track with another channel once in steady state operation, the LTM4620 is forced into continuous mode operation as soon as VFB is below 0.54V regardless of the setting on the MODE_PLLIN pin. 

Ratiometric tracking can be achieved by a few simple calculations and the slew rate value applied to the master’s TRACK pin. As mentioned above, the TRACK pin has a control range from 0 to 0.6V. The master’s TRACK pin slew rate is directly equal to the master’s output slew rate in Volts/Time. The equation: 

**==> picture [80 x 26] intentionally omitted <==**

where MR is the master’s output slew rate and SR is the slave’s output slew rate in Volts/Time. When coincident tracking is desired, then MR and SR are equal, thus RTB is equal the 60.4k. RTA is derived from equation: 

**==> picture [136 x 45] intentionally omitted <==**

- where VFB is the feedback voltage reference of the regula tor, and VTRACK is 0.6V. Since RTB is equal to the 60.4k 

top feedback resistor of the slave regulator in equal slew rate or coincident tracking, then RTA is equal to RFB with VFB = VTRACK. Therefore RTB = 60.4k, and RTA = 60.4k in Figure 6. 

In ratiometric tracking, a different slew rate maybe desired for the slave regulator. RTB can be solved for when SR is slower than MR. Make sure that the slave supply slew rate is chosen to be fast enough so that the slave output voltage will reach it final value before the master output. 

For example, MR = 1.5V/1ms, and SR = 1.2V/1ms. Then RTB = 76.8k. Solve for RTA to equal to 49.9k. 

Each of the TRACK pins will have the 1.3µA current source on when a resistive divider is used to implement tracking on that specific channel. This will impose an offset on the TRACK pin input. Smaller values resistors with the same ratios as the resistor values calculated from the above equation can be used. For example, where the 60.4k is used then a 6.04k can be used to reduce the TRACK pin offset to a negligible value. 

## **Power Good** 

The PGOOD pins are open drain pins that can be used to monitor valid output voltage regulation. This pin monitors a ±10% window around the regulation point. A resistor can be pulled up to a particular supply voltage no greater than 6V maximum for monitoring. 

## **Stability Compensation** 

The module has already been internally compensated for all output voltages. Table 4 is provided for most application requirements. LTpowerCAD will be provided for other control loop optimization. 

## **Run Enable** 

The RUN pins have an enable threshold of 1.4V maximum, typically 1.25V with 150mV of hysteresis. They control the turn on each of the channels and INTVCC. These pins can be pulled up to VIN for 5V operation, or a 5V Zener diode can be placed on the pins and a 10k to 100k resistor can be placed up to higher than 5V input for enabling the channels. The RUN pins can also be used for output voltage sequencing. In parallel operation the RUN pins can be tie together 

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LTM4620 

## **APPLICATIONS INFORMATION** 

and controlled from a single control. See the Typical Application circuits in Figure 23. 

## **INTVCC and EXTVCC** 

The LTM4620 module has an internal 5V low dropout regulator that is derived from the input voltage. This regulator is used to power the control circuitry and the power MOSFET drivers. This regulator can source up to 70mA, and typically uses ~30mA for powering the device at the maximum frequency. This internal 5V supply is enabled by either RUN1 or RUN2. 

EXTVCC allows an external 5V supply to power the LTM4620 and reduce power dissipation from the internal low dropout 5V regulator. The power loss savings can be calculated by: 

**==> picture [137 x 12] intentionally omitted <==**

EXTVCC has a threshold of 4.7V for activation, and a maximum rating of 6V. When using a 5V input, connect this 5V input to EXTVCC also to maintain a 5V gate drive level. EXTVCC must sequence on after VIN, and EXTVCC must sequence off before VIN. 

## **Differential Remote Sense Amplifier** 

An accurate differential remote sense amplifier is provided to sense low output voltages accurately at the remote load points. This is especially true for high current loads. The amplifier can be used on one of the two channels, or on a single parallel output. It is very important that the DIFFP and DIFFN are connected properly at the output, and DIFFOUT is connected to either VOUTS1 or VOUTS2. In parallel operation, the DIFFP and DIFFN are connected properly at the output, and DIFFOUT is connected to one of the VOUTS pins. Review the parallel schematics in Figure 24 and review Figure 2. 

## **SW Pins** 

The SW pins are generally for testing purposes by monitoring these pins. These pins can also be used to dampen out switch node ringing caused by LC parasitic in the switched current paths. Usually a series R-C combination is used called a snubber circuit. The resistor will dampen the resonance and the capacitor is chosen to only affect the high frequency ringing across the resistor. If the stray 

inductance or capacitance can be measured or approximated then a somewhat analytical technique can be used to select the snubber values. The inductance is usually easier to predict. It combines the power path board inductance in combination with the MOSFET interconnect bond wire inductance. 

First the SW pin can be monitored with a wide bandwidth scope with a high frequency scope probe. The ring frequency can be measured for its value. The impedance Z can be calculated: 

**==> picture [65 x 14] intentionally omitted <==**

where f is the resonant frequency of the ring, and L is the total parasitic inductance in the switch path. If a resistor is selected that is equal to Z, then the ringing should be dampened. The snubber capacitor value is chosen so that its impedance is equal to the resistor at the ring frequency. Calculated by: Z(C) = 1/(2πfC). These values are a good place to start with. Modification to these components should be made to attenuate the ringing with the least amount of power loss. 

## **Temperature Monitoring (TEMP)** 

A diode connected PNP transistor is used for the TEMP monitor function by monitoring its voltage over temperature. The temperature dependence of this diode can be understood in the equation: 

**==> picture [76 x 30] intentionally omitted <==**

Where VT is the thermal voltage (kT/q), and n, the ideality factor is 1 for the two diode connected PNPs being used in the LTM4620. Since ID has an exponential temperature dependence that can be understood from the typical empirical equation for IS: 

## IS = I0 exp (–VG0/VT), 

Where Io is some process and geometry dependent current (Io is typically around 20 orders of magnitude larger than IS at room temperature, so Io is much larger than typical values of ID), and VG0 is the band gap voltage of 1.2V extrapolated to absolute zero of –273°C Kelvin. Figure 8 shows a plot of the diode temperature characteristic of 

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LTM4620 

## **APPLICATIONS INFORMATION** 

the diode connected PNP transistor biased with a 100µA current source. This plot would extend to the left back to 1.2V at –273°C Kelvin. This curve is stop at –55°C due to the test system limits. 

If we take the IS equation and substitute into the VD equation, then we get: 

**==> picture [164 x 30] intentionally omitted <==**

The expression shows that the junction voltage of the PNP connected diode decreases linearly if Io were constant from a value VG0 of 1.2V at absolute zero to a decreasing value with increased temperature. 

If we take this equation and differentiate it with respect to temperature T, then: 

**==> picture [172 x 27] intentionally omitted <==**

change as a function of temperature is the typical ~–2mV/°C. This equation is simplified for the first order derivation. 

Solving for T, T = –(VG0 – VD)/ dVD provide the temperature. 

1st Example: Figure 4 for 27°C, or 300°C Kelvin the diode voltage is 0.598V, thus, 300°C = –(1200mV – 598mV)/ –2mV/°C) 

2nd Example: Figure 4 for 75°C, or 350°C Kelvin the diode voltage is 0.50V, thus, 350°C = –(1200mV – 500mV)/ –2mV/°C) 

Converting the Kelvin scale to Celsius is simply taking the Kelvin temp and subtracting –273°C Kelvin from it. 

**==> picture [162 x 156] intentionally omitted <==**

**----- Start of picture text -----**<br>
0.8<br>ID = 100µA<br>0.7<br>0.6<br>0.5<br>0.4<br>0.3<br>–50 –25 0 25 50 75 100 125<br>TEMPERATURE (°C) 4620 F08<br>TEMP PIN DIODE VOLTAGE (V)<br>**----- End of picture text -----**<br>


**Figure 8. Diode Voltage VD vs Temperature T(°C) for Different Bias Currents** 

The diode connected PNP transistor can be pulled up to VIN with a resistor to set the current to 100µA for using this diode connected transistor as a general temperature monitor by monitoring the diode voltage drop with temperature. See Figure 24 for an example. 

## **Thermal Considerations and Output Current Derating** 

The thermal resistances reported in the Pin Configuration section of the data sheet are consistent with those parameters defined by JESD 51-12 and are intended for use with finite element analysis (FEA) software modeling tools that leverage the outcome of thermal modeling, simulation, and correlation to hardware evaluation performed on a µModule package mounted to a hardware test board defined by JESD 51-9 (“Test Boards for Area Array Surface Mount Package Thermal Measurements”). The motivation for providing these thermal coefficients is found in JESD 51-12 (“Guidelines for Reporting and Using Electronic Package Thermal Information”). 

A typical forward voltage is measured and placed in the electrical characteristics section of the data sheet, and Figure 8 is the plot of this forward voltage. Measure this forward voltage at 27°C to establish a reference point. Then use the above expression while measuring the forward voltage over temperature will provide a general temperature monitor. 

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LTM4620 

## **APPLICATIONS INFORMATION** 

Many designers may opt to use laboratory equipment and a test vehicle such as the demo board to anticipate the µModule regulator’s thermal performance in their application at various electrical and environmental operating conditions to compliment any FEA activities. Without FEA software, the thermal resistances reported in the Pin Configuration section are in-and-of themselves not relevant to providing guidance of thermal performance; instead, the derating curves provided in the data sheet can be used in a manner that yields insight and guidance pertaining to one’s application-usage, and can be adapted to correlate thermal performance to one’s own application. 

The Pin Configuration section gives four thermal coefficients explicitly defined in JESD 51-12; these coefficients are quoted or paraphrased below: 

1. θ JA, the thermal resistance from junction to ambient, is the natural convection junction-to-ambient air thermal resistance measured in a one cubic foot sealed enclosure. This environment is sometimes referred to as “still air” although natural convection causes the air to move.  This value is determined with the part mounted to a JESD 51-9 defined test board, which does not reflect an actual application or viable operating condition. 

2. θ JCbottom, the thermal resistance from junction to the bottom of the product case, is determined with all of the component power dissipation flowing through the bottom of the package. In the typical µModule, the bulk of the heat flows out the bottom of the package, but there is always heat flow out into the ambient environment. As a result, this thermal resistance value may be useful for comparing packages but the test conditions don’t generally match the user’s application. 

3. θ JCtop, the thermal resistance from junction to top of the product case, is determined with nearly all of the component power dissipation flowing through the top of the package. As the electrical connections of the typical µModule are on the bottom of the package, it is rare for an application to operate such that most of the heat flows from the junction to the top of the part. 

As in the case of θ JCbottom, this value may be useful for comparing packages but the test conditions don’t generally match the user’s application. 

4. θ JB, the thermal resistance from junction to the printed circuit board, is the junction-to-board thermal resistance where almost all of the heat flows through the bottom of the µModule and into the board, and is really the sum of the θ JCbottom and the thermal resistance of the bottom of the part through the solder joints and through a portion of the board. The board temperature is measured a specified distance from the package, using a two sided, two layer board. This board is described in JESD 51-9. 

A graphical representation of the aforementioned thermal resistances is given in Figure 9; blue resistances are contained within the µModule regulator, whereas green resistances are external to the µModule package. 

As a practical matter, it should be clear to the reader that no individual or sub-group of the four thermal resistance parameters defined by JESD 51-12 or provided in the Pin Configuration section replicates or conveys normal operating conditions of a µModule regulator. For example, in normal board-mounted applications, never does 100% of the device’s total power loss (heat) thermally conduct exclusively through the top or exclusively through bottom of the µModule package—as the standard defines for θ JCtop and θ JCbottom, respectively. In practice, power loss is thermally dissipated in both directions away from the package—granted, in the absence of a heat sink and airflow, a majority of the heat flow is into the board. 

Within the LTM4620, be aware there are multiple power devices and components dissipating power, with a consequence that the thermal resistances relative to different junctions of components or die are not exactly linear with respect to total package power loss. To reconcile this complication without sacrificing modeling simplicity— but also, not ignoring practical realities—an approach has been taken using FEA software modeling along with laboratory testing in a controlled-environment chamber to reasonably define and correlate the thermal resistance 

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LTM4620 

## **APPLICATIONS INFORMATION** 

values supplied in this data sheet: (1) Initially, FEA software is used to accurately build the mechanical geometry of the LTM4620 and the specified PCB with all of the correct material coefficients along with accurate power loss source definitions; (2) this model simulates a softwaredefined JEDEC environment consistent with JESD 51-12 to predict power loss heat flow and temperature readings at different interfaces that enable the calculation of the JEDEC-defined thermal resistance values; (3) the model and FEA software is used to evaluate the LTM4620 with heat sink and airflow; (4) having solved for and analyzed these thermal resistance values and simulated various operating conditions in the software model, a thorough laboratory evaluation replicates the simulated conditions with thermocouples within a controlled-environment chamber while operating the device at the same power loss as that which was simulated. An outcome of this process and due diligence yields a set of derating curves provided in other sections of this data sheet. After these laboratory tests have been performed, then the θ JB and 

θ BA are summed together to correlate quite well with the LTM4620 model with no airflow or heat sinking in a properly define chamber. This θ JB + θ BA value is shown in the Pin Configuration section and should accurately equal the θ JA value  because approximately 100% of power loss flows from the junction through the board into ambient with no airflow or top mounted heat sink. Each system has its own thermal characteristics, therefore thermal analysis must be performed by the user in a particular system. 

The LTM4620 has been designed to effectively remove heat from both the top and bottom of the package. The bottom substrate material has very low thermal resistance to the printed circuit board and the exposed top metal is thermally connected to the power devices and the power inductors. An external heat sink can be applied to the top of the device for excellent heat sinking with airflow. Basically all power dissipating devices are mounted directly to the substrate and the top exposed metal. This provides two low thermal resistance paths to remove heat. 

**==> picture [396 x 163] intentionally omitted <==**

**----- Start of picture text -----**<br>
JUNCTION-TO-AMBIENT RESISTANCE (JESD 51-9 DEFINED BOARD)<br>JUNCTION-TO-CASE (TOP) CASE (TOP)-TO-AMBIENT<br>RESISTANCE RESISTANCE<br>JUNCTION-TO-BOARD RESISTANCE<br>JUNCTION AMBIENT<br>JUNCTION-TO-CASE CASE (BOTTOM)-TO-BOARD BOARD-TO-AMBIENT<br>(BOTTOM) RESISTANCE RESISTANCE RESISTANCE<br>4620 F10<br>µMODULE DEVICE<br>**----- End of picture text -----**<br>


**Figure 9. Graphical Representation of JESD 51-12 Thermal Coefficients** 

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LTM4620 

## **APPLICATIONS INFORMATION** 

Figure 10 shows a modeled temperature plot of the LTM4620 with BGA heat sink and 200LFM airflow with 4.7W of internal dissipation. 

Figure 11 shows a modeled temperature plot of the LTM4620 with no heat sink and 200LFM airflow with 4.7W of internal dissipation. 

**Figure 10. LTM4620 12V to 1.2V at 26A with 200LFM, External Heat Sink** 

These plots equate to a paralleled 1.2V at 26A design operating at 86% efficiency. 

## **Safety Considerations** 

The LTM4620 modules do not provide isolation from VIN to VOUT. There is no internal fuse. If required, a slow blow fuse with a rating twice the maximum input current needs to be provided to protect each unit from catastrophic failure. 

The fuse or circuit breaker should be selected to limit the current to the regulator during overvoltage in case of an internal top MOSFET fault. If the internal top MOSFET fails, then turning it off will not resolve the overvoltage, thus the internal bottom MOSFET will turn on indefinitely trying to protect the load. Under this fault condition, the input voltage will source very large currents to ground through the failed internal top MOSFET and enabled internal bottom MOSFET. This can cause excessive heat and board damage depending on how much power the input voltage can deliver to this system. A fuse or circuit breaker can be used as a secondary fault protector in this situation. 

The device does support over current protection. A temperature diode is provided for monitoring internal temperature, and can be used to detect the need for thermal shutdown that can be done by controlling the RUN pin. 

## **Power Derating** 

**Figure 11. LTM4620 12V to 1.2V at 26A with 200LFM, No External Heat Sink** 

The 1.0V and 2.5V power loss curves in Figures 12 and 13 can be used in coordination with the load current derating curves in Figures 14 to 21 for calculating an approximate θ JA thermal resistance for the LTM4620 with various heat sinking and airflow conditions. The power loss curves are taken at room temperature, and are increased with a 1.35 to 1.4 multiplicative factor at 125°C. These factors come from the fact that the power loss of the regulator increases about 45% from 25°C to 150°C, thus a 50% spread over 

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LTM4620 

## **APPLICATIONS INFORMATION** 

125°C delta equates to ~0.35%/°C loss increase. A 125°C maximum junction minus 25°C room temperature equates to a 100°C increase. This 100°C increase multiplied by 0.35%/°C equals a 35% power loss increase at the 125°C junction, thus the 1.35 multiplier. 

The derating curves are plotted with VOUT1 and VOUT2 in parallel single output operation starting at 26A of load with low ambient temperature. The output voltages are 1.0V and 2.5V. These are chosen to include the lower and higher output voltage ranges for correlating the thermal resistance. Thermal models are derived from several temperature measurements in a controlled temperature chamber along with thermal modeling analysis. 

The junction temperatures are monitored while ambient temperature is increased with and without airflow. The power loss increase with ambient temperature change is factored into the derating curves. The junctions are maintained at ~120°C maximum while lowering output current or power while increasing ambient temperature. The decreased output current will decrease the internal module loss as ambient temperature is increased. 

The monitored junction temperature of 120°C minus the ambient operating temperature specifies how much temperature rise can be allowed. As an example in Figure 14, the load current is derated to ~19A at ~80°C with no air or heat sink and the power loss for the 12V to 1.0V at 19A output is a ~5.1W loss. The 5.1W loss is calculated with the ~3.75W room temperature loss from the 12V to 1.0V power loss curve at 19A, and the 1.35 multiplying factor at 125°C ambient. If the 80°C ambient temperature is subtracted from the 120°C junction temperature, then the difference of 40°C divided by 5.1W equals a 7.8°C/W θ JA thermal resistance. Table 2 specifies a 6.5 to 7°C/W value which is pretty close. The airflow graphs are more 

accurate due to the fact that the ambient temperature environment is controlled better with airflow. As an example in Figure 15, the load current is derated to ~22A at ~90°C with 200LFM of airflow and the power loss for the 12V to 1.0V at 22A output is a ~5.94W loss. 

The 5.94W loss is calculated with the ~4.4W room temperature loss from the 12V to 1.0V power loss curve at 22A, and the 1.35 multiplying factor at 125°C ambient. If the 90°C ambient temperature is subtracted from the 120°C junction temperature, then the difference of 30°C divided by 5.94W equals a 5.1°C/W θ JA thermal resistance. Table 2 specifies a 5.5°C/W value which is pretty close. Tables 2 and 3 provide equivalent thermal resistances for 1.0V and 2.5V outputs with and without airflow and heat sinking. 

The derived thermal resistances in Tables 2 and 3 for the various conditions can be multiplied by the calculated power loss as a function of ambient temperature to derive temperature rise above ambient, thus maximum junction temperature. Room temperature power loss can be derived from the efficiency curves and adjusted with the above ambient temperature multiplicative factors. The printed circuit board is a 1.6mm thick four layer board with two ounce copper for the two outer layers and one ounce copper for the two inner layers. The PCB dimensions are 101mm × 114mm. The BGA heat sinks are listed in Table 3. 

## **Layout Checklist/Example** 

The high integration of LTM4620 makes the PCB board layout very simple and easy. However, to optimize its electrical and thermal performance, some layout considerations are still necessary. 

- Use large PCB copper areas for high current paths, including VIN, GND, VOUT1 and VOUT2. It helps to minimize the PCB conduction loss and thermal stress. 

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## **APPLICATIONS INFORMATION** 

## **Table 2. 1.0V Output** 

|**Table 2. 1.0V Output**|||||||
|---|---|---|---|---|---|---|
|**DERATING CURVE**|**VIN (V)**|**POWER LOSS CURVE**|**AIRFLOW(LFM)**|**HEAT SINK**|**LGA**<br>θ**JA (°C/W)**|**BGA**<br>θ**JA (°C/W)**|
|Figures 14,15|5,12|Figure 12|0|None|6.5 to 7|6.5 to 7|
|Figures 14,15|5,12|Figure 12|200|None|5.5|5.5|
|Figures 14,15|5,12|Figure 12|400|None|5|5|
|Figures 16,17|5,12|Figure 12|0|BGA Heat Sink|6.5|6.5|
|Figures 16,17|5,12|Figure 12|200|BGA Heat Sink|5|5|
|Figures 16,17|5,12|Figure 12|400|BGA Heat Sink|4|4|



**Table 3. 2.5V Output** 

|**Table 3. 2.5V Output**|||||||||
|---|---|---|---|---|---|---|---|---|
|**DERATING CURVE**|**VIN (V)**||**POWER LOSS CURVE**|**AIRFLOW(LFM)**||**HEAT SINK**|**LGA**<br>θ**JA (°C/W)**|**BGA**<br>θ**JA (°C/W)**|
|Figures 18,19|5,12||Figure 13|0||None|6.5 to 7|6.5 to 7|
|Figures 18,19|5,12||Figure 13|200||None|5.5 to 6|5.5 to 6|
|Figures 18,19|5,12||Figure 13|400||None|4.5|4.5|
|Figures 20,21|5,12||Figure 13|0||BGA Heat Sink|6.5 to 7|6.5 to 7|
|Figures 20,21|5,12||Figure 13|200||BGA Heat Sink|4|4|
|Figures 20,21|5,12||Figure 13|400||BGA Heat Sink|3.5|3.5|
|**HEAT SINK MANUFACTURER**<br>**PART NUMBER**<br>**WEBSITE**<br>Aavid Thermalloy<br>375424B00034G<br>www.aavid.com<br>Cool Innovations<br>4-050503P to 4-050508P<br>www.coolinnovations.com|||||||||
|**HEAT SINK MANUFACTURER**||**PART NUMBER**|||**WEBSITE**||||
|Aavid Thermalloy||375424B00034G|||www.aavid.com||||
|Cool Innovations||4-050503P to 4-050508P|||www.coolinnovations.com||||



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## **APPLICATIONS INFORMATION** 

**Table 4. Output Voltage Response vs Component Matrix (Refer to Figure 23) 0A to 7A Load Step Typical Measured Values** 

|**VENDORS**|**VALUE**|**PART NUMBER**|
|---|---|---|
|TDK,COUT1Ceramic|100µF 6.3V|C4532X5R0J107MZ|
|Murata,COUT1Ceramic|100µF 6.3V|GRM32ER60J107M|
|AVX, COUT1Ceramic|100µF 6.3V|18126D107MAT|
|Sanyo POSCAP, COUT2Bulk|470µF 4V|4TPF470ML|
|Sanyo POSCAP, COUT2Bulk|470µF 6.3V|6TPD470M|
|Sanyo, CINBulk|56µF 25V|25SVP56M|



|**VOUT**<br>**(V)**|**CIN**<br>**(CERAMIC)**|**CIN**<br>**(BULK)****|**COUT1**<br>**(CERAMIC)**|**COUT2**<br>**(BULK)**|**CFF**<br>**(pF)**|**CBOT**<br>**(pF)**|**CCOMP**<br>**(pF)**|**VIN**<br>**(V)**|**DROOP**<br>**(mV)**|**P-P**<br>**DEVIATION**<br>**AT 7A LOAD**<br>**STEP(mV)**|**RECOVERY**<br>**TIME**<br>**(µs)**|<br>**LOAD**<br>**STEP**<br>**(A/µs)**|**RFB**<br>**(kΩ)**|**FREQ**|
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|1|22µF × 3|56µF|100µF|470µF × 2|100|None|None|5|65|130|30|7|90.9|400|
|1|22µF × 3|56µF|100µF|470µF × 2|100|None|None|12|65|130|30|7|90.9|400|
|1|22µF × 3|56µF|100µF × 3|470µF × 2|100|None|None|5|60|120|30|7|90.9|400|
|1|22µF × 3|56µF|100µF × 3|470µF × 2|100|None|None|12|60|120|30|7|90.9|400|
|1.2|22µF × 3|56µF|100µF × 3|470µF × 2|100|None|None|5|65|130|30|7|60.4|500|
|1.2|22µF × 3|56µF|100µF × 3|470µF × 2|100|None|None|12|65|130|30|7|60.4|500|
|1.2|22µF × 3|56µF|100µF|470µF × 2|100|None|None|5|68|136|35|7|60.4|500|
|1.2|22µF × 3|56µF|100µF|470µF × 2|100|None|None|12|68|136|30|7|60.4|500|
|1.5|22µF × 3|56µF|100µF|470µF × 2|100|None|None|5|70|140|35|7|40.2|550|
|1.5|22µF × 3|56µF|100µF|470µF × 2|100|None|None|12|70|140|30|7|40.2|550|
|1.8|22µF × 3|56µF|100µF|470µF|100|None|None|5|75|150|30|7|30.2|600|
|1.8|22µF × 3|56µF|100µF|470µF|100|None|None|12|75|150|30|7|30.2|600|
|1.8|22µF × 3|56µF|100µF × 3|None|150|None|None|5|100|200|15|7|30.2|600|
|1.8|22µF × 3|56µF|100µF × 3|None|150|None|None|12|100|200|18|7|30.2|600|
|2.5|22µF × 3|56µF|100µF × 3|None|220|None|None|5|100|200|20|7|19.1|750|
|2.5|22µF × 3|56µF|100µF × 3|None|220|None|None|12|100|200|20|7|19.1|750|
|2.5|22µF × 3|56µF|100µF|470µF|150|None|None|5|85|170|30|7|19.1|750|
|2.5|22µF × 3|56µF|100µF|470µF|150|None|None|12|85|170|30|7|19.1|750|



**Bulk capacitance is optional if VIN has very low input impedance. 

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LTM4620 

## **APPLICATIONS INFORMATION** 

**==> picture [364 x 575] intentionally omitted <==**

**----- Start of picture text -----**<br>
6 9<br>5VIN, 1VOUT 5VIN, 2.5VOUT<br>12VIN, 1VOUT 8 12VIN, 2.5VOUT<br>5<br>7<br>4 6<br>5<br>3<br>4<br>2 3<br>2<br>1<br>1<br>0 0<br>0 2 4 6 8 10 12 14 16 18 20 22 24 26 0 2 4 6 8 10 12 14 16 18 20 22 24 26<br>LOAD CURRENT (A) LOAD CURRENT (A)<br>4620 F12 4620 F13<br>Figure 12. 1.0V Power Loss Curve Figure 13. 2.5V Power Loss Curve<br>26 26<br>24 24<br>22 22<br>20 20<br>18 18<br>16 16<br>14 14<br>12 12<br>10 10<br>8 8<br>6 6<br>4 400LFM 4 400LFM<br>200LFM 200LFM<br>2 2<br>0LFM 0LFM<br>0 0<br>0 20 40 60 80 100 120 0 20 40 60 80 100 120<br>AMBIENT TEMPERATURE (°C) AMBIENT TEMPERATURE (°C)<br>4620 F14 4620 F15<br>Figure 14. 12V to 1V Derating  Figure 15. 5V to 1V Derating<br>Curve, No Heat Sink Curve, No Heat Sink<br>26 26<br>24 24<br>22 22<br>20 20<br>18 18<br>16 16<br>14 14<br>12 12<br>10 10<br>8 8<br>6 6<br>4 400LFM 4 400LFM<br>200LFM 200LFM<br>2 2<br>0LFM 0LFM<br>0 0<br>0 20 40 60 80 100 120 0 20 40 60 80 100 120<br>AMBIENT TEMPERATURE (°C) AMBIENT TEMPERATURE (°C)<br>4620 F16 4620 F17<br>POWER LOSS (W) POWER LOSS (W)<br>LOAD CURRENT (A)<br>CH1 AND CH2 COMBINED LOAD CURRENT (A)<br>**----- End of picture text -----**<br>


**==> picture [159 x 361] intentionally omitted <==**

**----- Start of picture text -----**<br>
26<br>24<br>22<br>20<br>18<br>16<br>14<br>12<br>10<br>8<br>6<br>4 400LFM<br>200LFM<br>2<br>0LFM<br>0<br>0 20 40 60 80 100 120<br>AMBIENT TEMPERATURE (°C)<br>4620 F14<br>Figure 14. 12V to 1V Derating<br>Curve, No Heat Sink<br>26<br>24<br>22<br>20<br>18<br>16<br>14<br>12<br>10<br>8<br>6<br>4 400LFM<br>200LFM<br>2<br>0LFM<br>0<br>0 20 40 60 80 100 120<br>AMBIENT TEMPERATURE (°C)<br>LOAD CURRENT (A)<br>LOAD CURRENT (A)<br>**----- End of picture text -----**<br>


**Figure 16. 12V to 1V Derating Curve, BGA Heat Sink** 

**Figure 17. 5V to 1V Derating Curve, BGA Heat Sink** 

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LTM4620 

## **APPLICATIONS INFORMATION** 

**==> picture [368 x 371] intentionally omitted <==**

**----- Start of picture text -----**<br>
26 26<br>24 24<br>22 22<br>20 20<br>18 18<br>16 16<br>14 14<br>12 12<br>10 10<br>8 8<br>6 6<br>4 400LFM 4 400LFM<br>2 200LFM 2 200LFM<br>0LFM 0LFM<br>0 0<br>0 20 40 60 80 100 120 0 20 40 60 80 100 120<br>AMBIENT TEMPERATURE (°C) AMBIENT TEMPERATURE (°C)<br>4620 F18 4620 F19<br>Figure 18. 12V to 2.5V Derating  Figure 19. 5V to 2.5V Derating<br>Curve, No Heat Sink Curve, No Heat Sink<br>26 26<br>24 24<br>22 22<br>20 20<br>18 18<br>16 16<br>14 14<br>12 12<br>10 10<br>8 8<br>6 6<br>4 400LFM 4 400LFM<br>200LFM 200LFM<br>2 2<br>0LFM 0LFM<br>0 0<br>0 20 40 60 80 100 120 0 20 40 60 80 100 120<br>AMBIENT TEMPERATURE (°C) AMBIENT TEMPERATURE (°C)<br>4620 F20 4620 F21<br>LOAD CURRENT (A) LOAD CURRENT (A)<br>LOAD CURRENT (A) LOAD CURRENT (A)<br>**----- End of picture text -----**<br>


**Figure 20. 12V to 2.5V Derating Curve, BGA Heat Sink** 

**Figure 21. 5V to 2.5V Derating Curve, BGA Heat Sink** 

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LTM4620 

## **APPLICATIONS INFORMATION** 

- Place high frequency ceramic input and output capacitors next to the VIN, PGND and VOUT pins to minimize high frequency noise. 

- Place a dedicated power ground layer underneath the unit. 

- To minimize the via conduction loss and reduce module thermal stress, use multiple vias for interconnection between top layer and other power layers. 

- Do not put via directly on the pad, unless they are capped or plated over. 

- Use a separated SGND ground copper area for components connected to signal pins. Connect the SGND to GND underneath the unit. 

- For parallel modules, tie the VOUT, VFB, and COMP pins together. Use an internal layer to closely connect these pins together. The TRACK pin can be tied a common capacitor for regulator soft-start. 

- Bring out test points on the signal pins for monitoring. 

- Figure 22 gives a good example of the recommended layout. 

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LTM4620 

## **APPLICATIONS INFORMATION** 

## **LGA** 

**==> picture [260 x 247] intentionally omitted <==**

**----- Start of picture text -----**<br>
CIN1 CIN2<br>VIN<br>M<br>L<br>K<br>GND J GND<br>H<br>G<br>SGND<br>F<br>COUT1 COUT2<br>E<br>D<br>C<br>B<br>A<br>1 2 3 4 5 6 7 8 9 10 11 12<br>VOUT1 GND VOUT2<br>4620 F22a<br>CNTRL<br>**----- End of picture text -----**<br>


## **BGA** 

**==> picture [260 x 246] intentionally omitted <==**

**----- Start of picture text -----**<br>
CIN1 CIN2<br>VIN<br>M<br>L<br>K<br>GND J GND<br>H<br>G<br>SGND<br>F<br>COUT1 COUT2<br>E<br>D<br>C<br>B<br>A<br>1 2 3 4 5 6 7 8 9 10 11 12<br>VOUT1 GND VOUT2<br>4620 F22b<br>CNTRL<br>**----- End of picture text -----**<br>


**Figure 22. Recommended PCB Layout** 

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LTM4620 

## **TYPICAL APPLICATIONS** 

**==> picture [240 x 588] intentionally omitted <==**

**----- Start of picture text -----**<br>
OUT1<br>V 1.5V AT 13A<br>OUT2<br>C 470µF 6.3V<br>4620 F23<br>+ CBOT SEE TABLE 4**<br>OUT2<br>COUT1 100µF 6.3V V 1.2V AT 13A COUT2 470µF 6.3V<br>*<br>FB1<br>* R 40.2k +<br>FF<br>C<br>*<br>RFB2 60.4k COUT1 100µF 6.3V<br>**<br>COMP PGOOD2<br>C CC R3 10k<br>PGOOD1 INTV<br>CC R2 10k VOUT1 OUTS1 SW1 VFB1 VFB2 OUTS2 VOUT2 SW2<br>V COMP1 COMP2 V<br>INTV PGOOD1 PGOOD2 DIFFOUT<br>CC<br>C10 4.7µF EXTV DIFFN<br>CC<br>INTV<br>LTM4620 DIFFP<br>CLKOUT<br>GND<br>VIN TEMP RUN1 RUN2 TRACK1 TRACK2 fSET PHASMD SGND<br>MODE_PLLIN<br>R7 10k<br>R4 121k<br>C1 22µF 25V<br>TRACK2 C9 0.1µF<br>C2 22µF 25V<br>TRACK1 C5 0.1µF<br>C3 22µF 25V<br>5V TO 16V INTERMEDIATE BUS<br>D1* 5.1V ZENER<br>R1* 10k<br>* PULL-UP RESISTOR AND ZENER ARE OPTIONAL.<br>C4 22µF 25V<br>IN<br>C (OPT)<br>+<br>**----- End of picture text -----**<br>


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LTM4620 

## **TYPICAL APPLICATIONS** 

**==> picture [274 x 530] intentionally omitted <==**

**----- Start of picture text -----**<br>
1.5V AT 26A<br>4620 F24<br>OUT2 OUT2<br>C 470µF 6.3V C 470µF 6.3V<br>+ +<br>OUT1 OUT1<br>C 100µF 6.3V C 100µF 6.3V<br>PGOOD1 R5 40.2k<br>PGOOD1<br>2 2<br>CC R2 5k VOUT1 OUTS1 SW1 VFB1 VFB2 OUTS2 V OUT2 S W D<br>V COMP1 COMP2 V<br>INTV PGOOD1 PGOO DIFFOUT<br>CC<br>C10 4.7µF EXTV DIFFN<br>CC<br>INTV<br>LTM4620 DIFFP<br>CC<br>INTV CLKOUT<br>GND<br>= RT<br>1 2<br>ACK1 SGND<br>VIN TEMP RUN RUN TR TRACK2 fSET PHASMD<br> – 0.6V MODE_PLLIN<br>IN 100µA<br>V<br>IN<br>V<br>R4 121k<br>C1 22µF 25V<br>C9 0.1µF<br>C2 22µF 25V<br>A/D TRACK1<br>C11 22µF 25V<br>5V TO 16V INTERMEDIATE BUS<br>C3 22µF 25V<br>D1* 5.1V ZENER<br>R1* 10k<br>* PULL-UP RESISTOR AND ZENER ARE OPTIONAL.<br>**----- End of picture text -----**<br>


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LTM4620 

## **TYPICAL APPLICATIONS** 

**==> picture [269 x 595] intentionally omitted <==**

**----- Start of picture text -----**<br>
OUT1 OUT2<br>V 1.2V AT 13A V 1V AT 13A<br>COUT2 470µF 6.3V 4620 F25<br>OUT2<br>C 470µF 6.3V<br>+<br>+<br>OUT1<br>C 100µF 6.3V<br>COUT1 100µF 6.3V<br>R5 60.4k<br>R8 90.9k PGOOD2<br>PGOOD1 CC R3 10k<br>INTV<br>2<br>CC R2 10k VO UT1 OUTS1 SW1 VFB1 VFB2 OUTS2 VOUT2 SW2 D<br>V COMP1 COMP2 V<br>INTV PGOOD1 PGOO DIFFOUT<br>CC<br>C10 4.7µF EXTV DIFFN<br>CC<br>INTV<br>LTM4620 DIFFP<br>CLKOUT<br>GND<br>SGND<br>V IN TEMP UN1 R RUN2 TRACK1 TRACK2 fSET PHASMD<br>MODE_PLLIN<br>R6 10k<br>R4 121k Figure 25. LTM4620 1.2V and 1V Output Tracking<br>C1 22µF 25V<br>R7 90.9k<br>C2 22µF 25V<br>R9 60.4k<br>1.2V<br>C3 22µF 25V C5 0.1µF<br>INTERMEDIATE BUS<br>R1* 10k<br>* PULL-UP RESISTOR AND ZENER ARE OPTIONAL.<br>C4 22µF 25V D1* 5.1V ZENER<br>IN<br>V<br>5V TO 16V<br>**----- End of picture text -----**<br>


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LTM4620 

## **TYPICAL APPLICATIONS** 

**==> picture [514 x 416] intentionally omitted <==**

**----- Start of picture text -----**<br>
INTVCC<br>C10 R2<br>CLK1 4.7µF 5k<br>PGOOD1<br>INTERMEDIATE BUS MODE_PLLIN CLKOUT INTVCC EXTVCC PGOOD1<br>5V TO 16VVIN R1*10k C322µF C222µF C122µF R610k VIN VVOUTS1OUT1 100µFCOUT1 + C470µFOUT2<br>25V 25V 25V TEMP SW1 6.3V 6.3V<br>RUN VFB1 VFB<br>RUN1<br>VFB2 R5<br>RUN 2 LTM4620 60.4k<br>COMP1<br>D1* TRACK1 TRACK 1<br>5.1V ZENER COMP2 COMP<br>TRACK2<br>VOUTS2<br>fSET VOUT2<br>R4 P H ASMD S W2 C100µFOUT1 + C470µFOUT2<br>121k PGOO D2 PGOOD1 6.3V 6.3V<br>SGND GND DIFFP DIFFN DIFFOUT<br>VOUT<br>1.2V AT 50A<br>C16<br>CLK1 4.7µF PGOOD1<br>5V TO 16V INTERMEDIATE BUS MODE_PLLIN CLKOUT INTVCC EXTVCC PGOOD1<br>C1222µF C1522µF C522µF R910k VIN VVOUTS1OUT1 C100µFOUT1 + C470µFOUT2<br>25V 25V 25V TEM P SW1 6.3V 6.3V<br>RUN1 R UN1 VFB1 VFB<br>RUN2 LTM4620 VFB2<br>TRACK1 TR A CK1 COMP1 COMP<br>TRACK 2 COMP2<br>C19 VOUTS2<br>0.22µF fSET VOUT2<br>P H ASMD S W2 C100µFOUT1 + C470µFOUT2<br>R10 PGOO D2 PGOOD1 6.3V 6.3V<br>121k<br>SGND GND DIFFP DIFFN DIFFOUT<br>* PULL-UP RESISTOR AND ZENER ARE OPTIONAL. INTVCC 4620 F26<br>**----- End of picture text -----**<br>


**Figure 26. 4-Phase, 1.2V at 50A** 

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LTM4620 

## **PACKAGE DESCRIPTION** 

**==> picture [35 x 31] intentionally omitted <==**

## **PACKAGE ROW AND COLUMN LABELING MAY VARY AMONG µModule PRODUCTS. REVIEW EACH PACKAGE LAYOUT CAREFULLY.** 

## **LTM4620 Component LGA Pinout** 

|**PIN ID**|**FUNCTION**|**PIN ID**|**FUNCTION**|**PIN ID**|**FUNCTION**|**PIN ID**|**FUNCTION**|**PIN ID**|**FUNCTION**|**PIN ID**|**FUNCTION**|
|---|---|---|---|---|---|---|---|---|---|---|---|
|A1|VOUT1|B1|VOUT1|C1|VOUT1|D1|GND|E1|GND|F1|GND|
|A2|VOUT1|B2|VOUT1|C2|VOUT1|D2|GND|E2|GND|F2|GND|
|A3|VOUT1|B3|VOUT1|C3|VOUT1|D3|GND|E3|GND|F3|GND|
|A4|VOUT1|B4|VOUT1|C4|VOUT1|D4|GND|E4|GND|F4|MODE_PLLIN|
|A5|VOUT1|B5|VOUT1|C5|VOUT1S|D5|VFB1|E5|TRACK1|F5|RUN1|
|A6|GND|B6|GND|C6|fSET|D6|SGND|E6|COMP1|F6|SGND|
|A7|GND|B7|GND|C7|SGND|D7|VFB2|E7|COMP2|F7|SGND|
|A8|VOUT2|B8|VOUT2|C8|VOUT2S|D8|TRACK2|E8|DIFFP|F8|DIFFOUT|
|A9|VOUT2|B9|VOUT2|C9|VOUT2|D9|GND|E9|DIFFN|F9|RUN2|
|A10|VOUT2|B10|VOUT2|C10|VOUT2|D10|GND|E10|GND|F10|GND|
|A11|VOUT2|B11|VOUT2|C11|VOUT2|D11|GND|E11|GND|F11|GND|
|A12|VOUT2|B12|VOUT2|C12|VOUT2|D12|GND|E12|GND|F12|GND|
|||||||||||||
|**PIN ID**|**FUNCTION**|**PIN ID**|**FUNCTION**|**PIN ID**|**FUNCTION**|**PIN ID**|**FUNCTION**|**PIN ID**|**FUNCTION**|**PIN ID**|**FUNCTION**|
|G1|GND|H1|GND|J1|GND|K1|GND|L1|GND|M1|GND|
|G2|SW1|H2|GND|J2|VIN|K2|VIN|L2|VIN|M2|VIN|
|G3|GND|H3|GND|J3|VIN|K3|VIN|L3|VIN|M3|VIN|
|G4|PHASMD|H4|GND|J4|VIN|K4|VIN|L4|VIN|M4|VIN|
|G5|CLKOUT|H5|GND|J5|GND|K5|GND|L5|VIN|M5|VIN|
|G6|SGND|H6|GND|J6|TEMP|K6|GND|L6|VIN|M6|VIN|
|G7|SGND|H7|GND|J7|EXTVCC|K7|GND|L7|VIN|M7|VIN|
|G8|PGOOD2|H8|INTVCC|J8|GND|K8|GND|L8|VIN|M8|VIN|
|G9|PGOOD1|H9|GND|J9|VIN|K9|VIN|L9|VIN|M9|VIN|
|G10|GND|H10|GND|J10|VIN|K10|VIN|L10|VIN|M10|VIN|
|G11|SW2|H11|GND|J11|VIN|K11|VIN|L11|VIN|M11|VIN|
|G12|GND|H12|GND|J12|GND|K12|GND|L12|GND|M12|GND|



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LTM4620 

## **PACKAGE DESCRIPTION** 

## **Please refer to http://www.linear.com/product/LTM4620#packaging for the most recent package drawings.** 

**==> picture [485 x 615] intentionally omitted <==**

**----- Start of picture text -----**<br>
7<br>SEE NOTES<br>DIA 0.630 PAD 1<br>M L K J H G F E D C B A LGA 144 1112 REV C<br>DETAIL A 12<br>3<br>b 4<br>5<br>6<br>G<br>7<br>8 µModule<br>e PACKAGE BOTTOM VIEW LTMXXXXXX<br>9 PACKAGE IN TRAY LOADING ORIENTATION<br>PACKAGE ROW AND COLUMN LABELING MAY VARY  AMONG µModule PRODUCTS. REVIEW EACH PACKAGE  LAYOUT CAREFULLY<br>3x, C (0.22 x45°) 10 !<br>11 DETAILS OF PAD #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE PAD #1 IDENTIFIER MAY BE EITHER A MOLD OR  MARKED FEATURE<br>b e 12 NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994 2. ALL DIMENSIONS ARE IN MILLIMETERS 3        LAND DESIGNATION PER JESD MO-222, SPP-010 4 5. PRIMARY DATUM -Z- IS SEATING PLANE 6. THE TOTAL NUMBER OF PADS: 144 7 COMPONENT PIN “A1” TRAY PIN 1 BEVEL<br>F PADS 3<br>SEE NOTES<br>NOTES<br> 4.41mm) A<br>× DETAIL B<br> 15mm  MAX 4.51 0.66 0.46 4.05 0.15 0.10 0.05<br>×<br>H1 YX NOM 4.41 0.63 15.00 15.00 1.27 13.97 13.97 0.41 4.00<br>LGA Package SUBSTRATE S DIMENSIONS<br>eee<br>MIN 4.31 0.60 0.36 3.95<br>MOLD CAP H2 DETAIL B DETAIL A<br>TOTAL NUMBER OF LGA PADS: 144<br>144-Lead (15mm  (Reference LTC DWG # 05-08-1844 Rev C) A b D E e F G H1 H2 aaa bbb eee<br>0.630 ±0.025 SQ. 143x SYMBOL<br>aaa  Z<br>Y E<br>X<br>D<br>TOP VIEW<br>PACKAGE TOP VIEW<br>SUGGESTED PCB LAYOUT<br>aaa  Z PAD 1 CORNER 4 6.9850 5.7150 4.4450 3.1750 1.9050 0.6350 0.0000 0.6350 1.9050 3.1750 4.4450 5.7150 6.9850<br>Z<br>Zbbb<br>6.9850<br>5.7150<br>4.4450<br>3.1750<br>1.9050<br>0.6350<br>0.0000<br>0.6350<br>1.9050<br>3.1750<br>4.4450<br>5.7150<br>6.9850<br>**----- End of picture text -----**<br>


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LTM4620 

## **PACKAGE DESCRIPTION** 

## **Please refer to http://www.linear.com/product/LTM4620#packaging for the most recent package drawings.** 

**==> picture [466 x 610] intentionally omitted <==**

**----- Start of picture text -----**<br>
7<br>SEE NOTES<br>PIN 1<br>M L K J H G F E D C B A<br>1<br>DETAIL A 2<br>3<br>b 4<br>5<br>6<br>G<br>7<br>8<br>e PACKAGE BOTTOM VIEW<br>9<br>LTMXXXXXX µModule<br>10<br>PACKAGE ROW AND COLUMN LABELING MAY VARY  AMONG µModule PRODUCTS. REVIEW EACH PACKAGE  LAYOUT CAREFULLY<br>11<br>!<br>12 DETAILS OF PIN #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE PIN #1 IDENTIFIER MAY BE EITHER A MOLD OR  MARKED FEATURE<br>NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994 2. ALL DIMENSIONS ARE IN MILLIMETERS 3        BALL DESIGNATION PER JESD MS-028 AND JEP95 4 5. PRIMARY DATUM -Z- IS SEATING PLANE 6. SOLDER BALL COMPOSITION CAN BE 96.5% Sn/3.0% Ag/0.5% Cu  OR Sn Pb EUTECTIC 7 BEVEL<br>b e 3 PIN “A1” TRAY PIN 1<br>F COMPONENT<br>SEE NOTES<br>Z<br>5.01mm) A A2 NOTES BALL HT BALL DIMENSION PAD DIMENSION SUBSTRATE THK MOLD CAP HT<br>× DETAIL B<br>15mm  PACKAGE SIDE VIEW MAX 5.21 0.70 4.51 0.90 0.66 0.46 4.05 0.15 0.10 0.20 0.30 0.15<br>× Y<br>H1 XZ Z DIMENSIONS NOM 5.01 0.60 4.41 0.75 0.63 15.00 15.00 1.27 13.97 13.97 0.41 4.00<br>BGA Package A1 SUBSTRATE M M<br>ddd eee<br>b1 MIN 4.81 0.50 4.31 0.60 0.60 0.36 3.95 TOTAL NUMBER OF BALLS: 144<br>ccc  Z MOLD CAP H2 DETAIL B DETAIL A<br>144-Lead (15mm (Reference LTC DWG # 05-08-1880 Rev C) Øb (144 PLACES) A A1 A2 b b1 D E e F G H1 H2 aaa bbb ccc ddd eee<br>SYMBOL<br>aaa  Z<br>Y E 0.0000<br>6.9850 5.7150 4.4450 3.1750 1.9050 0.6350 0.6350 1.9050 3.1750 4.4450 5.7150 6.9850<br>X<br>D<br>TOP VIEW<br>PACKAGE TOP VIEW<br>SUGGESTED PCB LAYOUT<br>aaa  Z 4<br>PIN “A1” CORNER<br>0.630 ±0.025 Ø 144x<br>Z<br>Z//  bbb<br>6.9850<br>5.7150<br>4.4450<br>3.1750<br>1.9050<br>0.6350<br>0.0000<br>0.6350<br>1.9050<br>3.1750<br>4.4450<br>5.7150<br>6.9850<br>**----- End of picture text -----**<br>


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LTM4620 

## **REVISION HISTORY** 

|**REV**|**DATE**|**DESCRIPTION**|**PAGE NUMBER**|
|---|---|---|---|
|A|10/13|Revised temperature monitoring (TEMP) explanation<br>Added BGA package|20, 21<br>2, 38, 40|
|B|02/14|Added SnPb BGA package option|1, 2|
|C|06/17|Added LTM4620Y MP-Grade to the Order Information|2|



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Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.For more information www.linear.com/LTM4620 

LTM4620 

## **PACKAGE PHOTO** 

**==> picture [16 x 9] intentionally omitted <==**

**----- Start of picture text -----**<br>
LGA<br>**----- End of picture text -----**<br>


**==> picture [17 x 9] intentionally omitted <==**

**----- Start of picture text -----**<br>
BGA<br>**----- End of picture text -----**<br>


## **RELATED PARTS** 

|**PART NUMBER**|**DESCRIPTION**|**COMMENTS**|
|---|---|---|
|LTM4628|Dual 8A, Single 16A µModule Regulator|Pin Compatible with LTM4620; 4.5V ≤ VIN≤ 26.5V, 0.6V ≤ VOUT≤ 5.5V,<br>15mm × 15mm × 4.32mm|
|LTM4611|Ultralow VIN, 15A µModule Regulator|1.5V ≤ VIN≤ 5.5V, 0.8V ≤ VOUT≤ 5V, 15mm × 15mm × 4.32mm|
|LTM4627|15A DC/DC µModule Regulator|4.5V ≤ VIN≤ 20V; 0.6V ≤ VOUT≤ 5V|
|LTM8062/<br>LTM8062A|32VIN, 2A µModule Battery Charger with Maximum<br>Peak Power Tracking(MPPT)|Adjustable VBATTUp to 14.4V (18.8V for the LTM8062A), C/10 or Timer<br>Termination, 9mm × 15mm × 4.32mm LGA Package|
|LTM8027|60VIN, 4A DC/DC Step-Down µModule Regulator|4.5V ≤ VIN≤ 60V, 2.5V ≤ VOUT≤ 24V, 15mm × 15mm × 4.32mm LGA Package|
|LTM4613|EN55022B Compliant 36VIN, 8A Step-Down<br>µModule Regulator|5V ≤ VIN≤ 36V, 3.3V ≤ VOUT≤ 15V, Synchronizable, Parallelable,<br>15mm × 15mm × 4.32mm LGA Package|
|LTM4637|20A µModule Regulator|4.5V ≤ VIN≤ 20V, 0.6V ≤ VOUT≤ 5.5V, 15mm×15mm×4.32mm|



## **DESIGN RESOURCES** 

|**DESIGN RESOURCES**|||
|---|---|---|
|**SUBJECT**|**DESCRIPTION**||
|µModule Design and Manufacturing Resources|Design:<br>• Selector Guides<br>• Demo Boards and Gerber Files<br>• Free Simulation Tools|Manufacturing:<br>• Quick Start Guide<br>• PCB Design, Assembly and Manufacturing Guidelines<br>• Package and Board Level Reliability|
|µModule Regulator Products Search|1.  Sort table of products by parameters and download the result as a spread sheet.<br>2. Search using the Quick Power Search parametric table.<br>Quick Power Search<br>Input<br>Vip, (Min)<br>V_<br>Vin (Max)<br>vi<br>Output<br>Vout<br>Vv<br>lout<br>A||
|TechClip Videos|Quick videos detailing how to bench test electrical and thermal performance of µModule products.||
|Digital Power System Management|Linear Technology’s family of digital power supply management ICs are highly integrated solutions that<br>offer essential functions, including power supply monitoring, supervision, margining and sequencing,<br>and feature EEPROM for storing user configurations and fault logging.||



4620fc 

For more information AT www.linear.com/LTM4620 NOW PARTANALOG LINEAR | ESAs 

LT 0617 REV C • PRINTED IN USA www.linear.com/LTM4620 

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 LINEAR TECHNOLOGY CORPORATION 2012