LTM4606IY#PBF

LTM4606 

## Ultralow EMI 28VIN, 6A DC/DC µModule Regulator 

## **FEATURES** 

- n **Complete Low EMI Switch Mode Power Supply** 

- n **Wide Input Voltage Range: 4.5V to 28V** 

- n **6A DC Typical, 8A Peak Output Current** 

- n **0.6V to 5V Output Voltage Range** 

- n **EN55022 Class B Certified** 

- n **Output Voltage Tracking and Margining** 

- n **PLL Frequency Synchronization** 

- n **±1.75% Total DC Error** 

- n **Power Good Output** 

- n **Current Foldback Protection (Disabled at Start-Up)** 

- n **Parallel/Current Sharing** 

- n Current Mode Control 

- n Up to 93% Efficiency at 5VIN, 3.3VOUT 

- n Programmable Soft-Start 

- n Output Overvoltage Protection 

- n –55°C to 125°C Operating Temperature Range (LTM4606MP) 

- n SnPb or RoHS Compliant Finish 

- n 15mm × 15mm × 2.82mm LGA Package 

   - 15mm × 15mm × 3.42mm BGA Package 

## **APPLICATIONS** 

- n ASICs or FPGA Transceivers 

- n Telecom, Servers and Networking Equipment 

- n Industrial Equipment 

- n RF Equipment 

## **DESCRIPTION** 

The LTM[®] 4606 is a complete EN55022 Class B certified noise high voltage 6A switching mode DC/DC power supply. Included in the package are the switching controller, power FETs, inductor, and all support components. The on-board input filter and noise cancellation circuits achieve low noise operation, thus effectively reducing the electromagnetic interference (EMI). Operating over an input voltage range of 4.5V to 28V, the LTM4606 supports an output voltage range of 0.6V to 5V, set by a single resistor. This high efficiency design delivers 6A continuous current (8A peak). Only bulk input and output capacitors are needed to finish the design. 

High switching frequency and an adaptive on-time current mode architecture enables a very fast transient response to line and load changes without sacrificing stability. The device supports output voltage tracking and output voltage margining. 

Furthermore, the µModule[®] regulator can be synchronized with an external clock for reducing undesirable frequency harmonics and allows PolyPhase[®] operation for high load currents. 

The LTM4606 is offered in space saving 15mm × 15mm × 2.82mm LGA and 15mm × 15mm × 3.42mm BGA packages. The LTM4606 is available with SnPb (BGA) or RoHS compliant terminal finish. 

All registered trademarks and trademarks are the property of their respective owners. Protected by U.S. patents, including 5481178, 5847554, 6304066, 6476589, 6580258, 6677210, 6774611, 8163643. 

## **TYPICAL APPLICATION** 

## **Radiated Emission Scan at 12VIN, 2.5VOUT/6A** 

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50<br>Ultralow Noise 2.5V/6A Power Supply with 4.5V to 28V Input<br>40<br>4.5V TO 28V CLOCK SYNC {ttt ttt<br>30 || [Pre]<br>PGOODVIN PLLINVOUT 2.5V AT 6A 20 ==VERnenn<br>ON/OFF RUNCOMP LTM4606 VFB 47pF COUT 10<br>10µFCIN INTVCC 19.1kRFB Tr 0 weeWTet<br>35V DRVCC FCB " –10 Pi TT Ty TE yy<br>CERAMIC fSET MARG0 MARGIN<br>x2 TRACK/SSCONTROL TRACK/SS MARG1 CONTROL –20 Pi TTT TT Ey TT<br>10µF VD SGND PGNDMPGM 392k –30 FH<br>35V 5% MARGIN 30 226.2 422.4 618.6 814.8 1010<br>128.1 324.3 520.5 716.7 912.9<br>4606 TA01a<br>FREQUENCY (MHz)<br>4606 TA01b<br>SIGNAL AMPLITUDE (dBµV/m)<br>**----- End of picture text -----**<br>


Rev. E 

1 

For more information www.analog.com 

Document Feedback 

## LTM4606 

## **ABSOLUTE MAXIMUM RATINGS** 

## **(Note 1)** 

DRVCC, VOUT ................................................–0.3V to 6V PLLIN, FCB, TRACK/SS, MPGM, MARG0, MARG1, PGOOD, RUN  ..............–0.3V to INTVCC + 0.3V VFB, COMP ................................................ –0.3V to 2.7V VIN, VD ....................................................... –0.3V to 28V 

Internal Operating Temperature Range (Note 2) E and I Grades ...................................–40°C to 125°C MP Grade ........................................... –55°C to 125°C Junction Temperature ........................................... 125°C Storage Temperature Range .................. –55°C to 125°C 

## **PIN CONFIGURATION** 

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TOP VIEW TOP VIEW<br>BANK 1VIN VD fSET BANK 1VIN VD fSET<br>MARG0 MARG0<br>SGND MARG1 SGND MARG1<br>DRVCC DRVCC<br>BANK 2PGND VFB BANK 2PGND VFB<br>PGOOD PGOOD<br>SGND SGND<br>NC NC<br>VOUT NC VOUT NC<br>BANK 3 NC BANK 3 NC<br>FCB FCB<br>BGA PACKAGE LGA PACKAGE<br>133-LEAD (15mm × 15mm × 3.42mm) 133-LEAD (15mm × 15mm × 2.82mm)<br>TJMAX = 125°C, θJA = 15°C/W, θJCbottom = 6°C/W, θJCtop = 16°C/W TJMAX = 125°C, θJA = 15°C/W, θJCbottom = 6°C/W, θJCtop = 16°C/W<br>θJA DERIVED FROM 95mm × 76mm PCB WITH 4 LAYERS  θJA DERIVED FROM 95mm × 76mm PCB WITH 4 LAYERS<br>WEIGHT = 1.9g WEIGHT = 1.7g<br>CC CC<br>INTV PLLIN TRACK/SS RUN COMP MPGM INTV PLLIN TRACK/SS RUN COMP MPGM<br>**----- End of picture text -----**<br>


## **ORDER INFORMATION** 

|**PART NUMBER**|**PAD OR BALL FINISH**|**PART MARKING***|**PART MARKING***|**PACKAGE**<br>**TYPE**|**MSL**<br>**RATING**|**TEMPERATURE RANGE**<br>**(Note 2)**|
|---|---|---|---|---|---|---|
|||**DEVICE**|**FINISH CODE**||||
|LTM4606EV#PBF|Au (RoHS)|LTM4606V|e4|LGA|3|–40°C to 125°C|
|LTM4606IV#PBF|Au(RoHS)|LTM4606V|e4|LGA|3|–40°C to 125°C|
|LTM4606MPV#PBF|Au(RoHS)|LTM4606MPV|e4|LGA|3|–55°C to 125°C|
|LTM4606EY#PBF|SAC305(RoHS)|LTM4606Y|e1|BGA|3|–40°C to 125°C|
|LTM4606IY#PBF|SAC305(RoHS)|LTM4606Y|e1|BGA|3|–40°C to 125°C|
|LTM4606IY|SnPb(63/37)|LTM4606Y|e0|BGA|3|–40°C to 125°C|
|LTM4606MPY#PBF|SAC305(RoHS)|LTM4606Y|e1|BGA|3|–55°C to 125°C|
|LTM4606MPY|SnPb (63/37)|LTM4606Y|e0|BGA|3|–55°C to 125°C|



- Contact the factory for parts specified with wider operating temperature ranges. *Pad or ball finish code is per IPC/JEDEC J-STD-609. 

- Recommended LGA and BGA PCB Assembly and Manufacturing Procedures 

- LGA and BGA Package and Tray Drawings 

Rev. E 

2 

For more information www.analog.com 

LTM4606 

**ELECTRICAL CHARACTERISTICS The** l **denotes the specifications which apply over the specified internal operating temperature range, otherwise specifications are at TA = 25°C (Note 2). VIN = 12V, unless otherwise noted. Per typical application (front page) configuration, RFB = 40.2k.** 

|**SYMBOL**|**PARAMETER**|**CONDITIONS**|**CONDITIONS**|**MIN**<br>**TYP**<br>**MAX**|**UNITS**|
|---|---|---|---|---|---|
|VIN(DC)|Input DC Voltage||l|4.5<br>28|V|
|VOUT(DC)|Output Voltage, Total Variation with<br>Line and Load|CIN= 10µF ×2, COUT= 200µF; FCB = 0<br>VIN= 5V to 28V, IOUT= 0A to 6A,(Note 4)|l|1.474<br>1.5<br>1.526|V|
|**Input Specifications**||||||
|VIN(UVLO)|Undervoltage Lockout Threshold|IOUT= 0A||3.2<br>4|V|
|IINRUSH(VIN)|Input Inrush Current at Start-Up|IOUT= 0A, CIN= 10µF ×2, COUT= 200µF,<br>VOUT= 1.5V<br>VIN= 5V<br>VIN= 12V||0.6<br>0.7|A<br>A|
|IQ(VIN)|Input Supply Bias Current|VIN= 5V, VOUT= 1.5V, Switching Continuous<br>VIN= 12V, VOUT= 1.5V, Switching Continuous<br>Shutdown, RUN = 0, VIN= 12V||27<br>25<br>22|mA<br>mA<br>µA|
|IS(VIN)|Input Supply Current|VIN= 12V, VOUT= 1.5V, IOUT= 6A<br>VIN= 5V, VOUT= 1.5V, IOUT= 6A||0.96<br>2.18|A<br>A|
|INTVCC|VIN= 12V, RUN > 2V|No Load||4.7<br>5<br>5.3|V|
|**Output Specifications**||||||
|IOUT(DC)|Output Continuous Current Range|VIN= 12V, VOUT= 1.5V (Note 4)||0<br>6|A|
|DVOUT(LINE)/VOUT|Line Regulation Accuracy|VOUT= 1.5V, FCB = 0V, VIN= 4.5V to 28V,<br>IOUT= 0A|l|0.05<br>0.3|%|
|DVOUT(LOAD)/VOUT|Load Regulation Accuracy|VOUT= 1.5V, FCB = 0V, IOUT= 0A to 6A<br>VIN= 12V(Note 4)|l|0.3|%|
|VIN(AC)|Input Ripple Voltage|IOUT= 0A, CIN= 10µF X5R Ceramic ×3 and<br>100µF Electrolytic<br>VIN= 5V, VOUT= 1.5V<br>VIN= 12V, VOUT= 1.5V||2<br>3|mVP-P<br>mVP-P|
|VOUT(AC)|Output Ripple Voltage|IOUT= 0A, COUT= 22µF X5R Ceramic ×3 and<br>100µF X5R Ceramic<br>VIN= 5V, VOUT= 1.5V<br>VIN= 12V, VOUT= 1.5V||8<br>11|mVP-P<br>mVP-P|
|fS|Output Ripple Voltage Frequency|IOUT= 5A, VIN= 12V, VOUT= 1.5V||900|kHz|
|DVOUT(START)|Turn-On Overshoot|COUT= 200µF, VOUT= 1.5V, IOUT= 0A,<br>TRACK/SS = 10nF<br>VIN= 12V<br>VIN= 5V||20<br>20|mV<br>mV|
|tSTART|Turn-On Time|COUT= 200µF; VOUT= 1.5V, TRACK/SS =<br>Open<br>IOUT= 1A Resistive Load<br>VIN= 5V<br>VIN= 12V||0.5<br>0.5|ms<br>ms|
|DVOUT(LS)|Peak Deviation for Dynamic Load|Load: 0% to 50% to 0% of Full Load<br>COUT= 22µF Ceramic, 470µF ×2<br>VIN= 12V<br>VOUT= 1.5V||35|mV|
|tSETTLE|Settling Time for Dynamic Load Step|Load: 0% to 50% to 0% of Full Load,<br>VIN= 12V||25|µs|
|IOUT(PK)|Output Current Limit|COUT= 200µF<br>VIN= 5V, VOUT= 1.5V<br>VIN= 12V, VOUT= 1.5V||10<br>10|A<br>A|



Rev. E 

3 

For more information www.analog.com 

## LTM4606 

**ELECTRICAL CHARACTERISTICS The** l **denotes the specifications which apply over the specified internal operating temperature range, otherwise specifications are at TA = 25°C (Note 2). VIN = 12V, unless otherwise noted. Per typical application (front page) configuration, RFB = 40.2k.** 

|**SYMBOL**|**PARAMETER**|**CONDITIONS**|**CONDITIONS**|**MIN**<br>**TYP**<br>**MAX**|**UNITS**|
|---|---|---|---|---|---|
|**Control Section**||||||
|VFB|Voltage at VFBPin|IOUT= 0A, VOUT= 1.5V|l|0.591<br>0.6<br>0.609|V|
|VRUN|RUN Pin On/Off Threshold|||1<br>1.5<br>1.9|V|
|ITRACK/SS|Soft-Start Charging Current|VTRACK/SS= 0V||–1<br>–1.5<br>–2|µA|
|VFCB|Forced Continuous Threshold|||0.57<br>0.6<br>0.63|V|
|IFCB|Forced Continuous Pin Current|VFCB= 0V||–1<br>–2|µA|
|tON(MIN)|Minimum On Time|(Note 3)||50<br>100|ns|
|tOFF(MIN)|Minimum Off Time|(Note 3)||250<br>400|ns|
|RPLLIN|PLLIN Input Resistor|||50|kW|
|IDRVCC|Current into DRVCCPin|VOUT= 1.5V, IOUT= 1A, DRVCC= 5V||15<br>25|mA|
|RFBHI|Resistor Between VOUTand VFBPins|||60.098<br>60.4<br>60.702|kW|
|VRUN(MAX)|Maximum RUN Pin Voltage|5.1V Zener Clamp||5|V|
|**Margin Section**||||||
|VMPGM|Margin Reference Voltage|||1.18|V|
|VMARG0, VMARG1|MARG0, MARG1 Voltage Threshold|||1.4|V|
|**PGOOD**||||||
|DVFBH|PGOOD Upper Threshold|VFBRising||7<br>10<br>13|%|
|DVFBL|PGOOD Lower Threshold|VFBFalling||–7<br>–10<br>–13|%|
|DVFB(HYS)|PGOOD Hysteresis|VFBReturning||1.5|%|
|VPGL|PGOOD Low Voltage|IPGOOD= 5mA||0.15<br>0.4|V|



**Note 1:** Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. 

**Note 2:** The LTM4606E is guaranteed to meet performance specifications over the 0°C to 125°C internal operating temperature range. Specifications over the –40°C to 125°C internal operating temperature range are assured by design, characterization and correlation with statistical process controls. The LTM4606I is guaranteed to meet specifications over the 

–40°C to 125°C internal operating temperature range. The LTM4606MP is guaranteed and tested over the –55°C to 125°C internal operating temperature range. Note that the maximum ambient temperature consistent with these specifications is determined by specific operating conditions in conjunction with board layout, the rated package thermal resistance and other environmental factors. 

**Note 3:** 100% tested at die level only. 

**Note 4:** See output current derating curves for different VIN, VOUT and TA. 

Rev. E 

4 

For more information www.analog.com 

LTM4606 

## **TYPICAL PERFORMANCE CHARACTERISTICS** 

**Efficiency vs Load Current with 5VIN (FCB = 0)** 

**Efficiency vs Load Current with 12VIN (FCB = 0)** 

**Efficiency vs Load Current with 24VIN (FCB = 0)** 

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100 100 100<br>90 90 90<br>80 fa 80 80 tH<br>Fas) (22555 [leeee<br>70 70 70<br>0.6VOUT 1.2VOUT<br>60 1.2VOUT 60 1.5VOUT 60<br>1.8VOUT 2.5VOUT 2.5VOUT<br>2.5VOUT 3.3VOUT 3.3VOUT<br>50 [ i= 3.3VOUT 50 ta = 5VOUT 50 aa” an |" 5VOUT<br>0 1 2 3 4 5 6 0 1 2 3 4 5 6 0 1 2 3 4 5 6<br>LOAD CURRENT (A) LOAD CURRENT (A) LOAD CURRENT (A)<br>4606 G01 4606 G02 4606 G03<br>1.2V Transient Response 1.5V Transient Response 1.8V Transient Response<br>IOUTOUT IOUTOUT IOUTOUT<br>2A/DIV 2A/DIV 2A/DIV<br>erally ial irl<br>VOUTOUT VOUTOUT VOUTOUT<br>50mV/DIV coloonleumlon Leowares Noeeamalana 50mV/DIV verti eect Nenana 50mV/DIV Leolanelwuele<br>—FECFEC roEEEEEE PRSren merrierreer mar aeSSSS [pesteenerSSSNeombeuubannaesenerSSSNeombeuubannaesSSSNeombeuubannaesNeombeuubannaesaes<br>50µs/DIV 4606 G04 50µs/DIV 4606 G05 50µs/DIV 4606 G06<br>1.2V AT 3.5A/µs LOAD STEP 1.5V AT 3.5A/µs LOAD STEP 1.8V AT 3.5A/µs LOAD STEP<br>COUT = 2× 22µF, 10V CERAMICOUT = 2× 22µF, 10V CERAMIC = 2× 22µF, 10V CERAMIC COUT = 2× 22µF, 10V CERAMICOUT = 2× 22µF, 10V CERAMIC = 2× 22µF, 10V CERAMIC COUT = 2× 22µF, 10V CERAMICOUT = 2× 22µF, 10V CERAMIC = 2× 22µF, 10V CERAMIC<br>1× 100µF, 6.3V CERAMIC 1× 100µF, 6.3V CERAMIC 1× 100µF, 6.3V CERAMIC<br>EFFICIENCY (%) EFFICIENCY (%) EFFICIENCY (%)<br>**----- End of picture text -----**<br>


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IOUTOUT IOUTOUT IOUTOUT<br>2A/DIV 2A/DIV 2A/DIV<br>erally ial irl<br>VOUTOUT VOUTOUT VOUTOUT<br>50mV/DIV coloonleumlon Leowares Noeeamalana 50mV/DIV verti eect Nenana 50mV/DIV Leolanelwuele<br>ren reer mar<br>—FECFEC roEEEEEE PRSren merrierreer aeSSSS [pesteenerSSSNeombeuubannaesenerSSSNeombeuubannaesSSSNeombeuubannaesNeombeuubannaesaes<br>50µs/DIV 4606 G04 50µs/DIV 4606 G05 50µs/DIV<br>1.2V AT 3.5A/µs LOAD STEP 1.5V AT 3.5A/µs LOAD STEP 1.8V AT 3.5A/µs LOAD STEP<br>COUT = 2× 22µF, 10V CERAMICOUT = 2× 22µF, 10V CERAMIC = 2× 22µF, 10V CERAMIC COUT = 2× 22µF, 10V CERAMICOUT = 2× 22µF, 10V CERAMIC = 2× 22µF, 10V CERAMIC COUT = 2× 22µF, 10V CERAMICOUT = 2× 22µF, 10V CERAMIC = 2× 22µF, 10V CERAMIC<br>1× 100µF, 6.3V CERAMIC 1× 100µF, 6.3V CERAMIC 1× 100µF, 6.3V CERAMIC<br>**----- End of picture text -----**<br>


**2.5V Transient Response** 

**3.3V Transient Response** 

**–55°C, Start-Up, IOUT = 0A** 

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IOUT IOUT<br>2A/DIV 2A/DIV<br>FST EE |||<br>ee TPP PPE erry<br>VOUT VOUT<br>50mV/DIV Saeed 100mV/DIV Soea” a<br>50µs/DIV 4606 G07 50µs/DIV 4606 G08<br>2.5V AT 3.5A/µs LOAD STEP 3.3V AT 3.5A/µs LOAD STEP<br>COUT = 2× 22µF, 10V CERAMIC COUT = 2× 22µF, 10V CERAMIC<br>1× 100µF, 6.3V CERAMIC 1× 100µF, 6.3V CERAMIC<br>**----- End of picture text -----**<br>


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0.5V/DIVVOUT are<br>a<br>IIN<br>0.5A/DIV —————FEE EE<br>VIN = 12V 1ms/DIV 4606 G09<br>VOUT = 1.5V<br>COUT = 2× 22µF, 10V CERAMIC<br>  1× 100µF, 6.3V CERAMIC<br>SOFT-START = 3.9nF<br>**----- End of picture text -----**<br>


Rev. E 

5 

For more information www.analog.com 

## LTM4606 

## **TYPICAL PERFORMANCE CHARACTERISTICS** 

## **–55°C, Start-Up, IOUT = 6A** 

**Start-Up, IOUT = 0A** 

**Start-Up, IOUT = 6A (Resistive Load)** 

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VOUT<br>0.5V/DIV VOUT<br>0.5V/DIV<br>IIN<br>0.5A/DIV<br>VIN = 12V 1ms/DIV 4606 G10 0.5A/DIVIIN 2 t : i 1 2 . 2 .<br>VOUT = 1.5V<br>COUT = 2× 22µF, 10V CERAMIC  1× 100µF, 6.3V CERAMIC VIN = 12V 1ms/DIV 4606 G11<br>SOFT-START = 3.9nF VOUT = 1.5V<br>COUT = 1× 22µF, 6.3V CERAMIC<br>  1× 330µF, 4V SANYO POSCAP<br>SOFT-START = 3.9nF<br>**----- End of picture text -----**<br>


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VOUT<br>0.5V/DIV<br>IIN<br>0.5A/DIV cf 5 2<br>VIN = 12V 1ms/DIV 4606 G12<br>VOUT = 1.5V<br>COUT = 1× 22µF, 6.3V CERAMIC<br>  1× 330µF, 4V SANYO POSCAP<br>SOFT-START = 3.9nF<br>**----- End of picture text -----**<br>


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Short-Circuit Protection,   Short-Circuit Protection,<br>Start Into Pre-Biased Output IOUT = 0A IOUT = 6A<br>VIN<br>2V/DIV<br>VOUT VOUT VOUT<br>1V/DIV 2V/DIV 1V/DIV<br>IIN IIN<br>0.2A/DIV 2A/DIV<br>20ms/DIV 4606 G13a VIN = 12V 50µs/DIV 4606 G13 VIN = 12V 50µs/DIV 4606 G14<br>VIN = 12V VOUT = 2.5V VOUT = 2.5V<br>VOUT = 5V COUT = 2× 22µF, 10V CERAMIC COUT = 2× 22µF, 10V CERAMIC<br>COUT = 2× 22µF, 10V CERAMIC   1× 100µF, 6.3V CERAMIC   1× 100µF, 6.3V CERAMIC<br> 1× 100µF, 6.3V CERAMIC SOFT-START = 0.1µF SOFT-START = 0.1µF<br>SOFT-START = 0.1µF<br>**----- End of picture text -----**<br>


## **VIN to VOUT Step-Down Operation Region** 

## **VFB vs Temperature** 

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28 0.606<br>SEE FREQUENCY ADJUSTMENT SECTION<br>FOR OPERATIONS OUTSIDE THIS REGION<br>24 0.604<br>20 0.602<br>OPERATION REGION<br>16 WITH DEFAULT FREQUENCY 0.600<br>12 0.598<br>0.596<br>8<br>4.5 0.594<br>0.6 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 –55 –25 5 35 65 95 125<br>VOUT (V) TEMPERATURE (°C)<br>4606 G15 4606 G16<br> (V)  (V)<br>IN FB<br>V V<br>**----- End of picture text -----**<br>


Rev. E 

6 

For more information www.analog.com 

LTM4606 

## **TYPICAL PERFORMANCE CHARACTERISTICS** 

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Input Ripple Output Ripple<br>VIN 2mV/DIVVOUT<br>10mV/DIV<br>JMU AMV Lill A Ai<br>| [oo po<br>| [oo po<br>Pp VIN = 5V 2µs/DIV 4606 G17 Po VIN = 5V 2µs/DIV 4606 G18<br>VOUT = 1V AT 6A VOUT = 1V AT 6A<br>CIN = 3× 10µF, 25V CERAMIC COUT = 2× 22µF, 6.3V CERAMIC<br>1× 150µF BULK  1× 100µF, 6.3V CERAMIC<br>BW = 300MHz BW = 300MHz<br>**----- End of picture text -----**<br>


## **PIN FUNCTIONS** 

## **PACKAGE ROW AND COLUMN LABELING MAY VARY AMONG µModule PRODUCTS. REVIEW EACH PACKAGE LAYOUT CAREFULLY.** 

**VIN (Bank 1):** Power Input Pins. Apply input voltage between these pins and PGND pins. Recommend placing input decoupling capacitance directly between VIN pins and PGND pins. 

**VOUT (Bank 3):** Power Output Pins. Apply output load between these pins and PGND pins. Recommend placing output decoupling capacitance directly between these pins and PGND pins (see Figure 17). 

**PGND (Bank 2):** Power Ground Pins for Both Input and Output Returns. 

**VD (Pins B7, C7):** Top FET Drain Pins. Add more capacitors between VD and ground to handle the input RMS current and reduce the input ripple further. 

**DRVCC (Pins C10, E11, E12):** These pins normally connect to INTVCC for powering the internal MOSFET drivers. They can be biased up to 6V from an external supply with about 50mA capability, or an external circuit as shown in Figure 18. This improves efficiency at the higher input voltages by reducing power dissipation in the module. 

**INTVCC (Pin A7):** This pin is for additional decoupling of the 5V internal regulator. 

**PLLIN (Pin A8):** External Clock Synchronization Input to the Phase Detector. This pin is internally terminated to SGND with a 50k resistor. Apply a clock with high level above 2V and below INTVCC. See the Applications Information section. 

**FCB (Pin M12):** Forced Continuous Input. Connect this pin to SGND to force continuous synchronization operation at low load, to INTVCC to enable discontinuous mode operation at low load or to a resistive divider from a secondary output when using a secondary winding. 

**TRACK/SS (Pin A9):** Output Voltage Tracking and SoftStart Pin. When the module is configured as a master output, then a soft-start capacitor is placed on this pin to ground to control the master ramp rate. A soft-start capacitor can be used for soft-start turn-on in a standalone regulator. Slave operation is performed by putting a resistor divider from the master output to ground, and connecting the center point of the divider to this pin. See the Applications Information section. 

**MPGM (Pins A12, B11):** Programmable Margining Input. A resistor from these pins to ground sets a current that is equal to 1.18V/R. This current multiplied by 10kW will equal a value in millivolts that is a percentage of the 0.6V reference voltage. See the Applications Information section. To parallel LTM4606s, each requires an individual MPGM resistor. Do not tie MPGM pins together. 

Rev. E 

7 

For more information www.analog.com 

LTM4606 

## **PIN FUNCTIONS** 

**fSET (Pin B12):** Frequency set internally to 800kHz in continuous conducting mode at light load. An external resistor can be placed from this pin to ground to increase frequency. See the Applications Information section for frequency adjustment. 

**VFB (Pin F12):** The Negative Input of the Error Amplifier. Internally, this pin is connected to VOUT with a 60.4k precision resistor. Different output voltages can be programmed with an additional resistor between the VFB and SGND pins. See the Applications Information section. 

**MARG0 (Pin C12):** LSB Logic Input for the Margining Function. Together with the MARG1 pin, the MARG0 pin will determine if a margin high, margin low, or no margin state is applied. The pin has an internal pull-down resistor of 50k. See the Applications Information section. 

**MARG1 (Pins C11, D12):** MSB Logic Input for the Margining Function. Together with the MARG0 pin, the MARG1 pins will determine if a margin high, margin low, or no margin state is applied. The pins have an internal pull-down resistor of 50k. See the Applications Information section. 

**SGND (Pins D9, H12):** Signal Ground Pins. These pins connect to PGND at output capacitor point. See Figure 17. 

**COMP (Pins A11, D11):** Current Control Threshold and Error Amplifier Compensation Point. The current comparator threshold increases with this control voltage. The voltage ranges from 0V to 2.4V with 0.7V corresponding to zero sense voltage (zero current). 

**PGOOD (Pin G12):** Output Voltage Power Good Indicator. Open-drain logic output that is pulled to ground when the output voltage is not within ±10% of the regulation point, after a 25µs power bad mask timer expires. 

**RUN (Pins A10, B9):** Run Control Pins. A voltage above 1.9V will turn on the module, and below 1V will turn off the module. A programmable UVLO function can be accomplished with a resistor divider from VIN to ground. See Figure 1. This pin has a 5.1V Zener to ground. Maximum pin voltage is 5V. Limit current into the RUN pin to less than 1mA. 

**NC (Pins J12, K12, L12):** These pads must be left floating (electrical open circuit) and are used for enhanced solder joint strength. 

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LTM4606 

## **BLOCK DIAGRAM** 

**==> picture [509 x 343] intentionally omitted <==**

**----- Start of picture text -----**<br>
VIN<br>>1.9V = ON<br>R1<br><1V = OFF VOUT<br>UVLO MAX = 5V RUN INPUT VIN<br>FUNCTION PGOOD 5.1V FILTER + 4.5V TO 28V<br>R2 ZENER 1.5µF CIN<br>COMP<br>60.4k<br>INTERNAL VD<br>COMP CD<br>POWER CONTROL M1<br>SGND<br>1µH VOUT<br>MARG1 2.5V<br>AT 6A<br>MARG0<br>NOISE<br>VFB 50k 50k CANCEL- 22µF<br>+<br>RFB fSET M2 LATION COUT<br>19.1k<br>41.2k<br>PGND<br>FCB<br>10k<br>MPGM<br>TRACK/SS<br>CSS PLLIN<br>50k<br>4.7µF<br>INTVCC<br>DRVCC<br>4606 F01<br>**----- End of picture text -----**<br>


**Figure 1. Simplified Block Diagram** 

## **DECOUPLING REQUIREMENTS TA = 25°C. Use Figure 1 configuration.** 

|**SYMBOL**|**PARAMETER**|**CONDITIONS**|**CONDITIONS**|**MIN**<br>**TYP**<br>**MAX**|**UNITS**|
|---|---|---|---|---|---|
|CIN|External Input Capacitor Requirement<br>(VIN= 4.5V to 28V, VOUT= 2.5V)|IOUT= 6A||10|µF|
|COUT|External Output Capacitor Requirement<br>(VIN= 4.5V to 28V, VOUT= 2.5V)|IOUT= 6A||100<br>200|µF|



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LTM4606 

## **OPERATION** 

## **Power Module Description** 

The LTM4606 is a standalone non-isolated switching mode DC/DC power supply. It can deliver up to 6A of DC output current with some external input and output capacitors. This module provides precisely regulated output voltage programmable via one external resistor from 0.6VDC to 5.0VDC over a 4.5V to 28V input voltage range. The typical application schematic is shown in Figure 20. 

The LTM4606 has an integrated constant on-time current mode regulator, ultralow RDS(ON) FETs with fast switching speed and integrated Schottky diodes. With current mode control and internal feedback loop compensation, the LTM4606 module has sufficient stability margins and good transient performance under a wide range of operating conditions and with a wide range of output capacitors, even all ceramic output capacitors. 

Current mode control provides cycle-by-cycle fast current limiting. Besides, foldback current limiting is provided in an overcurrent condition while VFB drops. Internal overvoltage and undervoltage comparators pull the open-drain PGOOD output low if the output feedback voltage exits a ±10% window around the regulation point. Furthermore, in an overvoltage condition, internal top FET M1 is turned off and bottom FET M2 is turned on and held on until the overvoltage condition clears. 

Input filter and noise cancellation circuits reduce the noise coupling to I/O sides, and ensure the electromagnetic interference (EMI) to meet EN55022 Class B limits. 

Pulling the RUN pin below 1V forces the controller into its shutdown state, turning off both M1 and M2. At low load currents, discontinuous mode (DCM) operation can be enabled to achieve higher efficiency compared to continuous mode (CCM) by setting the FCB pin higher than 0.6V. 

When the DRVCC pin is connected to INTVCC an integrated 5V linear regulator powers the internal gate drivers. If a 5V external bias supply is applied on the DRVCC pin, then an efficiency improvement will occur due to the reduced power loss in the internal linear regulator. This is especially true at the higher input voltage range. 

The MPGM, MARG0 and MARG1 pins are used to support voltage margining, where the percentage of margin is programmed by the MPGM pin, and the MARG0 and MARG1 selected margining. The PLLIN pin provides frequency synchronization of the device to an external clock. The TRACK/SS pin is used for power supply tracking and soft-start programming. 

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LTM4606 

## **APPLICATIONS INFORMATION** 

The typical LTM4606 application circuit is shown in Figure 20. External component selection is primarily determined by the maximum load current and output voltage. Refer to Table 2 for specific external capacitor requirements for a particular application. 

## **VIN to VOUT Step-Down Ratios** 

Under the default frequency, there are restrictions in the maximum VIN and VOUT step-down ratio that can be achieved for a given input voltage. These constraints are caused by the limitation of the minimum on and off time in the internal switches. Refer to the Frequency Adjustment section to change the switching frequency and get wider input and output ranges. See the Thermal Considerations and Output Current Derating section in this data sheet for the current restrictions. 

## **Output Voltage Programming and Margining** 

The PWM controller has an internal 0.6V reference voltage. As shown in the Block Diagram, a 60.4k internal feedback resistor connects the VOUT and VFB pins together. Adding a resistor RFB from the VFB pin to the SGND pin programs the output voltage: 

**==> picture [188 x 77] intentionally omitted <==**

**Table 1. RFB Standard 1% Resistor Values vs VOUT** 

|**RFB**<br>**(kΩ)**|Open|60.4|40.2|30.1|25.5|19.1|13.3|8.25|
|---|---|---|---|---|---|---|---|---|
|**VOUT**<br>**(V)**|0.6|1.2|1.5|1.8|2|2.5|3.3|5|



The MPGM pin programs a current that when multiplied by an internal 10k resistor sets up the 0.6V reference ± offset for margining. A 1.18V reference divided by the 

RPGM resistor on the MPGM pin programs the current. Calculate V : OUT(MARGIN) 

**==> picture [138 x 27] intentionally omitted <==**

where %VOUT is the percentage of VOUT you want to margin, and VOUT(MARGIN) is the margin quantity in volts: 

**==> picture [255 x 70] intentionally omitted <==**

The margining voltage, VOUT(MARGIN), will be added or subtracted from the nominal output voltage as determined by the state of the MARG0 and MARG1 pins. See the truth table below: 

|<br>table below:|||
|---|---|---|
|**MARG1**|**MARG0**|**MODE**|
|LOW|LOW|NO MARGIN|
|LOW|HIGH|MARGIN UP|
|HIGH|LOW|MARGIN DOWN|
|HIGH|HIGH|NO MARGIN|



## **Input Capacitors and Input EMI Noise Attenuation** 

The LTM4606 is designed to achieve low input conducted EMI noise due to the fast switching of turn-on and turnoff. In the LTM4606, a high frequency inductor is integrated to the input line for noise attenuation. VD and VIN pins are available for external input capacitors to form a high frequency π filter. As shown in Figure 19, the ceramic capacitor C1 on the VD pins is used to handle most of the RMS current into the converter, so careful attention is needed for capacitor C1 selection. 

For a buck converter, the switching duty cycle can be estimated as: 

**==> picture [44 x 30] intentionally omitted <==**

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LTM4606 

## **APPLICATIONS INFORMATION** 

Without considering the inductor ripple current, the RMS current of the input capacitor can be estimated as: 

**==> picture [161 x 32] intentionally omitted <==**

In the above equation, η is the estimated efficiency of the power module. Note the capacitor ripple current ratings are often based on temperature and hours of life. This makes it advisable to properly derate the capacitor, or choose a capacitor rated at a higher temperature than required. Always contact the capacitor manufacturer for derating requirements. 

In a typical 6A output application, one or two very low ESR X5R or X7R, 10µF ceramic capacitors are recommended for C1. This decoupling capacitor should be placed directly adjacent to the module VD pins in the PCB layout to minimize the trace inductance and high frequency AC noise. Each 10µF ceramic is typically good for 2 to 3 amps of RMS ripple current. Refer to your ceramics capacitor catalog for the RMS current ratings. 

To attenuate high frequency noise, extra input capacitors should be connected to the VIN pads and placed before the high frequency inductor to form the π filter. One of these low ESR ceramic capacitors is recommended to be placed close to the connection into the system board. A large bulk 100µF capacitor is only needed if the input source impedance is compromised by long inductive leads or traces. Figure 2 shows the radiated EMI test results to 

**==> picture [163 x 168] intentionally omitted <==**

**----- Start of picture text -----**<br>
50<br>40 PT ett ty Ty<br>30 ee<br>20 ==, VuEnene<br>10 yeer<br>0 Wee<br>–10 PT Tt TT yyy<br>–20 PT ett ty Ty<br>–30<br>Peper rere<br>30 226.2 422.4 618.6 814.8 1010<br>128.1 324.3 520.5 716.7 912.9<br>FREQUENCY (MHz)<br>4606 F02<br>SIGNAL AMPLITUDE (dBµV/m)<br>**----- End of picture text -----**<br>


**Figure 2. Radiated Emission Scan with 12VIN to 2.5VOUT at 6A (1×100µF X7R Ceramic COUT)** 

meet EN55022 Class B. For different applications, input capacitance may be varied to meet different radiated EMI limits. 

## **Output Capacitors** 

The LTM4606 is designed for low output voltage ripple. The bulk output capacitors defined as COUT are chosen with low enough effective series resistance (ESR) to meet the output voltage ripple and transient requirements. COUT can be a low ESR tantalum capacitor, low ESR polymer capacitor or ceramic capacitor. The typical capacitance is 200µF if all ceramic output capacitors are used. Additional output filtering may be required by the system designer, if further reduction of output ripple or dynamic transient spike is required. Table 2 shows a matrix of different output voltages and output capacitors to minimize the voltage droop and overshoot during a 3A/µs transient. The table optimizes total equivalent ESR and total bulk capacitance to maximize transient performance. 

Multiphase operation with multiple LTM4606 devices in parallel will lower the effective output ripple current due to the phase interleaving operation. Refer to Figure 3 for the normalized output ripple current versus the duty cycle. Figure 3 provides a ratio of peak-to-peak output ripple current to the inductor ripple current as functions of duty cycle and the number of paralleled phases. Pick the corresponding duty cycle and the number of phases to get the correct output ripple current value. For example, each phase’s inductor ripple current DIr at zero duty cycle is ~2.5A for a 12V to 2.5V design. The duty cycle is about 0.21. The 2-phase curve has a ratio of ~0.58 for a duty cycle of 0.21. This 0.58 ratio of output ripple current to the inductor ripple current DIr at 2.5A equals ~1.5A of the output ripple current (∆IL). 

The output ripple voltage has two components that are related to the amount of bulk capacitance and effective series resistance (ESR) of the output bulk capacitance. The equation is: 

**==> picture [195 x 34] intentionally omitted <==**

where f is the frequency and N is the number of paralleled phases. 

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LTM4606 

## **APPLICATIONS INFORMATION** 

**==> picture [308 x 292] intentionally omitted <==**

**----- Start of picture text -----**<br>
1.00<br>0.95 1-PHASE<br>2-PHASE<br>0.90<br>3-PHASE<br>0.85 4-PHASE<br>6-PHASE<br>0.80<br>0.75<br>0.70<br>0.65<br>0.60<br>0.55<br>0.50<br>0.45<br>0.40<br>0.35<br>0.30<br>0.25<br>0.20<br>0.15<br>0.10<br>0.05<br>0<br>0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 0.6 0.65 0.7 0.75 0.8 0.85 0.9<br>DUTY CYCLE (VO/VIN) 4606 F03<br>DIr<br>PEAK-TO-PEAK OUTPUT RIPPLE CURRENT<br>RATIO =<br>**----- End of picture text -----**<br>


**Figure 3. Normalized Output Ripple Current vs Duty Cycle, Dlr = VOT/LI** 

## **Fault Conditions: Current Limit and Overcurrent Foldback** 

LTM4606 has a current mode controller, which inherently limits the cycle-by-cycle inductor current not only in steady-state operation, but also in transient. 

To further limit current in the event of an overload condition, the LTM4606 provides foldback current limiting. If the output voltage falls by more than 50%, then the maximum output current is progressively lowered to about one sixth of its full current limit value. 

## **Soft-Start and Tracking** 

The TRACK/SS pin provides a means to either soft-start the regulator or track it to a different power supply. 

A capacitor on this pin will program the ramp rate of the output voltage. A 1.5µA current source will charge up the external soft-start capacitor to 80% of the 0.6V internal voltage reference plus or minus any margin delta. This will control the ramp of the internal reference and the output voltage. The total soft-start time can be calculated as: 

**==> picture [226 x 29] intentionally omitted <==**

When the RUN pin falls below 1.5V, then the TRACK/SS pin is reset to allow for proper soft-start control when the regulator is enabled again. Current foldback and forced continuous mode are disabled during the soft-start process. The soft-start function can also be used to control the output ramp up time, so that another regulator can be easily tracked to it. 

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LTM4606 

## **APPLICATIONS INFORMATION** 

## **Output Voltage Tracking** 

Output voltage tracking can be programmed externally using the TRACK/SS pin. The output can be tracked up and down with another regulator. Figure 4 shows an example of coincident tracking where the master regulator’s output is divided down with an external resistor divider that is the same as the slave regulator’s feedback divider. Ratiometric modes of tracking can be achieved by selecting different resistor values to change the output tracking ratio. The master output must be greater than the slave output for the tracking to work. Figure 5 shows the coincident output tracking characteristics. 

**==> picture [247 x 155] intentionally omitted <==**

**----- Start of picture text -----**<br>
VIN<br>100k<br>VD VIN PLLIN<br>SLAVE<br>PGOOD VOUT OUTPUT<br>RUN LTM4606 VFB COUT 2.5V<br>CIN COMP FCB<br>INTVCC MARG0<br>MASTER<br>OUTPUT DRVCC MARG1<br>R2<br>60.4k fSET MPGM<br>TRACK<br>CONTROL TRACK/SS 19.1k<br>R1 SGND PGND<br>19.1k<br>4606 F04<br>**----- End of picture text -----**<br>


**Figure 4. Coincident Tracking Schematic** 

**==> picture [163 x 125] intentionally omitted <==**

**----- Start of picture text -----**<br>
MASTER OUTPUT<br>SLAVE OUTPUT<br>OUTPUT<br>VOLTAGE<br>TIME 4606 F05<br>**----- End of picture text -----**<br>


## **Run Enable** 

The RUN pin is used to enable the power module. The pin has an internal 5.1V Zener to ground. The pin can be driven with a logic input not to exceed 5V. 

The RUN pin can also be used as an undervoltage lock out (UVLO) function by connecting a resistor divider from the input supply to the RUN pin: 

**==> picture [105 x 27] intentionally omitted <==**

See Figure 1, Simplified Block Diagram. 

## **Power Good** 

The PGOOD pin is an open-drain pin that can be used to monitor valid output voltage regulation. This pin monitors a ±10% window around the regulation point and tracks with margining. 

## **COMP Pin** 

This pin is the external compensation pin. The module has already been internally compensated for most output voltages. Table 2 is provided for most application requirements. LTpowerCAD **[®]** is available for other control loop optimization. 

## **FCB Pin** 

The FCB pin determines whether the bottom MOSFET remains on when current reverses in the inductor. Tying this pin above its 0.6V threshold enables discontinuous operation where the bottom MOSFET turns off when inductor current reverses. FCB pin below the 0.6V threshold forces continuous synchronous operation, allowing current to reverse at light loads and maintain low output ripple. 

**Figure 5. Coincident Output Tracking Characteristics** 

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LTM4606 

## **APPLICATIONS INFORMATION** 

## **PLLIN** 

The power module has a phase-locked loop comprised of an internal voltage controlled oscillator and a phase detector. This allows the internal top MOSFET turn-on to be locked to the rising edge of the external clock. The frequency range is ±30% around the operating frequency. A pulse detection circuit is used to detect a clock on the PLLIN pin to turn on the phase lock loop. The pulse width of the clock has to be at least 400ns and the amplitude at least 2V. The PLLIN pin must be driven from a low impedance source such as a logic gate located close to the pin. During the start-up of the regulator, the phase-locked loop function is disabled. 

## **INTVCC and DRVCC Connection** 

An internal low dropout regulator produces an internal 5V supply that powers the control circuitry and DRVCC for driving the internal power MOSFETs. Therefore, if the system does not have a 5V power rail, the LTM4606 can be directly powered by VIN. The gate driver current through the LDO is about 20mA. The internal LDO power dissipation can be calculated as: 

PLDO_LOSS = 20mA • (VIN – 5V) 

The LTM4606 also provides an external gate driver voltage pin DRVCC. If there is a 5V rail in the system, it is recommended to connect DRVCC pin to the external 5V rail. This is especially true for higher input voltages. Do not apply more than 6V to the DRVCC pin. A 5V output can be used to power the DRVCC pin with an external circuit as shown in Figure 18. 

## **Thermal Considerations and Output Current Derating** 

In different applications, LTM4606 operates in a variety of thermal environments. The maximum output current is limited by the environment thermal condition. Sufficient cooling should be provided to help ensure reliable operation. When the cooling is limited, proper output current derating is necessary, considering ambient temperature, airflow, input/output condition, and the need for increased reliability. 

The power loss curves in Figures 6 and 7 can be used in coordination with the load current derating curves in Figures 8 to 15 for calculating an approximate θJA for the module. The graphs delineate between no heat sink, and a BGA heat sink. Each of the load current derating curves will lower the maximum load current as a function of the increased ambient temperature to keep the maximum junction temperature of the power module at 125°C maximum. Each of the derating curves and the power loss curve that corresponds to the correct output voltage can be used to solve for the approximate θJA of the condition. Each figure has three curves that are taken at three different air flow conditions. Table 3 and Table 4 provide the approximate θJA for Figures 8 to 15. A complete explanation of the thermal characteristics is provided in the thermal Application Note AN110. 

## **Safety Considerations** 

The LTM4606 modules do not provide galvanic isolation from VIN to VOUT. There is no internal fuse. If required, a slow blow fuse with a rating twice the maximum input current needs to be provided to protect each unit from catastrophic failure. 

## **Parallel Operation of the Module** 

The LTM4606 device is an inherently current mode controlled device. Parallel modules will have very good current sharing. This will balance the thermals on the design. The voltage feedback equation changes with the variable N as modules are paralleled: 

**==> picture [115 x 42] intentionally omitted <==**

N is the number of paralleled modules. 

## **Radiated EMI Noise** 

High radiated EMI noise is a disadvantage for switching regulators by nature. Fast switching turn-on and turn-off make large di/dt change in the converters, which act as the radiation sources in most systems. The LTM4606 integrates the feature to minimize the radiated EMI noise for applications with low noise requirements. Optimized gate driver for the MOSFET and noise cancellation network are installed inside the LTM4606 to achieve low radiated EMI noise. Figure 16 shows a typical example for LTM4606 to meet the Class B of EN55022 radiated emission limit. 

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LTM4606 

## **APPLICATIONS INFORMATION** 

**==> picture [386 x 591] intentionally omitted <==**

**----- Start of picture text -----**<br>
2.5 4.0<br>3.5<br>2.0<br>3.0 24V LOSS<br>12V LOSS<br>2.5<br>1.5<br>5V LOSS 2.0<br>1.0 1.5 12V LOSS<br>1.0<br>0.5<br>0.5<br>0 0<br>0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7<br>OUTPUT CURRENT (A) OUTPUT CURRENT (A)<br>4606 F06 4606 F07<br>Figure 6. 1.5V Power Loss Figure 7. 3.3V Power Loss<br>6 6<br>5 5<br>4 4<br>3 3<br>2 2<br>1 5VIN, 1.5VOUT, 0LFM 1 5VIN, 1.5VOUT, 0LFM<br>5VIN, 1.5VOUT, 200LFM 5VIN, 1.5VOUT, 200LFM<br>5VIN, 1.5VOUT, 400LFM 5VIN, 1.5VOUT, 400LFM<br>0 0<br>75 80 85 90 95 75 80 85 90 95<br>AMBIENT TEMPERATURE (°C) AMBIENT TEMPERATURE (°C)<br>4606 F08 4606 F09<br>Figure 8. No Heat Sink Figure 9. BGA Heat Sink<br>6 6<br>5 5<br>4 4<br>3 3<br>2 2<br>1 1 12VIN, 1.5VOUT, 0LFM<br>12VIN, 1.5VOUT, 200LFM<br>12VIN, 1.5VOUT, 400LFM<br>0 0<br>70 75 80 85 90 95 70 75 80 85 90 95<br>AMBIENT TEMPERATURE (°C) AMBIENT TEMPERATURE (°C)<br>12VIN, 1.5VOUT, 0LFM 4606 F10 4606 F11<br>12VIN, 1.5VOUT, 200LFM<br>12VIN, 1.5VOUT, 400LFM<br>POWER LOSS (W) POWER LOSS (W)<br>MAXIMUM LOAD CURRENT (A) MAXIMUM LOAD CURRENT (A)<br>MAXIMUM LOAD CURRENT (A) MAXIMUM LOAD CURRENT (A)<br>**----- End of picture text -----**<br>


**Figure 10. No Heat Sink** 

**Figure 11. BGA Heat Sink** 

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LTM4606 

## **APPLICATIONS INFORMATION** 

**==> picture [388 x 365] intentionally omitted <==**

**----- Start of picture text -----**<br>
6 6<br>5 5<br>aN pi NA I<br>4 4<br>P| WAL | IAM<br>3 3<br>See PF [NYT]<br>2 2<br>ART aan ae<br>1 12VIN, 3.3VOUT, 0LFM 1 12VIN, 3.3VOUT, 0LFM<br>12VIN, 3.3VOUT, 200LFM 12VIN, 3.3VOUT, 200LFM<br>12VIN, 3.3VOUT, 400LFM 12VIN, 3.3VOUT, 400LFM<br>0 eM 0 BNE<br>70 75 80 85 90 95 70 75 80 85 90 95<br>AMBIENT TEMPERATURE (°C) AMBIENT TEMPERATURE (°C)<br>4606 F12 4606 F13<br>Figure 12. No Heat Sink Figure 13. BGA Heat Sink<br>6 6<br>5 5<br>TY TREAT<br>4 4<br>INN PLN<br>3 Pf | VY 3 | NEA<br>2 2<br>1 c 24VIN, 3.3V ea OUT, 0LFM 1 p 24VIN, 3.3VOUT, 0LFM V<br>24VIN, 3.3VOUT, 200LFM 24VIN, 3.3VOUT, 200LFM<br>0 Ee 24VIN, 3.3VOUT, 400LFM 0 24VIN, 3.3VOUT, 400LFM<br>60 65 70 75 80 85 60 65 70 75 80 85 90<br>AMBIENT TEMPERATURE (°C) AMBIENT TEMPERATURE (°C)<br>4606 F14 4606 G15<br>MAXIMUM LOAD CURRENT (A) MAXIMUM LOAD CURRENT (A)<br>MAXIMUM LOAD CURRENT (A) MAXIMUM LOAD CURRENT (A)<br>**----- End of picture text -----**<br>


**Figure 14. No Heat Sink** 

**Figure 15. BGA Heat Sink** 

**==> picture [163 x 168] intentionally omitted <==**

**----- Start of picture text -----**<br>
50<br>40 ERR EeEeee<br>i<br>3020 maa<br>10 LE [ee] A ed<br>–100 WeePTT<br>–20 PT TET ET ET yy<br>–30<br>SEREEEEEEE<br>30 226.2 422.4 618.6 814.8 1010<br>128.1 324.3 520.5 716.7 912.9<br>FREQUENCY (MHz)<br>4606 F16<br>SIGNAL AMPLITUDE (dBµV/m)<br>**----- End of picture text -----**<br>


**Figure 16. Radiated Emission Scan with 12VIN to 2.5VOUT at 6A (1×100µF X7R Ceramic COUT)** 

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LTM4606 

## **APPLICATIONS INFORMATION** 

**Table 2. Output Voltage Response vs Component Matrix (Refer to Figure 20)** 

## **TYPICAL MEASURED VALUES** 

|**TYPICAL MEASURED VALUES**|**TYPICAL MEASURED VALUES**|**TYPICAL MEASURED VALUES**|||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|
|**COUT1 VENDORS**|||**PART NUMBER**||||**COUT2 VENDORS**|||**PART NUMBER**|||
|TAIYO YUDEN|||JMK316BJ226ML-T501(22µF,6.3V)||||SANYO POSCAP|||6TPE220MIL(220µF,6.3V)|||
|TAIYO YUDEN|||JMK325BJ476MM-T(47µF,6.3V)||||SANYO POSCAP|||2R5TPE330M9(330µF,2.5V)|||
|TDK|||C3225X5R0J476M(47µF,6.3V)||||SANYO POSCAP|||4TPE330MCL(330µF,4V)|||
||||||||||||||
|**VOUT**<br>**(V)**|**CIN**<br>**(CERAMIC)**|**CIN**<br>**(BULK)**||**COUT1**<br>**(CERAMIC)**|**COUT2**<br>**(BULK)**|**VIN**<br>**(V)**||**DROOP**<br>**(mV)**|**PEAK TO**<br>**PEAK(mV)**|**RECOVERY**<br>**TIME(µs)**|**LOAD STEP**<br>**(A/µs)**|**RFB**<br>**(k**W**)**|
|1.2|2×10µF 35V|150µF 35V||1 × 22µF 6.3V|330µF 4V|5||34|68|30|3|60.4|
|1.2|2×10µF 35V|150µF 35V||1 × 47µF 6.3V|330µF 2.5V|5||22|40|26|3|60.4|
|1.2|2×10µF 35V|150µF 35V||2 × 47µF 6.3V|220µF 6.3V|5||20|40|24|3|60.4|
|1.2|2×10µF 35V|150µF 35V||4 × 47µF 6.3V|NONE|5||32|60|18|3|60.4|
|1.2|2 × 10µF 35V|150µF 35V||1 × 22µF 6.3V|330µF 4V|12||34|68|30|3|60.4|
|1.2|2 × 10µF 35V|150µF 35V||1 × 47µF 6.3V|330µF 2.5V|12||22|40|26|3|60.4|
|1.2|2 × 10µF 35V|150µF 35V||2 × 47µF 6.3V|220µF 6.3V|12||20|39|24|3|60.4|
|1.2|2 × 10µF 35V|150µF 35V||4 × 47µF 6.3V|NONE|12||29.5|55|18|3|60.4|
|1.5|2 × 10µF 35V|150µF 35V||1 × 22µF 6.3V|330µF 4V|5||35|70|30|3|40.2|
|1.5|2 × 10µF 35V|150µF 35V||1 × 47µF 6.3V|330µF 2.5V|5||25|48|30|3|40.2|
|1.5|2 × 10µF 35V|150µF 35V||2 × 47µF 6.3V|220µF 6.3V|5||24|47.5|26|3|40.2|
|1.5|2 × 10µF 35V|150µF 35V||4 × 47µF 6.3V|NONE|5||36|68|26|3|40.2|
|1.5|2 × 10µF 35V|150µF 35V||1 × 22µF 6.3V|330µF 4V|12||35|70|30|3|40.2|
|1.5|2 × 10µF 35V|150µF 35V||1 × 47µF 6.3V|330µF 2.5V|12||25|48|30|3|40.2|
|1.5|2 × 10µF 35V|150µF 35V||2 × 47µF 6.3V|220µF 6.3V|12||24|45|26|3|40.2|
|1.5|2 × 10µF 35V|150µF 35V||4 × 47µF 6.3V|NONE|12||32.6|61.9|26|3|40.2|
|1.8|2 × 10µF 35V|150µF 35V||1 × 22µF 6.3V|330µF 4V|5||38|76|37|3|30.1|
|1.8|2 × 10µF 35V|150µF 35V||1 × 47µF 6.3V|330µF 2.5V|5||29.5|57.5|30|3|30.1|
|1.8|2 × 10µF 35V|150µF 35V||2 × 47µF 6.3V|220µF 6.3V|5||28|55|26|3|30.1|
|1.8|2 × 10µF 35V|150µF 35V||4 × 47µF 6.3V|NONE|5||43|80|26|3|30.1|
|1.8|2 × 10µF 35V|150µF 35V||1 × 22µF 6.3V|330µF 4V|12||38|76|37|3|30.1|
|1.8|2 × 10µF 35V|150µF 35V||1 × 47µF 6.3V|330µF 2.5V|12||28|55|30|3|30.1|
|1.8|2 × 10µF 35V|150µF 35V||2 × 47µF 6.3V|220µF 6.3V|12||27|52|26|3|30.1|
|1.8|2 × 10µF 35V|150µF 35V||4 × 47µF 6.3V|NONE|12||36.4|70|26|3|30.1|
|2.5|2 × 10µF 35V|150µF 35V||1 × 22µF 6.3V|330µF 4V|5||38|78|40|3|19.1|
|2.5|2 × 10µF 35V|150µF 35V||1 × 47µF 6.3V|330µF 4V|5||37.6|74|34|3|19.1|
|2.5|2 × 10µF 35V|150µF 35V||2 × 47µF 6.3V|220µF 6.3V|5||39.5|78.1|28|3|19.1|
|2.5|2 × 10µF 35V|150µF 35V||4 × 47µF 6.3V|NONE|5||66|119|12|3|19.1|
|2.5|2 × 10µF 35V|150µF 35V||1 × 22µF 6.3V|330µF 4V|12||38|78|40|3|19.1|
|2.5|2 × 10µF 35V|150µF 35V||1 × 47µF 6.3V|330µF 4V|12||34.5|66.3|34|3|19.1|
|2.5|2 × 10µF 35V|150µF 35V||2 × 47µF 6.3V|220µF 6.3V|12||35.8|68.8|28|3|19.1|
|2.5|2 × 10µF 35V|150µF 35V||4 × 47µF 6.3V|NONE|12||50|98|18|3|19.1|
|3.3|2 × 10µF 35V|150µF 35V||1 × 22µF 6.3V|330µF 4V|7||42|86|40|3|13.3|
|3.3|2 × 10µF 35V|150µF 35V||1 × 47µF 6.3V|330µF 4V|7||47|89|32|3|13.3|
|3.3|2 × 10µF 35V|150µF 35V||2 × 47µF 6.3V|220µF 6.3V|7||50|94|28|3|13.3|
|3.3|2 × 10µF 35V|150µF 35V||4 × 47µF 6.3V|NONE|7||75|141|14|3|13.3|
|3.3|2 × 10µF 35V|150µF 35V||1 × 22µF 6.3V|330µF 4V|12||42|86|40|3|13.3|
|3.3|2 × 10µF 35V|150µF 35V||1 × 47µF 6.3V|330µF 4V|12||47|88|32|3|13.3|
|3.3|2 × 10µF 35V|150µF 35V||2 × 47µF 6.3V|220µF 6.3V|12||50|94|28|3|13.3|
|3.3|2 × 10µF 35V|150µF 35V||4 × 47µF 6.3V|NONE|12||69|131|22|3|13.3|
|5|2 × 10µF 35V|150µF 35V||4 × 47µF 6.3V|NONE|12||110|215|20|3|8.25|
|5|2 × 10µF 35V|150µF 35V||4 × 47µF 6.3V|NONE|15||110|215|20|3|8.25|
|5|2 × 10µF 35V|150µF 35V||4 × 47µF 6.3V|NONE|20||110|217|20|3|8.25|



Rev. E 

18 

For more information www.analog.com 

LTM4606 

## **APPLICATIONS INFORMATION** 

**Table 3. 1.5V Output** 

|**Table 3. 1.5V Output**||||||
|---|---|---|---|---|---|
|**DERATING CURVE**|**VIN (V)**|**POWER LOSS CURVE**|**AIR FLOW(LFM)**|**HEAT SINK**|θ**JA (°C/W)**|
|Figure 8, Figure 10|5, 12|Figure 6|0|None|13.5|
|Figure 8, Figure 10|5, 12|Figure 6|200|None|10|
|Figure 8, Figure 10|5, 12|Figure 6|400|None|9|
|Figure 9, Figure 11|5, 12|Figure 6|0|BGA Heat Sink|9.5|
|Figure 9, Figure 11|5, 12|Figure 6|200|BGA Heat Sink|7|
|Figure 9, Figure 11|5, 12|Figure 6|400|BGA Heat Sink|5|



## **Table 4. 3.3V Output** 

|**Table 4. 3.3V Output**||||||
|---|---|---|---|---|---|
|**DERATING CURVE**|**VIN (V)**|**POWER LOSS CURVE**|**AIR FLOW(LFM)**|**HEAT SINK**|θ**JA (°C/W)**|
|Figure 12, Figure 14|12, 24|Figure 7|0|None|13.5|
|Figure 12, Figure 14|12, 24|Figure 7|200|None|11|
|Figure 12, Figure 14|12, 24|Figure 7|400|None|10|
|Figure 13, Figure 15|12, 24|Figure 7|0|BGA Heat Sink|10|
|Figure 13, Figure 15|12, 24|Figure 7|200|BGA Heat Sink|7|
|Figure 13, Figure 15|12, 24|Figure 7|400|BGA Heat Sink|5|
|||||||
|**Heat Sink Manufacturer**||**PART NUMBER**||**WEBSITE**||
|AAVID Thermalloy||375424B00034G||www.aavidthermalloy.com||
|Cool Innovations||4-050503P to 4-050508P||www.cooinnovations.com||



## **Layout Checklist/Example** 

The high integration of LTM4606 makes the PCB board layout very simple and easy. However, to optimize its electrical and thermal performance, some layout considerations are still necessary. 

- Use large PCB copper areas for high current path, including VIN, PGND and VOUT. It helps to minimize the PCB conduction loss and thermal stress. 

- Place high frequency ceramic input and output capacitors next to the VD, PGND and VOUT pins to minimize high frequency noise. 

- Place a dedicated power ground layer underneath the unit. 

- Use round corners for the PCB copper layer to minimize the radiated noise. 

- To minimize the EMI noise and reduce module thermal stress, use multiple vias for interconnection between top layer and other power layers on different locations. 

- Do not put vias directly on pads, unless they are capped. 

- Use a separated SGND ground copper area for components connected to signal pins. Connect the SGND to PGND underneath the unit. 

- Place one or more high frequency ceramic capacitors close to the connection into the system board. 

Figure 17 gives a good example of the recommended layout. 

**==> picture [239 x 160] intentionally omitted <==**

**----- Start of picture text -----**<br>
VIN CIN CIN<br>PGND<br>SIGNAL<br>GND<br>COUT COUT<br>VOUT<br>4606 F17<br>(LGA Shown, for BGA Use Circle Pads)<br>**----- End of picture text -----**<br>


**Figure 17. Recommended PCB Layout** 

Rev. E 

19 

For more information www.analog.com 

LTM4606 

## **APPLICATIONS INFORMATION** 

## **Frequency Adjustment** 

The LTM4606 is designed to typically operate at 800kHz across most input conditions. The fSET pin is typically left open. The switching frequency has been optimized for maintaining constant output ripple noise over most operating ranges. The 800kHz switching frequency and the 400ns minimum off time can limit operation at higher duty cycles like 5V to 3.3V, and produce excessive inductor ripple currents for lower duty cycle applications like 28V to 5V. 

## **Example for 5V Output** 

LTM4606 minimum on-time = 100ns tON = ((VOUT • 10pF)/IfSET), for VOUT > 4.8V use 4.8V 

LTM4606 minimum off-time = 400ns tOFF = t – tON, where t = 1/Frequency 

Duty Cycle = tON/t or VOUT/VIN 

Equations for setting frequency: 

IfSET = (VIN/(3 • RfSET)), where the internal RfSET is 41.2k. For 28V input operation, IfSET = 227µA. tON = ((4.8 • 10pF)/ IfSET), tON = 211ns. Frequency = (VOUT/(VIN • tON)) = (5V/ (28 • 211ns)) ~ 850kHz. The inductor ripple current begins to get high at the higher input voltages due to a larger voltage across the inductor. The current ripple is ~5A at 20% duty cycle for the integrated 1µH inductor. The inductor ripple current can be lowered at the higher input voltages by adding an external resistor from fSET to ground to increase the switching frequency. A 4A ripple current is chosen, and the total peak current is equal to 1/2 of the 4A ripple current plus the output current. For 5V output, current is limited to 5A, so the total peak current is less than 7A. This is below the 8A peak specified value. A 150k resistor is placed from fSET to ground, and the parallel combination of 150k and 41.2k equates to 32.3k. The IfSET calculation with 32.3k and 28V input voltage equals 289µA. This equates to a tON of 166ns. This will increase the switching frequency from 850kHz to ~1MHz for the 28V to 5V conversion. The minimum on time is above 100ns at 28V input. Since the switching frequency is approximately constant over input and output conditions, then the lower input voltage range is limited to 8V for the 1MHz operation due to the 400ns minimum off time. Equation: tON = (VOUT/VIN) • (1/ Frequency) equates to a 375ns on time, and a 400ns off 

time. Figure 18 shows an operating range of 10V to 28V for 1MHz operation with a 150k resistor to ground, and an 8V to 16V operating range for fSET floating. These modifications are made to provide wider input voltage ranges for the 5V output designs while limiting the inductor ripple current, and maintaining the 400ns minimum off-time. 

## **Example for 3.3V Output** 

LTM4606 minimum on-time = 100ns tON = ((VOUT • 10pF)/IfSET) 

LTM4606 minimum off-time = 400ns tOFF = t – tON, where t = 1/Frequency 

Duty Cycle (DC) = tON/t or VOUT/VIN 

Equations for setting frequency: 

IfSET = (VIN/(3 • RfSET)), for 28V input operation, IfSET = 227µA, tON = ((3.3 • 10pF)/IfSET), tON = 145ns, where the internal RfSET is 41.2k. Frequency = (VOUT/(VIN • tON)) = (3.3V/(28 • 145ns)) ~ 810kHz. The minimum on-time and minimum-off time are within specification at 146ns and 1089ns. But the 4.5V minimum input for converting 3.3V output will not meet the minimum off-time specification of 400ns. tON = 905ns, Frequency = 810kHz, tOFF = 329ns. 

## **Solution** 

Lower the switching frequency at lower input voltages to allow for higher duty cycles, and meet the 400ns minimum off-time at 4.5V input voltage. The off-time should be about 500ns with 100ns guard band. The duty cycle for (3.3V/4.5V) = ~73%. Frequency = (1 – DC)/tOFF or (1 – 0.73)/500ns = 540kHz. The switching frequency needs to be lowered to 540kHz at 4.5V input. tON = DC/ frequency, or 1.35µs. The fSET pin voltage compliance is 1/3 of VIN, and the IfSET current equates to 36µA with the internal 41.2k. The IfSET current needs to be 24µA for 540kHz operation. A resistor can be placed from VOUT to fSET to lower the effective IfSET current out of the fSET pin to 24µA. The fSET pin is 4.5V/3 =1.5V and VOUT = 3.3V, therefore a 150k resistor will source 12µA into the fSET node and lower the IfSET current to 24µA. This enables the 540kHz operation and the 4.5V to 28V input operation for down converting to 3.3V output as shown in Figure 19. The frequency will scale from 540kHz to 950kHz over this input range. This provides for an effective output current of 5A over the input range. 

Rev. E 

20 

For more information www.analog.com 

LTM4606 

## **TYPICAL APPLICATIONS** 

**==> picture [397 x 453] intentionally omitted <==**

**----- Start of picture text -----**<br>
VOUT<br>10V TO 28V<br>C1<br>10µF<br>R4 R3<br>100k 100k VD VIN PLLIN<br>5V AT 5A<br>PGOOD VOUT<br>C2<br>CIN ON/OFF RUNCOMP LTM4606 VFB 100pF C22µFOUT1 + C220µFOUT2<br>10µF35V INTVCC R8.25kFB 6.3V 6.3V<br>CERAMIC DRVCC FCB<br>x2 fSET MARG0 MARGIN<br>TRACK/SS MARG1 CONTROL REFER TO TABLE 2<br>MPGM FOR OUTPUT CAPACITOR<br>TRACK/SS SELECTIONS<br>SGND PGND R1<br>CONTROL<br>RfSET 392k<br>150k 5% MARGIN<br>IMPROVE EFFICIENCY<br>FOR ≥12V INPUT<br>4606 TA02<br>Figure 18. 10V to 28VIN, 5V at 5A Design<br>VOUT<br>4.5V TO 28V<br>C1<br>10µF<br>R4 R3<br>100k 100k VD VIN PLLIN<br>3.3V AT 5A<br>PGOOD VOUT<br>C2<br>CIN ON/OFF RUNCOMP LTM4606 VFB 100pF C22µFOUT1 + C220µFOUT2<br>10µF35V INTVCC R13.3kFB 6.3Vx2 6.3V<br>CERAMIC DRVCC FCB<br>x2 fSET MARG0 MARGIN<br>TRACK/SS MARG1 CONTROL<br>R150kfSET MPGM REFER TO TABLE 2FOR OUTPUT CAPACITOR<br>SGND PGND R1 SELECTIONS<br>TRACK/SS 392k<br>VOUT CONTROL 5% MARGIN<br>4606 TA03<br>**----- End of picture text -----**<br>


**Figure 19. 3.3V at 5A Design** 

Rev. E 

21 

For more information www.analog.com 

LTM4606 

## **TYPICAL APPLICATIONS** 

**==> picture [448 x 492] intentionally omitted <==**

**----- Start of picture text -----**<br>
VOUT<br>4.5V TO 28V C1 CLOCK SYNC<br>10µF<br>R4 R3<br>100k 100k VD VIN PLLIN<br>2.5V AT 6A<br>PGOOD VOUT C2<br>ON/OFF RUNCOMPINTVCC LTM4606 VFB R19.1kFB100pF C22µF6.3VOUT1 + C220µF6.3VOUT2<br>DRVCC FCB<br>fSET MARG0 MARGIN<br>TRACK/SS MARG1 CONTROL<br>CIN C4 MPGM<br>10µF35V 0.01µF SGND PGND R1<br>CERAMIC 392k<br>x2 5% MARGIN<br>4606 TA04<br>Figure 20. Typical 4.5V to 28VIN, 2.5V at 6A Design<br>VOUT<br>VIN<br>4.5V TO 28V<br>C1<br>10µF CLOCK SYNC<br>0° PHASE<br>R4 R2<br>100k 100k VD VIN PLLIN 2.5V AT 12A<br>PGOODRUN LTM4606 VOUT 220pFC6 C22µFOUT1 + COUT2<br>COMP VFB 6.3V 220µF<br>INTVCC FCB 6.3V<br>C210µF35V DRVfSET CC MARG0 MARGIN<br>+ C5 TRACK/SS MARG1 CONTROL<br>100µF C4 MPGM<br>2-PHASE 35V 0.33µF SGND PGND R1392k R9.53kFB<br>OSCILLATOR<br>V [+] OUT1 5% MARGIN<br>R5 C7 GND OUT2<br>118k 0.1µF SET MOD<br>C3<br>LTC6908-1 10µF CLOCK SYNC<br>180° PHASE<br>R3100k VD VIN PLLIN<br>PGOODRUN LTM4606 VOUT C22µFOUT3 + COUT4<br>COMP VFB 6.3V 220µF<br>C8 INTVCC FCB 6.3V<br>10µF<br>35V<br>DRVCC MARG0<br>fSET MARG1<br>TRACK/SS MPGM<br>SGND PGND R6<br>392k<br>5% MARGIN<br>4606 TA05<br>**----- End of picture text -----**<br>


**Figure 21. 2-Phase, Parallel 2.5V at 12A Design** 

Rev. E 

22 

For more information www.analog.com 

LTM4606 

## **TYPICAL APPLICATIONS** 

**==> picture [437 x 291] intentionally omitted <==**

**----- Start of picture text -----**<br>
3.3V<br>VIN<br>5V TO 28V<br>C3<br>10µF CLOCK SYNC<br>0° PHASE<br>R4 R2<br>100k 100k VD VIN PLLIN<br>3.3V AT 6A<br>PGOODRUN LTM4606 VOUT C622pF C100µFOUT1 + COUT2<br>COMP VFB 6.3V 220µF<br>6.3V<br>INTVCC FCB<br>C2 DRVCC<br>10µF fSET MARG0 MARGIN<br>+ C5 35V TRACK/SS MARG1 CONTROL<br>100µF MPGM<br>35V C7 SGND PGND R1 RFB1<br>OSCILLATOR2-PHASE 0.15µF 392k 13.3k<br>V [+] OUT1 3.3V 5% MARGIN<br>R5 C9 GND OUT2<br>118k 0.1µF SET MOD<br>C4<br>LTC6908-1 10µF CLOCK SYNC<br>R7 180° PHASE<br>R3100k 100k VD VIN PLLIN 2.5V AT 6A<br>PGOODRUN LTM4606 VOUT C122pF C100µFOUT3 + COUT4<br>COMP VFB 6.3V 220µF<br>6.3V<br>C8 3.3V TRACK INTVCC FCB<br>10µF<br>35V<br>R8 DRVCC MARG0 MARGIN<br>60.4k fSET MARG1 CONTROL<br>TRACK/SS MPGM<br>R9 SGND PGND R6 RFB2<br>19.1k 392k 19.1k<br>4606 TA06<br>**----- End of picture text -----**<br>


**Figure 22. 2-Phase, 3.3V and 2.5V Outputs at 6A with Tracking and Margining** 

**==> picture [445 x 290] intentionally omitted <==**

**----- Start of picture text -----**<br>
1.8V<br>4.5V TO 28V<br>C3<br>10µF CLOCK SYNC<br>0° PHASE<br>R4 R2<br>100k 100k VD VIN PLLIN 1.8V AT 6A<br>PGOODRUNCOMP LTM4606 VOUVFB T C6100pF C100µF6.3VOUT1 + C220µF6.3VOUT2<br>INTVCC FCB<br>C2 DRVCC<br>10µF fSET MARG0 MARGIN<br>+ C5 35V TRACK/SS MARG1 CONTROL<br>100µF MPGM<br>35V C7 SGND PGND R1 RFB1<br>OSCILLATOR2-PHASE 0.15µF 392k 30.1k<br>V [+] OUT1 1.8V 5% MARGIN<br>R5 C9 GND OUT2<br>182k 0.1µF SET MOD<br>C4<br>LTC6908-1 10µF CLOCK SYNC<br>R7 180° PHASE<br>R3100k 100k VD VIN PLLIN 1.5V AT 6A<br>C810µF 1.8V TRACK PGOODRUNCOMPINTVCCLTM4606 VFCBOUVFB T C1100pF C22µF6.3VOUT3 + C220µF6.3VOUT4<br>35V<br>R8 DRVCC MARG0 MARGIN<br>60.4k fSET MARG1 CONTROL<br>TRACK/SS MPGM<br>R9 SGND PGND R6 RFB2<br>40.2k 392k 40.2k<br>4606 TA07<br>**----- End of picture text -----**<br>


**Figure 23. 2-Phase, 1.8V and 1.5V Outputs at 6A with Tracking and Margining** 

Rev. E 

23 

For more information www.analog.com 

LTM4606 

## **PACKAGE DESCRIPTION** 

## **Pin Assignment Tables (Arranged by Pin Function)** 

|**PIN NAME**<br>A1<br>A2<br>A3<br>A4<br>A5<br>A6<br>VIN<br>VIN<br>VIN<br>VIN<br>VIN<br>VIN<br>B1<br>B2<br>B3<br>B4<br>B5<br>B6<br>VIN<br>VIN<br>VIN<br>VIN<br>VIN<br>VIN<br>C1<br>C2<br>C3<br>C4<br>C5<br>C6<br>VIN<br>VIN<br>VIN<br>VIN<br>VIN<br>VIN|**PIN NAME**<br>D1<br>D2<br>D3<br>D4<br>D5<br>D6<br>PGND<br>PGND<br>PGND<br>PGND<br>PGND<br>PGND<br>E1<br>E2<br>E3<br>E4<br>E5<br>E6<br>E7<br>E8<br>PGND<br>PGND<br>PGND<br>PGND<br>PGND<br>PGND<br>PGND<br>PGND<br>F1<br>F2<br>F3<br>F4<br>F5<br>F6<br>F7<br>F8<br>F9<br>PGND<br>PGND<br>PGND<br>PGND<br>PGND<br>PGND<br>PGND<br>PGND<br>PGND<br>G1<br>G2<br>G3<br>G4<br>G5<br>G6<br>G7<br>G8<br>G9<br>G10<br>G11<br>PGND<br>PGND<br>PGND<br>PGND<br>PGND<br>PGND<br>PGND<br>PGND<br>PGND<br>PGND<br>PGND<br>H1<br>H2<br>H3<br>H4<br>H5<br>H6<br>H7<br>H8<br>H9<br>H10<br>H11<br>PGND<br>PGND<br>PGND<br>PGND<br>PGND<br>PGND<br>PGND<br>PGND<br>PGND<br>PGND<br>PGND|**PIN NAME**<br>D1<br>D2<br>D3<br>D4<br>D5<br>D6<br>PGND<br>PGND<br>PGND<br>PGND<br>PGND<br>PGND<br>E1<br>E2<br>E3<br>E4<br>E5<br>E6<br>E7<br>E8<br>PGND<br>PGND<br>PGND<br>PGND<br>PGND<br>PGND<br>PGND<br>PGND<br>F1<br>F2<br>F3<br>F4<br>F5<br>F6<br>F7<br>F8<br>F9<br>PGND<br>PGND<br>PGND<br>PGND<br>PGND<br>PGND<br>PGND<br>PGND<br>PGND<br>G1<br>G2<br>G3<br>G4<br>G5<br>G6<br>G7<br>G8<br>G9<br>G10<br>G11<br>PGND<br>PGND<br>PGND<br>PGND<br>PGND<br>PGND<br>PGND<br>PGND<br>PGND<br>PGND<br>PGND<br>H1<br>H2<br>H3<br>H4<br>H5<br>H6<br>H7<br>H8<br>H9<br>H10<br>H11<br>PGND<br>PGND<br>PGND<br>PGND<br>PGND<br>PGND<br>PGND<br>PGND<br>PGND<br>PGND<br>PGND|**PIN NAME**<br>J1<br>J2<br>J3<br>J4<br>J5<br>J6<br>J7<br>J8<br>J9<br>J10<br>J11<br>VOUT<br>VOUT<br>VOUT<br>VOUT<br>VOUT<br>VOUT<br>VOUT<br>VOUT<br>VOUT<br>VOUT<br>VOUT<br>K1<br>K2<br>K3<br>K4<br>K5<br>K6<br>K7<br>K8<br>K9<br>K10<br>K11<br>VOUT<br>VOUT<br>VOUT<br>VOUT<br>VOUT<br>VOUT<br>VOUT<br>VOUT<br>VOUT<br>VOUT<br>VOUT<br>L1<br>L2<br>L3<br>L4<br>L5<br>L6<br>L7<br>L8<br>L9<br>L10<br>L11<br>VOUT<br>VOUT<br>VOUT<br>VOUT<br>VOUT<br>VOUT<br>VOUT<br>VOUT<br>VOUT<br>VOUT<br>VOUT<br>M1<br>M2<br>M3<br>M4<br>M5<br>M6<br>M7<br>M8<br>M9<br>M10<br>M11<br>VOUT<br>VOUT<br>VOUT<br>VOUT<br>VOUT<br>VOUT<br>VOUT<br>VOUT<br>VOUT<br>VOUT<br>VOUT|**PIN NAME**|**PIN NAME**|
|---|---|---|---|---|---|
||D1<br>D2<br>D3<br>D4<br>D5<br>D6|PGND<br>PGND<br>PGND<br>PGND<br>PGND<br>PGND||A7<br>A8<br>A9<br>A10<br>A11<br>A12|INTVCC<br>PLLIN<br>TRACK/SS<br>RUN<br>COMP<br>MPGM|
||E1<br>E2<br>E3<br>E4<br>E5<br>E6<br>E7<br>E8|PGND<br>PGND<br>PGND<br>PGND<br>PGND<br>PGND<br>PGND<br>PGND||B7<br>B8<br>B9<br>B10<br>B11<br>B12|VD<br>-<br>RUN<br>-<br>MPGM<br>fSET|
|||||C7<br>C8<br>C9<br>C10<br>C11<br>C12|VD<br>-<br>-<br>DRVCC<br>MARG1<br>MARG0|
||F1<br>F2<br>F3<br>F4<br>F5<br>F6<br>F7<br>F8<br>F9|PGND<br>PGND<br>PGND<br>PGND<br>PGND<br>PGND<br>PGND<br>PGND<br>PGND||||
|||||D7<br>D8<br>D9<br>D10<br>D11<br>D12|-<br>-<br>SGND<br>-<br>COMP<br>MARG1|
||G1<br>G2<br>G3<br>G4<br>G5<br>G6<br>G7<br>G8<br>G9<br>G10<br>G11|PGND<br>PGND<br>PGND<br>PGND<br>PGND<br>PGND<br>PGND<br>PGND<br>PGND<br>PGND<br>PGND||||
|||||E9<br>E10<br>E11<br>E12|-<br>-<br>DRVCC<br>DRVCC|
|||||F10<br>F11<br>F12|-<br>-<br>VFB|
|||||G12|PGOOD|
|||||H12|SGND|
||H1<br>H2<br>H3<br>H4<br>H5<br>H6<br>H7<br>H8<br>H9<br>H10<br>H11|PGND<br>PGND<br>PGND<br>PGND<br>PGND<br>PGND<br>PGND<br>PGND<br>PGND<br>PGND<br>PGND||||
|||||J12|NC|
|||||K12|NC|
|||||L12|NC|
|||||M12|FCB|
|||||||



Rev. E 

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For more information www.analog.com 

LTM4606 

## **PACKAGE DESCRIPTION** 

**==> picture [472 x 622] intentionally omitted <==**

**----- Start of picture text -----**<br>
6<br>SEE NOTES<br>PIN 1<br>12 11 10 9 8 7 6 5 4 3 2 1<br>A<br>BGA 133 0517 REV A<br>B<br>C<br>D<br>E<br>e<br>F<br>G<br>G<br>H<br>PACKAGE BOTTOM VIEW<br>J<br>LTMXXXXXX µModule<br>K PACKAGE IN TRAY LOADING ORIENTATION<br>L b PACKAGE ROW AND COLUMN LABELING MAY VARY  AMONG µModule PRODUCTS. REVIEW EACH PACKAGE  LAYOUT CAREFULLY<br>!<br>M DETAILS OF PIN #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE PIN #1 IDENTIFIER MAY BE EITHER A MOLD OR  MARKED FEATURE<br>DETAIL A b e NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994 2. ALL DIMENSIONS ARE IN MILLIMETERS 3        BALL DESIGNATION PER JESD MS-028 AND JEP95 4 5. PRIMARY DATUM -Z- IS SEATING PLANE 6 PIN “A1” TRAY PIN 1 BEVEL<br>3 COMPONENT<br>F<br>SEE NOTES<br>A A2<br>3.42mm) NOTES BALL HT BALL DIMENSION PAD DIMENSION SUBSTRATE THK MOLD CAP HT<br>× DETAIL B<br>PACKAGE SIDE VIEW MAX 3.62 0.70 2.92 0.90 0.66 0.37 2.55 0.15 0.10 0.20 0.30 0.15<br>15mm<br>× Y<br>BGA Package A1 SUBSTRATE H1 MXZ MZ DIMENSIONS NOM 3.42 0.60 2.82 0.75 0.63 15.0 15.0 1.27 13.97 13.97 0.32 2.50<br>ddd eee<br>b1 TOTAL NUMBER OF BALLS: 133<br>ccc  Z MOLD CAP H2 DETAIL B DETAIL A MIN 3.22 0.50 2.72 0.60 0.60 0.27 2.45<br>133-Lead (15mm (Reference LTC DWG # 05-08-1943 Rev A) Øb (133 PLACES) A A1 A2 b b1 D E e F G H1 H2 aaa bbb ccc ddd eee<br>SYMBOL<br>aaa  Z<br>0.0000<br>D X 6.9850 5.7150 4.4450 3.1750 1.9050 0.6350 0.6350 1.9050 3.1750 4.4450 5.7150 6.9850<br>Y<br>E<br>TOP VIEW<br>PACKAGE TOP VIEW<br>SUGGESTED PCB LAYOUT<br>4<br>PIN “A1” CORNER<br>0.630 ±0.025 Ø 133x<br>Z<br>Z<br>Z//  bbb<br>6.9850<br>5.7150<br>4.4450<br>3.1750<br>1.9050<br>0.6350<br>0.0000<br>0.6350<br>1.9050<br>3.1750<br>4.4450<br>5.7150<br>6.9850<br>aaa  Z<br>**----- End of picture text -----**<br>


Rev. E 

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For more information www.analog.com 

LTM4606 

## **PACKAGE DESCRIPTION** 

**==> picture [474 x 619] intentionally omitted <==**

**----- Start of picture text -----**<br>
7<br>SEE NOTES<br>C(0.30) PAD 1<br>12 11 10 9 8 7 6 5 4 3 2 1<br>DETAIL A BA<br>LGA 133 1212 REV A<br>C<br>D<br>E<br>13.97 BSC F<br>G<br>H µModule<br>LTMXXXXXX<br>PACKAGE BOTTOM VIEW<br>J PACKAGE IN TRAY LOADING ORIENTATION<br>K<br>L<br>M COMPONENT PIN “A1” TRAY PIN 1 BEVEL<br>1.27 BSC<br>13.97 BSC PADS 3<br>SEE NOTES<br>0.12 – 0.28<br> 2.82mm)<br>× 2.72 – 2.92 DETAIL B<br> 15mm<br>×<br>0.27 – 0.37 Y<br>X<br>LGA Package SUBSTRATE S<br>eee<br>MOLD CAP DETAIL B 0.10 0.10 0.05<br>DETAIL A TOLERANCE<br>PACKAGE ROW AND COLUMN LABELING MAY VARY  AMONG µModule PRODUCTS. REVIEW EACH PACKAGE  LAYOUT CAREFULLY<br>133-Lead (15mm  (Reference LTC DWG # 05-08-1766 Rev A) !<br>DETAILS OF PAD #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE PAD #1 IDENTIFIER MAY BE EITHER A MOLD OR  MARKED FEATURE aaa bbb eee<br>0.630 ±0.025 SQ. 133x<br>2.45 – 2.55 aaa  Z NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994 2. ALL DIMENSIONS ARE IN MILLIMETERS 3        LAND DESIGNATION PER JESD MO-222, SPP-010 4 5. PRIMARY DATUM -Z- IS SEATING PLANE 6. THE TOTAL NUMBER OF PADS: 133 7 SYMBOL<br>Y 15 BSC<br>X<br>15 BSC<br>TOP VIEW<br>PACKAGE TOP VIEW<br>SUGGESTED PCB LAYOUT<br>aaa  Z PAD 1 CORNER 4 6.9850 5.7150 4.4450 3.1750 1.9050 0.6350 0.0000 0.6350 1.9050 3.1750 4.4450 5.7150 6.9850<br>Z<br>Zbbb<br>6.9850<br>5.7150<br>4.4450<br>3.1750<br>1.9050<br>0.6350<br>0.0000<br>0.6350<br>1.9050<br>3.1750<br>4.4450<br>5.7150<br>6.9850<br>**----- End of picture text -----**<br>


Rev. E 

26 

For more information www.analog.com 

LTM4606 

## **REVISION HISTORY** 

|**REV**|**DATE**|**DESCRIPTION**|**PAGE NUMBER**|
|---|---|---|---|
|A|3/10|Change to Features.<br>Change to Absolute Maximum Ratings.<br>Changes to Electrical Characteristics.<br>Changes to Related Parts.|1<br>2<br>2, 3<br>25|
|B|3/11|Text updated throughout the data sheet.<br>Graph replaced on the front page, Figure 2, and Figure 16.<br>Added value of 1µH to inductor on Figure 1.<br>Updated Related Parts.|1-28<br>1, 12, 17<br>9<br>28|
|C|10/13|Add BGA Package Option.<br>Add Start Into Pre-Bias Output Graph.<br>Clarify Voltage Margining function.<br>Add Recommended External Heat Sink Vendors.<br>Update LGA Package Outline Drawing.|1, 2, 19, 25, 28<br>6<br>11<br>19<br>26|
|D|2/14|Added SnPb package option.|1, 2|
|E|6/21|Added MPV to part marking.|2|



Rev. E 

27 

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implicatiFor more informati **on** or otherwise under any patent or patent rights of Analog Devices.www.analog.com 

LTM4606 

## **PACKAGE PHOTOGRAPH** 

**==> picture [379 x 87] intentionally omitted <==**

**----- Start of picture text -----**<br>
2.82mm 3.42mm<br>15mm _ 15mm ><br>seeee<br>15mm 15mm<br>os LT LINEAR SEER *<br> estat oi) SERRE Eee<br>**----- End of picture text -----**<br>


## **RELATED PARTS** 

|**PART NUMBER**|**DESCRIPTION**<br>~~po~~|**COMMENTS**|
|---|---|---|
|LTM4601/|12A DC/DC µModule Regulator with PLL, Output|Synchronizable, PolyPhase Operation, LTM4601-1/LTM4601A-1 Version Has No|
|LTM4601A|Tracking/Margining and Remote Sensing|Remote Sensing, LGA Package|
|LTM4618|6A DC/DC µModule Regulator with PLL,|4.5V ≤ VIN≤ 26.5V, 0.8V ≤ VOUT≤ 5V, Synchronizable, 9mm × 15mm × 4.3mm|
||Output Tracking|LGA Package|
|LTM4604A|Low VIN4A DC/DC µModule Regulator<br>~~po~~|2.375V ≤ VIN≤ 5.5V, 0.8V ≤ VOUT≤ 5V, 9mm × 15mm × 2.3mm LGA Package|
|LTM4608A|Low VIN8A DC/DC µModule Regulator<br>~~po~~|2.375V ≤ VIN≤ 5.5V, 0.6V ≤ VOUT≤ 5V, 9mm × 15mm × 2.8mm LGA Package|
|LTM4612|Low Noise 5A, 15VOUTDC/DC µModule Regulator<br>~~po~~|Low Noise, with PLL, Output Tracking and Margining, LTM4606 Pin-Compatible|
|LTM4613|Low Noise 8A, 15VOUTDC/DC µModule Regulator<br>~~po~~|Low Noise, with PLL, Output Tracking and Margining, EN55022B Compliant|
|LTM4627|15A DC/DC µModule Regulator|4.5V ≤ VIN≤ 20V, 0.6V ≤ VOUT≤ 5V, ±1.5% Total DC Output Accuracy,|
|||15mm × 15mm × 4.32mm LGA Package|
|**EN55022 Class B Certified DC/DC µModule Regulators**|||
|LTM8020|High VIN0.2A DC/DC Step-Down µModule Regulator<br>~~PO~~|4V ≤ VIN≤ 36V, 1.25V ≤ VOUT≤ 5V, 6.25mm × 6.25mm × 2.3mm LGA Package|
|LTM8021|High VIN0.5A DC/DC Step-Down µModule Regulator<br>~~po~~|3V ≤ VIN≤ 36V, 0.8V ≤ VOUT≤ 5V, 6.25mm × 11.25mm × 2.8mm LGA Package|
|LTM8022/|36VIN, 1A and 2A DC/DC µModule Regulators|Pin Compatible, 4.5V ≤ VIN≤ 36V, 9mm × 11.25mm × 2.8mm LGA Package|
|LTM8023|||
|LTM8031/|1A, 2A EMC DC/DC µModule Regulators|EN55022 Class B Compliant, 3.6V ≤ VIN≤ 36V, 0.8V ≤ VOUT≤ 10V,|
|LTM8032||Pin Compatible, 9mm × 15mm × 2.82mm LGA Package|
|LTM8033|3A EMC DC/DC µModule Regulator|3.6V ≤ VIN≤ 36V, 0.8V ≤ VOUT≤ 24V, 11.25mm × 15mm × 4.32mm LGA|
|||Package|



Rev. E 

06/21 

28 

For more information www.analog.com Ca A[bevices] 

www.analog.com 

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