LIS2DTW12TR

MEMS Module, 3-Axis Accelerometer, Temperature Sensor, 1.62 V to 3.6 V, ± 16g, LGA-12

⚠️ Reference pricing provided. In case of supply shortages, we will connect you with our trusted procurement partners to ensure your project's continuity.
Manufacturer: STMICROELECTRONICS
Product type: MEMS Accelerometers
MEMS Module Function:Tri-Axis Accelerometer; Supply Voltage Min:1.62V; Supply Voltage Max:3.6V; Sensor Case Style:LGA; No. of Pins:12Pins; Gyroscope Range:-; Acceleration Range:± 2g, ±
MSL: MSL 1 - Unlimited
SVHC: No SVHC (25-Jun-2025)
No. of Pins: 12Pins
Sensor Type: Accelerometer, Temperature Sensor
Sensing Axis: X, Y, Z
Product Range: -
Qualification: -
Sensitivity Typ: 0.24mg/digit, 0.48mg/digit, 0.97mg/digit, 1.95mg/digit
Output Interface: I2C, SPI
Sensor Case Style: LGA
Supply Voltage Max: 3.6V
Supply Voltage Min: 1.62V
MEMS Module Function: Tri-Axis Accelerometer
Sensor Case / Package: LGA
Operating Temperature Max: 85°C
Operating Temperature Min: -40°C
Temperature Sensing Range: -40°C to +85°C
Sensing Range - Accelerometer: ± 2g, ± 4g, ± 8g, ± 16g
Delivery and price
Units per pack	5000
Price	1.28 €
Current stock	1000+
Lead time	30 days
Datasheet
**LIS2DTW12** 

Datasheet 

## MEMS digital output dual motion and temperature sensor 

## **Features** 

- Ultra-low power consumption: 50 nA in power-down mode, below 1 µA in active low-power mode 

- Very low noise: down to 1.3 m _g_ RMS in low-power mode 

- 0.8 °C (typ. accuracy) embedded temperature sensor 

- Multiple operating modes with multiple bandwidths 

- Android stationary detection, motion detection 

- Supply voltage, 1.62 V to 3.6 V 

- Independent IO supply 

- ±2 _g_ /±4 _g_ /±8 _g_ /±16 _g_ full scale 

- High-speed I²C/SPI digital output interface 

- Single data conversion on demand 

- 16-bit accelerometer data output 

- 12-bit temperature data output 

- Self-test 

- 32-level FIFO 

- 10000 _g_ high shock survivability 

- • ECOPACK, RoHS and “Green” compliant 

## **Applications** 

|**Product summary**|**Product summary**|
|---|---|
|**Order code**|LIS2DTW12TR|
|**Temperature**<br>**range [°C]**|-40 to +85|
|**Package**|LGA-12|
|**Packing**|Tape and reel|



## **Product label** 

- Fragile shipment tracking 

- Motion and temperature monitoring in battery-powered devices 

- Gesture recognition and gaming 

- Motion-activated functions and user interfaces 

- Display orientation 

- Tap/double-tap recognition 

- Free-fall detection 

- Smart power saving for handheld devices 

- • Hearing aids 

- Portable healthcare devices 

- • Wireless sensor nodes 

- Motion-enabled metering devices 

## **Description** 

The LIS2DTW12 is an ultra-low-power high-performance three-axis linear accelerometer and temperature sensor belonging to the “femto” family which leverages on the robust and mature manufacturing processes already used for the production of micromachined accelerometers. 

The device has user-selectable full scales of ±2 _g_ /±4 _g_ /±8 _g_ /±16 _g_ and is capable of measuring accelerations with output data rates from 1.6 Hz to 1600 Hz. 

The LIS2DTW12 has an embedded 0.8 °C (typ. accuracy) temperature sensor with ODRs ranging from 50 to 1.6 Hz and resolution from 8 to 12 bits. 

**DS12825** - **Rev 3** - **July 2019** For further information contact your local STMicroelectronics sales office. 

www.st.com 

**LIS2DTW12** 

The LIS2DTW12 has an integrated 32-level first-in, first-out (FIFO) buffer allowing the user to store data in order to limit intervention by the host processor. 

The embedded self-test capability allows the user to check the functioning of the sensor in the final application. 

The device has a dedicated internal engine to process motion and acceleration detection including free-fall, wakeup, highly configurable single/double-tap recognition, activity/inactivity, stationary/motion detection, portrait/landscape detection and 6D/4D orientation. 

The LIS2DTW12 is available in a small thin plastic land grid array package (LGA) and it is guaranteed to operate over an extended temperature range from -40 °C to +85 °C. 

**DS12825** - **Rev 3** 

**page 2/65** 

**LIS2DTW12 Block diagram and pin description** 

**1 Block diagram and pin description** 

## **1.1 Block diagram** 

**Figure 1. Block diagram** 

**==> picture [374 x 145] intentionally omitted <==**

**----- Start of picture text -----**<br>
X+<br>Y+ CHARGE<br>Z+ AMPLIFIE R CS<br>A/D  CONTROL  I C2 SCL/SPC<br>a MUX CONVERTER LOGIC SDA/SDO/SDI<br>Z- SPI<br>SDO/SA0<br>Y-<br>X-<br>TEMPERATURE SENSOR<br>SELF TEST  REFERENCE TRIMMINGCIRCUITS CLOCK 32 LevelFIFO  INTERRUPT GEN.CONTROL LOGIC& INT1INT2<br>**----- End of picture text -----**<br>


**DS12825** - **Rev 3** 

**page 3/65** 

**LIS2DTW12 Pin description** 

## **1.2 Pin description** 

**Figure 2. Pin connections** 

**==> picture [371 x 191] intentionally omitted <==**

**----- Start of picture text -----**<br>
Z<br>1<br>VDDIO 10 11 12 1 SCL/SPC<br>VDD 9 2 CS<br>GND 8 3 SDO/SA0<br>X Y<br>RES 7 6 5 4 SDA/SDI/SDO<br>(TOPVIEW)<br>DIRECTION OF THE<br>DETECTABLE<br>ACCELERATIONS (BOTTOM VIEW)<br>INT2 INT1<br>GND NC<br>**----- End of picture text -----**<br>


**Table 1. Pin description** 

|**Pin#**|**Name**|**Function**|
|---|---|---|
|1|SCL<br>SPC|I²C serial clock (SCL)<br>SPI serial port clock (SPC)|
|2(1)|CS|SPI enable<br>I²C/SPI mode selection<br>(1: SPI idle mode / I²C communication enabled;<br>0: SPI communication mode / I²C disabled)|
|3(1)|SDO<br>SA0|SPI serial data output (SDO)<br>I²C less significant bit of the device address (SA0)|
|4|SDA<br>SDI<br>SDO|I²C serial data (SDA)<br>SPI serial data input (SDI)<br>3-wire interface serial data output (SDO)|
|5|NC|Internally not connected. Can be tied to VDD, VDDIO, or GND.|
|6|GND|0 V supply|
|7|RES|Connect to GND|
|8|GND|0 V supply|
|9|VDD|Power supply|
|10|VDD_IO|Power supply for I/O pins|
|11|INT2|Interrupt pin 2. Clock input when selected in single data conversion on demand.|
|12|INT1|Interrupt pin 1|



_1. SDO/SA0 and CS pins are internally pulled up. Refer to Table 2. Internal pull-up values (typ.) for SDO/SA0 and CS pins for the internal pull-up values (typ)._ 

**DS12825** - **Rev 3** 

**page 4/65** 

**LIS2DTW12 Pin description** 

**Table 2. Internal pull-up values (typ.) for SDO/SA0 and CS pins** 

|**VddIO**|**Resistor value for SDO/SA0 and CS pins**|
|---|---|
|**_**|**Typ. (kΩ)**|
|1.7 V|54.4|
|1.8 V|49.2|
|2.5 V|30.4|
|3.6 V|20.4|



**DS12825** - **Rev 3** 

**page 5/65** 

**LIS2DTW12 Mechanical and electrical specifications** 

## **2 Mechanical and electrical specifications** 

## **2.1 Mechanical characteristics** 

@ Vdd = 1.8 V, T = 25 °C unless otherwise noted. The product is factory calibrated at 1.8 V. The operational power supply range is from 1.62 V to 3.6 V. 

**Table 3. Mechanical characteristics** 

|**Symbol**|**Parameter**|**Test conditions**|**Min. **|**Typ.(1) **|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|FS|Measurement range|||±2||_g_|
|||||±4|||
|||||±8|||
|||||±16|||
|So|Sensitivity|@ FS ±2_g_in High-Performance Mode and all low-power<br>modes except Low-Power Mode 1||0.244||m_g_/digit|
|||@ FS ±4_g_in High-Performance Mode and all low-power<br>modes except Low-Power Mode 1||0.488|||
|||@ FS ±8_g_in High-Performance Mode and all low-power<br>modes except Low-Power Mode 1||0.976|||
|||@ FS ±16_g_in High-Performance Mode and all low-<br>power modes except Low-Power Mode 1||1.952|||
|||@ FS ±2_g_in Low-Power Mode 1||0.976|||
|||@ FS ±4_g_in Low-Power Mode 1||1.952|||
|||@ FS ±8_g_in Low-Power Mode 1||3.904|||
|||@ FS ±16_g_in Low-Power Mode 1||7.808|||
|An|Noise density - High-performance<br>Mode(2)|@ FS ±2_g_||90||µ_g_/√Hz|
|RMS|RMS noise - Low-Power Modes(3)<br>@ FS ±2_g_|Low-Power Mode 4||1.3||m_g_(RMS)|
|||Low-Power Mode 3||1.8|||
|||Low-Power Mode 2||2.4|||
|||Low-Power Mode 1||4.5|||
|TyOff|Zero-_g_level offset accuracy(4)|||±20||m_g_|
|TCO|Zero-g offset change vs. temperature|||±0.2||m_g_/°C|
|TCS|Sensitivity change vs. temperature|||0.01||%/°C|
|ST|Self-test positive difference||70||1500|m_g_|



_1. Typical specifications are not guaranteed._ 

_2. Noise density is the same for all ODRs. Low-noise setting enabled._ 

_3. RMS noise is the same for all ODRs. Low-noise setting enabled._ 

_4. Values after factory calibration test and trimming._ 

**DS12825** - **Rev 3** 

**page 6/65** 

**LIS2DTW12 Electrical characteristics** 

## **2.2 Electrical characteristics** 

@ Vdd = 1.8 V, T = 25 °C unless otherwise noted. The product is factory calibrated at 1.8 V. The operational power supply range is from 1.62 V to 3.6 V. 

**Table 4. Electrical characteristics** 

|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.(1)**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|Vdd|Supply voltage||1.62|1.8|3.6|V|
|Vdd_IO|I/O pins supply voltage(2)||1.62||Vdd+0.1|V|
|IddHR|Current consumption in High-Performance Mode(3)|@ ODR range<br>12.5 Hz - 1600 Hz, 14-bit||90||µA|
|IddLP|Current consumption in Low-Power Mode(4)|ODR 100 Hz||5||µA|
|||ODR 50 Hz||3|||
|||ODR 12.5 Hz||1|||
|||ODR 1.6 Hz||0.38|||
|Idd_PD|Current consumption in power-down|||50||nA|
|VIH|Digital high-level input voltage||0.8*Vdd_IO|||V|
|VIL|Digital low-level input voltage||||0.2*Vdd_IO|V|
|VOH|Digital high-level output voltage|IOH= 4 mA(5)|VDD_IO - 0.2 V|||V|
|VOL|Digital low-level output voltage|IOL= 4 mA(5)|||0.2 V|V|



_1. Typical specifications are not guaranteed._ 

_2. It is possible to remove Vdd maintaining Vdd_IO without blocking the communication busses. In this condition the measurement chain is powered off._ 

_3. Low-noise setting disabled._ 

_4. Low-Power Mode 1. Low-noise setting disabled._ 

_5. 4 mA is the maximum driving capability, ie. the maximum DC current that can be sourced/sunk by the digital pad in order to guarantee the correct digital output voltage levels VOH and VOL._ 

**DS12825** - **Rev 3** 

**page 7/65** 

**LIS2DTW12 Temperature sensor characteristics** 

## **2.3 Temperature sensor characteristics** 

@ Vdd = 1.8 V, T = 25 °C unless otherwise noted. 

**Table 5. Temperature sensor characteristics** 

|**Symbol**|**Parameter**|**Min.**|**Typ.(1)**|**Max.**|**Unit**|
|---|---|---|---|---|---|
|Top|Operating temperature range|-40||+85|°C|
|Tacc|Temperature accuracy (0 °C to 70 °C)||±0.8||°C|
||Temperature accuracy (-40 °C to +85 °C)||±1.3|||
|TODR|Temperature refresh rate in High-Performance Mode for all ODRs<br>or in low-power modes for ODRs equal to 200/100/50 Hz||50||Hz|
||Temperature refresh rate in low-power modes for ODR equal to 25 Hz||25|||
||Temperature refresh rate in low-power modes for ODR equal to 12.5 Hz||12.5|||
||Temperature refresh rate in low-power modes for ODR equal to 1.6 Hz||1.6|||



_1. Typical specifications are not guaranteed._ 

**DS12825** - **Rev 3** 

**page 8/65** 

**LIS2DTW12 Communication interface characteristics** 

## **2.4 Communication interface characteristics** 

## **2.4.1 SPI - serial peripheral interface** 

Subject to general operating conditions for Vdd and Top. 

**Table 6. SPI slave timing values** 

|**Smbol**|**Parameter**|**Value (1)**|**Value (1)**|**Unit**|
|---|---|---|---|---|
|**y**||**Min**|**Max**||
|tc(SPC)|SPI clock cycle|100||ns|
|fc(SPC)|SPI clock frequency||10|MHz|
|tsu(CS)|CS setup time|6||ns|
|th(CS)|CS hold time|8|||
|tsu(SI)|SDI input setup time|12|||
|th(SI)|SDI input hold time|15|||
|tv(SO)|SDO valid output time||50||
|th(SO)|SDO output hold time|9|||
|tdis(SO)|SDO output disable time||50||



_1. 10 MHz clock frequency for SPI with both 4 and 3 wires, based on characterization results, not tested in production._ 

**Figure 3. SPI slave timing diagram** 

**==> picture [343 x 132] intentionally omitted <==**

**----- Start of picture text -----**<br>
CS<br>tsu(CS) tc(SPC) th(CS)<br>SPC<br>tsu(SI) th(SI)<br>SDI MSB IN  LSB IN<br>tv(SO) th(SO) tdis(SO)<br>SDO MSB OUT  LSB OUT<br>**----- End of picture text -----**<br>


_Note: Measurement points are done at 0.2·Vdd_IO and 0.8·Vdd_IO, for both input and output ports._ 

**DS12825** - **Rev 3** 

**page 9/65** 

**LIS2DTW12 Communication interface characteristics** 

## **2.4.2 I²C - inter-IC control interface** 

Subject to general operating conditions for Vdd and Top. 

**Table 7. I²C slave timing values** 

|**Smbol**|**Parameter**|**I²C standard mode(1)**|**I²C standard mode(1)**|**I²C fast mode(1)**|**I²C fast mode(1)**|**Unit**|
|---|---|---|---|---|---|---|
|**y**||**Min**|**Max**|**Min**|**Max**||
|f(SCL)|SCL clock frequency|0|100|0|400|kHz|
|tw(SCLL)|SCL clock low time|4.7||1.3||µs|
|tw(SCLH)|SCL clock high time|4.0||0.6|||
|tsu(SDA)|SDA setup time|250||100||ns|
|th(SDA)|SDA data hold time|0.01|3.45|0.01|0.9|µs|
|th(ST)|START condition hold time|4||0.6||µs|
|tsu(SR)|Repeated START condition setup time|4.7||0.6|||
|tsu(SP)|STOP condition setup time|4||0.6|||
|tw(SP:SR)|Bus free time between STOP and START condition|4.7||1.3|||



_1. Data based on standard I²C protocol requirement, not tested in production._ 

**Figure 4. I²C slave timing diagram** 

**==> picture [349 x 134] intentionally omitted <==**

**----- Start of picture text -----**<br>
REPEATED<br>START<br>START<br>tsu(SR)<br>SDA tw(SP:SR) START<br>tsu(SDA) th(SDA)<br>tsu(SP) STOP<br>SCL<br>th(ST) tw(SCLL) tw(SCLH)<br>**----- End of picture text -----**<br>


Note: Measurement points are done at 0.2·Vdd_IO and 0.8·Vdd_IO, for both ports. 

**DS12825** - **Rev 3** 

**page 10/65** 

**LIS2DTW12 Communication interface characteristics** 

## **Table 8. I²C high-speed mode specifications at 1 MHz and 3.4 MHz** 

|**Mode**|**Symbol**|**Parameter**|**Min**|**Max**|**Unit**|
|---|---|---|---|---|---|
|Fast mode plus(1)|fSCL|SCL clock frequency|0|1|MHz|
||tHD;STA|Hold time (repeated) START condition|260|-|ns|
||tLOW|Low period of the SCL clock|500|-||
||tHIGH|High period of the SCL clock|260|-||
||tSU;STA|Setup time for a repeated START condition|260|-||
||tHD;DAT|Data hold time|0|-||
||tSU;DAT|Data setup time|50|-||
||trDA|Rise time of SDA signal|-|120||
||tfDA|Fall time of SDA signal|-|120||
||trCL|Rise time of SCL signal|20*Vdd/5.5|120||
||tfCL|Fall time of SCL signal|20*Vdd/5.5|120||
||tSU;STO|Setup time for STOP condition|260|-||
||Cb|Capacitive load for each bus line|-|550|pF|
||tVD;DAT|Data valid time|-|450|ns|
||tVD;ACK|Data valid acknowledge time|-|450||
||VnL|Noise margin at low level|0.1Vdd|-|V|
||VnH|Noise margin at high level|0.2Vdd|-||
||tSP|Pulse width of spikes that must be suppressed by the input filter|0|50|ns|
|High-speed mode(1)|fSCLH|SCLH clock frequency|0|3.4|MHz|
||tSU;STA|Setup time for a repeated START condition|160|-|ns|
||tHD;STA|Hold time (repeated) START condition|160|-||
||tLOW|Low period of the SCLH clock|160|-||
||tHIGH|High period of the SCLH clock|60|-||
||tSU;DAT|Data setup time|10|-||
||tHD;DAT|Data hold time|0|70||
||trCL|Rise time of SCLH signal|10|40||
||trCL1|Rise time of SCLH signal after a repeated START condition and after an<br>acknowledge bit|10|80||
||tfCL|Fall time of SCLH signal|10|40||
||trDA|Rise time of SDAH signal|10|80||
||tfDA|Fall time of SDAH signal|10|80||
||tSU;STO|Setup time for STOP condition|160|-||
||Cb|Capacitive load for each bus line|-|100|pF|
||VnH|Noise margin at high level|0.2Vdd|-|V|
||tSP|Pulse width of spikes that must be suppressed by the input filter|0|10|ns|



_1. Data based on characterization, not tested in production._ 

**DS12825** - **Rev 3** 

**page 11/65** 

**LIS2DTW12 Absolute maximum ratings** 

## **2.5 Absolute maximum ratings** 

Stresses above those listed as “absolute maximum ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device under these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. 

**Table 9. Absolute maximum ratings** 

|**Symbol**<br>~~a~~|**Ratings**<br>~~es~~|**Maximum value**<br>~~es~~<br>~~ee~~|**Unit**<br>~~es~~<br>e~~e~~|
|---|---|---|---|
|Vdd|Supply voltage|-0.3 to 4.8<br>~~ee ~~|V<br> e~~e~~|
|Vdd_IO|I/O pins supply voltage|-0.3 to 4.8|V|
|Vin|Input voltage on any control pin<br>(CS, SCL/SPC, SDA/SDI/SDO, SDO/SA0)|-0.3 to Vdd_IO +0.3|V|
|APOW|Acceleration (any axis, powered, Vdd = 1.8 V)|3000_g_for 0.5 ms|_g_|
|||10000_g_for 0.2 ms|_g_|
|AUNP|Acceleration (any axis, unpowered)|3000_g_for 0.5 ms|_g_|
|||10000_g_for 0.2 ms|_g_|
|TOP|Operating temperature range|-40 to +85|°C|
|TSTG|Storage temperature range|-40 to +125|°C|
|ESD|Electrostatic discharge protection|2 (HBM)|kV|



_Note:_ 

_Supply voltage on any pin should never exceed 4.8 V._ 

_This device is sensitive to mechanical shock, improper handling can cause permanent damage to the part._ 

_This device is sensitive to electrostatic discharge (ESD), improper handling can cause permanent damage to the part._ 

**DS12825** - **Rev 3** 

**page 12/65** 

**LIS2DTW12 Terminology and functionality** 

## **3 Terminology and functionality** 

## **3.1 Terminology** 

## **3.1.1 Sensitivity** 

Sensitivity describes the gain of the sensor and can be determined by applying 1 _g_ acceleration to it. As the sensor can measure DC accelerations this can be done easily by pointing the axis of interest towards the center of the Earth, noting the output value, rotating the sensor by 180 degrees (pointing to the sky) and noting the output value again. By doing so, ±1 _g_ acceleration is applied to the sensor. Subtracting the larger output value from the smaller one, and dividing the result by 2, leads to the actual sensitivity of the sensor. This value changes very little over temperature and time. The sensitivity tolerance describes the range of sensitivities of a large population of sensors. 

## **3.1.2 Zero-g level offset** 

Zero- _g_ level offset describes the deviation of an actual output signal from the ideal output signal if no acceleration is present. A sensor in a steady state on a horizontal surface will measure 0 _g_ on the X-axis and 0 _g_ on the Y-axis whereas the Z-axis will measure 1 _g_ . The output is ideally in the middle of the dynamic range of the sensor (content of OUT registers 00h, data expressed as two’s complement number). A deviation from ideal value in this case is called Zero- _g_ level offset. Offset is to some extent a result of stress to the MEMS sensor and therefore the offset can slightly change after mounting the sensor onto a printed circuit board or exposing it to extensive mechanical stress. Offset changes little over temperature, see “Zero- _g_ level offset change vs. temperature”. 

**DS12825** - **Rev 3** 

**page 13/65** 

**LIS2DTW12 Functionality** 

## **3.2 Functionality** 

## **3.2.1 Operating modes** 

Two sets of operating modes have been designed to offer the customer a broad choice of noise/power consumption combinations: 

- Low-noise disabled (see Table 10. Operating modes - low-noise setting disabled) 

- Low-noise enabled (see Table 11. Operating modes - low-noise setting enabled) 

Writing the LOW_NOISE bit in CTRL6 (25h) selects the operating mode (low-noise). 

From each of these two sets, five operating modes have been designed: 

- 1 High-Performance Mode: focus on low noise 

- 4 Low-Power Modes: trade-off between noise and power consumption 

These operating modes are selected by writing the MODE[1:0] and LP_MODE[1:0] bits in CTRL1 (20h). 

**Table 10. Operating modes - low-noise setting disabled** 

|**Parameter**|**Parameter**|**High-Performance**<br>**Mode**|**Low-Power**<br>**Mode 4**|**Low-Power**<br>**Mode 3**|**Low-Power**<br>**Mode 2**|**Low-Power**<br>**Mode 1**|
|---|---|---|---|---|---|---|
|Resolution [bit]||14-bit|14-bit|14-bit|14-bit|12-bit|
|ODR [Hz]||12.5 - 1600|1.6 - 200|1.6 - 200|1.6 - 200|1.6 - 200|
|BW [Hz]||ODR/2 (N/A for<br>1600 Hz),<br>ODR/4, ODR/10,<br>ODR/20|180<br>ODR/4,<br>ODR/10,<br>ODR/20|360<br>ODR/4,<br>ODR/10,<br>ODR/20|720<br>ODR/4,<br>ODR/10,<br>ODR/20|3200<br>ODR/4,<br>ODR/10,<br>ODR/20|
|Noise density [µ_g_/√Hz]<br>@ FS = ±2_g_, ODR=200 Hz||110|160|210|300|550|
|Current consumption [µA]<br>@ Vdd=1.8 V|ODR=1.6 Hz|-|0.65|0.55|0.45|0.38|
||ODR=12.5 Hz|90|4|2.5|1.6|1|
||ODR=25 Hz|90|8.5|4.5|3|1.5|
||ODR=50 Hz|90|16|9|5.5|3|
||ODR=100 Hz|90|32|17.5|10.5|5|
||ODR=200 Hz|90|63|34.5|20.5|10|
||ODR=400, 800,<br>1600 Hz|90|-|-|-|-|



**DS12825** - **Rev 3** 

**page 14/65** 

**LIS2DTW12 Functionality** 

## **Table 11. Operating modes - low-noise setting enabled** 

|**Parameter**|**Parameter**|**High-Performance**<br>**Mode**|**Low-Power**<br>**Mode 4**|**Low-Power**<br>**Mode 3**|**Low-Power**<br>**Mode 2**|**Low-Power**<br>**Mode 1**|
|---|---|---|---|---|---|---|
|Resolution [bit]||14-bit|14-bit|14-bit|14-bit|12-bit|
|ODR [Hz]||12.5 - 1600|1.6 - 200|1.6 - 200|1.6 - 200|1.6 - 200|
|BW [Hz]||ODR/2 (N/A for<br>1600 Hz),<br>ODR/4, ODR/10,<br>ODR/20|180<br>ODR/4,<br>ODR/10,<br>ODR/20|360<br>ODR/4,<br>ODR/10,<br>ODR/20|720<br>ODR/4,<br>ODR/10,<br>ODR/20|3200<br>ODR/4,<br>ODR/10,<br>ODR/20|
|Noise density [µ_g_/√Hz]<br>@ FS = ±2_g_, ODR=200 Hz||90|130|180|240|450|
|Current consumption [µA]<br>@ Vdd=1.8 V|ODR=1.6 Hz|-|0.7|0.6|0.5|0.4|
||ODR=12.5 Hz|120|5|3|2|1.1|
||ODR=25 Hz|120|10|6|3.5|2|
||ODR=50 Hz|120|20|11|7|3.5|
||ODR=100 Hz|120|39|21.5|13|6|
||ODR=200 Hz|120|77|42|25|12|
||ODR=400, 800,<br>1600 Hz|120|-|-|-|-|



**DS12825** - **Rev 3** 

**page 15/65** 

**LIS2DTW12 Functionality** 

## **3.2.2 Single data conversion on-demand mode** 

The device features a single data conversion on-demand mode which is valid for both sets of operating modes (low-noise disabled or enabled) in the 4 low-power modes. This mode is enabled by writing the MODE[1:0] bits to '10' in CTRL1 (20h). Low power modes are selected by writing the LP_MODE[1:0] bits in CTRL1 (20h). 

The trigger for output data generation can be managed through the I²C/SPI or by applying a clock signal on the INT2 pin acting here as an input by writing the SLP_MODE_ SEL bit in CTRL3 (22h): 

- When SLP_MODE_SEL = '0', output data generation is triggered by the clock signal on the INT2 pin (see Figure 5. Single data conversion on-demand functionality). 

- When SLP_MODE_SEL = '1', output data generation starts when the SLP_MODE_1 bit is set to '1' logic through the I²C/SPI. When XL data are available in the registers, this bit is automatically set to '0' and the device is ready for another triggered session. 

Output data are generated according to the selected low-power mode. 

When output data is saved in an output register or FIFO, the device goes to power-down mode and waits for a new trigger. 

All ODRs in the range from 0 to up to 200 Hz are supported due to the INT2 clock input. 

A DRDY signal or FIFO flags are available on the INT1 pin. 

Power consumption is the same as that of standard low-power modes for the same ODR. 

## **Figure 5. Single data conversion on-demand functionality** 

Trigger Signal (INT2 pin) 

**==> picture [265 x 26] intentionally omitted <==**

**----- Start of picture text -----**<br>
T_on PD T_on<br>**----- End of picture text -----**<br>


DRDY (INT1 pin) 

At the end of turn-on time T_on, the DRDY interrupt is activated, output data are available to be read and the device goes into power-down. T_on values depend on the low-power mode as follows: T_on (typ.) = 

- 1.20 ms for Low-Power Mode 1 

- 1.70 ms for Low-Power Mode 2 

- 2.30 ms for Low-Power Mode 3 

- 3.55 ms for Low-Power Mode 4 

## **3.2.3** 

## **Self-test** 

The self-test allows checking the sensor functionality without moving it. The self-test function is off when the selftest bits (ST) are programmed to ‘00’. When the self-test bits are changed, an actuation force is applied to the sensor, simulating a definite input acceleration. In this case the sensor outputs will exhibit a change in their DC levels which are related to the selected full scale through the device sensitivity. When the self-test is activated, the device output level is given by the algebraic sum of the signals produced by the acceleration acting on the sensor and by the electrostatic test-force. If the output signals change within the amplitude specified in Table 3. Mechanical characteristics, then the sensor is working properly and the parameters of the interface chip are within the defined specifications. 

**DS12825** - **Rev 3** 

**page 16/65** 

**LIS2DTW12 Functionality** 

## **3.2.4 Activity/Inactivity, Android stationary/motion-detection functions** 

The activity/inactivity function recognizes the device’s sleep state and allows reducing system power consumption. 

When the activity/inactivity function is activated by setting the INTERRUPTS_ENABLE bit in CTRL7 (3Fh) and the SLEEP_ON bit in WAKE_UP_THS (34h), the LIS2DTW12 automatically goes to 12.5 Hz ODR in the low-power mode previously selected by the LP_MODE[1:0] bits in CTRL1 (20h) if the sleep state condition is detected and wakes up as soon as the interrupt event has been detected, increasing the output data rate and bandwidth. With this feature the system may be efficiently switched from low-power mode to full performance depending on user-selectable positioning and acceleration events, thus ensuring power saving and flexibility. The Android stationary/motion detection function only recognizes the device’s sleep state. 

When the Android stationary/motion-detection function is activated by setting the STATIONARY bit in WAKE_UP_DUR (35h), the LIS2DTW12 detects acceleration below a fixed threshold but does not change either ODR or operating mode (High-Performance mode or Low-Power mode) after sleep state detection. 

The Activity/Inactivity recognition function can use the high-pass filter or the offset outputs, this choice can be made through the USR_OFF_ON_OUT bit in CTRL7 (3Fh). 

If the device is in sleep (inactivity/stationary) mode, when at least one of the axes exceeds the threshold in WAKE_UP_THS (34h), the device goes into a sleep-to-wake state (as wake-up). 

For the activity/inactivity function, the device, in a wake-up state, will return to the operating mode (HP or LP) and ODR before sleep state detection. 

Activity/Inactivity, Android stationary/motion-detection threshold and duration can be configured in the following control registers: 

WAKE_UP_THS (34h) 

WAKE_UP_DUR (35h) 

## **3.2.5** 

## **High tap/double-tap user configurability** 

The device embeds the possibility to select the following parameters: 

- single axis or multiple axes in TAP_THS_Z (32h) 

- axis priority in TAP_THS_Y (31h) 

- threshold value of each axis in TAP_THS_X (30h), TAP_THS_Y (31h), and TAP_THS_Z (32h) 

- max time threshold between 2 consecutive taps for double-tap recognition, min time threshold between 2 consecutive taps to detect a new tap event in INT_DUR (33h) 

## **3.2.6 Offset management** 

The user can manage offset in the output or for wakeup detection using dedicated embedded hardware (see Section  5.1  Block diagram of filters). 

**DS12825** - **Rev 3** 

**page 17/65** 

**LIS2DTW12 Sensing element** 

## **3.3 Sensing element** 

A proprietary process is used to create a surface micromachined accelerometer. The technology allows processing suspended silicon structures which are attached to the substrate in a few points called anchors and are free to move in the direction of the sensed acceleration. In order to be compatible with the traditional packaging techniques, a cap is placed on top of the sensing element to avoid blocking the moving parts during the molding phase of the plastic encapsulation. When an acceleration is applied to the sensor the proof mass displaces from its nominal position, causing an imbalance in the capacitive half-bridge. This imbalance is measured using charge integration in response to a voltage pulse applied to the capacitor. 

At steady-state the nominal value of the capacitors are a few pF and when an acceleration is applied, the maximum variation of the capacitive load is in the fF range. 

## **3.4 IC interface** 

The complete measurement chain is composed of a low-noise capacitive amplifier which converts the capacitive unbalancing of the MEMS sensor into an analog voltage using an analog-to-digital converter. 

The acceleration data may be accessed through an I²C/SPI interface thus making the device particularly suitable for direct interfacing with a microcontroller. 

The LIS2DTW12 features a data-ready signal which indicates when a new set of measured acceleration data is available, thus simplifying data synchronization in the digital system that uses the device. 

## **3.5 Factory calibration** 

The IC interface is factory-calibrated for sensitivity (So) and Zero-g level offset. 

The trim values are stored inside the device in nonvolatile memory. Any time the device is turned on, the trimming parameters are downloaded into the registers to be used during active operation. This allows using the device without further calibration. If an accidental write occurs in the registers where trimming parameters are stored, the BOOT bit in CTRL2 (21h) can help to retrieve the correct trimming parameters from nonvolatile memory without the need to switch on/off the device. This bit is automatically reset at the end of the download operation. Setting this bit has no impact on the control registers. 

## **3.6 Temperature sensor** 

The temperature is available in OUT_T_L (0Dh), OUT_T_H (0Eh) stored as two's complement data, left-justified in 12-bit mode. 

Refer to Table 5. Temperature sensor characteristics for the conversion factor. 

**DS12825** - **Rev 3** 

**page 18/65** 

**LIS2DTW12 Application hints** 

**4** 

## **Application hints** 

**Figure 6. LIS2DTW12 electrical connections (top view)** 

**==> picture [367 x 208] intentionally omitted <==**

**----- Start of picture text -----**<br>
Vdd_IO<br>100nF<br>HOST<br>GND I [2] C / SPI (3/4-w)<br>Vdd<br>10µF LIS2DTW12<br>SCL/SPC Vdd_IO<br>1 12 11 10<br>CS VDD<br>2 9 100nF<br>GND I [2] C configuration<br>SDO/SA0 GND<br>3 8 Vdd_IO<br>SDA/SDI/SDO 4 5 6 7 RES<br>Rpu Rpu<br>SCL<br>SDA<br>Pull-up to be added<br>Rpu=10kOhm<br>INT1 INT2<br>NC GND<br>**----- End of picture text -----**<br>


The device core is supplied through the Vdd line while the I/O pads are supplied through the Vdd_IO line. Power supply decoupling capacitors (100 nF ceramic, 10 µF aluminum) should be placed as near as possible to pin 9 of the device (common design practice). 

All the voltage and ground supplies must be present at the same time to have proper behavior of the IC (refer to Figure 6. LIS2DTW12 electrical connections (top view)). It is possible to remove Vdd while maintaining Vdd_IO without blocking the communication bus, in this condition the measurement chain is powered off. 

The functionality of the device and the measured acceleration data are selectable and accessible through the I²C or SPI interfaces. When using the I²C, CS must be tied high (i.e. connected to Vdd_IO). 

The functions, the threshold and the timing of the two interrupt pins (INT1 and INT2) can be completely programmed by the user through the I²C/SPI interface. 

**DS12825** - **Rev 3** 

**page 19/65** 

**LIS2DTW12 Application hints** 

## **Table 12. Internal pin status** 

|**Pin #**|**Name**|**Function**|**Pin status**|
|---|---|---|---|
|1|SCL<br>SPC|I²C serial clock (SCL)<br>SPI serial port clock (SPC)|Default: open drain|
|2|CS|SPI enable<br>I²C/SPI mode selection<br>1: SPI idle mode / I²C communication enabled<br>0: SPI communication mode / I²C disabled|Default: input with internal pull-up(1)|
|3|SDO<br>SA0|Serial data output (SDO)<br>I²C less significant bit of the device address (SA0)|Default: input with internal pull-up|
|4|SDA<br>SDI<br>SDO|I²C serial data (SDA)<br>SPI serial data input (SDI)<br>3-wire interface serial data output (SDO)|Default: (SDA) input open drain|
|5|NC|Internally not connected. Can be tied to VDD, VDDIO, or GND.||
|6|GND|0 V supply||
|7|RES|Connect to GND||
|8|GND|0 V supply||
|9|VDD|Power supply||
|10|VDD_IO|Power supply for I/O pins||
|11|INT2|Interrupt pin 2. Clock input when selected in single data conversion on demand.|Default: push-pull output forced to Gnd|
|12|INT1|Interrupt pin 1|Default: push-pull output forced to Gnd|



_1. In order to disable the internal pull-up on the CS pin, write '1' to the CS_PU_DISC bit in CTRL2 (21h)._ 

**DS12825** - **Rev 3** 

**page 20/65** 

**LIS2DTW12 Digital main blocks** 

**5 Digital main blocks** 

## **5.1 Block diagram of filters** 

**Figure 7. Accelerometer chain** 

Referring to Figure 7. Accelerometer chain, the first block is the Low-Pass Filter 1 (LPF1) whose behavior is a function of the actual ODR and mode selected in CTRL1 (20h). The signal is then downsampled and can be either directly sent to the output registers or to the Low-Pass Filter 2 (LPF2) or High-Pass-Filter (HP) using the BW_FILT[1:0] bits and FDS bit in CTRL6 (25h). 

In the low-pass path, it is possible to apply a user offset determined by the X_OFS_USR (3Ch), Y_OFS_USR (3Dh), Z_OFS_USR (3Eh) register values and the USR_OFF_W bit in CTRL7 (3Fh) and send the result to the output using the USR_OFF_ON_OUT bit in CTRL7 (3Fh). 

In the high-pass path, it is possible to use the high-pass filter reference mode (HP) using the HP_REF_MODE bit in CTRL7 (3Fh). 

**DS12825** - **Rev 3** 

**page 21/65** 

**LIS2DTW12 Data stabilization time vs. ODR/device setting** 

## **5.2 Data stabilization time vs. ODR/device setting** 

Some data samples need to be discarded when changing the ODR in HP mode with ODR/2 bandwidth selection. The table below provides the number of samples to be discarded in order to obtain valid usable data. 

**Table 13. Number of samples to be discarded** 

|**MODE[1:0] in**<br>**CTRL1 (20h)**|**ODR [Hz]**|**BW_FILT[1:0] in**<br>**CTRL6 (25h)**|**Samples to be discarded**|
|---|---|---|---|
|00|-|00|0|
|01|12.5||0|
||25||0|
||50||0|
||100||1|
||200||1|
||400||1|
||800||1|
||1600||2|



**DS12825** - **Rev 3** 

**page 22/65** 

**LIS2DTW12 FIFO** 

## **5.3 FIFO** 

The LIS2DTW12 embeds 32 slots of 14-bit data FIFO for each of the three output channels, X, Y and Z of the acceleration data. This allows consistent power saving for the system, since the host processor does not need to continuously poll data from the sensor, but it can wake up only when needed and burst the significant data out from the FIFO. 

The internal FIFO allows collecting 32 samples (14-bit size data) for each axis. 

When the FIFO mode is other than Bypass, reading the output registers (28h to 2Dh) returns the oldest FIFO sample set. In order to minimize communication between the master and slave, the address read may be automatically incremented by the device by setting the IF_ADD_INC bit of CTRL2 (21h) to '1'; the device rolls back to 0x28 when register 0x2D is reached. 

This buffer can work according to the following 5 different modes: 

- Bypass mode 

- FIFO mode 

- Continuous-to-FIFO 

- Bypass-to-Continuous 

- Continuous 

Each mode is selected by the FMode[2:0] bits in the FIFO_CTRL (2Eh) register. 

Programmable FIFO threshold is selected in FIFO_CTRL (2Eh). Status and FIFO overrun events are available in the  FIFO_SAMPLES (2Fh) register and can be used to generate dedicated interrupts on the INT1 and INT2 pins using the CTRL4_INT1_PAD_CTRL (23h) and CTRL5_INT2_PAD_CTRL (24h) registers. 

FIFO_SAMPLES (2Fh) (FIFO_FTH) goes to '1' when the number of unread samples FIFO_SAMPLES (2Fh) (Diff[5:0]) is greater than or equal to FTH[4:0] in FIFO_CTRL (2Eh). 

If FTH[4:0] is equal to '0', FIFO_SAMPLES (2Fh) (FIFO_FTH) goes to '0'. 

FIFO_SAMPLES (2Fh) (FIFO_OVR) is equal to '1' if a FIFO slot is overwritten. 

FIFO_SAMPLES (2Fh) (Diff[5:0]) contains stored data levels of unread samples. When Diff[5:0] is equal to ‘000000’, FIFO is empty. When Diff[5:0] is equal to ‘100000’, FIFO is full and the unread samples are 32. 

To guarantee the correct acquisition of data during the switching into and out of FIFO, the first sample acquired must be discarded. 

When the FIFO threshold status flag is '0'-logic, FIFO filling is lower than the threshold level and when '1'-logic, FIFO filling is equal to or higher than the threshold level. 

**DS12825** - **Rev 3** 

**page 23/65** 

**LIS2DTW12 FIFO** 

**5.3.1 Bypass mode** In Bypass mode (FIFO_CTRL (2Eh) (FMode [2:0])= 000), the FIFO is not operational, no data is collected in FIFOFIFO_CTRL (2Eh) (FMode [2:0])= 000), the FIFO is not operational, no data is collected in FIFO (FMode [2:0])= 000), the FIFO is not operational, no data is collected in FIFO memory, and it remains empty with the only actual sample available in the output registers. Bypass mode is also used to reset the FIFO when in FIFO mode. For each channel only the first address is used. When new data is available, the old data is overwritten. **5.3.2 FIFO mode** In FIFO mode (FIFO_CTRL (2Eh)(FMode [2:0])= 001) data from the X, Y and Z channels are stored in the FIFO until it is full, when 32 unread samples are stored in memory, data collecting is stopped. To reset the FIFO content, Bypass mode should be written in the FIFO_CTRL (2Eh) register, setting the FMODEFIFO_CTRL (2Eh) register, setting the FMODE register, setting the FMODE [2:0] bits to '000'. After this reset command, it is possible to restart FIFO mode, writing the value '001' in FIFO_CTRL (2Eh)(FMODE [2:0]).(FMODE [2:0]). The FIFO buffer can memorize 32 slots of X, Y and Z data. **5.3.3 Continuous mode** Continuous mode (FIFO_CTRL (2Eh) (FMode[2:0] = 110) provides a continuous FIFO update: when 32 unread samples are stored in memory, as new data arrives the oldest data is discarded and overwritten by the newer. A FIFO threshold flag FIFO_SAMPLES (2Fh) (FIFO_FTH) is asserted when the number of unread samples in FIFO is greater than or equal to (FIFO_CTRL (2Eh)FTH[4:0]). 

In Bypass mode (FIFO_CTRL (2Eh) (FMode [2:0])= 000), the FIFO is not operational, no data is collected in FIFOFIFO_CTRL (2Eh) (FMode [2:0])= 000), the FIFO is not operational, no data is collected in FIFO (FMode [2:0])= 000), the FIFO is not operational, no data is collected in FIFO memory, and it remains empty with the only actual sample available in the output registers. Bypass mode is also used to reset the FIFO when in FIFO mode. 

To reset the FIFO content, Bypass mode should be written in the FIFO_CTRL (2Eh) register, setting the FMODEFIFO_CTRL (2Eh) register, setting the FMODE register, setting the FMODE [2:0] bits to '000'. After this reset command, it is possible to restart FIFO mode, writing the value '001' in FIFO_CTRL (2Eh)(FMODE [2:0]).(FMODE [2:0]). 

It is possible to route FIFO_SAMPLES (2Fh)(FTH) to the INT1 pin by writing the INT1_FTH bit to '1' in register CTRL4_INT1_PAD_CTRL (23h) or to the INT2 pin by writing the INT2_FTH bit to '1' in register CTRL5_INT2_PAD_CTRL (24h). 

If an overrun occurs, the oldest sample in FIFO is overwritten and the FIFO_OVR flag in FIFO_SAMPLES (2Fh) is asserted. 

In order to empty the FIFO before it is full, it is also possible to pull from FIFO the number of unread samples available in FIFO_SAMPLES (2Fh) (Diff[5:0]). 

**DS12825** - **Rev 3** 

**page 24/65** 

**LIS2DTW12 FIFO** 

## **5.3.4** 

## **Continuous-to-FIFO mode** 

In Continuous-to-FIFO mode FIFO_CTRL (2Eh)(FMode[2:0] = 011), FIFO operates in Continuous mode and FIFO mode starts upon an internal trigger event. When the FIFO is full, data collecting is stopped. The trigger could be a single or double tap, wake-up, free-fall, 6D interrupt or any combination of these events, but every interrupt has to be routed on the corresponding pad to be used as a trigger. 

**Figure 8. Continuous-to-FIFO mode** 

**==> picture [335 x 165] intentionally omitted <==**

**----- Start of picture text -----**<br>
— xi,yi e ,zi /L_]_ x0 y0 z0 xi,yi,zi x0 y0 z0<br>x1 y1 z1<br>[L | —e l _yT x1 y1 [| z1<br>[ff rT...<br>x2 y2 z2<br>x2 y2 z2<br>x30 y30 z30<br>x31 y31 z31<br>x31 y31 z31<br>Continuous Mode FIFO Mode<br>**----- End of picture text -----**<br>


**Trigger event** 

**Figure 9. Trigger event to FIFO for Continuous-to-FIFO mode** 

**DS12825** - **Rev 3** 

**page 25/65** 

**LIS2DTW12 FIFO** 

## **5.3.5 Bypass-to-Continuous mode** 

In Bypass-to-Continuous mode (FIFO_CTRL (2Eh)(FMode[2:0] = '100'), data measurement storage inside FIFO starts in Continuous mode upon an internal trigger event, then the sample that follows the trigger is available in FIFO. The trigger could be a single or double tap, wake-up, free-fall, 6D interrupt or any combination of these events, but every interrupt has to be routed on the corresponding pad to be used as a trigger. 

**Figure 10. Bypass-to-Continuous mode** 

**==> picture [346 x 170] intentionally omitted <==**

**----- Start of picture text -----**<br>
— xi,y + i,zi (—T_T_ x0 y0 z0 — xi,yi,z e i  ft x0 y0 z0<br>x1 y1 z1<br>x1 y1 z1<br>x2 y2 z2<br>empty x2 y2 z2 ae<br>x30 y30 z30<br>x31 y31 z31<br>x31 y31 z31 =<br>Bypass Mode Continuous Mode<br>ee Ot e e<br>Trigger event<br>**----- End of picture text -----**<br>


**Figure 11. Trigger event to FIFO for Bypass-to-Continuous mode** 

**DS12825** - **Rev 3** 

**page 26/65** 

**LIS2DTW12 Digital interfaces** 

## **6** 

## **Digital interfaces** 

The registers embedded inside the LIS2DTW12 may be accessed through both the I²C and SPI serial interfaces. The latter may be SW configured to operate either in 3-wire or 4-wire interface mode. 

The serial interfaces are mapped to the same pins. To select/exploit the I²C interface, the CS line must be tied high (i.e. connected to Vdd_IO). 

**Table 14. Serial interface pin description** 

|**Pin name**|**Pin description**|
|---|---|
|CS|SPI enable<br>I²C/SPI mode selection<br>(1: SPI idle mode / I²C communication enabled;<br>0: SPI communication mode / I²C disabled)|
|SCL<br>SPC|I²C serial clock (SCL)<br>SPI serial port clock (SPC)|
|SDA<br>SDI<br>SDO|I²C serial data (SDA)<br>SPI serial data input (SDI)<br>3-wire interface serial data output (SDO)|
|SA0<br>SDO|I²C address selection (SA0)<br>SPI serial data output (SDO)|



## **6.1 I²C serial interface** 

The LIS2DTW12 I²C is a bus slave. The I²C is employed to write data into registers whose content can also be read back. 

The relevant I²C terminology is given in the table below. 

**Table 15. I²C terminology** 

|**Term**|**Description**|
|---|---|
|Transmitter|The device which sends data to the bus|
|Receiver|The device which receives data from the bus|
|Master|The device which initiates a transfer, generates clock signals and terminates a transfer|
|Slave|The device addressed by the master|



There are two signals associated with the I²C bus: the serial clock line (SCL) and the Serial DAta line (SDA). The latter is a bidirectional line used for sending and receiving the data to/from the interface. Both the lines must be connected to Vdd_IO through an external pull-up resistor. When the bus is free, both the lines are high. The I²C interface is compliant with fast mode (400 kHz) I²C standards as well as with normal mode. In order to disable the I²C block, CTRL2 (21h) (I2C_DISABLE) = 1 must be set. 

**DS12825** - **Rev 3** 

**page 27/65** 

**LIS2DTW12 I²C serial interface** 

## **6.1.1 I²C operation** 

The transaction on the bus is started through a START (ST) signal. A START condition is defined as a high-to-low transition on the data line while the SCL line is held high. After this has been transmitted by the master, the bus is considered busy. The next byte of data transmitted after the start condition contains the address of the slave in the first 7 bits and the eighth bit tells whether the master is receiving data from the slave or transmitting data to the slave. When an address is sent, each device in the system compares the first seven bits after a start condition with its address. If they match, the device considers itself addressed by the master. 

The Slave Address (SAD) associated to the LIS2DTW12 is 001100xb where the x bit is modified by the SA0/SDO pin in order to modify the device address. If the SA0/SDO pin is connected to the supply voltage, the address is 0011001b, otherwise if the SA0/SDO pin is connected to ground, the address is 0011000b. This solution permits to connect and address two different accelerometers to the same I²C lines. 

Data transfer with acknowledge is mandatory. The transmitter must release the SDA line during the acknowledge pulse. The receiver must then pull the data line low so that it remains stable low during the high period of the acknowledge clock pulse. A receiver which has been addressed is obliged to generate an acknowledge after each byte of data received. 

The I²C embedded inside the LIS2DTW12 behaves like a slave device and the following protocol must be adhered to. After the start condition (ST) a slave address is sent. Once a slave acknowledge (SAK) has been returned, an 8-bit sub-address (SUB) is transmitted: the 7 LSb represents the actual register address while the CTRL2 (21h) (IF_ADD_INC) bit defines the address increment. 

The slave address is completed with a Read/Write bit. If the bit is ‘1’ (Read), a repeated START (SR) condition must be issued after the two sub-address bytes. If the bit is ‘0’ (Write) the master will transmit to the slave with direction unchanged. Table 16 explains how the SAD+Read/Write bit pattern is composed, listing all the possible configurations. 

**Table 16. SAD+Read/Write patterns** 

|**Command**|**SAD[6:1]**|**SAD[0] = SA0**|**R/W**|**SAD+R/W**|
|---|---|---|---|---|
|Read|001100|0|1|00110001 (31h)|
|Write|001100|0|0|00110000 (30h)|
|Read|001100|1|1|00110011 (33h)|
|Write|001100|1|0|00110010 (32h)|



## **Table 17. Transfer when master is writing one byte to slave** 

|Master|ST|SAD + W||SUB||DATA||SP|
|---|---|---|---|---|---|---|---|---|
|Slave|||SAK||SAK||SAK||



**Table 18. Transfer when master is writing multiple bytes to slave** 

|Master|ST|SAD + W||SUB||DATA||DATA||SP|
|---|---|---|---|---|---|---|---|---|---|---|
|Slave|||SAK||SAK||SAK||SAK||



**Table 19. Transfer when master is receiving (reading) one byte of data from slave** 

|Master|ST|SAD + W||SUB||SR|SAD + R|||NMAK|SP|
|---|---|---|---|---|---|---|---|---|---|---|---|
|Slave|||SAK||SAK|||SAK|DATA|||



**Table 20. Transfer when master is receiving (reading) multiple bytes of data from slave** 

|Master|ST|SAD<br>+W||SUB||SR|SAD+R|||MAK||MAK||NMAK|SP|
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|



**DS12825** - **Rev 3** 

**page 28/65** 

**LIS2DTW12 SPI bus interface** 

Slave SAK SAK SAK DATA DATA DATA 

Data are transmitted in byte format (DATA). Each data transfer contains 8 bits. The number of bytes transferred per transfer is unlimited. Data is transferred with the Most Significant bit (MSb) first. If a receiver can’t receive another complete byte of data until it has performed some other function, it can hold the clock line, SCL low to force the transmitter into a wait state. Data transfer only continues when the receiver is ready for another byte and releases the data line. If a slave receiver doesn’t acknowledge the slave address (i.e. it is not able to receive because it is performing some real-time function) the data line must be left high by the slave. The master can then abort the transfer. A low-to-high transition on the SDA line while the SCL line is high is defined as a STOP condition. Each data transfer must be terminated by the generation of a STOP (SP) condition. 

In the presented communication format MAK is Master acknowledge and NMAK is No Master Acknowledge. 

## **6.2 SPI bus interface** 

The LIS2DTW12 SPI is a bus slave. The SPI allows writing to and reading from the registers of the device. The serial interface interacts with the application using 4 wires: **CS** , **SPC** , **SDI** and **SDO** . 

**Figure 12. Read and write protocol** 

**==> picture [332 x 104] intentionally omitted <==**

**----- Start of picture text -----**<br>
CS<br>SPC<br>SDI<br>RW DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0<br>AD6 AD5 AD4 AD3 AD2 AD1 AD0<br>SDO<br>DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0<br>**----- End of picture text -----**<br>


**CS** is the serial port enable and it is controlled by the SPI master. It goes low at the start of the transmission and goes back high at the end. **SPC** is the serial port clock and it is controlled by the SPI master. It is stopped high when **CS** is high (no transmission). **SDI** and **SDO** are respectively the serial port data input and output. Those lines are driven at the falling edge of **SPC** and should be captured at the rising edge of **SPC** . 

Both the read register and write register commands are completed in 16 clock pulses or in multiples of 8 in case of multiple read/write bytes. Bit duration is the time between two falling edges of **SPC** . The first bit (bit 0) starts at the first falling edge of **SPC** after the falling edge of **CS** while the last bit (bit 15, bit 23, ...) starts at the last falling edge of SPC just before the rising edge of **CS** . 

**bit 0** : RW bit. When 0, the data DI(7:0) is written into the device. When 1, the data DO(7:0) from the device is read. In latter case, the chip will drive **SDO** at the start of bit 8. 

**bit 1-7** : address AD(6:0). This is the address field of the indexed register. 

**bit 8-15** : data DI(7:0) (write mode). This is the data that is written into the device (MSb first). 

**bit 8-15** : data DO(7:0) (read mode). This is the data that is read from the device (MSb first). 

In multiple read/write commands additional blocks of 8 clock periods will be added. When the CTRL2 (21h) (IF_ADD_INC) bit is ‘0’, the address used to read/write data remains the same for every block. When the CTRL2 (21h) (IF_ADD_INC) bit is ‘1’, the address used to read/write data is increased at every block. 

The function and the behavior of **SDI** and **SDO** remain unchanged. 

**DS12825** - **Rev 3** 

**page 29/65** 

**LIS2DTW12 SPI bus interface** 

## **6.2.1 SPI read** 

## **Figure 13. SPI read protocol** 

**==> picture [362 x 114] intentionally omitted <==**

**----- Start of picture text -----**<br>
CS<br>SPC<br>SDI<br>RW<br>AD6 AD5 AD4 AD3 AD2 AD1 AD0<br>SDO<br>DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0<br>**----- End of picture text -----**<br>


The SPI read command is performed with 16 clock pulses. A multiple byte read command is performed by adding blocks of 8 clock pulses to the previous one. 

**bit 0** : READ bit. The value is 1. 

**bit 1-7** : address AD(6:0). This is the address field of the indexed register. 

**bit 8-15** : data DO(7:0) (read mode). This is the data that will be read from the device (MSb first). 

**bit 16-...** : data DO(...-8). Additional data in multiple byte reads. 

## **Figure 14. Multiple byte SPI read protocol (2-byte example)** 

**==> picture [357 x 97] intentionally omitted <==**

**----- Start of picture text -----**<br>
CS<br>SPC<br>SDI<br>RW<br>AD6 AD5 AD4AD3 AD2 AD1 AD0<br>SDO<br>DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 DO15 DO14 DO13 DO12 DO11DO10 DO9 DO8<br>**----- End of picture text -----**<br>


**DS12825** - **Rev 3** 

**page 30/65** 

**LIS2DTW12 SPI bus interface** 

## **6.2.2 SPI write** 

## **Figure 15. SPI write protocol** 

**==> picture [370 x 82] intentionally omitted <==**

**----- Start of picture text -----**<br>
CS<br>SPC<br>SDI<br>RW DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0<br>AD6 AD5 AD4 AD3 AD2 AD1 AD0<br>**----- End of picture text -----**<br>


The SPI write command is performed with 16 clock pulses. A multiple byte write command is performed by adding blocks of 8 clock pulses to the previous one. 

**bit 0** : WRITE bit. The value is 0. 

**bit 1 -7** : address AD(6:0). This is the address field of the indexed register. 

**bit 8-15** : data DI(7:0) (write mode). This is the data that is written inside the device (MSb first). 

**bit 16-...** : data DI(...-8). Additional data in multiple byte writes. 

**Figure 16. Multiple byte SPI write protocol (2-byte example)** 

**==> picture [380 x 83] intentionally omitted <==**

**----- Start of picture text -----**<br>
CS<br>SPC<br>SDI<br>DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 DI15 DI14 DI13 DI12 DI11 DI10 DI9 DI8<br>RW<br>AD6 AD5 AD4 AD3 AD2 AD1 AD0<br>**----- End of picture text -----**<br>


**DS12825** - **Rev 3** 

**page 31/65** 

**LIS2DTW12 SPI bus interface** 

## **6.2.3 SPI read in 3-wire mode** 

3-wire mode is entered by setting the CTRL2 (21h) (SIM) bit equal to ‘1’ (SPI serial interface mode selection). 

## **Figure 17. SPI read protocol in 3-wire mode** 

**==> picture [361 x 80] intentionally omitted <==**

**----- Start of picture text -----**<br>
CS<br>SPC<br>SDI/O<br>RW DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0<br>AD6 AD5 AD4 AD3 AD2 AD1 AD0<br>**----- End of picture text -----**<br>


The SPI read command is performed with 16 clock pulses: 

**bit 0** : READ bit. The value is 1. 

**bit 1-7** : address AD(6:0). This is the address field of the indexed register. **bit 8-15** : data DO(7:0) (read mode). This is the data that is read from the device (MSb first). A multiple read command is also available in 3-wire mode. 

**DS12825** - **Rev 3** 

**page 32/65** 

**LIS2DTW12 Register mapping** 

**7** 

## **Register mapping** 

The table given below provides a list of the 8-bit registers embedded in the device and the corresponding addresses. 

**Table 21. Register map** 

|**N**|**T(1)**|**Register address**|**Register address**|**Dflt**|**Ct**|
|---|---|---|---|---|---|
|**ame**|**ype**|**Hex**|**Binary**|**eau**|**ommen**|
|OUT_T_L|R|0D|00001101|00000000|Temp sensor output|
|OUT_T_H|R|0E|00001110|00000000||
|WHO_AM_I|R|0F|00001111|01000100|Who am I ID|
|RESERVED|-|10-1F||-|RESERVED|
|CTRL1|R/W|20|00100000|00000000|Control registers|
|CTRL2|R/W|21|00100001|00000100||
|CTRL3|R/W|22|00100010|00000000||
|CTRL4_INT1_PAD_CTRL|R/W|23|00100011|00000000||
|CTRL5_INT2_PAD_CTRL|R/W|24|00100100|00000000||
|CTRL6|R/W|25|00100101|00000000||
|RESERVED|-|26||-|RESERVED|
|STATUS|R|27|00100111|00000000|Status data register|
|OUT_X_L|R|28|00101000|00000000|Output registers|
|OUT_X_H|R|29|00101001|00000000||
|OUT_Y_L|R|2A|00101010|00000000||
|OUT_Y_H|R|2B|00101011|00000000||
|OUT_Z_L|R|2C|00101100|00000000||
|OUT_Z_H|R|2D|00101101|00000000||
|FIFO_CTRL|R/W|2E|00101110|00000000|FIFO control register|
|FIFO_SAMPLES|R|2F|00101111|00000000|Unread samples stored in FIFO|
|TAP_THS_X|R/W|30|00110000|00000000|Tap thresholds|
|TAP_THS_Y|R/W|31|00110001|00000000||
|TAP_THS_Z|R/W|32|00110010|00000000||
|INT_DUR|R/W|33|00110011|00000000|Interrupt duration|
|WAKE_UP_THS|R/W|34|00110100|00000000|Tap/double-tap selection,<br>inactivity enable,<br>wakeup threshold|
|WAKE_UP_DUR|R/W|35|00110101|00000000|Wakeup duration|
|FREE_FALL|R/W|36|00110110|00000000|Free-fall configuration|
|STATUS_DUP|R|37|00110111|00000000|Status register|
|WAKE_UP_SRC|R|38|00111000|00000000|Wakeup source|
|TAP_SRC|R|39|00111001|00000000|Tap source|
|SIXD_SRC|R|3A|00111010|00000000|6D source|



**DS12825** - **Rev 3** 

**page 33/65** 

**LIS2DTW12 Register mapping** 

|**N**|**T(1)**|**Register address**|**Register address**|**Dflt**|**Ct**|
|---|---|---|---|---|---|
|**ame**|**ype**|**Hex**|**Binary**|**eau**|**ommen**|
|ALL_INT_SRC|R|3B|00111011|00000000||
|X_OFS_USR|R/W|3C|00111100|00000000||
|Y_OFS_USR|R/W|3D|00111110|00000000||
|Z_OFS_USR|R/W|3E|00000100|00000000||
|CTRL7|R/W|3F|00000100|00000000||



_1. R = read-only register, R/W = readable/writable register_ 

Registers marked as Reserved must not be changed. Writing to those registers may cause permanent damage to the device. 

The content of the registers that are loaded at boot should not be changed. They contain the factory calibration values. Their content is automatically restored when the device is powered up. 

**DS12825** - **Rev 3** 

**page 34/65** 

**LIS2DTW12 Register description** 

## **8 Register description** 

## **8.1 OUT_T_L (0Dh)** 

Temperature output register in 12-bit resolution (r). 

## **Table 22. OUT_T_L register** 

TEMP3 TEMP2 TEMP1 TEMP0 0 0 0 0 

## **Table 23. OUT_T_L register description** 

The 8 least significant bits of the temperature sensor output. 0 LSB = 25 °C. Sensitivity = 16 LSB/°C. TEMP[3:0] Together with OUT_T_H (0Eh), it forms the output value expressed as a 16-bit word in 2's complement. 

## **8.2 OUT_T_H (0Eh)** 

Temperature output register in 12-bit resolution (r). 

## **Table 24. OUT_T_H register** 

TEMP11 TEMP10 TEMP9 TEMP8 TEMP7 TEMP6 TEMP5 TEMP4 

## **Table 25. OUT_T_H register description** 

The 8 most significant bits of the temperature sensor output. 0 LSB = 25 °C. Sensitivity = 16 LSB/°C. TEMP[11:4] Together with OUT_T_L (0Dh), it forms the output value expressed as a 16-bit word in 2's complement 

## **8.3 WHO_AM_I (0Fh)** 

Who_AM_I register (r). This register is a read-only register. Its value is fixed at 44h. 

## **Table 26. WHO_AM_I register default values** 

0 1 0 0 0 1 0 0 

**DS12825** - **Rev 3** 

**page 35/65** 

**LIS2DTW12 CTRL1 (20h)** 

## **8.4 CTRL1 (20h)** 

Control register 1 (r/w) 

## **Table 27. Control register 1** 

ODR3 ODR2 ODR1 ODR0 MODE1 MODE0 LP_MODE1 LP_MODE0 

## **Table 28. Control register 1 description** 

|ODR[3:0]|Output data rate and mode selection (seeTable 29. Data rate configuration)|
|---|---|
|MODE[1:0]|Mode selection (seeTable 30. Mode selection)|
|LP_MODE[1:0]|Low-power mode selection (seeTable 31. Low-power mode selection)|



ODR[3:0] is used to set the power mode and ODR selection. The following table lists the bit settings for powerdown mode and each available frequency. 

**Table 29. Data rate configuration** 

|**ODR[3:0]**|**Power mode / data rate configuration**|
|---|---|
|0000|Power-down|
|0001|High-Performance / Low-Power mode 12.5/1.6 Hz|
|0010|High-Performance / Low-Power mode 12.5 Hz|
|0011|High-Performance / Low-Power mode 25 Hz|
|0100|High-Performance / Low-Power mode 50 Hz|
|0101|High-Performance / Low-Power mode 100 Hz|
|0110|High-Performance / Low-Power mode 200 Hz|
|0111|High-Performance / Low-Power mode 400/200 Hz|
|1000|High-Performance / Low-Power mode 800/200 Hz|
|1001|High-Performance / Low-Power mode 1600/200 Hz|



**Table 30. Mode selection** 

|**MODE[1:0]**|**Mode and resolution**|
|---|---|
|00|Low-Power Mode (12/14-bit resolution)|
|01|High-Performance Mode (14-bit resolution)|
|10|Single data conversion on demand mode (12/14-bit resolution)|
|11|-|



**Table 31. Low-power mode selection** 

|**LP_MODE[1:0]**|**Power mode and resolution**|
|---|---|
|00|Low-Power Mode 1 (12-bit resolution)|
|01|Low-Power Mode 2 (14-bit resolution)|
|10|Low-Power Mode 3 (14-bit resolution)|



**DS12825** - **Rev 3** 

**page 36/65** 

**LIS2DTW12 CTRL2 (21h)** 

|**LP_MODE[1:0]**|**Power mode and resolution**|
|---|---|
|11|Low-Power Mode 4 (14-bit resolution)|



## **8.5 CTRL2 (21h)** 

Control register 2 (r/w) 

**Table 32. Control register 2** 

|BOOT|SOFT_<br>RESET|0(1)|CS_PU_<br>DISC|BDU|IF_ADD_ INC|I2C_<br>DISABLE|SIM|
|---|---|---|---|---|---|---|---|



_1. This bit must be set to ‘0’ for the correct operation of the device._ 

|BOOT|Boot enables retrieving the correct trimming parameters from nonvolatile memory into registers where<br>trimming parameters are stored.<br>Once the operation is over, this bit automatically returns to 0.<br>Default value: 0 (0: disabled; 1: enabled)|
|---|---|
|SOFT_RESET|Soft reset acts as reset for all control registers, then goes to 0.<br>Default value: 0 (0: disabled; 1: enabled)|
|CS_PU_DISC|Disconnect CS pull-up. Default value: 0<br>(0: pull-up connected to CS pin;<br>1: pull-up disconnected to CS pin)|
|BDU|Block data update. Default value: 0<br>(0: continuous update; 1: output registers not updated until MSB and LSB read)|
|IF_ADD_INC|Register address automatically incremented during multiple byte access with a serial interface (I²C or SPI).<br>Default value: 1 (0: disabled; 1: enabled)|
|I2C_DISABLE|Disable I²C communication protocol. Default value: 0<br>(0: SPI and I²C interfaces enabled; 1: I²C mode disabled)|
|SIM|SPI serial interface mode selection. Default value: 0<br>0: 4-wire interface; 1: 3-wire interface|



The BDU bit is used to inhibit the update of the output registers until both upper and lower register parts are read. In default mode (BDU = ‘0’) the output register values are updated continuously. When the BDU is activated (BDU = ‘1’), the content of the output registers is not updated until both MSB and LSB are read which avoids reading values related to different sample times. 

**DS12825** - **Rev 3** 

**page 37/65** 

**LIS2DTW12 CTRL3 (22h)** 

## **8.6 CTRL3 (22h)** 

Control register 3 (r/w) 

## **Table 33. Control register 3** 

|ST2|ST1|PP_OD|LIR|H_LACTIVE|0|SLP_<br>MODE_SEL|SLP_<br>MODE_1|
|---|---|---|---|---|---|---|---|



## **Table 34. Control register 3 description** 

||**Table 34.Control register 3 description**|
|---|---|
|ST[2:1]|Self-test enable. Default value: 00<br>(00: Self-test disabled; Other: seeTable 35. Self-test mode selection)|
|PP_OD|Push-pull/open-drain selection on interrupt pad. Default value: 0<br>(0: push-pull; 1: open-drain)|
|LIR|Latched Interrupt. Switches between latched ('1'-logic) and pulsed ('0'-logic) mode for function source signals<br>and interrupts routed to pins (wakeup, single/double-tap). Default value: 0<br>(0: interrupt request not latched; 1: interrupt request latched)|
|H_LACTIVE|Interrupt active high, low. Default value: 0<br>(0: active high; 1: active low)|
|SLP_<br>MODE_SEL|Single data conversion on demand mode selection:<br>0: enabled with external trigger on INT2;<br>1: enabled by I²C/SPI writing SLP_MODE_1 to 1.|
|SLP_<br>MODE_1|Single data conversion on demand mode enable. When SLP_MODE_SEL = '1' and this bit is set to '1' logic,<br>single data conversion on demand mode starts. When XL data are available in the registers, this bit is set to '0'<br>automatically and the device is ready for another triggered session.|



## **Table 35. Self-test mode selection** 

|**ST2**|**ST1**|**Self-test mode**|
|---|---|---|
|0|0|Normal mode|
|0|1|Positive sign self-test|
|1|0|Negative sign self-test|
|1|1|-|



**DS12825** - **Rev 3** 

**page 38/65** 

**LIS2DTW12 CTRL4_INT1_PAD_CTRL (23h)** 

## **8.7 CTRL4_INT1_PAD_CTRL (23h)** 

Control register 4 (r/w) 

## **Table 36. Control register 4** 

|INT1_6D|INT1_<br>SINGLE_TAP|INT1_WU|INT1_FF|INT1_TAP|INT1_<br>DIFF5|INT1_<br>FTH|INT1_<br>DRDY|
|---|---|---|---|---|---|---|---|



## **Table 37. Control register 4 description** 

6D recognition is routed to INT1 pad. Default: 0 INT1_6D (0: disabled; 1: enabled) Single-tap recognition is routed to INT1 pad. Default value: 0 INT1_SINGLE_TAP (0: disabled; 1: enabled) Wakeup recognition is routed to INT1 pad. Default value: 0 INT1_WU (0: disabled; 1: enabled) Free-fall recognition is routed to INT1 pad. Default value: 0 INT1_FF (0: disabled; 1: enabled) Double-tap recognition is routed to INT1 pad. Default value: 0 INT1_TAP (0: disabled; 1: enabled) FIFO full recognition is routed to INT1 pad. Default value: 0 INT1_DIFF5 (0: disabled; 1: enabled) FIFO threshold interrupt is routed to INT1 pad. Default value: 0 INT1_FTH (0: disabled; 1: enabled) Data-Ready is routed to INT1 pad. Default value: 0 INT1_DRDY (0: disabled; 1: enabled) 

**DS12825** - **Rev 3** 

**page 39/65** 

**LIS2DTW12 CTRL5_INT2_PAD_CTRL (24h)** 

## **8.8 CTRL5_INT2_PAD_CTRL (24h)** 

Control register 5 (r/w) 

## **Table 38. Control register 5** 

|INT2_<br>SLEEP_STATE|INT2_<br>SLEEP_CHG|INT2_<br>BOOT|INT2_<br>DRDY_T|INT2_<br>OVR|INT2_<br>DIFF5|INT2_<br>FTH|INT2_<br>DRDY|
|---|---|---|---|---|---|---|---|



## **Table 39. Control register 5 description** 

Enable routing of SLEEP_STATE on INT2 pad. Default value: 0 INT2_SLEEP_STATE (0: disabled; 1: enabled) Sleep change status routed to INT2 pad. Default value: 0 INT2_SLEEP_CHG (0: disabled; 1: enabled) Boot state routed to INT2 pad. Default value: 0 INT2 _BOOT (0: disabled; 1: enabled) Temperature data-ready is routed to INT2. Default value: 0 INT2_DRDY_T (0: disabled; 1: enabled) FIFO overrun interrupt is routed to INT2 pad. Default value: 0 INT2 _OVR (0: disabled; 1: enabled) FIFO full recognition is routed to INT2 pad. Default value: 0 INT2_DIFF5 (0: disabled; 1: enabled) FIFO threshold interrupt is routed to INT2 pad. Default value: 0 INT2 _FTH (0: disabled; 1: enabled) Data-ready is routed to INT2 pad. Default value: 0 INT2 _DRDY (0: disabled; 1: enabled) 

**DS12825** - **Rev 3** 

**page 40/65** 

**LIS2DTW12 CTRL6 (25h)** 

## **8.9 CTRL6 (25h)** 

Control register 6 (r/w) 

## **Table 40. Control register 6** 

|BW_FILT1|BW_FILT0|FS1|FS0|FDS|LOW_<br>NOISE|0|0|
|---|---|---|---|---|---|---|---|



|BW_FILT[1:0]|Bandwidth selection (seeTable 41. Digital filtering cutoff selection)|
|---|---|
|FS[1:0]|Full-scale selection (seeTable 42. Full-scale selection)|
|FDS|Filtered data type selection. Default value: 0<br>(0: low-pass filter path selected;<br>1: high-pass filter path selected)|
|LOW_NOISE|Low-noise configuration.<br>(0: disabled; 1: enabled)|



**Table 41. Digital filtering cutoff selection** 

|**BW_FILT[1:0]**|**Bandwidth selection**|
|---|---|
|00|ODR/2 (up to ODR = 800 Hz, 400 Hz when ODR = 1600 Hz)|
|01|ODR/4 (HP/LP)|
|10|ODR/10 (HP/LP)|
|11|ODR/20 (HP/LP)|



**Table 42. Full-scale selection** 

|**FS[1:0]**|**Full-scale selection**|
|---|---|
|00|±2_g_|
|01|±4_g_|
|10|±8_g_|
|11|±16_g_|



**DS12825** - **Rev 3** 

**page 41/65** 

**LIS2DTW12 STATUS (27h)** 

## **8.10 STATUS (27h)** 

Status register (r). 

## **Table 43. STATUS register** 

|FIFO_THS|WU_IA|SLEEP_<br>STATE|DOUBLE_<br>TAP|SINGLE_<br>TAP|6D_IA|FF_IA|DRDY|
|---|---|---|---|---|---|---|---|



## **Table 44. STATUS register description** 

||**Table 44.STATUS register description**|
|---|---|
|FIFO_THS|FIFO threshold status flag.<br>(0: FIFO filling is lower than threshold level; 1: FIFO filling is equal to or higher than the threshold level.)|
|WU_IA|Wakeup event detection status.<br>(0: Wakeup event not detected; 1: Wakeup event detected)|
|SLEEP_<br>STATE|Sleep event status.<br>(0: Sleep event not detected; 1: Sleep event detected)|
|DOUBLE_<br>TAP|Double-tap event status<br>(0: Double-tap event not detected; 1: Double-tap event detected)|
|SINGLE_<br>TAP|Single-tap event status<br>(0: Single-tap event not detected; 1: Single-tap event detected)|
|6D_IA|Source of change in position portrait/landscape/face-up/face-down.<br>(0: no event detected; 1: a change in position detected)|
|FF_IA|Free-fall event detection status.<br>(0: free-fall event not detected; 1: free-fall event detected)|
|DRDY|Data-ready status.<br>(0: not ready; 1: X-, Y- and Z-axis new data available)|



**DS12825** - **Rev 3** 

**page 42/65** 

**LIS2DTW12 OUT_X_L (28h)** 

## **8.11 OUT_X_L (28h)** 

X-axis LSB output register (r). 

## **Table 45. OUT_X_L register** 

X_L7 X_L6 X_L5 X_L4 X_L3[(1)] X_L2[(1)] 0 0 

_1. If Low-Power Mode 1 is enabled, this bit is set to 0._ 

The 8 least significant bits of linear acceleration sensor X-axis output. Together with the OUT_X_H (29h) register, it forms the output value expressed as a 16-bit word in 2's complement. 

## **8.12 OUT_X_H (29h)** 

X-axis MSB output register (r). 

## **Table 46. OUT_X_H register** 

X_H7 X_H6 X_H5 X_H4 X_H3 X_H2 X_H1 X_H0 

The 8 most significant bits of linear acceleration sensor X-axis output. Together with the OUT_X_L (28h) register, it forms the output value expressed as a 16-bit word in 2's complement. 

## **8.13 OUT_Y_L (2Ah)** 

Y-axis LSB output register (r). 

**Table 47. OUT_Y_L register** 

Y_L7 Y_L6 Y_L5 Y_L4 Y_L3[(1)] Y_L2[(1)] 0 0 

_1. If Low-Power Mode 1 is enabled, this bit is set to 0._ 

The 8 least significant bits of linear acceleration sensor Y-axis output. Together with the OUT_Y_H (2Bh) register, it forms the output value expressed as a 16-bit word in 2's complement. 

## **8.14 OUT_Y_H (2Bh)** 

Y-axis MSB output register (r). 

**Table 48. OUT_Y_H register** 

Y_H7 Y_H6 Y_H5 Y_H4 Y_H3 Y_H2 Y_H1 Y_H0 

The 8 most significant bits of linear acceleration sensor Y-axis output. Together with the OUT_Y_L (2Ah) register, it forms the output value expressed as a 16-bit word in 2's complement. 

**DS12825** - **Rev 3** 

**page 43/65** 

**LIS2DTW12 OUT_Z_L (2Ch)** 

## **8.15 OUT_Z_L (2Ch)** 

Z-axis LSB output register (r). 

## **Table 49. OUT_Z_L register** 

Z_L7 Z_L6 Z_L5 Z_L4 Z_L3[(1)] Z_L2[(1)] 0 0 

_1. If Low-power Mode 1 is enabled, this bit is set to 0._ 

The 8 least significant bits of linear acceleration sensor Z-axis output. Together with the OUT_Z_H (2Dh) register, it forms the output value expressed as a 16-bit word in 2's complement. 

## **8.16 OUT_Z_H (2Dh)** 

Z-axis MSB output register (r). 

## **Table 50. OUT_Z_H register** 

Z_H7 Z_H6 Z_H5 Z_H4 Z_H3 Z_H2 Z_H1 Z_H0 

The 8 most significant bits of linear acceleration sensor Z-axis output. Together with the OUT_Z_L (2Ch) register, it forms the output value expressed as a 16-bit word in 2's complement. 

## **8.17 FIFO_CTRL (2Eh)** 

FIFO control register (r/w). 

**Table 51. FIFO_CTRL register** 

FMode2 FMode1 FMode0 FTH4 FTH3 FTH2 FTH1 FTH0 

## **Table 52. FIFO_CTRL register description** 

|FMode[2:0]|FIFO mode selection bits. Default: 000. For further details refer toTable 53. FIFO mode selection|
|---|---|
|FTH[4:0]|FIFO threshold level setting.|



**Table 53. FIFO mode selection** 

|**FMode[2:0]**|**Mode description**|
|---|---|
|000|Bypass mode: FIFO turned off|
|001|FIFO mode: Stops collecting data when FIFO is full.|
|010|Reserved|
|011|Continuous-to-FIFO: Stream mode until trigger is deasserted, then FIFO mode|
|100|Bypass-to-Continuous: Bypass mode until trigger is deasserted, then FIFO mode|
|101|Reserved|
|110|Continuous mode: If the FIFO is full, the new sample overwrites the older sample.|
|111|Reserved|



**DS12825** - **Rev 3** 

**page 44/65** 

**LIS2DTW12 FIFO_SAMPLES (2Fh)** 

## **8.18 FIFO_SAMPLES (2Fh)** 

FIFO_SAMPLES control register (r). 

## **Table 54. FIFO_SAMPLES register** 

|FIFO_<br>FTH|FIFO_<br>OVR|Diff5|Diff4|Diff3|Diff2|Diff1|Diff0|
|---|---|---|---|---|---|---|---|



## **Table 55. FIFO_SAMPLES register desription** 

||**Table 55.FIFO_SAMPLES register desription**|
|---|---|
|FIFO_FTH|FIFO threshold status flag.<br>(0: FIFO filling is lower than threshold level;<br>1: FIFO filling is equal to or higher than the threshold level.)|
|FIFO_OVR|FIFO overrun status.<br>(0: FIFO is not completely filled;<br>1: FIFO is completely filled and at least one sample has been overwritten)|
|Diff[5:0]|Represents the number of unread samples stored in FIFO.<br>(000000 = FIFO empty; 100000 = FIFO full, 32 unread samples).|



## **8.19 TAP_THS_X (30h)** 

4D configuration enable and TAP threshold configuration (r/w). 

## **Table 56. TAP_THS_X register** 

|4D_EN|6D_THS1|6D_THS0|TAP_<br>THSX_4|TAP_<br>THSX_3|TAP_<br>THSX_2|TAP_<br>THSX_1|TAP_<br>THSX_0|
|---|---|---|---|---|---|---|---|



## **Table 57. TAP_THS_X register description** 

||**Table 57.TAP_THS_X register description**|
|---|---|
|4D_EN|4D detection portrait/landscape position enable.<br>(0: no position detected;<br>1: portrait/landscape detection and face-up/face-down position enabled).|
|6D_THS[1:0]|Thresholds for 4D/6D function @ FS = ±2_g_(refer toTable 58. 4D/6D threshold setting FS @ ±2_g_)|
|TAP_THSX_[4:0]|Threshold for TAP recognition @ FS = ±2_g_on X direction|



**Table 58. 4D/6D threshold setting FS @ ±2** _**g**_ 

|**6D_THS[1:0]**|**Threshold decoding (degrees)**|
|---|---|
|00|6 (80 degrees)|
|01|11 (70 degrees)|
|10|16 (60 degrees)|
|11|21 (50 degrees)|



**DS12825** - **Rev 3** 

**page 45/65** 

**LIS2DTW12 TAP_THS_Y (31h)** 

## **8.20 TAP_THS_Y (31h)** 

## **Table 59. TAP_THS_Y register** 

|TAP_<br>PRIOR_2|TAP_<br>PRIOR_1|TAP_<br>PRIOR_0|TAP_<br>THSY_4|TAP_<br>THSY_3|TAP_<br>THSY_2|TAP_<br>THSY_1|TAP_<br>THSY_0|
|---|---|---|---|---|---|---|---|



## **Table 60. TAP_THS_Y register description** 

||**Table 60.TAP_THS_Y register description**|
|---|---|
|TAP_PRIOR_[2:0]|Selection of priority axis for tap detection (seeTable 61. Selection of axis priority for tap detection).|
|TAP_THSY_[4:0]|Threshold for tap recognition @ FS = ±2_g_on Y direction.|



**Table 61. Selection of axis priority for tap detection** 

|**TAP_PRIOR_[2:0]**|**Max priority**|**Mid priority**|**Min priority**|
|---|---|---|---|
|000|X|Y|Z|
|001|Y|X|Z|
|010|X|Z|Y|
|011|Z|Y|X|
|100|X|Y|Z|
|101|Y|Z|X|
|110|Z|X|Y|
|111|Z|Y|X|



## **8.21 TAP_THS_Z (32h)** 

**Table 62. TAP_THS_Z register** 

|TAP_X_<br>EN|TAP_Y_<br>EN|TAP_Z_<br>EN|TAP_<br>THSZ_4|TAP_<br>THSZ_3|TAP_<br>THSZ_2|TAP_<br>THSZ_1|TAP_<br>THSZ_0|
|---|---|---|---|---|---|---|---|



**Table 63. TAP_THS_Z register description** 

|TAP_X_EN|Enables X direction in tap recognition.<br>(0: disabled; 1: enabled)|
|---|---|
|TAP_Y_EN|Enables Y direction in tap recognition.<br>(0: disabled; 1: enabled)|
|TAP_Z_EN|Enables Z direction in tap recognition.<br>(0: disabled; 1: enabled)|
|TAP_THSZ_[4:0]|Threshold for tap recognition @ FS = ±2_g_on Z direction.|



**DS12825** - **Rev 3** 

**page 46/65** 

**LIS2DTW12 INT_DUR (33h)** 

## **8.22 INT_DUR (33h)** 

Interrupt duration register (r/w). 

## **Table 64. INT_DUR register** 

LATENCY3 LATENCY2 LATENCY1 LATENCY0 QUIET1 QUIET0 SHOCK1 SHOCK0 

## **Table 65. INT_DUR register description** 

Duration of maximum time gap for double-tap recognition. When double-tap recognition is enabled, this register expresses the maximum time between two successive detected taps to determine a double-tap event. LATENCY[3:0] Default value is LATENCY[3:0] = 0000 (which is 16 * 1/ODR) 1 LSB = 32 * 1/ODR Expected quiet time after a tap detection: this register represents the time after the first detected tap in which there must not be any overthreshold event. QUIET[1:0] Default value is QUIET[1:0] = 00 (which is 2 * 1/ODR) 1 LSB = 4 * 1/ODR Maximum duration of over-threshold event: this register represents the maximum time of an over-threshold signal detection to be recognized as a tap event. SHOCK[1:0] Default value is SHOCK[1:0] = 00 (which is 4 * 1/ODR) 1 LSB = 8 *1/ODR 

## **8.23 WAKE_UP_THS (34h)** 

Wakeup threshold register (r/w). 

## **Table 66. WAKE_UP_THS register** 

|SINGLE_<br>DOUBLE_<br>TAP|SLEEP_ ON|WK_THS5|WK_THS4|WK_THS3|WK_THS 2|WK_THS 1|WK_THS 0|
|---|---|---|---|---|---|---|---|



## **Table 67. WAKE_UP_THS register description** 

|SINGLE_DOUBLE_ TAP|Enable single/double-tap event. Default value: 0<br>(0: only single-tap event is enabled; 1: single and double-tap events are enabled)|
|---|---|
|SLEEP_ON|Sleep (inactivity) enable. Default value: 0<br>(0: sleep disabled; 1: sleep enabled)|
|WK_THS[5:0]|Wakeup threshold, 6-bit unsigned 1 LSB = 1/64 of FS. Default value: 000000|



**DS12825** - **Rev 3** 

**page 47/65** 

**LIS2DTW12 WAKE_UP_DUR (35h)** 

## **8.24 WAKE_UP_DUR (35h)** 

Wakeup and sleep duration configuration register (r/w). 

## **Table 68. WAKE_UP_DUR register** 

|FF_DUR5|WAKE_<br>DUR1|WAKE_<br>DUR0|STATIONARY|SLEEP_ DUR3|SLEEP_ DUR2|SLEEP_ DUR1|SLEEP_ DUR0|
|---|---|---|---|---|---|---|---|



## **Table 69. WAKE_UP_DUR register description** 

||**Table 69.WAKE_UP_DUR register description**|
|---|---|
|FF_DUR5|Free-fall duration. In conjunction with FF_DUR [4:0] bit inFREE_FALL (36h)register.<br>1 LSB = 1 * 1/ODR|
|WAKE_DUR[1:0]|Wakeup duration. 1 LSB = 1 *1/ODR|
|STATIONARY|Enable stationary detection / motion detection with no automatic ODR change when detecting stationary state.<br>Default value: 0<br>(0: disabled; 1: enabled)|
|SLEEP_ DUR[3:0]|Duration to go in sleep mode.<br>Default value is SLEEP_ DUR[3:0] = 0000 (which is 16 * 1/ODR).<br>1 LSB = 512 * 1/ODR|



## **8.25 FREE_FALL (36h)** 

Free-fall duration and threshold configuration register (r/w). 

## **Table 70. FREE_FALL register** 

FF_DUR4 FF_DUR3 FF_DUR2 FF_DUR1 FF_DUR0 FF_THS2 FF_THS1 FF_THS0 

## **Table 71. FREE_FALL register description** 

||**Table 71.FREE_FALL register description**|
|---|---|
|FF_DUR [4:0]|Free-fall duration. In conjunction with FF_DUR5 bit inWAKE_UP_DUR (35h)register.<br>1 LSB = 1 * 1/ODR|
|FF_THS [2:0]|Free-fall threshold @ FS = ±2_g_(refer toTable 72. FREE_FALL threshold decoding @ ± 2_g_FS)|



**Table 72. FREE_FALL threshold decoding @ ± 2** _**g**_ **FS** 

|**FF_THS[2:0]**|**Threshold decoding (LSB)**|
|---|---|
|000|5|
|001|7|
|010|8|
|011|10|
|100|11|
|101|13|
|110|15|
|111|16|



**DS12825** - **Rev 3** 

**page 48/65** 

**LIS2DTW12 STATUS_DUP (37h)** 

## **8.26 STATUS_DUP (37h)** 

Event detection status register (r). 

## **Table 73. STATUS_DUP register** 

|OVR|DRDY_T|SLEEP_<br>STATE_IA|DOUBLE_<br>TAP|SINGLE_<br>TAP|6D_IA|FF_IA|DRDY|
|---|---|---|---|---|---|---|---|



## **Table 74. STATUS_DUP register description** 

||**Table 74.STATUS_DUP register description**|
|---|---|
|OVR|FIFO overrun status flag.<br>(0: FIFO is not completely filled;<br>1: FIFO is completely filled and at least one sample has been overwritten)|
|DRDY_T|Temperature status.<br>(0: data not available; 1: a new set of data is available)|
|SLEEP_ STATE_IA|Sleep event status.<br>(0: Sleep event not detected; 1: Sleep event detected)|
|DOUBLE_ TAP|Double-tap event status:<br>(0: Double-tap event not detected; 1: Double-tap event detected)|
|SINGLE_ TAP|Single-tap event status:<br>(0: Single-tap event not detected; 1: Single-tap event detected)|
|6D_IA|Source of change in position portrait/landscape/face-up/face-down.<br>(0: no event detected; 1: a change in position is detected)|
|FF_IA|Free-fall event detection status.<br>(0: free-fall event not detected; 1: free-fall event detected)|
|DRDY|Data-ready status.<br>(0: not ready; 1: X-, Y- and Z-axis new data available)|



**DS12825** - **Rev 3** 

**page 49/65** 

**LIS2DTW12 WAKE_UP_SRC (38h)** 

## **8.27 WAKE_UP_SRC (38h)** 

Wakeup source register (r). 

## **Table 75. WAKE_UP_SRC register** 

|0|0|FF_IA|SLEEP_<br>STATE IA|WU_IA|X_WU|Y_WU|Z_WU|
|---|---|---|---|---|---|---|---|



## **Table 76. WAKE_UP_SRC register description** 

Free-fall event detection status. FF_IA (0: FF event not detected; 1: FF event detected) Sleep event status. SLEEP_ STATE IA (0: Sleep event not detected; 1: Sleep event detected) Wakeup event detection status. WU_IA (0: Wakeup event not detected; 1: Wakeup event is detected) Wakeup event detection status on X-axis. X_WU (0: Wakeup event on X not detected; 1: Wakeup event on X-axis is detected) Wakeup event detection status on Y-axis. Y_WU (0: Wakeup event on Y not detected; 1: Wakeup event on Y-axis is detected) Wakeup event detection status on Z-axis. Z_WU (0: Wakeup event on Z not detected; 1: Wakeup event on Z-axis is detected) 

**DS12825** - **Rev 3** 

**page 50/65** 

**LIS2DTW12 TAP_SRC (39h)** 

## **8.28 TAP_SRC (39h)** 

Tap source register (r). 

## **Table 77. TAP_SRC register** 

|0|TAP_IA|SINGLE_<br>TAP|DOUBLE_<br>TAP|TAP_SIGN|X_TAP|Y_TAP|Z_TAP|
|---|---|---|---|---|---|---|---|



## **Table 78. TAP_SRC register description** 

Tap event status. TAP_IA (0: tap event not detected; 1: tap event detected) Single-tap event status. SINGLE_TAP (0: single-tap event not detected; 1: single-tap event detected) Double-tap event status. DOUBLE_TAP (0: double-tap event not detected; 1: double-tap event detected) Sign of acceleration detected by tap event. TAP_SIGN (0: positive sign of acceleration detected; 1: negative sign of acceleration detected) Tap event detection status on X-axis. X_TAP (0: Tap event on X not detected; 1: Tap event on X-axis is detected) Tap event detection status on Y-axis. Y_TAP (0: Tap event on Y not detected; 1: Tap event on Y-axis is detected) Tap event detection status on Z-axis. Z_TAP (0: Tap event on Z not detected; 1: Tap event on Z-axis is detected) 

**DS12825** - **Rev 3** 

**page 51/65** 

**LIS2DTW12 SIXD_SRC (3Ah)** 

## **8.29 SIXD_SRC (3Ah)** 

6D source register (r). 

## **Table 79. SIXD_SRC register** 

0 6D_IA ZH ZL YH YL XH XL 

## **Table 80. SIXD_SRC register description** 

Source of change in position portrait/landscape/face-up/face-down. 6D_IA (0: no event detected; 1: a change in position is detected) ZH over threshold. ZH (0: ZH does not exceed the threshold; 1: ZH is over the threshold) ZL over threshold. ZL (0: ZL does not exceed the threshold; 1: ZL is over the threshold) YH over threshold. YH (0: YH does not exceed the threshold; 1: YH is over the threshold) YL over threshold. YL (0: YL does not exceed the threshold; 1: YL is over the threshold) XH over threshold. XH (0: XH does not exceed the threshold; 1: XH is over the threshold) XL over threshold. XL (0: XL does not exceed the threshold; 1: XL is over the threshold) 

**DS12825** - **Rev 3** 

**page 52/65** 

**LIS2DTW12 ALL_INT_SRC (3Bh)** 

## **8.30 ALL_INT_SRC (3Bh)** 

Reading this register, all related interrupt function flags routed to the INT pads are reset simultaneously. 

## **Table 81. ALL_INT_SRC register** 

|0|0|SLEEP_<br>CHANGE_IA|6D_IA|DOUBLE_<br>TAP|SINGLE_<br>TAP|WU_IA|FF_IA|
|---|---|---|---|---|---|---|---|
|**Table 82.ALL_INT_SRC register description**||||||||
|SLEEP_CHANGE_IA||Sleep change status.<br>(0: Sleep change not detected; 1: Sleep change detected)||||||
|6D_IA||Source of change in position portrait/landscape/face-up/face-down.<br>(0: no event detected; 1: a change in position detected)||||||
|DOUBLE_TAP||Double-tap event status.<br>(0: double-tap event not detected; 1: double-tap event detected)||||||
|SINGLE_TAP||Single-tap event status.<br>(0: single-tap event not detected; 1: single-tap event detected)||||||
|WU_IA||Wakeup event detection status.<br>(0: wakeup event not detected; 1: wakeup event detected)||||||
|FF_IA||Free-fall event detection status.<br>(0: free-fall event not detected; 1: free-fall event detected)||||||



**DS12825** - **Rev 3** 

**page 53/65** 

**LIS2DTW12 X_OFS_USR (3Ch)** 

## **8.31 X_OFS_USR (3Ch)** 

## **Table 83. X_OFS_USR register** 

|X_OFS_<br>USR_7|X_OFS_<br>USR_6|X_OFS_<br>USR_5|X_OFS_<br>USR_4|X_OFS_<br>USR_3|X_OFS_<br>USR_2|X_OFS_<br>USR_1|X_OFS_<br>USR_0|
|---|---|---|---|---|---|---|---|



## **Table 84. X_OFS_USR register description** 

X_OFS_USR_[7:0] Two's complement user offset value on X-axis data, used for wakeup function. 

## **8.32 Y_OFS_USR (3Dh)** 

## **Table 85. Y_OFS_USR register** 

|Y_OFS_<br>USR_7|Y_OFS_<br>USR_6|Y_OFS_<br>USR_5|Y_OFS_<br>USR_4|Y_OFS_<br>USR_3|Y_OFS_<br>USR_2|Y_OFS_<br>USR_1|Y_OFS_<br>USR_0|
|---|---|---|---|---|---|---|---|



## **Table 86. Y_OFS_USR register description** 

Y_OFS_USR_[7:0] Two's complement user offset value on Y-axis data, used for wakeup function. 

## **8.33 Z_OFS_USR (3Eh)** 

## **Table 87. Z_OFS_USR register** 

|Z_OFS_<br>USR_7|Z_OFS_<br>USR_6|Z_OFS_<br>USR_5|Z_OFS_<br>USR_4|Z_OFS_<br>USR_3|Z_OFS_<br>USR_2|Z_OFS_<br>USR_1|Z_OFS_<br>USR_0|
|---|---|---|---|---|---|---|---|



## **Table 88. Z_OFS_USR register description** 

Z_OFS_USR_[7:0] Two's complement user offset value on Z-axis data, used for wakeup function. 

**DS12825** - **Rev 3** 

**page 54/65** 

**LIS2DTW12 CTRL7 (3Fh)** 

## **8.34 CTRL7 (3Fh)** 

## **Table 89. CTRL7 register** 

|DRDY_<br>PULSED|INT2_ON_<br>INT1|INTERRUPTS<br>_ENABLE|USR_OFF<br>_ON_OUT|USR_OFF<br>_ON_WU|USR_<br>OFF _W|HP_REF<br>_MODE|LPASS_<br>ON6D|
|---|---|---|---|---|---|---|---|



## **Table 90. CTRL7 register description** 

||**Table 90.CTRL7 register description**|
|---|---|
|DRDY_PULSED|Switches between latched and pulsed mode for data ready interrupt.<br>(0: latched mode is used; 1: pulsed mode enabled for data-ready)|
|INT2_ON_INT1|Signal routing.<br>(1: all signals available only on INT2 are routed on INT1)|
|INTERRUPTS_ENABLE|Enable interrupts.|
|USR_OFF_ON_OUT|Enable application of user offset value on XL output data registers.<br>FDS bit inCTRL6 (25h)must be set to '0'-logic (low-pass path selected).|
|USR_OFF_ON_WU|Enable application of user offset value on XL data for wakeup function only.|
|USR_OFF_W|Selects the weight of the user offset words specified by X_OFS_USR_[7:0], Y_OFS_USR_[7:0] and<br>Z_OFS_USR_[7:0] bits.<br>(0: 977 µg/LSB; 1: 15.6 mg/LSB)|
|HP_REF_MODE|High-pass filter reference mode enable.<br>(0: high-pass filter reference mode disabled (default);<br>1: high-pass filter reference mode enabled)|
|LPASS_ON6D|(0: ODR/2 low pass filtered data sent to 6D interrupt function (default);<br>1: LPF2 output data sent to 6D interrupt function)|



**DS12825** - **Rev 3** 

**page 55/65** 

**LIS2DTW12 Package information** 

## **9 Package information** 

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark. 

## **9.1** 

## **Soldering information** 

The LGA package is compliant with the ECOPACK[®] , RoHS and “Green” standard. It is qualified for soldering heat resistance according to JEDEC J-STD-020. Land pattern and soldering recommendations are available at www.st.com. 

## **9.2 LGA-12 package information** 

## **Figure 18. LGA-12 2.0 x 2.0 x 0.7 mm package outline and mechanical data** 

Dimensions are in millimeter unless otherwise specified General Tolerance is +/-0.15mm unless otherwise specified 

## **OUTER DIMENSIONS** 

|**ITEM**<br>Length[L]<br>Width[W]<br>Height [H]|**DIMENSION[mm]**|**TOLERANCE[mm]**|
|---|---|---|
||2|±0.1|
||2|±0.1|
||0.7 MAX|/|
||||



**DS12825** - **Rev 3** 

**page 56/65** 

**LIS2DTW12 LGA-12 packing information** 

## **9.3 LGA-12 packing information** 

**Figure 19. Carrier tape information for LGA-12 package** 

**Figure 20. LGA-12 package orientation in carrier tape** 

**DS12825** - **Rev 3** 

**page 57/65** 

**LIS2DTW12** 

## **Revision history** 

## **Table 91. Document revision history** 

|**Date**|**Revision**|**Changes**|
|---|---|---|
|07-Jan-2019|1|Initial release|
|03-May-2019|2|Updated Figure 19. Carrier tape information for LGA-12 package|
|02-Jul-2019|3|UpdatedOUT_T_L (0Dh)andOUT_T_H (0Eh)|



**DS12825** - **Rev 3** 

**page 58/65** 

**LIS2DTW12 Contents** 

|**Contents**|**Contents**||
|---|---|---|
|**1**|**Block**|**diagram and pin description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3**|
||**1.1**|Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3|
||**1.2**|Pin description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4|
|**2**|**Mechanical and electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6**||
||**2.1**|Mechanical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6|
||**2.2**|Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7|
||**2.3**|Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8|
||**2.4**|Communication interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9|
|||**2.4.1**<br>SPI - serial peripheral interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9|
|||**2.4.2**<br>I²C - inter-IC control interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10|
||**2.5**|Absolute maximum ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11|
|**3**|**Terminology and functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13**||
||**3.1**|Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13|
|||**3.1.1**<br>Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13|
|||**3.1.2**<br>Zero-g level offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13|
||**3.2**|Functionality. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14|
|||**3.2.1**<br>Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14|
|||**3.2.2**<br>Single data conversion on-demand mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16|
|||**3.2.3**<br>Self-test. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16|
|||**3.2.4**<br>Activity/Inactivity, Android stationary/motion detection functions . . . . . . . . . . . . . . . . . . . . 17|
|||**3.2.5**<br>High tap/double-tap user configurability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17|
|||**3.2.6**<br>Offset management. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17|
||**3.3**|Sensing element . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18|
||**3.4**|IC interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18|
||**3.5**|Factory calibration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18|
||**3.6**|Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18|
|**4**|**Application hints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19**||
|**5**|**Digital main blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21**||
||**5.1**|Block diagram of filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21|



**DS12825** - **Rev 3** 

**page 59/65** 

**LIS2DTW12 Contents** 

||**5.2**|Data stabilization time vs. ODR/device setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22|
|---|---|---|
||**5.3**|FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23|
|||**5.3.1**<br>Bypass mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24|
|||**5.3.2**<br>FIFO mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24|
|||**5.3.3**<br>Continuous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24|
|||**5.3.4**<br>Continuous-to-FIFO mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25|
|||**5.3.5**<br>Bypass-to-Continuous mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26|
|**6**|**Digital interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27**||
||**6.1**|I²C serial interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27|
|||**6.1.1**<br>I²C operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28|
||**6.2**|SPI bus interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29|
|||**6.2.1**<br>SPI read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30|
|||**6.2.2**<br>SPI write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31|
|||**6.2.3**<br>SPI read in 3-wire mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32|
|**7**|**Register mapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33**||
|**8**|**Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35**||
||**8.1**|OUT_T_L (0Dh). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35|
||**8.2**|OUT_T_H (0Eh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35|
||**8.3**|WHO_AM_I (0Fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35|
||**8.4**|CTRL1 (20h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36|
||**8.5**|CTRL2 (21h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37|
||**8.6**|CTRL3 (22h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38|
||**8.7**|CTRL4_INT1_PAD_CTRL (23h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39|
||**8.8**|CTRL5_INT2_PAD_CTRL (24h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40|
||**8.9**|CTRL6 (25h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41|
||**8.10**|STATUS (27h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42|
||**8.11**|OUT_X_L (28h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43|
||**8.12**|OUT_X_H (29h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43|
||**8.13**|OUT_Y_L (2Ah). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43|
||**8.14**|OUT_Y_H (2Bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43|
||**8.15**|OUT_Z_L (2Ch). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44|



**DS12825** - **Rev 3** 

**page 60/65** 

**LIS2DTW12 Contents** 

||**8.16**|OUT_Z_H (2Dh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44|
|---|---|---|
||**8.17**|FIFO_CTRL (2Eh). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44|
||**8.18**|FIFO_SAMPLES (2Fh). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45|
||**8.19**|TAP_THS_X (30h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45|
||**8.20**|TAP_THS_Y (31h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46|
||**8.21**|TAP_THS_Z (32h). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46|
||**8.22**|INT_DUR (33h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47|
||**8.23**|WAKE_UP_THS (34h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47|
||**8.24**|WAKE_UP_DUR (35h). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48|
||**8.25**|FREE_FALL (36h). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48|
||**8.26**|STATUS_DUP (37h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49|
||**8.27**|WAKE_UP_SRC (38h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50|
||**8.28**|TAP_SRC (39h). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51|
||**8.29**|SIXD_SRC (3Ah). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52|
||**8.30**|ALL_INT_SRC (3Bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53|
||**8.31**|X_OFS_USR (3Ch). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54|
||**8.32**|Y_OFS_USR (3Dh). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54|
||**8.33**|Z_OFS_USR (3Eh). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54|
||**8.34**|CTRL7 (3Fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55|
|**9**|**Package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56**||
||**9.1**|Soldering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56|
||**9.2**|LGA-12 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56|
||**9.3**|LGA-12 packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56|
|**Revision**||**history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58**|



**DS12825** - **Rev 3** 

**page 61/65** 

**LIS2DTW12 List of tables** 

## **List of tables** 

|**Table**|**1.**|Pin description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4|
|---|---|---|
|**Table**|**2.**|Internal pull-up values (typ.) for SDO/SA0 and CS pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5|
|**Table**|**3.**|Mechanical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6|
|**Table**|**4.**|Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7|
|**Table**|**5.**|Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8|
|**Table**|**6.**|SPI slave timing values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9|
|**Table**|**7.**|I²C slave timing values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10|
|**Table**|**8.**|I²C high-speed mode specifications at 1 MHz and 3.4 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11|
|**Table**|**9.**|Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12|
|**Table**|**10.**|Operating modes - low-noise setting disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14|
|**Table**|**11.**|Operating modes - low-noise setting enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15|
|**Table**|**12.**|Internal pin status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20|
|**Table**|**13.**|Number of samples to be discarded . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22|
|**Table**|**14.**|Serial interface pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27|
|**Table**|**15.**|I²C terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27|
|**Table**|**16.**|SAD+Read/Write patterns. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28|
|**Table**|**17.**|Transfer when master is writing one byte to slave. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28|
|**Table**|**18.**|Transfer when master is writing multiple bytes to slave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28|
|**Table**|**19.**|Transfer when master is receiving (reading) one byte of data from slave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28|
|**Table**|**20.**|Transfer when master is receiving (reading) multiple bytes of data from slave . . . . . . . . . . . . . . . . . . . . . . . . . 28|
|**Table**|**21.**|Register map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33|
|**Table**|**22.**|OUT_T_L register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35|
|**Table**|**23.**|OUT_T_L register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35|
|**Table**|**24.**|OUT_T_H register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35|
|**Table**|**25.**|OUT_T_H register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35|
|**Table**|**26.**|WHO_AM_I register default values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35|
|**Table**|**27.**|Control register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36|
|**Table**|**28.**|Control register 1 description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36|
|**Table**|**29.**|Data rate configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36|
|**Table**|**30.**|Mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36|
|**Table**|**31.**|Low-power mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36|
|**Table**|**32.**|Control register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37|
|**Table**|**33.**|Control register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38|
|**Table**|**34.**|Control register 3 description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38|
|**Table**|**35.**|Self-test mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38|
|**Table**|**36.**|Control register 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39|
|**Table**|**37.**|Control register 4 description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39|
|**Table**|**38.**|Control register 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40|
|**Table**|**39.**|Control register 5 description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40|
|**Table**|**40.**|Control register 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41|
|**Table**|**41.**|Digital filtering cutoff selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41|
|**Table**|**42.**|Full-scale selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41|
|**Table**|**43.**|STATUS register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42|
|**Table**|**44.**|STATUS register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42|
|**Table**|**45.**|OUT_X_L register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43|
|**Table**|**46.**|OUT_X_H register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43|
|**Table**|**47.**|OUT_Y_L register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43|
|**Table**|**48.**|OUT_Y_H register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43|
|**Table**|**49.**|OUT_Z_L register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44|
|**Table**|**50.**|OUT_Z_H register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44|
|**Table**|**51.**|FIFO_CTRL register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44|
|**Table**|**52.**|FIFO_CTRL register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44|



**DS12825** - **Rev 3** 

**page 62/65** 

**LIS2DTW12 List of tables** 

**Table 53.** FIFO mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 **Table 54.** FIFO_SAMPLES register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 **Table 55.** FIFO_SAMPLES register desription . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 **Table 56.** TAP_THS_X register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 **Table 57.** TAP_THS_X register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 **Table 58.** 4D/6D threshold setting FS @ ±2 _g_ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 **Table 59.** TAP_THS_Y register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 **Table 60.** TAP_THS_Y register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 **Table 61.** Selection of axis priority for tap detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 **Table 62.** TAP_THS_Z register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 **Table 63.** TAP_THS_Z register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 **Table 64.** INT_DUR register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 **Table 65.** INT_DUR register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 **Table 66.** WAKE_UP_THS register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 **Table 67.** WAKE_UP_THS register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 **Table 68.** WAKE_UP_DUR register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 **Table 69.** WAKE_UP_DUR register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 **Table 70.** FREE_FALL register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 **Table 71.** FREE_FALL register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 **Table 72.** FREE_FALL threshold decoding @ ± 2 _g_ FS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 **Table 73.** STATUS_DUP register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 **Table 74.** STATUS_DUP register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 **Table 75.** WAKE_UP_SRC register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 **Table 76.** WAKE_UP_SRC register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 **Table 77.** TAP_SRC register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 **Table 78.** TAP_SRC register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 **Table 79.** SIXD_SRC register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 **Table 80.** SIXD_SRC register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 **Table 81.** ALL_INT_SRC register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 **Table 82.** ALL_INT_SRC register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 **Table 83.** X_OFS_USR register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 **Table 84.** X_OFS_USR register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 **Table 85.** Y_OFS_USR register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 **Table 86.** Y_OFS_USR register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 **Table 87.** Z_OFS_USR register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 **Table 88.** Z_OFS_USR register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 **Table 89.** CTRL7 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 **Table 90.** CTRL7 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 **Table 91.** Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 

**DS12825** - **Rev 3** 

**page 63/65** 

**LIS2DTW12 List of figures** 

## **List of figures** 

|**Figure**|**1.**|Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3|
|---|---|---|
|**Figure**|**2.**|Pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4|
|**Figure**|**3.**|SPI slave timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9|
|**Figure**|**4.**|I²C slave timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10|
|**Figure**|**5.**|Single data conversion on-demand functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16|
|**Figure**|**6.**|LIS2DTW12 electrical connections (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19|
|**Figure**|**7.**|Accelerometer chain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21|
|**Figure**|**8.**|Continuous-to-FIFO mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25|
|**Figure**|**9.**|Trigger event to FIFO for Continuous-to-FIFO mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25|
|**Figure**|**10.**|Bypass-to-Continuous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26|
|**Figure**|**11.**|Trigger event to FIFO for Bypass-to-Continuous mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26|
|**Figure**|**12.**|Read and write protocol. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29|
|**Figure**|**13.**|SPI read protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30|
|**Figure**|**14.**|Multiple byte SPI read protocol (2-byte example). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30|
|**Figure**|**15.**|SPI write protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31|
|**Figure**|**16.**|Multiple byte SPI write protocol (2-byte example) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31|
|**Figure**|**17.**|SPI read protocol in 3-wire mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32|
|**Figure**|**18.**|LGA-12 2.0 x 2.0 x 0.7 mm package outline and mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56|
|**Figure**|**19.**|Carrier tape information for LGA-12 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57|
|**Figure**|**20.**|LGA-12 package orientation in carrier tape. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57|



**DS12825** - **Rev 3** 

**page 64/65** 

**LIS2DTW12** 

## **IMPORTANT NOTICE – PLEASE READ CAREFULLY** 

STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. 

Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. 

No license, express or implied, to any intellectual property right is granted by ST herein. 

Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. 

ST and the ST logo are trademarks of ST. For additional information about ST trademarks, please refer to www.st.com/trademarks. All other product or service names are the property of their respective owners. 

Information in this document supersedes and replaces information previously supplied in any prior versions of this document. 

© 2019 STMicroelectronics – All rights reserved 

**DS12825** - **Rev 3** 

**page 65/65**
Updated at April 22, 2026
STMicroelectronics is a global leader in the semiconductor industry, recognized for developing highly integrated, energy-efficient solutions that power modern electronics. With a strong focus on innovation, ST provides a comprehensive portfolio of microelectronics that address the demanding requirements of industrial, automotive, communications, and consumer applications. Our extensive selection of STMicroelectronics components is built around a robust lineup of discrete semiconductors and circuit protection devices. We offer a wide variety of single MOSFETs, Schottky diodes, and fast and ultrafast recovery rectifier diodes, designed to deliver exceptional efficiency and thermal performance in power management and conversion systems. For robust circuit protection, our inventory features hundreds of transient voltage suppressors and TVS diodes that safeguard sensitive electronic components against destructive voltage spikes. In addition to core power discretes like TRIACs, SCRs, bipolar transistors, and single IGBTs, our STMicroelectronics range includes specialized integrated passive filters and MEMS sensors. Furthermore, ST offers advanced integrated passive devices, such as baluns and RF filters, which utilize high-quality monolithic RF IPD processes on glass or high-resistance silicon substrates. These components provide competitive cost structures, reduced power losses, and simplified RFIC-to-antenna matching, ensuring optimal system performance and delivering the reliability required for next-generation wireless and power designs.
About Novapart

Novapart is a B2B electronic component broker specialising in stock shortages and cost reduction. We source hard-to-find parts and identify compliant alternatives across a catalogue of 410,000+ components from 500+ manufacturers.
Learn more →
Stock Shortage Specialist

When a component is unavailable, discontinued or has an unacceptable lead time, we tap into our network of vetted European and Asian distributors to source what you need — without compromising on quality or traceability.
Request a quote →
Compliant Alternatives

We identify pin-to-pin, electrically equivalent substitutes that meet the same certifications (RoHS, AEC-Q100, REACH) as your original specification — validated against datasheets, not just part numbers. Often at a lower cost.
BOM Analysis service →