LIS2DETR

MEMS Accelerometer, 3-Axis, Digital, X, Y, Z, ± 2g, ± 4g, ± 8g, ± 16g, 1.71 V, 3.6 V, LGA

⚠️ Reference pricing provided. In case of supply shortages, we will connect you with our trusted procurement partners to ensure your project's continuity.
Manufacturer: STMICROELECTRONICS
Product type: MEMS Accelerometers
No. of Pins: 14Pins
Sensitivity Typ: 15.6mg/digit, 31.2mg/digit, 62.5mg/digit, 187.5mg/digit
Measurement Axis: X, Y, Z
Sensor Case Style: LGA
Acceleration Range: ± 2g, ± 4g, ± 8g, ± 16g
MEMS Sensor Output: Digital
Supply Voltage Max: 3.6V
Supply Voltage Min: 1.71V
Delivery and price
Units per pack	1
Price	0.45 €
Current stock	10+
Lead time	30 days
Datasheet
## **LIS2DE** 

## MEMS digital output motion sensor: ultra-low-power high-performance 3-axis "femto" accelerometer 

**Datasheet** - **production data** 

- Intelligent power saving for handheld devices 

- Pedometers 

- Display orientation 

- Gaming and virtual reality input devices 

## **LGA-14 (2.0x2.0x1 mm)** 

- Impact recognition and logging 

- Vibration monitoring and compensation 

## **Features** 

- Wide supply voltage, 1.71 V to 3.6 V 

- Independent IO supply (1.8 V) and supply voltage compatible 

- Ultra-low-power mode consumption down to 2 μA 

- 2 _g_ /±4 _g_ /8 _g_ /16 _g_ dynamically selectable full scales 

- I[2] C/SPI digital output interface 

- 8-bit data output 

- 2 independent programmable interrupt generators for free-fall and motion detection 

- 6D/4D orientation detection 

- “Sleep-to-wake” and “Return-to-sleep” functions 

- Free-fall detection 

- Motion detection 

- Embedded temperature sensor 

- Embedded self-test 

- Embedded FIFO 

- 10000 _g_ high shock survivability 

- ECOPACK[®] , RoHS and “Green” compliant 

## **Description** 

The LIS2DE is an ultra-low-power highperformance 3-axis linear accelerometer belonging to the “femto” family, with digital I[2] C/SPI serial interface standard output. The device features ultra-low-power operational modes that allow advanced power saving and smart embedded functions. 

The LIS2DE has dynamically user-selectable full scales of 2 _g_ /4 _g_ /8 _g_ /16 _g_ and is capable of measuring accelerations with output data rates from 1 Hz to 5 kHz. The self-test capability allows the user to check the functioning of the sensor in the final application. The device may be configured to generate interrupt signals by two independent inertial wakeup/free-fall events as well as by the position of the device itself. Thresholds and the timing of interrupt generators are programmable by the end user on the fly. The LIS2DE has an integrated 32-level first-in, first-out (FIFO) buffer allowing the user to store data in order to limit intervention by the host processor. The LIS2DE is available in a small thin plastic land grid array package (LGA) and it is guaranteed to operate over an extended temperature range from -40 °C to +85 °C. 

**Table 1. Device summary** 

## **Applications** 

- Motion-activated functions 

- Free-fall detection 

- Click/double-click recognition 

|**Order codes**|**Temp.**<br>**range [****C]**|**Package**|**Packaging**|
|---|---|---|---|
|LIS2DE|-40 to +85|LGA-14|Tray|
|LIS2DETR|-40 to +85|LGA-14|Tape and reel|



June 2014 

This is information on a product in full production. 

DocID023717 Rev 2 

1/45 

_www.st.com_ 

**Contents** 

**LIS2DE** 

## **Contents** 

|**1**|**Block**|**diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7**|
|---|---|---|
||1.1|Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7|
||1.2|Pin description  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7|
|**2**|**Mechanical and electrical specifications  . . . . . . . . . . . . . . . . . . . . . . . . 9**||
||2.1|Mechanical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9|
||2.2|Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10|
||2.3|Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10|
||2.4|Communication interface characteristics  . . . . . . . . . . . . . . . . . . . . . . . . . 11|
|||2.4.1<br>SPI - serial peripheral interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11|
|||2.4.2<br>I2C - inter-IC control interface  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12|
||2.5|Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13|
|**3**|**Terminology and functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14**||
||3.1|Terminology  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14|
|||3.1.1<br>Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14|
|||3.1.2<br>Zero-g level  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14|
||3.2|Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14|
|||3.2.1<br>Normal mode, low-power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14|
|||3.2.2<br>Self-test  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14|
|||3.2.3<br>6D / 4D orientation detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15|
|||3.2.4<br>Sleep-to-wake and return-to-sleep functions . . . . . . . . . . . . . . . . . . . . . 15|
||3.3|Sensing element . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15|
||3.4|IC interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16|
||3.5|Factory calibration  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16|
||3.6|FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16|
||3.7|Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16|
|**4**|**Application hints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17**||
||4.1|Soldering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17|
|**5**|**Digital main blocks  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18**||
||5.1|FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18|
|2/45||DocID023717 Rev 2|



|**LIS2DE**||**Contents**|
|---|---|---|
|||5.1.1<br>Bypass mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18|
|||5.1.2<br>FIFO mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18|
|||5.1.3<br>Stream mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18|
|||5.1.4<br>Stream-to-FIFO mode  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19|
|||5.1.5<br>Retrieving data from FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19|
|**6**|**Digital interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20**||
||6.1|I2C serial interface  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20|
|||6.1.1<br>I2C operation  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21|
||6.2|SPI bus interface  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22|
|||6.2.1<br>SPI read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23|
|||6.2.2<br>SPI write  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24|
|||6.2.3<br>SPI read in 3-wire mode  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25|
|**7**|**Register mapping  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26**||
|**8**|**Register description  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28**||
||8.1|STATUS_REG_AUX (07h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28|
||8.2|OUT_TEMP_L (0Ch), OUT_TEMP_H (0Dh)  . . . . . . . . . . . . . . . . . . . . . . 28|
||8.3|INT_COUNTER_REG (0Eh)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28|
||8.4|WHO_AM_I (0Fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28|
||8.5|TEMP_CFG_REG (1Fh)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28|
||8.6|CTRL_REG1 (20h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29|
||8.7|CTRL_REG2 (21h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29|
||8.8|CTRL_REG3 (22h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30|
||8.9|CTRL_REG4 (23h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31|
||8.10|CTRL_REG5 (24h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31|
||8.11|CTRL_REG6 (25h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32|
||8.12|REFERENCE (26h)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32|
||8.13|STATUS_REG2 (27h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32|
||8.14|OUT_X (29h)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33|
||8.15|OUT_Y (2Bh)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33|
||8.16|OUT_Z (2Dh)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33|
||8.17|FIFO_CTRL_REG (2Eh)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33|
||8.18|FIFO_SRC_REG (2Fh)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34|



3/45 

DocID023717 Rev 2 

**Contents** 

**LIS2DE** 

||8.19|IG1_CFG (30h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34|
|---|---|---|
||8.20|IG1_SOURCE (31h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35|
||8.21|IG1_THS (32h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36|
||8.22|IG1_DURATION (33h)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36|
||8.23|IG2_CFG (34h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36|
||8.24|IG2_SOURCE (35h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37|
||8.25|IG2_THS (36h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38|
||8.26|IG2_DURATION (37h)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38|
||8.27|CLICK_CFG (38h)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38|
||8.28|CLICK_SRC (39h)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39|
||8.29|CLICK_THS (3Ah)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39|
||8.30|TIME_LIMIT (3Bh)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39|
||8.31|TIME_LATENCY (3Ch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40|
||8.32|TIME_WINDOW (3Dh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40|
||8.33|Act_THS (3Eh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40|
||8.34|Act_DUR (3Fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40|
|**9**|**Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41**||
|**10**|**Revision history  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43**||



4/45 

DocID023717 Rev 2 

**LIS2DE** 

**List of tables** 

## **List of tables** 

|Table|1.|Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1|
|---|---|---|
|Table|2.|Pin description  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8|
|Table|3.|Mechanical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9|
|Table|4.|Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10|
|Table|5.|Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10|
|Table|6.|SPI slave timing values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11|
|Table|7.|I2C slave timing values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12|
|Table|8.|Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13|
|Table|9.|Operating mode selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14|
|Table|10.|Serial interface pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20|
|Table|11.|Serial interface pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20|
|Table|12.|SAD+Read/Write patterns  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21|
|Table|13.|Transfer when master is writing one byte to slave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21|
|Table|14.|Transfer when master is writing multiple bytes to slave . . . . . . . . . . . . . . . . . . . . . . . . . . . 22|
|Table|15.|Transfer when master is receiving (reading) one byte of data from slave  . . . . . . . . . . . . . 22|
|Table|16.|Transfer when master is receiving (reading) multiple bytes of data from slave . . . . . . . . . 22|
|Table|17.|Register address map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26|
|Table|18.|STATUS_REG_AUX register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28|
|Table|19.|STATUS_REG_AUX register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28|
|Table|20.|INT_COUNTER_REG register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28|
|Table|21.|WHO_AM_I register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28|
|Table|22.|TEMP_CFG_REG register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28|
|Table|23.|TEMP_CFG_REG register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28|
|Table|24.|CTRL_REG1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29|
|Table|25.|CTRL_REG1 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29|
|Table|26.|Data rate configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29|
|Table|27.|CTRL_REG2 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29|
|Table|28.|CTRL_REG2 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30|
|Table|29.|High-pass filter mode configuration  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30|
|Table|30.|CTRL_REG3 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30|
|Table|31.|CTRL_REG3 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30|
|Table|32.|CTRL_REG4 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31|
|Table|33.|CTRL_REG4 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31|
|Table|34.|Self-test mode configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31|
|Table|35.|CTRL_REG5 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31|
|Table|36.|CTRL_REG5 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31|
|Table|37.|CTRL_REG6 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32|
|Table|38.|CTRL_REG6 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32|
|Table|39.|REFERENCE register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32|
|Table|40.|REFERENCE register description  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32|
|Table|41.|STATUS_REG2 register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32|
|Table|42.|STATUS_REG2 register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32|
|Table|43.|FIFO_CTRL_REG register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33|
|Table|44.|FIFO_CTRL_REG register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33|
|Table|45.|FIFO mode configuration  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34|
|Table|46.|FIFO_SRC_REG register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34|
|Table|47.|FIFO_SRC_REG register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34|
|Table|48.|IG1_CFG register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34|



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**LIS2DE** 

|Table|49.|IG1_CFG register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34|
|---|---|---|
|Table|50.|Interrupt mode  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35|
|Table|51.|IG1_SOURCE register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35|
|Table|52.|IG1_SOURCE register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35|
|Table|53.|IG1_THS register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36|
|Table|54.|IG1_THS register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36|
|Table|55.|IG1_DURATION register  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36|
|Table|56.|IG1_DURATION register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36|
|Table|57.|IG2_CFG register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36|
|Table|58.|IG2_CFG register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36|
|Table|59.|Interrupt mode  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37|
|Table|60.|IG2_SOURCE register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37|
|Table|61.|IG2_SOURCE register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37|
|Table|62.|IG2_THS register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38|
|Table|63.|IG2_THS register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38|
|Table|64.|IG2_DURATION register  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38|
|Table|65.|IG2_DURATION register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38|
|Table|66.|CLICK_CFG register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38|
|Table|67.|CLICK_CFG register description  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38|
|Table|68.|CLICK_SRC register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39|
|Table|69.|CLICK_SRC register description  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39|
|Table|70.|CLICK_THS register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39|
|Table|71.|CLICK_THS register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39|
|Table|72.|TIME_LIMIT register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39|
|Table|73.|TIME_LIMIT register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39|
|Table|74.|TIME_LATENCY register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40|
|Table|75.|TIME_LATENCY register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40|
|Table|76.|TIME_WINDOW register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40|
|Table|77.|TIME_WINDOW register description  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40|
|Table|78.|Act_THS register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40|
|Table|79.|Act_THS register description  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40|
|Table|80.|Act_DUR register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40|
|Table|81.|Act_DUR register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40|
|Table|82.|LGA-14 2x2x1 mechanical dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42|
|Table|83.|Document revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43|



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DocID023717 Rev 2 

**LIS2DE** 

**List of figures** 

## **List of figures** 

|Figure|1.|Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8|
|---|---|---|
|Figure|2.|Pin connections  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8|
|Figure|3.|SPI slave timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12|
|Figure|4.|I2C slave timing diagram  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13|
|Figure|5.|LIS2DE electrical connections  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18|
|Figure|6.|Read and write protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24|
|Figure|7.|SPI read protocol  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24|
|Figure|8.|Multiple byte SPI read protocol (2-byte example). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25|
|Figure|9.|SPI write protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25|
|Figure|10.|Multiple byte SPI write protocol (2-byte example). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26|
|Figure|11.|SPI read protocol in 3-wire mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26|
|Figure|12.|LGA-14 2x2x1 mechanical drawing  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43|



7/45 

DocID023717 Rev 2 

**LIS2DE** 

**Block diagram and pin description** 

## **1 Block diagram and pin description** 

## **1.1 Block diagram** 

**==> picture [114 x 11] intentionally omitted <==**

**----- Start of picture text -----**<br>
Figure 1. Block diagram<br>**----- End of picture text -----**<br>


**==> picture [405 x 186] intentionally omitted <==**

**----- Start of picture text -----**<br>
X+<br>Y+ CHARGE CS<br>Z+ AMPLIFIER<br>CONTROL  I2C SCL/SPC<br>a MUX CONVERTERA/D  LOGIC SDA/SDO/SDI<br>SPI<br>Z- SDO/SA0<br>Y-<br>X-<br>SELF TEST TemperatureSensor TRIMMINGCIRCUITS CLOCK 32 Level FIFO INTERRUPT GEN.CONTROL LOGIC& INT 1INT 2<br>AM14758V1<br>**----- End of picture text -----**<br>


## **1.2 Pin description** 

**Figure 2. Pin connections** 

**==> picture [405 x 216] intentionally omitted <==**

**----- Start of picture text -----**<br>
Z<br>Pin 1 indicator<br>12 14<br>11 1 SCL/SPC<br>1<br>SDA/SDI/SDO<br>GND SDO/SA0<br>Vdd 8 4 CS<br>7 5<br>X Y<br>(TOP VIEW) (BOTTOM VIEW)<br>DIRECTION OF THE<br>DETECTABLE<br>ACCELERATIONS<br>AM14759V1<br>Res Res<br>Vdd_IO INT1 INT2<br>**----- End of picture text -----**<br>


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**LIS2DE** 

**Block diagram and pin description** 

**Table 2. Pin description** 

|||**Table 2. Pin description**|
|---|---|---|
|**Pin#**|**Name**|**Function**|
|1|SCL<br>SPC|I2C serial clock (SCL)<br>SPI serial port clock (SPC)|
|2|SDA<br>SDI<br>SDO|I2C serial data (SDA)<br>SPI serial data input (SDI)<br>3-wire interface serial data output (SDO)|
|3|SDO<br>SA0|SPI serial data output (SDO)<br>I2C least significant bit of the device address (SA0)|
|4|CS|SPI enable<br>I2C/SPI mode selection (1: SPI idle mode / I2C communication<br>enabled; 0: SPI communication mode / I2C disabled)|
|5|INT2|Interrupt 2|
|6|INT1|Interrupt 1|
|7|Vdd_IO|Power supply for I/O pins|
|8|Vdd|Power supply|
|9|GND|0 V supply|
|10|RES|Connect to GND|
|11|RES|Connect to GND|
|12-14|GND|Connect to GND|



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**Mechanical and electrical specifications** 

**LIS2DE** 

## **2 Mechanical and electrical specifications** 

## **2.1 Mechanical characteristics** 

Vdd = 2.5 V, T = 25 °C unless otherwise noted[(a)] . 

**Table 3. Mechanical characteristics** 

|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.(1)**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|FS|Measurement range(2)|FS bit set to 00||±2.0||_g_|
|||FS bit set to 01||±4.0|||
|||FS bit set to 10||±8.0|||
|||FS bit set to 11||±16.0|||
|So|Sensitivity|FS bit set to 00||15.6||m_g_/digit|
|||FS bit set to 01||31.2||m_g_/digit|
|||FS bit set to 10||62.5||m_g_/digit|
|||FS bit set to 11||187.5||m_g_/digit|
|TCSo|Sensitivity change vs.<br>temperature|FS bit set to 00||±0.05||%/°C|
|TyOff|Typical zero-_g_level<br>offset accuracy(3)(4)|FS bit set to 00||±100||m_g_|
|TCOff|Zero-_g_level change<br>vs. temperature|Max. delta from 25 °C||±1.0||m_g_/°C|
|Vst|Self-test<br>output change(5)(6)(7)|FS bit set to 00<br>X-axis|50||1800|m_g_|
|||FS bit set to 00<br>Y-axis|50||1800|m_g_|
|||FS bit set to 00<br>Z-axis|50||1800|m_g_|
|Top|Operating<br>temperature range||-40||+85|°C|



1. Typical specifications are not guaranteed. 

2. Verified by wafer level test and measurement of initial offset and sensitivity. 

3. Typical zero- _g_ level offset value after MSL3 preconditioning. 

4. Offset can be eliminated by enabling the built-in high-pass filter. 

5. The sign of the “self-test output change” is defined by CTRL_REG4 ST sign bits, for all axes. 

6. The “self-test output change” is defined as the absolute value of: OUTPUT[LSb](CTRL_REG4 ST1, ST0 bits=01) - OUTPUT[LSb](CTRL_REG4 ST1, ST0 bits=00) 

7. Output data reaches 99% of final value after 1ms+1/ODR when enabling the self-test mode, due to device filtering. 

a. The product is factory calibrated at 2.5 V. The operational power supply range is from 1.71 V to 3.6 V. 

10/45 

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**LIS2DE** 

**Mechanical and electrical specifications** 

## **2.2 Temperature sensor characteristics** 

Vdd = 2.5 V, T = 25 °C unless otherwise noted[ (b)] . 

**Table 4. Temperature sensor characteristics** 

|**Symbol**|**Parameter**|**Test condition**|**Min.**|**Typ.(1)**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|TSDr|Temperature sensor output change vs.<br>temperature|-||1||digit/°C(2)|
|TODR|Temperature refresh rate|||ODR||Hz|
|Top|Operating temperature range||-40||+85|°C|



1. Typical specifications are not guaranteed. Temperature sensor operation is guaranteed in the range 2 V - 3.6 V. 

2. 8-bit resolution. 

## **2.3 Electrical characteristics** 

Vdd = 2.5 V, T = 25 °C unless otherwise noted[(c)] . 

**Table 5. Electrical characteristics** 

|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.(1)**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|Vdd|Supply voltage||1.71|2.5|3.6|V|
|Vdd_IO|I/O pins supply voltage(2)||1.71||Vdd+0.1|V|
|Idd|Current consumption in normal mode|50 Hz ODR||11||μA|
|Idd|Current consumption in normal mode|1 Hz ODR||2||μA|
|IddLP|Current consumption in low-power mode|50 Hz ODR||6||μA|
|IddPdn|Current consumption in power-down<br>mode|||0.5||μA|
|VIH|Digital high-level input voltage||0.8*Vdd_IO|||V|
|VIL|Digital low-level input voltage||||0.2*Vdd_IO|V|
|VOH|High-level output voltage||0.9*Vdd_IO|||V|
|VOL|Low-level output voltage||||0.1*Vdd_IO|V|
|BW|System bandwidth(3)|||ODR/2||Hz|
|Top|Operating temperature range||-40||+85|°C|



1. Typical specifications are not guaranteed. 

2. It is possible to remove Vdd while maintaining Vdd_IO without blocking the communication busses. In this condition the measurement chain is powered off. 

3. Refer to _Table 26_ for the ODR value and configuration. 

   - b. The product is factory calibrated at 2.5 V. 

c. The product is factory calibrated at 2.5 V. The operational power supply range is from 1.71 V to 3.6 V. 

11/45 

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**Mechanical and electrical specifications** 

**LIS2DE** 

## **2.4 Communication interface characteristics** 

## **2.4.1 SPI - serial peripheral interface** 

Subject to general operating conditions for Vdd and Top. 

**Table 6. SPI slave timing values** 

|**Symbol**|**Parameter**|**Value (**1**)**|**Value (**1**)**|**Unit**|
|---|---|---|---|---|
|||**Min.**|**Max.**||
|tc(SPC)|SPI clock cycle|100||ns|
|fc(SPC)|SPI clock frequency||10|MHz|
|tsu(CS)|CS setup time|6||ns|
|th(CS)|CS hold time|8|||
|tsu(SI)|SDI input setup time|5|||
|th(SI)|SDI input hold time|15|||
|tv(SO)|SDO valid output time||50||
|th(SO)|SDO output hold time|9|||
|tdis(SO)|SDO output disable time||50||



**Figure 3. SPI slave timing diagram** 

_Note: Values are guaranteed at 10 MHz clock frequency for SPI with both 4 and 3 wires, based on characterization results, not tested in production._ 

_Measurement points are done at 0.2·Vdd_IO and 0.8·Vdd_IO, for both the input and output ports._ 

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**LIS2DE** 

**Mechanical and electrical specifications** 

## **2.4.2 I[2] C - inter-IC control interface** 

Subject to general operating conditions for Vdd and Top. 

**Table 7. I[2] C slave timing values** 

|**Symbol**|**Parameter**|**I2C standard mode (1)**|**I2C standard mode (1)**|**I2C fast mode (1)**|**I2C fast mode (1)**|**Unit**|
|---|---|---|---|---|---|---|
|||**Min.**|**Max.**|**Min.**|**Max.**||
|f(SCL)|SCL clock frequency|0|100|0|400|kHz|
|tw(SCLL)|SCL clock low time|4.7||1.3||μs|
|tw(SCLH)|SCL clock high time|4.0||0.6|||
|tsu(SDA)|SDA setup time|250||100||ns|
|th(SDA)|SDA data hold time|0.01|3.45|0.01|0.9|μs|
|tr(SDA)tr(SCL)|SDA and SCL rise time||1000|20 + 0.1Cb<br>(2)|300|ns|
|tf(SDA)tf(SCL)|SDA and SCL fall time||300|20 + 0.1Cb<br>(**2)**|300||
|th(ST)|START condition hold time|4||0.6||μs|
|tsu(SR)|Repeated START condition<br>setup time|4.7||0.6|||
|tsu(SP)|STOP condition setup time|4||0.6|||
|tw(SP:SR)|Bus free time between STOP<br>and START condition|4.7||1.3|||



1. Data based on standard I[2] C protocol requirement, not tested in production. 

2. Cb = total capacitance of one bus line, in pF. 

**Figure 4. I[2] C slave timing diagram** 

**==> picture [461 x 161] intentionally omitted <==**

**----- Start of picture text -----**<br>
REPEATED<br>ST ART<br>START<br>tsu(SR)<br>SDA  tw(SP:SR) START<br>tf(SDA) tr(SDA) tsu(SDA) th(SDA)<br>tsu(SP) STOP<br>SCL<br>th(ST) tw(SCLL) tw(SCLH) tr(SCL) tf(SCL) AM07229v1<br>**----- End of picture text -----**<br>


_Note: Measurement points are done at 0.2·Vdd_IO and 0.8·Vdd_IO, for both ports._ 

13/45 

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**Mechanical and electrical specifications** 

**LIS2DE** 

## **2.5 Absolute maximum ratings** 

Stresses above those listed as “absolute maximum ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device under these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. 

**Table 8. Absolute maximum ratings** 

|**Symbol**|**Ratings**|**Maximum value**|**Unit**|
|---|---|---|---|
|Vdd|Supply voltage|-0.3 to 4.8|V|
|Vdd_IO|I/O pins supply voltage|-0.3 to 4.8|V|
|Vin|Input voltage on any control pin<br>(CS, SCL/SPC, SDA/SDI/SDO, SDO/SA0)|-0.3 to Vdd_IO +0.3|V|
|APOW|Acceleration (any axis, powered, Vdd = 2.5 V)|3000 for 0.5 ms|g|
|||10000 for 0.1 ms|g|
|AUNP|Acceleration (any axis, unpowered)|3000 for 0.5 ms|g|
|||10000 for 0.1 ms|g|
|TOP|Operating temperature range|-40 to +85|°C|
|TSTG|Storage temperature range|-40 to +125|°C|
|ESD|Electrostatic discharge protection|2 (HBM)|kV|



_Note: Supply voltage on any pin should never exceed 4.8 V._ 

This device is sensitive to mechanical shock, improper handling can cause permanent damage to the part. 

This device is sensitive to electrostatic discharge (ESD), improper handling can cause permanent damage to the part. 

14/45 DocID023717 Rev 2 ~~>~~ 

**LIS2DE** 

**Terminology and functionality** 

## **3 Terminology and functionality** 

## **3.1 Terminology** 

## **3.1.1 Sensitivity** 

Sensitivity describes the gain of the sensor and can be determined, for example, by applying 1 _g_ acceleration to it. As the sensor can measure DC accelerations, this can be done easily by pointing the axis of interest towards the center of the Earth, noting the output value, rotating the sensor by 180 degrees (pointing to the sky) and noting the output value again. By doing so, ±1 _g_ acceleration is applied to the sensor. Subtracting the larger output value from the smaller one, and dividing the result by 2, leads to the actual sensitivity of the sensor. This value changes very little over temperature and also time. The sensitivity tolerance describes the range of sensitivities of a large population of sensors. 

## **3.1.2 Zero-** _**g**_ **level** 

Zero- _g_ level offset (TyOff) describes the deviation of an actual output signal from the ideal output signal if no acceleration is present. A sensor in a steady-state on a horizontal surface measures 0 _g_ on the X-axis and 0 _g_ on the Y-axis whereas the Z-axis measures 1 _g_ . The output is ideally in the middle of the dynamic range of the sensor (content of OUT registers 00h, data expressed as two’s complement number). A deviation from the ideal value in this case is called Zero- _g_ offset. Offset is, to some extent, a result of stress to the MEMS sensor and therefore the offset can slightly change after mounting the sensor onto a printed circuit board or exposing it to extensive mechanical stress. Offset changes little over temperature, see “Zero- _g_ level change vs. temperature”. The Zero- _g_ level tolerance (TyOff) describes the standard deviation of the range of Zero- _g_ levels of a population of sensors. 

## **3.2 Functionality** 

## **3.2.1 Normal mode, low-power mode** 

The LIS2DE provides two different operating modes: _normal mode_ and _low-power mode_ . _Table 9_ summarizes how to select the operating mode. 

**Table 9. Operating mode selection** 

|**CTRL_REG1 [3] (LPen bit)**|**Operating mode**|
|---|---|
|1|Low-power mode|
|0|Normal mode|



## **3.2.2 Self-test** 

The self-test allows the sensor functionality to be checked without moving it. The self-test function is off when the self-test bit (ST) is programmed to ‘0’. When the self-test bit is programmed to ‘1’, an actuation force is applied to the sensor, simulating a definite input acceleration. In this case the sensor outputs exhibit a change in their DC levels which are related to the selected full scale through the device sensitivity. 

15/45 

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**Terminology and functionality** 

**LIS2DE** 

When the self-test is activated, the device output level is given by the algebraic sum of the signals produced by the acceleration acting on the sensor and by the electrostatic testforce. If the output signals change within the amplitude specified in _Table 3_ , then the sensor is working properly and the parameters of the interface chip are within the defined specifications. 

## **3.2.3 6D / 4D orientation detection** 

The LIS2DE includes 6D / 4D orientation detection. 

**6D / 4D orientation recognition** : In this configuration the interrupt is generated when the device is stable in a known direction. In 4D configuration Z-axis position detection is disabled. 

## **3.2.4** 

## **Sleep-to-wake and return-to-sleep functions** 

The LIS2DE can be programmed to automatically switch to low-power mode upon recognition of a determined event. Once the event condition is over, the device returns to the preset normal mode. 

To enable this function, the desired threshold value must be stored in the _Act_THS (3Eh)_ registers, while the duration value must be written in the _Act_DUR (3Fh)_ register. 

When the acceleration, which is internally high-pass filtered, becomes lower than the threshold value on all of the three axes, the device automatically switches to Low-power mode (10 Hz ODR). 

During this condition, the ODRx bits and LPen bit inside _CTRL_REG1 (20h)_ are not considered. 

Once the acceleration rises above the threshold (at least on one axis), the system restores the operating mode and ODRs as per the _CTRL_REG1 (20h)_ and _CTRL_REG4 (23h)_ settings. 

## **3.3 Sensing element** 

A proprietary process is used to create a surface micromachined accelerometer. The technology allows processing suspended silicon structures which are attached to the substrate in a few points called anchors and are free to move in the direction of the sensed acceleration. To be compatible with the traditional packaging techniques, a cap is placed on top of the sensing element to avoid the moving parts from being blocked during the molding phase of the plastic encapsulation. 

When an acceleration is applied to the sensor the proof mass displaces from its nominal position, causing an imbalance in the capacitive half bridge. This imbalance is measured using charge integration in response to a voltage pulse applied to the capacitor. 

At steady-state the nominal value of the capacitors are a few pF and when an acceleration is applied, the maximum variation of the capacitive load is in the fF range. 

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**Terminology and functionality** 

## **3.4 IC interface** 

The complete measurement chain is made up of a low-noise capacitive amplifier which converts the capacitive unbalancing of the MEMS sensor into an analog voltage using an analog-to-digital converter. 

The acceleration data may be accessed through an I[2] C/SPI interface, therefore making the device particularly suitable for direct interfacing with a microcontroller. 

The LIS2DE features a data-ready signal (DRDY) which indicates when a new set of measured acceleration data is available, therefore simplifying data synchronization in the digital system that uses the device. 

The LIS2DE may also be configured to generate an inertial wakeup and free-fall interrupt signal according to a programmed acceleration event along the enabled axes. Both free-fall and wakeup can be available simultaneously on two different pins. 

## **3.5 Factory calibration** 

The IC interface is factory calibrated for sensitivity (So) and Zero- _g_ level (TyOff). 

The trimming values are stored inside the device in non-volatile memory. Any time the device is turned on, the trimming parameters are downloaded into the registers to be used during the active operation. This allows the device to be used without further calibration. 

## **3.6** 

## **FIFO** 

The LIS2DE contains a 32-level FIFO for each of the three output channels, X, Y and Z. Buffered output allows 4 operation modes: FIFO, Stream, Stream-to-FIFO and Bypass. Where FIFO Bypass mode is activated FIFO is not operating and remains empty. In FIFO mode, data from acceleration detection on the X-, Y-, and Z-axis measurements are stored in FIFO. 

## **3.7 Temperature sensor** 

The LIS2DE is equipped with an internal temperature sensor. Temperature data can be enabled by setting the TEMP_EN bit of the _TEMP_CFG_REG (1Fh)_ register to “1”. 

To retrieve the temperature sensor data, the BDU bit on _CTRL_REG4 (23h)_ must be set to “1”. Both the OUT_TEMP_H and OUT_TEMP_L registers must be read. 

Temperature data is stored inside OUT_TEMP_H as two’s complement data, in 8-bit format, left-justified. 

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**Application hints** 

## **4 Application hints** 

**Figure 5. LIS2DE electrical connections** 

**==> picture [404 x 306] intentionally omitted <==**

**----- Start of picture text -----**<br>
Vdd_IO Vdd<br>GND<br>Pin 1 indicator<br>14 12<br>SCL/SPC<br>GND<br>1 11<br>SDA/SDI/SDO GND 10µF<br>SDO/SA0 GND<br>CS Vdd<br>4 8<br>100nF<br>5 7<br>GND<br>AM14760V1<br>INT2 INT1<br>Vdd_IO<br>**----- End of picture text -----**<br>


The device core is supplied through the Vdd line while the I/O pads are supplied through the Vdd_IO line. Power supply decoupling capacitors (100 nF ceramic, 10 μF aluminum) should be placed as near as possible to pin 8 of the device (common design practice). 

All the voltage and ground supplies must be present at the same time to have proper behavior of the IC (refer to _Figure 5_ ). It is possible to remove Vdd while maintaining Vdd_IO without blocking the communication bus. In this condition the measurement chain is powered off. 

The functionality of the device and the measured acceleration data is selectable and accessible through the I[2] C or SPI interfaces. When using the I[2] C, CS must be tied high. 

The functions, the threshold and the timing of the two interrupt pins (INT1 and INT2) can be completely programmed by the user through the I[2] C/SPI interface. 

## **4.1 Soldering information** 

The LGA package is compliant with the ECOPACK[®] , RoHS and “Green” standards. It is qualified for soldering heat resistance according to JEDEC J-STD-020. 

Leave “Pin 1 Indicator” unconnected during soldering. 

Land pattern and soldering recommendations are available at www.st.com. 

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**Digital main blocks** 

## **5 Digital main blocks** 

## **5.1 FIFO** 

The LIS2DE embeds a 32-level FIFO for each of the three output channels, X, Y and Z. This allows consistent power saving for the system, since the host processor does not need to continuously poll data from the sensor, but it can wake up only when needed and burst the significant data out from the FIFO. 

In order to enable the FIFO buffer, the FIFO_EN bit in _CTRL_REG5 (24h)_ must be set to ‘1’. 

This buffer can work according to four different modes: Bypass mode, FIFO mode, Stream mode and Stream-to-FIFO mode. Each mode is selected by the FM [1:0] bits in _FIFO_CTRL_REG (2Eh)_ . Programmable FIFO watermark level, FIFO empty or FIFO overrun events can be enabled to generate dedicated interrupts on the INT1 pin (configuration through _CTRL_REG3 (22h)_ ). 

FIFO_SRC_REG (EMPTY) is equal to ‘1’ when all FIFO samples are ready and FIFO is empty. 

FIFO_SRC_REG (WTM) goes to ‘1’ if a new data is written in the buffer and FIFO_SRC_REG (FSS [4:0]) is greater than or equal to FIFO_CTRL_REG (FTH [4:0]). FIFO_SRC_REG (WTM) goes to ‘0’ if reading X, Y, Z data slot from FIFO and FIFO_SRC_REG (FSS [4:0]) is less than or equal to FIFO_CTRL_REG (FTH [4:0]). FIFO_SRC_REG (OVRN_FIFO) is equal to ‘1’ if a FIFO slot is overwritten. 

## **5.1.1 Bypass mode** 

In Bypass mode the FIFO is not operational and for this reason it remains empty. For each channel only the first address is used. The remaining FIFO levels are empty. 

Bypass mode must be used in order to reset the FIFO buffer when a different mode is operating (i.e. FIFO mode). 

## **5.1.2 FIFO mode** 

In FIFO mode, the buffer continues filling data from the X, Y and Z accelerometer channels until it is full (32 samples set stored). When the FIFO is full, it stops collecting data from the input channels and the FIFO content remains unchanged. 

An overrun interrupt can be enabled, INT1_OVERRUN = '1' in the _CTRL_REG3 (22h)_ register, in order to be raised when the FIFO stops collecting data. When an overrun interrupt occurs, the first data has been overwritten and the FIFO stops collecting data from the input channels. 

At the end of the reading procedure it is necessary to exit Bypass mode in order to reset the FIFO content. After this reset command, it is possible to restart FIFO mode just by selecting the FIFO mode configuration (FM bits) in register _FIFO_CTRL_REG (2Eh)_ . 

## **5.1.3 Stream mode** 

In Stream mode the FIFO continues filling data from X, Y, and Z accelerometer channels, when the buffer is full (32 samples set stored) the FIFO buffer index restarts from the beginning and older data is replaced by the current. The oldest values continue to be overwritten until a read operation frees FIFO slots. 

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**Digital main blocks** 

An overrun interrupt can be enabled, INT1_OVERRUN = '1' in the _CTRL_REG3 (22h)_ register, in order to read the entire FIFO content at once. If, in the application, it is mandatory not to lose data and it is not possible to read at least one sample for each axis within one ODR period, a watermark interrupt can be enabled in order to read partially the FIFO and leave memory slots free for incoming data. 

Setting the FTH [4:0] bit in the _FIFO_CTRL_REG (2Eh)_ register to N value, the number of X, Y and Z data samples that should be read at the watermark interrupt rising is up to (N+1). 

## **5.1.4 Stream-to-FIFO mode** 

In Stream-to-FIFO mode, data from the X, Y and Z accelerometer channels are collected in a combination of Stream mode and FIFO mode; the FIFO buffer starts operating in Stream mode and switches to FIFO mode when the selected interrupt occurs. 

The FIFO operating mode changes according to the INT1 pin value if the TR bit is set to ‘0’ in the _FIFO_CTRL_REG (2Eh)_ register or the INT2 pin value if the TR bit is set to ‘1’ in the _FIFO_CTRL_REG (2Eh)_ register. 

When the interrupt pin is selected and the interrupt event is configured on the related pin, the FIFO operates in Stream mode if the pin value is equal to ‘0’ and it operates in FIFO mode if the pin value is equal to ‘1’. The switch mode is dynamically performed according to the pin value. 

Stream-to-FIFO can be used in order to analyze the sample history that generated an interrupt; the standard operation is to read FIFO content when FIFO mode is triggered and the FIFO buffer is full and stopped. 

## **5.1.5** 

## **Retrieving data from FIFO** 

FIFO reads must start from register 28h. 

FIFO X, Y and Z data are read from _OUT_X (29h)_ , _OUT_Y (2Bh)_ and _OUT_Z (2Dh)_ . When the FIFO is in Stream, Stream-to-FIFO or FIFO mode, a read operation to the _OUT_X (29h)_ , _OUT_Y (2Bh)_ and _OUT_Z (2Dh)_ registers provides the data stored in the FIFO. Each time data is read from the FIFO, the oldest X, Y and Z data are placed in the _OUT_X (29h)_ , _OUT_Y (2Bh)_ and _OUT_Z (2Dh)_ registers and both single read and read_burst[(d)] operations can be used. 

> d. The read address is automatically updated by the device and rolls back to 0x28 when register 0x2D is reached. In order to read all FIFO levels in a multiple byte read, 196 bytes (6 output registers by 32 levels) must be read. FIFO reads must start from register 0x28 for output update and 0x2D for FIFO pointer update. 

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**Digital interfaces** 

## **6 Digital interfaces** 

The registers embedded inside the LIS2DE may be accessed through both the I[2] C and SPI serial interfaces. The latter may be SW configured to operate either in 3-wire or 4-wire interface mode. 

The serial interfaces are mapped onto the same pads. To select/exploit the I[2] C interface, the CS line must be tied high (i.e. connected to Vdd_IO). 

**Table 10. Serial interface pin description** 

||**Table 10. Serial interface pin description**|
|---|---|
|**Pin name**|**Pin description**|
|CS|SPI enable<br>I2C/SPI mode selection (1: I2C mode; 0: SPI enabled)|
|SCL<br>SPC|I2C serial clock (SCL)<br>SPI serial port clock (SPC)|
|SDA<br>SDI<br>SDO|I2C serial data (SDA)<br>SPI serial data input (SDI)<br>3-wire interface serial data output (SDO)|
|SA0<br>SDO|I2C least significant bit of the device address (SA0)<br>SPI serial data output (SDO)|



## **6.1 I[2] C serial interface** 

The LIS2DE I[2] C is a bus slave. The I[2] C is employed to write data into registers whose content can also be read back. 

The relevant I[2] C terminology is given in the table below. 

**Table 11. Serial interface pin description** 

||**Table 11. Serial interface pin description**|
|---|---|
|**Term**|**Description**|
|Transmitter|The device which sends data to the bus|
|Receiver|The device which receives data from the bus|
|Master|The device which initiates a transfer, generates clock signals and terminates a<br>transfer|
|Slave|The device addressed by the master|



There are two signals associated with the I[2] C bus; the serial clock line (SCL) and the serial data line (SDA). The latter is a bidirectional line used for sending and receiving the data to/from the interface. Both lines must be connected to Vdd_IO through an external pull-up resistor. When the bus is free, both lines are high. 

The I[2] C interface is compliant with fast mode (400 kHz) I[2] C standards as well as with the normal mode. 

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## **6.1.1 I[2] C operation** 

The transaction on the bus is started through a START (ST) signal. A START condition is defined as a HIGH-to-LOW transition on the data line while the SCL line is held HIGH. After this has been transmitted by the master, the bus is considered busy. The next byte of data transmitted after the START condition contains the address of the slave in the first 7 bits and the eighth bit tells whether the master is receiving data from the slave or transmitting data to the slave. When an address is sent, each device in the system compares the first seven bits after a START condition with its address. If they match, the device considers itself addressed by the master. 

The slave address (SAD) associated to the LIS2DE is 010100xb. The **SDO** / **SA0** pad can be used to modify the least significant bit of the device address. If the SA0 pad is connected to a voltage supply, LSB is ‘1’ (address 0101001b) or, if the SA0 pad is connected to ground, the LSB value is ‘0’ (address 0101000b). This solution permits two different accelerometers to be connected and addressed to the same I[2] C lines. 

Data transfer with acknowledge is mandatory. The transmitter must release the SDA line during the acknowledge pulse. The receiver must then pull the data line LOW so that it remains stable low during the HIGH period of the acknowledge clock pulse. A receiver which has been addressed is obliged to generate an acknowledge after each byte of data received. 

The I[2] C embedded inside the LIS2DE behaves like a slave device and the following protocol must be adhered to. After the START condition (ST) a slave address is sent, once a slave acknowledge (SAK) has been returned, an 8-bit sub-address (SUB) is transmitted: the 7 LSB represent the actual register address while the MSB enables address auto increment. If the MSB of the SUB field is ‘1’, the SUB (register address) is automatically increased to allow multiple data read/write. 

The slave address is completed with a Read/Write bit. If the bit is ‘1’ (read), a repeated START (SR) condition must be issued after the two sub-address bytes; if the bit is ‘0’ (write), the master transmits to the slave with direction unchanged. _Table 12_ explains how the SAD+Read/Write bit pattern is composed, listing all the possible configurations. 

## **Table 12. SAD+Read/Write patterns** 

|**Command**|**SAD[6:1]**|**SAD[0] = SA0**|**R/W**|**SAD+R/W**|
|---|---|---|---|---|
|Read|010100|0|1|01010001 (51h)|
|Write|010100|0|0|01010000 (50h)|
|Read|010100|1|1|01010011 (53h)|
|Write|010100|1|0|01010010 (52h)|



## **Table 13. Transfer when master is writing one byte to slave** 

|**Master**|**ST**|**SAD + W**||**SUB**||**DATA**||**SP**|
|---|---|---|---|---|---|---|---|---|
|Slave|||SAK||SAK||SAK||



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**Table 14. Transfer when master is writing multiple bytes to slave** 

|**Master**|**ST**|**SAD + W**||**SUB**||**DATA**||**DATA**||**SP**|
|---|---|---|---|---|---|---|---|---|---|---|
|Slave|||SAK||SAK||SAK||SAK||



**Table 15. Transfer when master is receiving (reading) one byte of data from slave** 

|**Master**|**ST**|**SAD + W**||**SUB**||**SR**|**SAD + R**|||**NMAK**|**SP**|
|---|---|---|---|---|---|---|---|---|---|---|---|
|Slave|||SAK||SAK|||SAK|DATA|||



**Table 16. Transfer when master is receiving (reading) multiple bytes of data from slave** 

|**Master**|**ST**|**SAD+W**||**SUB**||**SR**|**SAD+R**|||**MAK**||**MAK**||**NMAK**|**SP**|
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|Slave|||SAK||SAK|||SAK|DATA||DATA||DATA|||



Data are transmitted in byte format (DATA). Each data transfer contains 8 bits. The number of bytes transferred per transfer is unlimited. Data is transferred with the most significant bit (MSB) first. If a receiver can’t receive another complete byte of data until it has performed some other function, it can hold the clock line SCL LOW to force the transmitter into a wait state. Data transfer only continues when the receiver is ready for another byte and releases the data line. If a slave receiver doesn’t acknowledge the slave address (i.e. it is not able to receive because it is performing some real-time function) the data line must be left HIGH by the slave. The master can then abort the transfer. A LOW-to-HIGH transition on the SDA line while the SCL line is HIGH is defined as a STOP condition. Each data transfer must be terminated by the generation of a STOP (SP) condition. 

In order to read multiple bytes, it is necessary to assert the most significant bit of the subaddress field. In other words, SUB(7) must be equal to 1 while SUB(6-0) represents the address of the first register to be read. 

In the presented communication format, MAK is master acknowledge and NMAK is no master acknowledge. 

## **6.2 SPI bus interface** 

The LIS2DE SPI is a bus slave. The SPI allows reading from and writing to the registers of the device. 

The serial interface interacts with the outside world with 4 wires: **CS** , **SPC** , **SDI** and **SDO** . 

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**Figure 6. Read and write protocol** 

**==> picture [405 x 135] intentionally omitted <==**

**----- Start of picture text -----**<br>
CS<br>SPC<br>SDI<br>RW DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0<br>MS AD5 AD4 AD3 AD2 AD1 AD0<br>SDO<br>DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0<br>**----- End of picture text -----**<br>


**CS** is the serial port enable and it is controlled by the SPI master. It goes low at the start of the transmission and goes back high at the end. **SPC** is the serial port clock and it is controlled by the SPI master. It is stopped high when **CS** is high (no transmission). **SDI** and **SDO** are respectively the serial port data input and output. These lines are driven at the falling edge of **SPC** and should be captured at the rising edge of **SPC** . 

Both the read register and write register commands are completed in 16 clock pulses or in multiples of 8 in the case of multiple read/write bytes. Bit duration is the time between two falling edges of **SPC** . The first bit (bit 0) starts at the first falling edge of **SPC** after the falling edge of **CS** while the last bit (bit 15, bit 23,...) starts at the last falling edge of SPC just before the rising edge of **CS** . 

_**bit 0**_ : RW bit. When 0, the data DI(7:0) is written into the device. When 1, the data DO(7:0) from the device is read. In latter case, the chip drives **SDO** at the start of bit 8. 

_**bit 1**_ : MS bit. When 0, the address remains unchanged in multiple read/write commands. When 1, the address is auto incremented in multiple read/write commands. 

_**bit 2-7**_ : address AD(5:0). This is the address field of the indexed register. 

_**bit 8-15**_ : data DI(7:0) (Write mode). This is the data that is written into the device (MSB first). 

_**bit 8-15**_ : data DO(7:0) (Read mode). This is the data that is read from the device (MSB first). 

In multiple read/write commands further blocks of 8 clock periods are added. When the the MS bit is ‘0’, the address used to read/write data remains the same for every block. When the MS bit is ‘1’, the address used to read/write data is increased at every block. 

The function and the behavior of **SDI** and **SDO** remain unchanged. 

## **6.2.1 SPI read** 

**Figure 7. SPI read protocol** 

**==> picture [404 x 111] intentionally omitted <==**

**----- Start of picture text -----**<br>
CS<br>SPC<br>SDI<br>RW<br>MS AD5 AD4 AD3 AD2 AD1 AD0<br>SDO<br>DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0<br>**----- End of picture text -----**<br>


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The SPI read command is performed with 16 clock pulses. The multiple byte read command is performed by adding blocks of 8 clock pulses to the previous one. 

_**bit 0**_ : READ bit. The value is 1. 

_**bit 1**_ : MS bit. When 0, does not increment the address; when 1, increments the address in multiple reads. 

_**bit 2-7**_ : address AD(5:0). This is the address field of the indexed register. 

_**bit 8-15**_ : data DO(7:0) (Read mode). This is the data that is read from the device (MSB first). 

_**bit 16-...**_ : data DO(...-8). Further data in a multiple byte read. 

**Figure 8. Multiple byte SPI read protocol (2-byte example)** 

**==> picture [404 x 137] intentionally omitted <==**

**----- Start of picture text -----**<br>
CS<br>SPC<br>SDI<br>RW<br>MS AD5 AD4 AD3 AD2 AD1 AD0<br>SDO<br>DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 DO15 DO14 DO13 DO12 DO11 DO10 DO9 DO8<br>**----- End of picture text -----**<br>


## **6.2.2 SPI write** 

**Figure 9. SPI write protocol** 

**==> picture [404 x 111] intentionally omitted <==**

**----- Start of picture text -----**<br>
CS<br>SPC<br>SDI<br>RW DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0<br>MS AD5 AD4 AD3 AD2 AD1 AD0<br>**----- End of picture text -----**<br>


The SPI write command is performed with 16 clock pulses. The multiple bytes write command is performed by adding blocks of 8 clock pulses to the previous one. 

_**bit 0**_ : WRITE bit. The value is 0. 

_**bit 1**_ : MS bit. When 0, does not increment the address; when 1, increments the address in multiple writes. 

_**bit 2 -7**_ : address AD(5:0). This is the address field of the indexed register. 

_**bit 8-15**_ : data DI(7:0) (Write mode). This is the data that is written inside the device (MSB first). 

_**bit 16-...**_ : data DI(...-8). Further data in multiple byte writes. 

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**Figure 10. Multiple byte SPI write protocol (2-byte example)** 

**==> picture [404 x 125] intentionally omitted <==**

**----- Start of picture text -----**<br>
CS<br>SPC<br>SDI<br>DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 DI15 DI14 DI13 DI12 DI11 DI10 DI9 DI8<br>RW<br>MS AD5 AD4 AD3 AD2 AD1 AD0<br>**----- End of picture text -----**<br>


## **6.2.3 SPI read in 3-wire mode** 

3-wire mode is entered by setting the SIM (SPI serial interface mode selection) bit to ‘1’ in CTRL_REG4. 

**Figure 11. SPI read protocol in 3-wire mode** 

**==> picture [404 x 104] intentionally omitted <==**

**----- Start of picture text -----**<br>
CS<br>SPC<br>SDI/O<br>RW DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0<br>MS AD5 AD4 AD3 AD2 AD1 AD0<br>**----- End of picture text -----**<br>


The SPI read command is performed with 16 clock pulses: 

_**bit 0**_ : READ bit. The value is 1. 

_**bit 1**_ : MS bit. When 0, does not increment the address; when 1, increments the address in multiple reads. 

_**bit 2-7**_ : address AD(5:0). This is the address field of the indexed register. 

_**bit 8-15**_ : data DO(7:0) (Read mode). This is the data that is read from the device (MSB first). 

The multiple read command is also available in 3-wire mode. 

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**Register mapping** 

## **7 Register mapping** 

_Table 17_ provides a list of the 8-bit registers embedded in the device and the corresponding addresses. 

**Table 17. Register address map** 

|**Name**|**Type**|**Register address**|**Register address**|**Default**|**Comment**|
|---|---|---|---|---|---|
|||**Hex**|**Binary**|||
|Reserved (do not modify)||00 - 06|||Reserved|
|STATUS_REG_AUX|r|07|000 0111|||
|Reserved|r|08-0B||Output|Reserved|
|OUT_TEMP_L|r|0C|000 1100|Output||
|OUT_TEMP_H|r|0D|000 1101|Output||
|INT_COUNTER_REG|r|0E|000 1110|||
|WHO_AM_I|r|0F|000 1111|00110011|Dummy register|
|Reserved (do not modify)||10 - 1E|||Reserved|
|TEMP_CFG_REG|rw|1F|001 1111|||
|CTRL_REG1|rw|20|010 0000|00000111||
|CTRL_REG2|rw|21|010 0001|00000000||
|CTRL_REG3|rw|22|010 0010|00000000||
|CTRL_REG4|rw|23|010 0011|00000000||
|CTRL_REG5|rw|24|010 0100|00000000||
|CTRL_REG6|rw|25|010 0101|00000000||
|REFERENCE|rw|26|010 0110|00000000||
|STATUS_REG2|r|27|010 0111|00000000||
|Reserved (do not modify)|-|28|010 1000|00000000|Reserved|
|OUT_X|r|29|010 1001|Output||
|Reserved (do not modify)|-|2A|010 1010|00000000|Reserved|
|OUT_Y|r|2B|010 1011|Output||
|Reserved (do not modify)|r|2C|010 1100|00000000|Reserved|
|OUT_Z|r|2D|010 1101|Output||
|FIFO_CTRL_REG|rw|2E|010 1110|00000000||
|FIFO_SRC_REG|r|2F|010 1111|||
|IG1_CFG|rw|30|011 0000|00000000||
|IG1_SOURCE|r|31|011 0001|00000000||
|IG1_THS|rw|32|011 0010|00000000||
|IG1_DURATION|rw|33|011 0011|00000000||



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**Register mapping** 

**Table 17. Register address map (continued)** 

|**Name**|**Type**|**Register address**|**Register address**|**Default**|**Comment**|
|---|---|---|---|---|---|
|||**Hex**|**Binary**|||
|IG2_CFG|rw|34|011 0100|00000000||
|IG2_SOURCE|r|35|011 0101|00000000||
|IG2_THS|rw|36|011 0110|00000000||
|IG2_DURATION|rw|37|011 0111|00000000||
|CLICK_CFG|rw|38|011 1000|00000000||
|CLICK_SRC|r|39|011 1001|00000000||
|CLICK_THS|rw|3A|011 1010|00000000||
|TIME_LIMIT|rw|3B|011 1011|00000000||
|TIME_LATENCY|rw|3C|011 1100|00000000||
|TIME_WINDOW|rw|3D|011 1101|00000000||
|Act_THS|rw|3E|011 1110|00000000||
|Act_DUR|rw|3F|011 1111|00000000||



Registers marked as _Reserved_ must not be changed. Writing to those registers may cause permanent damage to the device. 

The content of the registers that are loaded at boot should not be changed. They contain the factory calibration values. Their content is automatically restored when the device is powered up. 

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**Register description** 

## **8 Register description** 

## **8.1 STATUS_REG_AUX (07h)** 

## **Table 18. STATUS_REG_AUX register** 

|--|TOR|TOR|--|--|--|TDA|--|--|
|---|---|---|---|---|---|---|---|---|
|**Table 19. STATUS_REG_AUX register description**|||||||||
|TOR||Temperature data overrun. Default value: 0<br>(0: no overrun has occurred;<br>1: new temperature data has overwritten the previous data)|||||||
|TDA||Temperature new data available. Default value: 0<br>(0: new temperature data is not yet available;<br>1: new temperature data is available)|||||||



## **8.2 OUT_TEMP_L (0Ch), OUT_TEMP_H (0Dh)** 

Temperature sensor data. Refer to _Section 2.2: Temperature sensor characteristics_ for details on how to enable and read the temperature sensor output data. 

## **8.3 INT_COUNTER_REG (0Eh)** 

**Table 20. INT_COUNTER_REG register** 

IC7 IC6 IC5 IC4 IC3 IC2 IC1 IC0 

INT2 pin counter. This register can be reset by reading the _REFERENCE (26h)_ register. 

## **8.4** 

## **WHO_AM_I (0Fh)** 

## **Table 21. WHO_AM_I register** 

0 0 1 1 0 0 1 1 

Device identification register. 

## **8.5 TEMP_CFG_REG (1Fh)** 

## **Table 22. TEMP_CFG_REG register** 

|TEMP_EN1|TEMP_EN0|TEMP_EN0|0|0|0|0|0|0|
|---|---|---|---|---|---|---|---|---|
|**Table 23. TEMP_CFG_REG register description**|||||||||
|TEMP_EN [1:0]||Temperature sensor (T) enable. Default value: 00<br>(00: T disabled; 11: T enabled)|||||||



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## **8.6 CTRL_REG1 (20h)** 

**Table 24. CTRL_REG1 register** 

|ODR3|ODR2|ODR2|ODR1|ODR0|LPen|Zen|Yen|Xen|
|---|---|---|---|---|---|---|---|---|
|**Table 25. CTRL_REG1 register description**|||||||||
|ODR [3:0]||Data rate selection. Default value: 0000<br>(0000: Power-down mode; Others: Refer to_Table 26_)|||||||
|LPen||Low-power mode enable. Default value: 0<br>(0: Normal mode, 1: Low-power mode)|||||||
|Zen||Z-axis enable. Default value: 1<br>(0: Z-axis disabled; 1: Z-axis enabled)|||||||
|Yen||Y-axis enable. Default value: 1<br>(0: Y-axis disabled; 1: Y-axis enabled)|||||||
|Xen||X-axis enable. Default value: 1<br>(0: X-axis disabled; 1: X-axis enabled)|||||||



**ODR [3:0]** is used to set power mode and ODR selection. The following table provides all frequencies resulting from a combination of ODR [3:0]. 

**Table 26. Data rate configuration** 

|**ODR3**|**ODR2**|**ODR1**|**ODR0**|**Power mode selection**|
|---|---|---|---|---|
|0|0|0|0|Power-down mode|
|0|0|0|1|Normal / Low-power mode (1 Hz)|
|0|0|1|0|Normal / Low-power mode (10 Hz)|
|0|0|1|1|Normal / Low-power mode (25 Hz)|
|0|1|0|0|Normal / Low-power mode (50 Hz)|
|0|1|0|1|Normal / Low-power mode (100 Hz)|
|0|1|1|0|Normal / Low-power mode (200 Hz)|
|0|1|1|1|Normal / Low-power mode (400 Hz)|
|1|0|0|0|Low-power mode (1.6 KHz)|
|1|0|0|1|Normal (1.344 kHz) / Low-power mode (5.376 kHz)|



## **8.7 CTRL_REG2 (21h)** 

**Table 27. CTRL_REG2 register** 

HPM1 HPM0 HPCF2 HPCF1 FDS HPCLICK HPIS2 HPIS1 

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**Table 28. CTRL_REG2 register description** 

||**Table 28. CTRL_REG2 register description**|
|---|---|
|HPM [1:0]|High pass filter mode selection. Default value: 00<br>Refer to_Table 29_|
|HPCF [2:1]|High-pass filter cutoff frequency selection|
|FDS|Filtered data selection. Default value: 0<br>(0: internal filter bypassed; data from internal filter sent to output register and FIFO)|
|HPCLICK|High-pass filter enabled for CLICK function.<br>(0: filter bypassed; 1: filter enabled)|
|HPIS2|High-pass filter enabled for IG2<br>(0: filter bypassed; 1: filter enabled)|
|HPIS1|High-pass filter enabled for IG1<br>(0: filter bypassed; 1: filter enabled)|



**Table 29. High-pass filter mode configuration** 

|**HPM1**|**HPM0**|**High pass filter mode**|
|---|---|---|
|0|0|Normal mode (reset by reading the_REFERENCE (26h)_register)|
|0|1|Reference signal for filtering|
|1|0|Normal mode|
|1|1|Auto-reset on interrupt event|



## **8.8 CTRL_REG3 (22h)** 

**Table 30. CTRL_REG3 register** 

|INT1_<br>CLICK|INT1_ IG1|INT1_IG2|INT1_<br>DRDY1|INT1_<br>DRDY2|INT1_<br>WTM|INT1_<br>OVERRUN|--|
|---|---|---|---|---|---|---|---|



**Table 31. CTRL_REG3 register description** 

|INT1_CLICK|CLICK interrupt on INT1. Default value 0<br>(0: disable; 1: enable)|
|---|---|
|INT1_IG1|IG1 interrupt generator 1 on INT1. Default value 0<br>(0: disable; 1: enable)|
|INT1_IG2|IG2 interrupt generator 2 on INT1. Default value 0<br>(0: disable; 1: enable)|
|INT1_DRDY1|DRDY1 interrupt on INT1. Default value 0<br>(0: disable; 1: enable)|
|INT1_DRDY2|DRDY2 interrupt on INT1. Default value 0<br>(0: disable; 1: enable)|
|INT1_WTM|FIFO watermark interrupt on INT1. Default value 0<br>(0: disable; 1: enable)|
|INT1_OVERRUN|FIFO overrun interrupt on INT1. Default value 0<br>(0: disable; 1: enable)|



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## **8.9 CTRL_REG4 (23h)** 

|**CTRL_REG4 (23h)**|**CTRL_REG4 (23h)**|**CTRL_REG4 (23h)**|**CTRL_REG4 (23h)**|**CTRL_REG4 (23h)**|**CTRL_REG4 (23h)**|**CTRL_REG4 (23h)**|**CTRL_REG4 (23h)**|**CTRL_REG4 (23h)**|
|---|---|---|---|---|---|---|---|---|
|**Table 32. CTRL_REG4 register**|||||||||
|BDU|-||FS1|FS0|-|ST1|ST0|SIM|
|**Table 33. CTRL_REG4 register description**<br>BDU<br>Block data update. Default value: 0<br>(0: continuous update. For linear acceleration data output this bit must be set to 0;<br>1: this bit must be set to 1 for temperature sensor reading only)<br>FS [1:0]<br>Full-scale selection. Default value: 00<br>(00: ±2_g_; 01: ±4_g_; 10: ±8_g_; 11: ±16_g_)<br>ST [1:0]<br>Self-test enable. Default value: 00<br>(00: self-test disabled; Other: See_Table 34_)<br>SIM<br>SPI serial interface mode selection. Default value: 0<br>(0: 4-wire interface; 1: 3-wire interface)|||||||||
|||Block data update. Default value: 0<br>(0: continuous update. For linear acceleration data output this bit must be set to 0;<br>1: this bit must be set to 1 for temperature sensor reading only)|||||||
|||Full-scale selection. Default value: 00<br>(00: ±2_g_; 01: ±4_g_; 10: ±8_g_; 11: ±16_g_)|||||||
|||Self-test enable. Default value: 00<br>(00: self-test disabled; Other: See_Table 34_)|||||||
|||SPI serial interface mode selection. Default value: 0<br>(0: 4-wire interface; 1: 3-wire interface)|||||||



**Table 34. Self-test mode configuration** 

|**ST1**|**ST0**|**Self-test mode**|
|---|---|---|
|0|0|Normal mode|
|0|1|Self-test 0|
|1|0|Self-test 1|
|1|1|--|



## **8.10 CTRL_REG5 (24h)** 

**Table 35. CTRL_REG5 register** 

|BOOT|FIFO_EN|FIFO_EN|--|--|LIR_IG1|D4D_IG1|LIR_IG2|D4D_IG2|
|---|---|---|---|---|---|---|---|---|
|**Table 36. CTRL_REG5 register description**|||||||||
|BOOT||Reboot memory content. Default value: 0<br>(0: Normal mode; 1: reboot memory content)|||||||
|FIFO_EN||FIFO enable. Default value: 0<br>(0: FIFO disable; 1: FIFO enable)|||||||
|LIR_IG1||Latch interrupt request on IG1_SOURCE register, with IG1_SOURCE<br>register cleared by reading IG1_SOURCE itself. Default value: 0<br>(0: interrupt request not latched; 1: interrupt request latched)|||||||
|D4D_IG1||4D enable: 4D detection is enabled on INT1 when 6D bit on IG1_CFG is set<br>to ‘1’|||||||
|LIR_IG2||Latch interrupt request on IG2_SOURCE register, with IG2_SOURCE<br>register cleared by reading IG2_SOURCE itself. Default value: 0<br>(0: interrupt request not latched; 1: interrupt request latched)|||||||
|D4D_IG2||4D enable: 4D detection is enabled on Interrupt 2 generator when 6D bit on<br>IG2_CFG is set to ‘1’|||||||



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## **8.11 CTRL_REG6 (25h)** 

**Table 37. CTRL_REG6 register** 

|INT2_CLICK|INT2_IG1|INT2_IG2|INT2_BOOT|INT2_ACT|-|H_LACTIVE|-|
|---|---|---|---|---|---|---|---|



**Table 38. CTRL_REG6 register description** 

|INT2_CLICK|Click interrupt on INT2 pin. Default value: 0<br>(0: disable; 1: enable)|
|---|---|
|INT2_IG1|Interrupt generator 1 enabled on INT2 pin. Default value: 0<br>(0: function disable; 1: function enable)|
|INT2_IG2|Interrupt generator 2 enabled on INT2 pin. Default value: 0<br>(0: function disable; 1: function enable)|
|INT2_BOOT|Boot on INT2 pin enable. Default value: 0<br>(0: disable; 1: enable)|
|INT2_ACT|“Sleep-to-wake” / “Return-to-sleep” function interrupt enable on INT2 pin. Default<br>value: 0<br>(0: disable; 1: enable)|
|H_LACTIVE|Interrupt active value. Default value: 0<br>(0: interrupt active high; 1: interrupt active low)|



## **8.12 REFERENCE (26h)** 

## **Table 39. REFERENCE register** 

|Ref7|Ref6|Ref6|Ref5|Ref4|Ref3|Ref2|Ref1|Ref0|
|---|---|---|---|---|---|---|---|---|
|**Table 40. REFERENCE register description**|||||||||
|Ref [7:0]||Reference value for interrupt generation. Default value: 0000 0000|||||||



## **8.13 STATUS_REG2 (27h)** 

## **Table 41. STATUS_REG2 register** 

|ZYXOR|ZOR|YOR|XOR|ZYXDA|ZDA|YDA|XDA|
|---|---|---|---|---|---|---|---|
|**Table 42. STATUS_REG2 register description**||||||||
|ZYXOR|X-, Y- and Z-axis data overrun. Default value: 0<br>(0: no overrun has occurred; 1: a new set of data has overwritten the previous set)|||||||
|ZOR|Z-axis data overrun. Default value: 0<br>(0: no overrun has occurred; 1: new data for the Z-axis has overwritten the previous data)|||||||



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## **Table 42. STATUS_REG2 register description (continued)** 

||**Table 42. STATUS_REG2 register description (continued)**|
|---|---|
|YOR|Y-axis data overrun. Default value: 0<br>(0: no overrun has occurred;<br>1: new data for the Y-axis has overwritten the previous data)|
|XOR|X-axis data overrun. Default value: 0<br>(0: no overrun has occurred;<br>1: new data for the X-axis has overwritten the previous data)|
|ZYXDA|X-, Y- and Z-axis new data available. Default value: 0<br>(0: a new set of data is not yet available; 1: a new set of data is available)|
|ZDA|Z-axis new data available. Default value: 0<br>(0: new data for the Z-axis is not yet available;<br>1: new data for the Z-axis is available)|
|YDA|Y-axis new data available. Default value: 0<br>(0: new data for the Y-axis is not yet available;<br>1: new data for the Y-axis is available)|
|XDA|X-axis new data available. Default value: 0<br>(0: new data for the X-axis is not yet available;<br>1: new data for the X-axis is available)|



## **8.14 OUT_X (29h)** 

X-axis acceleration data. The value is expressed in two’s complement with 8-bit data representation left-justified. 

## **8.15 OUT_Y (2Bh)** 

Y-axis acceleration data. The value is expressed in two’s complement with 8-bit data representation left-justified. 

## **8.16 OUT_Z (2Dh)** 

Z-axis acceleration data. The value is expressed in two’s complement with 8-bit data representation left-justified. 

## **8.17 FIFO_CTRL_REG (2Eh)** 

**Table 43. FIFO_CTRL_REG register** 

|FM1|FM0|FM0|TR|FTH4|FTH3|FTH2|FTH1|FTH0|
|---|---|---|---|---|---|---|---|---|
|**Table 44. FIFO_CTRL_REG register description**|||||||||
|FM [1:0]||FIFO mode selection. Default value: 00 (see_Table 45_)|||||||
|TR||Trigger selection. Default value: 0<br>0: trigger event linked to trigger signal on INT1<br>1: trigger event linked to trigger signal on INT2|||||||
|FTH [4:0]||Default value: 0|||||||



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**Table 45. FIFO mode configuration** 

|**FM1**|**FM0**|**Self test mode**|
|---|---|---|
|0|0|Bypass mode|
|0|1|FIFO mode|
|1|0|Stream mode|
|1|1|Stream-to-FIFO mode|



## **8.18 FIFO_SRC_REG (2Fh)** 

**Table 46. FIFO_SRC_REG register** 

|WTM|OVRN_FIFO|OVRN_FIFO|EMPTY|FSS4|FSS3|FSS2|FSS1|FSS0|
|---|---|---|---|---|---|---|---|---|
|**Table 47. FIFO_SRC_REG register description**|||||||||
|WTM||WTM bit is set high when FIFO content exceeds watermark level|||||||
|OVRN_FIFO||OVRN bit is set high when FIFO buffer is full which means that the FIFO buffer<br>contains 32 unread samples. At the following ODR a new sample set replaces the<br>oldest FIFO value. The OVRN bit is set to 0 when the first sample set has been read|||||||
|EMPTY||EMPTY flag is set high when all FIFO samples have been read and FIFO is empty|||||||
|FSS [4:0]||FSS [4:0] field always contains the current number of unread samples stored in the<br>FIFO buffer. When FIFO is enabled, this value increases at ODR frequency until the<br>buffer is full, whereas, it decreases every time one sample set is retrieved from FIFO|||||||



## **8.19 IG1_CFG (30h)** 

## **Table 48. IG1_CFG register** 

|AOI|6D|ZHIE/<br>ZUPE|ZLIE/<br>ZDOWNE|YHIE/<br>YUPE|YLIE/<br>YDOWNE|XHIE/<br>XUPE|XLIE/<br>XDOWNE|
|---|---|---|---|---|---|---|---|



## **Table 49. IG1_CFG register description** 

|AOI|AND/OR combination of interrupt events. Default value: 0 (Refer to_������_<br>_��_)|
|---|---|
|6D|6-direction detection function enabled. Default value: 0 (Refer to_������_<br>_��_)|
|ZHIE/<br>ZUPE|Enable interrupt generation on Z high event or on direction recognition.<br>Default value: 0 (0: disable interrupt request; 1: enable interrupt request)|
|ZLIE/<br>ZDOWNE|Enable interrupt generation on Z low event or on direction recognition.<br>Default value: 0 (0: disable interrupt request; 1: enable interrupt request)|
|YHIE/<br>YUPE|Enable interrupt generation on Y high event or on direction recognition.<br>Default value: 0 (0: disable interrupt request; 1: enable interrupt request)|
|YLIE/<br>YDOWNE|Enable interrupt generation on Y low event or on direction recognition.<br>Default value: 0 (0: disable interrupt request; 1: enable interrupt request)|
|XHIE/<br>XUPE|Enable interrupt generation on X high event or on direction recognition. Default<br>value: 0 (0: disable interrupt request; 1: enable interrupt request)|
|XLIE/<br>XDOWNE|Enable interrupt generation on X low event or on direction recognition. Default<br>value: 0 (0: disable interrupt request; 1: enable interrupt request)|



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**Register description** 

The content of this register is loaded at boot. 

A write operation to this address is possible only after system boot. 

**Table 50. Interrupt mode** 

|||**Table 50. Interrupt mode**|
|---|---|---|
|**AOI**|**6D**|**Interrupt mode**|
|0|0|OR combination of interrupt events|
|0|1|6-direction movement recognition|
|1|0|AND combination of interrupt events|
|1|1|6-direction position recognition|



The difference between AOI-6D = ‘01’ and AOI-6D = ‘11’. 

AOI-6D = ‘01’ is movement recognition. An interrupt is generated when the orientation moves from an unknown zone to a known zone. The interrupt signal remains for a duration ODR. 

AOI-6D = ‘11’ is direction recognition. An interrupt is generated when the orientation is inside a known zone. The interrupt signal remains until the orientation is within the zone. 

## **8.20 IG1_SOURCE (31h)** 

**Table 51. IG1_SOURCE register** 

|0|0|IA|ZH|ZL|YH|YL|XH|XL|
|---|---|---|---|---|---|---|---|---|
|**Table 52. IG1_SOURCE register description**|||||||||
|IA|Interrupt active. Default value: 0<br>(0: no interrupt has been generated; 1: one or more interrupts have been generated)||||||||
|ZH|Z high. Default value: 0<br>(0: no interrupt, 1: Z high event has occurred)||||||||
|ZL|Z low. Default value: 0<br>(0: no interrupt; 1: Z low event has occurred)||||||||
|YH|Y high. Default value: 0<br>(0: no interrupt, 1: Y high event has occurred)||||||||
|YL|Y low. Default value: 0<br>(0: no interrupt, 1: Y low event has occurred)||||||||
|XH|X high. Default value: 0<br>(0: no interrupt, 1: X high event has occurred)||||||||
|XL|X low. Default value: 0<br>(0: no interrupt, 1: X low event has occurred)||||||||



Interrupt 1 source register. Read-only register. 

Reading at this address clears the IG1_SOURCE IA bit (and the interrupt signal on the INT1 pin) and allows data in the IG1_SOURCE register to be refreshed if the latched option was chosen. 

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## **8.21 IG1_THS (32h)** 

## **Table 53. IG1_THS register** 

|0|THS6|THS6|THS5|THS4|THS3|THS2|THS1|THS0|
|---|---|---|---|---|---|---|---|---|
|**Table 54. IG1_THS register description**|||||||||
|THS [6:0]||Interrupt 1 threshold. Default value: 000 0000|||||||



## **8.22 IG1_DURATION (33h)** 

## **Table 55. IG1_DURATION register** 

|0|D6|D6|D5|D4|D3|D2|D1|D0|
|---|---|---|---|---|---|---|---|---|
|**Table 56. IG1_DURATION register description**|||||||||
|D [6:0]||Duration value. Default value: 000 0000|||||||



The D[6:0] bits set the minimum duration of the interrupt 1 event to be recognized. Duration steps and maximum values depend on the ODR chosen. 

## **8.23 IG2_CFG (34h)** 

**Table 57. IG2_CFG register** 

|AOI|6D|6D|ZHIE|ZLIE|YHIE|YLIE|XHIE|XLIE|
|---|---|---|---|---|---|---|---|---|
|**Table 58. IG2_CFG register description**|||||||||
|AOI||AND/OR combination of interrupt events. Default value: 0<br>(Refer to_Table 59: Interrupt mode_)|||||||
|6D||6-direction detection function enabled. Default value: 0<br>(Refer to_Table 59: Interrupt mode)_|||||||
|ZHIE||Enable interrupt generation on Z high event. Default value: 0<br>(0: disable interrupt request;<br>1: enable interrupt request on measured accel. value higher than preset threshold)|||||||
|ZLIE||Enable interrupt generation on Z low event. Default value: 03<br>(0: disable interrupt request;<br>1: enable interrupt request on measured accel. value lower than preset threshold)|||||||
|YHIE||Enable interrupt generation on Y high event. Default value: 0<br>(0: disable interrupt request;<br>1: enable interrupt request on measured accel. value higher than preset threshold)|||||||
|YLIE||Enable interrupt generation on Y low event. Default value: 0<br>(0: disable interrupt request;<br>1: enable interrupt request on measured accel. value lower than preset threshold)|||||||
|XHIE||Enable interrupt generation on X high event. Default value: 0<br>(0: disable interrupt request;<br>1: enable interrupt request on measured accel. value higher than preset threshold)|||||||
|XLIE||Enable interrupt generation on X low event. Default value: 0<br>(0: disable interrupt request;<br>1: enable interrupt request on measured accel. value lower than preset threshold)|||||||



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**Register description** 

The content of this register is loaded at boot. 

A write operation to this address is possible only after system boot. 

**Table 59. Interrupt mode** 

|||**Table 59. Interrupt mode**|
|---|---|---|
|**AOI**|**6D**|**Interrupt mode**|
|0|0|OR combination of interrupt events|
|0|1|6-direction movement recognition|
|1|0|AND combination of interrupt events|
|1|1|6-direction position recognition|



The difference between AOI-6D = ‘01’ and AOI-6D = ‘11’. 

AOI-6D = ‘01’ is movement recognition. An interrupt is generated when the orientation moves from an unknown zone to a known zone. The interrupt signal remains for a duration ODR. 

AOI-6D = ‘11’ is direction recognition. An interrupt is generated when the orientation is within a known zone. The interrupt signal remains while the orientation is within this zone. 

## **8.24 IG2_SOURCE (35h)** 

**Table 60. IG2_SOURCE register** 

|0|0|IA|ZH|ZL|YH|YL|XH|XL|
|---|---|---|---|---|---|---|---|---|
|**Table 61. IG2_SOURCE register description**|||||||||
|IA|Interrupt active. Default value: 0<br>(0: no interrupt has been generated; 1: one or more interrupts have been generated)||||||||
|ZH|Z high. Default value: 0<br>(0: no interrupt, 1: Z high event has occurred)||||||||
|ZL|Z low. Default value: 0<br>(0: no interrupt; 1: Z low event has occurred)||||||||
|YH|Y high. Default value: 0<br>(0: no interrupt, 1: Y high event has occurred)||||||||
|YL|Y low. Default value: 0<br>(0: no interrupt, 1: Y low event has occurred)||||||||
|XH|X high. Default value: 0<br>(0: no interrupt, 1: X high event has occurred)||||||||
|XL|X low. Default value: 0<br>(0: no interrupt, 1: X low event has occurred)||||||||



Interrupt 2 source register. Read-only register. 

Reading at this address clears the IG2_SOURCE IA bit (and the interrupt signal on the INT2 pin) and allows data in the IG2_SOURCE register to be refreshed if the latched option was chosen. 

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## **8.25 IG2_THS (36h)** 

|**IG2_THS (36h)**|**IG2_THS (36h)**|**IG2_THS (36h)**|**IG2_THS (36h)**|**IG2_THS (36h)**|**IG2_THS (36h)**|**IG2_THS (36h)**|**IG2_THS (36h)**|**IG2_THS (36h)**|
|---|---|---|---|---|---|---|---|---|
|**Table 62. IG2_THS register**|||||||||
|0|THS6||THS5|THS4|THS3|THS2|THS1|THS0|
|**Table 63. IG2_THS register description**|||||||||
|THS [6:0]||Interrupt 1 threshold. Default value: 000 0000|||||||



## **8.26 IG2_DURATION (37h)** 

**Table 64. IG2_DURATION register** 

|0|D6|D6|D5|D4|D3|D2|D1|D0|
|---|---|---|---|---|---|---|---|---|
|**Table 65. IG2_DURATION register description**|||||||||
|D [6:0]||Duration value. Default value: 000 0000|||||||



The **D [6:0]** bits set the minimum duration of the Interrupt 2 event to be recognized. Duration time steps and maximum values depend on the ODR chosen. 

## **8.27 CLICK_CFG (38h)** 

**Table 66. CLICK_CFG register** 

|--|--|--|ZD|ZS|YD|YS|XD|XS|
|---|---|---|---|---|---|---|---|---|
|**Table 67. CLICK_CFG register description**|||||||||
|ZD||Enable interrupt double click on Z-axis. Default value: 0<br>(0: disable interrupt request; 1: enable interrupt request on measured accel. value<br>higher than preset threshold)|||||||
|ZS||Enable interrupt single click on Z-axis. Default value: 0<br>(0: disable interrupt request; 1: enable interrupt request on measured accel. value<br>higher than preset threshold)|||||||
|YD||Enable interrupt double click on Y-axis. Default value: 0<br>(0: disable interrupt request; 1: enable interrupt request on measured accel. value<br>higher than preset threshold)|||||||
|YS||Enable interrupt single click on Y-axis. Default value: 0<br>(0: disable interrupt request; 1: enable interrupt request on measured accel. value<br>higher than preset threshold)|||||||
|XD||Enable interrupt double click on X-axis. Default value: 0<br>(0: disable interrupt request; 1: enable interrupt request on measured accel. value<br>higher than preset threshold)|||||||
|XS||Enable interrupt single click on X-axis. Default value: 0<br>(0: disable interrupt request; 1: enable interrupt request on measured accel. value<br>higher than preset threshold)|||||||



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## **8.28 CLICK_SRC (39h)** 

**Table 68. CLICK_SRC register** 

|-|IA|DCLICK|SCLICK|Sign|Z|Y|X|
|---|---|---|---|---|---|---|---|
|**Table 69. CLICK_SRC register description**||||||||
|IA|Interrupt active. Default value: 0<br>(0: no interrupt has been generated; 1: one or more interrupts have been generated)|||||||
|DCLICK|Double-click enable. Default value: 0 (0: double-click detection disable, 1: double-click<br>detection enable)|||||||
|SCLICK|Single-click enable. Default value: 0 (0: single-click detection disable, 1: single-click<br>detection enable)|||||||
|Sign|Click sign. 0: positive detection, 1: negative detection|||||||
|Z|Z click detection. Default value: 0<br>(0: no interrupt, 1: Z high event has occurred)|||||||
|Y|Y click detection. Default value: 0<br>(0: no interrupt, 1: Y high event has occurred)|||||||
|X|X click detection. Default value: 0<br>(0: no interrupt, 1: X high event has occurred)|||||||



## **8.29 CLICK_THS (3Ah)** 

**Table 70. CLICK_THS register** 

|LIR|THS6|THS6|THS5|THS4|THS3|THS2|THS1|THS0|
|---|---|---|---|---|---|---|---|---|
|**Table 71. CLICK_THS register description**|||||||||
|LIR||Latch interrupt request on CLICK_SRC register, with CLICK_SRC register cleared<br>by reading CLICK_SRC itself. Default value: 0<br>(0: interrupt request not latched; 1: interrupt request latched)|||||||
|THS [6:0]||Click threshold. Default value: 000 0000|||||||



## **8.30 TIME_LIMIT (3Bh)** 

**Table 72. TIME_LIMIT register** 

- TLI6 TLI5 TLI4 TLI3 TLI2 TLI1 TLI0 

## **Table 73. TIME_LIMIT register description** 

TLI [6:0] Click time limit. Default value: 000 0000 

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**Register description** 

## **8.31 TIME_LATENCY (3Ch)** 

**Table 74. TIME_LATENCY register** 

|TLA7|TLA6|TLA6|TLA5|TLA4|TLA3|TLA2|TLA1|TLA0|
|---|---|---|---|---|---|---|---|---|
|**Table 75. TIME_LATENCY register description**|||||||||
|TLA [7:0]||Double-click time latency. Default value: 0000 0000|||||||



## **8.32 TIME_WINDOW (3Dh)** 

**Table 76. TIME_WINDOW register** 

|TW7|TW6|TW6|TW5|TW4|TW3|TW2|TW1|TW0|
|---|---|---|---|---|---|---|---|---|
|**Table 77. TIME_WINDOW register description**|||||||||
|TW [7:0]||Double-click time window. Default value: 0000 0000|||||||



## **8.33 Act_THS (3Eh)** 

**Table 78. Act_THS register** 

-- Acth6 Acth5 Acth4 Acth3 Acth2 Acth1 Acth0 

## **Table 79. Act_THS register description** 

|Acth [6:0]|Sleep-to-wake, Return-to-sleep activation threshold<br>1LSB = 16 m_g_@ 2_g_FS|
|---|---|



## **8.34 Act_DUR (3Fh)** 

## **Table 80. Act_DUR register** 

ActD7 ActD6 ActD5 ActD4 ActD3 ActD2 ActD1 ActD0 

## **Table 81. Act_DUR register description** 

|ActD [7:0]|Sleep-to-wake, Return-to-sleep duration<br>DUR = (Act_DUR + 1)*8/ODR|
|---|---|



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**LIS2DE** 

## **9 Package information** 

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: _www.st.com_ . ECOPACK is an ST trademark. 

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**Table 82. LGA-14 2x2x1 mechanical dimensions** 

|**Dim.**|**Min.**|**Typ.**|**Max.**|
|---|---|---|---|
|A1|||1|
|A2||0.785||
|A3||0.200||
|D1|1.850|2.000|2.150|
|E1|1.850|2.000|2.150|
|L1||0.900||
|L2||1.250||
|N1||0.350||
|T1||0.275||
|T2||0.200||
|P1||0.850||
|P2||0.850||
|d||0.150||
|M||0.100||
|K||0.050||



**Figure 12. LGA-14 2x2x1 mechanical drawing** 

**==> picture [405 x 183] intentionally omitted <==**

**----- Start of picture text -----**<br>
8224765_A<br>**----- End of picture text -----**<br>


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## **10 Revision history** 

**Table 83. Document revision history** 

|**Date**|**Revision**|**Changes**|
|---|---|---|
|26-Sep-2012|1|Initial release.|
|19-Jun-2014|2|Document status promoted to production data<br>Updated Trigger mode to Stream-to-FIFO mode<br>Minor textual modifications throughout datasheet|



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