LIFCL-40-8BG256I
FPGA, CrossLink-NX, DLL, PLL, 39000 Macrocells, 950 mV to 1.05 V, CABGA-256
- Manufacturer: LATTICE SEMICONDUCTOR
- Product type: FPGAs
- MSL: MSL 3 - 168 hours
- SVHC: No SVHC (25-Jun-2025)
- FPGA Type: SRAM based FPGA
- FPGA Family: CrossLink-NX
- IC Mounting: Surface Mount
- No. of Pins: 256Pins
- Speed Grade: 8
- Product Range: -
- Qualification: -
- Total RAM Bits: 240Kbit
- No.of User I/Os: -
- Clock Management: DLL, PLL
- Logic Case Style: CABGA
- IC Case / Package: CABGA
- No. of Macrocells: 39000Macrocells
- I/O Supply Voltage: 3.3V
- No. of Logic Cells: 39000Logic Cells
- Process Technology: 28nm
- No. of Logic Blocks: 39000
- No. of Speed Grades: 8
- Core Supply Voltage Max: 1.05V
- Core Supply Voltage Min: 950mV
- Operating Frequency Max: 325.2MHz
- Operating Temperature Max: 100°C
- Operating Temperature Min: -40°C
| Delivery and price | |
|---|---|
| Units per pack | 25 |
| Price | 50.01 € |
| Current stock | 10+ |
| Lead time | 30 days |
## Os
## **CrossLink-NX Family**
## **Data Sheet**
FPGA-DS-02049-1.8
March 2023
**CrossLink-NX Family Data Sheet**
## **Disclaimers**
Lattice makes no warranty, representation, or guarantee regarding the accuracy of information contained in this document or the suitability of its products for any particular purpose. All information herein is provided AS IS, with all faults and associated risk the responsibility entirely of the Buyer. Buyer shall not rely on any data and performance specifications or parameters provided herein. Products sold by Lattice have been subject to limited testing and it is the Buyer's responsibility to independently determine the suitability of any products and to test and verify the same. No Lattice products should be used in conjunction with mission- or safety-critical or any other application in which the failure of Lattice’s product could create a situation where personal injury, death, severe property or environmental damage may occur. The information provided in this document is proprietary to Lattice Semiconductor, and Lattice reserves the right to make any changes to the information in this document or to any products at any time without notice.
© 2021-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
2
FPGA-DS-02049-1.8
**CrossLink-NX Family Data Sheet**
## **Contents**
|Acronyms in This Document ............................................................................................................................................... 11|Acronyms in This Document ............................................................................................................................................... 11|Acronyms in This Document ............................................................................................................................................... 11|
|---|---|---|
|1.|General Description .................................................................................................................................................... 13||
||1.1.|Features ............................................................................................................................................................ 13|
|2.|Architecture ................................................................................................................................................................ 17||
||2.1.|Overview ........................................................................................................................................................... 17|
||2.2.|PFU Blocks ......................................................................................................................................................... 19|
||2.2.1.|Slice ............................................................................................................................................................... 19|
||2.2.2.|Modes of Operation ...................................................................................................................................... 22|
||2.3.|Routing .............................................................................................................................................................. 23|
||2.4.|Clocking Structure ............................................................................................................................................. 23|
||2.4.1.|Global PLL ..................................................................................................................................................... 23|
||2.4.2.|Clock Distribution Network ........................................................................................................................... 24|
||2.4.3.|Primary Clocks .............................................................................................................................................. 25|
||2.4.4.|Edge Clock ..................................................................................................................................................... 26|
||2.4.5.|Clock Dividers ................................................................................................................................................ 26|
||2.4.6.|Clock Center Multiplexer Blocks ................................................................................................................... 27|
||2.4.7.|Dynamic Clock Select .................................................................................................................................... 27|
||2.4.8.|Dynamic Clock Control .................................................................................................................................. 28|
||2.4.9.|DDRDLL ......................................................................................................................................................... 28|
||2.5.|SGMII Tx/Rx ....................................................................................................................................................... 29|
||2.6.|sysMEM Memory .............................................................................................................................................. 30|
||2.6.1.|sysMEM Memory Block ................................................................................................................................ 30|
||2.6.2.|Bus Size Matching ......................................................................................................................................... 31|
||2.6.3.|RAM Initialization and ROM Operation ........................................................................................................ 31|
||2.6.4.|Memory Cascading ....................................................................................................................................... 31|
||2.6.5.|Single, Dual and Pseudo-Dual Port Modes ................................................................................................... 31|
||2.6.6.|Memory Output Reset .................................................................................................................................. 31|
||2.7.|Large RAM ......................................................................................................................................................... 32|
||2.8.|sysDSP ............................................................................................................................................................... 32|
||2.8.1.|sysDSP Approach Compared to General DSP ................................................................................................ 32|
||2.8.2.|sysDSP Architecture Features ....................................................................................................................... 33|
||2.9.|Programmable I/O (PIO) .................................................................................................................................... 35|
||2.10.|Programmable I/O Cell (PIC) ............................................................................................................................. 35|
||2.10.1.<br>Input Register Block .................................................................................................................................. 37||
||2.10.2.<br>Output Register Block ............................................................................................................................... 38||
||2.11.|Tri-state Register Block ..................................................................................................................................... 39|
||2.12.|DDR Memory Support ....................................................................................................................................... 40|
||2.12.1.<br>DQS Grouping for DDR Memory ............................................................................................................... 40||
||2.12.2.<br>DLL Calibrated DQS Delay and Control Block (DQSBUF) ........................................................................... 41||
||2.13.|sysI/O Buffer...................................................................................................................................................... 43|
||2.13.1.<br>Supported sysI/O Standards ..................................................................................................................... 43||
||2.13.2.<br>sysI/O Banking Scheme ............................................................................................................................ 44||
||2.13.3.<br>sysI/O Buffer Configurations .................................................................................................................... 47||
||2.14.|Analog Interface ................................................................................................................................................ 47|
||2.14.1.<br>Analog to Digital Converters ..................................................................................................................... 47||
||2.14.2.<br>Continuous Time Comparators ................................................................................................................. 47||
||2.14.3.<br>Internal Junction Temperature Monitoring Diode ................................................................................... 47||
||2.15.|IEEE 1149.1-Compliant Boundary Scan Testability............................................................................................ 47|
||2.16.|Device Configuration ......................................................................................................................................... 48|
||2.16.1.<br>Enhanced Configuration Options ............................................................................................................. 48||
||2.17.|Single Event Upset (SEU) Handling .................................................................................................................... 49|
© 2021-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02049-1.8
3
**CrossLink-NX Family Data Sheet**
||2.18.|On-Chip Oscillator ............................................................................................................................................. 49|
|---|---|---|
||2.19.|User I²C IP .......................................................................................................................................................... 49|
||2.20.|Trace ID ............................................................................................................................................................. 50|
||2.21.|Density Shifting ................................................................................................................................................. 50|
||2.22.|MIPI D-PHY Blocks ............................................................................................................................................. 50|
||2.23.|Peripheral Component Interconnect Express (PCIe) ......................................................................................... 51|
||2.24.|Cryptographic Engine ........................................................................................................................................ 52|
|3.|DC and Switching Characteristics for Commercial and Industrial ............................................................................... 53|DC and Switching Characteristics for Commercial and Industrial ............................................................................... 53|
||3.1.|Absolute Maximum Ratings .............................................................................................................................. 53|
||3.2.|Recommended Operating Conditions1, 2, 3......................................................................................................... 54|
||3.3.|Power Supply Ramp Rates ................................................................................................................................. 55|
||3.4.|Power up Sequence ........................................................................................................................................... 55|
||3.5.|On-Chip Programmable Termination ................................................................................................................ 55|
||3.6.|Hot Socketing Specifications ............................................................................................................................. 56|
||3.7.|ESD Performance ............................................................................................................................................... 56|
||3.8.|DC Electrical Characteristics .............................................................................................................................. 57|
||3.9.|Supply Currents ................................................................................................................................................. 58|
||3.10.|sysI/O Recommended Operating Conditions .................................................................................................... 59|
||3.11.|sysI/O Single-Ended DC Electrical Characteristics ............................................................................................. 60|
||3.12.|sysI/O Differential DC Electrical Characteristics ................................................................................................ 62|
||3.12.1.<br>LVDS .......................................................................................................................................................... 62||
||3.12.2.<br>LVDS25E (Output Only) ............................................................................................................................. 63||
||3.12.3.<br>SubLVDS (Input Only)................................................................................................................................ 64||
||3.12.4.<br>SubLVDSE/SubLVDSEH (Output Only)....................................................................................................... 64||
||3.12.5.<br>SLVS .......................................................................................................................................................... 65||
||3.12.6.<br>Soft MIPI D-PHY ........................................................................................................................................ 66||
||3.12.7.<br>Differential HSTL15D (Output Only) ......................................................................................................... 70||
||3.12.8.<br>Differential SSTL135D, SSTL15D (Output Only) ........................................................................................ 70||
||3.12.9.<br>Differential HSUL12D (Output Only) ......................................................................................................... 70||
||3.12.10.<br>Differential LVCMOS25D, LVCMOS33D, LVTTL33D (Output Only) ........................................................... 70||
||3.13.|Maximum sysI/O Buffer Speed .......................................................................................................................... 70|
||3.14.|Typical Building Block Function Performance ................................................................................................... 72|
||3.15.|LMMI ................................................................................................................................................................. 73|
||3.16.|Derating Timing Tables ...................................................................................................................................... 74|
||3.17.|External Switching Characteristics .................................................................................................................... 74|
||3.18.|sysCLOCK PLL Timing (VCC= 1.0 V) – Commercial/Industrial ............................................................................. 83|
||3.19.|Internal Oscillators Characteristics .................................................................................................................... 84|
||3.20.|User I2C Characteristics ..................................................................................................................................... 84|
||3.21.|Analog-Digital Converter (ADC) Block Characteristics ....................................................................................... 85|
||3.22.|Comparator Block Characteristics ..................................................................................................................... 86|
||3.23.|Digital Temperature Readout Characteristics ................................................................................................... 86|
||3.24.|Hardened MIPI D-PHY Characteristics ............................................................................................................... 86|
||3.25.|Hardened PCIe Characteristics .......................................................................................................................... 90|
||3.25.1.<br>PCIe (2.5 Gbps) ......................................................................................................................................... 90||
||3.25.2.<br>PCIe (5 Gbps) ............................................................................................................................................ 91||
||3.26.|SGMII Characteristics ........................................................................................................................................ 93|
||3.26.1.<br>SGMII Specifications ................................................................................................................................. 93||
||3.27.|sysCONFIG Port Timing Specifications ............................................................................................................... 93|
||3.28.|JTAG Port Timing Specifications ........................................................................................................................ 99|
||3.29.|Switching Test Conditions ............................................................................................................................... 100|
|4.|DC and Switching Characteristics for Automotive .................................................................................................... 101|DC and Switching Characteristics for Automotive .................................................................................................... 101|
||4.1.|Absolute Maximum Ratings ............................................................................................................................ 101|
||4.2.|Recommended Operating Conditions1, 2, 3....................................................................................................... 102|
||4.3.|Power Supply Ramp Rates ............................................................................................................................... 103|
© 2021-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02049-1.8
4
**CrossLink-NX Family Data Sheet**
||4.4.<br>Power up Sequence......................................................................................................................................... 103|
|---|---|
||4.5.<br>On-Chip Programmable Termination .............................................................................................................. 103|
||4.6.<br>Hot Socketing Specifications ........................................................................................................................... 104|
||4.7.<br>ESD Performance ............................................................................................................................................ 104|
||4.8.<br>DC Electrical Characteristics ............................................................................................................................ 105|
||4.9.<br>Supply Currents ............................................................................................................................................... 106|
||4.10.<br>sysI/O Recommended Operating Conditions .................................................................................................. 107|
||4.11.<br>sysI/O Single-Ended DC Electrical Characteristics3.......................................................................................... 108|
||4.12.<br>sysI/O Differential DC Electrical Characteristics .............................................................................................. 110|
||4.12.1.<br>LVDS ........................................................................................................................................................ 110|
||4.12.2.<br>LVDS25E (Output Only) .......................................................................................................................... 111|
||4.12.3.<br>SubLVDS (Input Only) ............................................................................................................................. 112|
||4.12.4.<br>SubLVDSE/SubLVDSEH (Output Only) .................................................................................................... 112|
||4.12.5.<br>SLVS ........................................................................................................................................................ 113|
||4.12.6.<br>Soft MIPI D-PHY ...................................................................................................................................... 114|
||4.12.7.<br>Differential HSTL15D (Output Only) ....................................................................................................... 117|
||4.12.8.<br>Differential SSTL135D, SSTL15D (Output Only) ...................................................................................... 117|
||4.12.9.<br>Differential HSUL12D (Output Only) ...................................................................................................... 117|
||4.12.10.<br>Differential LVCMOS25D, LVCMOS33D, LVTTL33D (Output Only) ......................................................... 117|
||4.13.<br>Maximum sysI/O Buffer Speed ....................................................................................................................... 117|
||4.14.<br>Typical Building Block Function Performance ................................................................................................. 120|
||4.15.<br>LMMI ............................................................................................................................................................... 121|
||4.16.<br>Derating Timing Tables .................................................................................................................................... 121|
||4.17.<br>External Switching Characteristics .................................................................................................................. 122|
||4.18.<br>sysCLOCK PLL Timing (VCC= 1.0 V) – Automotive ............................................................................................ 130|
||4.19.<br>Internal Oscillators Characteristics.................................................................................................................. 131|
||4.20.<br>User I2C Characteristics ................................................................................................................................... 131|
||4.21.<br>Analog-Digital Converter (ADC) Block Characteristics ..................................................................................... 132|
||4.22.<br>Comparator Block Characteristics ................................................................................................................... 133|
||4.23.<br>Digital Temperature Readout Characteristics ................................................................................................. 133|
||4.24.<br>Hardened MIPI D-PHY Characteristics ............................................................................................................. 133|
||4.25.<br>Hardened PCIe Characteristics ........................................................................................................................ 137|
||4.25.1.<br>PCIe (2.5 Gbps) ....................................................................................................................................... 137|
||4.25.2.<br>PCIe (5 Gbps) .......................................................................................................................................... 138|
||4.26.<br>SGMII Characteristics ...................................................................................................................................... 140|
||4.26.1.<br>SGMII Specifications ............................................................................................................................... 140|
||4.27.<br>sysCONFIG Port Timing Specifications ............................................................................................................ 140|
||4.28.<br>JTAG Port Timing Specifications ...................................................................................................................... 146|
||4.29.<br>Switching Test Conditions ............................................................................................................................... 147|
|5.|Pinout Information ................................................................................................................................................... 148|
||5.1.<br>Signal Descriptions .......................................................................................................................................... 148|
||5.2.<br>Pin Information Summary ............................................................................................................................... 154|
||5.2.1.<br>CrossLink-NX Family .................................................................................................................................... 154|
|6.|Ordering Information ............................................................................................................................................... 157|
||6.1.<br>Part Number Description ................................................................................................................................ 157|
||6.2.<br>Ordering Part Numbers ................................................................................................................................... 158|
||6.2.1.<br>Commercial ................................................................................................................................................. 158|
||6.2.2.<br>Industrial ..................................................................................................................................................... 158|
||6.2.3.<br>Automotive ................................................................................................................................................. 159|
|Supplemental Information ............................................................................................................................................... 160||
||For Further Information ................................................................................................................................................ 160|
|Technical Support Assistance ........................................................................................................................................... 161||
|Revision History ................................................................................................................................................................ 162||
© 2021-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02049-1.8
5
**CrossLink-NX Family Data Sheet**
## **Figures**
|Figure 2.1. Simplified Block Diagram, CrossLink-NX-40 Device (Top Level) ........................................................................ 18|Figure 2.1. Simplified Block Diagram, CrossLink-NX-40 Device (Top Level) ........................................................................ 18|
|---|---|
|Figure 2.2. Simplified Block Diagram, CrossLink-NX-17 Device (Top Level) ........................................................................ 18|Figure 2.2. Simplified Block Diagram, CrossLink-NX-17 Device (Top Level) ........................................................................ 18|
|Figure 2.3. PFU Diagram ..................................................................................................................................................... 19|Figure 2.3. PFU Diagram ..................................................................................................................................................... 19|
|Figure 2.4. Slice Diagram .................................................................................................................................................... 20|Figure 2.4. Slice Diagram .................................................................................................................................................... 20|
|Figure 2.5. Slice Configuration for LUT4 and LUT5 ............................................................................................................. 21|Figure 2.5. Slice Configuration for LUT4 and LUT5 ............................................................................................................. 21|
|Figure 2.6. General Purpose PLL Diagram ........................................................................................................................... 24|Figure 2.6. General Purpose PLL Diagram ........................................................................................................................... 24|
|Figure 2.7. Clocking ............................................................................................................................................................. 25|Figure 2.7. Clocking ............................................................................................................................................................. 25|
|Figure 2.8. Edge Clock Sources per Bank ............................................................................................................................ 26|Figure 2.8. Edge Clock Sources per Bank ............................................................................................................................ 26|
|Figure 2.9. DCS_CMUX Diagram ......................................................................................................................................... 27|Figure 2.9. DCS_CMUX Diagram ......................................................................................................................................... 27|
|Figure 2.10. DCS Waveforms .............................................................................................................................................. 28|Figure 2.10. DCS Waveforms .............................................................................................................................................. 28|
|Figure 2.11. DLLDEL Functional Diagram ............................................................................................................................ 29|Figure 2.11. DLLDEL Functional Diagram ............................................................................................................................ 29|
|Figure 2.12. DDRDLL Architecture ...................................................................................................................................... 29|Figure 2.12. DDRDLL Architecture ...................................................................................................................................... 29|
|Figure 2.13. SGMII CDR IP ................................................................................................................................................... 30|Figure 2.13. SGMII CDR IP ................................................................................................................................................... 30|
|Figure 2.14. Memory Core Reset ........................................................................................................................................ 32|Figure 2.14. Memory Core Reset ........................................................................................................................................ 32|
|Figure 2.15. Comparison of General DSP and CrossLink-NX Approaches ........................................................................... 33|Figure 2.15. Comparison of General DSP and CrossLink-NX Approaches ........................................................................... 33|
|Figure 2.16. DSP Functional Block Diagram ........................................................................................................................ 34|Figure 2.16. DSP Functional Block Diagram ........................................................................................................................ 34|
|Figure 2.17. Group of Two High Performance Programmable I/O Cells ............................................................................. 36|Figure 2.17. Group of Two High Performance Programmable I/O Cells ............................................................................. 36|
|Figure 2.18. Wide Range Programmable I/O Cells .............................................................................................................. 36|Figure 2.18. Wide Range Programmable I/O Cells .............................................................................................................. 36|
|Figure 2.19. Input Register Block for PIO on Top, Left, and Right Sides of the Device ....................................................... 37|Figure 2.19. Input Register Block for PIO on Top, Left, and Right Sides of the Device ....................................................... 37|
|Figure 2.20. Input Register Block for PIO on Bottom Side of the Device ............................................................................ 38|Figure 2.20. Input Register Block for PIO on Bottom Side of the Device ............................................................................ 38|
|Figure 2.21. Output Register Block on Top, Left, and Right Sides ...................................................................................... 38|Figure 2.21. Output Register Block on Top, Left, and Right Sides ...................................................................................... 38|
|Figure 2.22. Output Register Block on Bottom Side ........................................................................................................... 39|Figure 2.22. Output Register Block on Bottom Side ........................................................................................................... 39|
|Figure 2.23. Tri-state Register Block on Top, Left, and Right Sides..................................................................................... 39|Figure 2.23. Tri-state Register Block on Top, Left, and Right Sides..................................................................................... 39|
|Figure 2.24. Tri-state Register Block on Bottom Side ......................................................................................................... 40|Figure 2.24. Tri-state Register Block on Bottom Side ......................................................................................................... 40|
|Figure 2.25. DQS Grouping on the Bottom Edge ................................................................................................................ 41|Figure 2.25. DQS Grouping on the Bottom Edge ................................................................................................................ 41|
|Figure 2.26. DQS Control and Delay Block (DQSBUF) ......................................................................................................... 42|Figure 2.26. DQS Control and Delay Block (DQSBUF) ......................................................................................................... 42|
|Figure 2.27. sysI/O Banking ................................................................................................................................................ 45|Figure 2.27. sysI/O Banking ................................................................................................................................................ 45|
|Figure 2.28. PCIe Core ......................................................................................................................................................... 51|Figure 2.28. PCIe Core ......................................................................................................................................................... 51|
|Figure 2.29. PCIe Soft IP Wrapper....................................................................................................................................... 52|Figure 2.29. PCIe Soft IP Wrapper....................................................................................................................................... 52|
|Figure 2.30. Cryptographic Engine Block Diagram .............................................................................................................. 52|Figure 2.30. Cryptographic Engine Block Diagram .............................................................................................................. 52|
|Figure 3.1. On-Chip Termination ........................................................................................................................................ 55|Figure 3.1. On-Chip Termination ........................................................................................................................................ 55|
|Figure 3.2. LVDS25E Output Termination Example ............................................................................................................ 64|Figure 3.2. LVDS25E Output Termination Example ............................................................................................................ 64|
|Figure 3.3. SubLVDS Input Interface ................................................................................................................................... 64|Figure 3.3. SubLVDS Input Interface ................................................................................................................................... 64|
|Figure 3.4. SubLVDS Output Interface ................................................................................................................................ 65|Figure 3.4. SubLVDS Output Interface ................................................................................................................................ 65|
|Figure 3.5. SLVS Interface ................................................................................................................................................... 66|Figure 3.5. SLVS Interface ................................................................................................................................................... 66|
|Figure 3.6. MIPI Interface ................................................................................................................................................... 67|Figure 3.6. MIPI Interface ................................................................................................................................................... 67|
|Figure 3.7. Receiver RX.CLK.Centered Waveforms ............................................................................................................. 80|Figure 3.7. Receiver RX.CLK.Centered Waveforms ............................................................................................................. 80|
|Figure 3.8. Receiver RX.CLK.Aligned and DDR Memory Input Waveforms ......................................................................... 80|Figure 3.8. Receiver RX.CLK.Aligned and DDR Memory Input Waveforms ......................................................................... 80|
|Figure 3.9. Transmit TX.CLK.Centered and DDR Memory Output Waveforms ................................................................... 81|Figure 3.9. Transmit TX.CLK.Centered and DDR Memory Output Waveforms ................................................................... 81|
|Figure 3.10. Transmit TX.CLK.Aligned Waveforms .............................................................................................................. 81|Figure 3.10. Transmit TX.CLK.Aligned Waveforms .............................................................................................................. 81|
|Figure 3.11. DDRX71 Video Timing Waveforms .................................................................................................................. 82|Figure 3.11. DDRX71 Video Timing Waveforms .................................................................................................................. 82|
|Figure 3.12. Receiver DDRX71_RX Waveforms ................................................................................................................... 82|Figure 3.12. Receiver DDRX71_RX Waveforms ................................................................................................................... 82|
|Figure 3.13. Transmitter DDRX71_TX Waveforms .............................................................................................................. 83|Figure 3.13. Transmitter DDRX71_TX Waveforms .............................................................................................................. 83|
|Figure 3.14. Master SPI POR/REFRESH Timing .................................................................................................................... 95|Figure 3.14. Master SPI POR/REFRESH Timing .................................................................................................................... 95|
|Figure 3.15. Slave SPI/I|Figure 3.15. Slave SPI/I2C/I3C POR/REFRESH Timing .......................................................................................................... 95|
|Figure 3.16. Master SPI PROGRAMN Timing ...................................................................................................................... 96|Figure 3.16. Master SPI PROGRAMN Timing ...................................................................................................................... 96|
|Figure 3.17. Slave SPI/I|Figure 3.17. Slave SPI/I2C/I3C PROGRAMN Timing ............................................................................................................. 96|
|Figure 3.18. Master SPI Configuration Timing .................................................................................................................... 97|Figure 3.18. Master SPI Configuration Timing .................................................................................................................... 97|
|Figure 3.19. Slave SPI Configuration Timing ....................................................................................................................... 97|Figure 3.19. Slave SPI Configuration Timing ....................................................................................................................... 97|
|Figure 3.20. I|Figure 3.20. I2C /I3C Configuration Timing ......................................................................................................................... 97|
|Figure 3.21. Master SPI Wake-Up Timing ........................................................................................................................... 98|Figure 3.21. Master SPI Wake-Up Timing ........................................................................................................................... 98|
|Figure 3.22. Slave SPI/I|Figure 3.22. Slave SPI/I2C/I3C Wake-Up Timing .................................................................................................................. 98|
© 2021-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02049-1.8
6
**CrossLink-NX Family Data Sheet**
|Figure 3.23. JTAG Port Timing Waveforms ......................................................................................................................... 99|Figure 3.23. JTAG Port Timing Waveforms ......................................................................................................................... 99|
|---|---|
|Figure 3.24. Output Test Load, LVTTL and LVCMOS Standards ........................................................................................ 100|Figure 3.24. Output Test Load, LVTTL and LVCMOS Standards ........................................................................................ 100|
|Figure 4.1. On-Chip Termination ...................................................................................................................................... 103|Figure 4.1. On-Chip Termination ...................................................................................................................................... 103|
|Figure 4.2. LVDS25E Output Termination Example .......................................................................................................... 112|Figure 4.2. LVDS25E Output Termination Example .......................................................................................................... 112|
|Figure 4.3. SubLVDS Input Interface ................................................................................................................................. 112|Figure 4.3. SubLVDS Input Interface ................................................................................................................................. 112|
|Figure 4.4. SubLVDS Output Interface .............................................................................................................................. 113|Figure 4.4. SubLVDS Output Interface .............................................................................................................................. 113|
|Figure 4.5. SLVS Interface ................................................................................................................................................. 114|Figure 4.5. SLVS Interface ................................................................................................................................................. 114|
|Figure 4.6. MIPI Interface ................................................................................................................................................. 115|Figure 4.6. MIPI Interface ................................................................................................................................................. 115|
|Figure 4.7. Receiver RX.CLK.Centered Waveforms ........................................................................................................... 127|Figure 4.7. Receiver RX.CLK.Centered Waveforms ........................................................................................................... 127|
|Figure 4.8. Receiver RX.CLK.Aligned and DDR Memory Input Waveforms ....................................................................... 128|Figure 4.8. Receiver RX.CLK.Aligned and DDR Memory Input Waveforms ....................................................................... 128|
|Figure 4.9. Transmit TX.CLK.Centered and DDR Memory Output Waveforms ................................................................. 128|Figure 4.9. Transmit TX.CLK.Centered and DDR Memory Output Waveforms ................................................................. 128|
|Figure 4.10. Transmit TX.CLK.Aligned Waveforms ........................................................................................................... 128|Figure 4.10. Transmit TX.CLK.Aligned Waveforms ........................................................................................................... 128|
|Figure 4.11. DDRX71 Video Timing Waveforms ............................................................................................................... 129|Figure 4.11. DDRX71 Video Timing Waveforms ............................................................................................................... 129|
|Figure 4.12. Receiver DDRX71_RX Waveforms................................................................................................................. 129|Figure 4.12. Receiver DDRX71_RX Waveforms................................................................................................................. 129|
|Figure 4.13. Transmitter DDRX71_TX Waveforms ............................................................................................................ 130|Figure 4.13. Transmitter DDRX71_TX Waveforms ............................................................................................................ 130|
|Figure 4.14. Master SPI POR/REFRESH Timing ................................................................................................................. 142|Figure 4.14. Master SPI POR/REFRESH Timing ................................................................................................................. 142|
|Figure 4.15. Slave SPI/I|Figure 4.15. Slave SPI/I2C/I3C POR/REFRESH Timing ........................................................................................................ 142|
|Figure 4.16. Master SPI PROGRAMN Timing .................................................................................................................... 143|Figure 4.16. Master SPI PROGRAMN Timing .................................................................................................................... 143|
|Figure 4.17. Slave SPI/I|Figure 4.17. Slave SPI/I2C/I3C PROGRAMN Timing ........................................................................................................... 143|
|Figure 4.18. Master SPI Configuration Timing .................................................................................................................. 144|Figure 4.18. Master SPI Configuration Timing .................................................................................................................. 144|
|Figure 4.19. Slave SPI Configuration Timing ..................................................................................................................... 144|Figure 4.19. Slave SPI Configuration Timing ..................................................................................................................... 144|
|Figure 4.20. I|Figure 4.20. I2C /I3C Configuration Timing ....................................................................................................................... 144|
|Figure 4.21. Master SPI Wake-Up Timing ......................................................................................................................... 145|Figure 4.21. Master SPI Wake-Up Timing ......................................................................................................................... 145|
|Figure 4.22. Slave SPI/I|Figure 4.22. Slave SPI/I2C/I3C Wake-Up Timing ................................................................................................................ 145|
|Figure 4.23. JTAG Port Timing Waveforms ....................................................................................................................... 146|Figure 4.23. JTAG Port Timing Waveforms ....................................................................................................................... 146|
|Figure 4.24. Output Test Load, LVTTL and LVCMOS Standards ........................................................................................ 147|Figure 4.24. Output Test Load, LVTTL and LVCMOS Standards ........................................................................................ 147|
© 2021-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02049-1.8
7
**CrossLink-NX Family Data Sheet**
## **Tables**
|Table 1.1. CrossLink-NX Commercial/Industrial Family Selection Guide ............................................................................ 15|Table 1.1. CrossLink-NX Commercial/Industrial Family Selection Guide ............................................................................ 15|
|---|---|
|Table 1.2. CrossLink-NX Automotive Family Selection Guide ............................................................................................. 15|Table 1.2. CrossLink-NX Automotive Family Selection Guide ............................................................................................. 15|
|Table 2.1. Resources and Modes Available per Slice .......................................................................................................... 19|Table 2.1. Resources and Modes Available per Slice .......................................................................................................... 19|
|Table 2.2. Slice Signal Descriptions ..................................................................................................................................... 21|Table 2.2. Slice Signal Descriptions ..................................................................................................................................... 21|
|Table 2.3. Number of Slices Required to Implement Distributed RAM .............................................................................. 22|Table 2.3. Number of Slices Required to Implement Distributed RAM .............................................................................. 22|
|Table 2.4. sysMEM Block Configurations ............................................................................................................................ 31|Table 2.4. sysMEM Block Configurations ............................................................................................................................ 31|
|Table 2.5. Maximum Number of Elements in a sysDSP block ............................................................................................. 35|Table 2.5. Maximum Number of Elements in a sysDSP block ............................................................................................. 35|
|Table 2.6. Input Block Port Description .............................................................................................................................. 37|Table 2.6. Input Block Port Description .............................................................................................................................. 37|
|Table 2.7. Output Block Port Description ........................................................................................................................... 39|Table 2.7. Output Block Port Description ........................................................................................................................... 39|
|Table 2.8. Tri-state Block Port Description ......................................................................................................................... 40|Table 2.8. Tri-state Block Port Description ......................................................................................................................... 40|
|Table 2.9. DQSBUF Port List Description ............................................................................................................................. 42|Table 2.9. DQSBUF Port List Description ............................................................................................................................. 42|
|Table 2.10. Single-Ended I/O Standards ............................................................................................................................. 43|Table 2.10. Single-Ended I/O Standards ............................................................................................................................. 43|
|Table 2.11. Differential I/O Standards ................................................................................................................................ 44|Table 2.11. Differential I/O Standards ................................................................................................................................ 44|
|Table 2.12. Single-Ended I/O Standards Supported on Various Sides ................................................................................ 46|Table 2.12. Single-Ended I/O Standards Supported on Various Sides ................................................................................ 46|
|Table 2.13. Differential I/O Standards Supported on Various Sides ................................................................................... 46|Table 2.13. Differential I/O Standards Supported on Various Sides ................................................................................... 46|
|Table 3.1. Absolute Maximum Ratings ............................................................................................................................... 53|Table 3.1. Absolute Maximum Ratings ............................................................................................................................... 53|
|Table 3.2. Recommended Operating Conditions ................................................................................................................ 54|Table 3.2. Recommended Operating Conditions ................................................................................................................ 54|
|Table 3.3. Power Supply Ramp Rates ................................................................................................................................. 55|Table 3.3. Power Supply Ramp Rates ................................................................................................................................. 55|
|Table 3.4. Power-On Reset ................................................................................................................................................. 55|Table 3.4. Power-On Reset ................................................................................................................................................. 55|
|Table 3.5. On-Chip Termination Options for Input Modes ................................................................................................. 56|Table 3.5. On-Chip Termination Options for Input Modes ................................................................................................. 56|
|Table 3.6. Hot Socketing Specifications for GPIO ............................................................................................................... 56|Table 3.6. Hot Socketing Specifications for GPIO ............................................................................................................... 56|
|Table 3.7. DC Electrical Characteristics – Wide Range ........................................................................................................ 57|Table 3.7. DC Electrical Characteristics – Wide Range ........................................................................................................ 57|
|Table 3.8. DC Electrical Characteristics – High Speed ......................................................................................................... 57|Table 3.8. DC Electrical Characteristics – High Speed ......................................................................................................... 57|
|Table 3.9. Capacitors – Wide Range ................................................................................................................................... 57|Table 3.9. Capacitors – Wide Range ................................................................................................................................... 57|
|Table 3.10. Capacitors – High Performance ........................................................................................................................ 58|Table 3.10. Capacitors – High Performance ........................................................................................................................ 58|
|Table 3.11. Single Ended Input Hysteresis – Wide Range ................................................................................................... 58|Table 3.11. Single Ended Input Hysteresis – Wide Range ................................................................................................... 58|
|Table 3.12. Single Ended Input Hysteresis – High Performance ......................................................................................... 58|Table 3.12. Single Ended Input Hysteresis – High Performance ......................................................................................... 58|
|Table 3.13. sysI/O Recommended Operating Conditions ................................................................................................... 59|Table 3.13. sysI/O Recommended Operating Conditions ................................................................................................... 59|
|Table 3.14. sysI/O DC Electrical Characteristics – Wide Range I/O ..................................................................................... 60|Table 3.14. sysI/O DC Electrical Characteristics – Wide Range I/O ..................................................................................... 60|
|Table 3.15. sysI/O DC Electrical Characteristics – High Performance I/O ........................................................................... 61|Table 3.15. sysI/O DC Electrical Characteristics – High Performance I/O ........................................................................... 61|
|Table 3.16. I/O Resistance Characteristics .......................................................................................................................... 61|Table 3.16. I/O Resistance Characteristics .......................................................................................................................... 61|
|Table 3.17. V|Table 3.17. VINMaximum Overshoot/Undershoot Allowance – Wide Range1, 2................................................................ 62|
|Table 3.18. V|Table 3.18. VINMaximum Overshoot/Undershoot Allowance – High Performance1, 2....................................................... 62|
|Table 3.19. LVDS DC Electrical Characteristics|Table 3.19. LVDS DC Electrical Characteristics1.................................................................................................................. 63|
|Table 3.20. LVDS25E DC Conditions .................................................................................................................................... 63|Table 3.20. LVDS25E DC Conditions .................................................................................................................................... 63|
|Table 3.21. SubLVDS Input DC Electrical Characteristics .................................................................................................... 64|Table 3.21. SubLVDS Input DC Electrical Characteristics .................................................................................................... 64|
|Table 3.22. SubLVDS Output DC Electrical Characteristics ................................................................................................. 65|Table 3.22. SubLVDS Output DC Electrical Characteristics ................................................................................................. 65|
|Table 3.23. SLVS Input DC Characteristics .......................................................................................................................... 65|Table 3.23. SLVS Input DC Characteristics .......................................................................................................................... 65|
|Table 3.24. SLVS Output DC Characteristics ....................................................................................................................... 65|Table 3.24. SLVS Output DC Characteristics ....................................................................................................................... 65|
|Table 3.25. Soft D-PHY Input Timing and Levels ................................................................................................................. 68|Table 3.25. Soft D-PHY Input Timing and Levels ................................................................................................................. 68|
|Table 3.26. Soft D-PHY Output Timing and Levels .............................................................................................................. 68|Table 3.26. Soft D-PHY Output Timing and Levels .............................................................................................................. 68|
|Table 3.27. Soft D-PHY Clock Signal Specification ............................................................................................................... 69|Table 3.27. Soft D-PHY Clock Signal Specification ............................................................................................................... 69|
|Table 3.28. Soft D-PHY Data-Clock Timing Specifications ................................................................................................... 69|Table 3.28. Soft D-PHY Data-Clock Timing Specifications ................................................................................................... 69|
|Table 3.29. Maximum I/O Buffer Speed|Table 3.29. Maximum I/O Buffer Speed1, 2, 3, 4, 7.................................................................................................................. 70|
|Table 3.30. Pin-to-Pin Performance .................................................................................................................................... 72|Table 3.30. Pin-to-Pin Performance .................................................................................................................................... 72|
|Table 3.31. Register-to-Register Performance.................................................................................................................... 73|Table 3.31. Register-to-Register Performance.................................................................................................................... 73|
|Table 3.32. LMMI F|Table 3.32. LMMI FMAXSummary ........................................................................................................................................ 73|
|Table 3.33. External Switching Characteristics (V|Table 3.33. External Switching Characteristics (VCC= 1.0 V) ............................................................................................... 74|
|Table 3.34. sysCLOCK PLL Timing (V|Table 3.34. sysCLOCK PLL Timing (VCC= 1.0 V) – Commercial/Industrial ............................................................................ 83|
|Table 3.35. Internal Oscillators (V|Table 3.35. Internal Oscillators (VCC= 1.0 V) ....................................................................................................................... 84|
|Table 3.36. User I|Table 3.36. User I2C Specifications (VCC= 1.0 V) .................................................................................................................. 84|
|Table 3.37. ADC Specifications|Table 3.37. ADC Specifications1.......................................................................................................................................... 85|
© 2021-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
8
FPGA-DS-02049-1.8
**CrossLink-NX Family Data Sheet**
|Table 3.38. Comparator Specifications|Table 3.38. Comparator Specifications1.............................................................................................................................. 86|
|---|---|
|Table 3.39. DTR Specifications|Table 3.39. DTR Specifications1, 2........................................................................................................................................ 86|
|Table 3.40. Hardened D-PHY Input Timing and Levels ....................................................................................................... 86|Table 3.40. Hardened D-PHY Input Timing and Levels ....................................................................................................... 86|
|Table 3.41. Hardened D-PHY Output Timing and Levels .................................................................................................... 87|Table 3.41. Hardened D-PHY Output Timing and Levels .................................................................................................... 87|
|Table 3.42. Hardened D-PHY Pin Characteristic Specifications .......................................................................................... 89|Table 3.42. Hardened D-PHY Pin Characteristic Specifications .......................................................................................... 89|
|Table 3.43. Hardened D-PHY Clock Signal Specification ..................................................................................................... 89|Table 3.43. Hardened D-PHY Clock Signal Specification ..................................................................................................... 89|
|Table 3.44. Hardened D-PHY Data-Clock Timing Specifications ......................................................................................... 89|Table 3.44. Hardened D-PHY Data-Clock Timing Specifications ......................................................................................... 89|
|Table 3.45. PCIe (2.5 Gbps) ................................................................................................................................................. 90|Table 3.45. PCIe (2.5 Gbps) ................................................................................................................................................. 90|
|Table 3.46. PCIe (5 Gbps) .................................................................................................................................................... 91|Table 3.46. PCIe (5 Gbps) .................................................................................................................................................... 91|
|Table 3.47. SGMII ................................................................................................................................................................ 93|Table 3.47. SGMII ................................................................................................................................................................ 93|
|Table 3.48. sysCONFIG Port Timing Specifications ............................................................................................................. 93|Table 3.48. sysCONFIG Port Timing Specifications ............................................................................................................. 93|
|Table 3.49. JTAG Port Timing Specifications ....................................................................................................................... 99|Table 3.49. JTAG Port Timing Specifications ....................................................................................................................... 99|
|Table 3.50. Test Fixture Required Components, Non-Terminated Interfaces .................................................................. 100|Table 3.50. Test Fixture Required Components, Non-Terminated Interfaces .................................................................. 100|
|Table 4.1. Absolute Maximum Ratings ............................................................................................................................. 101|Table 4.1. Absolute Maximum Ratings ............................................................................................................................. 101|
|Table 4.2. Recommended Operating Conditions .............................................................................................................. 102|Table 4.2. Recommended Operating Conditions .............................................................................................................. 102|
|Table 4.3. Power Supply Ramp Rates ............................................................................................................................... 103|Table 4.3. Power Supply Ramp Rates ............................................................................................................................... 103|
|Table 4.4. Power-On Reset ............................................................................................................................................... 103|Table 4.4. Power-On Reset ............................................................................................................................................... 103|
|Table 4.5. On-Chip Termination Options for Input Modes ............................................................................................... 104|Table 4.5. On-Chip Termination Options for Input Modes ............................................................................................... 104|
|Table 4.6. Hot Socketing Specifications for GPIO ............................................................................................................. 104|Table 4.6. Hot Socketing Specifications for GPIO ............................................................................................................. 104|
|Table 4.7. DC Electrical Characteristics – Wide Range ...................................................................................................... 105|Table 4.7. DC Electrical Characteristics – Wide Range ...................................................................................................... 105|
|Table 4.8. DC Electrical Characteristics – High Speed ....................................................................................................... 105|Table 4.8. DC Electrical Characteristics – High Speed ....................................................................................................... 105|
|Table 4.9. Capacitors – Wide Range ................................................................................................................................. 105|Table 4.9. Capacitors – Wide Range ................................................................................................................................. 105|
|Table 4.10. Capacitors – High Performance ..................................................................................................................... 106|Table 4.10. Capacitors – High Performance ..................................................................................................................... 106|
|Table 4.11. Single Ended Input Hysteresis – Wide Range ................................................................................................. 106|Table 4.11. Single Ended Input Hysteresis – Wide Range ................................................................................................. 106|
|Table 4.12. Single Ended Input Hysteresis – High Performance ....................................................................................... 106|Table 4.12. Single Ended Input Hysteresis – High Performance ....................................................................................... 106|
|Table 4.13. sysI/O Recommended Operating Conditions ................................................................................................. 107|Table 4.13. sysI/O Recommended Operating Conditions ................................................................................................. 107|
|Table 4.14. sysI/O DC Electrical Characteristics – Wide Range I/O .................................................................................. 108|Table 4.14. sysI/O DC Electrical Characteristics – Wide Range I/O .................................................................................. 108|
|Table 4.15. sysI/O DC Electrical Characteristics – High Performance I/O|Table 4.15. sysI/O DC Electrical Characteristics – High Performance I/O3....................................................................... 109|
|Table 4.16. I/O Resistance Characteristics ........................................................................................................................ 109|Table 4.16. I/O Resistance Characteristics ........................................................................................................................ 109|
|Table 4.17. V|Table 4.17. VINMaximum Overshoot/Undershoot Allowance – Wide Range1, 2.............................................................. 110|
|Table 4.18. V|Table 4.18. VINMaximum Overshoot/Undershoot Allowance – High Performance1, 2..................................................... 110|
|Table 4.19. LVDS DC Electrical Characteristics|Table 4.19. LVDS DC Electrical Characteristics1................................................................................................................ 111|
|Table 4.20. LVDS25E DC Conditions .................................................................................................................................. 111|Table 4.20. LVDS25E DC Conditions .................................................................................................................................. 111|
|Table 4.21. SubLVDS Input DC Electrical Characteristics .................................................................................................. 112|Table 4.21. SubLVDS Input DC Electrical Characteristics .................................................................................................. 112|
|Table 4.22. SubLVDS Output DC Electrical Characteristics ............................................................................................... 113|Table 4.22. SubLVDS Output DC Electrical Characteristics ............................................................................................... 113|
|Table 4.23. SLVS Input DC Characteristics ........................................................................................................................ 113|Table 4.23. SLVS Input DC Characteristics ........................................................................................................................ 113|
|Table 4.24. SLVS Output DC Characteristics ..................................................................................................................... 113|Table 4.24. SLVS Output DC Characteristics ..................................................................................................................... 113|
|Table 4.25. Soft D-PHY Input Timing and Levels ............................................................................................................... 115|Table 4.25. Soft D-PHY Input Timing and Levels ............................................................................................................... 115|
|Table 4.26. Soft D-PHY Output Timing and Levels ............................................................................................................ 116|Table 4.26. Soft D-PHY Output Timing and Levels ............................................................................................................ 116|
|Table 4.27. Soft D-PHY Clock Signal Specification ............................................................................................................ 117|Table 4.27. Soft D-PHY Clock Signal Specification ............................................................................................................ 117|
|Table 4.28. Soft D-PHY Data-Clock Timing Specifications ................................................................................................. 117|Table 4.28. Soft D-PHY Data-Clock Timing Specifications ................................................................................................. 117|
|Table 4.29. Maximum I/O Buffer Speed|Table 4.29. Maximum I/O Buffer Speed1, 2, 3, 4, 7................................................................................................................ 117|
|Table 4.30. Pin-to-Pin Performance .................................................................................................................................. 120|Table 4.30. Pin-to-Pin Performance .................................................................................................................................. 120|
|Table 4.31. Register-to-Register Performance ................................................................................................................. 120|Table 4.31. Register-to-Register Performance ................................................................................................................. 120|
|Table 4.32. LMMI F|Table 4.32. LMMI FMAXSummary ...................................................................................................................................... 121|
|Table 4.33. External Switching Characteristics (V|Table 4.33. External Switching Characteristics (VCC= 1.0 V) ............................................................................................. 122|
|Table 4.34. sysCLOCK PLL Timing (V|Table 4.34. sysCLOCK PLL Timing (VCC= 1.0 V) – Automotive ........................................................................................... 130|
|Table 4.35. Internal Oscillators (V|Table 4.35. Internal Oscillators (VCC= 1.0 V) ..................................................................................................................... 131|
|Table 4.36. User I|Table 4.36. User I2C Specifications (VCC= 1.0 V) ................................................................................................................ 131|
|Table 4.37. ADC Specifications|Table 4.37. ADC Specifications3........................................................................................................................................ 132|
|Table 4.38. Comparator Specifications ............................................................................................................................. 133|Table 4.38. Comparator Specifications ............................................................................................................................. 133|
|Table 4.39. DTR Specifications|Table 4.39. DTR Specifications1, 2...................................................................................................................................... 133|
|Table 4.40. Hardened D-PHY Input Timing and Levels ..................................................................................................... 133|Table 4.40. Hardened D-PHY Input Timing and Levels ..................................................................................................... 133|
|Table 4.41. Hardened D-PHY Output Timing and Levels .................................................................................................. 134|Table 4.41. Hardened D-PHY Output Timing and Levels .................................................................................................. 134|
© 2021-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02049-1.8
9
**CrossLink-NX Family Data Sheet**
|Table 4.42. Hardened D-PHY Pin Characteristic Specifications ........................................................................................ 136|Table 4.42. Hardened D-PHY Pin Characteristic Specifications ........................................................................................ 136|
|---|---|
|Table 4.43. Hardened D-PHY Clock Signal Specification ................................................................................................... 136|Table 4.43. Hardened D-PHY Clock Signal Specification ................................................................................................... 136|
|Table 4.44. Hardened D-PHY Data-Clock Timing Specifications ....................................................................................... 136|Table 4.44. Hardened D-PHY Data-Clock Timing Specifications ....................................................................................... 136|
|Table 4.45. PCIe (2.5 Gbps) ............................................................................................................................................... 137|Table 4.45. PCIe (2.5 Gbps) ............................................................................................................................................... 137|
|Table 4.46. PCIe (5 Gbps) .................................................................................................................................................. 138|Table 4.46. PCIe (5 Gbps) .................................................................................................................................................. 138|
|Table 4.47. SGMII .............................................................................................................................................................. 140|Table 4.47. SGMII .............................................................................................................................................................. 140|
|Table 4.48. sysCONFIG Port Timing Specifications ........................................................................................................... 140|Table 4.48. sysCONFIG Port Timing Specifications ........................................................................................................... 140|
|Table 4.49. JTAG Port Timing Specifications ..................................................................................................................... 146|Table 4.49. JTAG Port Timing Specifications ..................................................................................................................... 146|
|Table 4.50. Test Fixture Required Components, Non-Terminated Interfaces .................................................................. 147|Table 4.50. Test Fixture Required Components, Non-Terminated Interfaces .................................................................. 147|
© 2021-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
10
FPGA-DS-02049-1.8
**CrossLink-NX Family Data Sheet**
## **Acronyms in This Document**
A list of acronyms used in this document.
|**Acronym **<br>~~ee~~<br>~~ee~~|**Definition**|
|---|---|
|AES<br>~~ee~~<br>~~ee~~|Advanced Encryption Standard|
|ADC<br>~~ee~~<br>~~a~~<br>~~ee~~|Analogto Digital Converter|
|BGA<br>~~ee~~|Ball Grid Array|
|CDR<br>~~ee~~<br>~~a~~<br>~~ee~~|Clock and Data Recovery|
|CRC<br>~~ee~~|Cycle RedundancyCode|
|CSI<br>~~ee~~<br>~~a~~|Camera Serial Interface|
|DCC<br>~~a~~<br>~~ee~~|Dynamic Clock Control|
|DCS<br>~~ee~~|Dynamic Clock Select|
|DDR<br>~~ee~~<br>~~a~~|Double Data Rate|
|DLL<br>~~a~~<br>~~a~~|DelayLocked Loop|
|DSI<br>~~a~~|DisplaySerial Interface|
|DSP<br>~~a~~|Digital Signal Processing|
|DTR<br>~~a~~<br>~~ee~~|Digital Temperature Readout|
|EBR<br>~~ee~~|Embedded Block RAM|
|ECC<br>~~ee~~<br>~~a~~|Error Correction Coding|
|ECLK<br>~~a~~|Edge Clock|
|FFT<br>~~a~~|Fast Fourier Transform|
|FIFO<br>~~a~~<br>~~ee~~|First In First Out|
|FIR<br>~~ee~~|Finite Impulse Response|
|HFOSC<br>~~ee~~<br>~~a~~|High FrequencyOscillator|
|HSP<br>~~a~~|High Speed Port|
|LFOSC<br>~~a~~|Low FrequencyOscillator|
|LC|Logic Cell|
|LRAM<br>~~a~~|Large RAM|
|LVCMOS<br>~~a~~<br>~~a~~|Low-Voltage ComplementaryMetal Oxide Semiconductor|
|LVDS<br>~~a~~|Low-Voltage Differential Signaling|
|LVPECL<br>~~a~~|Low Voltage Positive Emitter Coupled Logic|
|LVTTL<br>~~a~~|Low Voltage Transistor-Transistor Logic|
|LUT<br>~~a~~<br>~~a~~|Look UpTable|
|MAC<br>~~a~~<br>~~a~~|Message Authentication Codes|
|PCI<br>~~a~~|Peripheral Component Interconnect|
|PCS<br>~~a~~|Physical CodingSublayer|
|PCLK<br>~~a~~|PrimaryClock|
|PDPR<br>~~a~~<br>~~a~~<br>~~ee~~|Pseudo Dual Port RAM|
|PFU<br>~~a~~<br>~~ee~~|Programmable Functional Unit|
|PIC<br>~~ee~~<br>~~a~~|Programmable I/O Cells|
|PLL<br>~~a~~|Phase Locked Loop|
|POR<br>~~a~~|Power On Reset|
|SED<br>~~a~~<br>~~a~~<br>~~ee~~|Soft Error Detection|
|SER<br>~~a~~<br>~~ee~~|Soft Error Rate|
|SEU<br>~~ee~~<br>~~a~~<br>~~a~~|Single Event Upset|
|SHA<br>~~a~~<br>~~a~~||
|SLVS<br>~~a~~<br>~~a~~|Scalable Low-Voltage Signaling|
|SPI<br>~~a~~<br>~~a~~|Serial Peripheral Interface|
|SPR<br>~~a~~<br>~~a~~|Single Port RAM|
© 2021-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02049-1.8
11
**CrossLink-NX Family Data Sheet**
|**Acronym **|**Definition**|
|---|---|
|SRAM|Static Random-Access Memory|
|TAP|Test Access Port|
|TDM|Time Division Multiplexing|
|TLP|Transaction Layer Packet|
|TRNG|True Random Number Generator|
|UCFG|User Configuration Space Register Interface|
© 2021-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
12
FPGA-DS-02049-1.8
**CrossLink-NX Family Data Sheet**
## **1. General Description**
The CrossLink™-NX family of low-power FPGAs can be used in a wide range of applications and are optimized for bridging and processing needs in Embedded Vision applications – supporting a variety of high bandwidth sensor and display interfaces, video processing and machine learning inferencing. It is built on the Lattice Nexus FPGA platform, using low-power 28 nm FD-SOI technology. It combines the extreme flexibility of an FPGA with the low power and high reliability (due to extremely low SER) of FD-SOI technology, and offers small footprint package options.
CrossLink-NX supports a variety of interfaces including MIPI D-PHY (CSI-2, DSI), LVDS, SLVS, subLVDS, PCI Express (Gen1, Gen2), SGMII (Gigabit Ethernet), and more.
Processing features of CrossLink-NX include up to 39k Logic Cells, 56 multipliers (18 × 18), 2.9 Mb of embedded memory (consisting of EBR and LRAM blocks), distributed memory, DRAM interfaces (supporting DDR3, DDR3L, LPDDR2, and LPDDR3 up to 1066 Mbps × 16-bit data width).
CrossLink-NX FPGAs support fast configuration of its reconfigurable SRAM-based logic fabric, and ultra-fast configuration of its programmable sysI/O™. Security features to secure user designs include bitstream encryption and password protection. In addition to the high reliability inherent to FD-SOI technology (due to its extremely low SER), active reliability features such as built-in frame-based SED/SEC (for SRAM-based logic fabric), and ECC (for EBR and LRAM) are also supported. Dual 12-bit ADCs are available in each device for system monitoring functions.
The Lattice Radiant™ design software allows large complex user designs to be efficiently implemented in the CrossLink-NX FPGA family. Synthesis library support for CrossLink-NX devices is available for popular logic synthesis tools. Radiant tools use the synthesis tool output along with constraints from its floor planning tools to place and route the user design in the CrossLink-NX device. The tools extract timing from the routing and back-annotate it into the design for timing verification.
Lattice provides many pre-engineered IP (Intellectual Property) modules for the CrossLink-NX family. By using these configurable soft IP cores as standardized blocks, users are free to concentrate on the unique aspects of the design, increasing productivity.
## **1.1. Features**
- Programmable Architecture
- 17k to 39k logic cells
- 24 to 56 multipliers (18 × 18) in sysDSP™ blocks
- 2.5 to 2.9 Mb of embedded memory (EBR, LRAM)
- 36 to 192 programmable sysI/O (High Performance and Wide Range I/O)
- MIPI D-PHY
- Up to two hardened 4-lane MIPI D-PHY
- Up to eight lanes total
- Transmit or receive
- Supports CSI-2, DSI
- 20 Gbps aggregate bandwidth
- 2.5 Gbps per lane, 10 Gbps per D-PHY interface
- Additional Soft D-PHY interfaces supported by High Performance (HP) sysI/O
- Transmit or receive
- Supports CSI-2, DSI
- Up to 1.5 Gbps per lane
- Programmable sysI/O supports wide variety of interfaces
- High Performance (HP) on bottom I/O dual rank
- Supports up to 1.8 V VCCIO
- Mixed voltage support (1.0 V, 1.2 V, 1.5 V, 1.8 V)
- High-speed differential up to 1.5 Gbps
- Supports soft D-PHY (Tx/Rx), LVDS 7:1 (Tx/Rx), SLVS (Tx/Rx), subLVDS (Rx)
- Supports SGMII (Gb Ethernet) Two channels (Tx/Rx) @ 1.25 Gbps
- Dedicated DDR3/DDR3L and LPDDR2/LPDDR3 memory support with DQS logic, up to 1066 Mbps data rate and 16-bit data width
- Wide Range (WR) on Left, Right and Top I/O Banks
- Supports up to 3.3 V VCCIO
- Mixed voltage support (1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.3 V)
- Programmable slew rate (slow, med, fast)
- Controlled impedance mode
- Emulated LVDS support
- Hot Socketing Support
© 2021-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02049-1.8
13
**CrossLink-NX Family Data Sheet**
- Power Modes – Low Power versus HighPerformance
- User selectable
- Low-Power mode for power and/or thermal challenges
- High-Performance mode for faster processing
- Small footprint package options
- 4 mm × 4 mm to 10 mm × 10 mm package options
- 2x SGMII CDR at up to 1.25 Gbps – to support 2 channels SGMII using HP I/O
- CDR for RX
- 10b/8b decoding
- Independent Loss of Lock (LOL) detector for each CDR block
- sysCLOCK™ analog PLLs
- Three in 39k LC and two in 17k LC device
- Six outputs per PLL
- Fractional N
- Programmable and dynamic phase control
- sysDSP Enhanced DSP blocks
- Hardened pre-adder
- Dynamic Shift for AI/ML support
- Four 18 × 18, eight 9 × 9, two 18 × 36, or 36 × 36 multipliers
- Advanced 18 × 36, two 18 × 18, or four 8 × 8 MAC
- Flexible memory resources
- Up to 1.5 Mb sysMEM™ Embedded Block RAM (EBR)
- Programmable width
- • ECC[*]
- Single or dual clock FIFO
- 80k to 240k bits distributed RAM
- Large RAM Blocks
- 0.5 Mbits per block
- Up to five blocks (2.5 Mb total) per device
- SerDes – PCIe Gen2 x1 channel (Tx/Rx) hard IP in 39k LC device
- Configuration – Fast, Secure
- SPI – x1, x2, x4 up to 150 MHz
- Master and Slave SPI support
- JTAG
- I[2] C and I3C
- Ultrafast I/O configuration for instant-on support (under 3 ms)
- Less than 15 ms full device configuration for LIFCl-40
- Bitstream Security
- Encryption
- Authentication
- Cryptographic engine
- Bitstream encryption – using AES-256
- Bitstream authentication – using ECDSA
- Hashing algorithms – SHA, HMAC
- True Random Number Generator
- AES 128/256 Encryption
- Single Event Upset (SEU) Mitigation Support
- Extremely low Soft Error Rate (SER) due to FDSOI technology
- Soft Error Detect – Embedded hard macro
- Soft Error Correction – Without stopping user operation
- Soft Error Injection – Emulate SEU event to debug system error handling
- Dual ADCs – 1 MSPS, 12-bit SAR with Simultaneous Sampling[*]
- Two ADCs per device
- Three Continuous-time Comparators
- Simultaneous Sampling
- System Level Support
- IEEE 1149.1 and IEEE 1532 compliant
- Reveal Logic Analyzer
- On-chip oscillator for initialization and general use
- 1.0 V core power supply
- ***Note:** Available in select speed grades. See Ordering Information.
- Hard IP supports
- Gen1, Gen2, Multi-Function, End Point, Root Complex
- Internal bus interface support
- APB control bus
- AHB-Lite for data bus
- AXI4-streaming
© 2021-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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**CrossLink-NX Family Data Sheet**
**Table 1.1. CrossLink-NX Commercial/Industrial Family Selection Guide**
|**Device**|**LIFCL-17**|**LIFCL-40**|
|---|---|---|
|Logic Cells¹<br>~~GO~~|17k<br>~~GO~~|39k<br>~~GO~~|
|Embedded Memory (EBR)Blocks(18 kb)<br>~~GO~~|24<br>~~GO~~|84<br>~~GO~~|
|Embedded Memory (EBR)Bits(kb)<br>~~CO~~|432<br>~~CO~~|1,512<br>~~CO~~|
|Distributed RAM Bits(kb)<br>~~CO~~|108<br>~~CO~~|252<br>~~CO~~|
|Large Memory (LRAM)Blocks<br>~~CO~~|5<br>~~CO~~|2<br>~~CO~~|
|Large Memory (LRAM)Bits(kb) (512 kbits each)<br>~~CO~~|2560<br>~~CO~~|1024<br>~~CO~~|
|18 × 18 Multipliers<br>~~GD~~|24<br>~~GD~~|56<br>~~GD~~|
|ADC Blocks3<br>~~CO~~|2<br>~~CO~~|2<br>~~CO~~|
|450 MHz High FrequencyOscillator<br>~~OC~~|1<br>~~OC~~|1<br>~~OC~~|
|128 kHz Low Power Oscillator<br>~~CO~~|1<br>~~CO~~|1<br>~~CO~~|
|GPLL<br>~~CO~~<br>~~CO~~|2<br>~~CO~~<br>~~CO~~|3<br>~~CO~~<br>~~CO~~|
|Hardened 10 Gbps D-PHY Quads²<br>~~GD~~|2<br>~~GD~~|2<br>~~GD~~|
|Hardened 2.5 Gbps D-PHY Data Lanes(total)²<br>~~CC~~|8<br>~~CC~~|8<br>~~CC~~|
|PCIe Gen2 Hard IP<br>~~GF~~|—<br>~~GF~~|1<br>~~GF~~|
|**Packages (Size, Ball Pitch)**|**D-PHY Quads (D-PHY Data Lanes) / Wide Range (WR) GPIO**<br>**(Top/Left/Right Banks) / High Performance (HP) GPIOs (Bottom**<br>**Banks)**||
|72 WLCSP(3.8 mm × 4.1 mm, 0.4 mm)<br>~~CC~~|1(4)/15/24<br>~~CC~~|—<br>~~CC~~|
|72 QFN(10 mm × 10 mm, 0.5 mm)<br>~~CO~~|1(4)/17/22<br>~~CO~~|1(4)/17/22<br>~~CO~~|
|121 csfBGA(6 mm × 6 mm, 0.5 mm)<br>~~CO~~<br>~~CO~~|2(8)/23/48<br>~~CO~~<br>~~CO~~|2(8)/23/48<br>~~CO~~<br>~~CO~~|
|256 caBGA(14 mm × 14 mm, 0.8 mm)<br>~~GD~~|2(8)/29/48<br>~~GD~~|2(8)/88/148, PCIe x1<br>~~GD~~|
|289 csBGA(9.5 mm × 9.5 mm, 0.5 mm)<br>~~GD~~|—<br>~~GD~~|2(8)/105/148, PCIe x1<br>~~GD~~|
|400 caBGA(17 mm × 17 mm, 0.8 mm)<br>~~a~~|—|2(8)/117/148, PCIe x1|
## **Notes:**
1. Logic Cells = LUTs × 1.2 effectiveness.
2. Additional soft D-PHY Tx/Rx interfaces (at up to 1.5 Gbps per lane) are available using sysI/O.
3. Available in –8 and –9 speed grades.
**Table 1.2. CrossLink-NX Automotive Family Selection Guide**
|**Device**|**LIFCL-17**|**LIFCL-40**|
|---|---|---|
|Logic Cells¹|17k|39k|
|Embedded Memory (EBR) Blocks (18 kb)|24|84|
|Embedded Memory (EBR) Bits (kb)|432|1,512|
|Distributed RAM Bits (kb)|80|240|
|Large Memory (LRAM) Blocks|5|2|
|Large Memory (LRAM) Bits (kb)|2560|1024|
|18 × 18 Multipliers|24|56|
|ADC Blocks3|2|2|
|450 MHz High Frequency Oscillator|1|1|
|128 kHz Low Power Oscillator|1|1|
|GPLL|2|3|
|Hardened 10 Gbps D-PHY Quads²|2|2|
|Hardened 2.5 Gbps D-PHY Data Lanes (total)²|8|8|
© 2021-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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**CrossLink-NX Family Data Sheet**
|**Device**|**LIFCL-17**|**LIFCL-40**|
|---|---|---|
|PCIe Gen2 Hard IP|—|1|
|**Packages (Size, Ball Pitch)**|**D-PHY Quads (D-PHY Data Lanes) / Wide Range (WR) GPIO**<br>**(Top/Left/Right Banks) / High Performance (HP) GPIOs (Bottom**<br>**Banks)**||
|121 csfBGA(6 mm × 6 mm, 0.5 mm)|2(8)/23/48|2(8)/23/48|
|256 caBGA(14 mm × 14 mm, 0.8 mm)|2(8)/29/48|2(8)/88/74, PCIe x1|
## **Notes:**
1. Logic Cells = LUTs × 1.2 effectiveness.
2. Additional soft D-PHY Tx/Rx interfaces (at up to 1.5 Gbps per lane) are available using sysI/O.
3. Available in –7 speed grade.
© 2021-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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**CrossLink-NX Family Data Sheet**
## **2. Architecture**
## **2.1. Overview**
Each CrossLink-NX device contains an array of logic blocks surrounded by Programmable I/O Cells (PIC). Interspersed between the rows of logic blocks are rows of sysMEM Embedded Block RAM (EBR) and rows of sysDSP Digital Signal Processing blocks, as shown in Figure 2.1. The CrossLink-NX-40 devices have two rows of DSP blocks and contain three rows of sysMEM EBR blocks. In addition, CrossLink-NX-40 devices includes two Large SRAM blocks. The sysMEM EBR blocks are large, dedicated 18 kb fast memory blocks and have built-in ECC and FIFO support. Each sysMEM block can be configured to a single, pseudo dual or true dual port memory in a variety of depths and widths as RAM or ROM. Each DSP block supports a variety of multiplier and adder configurations with one 108-bit or two 54-bit accumulators supported, which are the building blocks for complex signal processing capabilities.
Each PIC block encompasses two PIO (PIO pairs) with their respective sysI/O buffers. The sysI/O buffers of the CrossLink-NX devices are arranged in seven banks allowing the implementation of a wide variety of I/O standards. The Wide Range (WR) I/O banks that are located on the top, left and right sides of the device provide flexible ranges of general purpose I/O configurations up to 3.3 V VCCIOs. The banks located on the bottom side of the device are dedicated to High Performance (HP) interfaces such as LVDS, MIPI, DDR3, LPDDR2, and LPDDR3 supporting up to 1.8 V VCCIOs.
The Programmable Functional Unit (PFU) contains the building blocks for logic, arithmetic, RAM and ROM functions. The PFU block is optimized for flexibility, allowing complex designs to be implemented quickly and efficiently. Logic Blocks are arranged in a two-dimensional array. The registers in the PFU and sysI/O blocks in CrossLink-NX devices can be configured to be SET or RESET. After power up and configuration, it enters into user mode with these registers SET/RESET according to the user design, allowing the device to power up in a known state for predictable system function.
In addition, CrossLink-NX-40 devices provide various system level hard IP functional and interface blocks such as PCIe, D-PHY, I[2] C, SGMII/CDR, and ADC blocks. The PCIe hard IP supports PCIe Generation 2.0 and the D-PHY supports up to 2.5 Gbps per lane. CrossLink-NX devices also provide security features to help protect user designs and deliver more robust reliability by offering enhanced frame based SED/SEC functions.
Other blocks provided include PLLs, DLLs, and configuration functions. The PLL and DLL blocks are located at the corners of each device. CrossLink-NX devices also include Lattice Memory Mapped Interface (LMMI) which is a Lattice standard to support simple read and write operations to control internal IP.
Every device in the family has a JTAG port. This family also provides an on-chip oscillator and soft error detect capability. The CrossLink-NX devices use 1.0 V as their core voltage.
© 2021-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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**CrossLink-NX Family Data Sheet**
**==> picture [476 x 327] intentionally omitted <==**
**----- Start of picture text -----**<br>
I/O Bank (Bank 0)<br>PLL D-PHY (4 Lanes) D-PHY (4 Lanes) PCIe<br>OSC Configuration & Security<br>I/O Bank Large I/O Bank<br>(Bank 7) RAM (Bank 1)<br>|<br>Large<br>RAM<br>I/O Bank<br>(Bank 6) I/O Bank<br>(Bank 2)<br>ADC<br>(2Ch)<br>| CDR<br>(2Ch)<br>PLL I/O Bank (Bank 5) I/O Bank (Bank 4) I/O Bank (Bank 3) PLL<br>oeLLL<br>**----- End of picture text -----**<br>
**==> picture [468 x 254] intentionally omitted <==**
**----- Start of picture text -----**<br>
Figure 2.1. Simplified Block Diagram, CrossLink-NX-40 Device (Top Level)<br>I/O Bank (Bank 0)<br>D-PHY (4 Lanes) D-PHY (4 Lanes)<br>OSC Configuration and Security<br>Es. ..<br>Large<br>RAM<br>I/O Bank<br>(Bank 1)<br>Large<br>RAM<br>Large<br>RAM<br>LargeRAM LargeRAM<br>ADC<br>(2Ch)<br>——Dg F<br>CDR<br>(2Ch)<br>PLL I/O Bank (Bank 5) I/O Bank (Bank 4) I/O Bank (Bank 3) PLL<br>a| fg SEE ElHL<br>Figure 2.2. Simplified Block Diagram, CrossLink-NX-17 Device (Top Level)<br>**----- End of picture text -----**<br>
© 2021-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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FPGA-DS-02049-1.8
**CrossLink-NX Family Data Sheet**
## **2.2. PFU Blocks**
The core of the CrossLink-NX device consists of PFU blocks. Each PFU block consists of four interconnected slices numbered 0-3 as shown in Figure 2.3. Each slice contains two LUTs. All the interconnections to and from PFU blocks are from routing.
The PFU block can be used to perform Logical, Arithmetic, RAM or ROM functions. Table 2.1 shows the functions each slice can perform in either Distributed SRAM or non-distributed SRAM modes.
**==> picture [412 x 225] intentionally omitted <==**
**----- Start of picture text -----**<br>
From<br>Routing<br>= -b<br>LUT4 & LUT4 & LUT4 & LUT4 & LUT4 & LUT4 & LUT4 & LUT4 &<br>CARRY CARRY CARRY CARRY CARRY CARRY CARRY CARRY<br>‘ ai - i e -a<br>Slice 0 Slice 1 Slice 2 Slice 3<br>D D D D D D D D<br>FF FF FF FF FF FF FF FF<br>UE EE EE JE<br>To<br>Routing<br>= ob<br>**----- End of picture text -----**<br>
**Figure 2.3. PFU Diagram**
## **2.2.1. Slice**
Each slice contains two LUT4s feeding two registers. In Distributed SRAM mode, Slice 0 and Slice 1 are configured as distributed memory and Slice 2 is not available as it is used to support Slice 0 and Slice 1, while Slice 3 is available as Logic or ROM. Table 2.1 shows the capability of the slices along with the operation modes they enable. In addition, each Slice contains logic that allows the LUTs to be combined to perform a LUT5 function. There is control logic to perform set/reset functions (programmable as synchronous/asynchronous), clock select, chip-select, and wider RAM/ROM functions.
**Table 2.1. Resources and Modes Available per Slice**
|**Slice**|**PFU(Used as Distributed SRAM)**|**PFU(Used as Distributed SRAM)**|**PFU(Not used as Distributed SRAM)**|**PFU(Not used as Distributed SRAM)**|
|---|---|---|---|---|
||**Resources**|**Modes**|**Resources**|**Modes**|
|Slice 0|2 LUT4s and 2 Registers|RAM|2 LUT4s and 2 Registers|Logic, Ripple, ROM|
|Slice 1|2 LUT4s and 2 Registers|RAM|2 LUT4s and 2 Registers|Logic, Ripple, ROM|
|Slice 2|2 LUT4s and 2 Registers|RAM|2 LUT4s and 2 Registers|Logic, Ripple, ROM|
|Slice 3|2 LUT4s and 2 Registers|Logic, Ripple, ROM|2 LUT4s and 2 Registers|Logic, Ripple, ROM|
Figure 2.4 shows an overview of the internal logic of the slice. The registers in the slice can be configured for positive/negative edge clocking.
Each slice has 17 input signals: 16 signals from routing and one from the carry-chain (from the adjacent slice or PFU). Three of them are used for FF control and shared between two slices (0/1 or 2/3). There are five outputs: four to routing and one to carry-chain (to the adjacent PFU). Table 2.2 and Figure 2.4 list the signals associated with all the slices. Figure 2.5 shows the slice signals that support a LUT5 or two LUT5 functions. F0 can be configured to have a LUT4 or LUT5 output while F1 is for a LUT4 output.
© 2021-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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**CrossLink-NX Family Data Sheet**
**==> picture [21 x 28] intentionally omitted <==**
**----- Start of picture text -----**<br>
LUT5<br>and<br>Carry<br>**----- End of picture text -----**<br>
**Figure 2.4. Slice Diagram**
© 2021-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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FPGA-DS-02049-1.8
**CrossLink-NX Family Data Sheet**
**==> picture [373 x 246] intentionally omitted <==**
**----- Start of picture text -----**<br>
A1<br>F1<br>B1<br>LUT4<br>C1<br>D1<br>1<br>F0<br>0<br>SEL<br>A0<br>B0<br>LUT4<br>C0<br>D0<br>**----- End of picture text -----**<br>
*Note: In RAM mode, LUT4s use the following signals: QWD0/1 QWDN0/1 QWAS00~03, QWAS10~13
**Figure 2.5. Slice Configuration for LUT4 and LUT5**
**Table 2.2. Slice Signal Descriptions**
|**Function**<br>~~pf~~<br>~~Ge~~|**Type **<br>~~pf~~<br>~~Ge~~|**Signal Names**<br>~~pf~~<br>~~Ge~~|**Description**<br>~~pf~~<br>~~Ge~~|
|---|---|---|---|
|Input<br>~~Ge~~<br>~~a~~|Data signal<br>~~Ge~~<br>~~a~~|A0, B0, C0, D0<br>~~Ge~~<br>~~Ge~~|Inputs to LUT4<br>~~Ge~~|
|Input<br>~~Ge~~<br>~~a~~|Data signal<br>~~Ge~~<br>~~a~~|A1, B1, C1, D1<br>~~Ge ~~<br>~~Ge~~|Inputs to LUT4<br> ~~Ge~~|
|Input<br>~~a ~~<br>~~GG~~|Data signal<br> ~~a~~<br>~~GG~~|M0, M1<br>~~Ge~~<br>~~GG~~|Direct input to FF from fabric<br>~~GG~~|
|Input<br>~~GG~~<br>~~GG~~<br>~~Ge~~|Control signal<br>~~GG~~<br>~~GG~~<br>~~Ge~~|SEL<br>~~GG~~<br>~~GG~~<br>~~Ge~~|LUT5 mux control input<br>~~GG~~<br>~~GG~~<br>~~Ge~~|
|Input<br>~~GG~~<br>~~Ge~~<br>~~**G**~~|Data signal<br>~~GG~~<br>~~Ge~~<br>~~**G**e~~|DI0, DI1<br>~~GG~~<br>~~Ge~~<br>~~e~~|Inputs to FF from LUT4 F0/F1 outputs<br>~~GG~~<br>~~Ge~~<br>~~Ge~~|
|Input<br>~~Ge~~<br>~~**G**~~|Control signal<br>~~Ge~~<br>~~**G**e~~|CE<br>~~Ge ~~<br>~~e~~|Clock Enable<br> ~~Ge~~<br>~~Ge~~|
|Input<br>~~**G**~~<br>~~a~~|Control signal<br>~~**G**e~~<br>~~a~~|LSR<br>~~e ~~<br>~~Ge~~|Local Set/Reset<br> ~~Ge~~<br>~~G~~|
|Input<br>~~a~~|Control signal<br>~~a~~|CLKIN<br>~~Ge~~|System Clock|
|Input<br>~~a ~~<br>~~GG~~<br>~~Ge~~|Inter-PFU signal<br> ~~a~~<br>~~GG~~<br>~~Ge~~|FCI<br>~~Ge~~<br>~~GG~~<br>~~Ge~~|Fast Carry-in1<br>~~GG~~<br>~~Ge~~|
|Output<br>~~GG~~<br>~~Ge~~<br>~~**G**~~|Data signals<br>~~GG~~<br>~~Ge~~<br>~~**G**e~~|F0<br>~~GG~~<br>~~Ge~~<br>~~e~~|LUT4/LUT5 output signal<br>~~GG~~<br>~~Ge~~<br>~~Ge~~|
|Output<br>~~Ge~~<br>~~**G**~~|Data signals<br>~~Ge~~<br>~~**G**e~~|F1<br>~~Ge ~~<br>~~e~~|LUT4 output signal<br> ~~Ge~~<br>~~Ge~~|
|Output<br>~~**G**~~|Data signals<br>~~**G**e~~|Q0, Q1<br>~~e ~~|Register outputs<br> ~~Ge~~<br>~~G~~|
|Output<br>~~a~~|Inter-PFU signal<br>~~De~~|FCO<br>~~De~~|Fast carrychain output1|
**Note** :
1. See Figure 2.4 for connection details.
© 2021-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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**CrossLink-NX Family Data Sheet**
## **2.2.2. Modes of Operation**
Slices 0-2 have up to four potential modes of operation: Logic, Ripple, RAM and ROM. Slice 3 is not needed for RAM mode, it can be used in Logic, Ripple, or ROM modes.
## **Logic Mode**
In this mode, the LUTs in each slice are configured as 4-input combinatorial lookup tables. A LUT4 can have 16 possible input combinations. Any four input logic functions can be generated by programming this lookup table. Since there are two LUT4s per slice, a LUT5 can be constructed within one slice.
## **Ripple Mode**
Ripple mode supports the efficient implementation of small arithmetic functions. In ripple mode, the following functions can be implemented by each slice:
- Addition 2-bit
- Subtraction 2-bit
- Add/Subtract 2-bit using dynamic control
- Up counter 2-bit
- Down counter 2-bit
- Up/Down counter with asynchronous clear 2-bit using dynamic control
- Up/Down counter with preload (sync) 2-bit using dynamic control
- Comparator functions of A and B inputs 2-bit
- A greater-than-or-equal-to B
- A not-equal-to B
- A less-than-or-equal-to B
- Up/Down counter with A greater-than-or-equal-to B comparator 2-bit using dynamic control
- Up/Down counter with A less-than-or-equal-to B comparator 2-bit using dynamic control
- Multiplier support Ai×Bj+1 + Ai+1×Bj in one logic cell with 2 logic cells per slice
- Serial divider 2-bit mantissa, shift 1bit/cycle
- Serial multiplier 2-bit, shift 1bit/cycle or 2bit/cycle
Ripple Mode includes an optional configuration that performs arithmetic using fast carry chain methods. In this configuration (also referred to as CCU2 mode) two additional signals, Carry Generate and Carry Propagate, are generated on a per slice basis to allow fast arithmetic functions to be constructed by concatenating Slices.
## **RAM Mode**
In this mode, a 16 × 4-bit distributed single or pseudo dual port RAM can be constructed in one PFU using each LUT block in Slice 0 and Slice 1 as a 16 × 2-bit memory in each slice. Slice 2 is used to provide memory address and control signals. CrossLink-NX devices support distributed memory initialization.
The Lattice design tools support the creation of a variety of different sized memories. Where appropriate, the software constructs these using distributed memory primitives that represent the capabilities of the PFU. Table 2.3 lists the number of slices required to implement different distributed RAM primitives. For more information about using RAM in CrossLink-NX devices, refer to Memory User Guide for Nexus Platform (FPGA-TN-02094).
## **Table 2.3. Number of Slices Required to Implement Distributed RAM**
||**SPR 16 × 4**|**PDPR 16 × 4**|
|---|---|---|
|Number of slices|3|3|
**Note** : SPR = Single Port RAM, PDPR = Pseudo Dual Port RAM
## **ROM Mode**
ROM mode uses the LUT logic; hence, Slice 0 through Slice 3 can be used in ROM mode. Preloading is accomplished through the programming interface during PFU configuration.
For more information, refer to Memory User Guide for Nexus Platform (FPGA-TN-02094).
© 2021-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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FPGA-DS-02049-1.8
**CrossLink-NX Family Data Sheet**
## **2.3. Routing**
There are many resources provided in the CrossLink-NX devices to route signals individually or as busses with related control signals. The routing resources consist of switching circuitry, buffers and metal interconnect (routing) segments.
The CrossLink-NX family has an enhanced routing architecture that produces a compact design. The Radiant software tool takes the output of the synthesis tool and places and routes the design.
## **2.4. Clocking Structure**
The CrossLink-NX clocking structure consists of clock synthesis blocks (PLLs), balanced clock tree networks (PCLK and ECLK), and efficient clock logic modules: Clock Dividers (PCLKDIV and ECLKDIV), Dynamic Clock Selection (DCS), Dynamic Clock Control (DCC), and DDRDLLs. Each of these functions is described as follows.
## **2.4.1. Global PLL**
The Global PLLs (GPLL) provide the ability to synthesize clock frequencies. The devices in the CrossLink-NX family support two or three full-featured General Purpose GPLLs.
The architecture of the GPLL is shown in Figure 2.6. A description of the GPLL functionality follows.
REFCLK is the reference frequency input to the PLL and its source can come from external CLK inputs or from internal routing. The CLKI input feeds into the input Clock Divider block.
CLKFB is the feedback signal to the GPLL which can come from a path internal to the PLL or from FPGA routing. The feedback divider is used to multiply the reference frequency and thus synthesize a higher or lower frequency clock output.
The PLL has six clock outputs CLKOP, CLKOS, CLKOS2, CLKOS3, CLKOS4, and CLKOS5. Each output has its own output divider, thus allowing the GPLL to generate different frequencies for each output. The output dividers can have a value from 1 to 128. Each GPLL output can be used to drive the primary clock or edge clock networks.
The setup and hold times of the device can be improved by programming a phase shift into the output clocks which advances or delays the output clock with reference to the un-shifted output clock. This phase shift can be either programmed during configuration or can be adjusted dynamically using the DIRSEL, DIR, DYNROTATE, and LOADREG ports.
The LOCK signal is asserted when the GPLL determines it has achieved lock and deasserted if a loss of lock is detected. The LOCK signal is asynchronous to the PLL clock outputs.
© 2021-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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**CrossLink-NX Family Data Sheet**
**==> picture [52 x 7] intentionally omitted <==**
**----- Start of picture text -----**<br>
(To bypass muxes)<br>**----- End of picture text -----**<br>
**Figure 2.6. General Purpose PLL Diagram**
For more details on the PLL, refer to the sysCLOCK PLL Design and User Guide for Nexus Platform (FPGA-TN-02095).
## **2.4.2. Clock Distribution Network**
There are two main clock distribution networks for any member of the CrossLink-NX product family, namely Primary Clock (PCLK) and Edge Clock (ECLK). These clock networks can be driven from many different sources, such as Clock Pins, PLL outputs, DLLDEL outputs, Clock Divider outputs, SerDes/PCS clocks and user logic. There are Clock Divider blocks (ECLKDIV and PCLKDIV) to provide a slower clock from these clock sources.
CrossLink-NX supports glitchless Dynamic Clock Control (DCC) for the PCLK Clock to save dynamic power. There are also Dynamic Clock Selection logic to allow glitchless selection between two clocks for the PCLK network (DCS).
An overview of the Clocking Network is shown in Figure 2.7 for CrossLink-NX device. The shaded blocks (PCIe and upper left PLL) are not available in the 17k Logic Cell device.
© 2021-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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**CrossLink-NX Family Data Sheet**
**==> picture [447 x 287] intentionally omitted <==**
**----- Start of picture text -----**<br>
PLL MIPI_DPHY0 MIPI_DPHY1 BANK 0 PCLK OSC<br>: 2 : / 2 2<br>TMID<br>32 |. [| 16 DCC<br>N<br>xa Primary 16 Primary Sources Primary. °<br>Clocks 16 Fabrici Fabrici 16 Clocks<br>12 12 Primary Sources 12 Primary Sources 12<br>12 DCC pcs| pcs<br>Enti Ent<br>4 18 Primary Sources<br>a |o<br>© 18 DCC<br>[| Cy<br>Z<br>:<br>BMID<br>|<br>PLL BANK 5 PCLK ECLK BANK 4 PCLK ECLK BANK 3 PCLK ECLK PLL<br>* * 4 4 * 4 :<br>Figure 2.7. Clocking<br>BANK 1 PCLK<br>RMID<br>BANK 2 PCLK<br>LMID<br>**----- End of picture text -----**<br>
## **2.4.3. Primary Clocks**
The CrossLink-NX device family provides low-skew, high fan-out clock distribution to all synchronous elements in the FPGA fabric through the Primary Clock Network. The CrossLink-NX PCLK clock network is a balanced clock structure which is designed to minimize the clock skew across all destinations in the FPGA core.
The primary clock network is divided into two clock domains depending on the device density. Each of these domains has 16 clocks that can be distributed to the fabric in the domain.
The Lattice Radiant software can automatically route each clock to one of the domains up to a maximum of 16 clocks per domain. You can change how the clocks are routed by specifying a preference in the Lattice Radiant software to locate the clock to a specific domain. The CrossLink-NX device provides the user with a maximum of 64 unique clock input sources that can be routed to the primary Clock network.
Primary clock sources are:
- Dedicated clock input pins
- PLL outputs
- PCLKDIV, ECLKDIV outputs
- Internal FPGA fabric entries (with minimum general routing)
- SGMII-CDR, D-PHY, PCIe clocks
- OSC clock
These sources are routed to each of four clock switches called a Mid Mux (LMID, RMID, TMID, BMID). The outputs of the Mid MUX are routed to the center of the FPGA where additional clock switches (DSC_CMUX) are used to route the primary clock sources to primary clock distribution to the CrossLink-NX fabric. These routing muxs are shown in Figure 2.7. There are potentially 64 unique clock domains that can be used in the largest CrossLink-NX Device. For more information about the primary clock tree and connections, refer to sysCLOCK PLL Design and User Guide for Nexus Platform (FPGA-TN-02095).
© 2021-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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**CrossLink-NX Family Data Sheet**
## **2.4.4. Edge Clock**
CrossLink-NX FPGAs have a number of high-speed edge clocks that are intended for use with the PIO in the implementation of high-speed interfaces. There are four (4) ECLK networks per bank I/O on the Bottom side of the device. The Edge clock network is powered by a separate power domain (to reduce power noise injection from the core and reduce overall noise induced jitter) while controlled by the same logic that gates the FPGA core and PCLK domains for power management.
Each Edge Clock can be sourced from the following:
- Dedicated PIO Clock input pins (PCLK)
- DLLDEL output (PIO Clock delayed by 90°)
- PLL outputs (CLKOP, CLKOS, CLKOS2, CLKOS3, CLKOS4, and CLKOS5)
- Internal Nodes
Figure 2.8 illustrates the various ECLK sources. Bank 3 is shown in the example. Bank 4 and Bank 5 are similar.
**==> picture [423 x 168] intentionally omitted <==**
**----- Start of picture text -----**<br>
From Banks 4, 5<br>Bank 3 PCLK Pin (even) 2 ECLKSYNC<br>DLLDEL<br>Bottom 6<br>Left GPLL<br>Bank 3 ECLK Tree<br>From Fabric<br>ECLKSYNC<br>ECLKDIV BMID<br>Bottom 6<br>Right GPLL<br>2<br>Bank 3 PCLK Pin (odd)<br>To Banks 4,5 Muxes<br>**----- End of picture text -----**<br>
**Figure 2.8. Edge Clock Sources per Bank**
The edge clocks have low injection delay and low skew. They are typically used for DDR Memory or Generic DDR interfaces. For detailed information on Edge Clock connections, refer to sysCLOCK PLL Design and User Guide for Nexus Platform (FPGA-TN-02095).
## **2.4.5. Clock Dividers**
CrossLink-NX devices have two distinct types of clock divider, Primary and Edge. There are from one (1) to eight (8) Primary Clock Dividers (PCLKDIV) and which are located in the DCS_CMUX block(s) at the center of the device. There are twelve (12) ECLKDIV dividers per device, locate near the bottom high-speed I/O banks.
The PCLKDIV supports ÷2, ÷4, ÷8, ÷16, ÷32, ÷64, ÷128, and ÷1 (bypass) operation. The PCLKDIV is fed from a DCSMUX within the DCS_CMUX block. The clock divider output drives one input of the DCS Dynamic Clock Select within the DSC_CMUX block. The Reset (RST) control signal is asynchronous and forces all outputs to low. The divider output starts at next cycle after the reset is synchronously released. The PCLKDIV is shown in context in Figure 2.9.
The ECLKDIV is intended to generate a slower-speed system clock from a high-speed edge clock. The block operates in a ÷2, ÷3.5, ÷4, or ÷5 mode and maintains a known phase relationship between the divided down clock and the highspeed clock based on the release of its reset signal. The ECLKDIV can be fed from selected PLL outputs, external primary clock pins (with or without DLLDEL Delay) or from routing. The clock divider outputs feed into the Bottom Mid-mux (BMID). The Reset (RST) control signal is asynchronous and forces all outputs to low. The divider output starts at next cycle after the reset is synchronously released.
The ECLKDIV block is shown in context in Figure 2.8. For further information on clock dividers, refer to sysCLOCK PLL Design and User Guide for Nexus Platform (FPGA-TN-02095).
© 2021-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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**CrossLink-NX Family Data Sheet**
## **2.4.6. Clock Center Multiplexer Blocks**
All clock sources are selected and combined for primary clock routing through the Dynamic Clock Selector Center Multiplexer logic (DCS_CMUX). There are one (1) or two (2) DCS_CMUX blocks per device. Each DCS_CMUX block contains two DCSMUX blocks, one PCLKDIV, one DCS block, and 1 or 2 CMUX blocks. See Figure 2.9 for a representative DCS_CMUX block diagram.
The heart of the DCS_CMUX is the Center Multiplexer (CMUX) block. It can accept up to 64 input clock sources (Midmuxes (RMID, LMID, TMIC, BMID) and DCC) and to drive up to 16 primary clock trunk lines.
Up to two (2) clock inputs to the DCS_CMUX can be routed through a Dynamic Clock Select block then routed to the CMUX. One (1) input to the DCS can be optionally divided by the Primary Clock Divider (PCLKDIV). For more information about the DCS_CMUX, refer to sysCLOCK PLL Design and User Guide for Nexus Platform (FPGA-TN-02095).
**==> picture [408 x 252] intentionally omitted <==**
**----- Start of picture text -----**<br>
16 16<br>16x (partial 16x (partial<br>(16/64):1) (16/64):1)<br>CMUX CMUX<br>16 16<br>DCS_CMUX dcs2cmux0<br>DCS<br>62<br>dcs1 dcs0<br>PCLKDIV<br>DCMUX DCMUX<br>(62:1) (62:1)<br>62 62<br>62 62<br>62<br>**----- End of picture text -----**<br>
**Figure 2.9. DCS_CMUX Diagram**
## **2.4.7. Dynamic Clock Select**
The Dynamic Clock Select (DCS) is a smart multiplexer function available in the primary clock routing. It switches between two independent input clock sources. Depending on the operational mode, it switches between two (2) independent input clock sources either with or without any glitches. This is achieved regardless of when the select signal is toggled. Both input clocks must be running to achieve a functioning glitchless DCS output clock, but running clocks are not required when used as a non-glitchless normal clock multiplexer.
There are one (1) or two (2) DCS blocks per device that feed all clock domains. The DCS blocks are located in the DCS_MUX block. The inputs to the DCS blocks come from MIDMUX outputs and user logic clocks through DCC elements. The DCS elements are located at the center of the PLC array core. The output of the DCS is connected to the inputs of Primary Clock Center MUXs (CMUX).
Figure 2.10 shows the timing waveforms of the default DCS operating mode. The DCS block can be programmed to other modes. For more information about the DCS, refer to sysCLOCK PLL Design and User Guide for Nexus Platform (FPGA-TN-02095).
© 2021-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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**CrossLink-NX Family Data Sheet**
**==> picture [421 x 187] intentionally omitted <==**
**----- Start of picture text -----**<br>
CLK0<br>clk0<br>pos<br>CLK1<br>FLL<br>clk1 clk1<br>pos neg<br>SEL<br>clk0<br>neg<br>DCSOUT<br>**----- End of picture text -----**<br>
**Figure 2.10. DCS Waveforms**
## **2.4.8. Dynamic Clock Control**
The Dynamic Clock Control (DCC), Domain Clock enable/disable feature allows internal logic control of the domain primary clock network. When a clock network is disabled, the clock signal is static and does not toggle. All the logic fed by that clock also does not toggle, reducing the overall power consumption of the device. The disable function is glitchless, and does not increase the clock latency to the primary clock network.
Four additional DCC elements control the clock inputs from the CrossLink-NX domain logic to the Center MUX elements (DSC_CMUX).
This DCC controls the clock sources from the Primary CLOCK MIDMUX before they are fed to the Primary Center MUXs that drive the domain clock network. For more information about the DCC, refer to sysCLOCK PLL Design and User Guide for Nexus Platform (FPGA-TN-02095).
## **2.4.9. DDRDLL**
CrossLink-NX has two identical DDRDLL blocks, located in the lower left and lower right corners of the device. Each DDRDLL (master DLL block) can generate a 9-bit phase shift value corresponding to a 90 degree phase shift of the reference clock input and provide this value to every DQS block and DLLDEL slave delay element. The reference clock can be either from a PLL, or an input pin. The DQSBUF uses this value to control the delay of the DQS inputs from a DDR memory interface to achieve a 90-degree shift in order to clock DQ inputs at the center of the data eye.
- The value is also sent to another slave DLL, DLLDEL, which takes a primary clock input and generates a 90-degree shifted clock output to drive the clocking structure. This is useful in an edge-aligned Generic DDR interface, where 90-degree clocking needs to be created. Not all primary clock inputs have associated DLLDEL control. Figure 2.11 shows DDRDLL connectivity to a DLLDEL block (connectivity to DQSBUF blocks is similar).
© 2021-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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**CrossLink-NX Family Data Sheet**
**==> picture [406 x 177] intentionally omitted <==**
**----- Start of picture text -----**<br>
To both BMID and<br>ECLKINMUX<br>PCLK Input<br>+<br>- DLLDEL<br>9 Right DDRDLL<br>9<br>Left DDRDLL<br>code1 code2<br>**----- End of picture text -----**<br>
**Figure 2.11. DLLDEL Functional Diagram**
Each DDRDLL can generate a delay value based on the reference clock frequency. The slave DLLs (DQSBUF and DLLDEL) use the value (code) to either create phase shifted inputs from the DDR memory or create a 90 degree shifted clock. Figure 2.12 shows the connections between the DDRDLL and the slave DLLs.
**==> picture [446 x 160] intentionally omitted <==**
**----- Start of picture text -----**<br>
Left Right<br>DDRDLL DDRDLL<br>Digital Delay Code (L) | | | Digital Delay Code (R)<br>Refclk Sel Refclk Sel<br>DLLDEL DLLDEL DQS0 DQS1 DLLDEL DQS0 DQS1<br>BANK5 ECLK BANK4 ECLK BANK3 ECLK<br>Figure 2.12. DDRDLL Architecture<br>i el nel<br>**----- End of picture text -----**<br>
## **2.5. SGMII Tx/Rx**
The CrossLink-NX device utilizes different components/resources for the transmit and receive paths of Serial Gigabit Media Independent Interface (SGMII). For the SGMII transmit path, generic DDR I/O with x5 gearing are used. For more information, refer to GDDRX5_TX.ECLK.Aligned Interface on the CrossLink-NX High-Speed I/O Interface (FPGA-TN02097).
For the SGMII receive path, one of the two available hardened CDR (Clock and Data Recovery) components can be used.
There are three main blocks in each CDR: the CDR, deserializer, and FIFO. Each CDR features two loops. The first loop is locked to the reference clock. Once locked, the loop switches to the data path loop where the CDR tracks the data signals to generate the correcting signals needed to achieve and maintain phase lock with the data. The data is then passed through a deserializer which deserialize the data to 10-bit parallel data. The 10-bit parallel data is then sent to the FIFO bridge, which allows the CDR to interface with the rest of the FPGA.
Figure 2.13 shows a block diagram of the SGMII CDR IP.
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**CrossLink-NX Family Data Sheet**
The two hardened blocks are located at the bottom left of the chip and uses the high speed I/O Bank 5 for the differential pair input. It is recommended that the reference clock should be entered through a GPIO that has connection to the PLL on the lower left corner as well.
For more information about how to implement the hardened CDR for SGMII solution, refer to the SGMII and Gb Ethernet PCS IP Core (FPGA-IPUG-02077).
**==> picture [396 x 244] intentionally omitted <==**
**----- Start of picture text -----**<br>
SGMII CDR IP<br>lmmi_dk<br>lmmi_request<br>lmmi_wrdn<br>lmmi_rdata[7:0]<br>lmmi_offset[3:0]<br>lmmi_rdata_valid<br>lmmi_wdata[7:0]<br>lmmi_ready<br>lmmi_reset<br>ip_ready<br>sgmii_cdr_icnst<1:0><br>rxd<9:0> sgmii_rxd<9:0><br>sgmii_in rxd_des<br>DUAL_LOOP<br>DESERIALIZER FIFO<br>CDR<br>rclk_des<br>dco_calib_rst<br>dco_facq_rst<br>rrst<br>sgmii_refclk(125 MHz) sgmii_pclk<br>sgmii_rclk<br>**----- End of picture text -----**<br>
**Figure 2.13. SGMII CDR IP**
## **2.6. sysMEM Memory**
CrossLink-NX devices contain a number of sysMEM Embedded Block RAM (EBR). The EBR consists of an 18 kb RAM with memory core, dedicated input registers and output registers as well as optional pipeline registers at the outputs. Each EBR includes functionality to support true dual-port, pseudo dual-port, single-port RAM, ROM and built in FIFO. In CrossLink-NX, unused EBR blocks is powered down to minimize power consumption.
## **2.6.1. sysMEM Memory Block**
The sysMEM block can implement single port, dual port or pseudo dual port memories. Each block can be used in a variety of depths and widths as listed in Table 2.4. FIFOs can be implemented using the built in read and write address counters and programmable full, almost full, empty and almost empty flags. The EBR block facilitates parity checking by supporting an optional parity bit for each data byte. EBR blocks provide byte-enable support for configurations with 18bit and 36-bit data widths. For more information, refer to Memory User Guide for Nexus Platform (FPGA-TN-02094).
EBR also provides a build in ECC engine, which is available in Commercial/Industrial –8 and –9 speed grades and Automotive –7 speed grade. The ECC engine supports a write data width of 32 bits and it can be cascaded for larger data widths such as x64. The ECC parity generator creates and stores parity data for each 32-bit word written. When a read operation is performed, it compares the data with its associated parity data and report back if any Single Event Upset (SEU) event has disturbed the data. Any single bit data disturb is automatically corrected at the data output. In addition, two dedicated error flags indicate if a single-bit or two-bit error has occurred.
© 2021-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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**CrossLink-NX Family Data Sheet**
## **Table 2.4. sysMEM Block Configurations**
|**Memory Mode**|**Configurations**|
|---|---|
|Single Port|16,384 × 1|
||8,192 × 2|
||4,096 × 4|
||2,048 × 9|
||1,024 × 18|
||512 × 36|
|True Dual Port|16,384 × 1|
||8,192 × 2|
||4,096 × 4|
||2,048 × 9|
||1,024 × 18|
|Pseudo Dual Port|16,384 × 1|
||8,192 × 2|
||4,096 × 4|
||2,048 × 9|
||1,024 × 18|
||512 × 36|
## **2.6.2. Bus Size Matching**
All of the multi-port memory modes support different widths on each of the ports (except ECC mode, which only supports a write data width of 32 bits). The RAM bits are mapped LSB word 0 to MSB word 0, LSB word 1 to MSB word 1, and so on. Although the word size and number of words for each port varies, this mapping scheme applies to each port.
## **2.6.3. RAM Initialization and ROM Operation**
If desired, the contents of the RAM can be pre-loaded during device configuration. By preloading the RAM block during the chip configuration cycle and disabling the write controls, the sysMEM block can also be utilized as a ROM.
## **2.6.4. Memory Cascading**
Larger and deeper blocks of RAM can be created using EBR sysMEM Blocks. Typically, the Lattice design tools cascade memory transparently, based on specific design inputs.
## **2.6.5. Single, Dual and Pseudo-Dual Port Modes**
In all the sysMEM RAM modes, the input data and address for the ports are registered at the input of the memory array. The output data of the memory is optionally registered at the output.
## **2.6.6. Memory Output Reset**
The EBR utilizes latches at the A and B output ports. These latches can be reset asynchronously or synchronously. RSTA and RSTB are local signals, which reset the output latches associated with Port A and Port B, respectively. The Global Reset (GSRN) signal can reset both ports. The output data latches and associated resets for both ports are as shown in Figure 2.14. The optional Pipeline Registers at the outputs of both ports are also reset in the same way.
© 2021-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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**CrossLink-NX Family Data Sheet**
**==> picture [350 x 222] intentionally omitted <==**
**----- Start of picture text -----**<br>
Memory Core D SET Q Port A[17:0]<br>a LCLR<br>Output Data<br> Latches<br>D SET Q Port B[17:0]<br>LCLR<br>_<br>RSTA<br>a Ee<br>RSTB<br>=> ><br>GSRN<br>=C ar<br>Programmable Disable<br>**----- End of picture text -----**<br>
**Figure 2.14. Memory Core Reset**
For further information on the sysMEM EBR block, see the list of technical documentation in Supplemental Information section.
## **2.7. Large RAM**
The CrossLink-NX device includes additional memory resources in the form of Large Random-Access Memory (LRAM) blocks.
The LRAM is designed to work as Single-Port RAM, Dual-Port RAM, Pseudo Dual-Port RAM, and ROM memories. It is meant to function as additional memory resources for users beyond what is available in the EBR and PFU.
Each individual Large RAM block contains 0.5 Mbits of memory, and has a programmable data width of up to 32 bits. Cascading Large RAM blocks allows data widths of up to 64 bits. Additionally, there is the ability to use either Error Correction Coding (ECC) or byte enable.
## **2.8. sysDSP**
The CrossLink-NX family provides an enhanced sysDSP architecture, making it ideally suited for low-cost, highperformance Digital Signal Processing (DSP) applications. Typical functions used in these applications are Finite Impulse Response (FIR) filters, Fast Fourier Transforms (FFT) functions, Correlators, Reed-Solomon/Turbo/Convolution encoders and decoders. These complex signal processing functions use similar building blocks such as multiply-adders and multiply-accumulators.
## **2.8.1. sysDSP Approach Compared to General DSP**
Conventional general-purpose DSP chips typically contain one to four (Multiply and Accumulate) MAC units with fixed data-width multipliers; this leads to limited parallelism and limited throughput. Their throughput is increased by higher clock speeds. In the CrossLink-NX device family, there are many DSP blocks that can be used to support different data widths. This allows users to use highly parallel implementations of DSP functions. You can optimize DSP performance versus area by choosing appropriate levels of parallelism. Figure 2.15 compares the fully serial implementation to the mixed parallel and serial implementation.
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**CrossLink-NX Family Data Sheet**
**==> picture [432 x 258] intentionally omitted <==**
**----- Start of picture text -----**<br>
Operand Operand Operand<br>A A A<br>Operand Operand Operand<br>B B B<br>Operand Operand<br>A B<br>X X X m/k<br>loops<br>Single M loops Multiplier Multiplier<br>Multiplier<br>Multiplier X 0 1 k<br>Accumulator<br>(k adds) +<br>Function Implemented in General<br>Purpose DSP<br>m/k<br>accumulate<br>Output<br>Function Implemented in<br>CrossLink-NX<br>**----- End of picture text -----**<br>
**Figure 2.15. Comparison of General DSP and CrossLink-NX Approaches**
## **2.8.2. sysDSP Architecture Features**
The CrossLink-NX sysDSP block contains two sysDSP slices. The CrossLink-NX sysDSP Slice has been significantly enhanced to provide functions needed for advanced processing applications. These enhancements provide improved flexibility and resource utilization.
The CrossLink-NX sysDSP block (two sysDSP slices) supports many functions that include the following:
- Symmetry support. The primary target application is wireless. 1D Symmetry is useful for many applications that use FIR filters when their coefficients have symmetry or asymmetry characteristics. The main motivation for using 1D symmetry is cost/size optimization. The expected size reduction is up to 2x.
- Odd Mode – Filter with Odd number of taps
- Even Mode – Filter with Even number of taps
- Two dimensional (2D) Symmetry Mode – Supports 2D filters for mainly video applications
- Dual-multiplier architecture. Lower accumulator overhead to half and the latency to half compared to single multiplier architecture.
- Fully cascadable DSP across slices. Support for symmetric, asymmetric and non-symmetric filters.
- Multiply (36 × 36, two 18 × 36, four 18 × 18 or eight 9 × 9)
- Multiply Accumulate (supports one 18 × 36 multiplier result accumulation, two 18 × 18 multiplier result accumulation or four 9 × 9 multiplier result accumulation)
- Two Multiplies feeding one Accumulate per cycle for increased processing with lower latency (two 18 × 18 Multiplies feed into an accumulator that can accumulate up to 54 bits)
- Pipeline registers
- 1D Symmetry support. The coefficients of FIR filters have symmetry or negative symmetry characteristics.
- Odd Mode – Filter with Odd number of taps
- Even Mode – Filter with Even number of taps
© 2021-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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**CrossLink-NX Family Data Sheet**
- 2D Symmetry support. The coefficients of 2D FIR filters have symmetry or negative symmetry characteristics.
- 3 × 3 and 3 × 5 – Internal DSP Slice support
- 5 × 5 and larger size 2D blocks – Semi internal DSP Slice support
- Flexible saturation and rounding options to satisfy a diverse set of applications situations
- Flexible cascading DSP blocks
- Minimizes fabric use for common DSP functions
- Enables implementation of FIR Filter or similar structures using dedicated sysDSP slice resources only
- Provides matching pipeline registers
- Can be configured to continue cascading from one row of sysDSP slices to another for longer cascade chains
- RTL Synthesis friendly synchronous reset on all registers, while still supporting asynchronous reset for legacy users
- • Dynamic MUX selection to allow Time Division Multiplexing (TDM) of resources for applications that require processor-like flexibility that enables different functions for each clock cycle
For most cases, as shown in Figure 2.16, the CrossLink-NX sysDSP block is backwards-compatible with the LatticeECP3™ sysDSP block, such that, legacy applications can be targeted to CrossLink-NX sysDSP. Figure 2.16 shows the diagram of sysDSP block.
**==> picture [429 x 324] intentionally omitted <==**
**----- Start of picture text -----**<br>
Input Input Input Input Input Input Input Input<br>B1 B1 B1 B1 B1 B1 B1 B1<br>Input |} Input Input tf Input j Input | Input J Input fj) Input Input ty} Input Input | Input Input |) Input Input Input<br>C B2 C B2 C B2 C B2 C B2 C B2 C B2 C B2<br>9 + 9 9 + 9 9 + 9 9 + 9 9 + 9 9 + 9 9 + 9 9 + 9<br>Input REG Input REG Input REG Input REG Input REG Input REG Input REG Input REG<br>A1 A1 A1 A1 A1 A1 A1 A1<br>Input Input Input Input Input Input Input Input<br>A2 A2 A2 A2 A2 A2 A2 A2<br>9 x 9 9 x 9 9 x 9 9 x 9 9 x 9 9 x 9 9 x 9 9 x 9<br>COCQCICSCQCQCDOS<br>18 X 18 18 X 18 18 X 18 18 X 18<br>rr re ee<br>18 X 36 (CSA) 18 X 36 (CSA)<br>ee<br>36 X 36 (CSA)<br>Pod<br>REG 18 REG 18 REG 18 REG 18 REG 18 REG 18 REG 18 REG 18<br>[| J J Jf JT J J J<br>ACC54 ACC54<br>ee<br>Output Register Output Register<br>a<br>Note : All Registers inside the DSP Block are Bypassable via Configuration Setting<br>**----- End of picture text -----**<br>
**Figure 2.16. DSP Functional Block Diagram**
The CrossLink-NX sysDSP block supports the following basic elements.
- MULT (Multiply)
- MAC (Multiply, Accumulate)
- MULTADDSUB (Multiply, Addition/Subtraction)
- MULTADDSUBSUM (Multiply, Addition/Subtraction, Summation)
© 2021-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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**CrossLink-NX Family Data Sheet**
Table 2.5 shows the capabilities of CrossLink-NX sysDSP block versus the above functions.
**Table 2.5. Maximum Number of Elements in a sysDSP block**
|**Width of Multiply**|**x9**|**x18**|**x36**|
|---|---|---|---|
|MULT|8|4|1|
|MAC|2|2|—|
|MULTADDSUB|2|2|—|
|MULTADDSUBSUM|2|2|—|
Some options are available in the four elements. The input register in all the elements can be directly loaded or can be loaded as a shift register from previous operand registers. By selecting _dynamic operation,_ the following operations are possible:
- In the Add/Sub option, the Accumulator can be switched between addition and subtraction on every cycle.
- The loading of operands can switch between parallel and serial operations.
For further information, refer to sysDSP User Guide for Nexus Platform (FPGA-TN-02096).
## **2.9. Programmable I/O (PIO)**
The programmable logic associated with an I/O is called a PIO. The individual PIO are connected to their respective sysI/O buffers and pads.
On all CrossLink-NX devices, two adjacent PIO can be combined to provide a complementary output driver pair.
## **2.10. Programmable I/O Cell (PIC)**
The programmable I/O cells (PIC) provides I/O function and necessary gearing logic associated with PIO. CrossLink-NX consists of base PIC and gearing PIC.
Base PICs contain three blocks: an input register block, output register block, and tri-state register block. These blocks contain registers for operating in a variety of modes along with the necessary clock and selection logic. Base PICs cover the top and left/right bank. Gearing PICs contain gearing logic and edge monitor used for locating the center of data window. Gearing PICs cover the bottom banks to support DDR operation.
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**CrossLink-NX Family Data Sheet**
**==> picture [289 x 275] intentionally omitted <==**
**----- Start of picture text -----**<br>
PIC<br>PIO A<br>Input<br>Register<br>Block<br>Output and<br>Tristate Pin<br>1 +h Register L A<br>Block<br>Core<br>Logic/ Input and Output<br>Routing Gearbox<br>PIO B<br>Input<br>Register<br>Block<br>Output and<br>Tristate Pin<br>Register ) | B<br>= Block<br>1 |Ld}<br>**----- End of picture text -----**<br>
**Figure 2.17. Group of Two High Performance Programmable I/O Cells**
**==> picture [369 x 275] intentionally omitted <==**
**----- Start of picture text -----**<br>
PIC<br>PIO A<br>Input<br>Register<br>Block<br>Output and<br>Tristate Pin<br>:ER Register A<br>i Block<br>Core<br>Logic/<br>Routing<br>=<br>PIO B<br>Input<br>Register<br>Block<br>Output and<br>ee. Tristate Pin<br>Register B<br>Block<br>—5<br>**----- End of picture text -----**<br>
**Figure 2.18. Wide Range Programmable I/O Cells**
© 2021-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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FPGA-DS-02049-1.8
**CrossLink-NX Family Data Sheet**
## **2.10.1. Input Register Block**
The input register blocks for the PIO on all edges contain delay elements and registers that can be used to condition high-speed interface signals before they are passed to the device core. In addition, the input register blocks for the PIO on the bottom edges include built-in FIFO logic to interface to DDR and LPDDR memory.
The Input register block on the bottom side includes gearing logic and registers to implement IDDRX1, IDDRX2, IDDRX4, IDDRX5 gearing functions. With two PICs sharing the DDR register path, it can also implement the IDDRX71 function used for 7:1 LVDS interfaces. It uses three sets of registers – shift, update, and transfer to implement gearing and the clock domain transfer. The first stage registers sample the high-speed input data by the high-speed edge clock on its rising and falling edges. The second stage registers perform data alignment based on the control signals. The third stage pipeline registers pass the data to the device core synchronized to the low-speed system clock. For more information on gearing function, refer to CrossLink-NX High-Speed I/O Interface (FPGA-TN-02097).
## **Input FIFO**
The CrossLink-NX PIO has a dedicated input FIFO per single-ended pin for input data register for DDR Memory interfaces. The FIFO resides before the gearing logic. It transfers data from DQS domain to continuous ECLK domain. On the Write side of the FIFO, it is clocked by DQS clock, which is the delayed version of the DQS Strobe signal from DDR memory. On the Read side of FIFO, it is clocked by ECLK. ECLK may be any high-speed clock with identical frequency as DQS (the frequency of the memory chip). Each DQS group has one FIFO control block. It distributes FIFO read/write pointers to every PIC in same DQS group. DQS Grouping and the DQS Control Block is described in DDR Memory Support section.
**Table 2.6. Input Block Port Description**
|**Name**|**Type **|**Description**|
|---|---|---|
|D|Input|High Speed Data Input|
|Q[1:0]/Q[3:0]/Q[6:0]/Q[7:0]/Q[9:0]|Output|Low Speed Data to the device core|
|RST|Input|Reset to the Output Block|
|SCLK|Input|Slow Speed System Clock|
|ECLK|Input|High Speed Edge Clock|
|DQS|Input|Clock from DQS control Block used to clock DDR memorydata|
|ALIGNWD|Input|Data Alignment signal from device core.|
Figure 2.19 shows the input register block for the PIO on the top, left, and right edges.
**==> picture [442 x 111] intentionally omitted <==**
**----- Start of picture text -----**<br>
INCK<br>D Programmable INFF<br>Delay Cell<br>INFF Q<br>SCLK IDDRX1 Q[1:0]<br>RST<br>**----- End of picture text -----**<br>
**Figure 2.19. Input Register Block for PIO on Top, Left, and Right Sides of the Device**
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**CrossLink-NX Family Data Sheet**
Figure 2.20 shows the input register block for the PIO located on the bottom edge.
**==> picture [393 x 175] intentionally omitted <==**
**----- Start of picture text -----**<br>
IN CK<br>IN FF<br>Programmable<br>D<br>Delay Cell<br>IN FF Q<br>Generic<br>IDDRX1<br>FIFO IDDRX2 Q[1:0]/<br>IDDRX4 Q[3:0]/<br>Delayed DQS ECLK IDDRX5 Q[6:0]*/<br>IDDRX71* Q[7:0]/<br>Q[9:0]<br>Memory<br>ECLK<br>IDDRX2<br>SCLK IDDRX4<br>RST<br>ALIGNWD<br>**----- End of picture text -----**<br>
*For 7:1 LVDS interface only. It is required to use PIO pair pins (PIOA/B or PIOC/D).
**Figure 2.20. Input Register Block for PIO on Bottom Side of the Device**
## **2.10.2. Output Register Block**
The output register block registers signals from the core of the device before they are passed to the sysI/O buffers.
The CrossLink-NX output data path has programmable registers and output gearing logic. On the bottom side, the output register block can support 1x, 2x, x4, x5, and 7:1 gearing enabling high speed DDR and DDR memory interfaces. On the top, left, and right sides, the banks support 1x gearing. The CrossLink-NX output data path diagram is shown in Figure 2.21. The programmable delay cells are also available in the output data path.
For a detailed description of the output register block modes and usage, refer to CrossLink-NX High-Speed I/O Interface (FPGA-TN-02097).
**==> picture [440 x 113] intentionally omitted <==**
**----- Start of picture text -----**<br>
Programmable<br>D Delay Cell Q<br>OUTFF<br>RST<br>SCLK Generic<br>ODDRX1<br>D[1:0]<br>**----- End of picture text -----**<br>
**Figure 2.21. Output Register Block on Top, Left, and Right Sides**
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**CrossLink-NX Family Data Sheet**
||D<br>RST<br>SCLK<br>ECLK<br>DQSW<br>DQSW270<br>Q[1:0]/<br>Q[3:0]/<br>Q[6:0]*/<br>Q[7:0]/|Generic<br>ODD RX1/<br>ODD RX2/<br>ODD R71*<br>Memory<br>ODD RX2<br>OSHX2<br>ODD RX4<br>Programmable<br>Delay Cell<br>OUTFF<br>ODD RX4<br>ODD RX5<br>~~Tea)~~<br>~~Mt~~|Generic<br>ODD RX1/<br>ODD RX2/<br>ODD R71*<br>Memory<br>ODD RX2<br>OSHX2<br>ODD RX4<br>Programmable<br>Delay Cell<br>OUTFF<br>ODD RX4<br>ODD RX5<br>~~Tea)~~<br>~~Mt~~|Generic<br>ODD RX1/<br>ODD RX2/<br>ODD R71*<br>Memory<br>ODD RX2<br>OSHX2<br>ODD RX4<br>Programmable<br>Delay Cell<br>OUTFF<br>ODD RX4<br>ODD RX5<br>~~Tea)~~<br>~~Mt~~|Generic<br>ODD RX1/<br>ODD RX2/<br>ODD R71*<br>Memory<br>ODD RX2<br>OSHX2<br>ODD RX4<br>Programmable<br>Delay Cell<br>OUTFF<br>ODD RX4<br>ODD RX5<br>~~Tea)~~<br>~~Mt~~|Generic<br>ODD RX1/<br>ODD RX2/<br>ODD R71*<br>Memory<br>ODD RX2<br>OSHX2<br>ODD RX4<br>Programmable<br>Delay Cell<br>OUTFF<br>ODD RX4<br>ODD RX5<br>~~Tea)~~<br>~~Mt~~|Q|
|---|---|---|---|---|---|---|---|
||Q[9:0]|||||||
||*For 7:1 LVDS interface only. It is required to use PIO pair pins PIOA/B.||*For 7:1 LVDS interface only. It is required to use PIO pair pins PIOA/B.|||||
|||||**Figure 2.22. Output Register Block on Bottom Side**||||
|**Table 2.7. Out**|**Table 2.7. Output Block Port Description**|||||||
|**Name**||||**Type**||**Description**||
|Q||||Output<br>High Speed Data Output||||
|D||||Input||Data from core to output SDR register||
|Q[1:0]/Q[3:0]/Q[6:0]/Q[7:0]/Q[9:0]||||Input||Low Speed Data from device core to output DDR register||
|RST||||Input||Reset to the Output Block||
|SCLK|SCLK|||Input||Slow Speed System Clock||
|ECLK|ECLK|||Input||High Speed Edge Clock||
|DQSW||||Input||Clock from DQS control Block used to generate DDR memory DQS output||
|DQSW270||||Input||Clock from DQS control Block used to generate DDR memory DQ output|Clock from DQS control Block used to generate DDR memory DQ output|
**Table 2.7. Output Block Port Description**
## **2.11. Tri-state Register Block**
The tri-state register block registers tri-state control signals from the core of the device before they are passed to the sysI/O buffers. The block contains a register for SDR operation. In SDR, the TD input feeds one of the flip-flops that then feeds the output. In DDR, operations used mainly for DDR memory interfaces can be implemented on the bottom side of the device. Here, two inputs feed the tri-state registers clocked by both ECLK and SCLK.
Figure 2.23 and Figure 2.24 show the Tri-state Register Block functions on the device. For a detailed description of the tri-state register block modes and usage, refer to CrossLink-NX High-Speed I/O Interface (FPGA-TN-02097).
**==> picture [298 x 84] intentionally omitted <==**
**----- Start of picture text -----**<br>
TQ<br>TD<br>RST TSFF<br>SCLK<br>po<br>Figure 2.23. Tri-state Register Block on Top, Left, and Right Sides<br>**----- End of picture text -----**<br>
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**CrossLink-NX Family Data Sheet**
**==> picture [332 x 239] intentionally omitted <==**
**----- Start of picture text -----**<br>
TQ<br>TD<br>TSFF<br>RST<br>SCLK<br>ECLK<br>THSX2<br>DQSW —_—__>»<br>DQSW270 ——__>»<br>T[1:0] ———_——_>»<br>**----- End of picture text -----**<br>
**Figure 2.24. Tri-state Register Block on Bottom Side**
**Table 2.8. Tri-state Block Port Description**
|**Name**|**Type**|**Description**|
|---|---|---|
|TD|Input|Tri-state Input to Tri-state SDR Register|
|RST|Input|Reset to the Tri-state Block|
|T[1:0]|Input|Tri-state input to TSHX2 function|
|SCLK|Input|Slow Speed System Clock|
|ECLK|Input|High Speed Edge Clock|
|DQSW|Input|Clock from DQS control Block used to generate DDR memory DQS output|
|DQSW270|Input|Clock from DQS control Block used to generate DDR memory DQ output|
|TQ|Output|Output of the Tri-state block|
## **2.12. DDR Memory Support**
## **2.12.1. DQS Grouping for DDR Memory**
Certain PICs have additional circuitry to allow the implementation of high-speed source synchronous and DDR3/DDR3L, LPDDR2 or LPDDR3 memory interfaces. The support varies by the edge of the device as detailed below.
PICs on the bottom side have fully functional elements supporting DDR3/DDR3L, LPDDR2, or LPDDR3 memory interfaces. Every 16 PIO on the bottom side are grouped into one DQS group, as shown in Figure 2.25. Within each DQS group, there are two pre-placed pins for DQS and DQS# signals. The rest of the pins in the DQS group can be used as DQ signals and DM signal. The number of pins in each DQS group bonded out is package dependent. DQS groups with less than 11 pins bonded out can only be used for LPDDR2/3 Command/ Address busses. In DQS groups with more than 11 pins bonded out, up to two pre-defined pins are assigned to be used as virtual VCCIO, by driving them high to make extra connections to the VCCIO power supply. These soft connections to VCCIO help reduce SSO noise. For details, refer to CrossLink-NX High-Speed I/O Interface (FPGA-TN-02097).
© 2021-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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**CrossLink-NX Family Data Sheet**
**==> picture [415 x 382] intentionally omitted <==**
**Figure 2.25. DQS Grouping on the Bottom Edge**
## **2.12.2. DLL Calibrated DQS Delay and Control Block (DQSBUF)**
To support DDR memory interfaces (DDR3/DDR3L, LPDDR2/3), the DQS strobe signal from the memory must be used to capture the data (DQ) in the PIC registers during memory reads. This signal is output from the DDR memory device aligned to data transitions and must be time shifted before it can be used to capture data in the PIC. This time shift is achieved by using the DQSBUF programmable delay line in the DQS Delay Block (DQS read circuit). The DQSBUF is implemented as a slave delay line and works in conjunction with a master DDRDLL.
This block also includes a slave delay line to generate delayed clocks used during writes to generate DQ and DQS with correct phases within one DQS group. There is a third delay line inside this block used to provide write leveling for DDR write if needed.
Each of the read and write side delays can be dynamically shifted using margin control signals from the core logic.
The FIFO Control Block included here generates the Read and Write Pointers for the FIFO inside the Input Register Block. These pointers are generated to control the DQS to ECLK domain crossing using the FIFO module.
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**CrossLink-NX Family Data Sheet**
**==> picture [413 x 215] intentionally omitted <==**
**----- Start of picture text -----**<br>
DQS BURST_DET<br>Preamble/Postamble Management<br>READ[1:0]<br>|<br>READ_CLK_SEL[2:0]<br>SCLK FIFO Control and Data Valid WRPNTR[2:0]<br>Generation RDPNTR[2:0]<br>ECLK<br>a DATAVALID<br>DQSR90<br>RD_CODN, RD_DIRECTION, RD_MOVE Slave Delay Line (RD) with RD_cout<br>Adjustment/Margin Test<br>|<br>WR_COUT<br>WRITE_LEVELING_LOADN<br>WRITE_LEVELING_DIRECTION DQSW270<br>WRITE_LEVELING_MOVE Slave Delay (WR) with<br>Adjustment/Margin Test and Write Leveling DQSW<br>WR_LOADN, WR_DIRECTION, WR_MOVE<br>DELAYCODE_I[8:0]<br>RST<br>DELAYCODE_O[8:0]<br>DONE_GWE<br>GSR<br>**----- End of picture text -----**<br>
**Figure 2.26. DQS Control and Delay Block (DQSBUF)**
**Table 2.9. DQSBUF Port List Description**
|**Name**<br>~~eG~~|**Type**<br>~~eG~~|**Description**<br>~~eG~~|
|---|---|---|
|DQS<br>~~a~~|Input|DDR memory DQS strobe|
|READ[1:0]<br>~~ee~~|Input<br>~~ee~~|Read Input from DDR Controller<br>~~ee~~|
|READCLKSEL[2:0]<br>~~eG~~|Input<br>~~eG~~|Read pulse selection<br>~~eG~~|
|SCLK<br>~~eG~~<br>~~ee~~|Input<br>~~eG~~<br>~~ee~~|Slow System Clock<br>~~eG~~<br>~~ee~~|
|ECLK<br>~~eG~~|Input<br>~~eG~~|High Speed Edge Clock (same frequency as DDR memory)<br>~~eG~~|
|RDLOADN, RDMOVE, RDDIRECTION<br>~~eG~~<br>~~a~~|Input<br>~~eG~~|Dynamic Margin Control ports for Read delay<br>~~eG~~|
|WRLOADN, WRMOVE, WRDIRECTION<br>~~eG~~|Input<br>~~eG~~|Dynamic Margin Control ports for Write delay<br>~~eG~~|
|DELAYCODE_I[8:0]<br>~~eG~~<br>~~ee~~<br>~~a~~|Input<br>~~eG~~<br>~~ee~~<br>~~ee~~|Dynamic Delay Control<br>~~eG~~<br>~~ee~~<br>~~ee~~|
|WRITE_LEVELING_LOADN,<br>WRITE_LEVELING_DIRECTION,<br>WRITE_LEVELING_MOVE<br>~~es~~<br>~~a~~|Input<br>~~es~~<br>~~ee~~|Write Leveling Control<br>~~es~~<br>~~ee~~|
|DQSR90<br>~~a~~|Output<br>~~ee~~|90 delay DQS used for Read<br>~~ee~~<br>~~G~~|
|DQSW270<br>~~a~~<br>~~ee~~|Output<br>~~ee~~<br>~~ee~~|90 delay clock used for DQ Write<br>~~ee~~<br>~~G~~<br>~~ee~~|
|DQSW<br>~~eG~~|Output<br>~~eG~~|Clock used for DQS Write<br>~~eG~~|
|RDPNTR[2:0]<br>~~eG~~<br>~~eG~~<br>~~ee~~|Output<br>~~eG~~<br>~~eG~~<br>~~ee G~~|Read Pointer for IFIFO module<br>~~eG~~<br>~~eG~~<br>~~G~~|
|WRPNTR[2:0]<br>~~eG~~<br>~~ee~~|Output<br>~~eG~~<br>~~ee G~~|Write Pointer for IFIFO module<br>~~eG~~<br>~~G~~|
|DATAVALID<br>~~ee~~<br>~~eG~~|Output<br>~~ee G~~<br>~~eG~~|Signal indicating start of valid data<br>~~G~~<br>~~eG~~|
|BURSTDET<br>~~eG~~<br>~~a~~|Output<br>~~eG~~|Burst Detect indicator<br>~~eG~~|
|RD_COUT<br>~~a~~|Output<br>~~G~~|Read Count<br>~~G~~|
|WR_COUT<br>~~eG~~|Output<br>~~eG~~|Write Count<br>~~eG~~|
|DELAYCODE_O[8:0]<br>~~eG~~<br>~~a~~|Output<br>~~eG~~|Dynamic Delay Control<br>~~eG~~|
© 2021-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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**CrossLink-NX Family Data Sheet**
## **2.13. sysI/O Buffer**
Each I/O is associated with a flexible buffer referred to as a sysI/O buffer. These buffers are arranged around the periphery of the device in groups referred to as banks. The sysI/O buffers allow users to implement a wide variety of standards that are found in today’s systems including LVDS, HSUL, SSTL Class I and II, LVCMOS, LVTTL, and MIPI.
The CrossLink-NX family contains multiple Programmable I/O Cell (PIC) blocks. Each PIC contains two Programmable I/O, PIOA and PIOB. Each PIO includes a sysI/O buffer and I/O logic. Two adjacent PIO can be joined to provide a differential I/O pair referred to as True and Comp, where True Pad is associated with the positive side of the differential I/O, and the complement with the negative.
The top, left and right side banks support I/O standards from 3.3 V to 1.0 V while the bottom supports I/O standards from 1.8 V to 1.0 V. Every pair of I/O on the bottom bank also have a true LVDS and SLVS Tx Driver. In addition, the bottom bank supports single-ended input termination. Both static and dynamic termination are supported. Dynamic termination is used to support the DDR/LPDDR interface standards. For more information about DDR implementation in I/O Logic and DDR memory interface support, refer to CrossLink-NX High-Speed I/O Interface (FPGA-TN-02097).
## **2.13.1. Supported sysI/O Standards**
CrossLink-NX sysI/O buffers support both single-ended differential and differential standards. Single-ended standards can be further subdivided into internally ratioed standards such as LVCMOS, LVTTL, and externally referenced standards such as HSUL and SSTL. The buffers support the LVTTL, LVCMOS 1.0 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V, and 3.3 V standards. Differential standards supported include LVDS, SLVS, differential LVCMOS, differential SSTL, and differential HSUL. For better support of video standards, subLVDS and MIPI_D-PHY are also supported. Table 2.10 and Table 2.11 provide a list of sysI/O standards supported in CrossLink-NX devices.
**Table 2.10. Single-Ended I/O Standards**
|**Standard**<br>~~C(O~~|**Input**<br>~~C(O~~|**Output**<br>~~C(O~~|**Bi-directional**<br>~~C(O~~|
|---|---|---|---|
|LVTTL33<br>~~a~~|Yes|Yes|Yes|
|LVCMOS33<br>~~CO~~|Yes<br>~~CO~~|Yes<br>~~CO~~|Yes<br>~~CO~~|
|LVCMOS25<br>~~OO~~|Yes<br>~~OO~~|Yes<br>~~OO~~|Yes<br>~~OO~~|
|LVCMOS18<br>~~OO~~<br>~~a~~|Yes<br>~~OO~~|Yes<br>~~OO~~|Yes<br>~~OO~~|
|LVCMOS15<br>~~a~~<br>~~a~~|Yes|Yes|Yes|
|LVCMOS12<br>~~a~~|Yes|Yes|Yes|
|LVCMOS10<br>~~a~~|Yes|No|No<br>~~G~~|
|HTSL15 I<br>~~a~~|Yes|Yes|Yes|
|SSTL 15 I<br>~~a~~<br>~~a~~|Yes|Yes|Yes|
|SSTL 135 I<br>~~a~~<br>~~a~~|Yes|Yes|Yes|
|HSUL12<br>~~a~~|Yes|Yes|Yes|
|LVCMOS18H<br>~~a~~|Yes|Yes|Yes|
|LVCMOS15H<br>~~a~~|Yes|Yes|Yes|
|LVCMOS12H<br>~~a~~<br>~~a~~|Yes|Yes|Yes|
|LVCMOS10H<br>~~a~~<br>~~a~~|Yes|Yes|Yes|
|LVCMOS10R<br>~~CD~~|Yes<br>~~CD~~|—<br>~~CD~~|Yes1<br>~~CD~~|
**Note:**
1. Output supported by LVCMOS10H.
© 2021-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02049-1.8
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**CrossLink-NX Family Data Sheet**
**Table 2.11. Differential I/O Standards**
|**Standard**|**Input**|**Output**|**Bi-directional**|
|---|---|---|---|
|LVDS<br>~~CC~~|Yes<br>~~CC~~|Yes<br>~~CC~~|Yes<br>~~CC~~|
|SUBLVDS<br>~~a ~~|Yes<br> ~~GO~~|No<br>~~GO~~|—<br>~~GO~~|
|SLVS<br>~~a~~|Yes|Yes|—|
|SUBLVDSE<br>~~a~~<br>~~a ~~|—<br> ~~GO~~|Yes<br>~~GO~~|—<br>~~GO~~|
|SUBLVDSEH<br>~~a~~|—|Yes|—|
|LVDSE<br>~~CC~~|—<br>~~CC~~|Yes<br>~~CC~~|—<br>~~CC~~|
|MIPI_D-PHY<br>~~CO~~|Yes<br>~~CO~~|Yes<br>~~CO~~|Yes<br>~~CO~~|
|HSTL15D_I<br>~~CO~~|Yes<br>~~CO~~|Yes<br>~~CO~~|Yes<br>~~CO~~|
|SSTL15D_I<br>~~CO~~<br>~~a ~~|Yes<br>~~CO~~<br> ~~GO~~|Yes<br>~~CO~~<br>~~GO~~|Yes<br>~~CO~~<br>~~GO~~|
|SSTL15D_II<br>~~a~~|Yes|Yes|Yes|
|SSTL135D_I<br>~~a ~~|Yes<br> ~~GC~~|Yes<br>~~GC~~|Yes<br>~~GC~~|
|SSTL135D_II<br>~~CC~~|Yes<br>~~CC~~|Yes<br>~~CC~~|Yes<br>~~CC~~|
|HSUL12D<br>~~CO~~|Yes<br>~~CO~~|Yes<br>~~CO~~|Yes<br>~~CO~~|
|LVTTL33D<br>~~CO~~<br>~~a ~~|—<br>~~CO~~<br> ~~GO~~|Yes<br>~~CO~~<br>~~GO~~|—<br>~~CO~~<br>~~GO~~|
|LVCMOS33D<br>~~OO~~|—<br>~~OO~~|Yes<br>~~OO~~|—<br>~~OO~~|
|LVCMOS25D<br>~~CD~~|—<br>~~CD~~|Yes<br>~~CD~~|—<br>~~CD~~|
## **2.13.2. sysI/O Banking Scheme**
CrossLink-NX devices have up to eight banks in total. For 40K device, there are one bank on top, two banks each at left and right side of device, and three on the bottom side of device. For 17k device, one bank on top, one on right side and three on the bottom side of device. The higher density CrossLink-NX device has more pins in each bank. Bank 0, Bank 1, Bank 2, Bank 6, and Bank 7 support up to VCCIO 3.3 V while Bank 3, Bank 4, and Bank 5 support up to VCCIO 1.8 V. In addition, Bank 3, Bank 4, and Bank 5 support two VREF inputs for flexibility to receive two different referenced input levels on the same bank. Figure 2.27 shows the location of each bank.
© 2021-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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**CrossLink-NX Family Data Sheet**
**==> picture [397 x 279] intentionally omitted <==**
**----- Start of picture text -----**<br>
VCCIO(0)<br>GND<br>-<br>Bank 0<br>GND GND<br>VCCIO(7) Bank 7* Bank 1 VCCIO(1)<br>t F<br>GND GND<br>VCCIO(6) Bank 6* Bank 2* VCCIO(2)<br>Bank 5 Bank 4 Bank 3<br>oe<br>GND GND GND<br>TT TT MM<br>VCCIO(5) VREF1(5) VREF2(5) VCCIO(4) VREF1(4) VREF2(4) VCCIO(3) VREF1(3) VREF2(3)<br>**----- End of picture text -----**<br>
**==> picture [120 x 6] intentionally omitted <==**
**----- Start of picture text -----**<br>
*Note: Bank not available in LIFCL-17.<br>**----- End of picture text -----**<br>
**Figure 2.27. sysI/O Banking**
## **Typical sysI/O Behavior During Power-up**
The internal Power-On-Reset (POR) signal is deactivated when VCC and VCCAUX have reached satisfactory levels. After the POR signal is deactivated the FPGA core logic becomes active. It is the responsibility of the user to ensure that all other VCCIO banks are active with valid input logic levels to properly control the output logic states of all the I/O banks that are critical to the application. For more information about controlling the output logic state with valid input logic levels during power-up in CrossLink-NX devices, see the list of technical documentation in Supplemental Information section.
VCC and VCCAUX supply the power to the FPGA core fabric, whereas VCCIO supplies power to the I/O buffers. In order to simplify the system design while providing consistent and predictable I/O behavior, it is recommended that the I/O buffers be powered-up prior to the FPGA core fabric. For the different power supply voltage levels supported by the I/O banks, refer to sysI/O User Guide for Nexus Platform (FPGA-TN-02067) for detailed information.
## **VREF1 and VREF2**
Bank 3, Bank 4, and Bank 5 can support two separate VREF input voltages, VREF1, and VREF2. To assign a VREF driver, use IO_Type = VREF1_DRIVER or VREF2_DRIVER. To assign VREF to a buffer, use VREF1_LOAD or VREF2_LOAD.
## **sysI/O Standards Supported by I/O Bank**
All banks can support multiple I/O standards under the VCCIO rules discussed above. Table 2.12 and Table 2.13 summarize the I/O standards supported on various sides of the CrossLink-NX device.
© 2021-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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**CrossLink-NX Family Data Sheet**
**Table 2.12. Single-Ended I/O Standards Supported on Various Sides**
|**Standard**<br>~~(CO~~|**Top**<br>~~(CO~~|**Left1**<br>~~(CO~~|**Right**<br>~~(CO~~|**Bottom**<br>~~(CO~~|
|---|---|---|---|---|
|LVTTL33<br>~~a~~|Yes|Yes|Yes|—|
|LVCMOS33<br>~~a~~<br>~~a~~|Yes|Yes|Yes|—|
|LVCMOS25<br>~~a~~|Yes|Yes|Yes|—|
|LVCMOS18<br>~~a~~<br>~~a~~<br>~~a~~|Yes|Yes|Yes|—|
|LVCMOS15<br>~~a~~|Yes|Yes|Yes|—|
|LVCMOS12<br>~~a~~<br>~~a~~|Yes<br>|Yes<br>|Yes<br>|—<br>|
|LVCMOS10<br>~~CC~~<br>~~a~~|Yes<br>~~CC~~|Yes<br>~~CC~~|Yes<br>~~CC~~|—<br>~~CC~~|
|LVCMOS18H<br>~~a~~|—|—|—|Yes|
|LVCMOS15H<br>~~a~~<br>~~a~~<br>~~a~~|—|—|—|Yes|
|LVCMOS12H<br>~~a~~<br>~~a~~|—|—|—|Yes|
|LVCMOS10H<br>~~a~~<br>~~a~~|—|—|—|Yes|
|LVCMOS10R<br>~~a~~<br>~~a~~<br>~~a~~|—|—|—|Yes|
|HTSL15 I<br>~~a~~|—|—|—|Yes|
|SSTL 15 I, II<br>~~a~~<br>~~a~~|—|—|—|Yes|
|SSTL 135 I, II<br>~~a~~|—<br>|—<br>|—<br>|Yes<br>|
|HSUL12<br>~~CC~~|—<br>~~CC~~|—<br>~~CC~~|—<br>~~CC~~|Yes<br>~~CC~~|
- **Note:** 1. Left bank is not available in LIFCL-17.
**Table 2.13. Differential I/O Standards Supported on Various Sides**
|**Standard**<br>~~a ~~|**Top**<br> ~~C(O~~|**Left1**<br>~~C(O~~|**Right**<br>~~C(O~~|**Bottom**<br>~~C(O~~|
|---|---|---|---|---|
|LVDS<br>~~a~~|—|—|—|Yes|
|SUBLVDS<br>~~a~~<br>~~a~~|—|—|—|Yes|
|SLVS<br>~~a~~|—|—|—|Yes|
|SUBLVDSE<br>~~a~~<br>~~ee~~|Yes<br>~~GG~~|Yes<br>~~GG~~|Yes<br>~~GG~~|—<br>~~GG~~|
|SUBLVDSEH<br>~~ee~~|—<br>~~GG~~|—<br>~~GG~~|—<br>~~GG~~|Yes<br>~~GG~~|
|LVDSE<br>~~ee~~<br>~~a~~|Yes<br>~~GG~~|Yes<br>~~GG~~|Yes<br>~~GG~~|—<br>~~GG~~|
|MIPI_D-PHY<br>~~a~~<br>~~a~~|—|—|—|Yes|
|HSTL15D_I<br>~~a~~<br>~~a~~|—|—|—|Yes|
|SSTL15D_I<br>~~a~~<br>~~ee~~|—<br>~~GG~~|—<br>~~GG~~|—<br>~~GG~~|Yes<br>~~GG~~|
|SSTL15D_II<br>~~ee~~|—<br>~~GG~~|—<br>~~GG~~|—<br>~~GG~~|Yes<br>~~GG~~|
|SSTL135D_I<br>~~ee~~<br>~~a~~|—<br>~~GG~~|—<br>~~GG~~|—<br>~~GG~~|Yes<br>~~GG~~|
|SSTL135D_II<br>~~a~~<br>~~a~~|—|—|—|Yes|
|HSUL12D<br>~~a~~<br>~~a~~|—|—|—|Yes|
|LVTTL33D<br>~~a~~<br>~~ee~~|Yes<br>~~GG~~|Yes<br>~~GG~~|Yes<br>~~GG~~|—<br>~~GG~~|
|LVCMOS33D<br>~~ee~~|Yes<br>~~GG~~|Yes<br>~~GG~~|Yes<br>~~GG~~|—<br>~~GG~~|
|LVCMOS25D<br>~~ee~~<br>~~a~~|Yes<br>~~GG~~|Yes<br>~~GG~~|Yes<br>~~GG~~|—<br>~~GG~~|
**Note:**
1. Left bank is not available in LIFCL-17.
## **Hot Socketing**
The CrossLink-NX devices have been carefully designed to ensure predictable behavior during power-up and powerdown. During power-up and power-down sequences, the I/O remain in tri-state until the power supply voltage is high enough to ensure reliable operation. In addition, leakage into I/O pins is controlled within specified limits. Bank 0, Bank 1, Bank 2, Bank 6, and Bank 7 wide range I/O (excluding MCLK/MCSN/MOSI/INITN/DONE) are hot socketable. Bank 3, Bank 4, and Bank 5 do not support hot socketing.
© 2021-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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**CrossLink-NX Family Data Sheet**
## **2.13.3. sysI/O Buffer Configurations**
This section describes the various sysI/O features available on the CrossLink-NX device. Refer to sysI/O User Guide for Nexus Platform (FPGA-TN-02067) for detailed information.
## **2.14. Analog Interface**
The CrossLink-NX family can provide an analog interface consisting of two Analog to Digital (ADC), three continuous time comparators, and an internal junction temperature monitoring diode. This feature is available in Commercial/Industrial –8 and –9 speed grades and Automotive –7 speed grade. The two ADCs can operate either sequentially or simultaneously.
## **2.14.1. Analog to Digital Converters**
The Analog to Digital Convertor is a 12-bit, 1 MSPS SAR (Successive Approximation Register) architecture converter. The ADC supports both continuous and single shot conversion modes.
Each ADC input can be selected among eight GPIO (General Purpose I/O) input pairs, one designated analog input pair, and three internal signals used to monitor voltage rails or an internal junction temperature sensing diode. The input signal can be converted in either uni-polar or bi-polar mode.
The reference voltage is selectable between the 1.2 V internal reference generator and an external reference. The ADC can convert up to a 1.8 V input signal with a 1.8 V external reference voltage. The ADC has an auto-calibration function which calibrates the gain and offset.
## **2.14.2. Continuous Time Comparators**
The continuous-time comparator can be used to monitor a dedicated input pair or a GPIO input pair. The output of the comparator is provided as continuous and latched outputs.
## **2.14.3. Internal Junction Temperature Monitoring Diode**
On-die junction temperature can be monitored using the internal junction temperature monitoring diode. The PTAT (proportional to absolute temperature) diode voltage can be monitored by the ADC to provide a digital temperature readout. Refer to ADC User Guide for Nexus Platform (FPGA-TN-02129) for more details.
## **2.15. IEEE 1149.1-Compliant Boundary Scan Testability**
All CrossLink-NX devices contain various ports that can be used for configuration, including a Test Access Port (TAP). This allows functional testing of the circuit board on which the device is mounted through a serial scan path that can access all critical logic nodes. Internal registers are linked internally, allowing test data to be shifted in and loaded directly onto test nodes, or test data to be captured and shifted out for verification. The test access port consists of dedicated I/O: TDI, TDO, TCK, and TMS. The test access port uses VCCIO1 for power supply. The test access port is supported for VCCIO1 = 1.8 V - 3.3 V.
For more information, refer to sysCONFIG User Guide for Nexus Platform (FPGA-TN-02099).
© 2021-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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**CrossLink-NX Family Data Sheet**
## **2.16. Device Configuration**
All CrossLink-NX devices contain two ports that can be used for device configuration. The Test Access Port (TAP), which supports bit-wide configuration, and the sysCONFIG port, support serial, quad, and byte configuration. The TAP supports both the IEEE Standard 1149.1 Boundary Scan specification and the IEEE Standard 1532 In-System Configuration specification. JTAG_EN is the only dedicated configuration pin. _PPROGRAMN/INITN/DONE_ are enabled by default, but can be turned into GPIO. The remaining sysCONFIG pins are used as dual function pins. Refer to sysCONFIG User Guide for Nexus Platform (FPGA-TN-02099) for more information about using the dual-use pins as general purpose I/O.
There are various ways to configure a CrossLink-NX device:
- JTAG (TAP)
- Master Serial Peripheral Interface (SPI) – to load from external SPI flash using x1, x2, or x4 (QSPI) interfaces.
- Inter-Integrated Circuit Bus (I[2] C)
- Improved Inter-Integrated Circuit Bus (I3C)
- Slave SPI from a system host
- Lattice Memory Mapped Interface (LMMI), refer to sysI/O User Guide for Nexus Platform (FPGA-TN-02067) for more details.
- JTAG, SSPI, MSPI, I[2] C, and I3C are supported for VCCIO = 1.8 V - 3.3 V
On power-up, based on the voltage level (high or low) of the PROGRAMN pin, the FPGA SRAM is configured by the appropriate sysCONFIG port. If PROGRAMN pin is _low_ , the FPGA is in Slave configuration mode (Slave SPI, Slave I[2] C or Slave I3C) and is waiting for the correct Slave Configuration port activation key. PROGRAMN must be driven high within 50 ns of the end of transmission of the Slave Configuration port activation key, that is, the deassertion of SCSN. If no slave port is declared active before the PROGRAMN pin is sensed HIGH, the FPGA is in Master SPI booting mode. In Master SPI booting mode, the FPGA boots from an external SPI flash. Once a configuration port is activated, it remains active throughout that configuration cycle. The IEEE 1149.1 port can be activated any time after power-up by enabling the JTAG_EN pin and sending the appropriate command through the TAP port.
## **2.16.1. Enhanced Configuration Options**
CrossLink-NX devices have enhanced configuration features such as:
- Early I/O release
- Bitstream Decryption
- Decompression Support
- Watchdog Timer support
- Dual and Multi-boot image support
Early I/O Release is a new configuration feature in which certain I/O banks are released earlier so that customer systems have minimal disruption. For more details, refer to sysCONFIG User Guide for Nexus Platform (FPGA-TN02099).
Watchdog Timer is a new configuration feature that helps users add a programmable timer option for timeout applications.
## **Dual-Boot and Multi-Boot Image Support**
Dual-boot and multi-boot images are supported for applications requiring reliable remote updates of configuration data for the system FPGA. After the system is running with a basic configuration, a new boot image can be downloaded remotely and stored in a separate location in the configuration storage device. Any time after the update the CrossLinkNX devices can be re-booted from this new configuration file. If there is a problem, such as corrupt data during download or incorrect version number with this new boot image, the CrossLink-NX device can revert back to the original backup golden configuration and try again. This all can be done without power cycling the system. For more information, refer to sysCONFIG User Guide for Nexus Platform (FPGA-TN-02099).
© 2021-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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**CrossLink-NX Family Data Sheet**
## **2.17. Single Event Upset (SEU) Handling**
CrossLink-NX devices are unique in that the underlying technology used to build these devices is much more robust and less prone to soft errors.
CrossLink-NX devices have an improved, hardware implemented, Soft Error Detection (SED) circuit which can be used to detect SRAM errors so they can be corrected. There are two layers of SED implemented in CrossLink-NX making it more robust and reliable.
The SED hardware in CrossLink-NX devices is part of the Configuration block. The SED module in CrossLink-NX is an enhanced version as compared to the SED modules implemented in other Lattice devices. The configuration data is divided into frames so that the entire FPGA can be programmed precisely with ease. The SED hardware reads data from the FPGAs configuration memory and performs an Error Correcting Code (ECC) calculation on every frame of configuration data (see Figure 2.1). Once an error is detected, a notification is generated and SED resumes operation. For single bit errors, the corrected value is rewritten to the particular frame using ECC information. If more than one-bit error is detected within one frame of configuration data, an error message is generated. CrossLink-NX devices also have dedicated logic to perform Cycle Redundancy Code (CRC) checks for the entire bitstream, which runs in parallel along with ECC.
After the ECC is calculated on all frames of configuration data, CRC is calculated and checked for the entire bitstream. ECC and CRC checks do not include the contents of RAMs (EBR, Large RAM, and distributed RAM).
For further information on SED support, refer to Soft Error Detection (SED)/Correction (SEC) User Guide for Nexus Platform (FPGA-TN-02076).
## **2.18. On-Chip Oscillator**
The CrossLink-NX device features two on board oscillators. Both Oscillators are controlled with internally generated current.
The Low Frequency Oscillator (LFOSC) is tailored for low power operation and runs at a nominal frequency of 128 kHz. The LFOSC always runs and can be used to perform always on functions with the lowest possible power. The High Frequency Oscillator (HFOSC) runs at a nominal frequency of 450 MHz, but can be divided down to a range of 256 MHz to 2 MHz by user attributes.
## **2.19. User I²C IP**
The CrossLink-NX device has one hard I[2] C interface, which can be configured either as a master (controller) or a slave (responder). The pins for the I²C interface are pre-assigned.
The interface core has the option to delay the either the input or the output data (SDA), or both, by 50 ns nominal, using dedicated on-chip delay elements. This provides an easier interface to any external I[2] C components. In addition, 50 ns glitch filters are available for both SDA and SCL.
When the IP interface is configured as master (controller), it is able to control other devices on the I[2] C bus through the pre-assigned pins. When the core is configured as a slave (responder), the device is able to provide, for example, I/O expansion to an I²C master (controller). The I²C core supports the following functionality:
- Master (controller) and Slave (responder) operation
- 7-bit and 10-bit addressing
- Multi-master (controller) arbitration support
- Clock stretching
- Up to 1 MHz data transfer speed (Standard-Mode, Fast-Mode, Fast-Mode Plus)
- General Call support
- Optional receive and transmit data FIFOs with programmable sizes
- Optionally 50 ns delay on input or output data (SDA), or both
- Hard-Connection and Programmable I/O Connection Support
- Programmable to a mode compliant with I3C requirements on legacy I[2] C Slave Devices.
- Fast-Mode and Fast-Mode Plus Support
© 2021-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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**CrossLink-NX Family Data Sheet**
- Disabled Clock Stretching
- 50 ns SCL and SDA Glitch Filters
- Programmable 7-bit Address
For further information on the User I²C, refer to I[2] C Hardened IP User Guide for Nexus Platform (FPGA-TN-02142)
## **2.20. Trace ID**
Each CrossLink-NX device contains a unique (per device) TraceID that can be used for tracking purposes or for IP security applications. The TraceID is 64 bits long. Eight out of 64 bits are user-programmable, the remaining 56 bits are factory-programmed. The TraceID is accessible through the SPI, I[2] C, or JTAG interfaces. For further information on TraceID, refer to Using TraceID (FPGA-TN-02084).
## **2.21. Density Shifting**
The CrossLink-NX family is designed to ensure that different density devices in the same family and in the same package have the same pinout. Furthermore, the architecture ensures a high success rate when performing design migration from lower density devices to higher density devices. In many cases, it is also possible to shift a low utilization design targeted for a high-density device to a lower density device. However, the exact details of the final resource utilization impact the likelihood of success in each case. An example is that some user I/O may become No Connects in smaller devices in the same package. Refer to the CrossLink-NX Pin Migration Tables and Lattice Radiant software for specific restrictions and limitations.
## **2.22. MIPI D-PHY Blocks**
The top side of the device includes two hardened MIPI D-PHYs. The hardened D-PHY can be configured to support either Camera Serial Interface (CSI-2) or Display Serial Interface (DSI) applications as either transmitter or receiver. Below is a summary of the features supported by the hardened D-PHYs.
- Transmit and receive compliant to the MIPI Alliance D-PHY specification version 1.2
- High-Speed (HS) and Low-Power (LP) mode support (including build-in contention detection)
- Supports continuous clock mode or low power (non-continuous) clock mode
- Up to 10 Gbps per D-PHY (2500 Mbps data rate per lane)
- Supports up to four data lanes and one clock lane per hardened D-PHY
CrossLink-NX’s programmable I/O can also be configured as soft MIPI D-PHYs. The soft D-PHY can be configured to support either Camera Serial Interface (CSI-2) or Display Serial Interface (DSI) applications as either transmitter or receiver. Below is a summary of the features supported by the soft D-PHY.
- Transmit and receive compatible to the MIPI Alliance D-PHY specification version 1.1
- High-Speed (HS) and Low-Power (LP) mode support (does not support contention detection)
- Supports continuous clock mode or low power (non-continuous) clock mode
- Up to 6 Gbps per port (1500 Mbps data rate per lane) in 121 csfBGA package
- Up to 5 Gbps per port (1250 Mbps data rate per lane) in other packages
- Supports up to four data lanes and one clock lane per port
© 2021-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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**CrossLink-NX Family Data Sheet**
## **2.23. Peripheral Component Interconnect Express (PCIe)**
The CrossLink-NX-40 Device features one lane of hardened PCIe on the top side of the device. The PCIe block implements all three layers defined by the PCI Express Specification: Physical, Data Link, and Transaction as shown in Figure 2.28. Below is a summary of the features supported by the PCIe block:
- Gen 1 (2.5 Gbps) and Gen 2 (5.0 Gbps) speed
- PCIe Express Base Specification 3.0 compliant including compliance with earlier PCI Express Specifications
- Multi-function support with up to four physical functions
- Endpoint and root complex support
- Type 0 Configuration Registers in Endpoint Mode
- Complete Error-Handling Support
- 32-bit Core Data Width
- Many power management features including power budgeting
**==> picture [337 x 238] intentionally omitted <==**
**----- Start of picture text -----**<br>
PCI Express Core<br>PHY TX<br>Tx<br>Tx Tx<br>eel Data VC0_TX<br>| PHY Trans<br>Link<br>Layer Layer<br>Layer<br>Rx<br>PHY RX Rx Rx VC0_RX<br>Data<br>PHY Trans<br>Link<br>Layer Layer<br>Layer<br>Power Management<br>Error Reporting (AER)<br>CLK, CONFIGURATION, AND MANAGEMENT<br>LMMI<br>CONFIGURATION REGISTERS<br>PHY Interface (PIPE)<br>**----- End of picture text -----**<br>
**Figure 2.28. PCIe Core**
The hardened PCIe block can be instantiated with the primitive _PCIe_ through Lattice Radiant software however, it is not recommended to directly instantiate the PCIe primitive itself. It is highly recommended to generate the PCIe Endpoint Soft IP through the Radiant IP Catalog and IP Block Wizard instead. In Figure 2.29, the PCIe core is configured as an Endpoint using a soft IP wrapper that provides useful functions such as bridging support for bus interfaces and DMA applications. In addition to the standard Transaction Layer Packet (TLP) interface, the data interface can also be configured to be AXI4 or AHB-Lite as well. The PCIe hardened block also features a register interface for LMMI and User Configuration Space Register Interface (UCFG). The PCIe block has many registers which contain information about the current status of the PCIe block as well as the capability to dynamically switch PCIe settings. One easy way to access these registers is through the Reveal Controller Tool.
For more information about the PCIe soft IP, refer to the PCIe Endpoint IP Core document.
© 2021-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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**CrossLink-NX Family Data Sheet**
**==> picture [379 x 138] intentionally omitted <==**
**----- Start of picture text -----**<br>
Top<br>Soft Logic PCIe Hard IP rxp_i/<br>AHB-Lite Rx TLP rxpn_i<br>/AXI-4<br>Data Interface Conversion Tx TLP<br>txp_o/<br>I Transaction Link Layer PHY Layer , txpn_o<br>Layer<br>LMMI<br>AHB-Lite<br>/APB refclkp_i/<br>Register Interface Conversion UCFG refclkn_i<br>**----- End of picture text -----**<br>
**Figure 2.29. PCIe Soft IP Wrapper**
## **2.24. Cryptographic Engine**
The CrossLink-NX family of devices support several cryptographic features that helps customer secure their design. Some of the key cryptographic features include Advanced Encryption Standard (AES), Hashing Algorithms and True Random Number Generator (TRNG). The CrossLink-NX device also features bitstream encryption (using AES-256), used for protecting confidential FPGA bitstream data, and bitstream authentication (using ECDSA), which maintains bitstream integrity and protects the FPGA design bitstream from copying and tampering.
The Cryptographic Engine (CRE) is the main engine, which is responsible for the bitstream encryption as well as authentication of the CrossLink-NX device. Once the bitstream is authenticated and the device is ready for user functions, the CRE is available for users to implement various cryptographic functions in the FPGA design. To enable specific cryptographic function, the CRE has to be configured by setting a few registers.
The Cryptographic Engine supports the below user-mode features:
- True Random Number generator (TRNG)
- Secure Hashing Algorithm (SHA)-256 bit
- Message Authentication Codes (MACs) – HMAC
- Lattice Memory Mapped Interface (LMMI) interface to user logic
- High Speed Port (HSP) for FIFO-based streaming data transfer
**==> picture [419 x 134] intentionally omitted <==**
**----- Start of picture text -----**<br>
Cryptographic Engine (CRE)<br>Unique ID<br>Control Register<br>LMMI / True Random Number Generator (TRNG)<br>FPGA High Speed Port<br>| ———— Pp<br>Fabric CRE Registers Advanced Encryption Standard (AES)<br>SHA256<br>Bitstream Encryption<br>[CS Fe<br>HMAC SHA256<br>Bitstream Authentication<br>Fr S~*S ec<br>**----- End of picture text -----**<br>
**Figure 2.30. Cryptographic Engine Block Diagram**
© 2021-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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**CrossLink-NX Family Data Sheet**
## **3. DC and Switching Characteristics for Commercial and Industrial**
All specifications in this Chapter are characterized within recommended operating conditions unless otherwise specified.
## **3.1. Absolute Maximum Ratings**
**Table 3.1. Absolute Maximum Ratings**
|**Symbol**<br>~~a~~|**Parameter**|**Min**|**Max**|**Unit**|
|---|---|---|---|---|
|VCC, VCCECLK<br>~~a~~<br><br>~~a~~|SupplyVoltage<br>~~a~~|–0.5<br>~~ee~~|1.10|V|
|VCCAUX, VCCAUXA,<br>VCCAUXH3, VCCAUXH4,<br>VCCAUXH5<br>~~a~~<br>~~a~~|Supply Voltage<br>~~a~~|–0.5<br>~~ee~~|1.98|V|
|VCCIO0, 1, 2, 6, 7<br>~~a ~~<br>~~a~~|I/O SupplyVoltage<br> ~~a~~|–0.5<br>~~ee~~|3.63|V|
|VCCIO3, 4, 5<br>~~a~~|I/O SupplyVoltage|–0.5|1.98|V|
|VCCPLL_DPHY0, 1<br>~~a~~|Hardened D-PHY PLL SupplyVoltage|–0.5|1.10|V|
|VCCPLLSD0<br>~~a~~|SerDes Block PLL SupplyVoltage|–0.5|1.98|V|
|VCCA_DPHY0, 1<br>~~a~~|AnalogSupplyVoltage for Hardened D-PHY|–0.5|1.98|V|
|VCC_DPHY0, 1<br>~~a~~<br>~~a~~|Digital SupplyVoltage for Hardened D-PHY|–0.5|1.10|V|
|VCCSD0<br>~~a~~<br>~~a~~|SerDes SupplyVoltage|–0.5|1.10|V|
|VCCADC18<br>~~a~~|ADC Block 1.8 V SupplyVoltage|–0.5|1.98|V|
|VCCAUXSD<br>~~a~~<br>~~a~~|SerDes and AUX SupplyVoltage<br>~~ee~~|–0.5<br>~~ee~~|1.98<br>~~ee~~|V|
|—<br>~~a~~<br>~~a~~|Input or I/O Voltage Applied, Bank 0, Bank<br>1,Bank 2, Bank 6, Bank 7<br>~~ee~~|–0.5<br>~~ee~~|3.63<br>~~ee~~|V|
|—<br>~~a~~<br>~~a~~|Input or I/O Voltage Applied, Bank 3, Bank 4,<br>Bank 5<br>~~ee~~|–0.5<br>~~ee~~|1.98<br>~~ee~~|V|
|—<br>~~a~~<br>~~a~~|Voltage Applied on SerDes Pins<br>~~ee ~~|–0.5<br> ~~ee ~~|1.98<br> ~~ee~~|V|
|TA<br>~~a~~<br>~~a~~|Storage Temperature(Ambient)|–65|+150|°C|
|TJ<br>~~a~~<br>~~a~~|Junction Temperature|—|+125|°C|
**Notes** :
1. Stress above those listed under the _Absolute Maximum Ratings_ may cause permanent damage to the device. Functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
2. Compliance with the Lattice Thermal Management document is required.
3. All voltages referenced to GND.
4. All VCCAUX should be connected on PCB.
© 2021-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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**CrossLink-NX Family Data Sheet**
## **3.2. Recommended Operating Conditions[1, 2, 3]**
**Table 3.2. Recommended Operating Conditions**
|**Symbol**<br>~~GC~~|**Parameter**<br>~~GC~~|**Conditions**<br>~~GC~~|**Min**<br>~~GC~~|**Typ. **<br>~~GC~~|**Max**<br>~~GC~~|**Unit**<br>~~GC~~|
|---|---|---|---|---|---|---|
|VCC,VCCECLK<br>~~Ce~~<br>~~a~~|Core SupplyVoltage<br>~~Ce~~<br>~~ee~~|VCC= 1.0<br>~~OO~~<br>~~ee~~|0.95<br>~~OO~~<br>~~ee~~|1.00<br>~~OO~~|1.05<br>~~ee~~|V<br>~~ee~~|
|VCCAUX<br>~~a~~<br>~~ee~~|Auxiliary Supply Voltage<br>~~ee~~|Bank 0, Bank 1, Bank 2, Bank 6,<br>Bank 7<br>~~ee~~|1.746<br>~~ee~~|1.80|1.89<br>~~ee~~|V<br>~~ee~~|
|VCCAUXH3/4/5<br>~~a~~<br>~~ee~~|AuxiliarySupplyVoltage<br>~~ee~~|Bank 3, Bank 4, Bank 5<br>~~ee~~|1.746<br>~~ee~~|1.80|1.89<br>~~ee~~|V<br>~~ee~~|
|VCCAUXA<br>~~ee~~<br>~~a~~|Auxiliary Supply Voltage for<br>core logic|—|1.746|1.80<br>~~ee~~|1.89<br>~~ee~~|V|
|VCCIO<br>~~a~~|I/O Driver Supply Voltage|VCCIO= 3.3 V, Bank 0, Bank 1,<br>Bank 2, Bank 6, Bank 7<br>~~ee~~|3.135<br>~~ee~~<br>~~e~~~~**e**~~|3.30<br>~~ee~~<br>~~ee~~<br>~~ee~~|3.465<br>~~ee~~<br>~~ee~~<br>~~ee~~|V<br>~~ee~~|
|||VCCIO= 2.5 V, Bank 0, Bank 1,<br>Bank 2, Bank 6, Bank 7<br>~~ee~~<br>~~a~~|2.375<br>~~ee~~<br>~~a~~<br>~~e~~~~**e**~~|2.50<br>~~ee~~<br>~~ee~~<br>~~a~~<br>~~ee~~|2.625<br>~~ee~~<br>~~ee~~<br>~~a~~<br>~~ee~~|V<br>~~ee~~<br>~~a~~|
|||VCCIO= 1.8 V, All Banks<br>~~a~~<br>~~e~~|1.71<br>~~a~~<br>~~e~~~~**e**~~<br>~~e~~|1.80<br>~~a~~<br>~~ee~~|1.89<br>~~a~~<br>~~ee~~|V<br>~~a~~|
|||VCCIO= 1.5 V, All Banks4<br>~~ee~~|1.425<br>~~ee~~|1.50<br>~~ee~~|1.575<br>~~ee~~|V<br>~~ee~~|
|||VCCIO= 1.35 V, All Banks (For<br>DDR3L Only)<br>~~ee~~|1.2825<br>~~ee~~|1.35<br>~~ee~~|1.4175<br>~~ee~~|V<br>~~ee~~|
|||VCCIO= 1.2 V, All Banks4<br>~~ee~~<br>~~ee~~|1.14<br>~~ee~~<br>~~ee~~|1.20<br>~~ee~~<br>~~ee~~|1.26<br>~~ee~~<br>~~ee~~|V<br>~~ee~~<br>~~ee~~|
|||VCCIO= 1.0 V, Bank 3, Bank 4,<br>Bank 5<br>~~ee~~|0.95<br>~~ee~~|1.00<br>~~ee~~|1.05<br>~~ee~~|V<br>~~ee~~|
|**D-PHY External Power Supplies**<br>~~ee~~<br>~~ee~~<br>~~pn~~|||||||
|VCCA_D-PHY<br>~~a~~|D-PHY Analog Power<br>Supply<br>~~ee~~|—<br>~~ee~~|1.71<br>~~ee~~|1.80<br>~~ee~~|1.89<br>~~ee~~|V<br>~~ee~~|
|VCC_D-PHY<br>~~Ge~~<br>~~ee~~|D-PHY Digital Power Supply<br>~~Ge~~|—<br>~~Ge~~|0.95<br>~~Ge~~|1.00<br>~~Ge~~|1.05<br>~~Ge~~|V<br>~~Ge~~|
|VCCPLL_D-PHY<br>~~ee~~|D-PHY PLL Power Supply|—|0.95|1.00|1.05|V|
|**ADC External Power Supplies**<br>~~ee~~<br>~~pn~~|||||||
|VCCADC18<br>~~eC~~|ADC 1.8 V Power Supply<br>~~eC~~|—<br>~~eC~~|1.71<br>~~eC~~|1.80<br>~~eC~~|1.89<br>~~eC~~|V<br>~~eC~~|
|**SerDes Block External Power Supplies**<br>~~a~~<br>~~es~~|||||||
|VCCSD0<br>~~a~~|Supply Voltage for SerDes<br>Block and SerDes I/O<br>~~es~~|—|0.95|1.00|1.05|V|
|VCCPLLSD0<br>~~a~~<br>~~a~~|SerDes Block PLL Supply<br>Voltage<br>~~es~~<br>~~es~~|—|1.71|1.80|1.89|V|
|VCCAUXSD<br>~~a~~|SerDes Block Auxiliary<br>SupplyVoltage<br>~~es~~|—|1.71|1.80|1.89|V|
|**Operating Temperature**<br>~~es~~|||||||
|tJCOM<br>~~a~~|Junction Temperature,<br>Commercial Operation|—|0|—|85|°C|
|tJIND<br>~~a~~<br>~~a~~|Junction Temperature,<br>Industrial Operation|—|–40|—|100|°C|
**Notes** :
1. For correct operation, all supplies must be held in their valid operation voltage range.
2. All supplies with same voltage should be from the same voltage source. Proper isolation filters are needed to properly isolate noise from each other.
3. Common supply rails must be tied together except SerDes.
4. MSPI (Bank0) and JTAG, SSPI, I[2] C, and I3C (Bank 1) ports are supported for VCCIO = 1.8 V to 3.3 V.
© 2021-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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**CrossLink-NX Family Data Sheet**
## **3.3. Power Supply Ramp Rates**
## **Table 3.3. Power Supply Ramp Rates**
|**Symbol**|**Parameter**|**Min**|**Typ**|**Max**|**Unit**|
|---|---|---|---|---|---|
|tRAMP|Power Supply ramp rates for all supplies1|0.1|—|50|V/ms|
**Notes** :
1. Assumes monotonic ramp rates.
2. All supplies need to be in the operating range as defined in Recommended Operating Conditions1, when the device has completed configuration and entering into User Mode. Supplies that are not in the operating range needs to be adjusted to faster ramp rate, or users have to delay configuration or wake up.
## **3.4. Power up Sequence**
Power-On-Reset (POR) puts the CrossLink-NX device into a reset state. There is no power up sequence required for the CrossLink-NX device.
**Table 3.4. Power-On Reset**
|**Symbol**|**Parameter**|**Parameter**|**Min**|**Typ**|**Max**|**Unit**|
|---|---|---|---|---|---|---|
|VPORUP|Power-On-Reset ramp-up trip<br>point (Monitoring VCC, VCCAUX,<br>VCCI00, and VCCI01)|VCC|0.73|—|0.83|V|
|||VCCAUX|1.34|—|1.71|V|
|||VCCIO0,VCCI01|0.89|—|1.05|V|
|VPORDN|Power-On-Reset ramp-up trip<br>point (Monitoring VCCand VCCAUX)|VCC|0.51|—|0.81|V|
|||VCCAUX|1.38|—|1.54|V|
## **3.5. On-Chip Programmab** l **e Termination**
The CrossLink-NX devices support a variety of programmable on-chip terminations options, including:
- Dynamically switchable Single-Ended Termination with programmable resistor values of 40 Ω, 50 Ω, 60 Ω, or 75 Ω.
- Common mode termination of 100 Ω for differential inputs.
**==> picture [202 x 142] intentionally omitted <==**
**----- Start of picture text -----**<br>
V CCIO<br>TERM<br>Zo = 40 , 50 , 60 , or 75<br>control<br>to VCCIO /2<br>Zo<br>Zo +<br>VREF -<br>OFF-chip ON-chip<br>Parallel Single-Ended Input<br>**----- End of picture text -----**<br>
**==> picture [32 x 8] intentionally omitted <==**
**----- Start of picture text -----**<br>
Zo = 50<br>**----- End of picture text -----**<br>
**==> picture [122 x 105] intentionally omitted <==**
**----- Start of picture text -----**<br>
Zo<br>+<br>2Zo -<br>Zo<br>OFF-chip ON-chip<br>Differential Input<br>**----- End of picture text -----**<br>
**Figure 3.1. On-Chip Termination**
See Table 3.5 for termination options for input modes.
© 2021-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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**CrossLink-NX Family Data Sheet**
**Table 3.5. On-Chip Termination Options for Input Modes**
|**IO_TYPE**|**Differential Termination Resistor1, 2**|**Terminate to VCCIO/21, 2**|
|---|---|---|
|subLVDS<br>~~a~~|100, OFF|OFF|
|SLVS<br>~~a~~|100, OFF|OFF|
|MIPI_DPHY<br>~~a~~|100|OFF|
|HSTL15D_I<br>~~a~~<br>~~a~~|100, OFF|OFF|
|SSTL15D_I<br>~~a~~|100, OFF|OFF|
|SSTL135D_I<br>~~a~~|100, OFF|OFF|
|HSUL12D<br>~~a~~|100, OFF|OFF<br>~~O~~|
|LVCMOS15H<br>~~a~~|OFF|OFF|
|LVCMOS12H<br>~~a~~<br>~~a~~|OFF|OFF|
|LVCMOS10H<br>~~a~~|OFF|OFF|
|LVCMOS12H<br>~~a~~|OFF|OFF|
|LVCMOS10H<br>~~a~~|OFF|OFF|
|LVCMOS18H<br>~~a~~|OFF|OFF, 40, 50, 60, 75|
|HSTL15_I<br>~~a~~<br>~~a~~|OFF|50|
|SSTL15_I<br>~~a~~|OFF|OFF, 40, 50, 60, 75|
|SSTL135_I<br>~~a~~|OFF|OFF, 40, 50, 60, 75|
|HSUL12<br>~~a~~|OFF|OFF, 40, 50, 60, 75|
## **Notes** :
1. TERMINATE to VCCIO/2 (Single-Ended) and DIFFRENTIAL TERMINATION RESISTOR when turned on can only have one setting per bank. Only left and right banks have this feature.
2. Use of TERMINATE to VCCIO/2 and DIFFRENTIAL TERMINATION RESISTOR are mutually exclusive in an I/O bank. On-chip termination tolerance –10%/+60%.
Refer to sysI/O User Guide for Nexus Platform (FPGA-TN-02067) for on-chip termination usage and value ranges.
## **3.6. Hot Socketing Specifications**
**Table 3.6. Hot Socketing Specifications for GPIO**
|**Symbol**|**Parameter**|**Condition**|**Min**|**Typ**|**Max**|**Unit**|
|---|---|---|---|---|---|---|
|IDK|Input or I/O Leakage Current for<br>Wide Range I/O (excluding<br>MCLK/MCSN/MOSI/INITN/DONE)|0 < VIN< VIH(max)<br>0 < VCC< VCC(max)<br>0 < VCCIO< VCCIO(max)<br>0 < VCCAUX< VCCAUX (max)|-1.5|—|1.5|mA|
## **Notes** :
- IDK is additive to IPU, IPD, or IBH.
- Hot socketing specs are defined at a device junction temperature of 85 °C or below. When the device junction temperature is above 85[o] C, the IDK current can exceed the above spec.
- Going beyond the hot socketing ranges specified here will cause exponentially higher Leakage currents and potential reliability issues. A total of 64 mA per 8 I/O should not be exceeded.
## **3.7. ESD Performance**
Refer to the CrossLink-NX Product Family Qualification Summary for complete Commercial and Industrial grade qualification data, including ESD performance.
© 2021-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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**CrossLink-NX Family Data Sheet**
## **3.8. DC Electrical Characteristics**
**Table 3.7. DC Electrical Characteristics – Wide Range**
|**Symbol**<br>~~aGGG~~<br>~~a~~|**Parameter**<br>~~GGG~~<br>|**Condition**<br>~~GGG~~<br>|**Min**<br>~~GGG~~<br>~~ee~~<br>|**Typ**<br>~~GGG~~<br>~~ee~~<br>|**Max**<br>~~GGG~~<br>|**Unit**<br>~~GGG~~<br>|
|---|---|---|---|---|---|---|
|IIL, IIH1<br>~~aee~~<br>~~a~~|Input or I/O Leakage current<br>(Commercial/Industrial)<br>~~ee~~<br>|0 ≤ VIN≤ VCCIO<br>~~ee~~<br>|—<br>~~ee~~<br>~~ee~~<br>|—<br>~~ee~~<br>~~ee~~<br>|10<br>~~ee~~<br>|µA<br>~~ee~~<br>|
|IIH2<br>~~aGG~~<br>~~a~~|Input or I/O Leakage current<br>~~GG~~<br>|VCCIO≤ VIN≤ VIH (max)<br>~~GG~~<br>|—<br>~~ee~~<br>~~GG~~<br>~~ee~~<br>|—<br>~~ee~~<br>~~GG~~<br>~~ee~~<br>|100<br>~~GG~~<br>|µA<br>~~GG~~<br>|
|IPU<br>~~aee~~<br>~~a~~<br>~~a~~|I/O Weak Pull-up Resistor<br>Current<br>~~ee~~<br><br>|0 ≤ VIN≤ 0.7 × VCCIO<br>~~ee~~<br><br>|–30<br>~~ee~~<br>~~ee~~<br><br>~~ee~~<br>|—<br>~~ee~~<br>~~ee~~<br><br>~~ee~~<br>|–150<br>~~ee~~<br><br>|µA<br>~~ee~~<br><br>|
|IPD<br>~~aee~~<br>~~a~~|I/O Weak Pull-down Resistor<br>Current<br>~~ee~~<br>|VIL(max) ≤ VIN≤ VCCIO<br>~~ee~~<br>|30<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>|—<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>|150<br>~~ee~~<br>|µA<br>~~ee~~<br>|
|IBHLS<br>~~aGG~~|Bus Hold Low SustainingCurrent<br>~~GG~~|VIN= VIL (max)<br>~~GG~~|30<br>~~ee~~<br>~~GG~~|—<br>~~ee~~<br>~~GG~~|~~GG~~|µA<br>~~GG~~|
|IBHHS<br>~~aGG~~<br>~~aGG~~|Bus Hold High SustainingCurrent<br>~~GG~~<br>~~GG~~|VIN= 0.7 × VCCIO<br>~~GG~~<br>~~GG~~|–30<br>~~ee~~<br>~~GG~~<br>~~GG~~|—<br>~~ee~~<br>~~GG~~<br>~~GG~~|~~GG~~<br>~~GG~~|µA<br>~~GG~~<br>~~GG~~|
|IBHLO<br>~~a a~~|Bus hold low Overdrive Current<br>~~a~~<br>~~GD~~|0 ≤ VIN≤ VCCIO<br>~~GD~~|—<br>~~GD~~|—<br>~~GD~~|150<br>~~GD~~|µA<br>~~GD~~|
|IBHHO<br>~~a ~~|Bus hold high Overdrive Current<br> ~~a~~<br>~~GG~~|0 ≤ VIN≤ VCCIO<br>~~GG~~|—<br>~~GG~~|—<br>~~GG~~|–150<br>~~GG~~|µA<br>~~GG~~|
|VBHT<br>~~a ~~|Bus Hold TripPoints<br> ~~a~~<br>~~GG~~|—<br>~~GG~~|VIL(max)<br>~~GG~~|—<br>~~GG~~|VIH(min)<br>~~GG~~|V<br>~~GG~~|
**Notes** :
1. Input or I/O leakage current is measured with the pin configured as an input or as an I/O with the output tri-stated. Bus Maintenance circuits are disabled.
2. The input leakage current IIH is the worst case input leakage per GPIO when the pad signal is high and also higher than the bank VCCIO. This is considered a mixed mode input.
**Table 3.8. DC Electrical Characteristics – High Speed**
|**Symbol**<br>~~pO~~<br>~~a~~|**Parameter**<br>~~pO~~|**Condition**<br>~~pO~~|**Min**<br>~~pO~~|**Typ**<br>~~pO~~<br>DO|**Max**<br>~~pO~~|**Unit**<br>~~pO~~|
|---|---|---|---|---|---|---|
|IIL, IIH1<br>~~a~~<br>~~a~~|Input or I/O Leakage<br>~~GG~~|0 ≤ VIN≤ VCCIO<br>~~GG~~|—<br>~~GG~~|—<br>~~GG~~<br>DO|10<br>~~GG~~|µA<br>~~GG~~|
|IPU<br>~~a~~|I/O Weak Pull-up Resistor<br>Current|0 ≤ VIN≤ 0.7 × VCCIO|–30|—<br>DO|–150|µA|
|IPD<br>~~a~~|I/O Weak Pull-down Resistor<br>Current<br>~~ee~~|VIL(max) ≤ VIN≤ VCCIO<br>~~ee~~|30<br>~~ee~~|—<br>~~ee~~|150<br>~~ee~~|µA<br>~~ee~~|
|IBHLS<br>~~a~~|Bus Hold Low SustainingCurrent<br>~~GG~~|VIN= VIL (max)<br>~~GG~~|30<br>~~GG~~|—<br>~~GG~~|—<br>~~GG~~|µA<br>~~GG~~|
|IBHHS<br>~~a~~|Bus Hold High SustainingCurrent|VIN= 0.7 × VCCIO|–30|—|—|µA|
|IBHLO<br>~~a~~<br>~~a~~|Bus hold low Overdrive Current<br>~~GG~~|0 ≤ VIN≤ VCCIO<br>~~GG~~|—<br>~~GG~~|—<br>~~GG~~|150<br>~~GG~~|µA<br>~~GG~~|
|IBHHO<br>~~a~~<br>~~a ~~|Bus hold high Overdrive Current<br>~~GG~~<br> ~~a~~<br>~~GG~~|0 ≤ VIN≤ VCCIO<br>~~GG~~<br>~~GG~~|—<br>~~GG~~<br>~~GG~~|—<br>~~GG~~<br>~~GG~~|–150<br>~~GG~~<br>~~GG~~|µA<br>~~GG~~<br>~~GG~~|
|VBHT<br>~~a~~|Bus Hold Trip Points|—|VIL<br>(max)|—|VIH(min)|V|
## **Note:**
1. Input or I/O leakage current is measured with the pin configured as an input or as an I/O with the output tri-stated. Bus Maintenance circuits are disabled.
**Table 3.9. Capacitors – Wide Range**
|**Symbol**|**Parameter**|**Condition**|**Min**|**Typ**|**Max**|**Unit**|
|---|---|---|---|---|---|---|
|C11|I/O Capacitance1|VCCIO= 3.3 V, 2.5 V, 1.8 V, 1.5 V, 1.2 V,<br>VCC= typ., VIO= 0 to VCCIO+ 0.2V|—|6|—|pF|
|C21|Dedicated Input Capacitance1|VCCIO= 3.3 V, 2.5 V, 1.8 V, 1.5 V, 1.2 V,<br>VCC= typ., VIO= 0 to VCCIO+ 0.2V|—|6|—|pF|
**Note** :
1. TA 25[o] C, f = 1.0 MHz.
© 2021-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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**CrossLink-NX Family Data Sheet**
**Table 3.10. Capacitors – High Performance Symbol Parameter Condition Min Typ Max Unit** VCCIO = 1.8 V, 1.5 V, 1.2 V, VCC = typ., C1[1 ] I/O Capacitance[1] — 6 — pF VIO = 0 to VCCIO + 0.2V VCCIO = 1.8 V, 1.5 V, 1.2 V, VCC = typ., C2[1 ] Dedicated Input Capacitance[1] — 6 — pF VIO = 0 to VCCIO + 0.2V VCCA_D-PHY = 1.8 V, VCC = typ., VIO = 0 C3[1 ] D-PHY I/O Capacitance — 5 — pF to V + 0.2V CCA_D-PHY VCCSD0 = 1.0 V, VCC = typ., VIO = 0 to C4[1 ] SerDes I/O Capacitance — 5 — pF VCCSD0 + 0.2 V ~~ee~~ **Note:** 1. TA 25[o] C, f = 1.0 MHz. **Table 3.11. Single Ended Input Hysteresis – Wide Range IO_TYPE VCCIO TYP Hysteresis** LVCMOS33 3.3 V 250 mV 3.3 V 200 mV LVCMOS25 2.5 V 250 mV LVCMOS18 1.8 V 180 mV LVCMOS15 1.5 V 50 mV LVCMOS12 1.2 V 0 LVCMOS10 1.2 V 0 ~~==~~ **Table 3.12. Single Ended Input Hysteresis – High Performance IO_TYPE VCCIO TYP Hysteresis** LVCMOS18H 1.8 V 180 mV 1.8 V 50 mV LVCMOS15H 1.5 V 150 mV LVCMOS12H 1.2 V 0 LVCMOS10H 1.0 V 0 MIPI-LP-RX 1.2 V >25 mV ~~—=_~~ **3.9. Supply Currents** For estimating and calculating current, use Power Calculator in Lattice Design software.
This operating and peak current is design dependent, and can be calculated in Lattice Design Software. Some blocks can be placed into low current standby modes. Refer to Power Management and Calculation for CrossLink-NX Devices (FPGA-TN-02075).
© 2021-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
58
FPGA-DS-02049-1.8
**CrossLink-NX Family Data Sheet**
## **3.10. sysI/O Recommended Operating Conditions**
**Table 3.13. sysI/O Recommended Operating Conditions**
|**Standard**<br>~~Bf~~|**Support Banks**<br>~~Bf~~|**VCCIO(Input)**<br>~~a~~|**VCCIO(Output)**<br>~~a~~|
|---|---|---|---|
|||**Typ.**<br>~~a~~|**Typ. **<br>~~a~~|
|**Single-Ended**<br>~~Bf a~~<br>~~**G**e~~<br>~~**G**O~~<br>~~Ge~~||||
|LVCMOS33<br>~~ee~~<br>~~Ge~~|0, 1, 2, 6, 7<br>~~ee~~<br>~~Ge~~|3.3<br>~~ee~~<br>~~**G**e~~|3.3<br>~~ee~~<br>~~**G**O~~|
|LVTTL33<br>~~Ge~~|0, 1, 2, 6, 7<br>~~Ge~~|3.3<br>~~**G**e~~|3.3<br>~~**G**O~~|
|LVCMOS25¹,²<br>~~Ge~~|0, 1, 2, 6, 7<br>~~Ge ~~|2.5, 3.3<br> ~~GG~~|2.5<br>~~GG~~|
|LVCMOS18¹,²<br>~~Ge~~<br>~~eG~~|0, 1, 2, 6, 7<br>~~Ge ~~<br>~~eG~~|1.2, 1.5, 1.8, 2.5, 3.3<br> ~~GG~~<br>~~GO~~|1.8<br>~~GG~~<br>~~GO~~|
|LVCMOS18H<br>~~eG~~<br>~~Ge~~|3, 4, 5<br>~~eG~~<br>~~Ge~~|1.8<br>~~GO~~<br>~~**G**e~~|1.8<br>~~GO~~<br>~~**G**O~~|
|LVCMOS15¹,²<br>~~eG~~<br>~~Ge~~<br>~~Ge~~|0, 1, 2, 6, 7<br>~~eG ~~<br>~~Ge~~<br>~~Ge~~|1.2, 1.5, 1.8, 2.5, 3.3<br> ~~GO~~<br>~~Ge~~<br>~~**G**e~~|1.5<br>~~GO~~<br>~~Ge~~<br>~~**G**O~~|
|LVCMOS15H¹<br>~~Ge~~|3, 4, 5<br>~~Ge~~|1.5, 1.8<br>~~**G**e~~|1.5<br>~~**G**O~~|
|LVCMOS12¹,²<br>~~Ge~~|0, 1, 2, 6, 7<br>~~Ge ~~|1.2, 1.5, 1.8, 2.5, 3.3<br> ~~GG~~|1.2<br>~~GG~~|
|LVCMOS12H¹<br>~~Ge~~<br>~~eG~~|3, 4, 5<br>~~Ge ~~<br>~~eG~~|1.2, 1.357, 1.5, 1.8<br> ~~GG~~<br>~~GO~~|1.2<br>~~GG~~<br>~~GO~~|
|LVCMOS10¹<br>~~eG~~<br>~~Ge~~|0, 1, 2, 6, 7<br>~~eG~~<br>~~Ge~~|1.2, 1.5, 1.8, 2.5, 3.3<br>~~GO~~<br>~~**G**e~~|—<br>~~GO~~<br>~~**G**O~~|
|LVCMOS10H¹<br>~~eG~~<br>~~Ge~~<br>~~Ge~~|3, 4, 5<br>~~eG ~~<br>~~Ge~~<br>~~Ge~~|1.0, 1.2, 1.357, 1.5, 1.8<br> ~~GO~~<br>~~Ge~~<br>~~**G**e~~|1.0<br>~~GO~~<br>~~Ge~~<br>~~**G**O~~|
|LVCMOS10R¹<br>~~Ge~~|3, 4, 5<br>~~Ge~~|1.0, 1.2, 1.357, 1.5, 1.8<br>~~**G**e~~|—<br>~~**G**O~~|
|SSTL135_I, SSTL135_II3<br>~~Ge~~|3, 4, 5<br>~~Ge ~~|1.357<br> ~~GG~~|1.35<br>~~GG~~|
|SSTL15_I, SSTL15_II3<br>~~Ge~~<br>~~eG~~|3, 4, 5<br>~~Ge ~~<br>~~eG~~|1.58<br> ~~GG~~<br>~~GO~~|1.58<br>~~GG~~<br>~~GO~~|
|HSTL15_I3<br>~~eG~~<br>~~Ge~~|3, 4, 5<br>~~eG~~<br>~~Ge~~|1.58<br>~~GO~~<br>~~**G**e~~|1.58<br>~~GO~~<br>~~GO~~|
|HSUL123<br>~~eG~~<br>~~Ge~~<br>~~Ge~~|3, 4, 5<br>~~eG ~~<br>~~Ge~~<br>~~Ge~~|1.2<br> ~~GO~~<br>~~Ge~~<br>~~**G**e~~|1.2<br>~~GO~~<br>~~Ge~~<br>~~GO~~|
|MIPI D-PHY LP Input6<br>~~Ge~~|3, 4, 5<br>~~Ge~~|1.2<br>~~**G**e~~|1.2<br>~~GO~~<br>~~D~~|
|**Differential6**||||
|LVDS<br>~~Ge~~|3, 4, 5<br>~~Ge ~~|1.2, 1.35, 1.5, 1.8<br> ~~GG~~|1.8<br>~~GG~~|
|LVDSE5<br>~~Ge~~<br>~~eG~~|0, 1, 2, 6, 7<br>~~Ge~~<br>~~eG~~|—<br>~~GG~~<br>~~GO~~|2.5<br>~~GG~~<br>~~GO~~|
|subLVDS<br>~~Ge~~<br>~~eG~~|3, 4, 5<br>~~Ge ~~<br>~~eG~~|1.2, 1.35, 1.5, 1.8<br> ~~GG~~<br>~~GO~~|—<br>~~GG~~<br>~~GO~~|
|subLVDSE5<br>~~eG~~<br>~~Ge~~|0, 1, 2, 6, 7<br>~~eG ~~<br>~~Ge~~|—<br> ~~GO~~<br>~~Ge~~|1.8<br>~~GO~~<br>~~Ge~~|
|subLVDSEH5<br>~~Ge~~<br>~~Ge~~<br>~~eG~~|3, 4, 5<br>~~Ge~~<br>~~Ge~~<br>~~eG~~|—<br>~~Ge~~<br>~~Ge~~<br>~~GO~~|1.8<br>~~Ge~~<br>~~Ge~~<br>~~GO~~|
|SLVS6<br>~~Ge~~<br>~~eG~~|3, 4, 5<br>~~Ge~~<br>~~eG~~|1.0, 1.2, 1.357, 1.5, 1.84<br>~~Ge~~<br>~~GO~~<br>~~G~~~~**e**~~|1.2, 1.357, 1.5, 1.84<br>~~Ge~~<br>~~GO~~<br>~~GO~~|
|MIPI D-PHY6<br>~~eG~~<br>~~Ge~~<br>|3, 4, 5<br>~~eG ~~<br>~~Ge~~<br>|1.2<br> ~~GO~~<br>~~Ge~~<br>~~G~~~~**e**~~<br>~~Ge~~|1.2<br>~~GO~~<br>~~Ge~~<br>~~GO~~<br>~~GO~~|
|LVCMOS33D5<br>~~G~~|0, 1, 2, 6, 7<br>~~G~~|—<br>~~G~~~~**e**~~<br>~~GGe~~|3.3<br>~~GO~~<br>~~GO~~|
|LVTTL33D5<br><br>~~Ge~~<br>~~De~~|0, 1, 2, 6, 7<br><br>~~Ge~~<br>~~De~~|—<br>~~Ge~~<br>~~Ge~~<br>~~OO~~<br>|3.3<br>~~GO~~<br>~~Ge~~<br>~~OO~~<br>|
|LVCMOS25D5<br>~~Ge~~<br>~~eG~~<br>~~De~~|0, 1, 2, 6, 7<br>~~Ge~~<br>~~eG~~<br>~~De~~|—<br>~~Ge~~<br>~~eG~~<br>~~OO~~<br>|2.5<br>~~Ge~~<br>~~eG~~<br>~~OO~~<br>|
|SSTL135D_I, SSTL135D_II5<br>~~eG~~<br>~~De~~|3, 4, 5<br>~~eG~~<br>~~De~~|—<br>~~eG~~<br>~~OO~~<br>~~GG~~<br>~~G~~~~**e**~~|1.357<br>~~eG~~<br>~~OO~~<br>~~GG~~<br>~~GO~~|
|SSTL15D_I, SSTL15D_II5<br>~~De~~<br>~~Ge~~<br>|3, 4, 5<br>~~De ~~<br>~~Ge~~<br>|—<br>~~OO~~<br> ~~GG~~<br>~~Ge~~<br>~~G~~~~**e**~~<br>~~Ge~~|1.5<br>~~OO~~<br>~~GG~~<br>~~Ge~~<br>~~GO~~<br>~~GO~~|
|HSTL15D_I5<br>~~G~~|3, 4, 5<br>~~G~~|—<br>~~G~~~~**e**~~<br>~~GGe~~|1.5<br>~~GO~~<br>~~GO~~|
|HSUL12D5<br><br>~~fe~~|3, 4, 5<br><br>~~fe~~|—<br>~~Ge~~<br>~~fe~~|1.2<br>~~GO~~<br>~~fe~~|
**Notes** :
1. Single-ended input can mix into I/O Banks with VCCIO different from the standard requires due to some of these input standards use internal supply voltage source (VCC, VCCAUX) to power the input buffer, which makes them to be independent of VCCIO voltage. For more details, refer to sysI/O User Guide for Nexus Platform (FPGA-TN-02067). The following is a brief guideline to follow:
- a. Weak pull-up on the I/O must be set to OFF.
- b. Bank 3, Bank 4, and Bank 5 I/O can only mix into banks with VCCIO higher than or equal to the pin standard, due to clamping diode on the pin in these banks. Bank 0, Bank 1, Bank 2, Bank 6, and Bank 7 does not have this restriction.
- c. LVCMOS25 uses VCCIO supply on input buffer in Bank 0, Bank 1, Bank 2, Bank 6, and Bank 7. It can be supported with VCCIO = 3.3 V to meet the VIH and VIL requirements, but there is additional current drawn on VCCIO. Hysteresis has to be disabled when using 3.3 V supply voltage.
- d. LVCMOS15 uses VCCIO supply on input buffer in Bank 3, Bank 4, and Bank 5. It can be supported with VCCIO = 1.8 V to meet the VIH and VIL requirements, but there is additional current drawn on VCCIO.
© 2021-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02049-1.8
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**CrossLink-NX Family Data Sheet**
2. Single-ended LVCMOS inputs can mixed into I/O Banks with different VCCIO, providing weak pull-up is not used. For additional information on Mixed I/O in Bank VCCIO, refer to sysI/O User Guide for Nexus Platform (FPGA-TN-02067) **.**
3. These inputs use differential input comparator in Bank 3, Bank 4, and Bank 5. The differential input comparator uses VCCAUXH power supply. These inputs require the VREF pin to provide the reference voltage in the Bank. Refer to sysI/O User Guide for Nexus Platform (FPGA-TN-02067) for details **.**
4. All differential inputs use differential input comparator in Bank 3, Bank 4, and Bank 5. The differential input comparator uses VCCAUXH power supply. There is no differential input signaling supported in Bank 0, Bank 1, Bank 2, Bank 6, and Bank 7.
5. These outputs are emulating differential output pair with single-ended output drivers with true and complement outputs driving on each of the corresponding true and complement output pair pins. The common mode voltage, VCM, is ½ × VCCIO. Refer to sysI/O User Guide for Nexus Platform (FPGA-TN-02067) for details **.**
6. Soft MIPI D-PHY HS using sysI/O is supported with SLVS input and output that can be placed in banks with VCCIO voltage shown in SLVS. D-PHY with HS and LP modes supported needs to be placed in banks with VCCIO voltage = 1.2 V. Soft MIPI D-PHY LP input and output using sysI/O are supported with LVCMOS12.
7. VCCIO = 1.35 V is only supported in Bank 3, Bank 4, and Bank 5, for use with DDR3L interface in the bank. These Input and Output standards can fit into the same bank with the VCCIO = 1.35 V.
8. LVCMOS15 input uses VCCIO supply voltage. If VCCIO is 1.8 V, the DC levels for LVCMOS15 are still met, but there could be increase in input buffer current.
## **3.11. sysI/O Single-Ended DC Electrical Characteristics**
**Table 3.14. sysI/O DC Electrical Characteristics – Wide Range I/O**
|**Input/Output**<br>**Standard2 **|**VIL**|**VIL**|**VIH**|**VIH**|**VOL Max**<br>**(V)**|**VOH Min**<br>**(V)**|**IOL(mA)**|**IOH(mA)**|
|---|---|---|---|---|---|---|---|---|
||**Min(V)**|**Max(V)**|**Min(V)**|**Max(V)**|||||
|LVTTL33<br>LVCMOS33<br>~~a~~|—|0.8|2.0|3.4654|0.4|VCCIO– 0.4|2, 4, 8,<br>12, 16,<br>“50RS”3|-2, -4, -8,<br>-12, -16,<br>“50RS”3|
|LVCMOS25<br>~~a~~<br>~~ee~~<br>~~a~~|—<br>~~ee~~|0.7<br>~~ee~~|1.7<br>~~ee~~|3.4654<br>~~ee~~|0.4<br>~~ee~~<br>~~es~~|VCCIO– 0.45<br>~~ee~~<br>~~es~~|2, 4, 8,<br>10,<br>“50RS”3<br>~~ee~~<br>~~ee~~|-2, -4, -8,<br>-10,<br>“50RS”3<br>~~ee~~|
|LVCMOS18<br>~~ee~~<br>~~a~~<br>~~ee~~|—<br>~~ee~~<br>|0.35 × VCCIO<br>~~ee~~<br>~~ry~~<br>|0.65 × VCCIO<br>~~ee~~<br>~~ry~~<br>|3.4654<br>~~ee~~<br>~~ry~~|0.4<br>~~ee~~<br>~~es~~<br>~~ts~~|VCCIO– 0.45<br>~~ee~~<br>~~es~~|2, 4, 8,<br>“50RS”3<br>~~ee~~<br>~~ee~~|-2, -4, -8,<br>“50RS”3<br>~~ee~~|
|LVCMOS15<br>~~ee ~~<br>~~a~~<br>~~ee~~<br>~~ee~~|—<br> ~~ee~~<br>~~es~~<br>|0.35 × VCCIO<br>~~ee~~<br>~~ry~~<br>~~es~~<br>|0.65 × VCCIO<br>~~ee~~<br>~~ry~~<br>~~**r**s~~|3.4654<br>~~ee~~<br>~~ry~~<br>~~ty~~|0.4<br>~~ee~~<br>~~es ~~<br>~~ts~~|VCCIO– 0.4<br>~~ee~~<br> ~~es ~~|2, 4<br>~~ee~~<br> ~~ee~~|-2, -4<br>~~ee~~|
|LVCMOS12<br>~~ee~~<br>~~ee ee~~|—<br>~~es~~<br>~~ee ee~~|0.35 × VCCIO<br>~~ry~~<br>~~es~~<br>~~ee~~|0.65 × VCCIO<br>~~ry~~<br>~~**r**s~~<br>~~r~~|3.4654<br>~~ry~~<br>~~ty~~|0.4<br>~~ts~~|VCCIO– 0.4|2, 4|-2, -4|
|LVCMOS10<br>~~ee ~~<br>~~ee ee~~|—<br> ~~es~~<br>~~ee ee~~|0.35 × VCCIO<br>~~ry~~<br>~~es~~<br>~~ee~~|0.65 × VCCIO<br>~~ry~~<br>~~**r**s~~<br>~~r~~|3.4654<br>~~ry ~~<br>~~ty~~|No O/P Support<br> ~~ts~~||||
**Notes** :
1. For electro-migration, the average DC current drawn by the I/O pads within a bank of I/O shall not exceed 10 mA per I/O average.
2. For the types of I/O standard supported in which bank, refer to sysI/O User Guide for Nexus Platform (FPGA-TN-02067) for details.
3. Select “50RS” in driver strength is selecting 50 Ω series impedance driver.
4. VIH (MAX) for inputs on these standards (in Bank 0, Bank 1, Bank 2, Bank 6, and Bank 7) can go up to 3.465 V if the input clamp is OFF. Otherwise, the input cannot be higher than VCCIO + 0.3 V.
© 2021-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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FPGA-DS-02049-1.8
|**Input/Output**<br>**Standard2 **<br>~~a~~|**VIL**<br>~~a~~|**VIL**<br>~~a~~|**VIH**<br>~~a~~|**VIH**<br>~~a~~|**VOL Max**<br>**(V)**<br>~~a~~|**VOH Min**<br>**(V)**<br>~~a~~|**IOL (mA)**<br>~~a~~|**IOH (mA)**<br>~~a~~|
|---|---|---|---|---|---|---|---|---|
||**Min(V)**<br>~~a~~|**Max(V)**<br>~~a~~|**Min(V)**<br>~~a~~|**Max(V)**<br>~~a~~|||||
|LVCMOS18H<br>~~a~~<br>~~ee~~|—<br>~~a~~<br>~~ee~~|0.35 ×<br>VCCIO<br>~~a~~<br>~~ee~~|0.65 × VCCIO<br>~~a~~<br>~~ee~~|VCCIO+<br>0.3<br>~~a~~<br>~~ee~~|0.4<br>~~a~~<br>~~ee~~|VCCIO– 0.45<br>~~a~~<br>~~ee~~|2, 4, 8, 12,<br>“50RS”3<br>~~a~~<br>~~es~~|-2, -4, -8,<br>-12,<br>“50RS”3<br>~~a~~<br>~~esee~~|
|LVCMOS15H<br>~~ee~~<br>~~a~~|—<br>~~ee~~<br>~~a~~|0.35 ×<br>VCCIO<br>~~ee~~|0.65 × VCCIO<br>~~ee~~<br>~~ee~~|VCCIO+<br>0.3<br>~~ee~~|0.4<br>~~ee~~<br>~~ee~~|VCCIO– 0.4<br>~~ee~~<br>~~ee~~|2, 4, 8,<br>“50RS”3<br>~~es~~<br>~~eee~~|-2, -4, -8,<br>“50RS”3<br>~~esee~~<br>~~eee~~|
|LVCMOS12H<br>~~ee ~~<br>~~a~~<br>~~a~~|—<br> ~~ee~~<br>~~a~~<br>~~a~~|0.35 ×<br>VCCIO<br>~~ee ~~|0.65 × VCCIO<br> ~~ee ~~<br>~~ee~~<br>~~ee~~|VCCIO+<br>0.3<br> ~~ee ~~|0.4<br> ~~ee~~<br>~~ee~~<br>~~ee~~|VCCIO– 0.4<br>~~ee ~~<br>~~ee~~<br>~~ee~~|2, 4, 8,<br>“50RS”3<br> ~~es~~<br>~~eee~~<br>~~eee~~|-2, -4, -8,<br>“50RS”3<br>~~es ee~~<br>~~eee~~<br>~~eee~~|
|LVCMOS10H<br>~~a~~<br>~~a~~<br>~~a~~|—<br>~~a~~<br>~~a~~<br>~~a~~|0.35 ×<br>VCCIO|0.65 × VCCIO<br>~~ee~~<br>~~ee~~<br>~~ee~~|VCCIO+<br>0.3|0.27 ×<br>VCCIO<br>~~ee~~<br>~~ee~~<br>~~ee~~|0.75 × VCCIO<br>~~ee ~~<br>~~ee~~<br>~~ee~~|2, 4<br> ~~eee~~<br>~~eee~~<br>~~eee~~|-2, -4<br>~~eee~~<br>~~eee~~<br>~~eee~~|
|SSTL15_I<br>~~a~~<br>~~a~~|—<br>~~a~~<br>~~a~~|VREF– 0.10|VREF+ 0.1<br>~~ee~~<br>~~ee~~|VCCIO+<br>0.3|0.30<br>~~ee~~<br>~~ee~~|VCCIO– 0.30<br>~~ee ~~<br>~~ee~~|7.5<br> ~~eee~~<br>~~eee~~|–7.5<br>~~eee~~<br>~~eee~~|
|SSTL15_II<br>~~a~~<br>~~eee~~<br>~~ee~~|—<br>~~a~~<br>~~eee~~<br>~~ee~~|VREF– 0.10<br>~~eee~~<br>~~ee~~|VREF+ 0.1<br>~~ee~~<br>~~eee~~<br>~~ee~~|VCCIO+<br>0.3<br>~~eee~~|0.30<br>~~ee~~<br>~~eee~~|VCCIO– 0.30<br>~~ee ~~<br>~~eee~~<br>~~eee~~|8.8<br> ~~eee~~<br>~~eee~~<br>~~eee~~|–8.8<br>~~eee~~<br>~~eee~~<br>~~eee~~|
|HSTL15_I<br>~~eee~~<br>~~ee~~<br>~~ee~~|—<br>~~eee~~<br>~~ee~~<br>~~ee~~|VREF– 0.10<br>~~eee~~<br>~~ee~~<br>~~ee~~|VREF+ 0.1<br>~~eee~~<br>~~ee~~<br>~~ee~~|VCCIO+<br>0.3<br>~~eee~~|0.40<br>~~eee~~|VCCIO– 0.40<br>~~eee~~<br>~~eee~~<br>~~eee~~|8<br>~~eee~~<br>~~eee~~<br>~~eee~~|–8<br>~~eee~~<br>~~eee~~<br>~~eee~~|
|SSTL135_I<br>~~ee~~<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~<br>~~ee~~|VREF– 0.09<br>~~ee~~<br>~~ee~~<br>~~ee~~|VREF+ 0.09<br>~~ee~~<br>~~ee~~<br>~~ee~~|VCCIO+<br>0.3|0.27|VCCIO– 0.27<br>~~eee~~<br>~~eee~~<br>~~eee~~|6.75<br>~~eee~~<br>~~eee~~<br>~~eee~~|–6.75<br>~~eee~~<br>~~eee~~<br>~~eee~~|
|SSTL135_II<br>~~ee~~<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~<br>~~ee~~|VREF– 0.09<br>~~ee~~<br>~~ee~~<br>~~ee~~|VREF+ 0.09<br>~~ee~~<br>~~ee~~<br>~~ee~~|VCCIO+<br>0.3|0.27<br>~~eee~~|VCCIO– 0.27<br>~~eee~~<br>~~eee~~<br>~~eee~~|8<br>~~eee~~<br>~~eee~~<br>~~eee~~|–8<br>~~eee~~<br>~~eee~~<br>~~eee~~|
|LVCMOS10R<br>~~ee~~<br>~~ee~~<br>~~a~~|—<br>~~ee~~<br>~~ee~~<br>~~ee~~|VREF– 0.10<br>~~ee~~<br>~~ee~~<br>~~ee~~|VREF+ 0.10<br>~~ee~~<br>~~ee~~<br>~~ee~~|VCCIO+<br>0.3<br>~~ee~~|—<br>~~eee~~<br>~~ee~~|—<br>~~eee~~<br>~~eee~~<br>~~ee~~|—<br>~~eee~~<br>~~eee~~<br>~~ee~~<br>~~ee~~|—<br>~~eee~~<br>~~eee~~<br>~~ee~~<br>~~ee~~|
|HSUL12<br>~~ee~~<br>~~a~~|—<br>~~ee~~<br>~~ee~~|VREF– 0.10<br>~~ee~~<br>~~ee~~|VREF+ 0.10<br>~~ee~~<br>~~ee~~|VCCIO+<br>0.3<br>~~ee~~|0.3<br>~~eee~~<br>~~ee~~|VCCIO– 0.3<br>~~eee~~<br>~~ee~~|8.8, 7.5,<br>6.25, 5<br>~~eee~~<br>~~ee~~<br>~~ee~~|-8.8, -7.5,<br>-6.25, -5<br>~~eee~~<br>~~ee~~<br>~~ee~~|
**Notes** :
1. For electro-migration, the average DC current drawn by the I/O pads within a bank of I/O shall not exceed 10 mA per I/O average.
2. For the types of I/O standard supported in which bank, refer to sysI/O User Guide for Nexus Platform (FPGA-TN-02067) for details.
3. Select “50RS” in driver strength is selecting 50 Ω series impedance driver.
**Table 3.16. I/O Resistance Characteristics**
|**Parameter**|**Description**|**Test Conditions**|**Min**|**Typ**|**Max**|**Unit**|
|---|---|---|---|---|---|---|
|50RS|Output Drive Resistance when 50RS<br>Drive Strength Selected|VCCIO= 1.8 V, 2.5 V, or 3.3 V|—|50|—|Ω|
|RDIFF|Input Differential Termination<br>Resistance|Bank 3, Bank 4, and Bank 5 for I/O<br>selected to be differential|—|100|—|Ω|
|SE Input<br>Termination|Input Single Ended Termination<br>Resistance|Bank 3, Bank 4, and Bank 5 for I/O<br>selected to be Single Ended|36|40|64|Ω|
||||46|50|80||
||||56|60|96||
||||71|75|120||
© 2021-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02049-1.8
61
**CrossLink-NX Family Data Sheet**
**Table 3.17. VIN Maximum Overshoot/Undershoot Allowance – Wide Range[1, 2]**
|**AC Voltage Overshoot**|**% of UI at –40 °C to 100 °C**|**AC Voltage Undershoot**|**% of UI at –40 °C to 100 °C**|
|---|---|---|---|
|VCCIO+ 0.4|100.0%|–0.4|100.0%|
|VCCIO+ 0.5|100.0%|–0.5|44.2%|
|VCCIO+ 0.6|94.0%|–0.6|10.1%|
|VCCIO+ 0.7|21.0%|–0.7|1.3%|
|VCCIO+ 0.8|10.2%|–0.8|0.3%|
|VCCIO+ 0.9|2.5%|–0.9|0.1%|
## **Notes:**
1. The peak overshoot or undershoot voltage and the duration above VCCIO + 0.2 V or below GND – 0.2 V must not exceed the values in this table.
2. For UI less than 20 µs.
**Table 3.18. VIN Maximum Overshoot/Undershoot Allowance – High Performance[1, 2]**
|**AC Voltage Overshoot**|**% of UI at –40 °C to 100 °C**|**AC Voltage Undershoot**|**% of UI at –40 °C to 100 °C**|
|---|---|---|---|
|VCCIO+ 0.5|100.0%|–0.5|100.0%|
|VCCIO+ 0.6|47.3%|–0.6|47.3%|
|VCCIO+ 0.7|10.9%|–0.7|10.9%|
|VCCIO+ 0.8|2.7%|–0.8|2.7%|
|VCCIO+ 0.9|0.7%|–0.9|0.7%|
## **Notes:**
1. The peak overshoot or undershoot voltage and the duration above VCCIO + 0.2 V or below GND – 0.2 V must not exceed the values in this table.
2. For UI less than 20 µs.
## **3.12. sysI/O Differential DC Electrical Characteristics**
## **3.12.1. LVDS**
LVDS input buffer on CrossLink-NX is powered by VCCAUX = 1.8 V, and protected by the bank VCCIO. Therefore, the LVDS input voltage cannot exceed the bank VCCIO voltage. LVDS output buffer is powered by the Bank VCCIO at 1.8 V.
LVDS can only be supported in Bank 3, Bank 4, and Bank 5. LVDS25 output can be emulated with LVDS25E in Bank 0, Bank 1, Bank 2, Bank 6, and Bank 7. This is described in LVDS25E (Output Only) section.
© 2021-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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**CrossLink-NX Family Data Sheet**
**Table 3.19. LVDS DC Electrical Characteristics[1 ]**
|**Parameter**<br>~~a~~|**Description**<br>~~a~~|**Test Conditions**<br>~~a~~|**Min**<br>~~a~~|**Typ**<br>~~a~~|**Max**<br>~~a~~|**Unit**<br>~~a~~|
|---|---|---|---|---|---|---|
|VINP, VINM<br>~~a~~|Input Voltage<br>~~a~~|—<br>~~a~~|0<br>~~a~~|—<br>~~a~~|1.603<br>~~a~~|V<br>~~a~~|
|VICM<br>~~ee~~|Input Common Mode Voltage<br>~~ee~~|Half the sum of the two Inputs<br>~~ee~~|0.05<br>~~ee~~|—<br>~~ee~~|1.552<br>~~ee~~|V<br>~~ee~~|
|VTHD<br>~~a~~|Differential Input Threshold<br>~~a~~|Difference between the two Inputs<br>~~a~~|±100<br>~~a~~|—<br>~~a~~|—<br>~~a~~|mV<br>~~a~~|
|IIN<br>~~a~~<br>~~a~~<br>~~eS~~|Input Current<br>~~a~~<br>~~a~~<br>|Power On or Power Off<br>~~a~~<br>~~a~~<br>|—<br>~~a~~<br>~~a~~<br>|—<br>~~a~~<br>~~a~~<br>|±10<br>~~a~~<br>~~a~~<br>|µA<br>~~a~~<br>~~a~~<br>|
|VOH<br>~~eS~~|Output High Voltage for VOPor VOM<br>|RT= 100 Ω<br>|—<br>|1.425<br>|1.60<br>|V<br>|
|VOL<br>~~eSa~~<br>~~ee~~|Output Low Voltage for VOPor VOM<br>~~a~~<br>|RT= 100 Ω<br>~~a~~<br>|0.9 V<br>~~a~~<br>|1.075<br>~~a~~<br>|—<br>~~a~~<br>|V<br>~~a~~<br>|
|VOD<br>~~ee~~|Output Voltage Differential<br>|(VOP- VOM), RT= 100 Ω<br>|250<br>|350<br>|450<br>|mV<br>|
|VOD<br>~~eea~~|Change in VODBetween High and<br>Low<br>~~a~~|—<br>~~a~~|—<br>~~a~~|—<br>~~a~~|50<br>~~a~~|mV<br>~~a~~|
|VOCM<br>~~a~~|Output Common Mode Voltage<br>~~a~~|(VOP+ VOM)/2, RT= 100 Ω<br>~~a~~|1.125<br>~~a~~|1.25<br>~~a~~|1.375<br>~~a~~|V<br>~~a~~|
|VOCM<br>~~a~~<br>~~a~~|Change in VOCM, VOCM(MAX)- VOCM(MIN)<br>~~a~~<br>~~a~~|—<br>~~a~~<br>~~a~~|—<br>~~a~~<br>~~a~~<br>~~ee~~|—<br>~~a~~<br>~~a~~<br>~~ee~~|50<br>~~a~~<br>~~a~~|mV<br>~~a~~<br>~~a~~|
|ISAB<br>~~a~~|Output Short Circuit Current<br>~~a~~<br>~~ee~~|VOD= 0 V Driver outputs shorted to<br>each other<br>~~a~~<br>~~ee~~|—<br>~~a~~<br>~~ee~~<br>~~ee~~|—<br>~~a~~<br>~~ee~~<br>~~ee~~|12<br>~~a~~<br>~~ee~~|mA<br>~~a~~<br>~~ee~~|
|VOS<br>~~a~~|Change in VOSbetween H and L<br>~~a~~|—<br>~~a~~|—<br>~~ee~~<br>~~a~~|—<br>~~ee~~<br>~~a~~|50<br>~~a~~|mV<br>~~a~~|
2. VICM is depending on VID, input differential voltage, so the voltage on pin cannot exceed VINP/INM(min/max) requirements. VICM(min) = VINP/ INM (min) + ½ VID, VICM(max) = VINP/ INM (max) – ½ VID. Values in the table is based on minimum VID of +/- 100 mV.
3. VINP and VINM (max) must be less than or equal to VCCIO in all cases.
## **3.12.2. LVDS25E (Output Only)**
Three sides of the CrossLink-NX devices, Top, Left and Right, support LVDS25 outputs with emulated complementary LVCMOS outputs in conjunction with a parallel resistor across the driver outputs. The scheme shown in Figure 3.2 is one possible solution for point-to-point signals.
**Table 3.20. LVDS25E DC Conditions**
|**Parameter**<br>~~a~~|**Description**<br>~~a~~<br>~~a~~|**Typical**<br>~~a~~|**Unit**<br>~~a~~|
|---|---|---|---|
|VCCIO<br>~~a~~<br>~~a~~|Output Driver Supply (±5%)<br>~~a~~<br>~~a~~<br>~~a~~<br>~~a~~|2.50<br>~~a~~<br>~~a~~<br>~~a~~|V<br>~~a~~<br>~~a~~<br>~~a~~|
|ZOUT<br>~~a~~|Driver Impedance<br>~~a~~<br>~~a~~|20<br>~~a~~|Ω<br>~~a~~|
|RS<br>~~a~~|Driver Series Resistor (±1%)|158|Ω|
|RP<br>~~a~~<br>~~a~~|Driver Parallel Resistor (±1%)<br>~~a~~|140<br>~~a~~|Ω<br>~~a~~|
|RT<br>~~a~~|Receiver Termination (±1%)|100|Ω|
|VOH<br>~~a~~<br>~~a ~~|Output High Voltage<br> ~~a~~|1.43|V|
|VOL<br>~~a~~|Output Low Voltage|1.07|V|
|VOD<br>~~a~~<br>~~a~~|Output Differential Voltage<br>~~a~~|0.35|V|
|VCM<br>~~a ~~<br>~~a~~|Output Common Mode Voltage<br> ~~a~~<br>~~a~~<br>~~a~~|1.25<br>~~a~~<br>~~a~~|V<br>~~a~~<br>~~a~~|
|ZBACK<br>~~a~~<br>~~es~~|Back Impedance<br>~~a~~<br>~~a~~|100.5<br>~~a~~|Ω<br>~~a~~|
|IDC<br>~~a~~<br>~~es~~|DC Output Current<br>~~a~~<br>~~a~~|6.03<br>~~a~~|mA<br>~~a~~|
© 2021-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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**CrossLink-NX Family Data Sheet**
**==> picture [398 x 139] intentionally omitted <==**
**----- Start of picture text -----**<br>
VCCIO = 2.5 V (± 5%)<br>RS = 158<br>(± 1%)<br>8 mA<br>LVCMOS25<br>RP = 140 RT = 100 +<br>VCCIO = 2.5 V (± 5%) -<br>RS = 158 (± 1%) (± 1%)<br>(± 1%)<br>8 mA<br>LVCMOS25<br>Transmission line, Zo = 100 differential<br>ON-chip OFF-chip OFF-chip ON-chip<br>**----- End of picture text -----**<br>
**Figure 3.2. LVDS25E Output Termination Example**
## **3.12.3. SubLVDS (Input Only)**
SubLVDS is a reduced-voltage form of LVDS signaling, very similar to LVDS. It is a standard used in many camera types of applications, and follow the SMIA 1.0, Part 2: CCP2 Specification. Being similar to LVDS, the CrossLink-NX devices can support the subLVDS input signaling with the same LVDS input buffer. The output for subLVDS is implemented in subLVDSE/subLVDSEH with a pair of LVCMOS18 output drivers (see SubLVDSE/SubLVDSEH (Output Only) section).
**Table 3.21. SubLVDS Input DC Electrical Characteristics**
**==> picture [485 x 259] intentionally omitted <==**
**----- Start of picture text -----**<br>
Parameter Description Test Conditions Min Typ Max Unit<br>VID Input Differential Threshold Voltage Over VICM range 70 150 200 mV<br>——_———— VICM Input Common Mode Voltage Half the sum of the two Inputs 0.4 0.9 1.4 [1 ] V<br>Note:<br>1. VICM + 1/2 VID cannot exceed the bank VCCIO in all cases.<br>Sub-LVDS Driver PCB Traces, Connectors or Cables<br>Z0 = 50<br>+ +<br>RT = 100<br>100 differential ± 1%*<br>– –<br>Z0 = 50<br>Off-chip On-chip<br>**----- End of picture text -----**<br>
**Figure 3.3. SubLVDS Input Interface**
## **3.12.4. SubLVDSE/SubLVDSEH (Output Only)**
SubLVDS output uses a pair of LVCMOS18 drivers with True and Complement outputs. The VCCIO of the bank used for subLVDSE or subLVDSEH needs to be powered by 1.8 V. SubLVDSE is for Bank 0, Bank 1, Bank 2, Bank 6, and Bank 7; and subLVDSEH is for Bank 3, Bank 4, and Bank 5.
Performance of the subLVDSE/subLVDSEH driver is limited to the performance of LVCMOS18.
© 2021-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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**CrossLink-NX Family Data Sheet**
**Table 3.22. SubLVDS Output DC Electrical Characteristics**
|**Parameter**|**Description**|**Test Conditions**|**Min**|**Typ**|**Max**|**Unit**|
|---|---|---|---|---|---|---|
|VOD|Output Differential Voltage Swing|—|—|150|—|mV|
|VOCM|Output Common Mode Voltage|Half the sum of the two Outputs|—|0.9|—|V|
**==> picture [435 x 177] intentionally omitted <==**
**----- Start of picture text -----**<br>
VCCIO = +1.8 V PCB Traces, Connectors or Cables<br>Z0 = 50<br>Rs = 267 ±1%<br>+ +<br>SubLVDS Output<br>SubLVDSE Rp = 121 ±1% 100 differential RT = 100 ±1% Sub-LVDS Recevier<br>SubLVDSEH<br>– –<br>Rs = 267 ±1%<br>Z0 = 50<br>0<br>On-chip Off-chip On-chip Off-chip<br>**----- End of picture text -----**<br>
**Figure 3.4. SubLVDS Output Interface**
## **3.12.5. SLVS**
Scalable Low-Voltage Signaling (SLVS) is based on a point-to-point signaling method defined in the JEDEC JESD8-13 (SLVS-400) standard. This standard evolved from the traditional LVDS standard with smaller voltage swings and a lower common-mode voltage. The 200 mV (400 mV p-p) SLVS swing contributes to a reduction in power.
The CrossLink-NX devices receive SLVS differential input with the LVDS input buffer. This LVDS input buffer is design to cover wide input common mode range that can meet the SLVS input standard specified by the JEDEC standard.
**Table 3.23. SLVS Input DC Characteristics**
|**Parameter**<br>~~—————————~~|**Description**<br>~~—————————~~|**Test Conditions**<br>~~—————————~~|**Min**<br>~~—————————~~|**Typ**<br>~~—————————~~|**Max**<br>~~—————————~~|**Unit**<br>~~—————————~~|
|---|---|---|---|---|---|---|
|VID<br>~~—————————~~|Input Differential Threshold Voltage<br>~~—————————~~|Over VICMrange<br>~~—————————~~|70<br>~~—————————~~|—<br>~~—————————~~|—<br>~~—————————~~|mV<br>~~—————————~~|
|VICM<br>~~—————————~~|Input Common Mode Voltage<br>~~—————————~~|Half the sum of the two Inputs<br>~~—————————~~|70<br>~~—————————~~|200<br>~~—————————~~|330<br>~~—————————~~|mV<br>~~—————————~~|
The SLVS output on CrossLink-NX is supported with the LVDS drivers found in Bank 3, Bank 4, and Bank 5. The LVDS driver on CrossLink-NX is a current controlled driver. It can be configured as LVDS driver, or configured with the 100 Ω differential termination with center-tap set to VOCM at 200 mV. This means the differential output driver can be placed into bank with VCCIO = 1.2 V, 1.5 V, or 1.8 V, even if it is powered by VCCIO.
**Table 3.24. SLVS Output DC Characteristics**
|**Parameter**|**Description**|**Test Conditions**|**Min**|**Typ**|**Max**|**Unit**|
|---|---|---|---|---|---|---|
|VCCIO|Bank VCCIO|—|–5%|1.2,<br>1.5,<br>1.8|+ 5%|V|
|VOD|Output Differential Voltage Swing|—|140|200|270|mV|
|VOCM|Output Common Mode Voltage|Half the sum of the two Outputs|150|200|250|mV|
|ZOS|Single-Ended Output Impedance|—|37.5|50|80|Ω|
© 2021-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02049-1.8
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**CrossLink-NX Family Data Sheet**
**Figure 3.5. SLVS Interface**
## **3.12.6. Soft MIPI D-PHY**
When Soft D-PHY is implemented inside the FPGA logic, the I/O interface needs to use sysI/O buffers to connect to external D-PHY pins.
The CrossLink-NX sysI/O provides support for SLVS, as described in SLVS section, plus the LVCMOS12 input / output buffers together to support the High Speed (HS) and Low Power (LP) mode as defined in MIPI Alliance Specification for D-PHY.
To support MIPI D-PHY with SLVS (LVDS) and LVCMOS12, the bank VCCIO cannot be set to 1.5 V or 1.8 V. It has to connect to 1.2 V or 1.1 V.
All other DC parameters are the same as listed in SLVS section. DC parameters for the LP driver and receiver are the same as listed in LVCMOS12.
© 2021-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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**CrossLink-NX Family Data Sheet**
**==> picture [402 x 386] intentionally omitted <==**
**----- Start of picture text -----**<br>
LVCMOS12<br>LP Data_P<br>LPenable<br>HSenabl e MIPI Receiver<br>100 Diff<br>+ +<br>HS Data Z0=50<br>- -<br>SLVS<br>LPenable<br>LP Data_N<br>LVCMOS12<br>MIPI_LP_RX<br>On-Chip<br>RXLP_P<br>MIPI Divider<br>+ +<br>HS Data Z0=50<br>- -<br>LVDS<br>MIPI_LP_RX<br>RXLP_N<br>**----- End of picture text -----**<br>
**Figure 3.6. MIPI Interface**
© 2021-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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**CrossLink-NX Family Data Sheet**
**Table 3.25. Soft D-PHY Input Timing and Levels**
|**Symbol**|**Description**|**Conditions**|**Min**|**Typ**|**Max**|**Unit**|
|---|---|---|---|---|---|---|
|**High Speed(Differential) Input DC Specifications**|||||||
|VCMRX(DC)<br>~~a~~<br>~~ee~~|Common-mode Voltage in High Speed Mode|—|70|—|330|mV|
|VIDTH<br>~~ee~~|Differential Input HIGH Threshold|—|70|—|—|mV|
|VIDTL<br>~~ee~~<br>~~a~~|Differential Input LOW Threshold|—|—|—|-70|mV|
|VIHHS<br>~~a~~|Input HIGH Voltage(for HS mode)|—|—|—|460|mV|
|VILHS<br>~~a~~|Input LOW Voltage|—|–40|—|—|mV|
|VTERM-EN<br>~~a~~|Single-ended voltage for HS Termination Enable4|—|—|—|450|mV|
|ZID<br>~~a~~|Differential Input Impedance|—|80|100|125|Ω|
|**High Speed(Differential) Input AC Specifications**<br>~~a~~|||||||
|ΔVCMRX(HF)1<br>~~a~~|Common-mode Interference(>450 MHz)|—|—|—|100|mV|
|ΔVCMRX(LF)2, 3<br>~~a~~|Common-mode Interference(50 MHz - 450 MHz)|—|–50|—|50|mV|
|CCM<br>~~a a~~|Common-mode Termination<br>~~a~~|—|||60|pF|
|**Low Power(Single-Ended) Input DC Specifications**|||||||
|VIH<br>~~a~~|Low Power Mode Input HIGH Voltage<br>~~a~~|—|740|—|—|mV|
|VIL<br>~~a~~|Low Power Mode Input LOW Voltage<br>~~a~~|—|—|—|480|mV|
|VIL-ULP<br>~~a~~|Ultra Low Power Input LOW Voltage<br>~~a~~|—|—|—|300|mV|
|VHYST<br>~~a~~|Low Power Mode Input Hysteresis<br>~~a~~|—|25|—|—|mV|
|℮SPIKE<br>~~a~~|Input Pulse Rejection<br>~~a~~|—|—|—|300|V∙ps|
|TMIN-RX<br>~~a~~<br>~~a~~|Minimum Pulse Width Response<br>~~a~~<br>~~a~~|—|20|—|—|ns|
|VINT<br>~~a~~|Peak Interference Amplitude<br>~~a~~|—|—|—|200|mV|
|fINT<br>~~a~~|Interference Frequency<br>~~a~~|—|450|—|—|MHz|
**Notes** :
1. This is peak amplitude of sine wave modulated to the receiver inputs.
2. Input common-mode voltage difference compared to average common-mode voltage on the receiver inputs.
3. Exclude any static ground shift of 50 mV.
4. High Speed Differential RTERM is enabled when both DP and DN are below this voltage.
**Table 3.26. Soft D-PHY Output Timing and Levels**
|**Symbol**<br>~~a~~|**Description**|**Conditions**|**Min**|**Typ**|**Max**|**Unit**|
|---|---|---|---|---|---|---|
|**High Speed(Differential) Output DC Specifications**<br>~~a~~|||||||
|VCMTX<br>~~a~~|Common-mode Voltage in High Speed Mode|—|150|200|250|mV|
||ΔVCMTX(1,0)|<br>~~a~~|VCMTXMismatch Between Differential HIGH<br>and LOW|—|—|—|5|mV|
||VOD|<br>~~a~~<br>~~ee~~|Output Differential Voltage<br>~~ee~~<br>||D-PHY-P – D-PHY-<br>N||140|200|270|mV|
||ΔVOD|<br>~~a~~<br>~~ee~~|VODMismatch Between Differential HIGH and<br>LOW<br>~~ee~~<br>|—|—|—|10|mV|
|VOHHS<br>~~ee~~|Single-Ended Output HIGH Voltage<br>~~ee~~<br>~~a~~|—<br>~~GO~~|—<br>~~GO~~|—<br>~~GO~~|360<br>~~GO~~|mV<br>~~GO~~|
|ZOS<br>~~ee~~<br>~~eG~~|Single Ended Output Impedance<br>~~ee~~<br><br>~~eG~~|—<br>~~eG~~|37.5<br>~~eG~~|50<br>~~eG~~|80<br>~~eG~~|Ω<br>~~eG~~|
|ΔZOS<br>~~eG~~<br>~~a~~|ZOSmismatch<br>~~eG~~<br>~~a~~|—<br>~~eG~~<br>~~GO~~|—<br>~~eG~~<br>~~GO~~|—<br>~~eG~~<br>~~GO~~|20<br>~~eG~~<br>~~GO~~|%<br>~~eG~~<br>~~GO~~|
|**High Speed(Differential) Output AC Specifications**<br>~~a a~~<br>~~GO~~<br>~~eeeG~~|||||||
|ΔVCMTX(LF)<br>~~ee~~<br>~~ee~~|Common-Mode Variation, 50 MHz–450 MHz<br>~~eG~~<br>~~a~~|—<br>~~eG~~<br>~~GO~~|—<br>~~eG~~<br>~~GO~~|—<br>~~eG~~<br>~~GO~~|25<br>~~eG~~<br>~~GO~~|mVRMS<br>~~eG~~<br>~~GO~~|
|ΔVCMTX(HF)<br>~~ee~~<br>~~ee~~|Common-Mode Variation, above 450 MHz<br>~~eG~~<br>~~a~~|—<br>~~eG~~<br>~~GO~~|—<br>~~eG~~<br>~~GO~~|—<br>~~eG~~<br>~~GO~~|15<br>~~eG~~<br>~~GO~~|mVRMS<br>~~eG~~<br>~~GO~~|
|tR<br>~~ee~~<br>~~a~~|Output 20%–80% Rise Time<br>Output 80%–20% Fall Time<br>~~a~~<br>~~ee~~|0.08 Gbps ≤ tR≤ 1.00<br>Gbps<br>~~GO~~|—<br>~~GO~~|—<br>~~GO~~|0.30<br>~~GO~~|UI<br>~~GO~~|
|||1.00 Gbps < tR≤ 1.50<br>Gbps<br>~~re~~|—<br>~~re~~|—<br>~~re~~|0.35<br>~~re~~|UI<br>~~re~~|
|tF<br>~~a~~|Output Data Valid After CLK Output<br>~~ee~~|0.08 Gbps ≤ tF≤ 1.00<br>Gbps|—|—|0.30|UI|
© 2021-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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FPGA-DS-02049-1.8
**CrossLink-NX Family**
**Data Sheet**
|**Symbol**<br>~~pO~~<br>~~a~~|**Description**<br>~~pO~~<br>~~ee~~|**Conditions**<br>~~pO~~|**Min**<br>~~pO~~|**Typ**<br>~~pO~~|**Max**<br>~~pO~~|**Unit**<br>~~pO~~|
|---|---|---|---|---|---|---|
|~~a~~|~~ee~~|1.00 Gbps < tF≤ 1.50<br>Gbps|—|—|0.35|UI|
|**Low Power(Single-Ended) Output DC Specifications**<br>~~a~~<br>~~ee~~|||||||
|VOH<br>~~a ~~<br>~~ee~~|Low Power Mode Output HIGH Voltage<br> ~~GO~~<br>~~GG~~|0.08 Gbps – 1.5 Gbps<br>~~GO~~<br>~~GG~~|1.07<br>~~GO~~<br>~~GG~~|1.2<br>~~GO~~<br>~~GG~~|1.3<br>~~GO~~<br>~~GG~~|V<br>~~GO~~<br>~~GG~~|
|VOL<br>~~ee~~|Low Power Mode Input LOW Voltage<br>~~GG~~|—<br>~~GG~~|–50<br>~~GG~~|—<br>~~GG~~|50<br>~~GG~~|mV<br>~~GG~~|
|ZOLP<br>~~ee~~<br>~~a a~~|Output Impedance in Low Power Mode<br>~~GG~~<br>~~a~~|—<br>~~GG~~<br>~~GO~~|110<br>~~GG~~<br>~~GO~~|—<br>~~GG~~<br>~~GO~~|—<br>~~GG~~<br>~~GO~~|Ω<br>~~GG~~<br>~~GO~~|
|**Low Power(Single-Ended) Output AC Specifications**<br>~~eea~~<br>~~GO~~|||||||
|tRLP<br>~~ee~~<br>~~ee~~|15%–85% Rise Time<br>~~a~~|—<br>~~GO~~|—<br>~~GO~~|—<br>~~GO~~|25<br>~~GO~~|ns<br>~~GO~~|
|tFLP<br>~~ee~~<br>~~ee~~|85%–15% Fall Time<br>~~a~~|—<br>~~GO~~|—<br>~~GO~~|—<br>~~GO~~|25<br>~~GO~~|ns<br>~~GO~~|
|tREOT<br>~~ee~~|HS – LP Mode Rise and Fall Time, 30%–85%|—|—|—|35|ns|
|TLP-PULSE-TX<br>~~i~~|Pulse Width of the LP Exclusive-OR Clock|First LP XOR Clock<br>Pulse after STOP<br>State or Last Pulse<br>before STOP State<br>~~ne~~|40<br>~~ne~~|—<br>~~ne~~|—<br>~~ne~~|ns<br>~~ne~~|
|||All Other Pulses<br>~~ne~~|20<br>~~ne~~|—<br>~~ne~~|—<br>~~ne~~|ns<br>~~ne~~|
|TLP-PER-TX<br>~~Ge~~|Period of the LP Exclusive-OR Clock<br>~~Ge~~|—<br>~~Ge~~|90<br>~~Ge~~|—<br>~~Ge~~|—<br>~~Ge~~|ns<br>~~Ge~~|
|CLOAD<br>~~a ~~|Load Capacitance<br> ~~a~~|—<br>~~GG~~|0<br>~~GG~~|—<br>~~GG~~|70<br>~~GG~~|pF<br>~~GG~~|
**Table 3.27. Soft D-PHY Clock Signal Specification**
|**Symbol**|**Description**|**Conditions**|**Min**|**Typ**|**Max**|**Unit**|
|---|---|---|---|---|---|---|
|**Clock Signal Specification**|||||||
|UI<br>Instantaneous|UIINST|—|—|—|12.5|ns|
|UI Variation|∆UI|—|–10%|—|10%|UI|
|||—|–5%|—|5%|UI|
**Table 3.28. Soft D-PHY Data-Clock Timing Specifications**
|**Symbol**<br>~~a~~|**Description**<br>~~a~~|**Conditions**<br>~~FO~~|**Min**<br>~~FO~~|**Typ**<br>~~GO~~|**Max**|**Unit**|
|---|---|---|---|---|---|---|
|**Data-Clock Timing Specifications**<br>~~a a~~<br>~~FO~~<br>~~GO~~|||||||
|TSKEW[TX]<br>~~Ce~~|Data to Clock Skew<br>~~Ce~~|0.08 Gbps ≤ TSKEW[TX]<br>≤ 1.00 Gbps<br>~~Ce~~|-0.15<br>~~Ce~~|—<br>~~Ce~~|0.15<br>~~Ce~~|UIINST<br>~~Ce~~|
|||1.00 Gbps < TSKEW[TX]<br>≤ 1.50 Gbps<br>~~Ce~~<br>~~ee~~|-0.20<br>~~Ce~~<br>~~ee~~|—<br>~~Ce~~<br>~~ee~~|0.20<br>~~Ce~~<br>~~ee~~|UIINST<br>~~Ce~~<br>~~ee~~|
|TSKEW[TLIS]<br>~~Ce~~<br>~~ee~~|Data to Clock Skew<br>~~Ce~~<br>~~ee~~|0.08 Gbps ≤ TSKEW[TLIS]<br>≤ 1.00 Gbps<br>~~Ce~~<br>~~ee~~<br>~~ee~~|-0.20<br>~~Ce~~<br>~~ee~~<br>~~ee~~|—<br>~~Ce~~<br>~~ee~~<br>~~ee~~|0.20<br>~~Ce~~<br>~~ee~~<br>~~ee~~|UIINST<br>~~Ce~~<br>~~ee~~<br>~~ee~~|
|||1.00 Gbps < TSKEW[TLIS]<br>≤ 1.50 Gbps<br>~~ee~~<br>~~a~~|-0.10<br>~~ee~~<br>~~a~~|—<br>~~ee~~<br>~~a~~|0.10<br>~~ee~~<br>~~a~~|UIINST<br>~~ee~~<br>~~a~~|
|TSETUP[RX]<br>~~ase~~|Input Data Setup Before CLK<br>~~ase~~|0.08 Gbps ≤ TSETUP[RX]<br>≤ 1.00 Gbps<br>~~ase~~|0.15<br>~~ase~~|—<br>~~ase~~|—<br>~~ase~~|UI<br>~~ase~~|
|||1.00 Gbps < TSETUP[RX]<br>≤ 1.50 Gbps<br>~~ase~~<br>~~pT~~|0.20<br>~~ase~~<br>~~pT~~|—<br>~~ase~~<br>~~pT~~|—<br>~~ase~~<br>~~pT~~|UI<br>~~ase~~<br>~~pT~~|
|THOLD[RX]<br>~~ase~~<br>~~ase~~|Input Data Hold After CLK<br>~~ase~~<br>~~ase~~|0.08 Gbps ≤ THOLD[RX]<br>≤ 1.00 Gbps<br>~~ase~~<br>~~pT~~<br>~~ase~~|0.15<br>~~ase~~<br>~~pT~~<br>~~ase~~|—<br>~~ase~~<br>~~pT~~<br>~~ase~~|—<br>~~ase~~<br>~~pT~~<br>~~ase~~|UI<br>~~ase~~<br>~~pT~~<br>~~ase~~|
|||1.00 Gbps < THOLD[RX]<br>≤ 1.50 Gbps<br>~~ase~~<br>~~a~~|0.20<br>~~ase~~<br>~~a~~|—<br>~~ase~~<br>~~a~~|—<br>~~ase~~<br>~~a~~|UI<br>~~ase~~<br>~~a~~|
FPGA-DS-02049-1.8
69
**CrossLink-NX Family Data Sheet**
## **3.12.7. Differential HSTL15D (Output Only)**
Differential HSTL outputs are implemented as a pair of complementary single-ended HSTL outputs.
## **3.12.8. Differential SSTL135D, SSTL15D (Output Only)**
Differential SSTL is used for differential clock in DDR3/DDR3L memory interface. All differential SSTL outputs are implemented as a pair of complementary single-ended SSTL outputs. All allowable single-ended output classes (class I and class II) are supported.
## **3.12.9. Differential HSUL12D (Output Only)**
Differential HSUL is used for differential clock in LPDDR2/LPDDR3 memory interface. All differential HSUL outputs are implemented as a pair of complementary single-ended HSUL12 outputs. All allowable single-ended drive strengths are supported.
## **3.12.10. Differential LVCMOS25D, LVCMOS33D, LVTTL33D (Output Only)**
Differential LVCMOS and LVTTL outputs are implemented as a pair of complementary single-ended outputs. All allowable single-ended output drive strengths are supported.
## **3.13. Maximum sysI/O Buffer Speed**
**Table 3.29. Maximum I/O Buffer Speed[1, 2, 3, 4, 7 ]**
|**Buffer**<br>~~Ge~~|**Description**<br>~~Ge~~|**Banks**<br>~~Ge~~|**Max**<br>~~Ge~~|**Unit**<br>~~Ge~~|
|---|---|---|---|---|
|**Maximum sysI/O Input Frequency**<br>~~pe~~|||||
|**Single-Ended**<br>~~Pe~~|||||
|LVCMOS33<br>~~Ge~~|LVCMOS33, VCCIO= 3.3 V<br>~~Ge~~|0, 1, 2, 6, 7<br>~~Ge~~|200<br>~~Ge~~|MHz<br>~~Ge~~|
|LVTTL33<br>~~Ce~~|LVTTL33, VCCIO= 3.3 V<br>~~Ce~~|0, 1, 2, 6, 7<br>~~Ce~~|200<br>~~Ce~~|MHz<br>~~Ce~~|
|LVCMOS25<br>~~GG~~|LVCMOS25, VCCIO= 2.5 V<br>~~GG~~|0, 1, 2, 6, 7<br>~~GG~~|200<br>~~GG~~|MHz<br>~~GG~~|
|LVCMOS185<br>~~GG~~<br>~~a~~|LVCMOS18, VCCIO= 1.8 V<br>~~GG~~<br>~~Ge~~|0, 1, 2, 6, 7<br>~~GG~~<br>~~Ge~~<br>~~GO~~|200<br>~~GG~~<br>~~Ge~~|MHz<br>~~GG~~<br>~~Ge~~|
|LVCMOS18H<br>~~Ge~~|LVCMOS18, VCCIO= 1.8 V<br>~~Ge~~|3, 4, 5<br>~~Ge~~<br>~~GO~~|200<br>~~Ge~~|MHz<br>~~Ge~~|
|LVCMOS155<br>~~Ge~~<br>~~Ge~~|LVCMOS15, VCCIO= 1.5 V<br>~~Ge~~<br>~~Ge~~|0, 1, 2, 6, 7<br>~~Ge~~<br>~~GO~~<br>~~Ge~~|100<br>~~Ge~~<br>~~Ge~~|MHz<br>~~Ge~~<br>~~Ge~~|
|LVCMOS15H5<br>~~Ge~~<br>~~a~~|LVCMOS15, VCCIO= 1.5 V<br>~~Ge~~<br>~~Ge~~|3, 4, 5<br>~~Ge~~<br>~~Ge~~|150<br>~~Ge~~<br>~~Ge~~|MHz<br>~~Ge~~<br>~~Ge~~|
|LVCMOS125<br>~~GG~~|LVCMOS12, VCCIO= 1.2 V<br>~~GG~~|0, 1, 2, 6, 7<br>~~GG~~|50<br>~~GG~~|MHz<br>~~GG~~|
|LVCMOS12H5<br>~~GG~~<br>~~Ge~~|LVCMOS12, VCCIO= 1.2 V<br>~~GG~~<br>~~Ge~~|3, 4, 5<br>~~GG~~<br>~~Ge~~|100<br>~~GG~~<br>~~Ge~~|MHz<br>~~GG~~<br>~~Ge~~|
|LVCMOS105<br>~~GG~~|LVCMOS 1.0, VCCIO= 1.2 V<br>~~GG~~|0, 1, 2, 6, 7<br>~~GG~~|50<br>~~GG~~|MHz<br>~~GG~~|
|LVCMOS10H5<br>~~GG~~<br>~~Ge~~|LVCMOS 1.0, VCCIO= 1.0 V<br>~~GG~~<br>~~Ge~~|3, 4, 5<br>~~GG~~<br>~~Ge~~|50<br>~~GG~~<br>~~Ge~~|MHz<br>~~GG~~<br>~~Ge~~|
|LVCMOS10R<br>~~GG~~|LVCMOS 1.0, VCCIOindependent<br>~~GG~~|3, 4, 5<br>~~GG~~|50<br>~~GG~~|MHz<br>~~GG~~|
|SSTL15_I, SSTL15_II<br>~~GG~~<br>~~Ge~~|SSTL_15, VCCIO= 1.5 V<br>~~GG~~<br>~~Ge~~|3, 4, 5<br>~~GG~~<br>~~Ge~~|1066<br>~~GG~~<br>~~Ge~~|Mbps<br>~~GG~~<br>~~Ge~~|
|SSTL135_I, SSTL135_II<br>~~GG~~|SSTL_135, VCCIO= 1.35 V<br>~~GG~~|3, 4, 5<br>~~GG~~|1066<br>~~GG~~|Mbps<br>~~GG~~|
|HSUL12<br>~~GG~~<br>~~ee~~|HSUL_12, VCCIO= 1.2 V<br>~~GG~~<br>~~ee~~|3, 4, 5<br>~~GG~~<br>~~ee~~|1066<br>~~GG~~<br>~~ee~~|Mbps<br>~~GG~~<br>~~ee~~|
|HSTL15<br>~~ee~~<br>~~a~~|HSTL15, VCCIO= 1.5 V<br>~~ee~~|3, 4, 5<br>~~ee~~|250<br>~~ee~~|Mbps<br>~~ee~~|
|MIPI D-PHY (LP Mode)<br>~~Ge~~|MIPI, Low Power Mode, VCCIO= 1.2 V<br>~~Ge~~|3, 4, 5<br>~~Ge~~|10<br>~~Ge~~|Mbps<br>~~Ge~~|
|**Differential8 **<br>~~pe~~|||||
|LVDS<br>~~pe~~|LVDS, VCCIOindependent QFN72, caBGA256,<br>csBGA289, and caBGA400<br>~~pe~~|3, 4, 5<br>~~pe~~|1250<br>~~pe~~|Mbps<br>~~pe~~|
||LVDS, VCCIOindependent csfBGA121|3, 4, 5|1500|Mbps|
|subLVDS|subLVDS, VCCIOindependent QFN72,<br>caBGA256, csBGA289, and caBGA400|3, 4, 5|1250|Mbps|
© 2021-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
70
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**CrossLink-NX Family**
**Data Sheet**
|**Buffer**<br>~~Ge~~<br>~~a~~|**Description**<br>~~Ge~~|**Banks**<br>~~Ge~~|**Max**<br>~~Ge~~|**Unit**<br>~~Ge~~|
|---|---|---|---|---|
|~~a~~|subLVDS, VCCIOindependent csfBGA121|3, 4, 5|1500|Mbps|
|SLVS<br>~~a~~|SLVS similar to MIPI HS, VCCIOindependent<br>QFN72, caBGA256, csBGA289, caBGA400|3, 4, 5|1250|Mbps|
||SLVS similar to MIPI HS, VCCIOindependent<br>csfBGA121|3, 4, 5|1500|Mbps|
|MIPI D-PHY (HS Mode)|MIPI, High Speed Mode, VCCIO= 1.2 V<br>QFN72|3, 4, 5|1250|Mbps|
||MIPI, High Speed Mode, VCCIO= 1.2 V<br>csfBGA121, caBGA256, csBGA289, caBGA400|3, 4, 5|1500|Mbps|
|SSTL15D<br>~~a~~|Differential SSTL15, VCCIOindependent|3, 4, 5|1066|Mbps|
|SSTL135D<br>~~eG~~|Differential SSTL135, VCCIOindependent<br>~~eG~~|3, 4, 5<br>~~eG~~|1066<br>~~eG~~|Mbps<br>~~eG~~|
|HUSL12D<br>~~a~~|Differential HSUL12, VCCIOindependent<br>~~ee~~|3, 4, 5|1066|Mbps|
|HSTL15D<br>~~a~~|Differential HSTL15, VCCIOindependent<br>~~ee~~|3, 4, 5|250|Mbps|
|**Maximum sysI/O Output Frequency**<br>~~a~~<br>~~ee~~<br>~~PR~~|||||
|**Single-Ended**<br>~~pe~~|||||
|LVCMOS33 (all drive strengths)<br>~~Ge~~|LVCMOS33, VCCIO= 3.3 V<br>~~Ge~~|0, 1, 2, 6, 7<br>~~Ge~~|200<br>~~Ge~~|MHz<br>~~Ge~~|
|LVCMOS33 (RS50)<br>~~Ce~~|LVCMOS33, VCCIO= 3.3 V, RSERIES= 50 Ω<br>~~Ce~~|0, 1, 2, 6, 7<br>~~Ce~~|200<br>~~Ce~~|MHz<br>~~Ce~~|
|LVTTL33 (all drive strengths)<br>~~Ce~~<br>~~a~~|LVTTL33, VCCIO= 3.3 V<br>~~Ce~~<br>~~GC~~|0, 1, 2, 6, 7<br>~~Ce~~<br>~~GC~~|200<br>~~Ce~~<br>~~GC~~|MHz<br>~~Ce~~<br>~~GC~~|
|LVTTL33 (RS50)<br>~~Ge~~|LVTTL33, VCCIO= 3.3 V, RSERIES= 50 Ω<br>~~Ge~~|0, 1, 2, 6, 7<br>~~Ge~~|200<br>~~Ge~~|MHz<br>~~Ge~~|
|LVCMOS25 (all drive strengths)<br>~~Ge~~|LVCMOS25, VCCIO= 2.5 V<br>~~Ge~~|0, 1, 2, 6, 7<br>~~Ge~~|200<br>~~Ge~~|MHz<br>~~Ge~~|
|LVCMOS25 (RS50)<br>~~GG~~|LVCMOS25, VCCIO= 2.5 V, RSERIES= 50 Ω<br>~~GG~~|0, 1, 2, 6, 7<br>~~GG~~|200<br>~~GG~~|MHz<br>~~GG~~|
|LVCMOS18 (all drive strengths)<br>~~GG~~<br>~~Ge~~|LVCMOS18, VCCIO= 1.8 V<br>~~GG~~<br>~~Ge~~|0, 1, 2, 6, 7<br>~~GG~~<br>~~Ge~~|200<br>~~GG~~<br>~~Ge~~|MHz<br>~~GG~~<br>~~Ge~~|
|LVCMOS18 (RS50)<br>~~Ge~~<br>~~a~~|LVCMOS18, VCCIO= 1.8 V, RSERIES= 50 Ω<br>~~Ge~~<br>~~Ge~~|0, 1, 2, 6, 7<br>~~Ge~~<br>~~Ge~~|200<br>~~Ge~~<br>~~Ge~~|MHz<br>~~Ge~~<br>~~Ge~~|
|LVCMOS18H (all drive strengths)<br>~~a~~|LVCMOS18, VCCIO= 1.8 V<br>~~GG~~|3, 4, 5<br>~~GG~~|200<br>~~GG~~|MHz<br>~~GG~~|
|LVCMOS18H (RS50)<br>~~a~~<br>~~Ge~~|LVCMOS18, VCCIO= 1.8 V, RSERIES= 50 Ω<br>~~GG~~<br>~~Ge~~|3, 4, 5<br>~~GG~~<br>~~Ge~~|200<br>~~GG~~<br>~~Ge~~|MHz<br>~~GG~~<br>~~Ge~~|
|LVCMOS15 (all drive strengths)<br>~~Ge~~<br>~~a~~|LVCMOS15, VCCIO= 1.5 V<br>~~Ge~~<br>~~Ge~~|0, 1, 2, 6, 7<br>~~Ge~~<br>~~Ge~~|100<br>~~Ge~~<br>~~Ge~~|MHz<br>~~Ge~~<br>~~Ge~~|
|LVCMOS15H (all drive strengths)<br>~~a~~|LVCMOS15, VCCIO= 1.5 V<br>~~GG~~|3, 4, 5<br>~~GG~~|150<br>~~GG~~|MHz<br>~~GG~~|
|LVCMOS12 (all drive strengths)<br>~~a~~<br>~~Ge~~<br>~~a~~|LVCMOS12, VCCIO= 1.2 V<br>~~GG~~<br>~~Ge~~|0, 1, 2, 6, 7<br>~~GG~~<br>~~Ge~~<br>~~GO~~|50<br>~~GG~~<br>~~Ge~~|MHz<br>~~GG~~<br>~~Ge~~|
|LVCMOS12H (all drive strengths)<br>~~Ge~~<br>~~a~~<br>~~a~~|LVCMOS12, VCCIO= 1.2 V<br>~~Ge~~<br>~~Ce~~|3, 4, 5<br>~~Ge~~<br>~~GO~~|100<br>~~Ge~~|MHz<br>~~Ge~~|
|LVCMOS10H (all drive strengths)<br>~~Ge~~<br>~~a~~<br>~~a~~|LVCMOS12, VCCIO= 1.2 V<br>~~Ge~~<br>~~Ce~~|3, 4, 5<br>~~Ge~~<br>~~GO~~|50<br>~~Ge~~|MHz<br>~~Ge~~|
|SSTL15_I, SSTL15_II<br>~~a~~|SSTL_15, VCCIO= 1.5 V<br>~~Ce~~<br>~~GG~~|3, 4, 5<br>~~GG~~|1066<br>~~GG~~|Mbps<br>~~GG~~|
|SSTL135_I, SSTL135_II<br>~~a~~<br>~~Ge~~|SSTL_135, VCCIO= 1.35 V<br>~~Ce~~<br>~~GG~~<br>~~Ge~~|3, 4, 5<br>~~GG~~<br>~~Ge~~|1066<br>~~GG~~<br>~~Ge~~|Mbps<br>~~GG~~<br>~~Ge~~|
|HSUL12 (all drive strengths)<br>~~Ge~~<br>~~a~~|HSUL_12, VCCIO= 1.2 V<br>~~Ge~~<br>~~Ge~~|3, 4, 5<br>~~Ge~~<br>~~Ge~~|1066<br>~~Ge~~<br>~~Ge~~|Mbps<br>~~Ge~~<br>~~Ge~~|
|HSTL15<br>~~GG~~|HSTL15, VCCIO= 1.5 V<br>~~GG~~|3, 4, 5<br>~~GG~~|250<br>~~GG~~|Mbps<br>~~GG~~|
|MIPI D-PHY (LP Mode)<br>~~De~~|MIPI, Low Power Mode, VCCIO= 1.2 V<br>~~De~~|3, 4, 5<br>~~De~~|10<br>~~De~~|Mbps<br>~~De~~|
|**Differential8 **<br>~~pe~~|||||
|LVDS<br>~~pe~~<br>~~eee~~|LVDS, VCCIO= 1.8 V QFN72, caBGA256,<br>csBGA289, and caBGA400<br>~~pe~~<br>~~eee~~|3, 4, 5<br>~~pe~~<br>~~eee~~|1250<br>~~pe~~<br>~~eee~~|Mbps<br>~~pe~~<br>~~eee~~|
||LVDS, VCCIO= 1.8 V csfBGA121<br>~~eee~~|3, 4, 5<br>~~eee~~|1500<br>~~eee~~|Mbps<br>~~eee~~|
|LVDS25E6<br>~~eee~~<br>~~Ge~~|LVDS25, Emulated, VCCIO= 2.5 V<br>~~eee~~<br>~~Ge~~|0, 1, 2, 6, 7<br>~~eee~~<br>~~Ge~~|400<br>~~eee~~<br>~~Ge~~|Mbps<br>~~eee~~<br>~~Ge~~|
|SubLVDSE6<br>~~GG~~|subLVDS, Emulated, VCCIO= 1.8 V<br>~~GG~~|0, 1, 2, 6, 7<br>~~GG~~|400<br>~~GG~~|Mbps<br>~~GG~~|
|SubLVDSEH6<br>~~GG~~<br>~~FC~~|subLVDS, Emulated, VCCIO= 1.8 V<br>~~GG~~<br>~~FC~~|3, 4, 5<br>~~GG~~<br>~~FC~~|800<br>~~GG~~<br>~~FC~~|Mbps<br>~~GG~~<br>~~FC~~|
© 2021-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02049-1.8
71
**CrossLink-NX Family Data Sheet**
|**Buffer**|**Description**|**Banks**|**Max**|**Unit**|
|---|---|---|---|---|
|SLVS|SLVS similar to MIPI, VCCIO= 1.2 V<br>QFN72, caBGA256, csBGA289, caBGA400|3, 4, 5|1250|Mbps|
||SLVS similar to MIPI, VCCIO= 1.2 V<br>csfBGA121|3, 4, 5|1500|Mbps|
|MIPI D-PHY (HS Mode)|MIPI, High Speed Mode, VCCIO= 1.2 V<br>QFN72|3, 4, 5|1250|Mbps|
||MIPI, High Speed Mode, VCCIO= 1.2 V<br>csfBGA121, caBGA256, csBGA289, caBGA400|3, 4, 5|1500|Mbps|
|SSTL15D|Differential SSTL15, VCCIO= 1.5 V|3, 4, 5|1066|Mbps|
|SSTL135D|Differential SSTL135, VCCIO= 1.35 V|3, 4, 5|1066|Mbps|
|HUSL12D|Differential HSUL12, VCCIO= 1.2 V|3, 4, 5|1066|Mbps|
|HSTL15D|Differential HSTL15, VCCIO= 1.5 V|3, 4, 5|250|Mbps|
**Notes** :
1. Maximum I/O speed is the maximum switching rate of the I/O operating within the guidelines of the defining standard. The actual interface speed performance using the I/O also depends on other factors, such as internal and external timing.
2. These numbers are characterized but not test on every device.
3. Performance is specified in MHz, as defined in clock rate when the sysI/O is used as pin. For data rate performance, this can be converted to Mbps, which equals to 2 times the clock rate.
4. LVCMOS and LVTTL are measured with load specified in Table 3.50.
5. These LVCMOS inputs can be placed in different VCCIO voltage. Performance may vary. Please refer to Lattice Design Software
6. These emulated outputs performance is based on externally properly terminated as described in LVDS25E (Output Only) and SubLVDSE/SubLVDSEH (Output Only).
7. All speeds are measured with fast slew.
8. For maximum differential I/O performance only Differential I/O should be placed in the bottom I/O banks. If this is not possible, the following will impact on maximum performance:
- a. If Fast Slew Rate LVCMOS I/O are used, they should be limited to no more than nine I/O (adjacent), four I/O (same bank), 55 I/O (left/right banks) to keep degradation below 50%.
- b. If non-Differential I/O (SLOW SLEW) are placed on the bottom but not within the same bank as differential I/O, then the maximum Differential performance is degraded to 70% of original when 21 aggressors are toggling.
- c. If non-Differential I/O (SLOW SLEW) are placed within the same bank as Differential I/O then the maximum performance is degraded to 50% of original when 16 aggressor are toggling.
- d. No performance impact if MIPI LP and MIPI HS are in the same bank.
- e. If Differential RX/TX I/O are both placed within the same bank then the maximum performance is degraded to 90%.
- f. For DDR3/3L, LPDDR2/3 separate DQ/DQS groups from Address/Commands/CLK groups into separate banks.
## **3.14. Typical Building Block Function Performance**
These building block functions can be generated using Lattice Design software tool. Exact performance may vary with the device and the design software tool version. The design software tool uses internal parameters that have been characterized but are not tested on every device.
**Table 3.30. Pin-to-Pin Performance**
|**Function**|**Typ. @ VCC =**<br>**1.0 V**|**Unit**|
|---|---|---|
|16-bit Decoder (I/O configured with LVCMOS18, Left and Right Banks)|5.5|ns|
|16-bit Decoder (I/O configured with HSTL15_I, Bottom Banks)|5.1|ns|
|16:1 Mux (I/O configured with LVCMOS18, Left and Right Banks)|6|ns|
|16:1 Mux (I/O configured with HSTL15_I, Bottom Banks)|6.1|ns|
**Note** : These functions are generated using Lattice Radiant Design software tool. Exact performance may vary with the device and the design software tool version. The design software tool uses internal parameters that have been characterized but are not tested on every device.
© 2021-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
72
FPGA-DS-02049-1.8
**CrossLink-NX Family Data Sheet**
**Table 3.31. Register-to-Register Performance**
|**Function**|**Typ. @ VCC =**<br>**1.0 V**|**Unit**|
|---|---|---|
|**Basic Functions**<br>~~Pe~~|||
|16-bit Adder<br>~~a~~|5002<br>~~a~~|MHz<br>~~a~~|
|32-bit Adder<br>~~a~~<br>~~a~~|496<br>~~a~~<br>~~a~~|MHz<br>~~a~~<br>~~a~~|
|16-bit Counter<br>~~a~~|402<br>~~a~~|MHz<br>~~a~~|
|32-bit Counter<br>~~a~~|371<br>~~a~~|MHz<br>~~a~~|
|**Embedded Memory Functions**<br>~~a~~<br>~~Ee~~|||
|512 × 36 Single Port RAM, with Output Register<br>~~a~~|5002<br>~~a~~|MHz<br>~~a~~|
|1024 × 18 True-Dual Port RAM using same clock, with EBR Output Registers<br>~~a~~<br>~~a~~|5002<br>~~a~~<br>~~a~~|MHz<br>~~a~~<br>~~a~~|
|1024 × 18 True-Dual Port RAM usingasynchronous clocks, with EBR Output Registers<br>~~a~~|5002<br>~~a~~|MHz<br>~~a~~|
|**Large Memory Functions**<br>~~pe~~|||
|32k × 32 Single Port RAM, with Output Register<br>~~a~~|1652<br>~~a~~|MHz<br>~~a~~|
|32k × 32 Single Port RAM with ECC, with Output Register<br>~~a~~|1302<br>~~a~~|MHz<br>~~a~~|
|32k × 32 True-Dual Port RAM using same clock, with Output Registers<br>~~a~~<br>~~a~~|3402<br>~~a~~<br>~~a~~|MHz<br>~~a~~<br>~~a~~|
|**Distributed Memory Functions**<br>~~pe~~|||
|16 × 4 Single Port RAM (One PFU)<br>~~pe~~<br>~~a~~|5002<br>~~pe~~<br>~~a~~|MHz<br>~~pe~~<br>~~a~~|
|16 × 2 Pseudo-Dual Port RAM (One PFU)<br>~~a~~|5002<br>~~a~~|MHz<br>~~a~~|
|16 × 4 Pseudo-Dual Port (Two PFUs)<br>~~a~~<br>~~a~~|5002<br>~~a~~<br>~~a~~|MHz<br>~~a~~<br>~~a~~|
|**DSP Functions**<br>~~Pe~~|||
|9 × 9 Multiplier with Input Output Registers<br>~~a~~|376<br>~~a~~|MHz<br>~~a~~|
|18 × 18 Multiplier with Input/Output Registers<br>~~a~~|287<br>~~a~~|MHz<br>~~a~~|
|36 × 36 Multiplier with Input/Output Registers<br>~~a~~|200<br>~~a~~|MHz<br>~~a~~|
|MAC 18 × 18 with Input/Output Registers<br>~~a~~|203<br>~~a~~|MHz<br>~~a~~|
|MAC 18 × 18 with Input/Pipelined/Output Registers<br>~~a~~<br>~~a~~|287<br>~~a~~<br>~~a~~|MHz<br>~~a~~<br>~~a~~|
|MAC 36 × 36 with Input/Output Registers<br>~~a~~|119<br>~~a~~|MHz<br>~~a~~|
|MAC 36 × 36 with Input/Pipelined/Output Registers<br>~~a~~<br>~~pf~~|155<br>~~a~~<br>~~pf~~|MHz<br>~~a~~<br>~~pf~~|
1. The Clock port is configured with LVDS I/O type. Performance Grade: 9_High-Performance_1.0V.
2. Limited by the Minimum Pulse Width of the component
3. These functions are generated using Lattice Radiant design software. Exact performance may vary with the device and the design software tool version. The design software tool uses internal parameters that have been characterized but are not tested on every device.
4. For the Pipelined designs, the number of pipeline stages used are 2.
## **3.15. LMMI**
Table 3.32 summarizes the performance of the LMMI interface with supported IPs. Additional timing requirement and constraint can be identified through the Lattice Radiance design tools.
**Table 3.32. LMMI FMAX Summary**
|**IP**|**FMAX (MHz)**|
|---|---|
|CDR0|73|
|CDR1|70|
|DPHY0|67|
|DPHY1|55|
|CRE|54|
|I2C|38|
|PCIe|57|
© 2021-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02049-1.8
73
**CrossLink-NX Family Data Sheet**
|**IP**|**FMAX (MHz)**|
|---|---|
|PLL_ULC|59|
|PLL_LLC|55|
|PLL_LRC|37|
## **3.16. Derating Timing Tables**
Logic timing provided in the following sections of this data sheet and the Lattice Radiant design tools are worst case numbers in the operating range. Actual delays at nominal temperature and voltage for best case process, can be much better than the values given in the tables. The Lattice Radiant design tool can provide logic timing numbers at a particular temperature and voltage.
## **3.17. External Switching Characteristics**
Over recommended commercial operating conditions.
|**Parameter**<br>~~a~~|**Description**<br>|–**9**<br>|–**9**<br>|–**8**<br>|–**8**<br>|–**7**<br>|–**7**<br>|**Unit**<br>|
|---|---|---|---|---|---|---|---|---|
|||**Min**<br>|**Max**<br>|**Min**<br>|**Max**<br>|**Min**<br>|**Max**<br>||
|**Clocks**<br>|||||||||
|**Primary Clock**<br><br>~~GO~~<br>~~OO~~|||||||||
|fMAX_PRI<br>~~se~~|Frequencyfor PrimaryClock<br>~~se~~|—<br>~~se~~<br>~~GO~~<br>~~GO~~|400<br>~~se~~<br>~~GO~~<br>~~GO~~|—<br>~~se~~<br>~~OO~~<br>~~OC~~|325.2<br>~~se~~<br>~~OO~~<br>~~OC~~|—<br>~~se~~<br>~~OO~~<br>~~OC~~|276<br>~~se~~<br>~~OC~~|MHz<br>~~se~~|
|tW_PRI<br>~~se~~<br>~~Se~~|Clock Pulse Width for PrimaryClock<br>~~se~~<br>~~Se~~|1.125<br>~~se~~<br>~~GO~~<br>~~Se~~<br>~~GO~~|—<br>~~se~~<br>~~GO~~<br>~~Se~~<br>~~GO~~|1.384<br>~~se~~<br>~~OO~~<br>~~Se~~<br>~~OC~~|—<br>~~se~~<br>~~OO~~<br>~~Se~~<br>~~OC~~|1.63<br>~~se~~<br>~~OO~~<br>~~Se~~<br>~~OC~~|—<br>~~se~~<br>~~Se~~<br>~~OC~~|ns<br>~~se~~<br>~~Se~~|
|tSKEW_PRI6<br>~~GO~~|PrimaryClock Skew Within a Device<br>~~GO~~|—<br>~~GO~~<br>~~GO~~|450<br>~~GO~~<br>~~GO~~|—<br>~~OC~~<br>~~GO~~|554<br>~~OC~~<br>~~GO~~|—<br>~~OC~~<br>~~GO~~|653<br>~~OC~~<br>~~GO~~|ps<br>~~GO~~|
|**Edge Clock**<br>~~pn~~|||||||||
|fMAX_EDGE<br>~~a GG~~<br>~~es~~|Frequencyfor Edge Clock Tree<br>~~GG~~<br>|—<br>~~GG~~<br>~~GO~~<br>|800<br>~~GG~~<br>~~GO~~<br>|—<br>~~GG~~<br>~~OO~~<br>|650.4<br>~~GG~~<br>~~OO~~<br>|—<br>~~GG~~<br>~~OO~~<br>|551.7<br>~~GG~~<br>|MHz<br>~~GG~~<br>|
|tW_EDGE<br>~~a GG~~<br>~~ee~~<br>~~es~~|Clock Pulse Width for Edge Clock<br>~~GG~~<br>~~ee~~<br>|0.537<br>~~GG~~<br>~~ee~~<br>~~GO~~<br>|—<br>~~GG~~<br>~~ee~~<br>~~GO~~<br>|0.661<br>~~GG~~<br>~~ee~~<br>~~OO~~<br>|—<br>~~GG~~<br>~~ee~~<br>~~OO~~<br>|0.779<br>~~GG~~<br>~~ee~~<br>~~OO~~<br>|—<br>~~GG~~<br>~~ee~~<br>|ns<br>~~GG~~<br>~~ee~~<br>|
|tSKEW_EDGE6<br>~~ee~~<br>~~es~~|Edge Clock Skew Within a Device<br>~~ee~~<br>~~De~~|—<br>~~ee~~<br>~~GO~~<br>~~De~~|120<br>~~ee~~<br>~~GO~~<br>~~De~~|—<br>~~ee~~<br>~~OO~~<br>~~De~~|148<br>~~ee~~<br>~~OO~~<br>~~De~~|—<br>~~ee~~<br>~~OO~~<br>~~De~~|174<br>~~ee~~<br>~~De~~|ps<br>~~ee~~<br>~~De~~|
|**Generic SDR Input**<br>~~GO OO~~<br>~~esDe~~<br>~~pe~~|||||||||
|**General I/O Pin Parameters Using Dedicated Primary Clock Input without PLL**<br>~~pe~~|||||||||
|tCO<br>~~GO~~<br>~~es~~|Clock to Output - PIO Output Register<br>~~GO~~<br>|—<br>~~GO~~<br>|6.45<br>~~GO~~<br>|—<br>~~GO~~<br>~~OO~~<br>|6.64<br>~~GO~~<br>~~OO~~<br>|—<br>~~GO~~<br>~~OO~~<br>|7.83<br>~~GO~~<br>|ns<br>~~GO~~<br>|
|tSU<br>~~GO~~<br>~~GO~~<br>~~es~~<br>~~ee~~|Clock to Data Setup- PIO Input Register<br>~~GO~~<br>~~GO~~<br><br>|0<br>~~GO~~<br>~~GO~~<br><br>|—<br>~~GO~~<br>~~GO~~<br><br>|0<br>~~GO~~<br>~~GO~~<br>~~OO~~<br><br>~~OO~~<br>|—<br>~~GO~~<br>~~GO~~<br>~~OO~~<br><br>~~OO~~<br>|0<br>~~GO~~<br>~~GO~~<br>~~OO~~<br><br>~~OO~~<br>|—<br>~~GO~~<br>~~GO~~<br><br>|ns<br>~~GO~~<br>~~GO~~<br><br>|
|tH<br>~~GO~~<br>~~es~~<br>~~ee~~|Clock to Data Hold - PIO Input Register<br>~~GO~~<br>~~GO~~<br>|2.94<br>~~GO~~<br>~~GO~~<br>|—<br>~~GO~~<br>~~GO~~<br>|3.32<br>~~GO~~<br>~~OO~~<br>~~GO~~<br>~~OO~~<br>|—<br>~~GO~~<br>~~OO~~<br>~~GO~~<br>~~OO~~<br>|3.92<br>~~GO~~<br>~~OO~~<br>~~GO~~<br>~~OO~~<br>|—<br>~~GO~~<br>~~GO~~<br>|ns<br>~~GO~~<br>~~GO~~<br>|
|tSU_DEL<br>~~es~~<br>~~ee~~|Clock to Data Setup - PIO Input Register with<br>Data Input Delay<br>~~GO~~<br>|1.84<br>~~GO~~<br>|—<br>~~GO~~<br>|1.84<br>~~OO~~<br>~~GO~~<br>~~OO~~<br>|—<br>~~OO~~<br>~~GO~~<br>~~OO~~<br>|1.84<br>~~OO~~<br>~~GO~~<br>~~OO~~<br>|—<br>~~GO~~<br>|ns<br>~~GO~~<br>|
|tH_DEL<br>~~eea~~|Clock to Data Hold - PIO Input Register with<br>Data Input Delay<br>~~a~~|0.16<br>~~a~~|—<br>~~a~~|0.16<br>~~OO~~<br>~~a~~|—<br>~~OO~~<br>~~a~~|0.16<br>~~OO~~<br>~~a~~|—<br>~~a~~|ns<br>~~a~~|
|**General I/O Pin Parameters Using Dedicated Primary Clock Input with PLL**<br>~~a~~<br>~~GO~~<br>~~GO~~|||||||||
|tCOPLL<br>~~Ce~~<br>~~a~~|Clock to Output - PIO Output Register<br>~~Ce~~<br>|—<br>~~Ce~~<br>~~GO~~<br>~~GO~~<br>|4.02<br>~~Ce~~<br>~~GO~~<br>~~GO~~<br>|—<br>~~Ce~~<br>~~GO~~<br>~~GO~~<br>|4.67<br>~~Ce~~<br>~~GO~~<br>~~GO~~<br>|—<br>~~Ce~~<br>~~GO~~<br>~~GO~~<br>|5.51<br>~~Ce~~<br>|ns<br>~~Ce~~<br>|
|tSUPLL<br>~~Se~~<br>~~a~~<br>~~i~~|Clock to Data Setup- PIO Input Register<br>~~Se~~<br><br>|1.23<br>~~GO~~<br>~~Se~~<br>~~GO~~<br><br>|—<br>~~GO~~<br>~~Se~~<br>~~GO~~<br><br>|1.23<br>~~GO~~<br>~~Se~~<br>~~GO~~<br><br>~~OO~~<br>|—<br>~~GO~~<br>~~Se~~<br>~~GO~~<br><br>~~OO~~<br>|1.23<br>~~GO~~<br>~~Se~~<br>~~GO~~<br><br>~~OO~~<br>|—<br>~~Se~~<br><br>|ns<br>~~Se~~<br><br>|
|tHPLL<br>~~a GG~~<br>~~i~~|Clock to Data Hold - PIO Input Register<br>~~GG~~<br>|0.98<br>~~GO~~<br>~~GG~~<br>|—<br>~~GO~~<br>~~GG~~<br>|1.21<br>~~GO~~<br>~~GG~~<br>~~OO~~<br>|—<br>~~GO~~<br>~~GG~~<br>~~OO~~<br>|1.42<br>~~GO~~<br>~~GG~~<br>~~OO~~<br>|—<br>~~GG~~<br>|ns<br>~~GG~~<br>|
|tSU_DELPLL<br>~~a GG~~<br>~~i~~|Clock to Data Setup - PIO Input Register with<br>Data Input Delay<br>~~GG~~<br>|4.74<br>~~GO~~<br>~~GG~~<br>|—<br>~~GO~~<br>~~GG~~<br>|4.74<br>~~GO~~<br>~~GG~~<br>~~OO~~<br>|—<br>~~GO~~<br>~~GG~~<br>~~OO~~<br>|4.74<br>~~GO~~<br>~~GG~~<br>~~OO~~<br>|—<br>~~GG~~<br>|ns<br>~~GG~~<br>|
|tH_DELPLL<br>~~ia~~|Clock to Data Hold - PIO Input Register with<br>Data Input Delay<br>~~a~~|0<br>~~a~~|—<br>~~a~~|0<br>~~OO~~<br>~~a~~|—<br>~~OO~~<br>~~a~~|0<br>~~OO~~<br>~~a~~|—<br>~~a~~|ns<br>~~a~~|
|**Generic DDR Input/Output**<br>~~a~~|||||||||
|**Generic DDRX1 Inputs/Outputs with Clock and Data Centered at Pin (GDDRX1_RX/TX.SCLK.Centered) using PCLK Clock Input –**<br>**Bank 0, Bank 1, Bank 2, Bank 6, and Bank 7 –Figure 3.7and Figure 3.9**<br>~~OO~~|||||||||
|tSU_GDDR1<br>~~OO~~<br>~~es~~|Input Data Setup Before CLK<br>~~OO~~<br>~~es~~|0.917<br>~~OO~~<br>~~es~~|—<br>~~OO~~<br>~~es~~|0.917<br>~~OO~~<br>~~es~~|—<br>~~OO~~<br>~~es~~|0.917<br>~~OO~~<br>~~es~~|—<br>~~OO~~<br>~~es~~|ns<br>~~OO~~<br>~~es~~|
|||0.275<br>~~es~~<br>~~a~~|—<br>~~es~~|0.275<br>~~es~~|—<br>~~es~~|0.275<br>~~es~~|—<br>~~es~~|UI<br>~~es~~|
FPGA-DS-02049-1.8
74
**CrossLink-NX Family Data Sheet**
|**Parameter**<br>~~ee~~<br>~~a~~<br>~~ee~~|**Description**<br>~~ee~~<br><br>~~ee~~|–**9**<br>~~ee~~<br>~~eeee~~<br>|–**9**<br>~~ee~~<br>~~eeee~~<br>|–**8**<br>~~ee~~<br>~~eeee~~<br>|–**8**<br>~~ee~~<br>~~eeee~~<br>|–**7**<br>~~ee~~<br>~~eeee~~<br>|–**7**<br>~~ee~~<br>~~eeee~~<br>|**Unit**<br>~~ee~~<br>~~ee~~<br><br>~~ee~~|
|---|---|---|---|---|---|---|---|---|
|||**Min**<br>~~ee~~<br>~~ee~~<br>|**Max**<br>~~ee~~<br>~~ee~~<br>|**Min**<br>~~ee~~<br>~~ee~~<br><br>~~rs~~|**Max**<br>~~ee~~<br>~~ee~~<br><br>~~ee~~|**Min**<br>~~ee~~<br>~~ee~~<br><br>~~ee~~|**Max**<br>~~ee~~<br>~~ee~~<br><br>~~ee~~||
|tHO_GDDR1<br>~~ee~~<br>~~a ~~<br>~~ee~~|Input Data Hold After CLK<br>~~ee~~<br> ~~ss~~<br>~~ee~~|0.917<br>~~ee~~<br>~~ee ~~<br>~~ss~~|—<br>~~ee~~<br> ~~ee ~~<br>~~ss~~|0.917<br>~~ee~~<br> ~~ee ~~<br>~~ss~~<br>~~rs~~|—<br>~~ee~~<br> ~~ee ~~<br>~~ss~~<br>~~ee~~|0.917<br>~~ee~~<br> ~~ee ~~<br>~~ss~~<br>~~ee~~|—<br>~~ee~~<br> ~~ee~~<br>~~ss~~<br>~~ee~~|ns<br>~~ee~~<br>~~ee~~<br>~~ss~~<br>~~ee~~|
|tDVB_GDDR1<br>~~ee~~|Output Data Valid After CLK Output<br>~~ee~~|1.217|—|1.113<br>~~rs~~|—<br>~~ee~~|1.014<br>~~ee~~|—<br>~~ee~~|ns<br>~~ee~~|
|||–0.45<br>~~a~~|—<br>~~a~~|–<br>0.554<br>~~rs~~<br>~~a~~|—<br>~~ee~~<br>~~a~~|–<br>0.653<br>~~ee~~<br>~~a~~|—<br>~~ee~~<br>~~a~~|ns + 1/2 UI<br>~~ee~~<br>~~a~~|
|tDQVA_GDDR1<br>~~ee~~<br>~~ee~~<br>~~es~~<br>~~es~~|Output Data Valid After CLK Output<br>~~ee~~<br>~~ee~~<br>|1.217<br>~~a~~<br>~~eee~~|—<br>~~a~~<br>~~eee~~|1.113<br>~~rs~~<br>~~a~~<br>~~eee~~|—<br>~~ee~~<br>~~a~~<br>~~eee~~|1.014<br>~~ee~~<br>~~a~~<br>~~eee~~|—<br>~~ee~~<br>~~a~~<br>~~eee~~|ns<br>~~ee~~<br>~~a~~<br>~~eee~~|
|||–0.45<br>~~eee~~<br>~~St~~<br><br>~~ID~~|—<br>~~eee~~<br>~~St~~<br><br>~~nD~~|–<br>0.554<br>~~eee~~<br>~~St~~<br><br>~~nD~~|—<br>~~eee~~<br>~~St~~<br>|–<br>0.653<br>~~eee~~<br>~~St~~<br>|—<br>~~eee~~<br>~~St~~<br>|ns + 1/2 UI<br>~~eee~~<br>~~St~~<br>|
|fDATA_GDDRX1<br>~~es~~<br>~~es~~<br>~~es~~|Input/Output Data Rate<br>~~es~~<br>~~**r**s~~|—<br>~~St~~<br>~~es~~<br>~~ID~~<br>~~UD~~|300<br>~~St~~<br>~~es~~<br>~~nD~~<br>~~r~~~~**r**~~|—<br>~~St~~<br>~~es~~<br>~~nD~~<br>~~**OD**~~|300<br>~~St~~<br>~~es~~<br>~~I~~|—<br>~~St~~<br>~~es~~|300<br>~~St~~<br>~~es~~|Mbps<br>~~St~~<br>~~es~~|
|fMAX_GDDRX1<br>~~es~~<br>~~es~~<br>~~es~~|Frequencyof PCLK<br><br>~~**r**s~~<br>~~r~~|—<br>~~St~~<br><br>~~ID~~<br>~~UD~~<br>~~(RO~~|150<br>~~St~~<br><br>~~nD~~<br>~~r~~~~**r**~~<br>~~t~~|—<br>~~St~~<br><br>~~nD~~<br>~~**OD**~~|150<br>~~St~~<br><br>~~I~~|—<br>~~St~~<br>|150<br>~~St~~<br>|MHz<br>~~St~~<br>|
|½ UI<br>~~es~~<br>~~es~~|Half of Data Bit Time, or 90 degree<br>~~**r**s~~<br>~~r~~|1.667<br>~~ID ~~<br>~~UD~~<br>~~(RO~~<br>~~Rts~~|—<br> ~~nD ~~<br>~~r~~~~**r**~~<br>~~t~~<br>~~rs~~|1.667<br> ~~nD~~<br>~~**OD**~~<br>~~rs~~|—<br>~~I~~<br>~~ts~~|1.667<br>~~ns~~|—<br>~~ns~~|ns|
|Output TX to Input RX Marginper Edge<br>~~**r**s ~~<br>~~es~~<br>~~r ~~<br>~~rs~~||0.3<br> ~~UD ~~<br> ~~(RO~~<br>~~rs~~<br>~~Rts~~|—<br> ~~r~~~~**r** ~~<br>~~t~~<br>~~rs~~<br>~~rs~~|0.197<br> ~~**OD** ~~<br>~~rs~~<br>~~rs~~|—<br> ~~I~~<br>~~rs~~<br>~~ts~~|0.097<br>~~rs~~<br>~~ns~~|—<br>~~rs~~<br>~~ns~~|ns<br>~~rs~~|
|**Generic DDRX1 Inputs/Outputs with Clock and Data Aligned at Pin (GDDRX1_RX/TX.SCLK.Aligned) using PCLK Clock Input –**<br>**Bank 0, Bank 1, Bank 2, Bank 6,and Bank 7 –Figure 3.8andFigure 3.10**<br>~~rs~~<br>~~Rts rs~~<br>~~rs ts~~<br>~~ns~~<br>~~OE~~|||||||||
|tDVA_GDDR1<br>~~OE~~<br>~~rs~~|Input Data Valid After CLK<br>~~OE~~<br>~~rs~~|—<br>~~OE~~<br>~~rs~~<br>~~ee~~|-0.917<br>~~OE~~<br>~~rs~~<br>~~ee~~|—<br>~~OE~~<br>~~rs~~<br>~~ee~~|**–**<br>0.917<br>~~OE~~<br>~~rs~~<br>~~ee~~|—<br>~~OE~~<br>~~rs~~<br>~~ee~~|-0.917<br>~~OE~~<br>~~rs~~<br>~~ee~~|ns + 1/2 UI<br>~~OE~~<br>~~rs~~<br>~~ee~~|
|||—<br>~~rs~~<br>~~ee~~<br>~~a~~|0.75<br>~~rs~~<br>~~ee~~<br>~~ee~~|—<br>~~rs~~<br>~~ee~~<br>~~ee~~|0.75<br>~~rs~~<br>~~ee~~<br>~~ee~~|—<br>~~rs~~<br>~~ee~~<br>~~ee~~|0.75<br>~~rs~~<br>~~ee~~<br>~~ee~~|ns<br>~~rs~~<br>~~ee~~|
|||—<br>~~rs~~<br>~~ee~~<br>~~a~~|0.225<br>~~rs~~<br>~~ee~~<br>~~ee~~|—<br>~~rs~~<br>~~ee ~~<br>~~ee~~|0.225<br>~~rs~~<br> ~~ee ~~<br>~~ee~~|—<br>~~rs~~<br> ~~ee ~~<br>~~ee~~|0.225<br>~~rs~~<br> ~~ee~~<br>~~ee~~|UI<br>~~rs~~<br>~~ee~~|
|tDVE_GDDR1<br>~~i~~<br>~~es~~<br>~~es~~|Input Data Hold After CLK<br>~~i~~<br>~~rs~~|0.917<br>~~a~~<br>~~i~~<br>~~a~~|—<br>~~ee~~<br>~~i~~<br>~~ee~~|0.917<br>~~ee ~~<br>~~i~~<br>~~ee~~|—<br> ~~ee ~~<br>~~i~~<br>~~ee~~|0.917<br> ~~ee ~~<br>~~i~~<br>~~ee~~|—<br> ~~ee~~<br>~~i~~<br>~~ee~~|ns + 1/2 UI<br>~~i~~|
|||2.583<br>~~i~~<br>~~a~~<br>~~a~~|—<br>~~i~~<br>~~ee~~<br>~~ee~~|2.583<br>~~i~~<br>~~ee~~<br>~~ee~~|—<br>~~i~~<br>~~ee~~<br>~~ee~~|2.583<br>~~i~~<br>~~ee~~<br>~~ee~~|—<br>~~i~~<br>~~ee~~<br>~~ee~~|ns<br>~~i~~|
|||0.775<br>~~i~~<br>~~a~~<br>~~a~~<br>~~ttn~~|—<br>~~i~~<br>~~ee~~<br>~~ee~~<br>~~rs~~|0.775<br>~~i~~<br>~~ee ~~<br>~~ee~~<br>~~ts~~|—<br>~~i~~<br> ~~ee ~~<br>~~ee~~<br>~~I~~|0.775<br>~~i~~<br> ~~ee~~<br>~~ee~~|—<br>~~i~~<br>~~ee~~<br>~~ee~~|UI<br>~~i~~|
|tDIA_GDDR1<br>~~es~~<br>~~es~~<br>~~ee~~|Output Data Invalid After CLK Output<br>~~rs~~<br>~~rs~~<br>|—<br>~~a~~<br>~~ttn~~<br>~~tty~~<br>|0.45<br>~~ee~~<br>~~rs~~<br>~~rs~~<br>|—<br>~~ee~~<br>~~ts~~<br>~~rs~~<br>|0.554<br>~~ee~~<br>~~I~~<br>|—<br>~~ee~~<br>|0.653<br>~~ee~~<br>|ns<br>|
|tDIB_GDDR1<br>~~es~~<br>~~es~~<br>~~ee~~<br>~~es~~|Output Data Invalid Before CLK Output<br>~~rs~~<br>~~rs~~<br><br>|—<br>~~a ~~<br>~~ttn~~<br>~~tty~~<br><br>~~ee ee~~<br>|0.45<br> ~~ee ~~<br>~~rs~~<br>~~rs~~<br><br>~~ee~~<br>|—<br> ~~ee ~~<br>~~ts~~<br>~~rs~~<br><br>~~ee~~<br>|0.554<br> ~~ee~~<br>~~I~~<br><br>~~ee~~<br>|—<br>~~ee ~~<br><br>~~ee~~<br>|0.653<br> ~~ee~~<br><br>~~ee~~<br>|ns<br><br>|
|fDATA_GDDRX1<br>~~es~~<br>~~ee~~<br>~~es~~|Input/Output Data Rate<br>~~rs ~~<br>~~rs~~<br>~~ee~~<br>|—<br> ~~ttn ~~<br>~~tty~~<br>~~ee~~<br>~~ee ee~~<br>|300<br> ~~rs ~~<br>~~rs~~<br>~~ee~~<br>~~ee~~<br>|—<br> ~~ts ~~<br>~~rs~~<br>~~ee~~<br>~~ee~~<br>|300<br> ~~I~~<br>~~ee~~<br>~~ee~~<br>|—<br>~~ee~~<br>~~ee~~<br>|300<br>~~ee~~<br>~~ee~~<br>|Mbps<br>~~ee~~<br>|
|fMAX_GDDRX1<br>~~ee~~<br>~~es~~|Frequency for PCLK<br>~~rs ~~<br>~~ee~~<br>|—<br> ~~tty ~~<br>~~ee~~<br>~~ee ee~~<br>|150<br> ~~rs ~~<br>~~ee~~<br>~~ee~~<br>|—<br> ~~rs~~<br>~~ee~~<br>~~ee~~<br>|150<br>~~ee~~<br>~~ee~~<br>|—<br>~~ee~~<br>~~ee~~<br>|150<br>~~ee~~<br>~~ee~~<br>|MHz<br>~~ee~~<br>|
|½ UI<br>~~es~~|Half of Data Bit Time, or 90 degree<br>|1.667<br>~~ee ee~~<br><br>~~Ges~~|—<br>~~ee~~<br><br>~~ee~~|1.667<br>~~ee~~<br><br>~~tees~~|—<br>~~ee~~<br><br>~~ee~~|1.667<br>~~ee~~<br>|—<br>~~ee~~<br>|ns<br>|
|Output TX to Input RX Margin per Edge<br>~~eses~~||0.3<br>~~ee ee~~<br>~~es~~<br>~~Ges~~|—<br>~~ee~~<br>~~es~~<br>~~ee~~|0.197<br>~~ee~~<br>~~es~~<br>~~tees~~|—<br>~~ee~~<br>~~es~~<br>~~ee~~|0.098<br>~~ee~~<br>~~es~~|—<br>~~ee~~<br>~~es~~|ns<br>~~es~~|
|**Generic DDRX1 Inputs/Outputs with Clock and Data Centered at Pin (GDDRX1_RX/TX.SCLK.Centered) using PCLK Clock Input –**<br>**Bank 3, Bank 4, and Bank 5 –Figure 3.7and Figure 3.9**<br>~~es~~<br>~~Ges ee tees ee~~<br>~~OO~~|||||||||
|tSU_GDDR1<br>~~OO~~<br>~~DE~~<br>~~ee~~|Input Data Setup Before CLK<br>~~OO~~<br>~~DE~~<br>~~es~~|0.55<br>~~OO~~<br>~~DE~~<br>~~a~~|—<br>~~OO~~<br>~~DE~~<br>~~e~~~~**e**~~|0.55<br>~~OO~~<br>~~DE~~<br>~~**e**e~~|—<br>~~OO~~<br>~~DE~~<br>~~ee~~|0.648<br>~~OO~~<br>~~DE~~<br>~~ee~~|—<br>~~OO~~<br>~~DE~~<br>~~ee~~|ns<br>~~OO~~<br>~~DE~~<br>~~ee~~|
|||0.275<br>~~DE~~<br>~~a~~<br>~~ee~~|—<br>~~DE~~<br>~~e~~~~**e**~~<br>~~ee~~|0.275<br>~~DE~~<br>~~**e**e~~<br>~~s~~|—<br>~~DE~~<br>~~ee~~<br>~~ee~~|0.275<br>~~DE~~<br>~~ee~~<br>~~ee~~|—<br>~~DE~~<br>~~ee~~<br>~~ee~~|UI<br>~~DE~~<br>~~ee~~|
|tHO_GDDR1<br>~~DE~~<br>~~ee~~<br>~~ee~~|Input Data Hold After CLK<br>~~DE~~<br>~~es~~<br>~~ee~~|0.55<br>~~DE~~<br>~~a~~<br>~~ee~~<br>~~eee~~|—<br>~~DE~~<br>~~e~~~~**e**~~<br>~~ee~~<br>~~eee~~|0.55<br>~~DE~~<br>~~**e**e~~<br>~~s~~<br>~~eee~~|—<br>~~DE~~<br>~~ee~~<br>~~ee~~<br>~~eee~~|0.648<br>~~DE~~<br>~~ee~~<br>~~ee~~<br>~~eee~~|—<br>~~DE~~<br>~~ee~~<br>~~ee~~<br>~~eee~~<br>~~EE~~|ns<br>~~DE~~<br>~~ee~~<br>~~eee~~<br>~~EE=~~|
|tDVB_GDDR1<br>~~ee~~<br>~~ee~~<br>~~ae~~|Output Data Valid After CLK Output<br>~~es ~~<br>~~ee~~|0.7<br>~~a~~<br> ~~ee ~~<br>~~eee~~|—<br>~~e~~~~**e** ~~<br> ~~ee~~<br>~~eee~~|0.631<br> ~~**e**e ~~<br>~~s ~~<br>~~eee~~|—<br> ~~ee ~~<br> ~~ee ~~<br>~~eee~~|0.744<br> ~~ee ~~<br> ~~ee ~~<br>~~eee~~|—<br> ~~ee ~~<br> ~~ee~~<br>~~eee~~<br>~~EE~~|ns<br> ~~ee~~<br>~~eee~~<br>~~EE=~~|
|||–0.300<br>~~eee~~<br>~~SEER~~|—<br>~~eee~~<br>~~SEER~~|–<br>0.369<br>~~eee~~<br>~~SEER~~|—<br>~~eee~~<br>~~SEER~~|–<br>0.435<br>~~eee~~<br>~~SEER~~|—<br>~~eee~~<br>~~SEER~~<br>~~EE~~<br>~~EE~~|ns + 1/2 UI<br>~~eee~~<br>~~SEER~~<br>~~EE=~~<br>~~EE=~~|
|tDQVA_GDDR1<br>~~ee~~<br>~~RR~~<br>~~ae~~<br>~~ee~~|Output Data Valid After CLK Output<br>~~ee ~~<br>~~RR~~<br>~~es~~|0.7<br> ~~eee~~<br>~~SEER~~<br>~~RR~~|—<br>~~eee~~<br>~~SEER~~<br>~~RR~~|0.631<br>~~eee~~<br>~~SEER~~<br>~~RR~~|—<br>~~eee~~<br>~~SEER~~<br>~~RR~~|0.744<br>~~eee~~<br>~~SEER~~<br>~~RR~~|—<br>~~eee~~<br>~~SEER~~<br>~~EE~~<br>~~RR~~<br>~~EE~~|ns<br>~~eee~~<br>~~SEER~~<br>~~EE =~~<br>~~RR~~<br>~~EE=~~|
|||–0.300<br>~~RR~~<br>~~EERE~~<br>~~ee~~|—<br>~~RR~~<br>~~EERE~~<br>~~Gee~~|–<br>0.369<br>~~RR~~<br>~~EERE~~<br>~~ee~~|—<br>~~RR~~<br>~~EERE~~<br>~~ee~~|–<br>0.435<br>~~RR~~<br>~~EERE~~<br>~~ee~~|—<br>~~RR~~<br>~~EERE~~<br>~~EE~~<br>~~ee~~|ns + 1/2 UI<br>~~RR~~<br>~~EERE~~<br>~~EE=~~|
|fDATA_GDDRX1<br>~~RR~~<br>~~ae~~<br>~~ee~~<br>~~ee~~|Input/Output Data Rate<br>~~RR~~<br>~~es~~<br>~~e~~~~**s**~~|—<br>~~RR~~<br>~~EERE~~<br>~~ee~~<br>~~er~~~~**es**~~|500<br>~~RR~~<br>~~EERE~~<br>~~Gee~~<br>~~e~~~~**s**~~|—<br>~~RR~~<br>~~EERE~~<br>~~ee~~<br>~~ed~~|500<br>~~RR~~<br>~~EERE~~<br>~~ee~~<br>~~ee~~|—<br>~~RR~~<br>~~EERE~~<br>~~ee~~|424<br>~~RR~~<br>~~EERE~~<br>~~EE~~<br>~~ee~~|Mbps<br>~~RR~~<br>~~EERE~~<br>~~EE=~~|
|fMAX_GDDRX1<br>~~ae~~<br>~~ee~~<br>~~ee~~|Frequency of PCLK<br>~~es~~<br>~~e~~~~**s**~~<br>~~r~~|—<br>~~ee~~<br>~~er~~~~**es**~~<br>~~te~~|250<br>~~Gee~~<br>~~e~~~~**s**~~<br>~~t~~|—<br>~~ee~~<br>~~ed~~<br>~~te~~|250<br>~~ee~~<br>~~ee~~<br>~~te~~|—<br>~~ee~~<br>~~es~~|212<br>~~EE~~<br>~~ee~~<br>~~ee~~|MHz<br>~~EE =~~|
|½ UI<br>~~ee~~<br>~~ee~~|Half of Data Bit Time, or 90 degree<br>~~es ~~<br>~~e~~~~**s**~~<br>~~r~~|—<br> ~~ee ~~<br>~~er~~~~**es**~~<br>~~te~~<br>~~eres~~|—<br> ~~Gee ~~<br>~~e~~~~**s**~~<br>~~t~~<br>~~ee~~|1<br> ~~ee ~~<br>~~ed~~<br>~~te~~<br>~~ed~~|—<br> ~~ee ~~<br>~~ee~~<br>~~te~~<br>~~ee~~|1.179<br> ~~ee ~~<br>~~es~~<br>~~es~~|—<br> ~~ee~~<br>~~ee~~|ns|
|Output TX to Input RX Margin per Edge<br>~~e~~~~**s** ~~<br>~~ee~~<br>~~r~~<br>~~es~~||0.15<br> ~~er~~~~**es** ~~<br>~~te~~<br>~~es~~<br>~~eres~~|—<br> ~~e~~~~**s** ~~<br>~~t~~<br>~~es~~<br>~~ee~~|0.081<br> ~~ed ~~<br>~~te ~~<br>~~es~~<br>~~ed~~|—<br> ~~ee~~<br> ~~te ~~<br>~~es~~<br>~~ee~~|0.095<br> ~~es ~~<br>~~es~~<br>~~es~~|—<br> ~~ee~~<br>~~es~~|ns<br>~~es~~|
© 2021-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02049-1.8
75
**CrossLink-NX Family Data Sheet**
|**Parameter**<br>~~a~~|**Description**<br>~~a~~|–**9**<br>~~a~~<br>~~ee~~|–**9**<br>~~a~~<br>~~ee~~|–**8**<br>~~a~~<br>~~eeeee~~|–**8**<br>~~a~~<br>~~eeeee~~|–**7**<br>~~a~~<br>~~eee~~|–**7**<br>~~a~~<br>~~eee~~|**Unit**<br>~~a~~|
|---|---|---|---|---|---|---|---|---|
|||**Min**<br>~~a~~<br>~~ee~~|**Max**<br>~~a~~<br>~~ee~~|**Min**<br>~~a~~<br>~~ee~~|**Max**<br>~~a~~<br>~~eee~~|**Min**<br>~~a~~<br>~~eee~~|**Max**<br>~~a~~<br>~~eee~~||
|**Generic DDRX1 Inputs/Outputs with Clock and Data Aligned at Pin (GDDRX1_RX/TX.SCLK.Aligned) using PCLK Clock Input –**<br>**Bank 3, Bank 4, and Bank 5 –Figure 3.8andFigure 3.10**<br>~~ee ee eee~~<br>~~eee~~<br>~~pt~~<br>~~|~~<br>~~||~~|||||||||
|tDVA_GDDR1|Input Data Valid After CLK|—<br>~~pt~~|-0.55<br>~~pt~~<br>~~|~~|—<br>~~|~~|**–**<br>0.550<br>~~|~~|—<br>~~|~~|-0.648|ns + 1/2 UI|
|||—<br>~~pt~~<br>~~|~~<br>~~|~~|0.45<br>~~pt~~<br>~~|~~<br>~~|~~<br>~~|~~|—<br>~~| ~~<br>~~|~~<br>~~fp~~|0.45<br> ~~|~~<br>~~|~~<br>~~fpfp~~|—<br>~~|~~<br>~~|~~<br>~~fp~~|0.53<br>~~fe~~<br>|ns<br>~~fe~~<br>|
|||—<br>~~|~~<br>~~|~~<br>~~|~~|0.225<br>~~|~~<br>~~|~~<br>~~|~~|—<br>~~|~~<br>~~fp~~<br>~~|~~|0.225<br>~~|~~<br>~~fpfp~~<br>~~|p~~|—<br>~~|~~<br>~~fptp~~<br>~~|p~~|0.225<br>~~fe~~<br>~~tp~~<br>~~|p~~|UI<br>~~fe~~<br>~~tp~~<br>|
|tDVE_GDDR1|Input Data Hold After CLK|0.55<br>~~|~~<br>~~|~~<br>~~|~~|—<br>~~|~~<br>~~|~~<br>~~|~~|0.55<br>~~fp~~<br>~~|~~<br>~~fp~~|—<br>~~fp fp~~<br>~~|p~~<br>~~fpft~~|0.648<br>~~fp~~<br>~~|p~~<br>~~ft~~|—<br><br>~~|pfe~~<br>|ns + 1/2 UI<br><br>~~fe~~<br>|
|||1.55<br>~~|~~<br>~~|~~<br>~~|~~|—<br>~~|~~<br>~~|~~<br>~~|~~|1.55<br>~~| ~~<br>~~fp~~<br>~~|~~|—<br> ~~|p~~<br>~~fpft~~<br>~~tt~~|1.827<br>~~|p~~<br>~~fttf~~<br>~~tt~~|—<br>~~|p~~<br>~~tf~~<br>~~tt~~|ns<br><br>~~tf~~<br>|
|||0.775<br>~~|~~<br>~~|~~|—<br>~~|~~<br>~~|~~|0.775<br>~~fp~~<br>~~|~~|—<br>~~fp ft~~<br>~~tt~~|0.775<br>~~fttf~~<br>~~tt~~|—<br>~~tf~~<br>~~ttfp~~|UI<br>~~tf~~<br>~~fp~~|
|tDIA_GDDR1<br>~~OO~~<br>~~a~~|Output Data Invalid After CLK Output<br>~~OO~~<br>|—<br>~~|~~<br>~~OO~~<br>~~ee~~<br>|0.3<br>~~|~~<br>~~OO~~<br>|—<br>~~| ~~<br>~~OO~~<br>|0.369<br> ~~tt~~<br>~~OO~~<br>|—<br>~~tt~~<br>~~OO~~<br>|0.435<br>~~tt~~<br>~~OO~~<br>|ns<br><br>~~OO~~<br>|
|tDIB_GDDR1<br>~~a~~<br>~~a~~|Output Data Invalid Before CLK Output<br>~~ee~~<br>|—<br>~~ee~~<br>~~ee~~<br>|0.3<br>~~ee~~<br>|—<br>~~ee~~<br>|0.369<br>~~ee~~<br>|—<br>~~ee~~<br>|0.435<br>~~ee~~<br>|ns<br>~~ee~~<br>|
|fDATA_GDDRX1<br>~~a~~|Input/Output Data Rate<br>|—<br>~~ee~~<br>|500<br>|—<br>|500<br>|—<br>|424<br>|Mbps<br>|
|fMAX_GDDRX1<br>~~ee~~|Frequency for PCLK<br>~~ee~~|—<br>~~ee~~|250<br>~~ee~~|—<br>~~ee~~|250<br>~~ee~~|—<br>~~ee~~|212<br>~~ee~~|MHz<br>~~ee~~|
|½ UI<br>~~ee~~<br>~~a~~|Half of Data Bit Time, or 90 degree<br>~~ee~~<br>|1<br>~~ee~~<br>|—<br>~~ee~~<br>|1<br>~~ee~~<br>|—<br>~~ee~~<br>|1.179<br>~~ee~~<br>|—<br>~~ee~~<br>|ns<br>~~ee~~<br>|
|Output TX to Input RX Margin per Edge<br>~~Oe~~||0.15<br>~~Oe~~|—<br>~~Oe~~|0.081<br>~~Oe~~|—<br>~~Oe~~|0.095<br>~~Oe~~|—<br>~~Oe~~|ns<br>~~Oe~~|
|**Generic DDRX2 Inputs/Outputs with Clock and Data Centered at Pin (GDDRX2_RX/TX.ECLK.Centered) using PCLK Clock Input -**<br>**Figure 3.7and Figure 3.9**<br>~~ee~~|||||||||
|tSU_GDDRX2<br>~~pe~~<br>~~a~~|Data Setup before CLK Input<br>~~pe~~<br>|0.175<br>~~pe~~<br>~~ee~~<br>|—<br>~~pe~~<br>~~ee~~<br>|0.175<br>~~pe~~<br>~~ee~~<br>|—<br>~~pe~~<br>~~ee~~<br>|0.206<br>~~pe~~<br>|—<br>~~pe~~<br>|ns<br>~~pe~~<br>|
|||0.175<br>~~pe~~<br>~~ee~~<br>|—<br>~~pe~~<br>~~ee~~<br><br>~~GOO~~|0.175<br>~~pe~~<br>~~ee~~<br><br>~~GOO~~|—<br>~~pe~~<br>~~ee~~<br><br>~~GOO~~|0.175<br>~~pe~~<br><br>~~GOO~~|—<br>~~pe~~<br>|UI<br>~~pe~~<br>|
|tHO_GDDRX2<br>~~pe~~<br>~~a ~~|Data Hold after CLK Input<br>~~pe~~<br> ~~GD~~|0.177<br>~~pe~~<br>~~ee ~~<br>~~GD~~|—<br>~~pe~~<br> ~~ee ~~<br>~~GD~~<br>~~GOO~~|0.177<br>~~pe~~<br> ~~ee ~~<br>~~GD~~<br>~~GOO~~|—<br>~~pe~~<br> ~~ee~~<br>~~GD~~<br>~~GOO~~|0.206<br>~~pe~~<br>~~GD~~<br>~~GOO~~|—<br>~~pe~~<br>~~GD~~|ns<br>~~pe~~<br>~~GD~~|
|tDVB_GDDRX2<br>~~FRR~~|Output Data Valid Before CLK Output<br>~~FRR~~|0.380<br>~~FRR~~<br>~~pt~~|—<br>~~GOO~~<br>~~FRR~~<br>~~pt~~<br>~~|~~|0.352<br>~~GOO~~<br>~~FRR~~<br>~~|~~|—<br>~~GOO~~<br>~~FRR~~<br>~~|~~|0.415<br>~~GOO~~<br>~~FRR~~|—<br>~~FRR~~|ns<br>~~FRR~~|
|||-0.120<br>~~FRR~~<br>~~pt~~|—<br>~~FRR~~<br>~~pt~~<br>~~|~~|–<br>0.148<br>~~FRR~~<br>~~|~~|—<br>~~FRR~~<br>~~|~~|–<br>0.174<br>~~FRR~~|—<br>~~FRR~~|ns + 1/2 UI<br>~~FRR~~|
|tDQVA_GDDRX2<br>~~=~~|Output Data Valid After CLK Output<br>~~=~~|0.380<br>~~pt~~<br>~~=~~<br>~~pf~~|—<br>~~pt~~<br>~~|~~<br>~~=~~<br>~~pf~~<br>~~|~~|0.352<br>~~|~~<br>~~=~~|—<br>~~|~~<br>~~=~~<br>~~|~~|0.415<br>~~=~~|—<br>~~=~~|ns<br>~~=~~|
|||-0.120<br>~~=~~<br>~~pf~~|—<br>~~=~~<br>~~pf~~<br>~~|~~|–<br>0.148<br>~~=~~|—<br>~~=~~<br>~~|~~|–<br>0.174<br>~~=~~|—<br>~~=~~|ns + 1/2 UI<br>~~=~~|
|fDATA_GDDRX2<br>~~GD~~<br>~~a~~|Input/Output Data Rate<br>~~GD~~<br>|—<br>~~pf~~<br>~~GD~~<br>|1000<br>~~pf~~<br>~~|~~<br>~~GD~~<br>|—<br>~~GD~~<br>~~GO~~<br>|1000<br>~~|~~<br>~~GD~~<br>|—<br>~~GD~~<br>|848<br>~~GD~~<br>|Mbps<br>~~GD~~<br>|
|fMAX_GDDRX2<br>~~GD~~<br>~~a~~<br>~~a~~|Frequencyfor ECLK<br>~~GD~~<br>~~GO~~<br>|—<br>~~GD~~<br>~~GO~~<br>|500<br>~~GD~~<br>~~GO~~<br><br>~~GO~~|—<br>~~GD~~<br>~~GO~~<br>~~GO~~<br><br>~~OO~~|500<br>~~GD~~<br>~~GO~~<br><br>~~OO~~|—<br>~~GD~~<br>~~GO~~<br><br>~~OO~~|424<br>~~GD~~<br>~~GO~~<br>|MHz<br>~~GD~~<br>~~GO~~<br>|
|½ UI<br>~~a ~~<br>~~a ~~|Half of Data Bit Time, or 90 degree<br> ~~GO~~<br> ~~GD~~|0.500<br>~~GO~~<br>~~GD~~|—<br>~~GO~~<br>~~GD~~<br>~~GO~~<br>~~OOO~~|0.500<br>~~GO~~<br>~~GO~~<br>~~GD~~<br>~~OO~~<br>~~OOO~~|—<br>~~GO~~<br>~~GD~~<br>~~OO~~<br>~~OOO~~|0.589<br>~~GO~~<br>~~GD~~<br>~~OO~~<br>~~OOO~~|—<br>~~GO~~<br>~~GD~~|ns<br>~~GO~~<br>~~GD~~|
|fPCLK<br>~~GD~~|PCLK frequency<br>~~GD~~|—<br>~~GD~~|250.0<br>~~GO ~~<br>~~GD~~<br>~~OOO~~<br>~~DO~~|—<br> ~~OO~~<br>~~GD~~<br>~~OOO~~<br>~~DO~~|250.0<br>~~OO~~<br>~~GD~~<br>~~OOO~~<br>~~DO~~|—<br>~~OO~~<br>~~GD~~<br>~~OOO~~<br>~~DO~~|212.1<br>~~GD~~|MHz<br>~~GD~~|
|Output TX to Input RX Marginper Edge<br>~~RD~~||0.230<br>~~RD~~|—<br>~~OOO~~<br>~~RD~~<br>~~DO~~|0.202<br>~~OOO~~<br>~~RD~~<br>~~DO~~|—<br>~~OOO~~<br>~~RD~~<br>~~DO~~|0.239<br>~~OOO~~<br>~~RD~~<br>~~DO~~|—<br>~~RD~~|ns<br>~~RD~~|
|**Generic DDRX2 Inputs/Outputs with Clock and Data Aligned at Pin (GDDRX2_RX/TX.ECLK.Aligned) using PCLK Clock Input -**<br>**Figure 3.8andFigure 3.10**<br>~~DO~~<br>~~____~~|||||||||
|tDVA_GDDRX2<br>~~[~~<br>~~i~~|Input Data Valid After CLK<br>~~[~~<br>~~i~~|—<br>~~[~~|–<br>0.275<br>~~[~~|—<br>~~[~~|-<br>0.275<br>~~[~~|—<br>~~[~~|–<br>0.324<br>~~[~~|ns + 1/2 UI<br>~~[~~|
|||—<br>~~[~~<br>~~ee~~<br>~~ee~~|0.225<br>~~[~~<br>~~ee~~<br>~~ee~~|—<br>~~[~~<br>~~ee~~<br>~~ee~~|0.225<br>~~[~~<br>~~ee~~<br>~~ee~~|—<br>~~[~~<br>~~ee~~<br>~~ee~~|0.265<br>~~[~~<br>~~ee~~<br>~~ee~~|ns<br>~~[~~<br>~~ee~~<br>~~ee~~|
|||—<br>~~[~~<br>~~ee~~<br>~~ee~~|0.225<br>~~[~~<br>~~ee~~<br>~~ee~~|—<br>~~[~~<br>~~ee~~<br>~~ee~~|0.225<br>~~[~~<br>~~ee~~<br>~~ee~~|—<br>~~[~~<br>~~ee~~<br>~~ee~~|0.225<br>~~[~~<br>~~ee~~<br>~~ee~~|UI<br>~~[~~<br>~~ee~~<br>~~ee~~|
|tDVE_GDDRX2<br>~~[~~<br>~~i~~|Input Data Hold After CLK<br>~~[~~<br>~~i~~|0.275<br>~~[~~<br>~~ee~~<br>~~==—==—~~<br>~~a~~|—<br>~~[~~<br>~~ee~~<br>~~==—==—~~<br>~~ee~~|0.275<br>~~[~~<br>~~ee~~<br>~~==—==—~~|—<br>~~[~~<br>~~ee~~<br>~~==—==—~~|0.324<br>~~[~~<br>~~ee~~<br>~~==—==—~~|—<br>~~[~~<br>~~ee~~<br>~~==—==—~~|ns + 1/2 UI<br>~~[~~<br>~~ee~~|
|||0.775<br>~~ee~~<br>~~a~~<br>~~a~~|—<br>~~ee~~<br>~~ee~~<br>~~ee~~|0.775<br>~~ee~~|—<br>~~ee~~|0.914<br>~~ee~~|—<br>~~ee~~|ns<br>~~ee~~|
|||0.775<br>~~ee ~~<br>~~a~~<br>~~a~~|—<br> ~~ee~~<br>~~ee~~<br>~~ee~~<br>~~OOD~~|0.775<br>~~ee ~~<br>~~OU~~|—<br> ~~ee~~<br>~~OU~~|0.775<br>~~ee ~~<br>~~OU~~|—<br> ~~ee ~~|UI<br> ~~ee~~|
|tDIA_GDDRX2<br>~~GD~~|Output Data Invalid After CLK Output<br>~~GD~~|—<br>~~a~~<br>~~GD~~|0.120<br>~~ee~~<br>~~GD~~<br>~~OOD~~<br>~~DO~~|—<br>~~GD~~<br>~~OU~~<br>~~GO~~|0.148<br>~~GD~~<br>~~OU~~<br>~~GO~~|—<br>~~GD~~<br>~~OU~~<br>~~GO~~|0.174<br>~~GD~~|ns<br>~~GD~~|
|tDIB_GDDRX2<br>~~GD~~<br>~~DD~~|Output Data Invalid Before CLK Output<br>~~GD~~<br>~~DD~~|—<br>~~GD~~<br>~~DD~~|0.120<br>~~GD~~<br>~~OOD~~<br>~~DD~~<br>~~DO~~|—<br>~~GD~~<br>~~OU~~<br>~~DD~~<br>~~GO~~|0.148<br>~~GD~~<br>~~OU~~<br>~~DD~~<br>~~GO~~|—<br>~~GD~~<br>~~OU~~<br>~~DD~~<br>~~GO~~|0.174<br>~~GD~~<br>~~DD~~|ns<br>~~GD~~<br>~~DD~~|
© 2021-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02049-1.8
76
**CrossLink-NX Family Data Sheet**
|**Parameter**<br>~~a~~|**Description**<br>~~a~~|–**9**<br>~~a~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|–**9**<br>~~a~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|–**8**<br>~~a~~<br>~~eeee~~|–**8**<br>~~a~~<br>~~eeee~~|–**7**<br>~~a~~<br>~~eee~~|–**7**<br>~~a~~<br>~~eee~~|**Unit**<br>~~a~~|
|---|---|---|---|---|---|---|---|---|
|||**Min**<br>~~a~~<br>~~ee~~<br>~~ee~~|**Max**<br>~~a~~<br>~~ee~~<br>~~ee~~|**Min**<br>~~a~~<br>~~ee~~<br>~~GO~~|**Max**<br>~~a~~<br>~~ee~~<br>~~GO~~|**Min**<br>~~a~~<br>~~eee~~<br>~~GO~~|**Max**<br>~~a~~<br>~~eee~~||
|fDATA_GDDRX2<br>~~eG~~|Input/Output Data Rate<br>~~eG~~|—<br>~~ee~~<br>~~ee~~<br>~~eG~~<br>~~QO~~|1000<br>~~ee~~<br>~~ee~~<br>~~eG~~<br>~~QO~~|—<br>~~ee ~~<br>~~eG~~<br>~~GO~~|1000<br> ~~ee~~<br>~~eG~~<br>~~GO~~|—<br>~~eee~~<br>~~eG~~<br>~~GO~~|848<br>~~eee~~<br>~~eG~~|Mbps<br>~~eG~~|
|fMAX_GDDRX2<br>~~ee~~|Frequencyfor ECLK<br>~~ee~~|—<br>~~ee~~<br>~~QO~~|500<br>~~ee~~<br>~~QO~~|—<br>~~GO~~<br>~~ee~~<br>~~OO~~|500<br>~~GO~~<br>~~ee~~<br>~~OO~~|—<br>~~GO~~<br>~~ee~~<br>~~OO~~|424<br>~~ee~~<br>~~OO~~|MHz<br>~~ee~~|
|½ UI<br>~~ee~~<br>~~GO~~|Half of Data Bit Time, or 90 degree<br>~~ee~~<br>~~GO~~|0.500<br>~~ee~~<br>~~QO~~<br>~~GO~~|—<br>~~ee~~<br>~~QO~~<br>~~GO~~|0.500<br>~~ee~~<br>~~GO~~<br>~~OO~~<br>~~OO~~|—<br>~~ee~~<br>~~GO~~<br>~~OO~~<br>~~OO~~|0.589<br>~~ee~~<br>~~GO~~<br>~~OO~~<br>~~OO~~|—<br>~~ee~~<br>~~GO~~<br>~~OO~~|ns<br>~~ee~~<br>~~GO~~|
|fPCLK<br>~~eG~~|PCLK frequency<br>~~eG~~|—<br>~~eG~~|250.0<br>~~eG~~|—<br>~~OO~~<br>~~eG~~<br>~~OO~~<br>~~DG~~|250.0<br>~~OO~~<br>~~eG~~<br>~~OO~~<br>~~DG~~|—<br>~~OO~~<br>~~eG~~<br>~~OO~~<br>~~DG~~|212.1<br>~~OO~~<br>~~eG~~|MHz<br>~~eG~~|
|Output TX to Input RX Marginper Edge<br>~~GO~~||0.105<br>~~GO~~|—<br>~~GO~~|0.077<br>~~OO~~<br>~~GO~~<br>~~DG~~|—<br>~~OO~~<br>~~GO~~<br>~~DG~~|0.091<br>~~OO~~<br>~~GO~~<br>~~DG~~|—<br>~~GO~~|ns<br>~~GO~~|
|**Generic DDRX4 Inputs/Outputs with Clock and Data Centered at Pin (GDDRX4_RX/TX.ECLK.Centered) using PCLK Clock Input -**<br>**Figure 3.7andFigure 3.9**<br>~~DG~~<br>~~aa~~<br>~~ee~~<br>~~ee~~|||||||||
|tSU_GDDRX4<br>~~a~~|Input Data Set-Up Before CLK<br>~~a~~|0.168<br>~~ee~~|—<br>~~ee~~|0.210<br>~~ee~~|—<br>~~ee~~|0.244|—|ns<br>~~ee~~|
|||0.252<br>~~ee~~<br>~~a~~<br>~~a~~|—<br>~~ee~~|0.252<br>~~ee~~<br>~~OO~~|—<br>~~ee~~<br>~~OO~~|0.252<br>~~OO~~|—|UI<br>~~ee~~|
|tHO_GDDRX4<br>~~a ~~<br>~~eG~~|Input Data Hold After CLK<br> ~~a~~<br>~~eG~~|0.174<br>~~ee~~<br>~~a~~<br>~~eG~~<br>~~a~~|—<br>~~ee~~<br>~~eG~~|0.210<br>~~ee~~<br>~~eG~~<br>~~OO~~|—<br>~~ee~~<br>~~eG~~<br>~~OO~~|0.244<br>~~eG~~<br>~~OO~~|—<br>~~eG~~|ns<br>~~ee~~<br>~~eG~~|
|tDVB_GDDRX4|Output Data Valid Before CLK Output|0.213<br>~~a|~~|—<br>||0.269<br>~~OO~~<br>||—<br>~~OO~~<br>~~tt~~|0.309<br>~~OO~~<br>~~tt~~|—<br>~~tt~~||
|||-0.120<br>~~|~~|—<br>||–<br>0.148<br>||—<br>~~tt~~|–<br>0.174<br>~~tt~~|—<br>~~tt|~~|~~|~~|
|tDQVA_GDDRX4|Input/Output Data Rate|0.213<br>~~|~~<br>~~a~~|—<br>|<br>||0.269<br>| <br>~~|~~|—<br> ~~tt~~<br>~~tt~~|0.309<br>~~tt~~<br>~~tt~~|—<br>~~tt~~<br>~~tt~~||
|||-0.120<br>~~|~~|—<br>||–<br>0.148<br>~~|~~<br>~~OG~~|—<br>~~tt~~<br>~~OG~~|–<br>0.174<br>~~tt~~<br>~~OG~~|—<br>~~tt~~||
|fDATA_GDDRX4<br>~~eG~~|Frequencyfor ECLK<br>~~eG~~|—<br>~~eG~~|1500<br>|<br>~~eG~~|—<br>~~| ~~<br>~~eG~~<br>~~OG~~<br>~~OO~~|1200<br> ~~tt~~<br>~~eG~~<br>~~OG~~<br>~~OO~~|—<br>~~tt~~<br>~~eG~~<br>~~OG~~<br>~~OO~~|1034<br>~~tt~~<br>~~eG~~|Mbps<br>~~eG~~|
|fMAX_GDDRX4<br>~~eG~~|PCLK frequency<br>~~eG~~|—<br>~~eG~~|750.0<br>~~eG~~|—<br>~~OG~~<br>~~eG~~<br>~~OO~~<br>~~OO~~|600<br>~~OG~~<br>~~eG~~<br>~~OO~~<br>~~OO~~|—<br>~~OG~~<br>~~eG~~<br>~~OO~~<br>~~OO~~|517<br>~~eG~~|MHz<br>~~eG~~|
|½ UI<br>~~GO~~|Half of Data Bit Time, or 90 degree<br>~~GO~~|0.333<br>~~GO~~<br>~~GO~~|—<br>~~GO~~<br>~~GO~~|0.417<br>~~OO~~<br>~~GO~~<br>~~OO~~<br>~~OO~~|—<br>~~OO~~<br>~~GO~~<br>~~OO~~<br>~~OO~~|0.483<br>~~OO~~<br>~~GO~~<br>~~OO~~<br>~~OO~~|—<br>~~GO~~|ns<br>~~GO~~|
|fPCLK<br>~~GO~~<br>~~en~~|Input Data Set-UpBefore CLK<br>~~GO~~<br>~~en~~|—<br>~~GO~~<br>~~en~~<br>~~GO~~|187.5<br>~~GO~~<br>~~en~~<br>~~GO~~|—<br>~~GO~~<br>~~OO~~<br>~~en~~<br>~~OO~~|150.0<br>~~GO~~<br>~~OO~~<br>~~en~~<br>~~OO~~|—<br>~~GO~~<br>~~OO~~<br>~~en~~<br>~~OO~~|129.3<br>~~GO~~<br>~~en~~|MHz<br>~~GO~~<br>~~en~~|
|Output TX to Input RX Marginper Edge<br>~~DD~~||0.080<br>~~GO~~<br>~~DD~~|—<br>~~GO~~<br>~~DD~~|0.102<br>~~OO~~<br>~~DD~~|—<br>~~OO~~<br>~~DD~~|0.116<br>~~OO~~<br>~~DD~~|—<br>~~DD~~|ns<br>~~DD~~|
|**Generic DDRX4 Inputs/Outputs with Clock and Data Aligned at Pin (GDDRX4_RX/TX.ECLK.Aligned) using PCLK Clock Input, Left**<br>**and Right sides Only -Figure 3.8and Figure 3.10**<br>~~|~~<br>|<br>~~|tt~~|||||||||
|tDVA_GDDRX4|Input Data Valid After CLK|—<br>~~|~~|–<br>0.183<br>||—<br>~~|~~|–<br>0.229<br>~~tt~~|—<br>~~tt~~|–<br>0.266<br>~~tt|~~|ns + 1/2 UI<br>~~|~~|
|||—<br>~~|~~<br>~~ee~~|0.150<br>|<br>~~ee~~|—<br>~~| ~~<br>~~ee~~|0.188<br> ~~tt~~<br>~~ee~~|—<br>~~tt~~<br>~~ee~~|0.218<br>~~tt~~<br>~~ee~~|ns<br><br>~~ee~~|
|||—<br>~~a~~|0.225<br>~~ee~~|—<br>~~ee~~|0.225<br>~~ee~~|—<br>~~ee~~|0.225<br>~~ee~~|UI<br>~~ee~~|
|tDVE_GDDRX4|Input Data Hold After CLK|0.183<br>~~a ~~<br>~~a~~|—<br> ~~ee~~|0.229<br>~~ee~~|—<br>~~ee~~|0.266<br>~~ee~~|—<br>~~ee~~|ns + 1/2 UI<br>~~ee~~|
|||0.517<br>~~a~~<br>~~a~~|—|0.646|—|0.749|—|ns|
|||0.775|—|0.775|—|0.775|—|UI|
|tDIA_GDDRX4<br>~~a~~|Output Data Invalid After CLK Output|—|0.120|—|0.148|—|0.17|ns|
|tDIB_GDDRX4<br>~~a~~|Output Data Invalid Before CLK Output|—|0.120|—|0.148|—|0.174|ns|
|fDATA_GDDRX4<br>~~a GOO~~|Input/Output Data Rate<br>~~GOO~~|—<br>~~GOO~~|1500<br>~~GOO~~|—<br>~~GOO~~|1200<br>~~GOO~~|—<br>~~GOO~~|1034<br>~~GOO~~|Mbps<br>~~GOO~~|
|fMAX_GDDRX4<br>~~a GOO~~|Frequencyfor ECLK<br>~~GOO~~|—<br>~~GOO~~|750<br>~~GOO~~|—<br>~~GOO~~|600<br>~~GOO~~|—<br>~~GOO~~|517<br>~~GOO~~|MHz<br>~~GOO~~|
|½ UI<br>~~ee~~|Half of Data Bit Time, or 90 degree<br>~~ee~~|0.333<br>~~ee~~|—<br>|0.417<br>~~ee~~|—<br>~~ee~~<br>~~OG~~|0.483<br>~~ee~~<br>~~OG~~|—<br>~~ee~~<br>~~OG~~|ns<br>~~ee~~|
|fPCLK<br>~~ee~~<br>~~GO~~|PCLK frequency<br>~~ee~~<br>~~GO~~|—<br>~~ee ~~<br>~~GO~~|187.5<br> <br>~~GO~~|—<br> ~~ee~~<br>~~GO~~<br>~~DO~~|150.0<br>~~ee~~<br>~~GO~~<br>~~OG~~<br>~~DO~~|—<br>~~ee~~<br>~~GO~~<br>~~OG~~<br>~~DO~~|129.3<br>~~ee~~<br>~~GO~~<br>~~OG~~|MHz<br>~~ee~~<br>~~GO~~|
|Output TX to Input RX Marginper Edge<br>~~GO~~||0.030<br>~~GO~~|—<br>~~GO~~|0.040<br>~~GO~~<br>~~DO~~|—<br>~~OG~~<br>~~GO~~<br>~~DO~~|0.044<br>~~OG~~<br>~~GO~~<br>~~DO~~|—<br>~~OG~~<br>~~GO~~|ns<br>~~GO~~|
|**Generic DDRX5 Inputs/Outputs with Clock and Data Centered at Pin (GDDRX5_RX/TX.ECLK.Centered) using PCLK Clock Input -**<br>**Figure 3.7and Figure 3.9**<br>~~DO~~<br>~~aeeeee~~|||||||||
|tSU_GDDRX5<br>~~a~~|Input Data Set-Up Before CLK<br>~~ee~~|0.179<br>~~eee~~|—<br>~~eee~~|0.187<br>~~eee~~|—<br>~~eee~~|0.224<br>~~eee~~|—<br>~~eee~~|ns<br>~~eee~~|
|||0.224<br>~~eee~~<br>~~a~~<br>~~GO~~|—<br>~~eee~~<br>~~GO~~|0.224<br>~~eee~~<br>~~OO~~|—<br>~~eee~~<br>~~OO~~|0.224<br>~~eee~~<br>~~OO~~|—<br>~~eee~~|UI<br>~~eee~~|
|tHO_GDDRX5<br>~~a ~~<br>~~ee~~|Input Data Hold After CLK<br> ~~ee ~~<br>~~ee~~|0.181<br> ~~eee~~<br>~~ee~~<br>~~GO~~<br>~~GG~~|—<br>~~eee~~<br>~~ee~~<br>~~GO~~<br>~~GG~~|0.187<br>~~eee~~<br>~~ee~~<br>~~OO~~<br>~~GG~~|—<br>~~eee~~<br>~~ee~~<br>~~OO~~<br>~~GG~~|0.224<br>~~eee~~<br>~~ee~~<br>~~OO~~|—<br>~~eee~~<br>~~ee~~|ns<br>~~eee~~<br>~~ee~~|
|tWINDOW_GDDRX5C<br>~~ee~~|Input Data Valid Window<br>~~ee~~|0.36<br>~~GO~~<br>~~ee~~<br>~~GG~~|—<br>~~GO~~<br>~~ee~~<br>~~GG~~|0.374<br>~~OO~~<br>~~ee~~<br>~~GG~~|—<br>~~OO~~<br>~~ee~~<br>~~GG~~|0.448<br>~~OO~~<br>~~ee~~|—<br>~~ee~~|ns<br>~~ee~~|
© 2021-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02049-1.8
77
**CrossLink-NX Family Data Sheet**
|**Parameter**<br>~~ee~~<br>~~ee~~<br>~~ee~~|**Description**<br>~~ee~~<br>~~ee~~<br>~~ee~~|**Description**<br>~~ee~~<br>~~ee~~<br>~~ee~~|–**9**<br>~~ee~~<br>~~aee~~|–**9**<br>~~ee~~<br>~~aee~~|–**8**<br>~~ee~~<br>~~eeee~~|–**8**<br>~~ee~~<br>~~eeee~~|–**7**<br>~~eee~~<br>~~eeee~~|–**7**<br>~~eee~~<br>~~eeee~~|**Unit**<br>~~eee~~<br>~~ee~~|
|---|---|---|---|---|---|---|---|---|---|
||||**Min**<br>~~ee~~<br>~~a~~|**Max**<br>~~ee~~<br>~~ee~~|**Min**<br>~~ee~~<br>~~ee~~|**Max**<br>~~ee~~<br>~~ee~~<br>~~ee~~|**Min**<br><br>~~ee~~<br>~~ee~~|**Max**<br>~~eee~~<br>~~ee~~<br>~~ee~~||
|tDVB_GDDRX5<br>~~ee ~~<br>~~ee~~<br>~~ee~~<br>~~es~~|Output Data Valid Before CLK Output<br> ~~ee~~<br>~~ee~~<br>~~ee~~<br>||0.280<br>~~ee~~<br>~~a~~|—<br>~~ee ~~<br>~~ee~~|0.269<br> ~~ee~~<br>~~ee~~|—<br>~~ee ~~<br>~~ee~~<br>~~ee~~|0.326<br> <br>~~ee~~<br>~~ee~~|—<br> ~~eee~~<br>~~ee~~<br>~~ee~~|ns<br>~~eee~~<br>~~ee~~|
||||–0.120<br>~~a~~<br>|—<br>~~ee~~<br>|–<br>0.148<br>~~ee~~<br>|—<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>|–<br>0.174<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>|—<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>|ns+1/2UI<br>~~ee~~<br>~~ee~~<br>|
|tDQVA_GDDRX5<br>~~ee~~<br>~~ee~~<br>~~es~~|Output Data Valid After CLK Output<br>~~ee~~<br>~~ee~~<br>||0.280<br>~~a ~~<br>|—<br> ~~ee ~~<br>|0.269<br> ~~ee ~~<br>|—<br> ~~ee~~<br>~~ee~~<br>~~ee~~<br>|0.326<br>~~ee ~~<br>~~ee~~<br>~~ee~~<br>|—<br> ~~ee~~<br>~~ee~~<br>~~ee~~<br>|ns<br>~~ee~~<br>~~ee~~<br>|
||||–0.120<br>|—<br>|–<br>0.148<br>|—<br>~~ee~~<br>~~ee~~<br>|–<br>0.174<br>~~ee~~<br>~~ee~~<br>|—<br>~~ee~~<br>~~ee~~<br>|ns+1/2UI<br>~~ee~~<br>~~ee~~<br>|
|fDATA_GDDRX5<br>~~ee~~<br>~~es~~<br>~~es~~<br>~~es~~|Input/Output Data Rate<br>~~ee~~<br>~~(sD~~<br>~~rs~~||—<br>~~(sD~~<br>~~Gs~~|1250<br>~~(sD~~<br>~~Gs~~|—<br>~~(sD~~<br>~~GD~~|1200<br>~~ee~~<br>~~ee~~<br>~~(sD~~|—<br>~~ee~~<br>~~ee~~<br>~~(sD~~|1000<br>~~ee~~<br>~~ee~~<br>~~(sD~~|Mbps<br>~~ee~~<br>~~ee~~<br>~~(sD~~|
|fMAX_GDDRX5<br>~~es~~<br>~~es~~<br>~~es~~<br>~~es~~|Frequencyfor ECLK<br>~~(sD~~<br>~~rs~~<br>~~re~~<br>||—<br>~~(sD~~<br>~~Gs~~<br>~~It~~<br>|625<br>~~(sD~~<br>~~Gs~~<br>~~rs~~<br>|—<br>~~(sD~~<br>~~GD~~<br>~~**rs**~~<br>|600<br>~~ee~~<br>~~(sD~~<br>~~G~~<br>|—<br>~~ee~~<br>~~(sD~~<br>~~G~~~~**s**~~<br>|500<br>~~ee~~<br>~~(sD~~<br>~~I~~<br>|MHz<br>~~ee~~<br>~~(sD~~<br>|
|½ UI<br><br>~~es~~<br>~~es~~<br>~~es~~|Half of Data Bit Time, or 90 degree<br>~~(sD~~<br>~~rs~~<br>~~re~~<br>||0.400<br>~~(sD~~<br>~~Gs~~<br>~~It~~<br><br>~~(ttre~~|—<br>~~(sD~~<br>~~Gs~~<br>~~rs~~<br><br>~~(ttre~~|0.417<br>~~(sD~~<br>~~GD~~<br>~~**rs**~~<br>|—<br>~~(sD~~<br>~~G~~<br><br>~~I~~|0.500<br>~~(sD~~<br>~~G~~~~**s**~~<br><br>~~I~~|—<br>~~(sD~~<br>~~I~~<br><br>~~I~~|ns<br>~~(sD~~<br>|
|fPCLK<br>~~es~~<br>~~es~~|PCLK frequency<br>~~rs~~<br>~~re~~<br>~~rns~~||—<br>~~Gs~~<br>~~It~~<br>~~rns~~<br>~~(ttre~~<br>~~ss~~|125.0<br>~~Gs~~<br>~~rs~~<br>~~rns~~<br>~~(ttre~~<br>~~ss~~|—<br>~~GD~~<br>~~**rs**~~<br>~~rns~~<br>~~Gs~~|120.0<br>~~G~~<br>~~rns~~<br>~~I~~|—<br>~~G~~~~**s**~~<br>~~rns~~<br>~~I~~|100.0<br>~~I~~<br>~~rns~~<br>~~I~~|MHz<br>~~rns~~|
|Output TX to Input RX Marginper Edge<br>~~re ~~<br>~~es~~<br>~~ns~~|||0.120<br> ~~It ~~<br><br>~~(ttre~~<br>~~ns~~<br>~~ss~~|—<br> ~~rs ~~<br><br>~~(ttre~~<br>~~ns~~<br>~~ss~~|0.102<br> ~~**rs**~~<br><br>~~ns~~<br>~~Gs~~|—<br>~~G~~<br><br>~~I~~<br>~~ns~~|0.126<br>~~G~~~~**s** ~~<br><br>~~I~~<br>~~ns~~|—<br> ~~I~~<br><br>~~I~~<br>~~ns~~|ns<br><br>~~ns~~|
|**Generic DDRX5 Inputs/Outputs with Clock and Data Aligned at Pin (GDDRX5_RX/TX.ECLK.Aligned) using PCLK Clock Input -**<br>**Figure 3.8andFigure 3.10**<br>~~ns~~<br>~~ssGs~~||||||||||
|tDVA_GDDRX5|Input Data Valid After CLK||—|–<br>0.220|—|–<br>0.229|—|–<br>0.275|ns + 1/2 UI|
||||—<br>~~a~~|0.180<br>~~ee~~|—<br>~~ee~~|0.188<br>~~ee~~|—<br>~~ee~~|0.225<br>~~ee~~|ns<br>~~ee~~|
||||—<br>~~a~~<br>~~a~~|0.225<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~|0.225<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~|0.225<br>~~ee~~|UI<br>~~ee~~|
|tDVE_GDDRX5<br>~~ee~~<br>~~es~~|Input Data Hold After CLK<br><br>||0.220<br>~~a~~<br>~~a~~<br>~~a~~|—<br>~~ee ~~<br>~~ee~~<br>~~ee~~|0.229<br> ~~ee ~~<br>~~ee~~<br>~~ee~~|—<br> ~~ee~~<br>~~ee~~<br>~~ee~~|0.275<br>~~ee~~<br>~~ee~~<br>~~es~~|—<br>~~ee~~<br>~~es~~|ns + 1/2 UI<br>~~ee~~|
||||0.620<br>~~a~~<br>~~a~~<br>~~a~~<br>|—<br>~~ee ~~<br>~~ee~~<br>~~ee~~<br>|0.646<br> ~~ee ~~<br>~~ee~~<br>|—<br> ~~ee ~~<br>~~ee~~<br>~~ee~~<br>|0.775<br> ~~ee~~<br>~~es~~<br>~~ee~~<br>|—<br>~~es~~<br>~~ee~~<br>|ns<br>~~ee~~<br>|
||||0.775<br>~~a~~<br>~~a~~<br><br>|—<br>~~ee~~<br>~~ee~~<br><br>|0.775<br>~~ee ~~<br><br>~~GD~~<br>|—<br> ~~ee ~~<br>~~ee~~<br><br>|0.775<br> ~~es~~<br>~~ee~~<br><br>|—<br>~~es~~<br>~~ee~~<br><br>|UI<br>~~ee~~<br><br>|
|tWINDOW_GDDRX5A<br>~~ee~~<br>~~es~~<br>~~es~~|Input Data Valid Window<br>~~rs~~<br>||0.440<br>~~a~~<br>~~rs~~<br><br>~~(Os~~|—<br>~~ee~~<br>~~rs~~<br><br>~~(Os~~|0.458<br>~~rs~~<br>~~GD~~<br><br>~~ID~~|—<br>~~ee~~<br>~~rs~~<br>|0.550<br>~~ee~~<br>~~rs~~<br>|—<br>~~ee~~<br>~~rs~~<br>|ns<br>~~ee~~<br>~~rs~~<br>|
|tDIA_GDDRX5<br>~~ee~~<br>~~es~~<br>~~es~~<br>~~es~~|Output Data Invalid After CLK Output<br>~~rs~~<br>~~es~~<br>~~rs~~||—<br>~~a~~<br>~~rs~~<br>~~es~~<br>~~(Os~~<br>~~ts~~|0.120<br>~~ee~~<br>~~rs~~<br>~~es~~<br>~~(Os~~<br>~~ts~~|—<br>~~rs~~<br>~~GD~~<br>~~es~~<br>~~ID~~<br>~~rs~~|0.148<br>~~ee~~<br>~~rs~~<br>~~es~~|—<br>~~ee ~~<br>~~rs~~<br>~~es~~|0.174<br> ~~ee~~<br>~~rs~~<br>~~es~~|ns<br>~~ee~~<br>~~rs~~<br>~~es~~|
|tDIB_GDDRX5<br>~~es~~<br>~~es~~<br>~~es~~<br>~~es~~|Output Data Invalid Before CLK Output<br><br>~~rs~~<br>~~rns~~<br>||—<br><br>~~(Os~~<br>~~ts~~<br>~~I~~<br>|0.120<br><br>~~(Os~~<br>~~ts~~<br>~~sD~~<br>|—<br>~~GD~~<br><br>~~ID~~<br>~~rs~~<br>~~sD~~<br>|0.148<br><br>~~I~~<br>|—<br><br>|0.174<br><br>|ns<br><br>|
|fDATA_GDDRX5<br>~~es~~<br>~~es~~<br>~~es~~<br>~~es~~|Input/Output Data Rate<br>~~rs~~<br>~~rns~~<br>||—<br>~~(Os~~<br>~~ts~~<br>~~I~~<br><br>~~(RD~~|1250<br>~~(Os ~~<br>~~ts~~<br>~~sD~~<br><br>~~OD~~|—<br> ~~ID~~<br>~~rs~~<br>~~sD~~<br><br>~~OD~~|1200<br>~~I~~<br><br>~~I~~|—<br>|1000<br>|Mbps<br>|
|fMAX_GDDRX5<br>~~es~~<br>~~es~~<br>~~es~~<br>~~a~~|Frequencyfor ECLK<br>~~rs ~~<br>~~rns~~<br>~~es~~<br>~~r~~~~**s**~~||—<br> ~~ts~~<br>~~I~~<br>~~es~~<br>~~(RD~~<br>~~sD~~|625<br>~~ts ~~<br>~~sD~~<br>~~es~~<br>~~OD~~<br>~~sD~~|—<br> ~~rs~~<br>~~sD~~<br>~~es~~<br>~~OD~~<br>~~sD I~~|600<br>~~I~~<br>~~es~~<br>~~I~~<br>~~I~~|—<br>~~es~~|500<br>~~es~~|MHz<br>~~es~~|
|½ UI<br>~~es~~<br>~~es~~<br>~~a~~|Half of Data Bit Time, or 90 degree<br>~~rns ~~<br>~~es~~<br>~~r~~~~**s**~~<br>~~n~~||0.400<br> ~~I ~~<br>~~es~~<br>~~(RD~~<br>~~sD~~<br>~~It~~|—<br> ~~sD~~<br>~~es~~<br>~~OD~~<br>~~sD~~<br>~~rs~~|0.417<br>~~sD ~~<br>~~es~~<br>~~OD~~<br>~~sD I~~<br>~~Is~~|—<br> ~~I~~<br>~~es~~<br>~~I~~<br>~~I~~<br>~~Ss~~|0.500<br>~~es~~<br>~~Ss~~|—<br>~~es~~|ns<br>~~es~~|
|fPCLK<br>~~es~~<br>~~a~~|PCLK frequency<br>~~r~~~~**s**~~<br>~~n~~||—<br>~~(RD ~~<br>~~sD~~<br>~~It~~<br>~~rs~~|125.0<br> ~~OD~~<br>~~sD~~<br>~~rs~~<br>~~rs~~|—<br>~~OD ~~<br>~~sD I~~<br>~~Is~~<br>~~ns~~|120.0<br> ~~I~~<br>~~I~~<br>~~Ss~~|—<br>~~Ss~~|100.0|MHz|
|Output TX to Input RX Marginper Edge<br>~~n~~<br>~~rs~~|||0.060<br>~~It~~<br>~~rs~~<br>~~rs~~|—<br>~~rs ~~<br>~~rs~~<br>~~rs~~|0.040<br> ~~Is ~~<br>~~rs~~<br>~~ns~~|—<br> ~~Ss~~<br>~~rs~~|0.051<br>~~Ss~~<br>~~rs~~|—<br>~~rs~~|ns<br>~~rs~~|
|**Soft D-PHY DDRX4 Inputs/Outputs with Clock and Data Centered at Pin, using PCLK Clock Input**<br>~~rs~~<br>~~ns~~<br>~~Ree~~||||||||||
|tSU_GDDRX4_MP<br>~~re~~<br>~~es~~|Input Data Set-Up Before CLK<br>~~re~~<br>~~rs I~~||0.133<br>~~re~~<br>~~a~~|—<br>~~re~~<br>~~ee~~|0.167<br>~~re~~<br>~~ee~~|—<br>~~re~~<br>~~ee~~|0.193<br>~~re~~<br>~~ee~~|—<br>~~re~~<br>~~ee~~|ns<br>~~re~~|
||||0.2<br>~~re~~<br>~~a~~<br>~~I~~|—<br>~~re~~<br>~~ee~~<br>~~rs~~|0.2<br>~~re~~<br>~~ee~~<br>~~ns~~|—<br>~~re~~<br>~~ee~~|0.2<br>~~re~~<br>~~ee~~|—<br>~~re~~<br>~~ee~~|UI<br>~~re~~|
|tHO_GDDRX4_MP<br>~~re~~<br>~~es~~|Input Data Hold After CLK<br>~~re~~<br>~~rs I~~||0.133<br>~~re~~<br>~~a~~<br>~~I~~<br>~~F SEE~~|—<br>~~re~~<br>~~ee~~<br>~~rs~~<br>~~SEE~~|0.167<br>~~re~~<br>~~ee~~<br>~~ns~~<br>~~SEE~~|—<br>~~re~~<br>~~ee~~<br>~~SEE~~|0.193<br>~~re~~<br>~~ee~~<br>~~SEE~~|—<br>~~re~~<br>~~ee~~<br>~~SEE~~|ns<br>~~re~~<br>~~SEE~~|
|tDVB_GDDRX4_MP<br>~~es~~<br>~~Tf~~|Output Data Valid Before CLK Output<br>~~rs I~~<br>~~Tf~~||0.133<br>~~a~~<br>~~I~~<br>~~Tf~~<br>~~F SEE~~<br>~~a~~|—<br>~~ee ~~<br>~~rs~~<br>~~Tf~~<br>~~SEE~~<br>~~ee~~|0.167<br> ~~ee ~~<br>~~ns~~<br>~~Tf~~<br>~~SEE~~<br>~~ee~~|—<br> ~~ee~~<br>~~Tf~~<br>~~SEE~~<br>~~ee~~|0.193<br>~~ee ~~<br>~~Tf~~<br>~~SEE~~<br>~~ee~~|—<br> ~~ee~~<br>~~Tf~~<br>~~SEE~~<br>~~es~~|ns<br>~~Tf~~<br>~~SEE~~|
||||0.2<br>~~Tf~~<br>~~F SEE~~<br>~~a~~|—<br>~~Tf~~<br>~~SEE~~<br>~~ee~~|0.2<br>~~Tf~~<br>~~SEE~~<br>~~ee~~|—<br>~~Tf~~<br>~~SEE~~<br>~~ee~~|0.2<br>~~Tf~~<br>~~SEE~~<br>~~ee~~|—<br>~~Tf~~<br>~~SEE~~<br>~~es~~|UI<br>~~Tf~~<br>~~SEE~~|
|tDQVA_GDDRX4_MP<br>~~re~~|Output Data Valid After CLK Output<br>~~re~~||0.133<br>~~F SEE~~<br>~~a~~<br>~~re~~<br>~~a~~|—<br>~~SEE~~<br>~~ee~~<br>~~re~~<br>~~ee~~|0.167<br>~~SEE~~<br>~~ee ~~<br>~~re~~<br>~~ee~~|—<br>~~SEE~~<br> ~~ee~~<br>~~re~~<br>~~ee~~|0.193<br>~~SEE~~<br>~~ee ~~<br>~~re~~<br>~~ee~~|—<br>~~SEE~~<br> ~~es~~<br>~~re~~<br>~~ee~~|ns<br>~~SEE~~<br>~~re~~|
||||0.2<br>~~re~~<br>~~a~~<br>~~ee~~|—<br>~~re~~<br>~~ee~~<br>~~ee es~~|0.2<br>~~re~~<br>~~ee~~<br>~~es~~|—<br>~~re~~<br>~~ee~~<br>~~ee~~|0.2<br>~~re~~<br>~~ee~~<br>~~es~~|—<br>~~re~~<br>~~ee~~|UI<br>~~re~~|
|fDATA_GDDRX4_MP<br>~~re~~<br>~~es~~|Input Data Bit Rate<br>for MIPI PHY<br>~~re~~<br>|WLCSP72<br>~~re~~<br>~~ee~~|—<br>~~re~~<br>~~a~~<br>~~ee~~<br>~~ee~~|—<br>~~re~~<br>~~ee ~~<br>~~ee~~<br>~~ee es~~|—<br>~~re~~<br> ~~ee ~~<br>~~ee~~<br>~~es~~|1000<br>~~re~~<br> ~~ee~~<br>~~ee~~<br>~~ee~~|—<br>~~re~~<br>~~ee ~~<br>~~ee~~<br>~~es~~|—<br>~~re~~<br> ~~ee~~<br>~~ee~~|Mbps<br>~~re~~<br>|
|||QFN72<br>~~ee~~<br>|—<br>~~ee~~<br>~~ee ~~<br>~~ET~~<br>|1250<br>~~ee~~<br> ~~ee es~~<br>~~ET~~<br>|—<br>~~ee~~<br>~~es ~~<br>~~ET LET~~<br>|1000<br>~~ee~~<br> ~~ee ~~<br>~~LET~~<br>|—<br>~~ee~~<br> ~~es~~<br>~~LET~~<br>|861<br>~~ee~~<br>~~LET~~<br>||
|||csfBGA121,<br>caBGA256,<br>csBGA289,<br>caBGA400<br>~~PL~~<br>|—<br>~~PL~~<br>~~ET~~<br><br>~~(I~~|1500<br>~~PL~~<br>~~ET~~<br><br>~~I~~|—<br>~~PL~~<br>~~ET LET~~<br><br>~~nD~~|1200<br>~~PL~~<br>~~LET~~<br><br>~~I~~|—<br>~~PL~~<br>~~LET~~<br>|1034<br>~~PL~~<br>~~LET~~<br>||
|½ UI<br>~~es~~|Half of Data Bit Time, or 90 degree<br>~~es~~||0.333<br>~~ET~~<br>~~es~~<br>~~(I~~<br>~~sD~~|—<br>~~ET~~<br>~~es~~<br>~~I~~<br>~~sD~~|0.417<br>~~ET LET~~<br>~~es~~<br>~~nD~~<br>~~sD~~|—<br>~~LET~~<br>~~es~~<br>~~I~~|0.483<br>~~LET~~<br>~~es~~|—<br>~~LET~~<br>~~es~~|ns<br>~~es~~|
|fPCLK<br>~~es~~<br>~~rs~~|PCLK frequency<br>~~es~~<br>~~rs~~||—<br>~~ET~~<br>~~es~~<br>~~(I~~<br>~~rs~~<br>~~sD~~<br>~~rs~~|187.5<br>~~ET~~<br>~~es~~<br>~~I~~<br>~~rs~~<br>~~sD~~<br>~~rs~~|—<br>~~ET LET~~<br>~~es~~<br>~~nD ~~<br>~~rs~~<br>~~sD~~<br>~~(ns~~|150.0<br>~~LET~~<br>~~es~~<br> ~~I~~<br>~~rs~~<br>~~ts~~|—<br>~~LET~~<br>~~es~~<br>~~rs~~<br>~~ts~~|129.3<br>~~LET~~<br>~~es~~<br>~~rs~~|MHz<br>~~es~~<br>~~rs~~|
|Output TX to Input RX Marginper Edge<br>~~rs~~<br>~~ns~~|||0.067<br>~~rs~~<br>~~sD~~<br>~~ns~~<br>~~rs~~|~~rs~~<br>~~sD~~<br>~~ns~~<br>~~rs~~|0.083<br>~~rs~~<br>~~sD~~<br>~~ns~~<br>~~(ns~~|~~rs~~<br>~~ns~~<br>~~ts~~|0.097<br>~~rs~~<br>~~ns~~<br>~~ts~~|~~rs~~<br>~~ns~~|ns<br>~~rs~~<br>~~ns~~|
© 2021-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
78
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**CrossLink-NX Family Data Sheet**
|**Parameter**<br>~~**e**l~~|**Description**|–**9**|–**9**|–**8**|–**8**|–**7**|–**7**|**Unit**|
|---|---|---|---|---|---|---|---|---|
|||**Min**|**Max**|**Min**|**Max**|**Min**|**Max**||
|**Video DDRX71 Inputs/Outputs with Clock and Data Aligned at Pin (GDDRX71_RX.ECLK) using PLL Clock Input - Figure 3.12and**<br>**Figure 3.13**<br>~~**e**l~~<br>~~e~~|||||||||
|tRPBi_DVA<br>~~i ee~~|Input Valid Bit "i" switch from CLK Rising Edge<br>("i" = 0 to 6, 0 aligns with CLK)<br>~~ee~~|—<br>~~ee~~<br>~~|~~|0.264<br>~~ee~~<br>~~|~~|—<br>~~ee~~<br>~~|}~~|0.264<br>~~ee~~<br>~~|}~~|—<br>~~ee~~<br>~~|}~~<br>~~**|**~~|0.3<br>~~ee~~|UI<br>~~ee~~<br>~~}~~|
|||—<br>~~ee~~<br>~~|~~|–<br>0.250<br>~~ee~~<br>~~|~~|—<br>~~ee~~<br>~~|}~~|–<br>0.250<br>~~ee~~<br>~~|}~~|—<br>~~ee~~<br>~~|}~~<br>~~**|**~~|–<br>0.249<br>~~ee~~|ns+(1/2+i)×UI<br>~~ee~~<br>~~}~~|
|tRPBi_DVE<br>~~a~~|Input Hold Bit "i" switch from CLK Rising Edge<br>("i" = 0 to 6, 0 aligns with CLK)<br>~~a~~|0.722<br>~~|~~<br>~~a~~|—<br>~~|~~<br>~~a~~|0.722<br>~~|}~~<br>~~a~~|—<br>~~|}~~<br>~~a~~|0.7<br>~~|}~~<br>~~**|**~~<br>~~a~~|—<br>~~a~~|UI<br>~~}~~<br>~~a~~|
|||0.235<br>~~a~~<br>~~a~~|—<br>~~a~~|0.235<br>~~a~~|—<br>~~a~~|0.249<br>~~a~~|—<br>~~a~~|ns+(1/2+i)×UI<br>~~a~~|
|tTPBi_DOV<br>~~i~~|Data Output Valid Bit "i" switch from CLK<br>RisingEdge("i" = 0 to 6, 0 aligns with CLK)<br>~~i~~|—<br>~~i~~|0.159<br>~~i~~|—<br>~~i~~|0.159<br>~~i~~|—<br>~~i~~|0.187<br>~~i~~|ns+i×UI<br>~~i~~|
|tTPBi_DOI<br>~~i~~<br>~~a~~|Data Output Invalid Bit "i" switch from CLK<br>RisingEdge("i" = 0 to 6, 0 aligns with CLK)<br>~~i~~<br>~~a~~|-0.159<br>~~i~~<br>~~a~~|—<br>~~i~~<br>~~a~~|-0.159<br>~~i~~<br>~~a~~<br>~~OO~~|—<br>~~i~~<br>~~a~~<br>~~OO~~|-<br>0.187<br>~~i~~<br>~~a~~<br>~~OO~~|—<br>~~i~~<br>~~a~~|ns+(i+ 1) ×UI<br>~~i~~<br>~~a~~|
|tTPBi_skew_UI<br>~~a~~<br>~~GO~~|TX skew in UI<br>~~a~~<br>~~GO~~|—<br>~~a~~<br>~~GO~~|0.150<br>~~a~~<br>~~GO~~|—<br>~~a~~<br>~~GO~~<br>~~OO~~<br>~~OO~~|0.150<br>~~a~~<br>~~GO~~<br>~~OO~~<br>~~OO~~|—<br>~~a~~<br>~~GO~~<br>~~OO~~<br>~~OO~~|0.150<br>~~a~~<br>~~GO~~|UI<br>~~a~~<br>~~GO~~|
|tB<br>~~eG~~|Serial Data Bit Time, = 1 UI<br>~~eG~~|1.058<br>~~eG~~|—<br>~~eG~~|1.058<br>~~OO~~<br>~~eG~~<br>~~OO~~<br>~~OG~~|—<br>~~OO~~<br>~~eG~~<br>~~OO~~<br>~~OG~~|1.247<br>~~OO~~<br>~~eG~~<br>~~OO~~<br>~~OG~~|—<br>~~eG~~|ns<br>~~eG~~|
|fDATA_TX71<br>~~eG~~|DDR71 Serial Data Rate<br>~~eG~~|—<br>~~eG~~|945<br>~~eG~~|—<br>~~OO~~<br>~~eG~~<br>~~OG~~|945<br>~~OO~~<br>~~eG~~<br>~~OG~~<br>~~GO~~|—<br>~~OO~~<br>~~eG~~<br>~~OG~~<br>~~GO~~|802<br>~~eG~~|Mbps<br>~~eG~~|
|fMAX_TX71<br>~~OO~~|DDR71 ECLK Frequency<br>~~OO~~|—<br>~~OO~~<br>~~QO~~|473<br>~~OO~~<br>~~QO~~|—<br>~~OG~~<br>~~OO~~<br>~~GO~~|473<br>~~OG~~<br>~~OO~~<br>~~GO~~<br>~~GO~~|—<br>~~OG~~<br>~~OO~~<br>~~GO~~<br>~~GO~~|401<br>~~OO~~|MHz<br>~~OO~~|
|fCLKIN<br>~~ee~~|7:1 Clock(PCLK)Frequency<br>~~ee~~|—<br>~~ee~~<br>~~QO~~<br>~~DO~~|135.0<br>~~ee~~<br>~~QO~~<br>~~DO~~|—<br>~~ee~~<br>~~GO~~|135.0<br>~~GO~~<br>~~ee~~<br>~~GO~~|—<br>~~GO~~<br>~~ee~~<br>~~GO~~|114.5<br>~~ee~~|MHz<br>~~ee~~|
|Output TX to Input RX Marginper Edge<br>~~ee~~<br>~~a~~||0.159<br>~~ee~~<br>~~QO~~<br>~~a~~<br>~~DO~~|—<br>~~ee~~<br>~~QO~~<br>~~a~~<br>~~DO~~|0.159<br>~~ee~~<br>~~GO~~<br>~~a~~|—<br>~~ee~~<br>~~GO~~<br>~~a~~|0.187<br>~~ee~~<br>~~GO~~<br>~~a~~|—<br>~~ee~~<br>~~a~~|ns<br>~~ee~~<br>~~a~~|
|**Memory Interface**<br>~~DO~~|||||||||
|**DDR3/DDR3L/LPDDR2/LPDDR3 READ(DQ Input Data are Aligned to DQS) -Figure 3.8**|||||||||
|tDVBDQ_DDR3<br>tDVBDQ_DDR3L<br>tDVBDQ_LPDDR2<br>tDVBDQ_LPDDR3|Data Input Valid before DQS Input|—|–<br>0.235|—|–<br>0.235|—|–<br>0.277|ns + 1/2 UI|
|tDVADQ_DDR3<br>tDVADQ_DDR3L<br>tDVADQ_LPDDR2<br>tDVADQ_LPDDR3|Data Input Valid after DQS Input|0.235|—|0.235|—|0.277|—|ns + 1/2 UI|
|fDATA_DDR3<br>fDATA_DDR3L<br>fDATA_LPDDR2<br>fDATA_LPDDR3|DDR Memory Data Rate|—|1066|—|1066|—|904|Mb/s|
|fMAX_ECLK_DDR3<br>fMAX_ECLK_DDR3L<br>fMAX_ECLK_LPDDR2<br>fMAX_ECLK_LPDDR3|DDR Memory ECLK Frequency|—|533|—|533|—|452|MHz|
|fMAX_SCLK_DDR3<br>fMAX_SCLK_DDR3L<br>fMAX_SCLK_LPDDR2<br>fMAX_SCLK_LPDDR3|DDR Memory SCLK Frequency|—|133.3|—|133.3|—|113|MHz|
|**DDR3/DDR3L/LPDDR2/LPDDR3 WRITE(DQ Output Data are Centered to DQS) -Figure 3.11**|||||||||
|tDQVBS_DDR3<br>tDQVBS_DDR3L<br>tDQVBS_LPDDR2<br>tDQVBS_LPDDR3|Data Output Valid before DQS Output|—|–<br>0.235|—|–<br>0.235|—|–<br>0.277|ns + 1/2 UI|
|tDQVAS_DDR3<br>tDQVAS_DDR3L<br>tDQVAS_LPDDR2<br>tDQVAS_LPDDR3|Data Output Valid after DQS Output|0.235|—|0.235|—|0.277|—|ns + 1/2 UI|
|fDATA_DDR3<br>fDATA_DDR3L<br>fDATA_LPDDR2<br>fDATA_LPDDR3|DDR Memory Data Rate|—|1066|—|1066|—|904|Mb/s|
© 2021-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02049-1.8
79
**CrossLink-NX Family Data Sheet**
|**Parameter**|**Description**|–**9**|–**9**|–**8**|–**8**|–**7**|–**7**|**Unit**|
|---|---|---|---|---|---|---|---|---|
|||**Min**|**Max**|**Min**|**Max**|**Min**|**Max**||
|fMAX_ECLK_DDR3<br>fMAX_ECLK_DDR3L<br>fMAX_ECLK_LPDDR2<br>fMAX_ECLK_LPDDR3|DDR Memory ECLK Frequency|—|533|—|533|—|452|MHz|
|fMAX_SCLK_DDR3<br>fMAX_SCLK_DDR3L<br>fMAX_SCLK_LPDDR2<br>fMAX_SCLK_LPDDR3|DDR Memory SCLK Frequency|—|133.3|—|133.3|—|113|MHz|
**Notes** :
1. Commercial timing numbers are shown. Industrial numbers are typically slower and can be extracted from the Lattice Radiant software.
2. General I/O timing numbers are based on LVCMOS 1.8, 8 mA, Fast Slew Rate, 0 pF load. Generic DDR timing are numbers based on LVDS I/O. DDR3 timing numbers are based on SSTL15. LPDDR2 and LPDDR3 timing numbers are based on HSUL12.
3. Uses LVDS I/O standard for measurements.
4. Maximum clock frequencies are tested under best case conditions. System performance may vary upon the user environment.
5. All numbers are generated with the Lattice Radiant software.
6. This clock skew is not the internal clock network skew. The Nexus family devices have very low internal clock network skew that can be approximated to 0 ps. These tSKEW values measured externally at system level includes additional skew added by the I/O, wire bonding and package ball.
**==> picture [448 x 130] intentionally omitted <==**
**----- Start of picture text -----**<br>
Rx CLK (in)<br>ee rs ee<br>Rx DATA (in)<br>tSU tSU<br>tHD tHD<br>**----- End of picture text -----**<br>
**Figure 3.7. Receiver RX.CLK.Centered Waveforms**
**==> picture [423 x 153] intentionally omitted <==**
**----- Start of picture text -----**<br>
½ UI<br>½ UI<br>1 UI<br>Rx CLK (in)<br>or DQS input<br>Rx DATA (in)<br>or DQS input<br>RR<br>tDVA/tDVADQ<br>tDVA/tDVADQ<br>tDVE/tDVEDQ<br>tDVE/tDVEDQ<br>**----- End of picture text -----**<br>
**Figure 3.8. Receiver RX.CLK.Aligned and DDR Memory Input Waveforms**
© 2021-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
80
FPGA-DS-02049-1.8
**CrossLink-NX Family Data Sheet**
**==> picture [343 x 142] intentionally omitted <==**
**----- Start of picture text -----**<br>
1/2 UI 1/2 UI 1/2 UI 1/2 UI<br>Tx CLK (out)<br>or DQS Output<br>Tx DATA (out)<br>or DQ Output<br>tDVB/tDQVBS tDVB/tDQVBS<br>tDVA/tDQVA tDVA/tDQVAS<br>**----- End of picture text -----**<br>
**Figure 3.9. Transmit TX.CLK.Centered and DDR Memory Output Waveforms**
**==> picture [309 x 120] intentionally omitted <==**
**----- Start of picture text -----**<br>
1 UI<br>Tx CLK (out)<br>Tx DATA (out)<br>tDIB || tDIB<br>tDIA tDIA<br>**----- End of picture text -----**<br>
**Figure 3.10. Transmit TX.CLK.Aligned Waveforms**
© 2021-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02049-1.8
81
**CrossLink-NX Family Data Sheet**
## **Receiver – Shown for one LVDS Channel**
|0!|0x<br>0x<br>0x<br>0x<br>0x<br>0x<br>0x<br>~~XOX 1X 2K 3X 4X 5X 6K~~<br>0!<br>1!<br>4<br>i<br>l<br>il<br>t<br>il<br>I<br>1<br>1<br>il<br>I<br>il<br>I<br>'<br>f<br>1<br>1|Bit #<br>10 – 1<br>11 – 2<br>12 – 3<br>13 – 4<br>14 – 5<br>15 – 6<br>16 – 7<br>~~6K OK 1X 2X 3X 4X 5X 6X~~<br>1!<br>2!<br>t<br>I<br>1<br>I<br>I<br>'<br>f<br>1<br>1|Bit #<br>20 – 8<br>21 – 9<br>22 – 10<br>23 – 11<br>24 – 12<br>25 – 13<br>26 – 14<br>~~6X OX 1X 2K SX 4X 5X OK~~<br>2!<br>3}<br>1<br>1<br>!<br>1<br>1<br>1<br>!<br>1<br>!<br>1<br>'<br>f<br>|<br>'<br>1<br>1<br>1|Bit #<br>30 – 15<br>31 – 16<br>32 – 17<br>33 – 18<br>34 – 19<br>35 – 20<br>36 – 21<br>~~OK OX 1X 2X 3X 4X 5X 6X~~<br>3}<br>4)<br>1<br>1<br>1<br>1<br>1<br>1<br>1<br>!<br>1<br>1<br>'<br>f<br>|<br>'<br>|<br>1<br>1<br>1|Bit #<br>40 – 22<br>41 – 23<br>42 – 24<br>43 – 25<br>44 – 26<br>45 – 27<br>46 – 28<br>~~6X 0)~~<br>4)<br>1<br>1<br>1<br>!<br>1<br>'<br>f<br>|<br>'<br>|<br>1<br>1|
|---|---|---|---|---|---|
|**For each Channel:**<br>**7-bit Output Words**<br>il<br>il<br>il<br>il||||||
## **Transmitter – Shown for one LVDS Channel**
# of Bits Data Out756 Mb/s ~~MAAPQAAAQAAAADAYAAZAA2ABDEDAAE|~~ (23¥45) ~~(EXO)~~ y ~~(2\3¥4Y5)2~~ 1 ~~(23¥4V5)YY)~~ | ~~(23¥4Y5)DALY(EX)~~ | Clock Out 01 1 2 | 3: 4: 108 MHz Bit # ~~**I**~~ Bit # ~~I~~ I Bit # ! Bit # 1 1 **For each Channel:** 00 – 1 ~~{~~ I 10 – 8 ~~f~~ 1 20 – 15 1 30 – 22 1 1 **7-bit Output Words** 00 – 200 – 3 11 – 912 – 10 21 – 1622 – 17 31 – 2332 – 24 **to FPGA Fabric** 00 – 4 13 – 11 23 – 18 33 – 25 00 – 5 14 – 12 24 – 19 34 – 26 00 – 6 **I** 15 – 13 II 25 – 20 ! 35 – 27 1 1 00 – 7 H 16 – 14 j 26 – 21 36 – 28
## **Figure 3.11. DDRX71 Video Timing Waveforms**
**==> picture [444 x 176] intentionally omitted <==**
**----- Start of picture text -----**<br>
Bit 0 Bit 1 Bit i<br>1 1/2 UI 1 I 1/2 UI 1<br>I 1 1 1 1<br>CLK (in) y 1 UI 11 11 " 1I<br>ul1 II 11 II<br>1 I 1<br>1 I 1 I<br>1 I 1 I<br>1 I 1 1<br>1 I 1 1<br>1 I 1 1<br>1 I 1 1<br>1 I 1 1<br>! I 1 1<br>! I 1 1<br>1 II 1 11<br>DATA (in)<br>1 t 1 t<br>i) 1 1 t 1<br>i]io tSU_0 !1 1 t 1<br>tHD_0<br>tSU_i<br>tHD_i<br>**----- End of picture text -----**<br>
**Figure 3.12. Receiver DDRX71_RX Waveforms**
© 2021-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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**CrossLink-NX Family Data Sheet**
|Bit 0<br>Bit 1<br>Bit i|
|---|
|1 UI|
|CLK (out)|
|tDIB_0<br>DATA (out)<br>tDIA_0<br>X00<br>0000<br>O~~NIO~~N|
|tDIB_i|
|tDIA_i|
|**Figure 3.13. Transmitter DDRX71_TX Waveforms**|
|**3.18. sysCLOCK PLL Timing (VCC = 1.0 V) – Commercial/Industrial**|
|**Table 3.34. sysCLOCK PLL Timing (VCC = 1.0 V) – Commercial/Industrial**|
|**Parameter**<br>**Descriptions**<br>**Conditions**<br>**Min**<br>**Typ.**<br>**Max**<br>**Units**<br>fIN<br>Input Clock Frequency (CLKI, CLKFB)<br>—<br>18<br>—<br>500<br>MHz<br>fOUT<br>Output Clock Frequency<br>—<br>6.25<br>—<br>800<br>MHz<br>fVCO<br>PLL VCO Frequency<br>—<br>800<br>—<br>1600<br>MHz<br>fPFD<br>Phase Detector Input Frequency<br>Without Fractional-N<br>Enabled<br>18<br>—<br>500<br>MHz<br>With Fractional-N<br>Enabled<br>18<br>—<br>100<br>MHz<br>**AC Characteristics**<br>tDT<br>Output Clock Duty Cycle<br>—<br>45<br>—<br>55<br>%<br>tPH4<br>Output Phase Accuracy<br>—<br>–5<br>—<br>5<br>%<br>tOPJIT1<br>Output Clock Period Jitter<br>fOUT≥ 200 MHz<br>—<br>—<br>250<br>ps p-p<br>fOUT< 200 MHz<br>—<br>—<br>0.05<br>UIPP<br>Output Clock Cycle-to-Cycle Jitter<br>fOUT≥ 200 MHz<br>—<br>—<br>250<br>ps p-p<br>fOUT< 200 MHz<br>—<br>—<br>0.05<br>UIPP<br>Output Clock Phase Jitter<br>fPFD≥ 200 MHz<br>—<br>—<br>250<br>ps p-p<br>60 MHz ≤ fPFD< 200 MHz<br>—<br>—<br>350<br>psp-p<br>30 MHz ≤ fPFD< 60 MHz<br>—<br>—<br>450<br>ps p-p<br>18 MHz ≤ fPFD< 30 MHz<br>—<br>—<br>650<br>ps p-p<br>Output Clock Period Jitter (Fractional-N)<br>fOUT≥ 200 MHz<br>—<br>—<br>350<br>ps p-p<br>fOUT< 200 MHz<br>—<br>—<br>0.07<br>UIPP<br>Output Clock Cycle-to-Cycle Jitter<br>(Fractional-N)<br>fOUT≥ 200 MHz<br>—<br>—<br>400<br>ps p-p<br>fOUT< 200 MHz<br>—<br>—<br>0.08<br>UIPP<br>fBW3<br>PLL Loop Bandwidth<br>—<br>0.45<br>—<br>13<br>MHz<br>tLOCK2<br>PLL Lock-in Time<br>—<br>—<br>—<br>10<br>ms<br>tUNLOCK<br>PLL Unlock Time (from RESET goes HIGH)<br>—<br>—<br>—<br>50<br>ns<br>~~ee~~<br>~~ee ae~~<br>~~—~~<br>~~ee ee ee oe oe~~<br>~~**i**—_—-:-—~~<br>~~er~~<br>~~aGG~~<br>~~a~~<br>~~ce~~<br>~~ee~~<br>~~ee~~<br>~~a~~<br>~~ee~~<br>~~ee~~<br>~~ee eee ee~~<br>~~es~~<br>~~ee on~~<br>~~re~~<br>~~pf~~<br>~~—~~<br>~~eeee~~<br>~~eeeeel~~|
© 2021-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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**CrossLink-NX Family Data Sheet**
|**Parameter**|**Descriptions**|**Conditions**|**Min**|**Typ.**|**Max**|**Units**|
|---|---|---|---|---|---|---|
|tIPJIT<br>~~es~~|Input Clock Period Jitter<br>~~ns~~|fPFD≥ 20 MHz|—|—|500|ps p-p|
|||fPFD< 20 MHz<br>~~ns~~|—<br>~~ns~~|—<br>~~ns~~|0.01<br>~~ns~~|UIPP<br>~~ns~~|
|tHI<br>~~es~~<br>~~es~~|Input Clock High Time<br>~~ns~~<br>~~ts rn~~|90% to 90%<br>~~ns~~<br>~~rn~~|0.5<br>~~ns~~|—<br>~~ns~~|—<br>~~ns~~|ns<br>~~ns~~|
|tLO<br>~~es~~<br>~~es~~<br>~~es~~<br>~~Fe~~|Input Clock Low Time<br>~~ns~~<br>~~ts rn~~<br>~~ts~~|10% to 10%<br>~~ns~~<br>~~rn~~<br>~~ts~~|0.5<br>~~ns~~<br>~~ts~~|—<br>~~ns~~<br>~~ts~~<br>~~I~~|—<br>~~ns~~<br>~~ts~~|ns<br>~~ns~~<br>~~ts~~|
|tRST<br>~~es~~<br>~~es~~<br>~~Fe~~|RST/ Pulse Width<br>~~ts rn~~<br>~~ts~~|—<br>~~rn~~<br>~~ts~~|1<br>~~ts~~|—<br>~~ts~~<br>~~I~~|—<br>~~ts~~|ms<br>~~ts~~|
|fSSC_MOD<br>~~es~~<br>~~Fe~~|Spread Spectrum Clock Modulation<br>~~ts~~|—<br>~~ts~~|20<br>~~ts~~|—<br>~~ts~~<br>~~I~~|200<br>~~ts~~|kHz<br>~~ts~~|
|fSSC_MOD_AMP<br>~~Fe~~|Spread Spectrum Clock Modulation<br>Amplitude Range|—<br>~~ee~~|0.25<br>~~eee~~|—<br>~~I~~<br>~~eee~~|2.00<br>~~eee~~|%<br>~~eee~~|
|fSSC_MOD_STEP<br>~~Fe~~<br>~~a~~|Spread Spectrum Clock Modulation<br>Amplitude Step Size<br>~~ee~~|—<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~eee~~|0.25<br>~~I~~<br>~~ee~~<br>~~eee~~|—<br>~~ee~~<br>~~eee~~|%<br>~~ee~~<br>~~eee~~|
**Notes** :
1. Jitter sample is taken over 10,000 samples for Period jitter, and 1,000 samples for Cycle-to-Cycle jitter of the primary PLL output with clean reference clock with no additional I/O toggling.
2. Output clock is valid after tLOCK for PLL reset and dynamic delay adjustment.
3. Result from Lattice Radiant software.
4. CLKOS as compared to CLKOP output for one phase step at the maximum VCO frequency.
## **3.19. Internal Oscillators Characteristics**
**Table 3.35. Internal Oscillators (VCC = 1.0 V)**
|**Symbol**|**Parameter Description**|**Min**|**Typ**|**Max**|**Unit**|
|---|---|---|---|---|---|
|fCLKHF|HFOSC CLKK Clock Frequency|418.5|450|481.5|MHz|
|fCLKLF|LFOSC CLKK Clock Frequency|25.6|32|38.4|kHz|
|DCHCLKHF|HFOSC Duty Cycle (Clock High Period)|45|50|55|%|
|DCHCLKLF|LFOSC Duty Cycle (Clock High Period)|45|50|55|%|
## **3.20. User I[2] C Characteristics**
**Table 3.36. User I[2] C Specifications (VCC = 1.0 V)**
|**Symbol**|**Parameter**<br>**Description**|**STD Mode**|**STD Mode**|**STD Mode**|**FAST Mode**|**FAST Mode**|**FAST Mode**|**FAST Mode Plus2**|**FAST Mode Plus2**|**FAST Mode Plus2**|**Units**|
|---|---|---|---|---|---|---|---|---|---|---|---|
|||**Min**|**Typ**|**Max**|**Min**|**Typ**|**Max**|**Min**|**Typ**|**Max**||
|fscl|SCL Clock<br>Frequency|—|—|100|—|—|400|—|—|1000|kHz|
|TDELAY1|Optional delay<br>through delayblock|—|—|62|—|—|62|—|—|62|ns|
**Notes** :
1. Refer to the I[2] C Specification for timing requirements. User design should set constraints in Lattice Design software to meet this industrial I[2] C Specification.
2. Fast Mode Plus maximum speed may be achieved by using external pull up resistor on I[2] C bus. Internal pull up may not be sufficient to support the maximum speed.
© 2021-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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**CrossLink-NX Family Data Sheet**
## **3.21. Analog-Digital Converter (ADC) Block Characteristics**
|**Symbol**<br>~~eS~~|**Description**|**Condition**|**Min**|**Typ**|**Max**|**Unit**|
|---|---|---|---|---|---|---|
|VREFINT_ADC<br>~~eS~~<br>~~a~~|ADC Internal Reference<br>Voltage<br>~~a~~|—<br>~~ee~~|1.142<br>~~ee~~|1.2|1.262|V|
|VREFEXT_ADC<br>~~a~~|ADC External Reference<br>Voltage<br>~~a~~|—|1.0|—|1.8|V|
|NRES_ADC<br>~~a~~|ADC Resolution<br>~~a~~|—|—|12|—|bits|
|ENOBADC<br>~~A~~|Effective Number of Bits<br>~~A~~|—<br>|9.9<br>|11<br><br>~~ee~~|—<br>|bits<br>|
|VSR_ADC<br>~~A~~|ADC Input Range<br>~~A ~~|Bipolar Mode, Internal VREF<br> ~~ee~~|VCM_ADC ―<br>VREFINT_ADC/4<br>~~ee~~|VCM_ADC<br>~~ee~~<br>~~ee~~<br>~~ee~~|VCM_ADC+<br>VREFINT_ADC/4<br>~~ee~~<br>~~ee~~|V<br>~~ee~~|
|||Bipolar Mode, External VREF<br>~~ee~~|VCM_ADC ―<br>VREFEXT_ADC/4<br>~~ee~~|VREFEXT_ADC<br>~~ee~~<br>~~ee~~<br>~~ee~~|VCM_ADC+<br>VREFEXT_ADC/4<br>~~ee~~<br>~~ee~~|V<br>~~ee~~|
|||Uni-polar Mode, Internal VREF<br>~~eS~~<br>~~OO~~|0<br>~~eS~~|—<br>~~ee ~~<br>~~eS~~|VREFINT_ADC<br> ~~ee~~<br>~~eS~~|V<br>~~eS~~|
|||Uni-polar Mode, External VREF<br>~~OO~~<br>~~es~~|0<br>~~ee~~|—<br>~~ee~~|VREFEXT_ADC|V|
|VCM_ADC<br>~~cee~~|ADC Input Common<br>Mode Voltage (for fully<br>differential signals)<br>~~cee~~|Internal VREF<br>~~OO~~<br>~~cee~~<br>~~es~~|—<br>~~cee~~<br>~~ee~~|VREFINT_ADC/2<br>~~cee~~<br>~~ee~~|—<br>~~cee~~|V<br>~~cee~~|
|||External VREF<br>~~cee~~<br>~~es~~|—<br>~~cee~~<br>~~ee~~|VREFEXT_ADC/2<br>~~cee~~<br>~~ee~~<br>~~ee~~|—<br>~~cee~~<br>~~ee~~|V<br>~~cee~~<br>~~ee~~|
|fCLK_ADC<br>~~i~~|ADC Clock Frequency<br>~~i~~|—<br>~~es~~|—<br>~~ee ~~|25<br> ~~ee~~|40|MHz|
|DCCLK_ADC<br>~~a~~|ADC Clock DutyCycle<br>~~a~~|—|48|50|52|%|
|fINPUT_ADC<br>~~A~~|ADC Input Frequency<br>~~A~~|—|—|—|500|kHz|
|FSADC<br>~~A~~<br>~~a~~|ADC SamplingRate<br>~~A~~<br>~~a~~|—|—|1|—|MS/s|
|NTRACK_ADC<br>~~A~~|ADC Input TrackingTime<br>~~A~~<br>~~a~~|—|4|—|—|cycles3|
|RIN_ADC<br>~~a~~|ADC Input Equivalent<br>Resistance<br>~~ee~~|1 MS/s, Sampled @ 2 clock<br>cycles<br>~~ee~~|—<br>~~ee~~|116<br>~~ee~~|—<br>~~ee~~|kΩ<br>~~ee~~|
|tCAL_ADC<br>~~i~~|ADC Calibration Time|—|—|—|6500|cycles3|
|LOUTput_ADC<br>~~a~~|ADC Conversion Time|Includes minimum tracking<br>time of four cycles|25|—|—|cycles3|
|DNLADC<br>~~a~~|ADC Differential<br>Nonlinearity|—|**–**1|—|1|LSB|
|INLADC<br>~~a~~|ADC Integral<br>Nonlinearity|—|**–**22|—|2.21|LSB|
|SFDRADC<br>~~a~~|ADC Spurious Free<br>Dynamic Range|—|67.7|77|—|dBc|
|THDADC<br>~~a~~|ADC Total Harmonic<br>Distortion|—|—|**–**76|**–**66.8|dB|
|SNRADC<br>~~a~~|ADC Signal to Noise<br>Ratio|—|61.9|68|—|dB|
|SNDRADC<br>~~a~~|ADC Signal to Noise Plus<br>Distortion Ratio<br>~~a~~|—<br>~~ee~~|61.7<br>~~ee~~|67|—|dB|
|ERRGAIN_ADC<br>~~i~~|ADC Gain Error<br>~~i~~<br>~~a~~|—<br>~~a~~|–0.5|—|0.5|% FSADC|
|ERROFFSET_ADC<br>~~i~~|ADC Offset Error<br>~~i~~|—|–2|—|2|LSB|
|CIN_ADC<br>~~i~~<br>~~a~~|ADC Input Equivalent<br>Capacitance<br>~~i~~<br>~~a~~|—|—|2|—|pF|
**Notes:**
1. ADC is available in Commercial/Industrial –8 and –9 speed grades.
2. Not tested; guaranteed by design.
3. ADC Sample Clock cycles. See ADC User Guide for Nexus Platform (FPGA-TN-02129) for more details.
© 2021-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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**CrossLink-NX Family Data Sheet**
## **3.22. Comparator Block Characteristics**
**Table 3.38. Comparator Specifications[1]**
|**Symbol**|**Description**|**Min**|**Typ**|**Max**|**Unit**|
|---|---|---|---|---|---|
|fIN_COMP|Comparator Input Frequency|—|—|10|MHz|
|VIN_COMP|Comparator Input Voltage|0|—|VCCADC18|V|
|VOFFSET_COMP|Comparator Input Offset|–23|—|24|mV|
|VHYST_COMP|Comparator Input Hysteresis|10|—|31|mV|
|VLATENCY_COMP|Comparator Latency|—|—|31|ns|
## **Note:**
1. Comparator is available in select speed grades. See Ordering Information.
## **3.23. Digital Temperature Readout Characteristics**
Digital temperature Readout (DTR) is implemented in one of the channels of ADC1.
**Table 3.39. DTR Specifications[1, 2]**
|**Symbol**|**Description**|**Condition**|**Min**|**Typ**|**Max**|**Unit**|
|---|---|---|---|---|---|---|
|DTRRANGE|DTR Detect Temperature<br>Range|—|–40|—|100|°C|
|DTRACCURACY|DTR Accuracy|with external voltage1<br>reference range of 1.0 V<br>to 1.8 V|–13|±4|13|°C|
|DTRRESOLUTION|DTR Resolution|with external voltage<br>reference|**–**0.3|—|0.3|°C|
**Notes:**
1. External voltage reference (VREF) should be 0.1% accurate or better. DTR sensitivity to VREF is -4.1 °C per VREF per-cent (for example, if the VREF is 1 % low, then the DTR will read +4.1 °C high).
2. DTR is available in Commercial/Industrial –8 and –9 speed grades.
## **3.24. Hardened MIPI D-PHY Characteristics**
**Table 3.40. Hardened D-PHY Input Timing and Levels**
|**Symbol**<br>~~a~~|**Description**<br>~~a~~<br>~~a~~|**Conditions**<br>~~a~~<br>~~a~~|**Min**<br>~~a~~<br>~~a~~|**Typ**<br>~~a~~<br>~~a~~|**Max**<br>~~a~~<br>~~a~~|**Unit**<br>~~a~~<br>~~a~~|
|---|---|---|---|---|---|---|
|**High Speed (Differential) Input DC Specifications**<br>~~a~~|||||||
|VCMRX(DC)<br>~~a~~<br>~~a~~|Common-mode Voltage in High Speed<br>Mode<br>~~a~~<br>~~a~~<br>~~a~~|—<br>~~a~~<br>~~a~~<br>~~ee~~|70<br>~~a~~<br>~~a~~|—<br>~~a~~<br>~~a~~<br>~~ee~~|330<br>~~a~~<br>~~a~~<br>~~ee~~|mV<br>~~a~~<br>~~a~~<br>~~ee~~|
|VIDTH<br>~~a~~<br>~~a~~|Differential Input HIGH Threshold<br>~~a~~<br>~~a~~<br>~~a~~|0.08 Gbps ≤ VIDTH≤ 1.5 Gbps<br>~~a~~<br>~~a~~<br>~~ee~~|70<br>~~a~~<br>~~a~~|—<br>~~a~~<br>~~a~~<br>~~ee~~|—<br>~~a~~<br>~~a~~<br>~~ee~~|mV<br>~~a~~<br>~~a~~<br>~~ee~~|
|||1.5 Gbps < VIDTH≤ 2.5 Gbps<br>~~a~~<br>~~ee~~<br>~~a~~|40<br>~~a~~<br>~~a~~<br>~~ee~~|—<br>~~a~~<br>~~ee~~<br>~~a~~|—<br>~~a~~<br>~~ee~~<br>~~a~~|mV<br>~~a~~<br>~~ee~~<br>~~a~~|
|VIDTL<br>~~a~~<br>~~ee~~|Differential Input LOW Threshold<br>~~a~~<br>~~a~~<br>~~ee~~|0.08 Gbps ≤ VIDTL≤ 1.5 Gbps<br>~~a~~<br>~~ee~~<br>~~a~~<br>~~ee~~|—<br>~~a~~<br>~~a~~<br>~~ee~~<br>~~ee~~|—<br>~~a~~<br>~~ee~~<br>~~a~~<br>~~ee~~|–70<br>~~a~~<br>~~ee~~<br>~~a~~<br>~~ee~~|mV<br>~~a~~<br>~~ee~~<br>~~a~~<br>~~ee~~|
|||1.5 Gbps < VIDTL≤ 2.5 Gbps<br>~~ee~~<br>~~a~~|—<br>~~ee~~<br>~~ee~~<br>~~a~~|—<br>~~ee~~<br>~~a~~|–40<br>~~ee~~<br>~~a~~|mV<br>~~ee~~<br>~~a~~|
|VIHHS<br>~~ee~~<br>~~Ge~~|Input HIGH Voltage (for HS mode)<br>~~ee~~<br>~~Ge~~|—<br>~~ee~~<br>~~a~~<br>~~Ge~~|—<br>~~ee~~<br>~~ee~~<br>~~a~~<br>~~Ge~~|—<br>~~ee~~<br>~~a~~<br>~~Ge~~|460<br>~~ee~~<br>~~a~~<br>~~Ge~~|mV<br>~~ee~~<br>~~a~~<br>~~Ge~~|
|VILHS<br>~~Ge~~<br>~~a~~<br>~~a~~|Input LOW Voltage<br>~~Ge~~<br>~~ee~~<br>|—<br>~~Ge~~<br>~~ee~~<br>|–40<br>~~Ge~~<br>~~ee~~<br>|—<br>~~Ge~~<br>|—<br>~~Ge~~<br>|mV<br>~~Ge~~<br>|
|VTERM-EN<br>~~a~~<br>~~a~~<br>~~a~~|Single-ended voltage for HS Termination<br>Enable4 <br>~~ee~~<br>|—<br>~~ee~~<br>|—<br>~~ee~~<br>|—<br>|450<br>|mV<br>|
|ZID<br>~~a~~|Differential Input Impedance<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~|80<br>~~ee~~<br>~~ee~~|100<br>~~ee~~|125<br>~~ee~~|Ω<br>~~ee~~|
© 2021-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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**CrossLink-NX Family Data Sheet**
|**Symbol**<br>~~a~~|**Description**<br>~~a~~|**Conditions**|**Min**|**Typ**|**Max**|**Unit**|
|---|---|---|---|---|---|---|
|**High Speed (Differential) Input AC Specifications**<br>~~Ct~~|||||||
|ΔVCMRX(HF)1<br>~~P~~|Common-mode Interference (>450 MHz)<br>~~Pf~~|0.08 Gbps ≤ ∆VCMRX(HF)≤ 1.5<br>Gbps<br>~~a~~|—<br>~~ee~~|—<br>~~ee~~|100<br>~~ee~~|mV<br>~~ee~~|
|||1.5 Gbps < ∆VCMRX(HF)≤ 2.5<br>Gbps<br>~~a~~|—<br>~~ee~~|—<br>~~ee~~|50<br>~~ee~~|mV<br>~~ee~~|
|ΔVCMRX(LF)2, 3<br>~~P~~<br>~~Pf~~<br>~~a~~|Common-mode Interference (50 MHz–450<br>MHz)<br>~~Pf~~<br>~~Pf~~<br>~~ee~~|0.08 Gbps ≤ ∆VCMRX(LF)≤ 1.5<br>Gbps<br>~~a~~<br>~~rr~~|–50<br>~~ee~~<br>~~rr~~<br>~~ee~~|—<br>~~ee~~<br>~~rr~~<br>~~ee~~|50<br>~~ee~~<br>~~rr~~<br>~~ee~~|mV<br>~~ee~~<br>~~rr~~<br>~~ee~~|
|||1.5 Gbps < ∆VCMRX(LF)≤ 2.5<br>Gbps<br>~~rr~~<br>~~ee~~|–25<br>~~rr~~<br>~~ee~~<br>~~ee~~|—<br>~~rr~~<br>~~ee~~|25<br>~~rr~~<br>~~ee~~|mV<br>~~rr~~<br>~~ee~~|
|CCM<br>~~Pf~~<br>~~a~~|Common-mode Termination<br>~~Pf~~<br>~~ee~~|—<br>~~rr~~<br>~~ee~~|—<br>~~rr~~<br>~~ee~~<br>~~ee~~|—<br>~~rr~~<br>~~ee ~~|60<br>~~rr~~<br> ~~ee~~|pF<br>~~rr~~<br>~~ee~~|
|**Low Power (Single-Ended) Input DC Specifications**<br>~~ee~~<br>~~ee ee~~<br>~~a~~|||||||
|VIH<br>~~a~~|Low Power Mode Input HIGH Voltage<br>~~a~~|—<br>~~a~~|760<br>~~a~~|—<br>~~a~~|—<br>~~a~~|mV<br>~~a~~|
|VIL<br>~~a~~|Low Power Mode Input LOW Voltage<br>~~a~~|—<br>~~a~~|—<br>~~a~~|—<br>~~a~~|550<br>~~a~~|mV<br>~~a~~|
|VIL-ULP<br>~~a~~|Ultra Low Power Input LOW Voltage<br>~~a~~|—<br>~~a~~|—<br>~~a~~|—<br>~~a~~|300<br>~~a~~|mV<br>~~a~~|
|VHYST<br>~~a~~|Low Power Mode Input Hysteresis<br>~~a~~|—<br>~~a~~|25<br>~~a~~|—<br>~~a~~|—<br>~~a~~|mV<br>~~a~~|
|℮SPIKE<br>~~a~~|Input Pulse Rejection<br>~~a~~|—<br>~~a~~|—<br>~~a~~|—<br>~~a~~|300<br>~~a~~|V∙ps<br>~~a~~|
|TMIN-RX<br>~~a~~|Minimum Pulse Width Response<br>~~a~~|—<br>~~a~~|20<br>~~a~~|—<br>~~a~~|—<br>~~a~~|ns<br>~~a~~|
|VINT<br>~~a~~|Peak Interference Amplitude<br>~~a~~|—<br>~~a~~|—<br>~~a~~|—<br>~~a~~|200<br>~~a~~|mV<br>~~a~~|
|fINT<br>~~a~~|Interference Frequency<br>~~a~~|—<br>~~a~~|450<br>~~a~~|—<br>~~a~~|—<br>~~a~~|MHz<br>~~a~~|
|**Contention Detector (LP-CD) DC Specifications**<br>~~a~~|||||||
|VIHCD<br>~~a~~|Contention Detect HIGH Voltage<br>~~a~~|—<br>~~a~~|450<br>~~a~~|—<br>~~a~~|—<br>~~a~~|mV<br>~~a~~|
|VILCD<br>~~a~~|Contention Detect LOW Voltage<br>~~a~~|—<br>~~a~~|—<br>~~a~~|—<br>~~a~~|200<br>~~a~~|mV<br>~~a~~|
**Notes** :
1. This is peak amplitude of sine wave modulated to the receiver inputs.
2. Input common-mode voltage difference compared to average common-mode voltage on the receiver inputs.
3. Exclude any static ground shift of 50 mV.
4. High Speed Differential RTERM is enabled when both DP and DN are below this voltage.
|**Symbol**<br>~~a~~|**Description**<br>~~a~~<br>~~a~~|**Conditions**<br>~~a~~<br>~~es~~|**Min**<br>~~a~~<br>~~ee~~|**Typ**<br>~~a~~<br>~~ee~~|**Max**<br>~~a~~<br>~~ee~~|**Unit**<br>~~a~~|
|---|---|---|---|---|---|---|
|**High Speed(Differential) Output DC Specifications**<br>~~a~~<br>~~es ee ee~~<br>~~aT~~<br>~~a~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|||||||
|VCMTX<br>~~aT~~<br>~~a~~|Common-mode Voltage in High Speed<br>Mode<br>~~aT~~<br>~~ee~~|—<br>~~aT~~<br>~~ee~~|150<br>~~aT~~<br>~~ee~~|200<br>~~aT~~<br>~~ee~~|250<br>~~aT~~<br>~~ee~~|mV<br>~~aT~~<br>~~ee~~|
||ΔVCMTX(1,0)|<br>~~a~~<br>~~a ee~~|VCMTXMismatch Between Differential<br>HIGH and LOW<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~|5<br>~~ee~~<br>~~ee~~|mV<br>~~ee~~<br>~~ee~~|
||VOD|<br>~~a ee~~<br>~~a ee~~|Output Differential Voltage<br>~~ee~~<br>~~ee~~||D-PHY-P – D-PHY-<br>N|<br>~~ee~~<br>~~ee~~|140<br>~~ee~~<br>~~ee~~|200<br>~~ee~~<br>~~ee~~|270<br>~~ee~~<br>~~ee~~|mV<br>~~ee~~<br>~~ee~~|
||ΔVOD|<br>~~a ee~~<br>~~Ge~~|VODMismatch Between Differential HIGH<br>and LOW<br>~~ee~~<br>~~Ge~~|—<br>~~ee~~<br>~~Ge~~|—<br>~~ee~~<br>~~Ge~~|—<br>~~ee~~<br>~~Ge~~|14<br>~~ee~~<br>~~Ge~~|mV<br>~~ee~~<br>~~Ge~~|
|VOHHS<br>~~a~~|Single-Ended Output HIGH Voltage<br>~~a~~|—<br>~~a~~|—<br>~~a~~|—<br>~~a~~|360<br>~~a~~|mV<br>~~a~~|
|ZOS<br>~~a~~<br>~~a~~|Single Ended Output Impedance<br>~~a~~<br>~~a~~|—<br>~~a~~<br>~~a~~|40<br>~~a~~<br>~~a~~|50<br>~~a~~<br>~~a~~|68<br>~~a~~<br>~~a~~|Ω<br>~~a~~<br>~~a~~|
|ΔZOS<br>~~a~~<br>~~a~~|ZOSmismatch<br>~~a~~<br>~~a~~|—<br>~~a~~<br>~~a~~|—<br>~~a~~<br>~~a~~|—<br>~~a~~<br>~~a~~|20<br>~~a~~<br>~~a~~|%<br>~~a~~<br>~~a~~|
|**High Speed(Differential) Output AC Specifications**<br>~~a]~~<br>~~a~~<br>~~eeee~~|||||||
|ΔVCMTX(LF)<br>~~a~~|Common-Mode Variation, 50 MHz – 450<br>MHz<br>~~ee~~|—<br>~~ee~~|—|—|25|mVRMS|
|ΔVCMTX(HF)<br>~~a~~<br>~~a~~|Common-Mode Variation, above 450 MHz<br>~~ee ~~|—<br> ~~ee~~|—|—|15|mVRMS|
## **Table 3.41. Hardened D-PHY Output Timing and Levels**
© 2021-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02049-1.8
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**CrossLink-NX Family Data Sheet**
|**Symbol**<br>~~es~~|**Description**|**Conditions**<br>~~a~~|**Min**<br>|**Typ**<br>|**Max**<br>|**Unit**<br>|
|---|---|---|---|---|---|---|
|tR<br>~~es~~|Output 20%–80% Rise Time|0.08 Gbps ≤ tR≤ 1<br>Gbps<br>~~a~~|—<br>|—<br><br>~~ee eee~~|0.30<br><br>~~eee~~|UI<br><br>~~eee~~|
|||1 Gbps < tR≤ 1.5<br>Gbps<br>~~ee~~|—<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee eee~~<br>~~ee~~|0.35<br>~~ee~~<br>~~eee~~|UI<br>~~ee~~<br>~~eee~~|
|||tR≤ 1.5 Gbps<br>~~ee~~|100<br>~~ee~~<br>~~ee~~<br>~~ee~~|—<br>~~ee eee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|—<br>~~eee~~<br>~~ee~~<br>~~ee~~|ps<br>~~eee~~<br>~~ee~~<br>~~ee~~|
|||1.5 Gbps < tR≤ 2.5<br>Gbps<br>~~ee~~|—<br>~~ee ~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|—<br> ~~ee~~<br>~~ee~~<br>~~ee~~<br>~~es~~|0.40<br>~~ee~~<br>~~ee~~|UI<br>~~ee~~<br>~~ee~~|
|||tR> 1.5 Gbps<br>~~ee~~|50<br>~~ee ~~<br>~~ee~~<br>~~ee~~<br>~~eee~~|—<br> ~~ee ~~<br>~~ee~~<br>~~es~~<br>~~ee~~|—<br> ~~ee~~<br>~~ee~~<br>~~ee~~|ps<br>~~ee~~<br>~~ee~~<br>~~ee~~|
|tF|Output 80%–20% Fall Time|0.08 Gbps ≤ tF≤ 1<br>Gbps<br>~~re~~|—<br>~~ee ~~<br>~~re~~<br>~~eee~~<br>~~ee~~|—<br> ~~es~~<br>~~re~~<br>~~ee~~<br>~~ee~~|0.30<br>~~re~~<br>~~ee~~<br>~~ee~~|UI<br>~~re~~<br>~~ee~~<br>~~ee~~|
|||1 Gbps < tF≤ 1.5<br>Gbps<br>~~ee~~|—<br>~~eee ~~<br>~~ee~~<br>~~ee~~<br>~~es~~|—<br> ~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|0.35<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|UI<br>~~ee~~<br>~~ee~~<br>~~ee~~|
|||tF≤ 1.5 Gbps<br>~~es~~<br>~~ee~~|100<br>~~ee ~~<br>~~es~~<br>~~es~~<br>~~ee~~|—<br> ~~ee~~<br>~~es~~<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~es~~<br>~~ee~~<br>~~ee~~|ps<br>~~ee~~<br>~~es~~<br>~~ee~~|
|||1.5 Gbps < tF≤ 2.5<br>Gbps<br>~~ee~~<br>~~ee~~|—<br>~~es ~~<br>~~ee~~<br>~~ee~~|—<br> ~~ee~~<br>~~ee~~<br>~~ee~~|0.40<br>~~ee~~<br>~~ee~~<br>~~ee~~|UI<br>~~ee~~<br>~~ee~~|
|||tF> 1.5 Gbps<br>~~ee~~|50<br>~~ee~~<br>~~es~~|—<br>~~ee~~<br>~~es~~|—<br>~~ee~~|ps<br>~~ee~~|
|**Low Power(Single-Ended) Output DC Specifications**<br>~~ee ee~~<br>~~ee~~<br>~~es~~<br>~~Re~~|||||||
|VOH<br>~~Md~~<br>~~es~~|Low Power Mode Output HIGH Voltage<br>~~Md~~|0.08 Gbps ≤ VOH≤<br>1.50 Gbps<br>~~Md~~|1.1<br>~~Md~~<br>~~ee~~|1.2<br>~~Md~~<br>~~ee~~|1.3<br>~~Md~~|V<br>~~Md~~|
|||VOH> 1.50 Gbps<br>~~Md~~<br>~~ee~~|0.95<br>~~Md~~<br>~~ee~~<br>~~ee~~|—<br>~~Md~~<br>~~ee~~<br>~~ee~~|1.3<br>~~Md~~<br>~~ee~~|V<br>~~Md~~<br>~~ee~~|
|VOL<br>~~es~~<br>~~es~~|Low Power Mode Input LOW Voltage<br>~~en~~|—|–50<br>~~ee~~|—<br>~~ee~~|50|mV|
|ZOLP<br>~~es~~<br>~~es~~|Output Impedance in Low Power Mode<br>~~en~~|—|106<br>~~ee ~~|—<br> ~~ee~~|—|Ω|
|**Low Power(Single-Ended) Output AC Specifications**<br>~~esen~~<br>~~Ct~~<br>~~es~~|||||||
|tRLP<br>~~Ct~~<br>~~es~~<br>~~es~~|15%–85% Rise Time<br>~~Ct~~<br>~~es~~|—<br>~~Ct~~<br>~~es~~|—<br>~~Ct~~<br>~~es~~|—<br>~~Ct~~<br>~~es~~|25<br>~~Ct~~<br>~~es~~|ns<br>~~Ct~~<br>~~es~~|
|tFLP<br>~~es~~<br>~~es~~<br>~~a~~|85%–15% Fall Time<br>~~es~~<br>~~ee~~|—<br>~~es~~<br>~~ee~~|—<br>~~es~~<br>~~ee~~|—<br>~~es~~|25<br>~~es~~|ns<br>~~es~~|
|tREOT<br>~~es~~<br>~~a~~<br>~~Pf~~|HS – LP Mode Rise and Fall Time, 30%–<br>85%<br>~~es~~<br>~~ee~~<br>~~Pf~~<br>~~EE~~|—<br>~~es~~<br>~~ee~~<br>~~EE~~|—<br>~~es~~<br>~~ee~~<br>~~EE~~|—<br>~~es~~|35<br>~~es~~|ns<br>~~es~~|
|TLP-PULSE-TX<br>~~a~~<br>~~Pf~~<br>~~es~~|Pulse Width of the LP Exclusive-OR Clock<br>~~ee~~<br>~~Pf~~<br>~~EE~~<br>~~ee~~|First LP XOR Clock<br>Pulse after STOP<br>State or Last Pulse<br>before STOP State<br>~~ee~~<br>~~EE~~|40<br>~~ee~~<br>~~EE~~|—|—|ns|
|||All Other Pulses<br>~~EE~~|20<br>~~EE~~|—|—|ns|
|TLP-PER-TX<br>~~Pf~~<br>~~es~~|Period of the LP Exclusive-OR Clock<br>~~Pf~~<br>~~EE~~<br>~~ee~~|—<br>~~EE~~|90<br>~~EE~~|—|—|ns|
|δV/δtSR<br>~~es~~<br>~~a~~<br>~~eee.)~~<br>~~es~~|Slew Rate @ CLOAD= 0pF<br>~~ee~~<br>~~a~~<br>~~a~~<br>~~eee.)~~|—<br>~~eee.)~~|—<br>~~eee.)~~|—<br>~~eee.)~~|500<br>~~eee.)~~|mV/ns<br>~~eee.)~~|
||Slew Rate @ CLOAD= 5pF<br>~~a~~<br>~~eee.)~~|—<br>~~eee.)~~|—<br>~~eee.)~~|—<br>~~eee.)~~|300<br>~~eee.)~~|mV/ns<br>~~eee.)~~|
||Slew Rate @ CLOAD= 20pF<br>~~a~~<br>~~a~~<br>~~eee.)~~|—<br>~~eee.)~~|—<br>~~eee.)~~|—<br>~~eee.)~~|250<br>~~eee.)~~|mV/ns<br>~~eee.)~~|
||Slew Rate @ CLOAD= 70pF<br>~~a~~<br>~~a~~<br>~~eee.)~~|—<br>~~ee~~<br>~~eee.)~~|—<br>~~ee~~<br>~~eee.)~~|—<br>~~ee~~<br>~~eee.)~~|150<br>~~ee~~<br>~~eee.)~~|mV/ns<br>~~ee~~<br>~~eee.)~~|
||Slew Rate @ CLOAD= 0 to 70 pF (Falling<br>Edge Only)<br>~~a~~<br>~~ee~~<br>~~eee.)~~|—<br>~~ee~~<br>~~ee~~<br>~~eee.)~~|30<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~eee.)~~|—<br>~~ee~~<br>~~ee~~<br>~~eee.)~~|—<br>~~ee~~<br>~~ee~~<br>~~eee.)~~|mV/ns<br>~~ee~~<br>~~ee~~<br>~~eee.)~~|
|||—<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~eee~~<br>~~eee.)~~|25<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~eee.)~~|—<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~eee.)~~|—<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~eee.)~~|mV/ns<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~eee.)~~|
||Slew Rate @ CLOAD= 0 to 70 pF (Rising<br>Edge Only)<br>~~ee~~<br>~~eee.)~~|—<br>~~ee ~~<br>~~ee~~<br>~~eee~~<br>~~eee.)~~|30<br> ~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~eee.)~~|—<br>~~ee~~<br>~~ee~~<br>~~eee.)~~|—<br>~~ee~~<br>~~ee~~<br>~~eee.)~~|mV/ns<br>~~ee~~<br>~~ee~~<br>~~eee.)~~|
|||—<br>~~ee~~<br>~~eee~~<br>~~es~~<br>~~eee.)~~|25<br>~~ee~~<br>~~ee~~<br>~~es~~<br>~~ee~~<br>~~eee.)~~|—<br>~~ee~~<br>~~es~~<br>~~eee.)~~|—<br>~~ee~~<br>~~es~~<br>~~eee.)~~|mV/ns<br>~~ee~~<br>~~es~~<br>~~eee.)~~|
||Slew Rate @ CLOAD= 0 to 70 pF (Rising<br>Edge Only)<br>~~ee~~<br>~~eee.)~~<br>~~ee~~|—<br>~~ee~~<br>~~eee ~~<br>~~es~~<br>~~eee.)~~|30 - 0.075 ×<br>(VO,INST- 700)<br>~~ee~~<br> ~~ee~~<br>~~es~~<br>~~ee~~<br>~~eee.)~~|—<br>~~ee~~<br>~~es~~<br>~~eee.)~~|—<br>~~ee~~<br>~~es~~<br>~~eee.)~~|mV/ns<br>~~ee~~<br>~~es~~<br>~~eee.)~~|
|||—<br>~~eee.)~~<br>~~a~~|25 - 0.0625 ×<br>(VO,INST- 550)<br>~~eee.)~~|—<br>~~eee.)~~|—<br>~~eee.)~~|mV/ns<br>~~eee.)~~|
|CLOAD<br>~~eee.)~~<br>~~es~~|Load Capacitance<br>~~eee.)~~<br>~~ee~~|—<br>~~eee.)~~<br>~~a~~|0<br>~~eee.)~~|—<br>~~eee.)~~|70<br>~~eee.)~~|pF<br>~~eee.)~~|
© 2021-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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**CrossLink-NX Family Data Sheet**
**Table 3.42. Hardened D-PHY Pin Characteristic Specifications**
|**Symbol**|**Description**|**Conditions**|**Min**|**Typ**|**Max**|**Unit**|
|---|---|---|---|---|---|---|
|**Pin Characteristic Specifications**<br>~~Pe~~|||||||
|VPIN<br>~~Poe~~<br>~~ee~~<br>~~ee~~|Pin Signal Voltage Range<br>~~Poe~~<br>~~DS~~|—<br>~~Poe~~<br>~~DS~~|–50<br>~~Poe~~<br>~~DS~~|—<br>~~Poe~~<br>~~DS~~<br>~~I~~|1350<br>~~Poe~~<br>~~DS~~<br>~~I~~|mV<br>~~Poe~~<br>~~DS~~|
|VPIN_LVLP<br>~~ee~~<br>~~ee~~<br>~~ee~~|Pin Signal Voltage Range in LVLP Operation<br>~~DS~~<br>~~nD~~|—<br>~~DS~~<br>~~DD~~|–50<br>~~DS~~<br>~~DD~~|—<br>~~DS~~<br>~~I~~<br>~~I~~|1150<br>~~DS~~<br>~~I~~|mV<br>~~DS~~|
|ILEAK<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|Pin Leakage Current<br>~~DS~~<br>~~nD~~<br>~~nD I~~<br>|—<br>~~DS~~<br>~~DD~~<br>~~I~~<br>|–100<br>~~DS~~<br>~~DD~~<br>~~SD~~<br>|—<br>~~DS~~<br>~~I~~<br>~~I~~<br>~~I~~<br>|100<br>~~DS~~<br>~~I~~<br>|µA<br>~~DS~~<br>|
|VGNDSH<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~a~~|Ground Shift<br>~~nD~~<br>~~nD I~~<br>~~ee~~|—<br>~~DD~~<br>~~I~~<br><br>~~In~~|–50<br>~~DD~~<br>~~SD~~<br><br>~~UD I~~|—<br>~~I ~~<br>~~I~~<br>~~I~~<br><br>~~I~~|50<br> ~~I~~<br>|mV<br>|
|VPIN(absmax)<br>~~ee~~<br>~~ee~~<br>~~a~~|Transient Pin Voltage Level<br>~~nD~~<br>~~nD I~~<br>~~eerrrnrrD~~<br>~~ee~~|—<br>~~DD~~<br>~~I~~<br>~~rrrnrrD~~<br>~~In~~<br>~~ee~~|–0.15<br>~~DD ~~<br>~~SD~~<br>~~rrrnrrD~~<br>~~UD I~~<br>~~ee~~|—<br> ~~I~~<br>~~I~~<br>~~rrrnrrD~~<br>~~I~~<br>~~eee~~|1.45<br>~~rrrnrrD~~<br>~~eee~~|V<br>~~rrrnrrD~~<br>~~eee~~|
|TVPIN(absmax)<br>~~ee ~~<br>~~a~~|Maximum Transient Time above VPIN(max)or<br>below VPIN(min)<br>~~nD I~~<br> ~~ee~~<br>~~ee~~|—<br>~~I~~<br><br>~~In~~<br>~~ee~~|—<br>~~SD ~~<br><br>~~UD I~~<br>~~ee~~|—<br> ~~I~~<br><br>~~I~~<br>~~eee~~|20<br><br>~~eee~~|ns<br><br>~~eee~~|
**Table 3.43. Hardened D-PHY Clock Signal Specification**
|**Symbol**<br>**Description**<br>**Conditions**<br>**Min**<br>**Typ**<br>**Max**|**Unit**|
|---|---|
|**Clock Signal Specification**||
|UI<br>Instantaneous<br>UIINST<br>—<br>—<br>—<br>12.5|ns|
|—<br>–10%<br>—<br>10%|UI|
|UI Variation<br>∆UI||
|—<br>–5%<br>—<br>5%|UI|
|**Table 3.44. Hardened D-PHY Data-Clock Timing Specifications**||
|**Symbol**<br>**Description**<br>**Conditions**<br>**Min**<br>**Typ**<br>**Max**<br>**Unit**<br>**Data-Clock Timing Specifications**<br>TSKEW[TX]<br>Data to Clock Skew<br>0.08 Gbps ≤ TSKEW[TX]<br>≤ 1.00 Gbps<br>–0.15<br>—<br>0.15<br>UIINST<br>1.00 Gbps < TSKEW[TX]<br>≤ 1.50 Gbps<br>–0.20<br>—<br>0.20<br>UIINST<br>TSETUP[RX]<br>Input Data Setup Before CLK<br>0.08 Gbps ≤ TSETUP[RX]<br>≤ 1.00 Gbps<br>0.15<br>—<br>—<br>UI<br>1.00 Gbps < TSETUP[RX]<br>≤ 1.50 Gbps<br>0.20<br>—<br>—<br>UI<br>THOLD[RX]<br>Input Data Hold After CLK<br>0.08 Gbps ≤ THOLD[RX]<br>≤ 1.00 Gbps<br>0.15<br>—<br>—<br>UI<br>1.00 Gbps < THOLD[RX]<br>≤ 1.50 Gbps<br>0.20<br>—<br>—<br>UI<br>FIN_DPHY<br>Input frequencyto Hardened D-PHY PLL<br>—<br>24<br>200<br>MHz<br>TSKEW[TX]<br>Dynamic<br>Dynamic Data to Clock Skew (Tx)<br>> 1.5 Gbps<br>–0.15<br>—<br>0.15<br>UIINST<br>ISI<br>Channel ISI<br>> 1.5 Gbps<br>—<br>—<br>0.20<br>UIINST<br>TSETUP[RX]+<br>THOLD[RX]<br>Dynamic<br>Dynamic Data to Clock Skew Window Rx<br>Tolerance<br>> 1.5 Gbps<br>0.50<br>—<br>—<br>UIINST<br>~~eenD~~<br>~~rn~~<br>~~I~~<br>~~Pee~~<br>~~P|~~<br>~~hd~~<br>~~Kp~~<br>~~a~~<br>~~P|~~<br>~~a~~<br>~~P|~~<br>~~hv~~<br>~~KC~~<br>~~a~~<br>~~eeDt~~<br>~~a ee~~<br>~~es ee ee ee~~<br>~~eses~~||
|© 2021-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed atwww.latticesemi.com/legal.||
|All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.||
**Table 3.44. Hardened D-PHY Data-Clock Timing Specifications**
FPGA-DS-02049-1.8
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**CrossLink-NX Family Data Sheet**
## **3.25. Hardened PCIe Characteristics**
## **3.25.1. PCIe (2.5 Gbps)**
**Table 3.45. PCIe (2.5 Gbps)**
|**Symbol**<br>~~Po~~|**Description**<br>~~ee~~|**Condition**<br>~~ee~~<br>~~ee~~|**Min.**<br>~~ee~~|**Typ. **|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|**Transmitter1**<br>~~Po~~<br>~~ee~~<br>~~ee~~<br>~~es~~<br>~~ns(GO~~|||||||
|UI<br>~~es~~<br>~~es~~|Unit Interval<br>~~ns~~<br>~~rs~~|—<br>~~(GO~~<br>~~(~~|399.88<br>~~(GO~~<br>~~(~~|400<br>~~(GO~~<br>~~(~~|400.12<br>~~(GO~~|ps<br>~~(GO~~|
|BWTX<br>~~es~~<br>~~es~~<br>~~ee~~|Tx PLL bandwidth<br>~~ns~~<br>~~rs~~<br>~~ee~~|—<br>~~(GO~~<br>~~(~~<br>~~es~~|1.5<br>~~(GO~~<br>~~(~~<br>~~es~~|—<br>~~(GO~~<br>~~(~~<br>~~ee~~|22<br>~~(GO~~|MHz<br>~~(GO~~|
|VTX-DIFF-PP<br>~~es~~<br>~~ee~~<br>~~ee~~|Differential p-p Tx voltage<br>swing<br>~~rs~~<br>~~ee~~<br>~~ee~~|—<br>~~(~~<br>~~es~~<br>~~es~~|0.8<br>~~(~~<br>~~es~~<br>~~es~~|—<br>~~(~~<br>~~ee~~<br>~~ee~~|1.2|Vp-p|
|VTX-DIFF-PP-LOW<br>~~ee ~~<br>~~ee~~<br>~~ee~~|Low power differential p-p Tx<br>voltage swing<br> ~~ee~~<br>~~ee~~<br>~~ee~~|—<br>~~es ~~<br>~~es~~<br>~~es~~|0.4<br> ~~es ~~<br>~~es~~<br>~~es~~|—<br> ~~ee~~<br>~~ee~~<br>~~ee~~|1.2|Vp-p|
|VTX-DE-RATIO-3.5dB<br>~~ee ~~<br>~~ee~~<br>~~es~~|Tx de-emphasis level ratio at<br>3.5 dB<br> ~~ee~~<br>~~ee~~<br>~~rns~~|—<br>~~es ~~<br>~~es~~<br>~~nr~~|3<br> ~~es ~~<br>~~es~~<br>~~ts~~|—<br> ~~ee~~<br>~~ee~~|4|dB|
|TTX-RISE-FALL<br>~~ee ~~<br>~~es~~<br>~~SE~~|Transmitter rise and fall time<br> ~~ee~~<br>~~rns~~<br>~~SE~~|—<br>~~es ~~<br>~~nr~~<br>|0.125<br> ~~es ~~<br>~~ts~~<br>|—<br> ~~ee~~<br>|—<br>|UI<br>|
|TTX-EYE<br>~~es~~<br>~~SE~~|Transmitter Eye, including all<br>jitter sources<br>~~rns ~~<br>~~SEEE~~|—<br> ~~nr~~<br>~~EE~~|0.75<br>~~ts~~<br>~~EE~~|—<br>~~EE~~|—<br>~~EE~~|UI<br>~~EE~~|
|TTX-EYE-MEDIAN-to-MAX-<br>JITTER<br>~~SE~~<br>~~a~~|Max. time between jitter<br>median and max deviation<br>from the median<br>~~SEEE~~<br>~~ee~~|—<br>~~EE~~<br>~~es~~|—<br>~~EE~~<br>~~ee~~|—<br>~~EE~~<br>~~ee~~|0.125<br>~~EE~~<br>~~ee~~|UI<br>~~EE~~<br>~~ee~~|
|RLTX-DIFF<br>~~SE~~<br>~~a~~<br>~~a~~|Tx Differential Return Loss,<br>including pkgand silicon<br>~~SEEE~~<br>~~ee~~<br>~~ee~~|—<br>~~EE~~<br>~~es~~<br>~~es~~|10<br>~~EE~~<br>~~ee~~<br>~~ee~~|—<br>~~EE~~<br>~~ee~~<br>~~ee~~|—<br>~~EE~~<br>~~ee~~<br>~~ee~~|dB<br>~~EE~~<br>~~ee~~<br>~~ee~~|
|RLTX-CM<br>~~a~~<br>~~a~~<br>~~es~~|Tx Common Mode Return Loss,<br>including pkgand silicon<br>~~ee~~<br>~~ee~~<br>~~rs~~|50 MHz < freq < 2.5 GHz<br>~~es ~~<br>~~es~~<br>~~(~~|6<br> ~~ee ~~<br>~~ee~~<br>~~(~~|—<br> ~~ee~~<br>~~ee~~<br>~~(~~|—<br>~~ee~~<br>~~ee~~|dB<br>~~ee~~<br>~~ee~~|
|ZTX-DIFF-DC<br>~~a~~<br>~~es~~<br>~~ee~~|DC differential Impedance<br>~~ee~~<br>~~rs~~<br>~~es~~|—<br>~~es ~~<br>~~(~~<br>~~es~~|80<br> ~~ee ~~<br>~~(~~<br>~~es~~|—<br> ~~ee~~<br>~~(~~<br>~~ee~~|120<br>~~ee~~|Ω<br>~~ee~~|
|VTX-CM-AC-P<br>~~es~~<br>~~ee~~<br>~~ee~~|Tx AC peak common mode<br>voltage, RMS<br>~~rs~~<br>~~es~~<br>~~ee~~|—<br>~~(~~<br>~~es~~<br>~~es~~|—<br>~~(~~<br>~~es~~<br>~~es~~|—<br>~~(~~<br>~~ee~~<br>~~ee~~|20|mV,<br>RMS|
|ITX-SHORT<br>~~ee~~<br>~~ee~~<br>~~ee~~|Transmitter short-circuit<br>current<br>~~es~~<br>~~ee~~<br>~~ee~~|—<br>~~es ~~<br>~~es~~<br>~~es~~|—<br> ~~es ~~<br>~~es~~<br>~~es~~|—<br> ~~ee~~<br>~~ee~~<br>~~ee~~|90|mA|
|VTX-DC-CM<br>~~ee~~<br>~~ee~~<br>~~ee~~|Transmitter DC common-mode<br>voltage<br>~~ee ~~<br>~~ee~~<br>~~ee~~|—<br> ~~es ~~<br>~~es~~<br>~~es~~|0<br> ~~es ~~<br>~~es~~<br>~~es~~|—<br> ~~ee~~<br>~~ee~~<br>~~ee~~|1.2|V|
|VTX-IDLE-DIFF-AC-p<br>~~ee~~<br>~~ee~~<br>~~ee~~|Electrical Idle Output peak<br>voltage<br>~~ee ~~<br>~~ee~~<br>~~ee~~|—<br> ~~es ~~<br>~~es~~<br>~~es~~|—<br> ~~es ~~<br>~~es~~<br>~~ee~~|—<br> ~~ee~~<br>~~ee~~<br>~~ee~~|20|mV|
|VTX-RCV-DETECT<br>~~ee~~<br>~~ee~~<br>~~es~~|Voltage change allowed during<br>Receiver Detect<br>~~ee ~~<br>~~ee~~<br>~~rs~~|—<br> ~~es ~~<br>~~es~~|—<br> ~~es ~~<br>~~ee~~|—<br> ~~ee~~<br>~~ee~~|600|mV|
|TTX-IDLE-MIN<br>~~ee~~<br>~~es~~<br>~~ee~~|Min. time in Electrical Idle<br>~~ee~~<br>~~rs~~<br>~~ee~~|—<br>~~es ~~<br>~~es~~|20<br> ~~ee ~~<br>~~es~~|—<br> ~~ee~~<br>~~ee~~|—|ns|
|TTX-IDLE-SET-TO-IDLE<br>~~es~~<br>~~ee~~<br>~~ee~~|Max. time from EI Order Set to<br>valid Electrical Idle<br>~~rs~~<br>~~ee~~<br>~~ee~~|—<br>~~es~~<br>~~es~~|—<br>~~es~~<br>~~es~~|—<br>~~ee~~<br>~~ee~~|8|ns|
|TTX-IDLE-TO-DIFF-DATA<br>~~ee~~<br>~~ee~~<br>~~ee~~|Max. time from Electrical Idle<br>to valid differential output<br>~~ee ~~<br>~~ee~~<br>~~ee~~|—<br> ~~es ~~<br>~~es~~<br>~~es~~|—<br> ~~es ~~<br>~~es~~<br>~~es~~|—<br> ~~ee~~<br>~~ee~~<br>~~ee~~|8<br>~~ee~~|ns|
|LTX-SKEW<br>~~ee~~<br>~~ee~~|Lane-to-Lane output skew<br>~~ee ~~<br>~~ee~~|—<br> ~~es ~~<br>~~es~~|—<br> ~~es ~~<br>~~es~~|—<br> ~~ee~~<br>~~ee~~|500 ps<br>+ 2 UI<br>~~ee~~|ps|
|**Receiver2**<br>~~ee ee es es ee ee~~<br>~~es~~<br>~~rsnn~~<br>~~I~~<br>~~I~~|||||||
|UI<br>~~es~~<br>~~ae~~|Unit Interval<br>~~rs~~<br>~~ee~~|—<br>~~nn~~<br>~~es~~|399.88<br>~~I~~<br>~~ee~~|400<br>~~ee~~|400.12<br>~~I~~|ps|
|VRX-DIFF-PP<br>~~es~~<br>~~ae~~<br>~~es~~|Differential Rx peak-peak<br>voltage<br>~~rs ~~<br>~~ee~~<br>~~es~~|—<br> ~~nn~~<br>~~es~~|0.175<br>~~I~~<br>~~ee~~|—<br>~~ee~~|1.2<br>~~I~~|Vp-p|
|TRX-EYE3<br>~~ae~~<br>~~es~~|Receiver eye openingtime<br>~~ee~~<br>~~es~~|—<br>~~es ~~|0.4<br> ~~ee~~|—<br>~~ee~~|—|UI|
|TRX-EYE-MEDIAN-to-MAX-<br>JITTER3<br>~~es~~<br>~~a~~|Max time delta between<br>median and deviation from<br>median<br>~~es~~<br>~~ee~~|—<br>~~ee~~|—|—<br>~~ee~~|0.3<br>~~ee~~|UI<br>~~ee~~|
|RLRX-DIFF<br>~~es~~<br>~~a~~|Receiver differential Return<br>Loss,packageplus silicon<br>~~es~~<br>~~ee~~|—<br>~~ee~~|10|—<br>~~ee~~|—<br>~~ee~~|dB<br>~~ee~~|
© 2021-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
90
FPGA-DS-02049-1.8
**CrossLink-NX Family Data Sheet**
|**Symbol**<br>~~Pr~~<br>~~ae~~|**Description**<br>~~eee~~<br>~~ee~~|**Condition**<br>~~eee~~<br>~~et~~<br>~~ee~~|**Min.**<br>~~et~~<br>~~ee~~|**Typ. **|**Max.**<br>~~ee~~|**Unit**<br>~~ee~~|
|---|---|---|---|---|---|---|
|RLRX-CM<br>~~Pr~~<br>~~ae~~<br>~~a~~|Receiver common mode Return<br>Loss,packageplus silicon<br>~~eee~~<br>~~ee~~<br>~~ee~~|—<br>~~eee~~<br>~~et~~<br>~~ee~~<br>~~ee~~|6<br>~~et~~<br>~~ee~~<br>~~ee~~|—|—<br>~~ee~~<br>~~ee~~|dB<br>~~ee~~<br>~~ee~~|
|ZRX-DC<br>~~ae~~<br>~~a~~<br>~~es~~|Receiver DC single ended<br>impedance<br>~~ee~~<br>~~ee~~|—<br>~~ee ~~<br>~~ee~~|40<br> ~~ee~~<br>~~ee~~|—|60<br>~~ee~~<br>~~ee~~|Ω<br>~~ee~~<br>~~ee~~|
|ZRX-DIFF-DC<br>~~a~~<br>~~es~~|Receiver DC differential<br>impedance<br>~~ee~~|—<br>~~ee ~~|80<br> ~~ee~~|—|120<br>~~ee~~|Ω<br>~~ee~~|
|ZRX-HIGH-IMP-DC<br>~~es~~<br>~~ae~~|Receiver DC single ended<br>impedance when powered<br>down<br>~~ee~~|—<br>~~ee~~|200k|—<br>~~ee~~|—<br>~~ee~~|Ω<br>~~ee~~|
|VRX-CM-AC-P3<br>~~es~~<br>~~ae~~<br>~~es~~|Rx AC peak common mode<br>voltage<br>~~ee~~<br>~~rs~~|—<br>~~ee~~|—|—<br>~~ee~~<br>~~(~~|150<br>~~ee~~|mV,<br>peak<br>~~ee~~|
|VRX-IDLE-DET-DIFF-PP<br>~~ae~~<br>~~es~~|Electrical Idle Detect Threshold<br>~~ee ~~<br>~~rs~~|—<br> ~~ee~~|65|—<br>~~ee~~<br>~~(~~|175<br>~~ee~~|mVp-p<br>~~ee~~|
|LRX-SKEW<br>~~es~~<br>~~Pe~~|Receiver –lane-lane skew<br>~~rs~~<br>~~Pe~~|—<br>~~Pe~~|~~Pe~~|—<br>~~(~~<br>~~Pe~~|20<br>~~Pe~~|ps<br>~~Pe~~|
## **Notes:**
1. Refer to PCI Express Base Specification Revision 3.0 Table 4.18 test condition and requirement for respective parameters.
2. Refer to PCI Express Base Specification Revision 3.0 Table 4.24 test condition and requirement for respective parameters.
3. Spec compliant requirement
## **3.25.2. PCIe (5 Gbps)**
**Table 3.46. PCIe (5 Gbps)**
|**Symbol**<br>~~Pr~~|**Description**<br>~~ee~~|**Test Conditions**<br>~~ee~~<br>~~ee~~|**Min**<br>~~ee~~|**Typ**|**Max**|**Unit**|
|---|---|---|---|---|---|---|
|**Transmit1**<br>~~Pr~~<br>~~ee~~<br>~~ee~~<br>~~Ree~~<br>~~esnDnn~~<br>~~GDII~~|||||||
|UI<br>~~es~~<br>~~a~~|Unit Interval<br>~~nD~~<br>~~ee~~|—<br>~~nn~~<br>~~ee~~|199.94<br>~~GD~~<br>~~ee~~|200<br>~~I~~<br>~~ee~~|200.06<br>~~I~~<br>~~ee~~|ps<br>~~ee~~|
|BWTX-PKG-PLL1<br>~~es ~~<br>~~a~~<br>~~a~~|Tx PLL bandwidth<br>correspondingto PKGTX-PLL1<br> ~~nD ~~<br>~~ee~~<br>~~ee~~|—<br> ~~nn~~<br>~~ee~~<br>~~ee~~|8<br>~~GD ~~<br>~~ee~~<br>~~ee~~|—<br> ~~I ~~<br>~~ee~~|16<br> ~~I~~<br>~~ee~~<br>~~ee~~|MHz<br>~~ee~~<br>~~ee~~|
|BWTX-PKG-PLL2<br>~~a~~<br>~~a~~<br>~~a~~|Tx PLL bandwidth<br>correspondingto PKGTX-PLL2<br>~~ee~~<br>~~ee~~<br>~~ee~~|—<br>~~ee ~~<br>~~ee~~<br>~~ee~~|5<br> ~~ee ~~<br>~~ee~~|—<br> ~~ee~~<br>~~ee~~|16<br>~~ee~~<br>~~ee~~<br>~~ee~~|MHz<br>~~ee~~<br>~~ee~~<br>~~ee~~|
|PKGTX-PLL1<br>~~a~~<br>~~a~~<br>~~a~~|Tx PLL Peaking<br>correspondingto PKGTX-PLL1<br>~~ee~~<br>~~ee~~<br>~~ee ee~~|—<br>~~ee ~~<br>~~ee~~<br>~~ee~~|—<br> ~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~|3<br>~~ee~~<br>~~ee~~<br>~~ee~~|dB<br>~~ee~~<br>~~ee~~<br>~~ee~~|
|PKGTX-PLL2<br>~~a~~<br>~~a~~<br>~~a~~|Tx PLL Peaking<br>correspondingto PKGTX-PLL2<br>~~ee~~<br>~~ee ee~~<br>|—<br>~~ee~~<br>~~ee~~<br>|—<br>~~ee~~<br>~~ee~~<br>|—<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>|1<br>~~ee~~<br>~~ee~~<br>~~eee~~<br>|dB<br>~~ee~~<br>~~ee~~<br>~~eee~~<br>|
|VTX-DIFF-PP<br>~~a ~~<br>~~aee~~<br>~~a~~<br>~~a~~|Differential p-p Tx voltage<br>swing<br> ~~ee ee~~<br>~~ee~~<br><br>|—<br>~~ee ~~<br>~~ee~~<br><br>|0.8<br> ~~ee ~~<br>~~ee~~<br>~~ee~~<br><br>~~ee~~<br>|—<br> ~~ee ~~<br>~~ee~~<br>~~ee~~<br><br>~~ee~~<br>|1.2<br> ~~ee~~<br>~~ee~~<br>~~eee~~<br><br>~~eee~~<br>|V, p-p<br>~~ee~~<br>~~ee~~<br>~~eee~~<br><br>~~eee~~<br>|
|VTX-DIFF-PP-LOW<br>~~a ee~~<br>~~aee~~<br>~~a~~<br>~~a~~|Low power differential p-p Tx<br>voltage swing<br>~~ee~~<br>~~ee~~<br><br>|—<br>~~ee~~<br>~~ee~~<br><br>|0.4<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br><br>~~ee~~<br>|—<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br><br>~~ee~~<br>|1.2<br>~~ee~~<br>~~eee~~<br>~~ee~~<br>~~eee~~<br><br>~~eee~~<br>|V, p-p<br>~~ee~~<br>~~eee~~<br>~~ee~~<br>~~eee~~<br><br>~~eee~~<br>|
|VTX-DE-RATIO-3.5dB<br>~~a ee~~<br>~~aee~~<br>~~a~~<br>~~ee~~|Tx de-emphasis level ratio at<br>3.5 dB<br>~~ee~~<br>~~ee~~<br><br>|—<br>~~ee~~<br>~~ee~~<br>|3<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br><br>~~ee~~|—<br>~~ee ~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br><br>~~ee~~|4<br> ~~eee~~<br>~~ee~~<br>~~eee~~<br>~~ee~~<br>~~eee~~<br><br>~~eee~~|dB<br>~~eee~~<br>~~ee~~<br>~~eee~~<br>~~ee~~<br>~~eee~~<br><br>~~eee~~|
|VTX-DE-RATIO-6dB<br>~~a ee~~<br>~~aee~~<br>~~ee~~<br>~~es~~|Tx de-emphasis level ratio at<br>6 dB<br>~~ee~~<br>~~ee~~<br>~~nD~~|—<br>~~ee~~<br>~~ee~~|5.5<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|—<br>~~ee ~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|6.5<br> ~~eee~~<br>~~ee~~<br>~~eee~~<br>~~ee~~<br>~~eee~~|dB<br>~~eee~~<br>~~ee~~<br>~~eee~~<br>~~ee~~<br>~~eee~~|
|TMIN-PULSE<br>~~a ee~~<br>~~ee~~<br>~~es~~<br>~~a~~|Instantaneous lonepulse width<br>~~ee~~<br>~~nD~~<br>~~nD~~|—<br>~~ee~~<br>~~Gs~~|0.9<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~Gs~~|—<br>~~ee ~~<br>~~ee~~<br>~~ee~~<br>~~I~~|—<br> ~~eee~~<br>~~ee~~<br>~~eee~~<br>~~I~~|UI<br>~~eee~~<br>~~ee~~<br>~~eee~~|
|TTX-RISE-FALL<br>~~ee ~~<br>~~es~~<br>~~a~~<br>~~a~~|Transmitter rise and fall time<br> ~~nD~~<br>~~nD~~<br>~~ee~~|—<br>~~Gs~~<br>~~ee~~|0.15<br>~~ee~~<br>~~Gs~~<br>~~ee~~|—<br>~~ee ~~<br>~~I~~<br>~~ee~~|—<br> ~~eee~~<br>~~I~~<br>~~ee~~|UI<br>~~eee~~<br>~~ee~~|
|TTX-EYE<br> <br>~~es~~<br>~~a~~<br>~~a~~<br>~~a~~|Transmitter Eye, including all<br>jitter sources<br> ~~nD~~<br>~~nD~~<br>~~ee~~<br>~~ee~~|—<br>~~Gs~~<br>~~ee~~<br>~~ee~~|0.75<br>~~Gs~~<br>~~ee~~<br>~~ee~~|—<br>~~I~~<br>~~ee~~<br>~~ee~~|—<br>~~I~~<br>~~ee~~<br>~~ee~~|UI<br>~~ee~~<br>~~ee~~|
|TTX-DJ<br>~~a~~<br>~~a~~<br>~~a~~<br>~~es~~|Tx deterministic jitter > 1.5<br>MHz<br>~~nD~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|—<br>~~Gs~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|—<br>~~Gs ~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|—<br> ~~I ~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|0.15<br> ~~I~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|UI<br>~~ee~~<br>~~ee~~<br>~~ee~~|
|TTX-RJ<br>~~a~~<br>~~a~~<br>~~es~~|Tx RMS jitter < 1.5 MHz<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ns~~|—<br>~~ee ~~<br>~~ee~~<br>~~ee~~<br>~~rs~~|—<br> ~~ee ~~<br>~~ee~~<br>~~ee~~|—<br> ~~ee ~~<br>~~ee~~<br>~~ee~~|3<br> ~~ee~~<br>~~ee~~<br>~~ee~~|ps,<br>RMS<br>~~ee~~<br>~~ee~~<br>~~ee~~|
|TRF-MISMATCH<br>~~a~~<br>~~es~~<br>~~Pf~~|Tx rise/fall time mismatch<br>~~ee~~<br>~~ee~~<br>~~ns~~<br>~~Pf~~|—<br>~~ee ~~<br>~~ee~~<br>~~rs~~<br>~~ff}~~|—<br> ~~ee ~~<br>~~ee~~<br>~~ff}~~|—<br> ~~ee ~~<br>~~ee~~<br>~~ff}~~|0.1<br> ~~ee~~<br>~~ee~~<br>~~ff}~~<br>~~+~~|UI<br>~~ee~~<br>~~ee~~<br>~~—~~|
|RLTX-DIFF<br>~~es~~<br>~~Pf~~|Tx Differential Return Loss,<br>including package and silicon<br>~~ee~~<br>~~ns~~<br>~~Pf~~<br>~~es~~|50 MHz < freq< 1.25 GHz<br>~~ee ~~<br>~~rs~~<br>~~ff}~~|10<br> ~~ee ~~<br>~~ff}~~<br>~~ee~~|—<br> ~~ee ~~<br>~~ff}~~|—<br> ~~ee~~<br>~~ff}~~<br>~~+~~|dB<br>~~ee~~<br>~~—~~|
|||1.25 GHz < freq< 2.5 GHz<br>~~ff}~~<br>~~es~~|8<br>~~ff}~~<br>~~es~~<br>~~ee~~|—<br>~~ff}~~<br>~~es~~|—<br>~~ff}~~<br>~~+~~<br>~~es~~|dB<br>~~—~~<br>~~es~~|
© 2021-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02049-1.8
91
**CrossLink-NX Family Data Sheet**
|**Symbol**<br>~~Pr~~<br>~~a~~|**Description**<br>~~ee~~<br>~~ee~~|**Test Conditions**<br>~~ee~~<br>~~ee~~<br>~~ee~~|**Min**<br>~~ee~~<br>~~ee~~|**Typ**<br>~~es~~|**Max**<br>~~ee~~|**Unit**<br>~~ee~~|
|---|---|---|---|---|---|---|
|RLTX-CM<br>~~Pr~~<br>~~a~~<br>~~es~~<br>~~ee~~|Tx Common Mode Return Loss,<br>including package and silicon<br>~~ee~~<br>~~ee~~<br>~~SD~~<br>|50 MHz < freq < 2.5 GHz<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~SD~~<br>~~rs~~<br>|6<br>~~ee~~<br>~~ee~~<br>~~SD~~<br>~~GD~~<br>|—<br>~~es~~<br>~~SD~~<br>~~I~~<br>|—<br>~~ee~~<br>~~SD~~<br>~~I~~|dB<br>~~ee~~<br>~~SD~~|
|ZTX-DIFF-DC<br>~~a~~<br>~~es~~<br>~~ee ee~~<br>~~a~~|DC differential Impedance<br>~~ee ~~<br>~~SD~~<br>~~ee~~|—<br> ~~ee ~~<br>~~SD~~<br>~~rs~~<br>~~ee~~|—<br> ~~ee ~~<br>~~SD~~<br>~~GD~~<br>~~es~~|—<br> ~~es~~<br>~~SD~~<br>~~I~~<br>~~es~~|120<br>~~ee~~<br>~~SD~~<br>~~I~~|Ω<br>~~ee~~<br>~~SD~~|
|VTX-CM-AC-PP<br>~~es~~<br>~~ee ee~~<br>~~a~~<br>~~a~~|Tx AC peak common mode<br>voltage, peak-peak<br>~~SD~~<br>~~ee~~<br>~~ee ee~~|—<br>~~SD~~<br>~~rs~~<br>~~ee~~<br>~~ee~~|—<br>~~SD~~<br>~~GD~~<br>~~es~~<br>~~ee~~|—<br>~~SD~~<br>~~I~~<br>~~es~~<br>~~ee~~|150<br>~~SD~~<br>~~I~~<br>~~eee~~|mV,<br>p-p<br>~~SD~~<br>~~eee~~|
|ITX-SHORT<br>~~ee ee~~<br>~~a~~<br>~~a~~<br>~~a~~|Transmitter short-circuit<br>current<br>~~ee ~~<br>~~ee ee~~<br>~~ee ee~~|—<br>~~rs~~<br> ~~ee ~~<br>~~ee~~<br>~~ee~~|—<br>~~GD ~~<br> ~~es ~~<br>~~ee~~<br>~~ee~~|—<br> ~~I ~~<br> ~~es~~<br>~~ee~~<br>~~ee~~|90<br> ~~I~~<br>~~eee~~<br>~~eee~~|mA<br>~~eee~~<br>~~eee~~|
|VTX-DC-CM<br>~~a~~<br>~~a~~<br>~~a~~|Transmitter DC common-mode<br>voltage<br>~~ee ee~~<br>~~ee ee~~<br>~~ee ee~~|—<br>~~ee ~~<br>~~ee~~<br>~~ee~~|0<br> ~~ee ~~<br>~~ee~~<br>~~ee~~|—<br> ~~ee ~~<br>~~ee~~<br>~~ee~~|1.2<br> ~~eee~~<br>~~eee~~<br>~~eee~~|V<br>~~eee~~<br>~~eee~~<br>~~eee~~|
|VTX-IDLE-DIFF-DC<br>~~a~~<br>~~a~~<br>~~a~~|Electrical Idle Output DC<br>voltage<br>~~ee ee~~<br>~~ee ee~~<br>~~ee ee~~|—<br>~~ee ~~<br>~~ee~~<br>~~ee~~|0<br> ~~ee ~~<br>~~ee~~<br>~~ee~~|—<br> ~~ee ~~<br>~~ee~~<br>~~ee~~|5<br> ~~eee~~<br>~~eee~~<br>~~eee~~|mV<br>~~eee~~<br>~~eee~~<br>~~eee~~|
|VTX-IDLE-DIFF-AC-p<br>~~a~~<br>~~a~~<br>~~es~~|Electrical Idle Differential<br>Outputpeak voltage<br>~~ee ee~~<br>~~ee ee~~<br>~~ee~~|—<br>~~ee ~~<br>~~ee~~<br>~~ee~~|—<br> ~~ee ~~<br>~~ee~~<br>~~ee~~|—<br> ~~ee ~~<br>~~ee~~<br>~~ee~~|20<br> ~~eee~~<br>~~eee~~<br>~~ee~~|mV<br>~~eee~~<br>~~eee~~<br>~~ee~~|
|VTX-RCV-DETECT<br>~~a~~<br>~~es~~<br>~~a~~|Voltage change allowed during<br>Receiver Detect<br>~~ee ee~~<br>~~ee~~<br>~~nD~~|—<br>~~ee ~~<br>~~ee~~<br>~~RI~~|—<br> ~~ee ~~<br>~~ee~~<br>~~IS~~|—<br> ~~ee ~~<br>~~ee~~<br>~~I~~|600<br> ~~eee~~<br>~~ee~~<br>~~I~~|mV<br>~~eee~~<br>~~ee~~|
|TTX-IDLE-MIN<br>~~es~~<br>~~a~~<br>~~a~~|Min. time in Electrical Idle<br>~~ee~~<br>~~nD~~<br>~~ee e~~<br>|—<br>~~ee~~<br>~~RI~~<br>~~e~~~~**e**~~<br>|20<br>~~ee~~<br>~~IS~~<br>~~**ee**~~|—<br>~~ee~~<br>~~I~~<br>~~ee~~|—<br>~~ee~~<br>~~I~~<br>~~**e**ee~~|ns<br>~~ee~~<br>~~ee~~|
|TTX-IDLE-SET-TO-IDLE<br>~~es~~<br>~~a~~<br>~~a~~|Max. time from EI Order Set to<br>valid Electrical Idle<br>~~ee~~<br>~~nD~~<br>~~ee e~~<br>~~ee~~|—<br>~~ee ~~<br>~~RI~~<br>~~e~~~~**e**~~<br>~~e~~|—<br> ~~ee ~~<br>~~IS ~~<br>~~**ee**~~|—<br> ~~ee~~<br> ~~I ~~<br>~~ee~~<br>~~ee~~|8<br>~~ee~~<br> ~~I~~<br>~~**e**ee~~|ns<br>~~ee~~<br>~~ee~~<br>~~e~~|
|TTX-IDLE-TO-DIFF-DATA<br>~~a ~~|Max. time from Electrical Idle<br>to valid differential output<br>~~ee e~~<br> ~~ee~~|—<br>~~e~~~~**e** ~~<br>~~e~~|—<br> ~~**ee** ~~|—<br> ~~ee ~~<br>~~ee~~|8<br> ~~**e**ee~~|ns<br>~~ee~~<br>~~e~~|
|**Receive2**<br> ~~ee e~~<br>~~ee~~<br>~~e~~<br>~~eee~~<br>~~a~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|||||||
|LTX-SKEW<br>~~eee~~<br>~~a~~<br>~~es~~|Lane-to-Lane output skew<br>~~eee~~<br>~~ee~~<br>~~nD~~|—<br>~~eee~~<br>~~ee~~<br>~~I~~|—<br>~~eee~~<br>~~ee~~<br>~~I~~|—<br>~~eee~~<br>~~ee~~<br>~~I~~|500 + 4<br>UI<br>~~eee~~<br>~~ee~~|ps<br>~~eee~~<br>~~ee~~|
|UI<br>~~a~~<br>~~es~~<br>~~ae~~|Unit Interval<br>~~ee~~<br>~~nD~~<br>~~ee~~|—<br>~~ee~~<br>~~I~~<br>~~ee~~|199.94<br>~~ee~~<br>~~I~~<br>~~ee~~|200<br>~~ee~~<br>~~I~~<br>~~ee~~|200.06<br>~~ee~~<br>~~ee~~|ps<br>~~ee~~<br>~~ee~~|
|VRX-DIFF-PP<br>~~es~~<br>~~ae~~|Differential Rx peak-peak<br>voltage<br>~~nD~~<br>~~ee~~|—<br>~~I~~<br>~~ee~~<br>~~Ge~~|0.343<br>~~I~~<br>~~ee~~<br>~~ee~~|—<br>~~I~~<br>~~ee~~<br>~~ee~~|1.2<br>~~ee~~|V, p-p<br>~~ee~~|
|TRX-RJ-RMS<br>~~ae~~<br>~~ee~~<br>~~pf~~|Receiver random jitter<br>tolerance(RMS)<br>~~ee ~~<br>~~ee~~<br>~~pf~~|1.5 MHz – 100 MHz<br>Random noise<br> ~~ee ~~<br>~~ee~~<br>~~Ge~~<br>~~Ge~~|—<br> ~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|4.2<br>~~ee~~<br>~~ee~~|ps,<br>RMS<br>~~ee~~<br>~~ee~~|
|TRX-DJ<br>~~ee~~<br>~~ee~~<br>~~pf~~<br>~~es~~|Receiver deterministic jitter<br>tolerance<br>~~ee~~<br>~~ee~~<br>~~pf~~<br>|—<br>~~ee~~<br>~~Ge ~~<br>~~ee~~<br>~~Ge~~<br>~~ff~~|—<br>~~ee~~<br> ~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ff~~|—<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~+}~~|88<br>~~ee~~<br>~~ee~~<br>~~+}~~|ps<br>~~ee~~<br>~~ee~~<br>~~+}~~|
|RLRX-DIFF<br>~~ee~~<br>~~pf~~<br>~~es~~<br>~~a~~|Receiver differential Return<br>Loss, package plus silicon<br>~~ee~~<br>~~pf~~<br>~~es~~|50 MHz < freq< 1.25 GHz<br>~~ee~~<br>~~Ge~~<br>~~ff~~|10<br>~~ee~~<br>~~ee~~<br>~~ff~~|—<br>~~ee~~<br>~~ee~~<br>~~+}~~|—<br>~~ee~~<br>~~+}~~|dB<br>~~ee~~<br>~~+}~~|
|||1.25 GHz < freq< 2.5 GHz<br>~~Ge~~<br>~~ff~~|8<br>~~ee~~<br>~~ff~~|—<br>~~ee~~<br>~~+}~~|—<br>~~+}~~|dB<br>~~+}~~|
|RLRX-CM<br>~~pf~~<br>~~es~~<br>~~a~~|Receiver common mode<br>Return Loss, package plus<br>silicon<br>~~pf~~<br>~~es~~|—<br>~~Ge ~~<br>~~ff~~|6<br> ~~ee~~<br>~~ff~~|—<br>~~ee~~<br>~~+}~~|—<br>~~+}~~|dB<br>~~+}~~|
|ZRX-DC<br>~~es ~~<br>~~a~~|Receiver DC single ended<br>impedance<br> ~~es~~|—<br>~~ff~~|40<br>~~ff ~~|—<br> ~~+}~~|60<br>~~+}~~|Ω<br>~~+}~~|
|ZRX-HIGH-IMP-DC<br> <br>~~a~~<br>~~a~~|Receiver DC single ended<br>impedance when powered<br>down<br> ~~es~~<br>~~ee~~|—<br>~~ee~~|200K<br>~~ee~~|—<br>~~ee~~|—<br>~~ee~~|Ω<br>~~ee~~|
|VRX-CM-AC-P3<br> <br>~~a~~<br>~~a~~<br>~~es~~|Rx AC peak common mode<br>voltage<br> ~~es~~<br>~~ee~~<br>~~ee~~|—<br>~~ee~~|—<br>~~ee~~<br>~~(~~|—<br>~~ee~~|150<br>~~ee~~|mV,<br>peak<br>~~ee~~|
|VRX-IDLE-DET-DIFF-PP<br>~~a~~<br>~~es~~<br>~~es~~|Electrical Idle Detect Threshold<br>~~ee~~<br>~~ee~~<br>~~nD~~|—<br>~~ee~~<br>~~I~~|65<br>~~ee~~<br>~~(~~<br>~~IS~~|—<br>~~ee ~~<br>~~I~~|1753<br> ~~ee~~|mv,pp<br>~~ee~~|
|LRX-SKEW<br>~~es ~~<br>~~es~~|Receiver –lane-lane skew<br> ~~ee~~<br>~~nD~~|—<br>~~I~~|—<br>~~(~~<br>~~IS~~|—<br>~~I~~|8|ns|
## **Notes:**
1. Refer to PCI Express Base Specification Revision 3.0 Table 4.18 test condition and requirement for respective parameters.
2. Refer to PCI Express Base Specification Revision 3.0 Table 4.24 test condition and requirement for respective parameters.
3. Spec compliant requirement
© 2021-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
92
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**CrossLink-NX Family Data Sheet**
## **3.26. SGMII Characteristics**
## **3.26.1. SGMII Specifications**
**Table 3.47. SGMII**
|**Symbol**|**Description**|**Test Conditions**|**Min**|**Typ**|**Max**|**Unit**|
|---|---|---|---|---|---|---|
|fDATA|SGMII Data Rate|—|—|1250|—|MHz|
|fREFCLK|SGMII Reference Clock Frequency (Data<br>Rate / 10)|—|—|125|—|MHz|
|JTOL_Dj|Jitter Tolerance, Deterministic|Periodic jitter<br>< 300 kHz|—|—|0.11|UI|
|JTOL_Tj|Jitter Tolerance, Total|Periodic jitter<br>< 300 kHz|—|—|0.31|UI|
|Δf/f|Data Rate and Reference Clock Accuracy|—|–300|—|300|ppm|
## **Notes:**
1. JTOT can meet the following jitter mask specification: 0 to 3.5 kHz: 10 UI; 3.5 to 700 kHz: log-log slope 10 UI to 0.05 UI; above 700 kHz: 0.05 UI.
2. SGMII is not supported on 72-pin packages (QFN and WLCSP).
## **3.27. sysCONFIG Port Timing Specifications**
**Table 3.48. sysCONFIG Port Timing Specifications**
|**Symbol**<br>~~a~~|**Parameter**<br>~~a~~|**Device**<br>~~a~~|**Min**<br>~~a~~|**Typ.**<br>~~a~~|**Max**<br>~~a~~|**Unit**<br>~~a~~|
|---|---|---|---|---|---|---|
|**Master SPI POR/REFRESH Timing**<br>~~a~~<br>~~a~~|||||||
|tICFG|REFRESH command executed, to the rising<br>edge of INITN (bulk-erase off)|—|—|—|30|µs|
|tVMC<br>~~a~~|Time from rising edge of INITN to the valid<br>Master MCLK<br>~~a~~<br>~~ee~~|—<br>~~a~~<br>~~ee~~|—<br>~~a~~<br>~~ee~~|—<br>~~a~~<br>~~ee~~|5<br>~~a~~<br>~~ee~~|µs<br>~~a~~<br>~~ee~~|
|fMCLK_DEF|Default MCLK frequency (Before MCLK<br>frequency selection in bitstream)|—|—|3.5|—|MHz|
|tICFG_POR|frequency selection in bitstream)<br>Time during POR, from VCC, VCCAUX, VCCIO0,<br>or VCCIO1 (whichever is the last) pass POR trip<br>voltage, to the rising edge if INITN|—|—|—|5|ms|
|**Slave SPI/I2C/I3C POR**<br>~~a~~|||||||
|tMSPI_INH<br>~~a~~<br>~~a~~|Time during POR, from VCC, VCCAUX, VCCIO0or<br>VCCIO1(whichever is the last) pass POR trip<br>voltage, to pull PROGRAMN LOW to prevent<br>entering MSPI mode<br>~~a~~<br>~~ee~~<br>|—<br>~~a~~<br>|—<br>~~a~~<br>|—<br>~~a~~<br>|1<br>~~a~~<br>|µs<br>~~a~~<br>|
|tACT_PROGRAMN_H<br>~~a~~<br>~~a~~|Minimum time driving PROGRAMN HIGH after<br>last activation clock<br>~~a~~<br>~~ee~~<br>|—<br>~~a~~<br>|50<br>~~a~~<br>|—<br>~~a~~<br>|—<br>~~a~~<br>|ns<br>~~a~~<br>|
|tCONFIG_CCLK<br>~~a~~<br>~~a~~|Minimum time to start driving CCLK (SSPI)<br>after PROGRAMN HIGH<br>~~a~~<br>~~ee~~<br>~~ee~~|—<br>~~a~~<br>~~ee~~|50<br>~~a~~<br>~~ee~~|—<br>~~a~~<br>~~ee~~|—<br>~~a~~<br>~~ee~~|ns<br>~~a~~<br>~~ee~~|
|tCONFIG_SCL<br>~~a~~|Minimum time to start driving SCL (I2C/I3C)<br>after PROGRAMN HIGH<br>~~a~~<br>~~a~~|—<br>~~a~~<br>~~a~~|50<br>~~a~~<br>~~a~~|—<br>~~a~~<br>~~a~~|—<br>~~a~~<br>~~a~~|ns<br>~~a~~<br>~~a~~|
|**PROGRAMN Configuration Timing**<br>~~a~~|||||||
|tPROGRAMN<br>~~a~~<br>~~a~~|PROGRAMN LOW pulse accepted<br>~~a~~<br>~~a~~|—<br>~~a~~<br>~~a~~|50<br>~~a~~<br>~~a~~|—<br>~~a~~<br>~~a~~|—<br>~~a~~<br>~~a~~|ns<br>~~a~~<br>~~a~~|
|tPROGRAMN_RJ<br>~~a~~|PROGRAMN LOW pulse rejected<br>~~a~~<br>~~a~~|—<br>~~a~~|—<br>~~a~~|—<br>~~a~~|25<br>~~a~~|ns<br>~~a~~|
|tINIT_LOW<br>~~a~~<br>~~a~~|PROGRAMN LOW to INITN LOW<br>~~a~~<br>~~a~~|—<br>~~a~~|—<br>~~a~~|—<br>~~a~~|100<br>~~a~~|ns<br>~~a~~|
© 2021-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02049-1.8
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**CrossLink-NX Family Data Sheet**
|**Symbol**<br>~~es~~|**Parameter**<br>~~G~~|**Device**<br>~~G~~|**Min**<br>~~G~~|**Typ.**<br>~~G~~|**Max**<br>~~G~~|**Unit**<br>~~G~~|
|---|---|---|---|---|---|---|
|tINIT_HIGH<br>~~es~~<br>~~a~~<br>~~es~~|PROGRAMN LOW to INITN HIGH (bulk-erase<br>off)<br>~~G~~<br>~~a~~<br>|LIFCL-40<br>~~G~~<br>~~a~~<br>~~ee~~<br>|—<br>~~G~~<br>~~a~~<br>~~ee~~<br>|30<br>~~G~~<br>~~a~~<br>|—<br>~~G~~<br>~~a~~<br>|µs<br>~~G~~<br>~~a~~<br>|
|||LIFCL-17<br>~~a~~<br>~~ee~~<br>|—<br>~~a~~<br>~~ee~~<br>|30<br>~~a~~<br>|—<br>~~a~~<br>|µs<br>~~a~~<br>|
|tDONE_LOW<br>~~es~~|PROGRAMN LOW to DONE LOW<br>~~G~~|—<br>~~ee~~<br>~~G~~|—<br>~~ee~~<br>~~G~~|—<br>~~G~~|55<br>~~G~~|µs<br>~~G~~|
|tDONE_HIGH2<br>~~es~~<br>~~Ge~~<br>~~es~~|PROGRAMN HIGH to DONE HIGH<br><br>~~Ge~~<br>~~Ge~~|—<br>~~ee ~~<br><br>~~Ge~~<br>~~Ge~~|~~ee~~<br><br>~~Ge~~<br>~~Ge~~|—<br><br>~~Ge~~<br>~~Ge~~|2<br><br>~~Ge~~<br>~~Ge~~|s<br><br>~~Ge~~<br>~~Ge~~|
|tIODISS<br>~~es~~|PROGRAMN LOW to I/O Disabled<br>~~Ge~~|—<br>~~Ge~~|—<br>~~Ge~~|—<br>~~Ge~~|125<br>~~Ge~~|ns<br>~~Ge~~|
|**Master SPI**<br>~~esGe~~<br>~~pe~~|||||||
|fMCLK1<br>~~pe~~<br>~~CO~~|Max selected MCLK output frequency<br>~~pe~~<br>~~CO~~|—<br>~~pe~~<br>~~CO~~|—<br>~~pe~~<br>~~CO~~|150<br>~~pe~~<br>~~CO~~|165<br>~~pe~~<br>~~CO~~|MHz<br>~~pe~~<br>~~CO~~|
|fMCLK_DC<br>~~eG~~|MCLK output clock duty cycle<br>~~eG~~|—<br>~~eG~~|40<br>~~eG~~|—<br>~~eG~~|60<br>~~eG~~|%<br>~~eG~~|
|tMCLKH<br>~~eG~~<br>~~eG~~|MCLK output clock pulse width HIGH<br>~~eG~~<br>~~eG~~|—<br>~~eG~~<br>~~eG~~|3<br>~~eG~~<br>~~eG~~|—<br>~~eG~~<br>~~eG~~|—<br>~~eG~~<br>~~eG~~|ns<br>~~eG~~<br>~~eG~~|
|tMCLKL<br>~~eG~~|MCLK output clock pulse width LOW<br>~~eG~~|—<br>~~eG~~|3<br>~~eG~~|—<br>~~eG~~|—<br>~~eG~~|ns<br>~~eG~~|
|tSU_MSI<br>~~eG~~|MSI to MCLK setup time<br>~~eG~~|—<br>~~eG~~|3<br>~~eG~~|—<br>~~eG~~|—<br>~~eG~~|ns<br>~~eG~~|
|tHD_MSI<br>~~Ge~~<br>~~es~~|MSI to MCLK hold time<br>~~Ge~~<br>~~Ge~~|—<br>~~Ge~~<br>~~Ge~~|0.5<br>~~Ge~~<br>~~Ge~~|—<br>~~Ge~~<br>~~Ge~~|—<br>~~Ge~~<br>~~Ge~~|ns<br>~~Ge~~<br>~~Ge~~|
|tCO_MSO2<br>~~es~~|MCLK to MSO delay<br>~~Ge~~|—<br>~~Ge~~|—<br>~~Ge~~|—<br>~~Ge~~|12<br>~~Ge~~|ns<br>~~Ge~~|
|**Slave SPI**<br>~~esGe~~<br>~~Pe~~|||||||
|fCCLK<br>~~eG~~|CCLK input clock frequency<br>~~eG~~|—<br>~~eG~~|—<br>~~eG~~|—<br>~~eG~~|135<br>~~eG~~|MHz<br>~~eG~~|
|tCCLKH<br>~~eG~~|CCLK input clock pulse width HIGH<br>~~eG~~|—<br>~~eG~~|3.5<br>~~eG~~|—<br>~~eG~~|—<br>~~eG~~|ns<br>~~eG~~|
|tCCLKL<br>~~eG~~|CCLK input clock pulse width LOW<br>~~eG~~|—<br>~~eG~~|3.5<br>~~eG~~|—<br>~~eG~~|—<br>~~eG~~|ns<br>~~eG~~|
|tVMC_SLAVE|Time from rising edge of INITN to Slave CCLK<br>driven|—|50|—|—|ns|
|tVMC_MASTER<br>~~eG~~|CCLK input clock duty cycle<br>~~eG~~|—<br>~~eG~~|40<br>~~eG~~|—<br>~~eG~~|60<br>~~eG~~|%<br>~~eG~~|
|tSU_SSI<br>~~eG~~<br>~~eG~~|SSI to CCLK setup time<br>~~eG~~<br>~~eG~~|—<br>~~eG~~<br>~~eG~~|3.2<br>~~eG~~<br>~~eG~~|—<br>~~eG~~<br>~~eG~~|—<br>~~eG~~<br>~~eG~~|ns<br>~~eG~~<br>~~eG~~|
|tHD_SSI<br>~~eG~~|SSI to CCLK hold time<br>~~eG~~|—<br>~~eG~~|1.9<br>~~eG~~|—<br>~~eG~~|—<br>~~eG~~|ns<br>~~eG~~|
|tCO_SSO<br>~~eG~~<br>~~ee~~|CCLK falling edge to valid SSO output<br>~~eG~~|—<br>~~eG~~|—<br>~~eG~~|—<br>~~eG~~|30<br>~~eG~~|ns<br>~~eG~~|
|tEN_SSO<br>~~ee~~<br>~~es~~|CCLK falling edge to SSO output enabled<br>~~G~~|—<br>~~G~~|—<br>~~G~~|—<br>~~G~~|30<br>~~G~~|ns<br>~~G~~|
|tDIS_SSO<br>~~ee~~<br>~~es~~|CCLK falling edge to SSO output disabled<br>~~G~~|—<br>~~G~~|—<br>~~G~~|—<br>~~G~~|30<br>~~G~~|ns<br>~~G~~|
|tHIGH_SCSN<br>~~es~~<br>~~eG~~|SCSN HIGH time<br>~~G~~<br>~~eG~~|—<br>~~G~~<br>~~eG~~|74<br>~~G~~<br>~~eG~~|—<br>~~G~~<br>~~eG~~|—<br>~~G~~<br>~~eG~~|ns<br>~~G~~<br>~~eG~~|
|tSU_SCSN<br>~~eG~~|SCSN to CCLK setup time<br>~~eG~~|—<br>~~eG~~|3.5<br>~~eG~~|—<br>~~eG~~|—<br>~~eG~~|ns<br>~~eG~~|
|tHD_SCSN<br>~~eG~~<br>~~Ge~~|SCSN to CCLK hold time<br>~~eG~~<br>~~Ge~~|—<br>~~eG~~<br>~~Ge~~|1.6<br>~~eG~~<br>~~Ge~~|—<br>~~eG~~<br>~~Ge~~|—<br>~~eG~~<br>~~Ge~~|ns<br>~~eG~~<br>~~Ge~~|
|**I2C/I3C**<br>~~Pe~~|||||||
|fSCL_I2C<br>~~GO~~|SCL input clock frequency for I2C<br>~~GO~~|—<br>~~GO~~|—<br>~~GO~~|—<br>~~GO~~|1<br>~~GO~~|MHz<br>~~GO~~|
|fSCL_I3C<br>~~GO~~<br>~~Ge~~<br>~~ee~~|SCL input clock frequency for I3C<br>~~GO~~<br>~~Ge~~|—<br>~~GO~~<br>~~Ge~~|—<br>~~GO~~<br>~~Ge~~|—<br>~~GO~~<br>~~Ge~~|12<br>~~GO~~<br>~~Ge~~|MHz<br>~~GO~~<br>~~Ge~~|
|tSCLH_I2C<br>~~ee~~|SCL input clock pulse width HIGH for I2C|—|400|—|—|ns|
|tSCLL_I2C<br>~~ee~~<br>~~eG~~|SCL input clock pulse width LOW for I2C<br>~~eG~~|—<br>~~eG~~|400<br>~~eG~~|—<br>~~eG~~|—<br>~~eG~~|ns<br>~~eG~~|
|tSU_SDA_I2C<br>~~eG~~<br>~~ee~~|SDA to SCL setup time for I2C<br>~~eG~~<br>~~ee~~|—<br>~~eG~~<br>~~ee~~|250<br>~~eG~~<br>~~ee~~|—<br>~~eG~~<br>~~ee~~|—<br>~~eG~~<br>~~ee~~|ns<br>~~eG~~<br>~~ee~~|
|tHD_SDA_I2C<br>~~ee~~<br>~~eG~~|SDA to SCL hold time for I2C<br>~~ee~~<br>~~eG~~|—<br>~~ee~~<br>~~eG~~|50<br>~~ee~~<br>~~eG~~|—<br>~~ee~~<br>~~eG~~|—<br>~~ee~~<br>~~eG~~|ns<br>~~ee~~<br>~~eG~~|
|tSU_SDA_I3C<br>~~eG~~<br>~~eG~~<br>~~es~~|SDA to SCL setup time for I3C<br>~~eG~~<br>~~eG~~|—<br>~~eG~~<br>~~eG~~|30<br>~~eG~~<br>~~eG~~|—<br>~~eG~~<br>~~eG~~|—<br>~~eG~~<br>~~eG~~|ns<br>~~eG~~<br>~~eG~~|
|tHD_SDA_I3C<br>~~es~~|SDA to SCL hold time for I3C|—|30|—|—|ns|
|tCO_SDA<br>~~es~~<br>~~eG~~|SCL falling edge to valid SDA output<br>~~eG~~|—<br>~~eG~~|—<br>~~eG~~|—<br>~~eG~~|200<br>~~eG~~|ns<br>~~eG~~|
|tEN_SDA<br>~~eG~~<br>~~Ge~~|SCL falling edge to SDA output enabled<br>~~eG~~<br>~~Ge~~|—<br>~~eG~~<br>~~Ge~~|—<br>~~eG~~<br>~~Ge~~|—<br>~~eG~~<br>~~Ge~~|200<br>~~eG~~<br>~~Ge~~|ns<br>~~eG~~<br>~~Ge~~|
|tDIS_SDA<br>~~es~~|SCL falling edge to SDA output disabled<br>~~es~~|—<br>~~es~~|—<br>~~es~~|—<br>~~es~~|200<br>~~es~~|ns<br>~~es~~|
|**Wake-Up Timing**<br>~~es~~<br>~~pC~~|||||||
|tWAKEUP_DONE_HIGH2|Last configuration clock cycle to DONE going<br>HIGH|—|—|—|60|µs|
|tFIO_EN2<br>~~a~~|User I/O enabled in Early I/O Mode<br>~~a~~|LIFCL-40<br>~~a~~|—<br>~~a~~|~~a~~|31184<br>~~a~~|cycles<br>~~a~~|
|||LIFCL-17<br>~~a~~<br>~~a~~|—<br>~~a~~<br>~~ee~~|~~a~~<br>~~ee ~~|20688<br>~~a~~<br> ~~ee~~|cycles<br>~~a~~<br>~~ee~~|
|tIOEN2<br>~~ee~~|Config clock to user I/O enabled<br>~~ee~~|—<br>~~ee~~|130<br>~~ee~~|—<br>~~ee~~|—<br>~~ee~~|ns<br>~~ee~~|
© 2021-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
94
FPGA-DS-02049-1.8
**CrossLink-NX Family**
**Data Sheet**
**Symbol Parameter Device Min Typ. Max Unit** tMCLKZ[2, 3] Master MCLK to Hi-Z — — — 2.5 µs ~~ee~~ **Notes** :
1. fMCLK has a dependency on HFOSC and is 1/3 of fCLKHF.
2. Based on 30k uncompressed/unauthenticated/default MCLK timing (3.5 MHz)/x1. Other permutations result in different values. 3. Measure using LVCMOS18, default MCLK frequency, slow slew rate.
**==> picture [441 x 499] intentionally omitted <==**
**----- Start of picture text -----**<br>
REFRESH Command tICFG<br>oo<br>VCC/VCCAUX/<br>VCCIO0/VCCIO1 tICFG_POR<br>INITN AW<br>DONE<br>WL<br>PROGRAMN fMCLK_DEF<br>tVMC<br>MCLK<br>MSI<br>Figure 3.14. Master SPI POR/REFRESH Timing<br>VCC/VCCAUX/<br>VCCIO0/VCCIO1 tICFG_POR<br>REFRESH Command tICFG<br>INITN OX<br>DONE<br>WW tMSPI_INH Slave Activation tACT_CRESETB_N<br>PROGRAMN<br>tACT_CCLK fCCLK tCONFIG_CCLK<br>CCLK<br>SSI<br>tACT_SCL fSCL tACT_CRESETB_N<br>tCONFIG_SCL<br>SCL<br>SDA<br>**----- End of picture text -----**<br>
**Figure 3.15. Slave SPI/I[2] C/I3C POR/REFRESH Timing**
© 2021-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02049-1.8
95
**CrossLink-NX Family Data Sheet**
**==> picture [125 x 11] intentionally omitted <==**
**----- Start of picture text -----**<br>
TN OC<br>**----- End of picture text -----**<br>
**Figure 3.16. Master SPI PROGRAMN Timing**
**Figure 3.17. Slave SPI/I[2] C/I3C PROGRAMN Timing**
© 2021-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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FPGA-DS-02049-1.8
**CrossLink-NX Family Data Sheet**
**==> picture [223 x 109] intentionally omitted <==**
**----- Start of picture text -----**<br>
fMCLK<br>tMCLKH —_><br>< —____—_- tMCLKL<br>MCLK tSU_MISO —_ tHD_MISO<br>MSI<br>tCO_MOSI<br>—_P > | <|—_—<br>MSO<br>**----- End of picture text -----**<br>
**Figure 3.18. Master SPI Configuration Timing**
**==> picture [286 x 190] intentionally omitted <==**
**----- Start of picture text -----**<br>
fCCLK<br>tCCLKH<br>CCLK —_—_ —S/- —><br>tCCLKL<br>tSU_MOSI tHD_MOSI<br>SSI<br>tSU_SCSN tHD_SCSN<br>SCSN<br>tHIGH_SCSN<br>tCO_MISO<br>SSO<br>i Se<br>tEN_MISO tDIS_MISO<br>SSO<br>**----- End of picture text -----**<br>
**Figure 3.19. Slave SPI Configuration Timing**
**==> picture [306 x 149] intentionally omitted <==**
**----- Start of picture text -----**<br>
fSCL<br>tSCLH<br>SCL<br>tSCLL<br>tSU_SDA tHD_SDA<br>SDA (input)<br>tCO_SDA<br>SDA (output)<br>tDIS_SDA<br>tEN_SDA<br>SDA (output)<br>**----- End of picture text -----**<br>
**Figure 3.20. I[2] C /I3C Configuration Timing**
© 2021-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02049-1.8
97
**CrossLink-NX Family Data Sheet**
**==> picture [346 x 417] intentionally omitted <==**
**----- Start of picture text -----**<br>
CRESET_B<br>INITN<br>tWAKEUP_DONE_HIGH Device Wake-Up<br>DONE<br>CONFIG tMWC<br>Starts fMCLK_def fMCLK tMCLKZ<br>MCLK<br>tFIO_EN<br>USER I/O tIOEN<br>(FAST I/O)<br>tIOEN<br>USER I/O<br>Figure 3.21. Master SPI Wake-Up Timing<br>CRESET_B<br>INITN<br>tWAKEUP_DONE_HIGH Device Wake-Up<br>DONE<br>CONFIG<br>Starts<br>CCLK/SCL<br>tFIO_EN<br>USER I/O tIOEN<br>(FAST I/Os)<br>tIOEN<br>‘af<br>USER I/O<br>He e<br>Figure 3.22. Slave SPI/I [2] C/I3C Wake-Up Timing<br>**----- End of picture text -----**<br>
© 2021-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
98
FPGA-DS-02049-1.8
**CrossLink-NX Family Data Sheet**
## **3.28. JTAG Port Timing Specifications**
**Table 3.49. JTAG Port Timing Specifications**
|**Symbol**|**Parameter**|**Min**|**Typ. **|**Max**|**Units**|
|---|---|---|---|---|---|
|fMAX|TCK clock frequency|—|—|25|MHz|
|tBTCPH|TCK clockpulse width high|20|—|—|ns|
|tBTCPL|TCK clockpulse width low|20|—|—|ns|
|tBTS|TCK TAP setuptime|5|—|—|ns|
|tBTH|TCK TAP hold time|5|—|—|ns|
|tBTRF|TAP controller TDO rise/fall time1|100|—|—|mV/ns|
|tBTCO|TAP controller fallingedge of clock to valid output|—|—|14|ns|
|tBTCODIS|TAP controller fallingedge of clock to valid disable|—|—|14|ns|
|tBTCOEN|TAP controller fallingedge of clock to valid enable|—|—|14|ns|
|tBTCRS|BSCAN test capture register setuptime|8|—|—|ns|
|tBTCRH|BSCAN test capture register hold time|25|—|—|ns|
|tBUTCO|BSCAN test update register, fallingedge of clock to valid output|—|—|25|ns|
|tBTUODIS|BSCAN test update register, fallingedge of clock to valid disable|—|—|25|ns|
|tBTUPOEN|BSCAN test update register, fallingedge of clock to valid enable|—|—|25|ns|
**Note:**
1. Based on default I/O setting of slow slew rate.
**==> picture [426 x 315] intentionally omitted <==**
**----- Start of picture text -----**<br>
TMS<br>TDI<br>tBTS tBTH<br>tBTCPH tBTCPL tBTCP<br>TCK<br>tBTCOEN tBTCO tBTCODIS<br>TDO V dilaD aat V dilaD aat<br>tBTCRH<br>tBTCRS<br>Data to be<br>Captured Data Captured<br>from I/O<br>tBTUPOEN tBUTCO tBTUODIS<br>Data to be<br>driven out V dilaD aat V dilaD aat<br>to I/O<br>**----- End of picture text -----**<br>
**Figure 3.23. JTAG Port Timing Waveforms**
© 2021-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02049-1.8
99
**CrossLink-NX Family Data Sheet**
## **3.29. Switching Test Conditions**
Figure 3.24 shows the output test load that is used for AC testing. The specific values for resistance, capacitance, voltage, and other test conditions are listed in Table 3.50.
**==> picture [190 x 122] intentionally omitted <==**
**----- Start of picture text -----**<br>
V T<br>R1<br>DUT Test Point<br>R2 CL*<br>:<br>**----- End of picture text -----**<br>
*CL Includes Test Fixture and Probe Capacitance
**Figure 3.24. Output Test Load, LVTTL and LVCMOS Standards**
**Table 3.50. Test Fixture Required Components, Non-Terminated Interfaces**
|**Test Condition**|**R1**|**R2**|**CL**|**Timing Ref.**|**VT**|
|---|---|---|---|---|---|
|LVTTL and other LVCMOS settings (L ≥ H, H ≥ L)|||0 pF|LVCMOS 3.3 = 1.5 V|—|
|||||LVCMOS 2.5 = VCCIO/2|—|
|||||LVCMOS 1.8 = VCCIO/2|—|
|||||LVCMOS 1.5 = VCCIO/2|—|
|||||LVCMOS 1.2 = VCCIO/2|—|
|LVCMOS 2.5 I/O(Z ≥ H)||1 MΩ|0pF|VCCIO/2|—|
|LVCMOS 2.5 I/O(Z ≥ L)|1 MΩ||0pF|VCCIO/2|VCCIO|
|LVCMOS 2.5 I/O(H ≥ Z)||100|0pF|VOH– 0.10|—|
|LVCMOS 2.5 I/O(L ≥ Z)|100||0pF|VOL+ 0.10|VCCIO|
**Note** :
1. Output test conditions for all other interfaces are determined by the respective standards.
© 2021-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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FPGA-DS-02049-1.8
**CrossLink-NX Family Data Sheet**
## **4. DC and Switching Characteristics for Automotive**
All specifications in this Chapter are characterized within recommended operating conditions unless otherwise specified.
## **4.1. Absolute Maximum Ratings**
**Table 4.1. Absolute Maximum Ratings**
|**Symbol**<br>~~a~~|**Parameter**|**Min**|**Max**|**Unit**|
|---|---|---|---|---|
|VCC, VCCECLK<br>~~a~~|SupplyVoltage|–0.5|1.10<br>~~ee~~|V|
|VCCAUX, VCCAUXA,<br>VCCAUXH3, VCCAUXH4,<br>VCCAUXH5<br>~~a~~<br>~~a~~|Supply Voltage<br>~~ee~~|–0.5<br>~~ee~~|1.98<br>~~ee~~<br>~~ee~~|V<br>~~ee~~|
|VCCIO0, 1, 2, 6, 7<br>~~a~~|I/O SupplyVoltage|–0.5|3.63<br>~~ee~~|V|
|VCCIO3, 4, 5<br>~~a~~|I/O SupplyVoltage|–0.5|1.98|V|
|VCCPLL_DPHY0, 1<br>~~a~~|Hardened D-PHY PLL SupplyVoltage|–0.5|1.10|V|
|VCCPLLSD0<br>~~a~~<br>~~a~~|SerDes Block PLL SupplyVoltage|–0.5|1.98|V|
|VCCA_DPHY0, 1<br>~~a~~|AnalogSupplyVoltage for Hardened D-PHY|–0.5|1.98|V|
|VCC_DPHY0, 1<br>~~a~~|Digital SupplyVoltage for Hardened D-PHY|–0.5|1.10|V|
|VCCSD0<br>~~a~~|SerDes SupplyVoltage|–0.5|1.10|V|
|VCCADC18<br>~~a~~|ADC Block 1.8 V SupplyVoltage|–0.5|1.98|V|
|VCCAUXSD<br>~~a~~<br>~~a~~|SerDes and AUX SupplyVoltage|–0.5|1.98|V|
|—<br>~~a~~|Input or I/O Voltage Applied, Bank 0, Bank<br>1,Bank 2, Bank 6, Bank 7|–0.5|3.63|V|
|—<br>~~a~~<br>~~a~~<br>~~a~~|Input or I/O Voltage Applied, Bank 3, Bank 4,<br>Bank 5|–0.5|1.98|V|
|—<br>~~a~~<br>~~a~~|Voltage Applied on SerDes Pins|–0.5|1.98|V|
|TA<br>~~a~~<br>~~a~~|Storage Temperature(Ambient)<br>|–65<br><br>~~DO~~|+150<br><br>~~DO~~|°C<br>|
|TJ<br>~~De~~|Junction Temperature<br>~~De~~|—<br>~~De~~<br>~~DO~~|+125<br>~~De~~<br>~~DO~~|°C<br>~~De~~|
**Notes** :
1. Stress above those listed under the _Absolute Maximum Ratings_ may cause permanent damage to the device. Functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
2. Compliance with the Lattice Thermal Management document is required.
3. All voltages referenced to GND.
4. All VCCAUX should be connected on PCB.
© 2021-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02049-1.8
101
**CrossLink-NX Family Data Sheet**
## **4.2. Recommended Operating Conditions[1, 2, 3]**
**Table 4.2. Recommended Operating Conditions**
|**Symbol**<br>~~eG~~|**Parameter**<br>~~eG~~|**Conditions**<br>~~GO~~|**Min**<br>~~GO~~|**Typ. **<br>~~GO~~|**Max**|**Unit**|
|---|---|---|---|---|---|---|
|VCC,VCCECLK<br>~~eG~~<br>~~a~~|Core SupplyVoltage<br>~~eG~~<br>~~ee~~|VCC= 1.0<br>~~GO~~<br>~~**e**e~~|0.95<br>~~GO~~<br>~~e~~|1.00<br>~~GO~~|1.05|V|
|VCCAUX<br>~~a~~<br><br>~~a~~|Auxiliary Supply Voltage<br>~~ee~~<br>|Bank 0, Bank 1, Bank 2, Bank 6,<br>Bank 7<br>~~**e**e~~<br>~~OO~~|1.746<br>~~e~~<br>~~OO~~|1.80<br>~~OO~~|1.89|V|
|VCCAUXH3/4/5<br>~~a~~<br>~~e~~<br>~~a~~|AuxiliarySupplyVoltage<br>~~ee~~<br>~~e~~|Bank 3, Bank 4, Bank 5<br>~~**e**e~~<br>~~eOO~~|1.746<br>~~e~~<br>~~OO~~|1.80<br>~~OO~~|1.89|V|
|VCCAUXA<br>~~e~~<br>~~a~~|Auxiliary Supply Voltage for<br>core logic<br>~~e~~|—<br>~~eOO~~<br>~~ee~~|1.746<br>~~OO~~<br>~~ee~~|1.80<br>~~OO~~<br>~~ee~~|1.89<br>~~ee~~|V<br>~~ee~~|
|VCCIO<br><br>~~a~~|I/O Driver Supply Voltage<br>|VCCIO= 3.3 V, Bank 0, Bank 1,<br>Bank 2, Bank 6, Bank 7<br>~~OO~~<br>~~ee~~<br>~~**e**e~~|3.135<br>~~OO~~<br>~~ee~~<br>~~e~~|3.30<br>~~OO~~<br>~~ee~~<br>~~ee~~|3.465<br>~~ee~~<br>~~ee~~|V<br>~~ee~~<br>~~ee~~|
|||VCCIO= 2.5 V, Bank 0, Bank 1,<br>Bank 2, Bank 6, Bank 7<br>~~ee~~<br>~~**e**e~~|2.375<br>~~ee~~<br>~~e~~|2.50<br>~~ee~~<br>~~ee~~|2.625<br>~~ee~~<br>~~ee~~|V<br>~~ee~~<br>~~ee~~|
|||VCCIO= 1.8 V, All Banks<br>~~**e**e~~|1.71<br>~~e~~<br>~~e~~|1.80<br>~~ee~~<br>~~e~~|1.89<br>~~ee~~<br>~~e~~|V<br>~~ee~~<br>~~e~~|
|||VCCIO= 1.5 V, All Banks4<br>~~ed~~|1.425<br>~~ed~~|1.50<br>~~ed~~|1.575<br>~~ed~~|V<br>~~ed~~|
|||VCCIO= 1.35 V, All Banks (For<br>DDR3L Only)<br>~~ee~~|1.2825<br>~~ee~~|1.35<br>~~ee~~|1.4175<br>~~ee~~|V<br>~~ee~~|
|||VCCIO= 1.2 V, All Banks4<br>~~es~~|1.14<br>~~es~~<br>~~ee~~|1.20<br>~~es~~<br>~~ee~~|1.26<br>~~es~~<br>~~ee~~|V<br>~~es~~<br>~~ee~~|
|||VCCIO= 1.0 V, Bank 3, Bank 4,<br>Bank 5<br>~~a~~|0.95<br>~~a~~<br>~~ee~~|1.00<br>~~a~~<br>~~ee~~|1.05<br>~~a~~<br>~~ee~~|V<br>~~a~~<br>~~ee~~|
|**D-PHY External Power Supplies**<br>~~ee~~<br>~~ee~~<br>~~pe~~|||||||
|VCCA_D-PHY<br>~~a~~|D-PHY Analog Power<br>Supply<br>~~ee~~|—<br>~~ee~~|1.71<br>~~ee~~|1.80<br>~~ee~~|1.89<br>~~ee~~|V<br>~~ee~~|
|VCC_D-PHY<br>~~GO~~|D-PHY Digital Power Supply<br>~~GO~~|—<br>~~GO~~|0.95<br>~~GO~~|1.00<br>~~GO~~|1.05<br>~~GO~~|V<br>~~GO~~|
|VCCPLL_D-PHY<br>~~sD~~|D-PHY PLL Power Supply<br>~~sD~~|—<br>~~sD~~|0.95<br>~~sD~~|1.00<br>~~sD~~|1.05<br>~~sD~~|V<br>~~sD~~|
|**ADC External Power Supplies**<br>~~sD~~<br>~~pn~~|||||||
|VCCADC18<br>~~eG~~|ADC 1.8 V Power Supply<br>~~eG~~|—<br>~~eG~~|1.71<br>~~eG~~|1.80<br>~~eG~~|1.89<br>~~eG~~|V<br>~~eG~~|
|**SerDes Block External Power Supplies**<br>~~a~~<br>~~ee~~<br>~~ee~~|||||||
|VCCSD0<br>~~a~~<br>~~a~~|Supply Voltage for SerDes<br>Block and SerDes I/O<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~|0.95<br>~~ee~~<br>~~ee~~|1.00|1.05|V|
|VCCPLLSD0<br>~~a~~<br>~~a~~<br>~~a~~|SerDes Block PLL Supply<br>Voltage<br>~~ee~~<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~<br>~~ee~~|1.71<br>~~ee~~<br>~~ee~~<br>~~ee~~|1.80|1.89|V|
|VCCAUXSD<br>~~a~~<br>~~a~~|SerDes Block Auxiliary<br>SupplyVoltage<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~|1.71<br>~~ee~~<br>~~ee~~|1.80|1.89|V|
|**Operating Temperature**<br>~~a~~<br>~~ee~~<br>~~ee~~<br>~~|~~<br>~~ee~~<br>~~ee~~|||||||
|tJAUTO<br>~~a~~|Junction Temperature,<br>Automotive Operation<br>~~a~~<br>~~ee~~|—<br>~~a~~<br>~~ee~~|–40<br>~~a~~<br>~~ee~~|—<br>~~a~~|125<br>~~a~~|°C<br>~~a~~|
**Notes** :
1. For correct operation, all supplies must be held in their valid operation voltage range.
2. All supplies with same voltage should be from the same voltage source. Proper isolation filters are needed to properly isolate noise from each other.
3. Common supply rails must be tied together except SerDes.
4. MSPI (Bank 0) and JTAG, SSPI, I[2] C, and I3C (Bank 1) ports are supported for VCCIO = 1.8 V to 3.3 V.
© 2021-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
102
FPGA-DS-02049-1.8
**CrossLink-NX Family Data Sheet**
## **4.3. Power Supply Ramp Rates**
## **Table 4.3. Power Supply Ramp Rates**
|**Symbol**|**Parameter**|**Min**|**Typ**|**Max**|**Unit**|
|---|---|---|---|---|---|
|tRAMP|Power Supply ramp rates for all supplies1|0.1|—|50|V/ms|
**Notes** :
1. Assumes monotonic ramp rates.
2. All supplies need to be in the operating range as defined in Recommended Operating Conditions1, when the device has completed configuration and entering into User Mode. Supplies that are not in the operating range needs to be adjusted to faster ramp rate, or users have to delay configuration or wake up.
## **4.4. Power up Sequence**
Power-On-Reset (POR) puts the CrossLink-NX device into a reset state. There is no power up sequence required for the CrossLink-NX device.
**Table 4.4. Power-On Reset**
|**Symbol**|**Parameter**|**Parameter**|**Min**|**Typ**|**Max**|**Unit**|
|---|---|---|---|---|---|---|
|VPORUP|Power-On-Reset ramp-up trip<br>point (Monitoring VCC, VCCAUX,<br>VCCI00, and VCCI01)|VCC|0.72|—|0.84|V|
|||VCCAUX|1.30|—|1.71|V|
|||VCCIO0,VCCI01|0.87|—|1.07|V|
|VPORDN|Power-On-Reset ramp-up trip<br>point (Monitoring VCCand VCCAUX)|VCC|0.48|—|0.85|V|
|||VCCAUX|1.36|—|1.57|V|
## **4.5. On-Chip Programmab** l **e Termination**
The CrossLink-NX devices support a variety of programmable on-chip terminations options, including:
- Dynamically switchable Single-Ended Termination with programmable resistor values of 40 Ω, 50 Ω, 60 Ω, or 75 Ω.
- Common mode termination of 100 Ω for differential inputs.
**==> picture [203 x 142] intentionally omitted <==**
**----- Start of picture text -----**<br>
V CCIO<br>TERM<br>Zo = 40 , 50 , 60 , or 75<br>control<br>to VCCIO /2<br>Zo<br>Zo +<br>VREF -<br>OFF-chip ON-chip<br>Parallel Single-Ended Input<br>**----- End of picture text -----**<br>
**==> picture [32 x 8] intentionally omitted <==**
**----- Start of picture text -----**<br>
Zo = 50<br>**----- End of picture text -----**<br>
**==> picture [122 x 105] intentionally omitted <==**
**----- Start of picture text -----**<br>
Zo<br>+<br>2Zo -<br>Zo<br>OFF-chip ON-chip<br>Differential Input<br>**----- End of picture text -----**<br>
**Figure 4.1. On-Chip Termination**
See Table 4.5 for termination options for input modes.
© 2021-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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**CrossLink-NX Family Data Sheet**
**Table 4.5. On-Chip Termination Options for Input Modes**
|**IO_TYPE**|**Differential Termination Resistor1, 2**|**Terminate to VCCIO/21, 2**|
|---|---|---|
|subLVDS<br>~~a~~|100, OFF|OFF|
|SLVS<br>~~a~~|100, OFF|OFF|
|MIPI_DPHY<br>~~a~~|100|OFF|
|HSTL15D_I<br>~~a~~<br>~~a~~|100, OFF|OFF|
|SSTL15D_I<br>~~a~~|100, OFF|OFF|
|SSTL135D_I<br>~~a~~|100, OFF|OFF|
|HSUL12D<br>~~a~~|100, OFF|OFF<br>~~O~~|
|LVCMOS15H<br>~~a~~|OFF|OFF|
|LVCMOS12H<br>~~a~~<br>~~a~~|OFF|OFF|
|LVCMOS10H<br>~~a~~|OFF|OFF|
|LVCMOS12H<br>~~a~~|OFF|OFF|
|LVCMOS10H<br>~~a~~|OFF|OFF|
|LVCMOS18H<br>~~a~~|OFF|OFF, 40, 50, 60, 75|
|HSTL15_I<br>~~a~~<br>~~a~~|OFF|50|
|SSTL15_I<br>~~a~~|OFF|OFF, 40, 50, 60, 75|
|SSTL135_I<br>~~a~~|OFF|OFF, 40, 50, 60, 75|
|HSUL12<br>~~a~~|OFF|OFF, 40, 50, 60, 75|
**Notes** :
1. TERMINATE to VCCIO/2 (Single-Ended) and DIFFRENTIAL TERMINATION RESISTOR when turned on can only have one setting per bank. Only left and right banks have this feature.
2. Use of TERMINATE to VCCIO/2 and DIFFRENTIAL TERMINATION RESISTOR are mutually exclusive in an I/O bank. On-chip termination tolerance –10%/+60%.
Refer to sysI/O User Guide for Nexus Platform (FPGA-TN-02067) for on-chip termination usage and value ranges.
## **4.6. Hot Socketing Specifications**
**Table 4.6. Hot Socketing Specifications for GPIO**
|**Symbol**|**Parameter**|**Condition**|**Min**|**Typ**|**Max**|**Unit**|
|---|---|---|---|---|---|---|
|IDK|Input or I/O Leakage Current for<br>Wide Range I/O (excluding<br>MCLK/MCSN/MOSI/INITN/DONE)|0 < VIN< VIH(max)<br>0 < VCC< VCC(max)<br>0 < VCCIO< VCCIO(max)<br>0 < VCCAUX< VCCAUX (max)|-1.5|—|1.5|mA|
## **Notes** :
- IDK is additive to IPU, IPD, or IBH.
- Hot socketing specs are defined at a device junction temperature of 85 °C or below. When the device temperature is above 85[o] C, the IDK current can exceed the above spec.
- Going beyond the hot socketing ranges specified here will cause exponentially higher Leakage currents and potential reliability issues. A total of 64 mA per 8 I/O should not be exceeded.
## **4.7. ESD Performance**
Refer to the CrossLink-NX Product Family Qualification Summary for complete Automotive grade qualification data, including ESD performance.
© 2021-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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**CrossLink-NX Family Data Sheet**
## **4.8. DC Electrical Characteristics**
**Table 4.7. DC Electrical Characteristics – Wide Range**
|**Symbol**<br>~~aGGG~~<br>~~a~~|**Parameter**<br>~~GGG~~<br>|**Condition**<br>~~GGG~~<br>|**Min**<br>~~GGG~~<br>~~ee~~<br>|**Typ**<br>~~GGG~~<br>~~ee~~<br>|**Max**<br>~~GGG~~<br>|**Unit**<br>~~GGG~~<br>|
|---|---|---|---|---|---|---|
|IIL, IIH1<br>~~aee~~<br>~~a~~|Input or I/O Leakage current<br>(Commercial/Industrial)<br>~~ee~~<br>|0 ≤ VIN≤ VCCIO<br>~~ee~~<br>|—<br>~~ee~~<br>~~ee~~<br>|—<br>~~ee~~<br>~~ee~~<br>|10<br>~~ee~~<br>|µA<br>~~ee~~<br>|
|IIH2<br>~~aGG~~<br>~~a~~|Input or I/O Leakage current<br>~~GG~~<br>|VCCIO≤ VIN≤ VIH (max)<br>~~GG~~<br>|—<br>~~ee~~<br>~~GG~~<br>~~ee~~<br>|—<br>~~ee~~<br>~~GG~~<br>~~ee~~<br>|100<br>~~GG~~<br>|µA<br>~~GG~~<br>|
|IPU<br>~~aee~~<br>~~a~~<br>~~a~~|I/O Weak Pull-up Resistor<br>Current<br>~~ee~~<br><br>|0 ≤ VIN≤ 0.7 × VCCIO<br>~~ee~~<br><br>|–30<br>~~ee~~<br>~~ee~~<br><br>~~ee~~<br>|—<br>~~ee~~<br>~~ee~~<br><br>~~ee~~<br>|–150<br>~~ee~~<br><br>|µA<br>~~ee~~<br><br>|
|IPD<br>~~aee~~<br>~~a~~|I/O Weak Pull-down Resistor<br>Current<br>~~ee~~<br>|VIL(max) ≤ VIN≤ VCCIO<br>~~ee~~<br>|30<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>|—<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>|150<br>~~ee~~<br>|µA<br>~~ee~~<br>|
|IBHLS<br>~~aGG~~|Bus Hold Low SustainingCurrent<br>~~GG~~|VIN= VIL (max)<br>~~GG~~|30<br>~~ee~~<br>~~GG~~|—<br>~~ee~~<br>~~GG~~|~~GG~~|µA<br>~~GG~~|
|IBHHS<br>~~aGG~~<br>~~aGG~~|Bus Hold High SustainingCurrent<br>~~GG~~<br>~~GG~~|VIN= 0.7 × VCCIO<br>~~GG~~<br>~~GG~~|–30<br>~~ee~~<br>~~GG~~<br>~~GG~~|—<br>~~ee~~<br>~~GG~~<br>~~GG~~|~~GG~~<br>~~GG~~|µA<br>~~GG~~<br>~~GG~~|
|IBHLO<br>~~a a~~|Bus Hold Low Overdrive Current<br>~~a~~<br>~~GD~~|0 ≤ VIN≤ VCCIO<br>~~GD~~|—<br>~~GD~~|—<br>~~GD~~|150<br>~~GD~~|µA<br>~~GD~~|
|IBHHO<br>~~a ~~|Bus Hold High Overdrive Current<br> ~~a~~<br>~~GG~~|0 ≤ VIN≤ VCCIO<br>~~GG~~|—<br>~~GG~~|—<br>~~GG~~|–150<br>~~GG~~|µA<br>~~GG~~|
|VBHT<br>~~a ~~|Bus Hold TripPoints<br> ~~a~~<br>~~GG~~|—<br>~~GG~~|VIL(max)<br>~~GG~~|—<br>~~GG~~|VIH(min)<br>~~GG~~|V<br>~~GG~~|
**Notes** :
1. Input or I/O leakage current is measured with the pin configured as an input or as an I/O with the output tri-stated. Bus Maintenance circuits are disabled.
2. The input leakage current IIH is the worst case input leakage per GPIO when the pad signal is high and also higher than the bank VCCIO. This is considered a mixed mode input.
**Table 4.8. DC Electrical Characteristics – High Speed**
|**Symbol**<br>~~pO~~<br>~~a~~|**Parameter**<br>~~pO~~|**Condition**<br>~~pO~~|**Min**<br>~~pO~~|**Typ**<br>~~pO~~<br>DO|**Max**<br>~~pO~~|**Unit**<br>~~pO~~|
|---|---|---|---|---|---|---|
|IIL, IIH1<br>~~a~~<br>~~a~~|Input or I/O Leakage<br>~~GG~~|0 ≤ VIN≤ VCCIO<br>~~GG~~|—<br>~~GG~~|—<br>~~GG~~<br>DO|10<br>~~GG~~|µA<br>~~GG~~|
|IPU<br>~~a~~|I/O Weak Pull-up Resistor<br>Current|0 ≤ VIN≤ 0.7 × VCCIO|–30|—<br>DO|–150|µA|
|IPD<br>~~a~~|I/O Weak Pull-down Resistor<br>Current<br>~~ee~~|VIL(max) ≤ VIN≤ VCCIO<br>~~ee~~|30<br>~~ee~~|—<br>~~ee~~|150<br>~~ee~~|µA<br>~~ee~~|
|IBHLS<br>~~a~~|Bus Hold Low SustainingCurrent<br>~~GG~~|VIN= VIL (max)<br>~~GG~~|30<br>~~GG~~|—<br>~~GG~~|—<br>~~GG~~|µA<br>~~GG~~|
|IBHHS<br>~~a~~|Bus Hold High SustainingCurrent|VIN= 0.7 × VCCIO|–30|—|—|µA|
|IBHLO<br>~~a~~<br>~~a~~|Bus Hold low Overdrive Current<br>~~GG~~|0 ≤ VIN≤ VCCIO<br>~~GG~~|—<br>~~GG~~|—<br>~~GG~~|150<br>~~GG~~|µA<br>~~GG~~|
|IBHHO<br>~~a~~<br>~~a ~~|Bus Hold high Overdrive Current<br>~~GG~~<br> ~~a~~<br>~~GG~~|0 ≤ VIN≤ VCCIO<br>~~GG~~<br>~~GG~~|—<br>~~GG~~<br>~~GG~~|—<br>~~GG~~<br>~~GG~~|–150<br>~~GG~~<br>~~GG~~|µA<br>~~GG~~<br>~~GG~~|
|VBHT<br>~~a~~|Bus Hold Trip Points|—|VIL<br>(max)|—|VIH(min)|V|
**Note:** Input or I/O leakage current is measured with the pin configured as an input or as an I/O with the output tri-stated. Bus Maintenance circuits are disabled.
**Table 4.9. Capacitors – Wide Range**
|**Symbol**|**Parameter**|**Condition**|**Min**|**Typ**|**Max**|**Unit**|
|---|---|---|---|---|---|---|
|C11|I/O Capacitance1|VCCIO= 3.3 V, 2.5 V, 1.8 V, 1.5 V, 1.2 V,<br>VCC= typ., VIO= 0 to VCCIO+ 0.2V|—|6|—|pF|
|C21|Dedicated Input Capacitance1|VCCIO= 3.3 V, 2.5 V, 1.8 V, 1.5 V, 1.2 V,<br>VCC= typ., VIO= 0 to VCCIO+ 0.2V|—|6|—|pF|
**Note** :
1. TA 25[o] C, f = 1.0 MHz.
© 2021-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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**CrossLink-NX Family Data Sheet**
|**Table 4.10. Capacitors – High Performance**||||
|---|---|---|---|
|**Symbol**<br>**Parameter**<br>**Condition**<br>**Min**<br>**Typ**<br>**Max**<br>**Unit**<br>C11<br>I/O Capacitance1<br>VCCIO= 1.8 V, 1.5 V, 1.2 V, VCC= typ.,<br>VIO= 0 to VCCIO+ 0.2V<br>—<br>6<br>—<br>pF<br>C21<br>Dedicated Input Capacitance1<br>VCCIO= 1.8 V, 1.5 V, 1.2 V, VCC= typ.,<br>VIO= 0 to VCCIO+ 0.2V<br>—<br>6<br>—<br>pF<br>C31<br>D-PHY I/O Capacitance<br>VCCA_D-PHY= 1.8 V, VCC= typ., VIO= 0<br>to VCCA_D-PHY+ 0.2V<br>—<br>5<br>—<br>pF<br>C41<br>SerDes I/O Capacitance<br>VCCSD0= 1.0 V, VCC= typ., VIO= 0 to<br>VCCSD0+ 0.2 V<br>—<br>5<br>—<br>pF<br>~~ee~~||||
|**Note:**||||
|1.<br>TA25oC, f = 1.0 MHz.||||
|**Table 4.11. Single Ended Input Hysteresis – Wide Range**||||
|**IO_TYPE**<br>**VCCIO**<br>**TYP Hysteresis**<br>LVCMOS33<br>3.3 V<br>250 mV<br>LVCMOS25<br>3.3 V<br>200 mV<br>2.5 V<br>250 mV<br>LVCMOS18<br>1.8 V<br>180 mV<br>LVCMOS15<br>1.5 V<br>50 mV<br>LVCMOS12<br>1.2 V<br>0<br>LVCMOS10<br>1.2 V<br>0<br>~~==~~||||
|**Table 4.12. Single Ended Input Hysteresis – High Performance**<br>**IO_TYPE**<br>**VCCIO**<br>**TYP Hysteresis**<br>LVCMOS18H<br>1.8 V<br>180 mV<br>LVCMOS15H<br>1.8 V<br>50 mV<br>1.5 V<br>150 mV<br>LVCMOS12H<br>1.2 V<br>0<br>LVCMOS10H<br>1.0 V<br>0<br>MIPI-LP-RX<br>1.2 V<br>>25 mV<br>~~—=_~~||||
|**4.9. Supply Currents**||||
|For estimating and calculating current, use Power Calculator in Lattice Design software.||||
This operating and peak current is design dependent, and can be calculated in Lattice Design software. Some blocks can be placed into low current standby modes. Refer to Power Management and Calculation for CrossLink-NX Devices (FPGA-TN-02075).
© 2021-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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**CrossLink-NX Family Data Sheet**
## **4.10. sysI/O Recommended Operating Conditions**
**Table 4.13. sysI/O Recommended Operating Conditions**
|**Standard**<br>~~Bf~~|**Support Banks**<br>~~Bf~~|**VCCIO(Input)**<br>~~a~~|**VCCIO(Output)**<br>~~a~~|
|---|---|---|---|
|||**Typ.**<br>~~a~~|**Typ. **<br>~~a~~|
|**Single-Ended**<br>~~Bf a~~<br>~~**G**e~~<br>~~**G**O~~<br>~~Ge~~||||
|LVCMOS33<br>~~ee~~<br>~~Ge~~|0, 1, 2, 6, 7<br>~~ee~~<br>~~Ge~~|3.3<br>~~ee~~<br>~~**G**e~~|3.3<br>~~ee~~<br>~~**G**O~~|
|LVTTL33<br>~~Ge~~|0, 1, 2, 6, 7<br>~~Ge~~|3.3<br>~~**G**e~~|3.3<br>~~**G**O~~|
|LVCMOS25¹,²<br>~~Ge~~|0, 1, 2, 6, 7<br>~~Ge ~~|2.5, 3.3<br> ~~GG~~|2.5<br>~~GG~~|
|LVCMOS18¹,²<br>~~Ge~~<br>~~eG~~|0, 1, 2, 6, 7<br>~~Ge ~~<br>~~eG~~|1.2, 1.5, 1.8, 2.5, 3.3<br> ~~GG~~<br>~~GO~~|1.8<br>~~GG~~<br>~~GO~~|
|LVCMOS18H<br>~~eG~~<br>~~Ge~~|3, 4, 5<br>~~eG~~<br>~~Ge~~|1.8<br>~~GO~~<br>~~**G**e~~|1.8<br>~~GO~~<br>~~**G**O~~|
|LVCMOS15¹,²<br>~~eG~~<br>~~Ge~~<br>~~Ge~~|0, 1, 2, 6, 7<br>~~eG ~~<br>~~Ge~~<br>~~Ge~~|1.2, 1.5, 1.8, 2.5, 3.3<br> ~~GO~~<br>~~Ge~~<br>~~**G**e~~|1.5<br>~~GO~~<br>~~Ge~~<br>~~**G**O~~|
|LVCMOS15H¹<br>~~Ge~~|3, 4, 5<br>~~Ge~~|1.5, 1.8<br>~~**G**e~~|1.5<br>~~**G**O~~|
|LVCMOS12¹,²<br>~~Ge~~|0, 1, 2, 6, 7<br>~~Ge ~~|1.2, 1.5, 1.8, 2.5, 3.3<br> ~~GG~~|1.2<br>~~GG~~|
|LVCMOS12H¹<br>~~Ge~~<br>~~eG~~|3, 4, 5<br>~~Ge ~~<br>~~eG~~|1.2, 1.357, 1.5, 1.8<br> ~~GG~~<br>~~GO~~|1.2<br>~~GG~~<br>~~GO~~|
|LVCMOS10¹<br>~~eG~~<br>~~Ge~~|0, 1, 2, 6, 7<br>~~eG~~<br>~~Ge~~|1.2, 1.5, 1.8, 2.5, 3.3<br>~~GO~~<br>~~**G**e~~|—<br>~~GO~~<br>~~**G**O~~|
|LVCMOS10H¹<br>~~eG~~<br>~~Ge~~<br>~~Ge~~|3, 4, 5<br>~~eG ~~<br>~~Ge~~<br>~~Ge~~|1.0, 1.2, 1.357, 1.5, 1.8<br> ~~GO~~<br>~~Ge~~<br>~~**G**e~~|1.0<br>~~GO~~<br>~~Ge~~<br>~~**G**O~~|
|LVCMOS10R¹<br>~~Ge~~|3, 4, 5<br>~~Ge~~|1.0, 1.2, 1.357, 1.5, 1.8<br>~~**G**e~~|—<br>~~**G**O~~|
|SSTL135_I, SSTL135_II3<br>~~Ge~~|3, 4, 5<br>~~Ge ~~|1.357<br> ~~GG~~|1.35<br>~~GG~~|
|SSTL15_I, SSTL15_II3<br>~~Ge~~<br>~~eG~~|3, 4, 5<br>~~Ge ~~<br>~~eG~~|1.58<br> ~~GG~~<br>~~GO~~|1.58<br>~~GG~~<br>~~GO~~|
|HSTL15_I3<br>~~eG~~<br>~~Ge~~|3, 4, 5<br>~~eG~~<br>~~Ge~~|1.58<br>~~GO~~<br>~~**G**e~~|1.58<br>~~GO~~<br>~~GO~~|
|HSUL123<br>~~eG~~<br>~~Ge~~<br>~~Ge~~|3, 4, 5<br>~~eG ~~<br>~~Ge~~<br>~~Ge~~|1.2<br> ~~GO~~<br>~~Ge~~<br>~~**G**e~~|1.2<br>~~GO~~<br>~~Ge~~<br>~~GO~~|
|MIPI D-PHY LP Input6<br>~~Ge~~|3, 4, 5<br>~~Ge~~|1.2<br>~~**G**e~~|1.2<br>~~GO~~<br>~~D~~|
|**Differential6**||||
|LVDS<br>~~Ge~~|3, 4, 5<br>~~Ge ~~|1.2, 1.35, 1.5, 1.8<br> ~~GG~~|1.8<br>~~GG~~|
|LVDSE5<br>~~Ge~~<br>~~eG~~|0, 1, 2, 6, 7<br>~~Ge~~<br>~~eG~~|—<br>~~GG~~<br>~~GO~~|2.5<br>~~GG~~<br>~~GO~~|
|subLVDS<br>~~Ge~~<br>~~eG~~|3, 4, 5<br>~~Ge ~~<br>~~eG~~|1.2, 1.35, 1.5, 1.8<br> ~~GG~~<br>~~GO~~|—<br>~~GG~~<br>~~GO~~|
|subLVDSE5<br>~~eG~~<br>~~Ge~~|0, 1, 2, 6, 7<br>~~eG ~~<br>~~Ge~~|—<br> ~~GO~~<br>~~Ge~~|1.8<br>~~GO~~<br>~~Ge~~|
|subLVDSEH5<br>~~Ge~~<br>~~Ge~~<br>~~eG~~|3, 4, 5<br>~~Ge~~<br>~~Ge~~<br>~~eG~~|—<br>~~Ge~~<br>~~Ge~~<br>~~GO~~|1.8<br>~~Ge~~<br>~~Ge~~<br>~~GO~~|
|SLVS6<br>~~Ge~~<br>~~eG~~|3, 4, 5<br>~~Ge~~<br>~~eG~~|1.0, 1.2, 1.357, 1.5, 1.84<br>~~Ge~~<br>~~GO~~<br>~~G~~~~**e**~~|1.2, 1.357, 1.5, 1.84<br>~~Ge~~<br>~~GO~~<br>~~GO~~|
|MIPI D-PHY6<br>~~eG~~<br>~~Ge~~<br>|3, 4, 5<br>~~eG ~~<br>~~Ge~~<br>|1.2<br> ~~GO~~<br>~~Ge~~<br>~~G~~~~**e**~~<br>~~Ge~~|1.2<br>~~GO~~<br>~~Ge~~<br>~~GO~~<br>~~GO~~|
|LVCMOS33D5<br>~~G~~|0, 1, 2, 6, 7<br>~~G~~|—<br>~~G~~~~**e**~~<br>~~GGe~~|3.3<br>~~GO~~<br>~~GO~~|
|LVTTL33D5<br><br>~~Ge~~<br>~~De~~|0, 1, 2, 6, 7<br><br>~~Ge~~<br>~~De~~|—<br>~~Ge~~<br>~~Ge~~<br>~~OO~~<br>|3.3<br>~~GO~~<br>~~Ge~~<br>~~OO~~<br>|
|LVCMOS25D5<br>~~Ge~~<br>~~eG~~<br>~~De~~|0, 1, 2, 6, 7<br>~~Ge~~<br>~~eG~~<br>~~De~~|—<br>~~Ge~~<br>~~eG~~<br>~~OO~~<br>|2.5<br>~~Ge~~<br>~~eG~~<br>~~OO~~<br>|
|SSTL135D_I, SSTL135D_II5<br>~~eG~~<br>~~De~~|3, 4, 5<br>~~eG~~<br>~~De~~|—<br>~~eG~~<br>~~OO~~<br>~~GG~~<br>~~G~~~~**e**~~|1.357<br>~~eG~~<br>~~OO~~<br>~~GG~~<br>~~GO~~|
|SSTL15D_I, SSTL15D_II5<br>~~De~~<br>~~Ge~~<br>|3, 4, 5<br>~~De ~~<br>~~Ge~~<br>|—<br>~~OO~~<br> ~~GG~~<br>~~Ge~~<br>~~G~~~~**e**~~<br>~~Ge~~|1.5<br>~~OO~~<br>~~GG~~<br>~~Ge~~<br>~~GO~~<br>~~GO~~|
|HSTL15D_I5<br>~~G~~|3, 4, 5<br>~~G~~|—<br>~~G~~~~**e**~~<br>~~GGe~~|1.5<br>~~GO~~<br>~~GO~~|
|HSUL12D5<br><br>~~fe~~|3, 4, 5<br><br>~~fe~~|—<br>~~Ge~~<br>~~fe~~|1.2<br>~~GO~~<br>~~fe~~|
**Notes** :
1. Single-ended input can mix into I/O Banks with VCCIO different from the standard requires due to some of these input standards use internal supply voltage source (VCC, VCCAUX) to power the input buffer, which makes them to be independent of VCCIO voltage. For more details, please refer to sysI/O User Guide for Nexus Platform (FPGA-TN-02067). The following is a brief guideline to follow:
- a. Weak pull-up on the I/O must be set to OFF.
- b. Bank 3, Bank 4, and Bank 5 I/O can only mix into banks with VCCIO higher than the pin standard, due to clamping diode on the pin in these banks. Bank 0, Bank 1, Bank 2, Bank 6, and Bank 7 does not have this restriction.
- c. LVCMOS25 uses VCCIO supply on input buffer in Bank 0, Bank 1, Bank 2, Bank 6, and Bank 7. It can be supported with VCCIO = 3.3 V to meet the VIH and VIL requirements, but there is additional current drawn on VCCIO. Hysteresis has to be disabled when using 3.3 V supply voltage.
- d. LVCMOS15 uses VCCIO supply on input buffer in Bank 3, Bank 4, and Bank 5. It can be supported with VCCIO = 1.8 V to meet the VIH and VIL requirements, but there is additional current drawn on VCCIO.
© 2021-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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**CrossLink-NX Family Data Sheet**
2. Single-ended LVCMOS inputs can mixed into I/O Banks with different VCCIO, providing weak pull-up is not used. For additional information on Mixed I/O in Bank VCCIO, refer to sysI/O User Guide for Nexus Platform (FPGA-TN-02067) **.**
3. These inputs use differential input comparator in Bank 3, Bank 4, and Bank 5. The differential input comparator uses VCCAUXH power supply. These inputs require the VREF pin to provide the reference voltage in the Bank. Refer to sysI/O User Guide for Nexus Platform (FPGA-TN-02067) for details **.**
4. All differential inputs use differential input comparator in Bank 3, Bank 4, and Bank 5. The differential input comparator uses VCCAUXH power supply. There is no differential input signaling supported in Bank 0, Bank 1, Bank 2, Bank 6, and Bank 7.
5. These outputs are emulating differential output pair with single-ended output drivers with true and complement outputs driving on each of the corresponding true and complement output pair pins. The common mode voltage, VCM, is ½ × VCCIO. Refer to sysI/O User Guide for Nexus Platform (FPGA-TN-02067) for details **.**
6. Soft MIPI D-PHY HS using sysI/O is supported with SLVS input and output that can be placed in banks with VCCIO voltage shown in SLVS. D-PHY with HS and LP modes supported needs to be placed in banks with VCCIO voltage = 1.2 V. Soft MIPI D-PHY LP input and output using sysI/O are supported with LVCMOS12.
7. VCCIO = 1.35 V is only supported in Bank 3, Bank 4, and Bank 5, for use with DDR3L interface in the bank. These Input and Output standards can fit into the same bank with the VCCIO = 1.35 V.
8. LVCMOS15 input uses VCCIO supply voltage. If VCCIO is 1.8 V, the DC levels for LVCMOS15 are still met, but there could be increase in input buffer current.
## **4.11. sysI/O Single-Ended DC Electrical Characteristics[3]**
**Table 4.14. sysI/O DC Electrical Characteristics – Wide Range I/O**
|**Input/Output**<br>**Standard2 **|**VIL**|**VIL**|**VIH**|**VIH**|**VOL Max**<br>**(V)**|**VOH Min**<br>**(V)**|**IOL(mA)**|**IOH(mA)**|
|---|---|---|---|---|---|---|---|---|
||**Min(V)**|**Max(V)**|**Min(V)**|**Max(V)**|||||
|LVTTL33<br>LVCMOS33<br>~~a~~|—|0.8|2.0|3.4654|0.4|VCCIO– 0.4|2, 4, 8,<br>12, 16,<br>“50RS”3|-2, -4, -8,<br>-12, -16,<br>“50RS”3|
|LVCMOS25<br>~~a~~<br>~~ee~~<br>~~a~~|—<br>~~ee~~|0.7<br>~~ee~~|1.7<br>~~ee~~|3.4654<br>~~ee~~|0.4<br>~~ee~~<br>~~es~~|VCCIO– 0.45<br>~~ee~~<br>~~es~~|2, 4, 8,<br>10,<br>“50RS”3<br>~~ee~~<br>~~ee~~|-2, -4, -8,<br>-10,<br>“50RS”3<br>~~ee~~|
|LVCMOS18<br>~~ee~~<br>~~a~~<br>~~ee~~|—<br>~~ee~~<br>|0.35 × VCCIO<br>~~ee~~<br>~~ry~~<br>|0.65 × VCCIO<br>~~ee~~<br>~~ry~~<br>|3.4654<br>~~ee~~<br>~~ry~~|0.4<br>~~ee~~<br>~~es~~<br>~~ts~~|VCCIO– 0.45<br>~~ee~~<br>~~es~~|2, 4, 8,<br>“50RS”3<br>~~ee~~<br>~~ee~~|-2, -4, -8,<br>“50RS”3<br>~~ee~~|
|LVCMOS15<br>~~ee ~~<br>~~a~~<br>~~ee~~<br>~~ee~~|—<br> ~~ee~~<br>~~es~~<br>|0.35 × VCCIO<br>~~ee~~<br>~~ry~~<br>~~es~~<br>|0.65 × VCCIO<br>~~ee~~<br>~~ry~~<br>~~**r**s~~|3.4654<br>~~ee~~<br>~~ry~~<br>~~ty~~|0.4<br>~~ee~~<br>~~es ~~<br>~~ts~~|VCCIO– 0.4<br>~~ee~~<br> ~~es ~~|2, 4<br>~~ee~~<br> ~~ee~~|-2, -4<br>~~ee~~|
|LVCMOS12<br>~~ee~~<br>~~ee ee~~|—<br>~~es~~<br>~~ee ee~~|0.35 × VCCIO<br>~~ry~~<br>~~es~~<br>~~ee~~|0.65 × VCCIO<br>~~ry~~<br>~~**r**s~~<br>~~r~~|3.4654<br>~~ry~~<br>~~ty~~|0.4<br>~~ts~~|VCCIO– 0.4|2, 4|-2, -4|
|LVCMOS10<br>~~ee ~~<br>~~ee ee~~|—<br> ~~es~~<br>~~ee ee~~|0.35 × VCCIO<br>~~ry~~<br>~~es~~<br>~~ee~~|0.65 × VCCIO<br>~~ry~~<br>~~**r**s~~<br>~~r~~|3.4654<br>~~ry ~~<br>~~ty~~|No O/P Support<br> ~~ts~~||||
**Notes** :
1. For electro-migration, the average DC current drawn by the I/O pads within a bank of I/O shall not exceed 10 mA per I/O average.
2. For the types of I/O standard supported in which bank, refer to sysI/O User Guide for Nexus Platform (FPGA-TN-02067) for details.
3. Select “50RS” in driver strength is selecting 50 Ω series impedance driver.
4. VIH (MAX) for inputs on these standards (in Bank 0, Bank 1, Bank 2, Bank 6, and Bank 7) can go up to 3.465 V if the input clamp is OFF. Otherwise, the input cannot be higher than VCCIO + 0.3 V.
© 2021-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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FPGA-DS-02049-1.8
|**Input/Output**<br>**Standard2 **<br>~~a~~|**VIL**<br>~~a~~|**VIL**<br>~~a~~|**VIH**<br>~~a~~|**VIH**<br>~~a~~|**VOL Max**<br>**(V)**<br>~~a~~|**VOH Min**<br>**(V)**<br>~~a~~|**IOL (mA)**<br>~~a~~|**IOH (mA)**<br>~~a~~|
|---|---|---|---|---|---|---|---|---|
||**Min(V)**<br>~~a~~|**Max(V)**<br>~~a~~|**Min(V)**<br>~~a~~|**Max(V)**<br>~~a~~|||||
|LVCMOS18H<br>~~a~~<br>~~ee~~|—<br>~~a~~<br>~~ee~~|0.35 ×<br>VCCIO<br>~~a~~<br>~~ee~~|0.65 × VCCIO<br>~~a~~<br>~~ee~~|VCCIO+<br>0.3<br>~~a~~<br>~~ee~~|0.4<br>~~a~~<br>~~ee~~|VCCIO– 0.45<br>~~a~~<br>~~ee~~|2, 4, 8, 12,<br>“50RS”3<br>~~a~~<br>~~es~~|-2, -4, -8,<br>-12,<br>“50RS”3<br>~~a~~<br>~~esee~~|
|LVCMOS15H<br>~~ee~~<br>~~a~~|—<br>~~ee~~<br>~~a~~|0.35 ×<br>VCCIO<br>~~ee~~|0.65 × VCCIO<br>~~ee~~<br>~~ee~~|VCCIO+<br>0.3<br>~~ee~~|0.4<br>~~ee~~<br>~~ee~~|VCCIO– 0.4<br>~~ee~~<br>~~ee~~|2, 4, 8,<br>“50RS”3<br>~~es~~<br>~~eee~~|-2, -4, -8,<br>“50RS”3<br>~~esee~~<br>~~eee~~|
|LVCMOS12H<br>~~ee ~~<br>~~a~~<br>~~a~~|—<br> ~~ee~~<br>~~a~~<br>~~a~~|0.35 ×<br>VCCIO<br>~~ee ~~|0.65 × VCCIO<br> ~~ee ~~<br>~~ee~~<br>~~ee~~|VCCIO+<br>0.3<br> ~~ee ~~|0.4<br> ~~ee~~<br>~~ee~~<br>~~ee~~|VCCIO– 0.4<br>~~ee ~~<br>~~ee~~<br>~~ee~~|2, 4, 8,<br>“50RS”3<br> ~~es~~<br>~~eee~~<br>~~eee~~|-2, -4, -8,<br>“50RS”3<br>~~es ee~~<br>~~eee~~<br>~~eee~~|
|LVCMOS10H<br>~~a~~<br>~~a~~<br>~~a~~|—<br>~~a~~<br>~~a~~<br>~~a~~|0.35 ×<br>VCCIO|0.65 × VCCIO<br>~~ee~~<br>~~ee~~<br>~~ee~~|VCCIO+<br>0.3|0.27 ×<br>VCCIO<br>~~ee~~<br>~~ee~~<br>~~ee~~|0.75 × VCCIO<br>~~ee ~~<br>~~ee~~<br>~~ee~~|2, 4<br> ~~eee~~<br>~~eee~~<br>~~eee~~|-2, -4<br>~~eee~~<br>~~eee~~<br>~~eee~~|
|SSTL15_I<br>~~a~~<br>~~a~~|—<br>~~a~~<br>~~a~~|VREF– 0.10|VREF+ 0.1<br>~~ee~~<br>~~ee~~|VCCIO+<br>0.3|0.30<br>~~ee~~<br>~~ee~~|VCCIO– 0.30<br>~~ee ~~<br>~~ee~~|7.5<br> ~~eee~~<br>~~eee~~|–7.5<br>~~eee~~<br>~~eee~~|
|SSTL15_II<br>~~a~~<br>~~eee~~<br>~~ee~~|—<br>~~a~~<br>~~eee~~<br>~~ee~~|VREF– 0.10<br>~~eee~~<br>~~ee~~|VREF+ 0.1<br>~~ee~~<br>~~eee~~<br>~~ee~~|VCCIO+<br>0.3<br>~~eee~~|0.30<br>~~ee~~<br>~~eee~~|VCCIO– 0.30<br>~~ee ~~<br>~~eee~~<br>~~eee~~|8.8<br> ~~eee~~<br>~~eee~~<br>~~eee~~|–8.8<br>~~eee~~<br>~~eee~~<br>~~eee~~|
|HSTL15_I<br>~~eee~~<br>~~ee~~<br>~~ee~~|—<br>~~eee~~<br>~~ee~~<br>~~ee~~|VREF– 0.10<br>~~eee~~<br>~~ee~~<br>~~ee~~|VREF+ 0.1<br>~~eee~~<br>~~ee~~<br>~~ee~~|VCCIO+<br>0.3<br>~~eee~~|0.40<br>~~eee~~|VCCIO– 0.40<br>~~eee~~<br>~~eee~~<br>~~eee~~|8<br>~~eee~~<br>~~eee~~<br>~~eee~~|–8<br>~~eee~~<br>~~eee~~<br>~~eee~~|
|SSTL135_I<br>~~ee~~<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~<br>~~ee~~|VREF– 0.09<br>~~ee~~<br>~~ee~~<br>~~ee~~|VREF+ 0.09<br>~~ee~~<br>~~ee~~<br>~~ee~~|VCCIO+<br>0.3|0.27|VCCIO– 0.27<br>~~eee~~<br>~~eee~~<br>~~eee~~|6.75<br>~~eee~~<br>~~eee~~<br>~~eee~~|–6.75<br>~~eee~~<br>~~eee~~<br>~~eee~~|
|SSTL135_II<br>~~ee~~<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~<br>~~ee~~|VREF– 0.09<br>~~ee~~<br>~~ee~~<br>~~ee~~|VREF+ 0.09<br>~~ee~~<br>~~ee~~<br>~~ee~~|VCCIO+<br>0.3|0.27<br>~~eee~~|VCCIO– 0.27<br>~~eee~~<br>~~eee~~<br>~~eee~~|8<br>~~eee~~<br>~~eee~~<br>~~eee~~|–8<br>~~eee~~<br>~~eee~~<br>~~eee~~|
|LVCMOS10R<br>~~ee~~<br>~~ee~~<br>~~a~~|—<br>~~ee~~<br>~~ee~~<br>~~ee~~|VREF– 0.10<br>~~ee~~<br>~~ee~~<br>~~ee~~|VREF+ 0.10<br>~~ee~~<br>~~ee~~<br>~~ee~~|VCCIO+<br>0.3<br>~~ee~~|—<br>~~eee~~<br>~~ee~~|—<br>~~eee~~<br>~~eee~~<br>~~ee~~|—<br>~~eee~~<br>~~eee~~<br>~~ee~~<br>~~ee~~|—<br>~~eee~~<br>~~eee~~<br>~~ee~~<br>~~ee~~|
|HSUL12<br>~~ee~~<br>~~a~~|—<br>~~ee~~<br>~~ee~~|VREF– 0.10<br>~~ee~~<br>~~ee~~|VREF+ 0.10<br>~~ee~~<br>~~ee~~|VCCIO+<br>0.3<br>~~ee~~|0.3<br>~~eee~~<br>~~ee~~|VCCIO– 0.3<br>~~eee~~<br>~~ee~~|8.0, 7.5,<br>6.25, 5<br>~~eee~~<br>~~ee~~<br>~~ee~~|-8.0, -7.5,<br>-6.25, -5<br>~~eee~~<br>~~ee~~<br>~~ee~~|
**Notes** :
1. For electro-migration, the average DC current drawn by the I/O pads within a bank of I/O shall not exceed 10 mA per I/O average.
2. For the types of I/O standard supported in which bank, refer to sysI/O User Guide for Nexus Platform (FPGA-TN-02067) for details.
3. Select “50RS” in driver strength is selecting 50 Ω series impedance driver.
**Table 4.16. I/O Resistance Characteristics**
|**Parameter**|**Description**|**Test Conditions**|**Min**|**Typ**|**Max**|**Unit**|
|---|---|---|---|---|---|---|
|50RS|Output Drive Resistance when 50RS<br>Drive Strength Selected|VCCIO= 1.8 V, 2.5 V, or 3.3 V|—|50|—|Ω|
|RDIFF|Input Differential Termination<br>Resistance|Bank 3, Bank 4, and Bank 5 for I/O<br>selected to be differential|—|100|—|Ω|
|SE Input<br>Termination|Input Single Ended Termination<br>Resistance|Bank 3, Bank 4, and Bank 5 for I/O<br>selected to be Single Ended|36|40|64|Ω|
||||46|50|80||
||||56|60|96||
||||71|75|120||
© 2021-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02049-1.8
109
**CrossLink-NX Family Data Sheet**
**Table 4.17. VIN Maximum Overshoot/Undershoot Allowance – Wide Range[1, 2]**
|**AC Voltage Overshoot**|**% of UI at –40 °C to 125 °C**|**AC Voltage Undershoot**|**% of UI at –40 °C to 125 °C**|
|---|---|---|---|
|VCCIO+ 0.4|100.0%|–0.4|100.0%|
|VCCIO+ 0.5|100.0%|–0.5|44.2%|
|VCCIO+ 0.6|94.0%|–0.6|10.1%|
|VCCIO+ 0.7|21.0%|–0.7|1.3%|
|VCCIO+ 0.8|10.2%|–0.8|0.3%|
|VCCIO+ 0.9|2.5%|–0.9|0.1%|
## **Notes:**
1. The peak overshoot or undershoot voltage and the duration above VCCIO + 0.2 V or below GND – 0.2 V must not exceed the values in this table.
2. For UI less than 20 µs.
**Table 4.18. VIN Maximum Overshoot/Undershoot Allowance – High Performance[1, 2]**
|**AC Voltage Overshoot**|**% of UI at –40 °C to 125 °C**|**AC Voltage Undershoot**|**% of UI at –40 °C to 125 °C**|
|---|---|---|---|
|VCCIO+ 0.5|100.0%|–0.5|100.0%|
|VCCIO+ 0.6|47.3%|–0.6|47.3%|
|VCCIO+ 0.7|10.9%|–0.7|10.9%|
|VCCIO+ 0.8|2.7%|–0.8|2.7%|
|VCCIO+ 0.9|0.7%|–0.9|0.7%|
## **Notes:**
1. The peak overshoot or undershoot voltage and the duration above VCCIO + 0.2 V or below GND – 0.2 V must not exceed the values in this table.
2. For UI less than 20 µs.
## **4.12. sysI/O Differential DC Electrical Characteristics**
## **4.12.1. LVDS**
LVDS input buffer on CrossLink-NX is operating with VCCAUX = 1.8 V and independent of Bank VCCIO voltage. LVDS output buffer is powered by the Bank VCCIO at 1.8 V.
LVDS can only be supported in Bank 3, Bank 4, and Bank 5. LVDS25 output can be emulated with LVDS25E in Bank 0, Bank 1, Bank 2, Bank 6, and Bank 7. This is described in LVDS25E (Output Only) section.
© 2021-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
110
FPGA-DS-02049-1.8
**CrossLink-NX Family**
**Data Sheet**
**Table 4.19. LVDS DC Electrical Characteristics[1 ]**
|**Parameter**<br>~~a~~|**Description**<br>~~a~~|**Test Conditions**<br>~~a~~|**Min**<br>~~a~~|**Typ**<br>~~a~~|**Max**<br>~~a~~|**Unit**<br>~~a~~|
|---|---|---|---|---|---|---|
|VINP, VINM<br>~~a~~|Input Voltage<br>~~a~~|—<br>~~a~~|0<br>~~a~~|—<br>~~a~~|1.60<br>~~a~~|V<br>~~a~~|
|VICM<br>~~ee~~|Input Common Mode Voltage<br>~~ee~~|Half the sum of the two Inputs<br>~~ee~~|0.05<br>~~ee~~|—<br>~~ee~~|1.552<br>~~ee~~|V<br>~~ee~~|
|VTHD<br>~~a~~|Differential Input Threshold<br>~~a~~|Difference between the two Inputs<br>~~a~~|±100<br>~~a~~|—<br>~~a~~|—<br>~~a~~|mV<br>~~a~~|
|IIN<br>~~a~~<br>~~a~~<br>~~eS~~|Input Current<br>~~a~~<br>~~a~~<br>|Power On or Power Off<br>~~a~~<br>~~a~~<br>|—<br>~~a~~<br>~~a~~<br>|—<br>~~a~~<br>~~a~~<br>|±10<br>~~a~~<br>~~a~~<br>|µA<br>~~a~~<br>~~a~~<br>|
|VOH<br>~~eS~~|Output High Voltage for VOPor VOM<br>|RT= 100 Ω<br>|—<br>|1.425<br>|1.60<br>|V<br>|
|VOL<br>~~eSa~~<br>~~ee~~|Output Low Voltage for VOPor VOM<br>~~a~~<br>|RT= 100 Ω<br>~~a~~<br>|0.9<br>~~a~~<br>|1.075<br>~~a~~<br>|—<br>~~a~~<br>|V<br>~~a~~<br>|
|VOD<br>~~ee~~|Output Voltage Differential<br>|(VOP- VOM), RT= 100 Ω<br>|250<br>|350<br>|450<br>|mV<br>|
|VOD<br>~~eea~~|Change in VODBetween High and<br>Low<br>~~a~~|—<br>~~a~~|—<br>~~a~~|—<br>~~a~~|50<br>~~a~~|mV<br>~~a~~|
|VOCM<br>~~a~~|Output Common Mode Voltage<br>~~a~~|(VOP+ VOM)/2, RT= 100 Ω<br>~~a~~|1.125<br>~~a~~|1.25<br>~~a~~|1.375<br>~~a~~|V<br>~~a~~|
|VOCM<br>~~a~~<br>~~a~~|Change in VOCM, VOCM(MAX)- VOCM(MIN)<br>~~a~~<br>~~a~~|—<br>~~a~~<br>~~a~~|—<br>~~a~~<br>~~a~~<br>~~ee~~|—<br>~~a~~<br>~~a~~<br>~~ee~~|50<br>~~a~~<br>~~a~~|mV<br>~~a~~<br>~~a~~|
|ISAB<br>~~a~~|Output Short Circuit Current<br>~~a~~<br>~~ee~~|VOD= 0 V Driver outputs shorted to<br>each other<br>~~a~~<br>~~ee~~|—<br>~~a~~<br>~~ee~~<br>~~ee~~|—<br>~~a~~<br>~~ee~~<br>~~ee~~|12<br>~~a~~<br>~~ee~~|mA<br>~~a~~<br>~~ee~~|
|VOS<br>~~a~~|Change in VOSbetween H and L<br>~~a~~|—<br>~~a~~|—<br>~~ee~~<br>~~a~~|—<br>~~ee~~<br>~~a~~|50<br>~~a~~|mV<br>~~a~~|
2. VICM is depending on VID, input differential voltage, so the voltage on pin cannot exceed VINP/INN(min/max) requirements. VICM(min) = VINP/INN(min) + ½ VID, VICM(max) = VINP/INN(max) – ½ VID. Values in the table is based on minimum VID of +/- 100 mV.
## **4.12.2. LVDS25E (Output Only)**
Three sides of the CrossLink-NX devices, Top, Left and Right, support LVDS25 outputs with emulated complementary LVCMOS outputs in conjunction with a parallel resistor across the driver outputs. The scheme shown in Figure 4.2 is one possible solution for point-to-point signals.
**Table 4.20. LVDS25E DC Conditions**
|**Parameter**<br>~~a~~|**Description**<br>~~a~~<br>~~a~~|**Typical**<br>~~a~~<br>~~a~~|**Unit**<br>~~a~~|
|---|---|---|---|
|VCCIO<br>~~a~~<br>~~a~~|Output Driver Supply (±5%)<br>~~a~~<br>~~a~~|2.50<br>~~a~~<br>~~a~~|V<br>~~a~~|
|ZOUT<br>~~a~~|Driver Impedance|20|Ω|
|RS<br>~~a~~<br>~~a~~|Driver Series Resistor (±1%)|158|Ω|
|RP<br>~~a~~|Driver Parallel Resistor (±1%)|140|Ω|
|RT<br>~~a~~<br>~~a~~|Receiver Termination (±1%)<br>~~a~~|100|Ω|
|VOH<br>~~a ~~<br>~~a~~|Output High Voltage<br> ~~a~~<br>~~a~~<br>~~a~~|1.43<br>~~a~~<br>~~a~~|V<br>~~a~~<br>~~a~~|
|VOL<br>~~a~~|Output Low Voltage<br>~~a~~|1.07<br>~~a~~|V<br>~~a~~|
|VOD<br>~~a~~<br>~~a~~|Output Differential Voltage<br>~~a~~<br>~~a~~<br>~~a~~|0.35<br>~~a~~<br>~~a~~|V<br>~~a~~<br>~~a~~|
|VCM<br>~~a~~|Output Common Mode Voltage|1.25|V|
|ZBACK<br>~~a~~<br>~~a~~|Back Impedance<br>~~a~~|100.5|Ω|
|IDC<br>~~a ~~<br>~~a~~|DC Output Current<br> ~~a~~<br>~~a~~|6.03<br>~~a~~|mA<br>~~a~~|
© 2021-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02049-1.8
111
**CrossLink-NX Family Data Sheet**
**==> picture [383 x 136] intentionally omitted <==**
**----- Start of picture text -----**<br>
VCCIO = 2.5 V (± 5%)<br>RS = 158<br>(± 1%)<br>8 mA<br>LVCMOS25<br>RP = 140 RT = 100 +<br>VCCIO = 2.5 V (± 5%) -<br>RS = 158 (± 1%) (± 1%)<br>(± 1%)<br>8 mA<br>LVCMOS25<br>Transmission line, Zo = 100 differential<br>ON-chip OFF-chip OFF-chip ON-chip<br>**----- End of picture text -----**<br>
**Figure 4.2. LVDS25E Output Termination Example**
## **4.12.3. SubLVDS (Input Only)**
SubLVDS is a reduced-voltage form of LVDS signaling, very similar to LVDS. It is a standard used in many camera types of applications, and follow the SMIA 1.0, Part 2: CCP2 Specification. Being similar to LVDS, the CrossLink-NX devices can support the subLVDS input signaling with the same LVDS input buffer. The output for subLVDS is implemented in subLVDSE/subLVDSEH with a pair of LVCMOS18 output drivers (see SubLVDSE/SubLVDSEH (Output Only) section).
**Table 4.21. SubLVDS Input DC Electrical Characteristics**
**==> picture [486 x 239] intentionally omitted <==**
**----- Start of picture text -----**<br>
Parameter Description Test Conditions Min Typ Max Unit<br>VID Input Differential Threshold Voltage Over VICM range 70 150 200 mV<br>—_—_———— VICM Input Common Mode Voltage Half the sum of the two Inputs 0.4 0.9 1.4 V<br>Sub-LVDS Driver PCB Traces, Connectors or Cables<br>Z0 = 50<br>+ +<br>RT = 100<br>100 differential ± 1%*<br>– –<br>Z0 = 50<br>Off-chip On-chip<br>**----- End of picture text -----**<br>
**Figure 4.3. SubLVDS Input Interface**
## **4.12.4. SubLVDSE/SubLVDSEH (Output Only)**
SubLVDS output uses a pair of LVCMOS18 drivers with True and Complement outputs. The VCCIO of the bank used for subLVDSE or subLVDSEH needs to be powered by 1.8 V. SubLVDSE is for Bank 0, Bank 1, Bank 2, Bank 5, and Bank 6; and subLVDSEH is for Bank 3, Bank 4, and Bank 5.
Performance of the subLVDSE/subLVDSEH driver is limited to the performance of LVCMOS18.
© 2021-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
112
FPGA-DS-02049-1.8
**CrossLink-NX Family**
**Data Sheet**
**Table 4.22. SubLVDS Output DC Electrical Characteristics**
**==> picture [489 x 511] intentionally omitted <==**
**----- Start of picture text -----**<br>
Parameter Description Test Conditions Min Typ Max Unit<br>VOD Output Differential Voltage Swing — — 150 — mV<br>es VOCM Output Common Mode Voltage Half the sum of the two Outputs — 0.9 — V<br>VCCIO = +1.8 V PCB Traces, Connectors or Cables<br>Z0 = 50<br>Rs = 267 ±1%<br>+ +<br>SubLVDS Output<br>SubLVDSE Rp = 121 ±1% 100 differential RT = 100 ±1% Sub-LVDS Recevier<br>SubLVDSEH<br>– –<br>Rs = 267 ±1%<br>Z0 = 50<br>aan<br>0<br>On-chip Off-chip On-chip Off-chip<br>Figure 4.4. SubLVDS Output Interface<br>4.12.5. SLVS<br>Scalable Low-Voltage Signaling (SLVS) is based on a point-to-point signaling method defined in the JEDEC JESD8-13<br>(SLVS-400) standard. This standard evolved from the traditional LVDS standard with smaller voltage swings and a lower<br>common-mode voltage. The 200 mV (400 mV p-p) SLVS swing contributes to a reduction in power.<br>The CrossLink-NX devices receive SLVS differential input with the LVDS input buffer. This LVDS input buffer is design to<br>cover wide input common mode range that can meet the SLVS input standard specified by the JEDEC standard.<br>Table 4.23. SLVS Input DC Characteristics<br>Parameter Description Test Conditions Min Typ Max Unit<br>VID Input Differential Threshold Voltage Over VICM range 70 — — mV<br>VICM Input Common Mode Voltage Half the sum of the two Inputs 70 200 330 mV<br>es ee<br>The SLVS output on CrossLink-NX is supported with the LVDS drivers found in Bank 3, Bank 4, and Bank 5. The LVDS<br>driver on CrossLink-NX is a current controlled driver. It can be configured as LVDS driver, or configured with the 100 Ω<br>differential termination with center-tap set to VOCM at 200 mV. This means the differential output driver can be placed<br>into bank with VCCIO = 1.2 V, 1.5 V, or 1.8 V, even if it is powered by VCCIO.<br>**----- End of picture text -----**<br>
**Table 4.24. SLVS Output DC Characteristics**
|**Parameter**|**Description**|**Test Conditions**|**Min**|**Typ**|**Max**|**Unit**|
|---|---|---|---|---|---|---|
|VCCIO|Bank VCCIO|—|–5%|1.2,<br>1.5,<br>1.8|+ 5%|V|
|VOD|Output Differential Voltage Swing|—|140|200|270|mV|
|VOCM|Output Common Mode Voltage|Half the sum of the two Outputs|150|200|250|mV|
|ZOS|Single-Ended Output Impedance|—|37.5|50|80|Ω|
© 2021-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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**CrossLink-NX Family Data Sheet**
**Figure 4.5. SLVS Interface**
## **4.12.6. Soft MIPI D-PHY**
When Soft D-PHY is implemented inside the FPGA logic, the I/O interface needs to use sysI/O buffers to connect to external D-PHY pins.
The CrossLink-NX sysI/O provides support for SLVS, as described in SLVS section, plus the LVCMOS12 input / output buffers together to support the High Speed (HS) and Low Power (LP) mode as defined in MIPI Alliance Specification for D-PHY.
To support MIPI D-PHY with SLVS (LVDS) and LVCMOS12, the bank VCCIO cannot be set to 1.5 V or 1.8 V. It must connect to 1.2 V or 1.1 V.
All other DC parameters are the same as listed in SLVS section. DC parameters for the LP driver and receiver are the same as listed in LVCMOS12.
© 2021-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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**CrossLink-NX Family Data Sheet**
**==> picture [356 x 344] intentionally omitted <==**
**----- Start of picture text -----**<br>
LVCMOS12<br>LP Data_P<br>LPenable<br>HSenabl e MIPI Receiver<br>100 Diff<br>+ +<br>HS Data Z0=50<br>- -<br>SLVS<br>LPenable<br>LP Data_N<br>LVCMOS12<br>MIPI_LP_RX<br>On-Chip<br>RXLP_P<br>MIPI Divider<br>+ +<br>HS Data Z0=50<br>- -<br>LVDS<br>MIPI_LP_RX<br>RXLP_N<br>**----- End of picture text -----**<br>
**Figure 4.6. MIPI Interface**
**Table 4.25. Soft D-PHY Input Timing and Levels**
|**Symbol**|**Description**|**Conditions**|**Min**|**Typ**|**Max**|**Unit**|
|---|---|---|---|---|---|---|
|**High Speed(Differential) Input DC Specifications**|||||||
|VCMRX(DC)|Common-mode Voltage in High Speed Mode|—|70|—|330|mV|
|VIDTH|Differential Input HIGH Threshold|—|70|—|—|mV|
|VIDTL|Differential Input LOW Threshold|—|—|—|-70|mV|
|VIHHS|Input HIGH Voltage(for HS mode)|—|—|—|460|mV|
|VILHS|Input LOW Voltage|—|–40|—|—|mV|
|VTERM-EN|Single-ended voltage for HS Termination Enable4|—|—|—|450|mV|
|ZID|Differential Input Impedance|—|80|100|125|Ω|
|**High Speed(Differential) Input AC Specifications**|||||||
|ΔVCMRX(HF)1|Common-mode Interference(>450 MHz)|—|—|—|100|mV|
|ΔVCMRX(LF)2, 3|Common-mode Interference(50 MHz - 450 MHz)|—|–50|—|50|mV|
|CCM|Common-mode Termination|—|||60|pF|
|**Low Power(Single-Ended) Input DC Specifications**|||||||
|VIH|Low Power Mode Input HIGH Voltage|—|820|—|—|mV|
|VIL|Low Power Mode Input LOW Voltage|—|—|—|480|mV|
|VIL-ULP|Ultra Low Power Input LOW Voltage|—|—|—|300|mV|
|VHYST|Low Power Mode Input Hysteresis|—|25|—|—|mV|
|℮SPIKE|Input Pulse Rejection|—|—|—|300|V∙ps|
© 2021-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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**CrossLink-NX Family Data Sheet**
|**Symbol**|**Description**|**Conditions**|**Min**|**Typ**|**Max**|**Unit**|
|---|---|---|---|---|---|---|
|TMIN-RX|Minimum Pulse Width Response|—|20|—|—|ns|
|VINT|Peak Interference Amplitude|—|—|—|200|mV|
|fINT|Interference Frequency|—|450|—|—|MHz|
**Notes** :
1. This is peak amplitude of sine wave modulated to the receiver inputs.
2. Input common-mode voltage difference compared to average common-mode voltage on the receiver inputs.
3. Exclude any static ground shift of 50 mV.
4. High Speed Differential RTERM is enabled when both DP and DN are below this voltage.
**Table 4.26. Soft D-PHY Output Timing and Levels**
|**Symbol**<br>~~a ~~|**Description**<br> ~~a~~|**Conditions**<br>~~GO~~|**Min**<br>~~GO~~|**Typ**<br>~~GO~~|**Max**<br>~~GO~~|**Unit**<br>~~GO~~|
|---|---|---|---|---|---|---|
|**High Speed(Differential) Output DC Specifications**<br>~~eeeG~~|||||||
|VCMTX<br>~~ee~~|Common-mode Voltage in High Speed Mode<br>~~eG~~|—<br>~~eG~~|135<br>~~eG~~|200<br>~~eG~~|250<br>~~eG~~|mV<br>~~eG~~|
||ΔVCMTX(1,0)|<br>~~ee~~<br>~~a~~<br>~~a~~|VCMTXMismatch Between Differential HIGH<br>and LOW<br>~~eG~~<br>~~ee~~|—<br>~~eG~~|—<br>~~eG~~|—<br>~~eG~~|15<br>~~eG~~|mV<br>~~eG~~|
||VOD|<br>~~a~~<br>~~a~~<br>~~a~~<br>~~ee~~|Output Differential Voltage<br>~~ee~~<br>~~ee~~<br>||D-PHY-P – D-PHY-<br>N|<br>~~ee~~<br>|100<br>~~ee~~<br>|200<br>~~ee~~<br>|270<br>|mV<br>|
||ΔVOD|<br>~~a~~<br>~~ee~~|VODMismatch Between Differential HIGH and<br>LOW<br>~~ee~~<br>~~ee~~<br>|—<br>~~ee~~<br>|—<br>~~ee~~<br>|—<br>~~ee~~<br>|50<br>|mV<br>|
|VOHHS<br>~~ee~~<br>~~ee~~|Single-Ended Output HIGH Voltage<br>~~ee~~<br>~~eG~~<br>|—<br>~~ee~~<br>~~eG~~<br>|—<br>~~ee~~<br>~~eG~~<br>|—<br>~~ee~~<br>~~eG~~<br>|385<br>~~eG~~<br>|mV<br>~~eG~~<br>|
|ZOS<br>~~ee~~<br>~~ee~~|Single Ended Output Impedance<br>~~ee~~<br>~~eG~~<br>~~GO~~|—<br>~~ee~~<br>~~eG~~<br>~~GO~~|37.5<br>~~ee~~<br>~~eG~~<br>~~GO~~|50<br>~~ee~~<br>~~eG~~<br>~~GO~~|80<br>~~eG~~<br>~~GO~~|Ω<br>~~eG~~<br>~~GO~~|
|ΔZOS<br><br>~~ee~~<br>~~a ~~|ZOSmismatch<br>~~eG~~<br><br> ~~a~~|—<br>~~eG~~<br><br>~~GO~~|—<br>~~eG~~<br><br>~~GO~~|—<br>~~eG~~<br><br>~~GO~~|20<br>~~eG~~<br><br>~~GO~~|%<br>~~eG~~<br><br>~~GO~~|
|**High Speed(Differential) Output AC Specifications**<br>~~eea~~<br>~~GO~~|||||||
|ΔVCMTX(LF)<br>~~ee~~<br>~~ee~~|Common-Mode Variation, 50 MHz–450 MHz<br>~~a~~<br>~~eG~~|—<br>~~GO~~<br>~~eG~~|—<br>~~GO~~<br>~~eG~~|—<br>~~GO~~<br>~~eG~~|30<br>~~GO~~<br>~~eG~~|mVRMS<br>~~GO~~<br>~~eG~~|
|ΔVCMTX(HF)<br>~~ee~~<br>~~ee~~|Common-Mode Variation, above 450 MHz<br>~~a~~<br>~~eG~~|—<br>~~GO~~<br>~~eG~~|—<br>~~GO~~<br>~~eG~~|—<br>~~GO~~<br>~~eG~~|17<br>~~GO~~<br>~~eG~~|mVRMS<br>~~GO~~<br>~~eG~~|
|tR<br>~~ee~~<br>~~a~~|Output 20%–80% Rise Time<br>Output 80%–20% Fall Time<br>~~eG~~|0.08 Gbps ≤ tR≤ 1.00<br>Gbps<br>~~eG~~|—<br>~~eG~~|—<br>~~eG~~|0.35<br>~~eG~~|UI<br>~~eG~~|
|tF<br>~~a~~|Output Data Valid After CLK Output|0.08 Gbps ≤ tF≤ 1.00<br>Gbps|—|—|0.27|UI|
|**Low Power(Single-Ended) Output DC Specifications**<br>~~a~~|||||||
|VOH<br>~~a~~|Low Power Mode Output HIGH Voltage<br>|0.08 Gbps – 1.5 Gbps<br>|1.07<br>|1.2<br>|1.3<br>|V<br>|
|VOL<br>~~eG~~<br>~~ee~~|Low Power Mode Input LOW Voltage<br>~~eG~~<br>~~eG~~|—<br>~~eG~~<br>~~eG~~|–50<br>~~eG~~<br>~~eG~~|—<br>~~eG~~<br>~~eG~~|50<br>~~eG~~<br>~~eG~~|mV<br>~~eG~~<br>~~eG~~|
|ZOLP<br>~~eG~~<br>~~ee~~|Output Impedance in Low Power Mode<br>~~eG~~<br>~~eG~~|—<br>~~eG~~<br>~~eG~~|110<br>~~eG~~<br>~~eG~~|—<br>~~eG~~<br>~~eG~~|—<br>~~eG~~<br>~~eG~~|Ω<br>~~eG~~<br>~~eG~~|
|**Low Power(Single-Ended) Output AC Specifications**<br>~~eeeG~~<br>~~eeeG~~|||||||
|tRLP<br>~~ee~~<br>~~ee~~|15%–85% Rise Time<br>~~eG~~<br>~~a~~|—<br>~~eG~~<br>~~GO~~|—<br>~~eG~~<br>~~GO~~|—<br>~~eG~~<br>~~GO~~|25<br>~~eG~~<br>~~GO~~|ns<br>~~eG~~<br>~~GO~~|
|tFLP<br>~~ee~~<br>~~ee~~|85%–15% Fall Time<br>~~eG~~<br>~~a~~|—<br>~~eG~~<br>~~GO~~|—<br>~~eG~~<br>~~GO~~|—<br>~~eG~~<br>~~GO~~|25<br>~~eG~~<br>~~GO~~|ns<br>~~eG~~<br>~~GO~~|
|tREOT<br>~~ee~~<br>~~eG~~|HS – LP Mode Rise and Fall Time, 30%–85%<br>~~a~~<br>~~eG~~|—<br>~~GO~~<br>~~eG~~|—<br>~~GO~~<br>~~eG~~|—<br>~~GO~~<br>~~eG~~|35<br>~~GO~~<br>~~eG~~|ns<br>~~GO~~<br>~~eG~~|
|TLP-PULSE-TX<br>~~eG~~<br>~~a~~<br>~~ee~~|Pulse Width of the LP Exclusive-OR Clock<br>~~eG~~<br>~~a~~|First LP XOR Clock<br>Pulse after STOP<br>State or Last Pulse<br>before STOP State<br>~~eG~~<br>~~eee~~|40<br>~~eG~~<br>~~eee~~|—<br>~~eG~~<br>~~eee~~|—<br>~~eG~~<br>~~eee~~|ns<br>~~eG~~<br>~~eee~~|
|||All Other Pulses<br>~~eee~~<br>~~GO~~|20<br>~~eee~~<br>~~GO~~|—<br>~~eee~~<br>~~GO~~|—<br>~~eee~~<br>~~GO~~|ns<br>~~eee~~<br>~~GO~~|
|TLP-PER-TX<br>~~ee~~<br>~~ee~~|Period of the LP Exclusive-OR Clock<br>~~a~~<br>~~D~~|—<br>~~GO~~<br>~~D~~|90<br>~~GO~~<br>~~D~~|—<br>~~GO~~<br>~~D~~|—<br>~~GO~~<br>~~D~~|ns<br>~~GO~~<br>~~D~~|
|CLOAD<br>~~ee~~<br>~~ee~~|Load Capacitance<br>~~a~~<br>~~D~~|—<br>~~GO~~<br>~~D~~|0<br>~~GO~~<br>~~D~~|—<br>~~GO~~<br>~~D~~|70<br>~~GO~~<br>~~D~~|pF<br>~~GO~~<br>~~D~~|
© 2021-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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**CrossLink-NX Family Data Sheet**
**Table 4.27. Soft D-PHY Clock Signal Specification**
|**Symbol**<br>**Description**|**Conditions**|**Min**|**Typ**|**Max**|**Unit**|
|---|---|---|---|---|---|
|**Clock Signal Specification**||||||
|UI<br>Instantaneous<br>UIINST|—|—|—|12.5|ns|
||—|–10%|—|10%|UI|
|UI Variation<br>∆UI||||||
||—|–5%|—|5%|UI|
|**Table 4.28. Soft D-PHY Data-Clock Timing Specifications**<br>**Symbol**<br>**Description**<br>**Conditions**<br>**Min**<br>**Typ**<br>**Max**<br>**Unit**<br>**Data-Clock Timing Specifications**<br>TSKEW[TX]<br>Data to Clock Skew<br>0.08 Gbps ≤ TSKEW[TX]<br>≤ 1.00 Gbps<br>-0.15<br>—<br>0.158<br>UIINST<br>TSKEW[TLIS]<br>Data to Clock Skew<br>0.08 Gbps ≤ TSKEW[TLIS]<br>≤ 1.00 Gbps<br>-0.20<br>—<br>0.20<br>UIINST<br>TSETUP[RX]<br>Input Data Setup Before CLK<br>0.08 Gbps ≤ TSETUP[RX]<br>≤ 1.00 Gbps<br>0.173<br>—<br>—<br>UI<br>THOLD[RX]<br>Input Data Hold After CLK<br>0.08 Gbps ≤ THOLD[RX]<br>≤ 1.00 Gbps<br>0.195<br>—<br>—<br>UI<br>~~aSsi~~||||||
|**4.12.7. Differential HSTL15D (Output Only)**||||||
|Differential HSTL outputs are implemented as a pair of complementary single-ended HSTL outputs.||||||
## **4.12.8. Differential SSTL135D, SSTL15D (Output Only)**
Differential SSTL is used for differential clock in DDR3/DDR3L memory interface. All differential SSTL outputs are implemented as a pair of complementary single-ended SSTL outputs. All allowable single-ended output classes (class I and class II) are supported.
## **4.12.9. Differential HSUL12D (Output Only)**
Differential HSUL is used for differential clock in LPDDR2/LPDDR3 memory interface. All differential HSUL outputs are implemented as a pair of complementary single-ended HSUL12 outputs. All allowable single-ended drive strengths are supported.
## **4.12.10. Differential LVCMOS25D, LVCMOS33D, LVTTL33D (Output Only)**
Differential LVCMOS and LVTTL outputs are implemented as a pair of complementary single-ended outputs. All allowable single-ended output drive strengths are supported.
## **4.13. Maximum sysI/O Buffer Speed**
|**Buffer**<br>~~———~~|**Description**<br>~~———~~|**Banks**<br>~~———~~|**Max**<br>~~———~~|**Unit**<br>~~———~~|
|---|---|---|---|---|
|**Maximum sysI/O Input Frequency**<br>~~———~~|||||
|**Single-Ended**<br>~~———~~|||||
|LVCMOS33<br>~~———~~|LVCMOS33, VCCIO= 3.3 V<br>~~———~~|0, 1, 2, 6, 7<br>~~———~~|200<br>~~———~~|MHz<br>~~———~~|
|LVTTL33<br>~~———~~|LVTTL33, VCCIO= 3.3 V<br>~~———~~|0, 1, 2, 6, 7<br>~~———~~|200<br>~~———~~|MHz<br>~~———~~|
|LVCMOS25<br>~~———~~|LVCMOS25, VCCIO= 2.5 V<br>~~———~~|0, 1, 2, 6, 7<br>~~———~~|200<br>~~———~~|MHz<br>~~———~~|
|LVCMOS185<br>~~———~~|LVCMOS18, VCCIO= 1.8 V<br>~~———~~|0, 1, 2, 6, 7<br>~~———~~|200<br>~~———~~|MHz<br>~~———~~|
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**CrossLink-NX Family Data Sheet**
|**Buffer**<br>~~a~~|**Description**|**Banks**|**Max**|**Unit**|
|---|---|---|---|---|
|LVCMOS18H<br>~~a~~|LVCMOS18, VCCIO= 1.8 V|3, 4, 5|200|MHz|
|LVCMOS155<br>~~a~~<br>~~a~~|LVCMOS15, VCCIO= 1.5 V|0, 1, 2, 6, 7|100|MHz|
|LVCMOS15H5<br>~~a~~|LVCMOS15, VCCIO= 1.5 V|3, 4, 5|150|MHz|
|LVCMOS125<br>~~a~~|LVCMOS12, VCCIO= 1.2 V|0, 1, 2, 6, 7|50|MHz|
|LVCMOS12H5<br>~~aC~~|LVCMOS12, VCCIO= 1.2 V<br>~~aC~~|3, 4, 5<br>~~aC~~|100<br>~~aC~~|MHz<br>~~aC~~|
|LVCMOS105<br>~~a~~|LVCMOS 1.0, VCCIO= 1.2 V|0, 1, 2, 6, 7|50|MHz|
|LVCMOS10H5<br>~~aC~~|LVCMOS 1.0, VCCIO= 1.0 V<br>~~aC~~|3, 4, 5<br>~~aC~~|50<br>~~aC~~|MHz<br>~~aC~~|
|LVCMOS10R<br>~~a~~|LVCMOS 1.0, VCCIOindependent|3, 4, 5|50|MHz|
|SSTL15_I, SSTL15_II<br>~~aC~~|SSTL_15, VCCIO= 1.5 V<br>~~aC~~|3, 4, 5<br>~~aC~~|1066<br>~~aC~~|Mbps<br>~~aC~~|
|SSTL135_I, SSTL135_II<br>~~a~~|SSTL_135, VCCIO= 1.35 V|3, 4, 5|1066|Mbps|
|HSUL12<br>~~a~~<br>~~Rs~~|HSUL_12, VCCIO= 1.2 V<br>~~Rs~~|3, 4, 5<br>~~Rs~~|1066<br>~~Rs~~|Mbps<br>~~Rs~~|
|HSTL15<br>~~Rs~~<br>~~a~~|HSTL15, VCCIO= 1.5 V<br>~~Rs~~|3, 4, 5<br>~~Rs~~|250<br>~~Rs~~|Mbps<br>~~Rs~~|
|MIPI D-PHY (LP Mode)<br>~~SC~~|MIPI, Low Power Mode, VCCIO= 1.2 V<br>~~SC~~|3, 4, 5<br>~~SC~~|10<br>~~SC~~|Mbps<br>~~SC~~|
|**Differential8 **<br>~~TT~~<br> ~~;~~|||||
|LVDS<br> ~~;~~|LVDS, VCCIOindependent QFN72, caBGA256,<br>csBGA289, and caBGA400<br>~~;~~|3, 4, 5|1250|Mbps|
||LVDS, VCCIOindependent csfBGA121<br>~~;~~|3, 4, 5|1500|Mbps|
|subLVDS<br> ~~;~~<br>~~pf~~|subLVDS, VCCIOindependent QFN72,<br>caBGA256, csBGA289, and caBGA400<br>~~;~~<br>~~pf~~|3, 4, 5<br>~~ft~~|1250<br>~~ft~~|Mbps|
||subLVDS, VCCIOindependent csfBGA121<br>~~pf~~|3, 4, 5<br>~~ft~~|1500<br>~~ft~~|Mbps|
|SLVS|SLVS similar to MIPI HS, VCCIOindependent<br>QFN72, caBGA256, csBGA289, caBGA400|3, 4, 5|1250|Mbps|
||SLVS similar to MIPI HS, VCCIOindependent<br>csfBGA121|3, 4, 5|1500|Mbps|
|MIPI D-PHY (HS Mode)|MIPI, High Speed Mode, VCCIO= 1.2 V<br>QFN72|3, 4, 5|1250|Mbps|
||MIPI, High Speed Mode, VCCIO= 1.2 V<br>csfBGA121, caBGA256, csBGA289, caBGA400|3, 4, 5|1500|Mbps|
|SSTL15D<br>~~es~~|Differential SSTL15, VCCIOindependent<br>~~es~~|3, 4, 5<br>~~es~~|1066<br>~~es~~|Mbps<br>~~es~~|
|SSTL135D<br>~~es~~<br>~~es~~|Differential SSTL135, VCCIOindependent<br>~~es~~<br>~~es~~|3, 4, 5<br>~~es~~<br>~~es~~|1066<br>~~es~~<br>~~es~~|Mbps<br>~~es~~<br>~~es~~|
|HUSL12D<br>~~es~~<br>~~es~~|Differential HSUL12, VCCIOindependent<br>~~es~~<br>~~es~~|3, 4, 5<br>~~es~~<br>~~es~~|1066<br>~~es~~<br>~~es~~|Mbps<br>~~es~~<br>~~es~~|
|HSTL15D<br>~~es~~<br>~~a~~|Differential HSTL15, VCCIOindependent<br>~~es~~|3, 4, 5<br>~~es~~|250<br>~~es~~|Mbps<br>~~es~~|
|**Maximum sysI/O Output Frequency**<br>~~a~~<br>~~TT~~|||||
|**Single-Ended**<br>~~TT~~|||||
|LVCMOS33 (all drive strengths)<br>~~TT~~<br>~~YO~~|LVCMOS33, VCCIO= 3.3 V<br>~~TT~~<br>~~YO~~|0, 1, 2, 6, 7<br>~~TT~~<br>~~YO~~|200<br>~~TT~~<br>~~YO~~|MHz<br>~~TT~~<br>~~YO~~|
|LVCMOS33 (RS50)<br>~~YO~~<br>~~a~~|LVCMOS33, VCCIO= 3.3 V, RSERIES= 50 Ω<br>~~YO~~|0, 1, 2, 6, 7<br>~~YO~~|200<br>~~YO~~|MHz<br>~~YO~~|
|LVTTL33 (all drive strengths)<br>~~a~~|LVTTL33, VCCIO= 3.3 V|0, 1, 2, 6, 7|200|MHz|
|LVTTL33 (RS50)<br>~~a~~<br>~~SO~~|LVTTL33, VCCIO= 3.3 V, RSERIES= 50 Ω<br>~~SO~~|0, 1, 2, 6, 7<br>~~SO~~|200<br>~~SO~~|MHz<br>~~SO~~|
|LVCMOS25 (all drive strengths)<br>~~SO~~<br>~~a~~|LVCMOS25, VCCIO= 2.5 V<br>~~SO~~|0, 1, 2, 6, 7<br>~~SO~~|200<br>~~SO~~|MHz<br>~~SO~~|
|LVCMOS25 (RS50)<br>~~a~~<br>~~a~~|LVCMOS25, VCCIO= 2.5 V, RSERIES= 50 Ω|0, 1, 2, 6, 7|200|MHz|
|LVCMOS18 (all drive strengths)<br>~~aC~~|LVCMOS18, VCCIO= 1.8 V<br>~~aC~~|0, 1, 2, 6, 7<br>~~aC~~|200<br>~~aC~~|MHz<br>~~aC~~|
|LVCMOS18 (RS50)<br>~~a~~|LVCMOS18, VCCIO= 1.8 V, RSERIES= 50 Ω<br>~~f~~|0, 1, 2, 6, 7|200|MHz|
© 2021-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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|**Buffer**<br>~~**p**O~~|**Description**|**Banks**|**Max**|**Unit**|
|---|---|---|---|---|
|LVCMOS18H (all drive strengths)<br>~~**p**O~~<br>~~po~~|LVCMOS18, VCCIO= 1.8 V<br>~~p~~|3, 4, 5<br>~~p~~|200<br>~~p~~|MHz<br>~~p~~|
|LVCMOS18H (RS50)<br>~~po~~<br>~~pO~~|LVCMOS18, VCCIO= 1.8 V, RSERIES= 50 Ω<br>~~p~~|3, 4, 5<br>~~p~~|200<br>~~p~~|MHz<br>~~p~~|
|LVCMOS15 (all drive strengths)<br>~~po~~<br>~~pO~~|LVCMOS15, VCCIO= 1.5 V|0, 1, 2, 6, 7|100|MHz|
|LVCMOS15H (all drive strengths)<br>~~pO~~<br>~~GD~~<br>~~po~~|LVCMOS15, VCCIO= 1.5 V<br>~~GD~~|3, 4, 5<br>~~GD~~|150<br>~~GD~~|MHz<br>~~GD~~|
|LVCMOS12 (all drive strengths)<br>~~GD~~<br>~~po~~<br>~~pO~~|LVCMOS12, VCCIO= 1.2 V<br>~~GD~~|0, 1, 2, 6, 7<br>~~GD~~|50<br>~~GD~~|MHz<br>~~GD~~|
|LVCMOS12H (all drive strengths)<br>~~po~~<br>~~pO~~<br>~~po~~|LVCMOS12, VCCIO= 1.2 V|3, 4, 5|100|MHz|
|LVCMOS10H (all drive strengths)<br>~~pO~~<br>~~po~~<br>~~**p**O~~|LVCMOS12, VCCIO= 1.2 V|3, 4, 5|50|MHz|
|SSTL15_I, SSTL15_II<br>~~po~~<br>~~**p**O~~|SSTL_15, VCCIO= 1.5 V|3, 4, 5|1066|Mbps|
|SSTL135_I, SSTL135_II<br>~~**p**O~~|SSTL_135, VCCIO= 1.35 V<br>~~p~~|3, 4, 5<br>~~p~~|1066<br>~~p~~|Mbps<br>~~p~~|
|HSUL12 (all drive strengths)<br>~~I~~<br>~~po~~|HSUL_12, VCCIO= 1.2 V<br>~~I~~|3, 4, 5<br>~~I~~|1066<br>~~I~~|Mbps<br>~~I~~|
|HSTL15<br>~~po~~<br>~~**p**O~~|HSTL15, VCCIO= 1.5 V|3, 4, 5|250|Mbps|
|MIPI D-PHY (LP Mode)<br>~~po~~<br>~~**p**O~~|MIPI, Low Power Mode, VCCIO= 1.2 V|3, 4, 5|10|Mbps|
|**Differential8 **<br>~~**p**O~~<br>~~T~~|||||
|LVDS<br>~~a~~|LVDS, VCCIO= 1.8 V QFN72, caBGA256,<br>csBGA289, and caBGA400<br>~~a~~|3, 4, 5<br>~~a~~|1250<br>~~a~~|Mbps<br>~~a~~|
||LVDS, VCCIO= 1.8 V csfBGA121<br>~~a~~<br>~~a~~|3, 4, 5<br>~~a~~<br>~~a~~|1500<br>~~a~~<br>~~a~~|Mbps<br>~~a~~<br>~~a~~|
|LVDS25E6<br>~~a~~<br>~~pp~~|LVDS25, Emulated, VCCIO= 2.5 V<br>~~a~~<br>~~a~~<br>~~pp~~|0, 1, 2, 6, 7<br>~~a~~<br>~~a~~<br>~~pp~~|400<br>~~a~~<br>~~a~~<br>~~pp~~|Mbps<br>~~a~~<br>~~a~~<br>~~pp~~|
|SubLVDSE6<br>~~I~~<br>~~po~~|subLVDS, Emulated, VCCIO= 1.8 V<br>~~I~~|0, 1, 2, 6, 7<br>~~I~~|400<br>~~I~~|Mbps<br>~~I~~|
|SubLVDSEH6<br>~~po~~|subLVDS, Emulated, VCCIO= 1.8 V|3, 4, 5|800|Mbps|
|SLVS<br>~~po~~|SLVS similar to MIPI, VCCIO= 1.2 V<br>QFN72, caBGA256, csBGA289, caBGA400|3, 4, 5|1250|Mbps|
||SLVS similar to MIPI, VCCIO= 1.2 V<br>csfBGA121|3, 4, 5|1500|Mbps|
|MIPI D-PHY (HS Mode)|MIPI, High Speed Mode, VCCIO= 1.2 V<br>QFN72|3, 4, 5|1250|Mbps|
||MIPI, High Speed Mode, VCCIO= 1.2 V<br>csfBGA121, caBGA256, csBGA289, caBGA400|3, 4, 5|1500|Mbps|
|SSTL15D<br>~~a~~|Differential SSTL15, VCCIO= 1.5 V|3, 4, 5|1066|Mbps|
|SSTL135D<br>~~a~~<br>~~pp~~<br>~~**p**O~~|Differential SSTL135, VCCIO= 1.35 V<br>~~pp~~|3, 4, 5<br>~~pp~~|1066<br>~~pp~~|Mbps<br>~~pp~~|
|HUSL12D<br>~~**p**O~~|Differential HSUL12, VCCIO= 1.2 V|3, 4, 5|1066|Mbps|
|HSTL15D<br>~~**p**O~~|Differential HSTL15, VCCIO= 1.5 V<br>~~O~~|3, 4, 5<br>~~O~~|250<br>~~O~~|Mbps<br>~~O~~|
**Notes** :
1. Maximum I/O speed is the maximum switching rate of the I/O operating within the guidelines of the defining standard. The actual interface speed performance using the I/O also depends on other factors, such as internal and external timing.
2. These numbers are characterized but not test on every device.
3. Performance is specified in MHz, as defined in clock rate when the sysI/O is used as pin. For data rate performance, this can be converted to Mbps, which equals to 2 times the clock rate.
4. LVCMOS and LVTTL are measured with load specified in Table 4.50.
5. These LVCMOS inputs can be placed in different VCCIO voltage. Performance may vary. Please refer to Lattice Design Software
6. These emulated outputs performance is based on externally properly terminated as described in LVDS25E (Output Only) and SubLVDSE/SubLVDSEH (Output Only).
7. All speeds are measured with fast slew.
8. For maximum differential I/O performance only Differential I/O should be placed in the bottom I/O banks. If this is not possible, the following will impact on maximum performance:
- a. If Fast Slew Rate LVCMOS I/O are used, they should be limited to no more than nine I/O (adjacent), four I/O (same bank), 55 I/O (left/right banks) to keep degradation below 50%.
- b. If non-Differential I/O (SLOW SLEW) are placed on the bottom but not within the same bank as differential I/O, then the maximum Differential performance is degraded to 70% of original when 21 aggressors are toggling.
© 2021-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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**CrossLink-NX Family Data Sheet**
- c. If non-Differential I/O (SLOW SLEW) are placed within the same bank as Differential I/O then the maximum performance is degraded to 50% of original when 16 aggressor are toggling.
- d. No performance impact if MIPI LP and MIPI HS are in the same bank.
- e. If Differential RX/TX I/O are both placed within the same bank then the maximum performance is degraded to 90%.
- f. For DDR3/3L, LPDDR2/3 separate DQ/DQS groups from Address/Commands/CLK groups into separate banks.
## **4.14. Typical Building Block Function Performance**
These building block functions can be generated using Lattice Design Software Tool. Exact performance may vary with the device and the design software tool version. The design software tool uses internal parameters that have been characterized but are not tested on every device.
## **Table 4.30. Pin-to-Pin Performance**
|**Function**|**Typ. @ VCC =**<br>**1.0 V**|**Unit**|
|---|---|---|
|16-bit Decoder (I/O configured with LVCMOS18, Left and Right Banks)|5.5|ns|
|16-bit Decoder (I/O configured with HSTL15_I, Bottom Banks)|5.1|ns|
|16:1 Mux (I/O configured with LVCMOS18, Left and Right Banks)|6|ns|
|16:1 Mux (I/O configured with HSTL15_I, Bottom Banks)|6.1|ns|
**Note** : These functions are generated using Lattice Radiant Design Software tool. Exact performance may vary with the device and the design software tool version. The design software tool uses internal parameters that have been characterized but are not tested on every device.
## **Table 4.31. Register-to-Register Performance**
|**Function**|**Typ. @ VCC =**<br>**1.0 V**|**Unit**|
|---|---|---|
|**Basic Functions**|||
|16-bit Adder<br>~~a~~|5002<br>~~a~~|MHz<br>~~a~~|
|32-bit Adder<br>~~eG~~|496<br>~~eG~~|MHz<br>~~eG~~|
|16-bit Counter<br>~~eG~~<br>~~a~~|402<br>~~eG~~<br>~~a~~|MHz<br>~~eG~~<br>~~a~~|
|32-bit Counter<br>~~a~~|371<br>~~a~~|MHz<br>~~a~~|
|**Embedded Memory Functions**|||
|512 × 36 Single Port RAM, with Output Register<br>~~a~~|5002<br>~~a~~|MHz<br>~~a~~|
|1024 × 18 True-Dual Port RAM using same clock, with EBR Output Registers<br>~~pf~~|5002<br>~~pf~~|MHz<br>~~pf~~|
|1024 × 18 True-Dual Port RAM using asynchronous clocks, with EBR Output Registers<br>~~pf~~<br>~~a~~|5002<br>~~pf~~<br>~~a~~|MHz<br>~~pf~~<br>~~a~~|
|**Large Memory Functions**<br>~~Pe~~|||
|32k × 32 Single Port RAM, with Output Register<br>~~pf~~|1652<br>~~pf~~|MHz<br>~~pf~~|
|32k × 32 Single Port RAM with ECC, with Output Register<br>~~a~~|1302<br>~~a~~|MHz<br>~~a~~|
|32k × 32 True-Dual Port RAM using same clock, with Output Registers<br>~~a~~|340<br>~~a~~|MHz<br>~~a~~|
|**Distributed Memory Functions**<br>~~a~~<br>~~Pe~~|||
|16 × 4 Single Port RAM (One PFU)<br>~~a~~|5002<br>~~a~~|MHz<br>~~a~~|
|16 × 2 Pseudo-Dual Port RAM (One PFU)<br>~~a~~<br>~~a~~|5002<br>~~a~~<br>~~a~~|MHz<br>~~a~~<br>~~a~~|
|16 × 4 Pseudo-Dual Port (Two PFUs)<br>~~a~~|5002<br>~~a~~|MHz<br>~~a~~|
|**DSP Functions**<br>~~a~~<br>~~pn~~|||
|9 × 9 Multiplier with Input Output Registers<br>~~pn~~<br>~~a~~|340<br>~~pn~~<br>~~a~~|MHz<br>~~pn~~<br>~~a~~|
|18 × 18 Multiplier with Input/Output Registers<br>~~a~~<br>~~a~~|260<br>~~a~~<br>~~a~~|MHz<br>~~a~~<br>~~a~~|
|36 × 36 Multiplier with Input/Output Registers<br>~~eG~~|184<br>~~eG~~|MHz<br>~~eG~~|
|MAC 18 × 18 with Input/Output Registers<br>~~eG~~<br>~~a~~|189<br>~~eG~~<br>~~a~~|MHz<br>~~eG~~<br>~~a~~|
|MAC 18 × 18 with Input/Pipelined/Output Registers<br>~~a~~|260<br>~~a~~|MHz<br>~~a~~|
|MAC 36 × 36 with Input/Output Registers<br>~~a~~<br>~~a~~|111<br>~~a~~<br>~~a~~|MHz<br>~~a~~<br>~~a~~|
© 2021-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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|**Function**|**Typ. @ VCC =**<br>**1.0 V**|**Unit**|
|---|---|---|
|MAC 36 × 36 with Input/Pipelined/Output Registers|145|MHz|
**Notes** :
1. The Clock port is configured with LVDS I/O type. Performance Grade: 9_High-Performance_1.0V.
2. Limited by the Minimum Pulse Width of the component
3. These functions are generated using Lattice Radiant Design software tool. Exact performance may vary with the device and the design software tool version. The design software tool uses internal parameters that have been characterized but are not tested on every device.
4. For the Pipelined designs, the number of pipeline stages used are 2.
## **4.15. LMMI**
Table 4.32 summarizes the performance of the LMMI interface with supported IPs. Additional timing requirement and constraint can be identified through the Lattice Radiance design tools.
**Table 4.32. LMMI FMAX Summary**
|**IP**|**FMAX (MHz)**|
|---|---|
|CDR0|73|
|CDR1|70|
|DPHY0|67|
|DPHY1|55|
|CRE|54|
|I2C|38|
|PCIe|57|
|PLL_ULC|59|
|PLL_LLC|55|
|PLL_LRC|37|
## **4.16. Derating Timing Tables**
Logic timing provided in the following sections of this data sheet and the Lattice Radiant design tools are worst case numbers in the operating range. Actual delays at nominal temperature and voltage for best case process, can be much better than the values given in the tables. The Lattice Radiant design tool can provide logic timing numbers at a particular temperature and voltage.
© 2021-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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**CrossLink-NX Family Data Sheet**
## **4.17. External Switching Characteristics**
Over recommended commercial operating conditions.
**Table 4.33. External Switching Characteristics (VCC = 1.0 V)**
|**Parameter**<br>~~a~~|**Description**<br>~~|~~<br>~~a~~|–**7 Auto**<br>~~|~~<br>~~a~~|–**7 Auto**<br>~~|~~<br>~~a~~|**Unit**<br>~~a~~|
|---|---|---|---|---|
|||**Min**<br>~~|~~<br>~~a~~|**Max**<br>~~a~~||
|**Clocks**<br>~~pe~~|||||
|**Primary Clock**<br>~~pn~~|||||
|fMAX_PRI<br>~~a~~<br>~~ee~~|Frequencyfor PrimaryClock|—|276|MHz|
|tW_PRI<br>~~ee~~|Clock Pulse Width for PrimaryClock|1.59|—|ns|
|tSKEW_PRI6<br>~~ee~~<br>~~a~~|PrimaryClock Skew Within a Device<br>|—<br>|653<br>|ps<br>|
|**Edge Clock**<br>~~pn~~|||||
|fMAX_EDGE<br>~~a~~|Frequencyfor Edge Clock Tree<br>|—<br>|551.7<br>|MHz<br>|
|tW_EDGE<br>~~Ce~~<br>~~es~~|Clock Pulse Width for Edge Clock<br>~~Ce~~|0.761<br>~~Ce~~|—<br>~~Ce~~|ns<br>~~Ce~~|
|tSKEW_EDGE6<br>~~es~~|Edge Clock Skew Within a Device|—|174|ps|
|**Generic SDR Input**<br>~~es~~<br>~~pt~~|||||
|**General I/O Pin Parameters Using Dedicated Primary Clock Input without PLL**<br>~~En~~|||||
|tCO<br>~~En~~<br>~~a~~|Clock to Output – PIO Output Register<br>~~En~~|—<br>~~En~~|7.91<br>~~En~~|ns<br>~~En~~|
|tSU<br>~~a~~<br>~~**e**s~~|Clock to Data Setup– PIO Input Register|0|—|ns|
|tH<br>~~**e**s~~|Clock to Data Hold – PIO Input Register|3.95|—|ns|
|tSU_DEL<br>~~**e**s~~<br>~~es~~|Clock to Data Setup– PIO Input Register with Data Input Delay<br>~~e~~|1.86<br>~~e~~|—<br>~~e~~|ns<br>~~e~~|
|tH_DEL<br>~~es~~|Clock to Data Hold – PIO Input Register with Data Input Delay|0.26|—|ns|
|**General I/O Pin Parameters Using Dedicated Primary Clock Input with PLL**<br>~~es~~<br>~~pn~~<br>~~es~~|||||
|tCOPLL<br>~~es~~<br>~~es~~|Clock to Output – PIO Output Register|—|5.57|ns|
|tSUPLL<br>~~es~~<br>~~es~~|Clock to Data Setup– PIO Input Register|1.31|—|ns|
|tHPLL<br>~~es~~<br>~~a~~<br>~~es~~|Clock to Data Hold - PIO Input Register|1.44|—|ns|
|tSU_DELPLL<br>~~a~~<br>~~es~~|Clock to Data Setup- PIO Input Register with Data Input Delay|4.99|—|ns|
|tH_DELPLL<br>~~es~~<br>~~a~~|Clock to Data Hold - PIO Input Register with Data Input Delay<br>|0<br>|—<br>|ns<br>|
|**Generic DDR Input/Output**<br>~~pe~~|||||
|**Generic DDRX1 Inputs/Outputs with Clock and Data Centered at Pin (GDDRX1_RX/TX.SCLK.Centered) using PCLK Clock Input**–<br>**Bank 0, Bank 1, Bank 2, Bank 6, and Bank 7 –Figure 4.7andFigure 4.9**|||||
|tSU_GDDR1<br>~~a~~|Input Data Setup Before CLK|0.917<br>~~a~~|—<br>~~ee~~|ns|
|||0.275<br>~~a~~|—<br>~~ee~~|UI|
|tHO_GDDR1<br>~~a~~<br>~~a~~|Input Data Hold After CLK<br>~~a~~|0.917<br>~~a~~<br>~~a~~|—<br>~~ee~~<br>|ns<br>|
|||0.275<br>~~aa~~|—<br>~~a~~|UI<br>~~a~~|
|tDVB_GDDR1<br>~~a~~<br>~~a~~<br>~~a~~|Output Data Valid After CLK Output<br>~~a~~<br>~~a~~|1.008<br>~~aa~~<br>~~aee~~|—<br>~~a~~|ns<br>~~a~~|
|||–0.659<br>~~aee~~|—|ns + 1/2 UI|
|tDQVA_GDDR1<br><br>~~a~~<br>~~es~~|Output Data Valid After CLK Output<br>|1.008<br>~~ee~~<br>~~ee~~|—<br>~~ee~~|ns<br>~~ee~~|
|||–0.659<br>~~ee~~<br>~~ee~~|—<br>~~ee~~|ns + 1/2 UI<br>~~ee~~|
|fDATA_GDDRX1<br><br>~~a~~<br>~~es~~<br>~~es~~|Input/Output Data Rate<br>|—<br>~~ee~~<br>~~ee~~|300<br>~~ee~~|Mbps<br>~~ee~~|
|fMAX_GDDRX1<br>~~es~~<br>~~es~~<br>~~es~~|Frequencyof PCLK<br>|—<br>~~ee~~<br>|150<br>~~ee~~<br>|MHz<br>~~ee~~<br>|
|½ UI<br>~~es~~<br>~~es~~|Half of Data Bit Time, or 90 degree<br>|1.667<br>|—<br>|ns<br>|
|Output TX to Input RX Marginper Edge<br>~~esa~~||0.091<br>~~a~~|—<br>~~a~~|ns<br>~~a~~|
|**Generic DDRX1 Inputs/Outputs with Clock and Data Aligned at Pin (GDDRX1_RX/TX.SCLK.Aligned) using PCLK Clock Input –**<br>**Bank 0, Bank 1, Bank 2, Bank 6, and Bank 7 –Figure 4.8 andFigure 4.10**<br>~~a~~<br>~~ee~~<br>~~a~~|||||
|tDVA_GDDR1|Input Data Valid After CLK|—<br>~~a~~<br>~~a~~|-0.917<br>~~a~~<br>~~ee~~<br>|ns + 1/2 UI<br>~~a~~<br>|
|||—<br>~~a~~<br>~~a~~|0.75<br>~~a~~<br>~~ee~~<br>|ns<br>~~a~~<br>|
|||—<br>~~es~~|0.225<br>~~es~~|UI<br>~~es~~|
© 2021-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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**CrossLink-NX Family**
**Data Sheet**
|**Parameter**<br>~~a~~|**Description**<br>~~|~~<br>~~a~~|–**7 Auto**<br>~~|~~<br>~~a~~|–**7 Auto**<br>~~|~~<br>~~a~~|**Unit**<br>~~a~~|
|---|---|---|---|---|
|||**Min**<br>~~|~~<br>~~a~~|**Max**<br>~~a~~||
|tDVE_GDDR1<br>~~Pe~~|Input Data Hold After CLK<br>~~Pe~~|0.917<br>~~a~~<br>~~Pe~~|—<br>~~a~~<br>~~a~~<br>~~Pe~~|ns + 1/2 UI<br>~~a~~<br>~~Pe~~|
|||2.583<br>~~Pe~~|—<br>~~Pe~~|ns<br>~~Pe~~|
|||0.775<br>~~Pe~~<br>~~a ~~|—<br>~~Pe~~<br> ~~a~~|UI<br>~~Pe~~|
|tDIA_GDDR1<br>~~eG~~|Output Data Invalid After CLK Output<br>~~eG~~|—<br>~~eG~~|0.659<br>~~eG~~|ns<br>~~eG~~|
|tDIB_GDDR1|Output Data Invalid Before CLK Output|—|0.659|ns|
|fDATA_GDDRX1<br>~~a~~|Input/Output Data Rate<br>~~a~~|—<br>~~a~~|300<br>~~a~~|Mbps<br>~~a~~|
|fMAX_GDDRX1<br>~~a~~|Frequency for PCLK<br>~~a~~|—<br>~~a~~|150<br>~~a~~|MHz<br>~~a~~|
|½ UI<br>~~a~~|Half of Data Bit Time, or 90 degree<br>~~a~~|1.667<br>~~a~~|—<br>~~a~~|ns<br>~~a~~|
|Output TX to Input RX Margin per Edge<br>~~a~~||0.091<br>~~a~~|—<br>~~a~~|ns<br>~~a~~|
|**Generic DDRX1 Inputs/Outputs with Clock and Data Centered at Pin (GDDRX1_RX/TX.SCLK.Centered) using PCLK Clock Input**–<br>**Bank 3, Bank 4, and Bank 5 –Figure 4.7andFigure 4.9**<br>~~es~~|||||
|tSU_GDDR1<br>~~es~~|Input Data Setup Before CLK<br>~~es~~|0.917<br>~~es~~|—<br>~~es~~|ns<br>~~es~~|
|||0.275<br>~~es~~<br>~~ee~~|—<br>~~es~~<br>~~ee~~|UI<br>~~es~~<br>~~ee~~|
|tHO_GDDR1<br>~~a~~|Input Data Hold After CLK<br>|0.917<br>|—<br>|ns<br>|
|tDVB_GDDR1<br>~~es~~<br>~~ee~~|Output Data Valid After CLK Output<br>~~es~~|1.227<br>~~es~~<br>~~a~~|—<br>~~es~~|ns<br>~~es~~|
|||–0.439<br>~~es~~<br>~~a~~|—<br>~~es~~|ns + 1/2 UI<br>~~es~~|
|tDQVA_GDDR1<br>~~ee~~|Output Data Valid After CLK Output|1.227<br>~~a~~|—|ns|
|||–0.439<br>~~a~~<br>~~a~~|—|ns + 1/2 UI|
|fDATA_GDDRX1<br>~~ee~~<br>~~a~~|Input/Output Data Rate|—<br>~~a~~|300|Mbps|
|fMAX_GDDRX1<br>~~a~~<br>~~a~~<br>~~es~~|Frequency of PCLK<br>|—<br>|150<br>|MHz<br>|
|½ UI<br>~~a~~<br>~~es~~|Half of Data Bit Time, or 90 degree<br>|1.667<br>|—<br>|ns<br>|
|Output TX to Input RX Margin per Edge<br>~~esa~~||0.311<br>~~a~~|—<br>~~a~~|ns<br>~~a~~|
|**Generic DDRX1 Inputs/Outputs with Clock and Data Aligned at Pin (GDDRX1_RX/TX.SCLK.Aligned) using PCLK Clock Input –**<br>**Bank 3, Bank 4, and Bank 5 –Figure 4.8 andFigure 4.10**|||||
|tDVA_GDDR1|Input Data Valid After CLK<br>~~**|**~~|—<br>~~pf~~<br>~~ee~~|-0.9167<br>~~pf~~<br>~~ee~~|ns + 1/2 UI<br>~~pf~~|
|||—<br>~~pf~~<br>~~ee~~<br>~~**|**~~|0.75<br>~~pf~~<br>~~ee~~|ns<br>~~pf~~|
|||—<br>~~ee ~~<br>~~**|**~~|0.225<br> ~~ee~~|UI|
|tDVE_GDDR1<br>~~i~~|Input Data Hold After CLK<br>~~**|**~~<br>~~i~~|0.9167<br>~~**|**~~<br>~~i~~|—<br>~~i~~|ns + 1/2 UI<br>~~i~~|
|||2.5833<br>~~i~~<br>~~a~~|—<br>~~i~~|ns<br>~~i~~|
|||0.775<br>~~i~~<br>~~a ~~|—<br>~~i~~<br> ~~a~~|UI<br>~~i~~|
|tDIA_GDDR1<br>~~a~~|Output Data Invalid After CLK Output<br>~~a~~|—<br>~~a~~|0.439<br>~~a~~|ns<br>~~a~~|
|tDIB_GDDR1<br>~~a~~<br>~~a~~|Output Data Invalid Before CLK Output<br>~~a~~<br>~~a~~|—<br>~~a~~<br>~~a~~|0.439<br>~~a~~<br>~~a~~|ns<br>~~a~~<br>~~a~~|
|fDATA_GDDRX1<br>~~a~~|Input/Output Data Rate<br>~~a~~|—<br>~~a~~|300<br>~~a~~|Mbps<br>~~a~~|
|fMAX_GDDRX1<br>~~a~~|Frequency for PCLK<br>~~a~~|—<br>~~a~~|150<br>~~a~~|MHz<br>~~a~~|
|½ UI<br>~~a~~<br>~~a~~<br>~~ce~~|Half of Data Bit Time, or 90 degree<br>~~a~~<br>~~a~~|1.667<br>~~a~~<br>~~a~~|—<br>~~a~~<br>~~a~~|ns<br>~~a~~<br>~~a~~|
|Output TX to Input RX Margin per Edge<br>~~ce~~||0.311|—|ns|
© 2021-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02049-1.8
123
**CrossLink-NX Family Data Sheet**
|**Parameter**|**Description**|–**7 Auto**|–**7 Auto**|**Unit**|
|---|---|---|---|---|
|||**Min**|**Max**||
|**Generic DDRX2 Inputs/Outputs with Clock and Data Centered at Pin (GDDRX2_RX/TX.ECLK.Centered) using PCLK Clock Input –**<br>**Figure 4.7 andFigure 4.9**<br>~~aaa~~<br>~~ee~~<br>~~a~~|||||
|tSU_GDDRX2<br>~~ee~~|Data Setup before CLK Input|0.270<br>~~a~~|—|ns|
|||0.162<br>~~a~~|—|UI|
|tHO_GDDRX2<br>~~ee~~<br>~~a~~|Data Hold after CLK Input<br>|0.270<br>~~a~~<br>|—<br>|ns<br>|
|tDVB_GDDRX2<br>~~ee~~<br>~~es~~|Output Data Valid Before CLK Output<br>~~es~~|0.658<br>~~a~~<br>~~es~~|—<br>~~es~~|ns<br>~~es~~|
|||–0.176<br>~~es~~<br>~~a~~|—<br>~~es~~|ns + 1/2 UI<br>~~es~~|
|tDQVA_GDDRX2<br>~~a~~|Output Data Valid After CLK Output|0.658<br>~~a~~|—|ns|
|||–0.176<br>~~a~~|—|ns + 1/2 UI|
|fDATA_GDDRX2<br>~~Ce~~<br>~~ee~~|Input/Output Data Rate<br>~~Ce~~|—<br>~~Ce~~|600<br>~~Ce~~|Mbps<br>~~Ce~~|
|fMAX_GDDRX2<br>~~ee~~<br>~~ee~~|Frequencyfor ECLK|—|300|MHz|
|½ UI<br>~~ee~~<br>~~ee~~<br>~~es~~|Half of Data Bit Time, or 90 degree<br>|0.833<br>|—<br>|ns<br>|
|fPCLK<br>~~ee~~<br>~~es~~|PCLK frequency<br>|—<br>|209.97<br>|MHz<br>|
|Output TX to Input RX Marginper Edge<br>~~esa~~||0.408<br>~~a~~|—<br>~~a~~|ns<br>~~a~~|
|**Generic DDRX2 Inputs/Outputs with Clock and Data Aligned at Pin (GDDRX2_RX/TX.ECLK.Aligned) using PCLK Clock Input –**<br>**Figure 4.8 andFigure 4.10**<br>~~es~~|||||
|tDVA_GDDRX2|Input Data Valid After CLK|—<br>~~es~~|–0.458|ns + 1/2 UI|
|||—<br>~~es~~<br>~~a ee~~|0.375<br>~~ee~~|ns<br>~~ee~~|
|||—<br>~~a ee~~<br>~~a~~|0.225<br>~~ee~~|UI<br>~~ee~~|
|tDVE_GDDRX2<br>~~ee~~|Input Data Hold After CLK|0.458<br>~~a~~|—|ns + 1/2 UI|
|||1.292<br>~~a ~~|—<br> ~~a~~|ns|
|||0.775<br>~~a~~|—|UI|
|tDIA_GDDRX2<br>~~ee~~|Output Data Invalid After CLK Output|—<br>~~a~~|0.176|ns|
|tDIB_GDDRX2<br>~~ee~~<br>~~a~~<br>~~es~~|Output Data Invalid Before CLK Output|—<br>~~a~~|0.176|ns|
|fDATA_GDDRX2<br>~~es~~|Input/Output Data Rate|—|600|Mbps|
|fMAX_GDDRX2<br>~~es~~<br>~~a~~|Frequencyfor ECLK<br>|—<br>|300<br>|MHz<br>|
|½ UI<br>~~aee~~<br>~~es~~|Half of Data Bit Time, or 90 degree<br>~~ee~~<br>|0.589<br>~~ee~~<br>|—<br>~~ee~~<br>|ns<br>~~ee~~<br>|
|fPCLK<br>~~ee~~<br>~~es~~|PCLK frequency<br>~~ee~~<br>|—<br>~~ee~~<br>|209.97<br>~~ee~~<br>|MHz<br>~~ee~~<br>|
|Output TX to Input RX Marginper Edge<br>~~esa~~||0.091<br>~~a~~|—<br>~~a~~|ns<br>~~a~~|
|**Generic DDRX4 Inputs/Outputs with Clock and Data Centered at Pin (GDDRX4_RX/TX.ECLK.Centered) using PCLK Clock Input –**<br>**Figure 4.7 andFigure 4.9**<br>~~a~~|||||
|tSU_GDDRX4<br>~~a~~<br>~~es~~|Input Data Set-Up Before CLK<br>~~a~~<br>|0.220<br>~~a~~|—<br>~~a~~|ns<br>~~a~~|
|||0.220<br>~~a~~<br>~~a~~<br>|—<br>~~a~~<br>~~a~~<br>|UI<br>~~a~~<br>|
|tHO_GDDRX4<br>~~es~~|Input Data Hold After CLK<br>|0.220<br>~~a~~<br>|—<br>~~a~~<br>|ns<br>|
|tDVB_GDDRX4<br>~~eses~~<br>~~a~~|Output Data Valid Before CLK Output<br>~~es~~|0.324<br>~~a ~~<br>~~es~~<br>~~ee~~|—<br> ~~a~~<br>~~es~~<br>~~ee~~|—<br>~~es~~<br>~~ee~~|
|||–0.176<br>~~es~~<br>~~ee~~|—<br>~~es~~<br>~~ee~~|—<br>~~es~~<br>~~ee~~|
|tDQVA_GDDRX4<br>~~es~~<br>~~a~~<br>~~**e**s~~|Input/Output Data Rate<br>~~es~~|0.324<br>~~es~~<br>~~ee~~|—<br>~~es~~<br>~~ee~~|—<br>~~es~~<br>~~ee~~|
|||–0.176<br>~~ee~~<br>~~a~~|—<br>~~ee~~<br>~~a~~|—<br>~~ee~~|
|fDATA_GDDRX4<br>~~**e**s~~|Frequencyfor ECLK|—<br>~~a~~|1000<br>~~a~~|Mbps|
|fMAX_GDDRX4<br>~~**e**s~~|PCLK frequency<br>~~G~~|—<br>~~a ~~<br>~~G~~|500<br> ~~a~~<br>~~G~~|MHz<br>~~G~~|
|½ UI<br>~~a~~<br>~~es~~|Half of Data Bit Time, or 90 degree<br>|0.5<br>|—<br>|ns<br>|
|fPCLK<br>~~a~~<br>~~es~~|Input Data Set-UpBefore CLK<br>|—<br>|125<br>|MHz<br>|
|Output TX to Input RX Marginper Edge<br>~~esa~~||0.124<br>~~a~~|—<br>~~a~~|ns<br>~~a~~|
|**Generic DDRX4 Inputs/Outputs with Clock and Data Aligned at Pin (GDDRX4_RX/TX.ECLK.Aligned) using PCLK Clock Input, Left**<br>**and Right sides Only –Figure 4.8 andFigure 4.10**|||||
|tDVA_GDDRX4|Input Data Valid After CLK|—<br>~~a~~|–0.275<br>~~a~~|ns + 1/2 UI<br>~~a~~|
|||—<br>~~a~~<br>~~ee~~|0.225<br>~~a~~|ns<br>~~a~~|
|||—<br>~~ee~~|0.225|UI|
© 2021-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
124
FPGA-DS-02049-1.8
**CrossLink-NX Family Data Sheet**
|**Parameter**<br>~~ee~~|**Description**<br>~~|~~|–**7 Auto**<br>~~|~~|–**7 Auto**<br>~~|~~|**Unit**|
|---|---|---|---|---|
|||**Min**<br>~~|~~|**Max**||
|tDVE_GDDRX4<br>~~ee~~|Input Data Hold After CLK<br>~~|~~|0.275<br>~~|~~<br>~~aa~~|—<br>~~aa~~|ns + 1/2 UI<br>~~aa~~|
|||0.775<br>~~|~~<br>~~a~~|—<br>~~a~~|ns|
|||0.775<br>~~a~~|—<br>~~a~~|UI|
|tDIA_GDDRX4<br>~~a~~|Output Data Invalid After CLK Output<br>|—<br>|0.176<br>|ns<br>|
|tDIB_GDDRX4<br>|Output Data Invalid Before CLK Output<br>|—<br>|0.176<br>|ns<br>|
|fDATA_GDDRX4<br>~~eG~~|Input/Output Data Rate<br>~~eG~~|—<br>~~eG~~|1000<br>~~eG~~|Mbps<br>~~eG~~|
|fMAX_GDDRX4<br>~~a~~|Frequencyfor ECLK<br>|—<br>~~ee~~<br>|500<br>~~ee~~<br>|MHz<br>~~ee~~<br>|
|½ UI<br>~~ee~~<br>~~a~~|Half of Data Bit Time, or 90 degree<br>~~ee~~<br>|0.5<br>~~ee~~<br>~~ee~~<br>|—<br>~~ee~~<br>~~ee~~<br>|ns<br>~~ee~~<br>~~ee~~<br>|
|fPCLK<br>~~a CO~~|PCLK frequency<br>~~CO~~|—<br>~~ee~~<br>~~CO~~|125<br>~~ee~~<br>~~CO~~|MHz<br>~~ee~~<br>~~CO~~|
|Output TX to Input RX Marginper Edge<br>~~Oo~~||0.049<br>~~Oo~~|—<br>~~Oo~~|ns<br>~~Oo~~|
|**Generic DDRX5 Inputs/Outputs with Clock and Data Centered at Pin (GDDRX5_RX/TX.ECLK.Centered) using PCLK Clock Input –**<br>**Figure 4.7 andFigure 4.9**<br>~~Oo~~|||||
|tSU_GDDRX5<br>~~a~~<br>~~ee~~|Input Data Set-Up Before CLK|0.22<br>~~a~~|—|ns|
|||0.22<br>~~a~~|—|UI|
|tHO_GDDRX5<br>~~ee~~|Input Data Hold After CLK|0.22|—|ns|
|tWINDOW_GDDRX5C<br>~~ee~~<br>~~a~~|Input Data Valid Window<br>|0.44<br>|—<br>|ns<br>|
|tDVB_GDDRX5<br>~~fp~~|Output Data Valid Before CLK Output<br>~~fp~~|0.324<br>~~fp~~|—<br>~~fp~~|ns<br>~~fp~~|
|||–0.176<br>~~fp~~<br>~~a~~|—<br>~~fp~~|ns+1/2UI<br>~~fp~~|
|tDQVA_GDDRX5<br>~~a~~<br>~~es~~|Output Data Valid After CLK Output|0.324<br>~~a~~|—|ns|
|||–0.176<br>~~a~~|—|ns+1/2UI|
|fDATA_GDDRX5<br>~~a~~<br>~~es~~|Input/Output Data Rate|—<br>~~a~~|1000|Mbps|
|fMAX_GDDRX5<br>~~es~~<br>~~a~~<br>~~ee~~|Frequencyfor ECLK<br>|—<br>|500<br>|MHz<br>|
|½ UI<br>~~ee~~|Half of Data Bit Time, or 90 degree<br>|0.5<br>|—<br>|ns<br>|
|fPCLK<br>~~eea~~|PCLK frequency<br>~~a~~|—<br>~~a~~|100<br>~~a~~|MHz<br>~~a~~|
|Output TX to Input RX Marginper Edge<br>~~a~~<br>~~a~~||0.124<br>~~a~~<br>~~a~~|—<br>~~a~~<br>~~a~~|ns<br>~~a~~<br>~~a~~|
|**Generic DDRX5 Inputs/Outputs with Clock and Data Aligned at Pin (GDDRX5_RX/TX.ECLK.Aligned) using PCLK Clock Input, Left**<br>**and Right sides Only –Figure 4.8 andFigure 4.10**<br>~~a~~|||||
|tDVA_GDDRX5|Input Data Valid After CLK|—<br>~~a~~|–0.275<br>~~a~~<br>~~a~~|ns + 1/2 UI<br>~~a~~|
|||—<br>~~a~~<br>~~a~~<br>~~ee~~|0.225<br>~~a~~<br>~~a~~|ns<br>~~a~~|
|||—<br>~~ee~~<br>~~a~~|0.225<br>~~ee ee~~|UI<br>~~ee~~|
|tDVE_GDDRX5|Input Data Hold After CLK|0.275<br>~~ee~~<br>~~a~~<br>~~ee~~|—<br>~~ee ee~~|ns + 1/2 UI<br>~~ee~~|
|||0.775<br>~~a~~<br>~~ee~~|—<br>~~ee ee~~|ns<br>~~ee~~|
|||0.775<br>~~ee~~<br>~~a~~|—<br>~~a~~|UI|
|tWINDOW_GDDRX5A<br>~~a~~<br>~~**e**e~~|Input Data Valid Window|0.55<br>~~a ~~|—<br> ~~a~~|ns|
|tDIA_GDDRX5<br>~~**e**e~~|Output Data Invalid After CLK Output|—|0.176|ns|
|tDIB_GDDRX5<br>~~**e**e~~|Output Data Invalid Before CLK Output<br>~~G~~|—<br>~~G~~|0.176<br>~~G~~|ns<br>~~G~~|
|fDATA_GDDRX5<br>~~a~~|Input/Output Data Rate|—|1000|Mbps|
|fMAX_GDDRX5<br>~~a~~<br>~~a~~|Frequencyfor ECLK|—|500|MHz|
|½ UI<br>~~a~~<br>~~a~~<br>~~ee~~|Half of Data Bit Time, or 90 degree<br>|0.5<br>|—<br>|ns<br>|
|fPCLK<br>~~ee~~|PCLK frequency<br>|—<br>|100<br>|MHz<br>|
|Output TX to Input RX Marginper Edge<br>~~eea~~||0.049<br>~~a~~|—<br>~~a~~|ns<br>~~a~~|
© 2021-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02049-1.8
125
**CrossLink-NX Family Data Sheet**
|**Parameter**<br>~~a~~|**Description**<br>~~a~~|**Description**<br>~~a~~|–**7 Auto**<br>~~a~~|–**7 Auto**<br>~~a~~|**Unit**<br>~~a~~|
|---|---|---|---|---|---|
||||**Min**<br>~~a~~|**Max**<br>~~a~~||
|**Soft D-PHY DDRX4 Inputs/Outputs with Clock and Data Centered at Pin, using PCLK Clock Input**||||||
|tSU_GDDRX4_MP<br>~~es~~|Input Data Set-Up Before CLK<br>~~es~~||0.21<br>~~es~~|—<br>~~es~~|ns<br>~~es~~|
||||0.21<br>~~es~~|—<br>~~es~~|UI<br>~~es~~|
|tHO_GDDRX4_MP<br>~~es~~<br>~~aee~~|Input Data Hold After CLK<br>~~es~~||0.2<br>~~es~~|—<br>~~es~~|ns<br>~~es~~|
||||0.2<br>~~es~~|—<br>~~es~~|UI<br>~~es~~|
|tDVB_GDDRX4_MP<br>~~ee~~|Output Data Valid Before CLK Output||0.3|—|ns|
||||0.3|—|UI|
|tDQVA_GDDRX4_MP<br>~~ee~~<br>~~a~~|Output Data Valid After CLK Output<br>||0.3<br>|—<br>|ns<br>|
||||0.3<br>|—<br>|UI<br>|
|fDATA_GDDRX4_MP<br>~~ass~~<br>~~es~~|Input Data Bit Rate for MIPI PHY<br>~~ss~~|csfBGA121<br>~~ss~~|—<br>~~ss~~|1000<br>~~ss~~|Mbps<br>~~ss~~|
|||caBGA256<br>~~ss~~<br>~~Py~~|—<br>~~ss~~<br>~~Py~~|1000<br>~~ss~~<br>~~Py~~|Mbps<br>~~ss~~<br>~~Py~~|
|½ UI<br>~~ss~~<br>~~es~~<br>~~es~~|Half of Data Bit Time, or 90 degree<br>~~ss~~<br>~~Py~~<br>||0.5<br>~~ss~~<br>~~Py~~<br>|—<br>~~ss~~<br>~~Py~~<br>|ns<br>~~ss~~<br>~~Py~~<br>|
|fPCLK<br>~~es~~<br>~~es~~|PCLK frequency<br>~~Py~~<br>||—<br>~~Py~~<br>|125<br>~~Py~~<br>|MHz<br>~~Py~~<br>|
|Output TX to Input RX Marginper Edge<br>~~esa~~|||0.1<br>~~a~~|—<br>~~a~~|ns<br>~~a~~|
|**Video DDRX71 Inputs/Outputs with Clock and Data Aligned at Pin (GDDRX71_RX.ECLK) using PLL Clock Input –Figure 4.12 and**<br>**Figure 4.13**||||||
|tRPBi_DVA<br>~~a~~<br>~~ee~~|Input Valid Bit "i" switch from CLK Rising Edge ("i" = 0 to 6, 0 aligns with<br>CLK)<br>~~a~~<br>~~es~~||—<br>~~a~~<br>~~es~~|0.277<br>~~a~~<br>~~es~~|UI<br>~~a~~<br>~~es~~|
||||—<br>~~a~~<br>~~es~~|–0.278<br>~~a~~<br>~~es~~|ns+(1/2+i)×UI<br>~~a~~<br>~~es~~|
|tRPBi_DVE<br>~~a~~<br>~~ee~~|Input Hold Bit "i" switch from CLK Rising Edge ("i" = 0 to 6, 0 aligns with<br>CLK)<br>~~a~~<br>~~es~~||0.711<br>~~a~~<br>~~es~~|—<br>~~a~~<br>~~es~~|UI<br>~~a~~<br>~~es~~|
||||0.263<br>~~es~~|—<br>~~es~~|ns+(1/2+i)×UI<br>~~es~~|
|tTPBi_DOV<br>~~ee~~<br>~~i~~|Data Output Valid Bit "i" switch from CLK Rising Edge ("i" = 0 to 6, 0 aligns<br>with CLK)<br>~~es~~||—<br>~~es~~|0.187<br>~~es~~|ns+i×UI<br>~~es~~|
|tTPBi_DOI<br>~~i~~<br>~~es~~|Data Output Invalid Bit "i" switch from CLK Rising Edge ("i" = 0 to 6, 0 aligns<br>with CLK)||-0.187|—|ns+(i+ 1)×UI|
|tTPBi_skew_UI<br>~~es~~|TX skew in UI||—|0.150|UI|
|tB<br>~~es~~<br>~~a~~<br>~~es~~|Serial Data Bit Time, = 1UI||1.247|—|ns|
|fDATA_TX71<br>~~a~~<br>~~es~~<br>~~ee~~|DDR71 Serial Data Rate||—|802|Mbps|
|fMAX_TX71<br>~~es~~<br>~~ee~~<br>~~es~~|DDR71 ECLK Frequency<br>||—<br>|401<br>|MHz<br>|
|fCLKIN<br>~~ee~~<br>~~es~~|7:1 Clock(PCLK)Frequency<br>||—<br>|113.4<br>|MHz<br>|
|Output TX to Input RX Marginper Edge<br>~~esa~~|||0.187<br>~~a~~|—<br>~~a~~|ns<br>~~a~~|
|**Memory Interface**||||||
|**DDR3/DDR3L/LPDDR2/LPDDR3 READ(DQ Input Data are Aligned to DQS) –Figure 4.8**||||||
|tDVBDQ_DDR3<br>tDVBDQ_DDR3L<br>tDVBDQ_LPDDR2<br>tDVBDQ_LPDDR3|Data Input Valid before DQS Input||—|–0.277|ns + 1/2 UI|
|tDVADQ_DDR3<br>tDVADQ_DDR3L<br>tDVADQ_LPDDR2<br>tDVADQ_LPDDR3|Data Input Valid after DQS Input||0.277|—|ns + 1/2 UI|
|fDATA_DDR3<br>fDATA_DDR3L<br>fDATA_LPDDR2<br>fDATA_LPDDR3|DDR Memory Data Rate||—|904|Mb/s|
|fMAX_ECLK_DDR3<br>fMAX_ECLK_DDR3L<br>fMAX_ECLK_LPDDR2<br>fMAX_ECLK_LPDDR3|DDR Memory ECLK Frequency||—|452|MHz|
© 2021-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
126
FPGA-DS-02049-1.8
**CrossLink-NX Family Data Sheet**
|**Parameter**|**Description**|–**7 Auto**|–**7 Auto**|**Unit**|
|---|---|---|---|---|
|||**Min**|**Max**||
|fMAX_SCLK_DDR3<br>fMAX_SCLK_DDR3L<br>fMAX_SCLK_LPDDR2<br>fMAX_SCLK_LPDDR3|DDR Memory SCLK Frequency|—|113|MHz|
|**DDR3/DDR3L/LPDDR2/LPDDR3 WRITE(DQ Output Data are Centered to DQS) –Figure 4.11**|||||
|tDQVBS_DDR3<br>tDQVBS_DDR3L<br>tDQVBS_LPDDR2<br>tDQVBS_LPDDR3|Data Output Valid before DQS Output|—|–0.277|ns + 1/2 UI|
|tDQVAS_DDR3<br>tDQVAS_DDR3L<br>tDQVAS_LPDDR2<br>tDQVAS_LPDDR3|Data Output Valid after DQS Output|0.277|—|ns + 1/2 UI|
|fDATA_DDR3<br>fDATA_DDR3L<br>fDATA_LPDDR2<br>fDATA_LPDDR3|DDR Memory Data Rate|—|904|Mb/s|
|fMAX_ECLK_DDR3<br>fMAX_ECLK_DDR3L<br>fMAX_ECLK_LPDDR2<br>fMAX_ECLK_LPDDR3|DDR Memory ECLK Frequency|—|452|MHz|
|fMAX_SCLK_DDR3<br>fMAX_SCLK_DDR3L<br>fMAX_SCLK_LPDDR2<br>fMAX_SCLK_LPDDR3|DDR Memory SCLK Frequency|—|113|MHz|
**Notes** :
1. Commercial timing numbers are shown. Industrial numbers are typically slower and can be extracted from the Lattice Radiant software.
2. General I/O timing numbers are based on LVCMOS 1.8, 8 mA, Fast Slew Rate, 0 pF load. Generic DDR timing are numbers based on LVDS I/O. DDR3 timing numbers are based on SSTL15. LPDDR2 and LPDDR3 timing numbers are based on HSUL12.
3. Uses LVDS I/O standard for measurements.
4. Maximum clock frequencies are tested under best case conditions. System performance may vary depending on the user environment.
5. All numbers are generated with the Lattice Radiant software.
6. This clock skew is not the internal clock network skew. The Nexus family devices have very low internal clock network skew that can be approximated to 0 ps. These tSKEW values measured externally at system level includes additional skew added by the I/O, wire bonding and package ball.
**==> picture [301 x 129] intentionally omitted <==**
**----- Start of picture text -----**<br>
Rx CLK (in)<br>es es<br>Rx DATA (in)<br>er<br>tSU tSU<br>tHD tHD<br>**----- End of picture text -----**<br>
**Figure 4.7. Receiver RX.CLK.Centered Waveforms**
© 2021-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02049-1.8
127
**CrossLink-NX Family Data Sheet**
**==> picture [423 x 153] intentionally omitted <==**
**----- Start of picture text -----**<br>
½ UI<br>½ UI<br>1 UI<br>Rx CLK (in)<br>or DQS input<br>Rx DATA (in)<br>or DQS input<br>RR<br>tDVA/tDVADQ<br>tDVA/tDVADQ<br>tDVE/tDVEDQ<br>tDVE/tDVEDQ<br>**----- End of picture text -----**<br>
## **Figure 4.8. Receiver RX.CLK.Aligned and DDR Memory Input Waveforms**
**==> picture [466 x 329] intentionally omitted <==**
**----- Start of picture text -----**<br>
1/2 UI 1/2 UI 1/2 UI 1/2 UI<br>Tx CLK (out)<br>or DQS Output<br>Tx DATA (out)<br>or DQ Output<br>(a<br>tDVB/tDQVBS tDVB/tDQVBS<br>tDVA/tDQVA tDVA/tDQVAS<br>Figure 4.9. Transmit TX.CLK.Centered and DDR Memory Output Waveforms<br>1 UI<br>Tx CLK (out)<br>Tx DATA (out)<br>tDIB | tDIB | es ||<br>tDIA tDIA<br>**----- End of picture text -----**<br>
**Figure 4.10. Transmit TX.CLK.Aligned Waveforms**
© 2021-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
128
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**CrossLink-NX Family Data Sheet**
## **Receiver – Shown for one LVDS Channel**
# of Bits 12 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 Data In 756 Mb/s ~~XOX 1X 2X 3X 4X 5X 6X OX 1X 2K 3X 4X SX OX OK 1K 2K 3K 4K SK KOK 1K 2X 3X 4X 5X 6X 0)~~ Clock In 0! 1! 2! 3} 4| 108 MHz i 1Ti1 ~~a~~ il 1 ! **I** 1 il ~~1~~ **I** ! I Bit # Bit # Bit # Bit # 0x 10 – 1 20 – 8 30 – 15 40 – 22 **For each Channel:** 0x 11 – 2 21 – 9 31 – 16 41 – 23 **7-bit Output Words** 0x0x 12 – 313 – 4 22 – 1023 – 11 32 – 1733 – 18 42 – 2443 – 25 **to FPGA Fabric 1** 0x0x il1 14 – 515 – 6 **I** 24 – 1225 – 13 ! 34 – 1935 – 20 **I** 44 – 2645 – 27 0x 16 – 7 26 – 14 36 – 21 46 – 28
## **Transmitter – Shown for one LVDS Channel**
# of Bits Data Out 756 Mb/s ~~ROKAN 2X SXAKSHKER~~ I ~~ON ANAK SHAN EX OX~~ L ~~OK K ZAK SHAKE EK~~ | ~~OX AX 2H SHAK EX OX}~~ I Clock Out 0! 1 2| 3} 4) 108 MHz 1 il I ! I Bit # II Bit # ilil Bit # II Bit # !! II **For each Channel:** 00 – 1 ii1 10 – 8 ilil ~~1~~ 20 – 15 1 **I** 30 – 22 !! I **I 7-bit Output Words** 00 – 200 – 3 11 – 912 – 10 21 – 1622 – 17 31 – 2332 – 24 **to FPGA Fabric** 00 – 4 13 – 11 23 – 18 33 – 25 00 – 5 14 – 12 24 – 19 34 – 26 00 – 6 1II 15 – 13 ilil 25 – 20 II 35 – 27 !! II 00 – 7 i 16 – 14 il1 26 – 21 II 36 – 28 !! II
**Figure 4.11. DDRX71 Video Timing Waveforms**
**==> picture [414 x 175] intentionally omitted <==**
**----- Start of picture text -----**<br>
Bit 0 Bit 1 Bit i<br>t 1/2 UI 1 1/2 UI<br>> ‘4 » !<br>CLK (in) 1 UI \'<br>!<br>1 ! H 1<br>I i ! 1<br>DATA (in)<br>i]i tSU_0 !1 1 I !<br>tHD_0<br>1<br>1 tSU_i 1 1<br>tHD_i<br>**----- End of picture text -----**<br>
**Figure 4.12. Receiver DDRX71_RX Waveforms**
© 2021-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02049-1.8
129
**CrossLink-NX Family Data Sheet**
**==> picture [395 x 198] intentionally omitted <==**
**----- Start of picture text -----**<br>
Bit 0 Bit 1 Bit i<br>1 UI<br>CLK (out)<br>DATA (out)<br>tDIB_0 X00 0000 O<br>tDIA_0<br>tDIB_i<br>tDIA_i<br>**----- End of picture text -----**<br>
**Figure 4.13. Transmitter DDRX71_TX Waveforms**
## **4.18. sysCLOCK PLL Timing (VCC = 1.0 V) – Automotive**
**Table 4.34. sysCLOCK PLL Timing (VCC = 1.0 V) – Automotive**
|**Parameter**<br>~~DG~~|**Descriptions**<br>~~DG~~|**Conditions**<br>~~DG~~|**Min**<br>~~DG~~|**Typ.**<br>~~DG~~|**Max**<br>~~DG~~|**Units**<br>~~DG~~|
|---|---|---|---|---|---|---|
|fIN|Input Clock Frequency (CLKI, CLKFB)|—|18|—|500|MHz|
|fOUT|Output Clock Frequency|—|6.25|—|800|MHz|
|fVCO<br>~~sO~~|PLL VCO Frequency<br>~~sO~~|—<br>~~sO~~|800<br>~~sO~~|—<br>~~sO~~|1600<br>~~sO~~|MHz<br>~~sO~~|
|fPFD<br>~~**e**~~|Phase Detector Input Frequency<br>~~**e**ee~~|Without Fractional-N<br>Enabled<br>~~ee~~|18<br>~~ee~~|—<br>~~ee~~|500<br>~~ee~~|MHz<br>~~ee~~|
|||With Fractional-N<br>Enabled<br>~~ee~~<br>~~e~~|18<br>~~ee~~<br>~~e~~|—<br>~~ee~~<br>~~e~~|100<br>~~ee~~<br>~~e~~|MHz<br>~~ee~~<br>~~e~~|
|**AC Characteristics**<br>~~**e**ee~~<br>~~e~~|||||||
|tDT<br>~~a~~|Output Clock Duty Cycle<br>~~a~~|—<br>~~a~~|45<br>~~a~~|—<br>~~a~~|55<br>~~a~~|%<br>~~a~~|
|tPH4<br>~~a~~|Output Phase Accuracy<br>~~a~~<br>~~a~~<br><br>~~a~~|—<br>~~a~~<br>~~G~~<br>|–5<br>~~a~~<br>|—<br>~~a~~<br>|5<br>~~a~~<br>|%<br>~~a~~<br>~~—~~|
|tOPJIT1<br>~~a~~|Output Clock Period Jitter<br>~~a~~<br>~~a~~<br>~~ey~~<br>~~a~~<br>~~a~~|fOUT≥ 200 MHz<br>~~a~~<br>~~G~~<br>~~ey~~|—<br>~~a~~<br>~~ey~~|—<br>~~a~~<br>~~ey~~|250<br>~~a~~<br>~~ey~~|ps p-p<br>~~a~~<br>~~ey—~~|
|||fOUT< 200 MHz<br>~~ey~~<br>~~ee~~<br>|—<br>~~ey~~<br><br>|—<br>~~ey~~<br>~~ee~~<br>|0.05<br>~~ey~~<br>~~ee~~<br>|UIPP<br>~~ey—~~<br>~~ee~~<br>|
||Output Clock Cycle-to-Cycle Jitter<br>~~ey~~<br>~~a~~<br>~~a~~|fOUT≥ 200 MHz<br>~~ey~~<br>~~ee~~<br>|—<br>~~ey~~<br><br>|—<br>~~ey~~<br>~~ee~~<br>|250<br>~~ey~~<br>~~ee~~<br>|ps p-p<br>~~ey—~~<br>~~ee~~<br>|
|||fOUT< 200 MHz<br><br>~~ee~~<br>~~=—====~~|—<br><br><br>~~=—====~~|—<br><br>~~ee~~<br>~~=—====~~|0.05<br><br>~~ee~~<br>~~=—====~~|UIPP<br>~~—~~<br>~~ee~~<br>~~=—====~~|
||Output Clock Phase Jitter<br>~~a~~|fPFD≥ 200 MHz<br>~~ee~~<br>~~=—====~~|—<br><br>~~=—====~~|—<br>~~ee~~<br>~~=—====~~|250<br>~~ee~~<br>~~=—====~~|ps p-p<br>~~ee~~<br>~~=—====~~|
|||60 MHz ≤ fPFD< 200 MHz<br>~~ee~~<br>~~=—====~~|—<br><br>~~=—====~~<br>~~ee~~|—<br>~~ee~~<br>~~=—====~~<br>~~ee~~|400<br>~~ee~~<br>~~=—====~~<br>~~on~~|psp-p<br>~~ee~~<br>~~=—====~~|
|||30 MHz ≤ fPFD< 60 MHz<br>~~ee~~<br>~~=—====~~<br>~~ee~~|—<br><br>~~=—====~~<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~=—====~~<br>~~ee~~<br>~~ee~~|500<br>~~ee~~<br>~~=—====~~<br>~~ee~~<br>~~on~~|ps p-p<br>~~ee~~<br>~~=—====~~<br>~~ee~~|
|||18 MHz ≤ fPFD< 30 MHz<br>~~ee~~<br>~~=—====~~<br>~~ee~~|—<br><br>~~=—====~~<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~=—====~~<br>~~ee~~<br>~~ee~~|725<br>~~ee~~<br>~~=—====~~<br>~~ee~~<br>~~on~~|ps p-p<br>~~ee~~<br>~~=—====~~<br>~~ee~~|
||Output Clock Period Jitter (Fractional-N)<br>~~a ~~<br>~~eee~~|fOUT≥ 200 MHz<br>~~ee ~~<br> ~~=—====~~<br>~~ee~~<br>~~eee~~|—<br> <br>~~=—====~~<br>~~ee~~<br>~~ee~~<br>~~eee~~|—<br> ~~ee~~<br>~~=—====~~<br>~~ee~~<br>~~ee ~~<br>~~eee~~|350<br>~~ee~~<br>~~=—====~~<br>~~ee~~<br> ~~on~~<br>~~eee~~|ps p-p<br>~~ee~~<br>~~=—====~~<br>~~ee~~<br>~~eee~~|
|||fOUT< 200 MHz<br>~~eee~~<br>~~Pt~~|—<br>~~eee~~<br>~~Pt~~|—<br>~~eee~~<br>~~Pt~~|0.07<br>~~eee~~<br>~~Pt~~|UIPP<br>~~eee~~<br>~~Pt~~|
||Output Clock Cycle-to-Cycle Jitter (Fractional-<br>N)<br>~~a~~|fOUT≥ 200 MHz<br>~~eee~~|—<br>~~eee~~|—<br>~~eee~~|400<br>~~eee~~|ps p-p<br>~~eee~~|
|||fOUT< 200 MHz<br>~~eee~~<br>~~ET~~|—<br>~~eee~~<br>~~ET~~|—<br>~~eee~~<br>~~ET~~|0.08<br>~~eee~~<br>~~ET~~|UIPP<br>~~eee~~<br>~~ET~~|
© 2021-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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**CrossLink-NX Family**
**Data Sheet**
|**Parameter**<br>~~GO~~<br>~~ee~~|**Descriptions**<br>~~GO~~|**Conditions**<br>~~GO~~|**Min**<br>~~GO~~|**Typ.**<br>~~GO~~|**Max**<br>~~GO~~|**Units**<br>~~GO~~|
|---|---|---|---|---|---|---|
|fBW3<br>~~ee~~|PLL Loop Bandwidth|—|0.45|—|13|MHz|
|tLOCK2<br>~~ee~~<br>~~a~~|PLL Lock-in Time<br>~~a~~|—<br>~~GG~~|—<br>~~GG~~|—|10|ms|
|tUNLOCK<br>~~a ~~|PLL Unlock Time (from RESETgoes HIGH)<br> ~~GO~~|—<br>~~GO~~|—<br>~~GO~~|—<br>~~GO~~|50<br>~~GO~~|ns<br>~~GO~~|
|tIPJIT<br>~~a~~|Input Clock Period Jitter|fPFD≥ 20 MHz<br>~~es~~|—<br>~~es~~|—<br>~~es~~|500<br>~~es~~|ps p-p<br>~~es~~|
|||fPFD< 20 MHz<br>~~es~~|—<br>~~es~~|—<br>~~es~~|0.01<br>~~es~~|UIPP<br>~~es~~|
|tHI<br>~~a~~|Input Clock High Time<br>~~eG~~|90% to 90%<br>~~eG~~|0.5<br>~~eG~~|—<br>~~eG~~|—<br>~~eG~~|ns<br>~~eG~~|
|tLO<br>~~a ~~|Input Clock Low Time<br> ~~a~~|10% to 10%<br>~~GO~~|0.5<br>~~GO~~|—<br>~~GO~~|—<br>~~GO~~|ns<br>~~GO~~|
|tRST<br>~~a eG~~|RST/ Pulse Width<br>~~eG~~|—<br>~~eG~~|1<br>~~eG~~|—<br>~~eG~~|—<br>~~eG~~|ms<br>~~eG~~|
|fSSC_MOD<br>~~a a~~|Spread Spectrum Clock Modulation Frequency<br>~~a~~|—<br>~~GO~~|20<br>~~GO~~|—<br>~~GO~~|200<br>~~GO~~|kHz<br>~~GO~~|
|fSSC_MOD_AMP<br>~~a a~~|Spread Spectrum Clock Modulation Amplitude<br>Range<br>~~a~~|—<br>~~GO~~|0.25<br>~~GO~~|—<br>~~GO~~|2.00<br>~~GO~~|%<br>~~GO~~|
|fSSC_MOD_STEP|Spread Spectrum Clock Modulation Amplitude<br>Step Size|—|—|0.25|—|%|
**Notes** :
1. Jitter sample is taken over 10,000 samples for Period jitter, and 1,000 samples for Cycle-to-Cycle jitter of the primary PLL output with clean reference clock with no additional I/O toggling.
2. Output clock is valid after tLOCK for PLL reset and dynamic delay adjustment.
3. Result from Lattice Radiant software.
4. CLKOS as compared to CLKOP output for one phase step at the maximum VCO frequency.
## **4.19. Internal Oscillators Characteristics**
**Table 4.35. Internal Oscillators (VCC = 1.0 V)**
|**Symbol**|**Parameter Description**|**Min**|**Typ**|**Max**|**Unit**|
|---|---|---|---|---|---|
|fCLKHF|HFOSC CLKK Clock Frequency|418.5|450|481.5|MHz|
|fCLKLF|LFOSC CLKK Clock Frequency|18.2|32|45.8|kHz|
|DCHCLKHF|HFOSC Duty Cycle (Clock High Period)|43|50|57|%|
|DCHCLKLF|LFOSC Duty Cycle (Clock High Period)|45|50|55|%|
## **4.20. User I[2] C Characteristics**
**Table 4.36. User I[2] C Specifications (VCC = 1.0 V)**
|**Symbol**|**Parameter**<br>**Description**|**STD Mode**|**STD Mode**|**STD Mode**|**FAST Mode**|**FAST Mode**|**FAST Mode**|**FAST Mode Plus2**|**FAST Mode Plus2**|**FAST Mode Plus2**|**Units**|
|---|---|---|---|---|---|---|---|---|---|---|---|
|||**Min**|**Typ**|**Max**|**Min**|**Typ**|**Max**|**Min**|**Typ**|**Max**||
|fscl|SCL Clock<br>Frequency|—|—|100|—|—|400|—|—|1000|kHz|
|TDELAY1|Optional delay<br>through delayblock|—|—|62|—|—|62|—|—|62|ns|
**Notes** :
1. Refer to the I[2] C Specification for timing requirements. User design should set constraints in Lattice Design Software to meet this industrial I[2] C Specification.
2. Fast Mode Plus maximum speed may be achieved by using external pull up resistor on I[2] C bus. Internal pull up may not be sufficient to support the maximum speed.
© 2021-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02049-1.8
131
**CrossLink-NX Family Data Sheet**
## **4.21. Analog-Digital Converter (ADC) Block Characteristics**
**Table 4.37. ADC Specifications[3]**
|**Symbol**<br>~~a GG~~<br>~~a~~|**Description**<br>~~GG~~|**Condition**<br>~~GG~~|**Min**<br>~~GG~~|**Typ**<br>~~GG~~|**Max**<br>~~GG~~<br>(OO|**Unit**<br>~~GG~~|
|---|---|---|---|---|---|---|
|VREFINT_ADC<br>~~a~~|ADC Internal Reference<br>Voltage<br>~~a~~|—<br>~~a~~|1.141|1.2|1.261<br>(OO|V|
|VREFEXT_ADC<br>~~a~~|ADC External Reference<br>Voltage<br>~~a~~<br>~~a~~|—<br>~~a~~<br>~~a~~|1.0<br>~~a~~|—<br>~~a~~|1.8|V|
|NRES_ADC<br>~~a~~|ADC Resolution<br>~~a~~<br>~~eG~~|—<br>~~a~~<br>~~eG~~|—<br>~~GO~~|12<br>~~GO~~|—<br>~~GO~~|bits|
|ENOBADC<br>~~a GO~~|Effective Number of Bits<br>~~GO~~|—<br>~~GO~~|9.9<br>~~GO~~|11<br>~~GO~~|—<br>~~GO~~|bits<br>~~GO~~|
|VSR_ADC<br>~~a GO~~<br>~~a~~|ADC Input Range<br>~~GO~~<br>|Bipolar Mode, Internal<br>VREF<br>~~GO~~<br>~~a~~|VCM_ADC ―<br>VREFINT_ADC/4<br>~~GO~~|VCM_ADC<br>~~GO~~|VCM_ADC+<br>VREFINT_ADC/4<br>~~GO~~|V<br>~~GO~~|
|||Bipolar Mode, External<br>VREF<br>~~a~~|VCM_ADC ―<br>VREFEXT_ADC/4|VREFEXT_ADC|VCM_ADC+<br>VREFEXT_ADC/4|V|
|||Uni-polar Mode, Internal<br>VREF<br>~~a~~|0|—|VREFINT_ADC|V|
|||Uni-polar Mode, External<br>VREF<br>~~a~~<br>~~i~~<br>|0<br>~~ee~~<br>|—<br>~~ee~~<br>|VREFEXT_ADC<br>~~ee~~<br>|V<br>~~ee~~<br>|
|VCM_ADC<br>~~ce~~<br>~~a~~<br>~~a~~|ADC Input Common Mode<br>Voltage (for fully<br>differential signals)<br>~~ce~~<br><br>|Internal VREF<br>~~ce~~<br>~~i~~<br>|—<br>~~ce~~<br>~~ee~~<br>|VREFINT_ADC/2<br>~~ce~~<br>~~ee~~<br>|—<br>~~ce~~<br>~~ee~~<br>|V<br>~~ce~~<br>~~ee~~<br>|
|||External VREF<br>~~ce~~<br>~~i~~<br><br>|—<br>~~ce~~<br>~~ee~~<br><br>~~GO~~<br>|VREFEXT_ADC/2<br>~~ce~~<br>~~ee~~<br><br>~~GO~~<br>|—<br>~~ce~~<br>~~ee~~<br><br>~~GO~~<br>|V<br>~~ce~~<br>~~ee~~<br><br>|
|fCLK_ADC<br>~~ce~~<br>~~a~~<br>~~a~~<br>~~a~~|ADC Clock Frequency<br>~~ce~~<br>~~eG~~<br><br>|—<br>~~ce~~<br>~~i~~<br>~~eG~~<br><br>|—<br>~~ce~~<br>~~ee ~~<br>~~eG~~<br>~~GO~~<br><br>~~GO~~<br>|25<br>~~ce~~<br> ~~ee ~~<br>~~eG~~<br>~~GO~~<br><br>~~GO~~<br>|40<br>~~ce~~<br> ~~ee~~<br>~~eG~~<br>~~GO~~<br><br>~~GO~~<br>|MHz<br>~~ce~~<br>~~ee~~<br>~~eG~~<br><br>|
|DCCLK_ADC<br>~~a~~<br>~~a~~<br>~~a~~|ADC Clock DutyCycle<br>~~eG~~<br>|—<br>~~eG~~<br>|48<br>~~GO~~<br>~~eG~~<br>~~GO~~<br><br>~~GO~~|50<br>~~GO~~<br>~~eG~~<br>~~GO~~<br><br>~~GO~~|52<br>~~GO~~<br>~~eG~~<br>~~GO~~<br><br>~~GO~~|%<br>~~eG~~<br>|
|fINPUT_ADC<br>~~a~~<br>~~a~~|ADC Input Frequency<br>~~eG~~|—<br>~~eG~~|—<br>~~GO~~<br>~~eG~~<br>~~GO~~|—<br>~~GO~~<br>~~eG~~<br>~~GO~~|500<br>~~GO~~<br>~~eG~~<br>~~GO~~|kHz<br>~~eG~~|
|FSADC<br>~~a~~|ADC SamplingRate<br>~~eG~~|—<br>~~eG~~|—<br>~~GO~~<br>~~GO~~|1<br>~~GO~~<br>~~GO~~|—<br>~~GO~~<br>~~GO~~|MS/s|
|NTRACK_ADC<br>~~a GO~~|ADC Input TrackingTime<br>~~GO~~|—<br>~~GO~~|4<br>~~GO~~|—<br>~~GO~~|—<br>~~GO~~|cycles2<br>~~GO~~|
|RIN_ADC<br>~~a GO~~<br>~~a~~|ADC Input Equivalent<br>Resistance<br>~~GO~~<br>~~a~~|1 MS/s, Sampled @ 2<br>clock cycles<br>~~GO~~<br>~~a~~|—<br>~~GO~~<br>~~a~~|116<br>~~GO~~<br>~~a~~|—<br>~~GO~~<br>~~a~~|kΩ<br>~~GO~~<br>~~a~~|
|tCAL_ADC<br>~~a~~|ADC Calibration Time<br>~~a~~|—<br>~~a~~|—<br>~~a~~|—<br>~~a~~|6500<br>~~a~~|cycles2<br>~~a~~|
|LOUTput_ADC<br>~~a~~|ADC Conversion Time<br>~~a~~|Includes minimum<br>tracking time of four<br>cycles<br>~~a~~<br>~~ee~~|25<br>~~a~~<br>~~ee~~|—<br>~~a~~<br>~~ee~~|—<br>~~a~~|cycles2<br>~~a~~|
|DNLADC<br>~~a~~<br>~~a~~|ADC Differential<br>Nonlinearity<br>~~a~~<br>~~a~~|—<br>~~a~~<br>~~ee~~<br>~~a~~|**–**1<br>~~a~~<br>~~ee~~<br>~~a~~<br>~~GO~~|—<br>~~a~~<br>~~ee~~<br>~~a~~<br>~~GO~~|1<br>~~a~~<br>~~a~~<br>~~GO~~|LSB<br>~~a~~<br>~~a~~|
|INLADC<br>~~a~~<br>~~eG~~|ADC Integral Nonlinearity<br>~~a~~<br>~~eG~~|—<br>~~a~~<br>~~eG~~|**–**21<br>~~a~~<br>~~eG~~<br>~~GO~~|—<br>~~a~~<br>~~eG~~<br>~~GO~~|2.21<br>~~a~~<br>~~eG~~<br>~~GO~~|LSB<br>~~a~~<br>~~eG~~|
|SFDRADC<br>~~eG~~<br>~~a~~|ADC Spurious Free<br>Dynamic Range<br>~~eG~~<br>~~a~~|—<br>~~eG~~<br>~~a~~|65.8<br>~~eG~~<br>~~GO~~<br>~~a~~|77<br>~~eG~~<br>~~GO~~<br>~~a~~|—<br>~~eG~~<br>~~GO~~<br>~~a~~|dBc<br>~~eG~~<br>~~a~~|
|THDADC<br>~~a~~<br>~~a~~|ADC Total Harmonic<br>Distortion<br>~~a~~<br>~~a~~|—<br>~~a~~<br>~~a~~|—<br>~~a~~<br>~~a~~<br>~~GO~~|**–**76<br>~~a~~<br>~~a~~<br>~~GO~~|**–**66.4<br>~~a~~<br>~~a~~<br>~~GO~~|dB<br>~~a~~<br>~~a~~|
|SNRADC<br>~~a~~<br>~~a~~|ADC Signal to Noise Ratio<br>~~a~~<br>~~a~~<br>~~eG~~|—<br>~~a~~<br>~~a~~<br>~~eG~~|61.6<br>~~a~~<br>~~a~~<br>~~eG~~<br>~~GO~~|68<br>~~a~~<br>~~a~~<br>~~eG~~<br>~~GO~~|—<br>~~a~~<br>~~a~~<br>~~eG~~<br>~~GO~~|dB<br>~~a~~<br>~~a~~<br>~~eG~~|
|SNDRADC<br>~~a~~<br>~~a~~|ADC Signal to Noise Plus<br>Distortion Ratio<br>~~a~~<br>|—<br>~~a~~<br>|61.5<br>~~GO~~<br>~~a~~<br>~~GO~~<br>|67<br>~~GO~~<br>~~a~~<br>~~GO~~<br>|—<br>~~GO~~<br>~~a~~<br>~~GO~~<br>|dB<br>~~a~~<br>|
|ERRGAIN_ADC<br>~~a~~<br>~~a~~<br>~~a~~|ADC Gain Error<br>~~a~~<br>~~a~~<br>~~eG~~<br>|—<br>~~a~~<br>~~a~~<br>~~eG~~<br>|–0.5<br>~~a~~<br>~~a~~<br>~~eG~~<br>~~GO~~<br><br>~~GO~~|—<br>~~a~~<br>~~a~~<br>~~eG~~<br>~~GO~~<br><br>~~GO~~|0.5<br>~~a~~<br>~~a~~<br>~~eG~~<br>~~GO~~<br><br>~~GO~~|% FSADC<br>~~a~~<br>~~a~~<br>~~eG~~<br>|
|ERROFFSET_ADC<br>~~a~~|ADC Offset Error<br>~~eG~~|—<br>~~eG~~|–2<br>~~GO~~<br>~~eG~~<br>~~GO~~|—<br>~~GO~~<br>~~eG~~<br>~~GO~~|2<br>~~GO~~<br>~~eG~~<br>~~GO~~|LSB<br>~~eG~~|
|CIN_ADC<br>~~a~~|ADC Input Equivalent<br>Capacitance<br>~~a~~|—<br>~~a~~|—<br>~~GO~~<br>~~a~~|2<br>~~GO~~<br>~~a~~|—<br>~~GO~~<br>~~a~~|pF<br>~~a~~|
1. Not tested; guaranteed by design.
2. ADC Sample Clock cycles. See ADC User Guide for Nexus Platform (FPGA-TN-02129) for more details.
3. ADC is available in Automotive –7 speed grade.
© 2021-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
132
FPGA-DS-02049-1.8
**CrossLink-NX Family Data Sheet**
## **4.22. Comparator Block Characteristics**
**Table 4.38. Comparator Specifications**
|**Symbol**|**Description**|**Min**|**Typ**|**Max**|**Unit**|
|---|---|---|---|---|---|
|fIN_COMP|Comparator Input Frequency|—|—|10|MHz|
|VIN_COMP|Comparator Input Voltage|0|—|VCC_ADC18|V|
|VOFFSET_COMP|Comparator Input Offset|–34.3|—|36.44|mV|
|VHYST_COMP|Comparator Input Hysteresis|10|—|31.62|mV|
|VLATENCY_COMP|Comparator Latency|—|—|31.24|ns|
## **4.23. Digital Temperature Readout Characteristics**
Digital temperature Readout (DTR) is implemented in one of the channels of ADC1.
**Table 4.39. DTR Specifications[1, 2]**
|**Symbol**|**Description**|**Condition**|**Min**|**Typ**|**Max**|**Unit**|
|---|---|---|---|---|---|---|
|DTRRANGE|DTR Detect Temperature<br>Range|—|–40|—|125|°C|
|DTRACCURACY|DTR Accuracy|with external voltage<br>reference range of 1.0 V<br>to 1.8 V|–16|±6|16|°C|
|DTRRESOLUTION|DTR Resolution|with external voltage<br>reference|–0.3|—|0.3|°C|
**Notes:**
1. External voltage reference (VREF) should be 0.1% accurate or better. DTR sensitivity to VREF is -4.1 °C per VREF per-cent (for example, if the VREF is 1 % low, then the DTR will read +4.1 °C high).
2. DTR is available in Automotive –7 speed grade.
## **4.24. Hardened MIPI D-PHY Characteristics**
**Table 4.40. Hardened D-PHY Input Timing and Levels**
|**Symbol**<br>~~pO~~|**Description**<br>~~pO~~|**Conditions**<br>~~pO~~|**Min**<br>~~pO~~|**Typ**<br>~~pO~~|**Max**<br>~~pO~~|**Unit**<br>~~pO~~|
|---|---|---|---|---|---|---|
|**High Speed (Differential) Input DC Specifications**<br>~~pT~~|||||||
|VCMRX(DC)<br>~~pT~~<br>~~a~~|Common-mode Voltage in High Speed<br>Mode<br>~~pT~~<br>~~a~~|—<br>~~pT~~<br>~~a~~|70<br>~~pT~~<br>~~a~~|—<br>~~pT~~<br>~~a~~|330<br>~~pT~~<br>~~a~~|mV<br>~~pT~~<br>~~a~~|
|VIDTH<br>~~a~~<br>~~Df~~|Differential Input HIGH Threshold<br>~~a~~<br>~~Df~~|0.08 Gbps ≤ VIDTH≤ 1.5 Gbps<br>~~a~~<br>~~**ee**~~|70<br>~~a~~<br>~~**ee**~~|—<br>~~a~~<br>~~**ee**~~|—<br>~~a~~<br>~~**ee**~~|mV<br>~~a~~|
|||1.5 Gbps < VIDTH≤ 2.5 Gbps<br>~~a~~<br>~~**ee**~~|40<br>~~a~~<br>~~**ee**~~|—<br>~~a~~<br>~~**ee**~~|—<br>~~a~~<br>~~**ee**~~|mV<br>~~a~~|
|VIDTL<br>~~a~~<br>~~Df~~<br>~~a~~|Differential Input LOW Threshold<br>~~a~~<br>~~Df~~|0.08 Gbps ≤ VIDTL≤ 1.5 Gbps<br>~~a~~<br>~~**ee**~~|—<br>~~a~~<br>~~**ee**~~|—<br>~~a~~<br>~~**ee**~~|–70<br>~~a~~<br>~~**ee**~~|mV<br>~~a~~|
|||1.5 Gbps < VIDTL≤ 2.5 Gbps<br>~~**ee**~~|—<br>~~**ee**~~|—<br>~~**ee**~~|–40<br>~~**ee**~~|mV|
|VIHHS<br>~~Df~~<br>~~a~~|Input HIGH Voltage (for HS mode)<br>~~Df~~|—<br>~~**ee** ~~|—<br> ~~**ee**~~|—<br>~~**ee**~~|460<br>~~**ee**~~|mV|
|VILHS<br>~~a DO~~|Input LOW Voltage<br>~~DO~~|—<br>~~DO~~|–40<br>~~DO~~|—<br>~~DO~~|—<br>~~DO~~|mV<br>~~DO~~|
|VTERM-EN<br>~~a DO~~<br>~~a~~|Single-ended voltage for HS Termination<br>Enable4 <br>~~DO~~<br>|—<br>~~DO~~<br>|—<br>~~DO~~<br>|—<br>~~DO~~<br>|450<br>~~DO~~<br>|mV<br>~~DO~~<br>|
|ZID<br>~~sD~~|Differential Input Impedance<br>~~sD~~|—<br>~~sD~~|80<br>~~sD~~|100<br>~~sD~~|125<br>~~sD~~|Ω<br>~~sD~~|
|**High Speed (Differential) Input AC Specifications**<br>~~pn~~<br>~~Pf~~<br>~~ee eee~~|||||||
|ΔVCMRX(HF)1<br>~~Pf~~|Common-mode Interference (>450 MHz)<br>~~Pf~~|0.08 Gbps ≤ ∆VCMRX(HF)≤ 1.5<br>Gbps<br>~~ee eee~~|—<br>~~eee~~|—<br>~~eee~~|100<br>~~eee~~|mV<br>~~eee~~|
|||1.5 Gbps < ∆VCMRX(HF)≤ 2.5<br>Gbps<br>~~ee eee~~|—<br>~~eee~~|—<br>~~eee~~|50<br>~~eee~~|mV<br>~~eee~~|
© 2021-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02049-1.8
133
**CrossLink-NX Family Data Sheet**
|**Symbol**<br>~~a~~|**Description**<br>~~a~~|**Conditions**<br>~~a~~|**Min**<br>~~a~~|**Typ**<br>~~a~~|**Max**<br>~~a~~|**Unit**<br>~~a~~|
|---|---|---|---|---|---|---|
|ΔVCMRX(LF)2, 3<br>~~Pf~~<br>~~a~~|Common-mode Interference (50 MHz–450<br>MHz)<br>~~Pf~~<br>~~ee~~|0.08 Gbps ≤ ∆VCMRX(LF)≤ 1.5<br>Gbps<br>~~re~~|–50<br>~~re~~<br>~~ee~~|—<br>~~re~~<br>~~ee~~|50<br>~~re~~<br>~~ee~~|mV<br>~~re~~<br>~~ee~~|
|||1.5 Gbps < ∆VCMRX(LF)≤ 2.5<br>Gbps<br>~~re~~<br>~~ee~~|–25<br>~~re~~<br>~~ee~~<br>~~ee~~|—<br>~~re~~<br>~~ee~~|25<br>~~re~~<br>~~ee~~|mV<br>~~re~~<br>~~ee~~|
|CCM<br>~~Pf~~<br>~~a~~|Common-mode Termination<br>~~Pf~~<br>~~ee~~|—<br>~~re~~<br>~~ee~~|—<br>~~re~~<br>~~ee~~<br>~~ee~~|—<br>~~re~~<br>~~ee ~~|60<br>~~re~~<br> ~~ee~~|pF<br>~~re~~<br>~~ee~~|
|**Low Power (Single-Ended) Input DC Specifications**<br>~~ee~~<br>~~ee ee~~<br>~~a~~|||||||
|VIH<br>~~a~~|Low Power Mode Input HIGH Voltage<br>~~a~~|—<br>~~a~~|780<br>~~a~~|—<br>~~a~~|—<br>~~a~~|mV<br>~~a~~|
|VIL<br>~~a~~<br>~~a~~|Low Power Mode Input LOW Voltage<br>~~a~~<br>~~a~~|—<br>~~a~~<br>~~a~~|—<br>~~a~~<br>~~a~~|—<br>~~a~~<br>~~a~~|540<br>~~a~~<br>~~a~~|mV<br>~~a~~<br>~~a~~|
|VIL-ULP<br>~~a~~|Ultra Low Power Input LOW Voltage<br>~~a~~|—<br>~~a~~|—<br>~~a~~|—<br>~~a~~|300<br>~~a~~|mV<br>~~a~~|
|VHYST<br>~~a~~|Low Power Mode Input Hysteresis<br>~~a~~|—<br>~~a~~|21<br>~~a~~|—<br>~~a~~|—<br>~~a~~|mV<br>~~a~~|
|℮SPIKE<br>~~a~~<br>~~a~~|Input Pulse Rejection<br>~~a~~<br>~~a~~|—<br>~~a~~<br>~~a~~|—<br>~~a~~<br>~~a~~|—<br>~~a~~<br>~~a~~|300<br>~~a~~<br>~~a~~|V∙ps<br>~~a~~<br>~~a~~|
|TMIN-RX<br>~~a~~|Minimum Pulse Width Response<br>~~a~~|—<br>~~a~~|20<br>~~a~~|—<br>~~a~~|—<br>~~a~~|ns<br>~~a~~|
|VINT<br>~~a~~|Peak Interference Amplitude<br>~~a~~|—<br>~~a~~|—<br>~~a~~|—<br>~~a~~|200<br>~~a~~|mV<br>~~a~~|
|fINT<br>~~a~~<br>~~a~~|Interference Frequency<br>~~a~~<br>~~a~~|—<br>~~a~~<br>~~a~~|450<br>~~a~~<br>~~a~~|—<br>~~a~~<br>~~a~~|—<br>~~a~~<br>~~a~~|MHz<br>~~a~~<br>~~a~~|
|**Contention Detector (LP-CD) DC Specifications**<br>~~a~~|||||||
|VIHCD<br>~~a~~|Contention Detect HIGH Voltage<br>~~a~~|—<br>~~a~~|450<br>~~a~~|—<br>~~a~~|—<br>~~a~~|mV<br>~~a~~|
|VILCD<br>~~a~~<br>~~a~~|Contention Detect LOW Voltage<br>~~a~~<br>~~a~~|—<br>~~a~~<br>~~a~~|—<br>~~a~~<br>~~a~~|—<br>~~a~~<br>~~a~~|200<br>~~a~~<br>~~a~~|mV<br>~~a~~<br>~~a~~|
**Notes** :
1. This is peak amplitude of sine wave modulated to the receiver inputs.
2. Input common-mode voltage difference compared to average common-mode voltage on the receiver inputs.
3. Exclude any static ground shift of 50 mV.
4. High Speed Differential RTERM is enabled when both DP and DN are below this voltage.
**Table 4.41. Hardened D-PHY Output Timing and Levels**
|**Symbol**<br>~~a~~<br>|**Description**<br>~~a~~<br>|**Conditions**<br>~~a~~<br>|**Min**<br>~~a~~<br>|**Typ**<br>~~a~~<br>|**Max**<br>~~a~~<br>|**Unit**<br>~~a~~<br>~~]~~|
|---|---|---|---|---|---|---|
|**High Speed(Differential) Output DC Specifications**<br>~~a]~~|||||||
|VCMTX<br><br>~~a~~<br>~~a~~|Common-mode Voltage in High Speed Mode<br><br>~~a~~<br>|—<br><br>~~a~~<br>|130<br><br>~~a~~<br>~~ee~~<br>|200<br><br>~~a~~<br>|250<br><br>~~a~~<br>|mV<br>~~]~~<br>~~a~~<br>|
||ΔVCMTX(1,0)|<br>~~a~~<br>~~a~~<br>~~a~~<br>~~a~~|VCMTXMismatch Between Differential HIGH<br>and LOW<br>~~a~~<br>~~a~~<br>~~ee~~<br><br>|—<br>~~a~~<br>~~a~~<br>~~ee~~<br><br>|—<br>~~a~~<br>~~a~~<br>~~ee~~<br>~~ee~~<br><br>~~ee~~<br>|—<br>~~a~~<br>~~a~~<br>~~ee~~<br><br>|7<br>~~a~~<br>~~a~~<br>~~ee~~<br><br>|mV<br>~~a~~<br>~~a~~<br>~~ee~~<br><br>|
||VOD|<br>~~a~~<br>~~a~~<br>~~a~~<br>~~a~~|Output Differential Voltage<br>~~a~~<br>~~ee~~<br>~~ee~~<br>||D-PHY-P – D-<br>PHY-N|<br>~~a~~<br>~~ee~~<br>~~ee~~<br>|120<br>~~a~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br><br>~~ee~~|200<br>~~a~~<br>~~ee~~<br>~~ee~~<br>|270<br>~~a~~<br>~~ee~~<br>~~ee~~<br>|mV<br>~~a~~<br>~~ee~~<br>~~ee~~<br>|
||ΔVOD|<br>~~a~~<br>~~a~~<br>~~a~~|VODMismatch Between Differential HIGH and<br>LOW<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~|14<br>~~ee~~<br>~~ee~~|mV<br>~~ee~~<br>~~ee~~|
|VOHHS<br>~~a~~<br>~~a~~<br>~~**e**e~~|Single-Ended Output HIGH Voltage<br>~~ee~~|—<br>~~ee~~|—<br>~~ee~~<br>~~ee~~<br>~~ee~~|—<br>~~ee~~|375<br>~~ee~~|mV<br>~~ee~~|
|ZOS<br>~~a~~<br>~~**e**e~~|Single Ended Output Impedance|—|35<br>~~ee~~|50|75|Ω|
|ΔZOS<br>~~**e**e~~|ZOSmismatch<br>~~e~~|—<br>~~e~~|—<br>~~e~~|—<br>~~e~~|20<br>~~e~~|%<br>~~e~~|
|**High Speed(Differential) Output AC Specifications**<br>~~a]~~|||||||
|ΔVCMTX(LF)<br>~~a~~|Common-Mode Variation, 50 MHz – 450 MHz|—|—|—|25|mVRMS|
|ΔVCMTX(HF)<br>~~a~~<br>~~a~~|Common-Mode Variation, above 450 MHz|—|—|—|15|mVRMS|
|tR<br>~~a~~|Output 20%–80% Rise Time|0.08 Gbps ≤ tR≤ 1<br>Gbps<br>~~eT~~|—<br>~~eT~~|—<br>~~eT~~|0.35<br>~~eT~~|UI<br>~~eT~~|
|||1 Gbps < tR≤ 1.5<br>Gbps<br>~~eT~~<br>~~eo~~|—<br>~~eT~~<br>~~eo~~|—<br>~~eT~~<br>~~eo~~|0.525<br>~~eT~~<br>~~eo~~|UI<br>~~eT~~<br>~~eo~~|
|||tR≤ 1.5 Gbps<br>~~eo~~<br>~~a~~|65<br>~~eo~~<br>~~a~~|—<br>~~eo~~<br>~~a~~|—<br>~~eo~~<br>~~a~~|ps<br>~~eo~~<br>~~a~~|
|||1.5 Gbps < tR<br>≤ 2.5 Gbps<br>~~a~~<br>~~eo~~|—<br>~~a~~<br>~~eo~~<br>~~a~~|—<br>~~a~~<br>~~eo~~<br>~~es~~|0.875<br>~~a~~<br>~~eo~~|UI<br>~~a~~<br>~~eo~~|
|||tR> 1.5 Gbps<br>~~eo~~<br>~~ee~~|50<br>~~eo~~<br>~~ee~~<br>~~a~~|—<br>~~eo~~<br>~~ee~~<br>~~es~~|—<br>~~eo~~<br>~~ee~~|ps<br>~~eo~~<br>~~ee~~|
© 2021-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
134
FPGA-DS-02049-1.8
**CrossLink-NX Family Data Sheet**
|**Symbol**<br>~~a ~~|**Description**<br> ~~OG~~|**Conditions**<br>~~OG~~<br>~~ee~~|**Min**<br>~~OG~~<br>~~ee~~|**Typ**<br>~~OG~~<br>~~ee~~|**Max**<br>~~OG~~<br>~~ee~~|**Unit**<br>~~OG~~<br>~~ee~~|
|---|---|---|---|---|---|---|
|tF|Output 80%–20% Fall Time<br>~~po~~|0.08 Gbps ≤ tF≤ 1<br>Gbps<br>~~ee~~|—<br>~~ee~~|—<br>~~ee~~|0.33<br>~~ee~~|UI<br>~~ee~~|
|||1 Gbps < tF≤ 1.5<br>Gbps<br>~~ee~~<br>~~fT~~<br>~~po~~|—<br>~~ee ~~<br>~~fT~~<br>|—<br> ~~ee~~<br>~~fT~~<br>|0.495<br>~~ee~~<br>~~fT~~<br>|UI<br>~~ee~~<br>~~fT~~<br>|
|||tF≤ 1.5 Gbps<br>~~po~~~~**e**e~~|80<br>~~e~~|—<br>~~ee~~|—<br>~~ee~~|ps<br>~~ee~~|
|||1.5 Gbps < tF<br>≤ 2.5 Gbps<br>~~po~~~~**e**e~~|—<br>~~e~~|—<br>~~ee~~|0.825<br>~~ee~~|UI<br>~~ee~~|
|||tF> 1.5 Gbps<br>~~**e**e~~|50<br>~~e ~~<br>~~s~~|—<br> ~~ee~~<br>~~s~~|—<br>~~ee~~<br>~~s~~|ps<br>~~ee~~<br>~~s~~|
|**Low Power(Single-Ended) Output DC Specifications**|||||||
|VOH<br>~~Pr~~<br>~~a~~|Low Power Mode Output HIGH Voltage<br>~~Pr~~<br>|0.08 Gbps ≤ VOH≤<br>1.50 Gbps<br>~~eee~~<br>|0.75<br>~~eee~~<br>~~ee~~<br>|—<br>~~eee~~<br>|1.5<br>~~eee~~<br>|V<br>~~eee~~<br>|
|||VOH> 1.50 Gbps<br>~~eee~~<br>~~es~~<br>|0.75<br>~~eee~~<br>~~es~~<br>~~ee~~<br>|—<br>~~eee~~<br>~~es~~<br>|1.5<br>~~eee~~<br>~~es~~<br>|V<br>~~eee~~<br>~~es~~<br>|
|VOL<br>~~Pr~~<br>~~a ~~|Low Power Mode Input LOW Voltage<br>~~Pr~~<br> ~~GOO~~|—<br>~~eee~~<br>~~es~~<br>~~GOO~~|–50<br>~~eee~~<br>~~es~~<br>~~ee~~<br>~~GOO~~|—<br>~~eee~~<br>~~es~~<br>~~GOO~~|50<br>~~eee~~<br>~~es~~<br>~~GOO~~|mV<br>~~eee~~<br>~~es~~<br>~~GOO~~|
|ZOLP<br>~~a ~~|Output Impedance in Low Power Mode<br> ~~FDO~~|—<br>~~FDO~~|106<br>~~FDO~~|—<br>~~FDO~~|—<br>~~FDO~~|Ω<br>~~FDO~~|
|**Low Power(Single-Ended) Output AC Specifications**|||||||
|tRLP<br>~~a ~~|15%–85% Rise Time<br> ~~DG~~|—<br>~~DG~~|—<br>~~DG~~|—<br>~~DG~~|25<br>~~DG~~|ns<br>~~DG~~|
|tFLP<br>~~a~~|85%–15% Fall Time<br>~~DO~~|—<br>~~DO~~|—<br>~~DO~~|—<br>~~DO~~|25<br>~~DO~~|ns<br>~~DO~~|
|tREOT<br>~~a ~~<br>~~ef~~|HS – LP Mode Rise and Fall Time, 30%–85%<br> ~~DO~~<br>~~ef~~<br>~~EET~~|—<br>~~DO~~<br>~~EET~~|—<br>~~DO~~<br>~~EET~~|—<br>~~DO~~<br>~~EET~~|35<br>~~DO~~<br>~~EET~~|ns<br>~~DO~~<br>~~EET~~|
|TLP-PULSE-TX<br>~~ef~~|Pulse Width of the LP Exclusive-OR Clock<br>~~ef~~<br>~~EET~~|FirsttLP XOR<br>Clock Pulse after<br>STOP State or<br>Last Pulse before<br>STOP State<br>~~EET~~|40<br>~~EET~~|—<br>~~EET~~|—<br>~~EET~~|ns<br>~~EET~~|
|||All Other Pulses<br>~~EET~~|20<br>~~EET~~|—<br>~~EET~~|—<br>~~EET~~|ns<br>~~EET~~|
|TLP-PER-TX<br>~~ef~~<br>~~a~~|Period of the LP Exclusive-OR Clock<br>~~ef~~<br>~~EET~~<br>~~DO~~|—<br>~~EET~~<br>~~DO~~|90<br>~~EET~~<br>~~DO~~|—<br>~~EET~~<br>~~DO~~|—<br>~~EET~~<br>~~DO~~|ns<br>~~EET~~<br>~~DO~~|
|δV/δtSR<br>~~a ~~<br>~~po~~<br>~~-~~|Slew Rate @ CLOAD= 0pF<br> ~~DO~~<br>~~DC~~<br>|—<br>~~DO~~<br>~~DC~~<br>|—<br>~~DO~~<br>~~DC~~<br>~~ee~~|—<br>~~DO~~<br>~~DC~~<br>~~ee~~|500<br>~~DO~~<br>~~DC~~<br>~~ee ee~~|mV/ns<br>~~DO~~<br>~~DC~~<br>~~ee~~|
||Slew Rate @ CLOAD= 5pF<br>~~GO~~<br>|—<br>~~GO~~<br>|—<br>~~GO~~<br>~~ee~~|—<br>~~GO~~<br>~~ee~~|300<br>~~GO~~<br>~~ee ee~~|mV/ns<br>~~GO~~<br>~~ee~~|
||Slew Rate @ CLOAD= 20pF<br>~~GC~~<br>|—<br>~~GC~~<br>|—<br>~~GC~~<br>~~ee~~|—<br>~~GC~~<br>~~ee~~|250<br>~~GC~~<br>~~ee ee~~|mV/ns<br>~~GC~~<br>~~ee~~|
||Slew Rate @ CLOAD= 70pF<br>~~GD~~<br>~~po~~<br>|—<br>~~GD~~<br>~~——y————~~<br>|—<br>~~GD~~<br>~~——y————~~<br>~~ee~~|—<br>~~GD~~<br>~~——y————~~<br>~~ee~~|250<br>~~GD~~<br>~~——y————~~<br>~~ee ee~~|mV/ns<br>~~GD~~<br>~~——y————~~<br>~~ee~~|
||Slew Rate @ CLOAD= 0 to 70 pF (Falling Edge<br>Only)<br>~~GD~~<br>~~po~~<br>~~ee~~|—<br>~~GD~~<br>~~——y————~~<br>|7<br>~~GD~~<br>~~——y————~~<br>~~ee~~|—<br>~~GD~~<br>~~——y————~~<br>~~ee~~|—<br>~~GD~~<br>~~——y————~~<br>~~ee ee~~|mV/ns<br>~~GD~~<br>~~——y————~~<br>~~ee~~|
|||—<br>~~——y————~~<br>~~es~~<br>|7<br>~~——y————~~<br>~~es~~<br>~~ee~~|—<br>~~——y————~~<br>~~es~~<br>~~ee~~|—<br>~~——y————~~<br>~~es~~<br>~~ee ee~~|mV/ns<br>~~——y————~~<br>~~es~~<br>~~ee~~|
||Slew Rate @ CLOAD= 0 to 70 pF (Rising Edge<br>Only)<br>~~po~~<br>~~ee~~|—<br>~~——y————~~<br>~~es~~<br><br>~~es~~|7<br>~~——y————~~<br>~~es~~<br>~~ee~~|—<br>~~——y————~~<br>~~es~~<br>~~ee~~|—<br>~~——y————~~<br>~~es~~<br>~~ee ee~~|mV/ns<br>~~——y————~~<br>~~es~~<br>~~ee~~|
|||—<br>~~es~~<br><br>~~es~~|7<br>~~es~~<br>~~ee~~|—<br>~~es~~<br>~~ee~~|—<br>~~es~~<br>~~ee ee~~|mV/ns<br>~~es~~<br>~~ee~~|
||Slew Rate @ CLOAD= 0 to 70 pF (Rising Edge<br>Only)<br>~~ee ~~|—<br>~~es~~<br> <br>~~es~~|7 - 0.075 ×<br>(VO,INST -<br>700)<br>~~es~~<br> ~~ee~~|—<br>~~es~~<br>~~ee~~|—<br>~~es~~<br>~~ee ee~~|mV/ns<br>~~es~~<br>~~ee~~|
|||—<br>|7 - 0.0625 ×<br>(VO,INST -<br>550)<br> ~~ee~~|—<br>~~ee~~|—<br>~~ee ee~~|mV/ns<br>~~ee~~|
|CLOAD<br>~~-~~<br>~~a ~~|Load Capacitance<br> <br> ~~DFO~~|—<br> <br>~~DFO~~|0<br> ~~ee~~<br>~~DFO~~|—<br>~~ee~~<br>~~DFO~~|70<br>~~ee ee~~<br>~~DFO~~|pF<br>~~ee~~<br>~~DFO~~|
© 2021-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02049-1.8
135
**CrossLink-NX Family Data Sheet**
**Table 4.42. Hardened D-PHY Pin Characteristic Specifications**
|**Symbol**<br>**Description**<br>**Conditions**<br>**Min**<br>**Typ**<br>**Max**<br>**Unit**|
|---|
|**Pin Characteristic Specifications**<br>VPIN<br>Pin Signal Voltage Range<br>—<br>–50<br>—<br>1350<br>mV<br>VPIN_LVLP<br>Pin Signal Voltage Range in LVLP Operation<br>—<br>–50<br>—<br>1150<br>mV<br>ILEAK<br>Pin Leakage Current<br>—<br>–100<br>—<br>100<br>µA<br>VGNDSH<br>Ground Shift<br>—<br>–50<br>—<br>50<br>mV<br>VPIN(absmax)<br>Transient Pin Voltage Level<br>—<br>–0.15<br>—<br>1.45<br>V<br>TVPIN(absmax)<br>Maximum Transient Time above VPIN(max)or<br>below VPIN(min)<br>—<br>—<br>—<br>20<br>ns<br>~~Pee~~<br>~~esenn~~<br>~~I I (I I~~<br>~~ee~~<br>~~ee~~<br>~~nD~~<br>~~DD~~<br>~~ee~~<br>~~ry~~<br>~~tn SD I~~<br>~~eeerry~~<br>~~Ur~~<br>~~I I~~<br>~~a ee~~<br>~~ee eee~~|
|**Table 4.43. Hardened D-PHY Clock Signal Specification**|
|**Symbol**<br>**Description**<br>**Conditions**<br>**Min**<br>**Typ**<br>**Max**<br>**Unit**|
|**Clock Signal Specification**|
|UI<br>Instantaneous<br>UIINST<br>—<br>—<br>—<br>12.5<br>ns|
|—<br>–10%<br>—<br>10%<br>UI|
|UI Variation<br>∆UI|
|—<br>–5%<br>—<br>5%<br>UI|
**Table 4.43. Hardened D-PHY Clock Signal Specification**
**Table 4.44. Hardened D-PHY Data-Clock Timing Specifications**
|**Symbol**<br>~~ee~~|**Description**<br>~~nD~~|**Conditions**|**Min**|**Typ**|**Max**|**Unit**|
|---|---|---|---|---|---|---|
|**Data-Clock Timing Specifications**<br>~~ee~~<br>~~nD~~<br>~~Pee~~|||||||
|TSKEW[TX]<br>~~a~~|Data to Clock Skew<br>~~a~~|0.08 Gbps ≤ TSKEW[TX]<br>≤ 1.00 Gbps<br>~~a~~|–0.15<br>~~a~~|—<br>~~a~~|0.15<br>~~a~~|UIINST<br>~~a~~|
|||1.00 Gbps < TSKEW[TX]<br>≤ 1.50 Gbps<br>~~a~~<br>~~a~~|–0.20<br>~~a~~<br>~~a~~|—<br>~~a~~<br>~~a~~|0.20<br>~~a~~<br>~~a~~|UIINST<br>~~a~~<br>~~a~~|
|TSETUP[RX]<br>~~a~~<br>~~SE~~|Input Data Setup Before CLK<br>~~a~~<br>~~SE~~|0.08 Gbps ≤ TSETUP[RX]<br>≤ 1.00 Gbps<br>~~a~~<br>~~a~~<br>~~SE~~|0.247<br>~~a~~<br>~~a~~<br>~~SE~~|—<br>~~a~~<br>~~a~~<br>~~SE~~|—<br>~~a~~<br>~~a~~<br>~~SE~~|UI<br>~~a~~<br>~~a~~<br>~~SE~~|
|||1.00 Gbps < TSETUP[RX]<br>≤ 1.50 Gbps<br>~~SE~~<br>~~EL~~|0.37<br>~~SE~~<br>~~EL~~|—<br>~~SE~~<br>~~EL~~|—<br>~~SE~~<br>~~EL~~|UI<br>~~SE~~<br>~~EL~~|
|THOLD[RX]<br>~~SE~~|Input Data Hold After CLK<br>~~SE~~|0.08 Gbps ≤ THOLD[RX]<br>≤ 1.00 Gbps<br>~~SE~~|0.2<br>~~SE~~|—<br>~~SE~~|—<br>~~SE~~|UI<br>~~SE~~|
|||1.00 Gbps < THOLD[RX]<br>≤ 1.50 Gbps<br>~~SE~~<br>~~EL~~|0.3<br>~~SE~~<br>~~EL~~|—<br>~~SE~~<br>~~EL~~|—<br>~~SE~~<br>~~EL~~|UI<br>~~SE~~<br>~~EL~~|
|FIN_DPHY<br>~~Pee~~<br>~~a~~|Input frequencyto Hardened D-PHY PLL<br>~~Pee~~<br>~~a~~|—<br>~~Pee~~<br>~~ee~~|24<br>~~Pee~~<br>~~ee~~|~~Pee~~<br>~~ee~~|200<br>~~Pee~~<br>~~ee~~|MHz<br>~~Pee~~<br>~~ee~~|
|TSKEW[TX]<br>Dynamic<br>~~a~~<br>~~es~~|Dynamic Data to Clock Skew (Tx)<br>~~a~~|> 1.5 Gbps<br>~~ee~~|–0.15<br>~~ee~~|—<br>~~ee~~|0.15<br>~~ee~~|UIINST<br>~~ee~~|
|ISI<br>~~a ~~<br>~~es~~|Channel ISI<br> ~~a~~|> 1.5 Gbps<br>~~ee~~|—<br>~~ee~~|—<br>~~ee~~|0.20<br>~~ee ~~|UIINST<br> ~~ee~~|
|TSETUP[RX]+<br>THOLD[RX]<br>Dynamic<br>~~es~~|Dynamic Data to Clock Skew Window Rx<br>Tolerance|> 1.5 Gbps|0.57|—|—|UIINST|
© 2021-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
136
FPGA-DS-02049-1.8
**CrossLink-NX Family Data Sheet**
## **4.25. Hardened PCIe Characteristics**
## **4.25.1. PCIe (2.5 Gbps)**
**Table 4.45. PCIe (2.5 Gbps)**
|**Symbol**<br>~~Po~~|**Description**<br>~~eee~~|**Condition**<br>~~eee~~<br>~~ee~~|**Min.**<br>~~ee~~|**Typ. **|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|**Transmitter1**<br>~~Po~~<br>~~eee~~<br>~~ee~~<br>~~es~~<br>~~ns(GO~~|||||||
|UI<br>~~es~~<br>~~es~~|Unit Interval<br>~~ns~~<br>~~rs~~|—<br>~~(GO~~|399.88<br>~~(GO~~|400<br>~~(GO~~<br>~~(~~|400.12<br>~~(GO~~|ps<br>~~(GO~~|
|BWTX<br>~~es~~<br>~~es~~<br>~~ee~~|Tx PLL bandwidth<br>~~ns~~<br>~~rs~~<br>~~ee~~|—<br>~~(GO~~<br>~~es~~|1.5<br>~~(GO~~<br>~~es~~|—<br>~~(GO~~<br>~~(~~<br>~~ee~~|22<br>~~(GO~~|MHz<br>~~(GO~~|
|VTX-DIFF-PP<br>~~es~~<br>~~ee~~<br>~~ee~~|Differential p-p Tx voltage<br>swing<br>~~rs~~<br>~~ee~~<br>~~ee~~|—<br>~~es~~<br>~~es~~|0.8<br>~~es~~<br>~~es~~|—<br>~~(~~<br>~~ee~~<br>~~ee~~|1.2|Vp-p|
|VTX-DIFF-PP-LOW<br>~~ee~~<br>~~ee~~<br>~~ee~~|Low power differential p-p Tx<br>voltage swing<br>~~ee~~<br>~~ee~~<br>~~ee~~|—<br>~~es ~~<br>~~es~~<br>~~es~~|0.4<br> ~~es ~~<br>~~es~~<br>~~es~~|—<br> ~~ee~~<br>~~ee~~<br>~~ee~~|1.2|Vp-p|
|VTX-DE-RATIO-3.5dB<br>~~ee~~<br>~~ee~~<br>~~es~~|Tx de-emphasis level ratio at<br>3.5 dB<br>~~ee~~<br>~~ee~~<br>~~rs nr~~|—<br>~~es ~~<br>~~es~~<br>~~nr~~|3<br> ~~es ~~<br>~~es~~<br>~~I~~|—<br> ~~ee~~<br>~~ee~~<br>~~nD~~|4<br>~~I~~|dB|
|TTX-RISE-FALL<br>~~ee~~<br>~~es~~<br>~~SE~~|Transmitter rise and fall time<br>~~ee~~<br>~~rs nr~~<br>~~SE~~|—<br>~~es ~~<br>~~nr~~<br>|0.125<br> ~~es ~~<br>~~I~~<br>|—<br> ~~ee~~<br>~~nD~~<br>|—<br>~~I~~<br>|UI<br>|
|TTX-EYE<br>~~es~~<br>~~SE~~|Transmitter Eye, including all<br>jitter sources<br>~~rs nr~~<br>~~SEEE~~|—<br>~~nr~~<br>~~EE~~|0.75<br>~~I~~<br>~~EE~~|—<br>~~nD ~~<br>~~EE~~|—<br> ~~I~~<br>~~EE~~|UI<br>~~EE~~|
|TTX-EYE-MEDIAN-to-MAX-<br>JITTER<br>~~SE~~<br>~~a~~|Max. time between jitter<br>median and max deviation<br>from the median<br>~~SEEE~~<br>~~es~~|—<br>~~EE~~<br>~~es~~|—<br>~~EE~~<br>~~ee~~|—<br>~~EE~~<br>~~ee~~|0.125<br>~~EE~~<br>~~ee~~|UI<br>~~EE~~<br>~~ee~~|
|RLTX-DIFF<br>~~SE~~<br>~~a~~<br>~~a~~|Tx Differential Return Loss,<br>including pkgand silicon<br>~~SEEE~~<br>~~es~~<br>~~es~~|—<br>~~EE~~<br>~~es~~<br>~~es~~|10<br>~~EE~~<br>~~ee~~<br>~~ee~~|—<br>~~EE~~<br>~~ee~~<br>~~ee~~|—<br>~~EE~~<br>~~ee~~<br>~~ee~~|dB<br>~~EE~~<br>~~ee~~<br>~~ee~~|
|RLTX-CM<br>~~a~~<br>~~a~~<br>~~es~~|Tx Common Mode Return Loss,<br>including pkgand silicon<br>~~es~~<br>~~es~~<br>~~rs~~|50 MHz < freq < 2.5 GHz<br>~~es ~~<br>~~es~~|6<br> ~~ee ~~<br>~~ee~~|—<br> ~~ee~~<br>~~ee~~<br>~~(~~|—<br>~~ee~~<br>~~ee~~|dB<br>~~ee~~<br>~~ee~~|
|ZTX-DIFF-DC<br>~~a~~<br>~~es~~<br>~~ee~~|DC differential Impedance<br>~~es~~<br>~~rs~~<br>~~es~~|—<br>~~es ~~<br>~~es~~|80<br> ~~ee ~~<br>~~es~~|—<br> ~~ee~~<br>~~(~~<br>~~ee~~|120<br>~~ee~~|Ω<br>~~ee~~|
|VTX-CM-AC-P<br>~~es~~<br>~~ee~~<br>~~ee~~|Tx AC peak common mode<br>voltage, RMS<br>~~rs~~<br>~~es~~<br>~~ee~~|—<br>~~es~~<br>~~es~~|—<br>~~es~~<br>~~es~~|—<br>~~(~~<br>~~ee~~<br>~~ee~~|20|mV,<br>RMS|
|ITX-SHORT<br>~~ee~~<br>~~ee~~<br>~~ee~~|Transmitter short-circuit<br>current<br>~~es~~<br>~~ee~~<br>~~ee~~|—<br>~~es ~~<br>~~es~~<br>~~es~~|—<br> ~~es ~~<br>~~es~~<br>~~es~~|—<br> ~~ee~~<br>~~ee~~<br>~~ee~~|90|mA|
|VTX-DC-CM<br>~~ee ~~<br>~~ee~~<br>~~ee~~|Transmitter DC common-mode<br>voltage<br> ~~ee ~~<br>~~ee~~<br>~~ee~~|—<br> ~~es ~~<br>~~es~~<br>~~es~~|0<br> ~~es ~~<br>~~es~~<br>~~es~~|—<br> ~~ee~~<br>~~ee~~<br>~~ee~~|1.2<br>~~ee~~|V<br>~~ee~~|
|VTX-IDLE-DIFF-AC-p<br>~~ee ~~<br>~~ee~~<br>~~ee~~|Electrical Idle Output peak<br>voltage<br> ~~ee ~~<br>~~ee~~<br>~~ee~~|—<br> ~~es ~~<br>~~es~~<br>~~es~~|—<br> ~~es ~~<br>~~es~~<br>~~ee~~|—<br> ~~ee~~<br>~~ee~~<br>~~ee~~|20<br>~~ee~~<br>~~ee~~|mV<br>~~ee~~|
|VTX-RCV-DETECT<br>~~ee~~<br>~~ee~~<br>~~es~~|Voltage change allowed during<br>Receiver Detect<br>~~ee~~<br>~~ee~~<br>~~nts~~|—<br>~~es ~~<br>~~es~~|—<br> ~~es ~~<br>~~ee~~|—<br> ~~ee ~~<br>~~ee~~|600<br> ~~ee~~<br>~~ee~~|mV<br>~~ee~~|
|TTX-IDLE-MIN<br>~~ee~~<br>~~es~~<br>~~ee~~|Min. time in Electrical Idle<br>~~ee~~<br>~~nts~~<br>~~ee~~|—<br>~~es ~~<br>~~es~~|20<br> ~~ee ~~<br>~~es~~|—<br> ~~ee ~~<br>~~ee~~|—<br> ~~ee~~|ns|
|TTX-IDLE-SET-TO-IDLE<br>~~es~~<br>~~ee~~<br>~~ee~~|Max. time from EI Order Set to<br>valid Electrical Idle<br>~~nts~~<br>~~ee~~<br>~~ee~~|—<br>~~es~~<br>~~es~~|—<br>~~es~~<br>~~es~~|—<br>~~ee~~<br>~~ee~~|8|ns|
|TTX-IDLE-TO-DIFF-DATA<br>~~ee ~~<br>~~ee~~<br>~~ee~~|Max. time from Electrical Idle<br>to valid differential output<br> ~~ee ~~<br>~~ee~~<br>~~ee~~|—<br> ~~es ~~<br>~~es~~<br>~~es~~|—<br> ~~es ~~<br>~~es~~<br>~~es~~|—<br> ~~ee~~<br>~~ee~~<br>~~ee~~|8<br>~~ee~~|ns|
|LTX-SKEW<br>~~ee ~~<br>~~ee~~|Lane-to-Lane output skew<br> ~~ee ~~<br>~~ee~~|—<br> ~~es ~~<br>~~es~~|—<br> ~~es ~~<br>~~es~~|—<br> ~~ee~~<br>~~ee~~|500 ps<br>+ 2 UI<br>~~ee~~|ps|
|**Receiver2**<br>~~ee~~<br>~~ee es es ee ee~~<br>~~es~~<br>~~rsnnn~~<br>~~I~~<br>~~I~~|||||||
|UI<br>~~es~~<br>~~a~~|Unit Interval<br>~~rs~~<br>~~ee~~|—<br>~~nnn~~<br>~~es~~|399.9<br>~~ee~~|400<br>~~I~~<br>~~ee~~|400.12<br>~~I~~<br>~~ee~~|ps<br>~~ee~~|
|VRX-DIFF-PP<br>~~es~~<br>~~a~~<br>~~es~~|Differential Rx peak-peak<br>voltage<br>~~rs ~~<br>~~ee~~<br>~~es~~|—<br> ~~nnn~~<br>~~es~~|0.175<br>~~ee~~|—<br>~~I~~<br>~~ee~~|1.2<br>~~I~~<br>~~ee~~|Vp-p<br>~~ee~~|
|TRX-EYE3<br>~~a~~<br>~~es~~|Receiver eye openingtime<br>~~ee~~<br>~~es~~|—<br>~~es ~~|0.4<br> ~~ee~~|—<br>~~ee~~|—<br>~~ee~~|UI<br>~~ee~~|
|TRX-EYE-MEDIAN-to-MAX-<br>JITTER3<br>~~es~~<br>~~a~~|Max time delta between<br>median and deviation from<br>median<br>~~es~~<br>~~a~~|—<br>~~ee~~|—|—<br>~~ee~~|0.3<br>~~ee~~|UI<br>~~ee~~|
|RLRX-DIFF<br>~~es~~<br>~~a~~|Receiver differential Return<br>Loss,packageplus silicon<br>~~es~~<br>~~a~~|—<br>~~ee~~|10|—<br>~~ee~~|—<br>~~ee~~|dB<br>~~ee~~|
© 2021-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02049-1.8
137
**CrossLink-NX Family Data Sheet**
|**Symbol**<br>~~es~~<br>~~ae~~|**Description**<br>~~ns~~<br>~~ee~~|**Condition**<br>~~(I~~<br>~~ee~~|**Min.**<br>~~(I~~<br>~~ee~~|**Typ. **<br>~~(I~~|**Max.**<br>~~I~~<br>~~ee~~|**Unit**<br>~~ee~~|
|---|---|---|---|---|---|---|
|RLRX-CM<br>~~es~~<br>~~ae~~<br>~~ae~~|Receiver common mode Return<br>Loss,packageplus silicon<br>~~ns~~<br>~~ee~~<br>~~ee~~|—<br>~~(I~~<br>~~ee~~<br>~~ee~~|6<br>~~(I~~<br>~~ee~~<br>~~ee~~|—<br>~~(I~~|—<br>~~I~~<br>~~ee~~|dB<br>~~ee~~|
|ZRX-DC<br>~~ae~~<br>~~ae~~<br>~~es~~|Receiver DC single ended<br>impedance<br>~~ee~~<br>~~ee~~|—<br>~~ee ~~<br>~~ee~~|40<br> ~~ee~~<br>~~ee~~|—|60<br>~~ee~~|Ω<br>~~ee~~|
|ZRX-DIFF-DC<br>~~ae~~<br>~~es~~|Receiver DC differential<br>impedance<br>~~ee~~|—<br>~~ee ~~|80<br> ~~ee~~|—|120|Ω|
|ZRX-HIGH-IMP-DC<br>~~es~~<br>~~ae~~|Receiver DC single ended<br>impedance when powered<br>down<br>~~ee~~|—<br>~~ee~~|200<br>~~ee~~|—|—<br>~~ee~~|kΩ<br>~~ee~~|
|VRX-CM-AC-P3<br>~~es~~<br>~~ae~~<br>~~es~~|Rx AC peak common mode<br>voltage<br>~~ee~~<br>~~rs~~|—<br>~~ee~~<br>~~(~~|—<br>~~ee~~<br>~~(~~|—<br>~~(~~|150<br>~~ee~~|mV,<br>peak<br>~~ee~~|
|VRX-IDLE-DET-DIFF-PP<br>~~ae ~~<br>~~es~~|Electrical Idle Detect Threshold<br> ~~ee ~~<br>~~rs~~|—<br> ~~ee ~~<br>~~(~~|65<br> ~~ee~~<br>~~(~~|—<br>~~(~~|175<br>~~ee~~|mVp-p<br>~~ee~~|
|LRX-SKEW<br>~~es~~<br>~~Pe~~|Receiver –lane-lane skew<br>~~rs~~<br>~~Pe~~|—<br>~~(~~<br>~~Pe~~|—<br>~~(~~<br>~~Pe~~|—<br>~~(~~<br>~~Pe~~|20<br>~~Pe~~|ps<br>~~Pe~~|
**Notes:**
1. Refer to PCI Express Base Specification Revision 3.0 Table 4.18 test condition and requirement for respective parameters.
2. Refer to PCI Express Base Specification Revision 3.0 Table 4.24 test condition and requirement for respective parameters.
3. Spec compliant requirement
## **4.25.2. PCIe (5 Gbps)**
**Table 4.46. PCIe (5 Gbps)**
|**Symbol**<br>~~Pr~~|**Description**<br>~~eee~~|**Test Conditions**<br>~~eee~~<br>~~ee~~|**Min**<br>~~ee~~|**Typ**|**Max**|**Unit**|
|---|---|---|---|---|---|---|
|**Transmit1**<br>~~Pr~~<br>~~eee~~<br>~~ee~~<br>~~eee~~|||||||
|UI<br>~~Poe~~<br>~~a~~|Unit Interval<br>~~Poe~~<br>~~ee~~|—<br>~~Poe~~<br>~~ee~~|199.94<br>~~Poe~~<br>~~ee~~|200<br>~~Poe~~<br>~~es~~|200.06<br>~~Poe~~<br>~~ee~~|ps<br>~~Poe~~<br>~~ee~~|
|BWTX-PKG-PLL1<br>~~a~~<br>~~a~~|Tx PLL bandwidth<br>correspondingto PKGTX-PLL1<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~|8<br>~~ee~~<br>~~ee~~|—<br>~~es~~<br>~~es~~|16<br>~~ee~~<br>~~ee~~|MHz<br>~~ee~~<br>~~ee~~|
|BWTX-PKG-PLL2<br>~~a~~<br>~~a~~<br>~~a~~|Tx PLL bandwidth<br>correspondingto PKGTX-PLL2<br>~~ee~~<br>~~ee~~<br>~~ee~~|—<br>~~ee ~~<br>~~ee~~<br>~~ee~~|5<br> ~~ee ~~<br>~~ee~~<br>~~ee~~|—<br> ~~es~~<br>~~es~~<br>~~ee~~|16<br>~~ee~~<br>~~ee~~<br>~~ee~~|MHz<br>~~ee~~<br>~~ee~~<br>~~ee~~|
|PKGTX-PLL1<br>~~a~~<br>~~a~~<br>~~a~~|Tx PLL Peaking<br>correspondingto PKGTX-PLL1<br>~~ee~~<br>~~ee~~<br>~~a~~|—<br>~~ee ~~<br>~~ee~~<br>~~ee~~|—<br> ~~ee ~~<br>~~ee~~<br>~~ee~~|—<br> ~~es~~<br>~~ee~~<br>~~ee~~|3<br>~~ee~~<br>~~ee~~<br>~~eee~~|dB<br>~~ee~~<br>~~ee~~<br>~~eee~~|
|PKGTX-PLL2<br>~~a~~<br>~~a~~<br>~~a~~|Tx PLL Peaking<br>correspondingto PKGTX-PLL2<br>~~ee~~<br>~~a~~<br>~~ee ee~~|—<br>~~ee ~~<br>~~ee~~<br>~~ee~~|—<br> ~~ee~~<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~<br>~~ee~~|1<br>~~ee ~~<br>~~eee~~<br>~~ee~~|dB<br> ~~ee~~<br>~~eee~~<br>~~ee~~|
|VTX-DIFF-PP<br>~~a ~~<br>~~a~~<br>~~a~~|Differential p-p Tx voltage<br>swing<br> ~~a~~<br>~~ee ee~~<br>~~ee ee~~|—<br>~~ee ~~<br>~~ee~~<br>~~ee~~|0.8<br> ~~ee ~~<br>~~ee~~<br>~~ee~~|—<br> ~~ee ~~<br>~~ee~~<br>~~ee~~|1.2<br> ~~eee~~<br>~~ee~~<br>~~ee~~|V, p-p<br>~~eee~~<br>~~ee~~<br>~~ee~~|
|VTX-DIFF-PP-LOW<br>~~a~~<br>~~a~~<br>~~a~~|Low power differential p-p Tx<br>voltage swing<br>~~ee ee~~<br>~~ee ee~~<br>~~ee ee~~|—<br>~~ee ~~<br>~~ee~~<br>~~ee~~|0.4<br> ~~ee~~<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~<br>~~ee~~|1.2<br>~~ee~~<br>~~ee~~<br>~~ee~~|V, p-p<br>~~ee~~<br>~~ee~~<br>~~ee~~|
|VTX-DE-RATIO-3.5dB<br>~~a~~<br>~~a~~<br>~~a~~|Tx de-emphasis level ratio at<br>3.5 dB<br>~~ee ee~~<br>~~ee ee~~<br>~~ee ee~~|—<br>~~ee ~~<br>~~ee~~<br>~~ee~~|3<br> ~~ee~~<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~<br>~~ee~~|4<br>~~ee~~<br>~~ee~~<br>~~ee~~|dB<br>~~ee~~<br>~~ee~~<br>~~ee~~|
|VTX-DE-RATIO-6dB<br>~~a~~<br>~~a~~<br>~~esDn~~<br>~~es~~|Tx de-emphasis level ratio at<br>6 dB<br>~~ee ee~~<br>~~ee ee~~<br>~~Dn~~|—<br>~~ee ~~<br>~~ee~~<br>~~Dn~~|5.5<br> ~~ee~~<br>~~ee~~<br>~~Dn~~<br>~~(~~|—<br>~~ee~~<br>~~ee~~<br>~~Dn~~|6.5<br>~~ee~~<br>~~ee~~<br>~~Dn~~|dB<br>~~ee~~<br>~~ee~~<br>~~Dn~~|
|TMIN-PULSE<br>~~a~~<br>~~esDn~~<br>~~es~~<br>~~a~~|Instantaneous lonepulse width<br>~~ee ee~~<br>~~Dn~~<br>~~nD~~|—<br>~~ee ~~<br>~~Dn~~|0.9<br> ~~ee~~<br>~~Dn~~<br>~~(~~|—<br>~~ee~~<br>~~Dn~~|—<br>~~ee~~<br>~~Dn~~|UI<br>~~ee~~<br>~~Dn~~|
|TTX-RISE-FALL<br>~~esDn~~<br>~~es~~<br>~~a~~<br>~~a~~|Transmitter rise and fall time<br>~~Dn~~<br>~~nD~~<br>~~ee~~|—<br>~~Dn~~<br>~~ee~~|0.15<br>~~Dn~~<br>~~(~~<br>~~ee~~|—<br>~~Dn~~<br>~~ee~~|—<br>~~Dn~~<br>~~ee~~|UI<br>~~Dn~~<br>~~ee~~|
|TTX-EYE<br>~~es~~<br>~~a~~<br>~~a~~<br>~~a~~|Transmitter Eye, including all<br>jitter sources<br>~~nD~~<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~|0.75<br>~~(~~<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~|UI<br>~~ee~~<br>~~ee~~|
|TTX-DJ<br>~~a~~<br>~~a~~<br>~~a~~<br>~~es~~|Tx deterministic jitter > 1.5<br>MHz<br>~~nD~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>|—<br>~~ee~~<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~<br>~~ee~~|0.15<br>~~ee~~<br>~~ee~~<br>~~ee~~|UI<br>~~ee~~<br>~~ee~~<br>~~ee~~|
|TTX-RJ<br>~~a~~<br>~~a~~<br>~~es~~|Tx RMS jitter < 1.5 MHz<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~es~~|—<br>~~ee ~~<br>~~ee~~<br>~~ee~~<br>~~rr (Is~~|—<br> ~~ee ~~<br>~~ee~~<br>~~ee~~<br>~~(Is~~|—<br> ~~ee~~<br>~~ee~~<br>~~ee~~<br>~~I~~|3<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~I~~|ps,<br>RMS<br>~~ee~~<br>~~ee~~<br>~~ee~~|
|TRF-MISMATCH<br>~~a~~<br>~~es~~<br>~~Bf~~|Tx rise/fall time mismatch<br>~~ee~~<br>~~ee~~<br>~~es~~<br>~~Bf~~|—<br>~~ee ~~<br>~~ee~~<br>~~rr (Is~~|—<br> ~~ee ~~<br>~~ee~~<br>~~(Is~~<br>~~+~~|—<br> ~~ee~~<br>~~ee~~<br>~~I~~<br>~~+~~|0.1<br>~~ee~~<br>~~ee~~<br>~~I~~<br>~~+~~|UI<br>~~ee~~<br>~~ee~~<br>~~—~~|
|RLTX-DIFF<br>~~es ~~<br>~~Bf~~|Tx Differential Return Loss,<br>including package and silicon<br>~~ee~~<br> ~~es~~<br>~~Bf~~<br>~~es~~|50 MHz < freq< 1.25 GHz<br>~~ee ~~<br>~~rr (Is~~|10<br> ~~ee ~~<br>~~(Is ~~<br>~~+~~<br>~~ee~~|—<br> ~~ee~~<br> ~~I ~~<br>~~+~~|—<br>~~ee~~<br> ~~I~~<br>~~+~~|dB<br>~~ee~~<br>~~—~~|
|||1.25 GHz < freq< 2.5 GHz<br>~~es~~|8<br>~~+~~<br>~~es~~<br>~~ee~~|—<br>~~+~~<br>~~es~~|—<br>~~+~~<br>~~es~~|dB<br>~~—~~<br>~~es~~|
© 2021-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
138
FPGA-DS-02049-1.8
**CrossLink-NX Family Data Sheet**
|**Symbol**<br>~~Pr~~<br>~~ae~~|**Description**<br>~~ee~~<br>~~ee~~|**Test Conditions**<br>~~ee~~<br>~~et~~<br>~~ee~~|**Min**<br>~~et~~<br>~~ee~~|**Typ**<br>~~es~~|**Max**<br>~~ee~~|**Unit**<br>~~ee~~|
|---|---|---|---|---|---|---|
|RLTX-CM<br>~~Pr~~<br>~~ae~~<br>~~es~~|Tx Common Mode Return Loss,<br>including package and silicon<br>~~ee~~<br>~~ee~~<br>~~nD nn~~|50 MHz < freq < 2.5 GHz<br>~~ee~~<br>~~et~~<br>~~ee~~<br>~~nn~~|6<br>~~et~~<br>~~ee~~<br>~~(TD~~|—<br>~~es~~<br>~~I~~|—<br>~~ee~~<br>~~I~~|dB<br>~~ee~~|
|ZTX-DIFF-DC<br>~~ae~~<br>~~es~~<br>~~a~~|DC differential Impedance<br>~~ee~~<br>~~nD nn~~<br>~~ee es~~|—<br>~~ee ~~<br>~~nn~~<br>~~es~~|—<br> ~~ee ~~<br>~~(TD~~<br>~~es~~|—<br> ~~es~~<br>~~I~~<br>~~es~~|120<br>~~ee~~<br>~~I~~|Ω<br>~~ee~~|
|VTX-CM-AC-PP<br>~~es~~<br>~~a~~<br>~~a~~|Tx AC peak common mode<br>voltage, peak-peak<br>~~nD nn~~<br>~~ee es~~<br>~~ee~~|—<br>~~nn~~<br>~~es~~<br>~~ee~~|—<br>~~(TD ~~<br>~~es~~<br>~~ee~~|—<br> ~~I ~~<br>~~es~~<br>~~ee~~|150<br> ~~I~~<br>~~eee~~|mV,<br>p-p<br>~~eee~~|
|ITX-SHORT<br>~~a~~<br>~~a~~<br>~~a~~|Transmitter short-circuit<br>current<br>~~ee es~~<br>~~ee~~<br>~~ee~~|—<br>~~es ~~<br>~~ee~~<br>~~ee~~|—<br> ~~es ~~<br>~~ee~~<br>~~ee~~|—<br> ~~es~~<br>~~ee~~<br>~~ee~~|90<br>~~eee~~<br>~~eee~~|mA<br>~~eee~~<br>~~eee~~|
|VTX-DC-CM<br>~~a~~<br>~~a~~<br>~~a~~|Transmitter DC common-mode<br>voltage<br>~~ee ~~<br>~~ee~~<br>~~ee~~|—<br> ~~ee ~~<br>~~ee~~<br>~~ee~~|0<br> ~~ee ~~<br>~~ee~~<br>~~ee~~|—<br> ~~ee ~~<br>~~ee~~<br>~~ee~~|1.2<br> ~~eee~~<br>~~eee~~<br>~~eee~~|V<br>~~eee~~<br>~~eee~~<br>~~eee~~|
|VTX-IDLE-DIFF-DC<br>~~a~~<br>~~a~~<br>~~a~~|Electrical Idle Output DC<br>voltage<br>~~ee ~~<br>~~ee~~<br>~~ee~~|—<br> ~~ee ~~<br>~~ee~~<br>~~ee~~|0<br> ~~ee ~~<br>~~ee~~<br>~~ee~~|—<br> ~~ee ~~<br>~~ee~~<br>~~ee~~|5<br> ~~eee~~<br>~~eee~~<br>~~ee~~|mV<br>~~eee~~<br>~~eee~~<br>~~ee~~|
|VTX-IDLE-DIFF-AC-p<br>~~a~~<br>~~a~~<br>~~a~~|Electrical Idle Differential<br>Outputpeak voltage<br>~~ee ~~<br>~~ee~~<br>~~ee~~|—<br> ~~ee ~~<br>~~ee~~<br>~~ee~~|—<br> ~~ee ~~<br>~~ee~~<br>~~ee~~|—<br> ~~ee ~~<br>~~ee~~|20<br> ~~eee~~<br>~~ee~~<br>~~ee~~|mV<br>~~eee~~<br>~~ee~~<br>~~ee~~|
|VTX-RCV-DETECT<br>~~a~~<br>~~a~~<br>~~es~~|Voltage change allowed during<br>Receiver Detect<br>~~ee ~~<br>~~ee~~<br>~~ns I~~|—<br> ~~ee ~~<br>~~ee~~<br>~~I~~|—<br> ~~ee ~~<br>~~ee~~<br>~~ED~~|—<br> ~~ee~~<br>~~I~~|600<br>~~ee~~<br>~~ee~~<br>~~I~~|mV<br>~~ee~~<br>~~ee~~|
|TTX-IDLE-MIN<br>~~a~~<br>~~es~~<br>~~a~~|Min. time in Electrical Idle<br>~~ee~~<br>~~ns I~~<br>~~ee~~|—<br>~~ee ~~<br>~~I~~<br>~~ee~~|20<br> ~~ee~~<br>~~ED~~<br>~~ee~~|—<br>~~I~~<br>~~ee~~|—<br>~~ee~~<br>~~I~~<br>~~eee~~|ns<br>~~ee~~<br>~~eee~~|
|TTX-IDLE-SET-TO-IDLE<br>~~es~~<br>~~a~~<br>~~a~~|Max. time from EI Order Set to<br>valid Electrical Idle<br>~~ns I~~<br>~~ee~~<br>~~ee~~|—<br>~~I~~<br>~~ee~~<br>~~ee~~|—<br>~~ED ~~<br>~~ee~~<br>~~ee~~|—<br> ~~I ~~<br>~~ee~~<br>~~ee~~|8<br> ~~I~~<br>~~eee~~<br>~~eee~~|ns<br>~~eee~~<br>~~eee~~|
|TTX-IDLE-TO-DIFF-DATA<br>~~a~~<br>~~a~~<br>~~a~~|Max. time from Electrical Idle<br>to valid differential output<br>~~ee ~~<br>~~ee~~<br>~~ee ee~~|—<br> ~~ee ~~<br>~~ee~~<br>~~ee~~|—<br> ~~ee ~~<br>~~ee~~<br>~~ee~~|—<br> ~~ee ~~<br>~~ee~~<br>~~ee~~|8<br> ~~eee~~<br>~~eee~~<br>~~ee~~|ns<br>~~eee~~<br>~~eee~~<br>~~ee~~|
|LTX-SKEW<br>~~a~~<br>~~a~~|Lane-to-Lane output skew<br>~~ee ~~<br>~~ee ee~~|—<br> ~~ee ~~<br>~~ee~~|—<br> ~~ee ~~<br>~~ee~~|—<br> ~~ee ~~<br>~~ee~~|500 + 4<br>UI<br> ~~eee~~<br>~~ee~~|ps<br>~~eee~~<br>~~ee~~|
|**Receive2**<br>~~a ee ee ee ee~~<br>~~ee~~<br>~~eee~~<br>~~ee~~<br>~~nnI~~<br>~~(OS(I~~|||||||
|UI<br>~~eee~~<br>~~ee~~<br>~~ae~~|Unit Interval<br>~~eee~~<br>~~nn~~<br>~~ee~~|—<br>~~eee~~<br>~~I~~<br>~~ee~~|199.94<br>~~eee~~<br>~~(OS~~<br>~~ee~~|200<br>~~eee~~<br>~~(I~~<br>~~ee~~|200.06<br>~~eee~~<br>~~ee~~|ps<br>~~eee~~<br>~~ee~~|
|VRX-DIFF-PP<br>~~ee~~<br>~~ae~~<br>~~ee~~|Differential Rx peak-peak<br>voltage<br>~~nn ~~<br>~~ee~~<br>~~ee Ge~~|—<br> ~~I~~<br>~~ee~~<br>~~Ge~~|0.343<br>~~(OS~~<br>~~ee~~<br>~~ee~~|—<br>~~(I~~<br>~~ee~~<br>~~ee~~|1.2<br>~~ee~~|V, p-p<br>~~ee~~|
|TRX-RJ-RMS<br>~~ae~~<br>~~ee~~<br>~~ee~~|Receiver random jitter<br>tolerance(RMS)<br>~~ee ~~<br>~~ee Ge~~<br>~~ee Ge~~|1.5 MHz – 100 MHz<br>Random noise<br> ~~ee ~~<br>~~Ge~~<br>~~Ge~~|—<br> ~~ee~~<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~<br>~~ee~~|4.2<br>~~ee~~|ps,<br>RMS<br>~~ee~~|
|TRX-DJ<br>~~ee~~<br>~~ee~~<br>~~ff~~|Receiver deterministic jitter<br>tolerance<br>~~ee Ge~~<br>~~ee Ge~~<br>~~ff~~|—<br>~~Ge~~<br>~~Ge~~<br>~~ff~~|—<br>~~ee~~<br>~~ee~~<br>~~ff~~|—<br>~~ee~~<br>~~ee~~<br>~~+}~~|88<br>~~+}~~|ps<br>~~+}~~|
|RLRX-DIFF<br>~~ee~~<br>~~ff~~<br>~~es~~|Receiver differential Return<br>Loss, package plus silicon<br>~~ee Ge~~<br>~~ff~~<br>~~es~~|50 MHz < freq< 1.25 GHz<br>~~Ge~~<br>~~ff~~|10<br>~~ee~~<br>~~ff~~|—<br>~~ee~~<br>~~+}~~|—<br>~~+}~~|dB<br>~~+}~~|
|||1.25 GHz < freq< 2.5 GHz<br>~~ff~~|8<br>~~ff~~|—<br>~~+}~~|—<br>~~+}~~|dB<br>~~+}~~|
|RLRX-CM<br>~~ff~~<br>~~es~~|Receiver common mode<br>Return Loss, package plus<br>silicon<br>~~ff~~<br>~~es~~|—<br>~~ff~~|6<br>~~ff ~~|—<br> ~~+}~~|—<br>~~+}~~|dB<br>~~+}~~|
|ZRX-DC<br>~~es~~<br>~~a~~|Receiver DC single ended<br>impedance<br>~~es~~|—|40|—|60|Ω|
|ZRX-HIGH-IMP-DC<br>~~a~~<br>~~ee~~|Receiver DC single ended<br>impedance when powered<br>down<br>~~ee~~|—<br>~~ee~~|200<br>~~ee~~|—<br>~~ee~~|—<br>~~eee~~|kΩ<br>~~eee~~|
|VRX-CM-AC-P3<br>~~a~~<br>~~ee~~<br>~~es~~|Rx AC peak common mode<br>voltage<br>~~ee~~<br>~~DG~~|—<br>~~ee~~<br>~~DG~~|—<br>~~ee~~<br>~~DG~~|—<br>~~ee~~<br>~~DG~~|150<br>~~eee~~<br>~~DG~~|mV,<br>peak<br>~~eee~~<br>~~DG~~|
|VRX-IDLE-DET-DIFF-PP<br>~~ee ~~<br>~~es~~|Electrical Idle Detect Threshold<br> ~~ee~~<br>~~DG~~|—<br>~~ee~~<br>~~DG~~<br>~~ee~~|65<br>~~ee~~<br>~~DG~~<br>~~ee~~|—<br>~~ee ~~<br>~~DG~~|1753<br> ~~eee~~<br>~~DG~~|mv,pp<br>~~eee~~<br>~~DG~~|
|LRX-SKEW<br>~~es~~<br>~~Pe~~|Receiver –lane-lane skew<br>~~DG~~<br>~~Pe~~|—<br>~~DG~~<br>~~Pe~~<br>~~ee~~|—<br>~~DG~~<br>~~Pe~~<br>~~ee~~|—<br>~~DG~~<br>~~Pe~~|8<br>~~DG~~<br>~~Pe~~|ns<br>~~DG~~<br>~~Pe~~|
2. Refer to PCI Express Base Specification Revision 3.0 Table 4.24 test condition and requirement for respective parameters.
3. Spec compliant requirement
© 2021-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02049-1.8
139
**CrossLink-NX Family Data Sheet**
## **4.26. SGMII Characteristics**
## **4.26.1. SGMII Specifications**
**Table 4.47. SGMII**
|**Symbol**|**Description**|**Test Conditions**|**Min**|**Typ**|**Max**|**Unit**|
|---|---|---|---|---|---|---|
|fDATA|SGMII Data Rate|—|—|1250|—|MHz|
|fREFCLK|SGMII Reference Clock Frequency (Data<br>Rate / 10)|—|—|125|—|MHz|
|JTOL_Dj|Jitter Tolerance, Deterministic|Periodic jitter<br>< 300 kHz|—|—|0.11|UI|
|JTOL_Tj|Jitter Tolerance, Total|Periodic jitter<br>< 300 kHz|—|—|0.31|UI|
|Δf/f|Data Rate and Reference Clock Accuracy|—|–300|—|300|ppm|
## **Notes:**
1. JTOT can meet the following jitter mask specification: 0 to 3.5 kHz: 10 UI; 3.5 to 700 kHz: log-log slope 10 UI to 0.05 UI; above 700 kHz: 0.05 UI.
2. SGMII is not supported on 72-pin packages (QFN and WLCSP).
## **4.27. sysCONFIG Port Timing Specifications**
**Table 4.48. sysCONFIG Port Timing Specifications**
|**Symbol**<br>~~a~~<br>~~Sa~~|**Parameter**<br>~~a~~|**Device**<br>~~a~~|**Min**<br>~~a~~|**Typ.**<br>~~a~~|**Max**<br>~~a~~|**Unit**<br>~~a~~|
|---|---|---|---|---|---|---|
|**Master SPI POR/REFRESH Timing**<br>~~aa~~<br>~~Sa~~|||||||
|tICFG<br>~~Sa~~|REFRESH command executed, to the last rising<br>edge of INITN (bulk-erase off)|—|—|—|30|µs|
|tVMC<br>~~a~~|Time from last rising edge of INITN to the valid<br>Master MCLK|—|—|—|5|µs|
|fMCLK_DEF<br>~~a~~|Default MCLK frequency (Before MCLK<br>frequency selection in bitstream)|—|—|3.5|—|MHz|
|tICFG_POR<br>~~a~~|frequency selection in bitstream)<br>Time during POR, from VCC, VCCAUX, VCCIO0,<br>or VCCIO1 (whichever is the last) pass POR trip<br>|—<br>|—<br>|—<br>|5<br>|ms<br>|
|**Slave SPI/I2C/I3C POR**<br>~~aa)~~|||||||
|tMSPI_INH|Time during POR, from VCC, VCCAUX, VCCIO0or<br>VCCIO1(whichever is the last) pass POR trip<br>voltage, to pull PROGRAMN LOW to prevent<br>entering MSPI mode|—|—|—|1|µs|
|tACT_PROGRAMN_H<br>~~a~~|Minimum time driving PROGRAMN HIGH after<br>last activation clock<br>~~a~~|—<br>~~a~~|50<br>~~a~~|—<br>~~a~~|—<br>~~a~~|ns<br>~~a~~|
|tCONFIG_CCLK<br>~~eo~~<br>~~Ps~~|Minimum time to start driving CCLK (SSPI)<br>after PROGRAMN HIGH<br>~~eo~~|—<br>~~eo~~|50<br>~~eo~~|—<br>~~eo~~|—<br>~~eo~~|ns<br>~~eo~~|
|tCONFIG_SCL<br>~~eo~~<br>~~Ps~~|Minimum time to start driving SCL (I2C/I3C)<br>after PROGRAMN HIGH<br>~~eo~~|—<br>~~eo~~|50<br>~~eo~~|—<br>~~eo~~|—<br>~~eo~~|ns<br>~~eo~~|
|**PROGRAMN Configuration Timing**<br>~~Ps~~<br>~~a)~~|||||||
|tPROGRAMN<br>~~a~~|PROGRAMN LOWpulse accepted|—|50|—|—|ns|
|tPROGRAMN_RJ<br>~~a~~|PROGRAMN LOW pulse rejected|—|—|—|25|ns|
|tINIT_LOW<br>~~a~~<br>~~a~~|PROGRAMN LOW to INITN LOW<br>|—<br><br>~~a~~|—<br><br>|—<br>|100<br>|ns<br>~~—~~|
|tINIT_HIGH<br>~~ee~~|PROGRAMN LOW to INITN HIGH (bulk-erase<br>off)<br>~~ee~~|LIFCL-40<br>~~ee~~<br>~~a~~|—<br>~~ee~~<br>|30<br>~~ee~~|—<br>~~ee~~|µs<br>~~ee—~~|
|||LIFCL-17<br>~~ee~~<br>~~a~~|—<br>~~ee~~<br>~~a~~|30<br>~~ee~~|—<br>~~ee~~|µs<br>~~ee—~~|
|tDONE_LOW<br><br>~~a~~|PROGRAMN LOW to DONE LOW<br>|—<br><br>~~a ~~|—<br><br>|—<br>|55<br>|µs<br>~~—~~|
© 2021-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
140
FPGA-DS-02049-1.8
**CrossLink-NX Family**
**Data Sheet**
|**Symbol**<br>~~eG~~|**Parameter**<br>~~eG~~|**Device**<br>~~eG~~|**Min**<br>~~eG~~|**Typ.**<br>~~eG~~|**Max**<br>~~eG~~|**Unit**<br>~~eG~~|
|---|---|---|---|---|---|---|
|tDONE_HIGH2<br>~~a~~|PROGRAMN HIGH to DONE HIGH<br>~~COO~~|—<br>~~COO~~|—<br>~~COO~~|—<br>~~COO~~|2<br>~~COO~~|s<br>~~COO~~|
|tIODISS<br>~~a ~~|PROGRAMN LOW to I/O Disabled<br> ~~F~~|—<br>~~F~~|—<br>~~F~~|—<br>~~F~~|125<br>~~F~~|ns<br>~~F~~|
|**Master SPI**<br>~~PR~~|||||||
|fMCLK1<br>~~Ge~~|Max selected MCLK output frequency<br>~~Ge~~|—<br>~~Ge~~|—<br>~~Ge~~|112.5<br>~~Ge~~|124<br>~~Ge~~|MHz<br>~~Ge~~|
|fMCLK_DC<br>~~pf~~|MCLK output clock duty cycle<br>~~pf~~|—<br>~~pf~~|40<br>~~pf~~|—<br>~~pf~~|60<br>~~pf~~|%<br>~~pf~~|
|tMCLKH<br>~~pf~~<br>~~eG~~|MCLK output clock pulse width HIGH<br>~~pf~~<br>~~eG~~|—<br>~~pf~~<br>~~eG~~|3.5<br>~~pf~~<br>~~eG~~|—<br>~~pf~~<br>~~eG~~|—<br>~~pf~~<br>~~eG~~|ns<br>~~pf~~<br>~~eG~~|
|tMCLKL<br>~~eG~~|MCLK output clock pulse width LOW<br>~~eG~~|—<br>~~eG~~|3.5<br>~~eG~~|—<br>~~eG~~|—<br>~~eG~~|ns<br>~~eG~~|
|tSU_MSI<br>~~pf~~|MSI to MCLK setup time<br>~~pf~~|—<br>~~pf~~|3<br>~~pf~~|—<br>~~pf~~|—<br>~~pf~~|ns<br>~~pf~~|
|tHD_MSI<br>~~pf~~<br>~~eG~~<br>~~es~~|MSI to MCLK hold time<br>~~pf~~<br>~~eG~~<br>~~Ge~~|—<br>~~pf~~<br>~~eG~~<br>~~Ge~~|0.5<br>~~pf~~<br>~~eG~~<br>~~Ge~~|—<br>~~pf~~<br>~~eG~~<br>~~Ge~~|—<br>~~pf~~<br>~~eG~~<br>~~Ge~~|ns<br>~~pf~~<br>~~eG~~<br>~~Ge~~|
|tCO_MSO2<br>~~es~~|MCLK to MSO delay<br>~~Ge~~|—<br>~~Ge~~|—<br>~~Ge~~|—<br>~~Ge~~|12<br>~~Ge~~|ns<br>~~Ge~~|
|**Slave SPI**<br>~~esGe~~<br>~~pe~~|||||||
|fCCLK<br>~~pe~~<br>~~eG~~|CCLK input clock frequency<br>~~pe~~<br>~~eG~~|—<br>~~pe~~<br>~~eG~~|—<br>~~pe~~<br>~~eG~~|—<br>~~pe~~<br>~~eG~~|120<br>~~pe~~<br>~~eG~~|MHz<br>~~pe~~<br>~~eG~~|
|tCCLKH<br>~~Ge~~|CCLK input clock pulse width HIGH<br>~~Ge~~|—<br>~~Ge~~|3.5<br>~~Ge~~|—<br>~~Ge~~|—<br>~~Ge~~|ns<br>~~Ge~~|
|tCCLKL<br>~~Ge~~|CCLK input clock pulse width LOW<br>~~Ge~~|—<br>~~Ge~~|3.5<br>~~Ge~~|—<br>~~Ge~~|—<br>~~Ge~~|ns<br>~~Ge~~|
|tVMC_SLAVE<br>~~a~~|Time from rising edge of INITN to Slave CCLK<br>driven<br>~~ee~~|—<br>~~ee~~|50<br>~~ee~~|—<br>~~ee~~|—<br>~~ee~~|ns<br>~~ee~~|
|tVMC_MASTER<br>~~eG~~<br>~~es~~|CCLK input clock duty cycle<br>~~eG~~<br>~~eG~~|—<br>~~eG~~<br>~~eG~~|40<br>~~eG~~<br>~~eG~~|—<br>~~eG~~<br>~~eG~~|60<br>~~eG~~<br>~~eG~~|%<br>~~eG~~<br>~~eG~~|
|tSU_SSI<br>~~es~~|SSI to CCLK setup time<br>~~eG~~|—<br>~~eG~~|3.2<br>~~eG~~|—<br>~~eG~~|—<br>~~eG~~|ns<br>~~eG~~|
|tHD_SSI<br>~~es~~<br>~~eG~~|SSI to CCLK hold time<br>~~eG~~<br>~~eG~~|—<br>~~eG~~<br>~~eG~~|1.9<br>~~eG~~<br>~~eG~~|—<br>~~eG~~<br>~~eG~~|—<br>~~eG~~<br>~~eG~~|ns<br>~~eG~~<br>~~eG~~|
|tCO_SSO<br>~~pf~~|CCLK falling edge to valid SSO output<br>~~pf~~|—<br>~~pf~~|—<br>~~pf~~|—<br>~~pf~~|30<br>~~pf~~|ns<br>~~pf~~|
|tEN_SSO<br>~~pf~~<br>~~eG~~|CCLK falling edge to SSO output enabled<br>~~pf~~<br>~~eG~~|—<br>~~pf~~<br>~~eG~~|—<br>~~pf~~<br>~~eG~~|—<br>~~pf~~<br>~~eG~~|30<br>~~pf~~<br>~~eG~~|ns<br>~~pf~~<br>~~eG~~|
|tDIS_SSO<br>~~eG~~<br>~~es~~|CCLK falling edge to SSO output disabled<br>~~eG~~<br>~~eG~~|—<br>~~eG~~<br>~~eG~~|—<br>~~eG~~<br>~~eG~~|—<br>~~eG~~<br>~~eG~~|30<br>~~eG~~<br>~~eG~~|ns<br>~~eG~~<br>~~eG~~|
|tHIGH_SCSN<br>~~es~~|SCSN HIGH time<br>~~eG~~|—<br>~~eG~~|74<br>~~eG~~|—<br>~~eG~~|—<br>~~eG~~|ns<br>~~eG~~|
|tSU_SCSN<br>~~es~~<br>~~pf~~<br>~~es~~|SCSN to CCLK setup time<br>~~eG~~<br>~~pf~~<br>~~eG~~|—<br>~~eG~~<br>~~pf~~<br>~~eG~~|3.5<br>~~eG~~<br>~~pf~~<br>~~eG~~|—<br>~~eG~~<br>~~pf~~<br>~~eG~~|—<br>~~eG~~<br>~~pf~~<br>~~eG~~|ns<br>~~eG~~<br>~~pf~~<br>~~eG~~|
|tHD_SCSN<br>~~pf~~<br>~~es~~|SCSN to CCLK hold time<br>~~pf~~<br>~~eG~~|—<br>~~pf~~<br>~~eG~~|1.6<br>~~pf~~<br>~~eG~~|—<br>~~pf~~<br>~~eG~~|—<br>~~pf~~<br>~~eG~~|ns<br>~~pf~~<br>~~eG~~|
|**I2C/I3C**<br>~~eseG~~<br>~~Pn~~|||||||
|fSCL_I2C<br>~~pf~~|SCL input clock frequency for I2C<br>~~pf~~|—<br>~~pf~~|—<br>~~pf~~|—<br>~~pf~~|1<br>~~pf~~|MHz<br>~~pf~~|
|fSCL_I3C<br>~~pf~~<br>~~GO~~|SCL input clock frequency for I3C<br>~~pf~~<br>~~GO~~|—<br>~~pf~~<br>~~GO~~|—<br>~~pf~~<br>~~GO~~|—<br>~~pf~~<br>~~GO~~|12<br>~~pf~~<br>~~GO~~|MHz<br>~~pf~~<br>~~GO~~|
|tSCLH_I2C<br>~~eG~~|SCL input clock pulse width HIGH for I2C<br>~~eG~~|—<br>~~eG~~|400<br>~~eG~~|—<br>~~eG~~|—<br>~~eG~~|ns<br>~~eG~~|
|tSCLL_I2C<br>~~pO~~|SCL input clock pulse width LOW for I2C<br>~~pO~~|—<br>~~pO~~|400<br>~~pO~~|—<br>~~pO~~|—<br>~~pO~~|ns<br>~~pO~~|
|tSU_SDA_I2C<br>~~pO~~<br>~~eC~~|SDA to SCL setup time for I2C<br>~~pO~~<br>~~eC~~|—<br>~~pO~~<br>~~eC~~|250<br>~~pO~~<br>~~eC~~|—<br>~~pO~~<br>~~eC~~|—<br>~~pO~~<br>~~eC~~|ns<br>~~pO~~<br>~~eC~~|
|tHD_SDA_I2C<br>~~pf~~|SDA to SCL hold time for I2C<br>~~pf~~|—<br>~~pf~~|50<br>~~pf~~|—<br>~~pf~~|—<br>~~pf~~|ns<br>~~pf~~|
|tSU_SDA_I3C<br>~~pf~~<br>~~eG~~|SDA to SCL setup time for I3C<br>~~pf~~<br>~~eG~~|—<br>~~pf~~<br>~~eG~~|30<br>~~pf~~<br>~~eG~~|—<br>~~pf~~<br>~~eG~~|—<br>~~pf~~<br>~~eG~~|ns<br>~~pf~~<br>~~eG~~|
|tHD_SDA_I3C<br>~~eG~~<br>~~eC~~|SDA to SCL hold time for I3C<br>~~eG~~<br>~~eC~~|—<br>~~eG~~<br>~~eC~~|30<br>~~eG~~<br>~~eC~~|—<br>~~eG~~<br>~~eC~~|—<br>~~eG~~<br>~~eC~~|ns<br>~~eG~~<br>~~eC~~|
|tCO_SDA<br>~~pf~~|SCL falling edge to valid SDA output<br>~~pf~~|—<br>~~pf~~|—<br>~~pf~~|—<br>~~pf~~|200<br>~~pf~~|ns<br>~~pf~~|
|tEN_SDA<br>~~pf~~<br>~~eG~~|SCL falling edge to SDA output enabled<br>~~pf~~<br>~~eG~~|—<br>~~pf~~<br>~~eG~~<br>~~CD~~|—<br>~~pf~~<br>~~eG~~<br>~~CD~~|—<br>~~pf~~<br>~~eG~~<br>~~CD~~|200<br>~~pf~~<br>~~eG~~|ns<br>~~pf~~<br>~~eG~~|
|tDIS_SDA<br>~~a~~|SCL falling edge to SDA output disabled<br>~~a~~|—<br>~~a~~<br>~~CD~~|—<br>~~a~~<br>~~CD~~|—<br>~~a~~<br>~~CD~~|200<br>~~a~~|ns<br>~~a~~|
|**Wake-Up Timing**<br>~~a~~<br>~~CD~~<br>~~pn~~|||||||
|tWAKEUP_DONE_HIGH2<br>~~pn~~|Last configuration clock cycle to DONE going<br>HIGH<br>~~pn~~|—<br>~~pn~~|—<br>~~pn~~|—<br>~~pn~~|60<br>~~pn~~|µs<br>~~pn~~|
|tFIO_EN2|User I/O enabled in Early I/O Mode|LIFCL-40|—||31184|cycles|
|||LIFCL-17|—|—|20688|cycles|
|tIOEN2<br>~~eG~~|Config clock to user I/O enabled<br>~~eG~~|—<br>~~eG~~|150<br>~~eG~~|—<br>~~eG~~|—<br>~~eG~~|ns<br>~~eG~~|
|tMCLKZ2, 3<br>~~eG~~<br>~~eG~~|Master MCLK to Hi-Z<br>~~eG~~<br>~~eG~~|—<br>~~eG~~<br>~~eG~~|—<br>~~eG~~<br>~~eG~~|—<br>~~eG~~<br>~~eG~~|2.5<br>~~eG~~<br>~~eG~~|µs<br>~~eG~~<br>~~eG~~|
© 2021-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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## **Notes** :
1. fMCLK has a dependency on HFOSC and is 1/3 of fCLKHF.
2. Based on 30k uncompressed/unauthenticated/default MCLK timing (3.5 MHz)/x1. Other permutations result in different values. 3. Measured using LVCMOS18, default MCLK frequency, slow slew rate.
**==> picture [414 x 465] intentionally omitted <==**
**----- Start of picture text -----**<br>
REFRESH Command tICFG<br>VCC/VCCAUX/<br>VCCIO0/VCCIO1 tICFG_POR<br>INITN<br>DONE<br>PROGRAMN fMCLK_DEF<br>tVMC<br>MCLK<br>h<br>MSI<br>Figure 4.14. Master SPI POR/REFRESH Timing<br>VCC/VCCAUX/<br>VCCIO0/VCCIO1 tICFG_POR<br>REFRESH Command tICFG<br>INITN<br>DONE<br>tMSPI_INH Slave Activation tACT_CRESETB_N<br>PROGRAMN<br>tACT_CCLK fCCLK tCONFIG_CCLK<br>CCLK<br>SSI<br>tACT_SCL fSCL tACT_CRESETB_N<br>tCONFIG_SCL<br>SCL<br>SDA<br>**----- End of picture text -----**<br>
**Figure 4.15. Slave SPI/I[2] C/I3C POR/REFRESH Timing**
© 2021-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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**CrossLink-NX Family Data Sheet**
**Figure 4.16. Master SPI PROGRAMN Timing**
**Figure 4.17. Slave SPI/I[2] C/I3C PROGRAMN Timing**
© 2021-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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**==> picture [223 x 108] intentionally omitted <==**
**----- Start of picture text -----**<br>
fMCLK<br>tMCLKH —_»<br>< —____—_ tMCLKL<br>MCLK tSU_MISO —_ tHD_MISO<br>MSI<br>tCO_MOSI<br>—_> > < —_—<br>MSO<br>**----- End of picture text -----**<br>
**Figure 4.18. Master SPI Configuration Timing**
**==> picture [287 x 191] intentionally omitted <==**
**----- Start of picture text -----**<br>
fCCLK<br>—_ tCCLKH<br>CCLK<br>tCCLKL<br>tSU_MOSI tHD_MOSI<br>SSI<br>tSU_SCSN tHD_SCSN<br>SCSN<br>tHIGH_SCSN<br>tCO_MISO<br>SSO<br>> Se<br>tEN_MISO tDIS_MISO<br>SSO<br>**----- End of picture text -----**<br>
**Figure 4.19. Slave SPI Configuration Timing**
**==> picture [306 x 150] intentionally omitted <==**
**----- Start of picture text -----**<br>
fSCL<br>tSCLH<br>SCL<br>tSCLL<br>tSU_SDA tHD_SDA<br>SDA (input)<br>tCO_SDA<br>SDA (output)<br>tDIS_SDA<br>tEN_SDA<br>SDA (output)<br>**----- End of picture text -----**<br>
**Figure 4.20. I[2] C /I3C Configuration Timing**
© 2021-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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**CrossLink-NX Family Data Sheet**
**==> picture [467 x 681] intentionally omitted <==**
**----- Start of picture text -----**<br>
CRESET_B<br>INITN<br>tWAKEUP_DONE_HIGH Device Wake-Up<br>DONE<br>CONFIG tMWC<br>Starts fMCLK_def fMCLK tMCLKZ<br>MCLK<br>tFIO_EN<br>USER I/O tIOEN<br>(FAST I/O)<br>tIOEN<br>USER I/O<br>Figure 4.21. Master SPI Wake-Up Timing<br>CRESET_B<br>INITN<br>tWAKEUP_DONE_HIGH Device Wake-Up<br>DONE<br>CONFIG<br>Starts<br>CCLK/SCL<br>tFIO_EN<br>USER I/O tIOEN<br>(FAST I/Os)<br>tIOEN<br>=<br>USER I/O<br>ee<br>Figure 4.22. Slave SPI/I [2] C/I3C Wake-Up Timing<br>© 2021-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.<br>All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.<br>FPGA-DS-02049-1.8<br>**----- End of picture text -----**<br>
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**CrossLink-NX Family Data Sheet**
## **4.28. JTAG Port Timing Specifications**
**Table 4.49. JTAG Port Timing Specifications**
|**Symbol**|**Parameter**|**Min**|**Typ. **|**Max**|**Units**|
|---|---|---|---|---|---|
|fMAX|TCK clock frequency|—|—|25|MHz|
|tBTCPH|TCK clockpulse width high|20|—|—|ns|
|tBTCPL|TCK clockpulse width low|20|—|—|ns|
|tBTS|TCK TAP setuptime|5|—|—|ns|
|tBTH|TCK TAP hold time|5|—|—|ns|
|tBTRF|TAP controller TDO rise/fall time1|100|—|—|mV/ns|
|tBTCO|TAP controller fallingedge of clock to valid output|—|—|14|ns|
|tBTCODIS|TAP controller fallingedge of clock to valid disable|—|—|14|ns|
|tBTCOEN|TAP controller fallingedge of clock to valid enable|—|—|14|ns|
|tBTCRS|BSCAN test capture register setuptime|8|—|—|ns|
|tBTCRH|BSCAN test capture register hold time|25|—|—|ns|
|tBUTCO|BSCAN test update register, fallingedge of clock to valid output|—|—|25|ns|
|tBTUODIS|BSCAN test update register, fallingedge of clock to valid disable|—|—|25|ns|
|tBTUPOEN|BSCAN test update register, fallingedge of clock to valid enable|—|—|25|ns|
**Note:**
1. Based on default I/O setting of slow slew rate.
**==> picture [426 x 314] intentionally omitted <==**
**----- Start of picture text -----**<br>
TMS<br>TDI<br>tBTS tBTH<br>tBTCPH tBTCPL tBTCP<br>TCK<br>tBTCOEN tBTCO tBTCODIS<br>TDO V dilaD aat V dilaD aat<br>tBTCRH<br>tBTCRS<br>Data to be<br>Captured Data Captured<br>from I/O<br>tBTUPOEN tBUTCO tBTUODIS<br>Data to be<br>driven out V dilaD aat V dilaD aat<br>to I/O<br>**----- End of picture text -----**<br>
**Figure 4.23. JTAG Port Timing Waveforms**
© 2021-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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**CrossLink-NX Family Data Sheet**
## **4.29. Switching Test Conditions**
Figure 3.24 shows the output test load that is used for AC testing. The specific values for resistance, capacitance, voltage, and other test conditions are listed in Table 4.50.
**==> picture [221 x 150] intentionally omitted <==**
**----- Start of picture text -----**<br>
V T<br>R1<br>DUT Test Point<br>R2 CL*<br>: L<br>**----- End of picture text -----**<br>
*CL Includes Test Fixture and Probe Capacitance
**Figure 4.24. Output Test Load, LVTTL and LVCMOS Standards**
**Table 4.50. Test Fixture Required Components, Non-Terminated Interfaces**
|**Test Condition**|**R1**|**R2**|**CL**|**Timing Ref.**|**VT**|
|---|---|---|---|---|---|
|LVTTL and other LVCMOS settings (L ≥ H, H ≥ L)|||0 pF|LVCMOS 3.3 = 1.5 V|—|
|||||LVCMOS 2.5 = VCCIO/2|—|
|||||LVCMOS 1.8 = VCCIO/2|—|
|||||LVCMOS 1.5 = VCCIO/2|—|
|||||LVCMOS 1.2 = VCCIO/2|—|
|LVCMOS 2.5 I/O(Z ≥ H)||1 MΩ|0pF|VCCIO/2|—|
|LVCMOS 2.5 I/O(Z ≥ L)|1 MΩ||0pF|VCCIO/2|VCCIO|
|LVCMOS 2.5 I/O(H ≥ Z)||100|0pF|VOH– 0.10|—|
|LVCMOS 2.5 I/O(L ≥ Z)|100||0pF|VOL+ 0.10|VCCIO|
**Note** : Output test conditions for all other interfaces are determined by the respective standards.
© 2021-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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**CrossLink-NX Family Data Sheet**
## **5. Pinout Information**
## **5.1. Signal Descriptions**
|**Signal Name**<br>~~ee a~~|**Bank**<br>~~a~~|**Type **|**Description**|
|---|---|---|---|
|**Power and GND**<br>~~ee a~~<br>~~a~~||||
|Vss<br>~~a~~|—<br>~~a~~|GND<br>~~a~~|Ground for internal FPGA logic and I/O<br>~~a~~|
|VSSA_D-PHY<br>~~a~~|—<br>~~a~~|GND<br>~~a~~|AnalogGround for D-PHY blocks<br>~~a~~|
|VSSSD<br>~~a~~|—<br>~~a~~|GND<br>~~a~~|Ground for SerDes blocks<br>~~a~~|
|VCC<br>~~a~~<br>~~ee~~|—<br>~~a~~<br>~~ee~~|Power<br>~~a~~<br>~~ee~~|Power supply pins for core logic. VCCis connected to 1.0 V (nom.)<br>supplyvoltage. Power On Reset(POR)monitors this supplyvoltage.<br>~~a~~<br>~~eee~~|
|VCCAUXA<br>~~ee~~|—<br>~~ee~~|Power<br>~~ee~~|Auxiliary power supply pin for internal analog circuitry. This supply is<br>connected to 1.8 V (nom.) supply voltage. POR monitors this supply<br>voltage.<br>~~eee~~|
|VCCAUX<br>~~ee~~|—<br>~~ee~~|Power<br>~~ee ~~|Auxiliary power supply pin for I/O Bank 0, Bank 1, Bank 2, Bank 6, and<br>Bank 7. This supply is connected to 1.8 V (nom.) supply voltage, and is<br>used forgeneratingstable drive current for the I/O.<br> ~~eee~~|
|VCCAUXHx|—|Power|Auxiliary power supply pin for I/O Bank 3, Bank 4, and Bank 5. This<br>supply is connected to 1.8 V (nom.) supply voltage, and is used for<br>generatingstable current for the differential input comparators.|
|VCCIOx<br>~~ee~~|0-7<br>~~ee~~|Power<br>~~ee~~|Power supply pins for I/O bank x.<br>For x = 0, 1, 2, 6, and 7, VCCIO can be connected to (nom.) 1.2 V, 1.5 V,<br>1.8 V, 2.5 V, or 3.3 V.<br>For x = 3, 4, and 5, VCCIO can be connected to (nom.) 1.0 V, 1.2 V,<br>1.35 V, 1.5 V, or 1.8 V.<br>There are dedicated and shared configuration pins in banks 0 and 1.<br>POR monitors these banks supplyvoltages.<br>~~ee~~|
|VCC_D-PHYx<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~|Power<br>~~ee~~|1.0 V (nom.) digital power supply for the hardened D-PHY blocks.<br>X = 0, 1<br>~~ee~~|
|VCCA_D-PHYx<br>~~ee ~~<br>~~ee~~<br>~~ee~~|—<br> ~~ee ~~<br>~~ee~~<br>~~ee~~|Power<br> ~~ee~~|1.8 V (nom.) analog power supply for the hardened D-PHY blocks.<br>X = 0, 1<br>~~ee~~|
|VCCPLL_D-PHYx<br>~~ee ~~<br>~~ee~~|—<br> ~~ee~~<br>~~ee~~|Power|1.0 V (nom.) power supply for the hardened D-PHY blocks.<br>X = 0, 1|
|VCCADC182, 3<br>~~ee ~~<br>~~a~~|—<br> ~~ee~~|Power|1.8 V(nom.) power supplyfor the ADC block.|
|VCCSD0<br>~~a~~|—|Power|1.0 V(nom.) power supplyfor the SerDes block.|
|VCCPLLSD0<br>~~a~~|—|Power|1.8 V(nom.) power supplyfor the PLL in the SerDes block.|
|VCCAUXSD<br>~~a~~|—|Power|1.8 V(nom.)auxiliary power supplyfor the SerDes block.|
|**Dedicated Pins**<br>~~a~~<br>~~a]~~||||
|**Dedicated Configuration I/O Pin**<br>~~a]~~<br>~~ee~~||||
|JTAG_EN<br>~~ee~~|1<br>~~ee~~|Input<br>~~ee~~|LVCMOS input pin. This input selects the JTAG shared GPIO to be used<br>for JTAG<br>0 = GPIO<br>1 = JTAG<br>~~ee~~|
|**Dedicated ADC I/O Pins2**<br>~~a]~~<br>~~a~~<br>~~eeee~~||||
|ADC_REF[0, 1]<br>~~a]~~<br>~~a~~|—<br>~~a]~~<br>~~ee~~|Input<br>~~a]~~<br>~~ee~~|ADC reference voltage, for each of the two ADC converters. If not used,<br>tie toground.<br>~~a]~~|
|ADC_DP/N[0, 1]<br>~~a~~<br>~~a~~|—<br>~~ee ~~<br>~~ee~~|Input<br> ~~ee~~<br>~~ee~~|Dedicated ADC input pairs, for each of the two ADC converters. If not<br>used, tie to ground.|
© 2021-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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|**Signal Name**<br>~~ee~~|**Bank**|**Type **|**Description**|
|---|---|---|---|
|**Dedicated High Speed I/O Pins**<br>~~ee~~<br>~~eeee~~||||
|SD0_RXDP/N<br>~~ee~~<br>~~a~~|—<br>~~ee~~<br>~~ee~~|Input<br>~~ee~~<br>~~ee~~|High Speed Data Differential Input Pairs|
|SD0_TXDP/N<br>~~ee ~~<br>~~a~~|—<br> ~~ee~~<br>~~ee~~|Output<br>~~ee~~<br>~~ee~~|High Speed Data Differential Output Pairs|
|SD0_REFCLKP/N<br>~~a~~|—<br>~~ee ~~|Input<br> ~~ee~~|High Speed Reference Clock Differential Input Pairs|
|SD0_REXT<br>~~a~~|—<br>~~ee~~|Input|High Speed External Reference Resistor Input. Resistor connects<br>between to this pin and SD0_REFRET pin. This is used to adjust the on-<br>chip differential termination impedance, based on the external<br>resistance value:<br>REXT= 909 Ω, RDIFF= 80 Ω<br>REXT= 976 Ω, RDIFF= 85 Ω<br>REXT= 1.02 kΩ, RDIFF= 90 Ω<br>REXT= 1.15 kΩ, RDIFF= 100 Ω|
|SD0_REFRET<br>~~a~~|—<br>~~ee~~|Input|High Speed Reference Return Input. These pins should be AC coupled<br>to the VCCPLLSD0 supply|
|**Dedicated D-PHY I/O Pins**<br>~~a~~<br>~~ee~~<br>~~a~~<br>~~ee~~||||
|D-PHY[0-1]_DP/N[0-3]<br>~~a~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~|Input,<br>Output<br>~~ee~~<br>~~es~~|Hardened D-PHY Data Input/Output Pairs, for each of the 4 High Speed<br>lanes in the 2 Hardened D-PHY Blocks|
|D-PHY[0-1]_CKP/N<br>~~a~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~|Input,<br>Output<br>~~ee~~<br>~~es~~|Hardened D-PHY Clock Input/Output Pairs, for each of the 2 Hardened<br>D-PHY Blocks|
|**Misc Pins**<br>~~ee ee es~~<br>~~ee~~||||
|NC<br>~~ee~~|—<br>|—<br>|No connect.<br>|
|RESERVED<br>~~eea~~|—<br>~~a~~|—<br>~~a~~|This pin is reserved and should not be connected to anything on the<br>~~a~~|
|**General Purpose I/O Pins**<br>~~a~~||||
|P[T/B/L/R] [Number]_[A/B]<br>~~a~~|T = 0<br>R = 1, 2<br>B = 3, 4, 5<br>L = 6. 7<br>~~a~~|Input,<br>Output,<br>Bi-Dir<br>~~a~~|Programmable User I/O:<br>[T/B/L/R] indicates the package pin/ball is in T (Top), B (Bottom), L<br>(Left), or R (Right) edge of the device.<br>[Number] identifies the PIO [A/B] pair.<br>[A/B] shows the package pin/ball is A or B signal in the pair. PIO A and<br>PIO B are grouped as a pair.<br>Each A/B pair in the bottom banks supports true differential input and<br>output buffers. When configured as differential input, differential<br>termination of 100 Ω can be selected.<br>Each A/B pair in the top, left and right banks does not support true<br>differential input or output buffer. It supports all single-ended inputs<br>and outputs, and can be used for emulated differential output buffer.<br>Some of these user-programmable I/O are used during configuration,<br>depending on the configuration mode. You need to make appropriate<br>connection on the board to isolate the two different functions<br>before/after configuration.<br>Some of these user-programmable I/O are shared with special function<br>pins. These pins, when not used as special purpose pins, can be<br>programmed as I/O for user logic.<br>During configuration the user-programmable I/O are tri-stated with an<br>internal weak pull-down resistor enabled. If any pin is not used (or not<br>bonded to a package pin), it is tri-stated and default to have weak pull-<br>down enabled after configuration.<br>~~a~~|
© 2021-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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**CrossLink-NX Family Data Sheet**
|**Signal Name**|**Bank**|**Type **|**Description**|
|---|---|---|---|
|**Shared Configuration Pins**<br>**1.**<br>**These pins can be used for configuration during configuration mode. When configuration is completed, these pins can be**<br>**used as GPIO, or shared function in GPIO. When these pins are used in dual function, users need to isolate the signal**<br>**paths for the dual functions on the board.**<br>**2.**<br>**The pins used are defined by the configuration modes detected. Slave SPI or I2C/I3C modes are detected during slave**<br>**activation. Pins that are not used in the configuration mode selected are tri-stated during configuration, and can connect**<br>**directly as GPIO in user’s function.**||||
|PRxxx /SDA/USER_SDA|1|Input,<br>Output,<br>Bi-Dir|Configuration:<br>I2C/I3C Mode: SDA signal<br>User Mode:<br>PRxxx: GPIO<br>User_SDA: SDA signal for I2C/I3C interface|
|PRxxx /SCL/USER_SCL|1|Input,<br>Output,<br>Bi-Dir|Configuration:<br>I2C/I3C Mode: SCL signal<br>User Mode:<br>PRxxx: GPIO<br>User_SDA: SCL signal for I2C/I3C interface|
|PRxxx/TDO/SSO|1|Input,<br>Output,<br>Bi-Dir|Configuration:<br>Slave SPI Mode: Slave Serial Output<br>User Mode:<br>PRxxx: GPIO<br>TDO: When JTAG_EN = 1, used as TDO signal for JTAG|
|PRxxx/TDI/SSI|1|Input,<br>Output,<br>Bi-Dir|Configuration:<br>Slave SPI Mode: Slave Serial Input<br>User Mode:<br>PRxxx: GPIO<br>TDI: When JTAG_EN = 1, used as TDI signal for JTAG|
|PRxxx/TMS/SCSN|1|Input,<br>Output,<br>Bi-Dir|Configuration:<br>Slave SPI Mode: Slave Chip Select<br>User Mode:<br>PRxxx: GPIO<br>TMS: When JTAG_EN = 1, used as TMS signal for JTAG|
|PRxxx/TCK/SCLK|1|Input,<br>Output,<br>Bi-Dir|Configuration:<br>Slave SPI Mode: Slave Clock Input<br>User Mode:<br>PRxxx: GPIO<br>TCK: When JTAG_EN = 1, used as TCK signal for JTAG|
|PTxxx/MCSNO|0|Input,<br>Output,<br>Bi-Dir|Configuration:<br>Flow-through Daisy Chain Mode: Chip Select Output<br>User Mode:<br>PTxxx: GPIO|
|PTxxx/MD3|0|Input,<br>Output,<br>Bi-Dir|Configuration:<br>Master Quad SPI Mode: I/O3<br>User Mode:<br>PTxxx: GPIO|
|PTxxx/MD2|0|Input,<br>Output,<br>Bi-Dir|Configuration:<br>Master Quad SPI Mode: I/O2<br>User Mode:<br>PTxxx: GPIO|
© 2021-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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**CrossLink-NX Family Data Sheet**
|**Signal Name**|**Bank**|**Type **|**Description**|
|---|---|---|---|
|PTxxx/MSI/MD1|0|Input,<br>Output,<br>Bi-Dir|Configuration:<br>Master SPI Mode: Master Serial Input<br>Master Quad SPI Mode: I/O1<br>User Mode:<br>PTxxx: GPIO|
|PTxxx/MSO/MD0|0|Input,<br>Output,<br>Bi-Dir|Configuration:<br>Master SPI Mode: Master Serial Output<br>Master Quad SPI Mode: I/O0<br>User Mode:<br>PTxxx: GPIO|
|PTxxx/MCSN/PCLKT0_1|0|Input,<br>Output,<br>Bi-Dir|Configuration:<br>Master SPI Mode: Master Chip Select Output<br>User Mode:<br>PTxxx: GPIO<br>PCLKT0_0: Top PCLK Input|
|PTxxx/MCLK/PCLKT0_0|0|Input,<br>Output,<br>Bi-Dir|Configuration:<br>Master SPI Mode: Master Clock Output<br>User Mode:<br>PTxxx: GPIO<br>PCLKT0_1: Top PCLK Input|
|PTxxx/PROGRAMN|0|Input,<br>Output,<br>Bi-Dir|Configuration:<br>PROGRAMN: Initiate configuration sequence when asserted LOW.<br>User Mode:<br>PTxxx: GPIO|
|PTxxx/INITN|0|Input,<br>Output,<br>Bi-Dir|Configuration:<br>INITN: Open Drain I/O pin. This signal is driven to LOW when<br>configuration sequence is started, to indicate the device is in<br>initialization state. This signal is released after initialization is<br>completed, and the configuration download can start. You can keep<br>drive this signal LOW to delay configuration download to start.<br>User Mode:<br>PTxxx: GPIO|
|PTxxx/DONE|0|Input,<br>Output,<br>Bi-Dir|Configuration:<br>DONE: Open Drain I/O pin. This signal is driven to LOW during<br>configuration time. It is released to indicate the device has completed<br>configuration. You can keep drive this signal LOW to delay the device to<br>wake up from configuration.<br>User Mode:<br>PTxxx: GPIO|
|**Shared User GPIO Pins**<br>**1.**<br>**Shared User GPIO pins are pins that can be used as GPIO, or functional pins that connect directly to specific functional**<br>**blocks, when device enters into User Mode.**<br>**2.**<br>**Declaring on assigning the pin as GPIO or specific functional pin is done by configuration bitstream, except JTAG pins.**<br>**3.**<br>**JTAG pins are controlled by JTAG_EN signal. When JTAG_EN = 1, the pins are used for JTAG interface. When JTAG = 0, the**<br>**pins are used as GPIO or specific functional pin defined by configuration bitstream.**<br>**4.**<br>**Refer to package pin file.**||||
|**Shared JTAG Pins**||||
|PRxxx/TDO/ yyyy|1|Input,<br>Output,<br>Bi-Dir|User Mode:<br>PRxxx: GPIO<br>TDO: When JTAG_EN = 1, used as TDO signal for JTAG<br>yyyy: Other possible selectable specific functional|
## **Shared User GPIO Pins**
**1. Shared User GPIO pins are pins that can be used as GPIO, or functional pins that connect directly to specific functional blocks, when device enters into User Mode.**
**2. Declaring on assigning the pin as GPIO or specific functional pin is done by configuration bitstream, except JTAG pins.**
**3. JTAG pins are controlled by JTAG_EN signal. When JTAG_EN = 1, the pins are used for JTAG interface. When JTAG = 0, the pins are used as GPIO or specific functional pin defined by configuration bitstream.**
**4. Refer to package pin file.**
## **Shared JTAG Pins**
PRxxx/TDO/ yyyy 1 Input, User Mode: Output, PRxxx: GPIO Bi-Dir TDO: When JTAG_EN = 1, used as TDO signal for JTAG yyyy: Other possible selectable specific functional
© 2021-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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**CrossLink-NX Family Data Sheet**
|**Signal Name**|**Bank**|**Type **|**Description**|
|---|---|---|---|
|PRxxx/TDI/yyyy|1|Input,<br>Output,<br>Bi-Dir|User Mode:<br>PRxxx: GPIO<br>TDI: When JTAG_EN = 1, used as TDI signal for JTAG<br>yyyy: Other possible selectable specific functional|
|PRxxx/TMS/ yyyy|1|Input,<br>Output,<br>Bi-Dir|User Mode:<br>PRxxx: GPIO<br>TMS: When JTAG_EN = 1, used as TMS signal for JTAG<br>yyyy: Other possible selectable specific functional|
|PRxxx/TCK/ yyyy|1|Input,<br>Output,<br>Bi-Dir|User Mode:<br>PRxxx: GPIO<br>TCK: When JTAG_EN = 1, used as TCK signal for JTAG<br>Yyyy: Other possible selectable specific functional|
|**Shared CLOCK Pins**<br>**1.**<br>**Some PCLK pins can also be used as GPLL reference clock input pin. Refer tosysCLOCK PLL Design and User Guide for**<br>**Nexus Platform (FPGA-TN-02095). **||||
|PBxxx/PCLK[T,C][3,4,5]_[0-<br>3]/yyyy|3, 4, 5|Input,<br>Output,<br>Bi-Dir|User Mode:<br>PBxxx: GPIO<br>PCLK: Primary Clock or GPLL Refclk signal<br>[T,C] = True/Complement when using differential signaling<br>[3,4,5] = Bank<br>[0-3] Up to 4 signals in the bank<br>yyyy: Otherpossible selectable specific functional|
|PTxxx/PCLKT0_[0-1]/yyyy|0|Input,<br>Output,<br>Bi-Dir|User Mode:<br>PTxxx: GPIO<br>PCLKT: Primary Clock or GPLL Refclk signal (Only Single Ended)<br>[0-1] Up to 2 signals in the bank<br>yyyy: Other possible selectable specific functional|
|PRxxx/PCLKT[1,2]_[0-2]/yyyy|1, 2|Input,<br>Output,<br>Bi-Dir|User Mode:<br>PRxxx: GPIO<br>PCLKT: Primary Clock or GPLL Refclk signal (Only Single Ended)<br>[0-2] Up to 3 signals in the bank<br>yyyy: Other possible selectable specific functional|
|PLxxx/PCLKT[6,7]_[0-2]/yyyy|6, 7|Input,<br>Output,<br>Bi-Dir|User Mode:<br>PLxxx: GPIO<br>PCLKT: Primary Clock or GPLL Refclk signal (Only Single Ended)<br>[0-2] Up to 3 signals in the bank<br>yyyy: Other possible selectable specific functional|
|PBxxx/LRC_GPLL[T,C]_IN/yyyy|3|Input,<br>Output,<br>Bi-Dir|User Mode:<br>PBxxx: GPIO<br>LRC_GPLL: Lower Right GPLL Refclk signal (PLLCK)<br>[T,C] = True/Complement when using differential signaling<br>yyyy: Other possible selectable specific functional|
|PBxxx/LLC_GPLL[T,C]_IN/yyyy|5|Input,<br>Output,<br>Bi-Dir|User Mode:<br>PBxxx: GPIO<br>LLC_GPLL: Lower Left GPLL Refclk signal (PLLCK)<br>[T,C] = True/Complement when using differential signaling<br>yyyy: Other possible selectable specific functional|
© 2021-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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**CrossLink-NX Family Data Sheet**
|**Signal Name**|**Bank**|**Type **|**Description**|
|---|---|---|---|
|PLxxx/ULC_GPLLT_IN/yyyy|7|Input,<br>Output,<br>Bi-Dir|User Mode:<br>PLxxx: GPIO<br>ULC_GPLL: Upper Left GPLL Refclk signal (Only Single Ended) (PLLCK)<br>yyyy: Other possible selectable specific functional|
|**Shared VREF Pins**||||
|PBxxx/VREF[3,4,5]_[1-2]/yyyy|3, 4, 5|Input,<br>Output,<br>Bi-Dir|User Mode:<br>PBxxx: GPIO<br>VREF: Reference Voltage for DDR memory function<br>[3,4,5] = Bank<br>[1-2] Up to VREFs for each bank<br>yyyy: Other possible selectable specific functional|
|**Shared ADC Pins**||||
|PBxxx/ADC_C[P,N]nn/yyyy|3, 4, 5|Input,<br>Output,<br>Bi-Dir|User Mode:<br>PBxxx: GPIO<br>ADC_C: ADC Channel Inputs<br>[P,N] = Positive or Negative Input<br>nn = ADC Channel number (0 – 15)<br>yyyy: Other possible selectable specific functional|
|**Shared Comparator Pins**||||
|PBxxx/COMP[1-3][P,N]/yyyy|3, 5|Input,<br>Output,<br>Bi-Dir|User Mode:<br>PBxxx: GPIO<br>COMP: Differential Comparator Input<br>[P,N] = Positive or Negative Input<br>[1-3] = Input to Comparators 1-3<br>yyyy: Other possible selectable specific functional|
|**Shared SGMII Pins**||||
|PBxxx/SGMII_RX[P,N][0-<br>1]/yyyy|3, 5|Input,<br>Output,<br>Bi-Dir|User Mode:<br>PBxxx: GPIO<br>SGMII_RX: Differential SGMII RX Inputs<br>[P,N] = Positive or Negative Input<br>[0-1] = Input to SGMII RX0 or RX1<br>yyyy: Other possible selectable specific functional|
**Notes:**
1. Not all signals are available as external pins in all packages. Refer to the Pinout List file for various package details.
2. ADC is available in Commercial/Industrial –8 and –9 speed grades and Automotive –7 speed grade.
3. On devices that do not support the ADC, this pin may be powered or left floating.
© 2021-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02049-1.8
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**CrossLink-NX Family Data Sheet**
## **5.2. Pin Information Summary**
## **5.2.1. CrossLink-NX Family**
|**Pin Information**<br>**Summary**<br>~~re~~|**Pin Information**<br>**Summary**<br>~~re~~|**LIFCL-17**<br>~~Ge~~<br>~~receecescece~~|**LIFCL-17**<br>~~Ge~~<br>~~receecescece~~|**LIFCL-17**<br>~~Ge~~<br>~~receecescece~~|**LIFCL-17**<br>~~Ge~~<br>~~receecescece~~|**LIFCL-40**<br>~~Ge~~<br>~~eeeeeeeeeeee~~|**LIFCL-40**<br>~~Ge~~<br>~~eeeeeeeeeeee~~|**LIFCL-40**<br>~~Ge~~<br>~~eeeeeeeeeeee~~|**LIFCL-40**<br>~~Ge~~<br>~~eeeeeeeeeeee~~|**LIFCL-40**<br>~~Ge~~<br>~~eeeeeeeeeeee~~|
|---|---|---|---|---|---|---|---|---|---|---|
|||**72 QFN**<br>~~re~~|**72WLCSP**<br>~~cee~~|**121csfBGA**<br>~~ces~~|**256caBGA**<br>~~cece~~|**72 QFN**<br>~~eee~~|**121csfBGA**<br>~~eee~~|**256caBGA**<br>~~ee~~|**289csBGA**<br>~~ee~~|**289csBGA**<br>**400caBGA**<br>~~ee~~|
|**User I/O Pins**<br>~~re cee ces cece eee eee ee ee ee~~<br>~~GO~~<br>~~po~~|||||||||||
|General<br>Purpose<br>Inputs/Outputs<br>per Bank<br>~~po~~<br>~~po~~<br>~~po~~|Bank 0<br>~~eG~~<br>~~po~~|11<br>~~eG~~<br>~~po~~|8<br>~~eG~~|12<br>~~eG~~|12<br>~~eG~~|10<br>~~eG~~|12<br>~~eG~~<br>~~GO~~|12<br>~~eG~~<br>~~GO~~|12<br>~~eG~~<br>~~GO~~|12<br>~~eG~~|
||Bank 1<br>~~po~~<br>~~po~~|7<br>~~po~~<br>|7<br>|11<br>|11<br>|7<br>|11<br>~~GO~~<br>|20<br>~~GO~~<br>|19<br>~~GO~~<br>|21<br>|
||Bank 2<br>~~po~~<br>~~po~~|0<br>~~po~~<br>|0<br>|0<br>|0<br>|0<br>|0<br>~~GO~~<br>|13<br>~~GO~~<br>|24<br>~~GO~~<br>|28<br>|
||Bank 3<br>~~popo~~|12<br>~~po~~|12<br>~~po~~|16<br>~~po~~|16<br>~~po~~|12<br>~~po~~|16<br>~~po~~|32<br>~~po~~|32<br>~~po~~|32<br>~~po~~|
||Bank 4<br>~~a~~<br>~~po~~|0<br><br>~~po~~|0<br>|16<br>|16<br>|0<br>|22<br><br>~~GO~~|32<br><br>~~GO~~|32<br><br>~~GO~~|32<br>|
||Bank 5<br>~~aeG~~<br>~~po~~|10<br>~~eG~~<br>~~po~~|12<br>~~eG~~|16<br>~~eG~~|16<br>~~eG~~|10<br>~~eG~~|10<br>~~eG~~<br>~~GO~~|10<br>~~eG~~<br>~~GO~~|10<br>~~eG~~<br>~~GO~~|10<br>~~eG~~|
||Bank 6<br>~~po~~|0<br>~~po~~|0|0|0|0|0<br>~~GO~~|26<br>~~GO~~|28<br>~~GO~~|28|
||Bank 7<br>~~po~~|0<br>~~po~~|0|0|0|0|0<br>~~GO~~|11<br>~~GO~~|16<br>~~GO~~|22|
|Total Single-Ended User<br>I/O<br>~~a~~<br>~~a~~||40<br>~~ee~~<br>|39<br>~~ee~~<br>|71<br>~~ee~~<br>|71<br>~~ee~~<br>|39<br>~~ee~~<br>|71<br>~~ee~~<br>~~GO~~<br>|156<br>~~ee~~<br>~~GO~~<br>|173<br>~~ee~~<br>|185<br>~~ee~~<br>|
|Differential<br>Input / Output<br>Pairs<br>~~eG~~<br>~~a~~<br>~~popo~~<br>~~a~~<br>~~a~~<br>~~a~~<br>~~pO~~<br>~~po~~|Bank 0<br>~~eG~~<br>~~a~~|0<br>~~eG~~<br>|0<br>~~eG~~<br>|0<br>~~eG~~<br>|0<br>~~eG~~<br>|0<br>~~eG~~<br>|0<br>~~eG~~<br>~~GO~~<br>|0<br>~~eG~~<br>~~GO~~<br>|0<br>~~eG~~<br>|0<br>~~eG~~<br>|
||Bank 1<br>~~a~~<br>~~po~~|0<br>~~GO~~<br>|0<br>~~GO~~<br>|0<br>~~GO~~<br>|0<br>~~GO~~<br>|0<br>~~GO~~<br>|0<br>~~GO~~<br>~~GO~~<br>|0<br>~~GO~~<br>~~GO~~<br>|0<br>~~GO~~<br>|0<br>~~GO~~<br>|
||Bank 2<br>~~a~~<br>~~po~~|0<br>~~GO~~<br>|0<br>~~GO~~<br>|0<br>~~GO~~<br>|0<br>~~GO~~<br>|0<br>~~GO~~<br>|0<br>~~GO~~<br>~~GO~~<br>|0<br>~~GO~~<br>~~GO~~<br>|0<br>~~GO~~<br>|0<br>~~GO~~<br>|
||Bank 3<br><br>~~popo~~|12<br>~~GO~~<br>~~po~~|12<br>~~GO~~<br>~~po~~|16<br>~~GO~~<br>~~po~~|16<br>~~GO~~<br>~~po~~|12<br>~~GO~~<br>~~po~~|16<br>~~GO~~<br>~~po~~|32<br>~~GO~~<br>~~po~~|32<br>~~GO~~<br>~~po~~|32<br>~~GO~~<br>~~po~~|
||Bank 4<br>~~a~~<br>~~a~~|0<br>~~eG~~<br>~~ee~~|0<br>~~eG~~<br>~~ee~~|16<br>~~eG~~<br>~~Ge GG~~|16<br>~~eG~~<br>~~GG~~|0<br>~~eG~~<br>~~GG~~|22<br>~~eG~~<br>~~GG~~|32<br>~~eG~~<br>~~GG~~|32<br>~~eG~~<br>~~GG~~|32<br>~~eG~~<br>~~GG~~|
||Bank 5<br>~~a~~|10<br>~~ee~~|12<br>~~ee~~|16<br>~~Ge GG~~|16<br>~~GG~~|10<br>~~GG~~|10<br>~~GG~~|10<br>~~GG~~|10<br>~~GG~~|10<br>~~GG~~|
||Bank 6<br>~~a ~~<br>~~a~~<br>~~pO~~|0<br> ~~ee~~<br>~~GO~~<br>~~pO~~|0<br>~~ee~~<br>~~GO~~|0<br>~~Ge GG~~<br>~~GO~~|0<br>~~GG~~<br>~~GO~~|0<br>~~GG~~<br>~~GO~~|0<br>~~GG~~<br>~~GO~~|0<br>~~GG~~<br>~~GO~~|0<br>~~GG~~<br>~~GO~~|0<br>~~GG~~<br>~~GO~~|
||Bank 7<br>~~a~~<br>~~pO~~<br>~~po~~|0<br>~~GO~~<br>~~pO~~|0<br>~~GO~~|0<br>~~GO~~|0<br>~~GO~~|0<br>~~GO~~|0<br>~~GO~~|0<br>~~GO~~|0<br>~~GO~~|0<br>~~GO~~|
|Total Differential I/O<br>~~pO~~<br>~~po~~||22<br>~~pO~~|24|48|48|22|48|74|74|74|
|**Power Pins**<br>~~po~~<br>~~po~~|||||||||||
|VCC,VCCECLK<br>~~po~~<br>~~po~~||8|3|3|5|8|3|5|6|8|
|VCCAUXA<br>~~po~~<br>~~po~~<br>~~po~~||0|0|0|0|0|0|1|1|1|
|VCCAUX<br>~~po~~<br>~~po~~<br>~~po~~||2|2|1|3|2|1|2|2|3|
|VCCAUXHx<br>~~po~~<br>~~po~~<br>~~po~~||2|2|3|3|2|3|3|3|3|
|VCCAUXSD<br>~~po~~<br>~~po~~||0|0|0|0|0|0|1|1|1|
|VCCIO<br>~~po~~<br>~~po~~<br>~~po~~<br>~~po~~|Bank 0<br>~~poa~~|1|1|1|1|1|1|1|1|1|
||Bank 1<br>~~a~~<br>~~se~~|1<br>~~se~~|1<br>~~GO~~|1<br>~~GO~~|1<br>~~GO~~|1<br>~~GO~~|1<br>~~GO~~|1<br>~~GO~~|2<br>~~GO~~|2<br>~~GO~~|
||Bank 2<br>~~se~~<br>~~a~~<br>~~po~~|0<br>~~se~~<br>~~po~~|0<br>~~GO~~|0<br>~~GO~~|0<br>~~GO~~|0<br>~~GO~~|0<br>~~GO~~|1<br>~~GO~~|2<br>~~GO~~|2<br>~~GO~~|
||Bank 3<br>~~a~~<br>~~po~~|2<br>~~po~~|1|1|1|2|1|1|2|2|
||Bank 4<br>~~po~~<br>~~po~~|0<br>~~po~~<br>~~po~~|0<br>~~po~~|1<br>~~po~~|1<br>~~po~~|0<br>~~po~~|1<br>~~po~~|1<br>~~po~~|2<br>~~po~~|2<br>~~po~~|
||Bank 5<br>~~a~~|1|1|1|1|1|1|1|1|1|
||Bank 6<br>~~a~~<br>~~se~~<br>~~po~~|0<br>~~se~~<br>~~po~~|0<br>~~GO~~|0<br>~~GO~~|0<br>~~GO~~|0<br>~~GO~~|0<br>~~GO~~|1<br>~~GO~~|2<br>~~GO~~|2<br>~~GO~~|
||Bank 7<br>~~se~~<br>~~po~~<br>~~po~~|0<br>~~se~~<br>~~po~~|0<br>~~GO~~|0<br>~~GO~~|0<br>~~GO~~|0<br>~~GO~~|0<br>~~GO~~|1<br>~~GO~~|2<br>~~GO~~|2<br>~~GO~~|
|VCC_D-PHYx<br>~~po~~<br>~~po~~<br>~~po~~||2<br>~~po~~|1|2|2|2|2|2|2|2|
|VCCA_D-PHYx<br>~~po~~<br>~~po~~<br>~~po~~||1|1|2|2|1|2|2|2|2|
|VCCPLL_D-PHYx<br>~~po~~<br>~~po~~<br>~~po~~||1|1|2|2|1|2|2|2|2|
|VCCSD0<br>~~po~~<br>~~po~~<br>~~po~~||0|0|0|0|0|0|1|2|2|
|VCCPLLSD0<br>~~po~~<br>~~po~~<br>~~po~~||0|0|0|0|0|0|1|1|1|
|VCCADC181<br>~~po~~<br>~~po~~<br>~~po~~||1|03|03|1|1|03|1|1|1|
|Total Power Pins<br>~~po~~<br>~~po~~||22|14|18|23|22|18|29|37|40|
© 2021-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02049-1.8
154
**CrossLink-NX Family Data Sheet**
|**Pin Information**<br>**Summary**<br><br>~~yee~~|**Pin Information**<br>**Summary**<br><br>~~yee~~|**LIFCL-17**<br>~~Ge~~<br>~~yee~~|**LIFCL-17**<br>~~Ge~~<br>~~yee~~|**LIFCL-17**<br>~~Ge~~<br>~~yee~~|**LIFCL-17**<br>~~Ge~~<br>~~yee~~|**LIFCL-40**<br>~~Ge~~<br>~~yee~~|**LIFCL-40**<br>~~Ge~~<br>~~yee~~|**LIFCL-40**<br>~~Ge~~<br>~~yee~~|**LIFCL-40**<br>~~Ge~~<br>~~yee~~|**LIFCL-40**<br>~~Ge~~<br>~~yee~~|
|---|---|---|---|---|---|---|---|---|---|---|
|||**72 QFN**<br>~~yee~~|**72WLCSP**<br>~~yee~~|**121csfBGA**<br>~~yee~~|**256caBGA**<br>~~yee~~|**72 QFN**<br>~~yee~~|**121csfBGA**<br>~~yee~~|**256caBGA**|**289csBGA**|**289csBGA**<br>**400caBGA**|
|**GND Pins**<br>~~po~~|||||||||||
|Vss<br>~~po~~<br>~~po~~||0|5|6|20|0|6|22|26|37|
|VSSADC<br>~~po~~<br>~~po~~<br>~~po~~||0|0|0|1|0|0|1|1|1|
|VSSSD<br>~~po~~<br>~~po~~<br>~~po~~||0|0|0|0|0|0|5|8|12|
|VSSA_D-PHY<br>~~po~~<br>~~po~~<br>~~po~~||0|3|5|8|0|5|8|9|7|
|Total GND Pins<br>~~po~~<br>~~po~~||0|8|11|29|0|11|36|44|57|
|**Dedicated Pins**<br>~~po~~|||||||||||
|Dedicated ADC Channels<br>(pairs)1||0|0|0|2|0|0|2|2|2|
|Dedicated ADC Reference<br>Voltage Pins1||0|0|0|2|0|0|2|2|2|
|Dedicated D-PHY Data<br>Channels(pairs)||4|4|8|8|4|8|8|8|8|
|Dedicated D-PHY Clock<br>(pairs)||1|1|2|2|1|2|2|2|2|
|**Dedicated Misc Pins**<br>~~po~~|||||||||||
|JTAGEN<br>~~po~~<br>~~po~~||1|1|1|1|1|1|1|1|1|
|NC<br>~~po~~<br>~~po~~<br>~~po~~||0|0|0|106|0|0|0|0|83|
|RESERVED<br>~~po~~<br>~~po~~<br>~~po~~||0<br>|0<br>|0<br>|0<br>|0<br>|0<br>|0<br>|0<br>|0<br>|
|Total Dedicated Pins<br>~~po~~<br>~~po~~||11<br>|11<br>|21<br>|133<br>|6<br>|11<br>|17<br>|17<br>|17<br>|
|**Shared Pins**<br>~~po~~<br>~~GO~~<br>~~po~~|||||||||||
|Shared<br>Configuration<br>Pins<br><br>~~po~~<br>~~po~~<br>~~po~~<br>~~po~~|Bank 0<br>~~eG~~<br>~~po~~|10<br>~~eG~~<br>~~po~~|8<br>~~eG~~|10<br>~~eG~~|10<br>~~eG~~|10<br>~~eG~~|10<br>~~eG~~<br>~~GO~~|10<br>~~eG~~<br>~~GO~~|10<br>~~eG~~<br>~~GO~~|10<br>~~eG~~|
||Bank 1<br>~~po~~|0<br>~~po~~|0|0|0|6|6<br>~~GO~~|6<br>~~GO~~|6<br>~~GO~~|6|
||Bank 2<br>~~po~~<br>~~po~~|0<br>~~po~~<br>~~po~~|0<br>~~po~~|0<br>~~po~~|0<br>~~po~~|0<br>~~po~~|0<br>~~GO~~<br>~~po~~|0<br>~~GO~~<br>~~po~~|0<br>~~GO~~<br>~~po~~|0<br>~~po~~|
||Bank 3<br>~~a~~<br>~~po~~|0<br>~~po~~|0|0|0|0|0|0|0|0|
||Bank 4<br>~~a~~<br>~~po~~<br>~~po~~|0<br>~~po~~<br>~~po~~|0|0|0|0|0|0|0|0|
||Bank 5<br>~~po~~<br>~~po~~<br>~~po~~|0<br>~~po~~<br>~~po~~<br>~~po~~|0|0|0|0|0|0|0|0|
||Bank 6<br>~~po~~<br>~~po~~|0<br>~~po~~<br>~~po~~|0|0|0|0|0|0|0|0|
||Bank 7<br>~~po~~<br>~~ee~~|0<br>~~po~~<br>~~ee~~|0<br>~~ee~~|0|0<br>~~GG~~|0<br>~~GG~~|0<br>~~GG~~|0<br>~~GG~~|0|0|
|Shared JTAG<br>Pins<br>~~po~~<br>~~po~~<br>~~po~~|Bank 0<br>~~a~~|0|0|0|0|0|0|0|0|0|
||Bank 1<br>~~a~~<br>~~a~~<br>~~po~~|4<br>~~po~~|4|4|4|4|4|4|4|4|
||Bank 2<br>~~a~~<br>~~po~~<br>~~po~~|0<br>~~po~~<br>~~po~~|0|0|0|0|0|0|0|0|
||Bank 3<br>~~po~~<br>~~po~~|0<br>~~po~~<br>~~po~~|0|0|0|0|0|0|0|0|
||Bank 4<br>~~po~~<br>~~po~~|0<br>~~po~~<br>~~po~~|0<br>~~po~~|0<br>~~po~~|0<br>~~po~~|0<br>~~po~~|0<br>~~po~~|0<br>~~po~~|0<br>~~po~~|0<br>~~po~~|
||Bank 5<br>~~a~~|0|0|0|0|0|0|0|0|0|
||Bank 6<br>~~a~~<br>~~a~~|0<br>|0<br>|0<br>|0<br>|0<br>|0<br>|0<br>|0|0|
||Bank 7<br>~~aee~~<br>~~po~~|0<br>~~ee~~<br>~~po~~|0<br>~~ee~~|0<br>~~ee~~|0<br>~~GO~~|0<br>~~GO~~|0<br>~~GO~~|0<br>~~GO~~|0|0|
|Shared PCLK<br>Pins<br>~~po~~<br>~~po~~<br>~~po~~|Bank 0<br>~~ee~~<br>~~po~~|0<br>~~ee~~<br>~~po~~|0<br>~~ee~~|2<br>~~ee ~~|2<br> ~~GO~~|2<br>~~GO~~|2<br>~~GO~~|2<br>~~GO~~|2|2|
||Bank 1<br>~~po~~<br>~~po~~|0<br>~~po~~<br>~~po~~|0<br>~~po~~|3<br>~~po~~|3<br>~~po~~|0<br>~~po~~|3<br>~~po~~|3<br>~~po~~|3<br>~~po~~|3<br>~~po~~|
||Bank 2<br>~~a~~|0|0|0|0|0|0|3|3|3|
||Bank 3<br>~~a~~<br>~~a~~<br>~~po~~|8|8|8|8|8|8|8|8|8|
||Bank 4<br>~~a~~<br>~~po~~<br>~~po~~|0<br>~~po~~|0|8|8|0|8|8|8|8|
||Bank 5<br>~~po~~<br>~~po~~|8<br>~~po~~|8|8|8|8|8|8|8|8|
||Bank 6<br>~~po~~<br>~~po~~|0<br>~~po~~<br>~~po~~|0<br>~~po~~|0<br>~~po~~|0<br>~~po~~|0<br>~~po~~|0<br>~~po~~|3<br>~~po~~|3<br>~~po~~|3<br>~~po~~|
||Bank 7<br>~~a~~|0<br>~~a~~|0<br>~~a~~|0<br>~~Ge~~|0<br>~~Ge~~|0|0|3|3|3|
© 2021-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02049-1.8
155
**CrossLink-NX Family Data Sheet**
|**Pin Information**<br>**Summary**<br>~~eee~~|**Pin Information**<br>**Summary**<br>~~eee~~|**LIFCL-17**<br>~~a~~<br>~~eeeeenseee~~|**LIFCL-17**<br>~~a~~<br>~~eeeeenseee~~|**LIFCL-17**<br>~~a~~<br>~~eeeeenseee~~|**LIFCL-17**<br>~~a~~<br>~~eeeeenseee~~|**LIFCL-40**<br>~~a~~<br>~~eeeeeoeee~~|**LIFCL-40**<br>~~a~~<br>~~eeeeeoeee~~|**LIFCL-40**<br>~~a~~<br>~~eeeeeoeee~~|**LIFCL-40**<br>~~a~~<br>~~eeeeeoeee~~|**LIFCL-40**<br>~~a~~<br>~~eeeeeoeee~~|
|---|---|---|---|---|---|---|---|---|---|---|
|||**72 QFN**<br>~~eee~~|**72WLCSP**<br>~~eens~~|**121csfBGA**<br>~~eens~~|**256caBGA**<br>~~eee~~|**72 QFN**<br>~~eee~~|**121csfBGA**<br>~~eee~~|**256caBGA**<br>~~ee~~|**289csBGA**<br>~~oe~~|**289csBGA**<br>**400caBGA**<br>~~ee~~|
|Shared GPLL<br>Pins<br>~~eee~~<br>~~po~~|Bank 0<br>~~eee~~<br>~~a~~<br>~~po|~~|0<br>~~eee ~~<br>~~eG~~<br>~~|CU~~|0<br> ~~eens~~<br>~~eG~~<br>~~CU~~|0<br>~~eens ~~<br>~~eG~~|0<br> ~~eee ~~<br>~~eG~~|0<br> ~~eee~~<br>~~eG~~|0<br>~~eee ~~<br>~~eG~~|0<br> ~~ee ~~<br>~~eG~~|0<br> ~~oe ~~<br>~~eG~~|0<br> ~~ee~~<br>~~eG~~|
||Bank 1<br>~~po|~~<br>~~a~~|0<br>~~|CU~~|0<br>~~CU~~<br>~~eG~~|0<br>~~eG~~|0<br>~~eG~~|0<br>~~Ge~~|0<br>~~Ge~~|0|0|0|
||Bank 2<br>~~po |~~<br>~~a~~|0<br>~~| CU~~|0<br>~~CU~~<br>~~eG~~|0<br>~~eG~~|0<br>~~eG~~|0<br>~~Ge~~|0<br>~~Ge~~|0|0|0|
||Bank 3<br>~~a~~<br>~~a~~<br>~~a~~|2<br>~~ee~~|2<br>~~eG~~<br>~~ee~~<br>~~ee~~|2<br>~~eG~~<br>~~ee~~<br>~~ee~~|2<br>~~eG ~~<br>~~ee~~<br>~~ee~~|2<br> ~~Ge~~<br>~~ee~~<br>~~Ge~~|2<br>~~Ge~~<br>~~ee~~|2<br>~~ee~~|2<br>~~ee~~|2<br>~~ee~~|
||Bank 4<br>~~a~~|0|0<br>~~ee~~|0<br>~~ee~~|0<br>~~ee~~|0<br>~~Ge~~|0|0|0|0|
||Bank 5<br>~~a~~<br>~~ee~~<br>~~a~~|2<br>~~ee~~|2<br>~~ee~~<br>~~ee~~<br>~~eG~~|2<br>~~ee~~<br>~~ee~~<br>~~eG~~|2<br>~~ee~~<br>~~ee~~<br>~~eG~~|2<br>~~Ge~~<br>~~ee~~<br>~~Ge~~|2<br>~~ee~~<br>~~Ge~~|2<br>~~ee~~|2<br>~~ee~~|2<br>~~ee~~|
||Bank 6<br>~~ee~~<br>~~a~~<br>~~sO~~|0<br>~~ee~~<br>~~sO~~|0<br>~~ee~~<br>~~eG~~<br>~~sO~~|0<br>~~ee~~<br>~~eG~~<br>~~Ge~~|0<br>~~ee~~<br>~~eG~~<br>~~Ge~~|0<br>~~ee~~<br>~~Ge~~<br>~~GO~~|0<br>~~ee~~<br>~~Ge~~<br>~~GO~~|0<br>~~ee~~<br>~~GO~~|0<br>~~ee~~<br>~~GO~~|0<br>~~ee~~<br>~~GO~~|
||Bank 7<br>~~a~~<br>~~sO~~|0<br>~~sO~~|0<br>~~eG~~<br>~~sO~~|0<br>~~eG~~<br>~~Ge~~|0<br>~~eG ~~<br>~~Ge~~|0<br> ~~Ge~~<br>~~GO~~|0<br>~~Ge~~<br>~~GO~~|2<br>~~GO~~|2<br>~~GO~~|2<br>~~GO~~|
|Shared VREF<br>Pins|Bank 0<br>~~sO~~<br>~~a~~<br>~~a~~|0<br>~~sO~~<br>~~eG~~|0<br>~~sO~~<br>~~eG~~<br>~~ee~~|0<br>~~Ge ~~<br>~~eG~~<br>~~ee~~|0<br> ~~Ge~~<br>~~eG~~<br>~~ee~~|0<br>~~GO~~<br>~~eG~~<br>~~Ge~~|0<br>~~GO~~<br>~~eG~~|0<br>~~GO~~<br>~~eG~~|0<br>~~GO~~<br>~~eG~~|0<br>~~GO~~<br>~~eG~~|
||Bank 1<br>~~a~~|0|0<br>~~ee~~|0<br>~~ee~~|0<br>~~ee~~|0<br>~~Ge~~|0|0|0|0|
||Bank 2<br>~~a~~<br>~~eG~~|0<br>~~eG~~|0<br>~~ee~~<br>~~eG~~|0<br>~~ee~~<br>~~eG~~|0<br>~~ee~~<br>~~eG~~|0<br>~~Ge~~<br>~~eG~~<br>~~Ge~~|0<br>~~eG~~<br>~~Ge~~|0<br>~~eG~~<br>~~Ge~~|0<br>~~eG~~|0<br>~~eG~~|
||Bank 3<br>~~a ee~~|2<br>~~ee~~|2<br>~~ee~~|2<br>~~ee~~|2<br>~~ee~~|2<br>~~ee~~<br>~~Ge~~|2<br>~~ee~~<br>~~Ge~~|2<br>~~ee~~<br>~~Ge~~|2<br>~~ee~~|2<br>~~ee~~|
||Bank 4<br>~~ee~~|0<br>~~ee~~|0<br>~~ee~~|2<br>~~ee~~|2<br>~~ee~~|0<br>~~Ge~~<br>~~ee~~|1<br>~~Ge~~<br>~~ee~~|2<br>~~Ge~~<br>~~ee~~|2<br>~~ee~~|2<br>~~ee~~|
||Bank 5<br>~~ee~~<br>~~eG~~|2<br>~~ee~~<br>~~eG~~|2<br>~~ee~~<br>~~eG~~|2<br>~~ee~~<br>~~eG~~|2<br>~~ee~~<br>~~eG~~|2<br>~~ee~~<br>~~eG~~|2<br>~~ee~~<br>~~eG~~|2<br>~~ee~~<br>~~eG~~|2<br>~~ee~~<br>~~eG~~|2<br>~~ee~~<br>~~eG~~|
||Bank 6<br>~~a~~|0<br>~~eG~~|0<br>~~eG~~|0|0<br>~~GG~~|0<br>~~GG~~|0<br>~~GG~~|0|0|0|
||Bank 7<br>~~a~~<br>~~a ee~~|0<br>~~eG~~<br>~~ee~~|0<br>~~eG~~<br>~~ee~~|0<br>~~ee~~|0<br>~~GG~~<br>~~ee~~|0<br>~~GG~~<br>~~ee~~|0<br>~~GG~~<br>~~ee~~|0<br>~~ee~~|0<br>~~ee~~|0<br>~~ee~~|
|Shared ADC<br>Channels<br>(pairs)1|Bank 0<br>~~a~~|0<br>~~eG~~|0<br>~~eG~~|0<br>~~eG~~|0<br>~~eG~~|0<br>~~eG~~|0<br>~~eG~~|0<br>~~eG~~|0<br>~~eG~~|0<br>~~eG~~|
||Bank 1<br>~~ee~~<br>~~a~~|0<br>~~ee~~|0<br>~~ee~~<br>~~eG~~|0<br>~~ee~~<br>~~eG~~|0<br>~~ee~~<br>~~eG~~|0<br>~~ee~~<br>~~Ge~~|0<br>~~ee~~<br>~~Ge~~|0<br>~~ee~~|0<br>~~ee~~|0<br>~~ee~~|
||Bank 2<br>~~ee~~<br>~~a~~|0<br>~~ee~~|0<br>~~ee~~<br>~~eG~~|0<br>~~ee~~<br>~~eG~~|0<br>~~ee~~<br>~~eG~~<br>~~GG~~|0<br>~~ee~~<br>~~Ge~~<br>~~GG~~|0<br>~~ee~~<br>~~Ge~~<br>~~GG~~|0<br>~~ee~~|0<br>~~ee~~|0<br>~~ee~~|
||Bank 3<br>~~a~~<br>~~GG~~|5<br>~~GG~~|5<br>~~eG~~<br>~~GG~~|7<br>~~eG~~<br>~~GG~~|7<br>~~eG ~~<br>~~GG~~<br>~~GG~~|5<br> ~~Ge~~<br>~~GG~~<br>~~GG~~|7<br>~~Ge~~<br>~~GG~~<br>~~GG~~|12<br>~~GG~~|12<br>~~GG~~|12<br>~~GG~~|
||Bank 4<br>~~GG~~<br>~~eG~~<br>~~a~~|0<br>~~GG~~<br>~~eG~~<br>|0<br>~~GG~~<br>~~eG~~<br>|0<br>~~GG~~<br>~~eG~~<br>|0<br>~~GG~~<br>~~GG~~<br>~~eG~~<br>|0<br>~~GG~~<br>~~GG~~<br>~~eG~~<br>~~Ge~~<br>|0<br>~~GG~~<br>~~GG~~<br>~~eG~~<br>~~Ge~~<br>|0<br>~~GG~~<br>~~eG~~<br>~~Ge~~<br>|0<br>~~GG~~<br>~~eG~~<br>|0<br>~~GG~~<br>~~eG~~<br>|
||Bank 5<br>~~a ee~~<br>~~a~~|4<br>~~ee~~<br>|4<br>~~ee~~<br>|4<br>~~ee~~<br>|4<br>~~ee~~<br>|4<br>~~ee~~<br>~~Ge~~<br>|4<br>~~ee~~<br>~~Ge~~<br>|4<br>~~ee~~<br>~~Ge~~<br>|4<br>~~ee~~<br>|4<br>~~ee~~<br>|
||Bank 6<br>~~a~~|0<br>~~eG~~|0<br>~~eG~~|0<br>~~eG~~|0<br>~~eG~~|0<br>~~Ge~~<br>~~eG~~|0<br>~~Ge~~<br>~~eG~~|0<br>~~Ge~~<br>~~eG~~|0<br>~~eG~~|0<br>~~eG~~|
||Bank 7<br>~~a eG~~<br>~~a~~|0<br>~~eG~~|0<br>~~eG~~|0<br>~~eG~~<br>~~GG~~|0<br>~~eG~~<br>~~GG~~|0<br>~~eG~~<br>~~GS~~|0<br>~~eG~~<br>~~GS~~|0<br>~~eG~~<br>~~GS~~|0<br>~~eG~~|0<br>~~eG~~|
|Shared<br>Comparator<br>Channels<br>(pairs)1, 2<br>~~po~~<br>~~po~~|Bank 0<br>~~Gs~~<br>~~a~~<br>~~po~~|0<br>~~Gs~~|0<br>~~Gs~~<br>~~eG~~|0<br>~~Gs~~<br>~~GG~~<br>~~eG~~|0<br>~~Gs~~<br>~~GG~~<br>~~eG~~|0<br>~~Gs~~<br>~~GS~~<br>~~Ge~~|0<br>~~Gs~~<br>~~GS~~<br>~~Ge~~|0<br>~~Gs~~<br>~~GS~~|0<br>~~Gs~~|0<br>~~Gs~~|
||Bank 1<br>~~Gs~~<br>~~a~~<br>~~po~~|0<br>~~Gs~~|0<br>~~Gs~~<br>~~eG~~|0<br>~~Gs~~<br>~~GG~~<br>~~eG~~|0<br>~~Gs~~<br>~~GG ~~<br>~~eG~~|0<br>~~Gs~~<br> ~~GS~~<br>~~Ge~~|0<br>~~Gs~~<br>~~GS~~<br>~~Ge~~|0<br>~~Gs~~<br>~~GS~~|0<br>~~Gs~~|0<br>~~Gs~~|
||Bank 2<br>~~po~~<br>~~a~~|0|0<br>~~eG~~|0<br>~~eG~~|0<br>~~eG~~|0<br>~~Ge~~<br>~~**G**~~|0<br>~~Ge~~<br>~~**G**e~~|0<br>~~e~~|0|0|
||Bank 3<br>~~po~~<br>~~a~~<br>~~a~~|0<br>~~Be~~|0<br>~~eG~~<br>~~Be~~|0<br>~~eG~~<br>~~Be~~|0<br>~~eG ~~<br>~~Be~~|0<br> ~~Ge~~<br>~~Be~~<br>~~**G**~~|0<br>~~Ge~~<br>~~Be~~<br>~~**G**e~~|3<br>~~Be~~<br>~~e~~|3<br>~~Be~~|3<br>~~Be~~|
||Bank 4<br>~~a~~|0|0<br>~~Ge~~|0<br>~~Ge~~|0|0<br>~~**G**~~|0<br>~~**G**e~~<br>~~e~~|0<br>~~e~~|0|0|
||Bank 5<br>~~a~~<br>~~a~~|0<br>~~GG~~|0<br>~~GG~~<br>~~eG~~|0<br>~~GG~~<br>~~eG~~|0<br>~~GG~~<br>~~eG~~|0<br>~~GG~~<br>~~Ge~~|0<br>~~GG~~<br>~~Ge~~|3|3|3|
||Bank 6<br>~~a~~<br>~~a~~|0<br>~~GG~~|0<br>~~GG~~<br>~~eG~~|0<br>~~GG ~~<br>~~eG~~|0<br> ~~GG~~<br>~~eG~~|0<br>~~GG~~<br>~~Ge~~|0<br>~~GG~~<br>~~Ge~~|0|0|0|
||Bank 7<br>~~a~~<br>~~a~~<br>~~po~~|0<br>~~Ge~~|0<br>~~eG~~<br>~~Ge~~|0<br>~~eG~~<br>~~GG~~|0<br>~~eG ~~<br>~~GG~~|0<br> ~~Ge~~<br>~~Ge~~|0<br>~~Ge~~<br>~~Ge~~|0|0|0|
|Shared SGMII<br>Channels (pairs)<br>~~po~~<br>~~po~~<br>~~Po~~|Bank 0<br>~~a~~<br>~~po~~|0<br>~~Ge~~|0<br>~~Ge~~|0<br>~~GG~~|0<br>~~GG~~|0<br>~~Ge~~|0<br>~~Ge~~|0|0|0|
||Bank 1<br>~~po~~<br>~~a~~|0<br>~~GG~~|0<br>~~GG~~|0<br>~~GG~~|0<br>~~GG~~|0<br>~~GG~~|0<br>~~GG~~|0|0|0|
||Bank 2<br>~~a~~<br>~~a~~<br>~~a~~|0<br>~~GG~~<br>~~eG~~|0<br>~~GG~~<br>~~eG~~<br>~~eG~~|0<br>~~GG ~~<br>~~eG~~<br>~~eG~~|0<br> ~~GG~~<br>~~eG~~<br>~~eG~~|0<br>~~GG~~<br>~~eG~~<br>~~Ge~~|0<br>~~GG~~<br>~~eG~~<br>~~Ge~~|0<br>~~eG~~|0<br>~~eG~~|0<br>~~eG~~|
||Bank 3<br>~~a~~<br>~~a~~|0<br>~~eG~~|0<br>~~eG~~<br>~~eG~~|0<br>~~eG~~<br>~~eG~~|0<br>~~eG~~<br>~~eG~~|0<br>~~eG~~<br>~~Ge~~|0<br>~~eG~~<br>~~Ge~~|0<br>~~eG~~|0<br>~~eG~~|0<br>~~eG~~|
||Bank 4<br>~~a~~<br>~~a~~<br>~~po~~|0<br>~~GG~~|0<br>~~eG~~<br>~~GG~~|0<br>~~eG~~<br>~~GG~~|0<br>~~eG ~~<br>~~GG~~|0<br> ~~Ge~~<br>~~GG~~|0<br>~~Ge~~<br>~~GG~~|0|0|0|
||Bank 5<br>~~a~~<br>~~po~~|2<br>~~GG~~|2<br>~~GG~~|2<br>~~GG ~~|2<br> ~~GG~~|2<br>~~GG~~|2<br>~~GG~~|2|2|2|
||Bank 6<br>~~po~~<br>~~a~~<br>~~Po~~|0<br>~~GG~~<br>~~Po~~|0<br>~~GG~~|0<br>~~GG~~|0<br>~~GG~~|0<br>~~GG~~|0<br>~~GG~~|0|0|0|
||Bank 7<br>~~a~~<br>~~Po~~|0<br>~~GG~~<br>~~Po~~|0<br>~~GG~~|0<br>~~GG ~~|0<br> ~~GG~~|0<br>~~GG~~|0<br>~~GG~~|0|0|0|
## **Notes:**
1. ADC is available in Commercial/Industrial –8 and –9 speed grades and Automotive –7 speed grade.
2. Comparator inputs are selected in the software to be separate (Bank 3) or combined with ADC Channels (Bank 5).
3. ADC is powered by VCCAUX.
© 2021-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02049-1.8
156
**CrossLink-NX Family Data Sheet**
## **6. Ordering Information**
Lattice provides a wide variety of services for its products including custom marking, factory programming, known good die, and application specific testing. Contact the local sales representatives for more details.
## **6.1. Part Number Description**
**==> picture [415 x 195] intentionally omitted <==**
**----- Start of picture text -----**<br>
LIFCL - 40 - X XXXX X<br>Grade<br>Device Family<br> C = Commercial<br> CrossLink-NX FPGA<br> I = Industrial<br> A = Automotive<br>Logic Capacity<br> 40 = 39 k Logic Cells<br>Package<br> SG72 = 72-pin QFN<br> MG121 = 121-ball csfBGA<br> BG256 = 256-ball caBGA<br> MG289 = 289-ball csBGA<br> BG400 = 400-ball caBGA<br>Speed (same number for HP and LP)*<br> 7 = Slowest<br> 8<br> 9 = Fastest<br>**----- End of picture text -----**<br>
**==> picture [415 x 190] intentionally omitted <==**
**----- Start of picture text -----**<br>
LIFCL - 17 - X XXXX X<br>Device Family Grade<br> CrossLink-NX FPGA C = Commercial<br> I = Industrial<br> A = Automotive<br>Logic Capacity<br> 17 = 17 k Logic Cells<br>Package<br> UWG72 = 72-ball WLCSP<br> SG72 = 72-pin QFN<br> MG121 = 121-ball csfBGA<br> BG256 = 256-ball caBGA<br>=<br>Speed (same number for HP and LP)*<br> 7 = Slowest<br> 8<br> 9 = Fastest<br>**----- End of picture text -----**<br>
> ***Note:** Input Comparator, ADC, EBR ECC, and DTR are only available in –7 (-A), –8 (-C/I), and –9 (-C/I) speed and grade.
© 2021-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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## **6.2. Ordering Part Numbers**
**==> picture [487 x 377] intentionally omitted <==**
**----- Start of picture text -----**<br>
||||||||||
|---|---|---|---|---|---|---|---|---|
|6.2.1.|Commercial|
|dG|Part Number|Speed|Packa|GO|ge|Pins|Temp.|Logic Cells (k)|
|LIFCL-17-7UWG72C|–7|Lead free WLCSP|72|Commercial|17|
|eG|
|LIFCL-17-8UWG72C|–8|Lead free WLCSP|72|Commercial|17|
|GO|
|fe|LIFCL-17-7SG72C|–7|Lead free QFN|GO|72|Commercial|17|
|GG|LIFCL-17-8SG72C|–8|Lead free QFN|72|Commercial|17|
|GG|LIFCL-17-9SG72C|–9|Lead free QFN|72|Commercial|17|
|LIFCL-17-7MG121C|–7|Lead free csfBGA|121|Commercial|17|
|feOG|
|LIFCL-17-8MG121C|–8|Lead free csfBGA|121|Commercial|17|
|ee|GO|
|LIFCL-17-9MG121C|–9|Lead free csfBGA|121|Commercial|17|
|feGO|
|LIFCL-17-7BG256C|–7|Lead free caBGA|256|Commercial|17|
|GG|
|LIFCL-17-8BG256C|–8|Lead free caBGA|256|Commercial|17|
|GG|
|LIFCL-17-9BG256C|–9|Lead free caBGA|256|Commercial|17|
|GG|
|ee|LIFCL-40-7SG72C|–7|Lead free QFN|GO|72|Commercial|39|
|fe|LIFCL-40-8SG72C|–8|Lead free QFN|GO|72|Commercial|39|
|GG|LIFCL-40-9SG72C|–9|Lead free QFN|72|Commercial|39|
|LIFCL-40-7MG121C|–7|Lead free csfBGA|121|Commercial|39|
|GG|
|LIFCL-40-8MG121C|–8|Lead free csfBGA|121|Commercial|39|
|GG|
|LIFCL-40-9MG121C|–9|Lead free csfBGA|121|Commercial|39|
|ee|GO|
|LIFCL-40-7MG289C|–7|Lead free csBGA|289|Commercial|39|
|fe|
|LIFCL-40-8MG289C|–8|Lead free csBGA|289|Commercial|39|
|fe|G|OO|
|LIFCL-40-9MG289C|–9|Lead free csBGA|289|Commercial|39|
|GG|
|LIFCL-40-7BG256C|–7|Lead free caBGA|256|Commercial|39|
|pO|
|LIFCL-40-8BG256C|–8|Lead free caBGA|256|Commercial|39|
|Ge|GO|
|LIFCL-40-9BG256C|–9|Lead free caBGA|256|Commercial|39|
|feGO|
|LIFCL-40-7BG400C|–7|Lead free caBGA|400|Commercial|39|
|Ge|
|LIFCL-40-8BG400C|–8|Lead free caBGA|400|Commercial|39|
|fe|OGGO|
|LIFCL-40-9BG400C|–9|Lead free caBGA|400|Commercial|39|
|GG|
**----- End of picture text -----**<br>
**6.2.2. Industrial**
**==> picture [486 x 218] intentionally omitted <==**
**----- Start of picture text -----**<br>
||||||||||
|---|---|---|---|---|---|---|---|---|
|ef|Part Number|Speed|Packa|OO|ge|Pins|Temp.|Logic Cells (k)|
|LIFCL-17-8UWG72I|–8|Lead free WLCSP|72|Industrial|17|
|feGO|
|Ge|LIFCL-17-7SG72I|–7|Lead free QFN|72|Industrial|17|
|fe|LIFCL-17-8SG72I|–8|OG|Lead free QFN|GO|72|Industrial|17|
|pf|LIFCL-17-9SG72I|–9|Lead free QFN|72|Industrial|17|
|LIFCL-17-7MG121I|–7|Lead free csfBGA|121|Industrial|17|
|dG|GO|
|LIFCL-17-8MG121I|–8|Lead free csfBGA|121|Industrial|17|
|dGGO|
|LIFCL-17-9MG121I|–9|Lead free csfBGA|121|Industrial|17|
|fe|
|LIFCL-17-7BG256I|–7|Lead free caBGA|256|Industrial|17|
|fe|OGGO|
|LIFCL-17-8BG256I|–8|Lead free caBGA|256|Industrial|17|
|pf|
|LIFCL-17-9BG256I|–9|Lead free caBGA|256|Industrial|17|
|dG|GO|
|dG|LIFCL-40-7SG72I|–7|Lead free QFN|GO|72|Industrial|39|
|Ge|LIFCL-40-8SG72I|–8|Lead free QFN|GO|72|Industrial|39|
|fe|LIFCL-40-9SG72I|–9|Lead free QFN|72|Industrial|39|
|LIFCL-40-7MG121I|–7|Lead free csfBGA|121|Industrial|39|
|ee|GODO|
|LIFCL-40-8MG121I|–8|Lead free csfBGA|121|Industrial|39|
|De|FO|
**----- End of picture text -----**<br>
© 2021-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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**Data Sheet**
|**Part Number**<br>~~eC~~|**Speed**<br>~~eC~~|**Package **<br>~~eC~~<br>~~GO~~|**Pins**<br>~~eC~~<br>~~GO~~|**Temp. **<br>~~eC~~|**Logic Cells(k)**<br>~~eC~~|
|---|---|---|---|---|---|
|LIFCL-40-9MG121I<br>~~GG~~|–9<br>~~GG~~|Lead free csfBGA<br>~~GO~~<br>~~GG~~|121<br>~~GO~~<br>~~GG~~|Industrial<br>~~GG~~|39<br>~~GG~~|
|LIFCL-40-7MG289I<br>~~GG~~|–7<br>~~GG~~|Lead free csBGA<br>~~GG~~|289<br>~~GG~~|Industrial<br>~~GG~~|39<br>~~GG~~|
|LIFCL-40-8MG289I<br>~~ee~~|–8<br>~~ee~~|Lead free csBGA<br>~~GO~~<br>~~GO~~|289<br>~~GO~~<br>~~GO~~|Industrial|39|
|LIFCL-40-9MG289I<br>~~ee~~<br>~~Ge~~|–9<br>~~ee~~<br>~~Ge~~|Lead free csBGA<br>~~GO~~<br>~~Ge~~<br>~~GO~~<br>~~Ge~~|289<br>~~GO~~<br>~~Ge~~<br>~~GO~~<br>~~Ge~~|Industrial<br>~~Ge~~|39<br>~~Ge~~|
|LIFCL-40-7BG256I<br>~~Ge~~|–7<br>~~Ge~~|Lead free caBGA<br>~~GO~~<br>~~Ge~~<br>~~Ge~~<br>~~GO~~|256<br>~~GO~~<br>~~Ge~~<br>~~Ge~~<br>~~GO~~|Industrial<br>~~Ge~~|39<br>~~Ge~~|
|LIFCL-40-8BG256I<br>~~Ge~~|–8<br>~~Ge~~|Lead free caBGA<br>~~Ge~~<br>~~Ge~~<br>~~GO~~|256<br>~~Ge~~<br>~~Ge~~<br>~~GO~~|Industrial<br>~~Ge~~|39<br>~~Ge~~|
|LIFCL-40-9BG256I<br>~~GG~~|–9<br>~~GG~~|Lead free caBGA<br>~~GO~~<br>~~GG~~|256<br>~~GO~~<br>~~GG~~|Industrial<br>~~GG~~|39<br>~~GG~~|
|LIFCL-40-7BG400I<br>~~GO~~|–7<br>~~GO~~|Lead free caBGA<br>~~GO~~<br>~~GO~~|400<br>~~GO~~<br>~~GO~~|Industrial<br>~~GO~~|39<br>~~GO~~|
|LIFCL-40-8BG400I<br>~~GO~~<br>~~fe~~|–8<br>~~GO~~<br>~~fe~~|Lead free caBGA<br>~~GO~~<br>~~fe~~<br>~~GO~~<br>~~FO~~|400<br>~~GO~~<br>~~fe~~<br>~~GO~~<br>~~FO~~|Industrial<br>~~GO~~<br>~~fe~~|39<br>~~GO~~<br>~~fe~~|
|LIFCL-40-9BG400I<br>~~De~~|–9<br>~~De~~|Lead free caBGA<br>~~GO~~<br>~~De~~<br>~~FO~~|400<br>~~GO~~<br>~~De~~<br>~~FO~~|Industrial<br>~~De~~|39<br>~~De~~|
## **6.2.3. Automotive**
|**Part Number**|**Speed**|**Package **|**Pins**|**Temp. **|**Logic Cells(k)**|
|---|---|---|---|---|---|
|LIFCL-17-7MG121A|–7|Lead free csfBGA|121|Automotive|17|
|LIFCL-17-7BG256A|–7|Lead free caBGA|256|Automotive|17|
|LIFCL-40-7MG121A|–7|Lead free csfBGA|121|Automotive|39|
|LIFCL-40-7BG256A|–7|Lead free caBGA|256|Automotive|39|
© 2021-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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**CrossLink-NX Family Data Sheet**
## **Supplemental Information**
## **For Further Information**
A variety of technical notes for the CrossLink-NX family are available.
- sub-LVDS Signaling Using Lattice Devices (FPGA-TN-02028)
- Thermal Management (FPGA-TN-02044)
- sysI/O User Guide for Nexus Platform (FPGA-TN-02067)
- Power Management and Calculation for CrossLink-NX Devices (FPGA-TN-02075)
- Soft Error Detection (SED)/Correction (SEC) User Guide for Nexus Platform (FPGA-TN-02076)
- CrossLink-NX Hardened D-PHY User Guide (FPGA-TN-02081)
- Using TraceID (FPGA-TN-02084)
- Memory User Guide for Nexus Platform (FPGA-TN-02094)
- sysCLOCK PLL Design and User Guide for Nexus Platform (FPGA-TN-02095)
- sysDSP User Guide for Nexus Platform (FPGA-TN-02096)
- CrossLink-NX High-Speed I/O Interface (FPGA-TN-02097)
- sysCONFIG User Guide for Nexus Platform (FPGA-TN-02099)
- ADC User Guide for Nexus Platform (FPGA-TN-02129)
- I[2] C Hardened IP User Guide for Nexus Platform (FPGA-TN-02142)
- Multi-Boot User Guide for Nexus Platform (FPGA-TN-02145)
- High-Speed PCB Design Considerations (FPGA-TN-02178)
- CrossLink-NX Hardware Checklist (FPGA-TN-02149)
- CrossLink-NX Single Event Upset (SEU) Report (FPGA-TN-02174)
- Lattice Memory Mapped Interface and Lattice Interrupt Interface User Guide (FPGA-UG-02039)
For further information on interface standards refer to the following websites:
- JEDEC Standards (LVTTL, LVCMOS, SSTL) – www.jedec.org
- PCI – www.pcisig.com
© 2021-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
160
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**CrossLink-NX Family Data Sheet**
## **Technical Support Assistance**
Submit a technical support case through www.latticesemi.com/techsupport. For frequently asked questions, refer to the Lattice Answer Database at ww.latticesemi.com/Support/AnswerDatabase.
© 2021-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02049-1.8
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**CrossLink-NX Family Data Sheet**
## **Revision History**
|**Revision History**|**Revision History**||
|---|---|---|
|**Revision 1.8, March 2023**|||
|**Section**<br>**Change Summary**<br>DC and Switching Characteristics<br>for Commercial and Industrial<br>Changed the Note 1.b information from_Bank 3, Bank 4, and Bank 5 I/O can only mix into_<br>_banks with VCCIO higher than the pin standard, due to clamping diode on the pin in these_<br>_banks. Bank 0, Bank 1, Bank 2, Bank 6, and Bank 7 does not have this restriction_<br>to_Bank 3, Bank 4, and Bank 5 I/O can only mix into banks with VCCIO higher than or equal to_<br>_the pin standard, due to clamping diode on the pin in these banks. Bank 0, Bank 1, Bank 2,_<br>_Bank 6, and Bank 7 does not have this restriction_inTable 3.13. sysI/O Recommended<br>OperatingConditions.<br>~~Pp~~|||
|**Revision 1.7, March 2023**<br>**Section**<br>**Change Summary**<br>Acronyms in This Document<br>Deleted Acronym “MLDVS’ and its definition “Multipoint Low-Voltage Differential Signaling”<br>in Acronyms in This Document table.<br>Supplemental Information<br>Added link for High Speed PCB Design Considerations(FPGA-TN-02178).<br>Technical Support Assistance<br>Added Technical Support Assistance section.<br>~~—~~|||
|**Revision 1.6, January 2023**<br>**Section**<br>**Change Summary**<br>Architecture<br>Adjustment in formatting to move Clocking Structure as sub-section under the Architecture<br>section.<br>DC and Switching Characteristics<br>for Commercial and Industrial<br>Updated the following in Table 3.33. External Switching Characteristics (VCC = 1.0 V):<br>•<br>Added footnote for tSKEW_PRIand tSKEW_EDGE.<br>Updated fDATA_GDDRX4_MPin Soft D-PHY DDRX4groupto addpackages.<br>DC and Switching Characteristics<br>for Automotive<br>Updated the following in Table 4.33. External Switching Characteristics (VCC = 1.0 V):<br>•<br>Added footnote for tSKEW_PRIand tSKEW_EDGE.<br>•<br>Updated fDATA_GDDRX4_MPin Soft D-PHY DDRX4groupto addpackages.<br>~~oe~~|||
|**Revision 1.5, September 2022**|||
||**Section**|**Change Summary**|
||All|Minor changes in formatting, including removing product name from heading, figure, and|
|||table names.|
||General Description|•<br>Updated the following in Table 1.1. CrossLink-NX Commercial/Industrial Family Selection|
|||Guide:|
|||•<br>Changed Distributed RAM for LIFCL-17 and LIFCL-40 to 108 kb and 252 kb,|
|||respectively.|
|||•<br>Changed HP GPIO for LIFCL-40 in 256 caBGA, 289 csBGA, and 400 caBGA packages|
|||from 74 to 148.|
|||•<br>Corrected typo from WLSCP to WLCSP.|
|||•<br>Updated table note 3 to specify available speed grade for Commercial/Industrial.|
|||•<br>Updated table note 3 to specify available speed grade for Automotive in Table 1.2.|
|||CrossLink-NX Automotive FamilySelection Guide.|
||Architecture|•<br>Updated Analog Interface section content to specify the speed grades the feature is|
|||available.|
|||•<br>Updated the following in SGMII Tx/Rx section:|
|||•<br>Changed section name from SGMII Clock Data Recovery to SGMII Tx/Rx.|
|||•<br>Updated content to specify that the device utilizes different components/resources|
|||for the SGMII transmit and receivepaths.|
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
© 2021-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
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|**Section**|**Change Summary**|
|---|---|
||•<br>Updated sysMEM Memory Block section content to specify the speed grades the ECC<br>engine is available.|
|DC and Switching Characteristics<br>for Commercial and Industrial|•<br>Added Table 3.17. VIN Maximum Overshoot/Undershoot Allowance – Wide Range and<br>Table 3.18. VIN Maximum Overshoot/Undershoot Allowance – High Performance.<br>•<br>Updated the following in Table 3.29. Maximum I/O Buffer Speed:<br>•<br>Changed max data rate (for both Maximum sysI/O Input and Output Frequency) of<br>caBGA256, csBGA289, and caBGA400 to 1500.<br>•<br>Updated footnote reference in the Differential groups.<br>•<br>Updated DSP functions in Table 3.31. Register-to-Register Performance.<br>•<br>Updated the following in Table 3.34. sysCLOCK PLL Timing (VCC = 1.0 V) –<br>Commercial/Industrial:<br>•<br>Raised minimum input clock frequency from 10 to 18 MHz.<br>•<br>Raised minimum phase detector input frequency from 10 to 18 MHz; removed table<br>note and table note reference.<br>•<br>Corrected tPHfootnote.<br>•<br>Removed and Added conditions for the tOPJITparameter to accurately reflect PLL<br>jitter performance.<br>•<br>Updated table note 1 in Table 3.37. ADC Specifications to specify available speed grade<br>for ADC.<br>•<br>Updated table note 2 in Table 3.39. DTR Specifications to specify available speed grade<br>for DTR.<br>•<br>Updated the following in SGMII Characteristics section:<br>•<br>Updated header and sub section names.<br>•<br>Updated table name to Table 3.47 SGMII and added table note 2 to specify SGMII is<br>not supported on 72-pinpackages.|
|DC and Switching Characteristics<br>for Automotive|•<br>Added Table 4.17. VIN Maximum Overshoot/Undershoot Allowance – Wide Range and<br>Table 4.18. VIN Maximum Overshoot/Undershoot Allowance – High Performance.<br>•<br>Updated Table 4.29. Maximum I/O Buffer Speed:<br>•<br>Changed max data rate (for both Maximum sysI/O Input and Output Frequency) of<br>caBGA256, csBGA289, and caBGA400 to 1500.<br>•<br>Updated footnote reference in the Differential groups.<br>•<br>Updated DSP functions in Table 4.31. Register-to-Register Performance.<br>•<br>Updated Table 4.33. External Switching Characteristics (VCC = 1.0 V) to remove -8 Auto<br>speed grade.<br>•<br>Updated the following in Table 4.34. sysCLOCK PLL Timing (VCC = 1.0 V) – Automotive:<br>•<br>Raised minimum input clock frequency from 10 to 18 MHz.<br>•<br>Raised minimum phase detector input frequency from 10 to 18 MHz; removed table<br>note and table note reference.<br>•<br>Corrected tPHfootnote.<br>•<br>Removed and Added conditions for the tOPJITparameter to accurately reflect PLL<br>jitter performance.<br>•<br>Added table note 3 in Table 4.37. ADC Specifications to specify available speed grade for<br>ADC.<br>•<br>Updated table note 2 in Table 4.39. DTR Specifications to specify available speed grade<br>for DTR.<br>•<br>Added SGMII Characteristics section.|
|Pinout Information|•<br>Updated table note 2 in Signal Descriptions to specify available speed grade for ADC.<br>•<br>Updated the following in Pin Information Summary:<br>•<br>Updated Bank 5 values for 72QFN and 121csfBGA (LIFCL-17 and LIFCL-40), 72WLCSP<br>and 256caBGA (LIFCL-17).<br>•<br>Updated table note 1 to specifyavailable speedgrade for ADC.|
© 2021-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02049-1.8
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**CrossLink-NX Family Data Sheet**
## **Revision 1.4, June 2022**
|**Section**|**Change Summary**|
|---|---|
|DC and Switching Characteristics<br>for Commercial and Industrial|Updated max value of ZOSin Table 3.22. SLVS Output DC Characteristics.|
|DC and Switching Characteristics<br>for Automotive|•<br>Updated LVDS and subLVDS VCCIO(Input) value in Table 4.13. sysI/O Recommended<br>Operating Conditions.<br>•<br>Updated max value of ZOSin Table 4.22. SLVS Output DC Characteristics.|
|Pinout Information|•<br>Added table note 3 and table note reference to VCCADC18in 72WLCSP and 121csfBGA<br>(LIFLCL-17 and LIFCL-40); Added table note and reference to table note for Dedicated<br>ADCI/O Pins; Adjustment in formatting to remove superscripts for Shared Configuration<br>Pins, Shared User GPIO Pins, and Shared CLOCK Pins in Signal Descriptions.<br>•<br>Added table note 3 and table note reference to VCCADC18; Updated 256caBGA, 289csBGA,<br>and 400caBGA values for Dedicated ADC channels, Dedicated ADC reference, and Total<br>Dedicated Pins; Updated 256caBGA and 289csBGA values for Bank 3 Shared Comparator<br>Channels and add table note 2 in Pin Information Summary.|
## **Revision 1.3, March 2022**
|**Section**|**Change Summary**|
|---|---|
|All|Adjustments in formatting and wording across the document, including changing the<br>reference document names from Usage Guide to User Guide and changing table footnote<br>with asterisk(*)to one(1).|
|General Description|•<br>Updated content, including rewording some bullet points in the Features section.<br>•<br>Added note for ECC in Flexible Memory Resources bullet point and Dual ADC bullet<br>point.<br>•<br>Updated Table 1.1. CrossLink-NX Commercial/Industrial Family Selection Guide and<br>Table 1.2. CrossLink-NX Automotive Family Selection Guide to add table note 3 for ADC<br>block.|
|Architecture|•<br>Updated content, including rewording some information in the following sections:<br>•<br>Overview<br>•<br>PFU Blocks<br>•<br>Routing<br>•<br>Programmable I/O (PIO)<br>•<br>Programmable I/O Cell (PIC)<br>•<br>Tri-state Register Block<br>•<br>DDR Memory Support<br>•<br>sysI/O Buffer<br>•<br>Analog Interface<br>•<br>Device Configuration<br>•<br>Single Event Upset (SEU) Handling<br>•<br>On-Chip Oscillator<br>•<br>User I²C IP<br>•<br>MIPI D-PHY Blocks<br>•<br>Peripheral Component Interconnect Express (PCIe)<br>•<br>Added information on select speed grades in sysMEM Memory Block and Analog<br>Interface.<br>•<br>Updated note reference in Table 2.2. Slice Signal Descriptions.<br>•<br>Updated TD[1:0] parameter name to T[1:0] in Table 2.8. Tri-state Block Port<br>Description.<br>•<br>Updated Figure 2.6. General Purpose PLL Diagram to correct shading in CLKOS4 and<br>CLKOS5.<br>•<br>Updated DELAY CODE to DELAYCODE_I and DELAYCODE_O in Figure 2.26. DQS Control<br>and DelayBlock(DQSBUF).|
© 2021-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02049-1.8
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**CrossLink-NX Family Data Sheet**
|**Section**|**Change Summary**|
|---|---|
|DC and Switching Characteristics<br>for Commercial and Industrial|•<br>Removed “Over Recommended Operating Conditions” info across the section.<br>•<br>Added this info in the section: All specifications in this Chapter are characterized within<br>recommended operating conditions unless otherwise specified.<br>•<br>Added Commercial and Industrial grade information in ESD Performance.<br>•<br>Updated TAmax value in Table 3.1. Absolute Maximum Ratings.<br>•<br>Updated table note 2 in Table 3.2. Recommended Operating Conditions.<br>•<br>Updated table note 2 in Table 3.6. Hot Socketing Specifications for GPIO.<br>•<br>Updated unit in Table 3.9. Capacitors – Wide Range, Table 3.10. Capacitors – High<br>Performance, Table 3.30. LMMI FMAX Summary, and Table 3.33. Internal Oscillators<br>(VCC = 1.0 V).<br>•<br>Updated LVDS and subLVDS VCCIO (Input) value in Table 3.13. sysI/O Recommended<br>Operating Conditions.<br>•<br>Updated VIH, VIL, IOL, IOHvalues and table notes in Table 3.14. sysI/O DC Electrical<br>Characteristics – Wide Range I/O and Table 3.15. sysI/O DC Electrical Characteristics –<br>High Performance I/O.<br>•<br>Updated information for VCCAUXin LVDS.<br>•<br>Changed VINNto VINMin table note 2 and added table note 3 in Table 3.17. LVDS DC<br>Electrical Characteristics1.<br>•<br>Added table note for VICMin SubLVDS (Input Only).<br>•<br>Updated min and max value of ZOSin Table 3.24. Soft D-PHY Output Timing and Levels.<br>•<br>Updated max value of HSTL15 in Table 3.27. CrossLink-NX Maximum I/O Buffer Speed.<br>•<br>Added reference to table note 2 for 32 k x 32 k True-Dual Port RAM in Table 3.29.<br>Register-to-Register Performance.<br>•<br>Updated Generic DDRX1 group to add WRIO and HPIO in Table 3.31. CrossLink-NX<br>External Switching Characteristics (VCC = 1.0 V).<br>•<br>Updated Min and Max values, added reference for table note 2 in cycles unit, and<br>added table notes for ADC in Table 3.35. ADC Specifications.<br>•<br>Added table note for Comparator in Table 3.36. Comparator Specifications1.<br>•<br>Added table note for ADC in Table 3.37. DTR Specifications.<br>•<br>Updated VTERM-ENdescription, min value of VIDTH (1.5 Gbps), and max value of VIDTL<br>•<br>(1.5 Gbps) in Table 3.38. Hardened D-PHY Input Timing and Levels.<br>•<br>Updated VTX-DE-RATIO-3.5dBdescription and ZRX-HIGH-IMP-DCmin value in Table 3.43. PCIe (2.5<br>Gbps).<br>•<br>Updated VTX-DE-RATIO-3.5dBand VTX-DE-RATIO-6dBdescription in Table 3.44. PCIe (5 Gbps).<br>•<br>Updated row name to Slave SPI/I2C/I3C POR, description of tMSPI_INMand tFIO_EN, max<br>value for tFIO_EN; Changed tDONE_HIGHto tWAKEUP_DONE_HIGHin Wake-Up Timing row, added<br>references table notes, and added table note 2 and 3 in Table 3.46. CrossLink-NX<br>sysCONFIG Port Timing Specifications.<br>•<br>Updated Figure 3.2. LVDS25E Output Termination Example, Figure 3.19. Slave SPI<br>Configuration Timing, Figure 3.20. I2C /I3C Configuration Timing, Figure 3.21. Master<br>SPI Wake-UpTiming, and Figure 3.22. Slave SPI/I2C/I3C Wake-UpTiming.|
© 2021-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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**CrossLink-NX Family Data Sheet**
|**Section**|**Change Summary**|
|---|---|
|DC and Switching Characteristics<br>for Automotive|•<br>Removed “Over Recommended Operating Conditions” info across the section.<br>•<br>Added this info in the section: All specifications in this Chapter are characterized within<br>recommended operating conditions unless otherwise specified.<br>•<br>Added Automotive grade information in ESD Performance.<br>•<br>Updated TAmax value in Table 4.1. Absolute Maximum Ratings.<br>•<br>Updated table note 2 in Table 4.6. Hot Socketing Specifications for GPIO.<br>•<br>Updated unit in Table 4.9. Capacitors – Wide Range, Table 4.10. Capacitors – High<br>Performance, Table 4.30. LMMI FMAX Summary, and Table 4.33. Internal Oscillators<br>(VCC = 1.0 V).<br>•<br>Updated VIH, VIL, IOL, IOHvalues and table notes in Table 4.14. sysI/O DC Electrical<br>Characteristics – Wide Range I/O and Table 4.15. sysI/O DC Electrical Characteristics –<br>High Performance I/O3.<br>•<br>Updated min and max value of ZOSand min value of VOH in Table 4.24. Soft D-PHY<br>Output Timing and Levels.<br>•<br>Updated Generic DDRX1 group to add WRIO and HPIO in Table 4.31. CrossLink-NX<br>External Switching Characteristics (VCC = 1.0 V).<br>•<br>Updated Min and Max values, added reference for table note 2 in cycles unit, and<br>added table notes for ADC in Table 4.35. ADC Specifications.<br>•<br>Added table notes in Table 4.37. DTR Specifications1.<br>•<br>Updated VTERM-ENdescription, min value of VIDTH (1.5 Gbps), and max value of VIDTL<br>(1.5 Gbps) in Table 4.38. Hardened D-PHY Input Timing and Levels.<br>•<br>Updated VTX-DE-RATIO-3.5dBdescription and ZRX-HIGH-IMP-DCmin value in Table 4.43. PCIe (2.5<br>Gbps).<br>•<br>Updated VTX-DE-RATIO-3.5dBand VTX-DE-RATIO-6dBdescription in Table 4.44. PCIe (5 Gbps).<br>•<br>Updated row name to Slave SPI/I2C/I3C POR, description of tMSPI_INM and tFIO_EN,<br>max value fortFIO_EN; Changed tDONE_HIGHto tWAKEUP_DONE_HIGHin Wake-Up Timing row,<br>added references table notes, and added table note 2 and 3 in Table 4.45. CrossLink-NX<br>sysCONFIG Port Timing Specifications.<br>•<br>Updated Figure 4.2. LVDS25E Output Termination Example, Figure 4.3. SubLVDS Input<br>Interface, Figure 4.4. SubLVDS Output Interface, Figure 4.5. SLVS Interface, Figure 4.21.<br>Master SPI Wake-UpTiming, and Figure 4.22. Slave SPI/I2C/I3C Wake-UpTiming.|
|Pinout Information|•<br>Updated description for ADC_REF and ADC_DP/N in Signal Descriptions.<br>•<br>Added table note and reference for Dedicated ADC Channels and Reference in<br>CrossLink-NX Family.|
|OrderingInformation|Added footnote for speed in LIFCL-40 and LIFCL-17 diagrams.|
**Revision 1.2, September 2021**
|**Section**|**Change Summary**|
|---|---|
|All|Changed 17 k and 39 k to 17k and 39k across the document.|
|Architecture|•<br>Changed Successive Approximation Resistor/Capacitor reference to Successive<br>Approximation Register in Analog to Digital Converters section.<br>•<br>Updated SGMII Clock Data Recovery (CDR) section to add information that SGMII CDR is<br>onlyavailable on commercial and industrialgrade devices.|
|DC and Switching Characteristics<br>for Commercial and Industrial|•<br>Updated Figure 3.3 to move resistor to the on-chip side.<br>•<br>Updated Figure 3.14 and Figure 3.15 to move location of power rail and tICFGparameter.<br>•<br>Updated SubLVDSE/SubLVDSEH (Output Only) section content to change Bank 5 and<br>Bank 6 to Bank 6 and Bank 7.<br>•<br>Removed table note 8 reference in Table 3.27.<br>•<br>Updated Min and Max value of fCLKHFin Table 3.33.<br>•<br>Updated DTRRANGEmax value, change values, and added note for external voltage<br>reference in DTRACCURACYin Table 3.37.<br>•<br>Updated table note and test conditions of JTOL_Djand JTOL_Tjin Table 3.45.|
© 2021-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02049-1.8
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**CrossLink-NX Family Data Sheet**
|**Section**|**Change Summary**|
|---|---|
||•<br>Added new row for tICFG_PORand updated max and unit for tICFG, unit of tVMC, typ of<br>fMCLK_DEF, max value of tDONE_LOW, and data in the I2C/I3C section in Table 3.46.<br>•<br>Updated table note and data for tBTRFin Table 3.47.Table 3.39|
|DC and Switching Characteristics<br>for Automotive|•<br>Added Power Supply Ramp Rates (section 4.3) to Switching Test Conditions (section<br>4.29) to complete the CrossLink-NX Automotive data for production release.<br>•<br>Updated Table 4.2 to change tAUTOto tJAUTO.|
## **Revision 1.1, July 2021**
|**Section**|**Change Summary**|
|---|---|
|All|•<br>Corrected units and measurements across the document.<br>•<br>Minor formatting across the document.<br>•<br>Changed 17K and 39K to 17 k and 39 k across the document.|
|Architecture|•<br>Updated Programmable I/O (PIO) content to remove reference to CrossLink-NX<br>regarding PIC.<br>•<br>Updated Programmable I/O Cell (PIC) to provide additional information on PIC.<br>•<br>Updated Figure 2.17 and Figure 2.18.<br>•<br>Added Trace ID section.<br>•<br>Updated Cryptographic Engine content.|
|Introduction|Minor formattingin Features section.|
|DC and Switching Characteristics<br>for Commercial and Industrial|•<br>Updated note in Table 3.6 and Table 3.27.<br>•<br>Added note 3 in Table 3.14 and Table 3.15.<br>•<br>Added three rows for fSSC in Table 3.32.<br>•<br>Changed EBR Output Registers to Output Registers for 32k × 32 True-Dual Large<br>Memory Functions in Table 3.29.<br>•<br>Updated max value for tOPJIT Output Clock Phase Jitter and added rows for fSSC_MOD<br>in Table 3.32.<br>•<br>Updated Table 3.35 to fill upemptycells.|
|Pinout Summary|•<br>Updated table in Signal Descriptions to add PLLCK in PBxxx/LRC_GPLL, PBxxx/LLC_GPLL,<br>and PBxxx/ULC_GPLL.<br>•<br>Updated table in CrossLink-NX Family to re-arrange pinout package from lowest to<br>highest.|
|References|Added reference documents.|
## **Revision 1.0, April 2021**
|**Section**|**Change Summary**|
|---|---|
|All|Production release|
© 2021-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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www.latticesemi.com
Updated at April 17, 2026
Lattice Semiconductor is a premier developer of low-power, programmable design solutions, specializing in Field-Programmable Gate Arrays (FPGAs) and Programmable Logic Devices (PLDs). Recognized for driving innovation in cost-effective and power-efficient architectures, the company provides essential semiconductor components for consumer, mobile, and industrial design applications. Our selection of Lattice Semiconductor products is focused on their highly regarded FPGA integrated circuits. Devices from industry-leading families like the iCE40, MachXO, and LatticeECP series offer designers an exceptional combination of high system integration and industry-low power consumption. These FPGAs are engineered to handle complex tasks such as sensor management, custom connectivity, and advanced video processing while minimizing overall board footprint. To ensure seamless integration from concept to production, Lattice backs its hardware with a comprehensive support ecosystem. Engineers can accelerate their development cycles utilizing intuitive tools like the Lattice Diamond design software, paired with flexible IP cores and reference designs that reduce design risk and increase system reliability.
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