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LIFCL-33U-7CTG104I
FPGA, SRAM, 51 I/O's, 33 Logic Cells, 28nm, Surface Mount, FCCSP-104, CrossLink-NX-33 Series
⚠️ Reference pricing provided. In case of supply shortages, we will connect you with our trusted procurement partners to ensure your project's continuity.
- Manufacturer: LATTICE SEMICONDUCTOR
- Product type: FPGAs
- SVHC: No SVHC (25-Jun-2025)
- FPGA Type: SRAM based FPGA
- IC Mounting: Surface Mount
- No. of Pins: 104Pins
- Speed Grade: 7
- Product Range: CrossLink-NX-33 Series
- Qualification: -
- No.of User I/Os: 51I/O's
- IC Case / Package: FCCSP
- No. of Logic Cells: 33Logic Cells
- Process Technology: 28nm
- Operating Temperature Max: 100°C
- Operating Temperature Min: -40°C
| Delivery and price | |
|---|---|
| Units per pack | 25 |
| Price | 41.4 € |
| Current stock | 500+ |
| Lead time | 30 days |
Datasheet
## **CrossLink-NX-33 and CrossLinkU-NX**
## **Data Sheet**
FPGA-DS-02104-1.0
July 2024
**CrossLink-NX-33 and CrossLinkU-NX Data Sheet**
mLATTICE
## **Disclaimers**
Lattice makes no warranty, representation, or guarantee regarding the accuracy of information contained in this document or the suitability of its products for any particular purpose. All information herein is provided AS IS, with all faults, and all associated risk is the responsibility entirely of the Buyer. The information provided herein is for informational purposes only and may contain technical inaccuracies or omissions, and may be otherwise rendered inaccurate for many reasons, and Lattice assumes no obligation to update or otherwise correct or revise this information. Products sold by Lattice have been subject to limited testing and it is the Buyer's responsibility to independently determine the suitability of any products and to test and verify the same. LATTICE PRODUCTS AND SERVICES ARE NOT DESIGNED, MANUFACTURED, OR TESTED FOR USE IN LIFE OR SAFETY CRITICAL SYSTEMS, HAZARDOUS ENVIRONMENTS, OR ANY OTHER ENVIRONMENTS REQUIRING FAIL-SAFE PERFORMANCE, INCLUDING ANY APPLICATION IN WHICH THE FAILURE OF THE PRODUCT OR SERVICE COULD LEAD TO DEATH, PERSONAL INJURY, SEVERE PROPERTY DAMAGE OR ENVIRONMENTAL HARM (COLLECTIVELY, "HIGH-RISK USES"). FURTHER, BUYER MUST TAKE PRUDENT STEPS TO PROTECT AGAINST PRODUCT AND SERVICE FAILURES, INCLUDING PROVIDING APPROPRIATE REDUNDANCIES, FAIL-SAFE FEATURES, AND/OR SHUT-DOWN MECHANISMS. LATTICE EXPRESSLY DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY OF FITNESS OF THE PRODUCTS OR SERVICES FOR HIGH-RISK USES. The information provided in this document is proprietary to Lattice Semiconductor, and Lattice reserves the right to make any changes to the information in this document or to any products at any time without notice.
© 2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02104-1.0
2
**CrossLink-NX-33 and CrossLinkU-NX Data Sheet**
mLATTICE
## **Contents**
|**Contents**|**Contents**|**Contents**|
|---|---|---|
|Contents ................................................................................................................................................................................ 3|||
|Acronyms in This Document ................................................................................................................................................. 9|||
|1.|General Description .................................................................................................................................................... 10||
||1.1.|Features ............................................................................................................................................................. 10|
|2.|Architecture ................................................................................................................................................................ 13||
||2.1.|Overview ........................................................................................................................................................... 13|
||2.2.|PFU Blocks ......................................................................................................................................................... 16|
||2.2.1.|Slice ............................................................................................................................................................... 16|
||2.2.2.|Modes of Operation ..................................................................................................................................... 19|
||2.3.|Routing .............................................................................................................................................................. 20|
||2.4.|Clocking Structure ............................................................................................................................................. 20|
||2.4.1.|Global PLL ..................................................................................................................................................... 20|
||2.4.2.|Clock Distribution Network .......................................................................................................................... 21|
||2.4.3.|Primary Clocks .............................................................................................................................................. 22|
||2.4.4.|Edge Clock .................................................................................................................................................... 23|
||2.4.5.|Clock Dividers ............................................................................................................................................... 23|
||2.4.6.|Clock Center Multiplexer Blocks ................................................................................................................... 24|
||2.4.7.|Dynamic Clock Select .................................................................................................................................... 24|
||2.4.8.|Dynamic Clock Control ................................................................................................................................. 25|
||2.4.9.|DDRDLL ......................................................................................................................................................... 25|
||2.5.|sysMEM Memory .............................................................................................................................................. 27|
||2.5.1.|sysMEM Memory Block ................................................................................................................................ 27|
||2.5.2.|Bus Size Matching ......................................................................................................................................... 27|
||2.5.3.|RAM Initialization and ROM Operation ........................................................................................................ 27|
||2.5.4.|Memory Cascading ....................................................................................................................................... 27|
||2.5.5.|Single, Dual and Pseudo-Dual Port Modes ................................................................................................... 28|
||2.5.6.|Memory Output Reset .................................................................................................................................. 28|
||2.6.|Large RAM ......................................................................................................................................................... 28|
||2.7.|sysDSP ............................................................................................................................................................... 29|
||2.7.1.|sysDSP Approach Compared to General DSP ............................................................................................... 29|
||2.7.2.|sysDSP Architecture Features ....................................................................................................................... 30|
||2.8.|Programmable I/O (PIO) .................................................................................................................................... 32|
||2.9.|Programmable I/O Cell (PIC) ............................................................................................................................. 32|
||2.9.1.|Input Register Block ...................................................................................................................................... 33|
||2.9.2.|Output Register Block ................................................................................................................................... 35|
||2.10.|Tri-state Register Block ...................................................................................................................................... 36|
||2.11.|sysI/O Buffer ...................................................................................................................................................... 37|
||2.11.1. Supported sysI/O Standards ......................................................................................................................... 37||
||2.11.2. sysI/O Banking Scheme ................................................................................................................................ 39||
||2.11.3. sysI/O Buffer Configurations ........................................................................................................................ 40||
||2.12.|IEEE 1149.1-Compliant Boundary Scan Testability ............................................................................................ 40|
||2.13.|Always On (AON) ............................................................................................................................................... 40|
||2.14.|USB .................................................................................................................................................................... 41|
||2.14.1. USB Hardware Architecture ......................................................................................................................... 42||
||2.14.1.3.<br>Clock, Reset, Debug, and Power ............................................................................................................... 43||
||2.14.2. USB RISC-V Firmware Stack and Host Software Interface ............................................................................ 44||
||2.15.|Device Configuration ......................................................................................................................................... 45|
||2.15.1. Enhanced Configuration Options ................................................................................................................. 45||
||2.16.|Single Event Upset (SEU) Handling .................................................................................................................... 46|
||2.17.|On-Chip Oscillator ............................................................................................................................................. 46|
||2.18.|User I²C IP .......................................................................................................................................................... 46|
||2.19.|Trace ID ............................................................................................................................................................. 47|
© 2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02104-1.0
3
**CrossLink-NX-33 and CrossLinkU-NX Data Sheet**
mLATTICE
||2.20.|Cryptographic Engine ........................................................................................................................................ 47|
|---|---|---|
|3.|DC and Switching Characteristics for Commercial and Industrial ............................................................................... 48||
||3.1.|Absolute Maximum Ratings .............................................................................................................................. 48|
||3.2.|Recommended Operating Conditions1, 2, 3......................................................................................................... 49|
||3.3.|Power Supply Ramp Rates2............................................................................................................................... 50|
||3.4.|Power up Sequence ........................................................................................................................................... 50|
||3.5.|On-Chip Programmable Termination ................................................................................................................ 50|
||3.6.|Hot Socketing Specifications ............................................................................................................................. 51|
||3.7.|ESD Performance ............................................................................................................................................... 51|
||3.8.|DC Electrical Characteristics .............................................................................................................................. 52|
||3.9.|Supply Currents ................................................................................................................................................. 53|
||3.10.|sysI/O Recommended Operating Conditions .................................................................................................... 54|
||3.11.|sysI/O Single-Ended DC Electrical Characteristics3............................................................................................ 55|
||3.12.|sysI/O Differential DC Electrical Characteristics ................................................................................................ 57|
||3.12.1. LVDS .............................................................................................................................................................. 57||
||3.12.2. LVDS25E (Output Only) ................................................................................................................................. 58||
||3.12.3. SubLVDS (Input Only) ................................................................................................................................... 59||
||3.12.4. SubLVDSE/SubLVDSEH (Output Only) .......................................................................................................... 59||
||3.12.5. SLVS .............................................................................................................................................................. 60||
||3.12.6. Soft MIPI D-PHY ............................................................................................................................................ 61||
||3.12.7. Differential HSTL15D (Output Only) ............................................................................................................. 65||
||3.12.8. Differential LVCMOS25D, LVCMOS33D, LVTTL33D (Output Only) ............................................................... 65||
||3.13.|Maximum sysI/O Buffer Speed .......................................................................................................................... 66|
||3.14.|Typical Building Block Function Performance ................................................................................................... 67|
||3.15.|LMMI ................................................................................................................................................................. 68|
||3.16.|Derating Timing Tables ...................................................................................................................................... 69|
||3.17.|External Switching Characteristics .................................................................................................................... 69|
||3.18.|sysCLOCK PLL Timing (VCC= 1.0 V) ..................................................................................................................... 77|
||3.19.|Internal Oscillators Characteristics .................................................................................................................... 79|
||3.20.|User I2C Characteristics ..................................................................................................................................... 79|
||3.21.|sysCONFIG Port Timing Specifications ............................................................................................................... 79|
||3.22.|AON Block Specifications (VCCAUX_AON= 1.8V) ..................................................................................................... 85|
||3.23.|Hardened USB Specifications ............................................................................................................................ 86|
||3.24.|JTAG Port Timing Specifications ........................................................................................................................ 86|
||3.25.|Switching Test Conditions ................................................................................................................................. 87|
|4.|Pinout Information ..................................................................................................................................................... 89||
||4.1.|Signal Descriptions ............................................................................................................................................ 89|
||4.2.|Pin Information Summary ................................................................................................................................. 94|
|5.|Ordering Information .................................................................................................................................................. 96||
||5.1.|Part Number Description................................................................................................................................... 96|
||5.2.|Ordering Part Numbers ..................................................................................................................................... 96|
||5.2.1.|Commercial ................................................................................................................................................... 96|
||5.2.2.|Industrial ....................................................................................................................................................... 96|
|References .......................................................................................................................................................................... 97|||
|Technical Support Assistance ............................................................................................................................................. 98|||
|Revision History .................................................................................................................................................................. 99|||
© 2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02104-1.0
4
**CrossLink-NX-33 and CrossLinkU-NX Data Sheet**
mLATTICE
## **Figures**
|Figure 2.1. LIFCL-33 Simplified Block Diagram ........................................................................................................................... 14|Figure 2.1. LIFCL-33 Simplified Block Diagram ........................................................................................................................... 14|
|---|---|
|Figure 2.2. LIFCL-33U Simplified Block Diagram ........................................................................................................................ 15|Figure 2.2. LIFCL-33U Simplified Block Diagram ........................................................................................................................ 15|
|Figure 2.3. PFU Diagram ............................................................................................................................................................ 16|Figure 2.3. PFU Diagram ............................................................................................................................................................ 16|
|Figure 2.4. Slice Diagram ........................................................................................................................................................... 17|Figure 2.4. Slice Diagram ........................................................................................................................................................... 17|
|Figure 2.5. Slice Configuration for LUT4 and LUT5 .................................................................................................................... 18|Figure 2.5. Slice Configuration for LUT4 and LUT5 .................................................................................................................... 18|
|Figure 2.6. General Purpose PLL Diagram .................................................................................................................................. 21|Figure 2.6. General Purpose PLL Diagram .................................................................................................................................. 21|
|Figure 2.7. Clocking .................................................................................................................................................................... 22|Figure 2.7. Clocking .................................................................................................................................................................... 22|
|Figure 2.8. Edge Clock Sources per Bank ................................................................................................................................... 23|Figure 2.8. Edge Clock Sources per Bank ................................................................................................................................... 23|
|Figure 2.9. DCS_CMUX Diagram ................................................................................................................................................ 24|Figure 2.9. DCS_CMUX Diagram ................................................................................................................................................ 24|
|Figure 2.10. DCS Waveforms ..................................................................................................................................................... 25|Figure 2.10. DCS Waveforms ..................................................................................................................................................... 25|
|Figure 2.11. DLLDEL Functional Diagram ................................................................................................................................... 26|Figure 2.11. DLLDEL Functional Diagram ................................................................................................................................... 26|
|Figure 2.12. DDRDLL Architecture ............................................................................................................................................. 26|Figure 2.12. DDRDLL Architecture ............................................................................................................................................. 26|
|Figure 2.13. Memory Core Reset ............................................................................................................................................... 28|Figure 2.13. Memory Core Reset ............................................................................................................................................... 28|
|Figure 2.14. Comparison of General DSP, LIFCL-33, and LIFCL-33U Approaches ...................................................................... 29|Figure 2.14. Comparison of General DSP, LIFCL-33, and LIFCL-33U Approaches ...................................................................... 29|
|Figure 2.15. DSP Functional Block Diagram ............................................................................................................................... 31|Figure 2.15. DSP Functional Block Diagram ............................................................................................................................... 31|
|Figure 2.16. Group of Two High Performance Programmable I/O Cells .................................................................................... 32|Figure 2.16. Group of Two High Performance Programmable I/O Cells .................................................................................... 32|
|Figure 2.17. Wide Range Programmable I/O Cells ..................................................................................................................... 33|Figure 2.17. Wide Range Programmable I/O Cells ..................................................................................................................... 33|
|Figure 2.18. Input Register Block for PIO on Top Side of the Device ......................................................................................... 34|Figure 2.18. Input Register Block for PIO on Top Side of the Device ......................................................................................... 34|
|Figure 2.19. Input Register Block for PIO on Bottom Side of the Device ................................................................................... 34|Figure 2.19. Input Register Block for PIO on Bottom Side of the Device ................................................................................... 34|
|Figure 2.20. Output Register Block on Top Side ........................................................................................................................ 35|Figure 2.20. Output Register Block on Top Side ........................................................................................................................ 35|
|Figure 2.21. Output Register Block on Bottom Side .................................................................................................................. 35|Figure 2.21. Output Register Block on Bottom Side .................................................................................................................. 35|
|Figure 2.22. Tri-state Register Block on Top Side ...................................................................................................................... 36|Figure 2.22. Tri-state Register Block on Top Side ...................................................................................................................... 36|
|Figure 2.23. Tri-state Register Block on Bottom Side ................................................................................................................ 36|Figure 2.23. Tri-state Register Block on Bottom Side ................................................................................................................ 36|
|Figure 2.24. AON Functional Block Diagram .............................................................................................................................. 41|Figure 2.24. AON Functional Block Diagram .............................................................................................................................. 41|
|Figure 2.25. USB Hard IP Functional Block Diagram .................................................................................................................. 42|Figure 2.25. USB Hard IP Functional Block Diagram .................................................................................................................. 42|
|Figure 2.26. Typical USB Hardware Application Diagram .......................................................................................................... 42|Figure 2.26. Typical USB Hardware Application Diagram .......................................................................................................... 42|
|Figure 2.27. LIFCL-33U USB RISC-V Host FW Stack .................................................................................................................... 44|Figure 2.27. LIFCL-33U USB RISC-V Host FW Stack .................................................................................................................... 44|
|Figure 2.28. Cryptographic Engine Block Diagram ..................................................................................................................... 47|Figure 2.28. Cryptographic Engine Block Diagram ..................................................................................................................... 47|
|Figure 3.1. On-Chip Termination ............................................................................................................................................... 50|Figure 3.1. On-Chip Termination ............................................................................................................................................... 50|
|Figure 3.2. LVDS25E Output Termination Example ................................................................................................................... 58|Figure 3.2. LVDS25E Output Termination Example ................................................................................................................... 58|
|Figure 3.3. SubLVDS Input Interface .......................................................................................................................................... 59|Figure 3.3. SubLVDS Input Interface .......................................................................................................................................... 59|
|Figure 3.4. SubLVDS Output Interface ....................................................................................................................................... 60|Figure 3.4. SubLVDS Output Interface ....................................................................................................................................... 60|
|Figure 3.5. SLVS Interface .......................................................................................................................................................... 61|Figure 3.5. SLVS Interface .......................................................................................................................................................... 61|
|Figure 3.6. MIPI Interface .......................................................................................................................................................... 62|Figure 3.6. MIPI Interface .......................................................................................................................................................... 62|
|Figure 3.7. Receiver RX.CLK.Centered Waveforms .................................................................................................................... 74|Figure 3.7. Receiver RX.CLK.Centered Waveforms .................................................................................................................... 74|
|Figure 3.8. Receiver RX.CLK.Aligned and DDR Memory Input Waveforms ................................................................................ 74|Figure 3.8. Receiver RX.CLK.Aligned and DDR Memory Input Waveforms ................................................................................ 74|
|Figure 3.9. Transmit TX.CLK.Centered and DDR Memory Output Waveforms .......................................................................... 75|Figure 3.9. Transmit TX.CLK.Centered and DDR Memory Output Waveforms .......................................................................... 75|
|Figure 3.10. Transmit TX.CLK.Aligned Waveforms ..................................................................................................................... 75|Figure 3.10. Transmit TX.CLK.Aligned Waveforms ..................................................................................................................... 75|
|Figure 3.11. DDRX71 Video Timing Waveforms ......................................................................................................................... 76|Figure 3.11. DDRX71 Video Timing Waveforms ......................................................................................................................... 76|
|Figure 3.12. Receiver DDRX71_RX Waveforms .......................................................................................................................... 76|Figure 3.12. Receiver DDRX71_RX Waveforms .......................................................................................................................... 76|
|Figure 3.13. Transmitter DDRX71_TX Waveforms ..................................................................................................................... 77|Figure 3.13. Transmitter DDRX71_TX Waveforms ..................................................................................................................... 77|
|Figure 3.14. Master SPI POR/REFRESH Timing ........................................................................................................................... 81|Figure 3.14. Master SPI POR/REFRESH Timing ........................................................................................................................... 81|
|Figure 3.15. Slave SPI/I|Figure 3.15. Slave SPI/I2C/I3C POR/REFRESH Timing ................................................................................................................. 82|
|Figure 3.16. Master SPI PROGRAMN Timing .............................................................................................................................. 82|Figure 3.16. Master SPI PROGRAMN Timing .............................................................................................................................. 82|
|Figure 3.17. Slave SPI/I|Figure 3.17. Slave SPI/I2C/I3C PROGRAMN Timing .................................................................................................................... 83|
|Figure 3.18. Master SPI Configuration Timing ........................................................................................................................... 83|Figure 3.18. Master SPI Configuration Timing ........................................................................................................................... 83|
|Figure 3.19. Slave SPI Configuration Timing .............................................................................................................................. 84|Figure 3.19. Slave SPI Configuration Timing .............................................................................................................................. 84|
|Figure 3.20. I|Figure 3.20. I2C /I3C Configuration Timing ................................................................................................................................. 84|
|Figure 3.21. Master SPI Wake-Up Timing .................................................................................................................................. 84|Figure 3.21. Master SPI Wake-Up Timing .................................................................................................................................. 84|
|Figure 3.22. Slave SPI/I|Figure 3.22. Slave SPI/I2C/I3C Wake-Up Timing ......................................................................................................................... 85|
|Figure 3.23. Configuration Error Notification ............................................................................................................................ 85|Figure 3.23. Configuration Error Notification ............................................................................................................................ 85|
|Figure 3.24. JTAG Port Timing Waveforms ................................................................................................................................ 87|Figure 3.24. JTAG Port Timing Waveforms ................................................................................................................................ 87|
© 2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02104-1.0
5
**CrossLink-NX-33 and CrossLinkU-NX Data Sheet**
mLATTICE
Figure 3.25. Output Test Load, LVTTL, and LVCMOS Standards ................................................................................................ 88
© 2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02104-1.0
6
**CrossLink-NX-33 and CrossLinkU-NX Data Sheet**
mLATTICE
## **Tables**
|Table 1.1. LIFCL-33/33U Key Features ....................................................................................................................................... 10|Table 1.1. LIFCL-33/33U Key Features ....................................................................................................................................... 10|
|---|---|
|Table 1.2. LIFCL-33/33U Commercial/Industrial Family Selection Guide .................................................................................. 12|Table 1.2. LIFCL-33/33U Commercial/Industrial Family Selection Guide .................................................................................. 12|
|Table 2.1. Resources and Modes Available per Slice ................................................................................................................. 16|Table 2.1. Resources and Modes Available per Slice ................................................................................................................. 16|
|Table 2.2. Slice Signal Descriptions ............................................................................................................................................ 18|Table 2.2. Slice Signal Descriptions ............................................................................................................................................ 18|
|Table 2.3. Number of Slices Required to Implement Distributed RAM ..................................................................................... 19|Table 2.3. Number of Slices Required to Implement Distributed RAM ..................................................................................... 19|
|Table 2.4. sysMEM Block Configurations ................................................................................................................................... 27|Table 2.4. sysMEM Block Configurations ................................................................................................................................... 27|
|Table 2.5. Maximum Number of Elements in a sysDSP Block .................................................................................................... 31|Table 2.5. Maximum Number of Elements in a sysDSP Block .................................................................................................... 31|
|Table 2.6. Input Block Port Description ..................................................................................................................................... 34|Table 2.6. Input Block Port Description ..................................................................................................................................... 34|
|Table 2.7. Output Block Port Description .................................................................................................................................. 36|Table 2.7. Output Block Port Description .................................................................................................................................. 36|
|Table 2.8. Tri-state Block Port Description ................................................................................................................................ 37|Table 2.8. Tri-state Block Port Description ................................................................................................................................ 37|
|Table 2.9. Single-Ended I/O Standards ...................................................................................................................................... 38|Table 2.9. Single-Ended I/O Standards ...................................................................................................................................... 38|
|Table 2.10. Differential I/O Standards ....................................................................................................................................... 38|Table 2.10. Differential I/O Standards ....................................................................................................................................... 38|
|Table 2.11. Single-Ended I/O Standards Supported on Various Sides ....................................................................................... 39|Table 2.11. Single-Ended I/O Standards Supported on Various Sides ....................................................................................... 39|
|Table 2.12. Differential I/O Standards Supported on Various Sides .......................................................................................... 40|Table 2.12. Differential I/O Standards Supported on Various Sides .......................................................................................... 40|
|Table 2.13. AON Port Description .............................................................................................................................................. 41|Table 2.13. AON Port Description .............................................................................................................................................. 41|
|Table 2.14. USB Endpoint FIFO Size and Burst Size (Maximum Packet Size) ............................................................................. 43|Table 2.14. USB Endpoint FIFO Size and Burst Size (Maximum Packet Size) ............................................................................. 43|
|Table 3.1. Absolute Maximum Ratings ...................................................................................................................................... 48|Table 3.1. Absolute Maximum Ratings ...................................................................................................................................... 48|
|Table 3.2. Recommended Operating Conditions ....................................................................................................................... 49|Table 3.2. Recommended Operating Conditions ....................................................................................................................... 49|
|Table 3.3. Power Supply Ramp Rates ........................................................................................................................................ 50|Table 3.3. Power Supply Ramp Rates ........................................................................................................................................ 50|
|Table 3.4. Power-On Reset ........................................................................................................................................................ 50|Table 3.4. Power-On Reset ........................................................................................................................................................ 50|
|Table 3.5. On-Chip Termination Options for Input Modes ........................................................................................................ 51|Table 3.5. On-Chip Termination Options for Input Modes ........................................................................................................ 51|
|Table 3.6. Hot Socketing Specifications for GPIO ...................................................................................................................... 51|Table 3.6. Hot Socketing Specifications for GPIO ...................................................................................................................... 51|
|Table 3.7. DC Electrical Characteristics – Wide Range ............................................................................................................... 52|Table 3.7. DC Electrical Characteristics – Wide Range ............................................................................................................... 52|
|Table 3.8. DC Electrical Characteristics – High Speed ................................................................................................................ 52|Table 3.8. DC Electrical Characteristics – High Speed ................................................................................................................ 52|
|Table 3.9. Capacitors – Wide Range .......................................................................................................................................... 52|Table 3.9. Capacitors – Wide Range .......................................................................................................................................... 52|
|Table 3.10. Capacitors – High Performance ............................................................................................................................... 53|Table 3.10. Capacitors – High Performance ............................................................................................................................... 53|
|Table 3.11. Single Ended Input Hysteresis – Wide Range .......................................................................................................... 53|Table 3.11. Single Ended Input Hysteresis – Wide Range .......................................................................................................... 53|
|Table 3.12. Single Ended Input Hysteresis – High Performance ................................................................................................ 53|Table 3.12. Single Ended Input Hysteresis – High Performance ................................................................................................ 53|
|Table 3.13. sysI/O Recommended Operating Conditions .......................................................................................................... 54|Table 3.13. sysI/O Recommended Operating Conditions .......................................................................................................... 54|
|Table 3.14. sysI/O DC Electrical Characteristics – Wide Range I/O ............................................................................................ 55|Table 3.14. sysI/O DC Electrical Characteristics – Wide Range I/O ............................................................................................ 55|
|Table 3.15. sysI/O DC Electrical Characteristics – High Performance I/O|Table 3.15. sysI/O DC Electrical Characteristics – High Performance I/O3................................................................................. 56|
|Table 3.16. I/O Resistance Characteristics ................................................................................................................................. 56|Table 3.16. I/O Resistance Characteristics ................................................................................................................................. 56|
|Table 3.17. V|Table 3.17. VINMaximum Overshoot/Undershoot Allowance – Wide Range1, 2........................................................................ 57|
|Table 3.18. V|Table 3.18. VINMaximum Overshoot/Undershoot Allowance – High Performance1, 2.............................................................. 57|
|Table 3.19. LVDS DC Electrical Characteristics|Table 3.19. LVDS DC Electrical Characteristics1......................................................................................................................... 57|
|Table 3.20. LVDS25E DC Conditions ........................................................................................................................................... 58|Table 3.20. LVDS25E DC Conditions ........................................................................................................................................... 58|
|Table 3.21. SubLVDS Input DC Electrical Characteristics (Over Recommended Operating Conditions) .................................... 59|Table 3.21. SubLVDS Input DC Electrical Characteristics (Over Recommended Operating Conditions) .................................... 59|
|Table 3.22. SubLVDS Output DC Electrical Characteristics ........................................................................................................ 59|Table 3.22. SubLVDS Output DC Electrical Characteristics ........................................................................................................ 59|
|Table 3.23. SLVS Input DC Characteristics ................................................................................................................................. 60|Table 3.23. SLVS Input DC Characteristics ................................................................................................................................. 60|
|Table 3.24. SLVS Output DC Characteristics .............................................................................................................................. 60|Table 3.24. SLVS Output DC Characteristics .............................................................................................................................. 60|
|Table 3.25. Soft D-PHY Input Timing and Levels ........................................................................................................................ 63|Table 3.25. Soft D-PHY Input Timing and Levels ........................................................................................................................ 63|
|Table 3.26. Soft D-PHY Output Timing and Levels ..................................................................................................................... 64|Table 3.26. Soft D-PHY Output Timing and Levels ..................................................................................................................... 64|
|Table 3.27. Soft D-PHY Clock Signal Specification ...................................................................................................................... 64|Table 3.27. Soft D-PHY Clock Signal Specification ...................................................................................................................... 64|
|Table 3.28. Soft D-PHY Data-Clock Timing Specifications .......................................................................................................... 65|Table 3.28. Soft D-PHY Data-Clock Timing Specifications .......................................................................................................... 65|
|Table 3.29. Maximum I/O Buffer Speed|Table 3.29. Maximum I/O Buffer Speed1, 2, 3, 4, 7......................................................................................................................... 66|
|Table 3.30. Pin-to-Pin Performance ........................................................................................................................................... 67|Table 3.30. Pin-to-Pin Performance ........................................................................................................................................... 67|
|Table 3.31. Register-to-Register Performance|Table 3.31. Register-to-Register Performance1, 3, 4.................................................................................................................... 68|
|Table 3.32. LMMI F|Table 3.32. LMMI FMAXSummary ............................................................................................................................................... 68|
|Table 3.33. External Switching Characteristics (V|Table 3.33. External Switching Characteristics (VCC= 1.0 V) ...................................................................................................... 69|
|Table 3.34. sysCLOCK PLL Timing (V|Table 3.34. sysCLOCK PLL Timing (VCC= 1.0 V) ........................................................................................................................... 77|
|Table 3.35. Internal Oscillators (V|Table 3.35. Internal Oscillators (VCC= 1.0 V) .............................................................................................................................. 79|
|Table 3.36. User I|Table 3.36. User I2C Specifications (VCC= 1.0 V) ......................................................................................................................... 79|
© 2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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**CrossLink-NX-33 and CrossLinkU-NX Data Sheet**
mLATTICE
|Table 3.37. sysCONFIG Port Timing Specifications .................................................................................................................... 79|Table 3.37. sysCONFIG Port Timing Specifications .................................................................................................................... 79|
|---|---|
|Table 3.38. AON Block Specification (V|Table 3.38. AON Block Specification (VCCAUX_AON= 1.8 V) ........................................................................................................... 85|
|Table 3.39. Hardened USB2 Specifications ................................................................................................................................ 86|Table 3.39. Hardened USB2 Specifications ................................................................................................................................ 86|
|Table 3.40. Hardened USB3 Specifications ................................................................................................................................ 86|Table 3.40. Hardened USB3 Specifications ................................................................................................................................ 86|
|Table 3.41. JTAG Port Timing Specifications .............................................................................................................................. 86|Table 3.41. JTAG Port Timing Specifications .............................................................................................................................. 86|
|Table 3.42. Test Fixture Required Components, Non-Terminated Interfaces ........................................................................... 88|Table 3.42. Test Fixture Required Components, Non-Terminated Interfaces ........................................................................... 88|
© 2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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**CrossLink-NX-33 and CrossLinkU-NX Data Sheet**
mLATTICE
## **Acronyms in This Document**
A list of acronyms used in this document.
|**Acronym **<br>~~a~~|**Definition**|
|---|---|
|AON<br>~~a~~|Always On|
|CDR<br>~~a~~|Clock and Data Recovery|
|CRC<br>~~a~~|Cycle RedundancyCode|
|DCC<br>~~a~~<br>~~a~~|Dynamic Clock Control|
|DCS<br>~~a~~|Dynamic Clock Select|
|DDR<br>~~a~~|Double Data Rate|
|DLL<br>~~a~~|DelayLocked Loop|
|DSP<br>~~a~~|Digital Signal Processing|
|EBR<br>~~a~~<br>~~a~~|Embedded Block RAM|
|ECC<br>~~a~~<br>~~a~~|Error Correction Coding|
|ECLK<br>~~a~~|Edge Clock|
|FFT<br>~~a~~|Fast Fourier Transform|
|FIFO<br>~~a~~|First In First Out|
|FIR<br>~~a~~|Finite Impulse Response|
|GPIO<br>~~a~~<br>~~a~~|General Purpose Input/Output|
|LC<br>~~a~~|Logic Cell|
|LRAM<br>~~a~~|Large RAM|
|LVCMOS<br>~~a~~|Low-Voltage ComplementaryMetal Oxide Semiconductor|
|LVDS<br>~~a~~|Low-Voltage Differential Signaling|
|LVPECL<br>~~a~~<br>~~a~~|Low Voltage Positive Emitter Coupled Logic|
|LVTTL<br>~~a~~|Low Voltage Transistor-Transistor Logic|
|LUT<br>~~a~~|Look UpTable|
|MPS|Maximum Packet Size|
|PCI<br>~~a~~|Peripheral Component Interconnect|
|PCLK<br>~~a~~<br>~~a~~|PrimaryClock|
|PDPR<br>~~a~~|Pseudo Dual Port RAM|
|PFU<br>~~a~~|Programmable Functional Unit|
|PIC<br>~~a~~|Programmable I/O Cells|
|PIPE<br>~~a~~<br>~~a~~|PHY Interface for PCI Express|
|PLL<br>~~a~~<br>~~a~~<br>~~a~~|Phase Locked Loop|
|POR<br>~~a~~|Power On Reset|
|SER<br>~~a~~<br>~~a~~|Soft Error Rate|
|SEU<br>~~a~~|Single Event Upset|
|SLVS<br>~~a~~<br>~~a~~|Scalable Low-Voltage Signaling|
|SPI<br>~~a~~<br>~~a~~|Serial Peripheral Interface|
|SPR<br>~~a~~<br>~~a~~|Single Port RAM|
|SRAM<br>~~a~~|Static Random-Access Memory|
|TAP<br>~~a~~|Test Access Port|
|TDM<br>~~a~~<br>~~a~~|Time Division Multiplexing|
|USB<br>~~a~~<br>~~a~~|Universal Serial Bus|
© 2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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**CrossLink-NX-33 and CrossLinkU-NX Data Sheet**
mLATTICE
## **1. General Description**
The CrossLink™-NX-33 and CrossLinkU™-NX devices (hereafter referred to as LIFCL-33 and LIFCL-33U respectively) can be used in a wide range of applications and are optimized for bridging and processing needs in Embedded Vision applications – supporting a variety of high bandwidth sensor and display interfaces, video processing and machine learning inferencing. It is built on the Lattice Nexus FPGA platform, using low-power 28 nm FD-SOI technology. It combines the extreme flexibility of an FPGA with the low power and high reliability (due to extremely low SER) of FD-SOI technology and offers small footprint package options.
LIFCL-33/33U devices support a variety of interfaces including MIPI D-PHY (CSI-2, DSI), LVDS, SLVS, subLVDS, and more. USB 2.0 and USB 3.2 Gen 1 are only supported in LIFCL-33U.
The processing features of the LIFCL-33U include up to 33k Logic Cells, sixty-four 18 × 18 multipliers, and 3.6 Mb of embedded memory (consisting of EBR and LRAM blocks), and distributed memory.
LIFCL-33/33U devices support fast configuration of its reconfigurable SRAM-based logic fabric. Security features to secure user designs include bitstream encryption and password protection. In addition to the high reliability inherent to FD-SOI technology (due to its extremely low SER), active reliability feature such as built-in frame-based SED/SEC (for SRAM-based logic fabric) is also supported.
Lattice Radiant™ design software allows large complex user designs to be efficiently implemented in LIFCL-33U device. Synthesis library support for the device is available for popular logic synthesis tools. Radiant tools use the synthesis tool output along with constraints from its floor planning tools to place and route the user design. The tools extract timing from the routing and back-annotate it into the design for timing verification.
Lattice provides many pre-engineered IP (Intellectual Property) modules. By using these configurable soft IP cores as standardized blocks, users are free to concentrate on the unique aspects of the design, increasing productivity.
## **1.1. Features**
Table 1.1 shows the key features of LIFCL-33/33U devices. Always On (AON), USB 2.0 and USB 3.2 Gen 1 are only supported in LIFCL-33U.
**Table 1.1. LIFCL-33/33U Key Features**
|**Programmable Architecture**|**MIPI D-PHY**|
|---|---|
|•<br>33k logic cells<br>•<br>64 multipliers (18 × 18 in sysDSP™ blocks)<br>•<br>3.6 Mb of embedded memory (EBR, LRAM)<br>•<br>60 programmable sysI/O<br>(High Performance and Wide Range I/O)|•<br>Soft D-PHY interfaces supported by High Performance (HP)<br>sysI/O<br>•<br>Transmit or receive<br>•<br>Supports CSI-2, DSI<br>•<br>Upto 1.2 Gbpsper lane|
|**Programmable sysI/O Supports Wide Variety of Interfaces**|**Cryptographic Engine**|
|•<br>High Performance (HP) on bottom I/O<br>dual rank<br>•<br>Supports up to 1.8 V VCCIO<br>•<br>Mixed voltage support (1.0 V, 1.2 V, 1.5 V, 1.8 V)<br>•<br>High-speed differential up to 1.2 Gbps<br>•<br>Supports soft D-PHY (Tx/Rx), LVDS 7:1 (Tx/Rx), SLVS<br>(Tx/Rx), subLVDS (Rx)<br>•<br>Wide Range (WR) on Top<br>I/O Banks<br>•<br>Supports up to 3.3 V VCCIO<br>•<br>Mixed voltage support (1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.3 V)<br>•<br>Programmable slew rate (slow, med, fast)<br>•<br>Controlled impedance mode<br>•<br>Emulated LVDS support<br>•<br>Hot SocketingSupport|•<br>Bitstream encryption – using AES-256<br>•<br>Bitstream authentication – using ECDSA<br>•<br>Hashing algorithms – SHA, HMAC<br>•<br>True Random Number Generator<br>•<br>AES 128/256 Encryption|
© 2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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**CrossLink-NX-33 and CrossLinkU-NX Data Sheet**
mLATTICE
|**sysDSP Enhanced DSP blocks**|**Single Event Upset (SEU) Mitigation Support**|
|---|---|
|•<br>Hardened pre-adder<br>•<br>Dynamic Shift for AI/ML support<br>•<br>Four 18 × 18, eight 9 × 9, two 18 × 36, or 36 × 36 multipliers<br>•<br>Advanced 18 × 36, two 18 × 18, or four 8 × 8 MAC|•<br>Extremely low Soft Error Rate (SER) due to FD-SOI technology<br>•<br>Soft Error Detect – Embedded hard macro<br>•<br>Soft Error Correction – Without stopping user operation<br>•<br>Soft Error Injection – Emulate SEU event to debug system<br>error handling|
|**sysCLOCK™ Analog PLL**|**Power Modes – Low Power versus High-Performance**|
|•<br>Six outputs per PLL<br>•<br>Fractional N<br>•<br>Programmable and dynamic phase control|•<br>User-selectable<br>•<br>Low-Power mode for power and/or thermal challenges<br>•<br>High-Performance mode for faster processing|
|**Flexible Memory Resources**|**Configuration – Fast, Secure**|
|•<br>Up to 1.1 Mb sysMEM™ Embedded Block RAM (EBR)<br>•<br>Programmable width<br>•<br>Single or dual clock FIFO<br>•<br>220k bits distributed RAM<br>•<br>Large RAM Blocks<br>•<br>0.5 Mbits per block<br>•<br>Upto five blocks(2.5 Mb total) per device|•<br>SPI – x1, x2, x4 up to 150 MHz<br>•<br>Master and Slave SPI support<br>•<br>JTAG<br>•<br>I2C and I3C<br>•<br>Bitstream Security<br>•<br>Encryption<br>•<br>Authentication|
|**Internal Bus Interface Support**|**USB 2.0/USB 3.2 Gen 1 PHY and USB 3.2 Gen 1 Controller**<br>**(LIFCL-33U)**|
|•<br>APB control bus<br>•<br>AHB-Lite for data bus<br>•<br>AXIprotocol|•<br>USB 3.2 Gen 1 at 5 Gbps x1 (-9 speed grade only)<br>•<br>USB 3.2 Gen 1 PHY and Controller (-9 speed grade only)<br>•<br>USB 2.0 PHY and Controller(All speedgrades)|
|**System Level Support**|**Always On (AON) Support for Low Power Applications**|
|•<br>IEEE 1149.1 and IEEE 1532 compliant<br>•<br>Reveal Logic Analyzer<br>•<br>On-chip oscillator for initialization and general use<br>•<br>1.0 V corepower supply|•<br>AON timer and power management<br>•<br>Supports lowest FPGA power for AON applications<br>•<br>Typical standby power <70 uA|
|**Small Footprint Package Options**||
|•<br>3.1 × 7.3 mm package options||
© 2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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**CrossLink-NX-33 and CrossLinkU-NX Data Sheet**
mLATTICE
**Table 1.2. LIFCL-33/33U Commercial/Industrial Family Selection Guide**
|**Device**|**LIFCL-33**|**LIFCL-33U**|
|---|---|---|
|Logic Cells¹<br>~~a~~|33k<br>~~a~~|33k<br>~~a~~|
|Embedded Memory (EBR)Blocks(18 kb)<br>~~a~~|64<br>~~a~~|64<br>~~a~~|
|Embedded Memory (EBR)Bits(kb)<br>~~a~~|1,152<br>~~a~~|1,152<br>~~a~~|
|Distributed RAM Bits(kb)<br>~~a~~|220<br>~~a~~|220<br>~~a~~|
|Large Memory (LRAM)Blocks<br>~~a~~<br>~~a~~|5<br>~~a~~<br>~~a~~|5<br>~~a~~<br>~~a~~|
|Large Memory (LRAM)Bits(kb) (512 kbits each)<br>~~a~~|2560<br>~~a~~|2560<br>~~a~~|
|18 × 18 Multipliers<br>~~a~~|64<br>~~a~~|64<br>~~a~~|
|450 MHz High FrequencyOscillator<br>~~a~~|1<br>~~a~~|1<br>~~a~~|
|128 kHz Low Power Oscillator<br>~~a~~|1<br>~~a~~|1<br>~~a~~|
|GPLL2<br>~~a~~<br>~~a~~|1<br>~~a~~<br>~~a~~|1<br>~~a~~<br>~~a~~|
|Always On(AON)Block<br>~~a~~|—<br>~~a~~|1<br>~~a~~|
|USB 2.0/USB 3.2 Gen 1 Interface3<br>~~a~~|—<br>~~a~~|1/1<br>~~a~~|
|**Packages(Size, Ball Pitch)**<br>~~CO~~|**Total I/O(Wide Range, High Performance)**<br>~~CO~~||
|84 WLCSP(3.1 mm × 7.3 mm, 0.5 mm)<br>~~a~~|60(34, 26)|44(17, 27)|
|104 FCCSP(5.5 mm x 8.5 mm, 0.65 mm)<br>~~a~~<br>~~a~~|—|52(20, 32)|
## **Notes:**
1. Logic Cells = LUTs × 1.2 effectiveness.
2. GPLL is only supported in 104 package of LIFCL-33U.
3. USB 3.2 Gen 1 is supported by -9 speed grade only.
© 2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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**CrossLink-NX-33 and CrossLinkU-NX Data Sheet**
mLATTICE
## **2. Architecture**
## **2.1. Overview**
Each LIFCL-33/33U device contains an array of logic blocks surrounded by Programmable I/O Cells (PIC). Interspersed between the rows of logic blocks are rows of sysMEM Embedded Block RAM (EBR) and rows of sysDSP Digital Signal Processing blocks, as shown in Figure 2.1 and Figure 2.2. The sysMEM EBR blocks are large, dedicated 18 kb fast memory blocks and have FIFO support. Each sysMEM block can be configured to a single, pseudo dual or true dual port memory in a variety of depths and widths as RAM or ROM. Each DSP block supports a variety of multiplier and adder configurations with one 108-bit or two 54-bit accumulators supported, which are the building blocks for complex signal processing capabilities.
Each PIC block encompasses two PIO (PIO pairs) with their respective sysI/O buffers. The sysI/O buffers of the LIFCL-33/33U devices are arranged in seven banks allowing the implementation of a wide variety of I/O standards. The Wide Range (WR) I/O banks that are located on the top side of the device provide flexible ranges of general purpose I/O configurations up to 3.3 V VCCIOs. The banks located on the bottom side of the device are dedicated to High Performance (HP) interfaces such as LVDS, MIPI supporting up to 1.8 V VCCIOs.
The Programmable Functional Unit (PFU) contains the building blocks for logic, arithmetic, RAM and ROM functions. The PFU block is optimized for flexibility, allowing complex designs to be implemented quickly and efficiently. Logic Blocks are arranged in a two-dimensional array. The registers in the PFU and sysI/O blocks in LIFCL-33/33U devices can be configured to be SET or RESET. After power up and configuration, it enters into user mode with these registers SET/RESET according to the user design, allowing the device to power up in a known state for predictable system function.
LIFCL-33U features like USB 3.2 Gen 1 and AON supports better system integration for host communications and low power applications.
LIFCL-33/33U devices also provide security features to help protect user designs and deliver more robust reliability by offering enhanced frame-based SED/SEC functions.
Other blocks provided include PLLs, DLLs, and configuration functions. The PLL and DLL blocks are located at the corners of each device. LIFCL-33/33U devices also include Lattice Memory Mapped Interface (LMMI) which is a Lattice standard to support simple read and write operations to control internal IP.
Every device in the family has a JTAG port. This family also provides an on-chip oscillator and soft error detect capability. The LIFCL-33/33U devices use 1.0 V as their core voltage.
© 2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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**CrossLink-NX-33 and CrossLinkU-NX Data Sheet**
**==> picture [420 x 304] intentionally omitted <==**
**----- Start of picture text -----**<br>
I/O Bank (Bank 5) I/O Bank (Bank 0) I/O Bank (Bank 1)<br>OSC Configuration & Security<br>Large<br>RAM0<br>Large<br>RAM1<br>><br>Large<br>RAM2<br>iseaszsitarass<br>a<br>Large<br>RAM3<br>Large<br>RAM4<br>iSnEnESESE ESTSES,<br>PLL I/O Bank (Bank 4) I/O Bank (Bank 3) I/O Bank (Bank 2)<br>**----- End of picture text -----**<br>
**Figure 2.1. LIFCL-33 Simplified Block Diagram**
© 2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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**CrossLink-NX-33 and CrossLinkU-NX Data Sheet**
USB3 I/O Bank (Bank 0) I/O Bank (Bank 1) OSC Configuration and Security AON Large RAM0 Large RAM1 ~~a~~ Large RAM2 ~~Siniinital~~ Large RAM3 Large RAM4 ~~erereare: reves,~~ PLL I/O Bank (Bank 4) I/O Bank (Bank 3) I/O Bank (Bank 2)
**Figure 2.2. LIFCL-33U Simplified Block Diagram**
© 2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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**CrossLink-NX-33 and CrossLinkU-NX Data Sheet**
## **2.2. PFU Blocks**
The core of the LIFCL-33/33U devices consist of PFU blocks. Each PFU block consists of four interconnected slices numbered 0-3 as shown in Figure 2.3. Each slice contains two LUTs. All the interconnections to and from PFU blocks are from routing. The PFU block can be used to perform Logical, Arithmetic, RAM or ROM functions. Table 2.1 shows the functions each slice can perform in either Distributed SRAM or non-distributed SRAM modes.
**==> picture [412 x 219] intentionally omitted <==**
**----- Start of picture text -----**<br>
From<br>Routing<br>J b&b<br>LUT4 & LUT4 & LUT4 & LUT4 & LUT4 & LUT4 & LUT4 & LUT4 &<br>CARRY CARRY CARRY CARRY CARRY CARRY CARRY CARRY<br>‘ ir -_ ii a re oe a<br>Slice 0 Slice 1 Slice 2 Slice 3<br>D D D D D D D D<br>FF FF FF FF FF FF FF FF<br>EEL EL EL<br>To<br>Routing<br>SJ<br>**----- End of picture text -----**<br>
**Figure 2.3. PFU Diagram**
## **2.2.1. Slice**
Each slice contains two LUT4s feeding two registers. In Distributed SRAM mode, Slice 0 and Slice 1 are configured as distributed memory and Slice 2 is not available as it is used to support Slice 0 and Slice 1, while Slice 3 is available as Logic or ROM. Table 2.1 shows the capability of the slices along with the operation modes they enable. In addition, each Slice contains logic that allows the LUTs to be combined to perform a LUT5 function. There is control logic to perform set/reset functions (programmable as synchronous/asynchronous), clock select, chip-select, and wider RAM/ROM functions.
**Table 2.1. Resources and Modes Available per Slice**
|**Slice**|**PFU(Used as Distributed SRAM)**|**PFU(Used as Distributed SRAM)**|**PFU(Not used as Distributed SRAM)**|**PFU(Not used as Distributed SRAM)**|
|---|---|---|---|---|
||**Resources**|**Modes**|**Resources**|**Modes**|
|Slice 0|2 LUT4s and 2 Registers|RAM|2 LUT4s and 2 Registers|Logic, Ripple, ROM|
|Slice 1|2 LUT4s and 2 Registers|RAM|2 LUT4s and 2 Registers|Logic, Ripple, ROM|
|Slice 2|2 LUT4s and 2 Registers|RAM|2 LUT4s and 2 Registers|Logic, Ripple, ROM|
|Slice 3|2 LUT4s and 2 Registers|Logic, Ripple, ROM|2 LUT4s and 2 Registers|Logic, Ripple, ROM|
Figure 2.4 shows an overview of the internal logic of the slice. The registers in the slice can be configured for positive/negative edge clocking.
Each slice has 17 input signals: 16 signals from routing and one from the carry-chain (from the adjacent slice or PFU). Three of them are used for FF control and shared between two slices (0/1 or 2/3). There are five outputs: four to routing and one to carry-chain (to the adjacent PFU). Table 2.2 and Figure 2.4 list the signals associated with all the slices. Figure 2.5 shows the slice signals that support a LUT5 or two LUT5 functions. F0 can be configured to have a LUT4 or LUT5 output while F1 is for a LUT4 output.
© 2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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**CrossLink-NX-33 and CrossLinkU-NX Data Sheet**
a@LATTICEag
LUT5 and Carry
**Figure 2.4. Slice Diagram**
© 2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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**CrossLink-NX-33 and CrossLinkU-NX Data Sheet**
mLATTICE
**==> picture [373 x 246] intentionally omitted <==**
**----- Start of picture text -----**<br>
A1<br>F1<br>B1<br>LUT4<br>C1<br>D1<br>1<br>F0<br>0<br>SEL<br>A0<br>B0<br>LUT4<br>C0<br>D0<br>**----- End of picture text -----**<br>
*Note: In RAM mode, LUT4s use the following signals: QWD0/1 QWDN0/1 QWAS00~03, QWAS10~13
**Figure 2.5. Slice Configuration for LUT4 and LUT5**
**Table 2.2. Slice Signal Descriptions**
|**Function**<br>~~GC~~|**Type **<br>~~GC~~|**Signal Names**<br>~~GC~~|**Description**<br>~~GC~~|
|---|---|---|---|
|Input<br>~~GC~~<br>~~eG~~|Data signal<br>~~GC~~<br>~~eG~~|A0, B0, C0, D0<br>~~GC~~<br>~~eG~~|Inputs to LUT4<br>~~GC~~<br>~~eG~~|
|Input<br>~~GG~~|Data signal<br>~~GG~~|A1, B1, C1, D1<br>~~GG~~|Inputs to LUT4<br>~~GG~~|
|Input<br>~~GC~~|Data signal<br>~~GC~~|M0, M1<br>~~GC~~|Direct input to FF from fabric<br>~~GC~~|
|Input<br>~~a~~|Control signal<br>~~Ge~~|SEL<br>~~Ge~~|LUT5 mux control input|
|Input<br>~~a~~<br>~~sO~~|Data signal<br>~~Ge~~<br>~~sO~~|DI0, DI1<br>~~Ge~~<br>~~sO~~|Inputs to FF from LUT4 F0/F1 outputs<br>~~sO~~|
|Input<br>~~sO~~<br>~~eG~~|Control signal<br>~~sO~~<br>~~eG~~|CE<br>~~sO~~<br>~~eG~~|Clock Enable<br>~~sO~~<br>~~eG~~|
|Input<br>~~eG~~<br>~~GG~~|Control signal<br>~~eG~~<br>~~GG~~|LSR<br>~~eG~~<br>~~GG~~|Local Set/Reset<br>~~eG~~<br>~~GG~~|
|Input<br>~~GC~~|Control signal<br>~~GC~~|CLKIN<br>~~GC~~|System Clock<br>~~GC~~|
|Input<br>~~a~~|Inter-PFU signal<br>~~Ge~~|FCI<br>~~Ge~~|Fast Carry-in1|
|Output<br>~~a~~<br>~~eG~~|Data signals<br>~~Ge~~<br>~~eG~~|F0<br>~~Ge~~<br>~~eG~~|LUT4/LUT5 output signal<br>~~eG~~|
|Output<br>~~eG~~<br>~~sO~~|Data signals<br>~~eG~~<br>~~sO~~|F1<br>~~eG~~<br>~~sO~~|LUT4 output signal<br>~~eG~~<br>~~sO~~|
|Output<br>~~sO~~<br>~~GG~~|Data signals<br>~~sO~~<br>~~GG~~|Q0, Q1<br>~~sO~~<br>~~GG~~|Register outputs<br>~~sO~~<br>~~GG~~|
|Output<br>~~CF~~|Inter-PFU signal<br>~~CF~~|FCO<br>~~CF~~|Fast carrychain output1<br>~~CF~~|
**Note** :
1. See Figure 2.4 for connection details.
© 2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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**CrossLink-NX-33 and CrossLinkU-NX Data Sheet**
mLATTICE
## **2.2.2. Modes of Operation**
Slices 0-2 have up to four potential modes of operation: Logic, Ripple, RAM and ROM. Slice 3 is not needed for RAM mode, it can be used in Logic, Ripple, or ROM modes.
## **Logic Mode**
In this mode, the LUTs in each slice are configured as 4-input combinatorial lookup tables. A LUT4 can have 16 possible input combinations. Any four input logic functions can be generated by programming this lookup table. Since there are two LUT4s per slice, a LUT5 can be constructed within one slice.
## **Ripple Mode**
Ripple mode supports the efficient implementation of small arithmetic functions. In ripple mode, the following functions can be implemented by each slice:
- Addition 2-bit
- Subtraction 2-bit
- Add/Subtract 2-bit using dynamic control
- Up counter 2-bit
- Down counter 2-bit
- Up/Down counter with asynchronous clear 2-bit using dynamic control
- Up/Down counter with preload (sync) 2-bit using dynamic control
- Comparator functions of A and B inputs 2-bit
- A greater-than-or-equal-to B
- A not-equal-to B
- A less-than-or-equal-to B
- Up/Down counter with A greater-than-or-equal-to B comparator 2-bit using dynamic control
- Up/Down counter with A less-than-or-equal-to B comparator 2-bit using dynamic control
- Multiplier support Ai × Bj + 1 + Ai + 1 × Bj in one logic cell with two logic cells per slice
- Serial divider 2-bit mantissa, shift 1bit/cycle
- Serial multiplier 2-bit, shift 1-bit/cycle or 2-bit/cycle
Ripple Mode includes an optional configuration that performs arithmetic using fast carry chain methods. In this configuration (also referred to as CCU2 mode) two additional signals, Carry Generate and Carry Propagate, are generated on a per slice basis to allow fast arithmetic functions to be constructed by concatenating Slices.
## **RAM Mode**
In this mode, a 16 × 4-bit distributed single or pseudo dual port RAM can be constructed in one PFU using each LUT block in Slice 0 and Slice 1 as a 16 × 2-bit memory in each slice. Slice 2 is used to provide memory address and control signals. LIFCL-33/33U devices support distributed memory initialization.
The Lattice design tools support the creation of a variety of different sized memories. Where appropriate, the software constructs these using distributed memory primitives that represent the capabilities of the PFU. Table 2.3 lists the number of slices required to implement different distributed RAM primitives. For more information about using RAM in LIFCL-33/33U devices, refer to Memory User Guide for Nexus Platform (FPGA-TN-02094).
## **Table 2.3. Number of Slices Required to Implement Distributed RAM**
||**SPR 16 × 4**|**PDPR 16 × 4**|
|---|---|---|
|Number of slices|3|3|
**Note** : SPR = Single Port RAM, PDPR = Pseudo Dual Port RAM
## **ROM Mode**
ROM mode uses the LUT logic; hence, Slice 0 through Slice 3 can be used in ROM mode. Preloading is accomplished through the programming interface during PFU configuration.
For more information, refer to Memory User Guide for Nexus Platform (FPGA-TN-02094).
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## **2.3. Routing**
There are many resources provided in the LIFCL-33/33U devices to route signals individually or as busses with related control signals. The routing resources consist of switching circuitry, buffers and metal interconnect (routing) segments.
LIFCL-33/33U devices have an enhanced routing architecture that produces a compact design. The Radiant software tool takes the output of the synthesis tool and places and routes the design.
## **2.4. Clocking Structure**
The LIFCL-33/33U clocking structure consists of clock synthesis blocks (PLLs), balanced clock tree networks (PCLK and ECLK), and efficient clock logic modules: Clock Dividers (PCLKDIV and ECLKDIV), Dynamic Clock Selection (DCS), Dynamic Clock Control (DCC), and DDRDLLs. Each of these functions is described as follows.
## **2.4.1. Global PLL**
The Global PLLs (GPLL) provide the ability to synthesize clock frequencies. The LIFCL-33/33U devices support two or three full-featured General Purpose GPLLs. The architecture of the GPLL is shown in Figure 2.6. A description of the GPLL functionality follows.
REFCLK is the reference frequency input to the PLL and its source can come from external CLK inputs or from internal routing. The CLKI input feeds into the input Clock Divider block.
CLKFB is the feedback signal to the GPLL which can come from a path internal to the PLL or from FPGA routing. The feedback divider is used to multiply the reference frequency and thus synthesize a higher or lower frequency clock output. The PLL has six clock outputs CLKOP, CLKOS, CLKOS2, CLKOS3, CLKOS4, and CLKOS5. Each output has its own output divider, thus allowing the GPLL to generate different frequencies for each output. The output dividers can have a value from 1 to 128. Each GPLL output can be used to drive the primary clock or edge clock networks.
The setup and hold times of the device can be improved by programming a phase shift into the output clocks which advances or delays the output clock with reference to the un-shifted output clock. This phase shift can be either programmed during configuration or can be adjusted dynamically using the DIRSEL, DIR, DYNROTATE, and LOADREG ports.
The LOCK signal is asserted when the GPLL determines it has achieved lock and deasserted if a loss of lock is detected. The LOCK signal is asynchronous to the PLL clock outputs.
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**CrossLink-NX-33 and CrossLinkU-NX Data Sheet**
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**==> picture [52 x 7] intentionally omitted <==**
**----- Start of picture text -----**<br>
(To bypass muxes)<br>**----- End of picture text -----**<br>
**Figure 2.6. General Purpose PLL Diagram**
For more details on the PLL, refer to the sysCLOCK PLL Design and User Guide for Nexus Platform (FPGA-TN-02095).
## **2.4.2. Clock Distribution Network**
There are two main clock distribution networks for any member of the LIFCL-33/33U product family, namely Primary Clock (PCLK) and Edge Clock (ECLK). These clock networks can be driven from many different sources, such as Clock Pins, PLL outputs, DLLDEL outputs, and Clock Divider outputs. There are Clock Divider blocks (ECLKDIV and PCLKDIV) to provide a slower clock from these clock sources.
LIFCL-33/33U devices support glitchless Dynamic Clock Control (DCC) for the PCLK Clock to save dynamic power. There are also Dynamic Clock Selection logic to allow glitchless selection between two clocks for the PCLK network (DCS).
An overview of the Clocking Network is shown in Figure 2.7 for the LIFCL-33/33U devices.
© 2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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**CrossLink-NX-33 and CrossLinkU-NX Data Sheet**
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**==> picture [321 x 287] intentionally omitted <==**
**----- Start of picture text -----**<br>
Bank 1 PCLK OSC<br>: :<br>TMID<br>16 DCC<br>Primary 16 Primary Sources Primary<br>i i 16<br>MUX | MUX<br>Pai<br>Enti Enti<br>18 Primary Sources<br>18 DCC<br>BMID<br>PLL BANK 4 PCLK ECLK BANK 3 PCLK ECLK BANK 2 PCLK ECLK<br>: : * * * * *<br>**----- End of picture text -----**<br>
**Figure 2.7. Clocking**
## **2.4.3. Primary Clocks**
The LIFCL-33/33U devices provide low-skew, high fan-out clock distribution to all synchronous elements in the FPGA fabric through the Primary Clock Network. The LIFCL-33/33U PCLK clock network is a balanced clock structure which is designed to minimize the clock skew across all destinations in the FPGA core.
The primary clock network is divided into two clock domains depending on the device density. Each of these domains has 16 clocks that can be distributed to the fabric in the domain.
The Lattice Radiant software can automatically route each clock to one of the domains up to a maximum of 16 clocks per domain. User can change how the clocks are routed by specifying a preference in the Lattice Radiant software to locate the clock to a specific domain. The LIFCL-33/33U devices provide the user with a maximum of 64 unique clock input sources that can be routed to the primary Clock network.
The primary clock sources are:
- Dedicated clock input pins
- PLL outputs
- PCLKDIV, ECLKDIV outputs
- Internal FPGA fabric entries (with minimum general routing)
- OSC clock
These sources are routed to each of four clock switches called a Mid Mux (LMID, RMID, TMID, BMID). The outputs of the Mid MUX are routed to the center of the FPGA where additional clock switches (DSC_CMUX) are used to route the primary clock sources to primary clock distribution to the LIFCL-33/33U fabric. These routing muxs are shown in Figure 2.7. There are potentially 64 unique clock domains that can be used in the largest LIFCL-33/33U device. For more information about the primary clock tree and connections, refer to sysCLOCK PLL Design and User Guide for Nexus Platform (FPGA-TN-02095).
© 2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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**CrossLink-NX-33 and CrossLinkU-NX Data Sheet**
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## **2.4.4. Edge Clock**
LIFCL-33/33U FPGAs have several high-speed edge clocks that are intended for use with the PIO in the implementation of high-speed interfaces. There are four (4) ECLK networks per bank I/O on the Bottom side of the device. The Edge clock network is powered by a separate power domain (to reduce power noise injection from the core and reduce overall noise induced jitter) while controlled by the same logic that gates the FPGA core and PCLK domains for power management. Each Edge Clock can be sourced from the following:
- Dedicated PIO Clock input pins (PCLK)
- DLLDEL output (PIO Clock delayed by 90°)
- PLL outputs (CLKOP, CLKOS, CLKOS2, CLKOS3, CLKOS4, and CLKOS5)
- Internal Nodes
Figure 2.8 illustrates the various ECLK sources. Bank 3 is shown in the example. Bank 2 and Bank 4 are similar.
**==> picture [420 x 171] intentionally omitted <==**
**----- Start of picture text -----**<br>
From Banks 2, 4<br>Bank 3 PCLK Pin (even) 2 ECLKSYNC<br>DLLDEL<br>Bottom 6<br>Left GPLL<br>Bank 3 ECLK Tree<br>From Fabric<br>ECLKSYNC<br>ECLKDIV BMID<br>2<br>Bank 3 PCLK Pin (odd)<br>To Banks 4,5 Muxes<br>**----- End of picture text -----**<br>
**Figure 2.8. Edge Clock Sources per Bank**
The edge clocks have low injection delay and low skew. They are typically used for Generic DDR interfaces. For detailed information on Edge Clock connections, refer to sysCLOCK PLL Design and User Guide for Nexus Platform (FPGA-TN-02095).
## **2.4.5. Clock Dividers**
LIFCL-33/33U devices have two distinct types of clock divider, Primary and Edge. There are from one (1) to eight (8) Primary Clock Dividers (PCLKDIV) and which are located in the DCS_CMUX block(s) at the center of the device. There are twelve (12) ECLKDIV dividers per device, locate near the bottom high-speed I/O banks.
The PCLKDIV supports ÷2, ÷4, ÷8, ÷16, ÷32, ÷64, ÷128, and ÷1 (bypass) operation. The PCLKDIV is fed from a DCSMUX within the DCS_CMUX block. The clock divider output drives one input of the DCS Dynamic Clock Select within the DSC_CMUX block. The Reset (RST) control signal is asynchronous and forces all outputs to low. The divider output starts at next cycle after the reset is synchronously released. The PCLKDIV is shown in context in Figure 2.8.
The ECLKDIV is intended to generate a slower-speed system clock from a high-speed edge clock. The block operates in a ÷2, ÷3.5, ÷4, or ÷5 mode and maintains a known phase relationship between the divided down clock and the high-speed clock based on the release of its reset signal. The ECLKDIV can be fed from selected PLL outputs, external primary clock pins (with or without DLLDEL Delay) or from routing. The clock divider outputs feed into the Bottom Mid-mux (BMID). The Reset (RST) control signal is asynchronous and forces all outputs to low. The divider output starts at next cycle after the reset is synchronously released.
The ECLKDIV block is shown in context in Figure 2.8. For further information on clock dividers, refer to sysCLOCK PLL Design and User Guide for Nexus Platform (FPGA-TN-02095).
© 2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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**CrossLink-NX-33 and CrossLinkU-NX Data Sheet**
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## **2.4.6. Clock Center Multiplexer Blocks**
All clock sources are selected and combined for primary clock routing through the Dynamic Clock Selector Center Multiplexer logic (DCS_CMUX). There are one (1) or two (2) DCS_CMUX blocks per device. Each DCS_CMUX block contains 2 DCSMUX blocks, 1 PCLKDIV, 1 DCS block, and 1 or 2 CMUX blocks. See Figure 2.9 for a representative DCS_CMUX block diagram.
The heart of the DCS_CMUX is the Center Multiplexer (CMUX) block. It can accept up to 64 input clock sources (Mid-muxes (RMID, LMID, TMIC, BMID) and DCC) and to drive up to 16 primary clock trunk lines.
Up to two (2) clock inputs to the DCS_CMUX can be routed through a Dynamic Clock Select block then routed to the CMUX. One (1) input to the DCS can be optionally divided by the Primary Clock Divider (PCLKDIV). For more information about the DCS_CMUX, refer to sysCLOCK PLL Design and User Guide for Nexus Platform (FPGA-TN-02095).
**==> picture [410 x 253] intentionally omitted <==**
**----- Start of picture text -----**<br>
16 16<br>16x (partial 16x (partial<br>(16/64):1) (16/64):1)<br>CMUX CMUX<br>16 16<br>DCS_CMUX dcs2cmux0<br>DCS<br>62<br>dcs1 dcs0<br>PCLKDIV<br>DCMUX DCMUX<br>(62:1) (62:1)<br>62 62<br>62 62<br>62<br>**----- End of picture text -----**<br>
**Figure 2.9. DCS_CMUX Diagram**
## **2.4.7. Dynamic Clock Select**
The Dynamic Clock Select (DCS) is a smart multiplexer function available in the primary clock routing. It switches between two independent input clock sources. Depending on the operational mode, it switches between two (2) independent input clock sources either with or without any glitches. This is achieved regardless of when the select signal is toggled. Both input clocks must be running to achieve a functioning glitchless DCS output clock, but running clocks are not required when used as a non-glitchless normal clock multiplexer.
There are one (1) or two (2) DCS blocks per device that feed all clock domains. The DCS blocks are located in the DCS_MUX block. The inputs to the DCS blocks come from MIDMUX outputs and user logic clocks via DCC elements. The DCS elements are located at the center of the PLC array core. The output of the DCS is connected to the inputs of Primary Clock Center MUXs (CMUX).
Figure 2.10 shows the timing waveforms of the default DCS operating mode. The DCS block can be programmed to other modes. For more information about the DCS, refer to sysCLOCK PLL Design and User Guide for Nexus Platform (FPGA-TN02095).
© 2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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**CrossLink-NX-33 and CrossLinkU-NX Data Sheet**
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CLK0<br>clk0<br>pos<br>CLK1<br>JLELbe<br>clk1 clk1<br>pos neg<br>SEL<br>1<br>clk0<br>neg<br>DCSOUT<br>**----- End of picture text -----**<br>
**Figure 2.10. DCS Waveforms**
## **2.4.8. Dynamic Clock Control**
The Dynamic Clock Control (DCC), Domain Clock enable/disable feature allows internal logic control of the domain primary clock network. When a clock network is disabled, the clock signal is static and does not toggle. All the logic fed by that clock also does not toggle, reducing the overall power consumption of the device. The disable function is glitchless, and does not increase the clock latency to the primary clock network.
Four additional DCC elements control the clock inputs from the LIFCL-33/33U domain logic to the Center MUX elements (DSC_CMUX).
This DCC controls the clock sources from the Primary CLOCK MIDMUX before they are fed to the Primary Center MUXs that drive the domain clock network. For more information about the DCC, refer to sysCLOCK PLL Design and User Guide for Nexus Platform (FPGA-TN-02095).
## **2.4.9. DDRDLL**
LIFCL-33/33U devices have two identical DDRDLL blocks, located in the lower left corner of the device. Each DDRDLL (master DLL block) can generate a 9-bit phase shift value corresponding to a 90-degree phase shift of the reference clock input and provide this value to every DQS block and DLLDEL slave delay element. The reference clock can be either from a PLL, or an input pin.
- The value is also sent to another slave DLL, DLLDEL, which takes a primary clock input and generates a 90-degree shifted clock output to drive the clocking structure. This is useful in an edge-aligned Generic DDR interface, where 90degree clocking needs to be created. Not all primary clock inputs have associated DLLDEL control. Figure 2.11 shows DDRDLL connectivity to a DLLDEL block.
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**CrossLink-NX-33 and CrossLinkU-NX Data Sheet**
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**==> picture [426 x 187] intentionally omitted <==**
**----- Start of picture text -----**<br>
To both BMID and<br>ECLKINMUX<br>PCLK Input<br>+<br>- DLLDEL<br>9 Right DDRDLL<br>9<br>Left DDRDLL<br>code1 code2<br>**----- End of picture text -----**<br>
**Figure 2.11. DLLDEL Functional Diagram**
Each DDRDLL can generate a delay value based on the reference clock frequency. The DLLDELs use the value (code) to either create phase shifted inputs from the DDR memory or create a 90-degree shifted clock. Figure 2.12 shows the connections between the DDRDLL and the DLLDELs.
**==> picture [423 x 135] intentionally omitted <==**
**----- Start of picture text -----**<br>
Left Right<br>DDRDLL DDRDLL<br>Digital Delay Code (L) Digital Delay Code (R)<br>Refclk Sel Refclk Sel<br>DLLDEL DLLDEL DQS0 DQS1 DLLDEL DQS0 DQS1<br>BANK4 ECLK BANK3 ECLK BANK2 ECLK<br>**----- End of picture text -----**<br>
**Figure 2.12. DDRDLL Architecture**
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**CrossLink-NX-33 and CrossLinkU-NX Data Sheet**
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## **2.5. sysMEM Memory**
LIFCL-33/33U devices contain a number of sysMEM Embedded Block RAM (EBR). The EBR consists of an 18 kb RAM with memory core, dedicated input registers and output registers as well as optional pipeline registers at the outputs. Each EBR includes functionality to support true dual-port, pseudo dual-port, single-port RAM, ROM and built in FIFO. In LIFCL-33/33U devices, unused EBR blocks is powered down to minimize power consumption.
## **2.5.1. sysMEM Memory Block**
The sysMEM block can implement single port, dual port or pseudo dual port memories. Each block can be used in a variety of depths and widths as listed in Table 2.4. FIFOs can be implemented using the built in read and write address counters and programmable full, almost full, empty and almost empty flags. The EBR block facilitates parity checking by supporting an optional parity bit for each data byte. EBR blocks provide byte-enable support for configurations with 18-bit and 36-bit data widths. For more information, refer to Memory User Guide for Nexus Platform (FPGA-TN-02094).
**Table 2.4. sysMEM Block Configurations**
|**Memory Mode**|**Configurations**|
|---|---|
|Single Port|16,384 × 1|
||8,192 × 2|
||4,096 × 4|
||2,048 × 9|
||1,024 × 18|
||512 × 36|
|True Dual Port|16,384 × 1|
||8,192 × 2|
||4,096 × 4|
||2,048 × 9|
||1,024 × 18|
|Pseudo Dual Port|16,384 × 1|
||8,192 × 2|
||4,096 × 4|
||2,048 × 9|
||1,024 × 18|
||512 × 36|
## **2.5.2. Bus Size Matching**
All the multi-port memory modes support different widths on each of the ports. The RAM bits are mapped LSB word 0 to MSB word 0, LSB word 1 to MSB word 1, and so on. Although the word size and number of words for each port varies, this mapping scheme applies to each port.
## **2.5.3. RAM Initialization and ROM Operation**
If desired, the contents of the RAM can be pre-loaded during device configuration. By preloading the RAM block during the chip configuration cycle and disabling the write controls, the sysMEM block can also be utilized as a ROM.
## **2.5.4. Memory Cascading**
Larger and deeper blocks of RAM can be created using EBR sysMEM Blocks. Typically, the Lattice design tools cascade memory transparently, based on specific design inputs.
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**CrossLink-NX-33 and CrossLinkU-NX Data Sheet**
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## **2.5.5. Single, Dual and Pseudo-Dual Port Modes**
In all the sysMEM RAM modes, the input data and address for the ports are registered at the input of the memory array. The output data of the memory is optionally registered at the output.
## **2.5.6. Memory Output Reset**
The EBR utilizes latches at the A and B output ports. These latches can be reset asynchronously or synchronously. RSTA and RSTB are local signals, which reset the output latches associated with Port A and Port B, respectively. The Global Reset (GSRN) signal can reset both ports. The output data latches and associated resets for both ports are as shown in Figure 2.13. The optional Pipeline Registers at the outputs of both ports are also reset in the same way.
**==> picture [351 x 223] intentionally omitted <==**
**----- Start of picture text -----**<br>
Memory Core D SET Q Port A[17:0]<br>LCLR<br>Ze<br>Output Data<br> Latches<br>D SET Q Port B[17:0]<br>LCLR<br>Ze<br>RSTA<br>Ee<br>RSTB<br>[> ><br>GSRN<br>=C ar<br>Programmable Disable<br>**----- End of picture text -----**<br>
**Figure 2.13. Memory Core Reset**
For further information on the sysMEM EBR block, see the list of technical documentation in References section.
## **2.6. Large RAM**
The LIFCL-33/33U devices include additional memory resources in the form of Large Random-Access Memory (LRAM) blocks.
The LRAM is designed to work as Single-Port RAM, Dual-Port RAM, Pseudo Dual-Port RAM, and ROM memories. It is meant to function as additional memory resources for the user beyond what is available in the EBR and PFU.
Each individual Large RAM block contains 0.5 Mbits of memory and has a programmable data width of up to 32 bits. Cascading Large RAM blocks allows data widths of up to 64 bits. Additionally, there is the ability to use either Error Correction Coding (ECC) or byte enable.
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## **2.7. sysDSP**
LIFCL-33/33U devices provide an enhanced sysDSP architecture, making it ideally suited for low-cost, high-performance Digital Signal Processing (DSP) applications. Typical functions used in these applications are Finite Impulse Response (FIR) filters, Fast Fourier Transforms (FFT) functions, Correlators, Reed-Solomon/Turbo/Convolution encoders and decoders. These complex signal processing functions use similar building blocks such as multiply-adders and multiply-accumulators.
## **2.7.1. sysDSP Approach Compared to General DSP**
Conventional general-purpose DSP chips typically contain one to four (Multiply and Accumulate) MAC units with fixed datawidth multipliers; this leads to limited parallelism and limited throughput. Their throughput is increased by higher clock speeds. In the LIFCL-33/33U device family, there are many DSP blocks that can be used to support different data widths. This allows the user to use highly parallel implementations of DSP functions. User can optimize DSP performance versus area by choosing appropriate levels of parallelism. Figure 2.14 compares the fully serial implementation to the mixed parallel and serial implementation.
**==> picture [432 x 258] intentionally omitted <==**
**----- Start of picture text -----**<br>
Operand Operand Operand<br>A A A<br>Operand Operand Operand<br>B B B<br>Operand Operand<br>A B<br>X X X m/k<br>loops<br>Single M loops Multiplier Multiplier<br>Multiplier<br>Multiplier X 0 1 k<br>Accumulator<br>(k adds) +<br>Function Implemented in General<br>Purpose DSP<br>m/k<br>accumulate<br>Output<br>Function Implemented in LIFCL-33 and<br>LIFCL-33U<br>**----- End of picture text -----**<br>
**Figure 2.14. Comparison of General DSP, LIFCL-33, and LIFCL-33U Approaches**
© 2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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**CrossLink-NX-33 and CrossLinkU-NX Data Sheet**
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## **2.7.2. sysDSP Architecture Features**
The LIFCL-33/33U sysDSP block contains two sysDSP slices. The LIFCL-33/33U sysDSP Slice has been significantly enhanced to provide functions needed for advanced processing applications. These enhancements provide improved flexibility and resource utilization.
The LIFCL-33/33U sysDSP block (two sysDSP slices) supports many functions that include the following:
- Symmetry support. The primary target application is wireless. 1D Symmetry is useful for many applications that use FIR filters when their coefficients have symmetry or asymmetry characteristics. The main motivation for using 1D symmetry is cost/size optimization. The expected size reduction is up to 2x.
- Odd Mode – Filter with Odd number of taps
- Even Mode – Filter with Even number of taps Two-dimensional (2D) Symmetry Mode – Supports 2D filters for mainly video applications
- Dual-multiplier architecture. Lower accumulator overhead to half and the latency to half compared to single multiplier architecture.
- Fully cascadable DSP across slices. Support for symmetric, asymmetric and non-symmetric filters.
- Multiply (36 × 36, two 18 × 36, four 18 × 18 or eight 9 × 9)
- Multiply Accumulate (supports one 18 × 36 multiplier result accumulation, two 18 × 18 multiplier result accumulation or four 9 × 9 multiplier result accumulation)
- Two Multiplies feeding one Accumulate per cycle for increased processing with lower latency (two 18 × 18 Multiplies feed into an accumulator that can accumulate up to 54 bits)
- Pipeline registers
- 1D Symmetry support. The coefficients of FIR filters have symmetry or negative symmetry characteristics.
- Odd Mode – Filter with Odd number of taps
- Even Mode – Filter with Even number of taps
- 2D Symmetry support. The coefficients of 2D FIR filters have symmetry or negative symmetry characteristics.
- 3 × 3 and 3 × 5 – Internal DSP Slice support
- 5 × 5 and larger size 2D blocks – Semi internal DSP Slice support
- Flexible saturation and rounding options to satisfy a diverse set of applications situations
- Flexible cascading DSP blocks
- Minimizes fabric use for common DSP functions
- Enables implementation of FIR Filter or similar structures using dedicated sysDSP slice resources only
- Provides matching pipeline registers Can be configured to continue cascading from one row of sysDSP slices to another for longer cascade chains
- RTL Synthesis friendly synchronous reset on all registers, while still supporting asynchronous reset for legacy users.
- Dynamic MUX selection to allow Time Division Multiplexing (TDM) of resources for applications that require processorlike flexibility that enables different functions for each clock cycle.
For most cases, as shown in Figure 2.15, the LIFCL-33/33U sysDSP block is backwards-compatible with the LatticeECP3™ sysDSP block, such that, legacy applications can be targeted to LIFCL-33/33U sysDSP. Figure 2.15 shows the diagram of sysDSP block.
© 2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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**CrossLink-NX-33 and CrossLinkU-NX Data Sheet**
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**----- Start of picture text -----**<br>
Input Input Input Input Input Input Input Input<br>B1 B1 B1 B1 B1 B1 B1 B1<br>Input p Input } Input fj) Input Input | Input J Input ff Input Input td) Input Input tt Input Input Input Input Input<br>C B2 C B2 C B2 C B2 C B2 C B2 C B2 C B2<br>9 + 9 9 + 9 9 + 9 9 + 9 9 + 9 9 + 9 9 + 9 9 + 9<br>Input Input Input Input Input Input Input Input<br>REG REG REG REG REG REG REG REG<br>A1 A1 A1 A1 A1 A1 A1 A1<br>Input Input Input Input Input Input Input Input<br>A2 A2 A2 A2 A2 A2 A2 A2<br>9 x 9 9 x 9 9 x 9 9 x 9 9 x 9 9 x 9 9 x 9 9 x 9<br>COCQCOCQCQCQCDOS<br>18 X 18 18 X 18 18 X 18 18 X 18<br>rr ee eee ee<br>18 X 36 (CSA) 18 X 36 (CSA)<br>rr<br>36 X 36 (CSA)<br>Po<br>REG 18 REG 18 REG 18 REG 18 REG 18 REG 18 REG 18 REG 18<br>[| J jf jf jf jf jf J)<br>ACC54 ACC54<br>a<br>Output Register Output Register<br>SS<br>Note : All Registers inside the DSP Block are Bypassable via Configuration Setting<br>**----- End of picture text -----**<br>
**Figure 2.15. DSP Functional Block Diagram**
The LIFCL-33/33U sysDSP block supports the following basic elements.
- MULT (Multiply)
- MAC (Multiply, Accumulate)
- MULTADDSUB (Multiply, Addition/Subtraction)
- MULTADDSUBSUM (Multiply, Addition/Subtraction, Summation)
Table 2.5 shows the capabilities of LIFCL-33/33U sysDSP block versus the above functions.
**Table 2.5. Maximum Number of Elements in a sysDSP Block**
|**Width of Multiply**|**x9**|**x18**|**x36**|
|---|---|---|---|
|MULT|8|4|1|
|MAC|2|2|—|
|MULTADDSUB|2|2|—|
|MULTADDSUBSUM|2|2|—|
Some options are available in the four elements. The input register in all the elements can be directly loaded or can be loaded as a shift register from previous operand registers. By selecting _dynamic operation,_ the following operations are possible:
- In the Add/Sub option, the Accumulator can be switched between addition and subtraction on every cycle.
- The loading of operands can switch between parallel and serial operations.
For further information, refer to sysDSP User Guide for Nexus Platform (FPGA-TN-02096).
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**CrossLink-NX-33 and CrossLinkU-NX Data Sheet**
## **2.8. Programmable I/O (PIO)**
The programmable logic associated with an I/O is called a PIO. The individual PIO are connected to their respective sysI/O buffers and pads.
On all LIFCL-33/33U devices, two adjacent PIO can be combined to provide a complementary output driver pair.
## **2.9. Programmable I/O Cell (PIC)**
The programmable I/O cells (PIC) provides I/O function and necessary gearing logic associated with PIO. LIFCL-33/33U devices consist of base PIC and gearing PIC.
Base PICs contain three blocks: an input register block, output register block, and tri-state register block. These blocks contain registers for operating in a variety of modes along with the necessary clock and selection logic. Base PICs cover the top bank. Gearing PICs contain gearing logic and edge monitor used for locating the center of data window. Gearing PICs cover the bottom banks to support DDR operation.
**==> picture [288 x 277] intentionally omitted <==**
**----- Start of picture text -----**<br>
PIC<br>PIO A<br>Input<br>Register<br>Block<br>Output and<br>Tristate Pin<br>Register A<br>1 ae Block<br>Core<br>Logic/ Input and Output<br>Gearbox<br>Routing<br>PIO B<br>Input<br>| ml=a Register<br>Block<br>Output and<br>Tristate Pin<br>| “ih<br>Register B<br>Block<br>cae<br>**----- End of picture text -----**<br>
**Figure 2.16. Group of Two High Performance Programmable I/O Cells**
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**CrossLink-NX-33 and CrossLinkU-NX Data Sheet**
**==> picture [285 x 277] intentionally omitted <==**
**----- Start of picture text -----**<br>
PIC<br>PIO A<br>Input<br>Register<br>Block<br>Output and<br>Tristate Pin<br>Register A<br>CHI Block<br>Core<br>Logic/ a =<br>Routing<br>PIO B<br>Input<br>Register<br>Block<br>Output and<br>Oh Tristate Pin<br>Register B<br>Block<br>——_ ie<br>**----- End of picture text -----**<br>
**Figure 2.17. Wide Range Programmable I/O Cells**
## **2.9.1. Input Register Block**
The input register blocks for the PIO on all edges contain delay elements and registers that can be used to condition highspeed interface signals before they are passed to the device core.
The Input register block on the bottom side includes gearing logic and registers to implement IDDRX1, IDDRX2, IDDRX4, IDDRX5 gearing functions. With two PICs sharing the DDR register path, it can also implement the IDDRX71 function used for 7:1 LVDS interfaces. It uses three sets of registers – shift, update, and transfer to implement gearing and the clock domain transfer. The first stage registers sample the high-speed input data by the high-speed edge clock on its rising and falling edges. The second stage registers perform data alignment based on the control signals. The third stage pipeline registers pass the data to the device core synchronized to the low-speed system clock. For more information on gearing function, refer to CrossLink-NX-33 and CrossLinkU-NX High-Speed I/O Interface (FPGA-TN-02280).
## **Input FIFO**
The LIFCL-33/33U PIO has a dedicated input FIFO per single-ended pin for input data register for DDR Memory interfaces. The FIFO resides before the gearing logic. It transfers data from DQS domain to continuous ECLK domain. On the Write side of the FIFO, it is clocked by DQS clock, which is the delayed version of the DQS Strobe signal from DDR memory. On the Read side of FIFO, it is clocked by ECLK. ECLK may be any high-speed clock with identical frequency as DQS (the frequency of the memory chip). Each DQS group has one FIFO control block. It distributes FIFO read/write pointers to every PIC in same DQS group.
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**CrossLink-NX-33 and CrossLinkU-NX Data Sheet**
**Table 2.6. Input Block Port Description**
|**Name**|**Type **|**Description**|
|---|---|---|
|D|Input|High Speed Data Input|
|Q[1:0]/Q[3:0]/Q[6:0]/Q[7:0]/Q[9:0]|Output|Low Speed Data to the device core|
|RST|Input|Reset to the Output Block|
|SCLK|Input|Slow Speed System Clock|
|ECLK|Input|High Speed Edge Clock|
|DQS|Input|Clock from DQS control Block used to clock DDR memorydata|
|ALIGNWD|Input|Data Alignment signal from device core.|
Figure 2.18 shows the input register block for the PIO on the top edge.
**==> picture [465 x 173] intentionally omitted <==**
**----- Start of picture text -----**<br>
INCK<br>D Programmable INFF<br>Delay Cell<br>INFF Q<br>SCLK IDDRX1 Q[1:0]<br>RST<br>Te<br>Figure 2.18. Input Register Block for PIO on Top Side of the Device<br>Figure 2.19 shows the input register block for the PIO located on the bottom edge.<br>**----- End of picture text -----**<br>
**==> picture [395 x 175] intentionally omitted <==**
**----- Start of picture text -----**<br>
IN CK<br>IN FF<br>Programmable<br>D<br>Delay Cell<br>IN FF Q<br>Generic<br>IDDRX1<br>FIFO IDDRX2 Q[1:0]/<br>IDDRX4 Q[3:0]/<br>Delayed DQS ECLK IDDRX5 Q[6:0]*/<br>IDDRX71* Q[7:0]/<br>Q[9:0]<br>Memory<br>ECLK<br>IDDRX2<br>SCLK IDDRX4<br>RST<br>ALIGNWD<br>**----- End of picture text -----**<br>
*For 7:1 LVDS interface only. It is required to use PIO pair pins (PIOA/B or PIOC/D).
**Figure 2.19. Input Register Block for PIO on Bottom Side of the Device**
© 2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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**CrossLink-NX-33 and CrossLinkU-NX Data Sheet**
## **2.9.2. Output Register Block**
The output register block registers signals from the core of the device before they are passed to the sysI/O buffers.
The LIFCL-33/33U output data path has programmable registers and output gearing logic. On the bottom side, the output register block can support 1x, 2x, x4, x5, and 7:1 gearing enabling high speed DDR and DDR memory interfaces. On the top side, the banks support 1x gearing. The LIFCL-33/33U output data path diagram is shown in Figure 2.20. The programmable delay cells are also available in the output data path.
For a detailed description of the output register block modes and usage, refer to CrossLink-NX-33 and CrossLinkU-NX High-
Speed I/O Interface (FPGA-TN-02280).
**==> picture [438 x 400] intentionally omitted <==**
**----- Start of picture text -----**<br>
Programmable<br>D Delay Cell Q<br>OUTFF<br>RST<br>SCLK Generic<br>ODDRX1<br>D[1:0]<br>er<br>Figure 2.20. Output Register Block on Top Side<br>Programmable<br>D Delay Cell<br>Q<br>OUTFF<br>RST Generic<br>SCLK ODD RX1/<br>ODD RX2/<br>ECLK ODD RX4<br>DQSW ODD RX5<br>ODD R71*<br>DQSW270<br>Memory<br>Q[1:0]/ ODD RX2<br>Q[3:0]/ OSHX2<br>Q[6:0]*/ ODD RX4<br>Q[7:0]/ i) _)-<br>Q[9:0]<br>*For 7:1 LVDS interface only. It is required to use PIO pair pins PIOA/B.<br>**----- End of picture text -----**<br>
**Figure 2.21. Output Register Block on Bottom Side**
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**CrossLink-NX-33 and CrossLinkU-NX Data Sheet**
a@LATTICE
**Table 2.7. Output Block Port Description**
|**Name**|**Type**|**Description**|
|---|---|---|
|Q|Output|High Speed Data Output|
|D|Input|Data from core to output SDR register|
|Q[1:0]/Q[3:0]/Q[6:0]/Q[7:0]/Q[9:0]|Input|Low Speed Data from device core to output DDR register|
|RST|Input|Reset to the Output Block|
|SCLK|Input|Slow Speed System Clock|
|ECLK|Input|High Speed Edge Clock|
|DQSW|Input|Clock from DQS control Block used to generate DDR memory DQS output|
|DQSW270|Input|Clock from DQS control Block used to generate DDR memory DQ output|
## **2.10. Tri-state Register Block**
The tri-state register block registers tri-state control signals from the core of the device before they are passed to the sysI/O buffers. The block contains a register for SDR operation. In SDR, the TD input feeds one of the flip-flops that then feeds the output. In DDR, operations used mainly for DDR memory interfaces can be implemented on the bottom side of the device. Here, two inputs feed the tri-state registers clocked by both ECLK and SCLK.
Figure 2.22 and Figure 2.23 show the Tri-state Register Block functions on the device. For a detailed description of the tri-state register block modes and usage, refer to CrossLink-NX-33 and CrossLinkU-NX High-Speed I/O Interface (FPGA-TN02280).
**==> picture [295 x 39] intentionally omitted <==**
**----- Start of picture text -----**<br>
TQ<br>TD<br>RST TSFF<br>SCLK<br>**----- End of picture text -----**<br>
**Figure 2.22. Tri-state Register Block on Top Side**
**==> picture [301 x 215] intentionally omitted <==**
**----- Start of picture text -----**<br>
TQ<br>TD<br>TSFF<br>RST<br>SCLK<br>ECLK<br>THSX2<br>DQSW<br>DQSW270 ——__—>|<br>T[1:0] ——_—_>|<br>**----- End of picture text -----**<br>
**Figure 2.23. Tri-state Register Block on Bottom Side**
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**CrossLink-NX-33 and CrossLinkU-NX Data Sheet**
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**Table 2.8. Tri-state Block Port Description**
|**Name**|**Type**|**Description**|
|---|---|---|
|TD|Input|Tri-state Input to Tri-state SDR Register|
|RST|Input|Reset to the Tri-state Block|
|T[1:0]|Input|Tri-state input to TSHX2 function|
|SCLK|Input|Slow Speed System Clock|
|ECLK|Input|High Speed Edge Clock|
|DQSW|Input|Clock from DQS control Block used to generate DDR memory DQS output|
|DQSW270|Input|Clock from DQS control Block used to generate DDR memory DQ output|
|TQ|Output|Output of the Tri-state block|
## **2.11. sysI/O Buffer**
Each I/O is associated with a flexible buffer referred to as a sysI/O buffer. These buffers are arranged around the periphery of the device in groups referred to as banks. The sysI/O buffers allow you to implement a wide variety of standards that are found in today’s systems including LVDS, LVCMOS, LVTTL, and MIPI.
The LIFCL-33/33U family contains multiple Programmable I/O Cell (PIC) blocks. Each PIC contains two Programmable I/O, PIOA and PIOB. Each PIO includes a sysI/O buffer and I/O logic. Two adjacent PIO can be joined to provide a differential I/O pair referred to as True and Comp, where True Pad is associated with the positive side of the differential I/O, and the complement with the negative.
The top side bank support I/O standards from 3.3 V to 1.0 V while the bottom supports I/O standards from 1.8 V to 1.0 V. Every pair of I/O on the bottom bank also have a true LVDS and SLVS Tx Driver. In addition, the bottom bank supports single-ended input termination. Both static and dynamic termination are supported. For more information about DDR implementation in I/O Logic and DDR memory interface support, refer CrossLink-NX-33 and CrossLinkU-NX High-Speed I/O Interface (FPGA-TN-02280).
## **2.11.1. Supported sysI/O Standards**
LIFCL-33/33U sysI/O buffers support both single-ended differential and differential standards. Single-ended standards can be further subdivided into internally ratioed standards such as LVCMOS, LVTTL and externally referenced standards such as HSTL. The buffers support the LVTTL, LVCMOS 1.0 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V, and 3.3 V standards. Differential standards supported include LVDS, SLVS, and differential LVCMOS. For better support of video standards, subLVDS and MIPI_D-PHY are also supported. Table 2.9 and Table 2.10 provide a list of sysI/O standards supported in LIFCL-33/33U devices.
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**CrossLink-NX-33 and CrossLinkU-NX Data Sheet**
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**Table 2.9. Single-Ended I/O Standards**
|**Standard**<br>~~GG~~|**Input**<br>~~GG~~|**Output**<br>~~GG~~|**Bi-directional**<br>~~GG~~|
|---|---|---|---|
|LVTTL33<br>~~GG~~|Yes<br>~~GG~~|Yes<br>~~GG~~|Yes<br>~~GG~~|
|LVCMOS33<br>~~CG~~|Yes<br>~~CG~~|Yes<br>~~CG~~|Yes<br>~~CG~~|
|LVCMOS25<br>~~GG~~|Yes<br>~~GG~~|Yes<br>~~GG~~|Yes<br>~~GG~~|
|LVCMOS18<br>~~GG~~<br>~~GG~~|Yes<br>~~GG~~<br>~~GG~~|Yes<br>~~GG~~<br>~~GG~~|Yes<br>~~GG~~<br>~~GG~~|
|LVCMOS15<br>~~DG~~|Yes<br>~~DG~~|Yes<br>~~DG~~|Yes<br>~~DG~~|
|LVCMOS12<br>~~GG~~|Yes<br>~~GG~~|Yes<br>~~GG~~|Yes<br>~~GG~~|
|LVCMOS10<br>~~GG~~|Yes<br>~~GG~~|No<br>~~GG~~|No<br>~~GG~~|
|HTSL15 I<br>~~GG~~|Yes<br>~~GG~~|Yes<br>~~GG~~|Yes<br>~~GG~~|
|LVCMOS18H<br>~~GG~~<br>~~GG~~|Yes<br>~~GG~~<br>~~GG~~|Yes<br>~~GG~~<br>~~GG~~|Yes<br>~~GG~~<br>~~GG~~|
|LVCMOS15H<br>~~DG~~|Yes<br>~~DG~~|Yes<br>~~DG~~|Yes<br>~~DG~~|
|LVCMOS12H<br>~~OG~~|Yes<br>~~OG~~|Yes<br>~~OG~~|Yes<br>~~OG~~|
|LVCMOS10H<br>~~GG~~|Yes<br>~~GG~~|Yes<br>~~GG~~|Yes<br>~~GG~~|
|LVCMOS10R<br>~~DO~~|Yes<br>~~DO~~|—<br>~~DO~~|Yes1<br>~~DO~~|
- **Note:** 1. Output supported by LVCMOS10H.
**Table 2.10. Differential I/O Standards**
|**Standard**<br>~~DG~~|**Input**<br>~~DG~~|**Output**<br>~~DG~~|**Bi-directional**<br>~~DG~~|
|---|---|---|---|
|LVDS<br>~~DG~~|Yes<br>~~DG~~|Yes<br>~~DG~~|Yes<br>~~DG~~|
|SUBLVDS<br>~~DG~~|Yes<br>~~DG~~|No<br>~~DG~~|—<br>~~DG~~|
|SLVS<br>~~GG~~|Yes<br>~~GG~~|Yes<br>~~GG~~|—<br>~~GG~~|
|SUBLVDSE<br>~~GG~~|—<br>~~GG~~|Yes<br>~~GG~~|—<br>~~GG~~|
|SUBLVDSEH<br>~~GG~~<br>~~GG~~|—<br>~~GG~~<br>~~GG~~|Yes<br>~~GG~~<br>~~GG~~|—<br>~~GG~~<br>~~GG~~|
|LVDSE<br>~~FeO~~|—<br>~~FeO~~|Yes<br>~~FeO~~|—<br>~~FeO~~|
|MIPI_D-PHY<br>~~GG~~|Yes<br>~~GG~~|Yes<br>~~GG~~|Yes<br>~~GG~~|
|HSTL15D_I<br>~~GG~~|Yes<br>~~GG~~|Yes<br>~~GG~~|Yes<br>~~GG~~|
|LVTTL33D<br>~~GG~~<br>~~DG~~|—<br>~~GG~~<br>~~DG~~|Yes<br>~~GG~~<br>~~DG~~|—<br>~~GG~~<br>~~DG~~|
|LVCMOS33D<br>~~DG~~<br>~~GG~~|—<br>~~DG~~<br>~~GG~~|Yes<br>~~DG~~<br>~~GG~~|—<br>~~DG~~<br>~~GG~~|
|LVCMOS25D<br>~~GG~~<br>~~DG~~|—<br>~~GG~~<br>~~DG~~|Yes<br>~~GG~~<br>~~DG~~|—<br>~~GG~~<br>~~DG~~|
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**CrossLink-NX-33 and CrossLinkU-NX Data Sheet**
mLATTICE
## **2.11.2. sysI/O Banking Scheme**
The LIFCL-33/33U devices have up to six banks in total. There are three banks on the top, and three at the bottom side of the device. Bank 0, Bank 1, and Bank 5 support up to VCCIO 3.3 V while Bank 2, Bank 3, and Bank 4 support up to VCCIO 1.8 V.
Bank 5 is only supported in LIFCL-33, while AON and USB signals are only available in LIFCL-33U.
## **Typical sysI/O Behavior During Power-up**
The internal Power-On-Reset (POR) signal is deactivated when VCC and VCCAUX have reached satisfactory levels. After the POR signal is deactivated the FPGA core logic becomes active. It is the responsibility of the user to ensure that all other VCCIO banks are active with valid input logic levels to properly control the output logic states of all the I/O banks that are critical to the application. For more information about controlling the output logic state with valid input logic levels during power-up in LIFCL-33/33U devices, see the list of technical documentation in References section.
VCC and VCCAUX supply the power to the FPGA core fabric, whereas VCCIO supplies power to the I/O buffers. To simplify the system design while providing consistent and predictable I/O behavior, it is recommended that the I/O buffers be poweredup prior to the FPGA core fabric. For the different power supply voltage levels supported by the I/O banks, refer to sysI/O User Guide for Nexus Platform (FPGA-TN-02067) for detailed information.
## **VREF1 and VREF2**
Bank 2, Bank 3, and Bank 4 can support two separate VREF input voltages, VREF1, and VREF2. To assign a VREF driver, use IO_Type = VREF1_DRIVER or VREF2_DRIVER. To assign VREF to a buffer, use VREF1_LOAD or VREF2_LOAD.
## **sysI/O Standards Supported by I/O Bank**
All banks can support multiple I/O standards under the VCCIO rules discussed above. Table 2.11 and Table 2.12 summarize the I/O standards supported on various sides of the LIFCL-33/33U devices.
**Table 2.11. Single-Ended I/O Standards Supported on Various Sides**
|**Standard**|**Top**|**Bottom**|
|---|---|---|
|LVTTL33|Yes|—|
|LVCMOS33|Yes|—|
|LVCMOS25|Yes|—|
|LVCMOS18|Yes|—|
|LVCMOS15|Yes|—|
|LVCMOS12|Yes|—|
|LVCMOS10|Yes|—|
|LVCMOS18H|—|Yes|
|LVCMOS15H|—|Yes|
|LVCMOS12H|—|Yes|
|LVCMOS10H|—|Yes|
|LVCMOS10R|—|Yes|
|HTSL15 I|—|Yes|
© 2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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**CrossLink-NX-33 and CrossLinkU-NX Data Sheet**
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**Table 2.12. Differential I/O Standards Supported on Various Sides**
|**Standard**|**Top**|**Bottom**|
|---|---|---|
|LVDS|—|Yes|
|SUBLVDS|—|Yes|
|SLVS|—|Yes|
|SUBLVDSE|Yes|—|
|SUBLVDSEH|—|Yes|
|LVDSE|Yes|—|
|MIPI_D-PHY|—|Yes|
|HSTL15D_I|—|Yes|
|LVTTL33D|Yes|—|
|LVCMOS33D|Yes|—|
|LVCMOS25D|Yes|—|
## **Hot Socketing**
LIFCL-33/33U devices have been carefully designed to ensure predictable behavior during power-up and power-down. During power-up and power-down sequences, the I/O remain in tri-state until the power supply voltage is high enough to ensure reliable operation. In addition, leakage into I/O pins is controlled within specified limits. Bank 0, Bank 1, and Bank 5 wide range I/O (excluding MCLK/MCSN/MOSI/INITN/DONE) are hot socketable. Bank 2, Bank 3, and Bank 4 do not support hot socketing.
## **2.11.3. sysI/O Buffer Configurations**
This section describes the various sysI/O features available on the LIFCL-33/33U devices. Refer to sysI/O User Guide for Nexus Platform (FPGA-TN-02067) for detailed information.
## **2.12. IEEE 1149.1-Compliant Boundary Scan Testability**
All LIFCL-33/33U devices contain various ports that can be used for configuration, including a Test Access Port (TAP). This allows functional testing of the circuit board on which the device is mounted through a serial scan path that can access all critical logic nodes. Internal registers are linked internally, allowing test data to be shifted in and loaded directly onto test nodes, or test data to be captured and shifted out for verification. The test access port consists of dedicated I/O: TDI, TDO, TCK, and TMS. The test access port uses VCCIO1 for power supply. The test access port is supported for VCCIO1 = 1.8 V - 3.3 V.
For more information, refer to sysCONFIG User Guide for Nexus Platform (FPGA-TN-02099).
## **2.13. Always On (AON)**
The Hardware (HW) AON block in LIFCL-33U is provided to support low power application, where the main FPGA device can be put in the power down state while the AON block continues to operate as a wake-up timer. The auxiliary power (always on power domain) to the AON block is provided by the dedicated VCCAUX_AON supply rail. This is isolated from the rest of the FPGA power domain that can be turned off for low power applications. The AON_OUT output pin is provided to control the external power switch and AON_INT is provided to interrupt or to override the power down state. Both external signals follow the 1.8 V LVCMOS I/O standard. Figure 2.24 shows the high-level block diagram with internal FPGA internal interface control signals for the AON block. Table 2.13 provides the descriptions of the AON ports.
For more information, refer to Always ON Module IP User Guide (FPGA-IPUG-02216).
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**CrossLink-NX-33 and CrossLinkU-NX Data Sheet**
mLATTICE
**==> picture [477 x 146] intentionally omitted <==**
**----- Start of picture text -----**<br>
cnt_set<15:0><br>pre_sleep AON_INT<br>test_mode_en AON<br>aon_timer_cal_clk<br>AON_OUT<br>pre_aon_out<br>FPGA Internal I/F External I/O Pins<br>**----- End of picture text -----**<br>
**Figure 2.24. AON Functional Block Diagram**
**Table 2.13. AON Port Description**
|**Interface**|**Port Names**|**In/Out to AON**|**Description**|
|---|---|---|---|
|FPGA<br>Internal I/F|cnt_set<15:0>|Input|Upon FPGA power up, this 16-bit AON timer counter value is used to set the<br>AON wake up timer output (AON_OUT). Internal timer is running at 1 kHz<br>nominal clock frequency|
||pre_sleep|Input|This input from the FPGA logic is used to indicate to the AON to drive the<br>AON_OUT low indicatingthat FPGA can bepowered down.|
||test_mode_en|Input|This input can be used to trigger AON test mode|
||aon_time_cal_clk|Output|Internal AON timer clock output can be used for calibration. Nominal clock<br>frequencyis 16 kHz.|
||pre_aon_out|Output|Internal test mode output before the AON_OUT external signal.|
|External|AON_INT|Input|Active high (AON_INT = 1) strobe signal to externally switch FPGA from<br>power down state(AON_OUT=0)topower on state(AON_OUT=1)|
||AON_OUT|Output|Always On output to control power regulator(s). FPGA Power Down=0; FPGA<br>Power Up= 1|
## **2.14. USB**
The Hardened USB block in CrossLink-NX33U is designed to support device controller applications such as image sensor data transfer through USB 3.2 Gen 1 and I[2] C, GPIO, SPI control signals through USB 2.0. It can support USB 3.2 Gen 1 (5 Gbps) and USB 2.0 HS (480 Mbps), and FS (12 Mbps) modes. Internal interface consists of PIPE interface to AXI (Main) DMA data transfer for high-speed video applications. For control interface, internal UTMI data is translated to AHB (Secondary) and LMMI interface to FPGA fabric. The high-level block diagram of the USB hard IP is shown in Figure 2.25.
© 2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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**CrossLink-NX-33 and CrossLinkU-NX Data Sheet**
**==> picture [497 x 239] intentionally omitted <==**
**----- Start of picture text -----**<br>
USB Hard IP<br>ref_clk DIV5<br>[|<br>FIFO PDP RAM<br>LMMI to AHB (S) UTMI USB2 PHY DP/DM<br>CS —<br>USB Device Controller<br>SSTX_P/SSTX_M<br>AXI (M) for DMA<br>PIPE USB3 PHY<br><> ——)<br>SSRX_P/SSRX_M<br>FPGA Fabric I/F External I/O Pins<br>**----- End of picture text -----**<br>
**Figure 2.25. USB Hard IP Functional Block Diagram**
## **2.14.1. USB Hardware Architecture**
The typical device applications found in USB 3.2 Gen 1 and LIFCL-33U internal interface are described in this section. The following are the example USB applications:
- USB low speed I/O interface aggregation
- USB video class streaming
Figure 2.26 shows the internal interface block diagram.
**==> picture [502 x 176] intentionally omitted <==**
**----- Start of picture text -----**<br>
CrossLink-NX-33U<br>USB Hard IP<br>ref_clk DIV5<br>Sys Mem RISC-V<br>- it —<br>MIPI Camera I/F Pre-procISP/Img UVC/RAW LMMI to AHB (S) FIFO PDP RAM<br>“ IC | Kx<br>SPI FLash SPI (M)<br>USB Device Controller UTMI USB2 PHY DP/DM<br>T S Fk AXI (M) for DMA<br>I²C Camera Control I²C (M)<br>FPGA Fabric I/F SSTX_P/SSTX_M<br>LED/DIP Switch GPIO PIPE USB3 PHY<br>eS<br>SSRX_P/SSRX_M<br>Typical Application (M) – Main(S) - Secondary<br>External I/O Pins<br>AHB-Bridge<br>**----- End of picture text -----**<br>
**Figure 2.26. Typical USB Hardware Application Diagram**
© 2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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**CrossLink-NX-33 and CrossLinkU-NX Data Sheet**
mLATTICE
## **2.14.1.1. USB Device Controller:**
The controller has the following interfaces:
- Application interfaces – AXI and LMMI per hard macro design. The secondary interface is LMMI used as control path for register and RAM debug access. The primary interface is AXI used ad data path for internal DMA accessing external memory. The hard-macro has internal bridge to convert LMMI interface.
- FIFO interface is implemented in PDP RAM and used to access EP RAM per IP definition.
- The PHY interfaces (UTMI and PIPE) are transparent and integrated in Hard Macro.
- Infrastructure connection for clock, reset, debug and power. Refer to Clock, Reset, Debug, and Power section for more details.
## **2.14.1.2. Endpoints**
The number of end points and packet sizes are user-configurable. Table 2.14 provides the maximum number and types of EP and maximum packet sizes supported by each end points.
**Table 2.14. USB Endpoint FIFO Size and Burst Size (Maximum Packet Size)**
|**EP Type**|**FIFO Size**||**Burst size**|
|---|---|---|---|
|Control BiDir|—||—|
|Bulk|4 kB||4x MPS|
|Bulk|4 kB||4x MPS|
|Isoc|4 kB||4x MPS|
|Isoc|4 kB||4x MPS|
|Interrupt|4 kB||4x MPS|
|Interrupt|256 B||—|
|Interrupt|256 B||—|
|Interrupt|256 B||—|
## **2.14.1.3. Clock, Reset, Debug, and Power**
- The following clocks need to be supplied per IP Databook:
- AHB bus clock and RAM clock can be the same
- U2MAC clock – same as UTMI clock
- U3MAC clock – link clock, or same as pipe clock
- Pipe clock – PHY interface clock
- Clock gating is enabled for low power device application.
- The USB device bus power is managed by the host controller (SoC) for LP PHY modes like P1/2/3 and link states like U1/2/3. The USB 2.0 mode enables LPM-L1 and suspend states to reduce the application power.
## **2.14.1.4. USB PHY**
- Reference clock and DIV5 is implemented in hard-macro.
- Based on speed negotiation, only one PHY is active during connect and are mutually exclusive.
## **2.14.1.5. Application Fabric**
- The application fabric could be AHB with the appropriate individual bridge (AHB to APB/AXI/LMMI) interface IP.
- Provides main (M) and secondary (S) nodes for all the controller interface with RISC-V.
## **2.14.1.6. RISCV**
- The core could be RISC-V MC SIP core with the Lattice Propel™ toolchain.
- The LRAMs are allocated for core system memory and as intermediate buffer to exchange data structures and payload between RISC-V and the controller such as USB, I[2] C, and SPI.
© 2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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**CrossLink-NX-33 and CrossLinkU-NX Data Sheet**
## **2.14.1.7. I/O Aggregation and Common Modules**
- The standard IP from the library is used for I[2] C, SPI, and GPIO.
- The SPI (M) controller is mandatory for all USB applications to interface with the flash memory.
- The I[2] C (M) controller is used for I/O aggregation to interface with platform sensors like temperature sensor.
- The GPIO controller provides access to input (such as DIP switches) and output (LED) wires.
## **2.14.1.8. Camera streaming Modules**
- The image preprocessing block provides the processed image which can be sent to the SoC imaging application. Two possible options are:
- Typical image preprocessing functions provide downscaling and optionally apply digital gain, gamma, and other functions.
- Optional standard ISP IP can be used for reference design to improve the image quality.
- There are two options for USB streaming:
- UVC – This needs the controller IP to convert pixel data to USB video class stream through bulk or isochronous endpoints.
- RAW streaming – this is custom streaming per Host RAW streaming driver requirement through bulk or isochronous endpoints.
- I[2] C primary controller is used as camera sensor programming interface.
- GPIO signal provides power and reset signals for camera sensor.
## **2.14.2. USB RISC-V Firmware Stack and Host Software Interface**
Figure 2.27 shows the RISCV Firmware (FW) stack and the Host Software (SW) interface with boot loader pointer to SPI Flash. The SPI Flash holds the FPGA bitfile (USB APP) and RISCV FW. The FW stack can be bare metal or RTOS-based, with the module in the figure are applicable for corresponding to typical USB application design.
The USB peripheral driver provides the device application layer based on the application.
**==> picture [459 x 268] intentionally omitted <==**
**----- Start of picture text -----**<br>
USB Host<br>Application SW<br>qe<br>USB RISC-V FW<br>LSIO Mod<br>Img Prc Mod HSIO Mod<br>UART Dbg<br>ISP/Img Drv I/O Agg Drv<br>GPIO Drv<br>CSI2 USB3 Device Drv<br>I²C Drv<br>DPHY Drv RAW/UVC Drv<br>SPI Drv<br>SPI Flash<br>RISC-V FW<br>Boot Loader Base FW, ISR, and Timer Scheduler<br>USB App |<br>e ae~ /<br>**----- End of picture text -----**<br>
**Figure 2.27. LIFCL-33U USB RISC-V Host FW Stack**
For more information, refer to USB 2.0/3.2 IP Core User Guide (FPGA-IPUG-02237).
© 2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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**CrossLink-NX-33 and CrossLinkU-NX Data Sheet**
mLATTICE
## **2.15. Device Configuration**
All LIFCL-33/33U devices contain two ports that can be used for device configuration. The Test Access Port (TAP), which supports bit-wide configuration, and the sysCONFIG port, support serial, quad, and byte configuration. The TAP supports both the IEEE Standard 1149.1 Boundary Scan specification and the IEEE Standard 1532 In-System Configuration specification. JTAG_EN is the only dedicated configuration pin. _PPROGRAMN/INITN/DONE_ are enabled by default but can be turned into GPIO. The remaining sysCONFIG pins are used as dual function pins. Refer to sysCONFIG User Guide for Nexus Platform (FPGA-TN-02099) for more information about using the dual-use pins as general purpose I/O.
There are various ways to configure the LIFCL-33/33U devices:
- JTAG (TAP)
- Master Serial Peripheral Interface (SPI) – to load from external SPI flash using x1, x2, or x4 (QSPI) interfaces.
- Inter-Integrated Circuit Bus (I[2] C)
- Improved Inter-Integrated Circuit Bus (I3C)
- Slave SPI from a system host
- Lattice Memory Mapped Interface (LMMI), refer to sysI/O User Guide for Nexus Platform (FPGA-TN-02067) for more details.
- JTAG, SSPI, MSPI, I[2] C, and I3C are supported for VCCIO = 1.8 V - 3.3 V
On power-up, based on the voltage level (high or low) of the PROGRAMN pin, the FPGA SRAM is configured by the appropriate sysCONFIG port. If PROGRAMN pin is _low_ , the FPGA is in Slave configuration mode (Slave SPI, Slave I[2] C, or Slave I3C) and is waiting for the correct Slave Configuration port activation key. PROGRAMN must be driven high within 50 ns of the end of transmission of the Slave Configuration port activation key, that is, the deassertion of SCSN. If no slave port is declared active before the PROGRAMN pin is sensed HIGH, the FPGA is in Master SPI booting mode. In Master SPI booting mode, the FPGA boots from an external SPI flash. Once a configuration port is activated, it remains active throughout that configuration cycle. The IEEE 1149.1 port can be activated any time after power-up by enabling the JTAG_EN pin and sending the appropriate command through the TAP port.
## **2.15.1. Enhanced Configuration Options**
LIFCL-33/33U devices have enhanced configuration features such as:
- Bitstream Decryption
- Decompression Support
- Watchdog Timer support
- Dual and Multi-boot image support
For more details, refer to sysCONFIG User Guide for Nexus Platform (FPGA-TN-02099).
The Watchdog Timer is a new configuration feature that helps the user to add a programmable timer option for timeout applications.
## **Dual-Boot and Multi-Boot Image Support**
Dual-boot and multi-boot images are supported for applications requiring reliable remote updates of configuration data for the system FPGA. After the system is running with a basic configuration, a new boot image can be downloaded remotely and stored in a separate location in the configuration storage device. Any time after the update the LIFCL-33/33U devices can be re-booted from this new configuration file. If there is a problem, such as corrupt data during download or incorrect version number with this new boot image, the LIFCL-33/33U devices can revert to the original backup golden configuration and try again. This all can be done without power cycling the system. For more information, refer to sysCONFIG User Guide for Nexus Platform (FPGA-TN-02099).
© 2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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**CrossLink-NX-33 and CrossLinkU-NX Data Sheet**
mLATTICE
## **2.16. Single Event Upset (SEU) Handling**
The LIFCL-33/33U devices are unique in that the underlying technology used to build these devices is much more robust and less prone to soft errors.
The LIFCL-33/33U devices have an improved, hardware implemented, Soft Error Detection (SED) circuit which can be used to detect SRAM errors so they can be corrected. There are two layers of SED implemented in LIFCL-33/33U devices, making it more robust and reliable.
The SED hardware in LIFCL-33/33U devices is part of the Configuration block. The SED module in LIFCL-33/33U is an enhanced version as compared to the SED modules implemented in other Lattice devices. The configuration data is divided into frames so that the entire FPGA can be programmed precisely with ease. The SED hardware reads data from the FPGAs configuration memory and performs an Error Correcting Code (ECC) calculation on every frame of configuration data (see Figure 2.2). Once an error is detected, a notification is generated and SED resumes operation. For single bit errors, the corrected value is rewritten to the frame using ECC information. If more than one-bit error is detected within one frame of configuration data, an error message is generated. LIFCL-33/33U devices also have dedicated logic to perform Cycle Redundancy Code (CRC) checks for the entire bitstream, which runs in parallel along with ECC.
After the ECC is calculated on all frames of configuration data, CRC is calculated and checked for the entire bitstream. ECC and CRC checks do not include the contents of RAMs (EBR, Large RAM, and distributed RAM).
For further information on SED support, refer to Soft Error Detection (SED)/Correction (SEC) User Guide for Nexus (FPGATN-02076).
## **2.17. On-Chip Oscillator**
The LIFCL-33/33U devices feature two on-chip oscillators. Both Oscillators are controlled with internally generated current.
The low frequency oscillator (LFOSC) is tailored for low power operation and runs at a nominal frequency of 128 kHz. The LFOSC always runs and can be used to perform always on functions with the lowest possible power. The high frequency oscillator (HFOSC) runs at a nominal frequency of 450 MHz but can be divided down to a range of 256 MHz to 2 MHz by user attributes.
For more information, refer to OSC Module User Guide (FPGA-IPUG-02065).
## **2.18. User I²C IP**
The LIFCL-33/33U devices have one hard I[2] C interface, which can be configured either as a master (controller) or a slave (target). The pins for the I²C interface are pre-assigned.
The interface core has the option to delay the either the input or the output data (SDA), or both, by 50 ns nominal, using dedicated on-chip delay elements. This provides an easier interface to any external I[2] C components. In addition, 50 ns glitch filters are available for both SDA and SCL.
When the IP interface is configured as master (controller), it is able to control other devices on the I[2] C bus through the preassigned pins. When the core is configured as a slave (responder), the device is able to provide, for example, I/O expansion to an I²C master (controller). The I²C core supports the following functionality:
- Master (controller) and Slave (target) operation
- 7-bit and 10-bit addressing
- Multi-master (controller) arbitration support
- Clock stretching
- Up to 1 MHz data transfer speed (Standard-Mode, Fast-Mode, Fast-Mode Plus)
- General Call support
- Optional receive and transmit data FIFOs with programmable sizes
- Optionally 50 ns delay on input or output data (SDA), or both
- Hard-Connection and Programmable I/O Connection Support
- Programmable to a mode compliant with I3C requirements on legacy I[2] C Slave Devices.
- Fast-Mode and Fast-Mode Plus Support
- Disabled Clock Stretching
© 2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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**CrossLink-NX-33 and CrossLinkU-NX Data Sheet**
- 50 ns SCL and SDA Glitch Filters
- Programmable 7-bit Address
- For further information on the User I²C, refer to I[2] C Hardened IP User Guide for Nexus Platform (FPGA-TN-02142)
## **2.19. Trace ID**
Each LIFCL-33/33U devices contain a unique (per device) TraceID that can be used for tracking purposes or for IP security applications. The TraceID is 64 bits long. Eight out of 64 bits are user-programmable, the remaining 56 bits are factoryprogrammed. The TraceID is accessible through the SPI, I[2] C, or JTAG interfaces. For further information on TraceID, refer to Using TraceID (FPGA-TN-02084).
## **2.20. Cryptographic Engine**
The LIFCL-33/33U family of devices support several cryptographic features that helps customer secure their design. Some of the key cryptographic features include Advanced Encryption Standard (AES), Hashing Algorithms and true random number generator (TRNG). The LIFCL-33/33U devices also feature bitstream encryption (using AES-256), used for protecting confidential FPGA bitstream data, and bitstream authentication (using ECDSA), which maintains bitstream integrity and protects the FPGA design bitstream from copying and tampering.
The Cryptographic Engine (CRE) is the main engine, which is responsible for the bitstream encryption as well as authentication of the LIFCL-33/33U devices. Once the bitstream is authenticated and the device is ready for user functions, the CRE is available for users to implement various cryptographic functions in the FPGA design. To enable specific cryptographic function, the CRE must be configured by setting a few registers.
The Cryptographic Engine supports the below user-mode features:
- True Random Number generator (TRNG)
- Secure Hashing Algorithm (SHA)-256 bit
- Message authentication codes (MACs) – HMAC
- Lattice Memory Mapped Interface (LMMI) interface to user logic
- High Speed Port (HSP) for FIFO-based streaming data transfer
**==> picture [466 x 151] intentionally omitted <==**
**----- Start of picture text -----**<br>
Cryptographic Engine (CRE)<br>Unique Device Secret<br>Control Register<br>ee<br>LMMI / True Random Number Generator (TRNG)<br>FPGA High Speed Port |<br>CRE Registers<br>Fabric ee ee Advanced Encryption Standard (AES)<br>SHA256<br>Bitstream Encryption<br>HMAC256<br>ge Bitstream Authentication —.<br>|<br>**----- End of picture text -----**<br>
**Figure 2.28. Cryptographic Engine Block Diagram**
© 2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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**CrossLink-NX-33 and CrossLinkU-NX Data Sheet**
## **3. DC and Switching Characteristics for Commercial and Industrial**
All specifications in this chapter are characterized within recommended operating conditions unless otherwise specified.
## **3.1. Absolute Maximum Ratings**
**Table 3.1. Absolute Maximum Ratings**
|**Symbol**<br>~~(GO~~|**Parameter**<br>~~(GO~~|**Min**<br>~~(GO~~|**Max**<br>~~(GO~~|**Unit**<br>~~(GO~~|
|---|---|---|---|---|
|VCC, VCCECLK<br>~~a~~|SupplyVoltage<br>~~ee~~|-0.5|1.10|V|
|VCCAUX, VCCAUXA, VCCAUXH2,<br>VCCAUXH3, VCCAUXH4,<br>VCCAUX_AON5<br>~~a~~|Supply Voltage<br>~~ee~~|-0.5<br>~~GG~~|1.98<br>~~GG~~|V|
|VCCIO0, 1, 5<br>~~a~~<br>~~eC~~|I/O SupplyVoltage<br>~~ee~~<br>~~eC~~|-0.5<br>~~eC~~<br>~~GG~~|3.63<br>~~eC~~<br>~~GG~~|V<br>~~eC~~|
|VCCIO2, 3, 4<br>~~GO~~|I/O SupplyVoltage<br>~~GO~~|-0.5<br>~~GG~~<br>~~GO~~|1.98<br>~~GG~~<br>~~GO~~|V<br>~~GO~~|
|AVDD335<br>~~GO~~<br>~~GC~~|Supply Voltage for Hardened USB5<br>~~GO~~<br>~~GC~~|-0.5<br>~~GO~~<br>~~GC~~|3.63<br>~~GO~~<br>~~GC~~|V<br>~~GO~~<br>~~GC~~|
|AVDD18, AVDD18_TX,<br>AVDD18_COM5<br>~~a~~|Supply Voltage for Hardened USB|-0.5|1.98|V|
|AVDD, AVDD_TX5<br>~~eG~~|Supply Voltage for Hardened USB<br>~~eG~~|-0.5<br>~~eG~~|1.10<br>~~eG~~|V<br>~~eG~~|
|—<br>~~a~~|Input or I/O Voltage Applied, Bank 0, Bank 1,<br>Bank 56|-0.5|3.63|V|
|—<br>~~a~~|Input or I/O Voltage Applied, Bank 2, Bank 3,<br>Bank 4|-0.5<br>~~GC~~|1.98<br>~~GC~~|V|
|TA<br>~~Ge~~|Storage Temperature(Ambient)<br>~~Ge~~|-65<br>~~Ge~~<br>~~GC~~<br>~~GD~~|+150<br>~~Ge~~<br>~~GC~~<br>~~GD~~|°C<br>~~Ge~~|
|TJ<br>~~Ce~~|Junction Temperature<br>~~Ce~~|—<br>~~GC~~<br>~~Ce~~<br>~~GD~~|+125<br>~~GC~~<br>~~Ce~~<br>~~GD~~|°C<br>~~Ce~~|
**Notes** :
1. Stress above those listed under the _Absolute Maximum Ratings_ may cause permanent damage to the device. Functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
2. Compliance with the Lattice Thermal Management document is required.
3. All voltages referenced to GND.
4. All VCCAUX should be connected on PCB.
5. VCCAUX_AON and all AVDD are only supported in LIFCL-33U.
6. Bank 5 is only supported in LIFCL-33.
© 2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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**CrossLink-NX-33 and CrossLinkU-NX Data Sheet**
## **3.2. Recommended Operating Conditions[1, 2, 3]**
**Table 3.2. Recommended Operating Conditions**
|**Symbol**<br>~~pO~~<br>~~a~~|**Parameter**<br>~~pO~~<br>|**Conditions**<br>~~pO~~<br>|**Min**<br>~~pO~~<br>|**Typ. **<br>~~pO~~<br>~~OO~~<br>|**Max**<br>~~pO~~<br>~~OO~~<br>|**Unit**<br>~~pO~~<br>|
|---|---|---|---|---|---|---|
|VCC,VCCECLK<br>~~GG~~<br>~~a~~|Core SupplyVoltage<br>~~GG~~<br>|VCC= 1.0<br>~~GG~~<br>|0.95<br>~~GG~~<br>|1.00<br>~~GG~~<br>~~OO~~<br>|1.05<br>~~GG~~<br>~~OO~~<br>|V<br>~~GG~~<br>|
|VCCAUX<br>~~a~~<br>~~po~~|AuxiliarySupplyVoltage<br>~~CQO~~|Bank 0, Bank 1, Bank 56<br>~~CQO~~|1.71<br>~~CQO~~|1.80<br>~~OO~~<br>~~CQO~~|1.89<br>~~OO~~<br>~~CQO~~|V<br>~~CQO~~|
|VCCAUXH2/3/4<br>~~a ~~<br>~~po~~|AuxiliarySupplyVoltage<br> ~~CQO~~|Bank 2, Bank 3, Bank 4<br>~~CQO~~|1.71<br>~~CQO~~|1.80<br>~~OO~~<br>~~CQO~~|1.89<br>~~OO~~<br>~~CQO~~|V<br>~~CQO~~|
|VCCAUXA,VCCAUX_AON5<br> <br>~~po~~<br>~~a~~|Auxiliary Supply Voltage<br>for core logic and AON<br> ~~CQO~~|—<br>~~CQO~~|1.71<br>~~CQO~~|1.80<br>~~CQO~~|1.89<br>~~CQO~~|V<br>~~CQO~~|
|AVDD335<br>~~a~~|Supply Voltage for<br>Hardened USB5|—|3.135|3.30|3.465|V|
|AVDD18, AVDD18_TX,<br>AVDD18_COM5<br>~~a~~|Supply Voltage for<br>Hardened USB|—|1.71|1.80|1.89|V|
|AVDD, AVDD_TX5<br>~~a~~|Supply Voltage for<br>Hardened USB|—|0.95<br>~~ee~~|1.00|1.05<br>~~ee~~|V<br>~~ee~~|
|VCCIO|I/O Driver Supply Voltage|VCCIO= 3.3 V, Bank 0, Bank 1,<br>Bank 56<br>~~a~~|3.135<br>~~a~~<br>~~ee~~<br>~~e~~~~**e**~~|3.30<br>~~a~~<br>~~eee~~|3.465<br>~~a~~<br>~~ee~~<br>~~eee~~|V<br>~~a~~<br>~~ee~~<br>~~eee~~|
|||VCCIO= 2.5 V, Bank 0, Bank 1,<br>Bank 56<br>~~a~~<br>~~es~~|2.375<br>~~a~~<br>~~ee~~<br>~~es~~<br>~~e~~~~**e**~~|2.50<br>~~a~~<br>~~es~~<br>~~eee~~|2.625<br>~~a~~<br>~~ee~~<br>~~es~~<br>~~eee~~|V<br>~~a~~<br>~~ee~~<br>~~es~~<br>~~eee~~|
|||VCCIO= 1.8 V, All Banks<br>~~es~~<br>~~e~~|1.71<br>~~es~~<br>~~e~~~~**e** ~~<br>~~e~~|1.80<br>~~es~~<br> ~~eee~~|1.89<br>~~es~~<br>~~eee~~|V<br>~~es~~<br>~~eee~~|
|||VCCIO= 1.5 V, All Banks4<br>~~ee~~|1.425<br>~~ee~~|1.50<br>~~ee~~|1.575<br>~~ee~~|V<br>~~ee~~|
|||VCCIO= 1.2 V, All Banks4<br>~~ee~~|1.14<br>~~ee~~|1.20<br>~~ee~~|1.26<br>~~ee~~<br>~~ee~~|V<br>~~ee~~<br>~~ee~~|
|||VCCIO= 1.0 V, Bank 2, Bank 3,<br>Bank 4<br>~~ee~~|0.95<br>~~ee~~|1.00<br>~~ee~~|1.05<br>~~ee~~<br>~~ee~~|V<br>~~ee~~<br>~~ee~~|
|**Operating Temperature**<br>~~ee~~<br>~~pe~~|||||||
|tJCOM<br>~~a~~|Junction Temperature,<br>Commercial Operation|—|0|—|85|°C|
|tJIND<br>~~a~~<br>~~a~~|Junction Temperature,<br>Industrial Operation|—|-40|—|100|°C|
**Notes** :
1. For correct operation, all supplies must be held in their valid operation voltage range.
2. All supplies with same voltage should be from the same voltage source. Proper isolation filters are needed to properly isolate noise from each other.
3. Common supply rails must be tied together.
4. MSPI (Bank0) and JTAG, SSPI, I[2] C, and I3C (Bank 1) ports are supported for VCCIO = 1.8 V to 3.3 V.
5. VCCAUX_AON and all AVDD are only supported in LIFCL-33U.
6. Bank 5 is only supported in LIFCL-33.
© 2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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**CrossLink-NX-33 and CrossLinkU-NX Data Sheet**
## **3.3. Power Supply Ramp Rates[2]**
## **Table 3.3. Power Supply Ramp Rates**
|**Symbol**|**Parameter**|**Min**|**Typ**|**Max**|**Unit**|
|---|---|---|---|---|---|
|tRAMP|Power Supply ramp rates for all supplies1|0.1|—|50|V/ms|
**Notes** :
1. Assumes monotonic ramp rates.
2. All supplies need to be in the operating range as defined in Recommended Operating Conditions, when the device has completed configuration and entering User Mode. Supplies that are not in the operating range needs to be adjusted to faster ramp rate, or users must delay configuration or wake up.
## **3.4. Power up Sequence**
Power-On-Reset (POR) puts the LIFCL-33/33U devices into a reset state. There is no power up sequence required for the LIFCL-33/33U devices.
**Table 3.4. Power-On Reset**
|**Symbol**|**Parameter**|**Parameter**|**Min**|**Typ**|**Max**|**Unit**|
|---|---|---|---|---|---|---|
|VPORUP|Power-On-Reset ramp-up trip point<br>(Monitoring VCC, VCCAUX, VCCI00, and<br>VCCI01)|VCC|0.73|—|0.83|V|
|||VCCAUX|1.34|—|1.62|V|
|||VCCIO0,VCCI01|0.89|—|1.05|V|
|VPORDN|Power-On-Reset ramp-up trip point<br>(Monitoring VCCand VCCAUX)|VCC|0.51|—|0.81|V|
|||VCCAUX|1.38|—|1.59|V|
## **3.5. On-Chip Programmab** l **e Termination**
The LIFCL-33/33U devices support a variety of programmable on-chip terminations options, including:
- Dynamically switchable Single-Ended Termination with programmable resistor values of 40 Ω, 50 Ω, 60 Ω, or 75 Ω.
- Common mode termination of 100 Ω for differential inputs.
**==> picture [202 x 141] intentionally omitted <==**
**----- Start of picture text -----**<br>
V CCIO<br>TERM<br>Zo = 40 , 50 , 60 , or 75<br>control<br>to VCCIO /2<br>Zo<br>Zo +<br>VREF -<br>OFF-chip ON-chip<br>Parallel Single-Ended Input<br>**----- End of picture text -----**<br>
**==> picture [154 x 142] intentionally omitted <==**
**----- Start of picture text -----**<br>
Zo = 50<br>Zo<br>+<br>2Zo -<br>Zo<br>OFF-chip ON-chip<br>Differential Input<br>**----- End of picture text -----**<br>
**Figure 3.1. On-Chip Termination**
See Table 3.5 for termination options for input modes.
© 2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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**CrossLink-NX-33 and CrossLinkU-NX Data Sheet**
mLATTICE
**Table 3.5. On-Chip Termination Options for Input Modes**
|**IO_TYPE**|**Differential Termination Resistor1**|**Terminate to VCCIO/21**|
|---|---|---|
|subLVDS|100, OFF|OFF|
|SLVS|100, OFF|OFF|
|MIPI_DPHY|100|OFF|
|HSTL15D_I|100, OFF|OFF|
|LVCMOS15H|OFF|OFF|
|LVCMOS12H|OFF|OFF|
|LVCMOS10H|OFF|OFF|
|LVCMOS12H|OFF|OFF|
|LVCMOS10H|OFF|OFF|
|LVCMOS18H|OFF|OFF, 40, 50, 60, 75|
|HSTL15_I|OFF|50|
## **Note** :
1. Use of TERMINATE to VCCIO/2 and DIFFERENTIAL TERMINATION RESISTOR are mutually exclusive in an I/O bank. On-chip termination tolerance –10%/+60%.
Refer to sysI/O User Guide for Nexus Platform (FPGA-TN-02067) for on-chip termination usage and value ranges.
## **3.6. Hot Socketing Specifications**
**Table 3.6. Hot Socketing Specifications for GPIO**
|**Symbol**|**Parameter**|**Condition**|**Min**|**Typ**|**Max**|**Unit**|
|---|---|---|---|---|---|---|
|IDK|Input or I/O Leakage Current for<br>Wide Range I/O (excluding<br>MCLK/MCSN/MOSI/INITN/DONE)|0 < VIN< VIH(max)<br>0 < VCC< VCC(max)<br>0 < VCCIO< VCCIO(max)<br>0 < VCCAUX< VCCAUX (max)|-1.5|—|1.5|mA|
**Notes** :
- IDK is additive to IPU, IPD, or IBH.
- Hot socketing specs are defined at a device junction temperature of 85 °C or below. When the device junction temperature is above 85[o] C, the IDK current can exceed the above spec.
- Going beyond the hot socketing ranges specified here will cause exponentially higher Leakage currents and potential reliability issues. A total of 64 mA per 8 I/O should not be exceeded.
## **3.7. ESD Performance**
Refer to the LIFCL-33/33U Product Family Qualification Summary for complete Commercial and Industrial grade qualification data, including ESD performance.
© 2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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**CrossLink-NX-33 and CrossLinkU-NX Data Sheet**
mLATTICE
## **3.8. DC Electrical Characteristics**
**Table 3.7. DC Electrical Characteristics – Wide Range**
|**Symbol**<br>**Parameter**<br>**Condition**<br>**Min**<br>**Typ**<br>**Max**<br>**Unit**<br>~~a GG~~|
|---|
|IIL, IIH1<br>Input or I/O Leakage current<br>(Commercial/Industrial)<br>0 ≤ VIN≤ VCCIO<br>—<br>—<br>10<br>µA<br>~~ee~~|
|IIH2<br>Input or I/O Leakage current<br>VCCIO≤ VIN≤ VIH (max)<br>—<br>—<br>100<br>µA<br>~~aGO~~|
|IPU<br>I/O Weak Pull-upResistor Current<br>0 ≤ VIN≤ 0.7 × VCCIO<br>-30<br>—<br>-150<br>µA<br>~~a~~<br>~~a~~<br>~~G~~|
|IPD<br>I/O Weak Pull-down Resistor<br>Current<br>VIL(max) ≤ VIN≤ VCCIO<br>30<br>—<br>150<br>µA<br>IBHLS<br>Bus Hold Low SustainingCurrent<br>VIN= VIL (max)<br>30<br>—<br>µA<br>IBHHS<br>Bus Hold High SustainingCurrent<br>VIN= 0.7 × VCCIO<br>-30<br>—<br>µA<br>IBHLO<br>Bus hold low Overdrive Current<br>0 ≤ VIN≤ VCCIO<br>—<br>—<br>150<br>µA<br>~~a~~<br>~~a~~<br>~~**a**~~<br>~~Ge~~<br>~~aa~~<br>~~a~~|
|IBHHO<br>Bus hold high Overdrive Current<br>0 ≤ VIN≤ VCCIO<br>—<br>—<br>-150<br>µA<br>~~a~~<br>~~GO~~|
|VBHT<br>Bus Hold TripPoints<br>—<br>VIL(max)<br>—<br>VIH(min)<br>V<br>~~a~~<br>~~a~~<br>~~D~~|
|**Notes**:|
|1.<br>Input or I/O leakage current is measured with the pin configured as an input or as an I/O with the output tristated. Bus Maintenance|
|circuits are disabled.|
|2.<br>The input leakage current IIHis the worst-case input leakage per GPIO when the pad signal is high and also higher than the bank|
|VCCIO. This is considered a mixed mode input.|
|**Table 3.8. DC Electrical Characteristics – High Speed**|
|**Symbol**<br>**Parameter**<br>**Condition**<br>**Min**<br>**Typ**<br>**Max**<br>**Unit**<br>IIL, IIH1<br>Input or I/O Leakage<br>0 ≤ VIN≤ VCCIO<br>—<br>—<br>10<br>µA<br>~~a~~<br>~~eG~~<br>~~C(O~~<br>~~a a~~<br>~~GO~~|
|IPU<br>I/O Weak Pull-upResistor Current<br>0 ≤ VIN≤ 0.7 × VCCIO<br>-30<br>—<br>-150<br>µA<br>~~a~~|
|IPD<br>I/O Weak Pull-down Resistor<br>Current<br>VIL(max) ≤ VIN≤ VCCIO<br>30<br>—<br>150<br>µA|
|IBHLS<br>Bus Hold Low SustainingCurrent<br>VIN= VIL (max)<br>30<br>—<br>—<br>µA<br>IBHHS<br>Bus Hold High SustainingCurrent<br>VIN= 0.7 × VCCIO<br>-30<br>—<br>—<br>µA<br>IBHLO<br>Bus hold low Overdrive Current<br>0 ≤ VIN≤ VCCIO<br>—<br>—<br>150<br>µA<br>~~aeG~~<br>~~CO~~<br>~~aeG~~<br>~~CO~~<br>~~aBG~~|
|IBHHO<br>Bus hold high Overdrive Current<br>0 ≤ VIN≤ VCCIO<br>—<br>—<br>-150<br>µA<br>~~aGC~~|
|VBHT<br>Bus Hold TripPoints<br>—<br>VIL(max)<br>—<br>VIH(min)<br>V<br>~~a~~|
**Note:**
1. Input or I/O leakage current is measured with the pin configured as an input or as an I/O with the output tri-stated. Bus Maintenance circuits are disabled.
**Table 3.9. Capacitors – Wide Range**
|**Symbol**|**Parameter**|**Condition**|**Min**|**Typ**|**Max**|**Unit**|
|---|---|---|---|---|---|---|
|C11|I/O Capacitance1|VCCIO= 3.3 V, 2.5 V, 1.8 V, 1.5 V, 1.2 V,<br>VCC= typ., VIO= 0 to VCCIO+ 0.2V|—|6|—|pF|
|C21|Dedicated Input Capacitance1|VCCIO= 3.3 V, 2.5 V, 1.8 V, 1.5 V, 1.2 V,<br>VCC= typ., VIO= 0 to VCCIO+ 0.2V|—|6|—|pF|
**Note** :
1. TA = 25[o] C, f = 1.0 MHz.
© 2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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**CrossLink-NX-33 and CrossLinkU-NX Data Sheet**
**Table 3.10. Capacitors – High Performance**
**Symbol Parameter Condition Min Typ Max Unit** VCCIO = 1.8 V, 1.5 V, 1.2 V, VCC = typ., C1[1 ] I/O Capacitance[1] — 6 — pF VIO = 0 to VCCIO + 0.2V VCCIO = 1.8 V, 1.5 V, 1.2 V, VCC = typ., C2[1 ] Dedicated Input Capacitance[1] — 6 — pF VIO = 0 to VCCIO + 0.2V VCCA_D-PHY = 1.8 V, VCC = typ., VIO = 0 to C3[1 ] D-PHY I/O Capacitance — 5 — pF V + 0.2V CCA_D-PHY **Note:** 1. TA = 25[o] C, f = 1.0 MHz. **Table 3.11. Single Ended Input Hysteresis – Wide Range IO_TYPE VCCIO TYP Hysteresis** LVCMOS33 3.3 V 250 mV 3.3 V 200 mV LVCMOS25 2.5 V 250 mV LVCMOS18 1.8 V 180 mV LVCMOS15 1.5 V 50 mV LVCMOS12 1.2 V 0 LVCMOS10 1.2 V 0 **Table 3.12. Single Ended Input Hysteresis – High Performance IO_TYPE VCCIO TYP Hysteresis** LVCMOS18H 1.8 V 180 mV 1.8 V 50 mV LVCMOS15H 1.5 V 150 mV LVCMOS12H 1.2 V 0 LVCMOS10H 1.0 V 0 MIPI-LP-RX 1.2 V >25 mV ~~=~~ **3.9. Supply Currents** For estimating and calculating current, use Power Calculator in the Lattice Design software. This operating and peak current is design dependent and can be calculated in the Lattice Design software. Some blocks can be placed into low current standby modes. Refer to Power Management and Calculation for CrossLink-NX Devices (FPGA- ~~[=]~~ TN-02075). © 2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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**CrossLink-NX-33 and CrossLinkU-NX Data Sheet**
mLATTICE
## **3.10. sysI/O Recommended Operating Conditions**
**Table 3.13. sysI/O Recommended Operating Conditions**
|**Standard**<br>~~Po~~|**Support Banks**|**VCCIO(Input)**<br>~~Ef~~|**VCCIO(Output)**<br>~~Ef~~<br>~~_~~|
|---|---|---|---|
|||**Typ.**<br>~~Ef~~<br>~~ee~~|**Typ. **<br>~~Ef~~<br>~~_~~<br>~~ee~~|
|**Single-Ended**<br>~~Po~~<br>~~Ef~~<br>~~_~~<br>~~pT~~<br>~~eGGO~~||||
|LVCMOS33<br>~~pT~~<br>~~eG~~|0, 1, 5<br>~~pT~~<br>~~eG~~|3.3<br>~~pT~~<br>~~GO~~|3.3<br>~~pT~~<br>~~GO~~|
|LVTTL33<br>~~eG~~<br>~~GG~~|0, 1, 5<br>~~eG ~~<br>~~GG~~|3.3<br> ~~GO~~<br>~~GG~~|3.3<br>~~GO~~<br>~~GG~~|
|LVCMOS25¹,²<br>~~GG~~|0, 1, 5<br>~~GG~~|2.5, 3.3<br>~~GG~~|2.5<br>~~GG~~|
|LVCMOS18¹,²<br>~~GG~~|0, 1, 5<br>~~GG~~|1.2, 1.5, 1.8, 2.5, 3.3<br>~~GG~~|1.8<br>~~GG~~|
|LVCMOS18H<br>~~sD~~|2, 3, 4<br>~~sD~~|1.8<br>~~sD~~|1.8<br>~~sD~~|
|LVCMOS15¹,²<br>~~sD~~<br>~~GG~~|0, 1, 5<br>~~sD~~<br>~~GG~~|1.2, 1.5, 1.8, 2.5, 3.3<br>~~sD~~<br>~~GG~~|1.5<br>~~sD~~<br>~~GG~~|
|LVCMOS15H¹<br>~~GG~~<br>~~**G**e~~|2, 3, 4<br>~~GG~~<br>~~e~~|1.5, 1.8<br>~~GG~~<br>~~Ge~~|1.5<br>~~GG~~<br>~~Ge~~|
|LVCMOS12¹,²<br>~~**G**e~~|0, 1, 5<br>~~e~~|1.2, 1.5, 1.8, 2.5, 3.3<br>~~Ge~~|1.2<br>~~Ge~~|
|LVCMOS12H¹<br>~~**G**e~~|2, 3, 4<br>~~e ~~|1.2, 1.35, 1.5, 1.8<br> ~~Ge~~<br>~~G~~|1.2<br>~~Ge~~<br>~~G~~|
|LVCMOS10¹<br>~~sD~~|0, 1, 5<br>~~sD~~|1.2, 1.5, 1.8, 2.5, 3.3<br>~~sD~~|—<br>~~sD~~|
|LVCMOS10H¹<br>~~sD~~<br>~~GG~~|2, 3, 4<br>~~sD~~<br>~~GG~~|1.0, 1.2, 1.35, 1.5, 1.8<br>~~sD~~<br>~~GG~~|1.0<br>~~sD~~<br>~~GG~~|
|LVCMOS10R¹<br>~~GG~~<br>~~**G**e~~|2, 3, 4<br>~~GG~~<br>~~e~~|1.0, 1.2, 1.35, 1.5, 1.8<br>~~GG~~<br>~~Ge~~|—<br>~~GG~~<br>~~Ge~~|
|HSTL15_I3<br>~~**G**e~~|2, 3, 4<br>~~e~~|1.57<br>~~Ge~~|1.57<br>~~Ge~~|
|MIPI D-PHY LP Input6<br>~~**G**e~~|2, 3, 4<br>~~e ~~|1.2<br> ~~Ge~~<br>~~G~~|1.2<br>~~Ge~~<br>~~G~~|
|**Differential6**<br>~~PT~~<br>~~eGGO~~||||
|LVDS<br>~~PT~~<br>~~eG~~|2, 3, 4<br>~~PT~~<br>~~eG~~|1.2, 1.35, 1.5, 1.8<br>~~PT~~<br>~~GO~~|1.8<br>~~PT~~<br>~~GO~~|
|LVDSE5<br>~~eG~~<br>~~GG~~|0, 1, 5<br>~~eG ~~<br>~~GG~~|—<br> ~~GO~~<br>~~GG~~|2.5<br>~~GO~~<br>~~GG~~|
|subLVDS<br>~~GG~~|2, 3, 4<br>~~GG~~|1.2, 1.35, 1.5, 1.8<br>~~GG~~|—<br>~~GG~~|
|subLVDSE5<br>~~Ge~~|0, 1, 5<br>~~Ge~~|—<br>~~Ge~~|1.8<br>~~Ge~~|
|subLVDSEH5<br>~~eG~~|2, 3, 4<br>~~eG~~|—<br>~~eG~~|1.8<br>~~eG~~|
|SLVS6<br>~~GG~~|2, 3, 4<br>~~GG~~|1.0, 1.2, 1.35, 1.5, 1.84<br>~~GG~~|1.2, 1.35, 1.5, 1.84<br>~~GG~~|
|MIPI_DPHY6<br>~~Ge~~|2, 3, 4<br>~~Ge~~|1.2<br>~~Ge~~|1.2<br>~~Ge~~|
|LVCMOS33D5<br>~~Ge~~<br>~~GG~~|0, 1, 5<br>~~Ge~~<br>~~GG~~|—<br>~~Ge~~<br>~~GG~~|3.3<br>~~Ge~~<br>~~GG~~|
|LVTTL33D5<br>~~GG~~<br>~~GG~~<br>~~**G**e~~|0, 1, 5<br>~~GG~~<br>~~GG~~<br>~~e~~|—<br>~~GG~~<br>~~GG~~<br>~~Ge~~|3.3<br>~~GG~~<br>~~GG~~<br>~~Ge~~|
|LVCMOS25D5<br>~~GG~~<br>~~**G**e~~|0, 1, 5<br>~~GG~~<br>~~e~~|—<br>~~GG~~<br>~~Ge~~|2.5<br>~~GG~~<br>~~Ge~~|
|HSTL15D_I5<br>~~**G**e~~|2, 3, 4<br>~~e ~~|—<br> ~~Ge~~<br>~~G~~|1.5<br>~~Ge~~<br>~~G~~|
**Notes** :
1. Single-ended input can mix into I/O Banks with VCCIO different from the standard requires due to some of these input standards use internal supply voltage source (VCC, VCCAUX) to power the input buffer, which makes them to be independent of VCCIO voltage. For more details, please refer to sysI/O User Guide for Nexus Platform (FPGA-TN-02067). The following is a brief guideline to follow:
- a. Weak pull-up on the I/O must be set to OFF.
- b. Bank 2, Bank 3, and Bank 4 I/O can only mix into banks with VCCIO higher than the pin standard, due to clamping diode on the pin in these banks. Bank 0 and Bank 1 does not have this restriction.
- c. LVCMOS25 uses VCCIO supply on input buffer in Bank 0, Bank 1, and Bank 5. It can be supported with VCCIO = 3.3 V to meet the VIH and VIL requirements, but there is additional current drawn on VCCIO. Hysteresis has to be disabled when using 3.3 V supply voltage.
- d. LVCMOS15 uses VCCIO supply on input buffer in Bank 2, Bank 3, and Bank 4. It can be supported with VCCIO = 1.8 V to meet the VIH and VIL requirements, but there is additional current drawn on VCCIO.
2. Single-ended LVCMOS inputs can mixed into I/O Banks with different VCCIO, providing weak pull-up is not used. For additional information on Mixed I/O in Bank VCCIO, refer to sysI/O User Guide for Nexus Platform (FPGA-TN-02067) **.**
3. These inputs use differential input comparator in Bank 2, Bank 3, and Bank 4. The differential input comparator uses VCCAUXH power supply. These inputs require the VREF pin to provide the reference voltage in the Bank. Refer to sysI/O User Guide for Nexus Platform (FPGA-TN-02067) for details **.**
4. All differential inputs use differential input comparator in Bank 2, Bank 3, and Bank 4. The differential input comparator uses VCCAUXH power supply. There is no differential input signaling supported in Bank 0, Bank 1, and Bank 5.
© 2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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**CrossLink-NX-33 and CrossLinkU-NX Data Sheet**
aLATTICE
5. These outputs are emulating differential output pair with single-ended output drivers with true and complement outputs driving on each of the corresponding true and complement output pair pins. The common mode voltage, VCM, is ½ × VCCIO. Refer to sysI/O User Guide for Nexus Platform (FPGA-TN-02067) for details **.**
6. Soft MIPI D-PHY HS using sysI/O is supported with SLVS input and output that can be placed in banks with VCCIO voltage shown in SLVS. D-PHY with HS and LP modes supported needs to be placed in banks with VCCIO voltage = 1.2 V. Soft MIPI D-PHY LP input and output using sysI/O are supported with LVCMOS12.
7. LVCMOS15 input uses VCCIO supply voltage. If VCCIO is 1.8 V, the DC levels for LVCMOS15 are still met, but there could be increase in input buffer current.
## **3.11. sysI/O Single-Ended DC Electrical Characteristics[3]**
**Table 3.14. sysI/O DC Electrical Characteristics – Wide Range I/O**
|**Input/Output**<br>**Standard**<br>~~es~~|**VIL**<br>~~re~~<br>~~es~~|**VIL**<br>~~re~~<br>~~es~~|**VIH**<br>~~re~~<br>~~es~~<br>~~ee~~|**VIH**<br>~~re~~<br>~~es~~<br>~~ee~~|**VOL Max**<br>**(V)**<br>~~es~~<br>~~ee~~|**VOH Min**<br>**(V)**<br>~~es~~|**IOL(mA)**<br>~~es~~|**IOH(mA)**<br>~~es~~|
|---|---|---|---|---|---|---|---|---|
||**Min(V)**<br>~~es~~|**Max(V)**<br>~~es~~|**Min(V)**<br>~~es~~|**Max(V)**<br>~~es~~<br>~~ee~~|||||
|LVTTL33<br>LVCMOS33|—|0.8|2.0|3.4654<br>~~ee~~|0.4<br>~~ee~~|VCCIO– 0.4|2, 4, 8, 12,<br>“50RS”3|-2, -4, -8,<br>-12,<br>“50RS”3|
||||||0.48|VCCIO– 0.52|16|-16|
|LVCMOS25<br>~~a~~|—<br>|0.7<br>|1.7<br>|3.4654<br>|0.4<br>|VCCIO– 0.45<br>~~**a**~~|2, 4, 8,<br>~~ee~~|-2, -4, -8|
|||||||VCCIO– 0.60<br>~~**a**~~<br>|10<br>~~ee~~<br>~~a~~<br>|-10<br>|
|||||||VCCIO– 0.64<br>~~**a**~~<br>|“50RS”3<br>~~ee~~<br>~~a~~<br>|“50RS”3<br>|
|LVCMOS18<br>~~a ~~|—<br> ~~ee~~|0.35 × VCCIO<br>~~ee~~|0.65 × VCCIO<br>~~ee~~|3.4654<br>~~ee~~|0.4<br>~~ee~~|VCCIO– 0.45<br>~~ee~~|2, 4, 8,<br>“50RS”3<br>~~a~~<br>~~ee~~|-2, -4, -8,<br>“50RS”3<br>~~ee~~|
|LVCMOS15<br>~~aa~~|—<br>~~aa~~|0.35 × VCCIO<br>~~aa~~|0.65 × VCCIO<br>~~aa~~|3.4654<br>~~aa~~|0.4|VCCIO– 0.4|2, 4|-2, -4|
|LVCMOS12<br>~~a~~|—<br>~~a~~|0.35 × VCCIO<br>~~a~~|0.65 × VCCIO|3.4654|0.4|VCCIO– 0.4|2, 4|-2, -4|
|LVCMOS10<br>~~a~~<br>~~a~~|—<br>~~a~~<br>~~a~~|0.35 × VCCIO<br>~~a~~<br>~~a~~|0.65 × VCCIO|3.4654|No O/P Support||||
**Notes** :
1. For electro-migration, the average DC current drawn by the I/O pads within a bank of I/O shall not exceed 10 mA per I/O average.
2. For the types of I/O standard supported in which bank, refer to sysI/O User Guide for Nexus Platform (FPGA-TN-02067) for details.
3. Select “50RS” in driver strength is selecting 50 Ω series impedance driver.
4. VIH (MAX) for inputs on these standards (in Bank 0, Bank 1, and Bank 5) can go up to 3.465 V if the input clamp is OFF. Otherwise, the input cannot be higher than VCCIO + 0.3 V.
© 2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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**CrossLink-NX-33 and CrossLinkU-NX Data Sheet**
mtLlLAT TICE
**Table 3.15. sysI/O DC Electrical Characteristics – High Performance I/O[3]**
|**Input/Output**<br>**Standard**<br>~~a~~|**VIL**|**VIL**|**VIH**|**VIH**|**VOL Max**<br>**(V)**|**VOH Min**<br>**(V)**|**IOL (mA)**|**IOH (mA)**|
|---|---|---|---|---|---|---|---|---|
||**Min(V)**<br>~~a~~|**Max(V)**|**Min(V)**|**Max(V)**|||||
|LVCMOS18H<br>~~a~~<br>~~ee~~|—<br>~~a~~<br>~~ee ee~~|0.35 × VCCIO<br>~~ee~~|0.65 × VCCIO<br>~~ee~~|VCCIO+<br>0.3<br>~~es~~|0.4<br>~~ee~~|VCCIO– 0.45<br>~~es ee~~|2, 4, 8, 12,<br>“50RS”3<br>~~ee~~|-2, -4, -8,<br>-12,<br>“50RS”3|
|LVCMOS15H<br>~~ee~~<br>~~a~~|—<br>~~ee ee~~|0.35 × VCCIO<br>~~ee~~<br>~~ee~~|0.65 × VCCIO<br>~~ee~~<br>~~ee~~|VCCIO+<br>0.3<br>~~es~~|0.4<br>~~ee~~<br>~~ee~~|VCCIO– 0.4<br>~~es ee~~<br>~~ee~~|2, 4, 8,<br>“50RS”3<br>~~ee~~<br>~~eee~~|-2, -4, -8,<br>“50RS”3<br>~~eee~~|
|LVCMOS12H<br>~~ee ~~<br>~~a~~<br>~~a~~|—<br> ~~ee ee~~|0.35 × VCCIO<br>~~ee ~~<br>~~ee~~<br>~~ee~~|0.65 × VCCIO<br> ~~ee ~~<br>~~ee~~<br>~~ee~~|VCCIO+<br>0.3<br> ~~es ~~|0.4<br> ~~ee~~<br>~~ee~~<br>~~ee~~|VCCIO– 0.4<br>~~es ee~~<br>~~ee~~<br>~~ee~~|2, 4, 8,<br>“50RS”3<br>~~ee~~<br>~~eee~~<br>~~eee~~|-2, -4, -8,<br>“50RS”3<br>~~eee~~<br>~~eee~~|
|LVCMOS10H<br>~~a~~<br>~~a~~<br>~~a~~|—|0.35 × VCCIO<br>~~ee~~<br>~~ee~~<br>~~ee~~|0.65 × VCCIO<br>~~ee~~<br>~~ee~~<br>~~ee~~|VCCIO+<br>0.3|0.27 ×<br>VCCIO<br>~~ee~~<br>~~ee~~<br>~~ee~~|0.75 × VCCIO<br>~~ee ~~<br>~~ee~~<br>~~ee~~|2, 4<br> ~~eee~~<br>~~eee~~<br>~~eee~~|-2, -4<br>~~eee~~<br>~~eee~~<br>~~eee~~|
|HSTL15_I<br>~~a~~<br>~~a~~|—|VREF– 0.10<br>~~ee~~<br>~~ee~~|VREF+ 0.15<br>~~ee~~<br>~~ee~~|VCCIO+<br>0.3|0.40<br>~~ee~~<br>~~ee~~|VCCIO– 0.40<br>~~ee ~~<br>~~ee~~|8<br> ~~eee~~<br>~~eee~~|–8<br>~~eee~~<br>~~eee~~|
|LVCMOS10R<br>~~a~~<br>~~EE~~|—<br>~~EE~~|VREF– 0.10<br>~~ee~~<br>~~EE~~|VREF+ 0.10<br>~~ee~~<br>~~EE~~|VCCIO+<br>0.3<br>~~EE~~|—<br>~~ee~~<br>~~EE~~|—<br>~~ee ~~<br>~~EE~~|—<br> ~~eee~~<br>~~EE~~|—<br>~~eee~~<br>~~EE~~|
2. For the types of I/O standard supported in which bank, refer to sysI/O User Guide for Nexus Platform (FPGA-TN-02067) for details. 3. Select “50RS” in driver strength is selecting 50 Ω series impedance driver.
**Table 3.16. I/O Resistance Characteristics**
|**Parameter**|**Description**|**Test Conditions**|**Min**|**Typ**|**Max**|**Unit**|
|---|---|---|---|---|---|---|
|50RS|Output Drive Resistance when 50RS<br>Drive Strength Selected|VCCIO= 1.8 V, 2.5 V, or 3.3 V|—|50|—|Ω|
|RDIFF|Input Differential Termination<br>Resistance|Bank 2, Bank 3, and Bank 4 for I/O<br>selected to be differential|—|100|—|Ω|
|SE Input<br>Termination|Input Single Ended Termination<br>Resistance|Bank 2, Bank 3, and Bank 4 for I/O<br>selected to be Single Ended|36|40|64|Ω|
||||46|50|80||
||||56|60|96||
||||67|75|120||
© 2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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**CrossLink-NX-33 and CrossLinkU-NX Data Sheet**
mLATTICE
**Table 3.17. VIN Maximum Overshoot/Undershoot Allowance – Wide Range[1, 2]**
|**AC Voltage Overshoot**|**% of UI at –40 °C to 100 °C**|**AC Voltage Undershoot**|**% of UI at –40 °C to 100 °C**|
|---|---|---|---|
|VCCIO+ 0.4|100.0%|-0.4|100.0%|
|VCCIO+ 0.5|100.0%|-0.5|44.2%|
|VCCIO+ 0.6|94.0%|-0.6|10.1%|
|VCCIO+ 0.7|21.0%|-0.7|1.3%|
|VCCIO+ 0.8|10.2%|-0.8|0.3%|
|VCCIO+ 0.9|2.5%|-0.9|0.1%|
## **Notes:**
1. The peak overshoot or undershoot voltage and the duration above VCCIO + 0.2 V or below GND – 0.2 V must not exceed the values in this table.
2. For UI less than 20 µs.
**Table 3.18. VIN Maximum Overshoot/Undershoot Allowance – High Performance[1, 2]**
|**AC Voltage Overshoot**|**% of UI at –40 °C to 100 °C**|**AC Voltage Undershoot**|**% of UI at –40 °C to 100 °C**|
|---|---|---|---|
|VCCIO+ 0.5|100.0%|-0.5|100.0%|
|VCCIO+ 0.6|47.3%|-0.6|47.3%|
|VCCIO+ 0.7|10.9%|-0.7|10.9%|
|VCCIO+ 0.8|2.7%|-0.8|2.7%|
|VCCIO+ 0.9|0.7%|-0.9|0.7%|
## **Notes:**
1. The peak overshoot or undershoot voltage and the duration above VCCIO + 0.2 V or below GND – 0.2 V must not exceed the values in this table.
2. For UI, less than 20 µs.
## **3.12. sysI/O Differential DC Electrical Characteristics**
## **3.12.1. LVDS**
LVDS input buffer on LIFCL-33/33U is powered by VCCAUX = 1.8 V, and protected by the bank VCCIO. Therefore, the LVDS input voltage cannot exceed the bank VCCIO voltage. LVDS output buffer is powered by the Bank VCCIO at 1.8 V.
LVDS can only be supported in Bank 2, Bank 3, and Bank 4. LVDS25 output can be emulated with LVDS25E in Bank 0, Bank 1, and Bank 5. This is described in LVDS25E (Output Only) section.
**Table 3.19. LVDS DC Electrical Characteristics[1 ]**
|**Parameter**<br>~~a~~|**Description**<br>~~a~~|**Test Conditions**<br>~~GG~~|**Min**<br>~~GG~~|**Typ**|**Max**|**Unit**|
|---|---|---|---|---|---|---|
|VINP, VINM<br>~~a~~<br>~~sO~~|Input Voltage<br>~~a~~<br>~~sO~~|—<br>~~GG~~<br>~~sO~~|0<br>~~GG~~<br>~~sO~~|—<br>~~sO~~|1.603<br>~~sO~~|V<br>~~sO~~|
|VICM<br>~~Ge~~|Input Common Mode Voltage<br>~~Ge~~|Half the sum of the two Inputs<br>~~Ge~~|0.05<br>~~Ge~~|—<br>~~Ge~~|1.552<br>~~Ge~~|V<br>~~Ge~~|
|VTHD<br>~~a~~<br>~~es~~|Differential Input Threshold<br>~~a~~<br>~~eG~~|Difference between the two Inputs<br>~~eG~~|±100<br>~~eG~~|—<br>~~eG~~|—<br>~~eG~~|mV<br>~~eG~~|
|IIN<br>~~a ~~<br>~~es~~<br>~~es~~|Input Current<br> ~~a~~<br>~~eG~~<br>~~Ge~~|Power On or Power Off<br>~~eG~~<br>~~Ge~~|—<br>~~eG~~<br>~~Ge~~|—<br>~~eG~~<br>~~Ge~~|±10<br>~~eG~~<br>~~Ge~~|µA<br>~~eG~~<br>~~Ge~~|
|VOH<br>~~es~~<br>~~es~~|Output High Voltage for VOPor VOM<br>~~eG~~<br>~~Ge~~|RT= 100 Ω<br>~~eG~~<br>~~Ge~~|—<br>~~eG~~<br>~~Ge~~|1.425<br>~~eG~~<br>~~Ge~~|1.60<br>~~eG~~<br>~~Ge~~|V<br>~~eG~~<br>~~Ge~~|
|VOL<br>~~es~~<br>~~Ge~~|Output Low Voltage for VOPor VOM<br>~~Ge~~<br>~~Ge~~|RT= 100 Ω<br>~~Ge~~<br>~~Ge~~|0.9 V<br>~~Ge~~<br>~~Ge~~|1.075<br>~~Ge~~<br>~~Ge~~|—<br>~~Ge~~<br>~~Ge~~|V<br>~~Ge~~<br>~~Ge~~|
|VOD<br>~~Ge~~|Output Voltage Differential<br>~~Ge~~|(VOP- VOM), RT= 100 Ω<br>~~Ge~~|250<br>~~Ge~~|350<br>~~Ge~~|450<br>~~Ge~~|mV<br>~~Ge~~|
|VOD<br>~~a~~|Change in VODBetween High and Low<br>|—<br>|—<br>|—<br>|50<br>|mV<br>|
|VOCM<br>~~aeG~~|Output Common Mode Voltage<br>~~eG~~|(VOP+ VOM)/2, RT= 100 Ω<br>~~eG~~|1.125<br>~~eG~~|1.25<br>~~eG~~|1.375<br>~~eG~~|V<br>~~eG~~|
|VOCM<br>~~eG~~|Change in VOCM, VOCM(MAX)- VOCM(MIN)<br>~~eG~~|—<br>~~eG~~|—<br>~~eG~~|—<br>~~eG~~|50<br>~~eG~~|mV<br>~~eG~~|
|ISAB<br>~~a~~|Output Short Circuit Current|VOD= 0 V Driver outputs shorted to<br>each other|—|—|12|mA|
|VOS<br>~~a~~<br>~~a~~|Change in VOSbetween H and L<br>~~GF~~|—<br>~~GF~~|—<br>~~GF~~|—<br>~~GF~~|50<br>~~GF~~|mV<br>~~GF~~|
© 2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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**CrossLink-NX-33 and CrossLinkU-NX Data Sheet**
a@LATTICE
## **Notes** :
1. LVDS input or output are supported in Bank 2, Bank 3, and Bank 4. LVDS input uses VCCAUX on the differential input comparator and can be in any VCCIO voltage bank. LVDS output uses VCCIO on the differential output driver, and can only be in bank with VCCIO = 1.8 V.
2. VICM is depending on VID, input differential voltage, so the voltage on pin cannot exceed VINP/ INM (min/max) requirements. VICM(min) = VINP/INM(min) + ½ VID, VICM(max) = VINP/INM (max) – ½ VID. Values in the table is based on minimum VID of +/- 100 mV.
3. VINP and VINM (max) must be less than or equal to VCCIO in all cases.
## **3.12.2. LVDS25E (Output Only)**
The top side of the LIFCL-33/33U devices support LVDS25 outputs with emulated complementary LVCMOS outputs in conjunction with a parallel resistor across the driver outputs. The scheme shown in Figure 3.2 is one possible solution for point-to-point signals.
**Table 3.20. LVDS25E DC Conditions**
|**Parameter**<br>~~a~~|**Description**<br>~~a~~<br>~~a~~|**Typical**<br>~~a~~<br>~~a~~|**Unit**<br>~~a~~<br>~~a~~|
|---|---|---|---|
|VCCIO<br>~~a~~|Output Driver Supply (±5%)<br>~~a~~|2.50<br>~~a~~|V<br>~~a~~|
|ZOUT<br>~~a~~<br>~~a~~|Driver Impedance<br>~~a~~<br>~~a~~<br>~~a~~|20<br>~~a~~<br>~~a~~<br>~~a~~|Ω<br>~~a~~<br>~~a~~<br>~~a~~|
|RS<br>~~a~~|Driver Series Resistor (±1%)<br>~~a~~<br>~~a~~|158<br>~~a~~<br>~~a~~|Ω<br>~~a~~<br>~~a~~|
|RP<br>~~a~~<br>~~a~~|Driver Parallel Resistor (±1%)<br>~~a~~<br>~~a~~<br>~~a~~<br>~~a~~|140<br>~~a~~<br>~~a~~<br>~~a~~<br>~~a~~|Ω<br>~~a~~<br>~~a~~<br>~~a~~<br>~~a~~|
|RT<br>~~a~~|Receiver Termination (±1%)<br>~~a~~<br>~~a~~|100<br>~~a~~<br>~~a~~|Ω<br>~~a~~<br>~~a~~|
|VOH<br>~~a~~|Output High Voltage<br>~~a~~<br>~~a~~|1.43<br>~~a~~<br>~~a~~|V<br>~~a~~<br>~~a~~|
|VOL<br>~~a~~|Output Low Voltage<br>~~a~~<br>~~a~~|1.07<br>~~a~~<br>~~a~~|V<br>~~a~~<br>~~a~~|
|VOD<br>~~a~~|Output Differential Voltage<br>~~a~~<br>~~a~~|0.35<br>~~a~~<br>~~a~~|V<br>~~a~~<br>~~a~~|
|VCM<br>~~a~~|Output Common Mode Voltage<br>~~a~~<br>~~a~~|1.25<br>~~a~~<br>~~a~~|V<br>~~a~~<br>~~a~~|
|ZBACK<br>~~a~~|Back Impedance<br>~~a~~<br>~~a~~|100.5<br>~~a~~<br>~~a~~|Ω<br>~~a~~<br>~~a~~|
|IDC<br>~~a~~|DC Output Current|6.03|mA|
VCCIO = 2.5 V (± 5%)
**==> picture [414 x 130] intentionally omitted <==**
**----- Start of picture text -----**<br>
RS = 158<br>(± 1%)<br>8 mA<br>LVCMOS25<br>><br>RP = 140 RT = 100 +<br>VCCIO = 2.5 V (± 5%) -<br>RS = 158 (± 1%) (± 1%)<br>(± 1%)<br>8 mA<br>> LVCMOS25<br>Transmission line, Zo = 100 differential<br>ON-chip OFF-chip OFF-chip ON-chip<br>**----- End of picture text -----**<br>
**Figure 3.2. LVDS25E Output Termination Example**
© 2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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**CrossLink-NX-33 and CrossLinkU-NX Data Sheet**
## **3.12.3. SubLVDS (Input Only)**
SubLVDS is a reduced-voltage form of LVDS signaling, very similar to LVDS. It is a standard used in many camera types of applications. Being similar to LVDS, the LIFCL-33/33U devices can support the subLVDS input signaling with the same LVDS input buffer. The output for subLVDS is implemented in subLVDSE/subLVDSEH with a pair of LVCMOS18 output drivers (see SubLVDSE/SubLVDSEH (Output Only) section).
**Table 3.21. SubLVDS Input DC Electrical Characteristics (Over Recommended Operating Conditions)**
**==> picture [505 x 348] intentionally omitted <==**
**----- Start of picture text -----**<br>
Parameter Description Test Conditions Min Typ Max Unit<br>VID Input Differential Threshold Voltage Over VICM range 70 150 200 mV<br>——_———— VICM Input Common Mode Voltage Half the sum of the two Inputs 0.4 0.9 1.4 [1 ] V<br>Note:<br>1. VICM + 1/2 VID cannot exceed the bank VCCIO in all cases.<br>Sub-LVDS Driver PCB Traces, Connectors or Cables<br>Z0 = 50<br>+ +<br>RT = 100<br>100 differential ± 1%*<br>– –<br>Z0 = 50<br>SSD<br>Off-chip On-chip<br>Figure 3.3. SubLVDS Input Interface<br>3.12.4. SubLVDSE/SubLVDSEH (Output Only)<br>SubLVDS output uses a pair of LVCMOS18 drivers with True and Complement outputs. The VCCIO of the bank used for<br>subLVDSE or subLVDSEH needs to be powered by 1.8V. SubLVDSE is for Bank 0, Bank 1, and Bank 5; and subLVDSEH is for<br>Bank 2, Bank 3, and Bank 4.<br>**----- End of picture text -----**<br>
Performance of the subLVDSE/subLVDSEH driver is limited to the performance of LVCMOS18.
|**Parameter**<br>~~————~~|**Description**<br>~~————~~|**Test Conditions**<br>~~————~~|**Min**<br>~~————~~|**Typ**<br>~~————~~|**Max**<br>~~————~~|**Unit**<br>~~————~~|
|---|---|---|---|---|---|---|
|VOD<br>~~————~~|Output Differential Voltage Swing<br>~~————~~|—<br>~~————~~|—<br>~~————~~|150<br>~~————~~|—<br>~~————~~|mV<br>~~————~~|
|VOCM<br>~~————~~|Output Common Mode Voltage<br>~~————~~|Half the sum of the two Outputs<br>~~————~~|—<br>~~————~~|0.9<br>~~————~~|—<br>~~————~~|V<br>~~————~~|
© 2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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**CrossLink-NX-33 and CrossLinkU-NX Data Sheet**
aLAT TICE
**==> picture [435 x 176] intentionally omitted <==**
**----- Start of picture text -----**<br>
VCCIO = +1.8 V PCB Traces, Connectors or Cables<br>Z0 = 50<br>Rs = 267 ±1%<br>+ +<br>SubLVDS Output<br>SubLVDSE Rp = 121 ±1% 100 differential RT = 100 ±1% Sub-LVDS Recevier<br>SubLVDSEH<br>– –<br>: Rs = 267 ±1% om 3<br>Z0 = 50<br>0<br>On-chip Off-chip On-chip Off-chip<br>**----- End of picture text -----**<br>
**Figure 3.4. SubLVDS Output Interface**
## **3.12.5. SLVS**
Scalable Low-Voltage Signaling (SLVS) is based on a point-to-point signaling method defined in the JEDEC JESD8-13 (SLVS-400) standard. This standard evolved from the traditional LVDS standard with smaller voltage swings and a lower common-mode voltage. The 200 mV (400 mV p-p) SLVS swing contributes to a reduction in power.
The LIFCL-33/33U devices receive SLVS differential input with the LVDS input buffer. This LVDS input buffer is design to cover wide input common mode range that can meet the SLVS input standard specified by the JEDEC standard.
**Table 3.23. SLVS Input DC Characteristics**
|**Parameter**|**Description**|**Test Conditions**|**Min**|**Typ**|**Max**|**Unit**|
|---|---|---|---|---|---|---|
|VID|Input Differential Threshold Voltage|Over VICMrange|70|—|—|mV|
|VICM|Input Common Mode Voltage|Half the sum of the two Inputs|70|200|330|mV|
The SLVS output on LIFCL-33/33U is supported with the LVDS drivers found in Bank 2, Bank 3, and Bank 4. The LVDS driver on LIFCL-33/33U is a current controlled driver. It can be configured as LVDS driver or configured with the 100 Ω differential termination with center-tap set to VOCM at 200 mV. This means the differential output driver can be placed into bank with VCCIO = 1.2 V, 1.5 V, or 1.8 V, even if it is powered by VCCIO.
**Table 3.24. SLVS Output DC Characteristics**
|**Parameter**|**Description**|**Test Conditions**|**Min**|**Typ**|**Max**|**Unit**|
|---|---|---|---|---|---|---|
|VCCIO|Bank VCCIO|—|-5%|1.2,<br>1.5,<br>1.8|+ 5%|V|
|VOD|Output Differential Voltage Swing|—|140|200|270|mV|
|VOCM|Output Common Mode Voltage|Half the sum of the two Outputs|150|200|250|mV|
|ZOS|Single-Ended Output Impedance|—|37.5|50|80|Ω|
© 2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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**CrossLink-NX-33 and CrossLinkU-NX Data Sheet**
aLATaa TICE
**Figure 3.5. SLVS Interface**
## **3.12.6. Soft MIPI D-PHY**
When Soft D-PHY is implemented inside the FPGA logic, the I/O interface needs to use sysI/O buffers to connect to external D-PHY pins.
The LIFCL-33/33U sysI/O provides support for SLVS, as described in SLVS section, plus the LVCMOS12 input / output buffers together to support the High Speed (HS) and Low Power (LP) mode as defined in MIPI Alliance Specification for D-PHY.
To support MIPI D-PHY with SLVS (LVDS) and LVCMOS12, the bank VCCIO cannot be set to 1.5 V or 1.8 V. It has to connect to 1.2 V, or 1.1 V.
All other DC parameters are the same as listed in SLVS section. DC parameters for the LP driver and receiver are the same as listed in LVCMOS12.
© 2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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**CrossLink-NX-33 and CrossLinkU-NX Data Sheet**
**==> picture [400 x 386] intentionally omitted <==**
**----- Start of picture text -----**<br>
LVCMOS12<br>LP Data_P<br>LPenable<br>HSenabl e MIPI Receiver<br>100 Diff<br>+ +<br>HS Data Z0=50<br>- -<br>SLVS<br>LPenable<br>LP Data_N<br>LVCMOS12<br>MIPI_LP_RX<br>On-Chip<br>RXLP_P<br>MIPI Divider<br>+ +<br>HS Data Z0=50<br>- -<br>LVDS<br>MIPI_LP_RX<br>RXLP_N<br>**----- End of picture text -----**<br>
**Figure 3.6. MIPI Interface**
© 2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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**CrossLink-NX-33 and CrossLinkU-NX Data Sheet**
mLATTICE
**Table 3.25. Soft D-PHY Input Timing and Levels**
|**Symbol**<br>~~a a~~|**Description**<br>~~a~~|**Conditions**|**Min**|**Typ**|**Max**|**Unit**|
|---|---|---|---|---|---|---|
|**High Speed(Differential) Input DC Specifications**<br>~~pn~~|||||||
|VCMRX(DC)<br>~~a~~<br>~~ee~~|Common-mode Voltage in High-Speed Mode|—|70|—|330|mV|
|VIDTH<br>~~ee~~|Differential Input HIGH Threshold|—|70|—|—|mV|
|VIDTL<br>~~ee~~<br>~~a~~|Differential Input LOW Threshold<br>~~a~~<br>~~a~~|—|—|—|-70|mV|
|VIHHS<br>~~a~~|Input HIGH Voltage(for HS mode)<br>~~a~~<br>~~a~~|—|—|—|460|mV|
|VILHS<br>~~a ~~<br>~~ee~~|Input LOW Voltage<br> ~~a~~<br>~~a~~|—|-40|—|—|mV|
|VTERM-EN<br>~~ee~~|Single-ended voltage for HS Termination Enable4<br>~~a~~|—|—|—|450|mV|
|ZID<br>~~ee~~<br>~~ee~~|Differential Input Impedance<br>~~a~~<br>~~ee~~|—<br>~~ee~~|80<br>~~ee~~|100<br>~~ee~~|125<br>~~ee~~|Ω<br>~~ee~~|
|**High Speed(Differential) Input AC Specifications**<br>~~ee~~<br>~~pT~~|||||||
|ΔVCMRX(HF)1<br>~~a~~<br>~~ee~~|Common-mode Interference(>450 MHz)|—|—|—|100|mV|
|ΔVCMRX(LF)2, 3<br>~~ee~~|Common-mode Interference(50 MHz - 450 MHz)|—|-50|—|50|mV|
|CCM<br>~~ee~~<br>~~a ~~|Common-mode Termination<br> ~~a~~|—|—|—|60|pF|
|**Low Power(Single-Ended) Input DC Specifications**<br>~~pT~~|||||||
|VIH<br>~~pT~~<br>~~a~~|Low Power Mode Input HIGH Voltage<br>~~pT~~|—<br>~~pT~~|740<br>~~pT~~|—<br>~~pT~~|—<br>~~pT~~|mV<br>~~pT~~|
|VIL<br>~~a ~~|Low Power Mode Input LOW Voltage<br> ~~a~~|—|—|—|480|mV|
|VIL-ULP<br>~~a~~|Ultra Low Power Input LOW Voltage<br>~~a~~<br>~~a~~|—|—|—|300|mV|
|VHYST<br>~~a~~<br>~~a~~|Low Power Mode Input Hysteresis<br>~~a~~<br>~~a~~<br>|—|25|—|—|mV|
|℮SPIKE<br>~~a~~|Input Pulse Rejection<br>~~a~~<br>|—|—|—|300|V∙ps|
|TMIN-RX<br>~~aa~~|Minimum Pulse Width Response<br>~~a~~<br>~~a~~<br>~~a~~|—|20|—|—|ns|
|VINT<br>~~a~~|Peak Interference Amplitude<br>~~a~~<br>~~a~~|—|—|—|200|mV|
|fINT<br>~~a a~~|Interference Frequency<br>~~a~~|—|450|—|—|MHz|
**Notes** :
1. This is peak amplitude of sine wave modulated to the receiver inputs.
2. Input common-mode voltage difference compared to average common-mode voltage on the receiver inputs.
3. Exclude any static ground shift of 50 mV.
4. High Speed Differential RTERM is enabled when both DP and DN are below this voltage.
© 2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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**Table 3.26. Soft D-PHY Output Timing and Levels**
|**Symbol**<br>~~GO~~|**Description**<br>~~GO~~|**Conditions**<br>~~GO~~|**Min**<br>~~GO~~|**Typ**<br>~~GO~~|**Max**<br>~~GO~~|**Unit**<br>~~GO~~|
|---|---|---|---|---|---|---|
|**High Speed(Differential) Output DC Specifications**<br>~~pn~~|||||||
|VCMTX<br>~~CO~~|Common-mode Voltage in High Speed Mode<br>~~CO~~|—<br>~~CO~~|150<br>~~CO~~|200<br>~~CO~~|250<br>~~CO~~|mV<br>~~CO~~|
||ΔVCMTX(1,0)|<br>~~a ee~~<br>~~Re~~|VCMTXMismatch Between Differential HIGH and<br>LOW<br>~~ee~~|—<br>~~ee~~|—<br>~~ee~~|—<br>~~ee~~|5<br>~~ee~~|mV<br>~~ee~~|
||VOD|<br>~~Re~~|Output Differential Voltage||D-PHY-P – D-PHY-N||140|200|270|mV|
||ΔVOD|<br>~~Re~~<br>~~a~~|VODMismatch Between Differential HIGH and<br>LOW<br>|—<br><br>~~CO~~|—<br><br>~~CO~~|—<br><br>~~OO~~|10<br><br>~~OO~~|mV<br>|
|VOHHS<br>~~aee~~|Single-Ended Output HIGH Voltage<br>~~ee~~|—<br>~~ee~~<br>~~CO~~|—<br>~~ee~~<br>~~CO~~|—<br>~~ee~~<br>~~OO~~|360<br>~~ee~~<br>~~OO~~|mV<br>~~ee~~|
|ZOS<br>~~OO~~|Single Ended Output Impedance<br>~~OO~~|—<br>~~CO~~<br>~~OO~~|37.5<br>~~CO~~<br>~~OO~~|50<br>~~OO~~<br>~~OO~~|80<br>~~OO~~<br>~~OO~~|Ω<br>~~OO~~|
|ΔZOS<br>~~DO~~|ZOSmismatch<br>~~DO~~|—<br>~~DO~~|—<br>~~DO~~|—<br>~~DO~~|20<br>~~DO~~|%<br>~~DO~~|
|**High Speed(Differential) Output AC Specifications**<br>~~pC~~<br>~~**e**s~~|||||||
|ΔVCMTX(LF)<br>~~**e**s~~|Common-Mode Variation, 50 MHz–450 MHz|—<br>~~CO~~|—<br>~~CO~~|—<br>~~OO~~|25<br>~~OO~~|mVRMS|
|ΔVCMTX(HF)<br>~~**e**s~~|Common-Mode Variation, above 450 MHz<br>~~e~~|—<br>~~e~~<br>~~CO~~|—<br>~~e~~<br>~~CO~~|—<br>~~e~~<br>~~OO~~|15<br>~~e~~<br>~~OO~~|mVRMS<br>~~e~~|
|tR|Output 20%–80% Rise Time<br>Output 80%–20% Fall Time|0.08 Gbps ≤ tR≤ 1.00<br>Gbps<br>~~CO~~|—<br>~~CO~~<br>~~ee~~|—<br>~~OO~~<br>~~eee~~|0.30<br>~~OO~~<br>~~eee~~|UI<br>~~eee~~|
|||1.00 Gbps < tR≤ 1.50<br>Gbps<br>~~a~~|—<br>~~a~~<br>~~ee~~|—<br>~~a~~<br>~~eee~~|0.35<br>~~a~~<br>~~eee~~|UI<br>~~a~~<br>~~eee~~|
|tF|Output Data Valid After CLK Output|0.08 Gbps ≤ tF≤ 1.00<br>Gbps<br>~~a~~|—<br>~~a~~<br>~~ee ~~<br>~~ee~~|—<br>~~a~~<br> ~~eee~~<br>~~ee~~|0.30<br>~~a~~<br>~~eee~~<br>~~ee~~|UI<br>~~a~~<br>~~eee~~<br>~~ee~~|
|||1.00 Gbps < tF≤ 1.50<br>Gbps<br>~~a~~|—<br>~~a~~<br>~~ee~~|—<br>~~a~~<br>~~ee~~|0.35<br>~~a~~<br>~~ee~~|UI<br>~~a~~<br>~~ee~~|
|**Low Power(Single-Ended) Output DC Specifications**<br>~~a~~<br>~~ee ee~~<br>~~pT~~|||||||
|VOH<br>~~OO~~|Low Power Mode Output HIGH Voltage<br>~~OO~~|0.08 Gbps – 1.5 Gbps<br>~~OO~~|1.07<br>~~OO~~|1.2<br>~~OO~~|1.3<br>~~OO~~|V<br>~~OO~~|
|VOL<br>~~GO~~|Low Power Mode Input LOW Voltage<br>~~GO~~|—<br>~~GO~~|-50<br>~~GO~~|—<br>~~GO~~|50<br>~~GO~~|mV<br>~~GO~~|
|ZOLP<br>~~a~~|Output Impedance in Low Power Mode<br>|—<br>|110<br>|—<br>|—<br>|Ω<br>|
|**Low Power(Single-Ended) Output AC Specifications**<br>~~apT~~|||||||
|tRLP<br>~~pT~~<br>~~OO~~|15%–85% Rise Time<br>~~pT~~<br>~~OO~~|—<br>~~pT~~<br>~~OO~~|—<br>~~pT~~<br>~~OO~~|—<br>~~pT~~<br>~~OO~~|25<br>~~pT~~<br>~~OO~~|ns<br>~~pT~~<br>~~OO~~|
|tFLP<br>~~OO~~<br>~~Rs~~|85%–15% Fall Time<br>~~OO~~<br>|—<br>~~OO~~<br>|—<br>~~OO~~<br>|—<br>~~OO~~<br>|25<br>~~OO~~<br>|ns<br>~~OO~~<br>|
|tREOT<br>~~Rs~~|HS – LP Mode Rise and Fall Time, 30%–85%<br>|—<br>|—<br>|—<br>|35<br>|ns<br>|
|TLP-PULSE-TX<br>~~Rsa~~|Pulse Width of the LP Exclusive-OR Clock<br>~~a ~~|First LP XOR Clock<br>Pulse after STOP State<br>or Last Pulse before<br>STOP State<br>~~eee~~|40<br>~~eee~~|—<br>~~eee~~|—<br>~~eee~~|ns<br>~~eee~~|
|||All Other Pulses<br> ~~eee~~|20<br>~~eee~~|—<br>~~eee~~|—<br>~~eee~~|ns<br>~~eee~~|
|TLP-PER-TX<br>~~OO~~|Period of the LP Exclusive-OR Clock<br>~~OO~~|—<br>~~OO~~|90<br>~~OO~~|—<br>~~OO~~|—<br>~~OO~~|ns<br>~~OO~~|
|CLOAD<br>~~a~~|Load Capacitance<br>~~a~~|—|0|—|70|pF|
**Table 3.27. Soft D-PHY Clock Signal Specification**
|**Symbol**|**Description**|**Conditions**|**Min**|**Typ**|**Max**|**Unit**|
|---|---|---|---|---|---|---|
|**Clock Signal Specification**|||||||
|UI<br>Instantaneous|UIINST|—|—|—|12.5|ns|
|UI Variation|∆UI|—|-10%|—|10%|UI|
|||—|-5%|—|5%|UI|
© 2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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**Table 3.28. Soft D-PHY Data-Clock Timing Specifications**
|**Symbol**<br>~~Ce~~|**Description**<br>~~Ce~~|**Conditions**<br>~~Ce~~<br>~~CGO~~|**Min**<br>~~Ce~~<br>~~CGO~~|**Typ**<br>~~Ce~~<br>~~GO~~|**Max**<br>~~Ce~~|**Unit**<br>~~Ce~~|
|---|---|---|---|---|---|---|
|**Data-Clock Timing Specifications**<br>~~CGO~~<br>~~GO~~<br>~~PF~~|||||||
|TSKEW[TX]<br>~~PF~~|Data to Clock Skew<br>~~PF~~|0.08 Gbps ≤ TSKEW[TX]≤<br>1.00 Gbps<br>~~PF~~|-0.15<br>~~PF~~<br>~~ee~~|—<br>~~PF~~<br>~~ee~~|0.15<br>~~PF~~<br>~~ee~~|UIINST<br>~~PF~~<br>~~ee~~|
|||1.00 Gbps < TSKEW[TX]≤<br>1.50 Gbps<br>~~PF~~<br>~~ee~~|-0.20<br>~~PF~~<br>~~ee~~<br>~~ee~~|—<br>~~PF~~<br>~~ee~~<br>~~ee~~|0.20<br>~~PF~~<br>~~ee~~<br>~~ee~~|UIINST<br>~~PF~~<br>~~ee~~<br>~~ee~~|
|TSKEW[TLIS]<br>~~So~~|Data to Clock Skew<br>~~So~~|0.08 Gbps ≤ TSKEW[TLIS]<br>≤ 1.00 Gbps<br>~~So~~|-0.20<br>~~ee~~<br>~~So~~<br>~~ee~~|—<br>~~ee ~~<br>~~So~~<br>~~ee~~|0.20<br> ~~ee~~<br>~~So~~<br>~~ee~~|UIINST<br>~~ee~~<br>~~So~~<br>~~ee~~|
|||1.00 Gbps < TSKEW[TLIS]<br>≤ 1.50 Gbps<br>~~So~~<br>~~ee~~|-0.10<br>~~So~~<br>~~ee~~<br>~~ee~~|—<br>~~So~~<br>~~ee~~<br>~~ee~~|0.10<br>~~So~~<br>~~ee~~<br>~~ee~~|UIINST<br>~~So~~<br>~~ee~~<br>~~ee~~|
|TSETUP[RX]<br>~~See~~|Input Data Setup Before CLK<br>~~See~~|0.08 Gbps ≤ TSETUP[RX]≤<br>1.00 Gbps<br>~~See~~|0.15<br>~~ee~~<br>~~See~~|—<br>~~ee ~~<br>~~See~~|—<br> ~~ee~~<br>~~See~~|UI<br>~~ee~~<br>~~See~~|
|||1.00 Gbps < TSETUP[RX]≤<br>1.50 Gbps<br>~~See~~<br>~~ee~~|0.20<br>~~See~~<br>~~ee~~|—<br>~~See~~<br>~~ee~~|—<br>~~See~~<br>~~ee~~|UI<br>~~See~~<br>~~ee~~|
|THOLD[RX]<br>~~PE~~|Input Data Hold After CLK<br>~~PE~~|0.08 Gbps ≤ THOLD[RX]≤<br>1.00 Gbps<br>~~PE~~|0.15<br>~~PE~~<br>~~ee~~|—<br>~~PE~~<br>~~ee~~|—<br>~~PE~~<br>~~ee~~|UI<br>~~PE~~<br>~~ee~~|
|||1.00 Gbps < THOLD[RX]≤<br>1.50 Gbps<br>~~PE~~<br>~~ee~~|0.20<br>~~PE~~<br>~~ee~~<br>~~ee~~|—<br>~~PE~~<br>~~ee~~<br>~~ee~~|—<br>~~PE~~<br>~~ee~~<br>~~ee~~|UI<br>~~PE~~<br>~~ee~~<br>~~ee~~|
## **3.12.8. Differential LVCMOS25D, LVCMOS33D, LVTTL33D (Output Only)**
Differential LVCMOS and LVTTL outputs are implemented as a pair of complementary single-ended outputs. All allowable single-ended output drive strengths are supported.
© 2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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## **3.13. Maximum sysI/O Buffer Speed**
Over recommended operating conditions.
**Table 3.29. Maximum I/O Buffer Speed[1, 2, 3, 4, 7 ]**
|**Buffer**<br>~~a~~|**Description**<br>~~a~~|**Banks**<br>~~a~~|**Max**<br>~~a~~|**Unit**<br>~~a~~|
|---|---|---|---|---|
|**Maximum sysI/O Input Frequency**<br>~~pe~~|||||
|**Single-Ended**<br>~~pe~~|||||
|LVCMOS33<br>~~a~~|LVCMOS33, VCCIO= 3.3 V|0, 1, 5|200|MHz|
|LVTTL33<br>~~CG~~|LVTTL33, VCCIO= 3.3 V<br>~~CG~~|0, 1, 5<br>~~CG~~|200<br>~~CG~~|MHz<br>~~CG~~|
|LVCMOS25<br>~~CG~~<br>~~a~~|LVCMOS25, VCCIO= 2.5 V<br>~~CG~~|0, 1, 5<br>~~CG~~|200<br>~~CG~~|MHz<br>~~CG~~|
|LVCMOS185<br>~~a~~|LVCMOS18, VCCIO= 1.8 V|0, 1, 5|200|MHz|
|LVCMOS18H<br>~~a~~|LVCMOS18, VCCIO= 1.8 V|2, 3, 4|200|MHz|
|LVCMOS155<br>~~a~~|LVCMOS15, VCCIO= 1.5 V|0, 1, 5|100|MHz|
|LVCMOS15H5<br>~~a~~|LVCMOS15, VCCIO= 1.5 V|2, 3, 4|150|MHz|
|LVCMOS125<br>~~a~~|LVCMOS12, VCCIO= 1.2 V|0, 1, 5|50|MHz|
|LVCMOS12H5<br>~~CC~~|LVCMOS12, VCCIO= 1.2 V<br>~~CC~~|2, 3, 4<br>~~CC~~|100<br>~~CC~~|MHz<br>~~CC~~|
|LVCMOS105<br>~~CC~~<br>~~a~~|LVCMOS 1.0, VCCIO= 1.2 V<br>~~CC~~|0, 1, 5<br>~~CC~~|50<br>~~CC~~|MHz<br>~~CC~~|
|LVCMOS10H5<br>~~CG~~|LVCMOS 1.0, VCCIO= 1.0 V<br>~~CG~~|2, 3, 4<br>~~CG~~|50<br>~~CG~~|MHz<br>~~CG~~|
|LVCMOS10R<br>~~CG~~<br>~~a~~|LVCMOS 1.0, VCCIOindependent<br>~~CG~~|2, 3, 4<br>~~CG~~|50<br>~~CG~~|MHz<br>~~CG~~|
|HSTL15<br>~~GC~~|HSTL15, VCCIO= 1.5 V<br>~~GC~~|2, 3, 4<br>~~GC~~|250<br>~~GC~~|Mbps<br>~~GC~~|
|MIPI D-PHY (LP Mode)<br>~~a~~|MIPI, Low Power Mode, VCCIO= 1.2 V|2, 3, 4|10|Mbps|
|**Differential8 **<br>~~pT~~|||||
|LVDS<br>~~GG~~|LVDS, VCCIOindependent<br>~~GG~~|2, 3, 4<br>~~GG~~|1250<br>~~GG~~|Mbps<br>~~GG~~|
|subLVDS<br>~~es~~|subLVDS, VCCIOindependent<br>~~es~~|2, 3, 4<br>~~es~~|1250<br>~~es~~|Mbps<br>~~es~~|
|SLVS<br>~~es~~|SLVS similar to MIPI HS, VCCIOindependent<br>~~es~~|2, 3, 4<br>~~es~~|1250<br>~~es~~|Mbps<br>~~es~~|
|MIPI D-PHY (HS Mode)<br>~~es~~|MIPI, High Speed Mode, VCCIO= 1.2 V<br>~~es~~<br>~~D~~|2, 3, 4<br>~~es~~<br>~~D~~|1250<br>~~es~~|Mbps<br>~~es~~|
|HSTL15D<br>~~ee~~|Differential HSTL15, VCCIOindependent<br>~~ee~~<br>~~D~~|2, 3, 4<br>~~ee~~<br>~~D~~|250<br>~~ee~~|Mbps<br>~~ee~~|
|**Maximum sysI/O Output Frequency**<br>~~D~~<br>~~pe~~|||||
|**Single-Ended**<br>~~|~~|||||
|LVCMOS33 (all drive strengths)<br>~~a~~|LVCMOS33, VCCIO= 3.3 V<br>~~a~~|0, 1, 5<br>~~a~~|200<br>~~a~~|MHz<br>~~a~~|
|LVCMOS33 (RS50)<br>~~GG~~|LVCMOS33, VCCIO= 3.3 V, RSERIES= 50 Ω<br>~~GG~~|0, 1, 5<br>~~GG~~|200<br>~~GG~~|MHz<br>~~GG~~|
|LVTTL33 (all drive strengths)<br>~~GG~~<br>~~a~~|LVTTL33, VCCIO= 3.3 V<br>~~GG~~|0, 1, 5<br>~~GG~~|200<br>~~GG~~|MHz<br>~~GG~~|
|LVTTL33 (RS50)<br>~~a~~|LVTTL33, VCCIO= 3.3 V, RSERIES= 50 Ω|0, 1, 5|200|MHz|
|LVCMOS25 (all drive strengths)<br>~~GG~~|LVCMOS25, VCCIO= 2.5 V<br>~~GG~~|0, 1, 5<br>~~GG~~|200<br>~~GG~~|MHz<br>~~GG~~|
|LVCMOS25 (RS50)<br>~~GO~~|LVCMOS25, VCCIO= 2.5 V, RSERIES= 50 Ω<br>~~GO~~|0, 1, 5<br>~~GO~~|200<br>~~GO~~|MHz<br>~~GO~~|
|LVCMOS18 (all drive strengths)<br>~~GO~~<br>~~a~~|LVCMOS18, VCCIO= 1.8 V<br>~~GO~~<br>~~a~~|0, 1, 5<br>~~GO~~<br>~~a~~|200<br>~~GO~~<br>~~a~~|MHz<br>~~GO~~<br>~~a~~|
|LVCMOS18 (RS50)<br>~~a~~<br>~~a~~|LVCMOS18, VCCIO= 1.8 V, RSERIES= 50 Ω<br>~~a~~<br>~~a~~|0, 1, 5<br>~~a~~<br>~~a~~|200<br>~~a~~<br>~~a~~|MHz<br>~~a~~<br>~~a~~|
|LVCMOS18H (all drive strengths)<br>~~GO~~|LVCMOS18, VCCIO= 1.8 V<br>~~GO~~|2, 3, 4<br>~~GO~~|200<br>~~GO~~|MHz<br>~~GO~~|
|LVCMOS18H (RS50)<br>~~GO~~<br>~~a~~|LVCMOS18, VCCIO= 1.8 V, RSERIES= 50 Ω<br>~~GO~~<br>~~a~~|2, 3, 4<br>~~GO~~<br>~~a~~|200<br>~~GO~~<br>~~a~~|MHz<br>~~GO~~<br>~~a~~|
|LVCMOS15 (all drive strengths)<br>~~a~~<br>~~a~~|LVCMOS15, VCCIO= 1.5 V<br>~~a~~<br>~~a~~|0, 1, 5<br>~~a~~<br>~~a~~|100<br>~~a~~<br>~~a~~|MHz<br>~~a~~<br>~~a~~|
|LVCMOS15H (all drive strengths)<br>~~GO~~|LVCMOS15, VCCIO= 1.5 V<br>~~GO~~|2, 3, 4<br>~~GO~~|150<br>~~GO~~|MHz<br>~~GO~~|
|LVCMOS12 (all drive strengths)<br>~~GO~~<br>~~a~~|LVCMOS12, VCCIO= 1.2 V<br>~~GO~~|0, 1, 5<br>~~GO~~|50<br>~~GO~~|MHz<br>~~GO~~|
|LVCMOS12H (all drive strengths)<br>~~GG~~|LVCMOS12, VCCIO= 1.2 V<br>~~GG~~|2, 3, 4<br>~~GG~~|100<br>~~GG~~|MHz<br>~~GG~~|
|LVCMOS10H (all drive strengths)<br>~~GG~~<br>~~a~~|LVCMOS12, VCCIO= 1.2 V<br>~~GG~~|2, 3, 4<br>~~GG~~|50<br>~~GG~~|MHz<br>~~GG~~|
|HSTL15<br>~~CD~~|HSTL15, VCCIO= 1.5 V<br>~~CD~~|2, 3, 4<br>~~CD~~|250<br>~~CD~~|Mbps<br>~~CD~~|
|MIPI D-PHY (LP Mode)<br>~~CD~~<br>~~a~~|MIPI, Low Power Mode, VCCIO= 1.2 V<br>~~CD~~<br>~~a~~|2, 3, 4<br>~~CD~~<br>~~a~~|10<br>~~CD~~<br>~~a~~|Mbps<br>~~CD~~<br>~~a~~|
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
© 2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
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~~a~~ **Buffer Description Banks Max Unit** ~~|~~ **Differential[8 ]** LVDS, VCCIO = 1.8 V USG84 2, 3, 4 1250 Mbps LVDS LVDS, VCCIO = 1.8 V CTG104 2, 3, 4 1500 Mbps ~~aaa ee a~~ LVDS25E[6 ] LVDS25, Emulated, VCCIO = 2.5 V 0, 1, 5 400 Mbps ~~a~~ SubLVDSE[6 ] subLVDS, Emulated, VCCIO = 1.8 V 0, 1, 5 400 Mbps ~~a~~ SubLVDSEH[6 ] subLVDS, Emulated, VCCIO = 1.8 V 2, 3, 4 800 Mbps SLVS similar to MIPI, VCCIO = 1.2 V USG84 2, 3, 4 1250 Mbps SLVS SLVS similar to MIPI, VCCIO = 1.2 V CTG104 2, 3, 4 1500 Mbps ~~_————EE~~ MIPI, High Speed Mode, VCCIO = 1.2 V USG84 2, 3, 4 1250 Mbps MIPI D-PHY (HS Mode) MIPI, High Speed Mode, VCCIO = 1.2 V CTG104 2, 3, 4 1500 Mbps ~~a ee a~~ HSTL15D Differential HSTL15, VCCIO = 1.5 V ~~ee~~ 2, 3, 4 250 Mbps **Notes** :
1. Maximum I/O speed is the maximum switching rate of the I/O operating within the guidelines of the defining standard. The actual interface speed performance using the I/O also depends on other factors, such as internal and external timing.
2. These numbers are characterized but not test on every device.
3. Performance is specified in MHz, as defined in clock rate when the sysI/O is used as pin. For data rate performance, this can be converted to Mbps, which equals to 2 times the clock rate.
4. LVCMOS and LVTTL are measured with load specified in Table 3.42.
5. These LVCMOS inputs can be placed in different VCCIO voltage. Performance may vary. Refer to Lattice Design software.
6. These emulated outputs performance is based on externally properly terminated as described in LVDS25E (Output Only) and SubLVDSE/SubLVDSEH (Output Only).
7. All speeds are measured with fast slew.
8. For maximum differential I/O performance only Differential I/O should be placed in the bottom I/O banks. If this is not possible, the following will impact on maximum performance:
- a. If Fast Slew Rate LVCMOS I/O are used, they should be limited to no more than nine I/O (adjacent), four I/O (same bank), 55 I/O to keep degradation below 50%.
- b. If non-Differential I/O (SLOW SLEW) are placed on the bottom but not within the same bank as differential I/O, then the maximum Differential performance is degraded to 70% of original when 21 aggressors are toggling.
- c. If non-Differential I/O (SLOW SLEW) are placed within the same bank as Differential I/O then the maximum performance is degraded to 50% of original when 16 aggressor are toggling.
- d. No performance impact if MIPI D-PHY LP and MIPI D-PHY HS are in the same bank.
- e. If Differential RX/TX I/O are both placed within the same bank, then the maximum performance is degraded to 90%.
## **3.14. Typical Building Block Function Performance**
These building block functions can be generated using Lattice Design software tool. Exact performance may vary with the device and the design software tool version. The design software tool uses internal parameters that have been characterized but are not tested on every device.
**Table 3.30. Pin-to-Pin Performance**
|**Function**|**Typ. @ VCC =**<br>**1.0 V**|**Unit**|
|---|---|---|
|16-bit Decoder (I/O configured with LVCMOS18, Top Banks)|5.5|ns|
|16-bit Decoder (I/O configured with HSTL15_I, Bottom Banks)|5.1|ns|
|16:1 Mux (I/O configured with LVCMOS18, Top Banks)|6|ns|
|16:1 Mux (I/O configured with HSTL15_I, Bottom Banks)|6.1|ns|
**Note** : These functions are generated using Lattice Radiant Design software tool. Exact performance may vary with the device and the design software tool version. The design software tool uses internal parameters that have been characterized but are not tested on every device.
© 2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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**Table 3.31. Register-to-Register Performance[1, 3, 4]**
|**Function**|**Typ. @ VCC =**<br>**1.0 V**|**Unit**|
|---|---|---|
|**Basic Functions**<br>~~pe~~|||
|16-bit Adder<br>~~a~~|5002<br>~~a~~<br>~~D~~|MHz<br>~~a~~|
|32-bit Adder<br>~~a~~<br>~~ee~~|496<br>~~a~~<br>~~ee~~<br>~~D~~|MHz<br>~~a~~<br>~~ee~~|
|16-bit Counter<br>~~CO~~|402<br>~~D~~<br>~~CO~~|MHz<br>~~CO~~|
|32-bit Counter<br>~~eC~~|371<br>~~eC~~|MHz<br>~~eC~~|
|**Embedded Memory Functions**<br>~~eC~~<br>~~pe~~|||
|512 × 36 Single Port RAM, with Output Register<br>~~a~~|5002<br>~~a~~<br>~~D~~|MHz<br>~~a~~|
|1024 × 18 True-Dual Port RAM using same clock, with EBR Output Registers<br>~~a~~<br>~~ee~~|5002<br>~~a~~<br>~~ee~~<br>~~D~~|MHz<br>~~a~~<br>~~ee~~|
|1024 × 18 True-Dual Port RAM usingasynchronous clocks, with EBR Output Registers<br>~~De~~|5002<br>~~D~~<br>~~De~~|MHz<br>~~De~~|
|**Large Memory Functions**<br>~~pe~~<br>~~G~~|||
|32k × 32 Single Port RAM, with Output Register<br>~~a~~|195<br>~~a~~<br>~~G~~|MHz<br>~~a~~|
|32k × 32 Single Port RAM with ECC, with Output Register<br>~~CO~~|170<br>~~G~~<br>~~CO~~<br>~~D~~|MHz<br>~~CO~~|
|32k × 32 True-Dual Port RAM using same clock, with Output Registers<br>~~CO~~<br>~~a~~|115<br>~~CO~~<br>~~a~~<br>~~D~~|MHz<br>~~CO~~<br>~~a~~|
|**Distributed Memory Functions**<br>~~D~~<br>~~fp~~<br>~~O~~|||
|16 × 4 Single Port RAM (One PFU)<br>~~fp~~<br>~~a~~|5002<br>~~fp~~<br>~~a~~<br>~~O~~|MHz<br>~~fp~~<br>~~a~~|
|16 × 2 Pseudo-Dual Port RAM (One PFU)<br>~~a~~|5002<br>~~O~~<br>~~a~~|MHz<br>~~a~~|
|16 × 4 Pseudo-Dual Port (Two PFUs)<br>~~a~~<br>~~DO~~|5002<br>~~a~~<br>~~DO~~|MHz<br>~~a~~<br>~~DO~~|
|**DSP Functions**<br>~~pe~~|||
|9 × 9 Multiplier with Input Output Registers<br>~~CO~~|376<br>~~CO~~|MHz<br>~~CO~~|
|18 × 18 Multiplier with Input/Output Registers<br>~~Ge~~|287<br>~~Ge~~|MHz<br>~~Ge~~|
|36 × 36 Multiplier with Input/Output Registers<br>~~GO~~|200<br>~~GO~~|MHz<br>~~GO~~|
|MAC 18 × 18 with Input/Output Registers<br>~~a~~|203<br>~~a~~|MHz<br>~~a~~|
|MAC 18 × 18 with Input/Pipelined/Output Registers<br>~~a~~<br>~~ee~~|287<br>~~a~~<br>~~ee~~|MHz<br>~~a~~<br>~~ee~~|
|MAC 36 × 36 with Input/Output Registers<br>~~a~~|119<br>~~a~~|MHz<br>~~a~~|
|MAC 36 × 36 with Input/Pipelined/Output Registers<br>~~a~~<br>~~eG~~|155<br>~~a~~<br>~~eG~~|MHz<br>~~a~~<br>~~eG~~|
1. The Clock port is configured with LVDS I/O type. Performance Grade: 8_High-Performance_1.0V.
2. Limited by the Minimum Pulse Width of the component.
3. These functions are generated using Lattice Radiant Design software tool. Exact performance may vary with the device and the design software tool version. The design software tool uses internal parameters that have been characterized but are not tested on every device.
4. For the Pipelined designs, the number of pipeline stages used are 2.
## **3.15. LMMI**
Table 3.34 summarizes the performance of the LMMI interface with supported IPs. Additional timing requirement and constraint can be identified through the Lattice Radiance design tools.
**Table 3.32. LMMI FMAX Summary**
|**IP**|**FMAX (MHz)**|
|---|---|
|CRE|54|
|I2C|38|
|PLL_LLC|55|
© 2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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## **3.16. Derating Timing Tables**
Logic timing provided in the following sections of this data sheet and the Lattice Radiant design tools are worst case numbers in the operating range. Actual delays at nominal temperature and voltage for best case process, can be much better than the values given in the tables. The Lattice Radiant design tool can provide logic timing numbers at a particular temperature and voltage.
## **3.17. External Switching Characteristics**
Over recommended commercial operating conditions.
**Table 3.33. External Switching Characteristics (VCC = 1.0 V)**
|**Parameter**<br>~~e~~|**Description**<br>~~e~~|**-9**<br>~~e~~~~**e**~~<br>~~ce~~|**-9**<br>~~e~~~~**e**~~<br>~~ce~~|**-8**<br>~~**e**~~<br>~~eeeee~~|**-8**<br>~~**e**~~<br>~~eeeee~~|**-7**<br>~~**e**~~<br>~~eee~~|**-7**<br>~~**e**~~<br>~~eee~~|**Unit**<br>~~**e**~~<br>~~ee~~|
|---|---|---|---|---|---|---|---|---|
|||**Min**<br>~~e~~<br>~~ce~~<br>~~a~~|**Max**<br>~~e~~~~**e**~~<br>~~ce~~|**Min**<br>~~**e**~~<br>~~ee~~|**Max**<br>~~**e**~~<br>~~eee~~<br>~~e~~|**Min**<br>~~**e**~~<br>~~eee~~<br>~~e~~|**Max**<br>~~**e**~~<br>~~eee~~<br>~~e~~||
|**Clocks**<br>~~ce ee eee ee~~<br>~~pT~~|||||||||
|**Primary Clocks**<br>~~pT~~<br>~~pe~~|||||||||
|fMAX_PRI<br>~~po~~|Frequency for Primary Clock<br>~~po~~|—<br>~~po~~|400<br>~~po~~|—<br>~~po~~|325.2<br>~~po~~|—<br>~~po~~|276<br>~~po~~|MHz<br>~~po~~|
|tW_PRI<br>~~po~~<br>~~a~~|Clock Pulse Width for Primary<br>~~po~~<br>~~ee~~|1.125<br>~~po~~<br>~~ee~~|—<br>~~po~~<br>~~ee~~|1.384<br>~~po~~<br>~~ee~~|—<br>~~po~~<br>~~ee~~|1.63<br>~~po~~<br>~~ee~~|—<br>~~po~~<br>~~ee~~|ns<br>~~po~~<br>~~ee~~|
|tSKEW_PRI6<br>~~a~~|Primary Clock Skew Within a<br>Device<br>~~ee~~|—<br>~~ee~~|450<br>~~ee~~|—<br>~~ee~~|554<br>~~ee~~|—<br>~~ee~~|653<br>~~ee~~|ps<br>~~ee~~|
|**Edge Clock**<br>~~a~~<br>~~eeee~~<br>~~|~~|||||||||
|fMAX_EDGE<br>~~po~~|Frequency for Edge Clock Tree<br>~~po~~|—<br>~~po~~|800<br>~~po~~|—<br>~~po~~|650.4<br>~~po~~|—<br>~~po~~|551.7<br>~~po~~|MHz<br>~~po~~|
|tW_EDGE<br>~~po~~|Clock Pulse Width for Edge Clock<br>~~po~~|0.537<br>~~po~~|—<br>~~po~~|0.661<br>~~po~~|—<br>~~po~~|0.779<br>~~po~~|—<br>~~po~~<br>~~GO~~|ns<br>~~po~~|
|tSKEW_EDGE6<br>~~GO~~|Edge Clock Skew Within a Device<br>~~GO~~|—<br>~~GO~~|120<br>~~GO~~|—<br>~~GO~~|148<br>~~GO~~|—<br>~~GO~~|174<br>~~GO~~<br>~~GO~~|ps<br>~~GO~~|
|**Generic SDR Input**<br>~~GO~~<br>~~pT~~|||||||||
|**General I/O Pin Parameters Using Dedicated Primary Clock Input without PLL**<br>~~fp~~|||||||||
|tCO<br>~~fp~~<br>~~po~~|Clock to Output - PIO Output<br>~~fp~~<br>~~po~~|—<br>~~fp~~<br>~~po~~|8.36<br>~~fp~~<br>~~po~~|—<br>~~fp~~<br>~~po~~|8.53<br>~~fp~~<br>~~po~~|—<br>~~fp~~<br>~~po~~|8.67<br>~~fp~~<br>~~po~~|ns<br>~~fp~~<br>~~po~~|
|tSU<br>~~a~~<br>~~a~~|Clock to Data Setup - PIO Input<br>~~GG~~|0<br>~~GG~~|—<br>~~GG~~|0<br>~~GG~~|—<br>~~GG~~<br>~~GO~~|0<br>~~GG~~<br>~~GO~~|—<br>~~GG~~|ns|
|tH<br>~~a~~<br>~~GG~~<br>~~a~~|Clock to Data Hold - PIO Input<br>~~GG~~<br>~~GG~~|3.73<br>~~GG~~<br>~~GG~~|—<br>~~GG ~~<br>~~GG~~|3.83<br> ~~GG~~<br>~~GG~~|—<br>~~GG~~<br>~~GG~~<br>~~GO~~|3.93<br>~~GG~~<br>~~GG~~<br>~~GO~~|—<br>~~GG~~<br>~~GG~~|ns<br>~~GG~~|
|tSU_DEL<br>~~a~~|Clock to Data Setup - PIO Input<br>~~GG~~|1.84<br>~~GG~~|—<br>~~GG~~|1.84<br>~~GG~~|—<br>~~GO~~<br>~~GG~~<br>~~GO~~|1.84<br>~~GO~~<br>~~GG~~<br>~~GO~~|—<br>~~GG~~|ns|
|tH_DEL(Top)<br>~~a~~<br>~~GG~~|Clock to Data Hold - PIO Input<br>~~GG~~<br>~~GG~~|0.22<br>~~GG~~<br>~~GG~~|—<br>~~GG ~~<br>~~GG~~|0.22<br> ~~GG~~<br>~~GG~~|—<br>~~GO~~<br>~~GG~~<br>~~GG~~<br>~~GO~~|0.22<br>~~GO~~<br>~~GG~~<br>~~GG~~<br>~~GO~~|—<br>~~GG~~<br>~~GG~~|ns<br>~~GG~~|
|tH_DEL(Bottom)|Clock to Data Hold - PIO Input<br>Register with Data Input Delay|1.77|—|1.77|—<br>~~GO~~|1.77<br>~~GO~~|—|ns|
|**General I/O Pin Parameters Using Dedicated Primary Clock Input with PLL**<br>~~fp~~|||||||||
|tCOPLL<br>~~fp~~<br>~~po~~<br>~~po~~|Clock to Output - PIO Output<br>~~fp~~<br>~~po~~<br>|—<br>~~fp~~<br>~~po~~<br>|4.55<br>~~fp~~<br>~~po~~<br>|—<br>~~fp~~<br>~~po~~<br>|4.67<br>~~fp~~<br>~~po~~<br>|—<br>~~fp~~<br>~~po~~<br>|5.51<br>~~fp~~<br>~~po~~<br>|ns<br>~~fp~~<br>~~po~~<br>|
|tSUPLL(Top)<br>~~po~~|Clock to Data Setup - PIO Input<br>|1.54<br>|—<br>|1.54<br>|—<br>|1.54<br>|—<br>|ns<br>|
|tH_DEL(Bottom)<br>~~popo~~|Clock to Data Setup - PIO Input<br>~~po~~|1.33<br>~~po~~|—<br>~~po~~|1.33<br>~~po~~|—<br>~~po~~|1.33<br>~~po~~|—<br>~~po~~|ns<br>~~po~~|
|tHPLL<br>~~pO~~<br>~~po~~|Clock to Data Hold - PIO Input<br>~~pO~~<br>|0.98<br>~~pO~~<br>|—<br>~~pO~~<br>|1.21<br>~~pO~~<br>|—<br>~~pO~~<br>~~GO~~<br>|1.42<br>~~pO~~<br>~~GO~~<br>|—<br>~~pO~~<br>|ns<br>~~pO~~<br>|
|tSU_DELPLL<br>~~pO~~<br>~~GG~~<br>~~po~~|Clock to Data Setup - PIO Input<br>~~pO~~<br>~~GG~~<br>|4.74<br>~~pO~~<br>~~GG~~<br>|—<br>~~pO~~<br>~~GG~~<br>|4.74<br>~~pO~~<br>~~GG~~<br>|—<br>~~pO~~<br>~~GG~~<br>~~GO~~<br>|4.74<br>~~pO~~<br>~~GG~~<br>~~GO~~<br>|—<br>~~pO~~<br>~~GG~~<br>|ns<br>~~pO~~<br>~~GG~~<br>|
|tH_DELPLL<br>~~po~~|Clock to Data Hold - PIO Input<br>|0.00<br>|—<br>|0<br>|—<br>~~GO~~<br>|0<br>~~GO~~<br>|—<br>|ns<br>|
|**Generic DDR Input/Output**<br>~~GO~~<br>~~popT~~|||||||||
|**Generic DDRX1 Inputs/Outputs with Clock and Data Centered at Pin(GDDRX1_RX/TX.SCLK.Centered) using PCLK Clock Input –**<br>~~fp~~<br>~~ee~~<br>~~esne~~<br>~~ee~~|||||||||
|tSU_GDDR1<br>~~fp~~<br>~~ee~~<br>~~po~~|Input Data Setup Before CLK<br>~~fp~~<br>~~es~~|0.917<br>~~fp~~<br>~~es~~|—<br>~~fp~~<br>~~ne~~|0.917<br>~~fp~~<br>~~ne~~|—<br>~~fp~~|0.917<br>~~fp~~<br>~~ee~~|—<br>~~fp~~<br>~~ee~~|ns<br>~~fp~~<br>~~ee~~|
|||0.275<br>~~es~~<br>~~a~~|—<br>~~ne~~|0.275<br>~~ne~~|—|0.275<br>~~ee~~|—<br>~~ee~~|UI<br>~~ee~~|
|tHO_GDDR1<br>~~ee~~<br>~~poa~~|Input Data Hold After CLK<br>~~es~~<br>~~_——————————EE~~|0.917<br>~~es ~~<br>~~a~~<br>~~_——————————EE~~|—<br> ~~ne~~<br>~~_——————————EE~~|0.917<br>~~ne~~<br>~~_——————————EE~~|—<br>~~_——————————EE~~|0.917<br>~~ee~~<br>~~_——————————EE~~|—<br>~~ee~~<br>~~_——————————EE~~|ns<br>~~ee~~<br>~~_——————————EE~~|
|tDVB_GDDR1<br>~~poa~~|Output Data Valid After CLK<br>Output<br>~~_——————————EE~~|1.134<br>~~a~~<br>~~_——————————EE~~|—<br>~~_——————————EE~~|1.113<br>~~_——————————EE~~|—<br>~~_——————————EE~~|1.014<br>~~_——————————EE~~|—<br>~~_——————————EE~~|ns<br>~~_——————————EE~~|
|||-0.533<br>~~_——————————EE~~<br>~~a~~|—<br>~~_——————————EE~~|-0.554<br>~~_——————————EE~~|—<br>~~_——————————EE~~|-0.653<br>~~_——————————EE~~|—<br>~~_——————————EE~~|ns + 1/2 UI<br>~~_——————————EE~~|
|tDQVA_GDDR1<br>~~a~~<br>~~a~~|Output Data Valid After CLK<br>Output<br>~~_——————————EE~~<br>~~ee~~|1.217<br>~~_——————————EE~~<br>~~a~~<br>~~ee~~|—<br>~~_——————————EE~~<br>~~eee~~|1.113<br>~~_——————————EE~~<br>~~eee~~|—<br>~~_——————————EE~~<br>~~eee~~|1.014<br>~~_——————————EE~~<br>~~eee~~|—<br>~~_——————————EE~~<br>~~eee~~|ns<br>~~_——————————EE~~<br>~~eee~~|
|||-0.45<br>~~ee ~~<br>~~a ~~|—<br> ~~eee~~<br> ~~ee~~|-0.554<br>~~eee~~<br>~~ee~~|—<br>~~eee~~<br>~~ee~~|-0.653<br>~~eee~~<br>~~ee~~|—<br>~~eee~~<br>~~ee~~|ns + 1/2 UI<br>~~eee~~<br>~~ee~~|
© 2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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|**Parameter**<br>~~J~~|**Description**<br>~~J~~|**-9**<br>~~aee~~|**-9**<br>~~aee~~|**-8**<br>~~ee~~<br>~~ee~~|**-8**<br>~~ee~~<br>~~ee~~|**-7**<br>~~ee~~<br>~~ee~~|**-7**<br>~~ee~~<br>~~ee~~|**Unit**|
|---|---|---|---|---|---|---|---|---|
|||**Min**<br>~~a~~|**Max**<br>~~ee~~|**Min**<br>~~ee~~|**Max**<br>~~ee~~<br>~~ee~~|**Min**<br>~~ee~~<br>~~ee~~|**Max**<br>~~ee~~||
|fDATA_GDDRX1<br>~~J~~<br>~~pO~~|Input/Output Data Rate<br>~~J~~<br>~~pO~~|—<br>~~a~~<br>~~pO~~<br>~~GOO~~|300<br>~~ee~~<br>~~pO~~<br>~~GOO~~|—<br>~~ee~~<br>~~pO~~<br>~~GOO~~|300<br>~~ee~~<br>~~ee ~~<br>~~pO~~<br>~~GOO~~|—<br>~~ee~~<br> ~~ee~~<br>~~pO~~<br>~~GO~~|300<br>~~ee~~<br>~~pO~~<br>~~GO~~|Mbps<br>~~pO~~|
|fMAX_GDDRX1<br>~~ee~~|Frequency of PCLK<br>~~ee~~|—<br>~~ee~~<br>~~GOO~~|150<br>~~ee~~<br>~~GOO~~|—<br>~~ee~~<br>~~GOO~~|150<br>~~ee~~<br>~~GOO~~|—<br>~~ee~~<br>~~GO~~|150<br>~~ee~~<br>~~GO~~|MHz<br>~~ee~~|
|½ UI<br>~~ee~~<br>~~pO~~|Half of Data Bit Time, or 90<br>~~ee~~<br>~~pO~~|1.667<br>~~ee~~<br>~~GOO~~<br>~~pO~~|—<br>~~ee~~<br>~~GOO~~<br>~~pO~~|1.667<br>~~ee~~<br>~~GOO~~<br>~~pO~~|—<br>~~ee~~<br>~~GOO~~<br>~~pO~~|1.667<br>~~ee~~<br>~~GO~~<br>~~pO~~|—<br>~~ee~~<br>~~GO~~<br>~~pO~~|ns<br>~~ee~~<br>~~pO~~|
|Output TX to Input RX Margin per Edge<br>~~OO~~||0.3<br>~~OO~~|—<br>~~OO~~|0.197<br>~~OO~~|—<br>~~OO~~|0.097<br>~~OO~~|—<br>~~OO~~|ns<br>~~OO~~|
|**Generic DDRX1 Inputs/Outputs with Clock and Data Aligned at Pin (GDDRX1_RX/TX.SCLK.Aligned) using PCLK Clock Input – Bank 0,**<br>**Bank 1 and Bank 5 –Figure 3.8andFigure 3.10**<br>~~OO~~|||||||||
|tDVA_GDDR1<br>~~OO~~|Input Data Valid After CLK<br>~~OO~~|—<br>~~OO~~<br>~~a~~<br>~~a~~|-0.917<br>~~OO~~|—<br>~~OO~~|-0.917<br>~~OO~~|—<br>~~OO~~|-0.917<br>~~OO~~|ns + 1/2 UI<br>~~OO~~<br>~~ee~~|
|||—<br>~~a ee~~<br>~~a~~|0.75<br>~~ee~~|—<br>~~ee~~|0.75<br>~~ee~~|—<br>~~ee~~|0.75<br>~~ee~~|ns<br>~~ee~~<br>~~ee~~|
|||—<br>~~a~~|0.225<br>~~a~~|—|0.225|—|0.225|UI<br>~~ee~~|
|tDVE_GDDR1|Input Data Hold After CLK|0.917<br>~~a ~~|—<br> ~~ee~~|0.917<br>~~ee~~|—<br>~~ee~~|0.917<br>~~ee~~|—<br>~~ee~~|ns + 1/2 UI<br>~~ee~~|
|||2.583<br>~~a~~<br>|—<br>~~ee~~|2.583<br>~~ee~~|—<br>~~ee~~|2.583|—|ns|
|||0.775<br>~~a ~~|—<br> ~~ee~~|0.775<br>~~ee~~|—<br>~~ee~~|0.775|—|UI|
|tDIA_GDDR1<br>~~pO~~|Output Data Invalid After CLK<br>~~pO~~|—<br> <br>~~pO~~|0.554<br> ~~ee~~<br>~~pO~~|—<br>~~ee ~~<br>~~pO~~|0.554<br> ~~ee~~<br>~~pO~~|—<br>~~pO~~|0.653<br>~~pO~~|ns<br>~~pO~~|
|tDIB_GDDR1<br>~~pO~~<br>~~pO~~|Output Data Invalid Before CLK<br>~~pO~~|—<br>~~pO~~|0.45<br>~~pO~~|—<br>~~pO~~|0.554<br>~~pO~~|—<br>~~pO~~<br>~~GO~~|0.653<br>~~pO~~<br>~~GO~~|ns<br>~~pO~~|
|fDATA_GDDRX1<br>~~GG~~<br>~~pO~~|Input/Output Data Rate<br>~~GG~~|—<br>~~GG~~|300<br>~~GG~~|—<br>~~GG~~|300<br>~~GG~~|—<br>~~GG~~<br>~~GO~~|300<br>~~GG~~<br>~~GO~~|Mbps<br>~~GG~~|
|fMAX_GDDRX1<br>~~GG~~<br>~~pO~~<br>~~es~~<br>~~GG~~|Frequency for PCLK<br>~~GG~~<br>~~GG~~<br>~~GG~~|—<br>~~GG~~<br>~~GG~~<br>~~GG~~|150<br>~~GG~~<br>~~GG~~<br>~~GG~~|—<br>~~GG~~<br>~~GG~~<br>|150<br>~~GG~~<br>~~GG~~<br>|—<br>~~GG~~<br>~~GO~~<br>~~GG~~<br>~~GO~~<br>|150<br>~~GG~~<br>~~GO~~<br>~~GG~~<br>~~GO~~<br>|MHz<br>~~GG~~<br>~~GG~~|
|½ UI<br>~~pO~~<br>~~es~~<br>~~GG~~|Half of Data Bit Time, or 90 degree<br>~~GG~~<br>~~GG~~|1.667<br>~~GG~~<br>~~GG~~|—<br>~~GG~~<br>~~GG~~|1.667<br>~~GG~~<br>|—<br>~~GG~~<br>|1.667<br>~~GO~~<br>~~GG~~<br>~~GO~~<br>|—<br>~~GO~~<br>~~GG~~<br>~~GO~~<br>|ns<br>~~GG~~|
|Output TX to Input RX Margin per Edge<br>~~esGG~~<br>~~GG~~||0.3<br>~~GG~~<br>~~GG~~|—<br>~~GG~~<br>~~GG ~~|0.197<br>~~GG~~<br> ~~GG~~|—<br>~~GG~~<br>~~GG~~|0.097<br>~~GG~~<br>~~GO~~<br>~~GG~~|—<br>~~GG~~<br>~~GO~~<br>~~GG~~|ns<br>~~GG~~|
|**Generic DDRX1 Inputs/Outputs with Clock and Data Centered at Pin (GDDRX1_RX/TX.SCLK.Centered) using PCLK Clock Input –**<br>**Bank 2, Bank 3, and Bank 4 –Figure 3.7and Figure 3.9**<br>~~———<—————~~|||||||||
|tSU_GDDR1<br>~~———<—————~~<br>~~a~~|Input Data Setup Before CLK<br>~~———<—————~~<br>|0.917<br>~~———<—————~~|—<br>~~———<—————~~|0.917<br>~~———<—————~~|—<br>~~———<—————~~|0.917<br>~~———<—————~~|—<br>~~———<—————~~|ns<br>~~———<—————~~|
|||0.275<br>~~———<—————~~<br>~~a~~<br>|—<br>~~———<—————~~<br>~~a~~<br>|0.275<br>~~———<—————~~<br>|—<br>~~———<—————~~<br>|0.275<br>~~———<—————~~<br>|—<br>~~———<—————~~<br>|UI<br>~~———<—————~~<br>|
|tHO_GDDR1<br>~~a~~|Input Data Hold After CLK<br>|0.917<br>~~a~~<br>|—<br>~~a~~<br>|0.917<br>|—<br>|0.917<br>|—<br>|ns<br>|
|fDATA_IN_GDDRX1<br>~~aeG~~<br>~~oo~~|Input Data Rate<br>~~eG~~|—<br>~~a ~~<br>~~eG~~<br>~~a~~|300<br> ~~a~~<br>~~eG~~<br>~~ee~~|—<br>~~eG~~<br>~~ee~~|300<br>~~eG~~|—<br>~~eG~~|300<br>~~eG~~|Mbps<br>~~eG~~|
|tDVB_GDDR1<br>~~oo~~|Output Data Valid After CLK<br>Output|0.670<br>~~a~~|~~ee~~|0.631<br>~~ee~~|—|0.744|—|ns|
|||-0.330<br>~~a~~|—<br>~~ee~~|-0.369<br>~~ee~~|—|-0.435|—|ns + 1/2 UI|
|tDQVA_GDDR1<br>~~oo~~<br>~~—~~<br>~~a~~|Output Data Valid After CLK<br>Output<br>~~—~~|0.7<br>~~a~~<br>~~a~~|—<br>~~ee~~|0.631<br>~~ee~~|—|0.744|—|ns|
|||-0.300<br>~~a ~~<br>~~a~~|—<br> ~~ee~~|-0.369<br>~~ee~~|—|-0.435<br>~~GO~~|—<br>~~GO~~|ns + 1/2 UI|
|fDATA_OUT_GDDRX1<br>~~GG~~<br>~~a~~|Output Data Rate<br>~~GG~~|—<br>~~GG~~|500<br>~~GG~~|—<br>~~GG~~|500<br>~~GG~~|—<br>~~GG~~<br>~~GO~~|424<br>~~GG~~<br>~~GO~~|Mbps<br>~~GG~~|
|fMAX_GDDRX1<br>~~GG~~<br>~~a~~<br>~~es~~|Frequency of PCLK<br>~~GG~~<br>~~GG~~<br>|—<br>~~GG~~<br>~~GG~~<br>|250<br>~~GG~~<br>~~GG~~<br>|—<br>~~GG~~<br>~~**G**~~<br>|250<br>~~GG~~<br>~~**G**G~~|—<br>~~GG~~<br>~~GO~~<br>~~G~~<br>~~OO~~|212<br>~~GG~~<br>~~GO~~<br>~~G~~<br>~~OO~~|MHz<br>~~GG~~|
|½ UI<br>~~es~~|Half of Data Bit Time, or 90 degree<br>~~GG~~<br>~~G~~|1<br>~~GG~~<br>~~G~~|—<br>~~GG~~<br>~~G~~|1<br>~~**G**~~<br>~~G~~|—<br>~~**G**G~~|1.179<br>~~G~~<br>~~OO~~|—<br>~~G~~<br>~~OO~~|ns|
|Output TX to Input RX Margin per Edge<br>~~GG~~<br>~~esG~~<br>~~rs~~||0.15<br>~~GG~~<br>~~G~~<br>~~rs~~|—<br>~~GG ~~<br>~~G~~<br>~~rs~~|0.081<br> ~~**G**~~<br>~~G~~<br>~~rs~~|—<br>~~**G**G~~<br>~~rs~~|0.095<br>~~G~~<br>~~OO~~<br>~~rs~~|—<br>~~G~~<br>~~OO~~<br>~~rs~~|ns<br>~~rs~~|
|**Generic DDRX1 Inputs/Outputs with Clock and Data Aligned at Pin (GDDRX1_RX/TX.SCLK.Aligned) using PCLK Clock Input – Bank 2,**<br>**Bank 3, and Bank 4 –Figure 3.8andFigure 3.10**<br>~~rs~~|||||||||
|tDVA_GDDR1|Input Data Valid After CLK|—<br>~~a~~<br>~~es~~|-0.917<br>~~ee~~|—<br>~~ee~~|-0.917<br>~~ee~~|—<br>~~ee~~|-0.917|ns + 1/2 UI|
|||—<br>~~a~~<br>~~es~~<br>~~a~~|0.75<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~|0.75<br>~~ee~~|—<br>~~ee~~|0.75|ns|
|||—<br>~~es ~~<br>~~a~~<br>~~es~~|0.225<br> ~~ee~~<br>~~ee~~<br>~~ee~~|—<br>~~ee ~~<br>~~ee~~<br>~~ee~~|0.225<br> ~~ee ~~<br>~~ee~~|—<br> ~~ee~~|0.225|UI|
|tDVE_GDDR1<br>~~a~~|Input Data Hold After CLK<br>|0.917<br>~~a~~<br>~~es~~<br>~~a~~|—<br>~~ee~~<br>~~ee~~<br>~~ee~~|0.917<br>~~ee~~<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~es~~|0.917|—|ns + 1/2 UI|
|||2.583<br>~~es ~~<br>~~a~~<br>~~ee~~<br>|—<br> ~~ee ~~<br>~~ee~~<br>~~ee~~<br>|2.583<br> ~~ee ~~<br>~~ee~~<br>~~ee ee~~<br>|—<br> ~~ee~~<br>~~es~~<br>~~ee~~<br>|2.583<br>|—<br>|ns<br>|
|||0.775<br>~~a~~<br>~~ee~~<br>|—<br>~~ee~~<br>~~ee~~<br>|0.775<br>~~ee ~~<br>~~ee ee~~<br>|—<br> ~~es~~<br>~~ee~~<br><br>~~GO~~|0.775<br><br>~~GO~~|—<br><br>~~GO~~|UI<br>|
|fDATA_IN_GDDRX1<br>~~a ~~|Input Data Rate<br> ~~GGG~~|—<br>~~ee ~~<br>~~GGG~~|300<br> ~~ee ~~<br>~~GGG~~|—<br> ~~ee ee~~<br>~~GGG~~|300<br>~~ee~~<br>~~GGG~~<br>~~GO~~|—<br>~~GGG~~<br>~~GO~~|300<br>~~GGG~~<br>~~GO~~|Mbps<br>~~GGG~~|
|tDIA_GDDR1|Output Data Invalid After CLK<br>Output|—|0.3|—|0.369<br>~~GO~~|—<br>~~GO~~|0.435<br>~~GO~~|ns|
|tDIB_GDDR1|Output Data Invalid Before CLK<br>Output|—|0.3|—|0.369|—|0.435|ns|
© 2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02104-1.0
70
**CrossLink-NX-33 and CrossLinkU-NX Data Sheet**
mLATTICE
|**Parameter**<br>**Description**<br>**-9**<br>**-8**<br>**-7**<br>**Unit**<br>**Min**<br>**Max**<br>**Min**<br>**Max**<br>**Min**<br>**Max**<br>fDATA_OUT_GDDRX1<br>Output Data Rate<br>—<br>500<br>—<br>500<br>—<br>424<br>Mbps<br>~~a~~<br>~~ee ee ee ee~~<br>~~a~~<br>~~po~~|
|---|
|fMAX_GDDRX1<br>Frequency for PCLK<br>—<br>250<br>—<br>250<br>—<br>212<br>MHz<br>~~pO~~|
|½ UI<br>Half of Data Bit Time, or 90 degree<br>1<br>—<br>1<br>—<br>1.179<br>—<br>ns<br>~~po~~|
|Output TX to Input RX Margin per Edge<br>0.15<br>—<br>0.081<br>—<br>0.095<br>—<br>ns|
|**Generic DDRX2 Inputs/Outputs with Clock and Data Centered at Pin (GDDRX2_RX/TX.ECLK.Centered) using PCLK Clock Input -**<br>**Figure 3.7and Figure 3.9**<br>tSU_GDDRX2<br>Data Setup before CLK Input<br>0.209<br>—<br>0.209<br>—<br>0.206<br>—<br>ns<br>0.209<br>—<br>0.209<br>—<br>0.175<br>—<br>UI<br>tHO_GDDRX2<br>Data Hold after CLK Input<br>0.213<br>—<br>0.213<br>—<br>0.206<br>—<br>ns<br>~~OO_~~<br>~~ce~~<br>~~ee eee ee eee~~<br>~~a~~<br>~~po~~|
|tDVB_GDDRX2<br>Output Data Valid Before CLK<br>Output<br>0.360<br>—<br>0.352<br>—<br>0.415<br>—<br>ns<br>-0.140<br>—<br>-0.148<br>—<br>-0.174<br>—<br>ns + 1/2 UI<br>tDQVA_GDDRX2<br>Output Data Valid After CLK<br>Output<br>0.38<br>—<br>0.352<br>—<br>0.415<br>—<br>ns<br>-0.12<br>—<br>-0.148<br>—<br>-0.174<br>—<br>ns + 1/2 UI<br>fDATA_GDDRX2<br>Input/Output Data Rate<br>—<br>1000<br>—<br>1000<br>—<br>848<br>Mbps<br>~~ye~~<br>~~a~~<br>~~a ee ee~~<br>~~eee~~<br>~~a~~<br>~~po~~|
|fMAX_GDDRX2<br>Frequency for ECLK<br>—<br>500<br>—<br>500<br>—<br>424<br>MHz<br>~~po~~|
|½ UI<br>Half of Data Bit Time, or 90 degree<br>0.5<br>—<br>0.5<br>—<br>0.589<br>—<br>ns<br>~~po~~|
|fPCLK<br>PCLK frequency<br>—<br>250<br>—<br>250<br>—<br>212.1<br>MHz<br>~~pO~~|
|Output TX to Input RX Margin per Edge<br>0.23<br>—<br>0.202<br>—<br>0.239<br>—<br>ns<br>~~GGG~~|
|**Generic DDRX2 Inputs/Outputs with Clock and Data Aligned at Pin (GDDRX2_RX/TX.ECLK.Aligned) using PCLK Clock Input -**|
|**Figure 3.8andFigure 3.10**|
|tDVA_GDDRX2<br>Input Data Valid After CLK<br>—<br>-0.275<br>—<br>-0.275<br>—<br>-0.324<br>ns + 1/2 UI<br>—<br>0.225<br>—<br>0.225<br>—<br>0.265<br>ns<br>~~aee~~|tDVA_GDDRX2<br>Input Data Valid After CLK<br>—<br>-0.275<br>—<br>-0.275<br>—<br>-0.324<br>ns + 1/2 UI<br>—<br>0.225<br>—<br>0.225<br>—<br>0.265<br>ns<br>~~aee~~|
|---|---|
|—<br>0.225<br>—<br>0.225<br>—<br>0.265<br>~~a~~|UI|
|tDVE_GDDRX2<br>Input Data Hold After CLK<br>0.275<br>—<br>0.275<br>—<br>0.324<br>—<br>0.775<br>—<br>0.775<br>—<br>0.914<br>—<br>0.775<br>—<br>0.775<br>—<br>0.775<br>—<br>~~a~~<br>~~SR~~<br>~~a~~|ns + 1/2 UI<br>ns<br>UI|
|tDIA_GDDRX2<br>Output Data Invalid After CLK<br>—<br>0.12<br>—<br>0.148<br>—<br>0.174<br>ns<br>tDIB_GDDRX2<br>Output Data Invalid Before CLK<br>—<br>0.12<br>—<br>0.148<br>—<br>0.174<br>ns<br>fDATA_GDDRX2<br>Input/Output Data Rate<br>—<br>1000<br>—<br>1000<br>—<br>848<br>Mbps<br>fMAX_GDDRX2<br>Frequency for ECLK<br>—<br>500<br>—<br>500<br>—<br>424<br>MHz<br>½ UI<br>Half of Data Bit Time, or 90 degree<br>0.5<br>—<br>0.5<br>—<br>0.589<br>—<br>ns<br>~~po~~<br>~~popo~~<br>~~popo~~||
|fPCLK<br>PCLK frequency<br>—<br>250<br>—<br>250<br>—<br>212.1<br>MHz<br>~~po~~||
|Output TX to Input RX Margin per Edge<br>0.105<br>—<br>0.077<br>—<br>0.091<br>—<br>ns<br>~~po~~||
|**Generic DDRX4 Inputs/Outputs with Clock and Data Centered at Pin (GDDRX4_RX/TX.ECLK.Centered) using PCLK Clock Input -**||
|**Figure 3.7andFigure 3.9**||
|tSU_GDDRX4<br>Input Data Set-Up Before CLK<br>0.210<br>—<br>0.210<br>—<br>0.244<br>—<br>ns<br>0.315<br>—<br>0.252<br>—<br>0.252<br>—<br>UI<br>tHO_GDDRX4<br>Input Data Hold After CLK<br>0.254<br>—<br>0.254<br>—<br>0.244<br>—<br>ns<br>tDVB_GDDRX4<br>Output Data Valid Before CLK<br>Output<br>0.193<br>—<br>0.269<br>—<br>0.309<br>—<br>ns<br>-0.140<br>—<br>–0.148<br>—<br>-0.174<br>—<br>ns + 1/2 UI<br>tDQVA_GDDRX4<br>Output Data Valid After CLK<br>Output<br>0.213<br>—<br>0.269<br>—<br>0.309<br>—<br>ns<br>-0.12<br>—<br>–0.148<br>—<br>-0.174<br>—<br>ns + 1/2 UI<br>fDATA_GDDRX4<br>Input/Output Data Rate<br>—<br>1500<br>—<br>1200<br>—<br>1034<br>Mbps<br>~~ee ee~~<br>~~ee~~<br>~~a~~<br>~~GG~~<br>~~GO~~<br>~~ee~~<br>~~ee eee eee~~<br>~~a~~<br>~~ee~~<br>~~ce ee ee ee ee ee~~<br>~~a~~||
|fMAX_GDDRX4<br>Frequency for ECLK<br>—<br>750<br>—<br>600<br>—<br>517<br>MHz<br>~~po~~||
© 2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02104-1.0
71
**CrossLink-NX-33 and CrossLinkU-NX Data Sheet**
mLATTICE
|**Parameter**<br>~~a~~<br>~~a~~|**Description**<br>~~a~~|**-9**<br>~~a~~<br>~~ee~~|**-9**<br>~~a~~<br>~~ee~~|**-8**<br>~~a~~<br>~~ee~~|**-8**<br>~~a~~<br>~~ee~~|**-7**<br>~~a~~<br>~~ee ee~~|**-7**<br>~~a~~<br>~~ee ee~~|**Unit**<br>~~a~~<br>~~ee~~|
|---|---|---|---|---|---|---|---|---|
|||**Min**<br>~~a~~<br>~~ee~~|**Max**<br>~~a~~<br>~~ee~~|**Min**<br>~~a~~<br>~~ee~~|**Max**<br>~~a~~<br>~~ee~~|**Min**<br>~~a~~<br>~~ee ee~~|**Max**<br>~~a~~<br>~~ee~~||
|½ UI<br>~~a~~<br>~~a~~|Half of Data Bit Time, or 90<br>degrees<br>~~a~~<br>~~a ee~~|0.333<br>~~a~~<br>~~ee~~<br>~~ee~~|—<br>~~a~~<br>~~ee ~~<br>~~ee~~|0.417<br>~~a~~<br> ~~ee~~<br>~~ee~~|—<br>~~a~~<br>~~ee ~~<br>~~ee~~|0.483<br>~~a~~<br> ~~ee ee~~<br>~~ee~~<br>~~GO~~|—<br>~~a~~<br>~~ee~~<br>~~ee~~<br>~~GO~~|ns<br>~~a~~<br>~~ee~~<br>~~ee~~|
|fPCLK<br>~~GG~~|PCLK frequency<br>~~GG~~|—<br>~~GG~~|187.5<br>~~GG~~|—<br>~~GG~~|150<br>~~GG~~|—<br>~~GG~~<br>~~GO~~|129.3<br>~~GG~~<br>~~GO~~|MHz<br>~~GG~~|
|Output TX to Input RX Margin per Edge||0.08|—|0.102|—|0.116<br>~~GO~~|—<br>~~GO~~|ns|
|**Generic DDRX4 Inputs/Outputs with Clock and Data Aligned at Pin (GDDRX4_RX/TX.ECLK.Aligned) using PCLK Clock Input -**<br>**Figure 3.8and Figure 3.10**<br>~~eee~~<br>~~Bfee~~|||||||||
|tDVA_GDDRX4<br>~~B~~<br>~~a~~|Input Data Valid After CLK<br>~~Bf~~<br>|—<br>~~ee~~|-0.216<br>~~ee~~|—<br>~~ee~~|-0.229<br>~~ee~~|—<br>~~ee~~|-0.266<br>~~ee~~|ns + 1/2 UI<br>~~ee~~|
|||—<br>~~ee~~|0.117<br>~~ee~~|—<br>~~ee~~|0.188<br>~~ee~~|—<br>~~ee~~|0.218<br>~~ee~~|ns<br>~~ee~~|
|||—<br>~~ee~~<br>~~a ee~~<br>~~a~~<br>|0.176<br>~~ee~~<br>~~ee~~<br>|—<br>~~ee~~<br>~~ee~~<br>|0.225<br>~~ee~~<br>~~ee~~<br>|—<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>|0.225<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>|UI<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>|
|tDVE_GDDRX4<br>~~B~~<br>~~ee~~<br>~~a~~|Input Data Hold After CLK<br>~~Bf ~~<br>~~ee~~<br>|0.227<br> ~~ee~~<br>~~ee~~<br>~~a~~<br>|—<br>~~ee~~<br>~~ee~~<br>|0.229<br>~~ee~~<br>~~ee~~<br>|—<br>~~ee~~<br>~~ee~~<br>|0.266<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>|—<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>|ns + 1/2 UI<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>|
|||0.560<br>~~ee~~<br>~~a~~<br>|—<br>~~ee~~<br>|0.646<br>~~ee~~<br>|—<br>~~ee~~<br>|0.749<br>~~ee~~<br>~~ee~~<br>|—<br>~~ee~~<br>~~ee~~<br>|ns<br>~~ee~~<br>~~ee~~<br>|
|||0.840<br>~~ee~~<br>~~a~~<br>|—<br>~~ee~~<br>|0.775<br>~~ee~~<br>|—<br>~~ee~~<br>|0.775<br>~~ee~~<br>~~ee~~<br>|—<br>~~ee~~<br>~~ee~~<br>|UI<br>~~ee~~<br>~~ee~~<br>|
|tDIA_GDDRX4<br>~~ee~~<br>~~a~~|Output Data Invalid After CLK<br>Output<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~a~~<br>~~ee~~|0.12<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~<br>~~ee~~|0.148<br>~~ee~~<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~<br>~~ee~~|0.174<br>~~ee~~<br>~~ee~~<br>~~ee~~|ns<br>~~ee~~<br>~~ee~~<br>~~ee~~|
|tDIB_GDDRX4<br>~~a~~|Output Data Invalid Before CLK<br>Output<br>~~ee~~|—<br>~~ee~~|0.12<br>~~ee~~|—<br>~~ee~~<br>~~ee~~|0.148<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~CO~~|0.174<br>~~ee~~<br>~~CO~~|ns<br>~~ee~~|
|fDATA_GDDRX4<br>~~a~~<br>~~(GG~~|Input/Output Data Rate<br>~~ee~~<br>~~(GG~~|—<br>~~ee~~<br>~~(GG~~|1500<br>~~ee~~<br>~~(GG~~|—<br>~~ee~~<br>~~ee~~<br>~~(GG~~|1200<br>~~ee~~<br>~~ee~~<br>~~(GG~~|—<br>~~ee~~<br>~~(GG~~<br>~~CO~~<br>~~CO~~|1034<br>~~ee~~<br>~~(GG~~<br>~~CO~~<br>~~CO~~|Mbps<br>~~ee~~<br>~~(GG~~|
|fMAX_GDDRX4<br>~~(GG~~|Frequency for ECLK<br>~~(GG~~|—<br>~~(GG~~|750<br>~~(GG~~|—<br>~~(GG~~|600<br>~~(GG~~|—<br>~~CO~~<br>~~(GG~~<br>~~CO~~|517<br>~~CO~~<br>~~(GG~~<br>~~CO~~|MHz<br>~~(GG~~|
|½ UI<br>~~eG~~|Half of Data Bit Time, or 90 degree<br>~~eG~~|0.333<br>~~eG~~<br>~~GG~~|—<br>~~eG~~<br>~~GG~~|0.417<br>~~eG~~<br>~~GG~~|—<br>~~eG~~<br>~~GG~~|0.483<br>~~CO~~<br>~~eG~~<br>~~CO~~|—<br>~~CO~~<br>~~eG~~<br>~~CO~~|ns<br>~~eG~~|
|fPCLK<br>~~a~~|PCLK frequency<br>~~a~~|—<br>~~a~~<br>~~GG~~|187.5<br>~~a~~<br>~~GG~~|—<br>~~a~~<br>~~GG~~|150<br>~~a~~<br>~~GG~~|—<br>~~a~~<br>~~CO~~|129.3<br>~~a~~<br>~~CO~~|MHz<br>~~a~~|
|Output TX to Input RX Margin per Edge||0.03<br>~~GG~~|—<br>~~GG~~|0.040<br>~~GG~~|—<br>~~GG~~|0.044<br>~~CO~~|—<br>~~CO~~|ns|
|**Generic DDRX5 Inputs/Outputs with Clock and Data Centered at Pin (GDDRX5_RX/TX.ECLK.Centered) using PCLK Clock Input -**<br>**Figure 3.7and Figure 3.9**<br>~~eee~~|||||||||
|tSU_GDDRX5<br>~~eee~~<br>~~a~~|Input Data Set-Up Before CLK<br>~~eee~~<br>~~ee~~|0.231<br>~~eee~~<br>~~ee~~|—<br>~~eee~~<br>~~ee~~|0.231<br>~~eee~~<br>~~ee~~|—<br>~~eee~~|0.224<br>~~eee~~|—<br>~~eee~~|ns<br>~~eee~~|
|||0.289<br>~~ee~~|—<br>~~ee~~|0.277<br>~~ee~~|—<br>~~GO~~|0.224<br>~~GO~~|—<br>~~GO~~|UI|
|tHO_GDDRX5<br>~~a~~<br>~~GO~~<br>~~ee~~|Input Data Hold After CLK<br>~~ee~~<br>~~GO~~<br>~~ee~~|0.229<br>~~ee~~<br>~~GO~~<br>|—<br>~~ee~~<br>~~GO~~<br>|0.229<br>~~ee~~<br>~~GO~~<br>|—<br>~~GO~~<br>~~GO~~<br>|0.224<br>~~GO~~<br>~~GO~~<br>~~GO~~<br>|—<br>~~GO~~<br>~~GO~~<br>~~GO~~<br>|ns<br>~~GO~~<br>|
|tWINDOW_GDDRX5C<br>~~GG~~<br>~~ee~~|Input Data Valid Window<br>~~GG~~<br>~~ee~~|—<br>~~GG~~<br>~~ree~~|—<br>~~GG~~<br>~~ee~~|—<br>~~GG~~<br>~~ee~~|—<br>~~GO ~~<br>~~GG~~<br>~~ee~~|—<br> ~~GO~~<br>~~GG~~<br>~~GO~~<br>~~ee~~|—<br>~~GO~~<br>~~GG~~<br>~~GO~~<br>~~ee~~|ns<br>~~GG~~<br>~~ee~~|
|tDVB_GDDRX5<br>~~GG~~<br>~~ee~~<br>~~ren~~|Output Data Valid Before CLK<br>Output<br>~~GG~~<br>~~ee~~<br>~~ren~~|0.249<br>~~GG~~<br>~~ree~~|—<br>~~GG~~<br>~~ee~~|0.269<br>~~GG~~<br>~~ee~~|—<br>~~GG~~<br>~~ee~~|0.326<br>~~GG~~<br>~~GO~~<br>~~ee~~|—<br>~~GG~~<br>~~GO~~<br>~~ee~~|ns<br>~~GG~~<br>~~ee~~|
|||-0.151<br>~~ree~~<br>~~ren~~|—<br>~~ee~~<br>~~ee~~|-0.148<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~|-0.174<br>~~GO~~<br>~~ee~~<br>~~ee~~|—<br>~~GO~~<br>~~ee~~<br>~~eee~~|ns+1/2UI<br>~~ee~~<br>~~eee~~|
|tDQVA_GDDRX5<br>~~ee~~<br>~~ren~~|Output Data Valid After CLK<br>Output<br>~~ee ~~<br>~~ren~~|0.249<br> ~~ree ~~<br>~~ren~~|—<br> ~~ee ~~<br>~~ee~~|0.269<br> ~~ee ~~<br>~~ee~~|—<br> ~~ee ~~<br>~~ee~~|0.326<br>~~GO~~<br> ~~ee ~~<br>~~ee~~|—<br>~~GO~~<br> ~~ee~~<br>~~eee~~|ns<br>~~ee~~<br>~~eee~~|
|||-0.151<br>~~ren~~|—<br>~~ee~~|-0.148<br>~~ee~~|—<br>~~ee~~|-0.174<br>~~ee~~<br>~~GO~~|—<br>~~eee~~|ns+1/2UI<br>~~eee~~|
|fDATA_GDDRX5<br>~~ren~~<br>~~GO~~<br>~~es~~|Input/Output Data Rate<br>~~ren~~<br>~~GO~~<br>|—<br>~~ren ~~<br>~~GO~~<br>~~GOGO~~<br>|1250<br> ~~ee ~~<br>~~GO~~<br>~~GOGO~~<br>|—<br> ~~ee ~~<br>~~GO~~<br>~~GOGO~~<br>|1200<br> ~~ee ~~<br>~~GO~~<br>~~GOGO~~<br>|—<br> ~~ee ~~<br>~~GO~~<br>~~GO~~<br>~~**GO**~~<br>|1000<br> ~~eee~~<br>~~GO~~<br>~~**GO**~~<br>|Mbps<br>~~eee~~<br>~~GO~~<br>|
|fMAX_GDDRX5<br>~~GO~~<br>~~a~~<br>~~es~~|Frequency for ECLK<br>~~GO~~<br>~~a~~<br>|—<br>~~GO~~<br>~~a~~<br>~~GOGO~~<br>|625<br>~~GO~~<br>~~a~~<br>~~GOGO~~<br>|—<br>~~GO~~<br>~~a~~<br>~~GOGO~~<br>|600<br>~~GO~~<br>~~a~~<br>~~GOGO~~<br>|—<br>~~GO~~<br>~~GO~~<br>~~a~~<br>~~**GO**~~<br>|500<br>~~GO~~<br>~~a~~<br>~~**GO**~~<br><br>~~O~~|MHz<br>~~GO~~<br>~~a~~<br>|
|½ UI<br>~~es~~|Half of Data Bit Time, or 90 degree<br>~~GG~~|0.4<br>~~GOGO~~<br>~~GG~~<br>~~GG~~|—<br>~~GOGO~~<br>~~GG~~<br>~~GG~~|0.417<br>~~GOGO~~<br>~~GG~~<br>~~GG~~|—<br>~~GOGO~~<br>~~GG~~<br>~~GG~~|0.500<br>~~**GO**~~<br>~~GG~~<br>~~OO~~|—<br>~~**GO**~~<br>~~GG~~<br>~~O~~<br>~~OO~~|ns<br>~~GG~~|
|fPCLK<br>~~es~~<br>~~a~~|PCLK frequency<br>~~GG~~<br>~~a~~|—<br>~~GOGO~~<br>~~GG~~<br>~~a~~<br>~~GG~~|125<br>~~GOGO~~<br>~~GG~~<br>~~a~~<br>~~GG~~|—<br>~~GOGO~~<br>~~GG~~<br>~~a~~<br>~~GG~~|120<br>~~GOGO ~~<br>~~GG~~<br>~~a~~<br>~~GG~~|—<br> ~~**GO**~~<br>~~GG~~<br>~~a~~<br>~~OO~~<br>~~DO~~|100.0<br>~~**GO**~~<br>~~GG~~<br>~~O~~<br>~~a~~<br>~~OO~~<br>~~DO~~|MHz<br>~~GG~~<br>~~a~~|
|Output TX to Input RX Margin per Edge<br>~~DG~~||0.12<br>~~GG~~<br>~~DG~~|—<br>~~GG~~<br>~~DG~~|0.102<br>~~GG~~<br>~~DG~~|—<br>~~GG~~<br>~~DG~~|0.126<br>~~OO~~<br>~~DG~~<br>~~DO~~|—<br>~~OO~~<br>~~DG~~<br>~~DO~~|ns<br>~~DG~~|
© 2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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**CrossLink-NX-33 and CrossLinkU-NX Data Sheet**
aLATTICE
|**Parameter**|**Description**|**-9**|**-9**|**-8**|**-8**|**-7**|**-7**|**Unit**|
|---|---|---|---|---|---|---|---|---|
|||**Min**|**Max**|**Min**|**Max**|**Min**|**Max**||
|**Generic DDRX5 Inputs/Outputs with Clock and Data Aligned at Pin (GDDRX5_RX/TX.ECLK.Aligned) using PCLK Clock Input -**<br>**Figure 3.8andFigure 3.10**<br>~~eee~~|||||||||
|tDVA_GDDRX5<br>~~|~~|Input Data Valid After CLK<br>~~|~~|—<br>~~**a**~~|-0.220<br>~~a~~|—<br>~~a~~|-0.229|—|-0.275|ns + 1/2 UI|
|||—<br>~~**a**~~|0.18<br>~~a~~|—<br>~~a~~|0.188|—|0.225|ns|
|||—<br>~~**a** ~~|0.225<br> ~~a~~|—<br>~~a~~|0.225|—|0.225|UI|
|tDVE_GDDRX5<br>~~a~~|Input Data Hold After CLK<br>~~a~~|0.22<br>~~————~~|—<br>~~————~~|0.229<br>~~————~~|—<br>~~————~~|0.275|—|ns + 1/2 UI|
|||0.62<br>~~————~~<br>~~a~~|—<br>~~————~~<br>~~a~~|0.646<br>~~————~~|—<br>~~————~~|0.775|—|ns|
|||0.775<br>~~————~~<br>~~a~~|—<br>~~————~~<br>~~a~~|0.775<br>~~————~~|—<br>~~————~~|0.775|—|UI|
|tWINDOW_GDDRX5A<br>~~a~~|Input Data Valid Window|—|—|—|—|—|—|ns|
|tDIA_GDDRX5<br>~~a~~<br>~~a eee~~|Output Data Invalid After CLK<br>Output<br>~~eee~~|—<br>~~eee~~|0.12<br>~~eee~~|—<br>~~eee~~|0.148<br>~~eee~~|—<br>~~eee~~|0.174<br>~~eee~~|ns<br>~~eee~~|
|tDIB_GDDRX5<br>~~a eee~~<br>~~a~~|Output Data Invalid Before CLK<br>Output<br>~~eee~~<br>~~ee~~|—<br>~~eee~~<br>~~ee ~~|0.12<br>~~eee~~<br> ~~ee~~|—<br>~~eee~~<br>~~ee~~|0.148<br>~~eee~~<br>~~ee~~|—<br>~~eee~~|0.174<br>~~eee~~|ns<br>~~eee~~|
|fDATA_GDDRX5<br>~~a~~|Input/Output Data Rate|—|1250|—|1200|—|1000|Mbps|
|fMAX_GDDRX5<br>~~a~~<br>~~a~~|Frequency for ECLK<br>|—<br>|625<br>|—<br>~~ee~~<br>|600<br>~~ee~~<br>|—<br>~~ee~~<br>|500<br>|MHz<br>|
|½ UI<br>~~a~~<br>~~a~~|Half of Data Bit Time or 90<br>degrees<br>~~ee~~<br>|0.4<br>~~ee~~<br>|—<br>~~ee~~<br>|0.417<br>~~ee~~<br>~~ee~~<br>|—<br>~~ee~~<br>~~ee~~<br>|0.500<br>~~ee~~<br>~~ee~~<br>|—<br>~~ee~~<br>|ns<br>~~ee~~<br>|
|fPCLK<br>~~a~~|PCLK frequency<br>|—<br>|125<br>|—<br>~~ee~~<br>|120<br>~~ee~~<br>|—<br>~~ee~~<br>|100.0<br>|MHz<br>|
|Output TX to Input RX Margin per Edge<br>~~aa~~||0.06<br>~~a~~|—<br>~~a~~|0.051<br>~~ee~~<br>~~a~~|—<br>~~ee~~<br>~~a~~|ns<br>~~ee~~<br>~~a~~|0.04<br>~~a~~|—<br>~~a~~|
|**Soft D-PHY DDRX4 Inputs/Outputs with Clock and Data Centered at Pin, using PCLK Clock Input**<br>~~a~~<br>~~ee eeeee~~<br>~~a~~|||||||||
|tSU_GDDRX4_MP<br>~~a~~<br>~~a~~<br>~~a~~|Input Data Set-Up Before CLK<br>~~a~~<br>~~a~~<br>~~ee~~|0.133<br>~~a~~<br>~~a~~<br>~~e ee~~|—<br>~~a~~<br>~~a~~<br>~~ee~~|0.167<br>~~a~~<br>~~a~~<br>~~ee~~|—<br>~~a~~<br>~~a~~<br>~~eee~~|0.193<br>~~a~~<br>~~a~~<br>~~eee~~|—<br>~~a~~<br>~~a~~<br>~~eee~~|ns<br>~~a~~<br>~~a~~<br>~~eee~~|
|||0.2<br>~~a~~<br>~~e ee~~|—<br>~~a~~<br>~~ee~~|0.2<br>~~a~~<br>~~ee~~|—<br>~~a~~<br>~~eee~~|0.2<br>~~a~~<br>~~eee~~|—<br>~~a~~<br>~~eee~~|UI<br>~~a~~<br>~~eee~~|
|tHO_GDDRX4_MP<br>~~a~~<br>~~a~~<br>~~_—_f~~|Input Data Hold After CLK<br>~~a~~<br>~~ee~~<br>~~_—_f~~|0.133<br>~~a~~<br>~~e ee~~|—<br>~~a~~<br>~~ee~~|0.167<br>~~a~~<br>~~ee~~|—<br>~~a~~<br>~~eee~~|0.193<br>~~a~~<br>~~eee~~|—<br>~~a~~<br>~~eee~~|ns<br>~~a~~<br>~~eee~~|
|tDVB_GDDRX4_MP<br>~~a~~<br>~~_—_f~~<br>~~a~~|Output Data Valid Before CLK<br>Output<br>~~ee~~<br>~~_—_f~~<br>~~ee~~|0.133<br>~~e ee~~|—<br>~~ee~~|0.167<br>~~ee~~|—<br>~~eee~~|0.193<br>~~eee~~|—<br>~~eee~~|ns<br>~~eee~~|
|||0.2<br>~~ee~~|—<br>~~eee~~|0.2<br>~~eee~~|—<br>~~eee~~|0.2<br>~~eee~~|—<br>~~eee~~|UI<br>~~eee~~|
|tDQVA_GDDRX4_MP<br>~~_—_f~~<br>~~a~~|Output Data Valid After CLK<br>Output<br>~~_—_f~~<br>~~ee~~|0.133<br>~~ee~~|—<br>~~eee~~|0.167<br>~~eee~~|—<br>~~eee~~|0.193<br>~~eee~~|—<br>~~eee~~|ns<br>~~eee~~|
|||0.2<br>~~ee~~|—<br>~~eee~~|0.2<br>~~eee~~|—<br>~~eee~~|0.2<br>~~eee~~|—<br>~~eee~~|UI<br>~~eee~~|
|fDATA_GDDRX4_MP<br>~~a~~<br>~~_~~<br>~~a~~|Input Data Bit Rate for MIPI PHY<br>(USG84)<br>~~ee~~<br>~~ee~~<br>|—<br>~~ee~~<br>~~ee~~<br>~~ee ee~~<br>|1250<br>~~eee~~<br>~~ee~~<br>~~ee~~<br>|—<br>~~eee~~<br>~~ee~~<br>~~ee~~<br>|1000<br>~~eee~~<br>~~ee~~<br>~~ee~~<br>|—<br>~~eee~~<br>~~ee~~<br>~~ee ee~~<br>|—<br>~~eee~~<br>~~ee~~<br>~~ee~~<br>|Mbps<br>~~eee~~<br>~~ee~~<br>~~ee~~<br>|
||Input Data Bit Rate for MIPI PHY<br>(CTG104)<br>~~ee~~<br>|—<br>~~ee~~<br>~~ee ee~~<br>|1500<br>~~ee~~<br>~~ee~~<br>|—<br>~~ee~~<br>~~ee~~<br>|1200<br>~~ee~~<br>~~ee~~<br>|—<br>~~ee~~<br>~~ee ee~~<br>|1034<br>~~ee~~<br>~~ee~~<br>|Mbps<br>~~ee~~<br>~~ee~~<br>|
|½ UI<br>~~_~~<br>~~a~~|Half of Data Bit Time or 90<br>~~ee~~<br>|0.333<br>~~ee~~<br>~~ee ee~~<br>|—<br>~~ee~~<br>~~ee~~<br>|0.417<br>~~ee~~<br>~~ee~~<br>|—<br>~~ee~~<br>~~ee ~~<br>|0.483<br>~~ee~~<br> ~~ee ee~~<br>|—<br>~~ee~~<br>~~ee~~<br>|ns<br>~~ee~~<br>~~ee~~<br>|
|fPCLK<br>~~a~~|PCLK frequency<br>~~a~~|—<br>~~a~~|187.5<br>~~a~~|—<br>~~a~~|150<br>~~a~~|—<br>~~a~~|129.3<br>~~a~~|MHz<br>~~a~~|
|Output TX to Input RX Margin per Edge<br>~~a~~<br>~~a~~||0.067<br>~~a~~<br>~~a~~|—<br>~~a~~<br>~~a~~|0.083<br>~~a~~<br>~~a~~|—<br>~~a~~<br>~~a~~|0.097<br>~~a~~<br>~~a~~|—<br>~~a~~<br>~~a~~|ns<br>~~a~~<br>~~a~~|
|**Video DDRX71 Inputs/Outputs with Clock and Data Aligned at Pin (GDDRX71_RX.ECLK) using PLL Clock Input - Figure 3.12and**<br>**Figure 3.13**<br>~~eee!~~<br>~~te~~<br>~~ee~~|||||||||
|tRPBi_DVA<br>~~t~~<br>~~ee~~|Input Valid Bit "i" switch from CLK<br>Rising Edge ("i" = 0 to 6, 0 aligns<br>with CLK)<br>~~te~~<br>~~Pot~~<br>~~ee~~|—<br>~~Pot~~<br>|0.264<br>~~Pot|~~<br>|—<br>~~|~~|0.264<br>~~ee~~|—<br>~~ee~~|0.3<br>~~ee~~|UI<br>~~ee~~|
|||—<br>~~Pot~~<br>~~es~~|-0.250<br>~~Pot|~~<br>~~es~~|—<br>~~|~~|-0.250<br>~~ee~~|—<br>~~ee~~|-0.249<br>~~ee~~|ns+(1/2+i)<br>× UI<br>~~ee~~|
|tRPBi_DVE<br>~~t~~<br>~~ee~~|Input Hold Bit "i" switch from CLK<br>Rising Edge ("i" = 0 to 6, 0 aligns<br>with CLK)<br>~~te~~<br>~~Pot~~<br>~~ee~~<br>~~pot~~|0.761<br>~~Pot~~<br>~~es~~<br>~~pot~~|—<br>~~Pot|~~<br>~~es~~<br>~~pot~~<br>~~|~~|0.761<br>~~|~~|—<br>~~ee~~|0.7<br>~~ee~~|—<br>~~ee~~|UI<br>~~ee~~|
|||0.276<br>~~Pot~~<br>~~es~~<br>~~pot~~|—<br>~~Pot|~~<br>~~es~~<br>~~pot~~<br>~~|~~|0.276<br>~~|~~|—|0.249|—|ns+(1/2+i)<br>× UI|
|tTPBi_DOV<br>~~ee~~|Data Output Valid Bit "i" switch<br>from CLK Rising Edge ("i" = 0 to 6,<br>0 aligns with CLK)<br>~~Pot~~<br>~~ee ~~<br>~~pot~~|—<br>~~Pot~~<br> ~~es~~<br>~~pot~~|0.159<br>~~Pot |~~<br>~~es~~<br>~~pot~~<br>~~|~~|—<br>~~|~~|0.159|—|0.187|ns+I × UI|
© 2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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**CrossLink-NX-33 and CrossLinkU-NX Data Sheet**
mLATTICE
|**Parameter**|**Description**|**-9**|**-9**|**-8**|**-8**|**-7**|**-7**|**Unit**|
|---|---|---|---|---|---|---|---|---|
|||**Min**|**Max**|**Min**|**Max**|**Min**|**Max**||
|tTPBi_DOI|Data Output Invalid Bit "i" switch<br>from CLK Rising Edge ("i" = 0 to 6,<br>0 aligns with CLK)|-0.159|—|-0.159|—|-0.187|—|ns+(i+ 1) ×<br>UI|
|tTPBi_skew_UI<br>~~po~~|TX skew in UI<br>~~po~~|—<br>~~po~~|0.15<br>~~po~~|—<br>~~po~~|0.15<br>~~po~~|—<br>~~po~~|0.150<br>~~po~~|UI<br>~~po~~|
|tB<br>~~po~~|Serial Data Bit Time, = 1 UI<br>~~po~~|1.058<br>~~po~~|—<br>~~po~~|1.058<br>~~po~~|—<br>~~po~~|1.247<br>~~po~~|—<br>~~po~~|ns<br>~~po~~|
|fDATA_TX71<br>~~po~~|DDR71 Serial Data Rate<br>~~po~~|—<br>~~po~~|945<br>~~po~~|—<br>~~po~~|945<br>~~po~~|—<br>~~po~~|802<br>~~po~~|Mbps<br>~~po~~|
|fMAX_TX71<br>~~po~~|DDR71 ECLK Frequency<br>~~po~~|—<br>~~po~~|473<br>~~po~~|—<br>~~po~~|473<br>~~po~~|—<br>~~po~~|401<br>~~po~~|MHz<br>~~po~~|
|fCLKIN<br>~~po~~<br>~~po~~|7:1 Clock (PCLK) Frequency<br>~~po~~<br>~~po~~|—<br>~~po~~<br>~~po~~|135<br>~~po~~<br>~~po~~|—<br>~~po~~<br>~~po~~|135<br>~~po~~<br>~~po~~|—<br>~~po~~<br>~~po~~|114.5<br>~~po~~<br>~~po~~|MHz<br>~~po~~<br>~~po~~|
|Output TX to Input RX Margin per Edge<br>~~GGG~~||0.159<br>~~GGG~~|—<br>~~GGG~~|0.159<br>~~GGG~~|—<br>~~GGG~~|0.187<br>~~GGG~~|—<br>~~GGG~~|ns<br>~~GGG~~|
- **Notes** :
1. Commercial timing numbers are shown. Industrial numbers are typically slower and can be extracted from the Lattice Radiant software.
2. General I/O timing numbers are based on LVCMOS 1.8, 8 mA, Fast Slew Rate, 0 pF load. Generic DDR timing are numbers based on LVDS I/O.
3. Uses LVDS I/O standard for measurements.
4. Maximum clock frequencies are tested under best case conditions. System performance may vary upon the user environment.
5. All numbers are generated with the Lattice Radiant software.
6. This clock skew is not the internal clock network skew. The Nexus family devices have very low internal clock network skew that can be approximated to 0 ps. These tSKEW values measured externally at system level includes additional skew added by the I/O, wire bonding and package ball.
**==> picture [296 x 127] intentionally omitted <==**
**----- Start of picture text -----**<br>
Rx CLK (in)<br>rs rs<br>Rx DATA (in)<br>a<br>tSU tSU<br>tHD tHD<br>**----- End of picture text -----**<br>
**Figure 3.7. Receiver RX.CLK.Centered Waveforms**
**==> picture [401 x 135] intentionally omitted <==**
**----- Start of picture text -----**<br>
½ UI<br>½ UI<br>1 UI<br>Rx CLK (in)<br>or DQS input<br>Rx DATA (in)<br>or DQS input<br>a) Vr<br>tDVA/tDVADQ<br>tDVA/tDVADQDVA/tDVADQ/tDVADQDVADQ<br>tDVE/tDVEDQ<br>**----- End of picture text -----**<br>
**==> picture [84 x 33] intentionally omitted <==**
**----- Start of picture text -----**<br>
tDVA/tDVADQDVA/tDVADQ/tDVADQDVADQ<br>tDVE/tDVEDQ<br>**----- End of picture text -----**<br>
**Figure 3.8. Receiver RX.CLK.Aligned and DDR Memory Input Waveforms**
© 2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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**CrossLink-NX-33 and CrossLinkU-NX Data Sheet**
a@LATTICE
**==> picture [467 x 334] intentionally omitted <==**
**----- Start of picture text -----**<br>
1/2 UI 1/2 UI 1/2 UI 1/2 UI<br>Tx CLK (out)<br>or DQS Output<br>Tx DATA (out)<br>or DQ Output<br>" |<br>tDVB/tDQVBS tDVB/tDQVBS<br>tDVA/tDQVA tDVA/tDQVAS<br>Figure 3.9. Transmit TX.CLK.Centered and DDR Memory Output Waveforms<br>1 UI<br>Tx CLK (out)<br>Tx DATA (out)<br>||) as |<br>tDIB tDIB<br>tDIA tDIA<br>**----- End of picture text -----**<br>
**Figure 3.10. Transmit TX.CLK.Aligned Waveforms**
© 2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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**CrossLink-NX-33 and CrossLinkU-NX Data Sheet**
aLATaa TICE
## **Receiver – Shown for one LVDS Channel**
|0!|0x<br>0x<br>0x<br>0x<br>0x<br>0x<br>0x<br>~~KOK 1X 2K 3X 4X 5X EK~~<br>0!<br>1|<br>i)<br>1<br>1<br>1<br>i)<br>1<br>1<br>1<br>i)<br>1<br>1<br>1<br>i)<br>1<br>1<br>1<br>i)<br>1<br>1<br>1|Bit #<br>10 – 1<br>11 – 2<br>12 – 3<br>13 – 4<br>14 – 5<br>15 – 6<br>16 – 7<br>~~EK ON 1X 2K SX 4X SX BY~~<br>1|<br>2<br>|<br>1<br>1<br>1<br>1<br>1<br>1<br>1<br>1<br>1<br>1<br>1<br>1<br>1<br>1<br>1<br>1<br>1<br>1<br>1<br>1|Bit #<br>20 – 8<br>21 – 9<br>22 – 10<br>23 – 11<br>24 – 12<br>25 – 13<br>26 – 14<br>~~BY ON 1X 2X 3K 4K SX OK~~<br>|<br>3!<br>1<br>1<br>1<br>1<br>1<br>1<br>1<br>1<br>1<br>1<br>1<br>1<br>1<br>1<br>1<br>1<br>1<br>1<br>1<br>1|Bit #<br>30 – 15<br>31 – 16<br>32 – 17<br>33 – 18<br>34 – 19<br>35 – 20<br>36 – 21<br>~~OK OK 1K 2K 3X 4X 5X 6X~~<br>3!<br>4<br>1<br>1<br>1<br>1<br>1<br>1<br>1<br>1<br>1<br>1<br>1<br>1<br>1<br>1<br>1<br>1<br>1<br>1<br>1<br>1|Bit #<br>40 – 22<br>41 – 23<br>42 – 24<br>43 – 25<br>44 – 26<br>45 – 27<br>46 – 28<br>~~6X 0)~~<br>4<br>1<br>1<br>1<br>1<br>1<br>1<br>1<br>1<br>1<br>1|
|---|---|---|---|---|---|
|**For each Channel:**<br>**7-bit Output Words**<br>i)<br>i)<br>i)<br>i)<br>i)||||||
## **Transmitter – Shown for one LVDS Channel**
# of Bits 12 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 Data Out 756 Mb/s ~~COD AQAAAA7DABAAABABZDAPDAQAA2AAADAS~~ Clock Out 0| 1! 2| 3} 4| 108 MHz ~~**1** 1~~ 1 1 1 1 Bit # ~~**1**~~ Bit # ~~1~~ Bit # Bit # **For each Channel:** 00 – 1 10 – 8 1 20 – 15 1 30 – 22 1 1 00 – 2 **1** 11 – 9 1 21 – 16 31 – 23 **7-bit Output Words** 00 – 3 12 – 10 1 22 – 17 1 32 – 24 1 1 **to FPGA Fabric** 00 – 4 **1** 13 – 11 1 23 – 18 33 – 25 00 – 5 14 – 12 1 24 – 19 1 34 – 26 1 1 00 – 6 **1** 15 – 13 **1** 25 – 20 35 – 27 00 – 7 16 – 14 26 – 21 36 – 28
**Figure 3.11. DDRX71 Video Timing Waveforms**
**==> picture [389 x 171] intentionally omitted <==**
**----- Start of picture text -----**<br>
Bit 0 Bit 1 Bit i<br>1/2 UI 1/2 UI<br>CLK (in) 1 UI \<br>'I<br>' H<br>DATA (in)<br>! tSU_0 1 I 1<br>tHD_0<br>es<br>1 tSU_i i)<br>tHD_i<br>**----- End of picture text -----**<br>
**Figure 3.12. Receiver DDRX71_RX Waveforms**
© 2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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**CrossLink-NX-33 and CrossLinkU-NX Data Sheet**
**==> picture [472 x 211] intentionally omitted <==**
**----- Start of picture text -----**<br>
Bit 0 Bit 1 Bit i<br>1 UI<br>CLK (out)<br>_}—} ><br>DATA (out)<br>tDIB_0 XC S 00 AHO }<br>tDIA_0<br>tDIB_i<br>tDIA_i<br>**----- End of picture text -----**<br>
**Figure 3.13. Transmitter DDRX71_TX Waveforms**
## **3.18. sysCLOCK PLL Timing (VCC = 1.0 V)**
Over recommended operating conditions.
**Table 3.34. sysCLOCK PLL Timing (VCC = 1.0 V)**
|**Parameter**<br>~~a~~|**Descriptions**<br>~~er~~|**Conditions**<br>~~(rr~~|**Min**<br>~~rs ts~~|**Typ.**<br>~~ts~~|**Max**<br>~~ns~~|**Units**|
|---|---|---|---|---|---|---|
|fIN<br>~~a~~<br>~~a~~|Input Clock Frequency (CLKI, CLKFB)<br>~~er~~<br>~~a~~|—<br>~~(rr~~<br>~~a~~|18<br>~~rs ts~~<br>~~a~~|—<br>~~ts~~<br>~~a~~|500<br>~~ns~~<br>~~a~~|MHz<br>~~a~~|
|fOUT<br>~~a~~|Output Clock Frequency<br>~~a~~|—<br>~~a~~|6.25<br>~~a~~|—<br>~~a~~|800<br>~~a~~|MHz<br>~~a~~|
|fVCO<br>~~a~~|PLL VCO Frequency<br>~~a~~|—<br>~~a~~|800<br>~~a~~|—<br>~~a~~|1600<br>~~a~~|MHz<br>~~a~~|
|fPFD<br>~~So~~<br>~~ee~~|Phase Detector Input Frequency<br>~~So~~<br>~~ee~~|Without Fractional-<br>N Enabled<br>~~So~~<br>~~ee~~|18<br>~~lcoo~~|—<br>~~lcoo~~<br>~~ee~~|500<br>~~lcoo~~<br>~~ee~~|MHz<br>~~lcoo~~<br>~~ee~~|
|||With Fractional-N<br>Enabled<br>~~So ~~<br>~~ee~~|18<br> ~~lcoo~~|—<br>~~lcoo~~<br>~~ee~~|100<br>~~lcoo~~<br>~~ee~~|MHz<br>~~lcoo~~<br>~~ee~~|
|**AC Characteristics**<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~es~~<br>~~es~~|||||||
|tDT<br>~~ee~~<br>~~a ee~~<br>~~es~~|Output Clock Duty Cycle<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~<br>~~es~~|45<br>~~ee~~|—<br>~~ee~~<br>~~ee~~|55<br>~~ee~~<br>~~ee~~|%<br>~~ee~~<br>~~ee~~|
|tPH4<br>~~a ee~~<br>~~es~~|Output Phase Accuracy<br>~~ee~~|—<br>~~ee~~<br>~~es~~|-5<br>~~ee~~|—<br>~~ee~~|5<br>~~ee~~|%<br>~~ee~~|
© 2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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mLATTICE
|**Parameter**<br>~~a ~~|**Descriptions**<br> ~~GG~~<br>~~ee~~|**Conditions**<br>~~GG~~|**Min**<br>~~GG~~|**Typ.**<br>~~GG~~<br>~~GO~~|**Max**<br>~~GG~~|**Units**<br>~~GG~~|
|---|---|---|---|---|---|---|
|tOPJIT1<br>~~o~~<br>~~es~~|Output Clock Period Jitter<br>~~ee~~<br>~~po~~|fOUT≥ 200 MHz<br>~~po~~|—|—<br>~~GO~~|250|ps p-p|
|||fOUT< 200 MHz<br>~~po~~|—|—<br>~~GO~~|0.05|UIPP|
||Output Clock Cycle-to-Cycle Jitter<br>~~ee~~<br>~~po~~<br>~~—y—ry————~~|fOUT≥ 200 MHz<br>~~po~~<br>~~—y—ry————~~|—<br>~~—y—ry————~~|—<br>~~GO~~<br>~~—y—ry————~~|250<br>~~—y—ry————~~|ps p-p<br>~~—y—ry————~~|
|||fOUT< 200 MHz<br>~~—y—ry————~~<br>~~es~~|—<br>~~—y—ry————~~<br>~~es~~|—<br>~~—y—ry————~~<br>~~es~~|0.05<br>~~—y—ry————~~<br>~~es~~|UIPP<br>~~—y—ry————~~<br>~~es~~|
||Output Clock Phase Jitter<br>~~ST~~<br>~~po~~<br>~~**p**~~<br>~~oO~~|fPFD ≥200 MHz<br>~~ST~~<br>~~po~~|—<br>~~ST~~|—<br>~~ST~~|250<br>~~ST~~|ps p-p<br>~~ST~~|
|||60 MHz≤fPFD< 200<br>~~ST~~<br>~~po~~|—<br>~~ST~~|—<br>~~ST~~|350<br>~~ST~~|ps p-p<br>~~ST~~|
|||30 MHz≤fPFD< 60<br>~~ST~~<br>~~po~~<br>~~es~~<br>~~**p**o~~|—<br>~~ST~~<br>~~es~~|—<br>~~ST~~<br>~~es~~|450<br>~~ST~~<br>~~es~~|ps p-p<br>~~ST~~<br>~~es~~|
|||18 MHz≤fPFD< 30<br>~~ST~~<br>~~**p**o~~|—<br>~~ST~~|—<br>~~ST~~|650<br>~~ST~~|ps p-p<br>~~ST~~|
||Output Clock Period Jitter (Fractional-N)<br>~~ST~~<br>~~**p**~~<br>~~oO~~|fOUT≥ 200 MHz<br>~~ST~~<br>~~**p**o~~|—<br>~~ST~~<br>~~|~~|—<br>~~ST~~<br>~~||~~|350<br>~~ST~~<br>~~||~~|ps p-p<br>~~ST~~<br>~~|~~|
|||fOUT< 200 MHz<br>~~**p**o~~|—<br>~~t~~<br>~~|~~|—<br>~~t~~<br>~~||~~|0.07<br>~~t~~<br>~~||~~|UIPP<br>~~t~~<br>~~|~~|
||Output Clock Cycle-to-Cycle Jitter (Fractional-N)<br>~~**p**~~<br>~~oO~~<br>|fOUT≥ 200 MHz<br>~~**p**o~~<br>|—<br>~~|~~<br>~~|~~<br>|—<br>~~| |~~<br>~~||~~<br>|400<br>~~| |~~<br>~~|~~<br>|ps p-p<br>~~|~~<br>|
|||fOUT< 200 MHz<br>~~pt~~<br>|—<br>~~pt~~<br>~~|~~<br>|—<br>~~pt~~<br>~~||~~<br>|0.08<br>~~pt~~<br>~~|~~<br>|UIPP<br>~~pt~~<br>|
|fBW3<br>~~es~~|PLL Loop Bandwidth<br>~~GG~~|—<br>~~pt~~<br>~~GG~~|0.45<br>~~pt~~<br>~~|~~<br>~~GG~~|—<br>~~pt~~<br>~~||~~<br>~~GG~~|13<br>~~pt~~<br>~~|~~<br>~~GG~~|MHz<br>~~pt~~<br>~~GG~~|
|tLOCK2<br>~~es~~<br>~~a~~|PLL Lock-in Time<br><br>~~GG~~|—<br><br>~~GG~~|—<br>~~|~~<br><br>~~GG~~|—<br>~~| |~~<br><br>~~GG~~|10<br>~~|~~<br><br>~~GG~~|ms<br><br>~~GG~~|
|tUNLOCK<br><br>~~ee~~|PLL Unlock Time (from RESET goes HIGH)<br><br>|—<br>|—<br>|—<br>|50<br>|ns<br>~~—~~|
|tIPJIT<br>~~ey~~<br>~~ee~~|Input Clock Period Jitter<br>~~ey~~<br>|fPFD≥ 20 MHz<br>~~ee~~<br>~~ey~~|—<br>~~ee~~<br>~~ey~~|—<br>~~ee~~<br>~~ey~~|500<br>~~ee~~<br>~~ey~~|ps p-p<br>~~ee~~<br>~~ey—~~|
|||fPFD< 20 MHz<br>~~ey~~|—<br>~~ey~~|—<br>~~ey~~|0.01<br>~~ey~~|UIPP<br>~~ey—~~|
|tHI<br><br>~~ee~~|Input Clock High Time<br><br>~~a~~|90% to 90%<br><br>~~GG~~|0.5<br><br>~~GG~~|—<br><br>~~GG~~<br>~~OO~~|—<br><br>~~GG~~<br>~~OO~~|ns<br>~~—~~<br>~~GG~~|
|tLO<br><br>~~ee~~<br>~~GG~~<br>~~a~~|Input Clock Low Time<br><br><br>~~GG~~<br>|10% to 10%<br><br>~~GG~~<br>|0.5<br><br>~~GG~~<br>~~GO~~<br>|—<br><br>~~GG~~<br>~~OO~~<br>~~GO~~<br>|—<br><br>~~GG~~<br>~~OO~~<br>~~GO~~<br>|ns<br>~~—~~<br>~~GG~~<br>|
|tRST<br>~~GG~~<br>~~eG~~<br>~~a~~|RST/ Pulse Width<br>~~GG~~<br>~~eG~~<br>|—<br>~~GG~~<br>~~eG~~<br>|1<br>~~GG~~<br>~~eG~~<br>~~GO~~<br>|—<br>~~GG~~<br>~~OO~~<br>~~eG~~<br>~~GO~~<br>|—<br>~~GG~~<br>~~OO~~<br>~~eG~~<br>~~GO~~<br>|ms<br>~~GG~~<br>~~eG~~<br>|
|fSSC_MOD<br>~~eG~~<br>~~a~~|Spread Spectrum Clock Modulation Frequency<br>~~eG~~<br>~~GG~~|—<br>~~eG~~<br>~~GG~~|20<br>~~eG~~<br>~~GO~~<br>~~GG~~|—<br>~~eG~~<br>~~GO~~<br>~~GG~~|200<br>~~eG~~<br>~~GO~~<br>~~GG~~|kHz<br>~~eG~~<br>~~GG~~|
|fSSC_MOD_AMP|Spread Spectrum Clock Modulation Amplitude<br>Range|—|0.25|—|2.00|%|
|fSSC_MOD_STEP<br>~~a~~|Spread Spectrum Clock Modulation Amplitude Step<br>Size<br>~~ee~~|—<br>~~ee~~|—<br>~~ee~~|0.25<br>~~ee~~|—<br>~~ee~~|%<br>~~ee~~|
**Notes** :
1. Jitter sample is taken over 10,000 samples for Period jitter, and 1,000 samples for Cycle-to-Cycle jitter of the primary PLL output with clean reference clock with no additional I/O toggling.
2. Output clock is valid after tLOCK for PLL reset and dynamic delay adjustment.
3. Result from Lattice Radiant software.
4. CLKOS as compared to CLKOP output for one phase step at the maximum VCO frequency.
© 2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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## **3.19. Internal Oscillators Characteristics**
**Table 3.35. Internal Oscillators (VCC = 1.0 V)**
|**Table 3.35. Internal Oscillators (VCC = 1.0 V)(VCC = 1.0 V)VCC = 1.0 V)CC = 1.0 V) = 1.0 V))**|**Table 3.35. Internal Oscillators (VCC = 1.0 V)(VCC = 1.0 V)VCC = 1.0 V)CC = 1.0 V) = 1.0 V))**|**Table 3.35. Internal Oscillators (VCC = 1.0 V)(VCC = 1.0 V)VCC = 1.0 V)CC = 1.0 V) = 1.0 V))**|**Table 3.35. Internal Oscillators (VCC = 1.0 V)(VCC = 1.0 V)VCC = 1.0 V)CC = 1.0 V) = 1.0 V))**|**Table 3.35. Internal Oscillators (VCC = 1.0 V)(VCC = 1.0 V)VCC = 1.0 V)CC = 1.0 V) = 1.0 V))**|
|---|---|---|---|---|
|**Symbol**<br>**Parameter Description**<br>**Min**<br>**Typ**<br>**Max**<br>**Unit**<br>fCLKHF<br>HFOSC CLKK Clock Frequency<br>418.5<br>450<br>481.5<br>MHz<br>fCLKLF<br>LFOSC CLKK Clock Frequency<br>25.6<br>32<br>38.4<br>kHz<br>DCHCLKHF<br>HFOSC DutyCycle (Clock High Period)<br>45<br>50<br>55<br>%<br>DCHCLKLF<br>LFOSC Duty Cycle (Clock High Period)<br>45<br>50<br>55<br>%<br>~~=~~|||||
|**3.20. User I2C Characteristics**|||||
|**Table 3.36. User I2C Specifications(VCC = 1.0 V)**|||||
|**Symbol**<br>**Parameter**<br>**Description**<br>**STD Mode**<br>**FAST Mode**<br>**FAST Mode Plus2**<br>**Units**<br>**Min**<br>**Typ**<br>**Max**<br>**Min**<br>**Typ**<br>**Max**<br>**Min**<br>**Typ**<br>**Max**<br>fscl<br>SCL Clock Frequency<br>—<br>—<br>100<br>—<br>—<br>400<br>—<br>—<br>1000<br>kHz<br>TDELAY1<br>Optional delay<br>through delayblock<br>—<br>—<br>62<br>—<br>—<br>62<br>—<br>—<br>62<br>ns<br>~~——---.-.——~~|||||
|**Notes**:|||||
|1.<br>Refer to the I2C Specification for timing requirements. User design should set constraints in Lattice Design software to meet this|C Specification for timing requirements. User design should set constraints in Lattice Design software to meet this||||
|industrial I2C Specification.|||||
2. Fast Mode Plus maximum speed may be achieved by using external pull up resistor on I[2] C bus. Internal pull up may not be sufficient to support the maximum speed.
## **3.21. sysCONFIG Port Timing Specifications**
Over recommended operating conditions.
**Table 3.37. sysCONFIG Port Timing Specifications**
|**Symbol**|**Parameter**|**Min**|**Typ.**|**Max**|**Unit**|
|---|---|---|---|---|---|
|**Master SPI POR/REFRESH Timing**||||||
|tICFG|REFRESH command executed, to the rising edge of<br>INITN (bulk-erase off)|—|—|30|µs|
|tVMC|Time from rising edge of INITN to the valid Master<br>MCLK|—|—|5|µs|
|fMCLK_DEF|Default MCLK frequency (Before MCLK frequency<br>selection in bitstream)|—|3.5|—|MHz|
|tICFG_POR|Time during POR, from VCC, VCCAUX, VCCIO0, or<br>VCCIO1 (whichever is the last) pass POR trip voltage, to<br>the rising edge if INITN|—|—|5|ms|
© 2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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a@LATTICE
|**Symbol**<br>~~eS~~|**Parameter**<br>|**Min**<br>|**Typ.**<br>|**Max**<br>|**Unit**<br>|
|---|---|---|---|---|---|
|**Slave SPI/I2C/I3C POR**<br>~~eSa~~||||||
|tMSPI_INH<br>~~a~~|Time during POR, from VCC, VCCAUX, VCCIO0or VCCIO1<br>(whichever is the last) pass POR trip voltage, to pull<br>PROGRAMN LOW to prevent entering MSPI mode<br>~~ee~~<br>|—<br>|—<br>|1<br>|µs<br>|
|tACT_PROGRAMN_H<br>~~a~~<br>~~a~~|Minimum time driving PROGRAMN HIGH after last<br>activation clock<br>~~a~~<br>~~ee~~<br>|50<br>~~a~~<br>|—<br>~~a~~<br>|—<br>~~a~~<br>|ns<br>~~a~~<br>|
|tCONFIG_CCLK<br>~~a~~|Minimum time to start driving CCLK (SSPI) after<br>PROGRAMN HIGH<br>~~ee~~<br>|50<br>|—<br>|—<br>|ns<br>|
|tCONFIG_SCL<br>~~a~~|Minimum time to start driving SCL (I2C/I3C) after<br>PROGRAMN HIGH<br>~~a~~|50<br>~~a~~|—<br>~~a~~|—<br>~~a~~|ns<br>~~a~~|
|**PROGRAMN Configuration Timing**<br>~~a~~||||||
|tPROGRAMN_L<br>~~a~~<br>~~a~~|PROGRAMN LOW pulse accepted<br>~~a~~<br>~~a~~|50<br>~~a~~<br>~~a~~|—<br>~~a~~<br>~~a~~|—<br>~~a~~<br>~~a~~|ns<br>~~a~~<br>~~a~~|
|tPROGRAMN_H<br>~~a~~|PROGRAMN HIGHpulse accepted<br>~~a~~|60<br>~~a~~|—<br>~~a~~|—<br>~~a~~|ns<br>~~a~~|
|tPROGRAMN_RJ<br>~~a~~|PROGRAMN LOW pulse rejected<br>~~a~~|—<br>~~a~~|—<br>~~a~~|25<br>~~a~~|ns<br>~~a~~|
|tINIT_LOW<br>~~a~~|PROGRAMN LOW to INITN LOW<br>~~a~~|—<br>~~a~~|—<br>~~a~~|100<br>~~a~~|ns<br>~~a~~|
|tINIT_HIGH<br>~~a~~|PROGRAMN LOW to INITN HIGH (bulk-erase off)<br>~~a~~|—<br>~~a~~|30<br>~~a~~|—<br>~~a~~|µs<br>~~a~~|
|tDONE_LOW<br>~~a~~<br>~~ee~~|PROGRAMN LOW to DONE LOW<br>~~a~~<br>|—<br>~~a~~<br>|—<br>~~a~~<br>|55<br>~~a~~<br>|µs<br>~~a~~<br>|
|tDONE_HIGH2<br>~~ee~~|PROGRAMN HIGH to DONE HIGH<br>|—<br>|—<br>|2<br>|s<br>|
|tIODISS<br>~~eea~~|PROGRAMN LOW to I/O Disabled<br>~~a~~|—<br>~~a~~|—<br>~~a~~|125<br>~~a~~|ns<br>~~a~~|
|**Master SPI**<br>~~a~~||||||
|fMCLK1<br>~~a~~|Max selected MCLK output frequency<br>~~a~~|—<br>~~a~~|150<br>~~a~~|165<br>~~a~~|MHz<br>~~a~~|
|fMCLK_DC<br>~~a~~<br>~~a~~|MCLK output clock duty cycle<br>~~a~~<br>~~a~~|40<br>~~a~~<br>~~a~~|—<br>~~a~~<br>~~a~~|60<br>~~a~~<br>~~a~~|%<br>~~a~~<br>~~a~~|
|tMCLKH<br>~~a~~|MCLK output clock pulse width HIGH<br>~~a~~|3<br>~~a~~|—<br>~~a~~|—<br>~~a~~|ns<br>~~a~~|
|tMCLKL<br>~~a~~<br>~~a~~|MCLK output clock pulse width LOW<br>~~a~~<br>~~a~~|3<br>~~a~~<br>~~a~~|—<br>~~a~~<br>~~a~~|—<br>~~a~~<br>~~a~~|ns<br>~~a~~<br>~~a~~|
|tSU_MSI<br>~~a~~|MSI to MCLK setup time<br>~~a~~|3<br>~~a~~|—<br>~~a~~|—<br>~~a~~|ns<br>~~a~~|
|tHD_MSI<br>~~a~~<br>~~a~~|MSI to MCLK hold time<br>~~a~~<br>~~a~~|0.5<br>~~a~~<br>~~a~~|—<br>~~a~~<br>~~a~~|—<br>~~a~~<br>~~a~~|ns<br>~~a~~<br>~~a~~|
|tCO_MSO2<br>~~a~~|MCLK to MSO delay<br>~~a~~|—<br>~~a~~|—<br>~~a~~|12<br>~~a~~|ns<br>~~a~~|
|**Slave SPI**<br>~~a~~||||||
|fCCLK<br>~~a~~<br>~~a~~|CCLK input clock frequency<br>~~a~~<br>~~a~~|—<br>~~a~~<br>~~a~~|—<br>~~a~~<br>~~a~~|135<br>~~a~~<br>~~a~~|MHz<br>~~a~~<br>~~a~~|
|tCCLKH<br>~~a~~<br>~~ee~~|CCLK input clock pulse width HIGH<br>~~a~~|3.5<br>~~a~~|—<br>~~a~~|—<br>~~a~~|ns<br>~~a~~|
|tCCLKL<br>~~a~~<br>~~ee~~<br>~~pf~~|CCLK input clock pulse width LOW<br>~~a~~<br>~~pf_____{_|—__}__|~~|3.5<br>~~a~~<br>~~_____{_|—__}__|~~|—<br>~~a~~<br>~~_____{_|—__}__|~~|—<br>~~a~~<br>~~_____{_|—__}__|~~|ns<br>~~a~~<br>~~_____{_|—__}__|—~~|
|tVMC_SLAVE<br>~~ee~~<br>~~pf~~|Time from rising edge of INITN to Slave CCLK driven<br>~~pf_____{_|—__}__|~~|50<br>~~_____{_|—__}__|~~|—<br>~~_____{_|—__}__|~~|—<br>~~_____{_|—__}__|~~|ns<br>~~_____{_|—__}__|—~~|
|tVMC_MASTER<br>~~pf~~|CCLK input clock duty cycle<br>~~pf_____{_|—__}__|~~|40<br>~~_____{_|—__}__|~~|—<br>~~_____{_|—__}__|~~|60<br>~~_____{_|—__}__|~~|%<br>~~_____{_|—__}__|—~~|
|tSU_SSI<br>~~pf~~<br>~~a~~|SSI to CCLK setup time<br>~~pf _____{_|—__}__|~~|3.2<br>~~_____{_|—__}__|~~|—<br>~~_____{_|—__}__|~~|—<br>~~_____{_|—__}__|~~|ns<br>~~_____{_|—__}__| —~~|
|tHD_SSI<br>~~a~~<br>~~a~~|SSI to CCLK hold time|1.9|—|—|ns|
|tCO_SSO<br>~~a~~|CCLK falling edge to valid SSO output|—|—|30|ns|
|tEN_SSO<br>~~a~~<br>~~a~~|CCLK falling edge to SSO output enabled|—|—|30|ns|
|tDIS_SSO<br>~~a~~|CCLK falling edge to SSO output disabled|—|—|30|ns|
|tHIGH_SCSN<br>~~a~~|SCSN HIGH time|74|—|—|ns|
|tSU_SCSN<br>~~a~~<br>~~a~~<br>~~ee~~|SCSN to CCLK setup time<br>|3.5<br>|—<br>|—<br>|ns<br>|
|tHD_SCSN<br>~~ee~~|SCSN to CCLK hold time<br>|1.6<br>|—<br>|—<br>|ns<br>|
|**I2C/I3C**<br>~~eea~~<br>~~ee~~||||||
|fSCL_I2C<br>~~a~~<br>~~ee~~|SCL input clock frequency for I2C<br>~~a~~|—<br>~~a~~|—<br>~~a~~|1<br>~~a~~|MHz<br>~~a~~|
|fSCL_I3C<br>~~ee~~<br>~~a~~|SCL input clock frequency for I3C|—|—|12|MHz|
|tSCLH_I2C<br>~~a~~<br>~~a~~<br>~~ee~~|SCL input clock pulse width HIGH for I2C|400|—|—|ns|
|tSCLL_I2C<br>~~ee~~|SCL input clock pulse width LOW for I2C|400|—|—|ns|
© 2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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mLATTICE
|**Symbol**<br>~~a~~|**Parameter**<br>~~a~~|**Min**<br>~~a~~|**Typ.**<br>~~a~~|**Max**<br>~~a~~|**Unit**<br>~~a~~|
|---|---|---|---|---|---|
|tSU_SDA_I2C<br>~~a~~|SDA to SCL setup time for I2C<br>~~a~~|250<br>~~a~~|—<br>~~a~~|—<br>~~a~~|ns<br>~~a~~|
|tHD_SDA_I2C<br>~~a~~|SDA to SCL hold time for I2C<br>~~a~~|50<br>~~a~~|—<br>~~a~~|—<br>~~a~~|ns<br>~~a~~|
|tSU_SDA_I3C<br>~~a~~|SDA to SCL setup time for I3C<br>~~a~~|30<br>~~a~~|—<br>~~a~~|—<br>~~a~~|ns<br>~~a~~|
|tHD_SDA_I3C<br>~~a~~|SDA to SCL hold time for I3C<br>~~a~~|30<br>~~a~~|—<br>~~a~~|—<br>~~a~~|ns<br>~~a~~|
|tCO_SDA<br>~~a~~|SCL falling edge to valid SDA output<br>~~a~~|—<br>~~a~~|—<br>~~a~~|200<br>~~a~~|ns<br>~~a~~|
|tEN_SDA<br>~~a~~|SCL falling edge to SDA output enabled<br>~~a~~|—<br>~~a~~|—<br>~~a~~|200<br>~~a~~|ns<br>~~a~~|
|tDIS_SDA<br>~~a~~<br>~~a~~|SCL falling edge to SDA output disabled<br>~~a~~<br>~~a~~|—<br>~~a~~<br>~~a~~|—<br>~~a~~<br>~~a~~|200<br>~~a~~<br>~~a~~|ns<br>~~a~~<br>~~a~~|
|**Wake-Up Timing**<br>~~a~~<br>~~eeee~~||||||
|tWAKEUP_DONE_HIGH2<br>~~a~~|Last configuration clock cycle to DONE going HIGH<br>~~a~~<br>~~ee~~|—<br>~~a~~<br>~~ee~~|—<br>~~a~~<br>~~ee~~|60<br>~~a~~|µs<br>~~a~~|
|tFIO_EN2<br>~~se~~|User I/O enabled in Early I/O Mode<br>~~ee ~~<br>~~se~~|—<br> ~~ee~~<br>~~se~~|~~ee~~<br>~~se~~|31184<br>~~se~~|cycles<br>~~se~~|
|tIOEN2<br>~~a~~|Config clock to user I/O enabled|130|—|—|ns|
|tMCLKZ2, 3<br>~~a~~|Master MCLK to Hi-Z|—|—|2.5|µs|
**Notes** :
1. fMCLK has a dependency on HFOSC and is 1/3 of fCLKHF.
2. Based on 30k uncompressed/unauthenticated/default MCLK timing (3.5 MHz)/x1. Other permutations result in different values.
3. Measure using LVCMOS18, default MCLK frequency, slow slew rate.
**==> picture [440 x 192] intentionally omitted <==**
**----- Start of picture text -----**<br>
REFRESH Command tICFG<br>VCC/VCCAUX/<br>VCCIO0/VCCIO1 tICFG_POR<br>INITN WY<br>DONE<br>Wi<br>PROGRAMN fMCLK_DEF<br>tVMC<br>MCLK<br>MSI<br>**----- End of picture text -----**<br>
**Figure 3.14. Master SPI POR/REFRESH Timing**
© 2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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## REFRESH Command
**==> picture [435 x 203] intentionally omitted <==**
**----- Start of picture text -----**<br>
VCC/VCCAUX/<br>VCCIO0/VCCIO1<br>tICFG<br>INITN<br>DONE<br>tMSPI_INH Slave Activation —| tACT_PROGRAMN_H<br>PROGRAMN<br>fCCLK tCONFIG_CCLK<br>CCLK<br>SSI<br>fSCL tACT_PROGRAMN_H<br>tCONFIG_SCL<br>SCL<br>A URORE A<br>SDA<br>**----- End of picture text -----**<br>
**Figure 3.15. Slave SPI/I[2] C/I3C POR/REFRESH Timing**
**Figure 3.16. Master SPI PROGRAMN Timing**
© 2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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**Figure 3.17. Slave SPI/I[2] C/I3C PROGRAMN Timing**
**==> picture [264 x 128] intentionally omitted <==**
**----- Start of picture text -----**<br>
fMCLK<br>tMCLKH ——_ ><br>< —_____—_ tMCLKL<br>MCLK tSU_MISO —__ tHD_MISO<br>MSI<br>tCO_MOSI<br>—~r | ~~<br>MSO<br>**----- End of picture text -----**<br>
**Figure 3.18. Master SPI Configuration Timing**
© 2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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**==> picture [15 x 7] intentionally omitted <==**
**----- Start of picture text -----**<br>
fCCLK<br>**----- End of picture text -----**<br>
**==> picture [323 x 184] intentionally omitted <==**
**----- Start of picture text -----**<br>
tCCLKH<br>CCLK<br>tCCLKL<br>tSU_MOSI tHD_MOSI<br>SSI<br>tSU_SCSN tHD_SCSN<br>SCSN = ===<br>tHIGH_SCSN<br>tCO_MISO<br>SSO<br>—— —<br>tEN_MISO tDIS_MISO<br>SSO<br>ee ae<br>**----- End of picture text -----**<br>
**Figure 3.19. Slave SPI Configuration Timing**
**==> picture [343 x 369] intentionally omitted <==**
**----- Start of picture text -----**<br>
fSCL<br>tSCLH<br>SCL<br>tSCLL<br>tSU_SDA tHD_SDA<br>SDA (input)<br>tCO_SDA<br>SDA (output)<br>tDIS_SDA<br>tEN_SDA<br>SDA (output)<br>i e e e ae<br>Figure 3.20. I [2] C /I3C Configuration Timing<br>CRESET_B<br>INITN<br>tWAKEUP_DONE_HIGH Device Wake-Up<br>DONE<br>CONFIG tMWC<br>Starts fMCLK_def fMCLK tMCLKZ<br>MCLK<br>tFIO_EN<br>USER I/O tIOEN<br>(FAST I/O)<br>tIOEN<br>USER I/O<br>**----- End of picture text -----**<br>
**Figure 3.21. Master SPI Wake-Up Timing**
© 2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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**==> picture [461 x 298] intentionally omitted <==**
**----- Start of picture text -----**<br>
CRESET_B<br>INITN<br>tWAKEUP_DONE_HIGH Device Wake-Up<br>DONE<br>CONFIG<br>Starts<br>CCLK/SCL<br>tFIO_EN<br>USER I/O tIOEN<br>(FAST I/Os)<br>tIOEN<br>eee<br>USER I/O<br>no<br>Figure 3.22. Slave SPI/I [2] C/I3C Wake-Up Timing<br>tINIT_HIGH tPROGRAM_H MSPI<br>Configuration<br>PROGRAMN<br>tPROGRAM_L SSPI/I2C/I3C<br>tINITL Configuration tINIT_HIGH Configuration<br>Error<br>INITN<br>tINIT_HIGH Restart<br>Configuration<br>Configuration<br>DONE Started<br>**----- End of picture text -----**<br>
**==> picture [164 x 9] intentionally omitted <==**
**----- Start of picture text -----**<br>
Note: tINITL = SRAM Memory Initialization Period<br>**----- End of picture text -----**<br>
**Figure 3.23. Configuration Error Notification**
## **3.22. AON Block Specifications (VCCAUX_AON = 1.8V)**
Over recommended operating conditions.
**Table 3.38. AON Block Specification (VCCAUX_AON = 1.8 V)**
|**Symbol**|**Description**|**Condition**|**Min**|**Typ.**|**Max**|**Unit**|
|---|---|---|---|---|---|---|
|ICCAUX_AON|AON Supply Current|—|—|70|—|uA|
|fOSC_AON_TIMER_CAL|Internal timer calibration frequency|—|—|11|—|kHz|
|tPWRDN|Power down time|—|—|—|90|sec|
|tPWRDN|Power down time|—|2.5|—|—|ms|
**Note:** AON is only supported in LIFCL-33U.
© 2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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## **3.23. Hardened USB Specifications**
Over recommended operating conditions.
**Table 3.39. Hardened USB2 Specifications**
|**Symbol**|**Description**|**Condition**|**Min**|**Typ.**|**Max**|**Unit**|
|---|---|---|---|---|---|---|
|fREF_CLK|Reference Clock Frequency|—|12/24/60|||MHz|
|tOFFSET|Clock offset|—|-300|—|300|ppm|
|tDUTY|Clock duty cycle|—|40|—|60|%|
|tRAN_JIT|Random Jitter|—|—|—|32|ps|
|tP2P_JIT|Period to Period Jitter|—|-100|—|1003|ps|
## **Notes:**
1. USB 2.0 is only supported in LIFCL-33U.
2. tRAN_JIT 1.5M to Nyquist frequency (Clock frequency/2).
3. tP2P_JIT is less than 10 MHz.
**Table 3.40. Hardened USB3 Specifications**
|**Symbol**<br>~~a ~~<br>~~ee~~|**Description**<br> ~~GG~~|**Condition**<br>~~GG~~|**Min**<br>~~GG~~|**Typ.**<br>~~GG~~|**Max**<br>~~GG~~|**Unit**<br>~~GG~~|
|---|---|---|---|---|---|---|
|fREF_CLK<br>~~ee~~<br>~~ee~~|Reference Clock Frequency<br>~~Se~~|—<br>~~GG~~|25/50/60<br>~~GG~~<br>~~GO~~|||MHz|
|tOFFSET<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|Clock offset<br>~~Se~~<br>~~eG~~<br>|—<br>~~GG~~<br>~~eG~~<br>|-150<br>~~GG~~<br>~~eG~~<br>|—<br>~~GO~~<br>~~eG~~<br>~~GO~~<br>|150<br>~~eG~~<br>|ppm<br>~~eG~~<br>|
|tDUTY<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|Clock duty cycle<br>~~Se~~<br>~~eG~~<br><br>|—<br>~~GG~~<br>~~eG~~<br><br>|40<br>~~GG~~<br>~~eG~~<br><br>|—<br>~~GO~~<br>~~eG~~<br>~~GO~~<br><br>~~**GO**~~<br>|60<br>~~eG~~<br><br>|%<br>~~eG~~<br><br>|
|tRAN_JIT<br>~~ee~~<br>~~ee~~<br>~~ee~~|Random Jitter<br>~~eG~~<br>~~eG~~<br>|—<br>~~eG~~<br>~~eG~~<br>|—<br>~~eG~~<br>~~eG~~<br>|—<br>~~eG~~<br>~~GO~~<br>~~eG~~<br>~~**GO**~~<br>|32<br>~~eG~~<br>~~eG~~<br>|ps<br>~~eG~~<br>~~eG~~<br>|
|tSKEW<br>~~ee~~<br>~~ee~~|Clock Skew<br>~~eG~~<br>~~eG~~|—<br>~~eG~~<br>~~eG~~|—<br>~~eG~~<br>~~eG~~|—<br>~~GO~~<br>~~eG~~<br>~~**GO**~~<br>~~eG~~|200<br>~~eG~~<br>~~eG~~|ps<br>~~eG~~<br>~~eG~~|
|tP2P_JIT<br>~~ee~~|Period to Period Jitter<br>~~eG~~|—<br>~~eG~~|-75<br>~~eG~~|—<br>~~**GO**~~<br>~~eG~~|753<br>~~eG~~|ps<br>~~eG~~|
|vCOMM|Input Common Mode Level|—|0|—|AVDD--0.5 *<br>Peak-Peak<br>Differential<br>swing4|V|
## **Notes:**
1. USB 3.2 Gen 1 is only supported in LIFCL-33U -9 speed grade.
2. tRAN_JIT 1.5M to Nyquist frequency (Clock frequency/2).
3. tP2P_JIT is less than 10 MHz.
4. VCOMM is only for external REFCLK:REFIN_CLK_EXT_P/N.
## **3.24. JTAG Port Timing Specifications**
Over recommended operating conditions.
**Table 3.41. JTAG Port Timing Specifications**
|**Symbol**<br>~~GO~~|**Parameter**<br>~~GO~~|**Min**<br>~~GO~~|**Typ. **<br>~~GO~~|**Max**<br>~~GO~~|**Units**<br>~~GO~~|
|---|---|---|---|---|---|
|fMAX<br>~~GO~~<br>~~Ce~~|TCK clock frequency<br>~~GO~~<br>~~Ce~~|—<br>~~GO~~<br>~~Ce~~|—<br>~~GO~~<br>~~Ce~~|25<br>~~GO~~<br>~~Ce~~|MHz<br>~~GO~~<br>~~Ce~~|
|tBTCPH<br>~~eG~~|TCK clockpulse width high<br>~~eG~~|20<br>~~eG~~|—<br>~~eG~~|—<br>~~eG~~|ns<br>~~eG~~|
|tBTCPL<br>~~eG~~<br>~~es~~|TCK clockpulse width low<br>~~eG~~|20<br>~~eG~~|—<br>~~eG~~|—<br>~~eG~~|ns<br>~~eG~~|
|tBTS<br>~~es~~|TCK TAP setuptime|5|—|—|ns|
|tBTH<br>~~es~~<br>~~sD~~|TCK TAP hold time<br>~~sD~~|5<br>~~sD~~|—<br>~~sD~~|—<br>~~sD~~|ns<br>~~sD~~|
|tBTRF<br>~~sD~~<br>~~eG~~<br>~~a~~|TAP controller TDO rise/fall time1<br>~~sD~~<br>~~eG~~|100<br>~~sD~~<br>~~eG~~<br>~~GO~~|—<br>~~sD~~<br>~~eG~~<br>~~GO~~|—<br>~~sD~~<br>~~eG~~|mV/ns<br>~~sD~~<br>~~eG~~|
|tBTCO<br>~~eC~~<br>~~a~~|TAP controller fallingedge of clock to valid output<br>~~eC~~|—<br>~~eC~~<br>~~GO~~|—<br>~~eC~~<br>~~GO~~|14<br>~~eC~~|ns<br>~~eC~~|
|tBTCODIS<br>~~a~~|TAP controller fallingedge of clock to valid disable|—<br>~~GO~~|—<br>~~GO~~|14|ns|
© 2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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|**Symbol**|**Parameter**|**Min**|**Typ. **|**Max**|**Units**|
|---|---|---|---|---|---|
|tBTCOEN|TAP controller fallingedge of clock to valid enable|—|—|14|ns|
|tBTCRS|BSCAN test capture register setuptime|8|—|—|ns|
|tBTCRH|BSCAN test capture register hold time|25|—|—|ns|
|tBUTCO|BSCAN test update register, fallingedge of clock to valid output|—|—|25|ns|
|tBTUODIS|BSCAN test update register, fallingedge of clock to valid disable|—|—|25|ns|
|tBTUPOEN|BSCAN test update register, fallingedge of clock to valid enable|—|—|25|ns|
**Note:**
1. Based on default I/O setting of slow slew rate.
**==> picture [495 x 548] intentionally omitted <==**
**----- Start of picture text -----**<br>
TMS<br>TDI<br>tBTS tBTH<br>tBTCPH tBTCPL tBTCP<br>TCK<br>tBTCOEN tBTCO tBTCODIS<br>TDO V dilaD aat V dilaD aat<br>tBTCRH<br>tBTCRS<br>Data to be<br>Captured Data Captured<br>from I/O<br>tBTUPOEN tBUTCO tBTUODIS<br>Data to be<br>driven out V dilaD aat V dilaD aat<br>to I/O<br>Figure 3.24. JTAG Port Timing Waveforms<br>3.25. Switching Test Conditions<br>Figure 3.25 shows the output test load that is used for AC testing. The specific values for resistance, capacitance, voltage,<br>and other test conditions are listed in [=] Table 3.42.<br>© 2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.<br>All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.<br>**----- End of picture text -----**<br>
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**==> picture [190 x 123] intentionally omitted <==**
**----- Start of picture text -----**<br>
V T<br>R1<br>DUT Test Point<br>R2 CL*<br>:<br>**----- End of picture text -----**<br>
*CL Includes Test Fixture and Probe Capacitance
**Figure 3.25. Output Test Load, LVTTL, and LVCMOS Standards**
**Table 3.42. Test Fixture Required Components, Non-Terminated Interfaces**
|**Test Condition**|**R1**|**R2**|**CL**|**Timing Ref.**|**VT**|
|---|---|---|---|---|---|
|LVTTL and other LVCMOS settings (L ≥ H, H ≥ L)|||0 pF|LVCMOS 3.3 = 1.5 V|—|
|||||LVCMOS 2.5 = VCCIO/2|—|
|||||LVCMOS 1.8 = VCCIO/2|—|
|||||LVCMOS 1.5 = VCCIO/2|—|
|||||LVCMOS 1.2 = VCCIO/2|—|
|LVCMOS 2.5 I/O(Z ≥ H)||1 MΩ|0pF|VCCIO/2|—|
|LVCMOS 2.5 I/O(Z ≥ L)|1 MΩ||0pF|VCCIO/2|VCCIO|
|LVCMOS 2.5 I/O(H ≥ Z)||100|0pF|VOH– 0.10|—|
|LVCMOS 2.5 I/O(L ≥ Z)|100||0pF|VOL+ 0.10|VCCIO|
**Note** : Output test conditions for all other interfaces are determined by the respective standards.
© 2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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## **4. Pinout Information**
## **4.1. Signal Descriptions**
|**Signal Name**<br>~~a ~~<br>~~ee~~|**Bank**<br> ~~a~~|**Type **<br>~~a~~|**Description**|
|---|---|---|---|
|**Power and GND**<br>~~ee~~||||
|Vss, AVSSx, VSS_AON1<br>~~ee~~|—|GND|Ground for internal FPGA logic, USB logic, Always ON(AON), and I/O|
|VCC<br>~~ee~~|—|Power|Power supply pins for core logic. VCCis connected to 1.0 V (nom.) supply<br>voltage. Power On Reset(POR)monitors this supplyvoltage.|
|VCCAUXA<br>~~a~~|—|Power|Auxiliary power supply pin for internal analog circuitry. This supply is<br>connected to 1.8 V (nom.) supply voltage. POR monitors this supply<br>voltage.|
|VCCAUX<br>~~rs~~|—<br>~~ee~~|Power<br>~~ee~~|Auxiliary power supply pin for I/O Bank 0, Bank 1, and Bank 5. This supply<br>is connected to 1.8 V (nom.) supply voltage, and is used for generating<br>stable drive current for the I/O.<br>~~ee~~|
|VCCAUXHx<br>~~rs~~|—<br>~~ee~~|Power<br>~~ee~~|Auxiliary power supply pin for I/O Bank 2, Bank 3, and Bank 4. This supply<br>is connected to 1.8 V (nom.) supply voltage and is used for generating<br>stable current for the differential input comparators.<br>~~ee~~|
|VCCAUX_AON1<br>~~rs~~<br>~~ee~~|81<br>~~ee~~<br>~~ee~~|Power<br>~~ee~~<br>~~ee~~|Auxiliary power for Always ON(AON)functional block<br>~~ee~~<br>~~ee~~|
|AVDD331<br>~~rs~~<br>~~ee~~<br>~~ee~~|80<br>~~ee~~<br>~~ee~~<br>~~ee~~|Power<br>~~ee~~<br>~~ee~~<br>~~ee~~|3.3 Vpower for Hardened USB Block<br>~~ee~~<br>~~ee~~|
|AVDD18, AVDD18_TX,<br>AVDD18_COM1<br>~~ee~~|80<br>~~ee~~|Power<br>~~ee~~|1.8 V power for Hardened USB Block|
|AVDD, AVDD_TX1<br>~~ee ~~|80<br> ~~ee ~~|Power<br> ~~ee~~|1.0 V power for Hardened USB Block|
|VCCIOx|0-42<br>0-53|Power|Power supply pins for I/O bank x.<br>For x = 0, 1, and 5, VCCIO can be connected to (nom.) 1.2 V, 1.5 V, 1.8 V,<br>2.5 V, or 3.3 V.<br>For x = 2, 3, and 4, VCCIO can be connected to (nom.) 1.0 V, 1.2 V, 1.35 V,<br>1.5 V, or 1.8 V.<br>There are dedicated and shared configuration pins in banks 0 and 1. POR<br>monitors these banks supplyvoltages.|
|**Dedicated Pins**<br>~~SE~~||||
|**Dedicated Configuration I/O Pin**<br>~~SE~~<br>~~a~~||||
|JTAG_EN|1|Input|LVCMOS input pin. This input selects the JTAG shared GPIO to be used for<br>JTAG<br>0 = GPIO<br>1 = JTAG|
|**Misc Pins**<br>~~a~~<br>~~ee~~<br>~~a~~||||
|NC<br>~~a~~<br>~~a~~<br>~~a~~|—<br>~~a~~<br>~~a~~<br>~~ee~~<br>|—<br>~~a~~<br>~~a~~<br>|No connect.<br>~~a~~<br>~~a~~<br>|
|RESERVED<br>~~a~~<br>~~a~~|—<br>~~a~~<br>~~ee~~<br>~~ee~~|—<br>~~a~~<br>~~ee~~|This pin is reserved and should not be connected to anything on the<br>board.<br>~~a~~<br>~~ee~~|
|**Always ON (AON) I/O Pins**<br>~~ee~~<br>~~a ee~~<br>~~Cn~~||||
|AON_xxx1<br>~~Cn~~<br>~~ee~~|81<br>~~Cn~~<br>~~ee~~|Input,<br>Output<br>~~Cn~~<br>~~ee~~|Dedicated input and output pin for AON function<br>~~Cn~~<br>~~ee~~|
|**USB I/O Pins**<br>~~ee~~<br>~~a~~||||
|DP/DM, TX_M/P, RX_M/P<br>~~a~~<br>~~a~~<br>~~a~~|—<br>~~a~~<br>~~a~~<br>~~ee~~|Input,<br>Output<br>~~a~~<br>~~a~~|USB Data pins<br>~~a~~<br>~~a~~|
|REFIN_CLK_EXT_P/N<br>~~a~~<br>~~a~~<br>~~a~~|—<br>~~a~~<br>~~a~~<br>~~ee~~|Input<br>~~a~~<br>~~a~~|USB Clock Pins<br>~~a~~<br>~~a~~|
|VBUS, REXT23<br>~~a~~|—<br>~~ee~~|Input,<br>Output|USB Control pins|
© 2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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|**Signal Name**|**Bank**|**Type **|**Description**|
|---|---|---|---|
|**General Purpose I/O Pins**||||
||||Programmable User I/O:|
||||[T/B/L/R] indicates the package pin/ball is in T (Top), B (Bottom) of the|
||||device.|
||||[Number] identifies the PIO [A/B] pair.|
||||[A/B] shows the package pin/ball is A or B signal in the pair. PIO A and PIO|
||||B are grouped as a pair.|
||||Each A/B pair in the bottom banks supports true differential input and|
||||output buffers. When configured as differential input, differential|
||||termination of 100 Ω can be selected.|
||||Each A/B pair in the top bank does not support true differential input or|
||T = 0, 1, 5|Input,|output buffer. It supports all single-ended inputs and outputs, and can be|
|P[T/B] [Number]_[A/B]|B = 2, 3, 4|Output,|used for emulated differential output buffer.|
|||Bi-Dir|Some of these user-programmable I/O are used during configuration,|
||||depending on the configuration mode. User needs to make appropriate|
||||connection on the board to isolate the two different functions|
||||before/after configuration.|
||||Some of these user-programmable I/O are shared with special function|
||||pins. These pins, when not used as special purpose pins, can be|
||||programmed as I/O for user logic.|
||||During configuration the user-programmable I/O are tri-stated with an|
||||internal weak pull-down resistor enabled. If any pin is not used (or not|
||||bonded to a package pin), it is tri-stated and default to have weak pull-|
||||down enabled after configuration.|
## **Shared Configuration Pins**
**1. These pins can be used for configuration during configuration mode. When configuration is completed, these pins can be used as GPIO, or shared function in GPIO. When these pins are used in dual function, the users need to isolate the signal paths for the dual functions on the board.**
**2. The pins used are defined by the configuration modes detected. Slave SPI or I[2] C/I3C modes are detected during slave activation. Pins that are not used in the configuration mode selected are tri-stated during configuration, and can connect directly as GPIO in user’s function.**
||||Configuration:|
|---|---|---|---|
|||Input,|I2C/I3C Mode: SDA signal|
|PTxxx/SDA/USER_SDA|1|Output,|User Mode:|
|||Bi-Dir|PTxxx: GPIO|
||||User_SDA: SDA signal for I2C/I3C interface|
||||Configuration:|
|||Input,|I2C/I3C Mode: SCL signal|
|PTxxx/SCL/USER_SCL|1|Output,|User Mode:|
|||Bi-Dir|PTxxx: GPIO|
||||User_SDA: SCL signal for I2C/I3C interface|
||||Configuration:|
|||Input,|Slave SPI Mode: Slave Serial Output|
|PTxxx/TDO/SSO|1|Output,|User Mode:|
|||Bi-Dir|PTxxx: GPIO|
||||TDO: When JTAG_EN = 1, used as TDO signal for JTAG|
||||Configuration:|
|||Input,|Slave SPI Mode: Slave Serial Input|
|PTxxx/TDI/SSI|1|Output,|User Mode:|
|||Bi-Dir|PTxxx: GPIO|
||||TDI: When JTAG_EN = 1, used as TDI signal for JTAG|
© 2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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**CrossLink-NX-33 and CrossLinkU-NX Data Sheet**
mLATTICE
|**Signal Name**|**Bank**|**Type **|**Description**|
|---|---|---|---|
|PTxxx/TMS/SCSN|1|Input,<br>Output,<br>Bi-Dir|Configuration:<br>Slave SPI Mode: Slave Chip Select<br>User Mode:<br>PTxxx: GPIO<br>TMS: When JTAG_EN = 1, used as TMS signal for JTAG|
|PTxxx/TCK/SCLK|1|Input,<br>Output,<br>Bi-Dir|Configuration:<br>Slave SPI Mode: Slave Clock Input<br>User Mode:<br>PTxxx: GPIO<br>TCK: When JTAG_EN = 1, used as TCK signal for JTAG|
|PTxxx/MCSNO|0|Input,<br>Output,<br>Bi-Dir|Configuration:<br>Flow-through Daisy Chain Mode: Chip Select Output<br>User Mode:<br>PTxxx: GPIO|
|PTxxx/MD3|0|Input,<br>Output,<br>Bi-Dir|Configuration:<br>Master Quad SPI Mode: I/O3<br>User Mode:<br>PTxxx: GPIO|
|PTxxx/MD2|0|Input,<br>Output,<br>Bi-Dir|Configuration:<br>Master Quad SPI Mode: I/O2<br>User Mode:<br>PTxxx: GPIO|
|PTxxx/MSI/MD1|0|Input,<br>Output,<br>Bi-Dir|Configuration:<br>Master SPI Mode: Master Serial Input<br>Master Quad SPI Mode: I/O1<br>User Mode:<br>PTxxx: GPIO|
|PTxxx/MSO/MD0|0|Input,<br>Output,<br>Bi-Dir|Configuration:<br>Master SPI Mode: Master Serial Output<br>Master Quad SPI Mode: I/O0<br>User Mode:<br>PTxxx: GPIO|
|PTxxx/MCSN/PCLKT0_1|0|Input,<br>Output,<br>Bi-Dir|Configuration:<br>Master SPI Mode: Master Chip Select Output<br>User Mode:<br>PTxxx: GPIO<br>PCLKT0_0: Top PCLK Input|
|PTxxx/MCLK/PCLKT0_0|0|Input,<br>Output,<br>Bi-Dir|Configuration:<br>Master SPI Mode: Master Clock Output<br>User Mode:<br>PTxxx: GPIO<br>PCLKT0_1: Top PCLK Input|
|PTxxx/PROGRAMN|0|Input,<br>Output,<br>Bi-Dir|Configuration:<br>PROGRAMN: Initiate configuration sequence when asserted LOW.<br>User Mode:<br>PTxxx: GPIO|
© 2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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**CrossLink-NX-33 and CrossLinkU-NX Data Sheet**
mLATTICE
|**Signal Name**|**Bank**|**Type **|**Description**|
|---|---|---|---|
||||Configuration:|
||||INITN: Open Drain I/O pin. This signal is driven to LOW when configuration|
|PTxxx/INITN|0|Input,<br>Output,<br>Bi-Dir|sequence is started, to indicate the device is in initialization state. This<br>signal is released after initialization is completed, and the configuration<br>download can start. User can keep drive this signal LOW to delay<br>configuration download to start.|
||||User Mode:|
||||PTxxx: GPIO|
||||Configuration:|
||||DONE: Open Drain I/O pin. This signal is driven to LOW during|
|||Input,|configuration time. It is released to indicate the device has completed|
|PTxxx/DONE|0|Output,|configuration. User can keep drive this signal LOW to delay the device to|
|||Bi-Dir|wake up from configuration.|
||||User Mode:|
||||PTxxx: GPIO|
## **Shared User GPIO Pins**
**1. Shared User GPIO pins are pins that can be used as GPIO, or functional pins that connect directly to specific functional blocks, when device enters into User Mode.**
**2. Declaring on assigning the pin as GPIO or specific functional pin is done by configuration bitstream, except JTAG pins.**
**3. JTAG pins are controlled by JTAG_EN signal. When JTAG_EN = 1, the pins are used for JTAG interface. When JTAG = 0, the pins are used as GPIO or specific functional pin defined by configuration bitstream.**
**4. Refer to package pin file.**
|**4.**<br>**Refer to package pin file.**||||
|---|---|---|---|
|**Shared JTAG Pins**||||
||||User Mode:|
||||PTxxx: GPIO|
||||TDO: When JTAG_EN = 1, used as TDO signal for JTAG|
||||yyyy: Other possible selectable specific functional|
|||Input,||
|PTxxx/TDO/yyyy|1|Output,||
|||Bi-Dir||
||||User Mode:|
|||Input,|PTxxx: GPIO|
|PTxxx/TDI/yyyy|1|Output,|TDI: When JTAG_EN = 1, used as TDI signal for JTAG|
|||Bi-Dir|yyyy: Other possible selectable specific functional|
||||User Mode:|
|||Input,|PTxxx: GPIO|
|PTxxx/TMS/yyyy|1|Output,<br>Bi-Dir|TMS: When JTAG_EN = 1, used as TMS signal for JTAG<br>yyyy: Other possible selectable specific functional|
||||User Mode:|
|||Input,|PTxxx: GPIO|
|PTxxx/TCK/ yyy|1|Output,<br>Bi-Dir|TCK: When JTAG_EN = 1, used as TCK signal for JTAG<br>Yyyy: Other possible selectable specific functional|
© 2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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**CrossLink-NX-33 and CrossLinkU-NX Data Sheet**
mLATTICE
|**Signal Name**|**Bank**|**Type **|**Description**|
|---|---|---|---|
|**Shared CLOCK Pins**<br>**1.**<br>**Some PCLK pins can also be used as GPLL reference clock input pin. Refer tosysCLOCK PLL Design and User Guide for Nexus**<br>**Platform (FPGA-TN-02095).**||||
|PBxxx/PCLK[T,C][2,3,4]_[0-<br>3]/yyyy|2, 3, 4|Input,<br>Output,<br>Bi-Dir|User Mode:<br>PBxxx: GPIO<br>PCLK: Primary Clock or GPLL Refclk signal<br>[T,C] = True/Complement when using differential signaling<br>[2,3,4] = Bank<br>[0-3] Up to 4 signals in the bank<br>yyyy: Otherpossible selectable specific functional|
|PTxxx/PCLKT0_[0-1]/yyyy|0|Input,<br>Output,<br>Bi-Dir|User Mode:<br>PTxxx: GPIO<br>PCLKT: Primary Clock or GPLL Refclk signal (Only Single Ended)<br>[0-1] Up to 2 signals in the bank<br>yyyy: Other possible selectable specific functional|
|PTxxx/PCLKT1_[0-3]/yyyy|1|Input,<br>Output,<br>Bi-Dir|User Mode:<br>PTxxx: GPIO<br>PCLKT: Primary Clock or GPLL Refclk signal (Only Single Ended)<br>[0-2] Up to 3 signals in the bank<br>yyyy: Other possible selectable specific functional|
|PBxxx/PCLK2_[0-3]/yyyy|2|Input,<br>Output,<br>Bi-Dir|User Mode:<br>PBxxx: GPIO<br>yyyy: Other possible selectable specific functional|
|PBxxx/LLC_GPLL[T,C]_IN/yyyy|4|Input,<br>Output,<br>Bi-Dir|User Mode:<br>PBxxx: GPIO<br>LLC_GPLL: Lower Left GPLL Refclk signal (PLLCK)<br>[T,C] = True/Complement when using differential signaling<br>yyyy: Other possible selectable specific functional|
|**Shared VREF Pins**||||
|PBxxx/VREF[2,3,4]_[1-2]/yyyy|2, 3, 4|Input,<br>Output,<br>Bi-Dir|User Mode:<br>PBxxx: GPIO<br>VREF: Reference Voltage for DDR memory function<br>[2,3,4] = Bank<br>[1-2] Up to VREFs for each bank<br>yyyy: Other possible selectable specific functional|
## **Notes:**
1. AON and all AVDD signals are only supported in LIFCL-33U.
2. Bank 0 to Bank 4 are supported in LIFCL-33U only.
3. Bank 0 to Bank 5 are supported in LIFCL-33 only.
© 2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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**CrossLink-NX-33 and CrossLinkU-NX Data Sheet**
nrLATTICE
## **4.2. Pin Information Summary**
|**Pin Information Summary**<br>~~po~~|**Pin Information Summary**<br>~~po~~|**NX33-84WLCSP**|**NX33U-84WLCSP**|**NX33U-104FCCSP**|
|---|---|---|---|---|
|**User I/O Pins**<br>~~po~~<br>~~EE"!~~|||||
|General Purpose I/O per Bank|Bank 0<br>~~eG~~|7<br>~~eG~~|7<br>~~eG~~|8<br>~~eG~~|
||Bank 1<br>~~se~~<br>~~Rs~~|11<br>~~se~~|9<br>~~se~~|11<br>~~se~~|
||Bank 2<br>~~Rs~~|14|14|16|
||Bank 3<br>~~Rs~~<br>~~eG~~|10<br>~~eG~~|11<br>~~eG~~|12<br>~~eG~~|
||Bank 4<br>~~pO~~<br>~~es~~|2<br>~~pO~~|2<br>~~pO~~|4<br>~~pO~~|
||Bank 5<br>~~es~~|15|0|0|
|Total Single-Ended User I/O<br>~~es~~<br>~~GG~~||59<br>~~GG~~|43<br>~~GG~~|51<br>~~GG~~|
|Differential I/O Pairs<br>~~GG~~|Bank 0<br>~~GG~~<br>~~He~~|3<br>~~GG~~<br>~~He~~|3<br>~~GG~~<br>~~He~~|4<br>~~GG~~<br>~~He~~|
||Bank 1<br>~~se~~<br>~~Rs~~|5<br>~~se~~|4<br>~~se~~|5<br>~~se~~|
||Bank 2<br>~~Rs~~|7|7|8|
||Bank 3<br>~~Rs~~<br>~~eG~~|5<br>~~eG~~|5<br>~~eG~~|6<br>~~eG~~|
||Bank 4<br>~~eG~~|1<br>~~eG~~|1<br>~~eG~~|2<br>~~eG~~|
||Bank 5<br>~~eG~~|7<br>~~eG~~|0<br>~~eG~~|0<br>~~eG~~|
|Total Differential I/O Pairs<br>~~eG~~<br>~~GG~~||28<br>~~eG~~<br>~~GG~~|20<br>~~eG~~<br>~~GG~~|25<br>~~eG~~<br>~~GG~~|
|**Power Pins**<br>~~Ee"~~|||||
|VCC<br>~~GG~~||5<br>~~GG~~|5<br>~~GG~~|7<br>~~GG~~|
|VCCAUX<br>~~GG~~||5<br>~~GG~~|5<br>~~GG~~|5<br>~~GG~~|
|VCCIO<br>~~GG~~|Bank 0<br>~~GG~~<br>~~GG~~|1<br>~~GG~~<br>~~GG~~|1<br>~~GG~~<br>~~GG~~|1<br>~~GG~~<br>~~GG~~|
||Bank 1<br>~~sD~~|1<br>~~sD~~|1<br>~~sD~~|1<br>~~sD~~|
||Bank 2<br>~~eG~~<br>~~es~~|1<br>~~eG~~|1<br>~~eG~~|1<br>~~eG~~|
||Bank 3<br>~~eG~~<br>~~es~~<br>~~es~~|1<br>~~eG~~|1<br>~~eG~~|1<br>~~eG~~|
||Bank 4<br>~~es~~<br>~~es~~<br>~~es~~|1|1|1|
||Bank 5<br>~~es~~<br>~~es~~|1|0|0|
|Total Power Pins<br>~~es~~<br>~~Ge~~||16<br>~~Ge~~|15<br>~~Ge~~|17<br>~~Ge~~|
|**GND Pins**<br>~~Ge~~<br>~~Ee"~~|||||
|VSS<br>~~GG~~||8<br>~~GG~~|8<br>~~GG~~|11<br>~~GG~~|
|Total GND Pins<br>~~GG~~||8<br>~~GG~~|8<br>~~GG~~|11<br>~~GG~~|
|**USB Hardened Block Pins**<br>~~GG~~<br>~~a~~|||||
|Hardened USB Pairs<br>~~a~~<br>~~GG~~||0<br>~~a~~<br>~~GG~~|3<br>~~a~~<br>~~GG~~|4<br>~~a~~<br>~~GG~~|
|REXT23<br>~~GG~~||0<br>~~GG~~|1<br>~~GG~~|1<br>~~GG~~|
|VBUS<br>~~GG~~<br>~~GG~~||0<br>~~GG~~<br>~~GG~~|1<br>~~GG~~<br>~~GG~~|1<br>~~GG~~<br>~~GG~~|
|AVDD<br>~~GG~~<br>~~CG~~||0<br>~~GG~~<br>~~CG~~|4<br>~~GG~~<br>~~CG~~|6<br>~~GG~~<br>~~CG~~|
|AVSS<br>~~GG~~||0<br>~~GG~~|2<br>~~GG~~|4<br>~~GG~~|
|**Always ON Block Pins**<br>~~eee~~|||||
|Always ON I/O<br>~~eee~~<br>~~GG~~||0<br>~~eee~~<br>~~GG~~|2<br>~~eee~~<br>~~GG~~|2<br>~~eee~~<br>~~GG~~|
|VCCAUX<br>~~GG~~<br>~~GG~~||0<br>~~GG~~<br>~~GG~~|1<br>~~GG~~<br>~~GG~~|1<br>~~GG~~<br>~~GG~~|
|VSS||0|0|1|
© 2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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**CrossLink-NX-33 and CrossLinkU-NX Data Sheet**
nrLATTICE
|**Pin Information Summary**<br>~~DG~~|**Pin Information Summary**<br>~~DG~~|**NX33-84WLCSP**<br>~~DG~~|**NX33U-84WLCSP**<br>~~DG~~|**NX33U-104FCCSP**<br>~~DG~~|
|---|---|---|---|---|
|**Dedicated Miscellaneous Pins**<br>~~DG~~<br>~~Ee"!~~|||||
|JTAGEN<br>~~GG~~||1<br>~~GG~~|1<br>~~GG~~|1<br>~~GG~~|
|**Shared Pins**<br>~~eee~~<br>~~Re~~|||||
|Shared Configuration<br>Pins<br>~~eee~~|Bank 0<br>~~eee~~<br>~~Re~~<br>~~Re~~|7<br>~~eee~~|7<br>~~eee~~|7<br>~~eee~~|
||Bank 1<br>~~Re~~<br>~~Re~~<br>~~Re~~|9|8|9|
||Bank 2<br>~~Re~~<br>~~Re~~|0|0|0|
||Bank 3<br>~~Re~~<br>~~eG~~<br>~~Re~~|0<br>~~eG~~|0<br>~~eG~~|0<br>~~eG~~|
||Bank 4<br>~~eG~~<br>~~Re~~|0<br>~~eG~~|0<br>~~eG~~|0<br>~~eG~~|
||Bank 5<br>~~Re~~<br>~~eG~~|0<br>~~eG~~|0<br>~~eG~~|0<br>~~eG~~|
|Shared JTAG Pins|Bank 0<br>~~eG~~<br>~~Re~~|0<br>~~eG~~|0<br>~~eG~~|0<br>~~eG~~|
||Bank 1<br>~~eG~~<br>~~Re~~<br>~~Re~~|4<br>~~eG~~|4<br>~~eG~~|4<br>~~eG~~|
||Bank 2<br>~~Re~~<br>~~Re~~<br>~~Re~~|0|0|0|
||Bank 3<br>~~Re~~<br>~~Re~~|0|0|0|
||Bank 4<br>~~Re~~<br>~~eG~~|0<br>~~eG~~|0<br>~~eG~~|0<br>~~eG~~|
||Bank 5<br>~~eG~~<br>~~eG~~<br>~~ee~~|0<br>~~eG~~<br>~~eG~~|0<br>~~eG~~<br>~~eG~~|0<br>~~eG~~<br>~~eG~~|
|Shared PCLK Pins|Bank 0<br>~~ee~~|0|0|0|
||Bank 1<br>~~ee~~<br>~~eG~~<br>~~Re~~|4<br>~~eG~~|4<br>~~eG~~|4<br>~~eG~~|
||Bank 2<br>~~eG~~<br>~~Re~~<br>~~Re~~|8<br>~~eG~~|8<br>~~eG~~|8<br>~~eG~~|
||Bank 3<br>~~Re~~<br>~~Re~~|8|8|8|
||Bank 4<br>~~Re~~<br>~~eG~~<br>~~ee~~|2<br>~~eG~~|2<br>~~eG~~|2<br>~~eG~~|
||Bank 5<br>~~ee~~<br>~~Re~~|0|0|0|
|Shared GPLL Pins|Bank 0<br>~~ee~~<br>~~Re~~<br>~~Re~~|0|0|0|
||Bank 1<br>~~Re~~<br>~~Re~~|0|0|0|
||Bank 2<br>~~Re~~<br>~~eG~~<br>~~es~~|0<br>~~eG~~|0<br>~~eG~~|0<br>~~eG~~|
||Bank 3<br>~~eG~~<br>~~es~~|0<br>~~eG~~|0<br>~~eG~~|0<br>~~eG~~|
||Bank 4<br>~~es~~<br>~~eG~~<br>~~Re~~|0<br>~~eG~~|0<br>~~eG~~|21<br>~~eG~~|
||Bank 5<br>~~Re~~<br>~~ee~~|0|0|0|
|Shared VREF Pins|Bank 0<br>~~Re~~<br>~~ee~~|0|0|0|
||Bank 1<br>~~ee~~<br>~~eG~~<br>~~Re~~|0<br>~~eG~~|0<br>~~eG~~|0<br>~~eG~~|
||Bank 2<br>~~Re~~|2|2|2|
||Bank 3<br>~~Re~~<br>~~eG~~<br>~~es~~|2<br>~~eG~~|2<br>~~eG~~|2<br>~~eG~~|
||Bank 4<br>~~eG~~<br>~~es~~<br>~~Re~~|1<br>~~eG~~|1<br>~~eG~~|2<br>~~eG~~|
||Bank 5<br>~~es~~<br>~~Re~~|0|0|0|
## **Note:**
1. GPLL is only supported in 104 package of LIFCL-33U.
© 2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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**CrossLink-NX-33 and CrossLinkU-NX Data Sheet**
## **5. Ordering Information**
Lattice provides a wide variety of services for its products including custom marking, factory programming, known good die, and application specific testing. Contact the local sales representatives for more details.
## **5.1. Part Number Description**
**==> picture [444 x 227] intentionally omitted <==**
**----- Start of picture text -----**<br>
LIFCL- 33X- X XXXX X<br>Device Family<br> CrossLink-NX-33 FPGA<br>Grade<br> C = Commercial<br>Logic Capacity I = Industrial<br> 33 = 33k Logic Cells<br> U = Hardened USB<br>Blank = No Hardened USB Package<br> USG84 = 84-ball WLCSP<br> CTG104 = 104-ball FCCSP<br>Speed<br>T E 7 = Slowest<br> 8<br> 9 = Fastest<br>**----- End of picture text -----**<br>
**Note:** ECC is only available on CTG104 -8 and -9 speed grade devices. USB 3.2 Gen 1 is only supported in LIFCL-33U -9 speed grade.
## **5.2. Ordering Part Numbers**
**5.2.1. Commercial**
|**Part Number**<br>**Speed**<br>**Package **<br>**Pins**<br>**Grade**<br>**Logic Cells(k)**<br>LIFCL-33-8USG84C<br>–8<br>Lead free WLCSP<br>84<br>Commercial<br>33<br>LIFCL-33U-7CTG104C<br>–7<br>Lead free FCCSP<br>104<br>Commercial<br>33<br>LIFCL-33U-8USG84C<br>–8<br>Lead free WLCSP<br>84<br>Commercial<br>33<br>LIFCL-33U-8CTG104C<br>–8<br>Lead free FCCSP<br>104<br>Commercial<br>33<br>LIFCL-33U-9CTG104C<br>–9<br>Lead free FCCSP<br>104<br>Commercial<br>33<br>~~———~~|
|---|
|**5.2.2. Industrial**<br>**Part Number**<br>**Speed**<br>**Package **<br>**Pins**<br>**Grade**<br>**Logic Cells(k)**<br>LIFCL-33-8USG84I<br>–8<br>Lead free WLCSP<br>84<br>Industrial<br>33<br>LIFCL-33U-7CTG104I<br>–7<br>Lead free FCCSP<br>104<br>Industrial<br>33<br>LIFCL-33U-8USG84I<br>–8<br>Lead free WLCSP<br>84<br>Industrial<br>33<br>LIFCL-33U-8CTG104I<br>–8<br>Lead free FCCSP<br>104<br>Industrial<br>33<br>LIFCL-33U-9CTG104I<br>–9<br>Lead free FCCSP<br>104<br>Industrial<br>33<br>~~Oo~~|
© 2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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**CrossLink-NX-33 and CrossLinkU-NX Data Sheet**
mLATTICE
## **References**
- CrossLink-NX web page
A variety of technical notes for LIFCL-33/33U devices are available.
- CrossLink-NX-33 and CrossLinkU-NX High-Speed I/O Interface (FPGA-TN-02280)
- CrossLink-NX Single Event Upset (SEU) Report (FPGA-TN-02174)
- High-Speed PCB Design Considerations (FPGA-TN-02178)
- I[2] C Hardened IP User Guide for Nexus Platform (FPGA-TN-02142)
- Lattice Memory Mapped Interface and Lattice Interrupt Interface User Guide (FPGA-UG-02039)
- Memory User Guide for Nexus Platform (FPGA-TN-02094)
- Multi-Boot User Guide for Nexus Platform (FPGA-TN-02145)
- Power Management and Calculation for CrossLink-NX Devices (FPGA-TN-02075)
- Soft Error Detection (SED)/Correction (SEC) User Guide for Nexus Platform (FPGA-TN-02076)
- sub-LVDS Signaling Using Lattice Devices (FPGA-TN-02028)
- sysCLOCK PLL Design and User Guide for Nexus Platform (FPGA-TN-02095)
- sysCONFIG User Guide for Nexus Platform (FPGA-TN-02099)
- sysDSP User Guide for Nexus Platform (FPGA-TN-02096)
- sysI/O User Guide for Nexus Platform (FPGA-TN-02067)
- Thermal Management (FPGA-TN-02044)
- Using TraceID (FPGA-TN-02084)
For more information on the LIFCL-33/33U-related IP, reference designs, and board documents, refer to the following pages:
- IP and Reference Designs for CrossLink-NX
- Development Kits and Boards for CrossLink-NX
For further information on interface standards refer to the following websites:
- JEDEC Standards (LVTTL, LVCMOS, SSTL) – www.jedec.org
Other references:
- Lattice Insights for Lattice Semiconductor training courses and learning plans
- Lattice Radiant FPGA design software
© 2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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**CrossLink-NX-33 and CrossLinkU-NX Data Sheet**
mLATTICE
## **Technical Support Assistance**
Submit a technical support case through www.latticesemi.com/techsupport.
For frequently asked questions, refer to the Lattice Answer Database at www.latticesemi.com/Support/AnswerDatabase.
© 2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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**CrossLink-NX-33 and CrossLinkU-NX Data Sheet**
## **Revision History**
## **Revision 1.0, July 2024**
|**Section**|**Change Summary**|
|---|---|
|All|Moved document status to_Production Release_.|
|Acronyms in This Document|Added row for PIPE.|
|General Desciption|•<br>UpdatedTable 1.1. LIFCL-33/33U Key Featuresto change AXI4-Streaming to_AXI protocol_<br>and added speed grade limitations in USB2.0/USB3.2 section.<br>•<br>Updated the following inTable 1.2. LIFCL-33/33U Commercial/Industrial Family Selection<br>Guide:<br>•<br>Added table note and reference to table note for GPLL.<br>•<br>Added table note and reference to table note for USB2.0/USB3.2.<br>•<br>Removed Soft D-PHY table note.|
|Architecture|•<br>Added document reference to AON IP User Guide inAlways On (AON)section.<br>•<br>Removed LS (1.5 Mbps) mode inUSBsection.<br>•<br>Added document reference to USB 2.0/3.2 IPUG inUSB RISC-V Firmware Stack and Host<br>Software Interfacesection.<br>•<br>Changed on board to_on-chip_and added document reference to OSC IPUG inOn-Chip<br>Oscillator.<br>•<br>Changed Responder to_Target_inUser I²C IP.|
|DC and Switching Characteristics<br>for Commercial and Industrial|•<br>UpdatedTable 3.1. Absolute Maximum Ratings:<br>•<br>Added VCCAUXH2and removed VCCAUXH5.<br>•<br>Changed VCCIO0, 1, 2, 6, 7to_VCCIO0, 1, 5_.<br>•<br>Changed VCCIO3, 4, 5to_VCCIO2, 3, 4_.<br>•<br>Added reference to footnote 5 in AVDD33.<br>•<br>Changed to_All AVDD_in footnote 5.<br>•<br>Updated the following inTable 3.2. Recommended Operating Conditions:<br>•<br>Changed VCCAUXH2/3/4/5to_VCCAUXH2/3/4_.<br>•<br>Added reference to footnote 5 in AVDD33.<br>•<br>Changed to_All AVDD_in footnote 5.<br>•<br>Added reference to footnote 2 inPower Supply Ramp Rates2section.<br>•<br>Fixed Differential typo in footnote ofTable 3.5. On-Chip Termination Options for Input<br>Modes.<br>•<br>Fixed typo from TA25 to_TA = 25_inTable 3.9. Capacitors – Wide RangeandTable 3.10.<br>Capacitors – High Performance.<br>•<br>Updated MIPI D-PHY to_MIPI_DPHY_inTable 3.13. sysI/O Recommended Operating<br>Conditions.<br>•<br>Updated the following inTable 3.29. Maximum I/O Buffer Speed:<br>•<br>Updated LVDS, SLVS, and MIPI D-PHY in Maximum sysI/O Output Frequency<br>Differential section to collapse rows and updated values for USG84 and CTG104<br>packages.<br>•<br>Changed MIPI LP and MIPI HS table note to_MIPI D-PHY LP and MIPI D-PHY HS_.<br>•<br>Updated the following inTable 3.33. External Switching Characteristics (VCC = 1.0 V):<br>•<br>Added -9 device column and values.<br>•<br>Updated -8 and -7 Min values for tSUand tH_DELPLLto_0_.<br>•<br>Updated -8 Max value for Generic DDRX2 I/O with Clock and Data Centered ½ UI from<br>500 to_—_.<br>•<br>Updated fDATA_GDDRX4to keep it in one row and Max values for -8 and 7 at 1200 and<br>1034, respectively; updated Description to_Input/Output Data Rate_.<br>•<br>UpdatedTable 3.37. sysCONFIG Port Timing Specificationsto change tPROGRAMNto<br>_tPROGRAMN_L_and added row for tPROGRAMN_H.<br>•<br>AddedFigure 3.23. Configuration Error Notification.<br>•<br>Added footnote inTable 3.38. AON Block Specification(VCCAUX_AON = 1.8 V).|
© 2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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**CrossLink-NX-33 and CrossLinkU-NX Data Sheet**
||**Section**|**Change Summary**|
|---|---|---|
|||•<br>Updated the following inHardened USB Specifications:|
|||•<br>Updated table name toTable 3.39. Hardened USB2 Specifications, removed tSKEWrow,|
|||updated fREF_CLKrow values to merge Min, Typ, and Max cells, updated max value of|
|||tRAN_JIT, updated row of tP2P_JITincluding symbol name, and added footnotes and|
|||reference to footnotes.|
|||•<br>AddedTable 3.40. Hardened USB3 Specifications.|
|||•<br>Updated to_All AVDD_for footnote 1 inSignal Descriptions.|
||Pinout Information|•<br>UpdatedPin Information Summarytable to add table note and reference to table note for|
|||GPLL Bank 4(NX33U-104FCCSP).|
|||•<br>UpdatedPart Number Descriptionto add 9 speed grade and updated note for ECC|
||Ordering Information|(including adding support information for USB 3.2 Gen 1).|
|||•<br>UpdatedOrderingPart Numberstables to add OPN for 9 CTG104 .|
|**Revision 0.94, February 2024**|||
|**Section**<br>**Change Summary**<br>Architecture<br>•<br>Updated DDRDLL and Input Register Block section to remove DQSBUF information.<br>•<br>Updated Edge Clock and sysI/O Buffer to remove DDR information.<br>•<br>Removed DLL Calibrated DQS Delayand Control Block section.<br>DC and Switching Characteristics<br>for Commercial and Industrial<br>•<br>Updated SubLVDS (Input Only) section to remove SMIA information.<br>•<br>Updated Figure 3.15. Slave SPI/I2C/I3C POR/REFRESH Timing to remove tICFG_POR,<br>tACT_CCLK, tACT_SCL and adjusted VCC/VCCAUX/VCCIO0/VCCIO1, REFRESH Command,<br>CCLK, SSI, SCL, and SDA signals, adjusted rising edge of PROGRAMN, and changed<br>tACT_CRESETB_N to tACT_PROGRAMN_H in the timing diagram.<br>•<br>Updated Table 3.29. Maximum I/O Buffer Speed to remove DDR3/3L footnote.<br>•<br>Updated GDDRX4 Inputs/Outputs with Clocks and Data Centered values in Table 3.33.<br>External SwitchingCharacteristics(VCC = 1.0 V).<br>~~CT~~|||
|**Revision 0.93, December 2023**|||
||**Section**|**Change Summary**|
|||•<br>Updated document title to_CrossLink-NX-33 and CrossLinkU-NX_.|
||All|•<br>Used_LIFCL-33/33U_to refer to the CrossLink-NX-33 and CrossLinkU-NX devices across the|
|||document.|
||Disclaimers|Updated this section.|
||General Description|Updated Table 1.2. LIFCL-33/33U Commercial/Industrial Family Selection Guide to change<br>device name to_LIFCL-33_and_LIFCL-33U_.|
||Architecture|•<br>Updated Figure 2.7. Clocking to remove LMID and RMID and update number of PCLK pin for|
|||top and bottom I/O banks.|
|||•<br>Updated Figure 2.14. Comparison of General DSP, LIFCL-33, and LIFCL-33U Approaches to|
|||change to Function Implemented in_LIFCL-33_and_LIFCL-33U_.|
||DC and Switching Characteristics|Updated Table 3.31. Register-to-Register Performance to change Large Memory Function values|
||for Commercial and Industrial|to 195, 170, and 115, add table note reference to 1, 2, and 3, and change performance grade in|
|||table note 1 to_8_.|
||References|Changed section name from Supplemental Information to_References_.|
||Technical Support Assistance|Added this section.|
© 2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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**CrossLink-NX-33 and CrossLinkU-NX Data Sheet**
mLATTICE
## **Revision 0.92, September 2023**
|**Section**|**Change Summary**|
|---|---|
|All|•<br>Added CrossLink-NX-33U support, including AON and USB, across the document.<br>•<br>Changed document title from CrossLink-NX-33 to_CrossLink-NX-33 and CrossLink-NX-33U_.|
|Acronyms in This Document|•<br>Added AON, GPIO, MPS, and USB definition.<br>•<br>Removed PCS from the acronym list.|
|General Description|•<br>Added USB 2.0, USB 3.2 Gen 1, and AON information for CrossLink-NX-33U only.<br>•<br>Restructured the Features section by adding Table 1.1. CrossLink-NX-33 and CrossLink-NX-<br>33U Key Features and updating the following in the table:<br>•<br>Changed programmable sysI/O from 68 to_60_.<br>•<br>Updated support from 1.5 Gbps to_1.2 Gbps_.<br>•<br>Removed_SEU Mitigation Support_and its sub-items from the Cryptographic Engine<br>section and added it as another main section.<br>•<br>Removed AXI4-Streaming as main section and moved it under_Internal Bus Interface_<br>_Support_section.<br>•<br>Added AON and USB 2.0/USB 3.2 Gen 1 sections.<br>•<br>Updated the following in Table 1.2. CrossLink-NX-33 and CrossLink-NX-33U<br>Commercial/Industrial Family Selection Guide:<br>•<br>Changed table name to add CrossLink-NX-33U.<br>•<br>Added column for CrossLink-NX-33U.<br>•<br>Added USB 2.0/USB 3.2 Gen 1 and AON support.<br>•<br>Added 104 FCCSP package.<br>•<br>Changed cell title to_Total I/O (Wide Range, High Performance)_and adjusted format.<br>•<br>Updated support from 1.5 Gbps to_1.2 Gbps_.|
|Architecture|•<br>Added Figure 2.2. CrossLink-NX-33U Simplified Block Diagram.<br>•<br>Updated Figure 2.14. Comparison of General DSP, CrossLink-NX-33, and CrossLink-NX-33U<br>Approaches to add CrossLink-NX-33U.<br>•<br>Added text in sysI/O Banking Scheme specifying Bank 5 is supported in CrossLink-NX-33 and<br>AON and USB signals in CrossLink-NX-33U only.<br>•<br>Added Always On (AON) and USB sections.<br>•<br>Updated Figure 2.29. Cryptographic Engine Block Diagram to change Unique ID to_Unique_<br>_Device Secret_and HMAC SHA256 to_HMAC256_.|
© 2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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**CrossLink-NX-33 and CrossLinkU-NX Data Sheet**
mLATTICE
|**Section**|**Change Summary**|
|---|---|
|DC and Switching Characteristics<br>for Commercial and Industrial|•<br>Updated the following in Table 3.1. Absolute Maximum Ratings:<br>•<br>Added VCCAUX_AONand AVDD, AVDD_TX.<br>•<br>Changed VCCA_DPHY0, 1to AVDD33 and updated Max value to 3.63.<br>•<br>Changed VCC_DPHY0, 1to AVDD18, AVDD18_TX, AVDD18_COM and updated Max value<br>to 1.98.<br>•<br>Added VCCAUX_AON and rows for AVDD33, AVDD, AVDD_TX, AVDD18, AVDD18_TX,<br>AVDD18_COM, and and AVDD, AVDD_TX in Table 3.2. Recommended Operating<br>Conditions.<br>•<br>Updated Table 3.14. sysI/O DC Electrical Characteristics – Wide Range I/O to change<br>LVCMOS10 VIL Min value to 0.35 x VCCIO.<br>•<br>Updated the following in Table 3.33. External Switching Characteristics (VCC = 1.0 V):<br>•<br>Added column and values for -7 speed grade.<br>•<br>Updated unit for tH_DEL(Bottom).<br>•<br>Changed -8 speed grade value of fMAX_GDDR2to blank.<br>•<br>Updated fDATA_GDDRX4_MPto add rows per package.<br>•<br>Added AON Block Specifications (VCCAUX_AON = 1.8V) and Hardened USB Specifications<br>sections.|
|Pinout Information|•<br>Updated the following in Signal Descriptions:<br>•<br>Added AVSSx and VSS_AONin VSSsignal and updated description to add USB logic and<br>AON.<br>•<br>Added rows for AVDD33, AVDD, AVDD_TX, AVDD18, AVDD18_TX, AVDD18_COM, and<br>REFIN_CLK_EXT_P/N.<br>•<br>Added table notes and reference to table notes to specify that AON and AVDD signals<br>are supported in CrossLink-NX-33U as well as Bank 0-4, and Bank 0-5 are supported in<br>CrossLink-NX-33.<br>•<br>Added Pin Information Summary.|
|Ordering Information|•<br>Added new package option CTG104, -7 speed grade, and note for -8 speed grade in Part<br>Number Description, as well as updated Logic Capacity to add Hardened USB.<br>•<br>Added CrossLink-NX-33U part numbers in Ordering Part Numbers.<br>•<br>Updated Commercial and Industrial tables to change column name from Tempto_Grade_.|
|Supplemental Information|•<br>Updated document links, rearranged list in alphabetical order, and updated document<br>name for High-Speed I/O Interface and Hardware Checklist documents.<br>•<br>Added references to the CrossLink-NX, Lattice Insights, and Lattice Radiant Web Page, IP<br>Core, Reference Design, and Evaluation Board documents.|
**Revision 0.91, March 2023**
|**Section**|**Change Summary**|
|---|---|
|Acronyms in This Document|Removed MLVDS in the table.|
|Architecture|Adjustment in formatting to move Clocking Structure as sub-section under the Architecture<br>section.|
|Supplemental Information|Added link for High Speed PCB Design Considerations (FPGA-TN-02178).|
|Technical Support Assistance|Added this section.|
© 2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02104-1.0
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**CrossLink-NX-33 and CrossLinkU-NX Data Sheet**
mLATTICE
## **Revision 0.90, November 2022**
|**Section**|**Change Summary**|
|---|---|
|All|Removed EBR-ECC references across the document.|
|Architecture|•<br>Removed HSUL and SSTL references in the following sections and tables:<br>•<br>sysI/O Buffer<br>•<br>Supported sysI/O Standards<br>•<br>Table 2.10. Single-Ended I/O Standards<br>•<br>Table 2.11. Differential I/O Standards<br>•<br>Table 2.12. Single-Ended I/O Standards Supported on Various Sides<br>•<br>Table 2.13. Differential I/O Standards Supported on Various Sides|
|DC and Switching Characteristics<br>for Commercial and Industrial|•<br>Removed Differential SSTL135D/SSTL15D and HSUL12D sections.<br>•<br>Added row for tJIND and removed VCCIO DDR3L in Table 3.2. Recommended Operating<br>Conditions.<br>•<br>Updated max value of VCCAUX for VPORUP and VPORDN in Table 3.4. Power-On Reset.<br>•<br>Removed HSUL and SSTL references in Table 3.5. On-Chip Termination Options for Input<br>Modes and Table 3.29. Maximum I/O Buffer Speed.<br>•<br>Removed table note referring to DDR3L and HSUL/SSTL references in Table 3.13. sysI/O<br>Recommended Operating Conditions.<br>•<br>Updated VOL (max), VOH (min), IOL and IOH for LVTTL33/LVCMOS33 and LVCMOS25 in Table<br>3.14. sysI/O DC Electrical Characteristics – Wide Range I/O.<br>•<br>Updated VIH (min) in HSTL15_I and removed SSTL and HSUL standards in Table 3.15. sysI/O<br>DC Electrical Characteristics – High Performance I/O.<br>•<br>Updated SE Input Termination min value from 71 to 67 in Table 3.16. I/O Resistance<br>Characteristics.<br>•<br>Updated Large Memory Function values in Table 3.31. Register-to-Register Performance.<br>•<br>Updated the following in Table 3.33. External Switching Characteristics (VCC = 1.0 V):<br>•<br>Updated max values of fMAX_PRI and tSKEW_PRI, and min value of tW_PRI in Primary<br>Clock.<br>•<br>Updated max values of fMAX_EDGE and tSKEW_EDGE, and min value of tW_EDGE in<br>Edge Clock.<br>•<br>Updated tCO max value, min value of tSU, tH, tSU_DEL, tH_DEL (top), and added tH_DEL<br>(bottom) in General I/O Pin Parameters Using Dedicated Primary Clock Input without<br>PLL.<br>•<br>Updated max value of tCO_PLL, min value of tSU_PLL (top), tH_PLL, tSU_DELPLL,<br>tH_DELPLL, and added tSU_PLL (bottom) in General I/O Pin Parameters Using Dedicated<br>Primary Clock Input with PLL.<br>•<br>Updated Generic DDR Input/Output group to reflect correct values.<br>•<br>Removed SSTL and HSUL references in footnote 2.<br>•<br>Added footnote and reference to footnote 6.<br>•<br>Updated entire content of Table 3.37. sysCONFIG Port Timing Specifications to reflect correct<br>values.|
|OrderingInformation|Updated section content, Includingdiagram, to remove -7 speedgrade.|
© 2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02104-1.0
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**CrossLink-NX-33 and CrossLinkU-NX Data Sheet**
mLATTICE
## **Revision 0.81, September 2022**
|**Section**|**Change Summary**|
|---|---|
|All|Minor changes in formatting, including removing product name from heading, figure, and table<br>names.|
|DC and Switching Characteristics<br>for Commercial and Industrial|•<br>Added Table 3.17. VIN Maximum Overshoot/Undershoot Allowance – Wide Range and Table<br>3.18. VIN Maximum Overshoot/Undershoot Allowance – High Performance.<br>•<br>Updated footnote reference in the Differential groups in Table 3.29. Maximum I/O Buffer<br>Speed.<br>•<br>Updated DSP functions in Table 3.31. Register-to-Register Performance.<br>•<br>Updated the following in Table 3.34. sysCLOCK PLL Timing (VCC = 1.0 V) –<br>Commercial/Industrial:<br>•<br>Raised minimum input clock frequency from 10 to 18 MHz.<br>•<br>Raised minimum phase detector input frequency from 10 to 18 MHz; removed table note<br>and table note reference.<br>•<br>Corrected tPHfootnote.<br>•<br>Removed and Added conditions for the tOPJITparameter to accurately reflect PLL jitter<br>performance.|
**Revision 0.80, June 2022**
|**Section**|**Change Summary**|
|---|---|
|All|•<br>Changed document status to Preliminary.<br>•<br>Minor adjustments in formattingacross the document.|
|Acronyms in This Document|•<br>Removed definition for ADC and DTR.|
|Introduction|•<br>Added note for ECC in Flexible Memory Resources bullet point.<br>•<br>Updated Table 1.1. CrossLink-NX-33 Commercial/Industrial Family Selection Guide to change<br>I/O count for 84 WLCSP to 34/26.|
|CrossLink-NX-33 Architecture|•<br>Updated Figure 2.1. CrossLink-NX-33 Simplified Block Diagram.<br>•<br>Added information on select speed grades in sysMEM Memory Block.<br>•<br>Updated TD[1:0] parameter name to T[1:0] in Table 2.8. Tri-state Block Port Description.<br>•<br>Updated DELAY CODE to DELAYCODE_I and DELAYCODE_O in Figure 2.23. DQS Control and<br>DelayBlock(DQSBUF).|
|DC and Switching Characteristics<br>for Commercial and Industrial|•<br>Added Commercial and Industrial grade information in ESD Performance.<br>•<br>Updated Figure 3.21. Master SPI Wake-Up Timing and Figure 3.22. Slave SPI/I2C/I3C Wake-Up<br>Timing to change tDONE_HIGHto tWAKEUP_DONE_HIGH.<br>•<br>Updated LVDS and subLVDS VCCIO(Input) value; Updated table note 1b and d to change bank<br>3, bank 4, and bank 5 to bank 2, bank 3, and bank 4 in Table 3.13. sysI/O Recommended<br>Operating Conditions.<br>•<br>Updated information for VCCAUXin LVDS.<br>•<br>Updated VIH, VIL, IOL, IOHvalues and table notes in Table 3.14. sysI/O DC Electrical<br>Characteristics – Wide Range I/O and Table 3.15. sysI/O DC Electrical Characteristics – High<br>Performance I/O.<br>•<br>Changed VINNto VINMin table note 2 and added table note 3 in Table 3.17. LVDS DC Electrical<br>Characteristics.<br>•<br>Added table note for VICMin Table 3.19. SubLVDS Input DC Electrical Characteristics (Over<br>Recommended Operating Conditions).<br>•<br>Updated max value of ZOSin Table 3.22. SLVS Output DC Characteristics.<br>•<br>Updated max value of ZOSin Table 3.24. Soft D-PHY Output Timing and Levels.<br>•<br>Updated max value of HSTL15 in Table 3.27. CrossLink-NX-33 Maximum I/O Buffer Speed.<br>•<br>Updated Generic DDRX1 group to add WRIO and HPIO in Table 3.31. CrossLink-NX-33 External<br>SwitchingCharacteristics(VCC = 1.0 V).|
© 2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02104-1.0
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**CrossLink-NX-33 and CrossLinkU-NX Data Sheet**
|**Section**|**Change Summary**|
|---|---|
|CrossLink-NX-33 Pinout<br>Information|Adjustment in formatting to remove superscripts for Shared Configuration Pins, Shared User GPIO<br>Pins, and Shared CLOCK Pins; Updated signal names and description, specifically for<br>Bank 1, for Shared JTAG Pins, Shared Configuration Pins, and Shared CLOCK Pins in Signal<br>Descriptions.|
|CrossLink-NX-33 Ordering<br>Information|•<br>Added note regarding availability of Input Comparator, ADC, EBR, ECC, and DTR in select<br>speed grades.<br>•<br>Added OrderingPart Numbers section.|
## **Revision 0.70, November 2021**
|**Section**|**Change Summary**|
|---|---|
|All|Advance release|
© 2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02104-1.0
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www.latticesemi.com
Updated at April 17, 2026
Lattice Semiconductor is a premier developer of low-power, programmable design solutions, specializing in Field-Programmable Gate Arrays (FPGAs) and Programmable Logic Devices (PLDs). Recognized for driving innovation in cost-effective and power-efficient architectures, the company provides essential semiconductor components for consumer, mobile, and industrial design applications. Our selection of Lattice Semiconductor products is focused on their highly regarded FPGA integrated circuits. Devices from industry-leading families like the iCE40, MachXO, and LatticeECP series offer designers an exceptional combination of high system integration and industry-low power consumption. These FPGAs are engineered to handle complex tasks such as sensor management, custom connectivity, and advanced video processing while minimizing overall board footprint. To ensure seamless integration from concept to production, Lattice backs its hardware with a comprehensive support ecosystem. Engineers can accelerate their development cycles utilizing intuitive tools like the Lattice Diamond design software, paired with flexible IP cores and reference designs that reduce design risk and increase system reliability.
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