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LIF-MD6000-6JMG80I
FPGA, CrossLink, PLL37 I/O, 400 MHz, 5936 Cells, 1.14 V to 1.26 V, CTFBGA-80
⚠️ Reference pricing provided. In case of supply shortages, we will connect you with our trusted procurement partners to ensure your project's continuity.
- Manufacturer: LATTICE SEMICONDUCTOR
- Product type: FPGAs
- MSL: MSL 3 - 168 hours
- SVHC: No SVHC (25-Jun-2025)
- FPGA Type: SRAM based FPGA
- FPGA Family: CrossLink
- IC Mounting: Surface Mount
- No. of Pins: 80Pins
- Speed Grade: 6
- No. of I/O's: 37I/O's
- Product Range: CrossLink LIF-MD
- Qualification: -
- Total RAM Bits: 180Kbit
- No.of User I/Os: 37I/O's
- Clock Management: PLL
- Logic Case Style: CTFBGA
- IC Case / Package: CTFBGA
- No. of Macrocells: 5936Macrocells
- I/O Supply Voltage: 3.465V
- No. of Logic Cells: 5936Logic Cells
- Process Technology: 40nm
- No. of Logic Blocks: 5936
- No. of Speed Grades: 6
- Core Supply Voltage Max: 1.26V
- Core Supply Voltage Min: 1.14V
- Operating Frequency Max: 400MHz
- Operating Temperature Max: 100°C
- Operating Temperature Min: -40°C
| Delivery and price | |
|---|---|
| Units per pack | 100 |
| Price | 12.38 € |
| Current stock | 50+ |
| Lead time | 30 days |
Datasheet
## Os
## **CrossLink Family**
## **Data Sheet**
FPGA-DS-02007-1.8
January 2021
**CrossLink Family Data Sheet**
## **Disclaimers**
Lattice makes no warranty, representation, or guarantee regarding the accuracy of information contained in this document or the suitability of its products for any particular purpose. All information herein is provided AS IS and with all faults, and all risk associated with such information is entirely with Buyer. Buyer shall not rely on any data and performance specifications or parameters provided herein. Products sold by Lattice have been subject to limited testing and it is the Buyer's responsibility to independently determine the suitability of any products and to test and verify the same. No Lattice products should be used in conjunction with mission- or safety-critical or any other application in which the failure of Lattice’s product could create a situation where personal injury, death, severe property or environmental damage may occur. The information provided in this document is proprietary to Lattice Semiconductor, and Lattice reserves the right to make any changes to the information in this document or to any products at any time without notice.
© 2015-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
2
FPGA-DS-02007-1.8
**CrossLink Family Data Sheet**
## **Contents**
|**Contents**|**Contents**|**Contents**|
|---|---|---|
|Acronyms in This Document ................................................................................................................................................. 6|||
|1.|General Description ...................................................................................................................................................... 7||
||1.1.|Features .............................................................................................................................................................. 7|
|2.|Product Feature Summary ............................................................................................................................................ 8||
|3.|Architecture Overview .................................................................................................................................................. 9||
||3.1.|MIPI D-PHY Blocks ............................................................................................................................................. 10|
||3.2.|Programmable I/O Banks .................................................................................................................................. 15|
||3.3.|sysI/O Buffers .................................................................................................................................................... 16|
||3.3.1.|Programmable PULLMODE Settings ............................................................................................................. 16|
||3.3.2.|Output Drive Strength .................................................................................................................................. 16|
||3.3.3.|On-Chip Termination .................................................................................................................................... 16|
||3.4.|Programmable FPGA Fabric .............................................................................................................................. 17|
||3.4.1.|PFU Blocks ..................................................................................................................................................... 17|
||3.4.2.|Slice ............................................................................................................................................................... 18|
||3.5.|Clocking Structure ............................................................................................................................................. 20|
||3.5.1.|sysCLK PLL ..................................................................................................................................................... 20|
||3.5.2.|Primary Clocks .............................................................................................................................................. 21|
||3.5.3.|Edge Clocks ................................................................................................................................................... 21|
||3.5.4.|Dynamic Clock Enables ................................................................................................................................. 22|
||3.5.5.|Internal Oscillator (OSCI) .............................................................................................................................. 22|
||3.6.|Embedded Block RAM Overview ....................................................................................................................... 23|
||3.7.|Power Management Unit .................................................................................................................................. 24|
||3.7.1.|PMU State Machine ...................................................................................................................................... 24|
||3.8.|User I2C IP .......................................................................................................................................................... 25|
||3.9.|Programming and Configuration ....................................................................................................................... 26|
|4.|DC and Switching Characteristics ............................................................................................................................... 27||
||4.1.|Absolute Maximum Ratings .............................................................................................................................. 27|
||4.2.|Recommended Operating Conditions ............................................................................................................... 27|
||4.3.|Power Supply Ramp Rates ................................................................................................................................ 28|
||4.4.|Power-On-Reset Voltage Levels ........................................................................................................................ 28|
||4.5.|Power Supply Sequence Requirements ............................................................................................................ 29|
||4.6.|ESD Performance .............................................................................................................................................. 29|
||4.7.|DC Electrical Characteristics .............................................................................................................................. 30|
||4.8.|CrossLink Supply Current .................................................................................................................................. 31|
||4.9.|Power Management Unit (PMU) Timing ........................................................................................................... 32|
||4.10.|sysI/O Recommended Operating Conditions .................................................................................................... 32|
||4.11.|sysI/O Single-Ended DC Electrical Characteristics ............................................................................................. 33|
||4.12.|sysI/O Differential Electrical Characteristics ..................................................................................................... 33|
||4.12.1.<br>LVDS/subLVDS/SLVS200 ........................................................................................................................... 33||
||4.12.2.<br>Hardened MIPI D-PHY I/Os ....................................................................................................................... 34||
||4.13.|CrossLink Maximum General Purpose I/O Buffer Speed................................................................................... 35|
||4.14.|CrossLink External Switching Characteristics .................................................................................................... 36|
||4.15.|sysCLOCK PLL Timing ......................................................................................................................................... 42|
||4.16.|Hardened MIPI D-PHY Performance ................................................................................................................. 43|
||4.17.|Internal Oscillators (HFOSC, LFOSC) .................................................................................................................. 43|
||4.18.|User I2C .............................................................................................................................................................. 44|
||4.19.|CrossLink sysCONFIG Port Timing Specifications .............................................................................................. 44|
||4.20.|SRAM Configuration Time from NVCM ............................................................................................................. 44|
||4.21.|Switching Test Conditions ................................................................................................................................. 45|
|5.|Pinout Information ..................................................................................................................................................... 46||
||5.1.|WLCSP36 Pinout ................................................................................................................................................ 46|
||5.2.|ucfBGA64 Pinout ............................................................................................................................................... 47|
© 2015-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02007-1.8
3
**CrossLink Family Data Sheet**
||5.3.<br>ctfBGA80/ckfBGA80 Pinout ............................................................................................................................... 49|
|---|---|
||5.4.<br>csfBGA81 Pinout ................................................................................................................................................ 51|
||5.5.<br>Dual Function Pin Descriptions ......................................................................................................................... 53|
||5.6.<br>Dedicated Function Pin Descriptions ................................................................................................................ 54|
||5.7.<br>Pin Information Summary ................................................................................................................................. 55|
|6.|CrossLink Part Number Description ............................................................................................................................ 56|
||6.1.<br>Ordering Part Numbers ..................................................................................................................................... 56|
|References .......................................................................................................................................................................... 57||
|Technical Support ............................................................................................................................................................... 57||
|Revision History .................................................................................................................................................................. 58||
## **Figures**
|Figure 3.1. CrossLink Device Block Diagram ......................................................................................................................... 9|Figure 3.1. CrossLink Device Block Diagram ......................................................................................................................... 9|
|---|---|
|Figure 3.2. CrossLink sysI/O Banking .................................................................................................................................. 10|Figure 3.2. CrossLink sysI/O Banking .................................................................................................................................. 10|
|Figure 3.3. MIPI DSI Transmit Interface with Hard D-PHY Module ..................................................................................... 11|Figure 3.3. MIPI DSI Transmit Interface with Hard D-PHY Module ..................................................................................... 11|
|Figure 3.4. MIPI CSI-2 Transmit Interface with Hard D-PHY Module .................................................................................. 12|Figure 3.4. MIPI CSI-2 Transmit Interface with Hard D-PHY Module .................................................................................. 12|
|Figure 3.5. MIPI DSI Receive Interface with Hard D-PHY Module ....................................................................................... 13|Figure 3.5. MIPI DSI Receive Interface with Hard D-PHY Module ....................................................................................... 13|
|Figure 3.6. MIPI CSI-2 Receive Interface with Hard D-PHY Module .................................................................................... 14|Figure 3.6. MIPI CSI-2 Receive Interface with Hard D-PHY Module .................................................................................... 14|
|Figure 3.7. CrossLink Device Simplified Block Diagram (Top Level) .................................................................................... 17|Figure 3.7. CrossLink Device Simplified Block Diagram (Top Level) .................................................................................... 17|
|Figure 3.8. CrossLink PFU Diagram ..................................................................................................................................... 17|Figure 3.8. CrossLink PFU Diagram ..................................................................................................................................... 17|
|Figure 3.9. Slice Diagram .................................................................................................................................................... 18|Figure 3.9. Slice Diagram .................................................................................................................................................... 18|
|Figure 3.10. Connectivity Supporting LUT5, LUT6, LUT7 and LUT8 .................................................................................... 19|Figure 3.10. Connectivity Supporting LUT5, LUT6, LUT7 and LUT8 .................................................................................... 19|
|Figure 3.11. CrossLink PLL Block Diagram ........................................................................................................................... 20|Figure 3.11. CrossLink PLL Block Diagram ........................................................................................................................... 20|
|Figure 3.12. CrossLink Clocking Structure ........................................................................................................................... 21|Figure 3.12. CrossLink Clocking Structure ........................................................................................................................... 21|
|Figure 3.13. CrossLink Edge Clock Sources per Bank .......................................................................................................... 22|Figure 3.13. CrossLink Edge Clock Sources per Bank .......................................................................................................... 22|
|Figure 3.14. CrossLink OSCI Component Symbol ................................................................................................................ 22|Figure 3.14. CrossLink OSCI Component Symbol ................................................................................................................ 22|
|Figure 3.15. CrossLink MIPI D-PHY Block ............................................................................................................................ 24|Figure 3.15. CrossLink MIPI D-PHY Block ............................................................................................................................ 24|
|Figure 3.16. CrossLink PMU State Machine ........................................................................................................................ 25|Figure 3.16. CrossLink PMU State Machine ........................................................................................................................ 25|
|Figure 4.1. Receiver RX.CLK.Centered Waveforms ............................................................................................................. 40|Figure 4.1. Receiver RX.CLK.Centered Waveforms ............................................................................................................. 40|
|Figure 4.2. Receiver RX.CLK.Aligned Input Waveforms ...................................................................................................... 40|Figure 4.2. Receiver RX.CLK.Aligned Input Waveforms ...................................................................................................... 40|
|Figure 4.3. Transmit TX.CLK.Centered Output Waveforms ................................................................................................ 40|Figure 4.3. Transmit TX.CLK.Centered Output Waveforms ................................................................................................ 40|
|Figure 4.4. Transmit TX.CLK.Aligned Waveforms ................................................................................................................ 41|Figure 4.4. Transmit TX.CLK.Aligned Waveforms ................................................................................................................ 41|
|Figure 4.5. DDRX71, DDRX141 Video Timing Waveforms ................................................................................................... 41|Figure 4.5. DDRX71, DDRX141 Video Timing Waveforms ................................................................................................... 41|
|Figure 4.6. Output Test Load, LVTTL and LVCMOS Standards ............................................................................................ 45|Figure 4.6. Output Test Load, LVTTL and LVCMOS Standards ............................................................................................ 45|
© 2015-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02007-1.8
4
**CrossLink Family Data Sheet**
## **Tables**
|Table 2.1. CrossLink Feature Summary ................................................................................................................................. 8|Table 2.1. CrossLink Feature Summary ................................................................................................................................. 8|
|---|---|
|Table 3.1. CrossLink Output Support per Bank Basis .......................................................................................................... 15|Table 3.1. CrossLink Output Support per Bank Basis .......................................................................................................... 15|
|Table 3.2. CrossLink Input Support per Bank Basis ............................................................................................................. 16|Table 3.2. CrossLink Input Support per Bank Basis ............................................................................................................. 16|
|Table 3.3. Drive Strength Values ........................................................................................................................................ 16|Table 3.3. Drive Strength Values ........................................................................................................................................ 16|
|Table 3.4. Slice Signal Descriptions ..................................................................................................................................... 19|Table 3.4. Slice Signal Descriptions ..................................................................................................................................... 19|
|Table 3.5. CrossLink PLL Port Definition ............................................................................................................................. 20|Table 3.5. CrossLink PLL Port Definition ............................................................................................................................. 20|
|Table 3.6. OSCI Component Port Definition ....................................................................................................................... 22|Table 3.6. OSCI Component Port Definition ....................................................................................................................... 22|
|Table 3.7. OSCI Component Attribute Definition ............................................................................................................... 22|Table 3.7. OSCI Component Attribute Definition ............................................................................................................... 22|
|Table 3.8. sysMEM Block Configurations ............................................................................................................................ 23|Table 3.8. sysMEM Block Configurations ............................................................................................................................ 23|
|Table 3.9. CrossLink sysCONFIG Pins .................................................................................................................................. 26|Table 3.9. CrossLink sysCONFIG Pins .................................................................................................................................. 26|
|Table 4.1. Absolute Maximum Ratings|Table 4.1. Absolute Maximum Ratings1, 2, 3........................................................................................................................ 27|
|Table 4.2. Recommended Operating Conditions|Table 4.2. Recommended Operating Conditions1, 2........................................................................................................... 27|
|Table 4.3. Power Supply Ramp Rates* ............................................................................................................................... 28|Table 4.3. Power Supply Ramp Rates* ............................................................................................................................... 28|
|Table 4.4. Power-On-Reset Voltage Levels|Table 4.4. Power-On-Reset Voltage Levels1, 3.................................................................................................................... 28|
|Table 4.5. DC Electrical Characteristics ............................................................................................................................... 30|Table 4.5. DC Electrical Characteristics ............................................................................................................................... 30|
|Table 4.6. CrossLink Supply Current ................................................................................................................................... 31|Table 4.6. CrossLink Supply Current ................................................................................................................................... 31|
|Table 4.7. PMU Timing* ...................................................................................................................................................... 32|Table 4.7. PMU Timing* ...................................................................................................................................................... 32|
|Table 4.8. sysI/O Recommended Operating Conditions|Table 4.8. sysI/O Recommended Operating Conditions1................................................................................................... 32|
|Table 4.9. sysI/O Single-Ended DC Electrical Characteristics|Table 4.9. sysI/O Single-Ended DC Electrical Characteristics1............................................................................................. 33|
|Table 4.10. LVDS/subLVDS1/SLVS200|Table 4.10. LVDS/subLVDS1/SLVS2001, 2............................................................................................................................ 33|
|Table 4.11. MIPI D-PHY ....................................................................................................................................................... 34|Table 4.11. MIPI D-PHY ....................................................................................................................................................... 34|
|Table 4.12. CrossLink Maximum I/O Buffer Speed ............................................................................................................. 35|Table 4.12. CrossLink Maximum I/O Buffer Speed ............................................................................................................. 35|
|Table 4.13. CrossLink External Switching Characteristics|Table 4.13. CrossLink External Switching Characteristics3, 4............................................................................................... 36|
|Table 4.14. sysCLOCK PLL Timing ........................................................................................................................................ 42|Table 4.14. sysCLOCK PLL Timing ........................................................................................................................................ 42|
|Table 4.15. 1500 Mb/s MIPI_DPHY_X8_RX/TX Timing Table (1500 Mb/s > MIPI D-PHY Data Rate > 1200 Mb/s)* .......... 43|Table 4.15. 1500 Mb/s MIPI_DPHY_X8_RX/TX Timing Table (1500 Mb/s > MIPI D-PHY Data Rate > 1200 Mb/s)* .......... 43|
|Table 4.16. 1200 Mb/s MIPI_DPHY_X4_RX/TX Timing Table (1200 Mb/s > MIPI D-PHY Data Rate > 1000 Mb/s) ............ 43|Table 4.16. 1200 Mb/s MIPI_DPHY_X4_RX/TX Timing Table (1200 Mb/s > MIPI D-PHY Data Rate > 1000 Mb/s) ............ 43|
|Table 4.17. 1000 Mb/s MIPI_DPHY_X4_RX/TX Timing Table (1000 Mb/s > MIPI D-PHY Data Rate > 10 Mb/s) ................ 43|Table 4.17. 1000 Mb/s MIPI_DPHY_X4_RX/TX Timing Table (1000 Mb/s > MIPI D-PHY Data Rate > 10 Mb/s) ................ 43|
|Table 4.18. Internal Oscillators ........................................................................................................................................... 43|Table 4.18. Internal Oscillators ........................................................................................................................................... 43|
|Table 4.19. User I|Table 4.19. User I2C1.......................................................................................................................................................... 44|
|Table 4.20. CrossLink sysCONFIG Port Timing Specifications ............................................................................................. 44|Table 4.20. CrossLink sysCONFIG Port Timing Specifications ............................................................................................. 44|
|Table 4.21. SRAM Configuration Time from NVCM ............................................................................................................ 44|Table 4.21. SRAM Configuration Time from NVCM ............................................................................................................ 44|
|Table 4.22. Test Fixture Required Components, Non-Terminated Interfaces* .................................................................. 45|Table 4.22. Test Fixture Required Components, Non-Terminated Interfaces* .................................................................. 45|
|Table 5.1. WLCSP36 Pinout ................................................................................................................................................. 46|Table 5.1. WLCSP36 Pinout ................................................................................................................................................. 46|
|Table 5.2. ucfBGA64 Pinout ................................................................................................................................................ 47|Table 5.2. ucfBGA64 Pinout ................................................................................................................................................ 47|
|Table 5.3. ctfBGA80/ckfBGA80 Pinout ............................................................................................................................... 49|Table 5.3. ctfBGA80/ckfBGA80 Pinout ............................................................................................................................... 49|
|Table 5.4. csfBGA81 Pinout ................................................................................................................................................ 51|Table 5.4. csfBGA81 Pinout ................................................................................................................................................ 51|
|Table 5.5. Dual Function Pin Descriptions .......................................................................................................................... 53|Table 5.5. Dual Function Pin Descriptions .......................................................................................................................... 53|
|Table 5.6. Dedicated Function Pin Descriptions ................................................................................................................. 54|Table 5.6. Dedicated Function Pin Descriptions ................................................................................................................. 54|
|Table 5.7. Pin Information Summary .................................................................................................................................. 55|Table 5.7. Pin Information Summary .................................................................................................................................. 55|
© 2015-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02007-1.8
5
**CrossLink Family Data Sheet**
## **Acronyms in This Document**
A list of acronyms used in this document.
|**Acronym **<br>~~ee~~|**Definition**|
|---|---|
|AR<br>~~ee~~<br>~~ee~~|Augmented Reality|
|ASIC<br>~~ee~~<br>~~ee~~|Application-Specific Integrated Circuit|
|BGA<br>~~ee~~<br>~~Ge~~|Ball Grid Array<br>~~Ge~~|
|CMOS<br>~~Ge~~<br>~~eG~~|ComplementaryMetal Oxide Semiconductor<br>~~Ge~~<br>~~eG~~|
|CSI<br>~~eG~~<br>~~eG~~<br>~~ee~~|Camera Serial Interface<br>~~eG~~<br>~~eG~~|
|DBI<br>~~eG~~<br>~~ee~~|DisplayBus Interface<br>~~eG~~|
|DDR<br>~~ee~~<br>~~eG~~|Double Data Rate<br>~~eG~~|
|DPI<br>~~eG~~<br>~~eG~~|DisplayPixel Interface<br>~~eG~~<br>~~eG~~|
|DSI<br>~~Ge~~|DisplaySerial Interface<br>~~Ge~~|
|EBR<br>~~Ge~~<br>~~eG~~|Embedded Block RAM<br>~~Ge~~<br>~~eG~~|
|ECLK<br>~~eG~~<br>~~eG~~|Edge Clock<br>~~eG~~<br>~~eG~~|
|FPGA<br>~~eG~~<br>~~eG~~<br>~~ee~~|Field-Programmable Gate Array<br>~~eG~~<br>~~eG~~|
|FPD<br>~~eG~~<br>~~ee~~|Flat Panel Display<br>~~eG~~|
|GPIO<br>~~ee~~<br>~~eG~~<br>~~ee~~|General-Purpose Input/Output<br>~~eG~~|
|HFOSC<br>~~ee~~|High FrequencyOscillator|
|HMI<br>~~ee~~<br>~~Ge~~|Human Machine Interface<br>~~Ge~~|
|I2C<br>~~Ge~~<br>~~eG~~|Inter-Integrated Circuit<br>~~Ge~~<br>~~eG~~|
|ISM<br>~~eG~~<br>~~eG~~<br>~~ee~~|Industrial, Scientific, Medical<br>~~eG~~<br>~~eG~~|
|LFOSC<br>~~eG~~<br>~~ee~~|Low FrequencyOscillator<br>~~eG~~|
|LUT<br>~~ee~~<br>~~eG~~|Look UpTable<br>~~eG~~|
|LVCMOS<br>~~eG~~<br>~~eG~~|Low-Voltage ComplementaryMetal Oxide Semiconductor<br>~~eG~~<br>~~eG~~|
|LVDS<br>~~Ge~~|Low-Voltage Differential Signaling<br>~~Ge~~|
|LVTTL<br>~~Ge~~<br>~~eG~~<br>~~ee~~|Low Voltage Transistor-Transistor Logic<br>~~Ge~~<br>~~eG~~|
|MIPI<br>~~eG~~<br>~~ee~~<br>~~a~~|Mobile IndustryProcessor Interface<br>~~eG~~<br>|
|NVCM<br>~~ee~~<br>~~a~~|Non-Volatile Configuration Memory<br>|
|OTP<br>~~aeG~~<br>~~ee~~|One Time Programmable<br>~~eG~~|
|PCLK<br>~~eG~~<br>~~ee~~<br>~~ee~~|PrimaryClock<br>~~eG~~|
|PFU<br>~~ee~~<br>~~ee~~|Programmable Functional Unit|
|PLL<br>~~ee~~<br>~~a~~|Phase Locked Loops<br>|
|PMU<br>~~aeG~~<br>~~ee~~|Power Management Unit<br>~~eG~~|
|RAM<br>~~eG~~<br>~~ee~~<br>~~a~~|Random Access Memory<br>~~eG~~<br>|
|Rx<br>~~ee~~<br>~~a~~|Receive<br>|
|SDR<br>~~aeG~~<br>~~ee~~|Single Data Rate<br>~~eG~~|
|SLVS200<br>~~eG~~<br>~~ee~~<br>~~ee~~|Scalable Low-Voltage Signaling<br>~~eG~~|
|SPI<br>~~ee~~<br>~~ee~~|Serial Peripheral Interface|
|TransFR<br>~~ee~~<br>~~a~~<br>~~ee~~|Transparent Field Reconfiguration|
|Tx<br>~~a~~<br>~~ee~~<br>~~a~~|Transmit<br>|
|UHD<br>~~ee~~<br>~~a~~|Ultra-High-Definition<br>|
|VR<br>~~aeG~~|Virtual Reality<br>~~eG~~|
|WLCSP<br>~~eG~~<br>~~Ge~~|Wafer Level ChipScale Packaging<br>~~eG~~<br>~~Ge~~|
© 2015-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02007-1.8
6
**CrossLink Family Data Sheet**
## **1. General Description**
CrossLink™ from Lattice Semiconductor is a
programmable video bridging device that supports a variety of protocols and interfaces for mobile image sensors and displays. The device is based on Lattice mobile FPGA 40-nm technology. It combines the extreme flexibility of an FPGA with the low power, low cost and small footprint of an ASIC.
CrossLink supports video interfaces including MIPI[®] DPI, MIPI DBI, CMOS camera and display interfaces, OpenLDI, FPD-Link, FLATLINK, MIPI D-PHY, MIPI CSI-2, MIPI DSI, SLVS200, subLVDS, HiSPi and more.
Lattice Semiconductor provides many pre-engineered IP (Intellectual Property) modules for CrossLink. By using these configurable soft core IPs as standardized blocks, designers are free to concentrate on the unique aspects of their design, increasing their productivity.
The Lattice Diamond[®] design software allows large complex designs to be efficiently implemented using CrossLink. Synthesis library support for CrossLink devices is available for popular logic synthesis tools. The Diamond tools use the synthesis tool output along with the constraints from its floor planning tools to place and route the design in the CrossLink device. The tools extract the timing from the routing and back-annotate it into the design for timing verification.
Interfaces on CrossLink provide a variety of bridging solutions for smart phone, tablets, wearables, VR, AR, Drone, Smart Home, HMI as well as adjacent ISM markets. The device is capable of supporting high-resolution, high-bandwidth content for mobile cameras and displays at 4 UHD and beyond.
- Programmable architecture 5936 LUTs
- 180 Kb block RAM
- 47 Kb distributed RAM
- Two hardened 4-lane MIPI D-PHY interfaces
- Transmit and receive
- 6 Gb/s per D-PHY interface
- Programmable source synchronous I/O
- MIPI D-PHY Rx, LVDS Rx, LVDS Tx, subLVDS Rx, SLVS200 Rx, HiSPi Rx
- Up to 1200 Mb/s per I/O
- Four high-speed clock inputs
- Programmable CMOS I/O
- LVTTL and LVCMOS
- 3.3 V, 2.5 V, 1.8 V and 1.2 V (outputs)
- LVCMOS differential outputs
- Flexible device configuration
- One Time Programmable (OTP) non-volatile configuration memory
- Master SPI boot from external flash
- Dual image booting supported
- I[2] C programming
- SPI programming
- TransFR™ I/O for simple field updates
- Enhanced system level support
- Reveal logic analyzer
- TraceID for system tracking
- On-chip hardened I[2] C block
- Applications examples
- Dual MIPI CSI-2 to Single MIPI CSI-2 Aggregation
- Quad MIPI CSI-2 to Single MIPI CSI-2 Aggregation
- Single MIPI DSI to Single MIPI DSI Repeater
## **1.1. Features**
- Ultra-low power
- Sleep Mode Support
- Normal Operation – From 5 mW to 150 mW
- Ultra small footprint packages
- 36-ball WLCSP (6 mm[2] )
- 64-ball ucfBGA (12 mm[2] )
- 80-ball ctfBGA (42 mm[2] )
- Single MIPI CSI-2 to Single MIPI CSI-2 Repeater
- Single MIPI DSI to Dual MIPI DSI Splitter
- Single MIPI CSI-2 to Dual MIPI CSI-2 Splitter
- MIPI DSI to OpenLDI/FPD-Link/LVDS Translator
- OpenLDI/FPD-Link/LVDS to MIPI DSI Translator MIPI DSI/CSI-2 to CMOS Translator
- CMOS to MIPI DSI/CSI-2 Translator
- subLVDS to MIPI CSI-2 Translator
- 80-ball ckfBGA (49 mm[2] )
- 81-ball csfBGA (20 mm[2] )
© 2015-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02007-1.8
7
**CrossLink Family Data Sheet**
## **2. Product Feature Summary**
Table 2.1 lists CrossLink device information and packages.
## **Table 2.1. CrossLink Feature Summary**
|**Device**|**CrossLink**|
|---|---|
|LUTs|5936|
|sysMEM Blocks (9 Kb)|20|
|Embedded Memory (Kb)|180|
|Distributed RAM Bits (Kb)|47|
|General Purpose PLL|1|
|NVCM|Yes|
|Embedded I2C|2|
|Oscillator (10 KHz)|1|
|Oscillator (48 MHz)|1|
|Hardened MIPI D-PHY|21, 2|
|**Packages (Footprint, Pitch)**|**I/O**|
|36 WLCSP2(2.535 × 2.583 mm2, 0.4 mm)|17|
|64 ucfBGA (3.5 × 3.5 mm2, 0.4 mm)|29|
|80 ctfBGA (6.5 x 6.5 mm2, 0.65 mm)|37|
|80 ckfBGA (7.0 x 7.0 mm2, 0.65 mm)|37|
|81 csfBGA (4.5 × 4.5 mm2, 0.5 mm)|37|
**Notes** :
1. Additional D-PHY Rx interfaces are available using programmable I/O.
2. Only one Hardened D-PHY is available in 36 WLCSP package.
© 2015-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
8
FPGA-DS-02007-1.8
**CrossLink Family Data Sheet**
## **3. Architecture Overview**
CrossLink is designed as a flexible, chip-to-chip bridging solution which supports a wide variety of applications. The device provides three key building blocks for these bridging applications:
- Up to two embedded Hard D-PHY blocks
- Two banks of flexible programmable I/O supporting a variety of standards including D-PHY Rx, subLVDS, SLVS200, LVDS, and CMOS
- A programmable logic core providing the LUTs, memory, and system resources to implement a wide range of bridging operations
In addition to these blocks, CrossLink also provides key system resources including a Power Management Unit, flexible configuration interface, additional CMOS GPIO, and user I[2] C blocks.
The block diagram for the device is shown in Figure 3.1.
**==> picture [426 x 322] intentionally omitted <==**
**----- Start of picture text -----**<br>
Programmable IO<br>MIPI D-PHY<br>Rx: D-PHY / subLVDS /<br>LVDS / SLVS200 / CMOS 6 Gb/s<br>Programmable FPGA Fabric Rx & Tx<br>Tx: LVDS / CMOS 5,936 LUTs<br>180 kbits block RAM 4 Data Lanes<br>Up to 1.2 Gb/s per Lane 47 kbits distributed RAM 1 Clock Lane<br>14 IO / 7 Pairs<br>Enough FPGA resources to handle video:<br>Muxing<br>Merging<br>Programmable IO Demuxing<br>Arbitration MIPI D-PHY<br>Rx: D-PHY / subLVDS / Splitting<br>LVDS / SLVS200 / CMOS Data Conversion 6 Gb/s<br>Custom Protocol Design Rx & Tx<br>Tx: LVDS / CMOS<br>4 Data Lanes<br>Up to 1.2 Gb/s per Lane 1 Clock Lane<br>16 IO / 8 Pairs<br>Power Management Unit GPIOs I2C / SPI [1]<br>**----- End of picture text -----**<br>
**Figure 3.1. CrossLink Device Block Diagram**
**Note** : I[2] C and SPI configuration modes are supported. User mode hardened I[2] C is also supported.
© 2015-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02007-1.8
9
**CrossLink Family Data Sheet**
## **3.1. MIPI D-PHY Blocks**
The top side of the device (Figure 3.2) includes two hard MIPI D-PHY quads. The D-PHY can be configured to support both camera interface (CSI-2) and display interface (DSI) applications. Below is a summary of the features supported by the hard D-PHY quads.
- Transmit and Receive compliant to MIPI Alliance Specification for D-PHY Revision 1.1
- High-Speed (HS) and Low-Power (LP) mode support (including built-in contention detect)
- Supports continuous clock mode or low power clock mode
- Up to 6 Gb/s per quad (1500 Mb/s data rate per lane)
- Dedicated PLL for Transmit Frequency Synthesis
Dedicated Serializer and De-Serializer blocks for fabric interfacing. Lattice Semiconductor provides a set of preengineered IP modules which include the full implementation and control of the hard D-PHY blocks to enable designers to focus on unique aspects of their design.
Figure 3.3 to Figure 3.6 show the signals connected to the fabric and the automatic settings when the hardened D-PHY is configured for the DSI/CSI-2 transmit and receive modes. Refer to CrossLink High-Speed I/O Interface (FPGA-TN02012) for more information on the Hard D-PHY quads.
**==> picture [247 x 277] intentionally omitted <==**
**----- Start of picture text -----**<br>
TOP<br>[oo1 ne nnn - nn 2-22 -- === === enon nn nnn nen eo 2 $$$ $2 2-2 one nee<br>!I1' ttottt t o t ttt 1'11 '<br>1I1 MIPI D-PHY 0 t o t MIPI D-PHY 1 '<br>!I1'[re ttottttot| ttt[ee1'11'<br>Bank 2 Bank 1 Bank 0<br>EE EE ran<br>i !eeequaccacencescacenccananccatemmecasesencencasencencacepecasscemaqessesss' 1 ' |<br>! ! !1Suungggggggggegqess==s==s= 1 \ t' ! 1 a 1 1 1 !\1 f iI iI1<br>! 1 f 1 \ i t ' \ ' \ 1<br>U-----}-----------)--------' L------}------------4------4 a nn ee<br>i |i H' 11 Hl1 'Hl<br>7 t T r 1 T<br>BOTTOM<br>GND VCCIO2 GND VCCIO1 GND VCCIO0<br>**----- End of picture text -----**<br>
**Figure 3.2. CrossLink sysI/O Banking**
© 2015-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
10
FPGA-DS-02007-1.8
**CrossLink Family Data Sheet**
MOBS SEMICONDUCTOR
**==> picture [367 x 562] intentionally omitted <==**
**----- Start of picture text -----**<br>
MIPIDPHYA<br>Bidirectional clk and data<br>CLKP<br>CLKN Mm —_<br>DP[3:1] mm —<br>DN[3:1] +"<br>DP0 <<<br>DN0 «><br>D0_RXLPP<br>RX - Data LP ports<br>D0_RXLPN<br>TX – Data HS ports<br>D0_TXHSEN<br>TXHSBYTECLK<br>Dy_HSTXDATA[15:0]<br>D0_TXLPEN TX – Data LP ports<br>D0_TXLPP<br>D0_TXLPN<br>Dx_TXLPP<br>Dx_TXLPN<br>TX – CLK HS ports<br>CLK_TXHSEN >]<br>CLK_TXHSGATE ——>|<br>TX – CLK LP ports<br>CLK_TXLPP<br>CLK_TXLPN<br>Control Ports<br>USRSTDBY<br>PDPLL<br>PLL Ports<br>REFCLK LOCK<br>* x = 1, 2, 3<br> y = 0, 1, 2, 3<br>**----- End of picture text -----**<br>
**Figure 3.3. MIPI DSI Transmit Interface with Hard D-PHY Module**
© 2015-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02007-1.8
11
**CrossLink Family Data Sheet**
**==> picture [398 x 564] intentionally omitted <==**
**----- Start of picture text -----**<br>
MIPIDPHYA<br>Bidirectional clk and data<br>CLKP<br>CLKN<br>DP[3:1]<br>DN[3:1]<br>DP0<br>DN0<br>TX – Data HS ports<br>D0_TXHSEN<br>TXHSBYTECLK<br>Dy_HSTXDATA[15:0]<br>TX – Data LP ports<br>D0_TXLPEN<br>TX – CLK HS ports<br>CLK_TXHSEN<br>CLK_TXHSGATE<br>TX – CLK LP ports<br>CLK_TXLPP<br>CLK_TXLPN<br>CLK_TXLPEN<br>Control Ports<br>USRSTDBY<br>PDPLL<br>PLL Ports<br>REFCLK LOCK<br>* x = 1, 2, 3<br> y = 0, 1, 2, 3<br>**----- End of picture text -----**<br>
**Figure 3.4. MIPI CSI-2 Transmit Interface with Hard D-PHY Module**
© 2015-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
12
FPGA-DS-02007-1.8
**CrossLink Family Data Sheet**
## HELAT TICE
**==> picture [388 x 558] intentionally omitted <==**
**----- Start of picture text -----**<br>
MIPIDPHYA<br>CLKP Bidirectional clk and data<br>CLKN<br>DPx<br>DNx<br>DP0<br>DN0<br>RX - Data HS ports<br>DO_RXHSEN Dy_HSRXDATA[15:0]<br>RXHSBYTECLK<br>RX - Data LP ports D0_RXLPP<br>D0_RXLPN<br>DO_RXLPEN<br>D0_CD<br>RX - CLK HS ports<br>CLKRXHSEN<br>CLKHSBYTE<br>RX - CLK LP ports<br>CLK_RXLPP<br>CLKRXLPEN CLK_RXLPN<br>CLK_CD<br>TX – Data LP ports<br>D0_TXLPP<br>D0_TXLPN<br>Control Ports<br>USRSTDBY<br>* x = 1, 2, 3<br> y = 0, 1, 2, 3<br>**----- End of picture text -----**<br>
**Figure 3.5. MIPI DSI Receive Interface with Hard D-PHY Module**
© 2015-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02007-1.8
13
**CrossLink Family Data Sheet**
**==> picture [376 x 422] intentionally omitted <==**
**----- Start of picture text -----**<br>
MIPIDPHYA<br>Bidirectional clk and data<br>CLKP<br>CLKN<br>DPx<br>DNx<br>DP0<br>DN0<br>RX - Data HS ports<br>Dy_HSRXDATA[15:0]<br>RXHSBYTECLK<br>RX - Data LP ports<br>D0_RXLPP<br>D0_RXLPN<br>D0_CD<br>RX - CLK HS ports<br>CLKHSBYTE<br>RX - CLK LP ports<br>CLK_RXLPP<br>CLK_RXLPN<br>CLK_CD<br>Control Ports<br>USRSTDBY<br>* x = 1, 2, 3<br> y = 0, 1, 2, 3<br>**----- End of picture text -----**<br>
**Figure 3.6. MIPI CSI-2 Receive Interface with Hard D-PHY Module**
© 2015-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02007-1.8
14
**CrossLink Family Data Sheet**
## **3.2. Programmable I/O Banks**
CrossLink devices provide programmable I/O which can be used to interface to a variety of external standards on Banks 1 and 2. CrossLink devices also provide dedicated CMOS GPIOs on Bank 0. Bank 0 GPIOs only support Single Data Rate (SDR) interfaces, while Bank 1 and Bank 2 support both SDR and Double Data Rate (DDR) interfaces. The GPIOs on Bank 0 do not include differential signaling capabilities. The location of the three Banks and their associated supplies are shown in Figure 3.2.
Bank 0 features:
- Support for the following single ended standards
- LVCMOS33
- LVCMOS25
- LVCMOS18
- LVTTL33
- Tri-state control for output
- Input/output register blocks
- Open-drain option and programmable input hysteresis
- Internal pull-up resistors with configurable values of 3.3 kΩ, 6.8 kΩ, and 10 kΩ
Bank 1 and Bank 2 features:
- Built-in support for the following differential standards
- LVDS – Tx and Rx
- SLVS200 – Rx
- subLVDS – Rx
- MIPI – Rx (both LP and HS receive on a single differential pair)
- Support for the following single ended standards
- LVCMOS33
- LVCMOS25
- LVCMOS18
- LVCMOS12 (Outputs Only)
- LVTTL33
- Independent voltage levels per bank based on VCCIO supply
- Input/output gearboxes per LVDS pair supporting several ratios for video interface applications
- DDRX1, DDRX2, DDRX4, DDRX8 and DDRX71, DDRX141
- Programmable delay cells to support edge-aligned and center-aligned interfaces
- Programmable differential termination (~ 100 Ω) with dynamic enable control
- Tri-state control for output
- Input/output register blocks
- Single-ended standards support open-drain and programmable input hysteresis
- Optional weak pull-up resistors
**Table 3.1. CrossLink Output Support per Bank Basis**
|**OUTPUT**|**BANK 0**|**BANK 1**|**BANK 2**|
|---|---|---|---|
|LVCMOS12|—|||
|LVCMOS18||||
|LVCMOS25||||
|LVCMOS33||||
|LVTTL33||||
|LVDS25|—|||
© 2015-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02007-1.8
15
**CrossLink Family Data Sheet**
**Table 3.2. CrossLink Input Support per Bank Basis**
|**INPUT**|**BANK 0**|**BANK 1**|**BANK 2**|
|---|---|---|---|
|LVCMOS12|—|—|—|
|LVCMOS18||||
|LVCMOS25||||
|LVCMOS33||||
|LVTTL33||||
|LVDS25|—|||
|MIPI D-PHY|—|||
|SLVS200|—|||
|subLVDS|—|||
## **3.3. sysI/O Buffers**
The CrossLink sysI/O buffers are distributed across three banks located at the bottom of the CrossLink device as shown in Figure 3.2. The sysI/O buffers support a wide variety of standards to interface to a range of systems including LVDS, subLVDS, LVCMOS, LVTTL, SLVS200 and MIPI. CrossLink supports single-ended buffers on all three banks. Differential I/O is supported on Bank 1 and Bank 2.
## **3.3.1. Programmable PULLMODE Settings**
The CrossLink sysI/O buffers offer multiple programmable value pull-up resistors on the three banks. The pull-up values are programmable on a “per-pin” basis. The default state of the I/O pins prior to configuration is tri-stated with a weak pull-up to VCCIOx. The I/O pins convert to the software user-defined settings after the configuration bitstream is successfully downloaded to the device. Each sysIO buffer can be programmed with a 100 kΩ (weak pull-up), 3.3 kΩ, 6.8 kΩ, 10 kΩ or no pull-up. These pull-up options allow an I[2] C interface to be place on the majority of the pins on the device. These options are not exclusively for I[2] C protocol and may be used for other functions.
## **3.3.2. Output Drive Strength**
Each CrossLink output can have its own individual drive strength setting, but is predefined based on the VCCIOx setting. Table 3.3 lists the drive settings for the corresponding I/O type.
**Table 3.3. Drive Strength Values**
|**VCCIOx (V)**|**I/O Type**|**Drive Strength (mA)**|
|---|---|---|
|3.3|LVTTL33|8|
|3.3|LVCMOS33|8|
|2.5|LVCMOS25|6|
|1.8|LVCMOS18|4|
|1.2|LVCMOS12|2|
## **3.3.3. On-Chip Termination**
Bank 1 and bank 2 of CrossLink support LVDS, SLVS200 subLVDS and MIPI D-PHY inputs. These two banks support onchip 100 Ω input differential termination between LVDS, SLVS200 and subLVDS pairs. For MIPI D-PHY inputs, the onchip 100 Ω termination is dynamically enabled based on the HSSEL (High Speed Select) signal.
See CrossLink High-Speed I/O Interface (FPGA-TN-02012) and CrossLink sysI/O Usage Guide (FPGA-TN-02016) for details.
© 2015-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02007-1.8
16
**CrossLink Family Data Sheet**
## **3.4. Programmable FPGA Fabric**
CrossLink is built around a programmable logic fabric consisting of 5936 four input lookup tables (LUT4) arranged alongside dedicated registers in Programmable Functional Units (PFU). These PFU blocks are the building blocks for logic, arithmetic, RAM and ROM functions. The PFU blocks are connected via a programmable routing network. The Lattice Diamond design software configures the PFU blocks and the programmable routing for each unique design. Interspersed between rows of PFU are rows of sysMEM™ Embedded Block RAM (EBR), with programmable I/O banks, embedded I[2] C and embedded MIPI D-PHY arranged on the top and bottom of the device as shown in Figure 3.7.
**==> picture [369 x 216] intentionally omitted <==**
**----- Start of picture text -----**<br>
MIPI D-PHY 0 MIPI D-PHY 1<br>PFU PFU PFU PFU PFU<br>4 EBR Blocks (9 kb each) 4 EBR Blocks (9 kb each) 4 EBR Blocks (9 kb each) 4 EBR Blocks (9 Kb each) 4 EBR Blocks (9 kb each)<br>PFU PFU PFU PFU PFU<br>Clocking PMU<br>Bank 2 PLL Bank 1 Bank 0<br>CONFIG<br>PEEEEEEEEEees DDRDLL2 OSC a DDRDLL1<br>I2C0 NVCM I2C1<br>**----- End of picture text -----**<br>
**Figure 3.7. CrossLink Device Simplified Block Diagram (Top Level)**
## **3.4.1. PFU Blocks**
The core of the CrossLink device consists of PFU blocks. Each PFU block consists of four interconnected slices numbered 0 – 3 as shown in Figure 3.8. Each slice contains two LUTs. All the interconnections to and from PFU blocks are from routing. The PFU block can be used in Distributed RAM or ROM function, or used to perform Logic, Arithmetic or ROM functions.
**==> picture [361 x 207] intentionally omitted <==**
**----- Start of picture text -----**<br>
From<br>Routing<br>J &<br>LUT4 & LUT4 & LUT4 & LUT4 & LUT4 & LUT4 & LUT4 & LUT4 &<br>CARRY CARRY CARRY CARRY CARRY CARRY CARRY CARRY<br>Slice 0 Slice 1 Slice 2 Slice 3<br>D D D D D D D D<br>FF FF FF FF FF FF FF FF<br>EE ELE<br>To<br>Routing<br>J &<br>**----- End of picture text -----**<br>
**Figure 3.8. CrossLink PFU Diagram**
© 2015-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02007-1.8
17
**CrossLink Family Data Sheet**
## **3.4.2. Slice**
Each slice contains two LUT4s feeding two registers. Each PFU contains logic that allows the LUTs to be combined to perform functions such as LUT5, LUT6, LUT7 and LUT8. There is control logic to perform set/reset functions (programmable as synchronous/asynchronous), clock select, chip-select and wider RAM/ROM functions. Figure 3.9 shows an overview of the internal logic of the slice. The registers in the slice can be configured for positive/negative and edge triggered or level sensitive clocks.
Each slice has 14 input signals: 13 signals from routing and 1 signal from the carry-chain routed from the adjacent slice or PFU. There are five outputs: four to routing and one to carry-chain (to the adjacent PFU). There are two inter slice/PFU output signals that are used to support wider LUT functions, such as LUT6, LUT7, and LUT8. Table 3.4 and Figure 3.10 list the signals associated with all the slices. Figure 3.8 shows the connectivity of the inter-slice/PFU signals that support LUT5, LUT6, LUT7, and LUT8.
**==> picture [169 x 398] intentionally omitted <==**
**----- Start of picture text -----**<br>
FCO<br>FXA<br>FXB ><br>M1 i<br>M0 i<br>A1<br>B1 LUT4 &<br>C1 | | < CARRY*<br>D1<br>a -<br>F1 in<br>F1<br>FF<br>: -<br>Q1<br>A0<br>B0 LUT4 &<br>C0 | | CARRY*<br>D0<br>og<br>F0 i<br>F0<br>FF<br>-<br>:<br>Q0CE lyid<br>CLK I<<br>LSR<br>FCI __4 From Different Slice/PFU<br>**----- End of picture text -----**<br>
**Notes** : For Slices 0 and 1, memory control signals are generated from Slice 2 as follows: WCK is CLK WRE is from LSR DI[3:2] for Slice 1 and DI[1:0] for Slice 0 data from Slice 2 WAD [A:D] is a 4-bit address from slice 2 LUT input
**Figure 3.9. Slice Diagram**
© 2015-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
18
FPGA-DS-02007-1.8
**CrossLink Family Data Sheet**
**==> picture [468 x 360] intentionally omitted <==**
**----- Start of picture text -----**<br>
PFU Col(n-1) PFU Col(n) PFU Col(n+1)<br>B1A1 F1 LUT8 B1A1 F1 LUT8 B1A1 F1 LUT8<br>C1 C1 C1<br>D1 Q1 D1 Q1 D1 Q1<br>A0 A0 A0<br>B0 LUT5 B0 LUT5 B0 LUT5<br>C0 F0 C0 F0 C0 F0<br>D0 D0 D0<br>FXB Q0 FXB Q0 FXB Q0<br>LUT7 Output FXA FXA FXA LUT7 Output<br>To Next PFU From Previous PFU<br>A1 LUT6 A1 LUT6 A1 LUT6<br>B1 F1 B1 F1 B1 F1<br>C1 C1 C1<br>D1 Q1 D1 Q1 D1 Q1<br>A0 A0 A0<br>B0 LUT5 B0 LUT5 B0 LUT5<br>C0 F0 C0 F0 C0 F0<br>D0 D0 D0<br>FXB Q0 FXB Q0 FXB Q0<br>FXA FXA FXA<br>B1A1 F1 LUT7 B1A1 F1 LUT7 B1A1 F1 LUT7<br>C1 C1 C1<br>D1 Q1 D1 Q1 D1 Q1<br>A0 A0 A0<br>B0 LUT5 B0 LUT5 B0 LUT5<br>C0 F0 C0 F0 C0 F0<br>D0 D0 D0<br>FXB Q0 FXB Q0 FXB Q0<br>FXA FXA FXA<br>Li Lr Oo<br>A1 LUT6 A1 LUT6 A1 LUT6<br>B1 F1 B1 F1 B1 F1<br>C1 C1 C1<br>D1 Q1 D1 Q1 D1 Q1<br>A0 A0 A0<br>B0 LUT5 B0 LUT5 B0 LUT5<br>C0 F0 C0 F0 C0 F0<br>D0 D0 D0<br>FXB Q0 FXB Q0 FXB Q0<br>FXA FXA FXA<br>Ce LE<br>3 3 3<br>SLICE SLICE SLICE<br>2 2 2<br>SLICE SLICE SLICE<br>1 1 1<br>SLICE SLICE SLICE<br>0 0 0<br>SLICE SLICE SLICE<br>**----- End of picture text -----**<br>
**Figure 3.10. Connectivity Supporting LUT5, LUT6, LUT7 and LUT8**
**Table 3.4. Slice Signal Descriptions**
|**Function**|**Type**|**Signal Names**|**Description**|
|---|---|---|---|
|Input|Data signal|A0, B0, C0, D0|Inputs to LUT4|
|Input|Data signal|A1, B1, C1, D1|Inputs to LUT4|
|Input|Multi-purpose|M0|Multipurpose Input|
|Input|Multi-purpose|M1|Multipurpose Input|
|Input|Control signal|CE|Clock Enable|
|Input|Control signal|LSR|Local Set/Reset|
|Input|Control signal|CLK|System Clock|
|Input|Inter-PFU signal|FCI|Fast Carry-in1|
|Input|Inter-slice signal|FXA|Intermediate signal to generate LUT6, LUT7 and LUT82|
|Input|Inter-slice signal|FXB|Intermediate signal to generate LUT6, LUT7 and LUT82|
|Output|Data signals|F0, F1|LUT4 output register bypass signals|
|Output|Data signals|Q0, Q1|Register outputs|
|Output|Inter-PFU signal|FCO|Fast carry chain output1|
**Notes** :
1. See Figure 3.9 for connection details.
2. Requires two adjacent PFUs.
© 2015-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02007-1.8
19
**CrossLink Family Data Sheet**
## **3.5. Clocking Structure**
The CrossLink device family provides resources to support a wide range of clocking requirements for programmable video bridging. These resources are described below. For details, refer to CrossLink sysCLOCK PLL/DLL Design and Usage Guide (FPGA-TN-02015).
## **3.5.1. sysCLK PLL**
The CrossLink sysCLK PLL provides the ability to synthesis clock frequencies (See Table 4.14 for input frequency range). The PLL provides features such as dynamic selectable clock input, clock injection delay removal, independent dynamic output enable control, and programmable output phase adjustment. The architecture of the PLL is shown in Figure 3.11.
**Figure 3.11. CrossLink PLL Block Diagram**
Table 3.5 provides a description of the signals in the PLL block.
**Table 3.5. CrossLink PLL Port Definition**
|**Signal**|**I/O**|**Description**|
|---|---|---|
|CLKI|I|Input clock to PLL|
|CLKFB|I|Feedback clock|
|USRSTDBY|I|Userport toput the PLL to sleepmode|
|PHASESEL[1:0]|I|Select the output affected byDynamic Phase adjustment|
|PHASEDIR|I|Dynamicphase adjustment direction|
|PHASESTEP|I|Dynamicphase adjustment step|
|PHASELOADREG|I|Load dynamicphase adjustment values into PLL|
|RST|I|Resets the whole PLL|
|ENCLKOP|I|Enable PLL output CLKOP|
|ENCLKOS|I|Enable PLL output CLKOS|
|ENCLKOS2|I|Enable PLL output CLKOS2|
|ENCLKOS3|I|Enable PLL output CLKOS3|
|PLLWAKESYNC|I|Enable PLL switchingfrom internal to user feedbackpath when PLL wake up|
|CLKOP|O|PLL main output clock|
|CLKOS|O|PLL output clock|
|CLKOS2|O|PLL output clock|
|CLKOS3|O|PLL output clock|
|LOCK|O|PLL LOCK to CLKI, asynchronous signal. Active high indicates PLL lock|
© 2015-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
20
FPGA-DS-02007-1.8
**CrossLink Family Data Sheet**
## **3.5.2. Primary Clocks**
The primary clock routing network is made up of low skew clock routing resources with connectivity to every synchronous element of the device. Primary clock sources are selected in the center mux and distributed on the primary clock routing to clock the synchronous elements in the FPGA fabric. CrossLink family of devices provide up to eight unique global primary clocks. Primary clock sources are:
- LVDS PIO pins
- GPIO pins
- PLL outputs
- Clock dividers
- Fabric internally generated clock signal
- Divided down clock from DPHY
- OSCI
The routing clock structure is shown in Figure 3.12.
**==> picture [425 x 266] intentionally omitted <==**
**----- Start of picture text -----**<br>
MIPI_DPHY0 MIPI_DPHY1<br>|<br>CLK_HS_BYTE_0 HS_BYTE_CLK0 (RX and TX) HS_BYTE_CLK1 (RX and TX) CLK_HS_BYTE_0<br>2 2<br>Center Mux<br>(8 PCLKs out)<br>2 2<br>K I +<br>OSC_HF OSC_LF<br>OSC PLL<br>—<br>CLKDIV CLKDIV CLKDIV CLKDIV<br>HL bea——<br>Edge Clocks Edge Clocks<br>Bank 2 Bank 1 Bank 0<br>GRPIO LVDSPIO LVDSPIO LVDSPIO LVDSPIO LVDSPIO LVDSPIO GRPIO GPIO GPIO<br>Entry Fabric Entry Fabric<br>**----- End of picture text -----**<br>
**Figure 3.12. CrossLink Clocking Structure**
## **3.5.3. Edge Clocks**
The CrossLink device has Edge Clock (ECLK) at the bottom two banks (Bank 1 and Bank 2) of the device (Figure 3.12). The CrossLink device has two edge clocks per Programmable I/O bank. These clocks, which have low injection time and skew, are used to clock I/O registers. Edge clock resources are designed for high speed I/O interfaces with high fan-out capability. The sources of edge clocks are:
- Dedicated Clock (PCLK) pins muxed with the DLLDEL output
- PLL outputs (CLKOP and CLKOS)
- Internal nodes
ELCK input MUX collects all clock sources as shown in Figure 3.13 below. There are two ECLK Input MUXs, one on each bank. It drives the ECLK SYNC modules and the ECLK Clock Divider through a 2 to 1 MUX.
© 2015-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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**CrossLink Family Data Sheet**
**==> picture [118 x 93] intentionally omitted <==**
**----- Start of picture text -----**<br>
Bank 1 or Bank 2 LVDS PCLK Pin<br>Bank 1 or Bank 2 DLLDEL Output<br>PLL CLKOP<br>PLL CLKOS<br>From Routing<br>**----- End of picture text -----**<br>
**==> picture [136 x 137] intentionally omitted <==**
**----- Start of picture text -----**<br>
From ECLKSYNC of<br>other bank on<br>same side<br>ECLK Tree<br>ECLKSYNCB<br>To ECLK of other<br>bank on same side<br>**----- End of picture text -----**<br>
**Figure 3.13. CrossLink Edge Clock Sources per Bank**
## **3.5.4. Dynamic Clock Enables**
Each PLL output has a user input signal to dynamically enable/disable its output to provide a glitch free clock. Then the clock enable signal is set to logic ‘0’, the corresponding output clock is held to logic ‘0’. This allows the user to save power by stopping the corresponding output clock when not in use.
## **3.5.5. Internal Oscillator (OSCI)**
The OSCI element performs multiple functions on the CrossLink device. It is used for configuration and available during user mode. OSCI element has the following features in user mode:
- Always-on low frequency clock output (LFCLKOUT) with nominal frequency of 10 kHz
- High-frequency clock output (HFCLKOUT) with nominal frequency of 48 MHz that can be enabled or disabled using HFOUTEN input
- Programmable output dividers (HFCLKDIV) for 48 MHz, 24 MHz, 12 MHz or 6 MHz HFCLKOUT output
- Both output clocks have a direct connection to primary clock routing
- Figure 3.14, Table 3.6 and Table 3.7 below show the OSCI definitions
**Figure 3.14. CrossLink OSCI Component Symbol**
**Table 3.6. OSCI Component Port Definition**
|**Port Name**|**I/O**|**Description**|
|---|---|---|
|HFOUTEN|I|High frequencyclock output enable|
|HFCLKOUT|O|High frequencyclock output|
|LFCLKOUT|O|Low Frequencyclock output|
**Table 3.7. OSCI Component Attribute Definition**
|**Defparam Name**|**Description**|**Value**|**Default**|
|---|---|---|---|
|HFCLKDIV|Configure HF oscillator output divider|1, 2, 4, 8|1|
© 2015-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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FPGA-DS-02007-1.8
**CrossLink Family Data Sheet**
## **3.6. Embedded Block RAM Overview**
CrossLink devices contain sysMEM Embedded Block RAM (EBR). The EBR consists of a 9-KB RAM with memory core, dedicated input registers and output registers with separate clock and clock enable.
Support for different memory configurations:
- Single Port
- True Dual Port
- Pseudo Dual Port
- ROM
- FIFO (logic wrapper added automatically by design tools)
Flexible customization features:
- Initialization of RAM/ROM
- Memory cascading (handled automatically by design tools)
- Optional parity bit support
- Byte-enable
- Multiple block size options
- RAM modes support optional Write Through or Read-Before-Write modes
For details, refer to CrossLink Memory Usage Guide (FPGA-TN-02017).
**Table 3.8. sysMEM Block Configurations**
|**Memory Mode**|**Memory Size Configurations**|
|---|---|
|Single Port|8,192 x 1<br>4,096 x 2<br>2,048 x 4<br>1,024 x 9<br>512 x 18|
|True Dual Port|8,192 x 1<br>4,096 x 2<br>2,048 x 4<br>1,024 x 9|
|Pseudo Dual Port|8,192 x 1<br>4,096 x 2<br>2,048 x 4<br>1,024 x 9<br>512 x 18|
|ROM|8,192 x 1<br>4,096 x 2<br>2,048 x 4<br>1,024 x 9<br>512 x 18|
© 2015-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02007-1.8
23
**CrossLink Family Data Sheet**
## **3.7. Power Management Unit**
The embedded Power Management Unit (PMU) allows low-power Sleep State of the device. Figure 3.15 shows the block diagram of the PMU IP.
When instantiated in the design, PMU is always on, and uses the low-speed clock from oscillator of the device to perform its operations.
The typical use case for the PMU is through a user implemented state machine that controls the sleep and wake up of the device. The state machine implemented in the FPGA fabric identifies when the device needs to go into sleep mode, issues the command through PMU’s FPGA fabric interface, assigns the parameters for sleep (time to wake up and so on) and issues Sleep command.
The device can be woken up externally using the PMU Wake-Up (USRWKUP) pin, or from the PMU Watch Dog Timer expiry or from I2C0 (address decoding detection or FIFO full in one of hardened I[2] C).
**==> picture [427 x 263] intentionally omitted <==**
**----- Start of picture text -----**<br>
Power Management Unit (PMU)<br>PMU Clock (From Oscillator)<br>(PMUCLK)<br>External User Wake-up<br>(USRWKUPN)<br>PMU Wake-up from I2C0<br>(PMUWKUP)<br>Power Control Unit<br>Watch Dog Timer<br>User Mode Signals<br>From FPGA Fabric<br>Register<br>PMU Control<br>Timer<br>Watch Dog<br>PMU Sleep Signal, SLEEP 8-bit Addressable Fabric Interface<br>**----- End of picture text -----**<br>
**Figure 3.15. CrossLink MIPI D-PHY Block**
## **3.7.1. PMU State Machine**
PMU can place the device in two mutually exclusive states – Normal State and Sleep State. Figure 3.16 shows the PMU State Machine triggers for transition from one state to the other.
- Normal state – All elements of the device are active to the extent required by the design. In this state, the device is at fully active and performing as required by the application.
- Note that the power consumption of the device is highest in this state.
- Sleep state – The device is power gated such that the device is not operational. The configuration of the device and the EBR contents are retained; thus in Sleep mode, the device does not lose configuration SRAM and EBR contents. When it transitions to Normal state, device operates with these contents preserved. The PMU is active along with the associated GPIOs.
- The power consumption of the device is lowest in this state. This helps reduce the overall power consumption for the device.
© 2015-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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FPGA-DS-02007-1.8
**CrossLink Family Data Sheet**
se G/MT TICE
**==> picture [278 x 116] intentionally omitted <==**
**----- Start of picture text -----**<br>
User Logic Initiated<br>Sleep Mode Normal Mode<br>User I2C/<br>External Wake-up/<br>WDT Expiry Wake-up<br>**----- End of picture text -----**<br>
**Figure 3.16. CrossLink PMU State Machine**
For more details, refer to Power Management and Calculation for CrossLink Devices (FPGA-TN-02018).
## **3.8. User I[2] C IP**
CrossLink devices have two I[2] C IP cores that can be configured either as an I[2] C master or as an I[2] C slave. The I2C0 core has pre-assigned pins, and supports PMU wakeup over I[2] C. The pins for the I2C1 interface are not pre-assigned – user can use any General Purpose I/O pins.
The I[2] C cores support the following functionality:
- Master and Slave operation
- 7-bit and 10-bit addressing
- Multi-master arbitration support
- Clock stretching
- Up to 1 MHz data transfer speed
- General call support
- Optionally delaying input or output data, or both
- Optional FIFO mode
- Transmit FIFO size is 10 bits x 16 bytes, receive FIFO size is 10 bits x 32 bytes
For further information on the User I[2] C, refer to CrossLink I2C Hardened IP Usage Guide (FPGA-TN-02019).
© 2015-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02007-1.8
25
**CrossLink Family Data Sheet**
## **3.9. Programming and Configuration**
CrossLink is a SRAM-based programmable logic device that includes an internal Non-Volatile Configuration Memory (NVCM), as well as flexible SPI and I[2] C configuration modes. CrossLink provides four modes for loading the configuration data into the SRAM memory.
- Self-Download (NVCM) mode – CrossLink retrieves bitstream from internal NVCM
- Master SPI mode – CrossLink retrieves bitstream from an external SPI Flash
- Slave SPI mode – System microprocessor writes bitstream to CrossLink through SPI port
- Slave I[2] C mode – System microprocessor writes bitstream to CrossLink through I[2] C port
CrossLink provides a set of sysCONFIG I/O pins to program and configure the FPGA. The sysCONFIG pins are grouped together to create ports (I[2] C, SSPI or MSPI) that are used to interact with the FPGA for programming, configuration, and access of resources inside the FPGA. The sysCONFIG pins (Table 3.9) in a configuration group may be active and used for programming the FPGA or they can be reconfigured to act as general purpose I/Os.
## **Table 3.9. CrossLink sysCONFIG Pins**
|**Pin Name**|**Associated sysCONFIG Port**|
|---|---|
|CRESETB|Self Download Mode/SSPI/MSPI/I2C|
|CDONE|Self Download Mode/SSPI/MSPI/I2C|
|SPI_SCK/MCK/SDA|SSPI/MSPI/I2C|
|SPI_SS/CSN/SCL|SSPI/MSPI/I2C|
|MOSI|SSPI/MSPI|
|MISO|SSPI/MSPI|
As external power ramps up, a Power On Reset (POR) circuit inside the FPGA becomes active. When POR conditions are met, the POR circuit releases an internal reset strobe, allowing the device to begin its initialization process. After CrossLink drives CDONE low, CrossLink enters the memory initialization phase where it clears all of the SRAM memory inside the FPGA. CrossLink remains in initialization state until the CRESETB pin is deasserted or after SSPI/SI[2] C activation code is received.
- After CRESETB goes from low to high, the Configuration Logic puts the device into master auto booting mode where it boots either from the internal NVRAM or an external SPI boot PROM.
- Holding the CRESETB low postpones the master auto booting event and allows the slave configuration ports (Slave SPI or Slave I[2] C) to detect a ‘Slave Active’ condition where the SPI or I[2] C Master sends an Activation Key code to CrossLink. An external SPI Master or I[2] C Master needs to write the Activation Key to the FPGA while CRESETB is held LOW and within 9.5 ms from Vcc min during power up to enter into one of the slave configuration modes.
- Sources should not drive output to CrossLink until configuration has been completed to ensure CrossLink is in a known state.
In addition to the flexible configuration modes, the CrossLink configuration engine supports the following special features:
- TransFR (Transparent Field Reconfiguration) allowing users to update logic in field without interrupting system operation by freezing I/O states during configuration
- Dual-Boot Support for primary and golden bitstreams provides automatic recovery from configuration failures
- Security and One-Time Programmable (OTP) modes protect bitstream integrity and prevent read back
- 64-bit unique TraceID per device
For more information, refer to CrossLink Programming and Configuration Usage Guide (FPGA-TN-02014).
© 2015-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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FPGA-DS-02007-1.8
**CrossLink Family Data Sheet**
## **4. DC and Switching Characteristics**
## **4.1. Absolute Maximum Ratings**
**Table 4.1. Absolute Maximum Ratings[1, 2, 3]**
|**Symbol**<br>~~eC~~|**Parameter**<br>~~eC~~|**Min**<br>~~eC~~|**Max**<br>~~eC~~|**Unit**<br>~~eC~~|
|---|---|---|---|---|
|VCC<br>~~a~~|Core Supply Voltage|–0.5|1.32|V|
|VCCGPLL<br>~~a~~|PLL Supply Voltage|–0.5<br>~~ee~~|1.32<br>~~eee~~|V<br>~~ee~~|
|VCCAUX<br>~~a ee~~<br>~~a~~|Auxiliary Supply Voltage for Bank 1, 2 and NVCM - @ 2.5 V4<br>~~ee~~|–0.5<br>~~ee~~<br>~~ee~~|2.75<br>~~ee~~<br>~~eee~~|V<br>~~ee~~<br>~~ee~~|
||Auxiliary Supply Voltage for Bank 1, 2 and NVCM - @ 3.3 V4<br>~~ee~~<br>~~a~~|–0.5<br>~~ee~~<br>~~ee~~<br>~~a~~|3.63<br>~~ee~~<br>~~eee~~<br>~~a~~|V<br>~~ee~~<br>~~ee~~<br>~~a~~|
|VCCIO<br>~~aCO~~|I/O Driver Supply Voltage for Banks 0, 1, 2<br>~~CO~~|–0.5<br>~~ee ~~<br>~~CO~~|3.63<br> ~~eee ~~<br>~~CO~~|V<br> ~~ee~~<br>~~CO~~|
|—<br>~~a~~|Input or I/O Transient Voltage Applied|–0.5|3.63<br>~~ee~~|V<br>~~ee~~|
|VCCA_DPHYx<br>VCCPLL_DPHY<br>VCCMU_DPHY1<br>~~ee~~<br>~~a~~|MIPI D-PHY Supply Voltages<br>~~ee~~|–0.5<br>~~ee~~|1.32<br>~~ee~~<br>~~ee~~|V<br>~~ee~~<br>~~ee~~|
|—<br>~~a~~<br>~~es G~~|Voltage Applied on MIPI D-PHY Pins<br>~~G~~|–0.5<br>~~G~~|1.32<br>~~ee~~<br>~~G~~|V<br>~~ee~~<br>~~G~~|
|TA<br>~~es G~~|Storage Temperature (Ambient)<br>~~G~~|–65<br>~~G~~|150<br>~~G~~|°C<br>~~G~~|
|TJ<br>~~es G~~<br>~~a~~|Junction Temperature (TJ)<br>~~G~~<br>~~a~~<br>~~a~~|—<br>~~G~~|+125<br>~~G~~|°C<br>~~G~~|
**Notes** :
1. Stress above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. Functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
2. Compliance with the Lattice Thermal Management document is required.
3. All voltages referenced to GND.
4. VCCAUX must be set to 2.5 V when an external I[2] C Master or SPI Master is used to program CrossLink’s NVCM. This restriction is not applicable for read access of the NVCM, such as Self-Download Mode, where the NVCM is already programmed and CrossLink retrieves the bitstream from the NVCM and programs it to the SRAM memory.
## **4.2. Recommended Operating Conditions**
|**Symbol**<br>~~a~~<br>~~es~~|**Parameter**<br>~~a~~<br>~~eC~~|**Min**<br>~~eC~~|**Max**<br>~~eC~~|**Unit**<br>~~eC~~|
|---|---|---|---|---|
|VCC<br>~~a~~<br>~~es~~|Core Supply Voltage<br>~~a~~<br>~~eC~~|1.14<br>~~eC~~|1.26<br>~~eC~~|V<br>~~eC~~|
|VCCGPLL<br>~~es~~<br>~~a~~|PLL Supply Voltage<br>~~eC~~<br>|1.14<br>~~eC~~<br><br>~~ee~~|1.26<br>~~eC~~<br><br>~~ee~~|V<br>~~eC~~<br><br>~~ee~~|
|VCCAUX<br>~~aee~~|Auxiliary Supply Voltage for Bank 1, 2 and NVCM - @ 2.5 V3<br>~~ee~~|2.375<br>~~ee~~<br>~~ee~~|2.625<br>~~ee~~<br>~~ee~~|V<br>~~ee~~<br>~~ee~~|
||Auxiliary Supply Voltage for Bank 1, 2 and NVCM - @ 3.3 V3<br>~~ee~~<br>~~Ge~~|3.135<br>~~ee~~<br>~~ee~~<br>~~Ge~~|3.465<br>~~ee~~<br>~~ee~~<br>~~Ge~~|V<br>~~ee~~<br>~~ee~~<br>~~Ge~~|
|VCCIO0<br>~~a~~<br>~~es~~|I/O Driver Supply Voltage for Bank 0<br>~~CG~~<br>|1.71<br>~~ee ~~<br>~~CG~~<br>|3.465<br> ~~ee ~~<br>~~CG~~<br>|V<br> ~~ee~~<br>~~CG~~<br>|
|VCCIO1/2<br>~~a ~~<br>~~es~~|I/O Driver Supply Voltage for Bank 1, 2<br> ~~CG~~<br>|1.14<br>~~CG~~<br>|3.465<br>~~CG~~<br>|V<br>~~CG~~<br>|
|TJIND<br>~~esa~~|Junction Temperature, Industrial Operation<br>~~a~~|–40<br>~~a~~|100<br>~~a~~|°C<br>~~a~~|
|**D-PHY External Power Supply**<br>~~a~~<br>~~|~~|||||
|VCCA_DPHYx<br>~~a~~|AnalogSupplyVoltage for D-PHY<br>~~a~~<br>~~eC~~|1.14<br>~~a~~<br>~~eC~~|1.26<br>~~a~~<br>~~eC~~|V<br>~~a~~<br>~~eC~~|
|VCCPLL_DPHYx<br>~~a~~<br>~~a~~|PLL Supplyvoltage for D-PHY<br>~~a~~<br>~~eC~~|1.14<br>~~a~~<br>~~eC~~|1.26<br>~~a~~<br>~~eC~~|V<br>~~a~~<br>~~eC~~|
|VCCMU_DPHY1<br>~~a~~|Supplyfor VCCA_DPHY1and VCCPLL_DPHY1on the WLCSP36package|1.14|1.26|V|
**Notes** :
1. For Correct Operation, all supplies must be held in their valid operation range.
2. Like power supplies, must be tied together if they are at the same supply voltage. Follow the noise filtering recommendations in CrossLink Hardware Checklist (FPGA-TN-02013).
3. VCCAUX must be set to 2.5 V when an external I[2] C Master or SPI Master is used to program CrossLink’s NVCM. This restriction is not applicable for read access of the NVCM, such as Self-Download Mode, where the NVCM is already programmed and CrossLink retrieves the bitstream from the NVCM and programs it to the SRAM memory.
© 2015-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02007-1.8
27
**CrossLink Family Data Sheet**
## **4.3. Power Supply Ramp Rates**
Over recommended operating conditions.
## **Table 4.3. Power Supply Ramp Rates***
|**Symbol**|**Parameter**|**Min**|**Max**|**Unit**|
|---|---|---|---|---|
|tRAMP|Power supply ramp rates for all power supplies|0.6|10|V/ms|
***Note** : Assume monotonic ramp rates.
## **4.4. Power-On-Reset Voltage Levels**
Over recommended operating conditions.
## **Table 4.4. Power-On-Reset Voltage Levels[1, 3]**
|**Symbol**|**Parameter**|**Parameter**|**Min**|**Max**|**Unit**|
|---|---|---|---|---|---|
|VPORUP|Power-On-Reset ramp up trip point<br>(Monitoring VCC, VCCIO0, and VCCAUX)|VCC|0.62|0.93|V|
|||VCCIO02|0.87|1.50|V|
|||VCCAUX|0.90|1.53|V|
|VPORDN|Power-On-Reset ramp down trip point<br>(Monitoring VCC, VCCIO0, and VCCAUX)|VCC|—|0.79|V|
|||VCCIO02|—|1.50|V|
|||VCCAUX|—|1.53|V|
## **Notes:**
1. These POR ramp up trip points are only provided for guidance. Device operation is only characterized for power supply voltages specified under recommended operating conditions.
2. Only VCCIO0 (Config Bank) has a Power-On-Reset ramp up trip point. All other VCCIOs do not have Power-On-Reset ramp up detection.
3. Configuration starts after VCC, VCCIO0 and VCCAUX reach VPORUP. For details, see tCONFIGURATION time in Table 4.21 on page 44.
© 2015-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
28
FPGA-DS-02007-1.8
**CrossLink Family Data Sheet**
## **4.5. Power Supply Sequence Requirements**
CrossLink includes the following supplies:
- VCC – Core supply
- VCCGPLL – PLL supply
- VCCAUX – Auxiliary supply
- VCCIOX (includes VCCIO0, VCCIO1 and VCCIO2) – Bank I/O driver supply
- VCCA_DPHYX (includes VCCA_DPHY0 and VCCA_DPHY1) – D-PHY analog supply
- VCCPLL_DPHYX (includes VCCPLL_DPHY0 and VCCPLL_DPHY1) – D-PHY PLL supply
- VCCMU_DPHY1 – VCCA_DPHY1 and VCCPLL_DPHY1 supplies for WLCSP36 package
It is recommended to bring up power supplies in the following order. Note that there is no specific timing delay between the power supplies.
## **Power Supply Power-Up Sequence**
1. VCCIOX supplies should be powered-up first, before the other supplies. VCCIOx must reach a level of 0.6 V before any subsequent power supplies are ramped.
2. VCC/VCCGPLL/VCCA_DPHYX/VCCPLL_DPHYX/VCCMU_DPHY1 should be powered-up next, after VCCIOX has reached a level of 0.6 V or higher.
3. VCCAUX must be powered up at the same time or after VCC. If VCC and VCCAUX are powered up concurrently, at no point can the VCCAUX supply be higher than VCC until the point when VCC has reached the minimum operating voltage.
## **Power Supply Power-Down Sequence**
There are no sequencing requirements for the Power-Down of the device. In the event that any supply is powered down below the POR trip point, then all supplies should be powered down before the device can be powered up following the Power Supply Power-Up Sequence.
## **4.6. ESD Performance**
Refer to the LIFMD Product Family Qualification Summary for complete qualification data, including ESD performance.
© 2015-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02007-1.8
29
**CrossLink Family Data Sheet**
## **4.7. DC Electrical Characteristics**
Over recommended operating conditions.
**Table 4.5. DC Electrical Characteristics**
|**Symbol**<br>~~a ~~|**Parameter**<br> ~~Ge~~|**Condition**<br>~~Ge~~|**Min**<br>~~Ge~~|**Typ**<br>~~Ge~~|**Max**<br>~~Ge~~|**Unit**<br>~~Ge~~|
|---|---|---|---|---|---|---|
|IIL, IIH1, 4, 5<br>~~a ~~<br>~~pf~~|Input or I/O Leakage<br> ~~GO~~<br>~~pf~~|0 ≤ VIN≤ VCCIO<br>~~GO~~<br>~~se~~|−10<br>~~GO~~<br>~~se~~|—<br>~~GO~~<br>~~se~~|+10<br>~~GO~~<br>~~se~~|µA<br>~~GO~~<br>~~se~~|
|IPU4<br>~~pf~~|Internal Pull-Up Current<br>~~pf~~|VCCIO= 1.8 V between 0 ≤ VIN≤ 0.65 * VCCIO<br>~~se~~<br>~~er~~|−3<br>~~se~~<br>~~er~~|—<br>~~se~~<br>~~er~~|−31<br>~~se~~<br>~~er~~|µA<br>~~se~~<br>~~er~~|
|||VCCIO= 2.5 V between 0 ≤ VIN≤ 0.65 * VCCIO<br>~~se~~<br>~~er~~|−8<br>~~se~~<br>~~er~~|—<br>~~se~~<br>~~er~~|−72<br>~~se~~<br>~~er~~|µA<br>~~se~~<br>~~er~~|
|||VCCIO= 3.3 V between 0 ≤ VIN≤ 0.65 * VCCIO<br>~~se~~<br>~~er~~<br>~~po~~|−11<br>~~se~~<br>~~er~~<br>~~po~~|—<br>~~se~~<br>~~er~~<br>~~po~~|−128<br>~~se~~<br>~~er~~<br>~~po~~|µA<br>~~se~~<br>~~er~~<br>~~po~~|
|C12<br>~~pf~~<br>~~a~~|I/O Capacitance2<br>~~pf~~<br>~~ee~~|VCCIO= 3.3 V, 2.5 V, 1.8 V, 1.2 V,<br>VCC= 1.2 V, VIO= 0 to VIH(MAX)<br>~~se~~<br>~~ee~~|—<br>~~se~~<br>~~ee~~|6<br>~~se~~<br>~~ee~~|—<br>~~se~~<br>~~ee~~|pF<br>~~se~~<br>~~ee~~|
|C22<br>~~a~~|Dedicated Input<br>Capacitance2|VCCIO= 3.3 V, 2.5 V, 1.8 V, 1.2 V,<br>VCC= 1.2 V, VIO= 0 to VIH(MAX)|—|6|—|pF|
|C32<br>~~a~~|MIPI D-PHY High Speed<br>I/O Capacitance|VCCIO= 2.5V,VCC= 1.2V, VCC*_DPHY= 1.2V , VIO<br>= 0 to VIH(MAX)|—|5|—|pF|
|VHYST3<br>~~a~~|Hysteresis for Single-<br>Ended Inputs|VCCIO= 3.3 V, 2.5 V, 1.8 V<br>VCC= 1.2 V, VIO= 0 to VIH(MAX)|—|200|—|mV|
## **Notes:**
1. Input or I/O leakage current is measured with the pin configured as an input or as an I/O with the output driver tristated. It is not measured with the output driver active. Bus maintenance circuits are disabled.
2. TA = 25[o] C, f = 1.0 MHz.
3. Hysteresis is not available for VCCIO = 1.2 V.
4. Weak pull-up setting. Programmable pull-up resistors on Bank 0 will see higher current. Refer to CrossLink sysI/O Usage Guide (FPGA-TN-02016) for details on programmable pull-up resistors.
5. Input pins are clamped to VCCIO and GND by a diode. When input is higher than VCCIO, or lower than GND, the Input Leakage current will be higher than the IIL and IIH.
© 2015-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
30
FPGA-DS-02007-1.8
**CrossLink Family Data Sheet**
## **4.8. CrossLink Supply Current**
Over recommended operating conditions.
**Table 4.6. CrossLink Supply Current**
|**Symbol**<br>~~a a~~|**Parameter**<br>~~a~~|**Typ**<br>~~a~~|**Unit**<br>~~a~~|
|---|---|---|---|
|**Normal Operation1**<br>~~PR~~||||
|ICC<br>~~a~~|Vcc Power Supply Current|7|mA|
|ICCPLL<br>~~a~~<br>~~a~~|PLL Power Supply Current<br>|50<br>|µA<br>|
|ICCAUX<br>~~ee~~|Auxiliary Power Supply Current for Bank 1, 2 and NVCM Programming Supply Current<br>~~ee~~|3<br>~~ee~~|mA<br>~~ee~~|
|ICCIOx<br>~~a~~|Bank x Power Supply Current (per Bank)|60|µA|
|ICCA_DPHYx<br>~~a~~|VCCA_DPHYxPower Supply Current|8.5|mA|
|ICCPLL_DPHYx<br>~~a~~|VCCPLL_DPHYxPower Supply Current|1.5|mA|
|ICCMLL_DPHYx<br>~~a~~|VCCA_DPHY1& VCCPLL_DPHY1Power Supply Operation Current for WLCSP36 Package<br>|10<br>|mA<br>|
|**Standby Current2**<br>~~pe~~||||
|ICC_STDBY<br>~~a~~|Vcc Power Supply Standby Current|4|mA|
|ICCPLL_STDBY<br>~~a~~<br>~~a~~<br>~~ee~~|PLL Power Supply Standby Current|10|µA|
|ICCAUX_STDBY<br>~~ee~~<br>~~es~~|Auxiliary Power Supply Current for Bank 1, 2 and NVCM Programming Supply Standby Current|0.2|mA|
|ICCIOx_STDBY<br>~~ee~~<br>~~es~~|Bank Power Supply Standby Current (per Bank)|6|µA|
|ICCA_DPHYx_STDBY<br>~~es~~<br>~~a~~<br>~~es~~|VCCA_DPHYxPower Supply Standby Current|6|µA|
|ICCPLL_DPHYx_STDBY<br>~~es~~<br>~~ee~~|VCCPLL_DPHYxPower Supply Standby Current<br>|4<br>|µA<br>|
|ICCMLL_DPHYx_STDBY<br>~~es~~<br>~~ee~~|VCCA_DPHY1& VCCPLL_DPHY1Power Supply Static Current for WLCSP36 Package<br>|10<br>|µA<br>|
|**Sleep/Power Down Mode Current3**<br>~~ee|~~||||
|ICC_SLEEP<br>~~a~~|Vcc Power Supply Sleep Current<br>~~a~~<br>~~a~~|0.2<br>~~a~~<br>~~a~~|mA<br>~~a~~<br>~~a~~|
|ICCPLL_SLEEP<br>~~a~~<br>~~es~~|PLL Power Supply Current|10|µA|
|ICCAUX_SLEEP<br>~~es~~|Auxiliary Power Supply Current for Bank 1, 2 and NVCM Programming Supply Current|20|µA|
|ICCIOx_SLEEP<br>~~es~~<br>~~a~~|Bank Power Supply Current (per Bank)<br>|6<br>|µA<br>|
|ICCA_DPHY_SLEEP<br>~~OO~~|VCCA_DPHYxPower Supply Sleep Current<br>~~OO~~|6<br>~~OO~~|µA<br>~~OO~~|
|ICCPLL_DPHY_SLEEP<br>~~OO~~<br>~~a~~<br>~~es~~|VCCPLL_DPHYxPower Supply Sleep Current<br>~~OO~~|4<br>~~OO~~|µA<br>~~OO~~|
|ICCAMLL_DPHYx_SLEEP<br>~~es~~|VCCA_DPHY1& VCCPLL_DPHY1Power Supply Static Current for WLCSP36 Package|10|µA|
1. Normal Operation
- 2:1 MIPI CSI-2 Image Sensor Aggregator Bridge design under the following conditions:
- a. TJ = 25 °C, all power supplies at nominal voltages.
- b. Typical processed device in csfBGA81 package.
- c. To determine power for all other applications and operating conditions, use Power Calculator in Lattice Diamond design software
2. Standby Operation
- A typically processed device in csfBGA81 package with “blank” pattern programmed. A “blank” pattern configures the part to the following conditions:
- a. All outputs are tri-stated, all inputs are held at either VCCIO, or GND.
- b. All clock inputs are at 0 MHz.
- c. TJ = 25 °C, all power supplies at nominal voltages.
- d. No pull-ups on I/O.
3. Sleep/Power Down Mode
- 2:1 MIPI CSI-2 Image Sensor Aggregator Bridge design under the following conditions:
- a. Design is put into Sleep/Power Down Mode with user logic powers down D-PHY, and enters into Sleep Mode in PMU.
- b. TJ = 25 °C, all power supplies at nominal voltages.
- c. Typical processed device in csfBGA81 package.
4. For ucfBGA64 package
- a. VCCA_DPHY0 and VCCA_DPHY1 are tied together as VCCA_DPHYx.
- b. VCCPLL_DPHY0 and VCCPLL_DPHY1 are tied together as VCCPLL_DPHYx.
© 2015-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02007-1.8
31
**CrossLink Family Data Sheet**
## 5. For WLCS36 package
- a. VCCGPLL and VCCIO1 (Bank 1) are tied together to VCC.
- b. VCCPLL_DPHY1 and VCCA_DPHY1 are tied together as VCCMU_DPHY1.
6. To determine the CrossLink start-up peak current, use the Power Calculator tool in the Lattice Diamond design software.
## **4.9. Power Management Unit (PMU) Timing**
Over recommended operating conditions.
## **Table 4.7. PMU Timing***
|**Symbol**|**Parameter**|**Device**|**Max**|**Unit**|
|---|---|---|---|---|
|tPMUWAKE|Time for PMU to wake from Sleep mode|All Devices|0.5|ms|
***Note** : For details on PMU usage, refer to Power Management and Calculation for CrossLink Devices (FPGA-TN-02018).
## **4.10. sysI/O Recommended Operating Conditions**
Over recommended operating conditions.
**Table 4.8. sysI/O Recommended Operating Conditions[1]**
|**Standard**<br>~~—__—————E~~<br>~~po~~<br>~~a~~|**VCCIO**<br>~~—__—————E~~<br>~~po~~|**VCCIO**<br>~~—__—————E~~<br>~~po~~|**VCCIO**<br>~~—__—————E~~<br>~~po~~|
|---|---|---|---|
||**Min**<br>~~—__—————E~~<br>~~po~~|**Typ**<br>~~—__—————E~~|**Max**<br>~~—__—————E~~|
|LVCMOS33/LVTTL33<br>~~—__—————E~~<br>~~po~~<br>~~a~~|3.135<br>~~—__—————E~~<br>~~po~~<br>~~GO~~|3.30<br>~~—__—————E~~<br>~~GO~~|3.465<br>~~—__—————E~~|
|LVCMOS25<br>~~po~~<br>~~a~~<br>~~a~~|2.375<br>~~po~~<br>~~GO~~<br>~~Ge~~|2.50<br>~~GO~~<br>~~Ge~~|2.625|
|LVCMOS18<br>~~eG~~<br>~~ee~~|1.710<br>~~eG~~<br>~~eG~~|1.80<br>~~eG~~<br>~~eG~~|1.890<br>~~eG~~|
|LVCMOS12 (Output only)2<br>~~ee~~<br>~~pO~~|1.140<br>~~eG~~<br>~~pO~~|1.20<br>~~eG~~|1.260|
|subLVDS (Input only)<br>~~ee~~<br>~~pO~~<br>~~——————————~~<br>~~oe~~|1.710<br>~~eG~~<br>~~pO~~<br>~~——————————~~|1.80<br>~~eG~~<br>~~——————————~~|1.890<br>~~——————————~~|
||2.375<br>~~pO~~<br>~~——————————~~|2.50<br>~~——————————~~|2.625<br>~~——————————~~|
||3.135<br>~~——————————~~<br>~~**eG**~~<br>|3.30<br>~~——————————~~<br>~~**eG**~~<br>|3.465<br>~~——————————~~<br>~~**eG**~~<br>|
|SLVS200 (Input only)3<br>~~oe~~<br>~~SS~~|1.140<br>~~**eG**~~<br>|1.20<br>~~**eG**~~<br>|1.260<br>~~**eG**~~<br>|
||1.710<br>~~**eG**~~<br>~~eG~~|1.80<br>~~**eG**~~<br>~~eG~~|1.890<br>~~**eG**~~<br>~~eG~~|
||2.375<br>~~**eG**~~<br><br>~~Ge~~|2.50<br>~~**eG**~~<br><br>~~Ge~~|2.625<br>~~**eG**~~<br><br>~~Ge~~|
||3.135<br>~~**eG**~~<br><br>~~Ge~~<br>~~SS~~|3.30<br>~~**eG**~~<br><br>~~Ge~~|3.465<br>~~**eG**~~<br><br>~~Ge~~|
|LVDS (Input only)<br>~~oe~~<br>~~SS~~|1.710<br>~~**eG**~~<br><br>~~SS~~|1.80<br>~~**eG**~~<br>|1.890<br>~~**eG**~~<br>|
||2.375<br>~~SS~~<br>~~es~~|2.50<br>~~es~~|2.625<br>~~es~~|
||3.135<br>~~SS~~<br>~~es~~<br>~~Oe~~|3.30<br>~~es~~<br>~~Oe~~|3.465<br>~~es~~<br>~~Oe~~|
|LVDS (Output only)<br>~~SS~~<br>~~a~~|2.375<br>~~SS~~<br>~~a~~|2.50<br>~~a~~<br>~~G~~|2.625<br>~~a~~|
|MIPI (Input only)<br>~~a~~<br>~~A~~|1.140<br>~~a~~<br>~~A~~|1.20<br>~~a~~<br>~~A~~<br>~~G~~|1.260<br>~~a~~<br>~~A~~|
2. For VCCIO1 and VCCIO2 only.
3. For SLVS200/MIPI interface I/O placement, see the Programmable I/O Banks section.
© 2015-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
32
FPGA-DS-02007-1.8
**CrossLink Family Data Sheet**
## **4.11. sysI/O Single-Ended DC Electrical Characteristics**
**Table 4.9. sysI/O Single-Ended DC Electrical Characteristics[1]**
|**Input/Output**<br>**Standard**<br>~~ese~~<br>~~a~~|**VIL**<br>~~ese~~|**VIL**<br>~~ese~~|**VIH**<br>~~ese~~|**VIH**<br>~~ese~~|**VOL Max**<br>**(V)**<br>~~ese~~|**VOH Min**<br>**(V)**<br>~~ese~~<br>~~ee~~|**IOL**<br> **(mA)**<br>~~ese~~<br>~~eee~~|**IOH**<br>**(mA)**<br>~~ese~~<br>~~eee~~|
|---|---|---|---|---|---|---|---|---|
||**Min (V)**<br>~~ese~~|**Max (V)**<br>~~ese~~|**Min (V)**<br>~~ese~~|**Max (V)**<br>~~ese~~|||||
|LVCMOS33/<br>LVTTL33<br>~~ee~~<br>~~a~~<br>~~a~~|–0.3<br>~~ee~~<br>|0.8<br>~~ee~~<br>~~ee~~<br>|2.0<br>~~ee~~<br>~~ee~~<br>|VCCIO+0.2<br>~~ee~~<br>~~ee~~<br>|0.40<br>~~ee~~|VCCIO− 0.4<br>~~ee~~<br>~~ee~~|8<br>~~ee~~<br>~~eee~~|–8<br>~~ee~~<br>~~eee~~|
||||||0.20<br>~~ee~~<br>~~ee~~<br>|VCCIO− 0.2<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>|0.1<br>~~ee~~<br>~~eee~~<br>~~ee~~<br>|–0.1<br>~~ee~~<br>~~eee~~<br>~~ee~~<br>|
|LVCMOS25<br>~~a~~<br>~~a~~|–0.3<br>|0.7<br>~~ee~~<br>|1.7<br>~~ee~~<br>|VCCIO+0.2<br>~~ee~~<br>|0.40<br>~~ee~~<br>|VCCIO− 0.4<br>~~ee~~<br>~~ee~~<br>|6<br>~~eee~~<br>~~ee~~<br>|–6<br>~~eee~~<br>~~ee~~<br>|
||||||0.20<br>~~ee~~<br>|VCCIO− 0.2<br>~~ee ~~<br>~~ee~~<br>|0.1<br> ~~eee~~<br>~~ee~~<br><br>~~eee~~|–0.1<br>~~eee~~<br>~~ee~~<br><br>~~eee~~|
|LVCMOS18<br>~~a ee~~|–0.3<br>~~ee~~|0.35 VCCIO<br>~~ee~~<br>~~ee~~|0.67 VCCIO<br>~~ee~~<br>~~ee~~|VCCIO+0.2<br>~~ee ~~<br>~~ee~~|0.40<br>~~ee~~<br>~~ee~~|VCCIO− 0.4<br>~~ee~~<br>~~ee~~|4<br>~~ee~~<br>~~ee~~<br>~~eee~~|–4<br>~~ee~~<br>~~ee~~<br>~~eee~~|
||||||0.20<br> ~~ee~~<br>~~ee~~|VCCIO− 0.2<br>~~ee ~~<br>~~ee~~|0.1<br> ~~ee~~<br>~~ee~~<br>~~eee~~|–0.1<br>~~ee~~<br>~~ee~~<br>~~eee~~|
|LVCMOS122<br>(Output only)<br>~~et~~|—<br>~~et~~|—<br>~~et~~|—<br>~~et~~|—<br>~~et~~|0.40<br>~~et~~|VCCIO− 0.4<br>~~et~~|2<br>~~eee~~<br>~~et~~|–2<br>~~eee~~<br>~~et~~|
||||||0.20<br>~~et~~|VCCIO− 0.2<br>~~et~~|0.1<br>~~et~~|–0.1<br>~~et~~|
**Notes:**
1. VCCIO in the table follows the VCCIO power rail setting of the respective bank.
2. For VCCIO1 and VCCIO2 only.
## **4.12. sysI/O Differential Electrical Characteristics**
## **4.12.1. LVDS/subLVDS/SLVS200**
Over recommended operating conditions.
**Table 4.10. LVDS/subLVDS1/SLVS200[1, 2]**
|**Parameter**<br>~~a~~|**Description**<br>~~a~~|**Test Conditions**<br>~~a~~|**Min**<br>~~a~~|**Typ**<br>~~a~~|**Max**<br>~~a~~|**Unit**<br>~~a~~|
|---|---|---|---|---|---|---|
|VINP, VINN<br>~~a~~|Input Voltage<br>~~a~~|—<br>~~a~~|0.00<br>~~a~~|—<br>~~a~~|2.40<br>~~a~~|V<br>~~a~~|
|VCM<br>~~a~~|Input Common Mode Voltage<br>~~a~~|Half the sum of the two inputs<br>~~a~~|0.05<br>~~a~~|—<br>~~a~~|2.35<br>~~a~~|V<br>~~a~~|
|VTHD(LVDS)<br>~~a~~|Differential Input Threshold<br>~~a~~|ǀVINP- VINNǀ<br>~~a~~|100<br>~~a~~|—<br>~~a~~|—<br>~~a~~|mV<br>~~a~~|
|VTHD(subLVDS)<br>~~a~~|Differential Input Threshold<br>~~a~~|ǀVINP- VINNǀ<br>~~a~~<br>~~ee~~|90<br>~~a~~<br>~~ee~~|—<br>~~a~~<br>~~ee~~|—<br>~~a~~|mV<br>~~a~~|
|VTHD(SLVS200)<br>~~a~~<br>~~ee~~|Differential Input Threshold<br>~~a~~<br>~~ee~~|ǀVINP- VINNǀ<br>~~a~~<br>~~ee~~<br>~~ee~~|70<br>~~a~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|—<br>~~a~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|—<br>~~a~~<br>~~ee~~<br>~~ee~~|mV<br>~~a~~<br>~~ee~~<br>~~ee~~|
|IIN<br>~~ee~~<br>~~ee~~|Input Current<br>~~ee~~<br>~~ee~~|Normal Mode<br>~~ee~~<br>~~ee~~<br>~~ee~~|−10<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|10<br>~~ee~~<br>~~ee~~<br>~~ee~~|µA<br>~~ee~~<br>~~ee~~<br>~~ee~~|
|||Standby Mode<br>~~ee ~~<br>~~ee~~|−10<br> ~~ee~~<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~<br>~~ee~~|10<br>~~ee~~<br>~~ee~~|µA<br>~~ee~~<br>~~ee~~|
|VOH<br>~~a~~|Output High Voltage for VOPor VOM<br>~~a~~|RT = 100 Ω<br>~~a~~|—<br>~~ee~~<br>~~a~~|1.43<br>~~ee~~<br>~~a~~|1.60<br>~~ee~~<br>~~a~~|V<br>~~ee~~<br>~~a~~|
|VOL<br>~~a~~<br>~~a~~|Output Low Voltage for VOPor VOM<br>~~a~~<br>~~a~~|RT = 100 Ω<br>~~a~~<br>~~a~~|0.90<br>~~a~~<br>~~a~~|1.08<br>~~a~~<br>~~a~~|—<br>~~a~~<br>~~a~~|V<br>~~a~~<br>~~a~~|
|VOD<br>~~a~~|Output Voltage Differential<br>~~a~~||VOP- VOM|, RT = 100 Ω<br>~~a~~|250<br>~~a~~|350<br>~~a~~|450<br>~~a~~|mV<br>~~a~~|
|∆VOD<br>~~a~~<br>~~a~~|Change in VODbetween High and<br>Low<br>~~a~~<br>~~a~~|—<br>~~a~~<br>~~a~~|—<br>~~a~~<br>~~a~~|—<br>~~a~~<br>~~a~~|50<br>~~a~~<br>~~a~~|mV<br>~~a~~<br>~~a~~|
|VOS<br>~~a~~<br>~~a~~|Output Voltage Offset (Common<br>Mode Voltage)<br>~~a~~<br>~~a~~|(VOP+ VOM)/2, RT = 100 Ω<br>~~a~~<br>~~a~~|1.125<br>~~a~~<br>~~a~~|1.250<br>~~a~~<br>~~a~~|1.375<br>~~a~~<br>~~a~~|V<br>~~a~~<br>~~a~~|
|∆VOS<br>~~a~~<br>~~a~~|Change in VOSbetween H and L<br>~~a~~<br>~~a~~<br>~~ee~~|—<br>~~a~~<br>~~a~~<br>~~ee~~|—<br>~~a~~<br>~~a~~|—<br>~~a~~<br>~~a~~|50<br>~~a~~<br>~~a~~|mV<br>~~a~~<br>~~a~~|
|ISAB<br>~~a~~<br>~~a~~|Output Short Circuit Current<br>~~a~~<br>~~a~~<br>~~ee~~|VOD= 0 V driver outputs shorted to<br>each other<br>~~a~~<br>~~a~~<br>~~ee~~|—<br>~~a~~<br>~~a~~|—<br>~~a~~<br>~~a~~|12<br>~~a~~<br>~~a~~|mA<br>~~a~~<br>~~a~~|
2. For SLVS200/MIPI interface I/O placement, see the Programmable I/O Banks section.
© 2015-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02007-1.8
33
**CrossLink Family Data Sheet**
## **4.12.2. Hardened MIPI D-PHY I/Os**
Over recommended operating conditions.
**Table 4.11. MIPI D-PHY**
|**Symbol**<br>~~a~~|**Description**<br>|**Min**<br>|**Typ**<br>|**Max**<br>|**Unit**<br>|
|---|---|---|---|---|---|
|**Receiver**<br>~~apT~~||||||
|**High Speed**<br>~~pT~~<br>~~a~~||||||
|VCMRX<br>~~pT~~<br>~~a~~<br>~~a~~|Common-Mode Voltage HS Receive Mode<br>~~pT~~<br>|70<br>~~pT~~<br>|—<br>~~pT~~<br>|330<br>~~pT~~<br>|mV<br>~~pT~~<br>|
|VIDTH<br>~~a~~<br>~~a~~|Differential Input High Threshold<br>|—<br>|—<br>|70<br>|mV<br>|
|VIDTL<br>~~aI~~<br>~~es~~|Differential Input Low Threshold<br>~~I~~|−70<br>~~I~~|—<br>~~I~~|—<br>~~I~~|mV<br>~~I~~|
|VIHHS<br>~~I~~<br>~~es~~<br>~~es~~|Single-ended input High Voltage<br>~~I~~|—<br>~~I~~|—<br>~~I~~|460<br>~~I~~|mV<br>~~I~~|
|VILHS<br>~~es~~<br>~~es~~|Single-ended Input Low Voltage|−40|—|—|mV|
|VTERM-EN<br>~~es~~<br>~~a~~|Single-ended Threshold for HS Termination Enable<br>|—<br>|—<br>|450<br>|mV<br>|
|ZID<br>~~Re~~|Differential Input Impedance<br>~~Re~~|80<br>~~Re~~|100<br>~~Re~~|125<br>~~Re~~|Ω<br>~~Re~~|
|**Low Power**<br>~~pT~~||||||
|VIH<br>~~a~~<br>~~es~~|Logic 1 Input Voltage|880|—|—|mV|
|VIL<br>~~es~~<br>~~es~~|Logic 0 Input Voltage, not in ULP State|—|—|550|mV|
|VIL-ULPS<br>~~es~~<br>~~es~~<br>~~es~~|Logic 0 Input Voltage, in ULP State|—|—|300|mV|
|VHYST<br>~~es~~<br>~~es~~|Input Hysteresis|25|—|—|mV|
|**Transmitter**<br>~~es~~<br>~~pT~~||||||
|**High Speed**<br>~~pT~~<br>~~pT~~||||||
|VCMTX<br>~~a~~|HS Transmit Static Common Mode Voltage|150|200|250|mV|
|VOD<br>~~a~~<br>~~a~~<br>~~a~~|HS Transmit Differential Voltage|140|200|270|mV|
|VOHHS<br>~~a~~|HS Single-ended Output High Voltage|—|—|360|mV|
|ZOS<br>~~a~~<br>~~a~~<br>~~ee~~|Single-ended Output Impedance|40|50|62.5|Ω|
|ΔZOS<br>~~ee~~|Single-ended Output Impedance Mismatch|—|—|10|%|
|**Low Power**<br>~~ee~~<br>~~pT~~<br>~~a~~||||||
|VOH<br>~~pT~~<br>~~a~~<br>~~es~~|Output High Voltage<br>~~pT~~|1.1<br>~~pT~~|1.2<br>~~pT~~|1.3<br>~~pT~~|V<br>~~pT~~|
|VOL<br>~~a~~<br>~~es~~<br>~~es~~|Output Low Voltage|−50|—|50|mV|
|ZOLP<br>~~es~~<br>~~es~~|Output Impedance in LP Mode|110|—|—|Ω|
© 2015-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
34
FPGA-DS-02007-1.8
**CrossLink Family Data Sheet**
## **4.13. CrossLink Maximum General Purpose I/O Buffer Speed**
Over recommended operating conditions.
**Table 4.12. CrossLink Maximum I/O Buffer Speed**
|**Buffer**<br>~~sn~~|**Description**<br>~~sn~~|**Max**<br>~~sn~~|**Unit**<br>~~sn~~|
|---|---|---|---|
|**Maximum Input Frequency**<br>~~pT~~<br>~~poPR}~~||||
|LVDS25<br>~~po~~|LVDS, VCCIO= 2.5 V, csfBGA81, ctfBGA80, ckfBGA80,<br>ucfBGA64packages<br>~~PR}~~|600<br>~~PR}~~|MHz<br>~~PR}~~|
||LVDS, VCCIO= 2.5 V, WLCSP36 package<br>~~PR}~~|500<br>~~PR}~~|MHz<br>~~PR}~~|
|subLVDS<br>~~po ~~<br>~~————EEE~~|subLVDS, VCCIO= 2.5 V, csfBGA81, ctfBGA80, ckfBGA80,<br>ucfBGA64packages<br> ~~PR}~~<br>~~————EEE~~|600<br>~~PR}~~<br>~~————EEE~~|MHz<br>~~PR}~~<br>~~————EEE~~|
||subLVDS, VCCIO= 2.5 V, WLCSP36 package<br>~~————EEE~~<br>~~a~~|500<br>~~————EEE~~<br>~~a~~|MHz<br>~~————EEE~~<br>~~a~~|
|MIPI D-PHY (HS)6, 7<br>~~—~~<br>~~———————~~|MIPI D-PHY, csfBGA81, ctfBGA80, ckfBGA80, ucfBGA64packages<br>~~I~~|600<br>~~I~~|MHz<br>~~I~~|
||MIPI D-PHY, WLCSP36package<br>~~I~~<br>~~———————~~|500<br>~~I~~<br>~~———————~~|MHz<br>~~I~~<br>~~———————~~|
|MIPI D-PHY (LP)7<br>~~———————~~|MIPI D-PHY, csfBGA81, ctfBGA80, ckfBGA80, ucfBGA64packages<br>~~———————~~|5<br>~~———————~~|MHz<br>~~———————~~|
||MIPI D-PHY, WLCSP36package<br>~~———————~~<br>~~a~~|5<br>~~———————~~<br>~~a~~|MHz<br>~~———————~~<br>~~a~~|
|SLVS2007<br>~~———————~~<br>~~ee~~|SLVS200, VCCIO=2.5 V, csfBGA81, ctfBGA80, ckfBGA80,<br>ucfBGA64packages<br>~~———————~~<br>~~a~~<br>~~ee~~|600<br>~~———————~~<br>~~a~~<br>~~ee~~|MHz<br>~~———————~~<br>~~a~~<br>~~ee~~|
||SLVS200, VCCIO=2.5 V, WLCSP36package<br>~~ee~~<br>~~a~~|500<br>~~ee~~<br>~~a~~|MHz<br>~~ee~~<br>~~a~~|
|LVCMOS33/LVTTL33<br>~~ee~~|LVCMOS/LVTTL, VCCIO= 3.3 V<br>~~ee~~|300<br>~~ee~~|MHz<br>~~ee~~|
|LVCMOS25D<br>~~a~~|Differential LVCMOS, VCCIO= 2.5 V|300|MHz|
|LVCMOS25<br>~~es~~|LVCMOS, VCCIO= 2.5 V<br>~~es~~|300<br>~~es~~|MHz<br>~~es~~|
|LVCMOS18<br>~~es~~<br>~~a~~|LVCMOS, VCCIO= 1.8 V<br>~~es~~|155<br>~~es~~|MHz<br>~~es~~|
|**Maximum Output Frequency**<br>~~pT~~||||
|LVDS25<br>~~a ~~|LVDS, VCCIO= 2.5 V, csfBGA81, ctfBGA80, ckfBGA80,<br>ucfBGA64packages<br>~~a~~|600|MHz|
||LVDS, VCCIO= 2.5 V, WLCSP36 package<br> ~~a~~<br>~~es~~|500<br>~~es~~|MHz<br>~~es~~|
|LVCMOS33/LVTTL33<br>~~Rs~~|LVCMOS/LVTTL, VCCIO= 3.3 V<br>~~Rs~~|300<br>~~Rs~~|MHz<br>~~Rs~~|
|LVTTL33D<br>~~Rs~~<br>~~es~~|Differential LVTTL, VCCIO= 3.3 V<br>~~Rs~~<br>~~es~~|300<br>~~Rs~~<br>~~es~~|MHz<br>~~Rs~~<br>~~es~~|
|LVCMOS33D<br>~~De~~|Differential LVCMOS, 3.3 V<br>~~De~~|300<br>~~De~~|MHz<br>~~De~~|
|LVCMOS25<br>~~a~~|LVCMOS, 2.5 V|300|MHz|
|LVCMOS25D<br>~~a~~<br>~~a~~|Differential LVCMOS, 2.5 V|300|MHz|
|LVCMOS18<br>~~pT~~<br>~~a~~|LVCMOS, 1.8 V<br>~~pT~~|155<br>~~pT~~|MHz<br>~~pT~~|
|LVCMOS12<br>~~pT~~<br>~~a~~|LVCMOS, VCCIO1/2= 1.2 V<br>~~pT~~|70<br>~~pT~~|MHz<br>~~pT~~|
**Notes** :
1. These maximum speeds are characterized but not tested on every device.
2. Maximum I/O speed for differential output standards emulated with resistors depends on the layout.
3. LVCMOS timing is measured with the load specified in Table 4.22.
4. Actual system operation may vary depending on user logic implementation.
5. Maximum data rate equals two times the clock rate when utilizing DDR.
6. This is the maximum MIPI D-PHY input rate on the programmable I/O banks 1 and 2. The hardened MIPI D-PHY input and output rates are described in Hardened MIPI D-PHY Performance section. For SLVS200/MIPI interface I/O placement, see the Programmable I/O Banks section.
7. Implement the following guidelines for I/O placement when MIPI Rx inputs are present on the programmable I/O banks to ensure optimal performance:
||Bank 1|Bank 2|
|---|---|---|
|SLVS200/MIPI Rx on Bank 1|No LVCMOS Outputs|No LVCMOS Outputs|
|SLVS200/MIPI Rx on Bank 2|No LVCMOS Outputs|No LVCMOS Outputs|
|SLVS200/MIPI Rx on Bank 1 and Bank 2|No LVCMOS Outputs|No LVCMOS Outputs|
© 2015-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02007-1.8
35
**CrossLink Family Data Sheet**
- The Diamond Software PAR Design Strategy setting of LVCMOS12_18_ONLY (default) allows outputs as long as they are LVCMOS12 or LVCMOS18.
- The Diamond Software PAR Design Strategy setting of LVCMOS_NOT_PERMITTED will cause an error in PAR regarding IO placement if there are any outputs in Bank 1 or Bank 2 when a MIPI Receiver interface is present.
## **4.14. CrossLink External Switching Characteristics**
Over recommended operating conditions.
|**Parameter**<br>~~ee~~|**Description**|**Conditions**<br>~~Pp~~|**–6**<br>~~Pp~~|**–6**<br>~~Pp~~|**Unit**|
|---|---|---|---|---|---|
||||**Min**<br>~~Pp~~|**Max**||
|**Clocks**<br>~~Pp~~<br>~~ee~~<br>~~pe~~||||||
|**Primary Clock**<br>~~Pp~~<br>~~ee~~||||||
|fMAX_PRI<br>~~a~~|Frequency for Primary Clock<br>Tree|—|—|150|MHz|
|tW_PRI<br>~~a~~|Clock Pulse Width for Primary<br>Clock|—|0.8|—|ns|
|tSKEW_PRI<br>~~a~~|Primary Clock Skew Within a<br>Clock|—|—|450|ps|
|**Edge Clock**<br>~~eeOO~~<br>~~ee A~~||||||
|fMAX_EDGE<br>~~ee~~<br>~~ee A~~|Frequencyfor Edge Clock Tree<br>~~OO~~<br>~~A~~|—<br>~~OO~~|—<br>~~OO~~|600<br>~~OO~~|MHz<br>~~OO~~|
|tW_EDGE<br>~~ee~~<br>~~ee A~~|Clock Pulse Width for Edge<br>Clock<br>~~OO~~<br>~~A~~|—<br>~~OO~~|0.783<br>~~OO~~|—<br>~~OO~~|ns<br>~~OO~~|
|tSKEW_EDGE<br>~~ee A~~<br>~~a ~~|Edge Clock Skew Within a Bank<br>~~A~~<br> ~~CO~~|—<br>~~CO~~|—<br>~~CO~~|120<br>~~CO~~|ps<br>~~CO~~|
|**Generic DDR Interfaces1**<br>~~ee A~~||||||
|**Generic DDRX8 or DDRX4 or DDRX2 I/O with Clock and Data Centered at General Purpose Pins (GDDRX8_RX/TX.ECLK.Centered**<br>**or GDDRX4_RX/TX.ECLK.Centered or GDDRX2_RX/TX.ECLK.Centered)**<br>~~OO~~||||||
|tSU_GDDRX2_4_8_CENTERED<br>~~a~~|Input Data Set-Up Before CLK<br>Risingand Fallingedges<br>~~a~~|—<br>~~a~~|0.167<br>~~a~~|—<br>~~a~~|ns<br>~~a~~|
|tHD_GDDRX2_4_8_CENTERED<br>~~a~~|Input Data Hold After CLK Rising<br>and Fallingedges<br>~~a~~|—<br>~~a~~|0.167<br>~~a~~|—<br>~~a~~|ns<br>~~a~~|
|tDVB_GDDRX2_4_8_CENTERED<br>~~a~~|Output Data Valid Before CLK<br>Output Rising and Falling edges<br>~~a~~|Data Rate = 1.2 Gb/s5<br>~~a~~|0.297<br>~~a~~<br>~~ee~~|—<br>~~a~~|ns<br>~~a~~|
|||Other Data Rates5<br>~~a~~<br>~~ee~~|−0.120<br>~~a~~<br>~~ee~~<br>~~ee~~|—<br>~~a~~<br>~~ee~~|ns+1/2UI<br>~~a~~<br>~~ee~~|
|tDVA_GDDRX2_4_8_CENTERED<br>~~a~~<br>~~—~~|Output Data Valid After CLK<br>Output Rising and Falling edges<br>~~a~~<br>~~—~~|Data Rate = 1.2 Gb/s5<br>~~a~~<br>~~ee~~<br>~~—~~|0.297<br>~~a~~<br>~~ee~~<br>~~ee~~<br>~~—~~|—<br>~~a~~<br>~~ee~~<br>~~—~~|ns<br>~~a~~<br>~~ee~~<br>~~—~~|
|||Other Data Rates5<br>~~—~~|−0.120<br>~~—~~<br>~~tT~~|—<br>~~—~~<br>~~tT~~|ns+1/2UI<br>~~—~~|
|fMAX_GDDRX2_4_8_CENTERED<br>~~==~~|Frequency for ECLK2<br>~~==~~|csfBGA81, ctfBGA80,<br>ckfBGA80, ucfBGA64<br>GDDRX2<br>~~P|~~<br>~~==~~|—<br>~~P|~~<br>~~tT~~<br>~~==~~|300<br>~~P|~~<br>~~tT~~<br>~~==~~|MHz<br>~~P|~~<br>~~==~~|
|||csfBGA81, ctfBGA80,<br>ckfBGA80, ucfBGA64<br>GDDRX4 and GDDRX8<br>~~==~~|—<br>~~tT~~<br>~~==~~|600<br>~~tT~~<br>~~==~~|MHz<br>~~==~~|
|||WLCSP36<br>GDDRX2<br>~~==~~|—<br>~~==~~|250<br>~~==~~|MHz<br>~~==~~|
36
FPGA-DS-02007-1.8
**CrossLink Family Data Sheet**
|**Parameter**<br>~~ee~~<br>~~OO~~|**Description**<br>~~OO~~|**Conditions**<br>~~Pp~~|**–6**<br>~~Pp~~|**–6**<br>~~Pp~~|**Unit**|
|---|---|---|---|---|---|
||||**Min**<br>~~Pp~~|**Max**||
|**Generic DDR Interfaces1**<br>~~Pp~~<br>~~ee~~<br>~~OO~~||||||
|**Generic DDRX8 or DDRX4 or DDRX2 I/O with Clock and Data Centered at General Purpose Pins (GDDRX8_RX/TX.ECLK.Centered**<br>**or GDDRX4_RX/TX.ECLK.Centered or GDDRX2_RX/TX.ECLK.Centered)**<br>~~OO~~||||||
|—<br>~~OO~~<br>~~A~~|—<br>~~OO~~<br>~~A~~|WLCSP36<br>GDDRX4 and GDDRX8<br>~~A~~|—<br>~~A~~|500<br>~~A~~|MHz<br>~~A~~|
|**Generic DDRX1 I/O with Clock and Data Centered at General Purpose Pins(GDDRX1_RX/TX.SCLK.Centered)**<br>~~A~~||||||
|tSU_GDDRX1_CENTERED<br>~~a~~|Input Data Set-Up Before CLK<br>Risingand Fallingedges<br>~~a~~|—<br>~~a~~|0.917<br>~~a~~|—<br>~~a~~|ns<br>~~a~~|
|tHD_GDDRX1_CENTERED<br>~~a~~|Input Data Hold After CLK Rising<br>and Fallingedges<br>~~a~~|—<br>~~a~~|0.917<br>~~a~~|—<br>~~a~~|ns<br>~~a~~|
|—<br>~~A~~|—<br>~~A~~|Data Rate = 300 Mb/s<br>~~A~~|1.217<br>~~A~~|—<br>~~A~~|ns<br>~~A~~|
|||Other Data Rates<br>~~A~~<br>~~ee~~|−0.450<br>~~A~~<br>~~ee~~|—<br>~~A~~<br>~~ee~~|ns+1/2UI<br>~~A~~<br>~~ee~~|
|—<br>~~a~~|—<br>~~a~~|Data Rate = 300 Mb/s<br>~~a~~|1.217<br>~~a~~|—<br>~~a~~|ns<br>~~a~~|
|||Other Data Rates<br>~~a~~<br>~~ee~~<br>~~DO~~|−0.450<br>~~a~~<br>~~ee~~<br>~~DO~~|—<br>~~a~~<br>~~ee~~<br>~~DO~~|ns+1/2UI<br>~~a~~<br>~~ee~~|
|fMAX_GDDRX1_CENTERED<br>~~A~~|Frequencyfor PCLK2<br>~~A~~|—<br>~~A~~<br>~~DO~~|—<br>~~A~~<br>~~DO~~|150<br>~~A~~<br>~~DO~~|MHz<br>~~A~~|
|**Generic DDRX8 or DDRX4 or DDRX2 I/O with Clock and Data Aligned at General Purpose Pins (GDDRX8_RX/TX.ECLK.Aligned or**<br>**GDDRX4_RX/TX.ECLK.Aligned or GDDRX2_RX/TX.ECLK.Aligned)**<br>~~DO~~<br>~~____~~||||||
|tSU_GDDRX2_4_8_ALIGNED<br>~~=~~|Input Data Valid After CLK<br>Rising and Falling edges<br>~~=~~|Data Rate = 1.2 Gb/s5<br>~~=~~|—<br>~~=~~|0.188<br>~~=~~|ns<br>~~=~~|
|||Other Data Rates5<br>~~=~~<br>~~ee~~|—<br>~~=~~<br>~~ee~~|−0.229<br>~~=~~<br>~~ee~~|ns+1/2UI<br>~~=~~<br>~~ee~~|
|tHD_GDDRX2_4_8_ALIGNED<br>~~a~~|Input Data Hold After CLK Rising<br>and Falling edges<br>~~a~~|Data Rate = 1.2 Gb/s5<br>~~a~~|0.646<br>~~a~~|—<br>~~a~~|ns<br>~~a~~|
|||Other Data Rates5<br>~~a~~<br>~~ee~~|0.229<br>~~a~~<br>~~ee~~|—<br>~~a~~<br>~~ee~~|ns+1/2UI<br>~~a~~<br>~~ee~~|
|tDIA_GDDRX2_4_8_ALIGNED<br>~~i~~|Output Data Invalid After CLK<br>Risingand Fallingedges Output|—|—|0.120|ns|
|tDIB_GDDRX2_4_8_ALIGNED<br>~~i~~|Output Data Invalid Before CLK<br>Output Risingand Fallingedges<br>~~A~~|—<br>~~A~~|—|0.120|ns|
|fMAX_GDDRX2_4_8_ALIGNED|Frequency for ECLK2|csfBGA81, ctfBGA80,<br>ckfBGA80, ucfBGA64<br>GDDRX2|—|300|MHz|
|||csfBGA81, ctfBGA80,<br>ckfBGA80, ucfBGA64<br>GDDRX4 and GDDRX8|—<br>~~ee~~|600|MHz|
|||WLCSP36 GDDRX2|—<br>~~ee~~|250|MHz|
|||WLCSP36 GDDRX4 and<br>GDDRX8<br>~~ee~~|—<br>~~ee~~<br>~~ee~~|500<br>~~ee~~|MHz<br>~~ee~~|
© 2015-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02007-1.8
37
**CrossLink Family Data Sheet**
|**Parameter**<br>~~ee~~|**Description**<br>~~ee~~|**Conditions**<br>~~ee~~|**–6**<br>~~Pe~~<br>~~ee~~|**–6**<br>~~Pe~~<br>~~ee~~|**Unit**<br>~~ee~~|
|---|---|---|---|---|---|
||||**Min**<br>~~ee~~|**Max**<br>~~ee~~||
|**Generic DDR Interfaces2**<br>~~Ce~~||||||
|**Generic DDRX1 I/O with Clock and Data Aligned at General Purpose Pins(GDDRX1_RX/TX.SCLK.Aligned)**<br>~~Ce~~<br>~~Ce~~||||||
|tSU_GDDRX1_ALIGNED<br>~~Ce~~<br>~~a~~<br>~~rr~~|Input Data Valid After CLK<br>Rising and Falling edges<br>~~Ce~~<br>~~a~~<br>~~rr~~|Data Rate = 300 Mb/s<br>~~Ce~~<br>~~a~~<br>|—<br>~~Ce~~<br>~~a~~<br>~~e~~~~**e**~~<br>|0.750<br>~~Ce~~<br>~~a~~<br>~~es~~<br>|ns<br>~~Ce~~<br>~~a~~|
|||Other Data Rates<br>~~a~~<br>~~es~~<br>|—<br>~~a~~<br>~~es~~<br>~~e~~~~**e**~~<br>|−0.917<br>~~a~~<br>~~es~~<br>~~es~~<br>|ns+1/2UI<br>~~a~~<br>~~es~~|
|tHD_GDDRX1_ALIGNED<br>~~rr~~<br>~~a~~<br>~~a~~|Input Data Hold After CLK Rising<br>and Falling edges<br>~~rr~~<br>~~ee ee~~|Data Rate = 300 Mb/s<br>|2.583<br>~~e~~~~**e**~~<br>~~ee ee~~|—<br>~~es~~<br>~~ee~~|ns|
|||Other Data Rates<br>~~e~~<br>~~ee~~|0.916<br>~~e~~~~**e**~~<br>~~eee ee~~|—<br>~~es~~<br>~~ee~~|ns+1/2UI|
|tDIA_GDDRX1_ALIGNED<br>~~rr~~<br>~~a~~<br>~~a~~|Output Data Invalid After CLK<br>Risingand Fallingedges Output<br>~~rr~~<br>~~ee ee~~<br>~~ee ee~~|—<br>~~e~~<br>~~ee~~<br>~~ee~~|—<br>~~e~~~~**e** ~~<br>~~eee ee~~|0.450<br> ~~es~~<br>~~ee~~|ns|
|tDIB_GDDRX1_ALIGNED<br>~~a~~|Output Data Invalid Before CLK<br>Output Risingand Fallingedges<br>~~ee ee~~<br>~~ee ee~~|—<br>~~ee~~<br>~~ee~~|—|0.450|ns|
|fMAX_GDDRX1_ALIGNED<br>~~sr~~|Frequencyfor ECLK2<br>~~ee ee~~<br>~~sr~~|—<br>~~ee~~<br>~~sr~~|—<br>~~sr~~|150<br>~~sr~~|MHz<br>~~sr~~|
|**General Purpose I/O MIPI D-PHY Rx with 1:8 or 1:16 Gearing**<br>~~sr~~<br>~~Ce~~||||||
|tSU_GDDRX_MP|Input Data Set-Up Before CLK|842 Mb/s < Data Rate ≤<br>1.2 Gb/s and<br>VIDTH= 140 mV<br>VIDTL= -140 mV|0.200|—|UI|
|||473 Mb/s < Data Rate≤<br>842 Mb/s and<br>VIDTH= 140 mV<br>VIDTL= -140 mV|0.150|—|UI|
|||Data Rate ≤ 473 Mb/s<br>and<br>VIDTH= 70 mV<br>VIDTL= -70 mV|0.150|—|UI|
|tHD_GDDRX_MP|Input Data Hold After CLK|842 Mb/s < Data Rate ≤<br>1.2 Gb/s and<br>VIDTH= 140 mV<br>VIDTL= -140 mV|0.200|—|UI|
|||473 Mb/s < Data Rate ≤<br>842 Mb/s &<br>VIDTH= 140 mV<br>VIDTL= -140 mV|0.150|—|UI|
|||Data Rate ≤ 473 Mb/s<br>and<br>VIDTH= 70 mV<br>VIDTL= -70 mV|0.150|—|UI|
|fMAX_GDDRX_MP<br>~~es~~|Frequency for ECLK2<br>~~es~~|csfBGA81, ctfBGA80,<br>ckfBGA80, ucfBGA64<br>~~es~~|—<br>~~es~~<br>~~ee~~|600<br>~~es~~|MHz<br>~~es~~|
|||WLCSP36<br>~~es~~<br>~~es~~|—<br>~~es~~<br>~~es~~<br>~~ee~~|500<br>~~es~~<br>~~es~~|MHz<br>~~es~~<br>~~es~~|
© 2015-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
38
FPGA-DS-02007-1.8
**CrossLink Family Data Sheet**
|**Parameter**<br>~~PO~~|**Description**<br>~~PO~~|**Conditions**<br>~~|~~<br>~~PO~~|**–6**<br>~~|ss~~<br>~~PO~~<br>~~Ee~~|**–6**<br>~~|ss~~<br>~~PO~~<br>~~Ee~~|**Unit**<br>~~PO~~|
|---|---|---|---|---|---|
||||**Min**<br>~~|~~<br>~~PO~~<br>~~Ee~~|**Max**<br><br>~~PO~~<br>~~Ee~~||
|**Generic DDRX71 or DDRX141 Inputs(GDDRX71_RX.ECLK or GDDRX141_RX.ECLK)**<br>~~Ee~~<br>~~Pee~~<br>~~Ssee~~<br>~~ee~~||||||
|tRPBi_DVA<br>~~Ss~~<br>~~a~~|Input Valid Bit "i" switching<br>from CLK Rising Edge<br>("i" = 0 to 6, 0 aligns with CLK)<br>~~ee~~|—<br>~~ee~~|—<br>~~ee~~<br>~~ee~~<br>~~ee~~|0.3<br>~~ee~~<br>~~ee~~<br>~~**e**ee~~|UI<br>~~ee~~<br>~~ee~~|
|||—<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|−0.222<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~**e**ee~~|ns+<br>(i+ 1/2)*UI<br>~~ee~~<br>~~ee~~<br>~~ee~~|
|tRPBi_DVE<br>~~Ss~~<br>~~a~~|Input Hold Bit "i" switching<br>from CLK Rising Edge<br>("i" = 0 to 6, 0 aligns with CLK)<br>~~ee~~|—<br>~~ee~~<br>~~ee~~<br>~~ee~~|0.7<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~**e**ee~~<br>~~ee~~|UI<br>~~ee~~<br>~~ee~~<br>~~ee~~|
|||—<br>~~ee~~|0.222<br>~~ee~~<br>~~ee~~|—<br>~~**e**ee~~<br>~~ee~~|ns+<br>(i+<br>1/2)*UI<br>~~ee~~|
|fMAX_RX71_141<br>~~a~~|DDR71/DDR141 ECLK<br>Frequency2|csfBGA81, ctfBGA80,<br>ckfBGA80, ucfBGA64,<br>WLCSP36<br>~~ee~~|—<br>~~ee ~~<br>~~ee~~|450<br> ~~**e**ee~~<br>~~ee~~|MHz<br>~~ee~~|
|**Generic DDR Interfaces1**<br>~~eee~~||||||
|**Generic DDRX71 Outputs with Clock and Data Aligned at Pin(GDDRX71_TX.ECLK)**<br>~~eee~~<br>~~Pee~~||||||
|tTPBi_DOV|Data Output Valid Bit "i"<br>switching from CLK Rising Edge<br>("i" = 0 to 6, 0 aligns with CLK)|—|—|0.143|ns+i*UI|
|tTPBi_DOI<br>~~ts~~|Data Output Invalid Bit "i"<br>switching from CLK Rising Edge<br>("i" = 0 to 6, 0 aligns with CLK)<br>~~rs~~|—<br>~~(~~|−0.143<br>~~(O~~|—|ns+i*UI|
|tTPBi_skew_UI<br>~~ts~~|Tx skew in UI<br>~~rs~~<br>~~hE~~|—<br>~~(~~<br>~~hE~~|—<br>~~(O~~|0.15|UI|
|fMAX_TX71<br>~~ts~~<br>~~Ff~~|DDR71 ECLK Frequency2<br>~~rs~~<br>~~Ff~~<br>~~hE~~|csfBGA81,<br>ctfBGA80, ckfBGA80,<br>ucfBGA64<br>~~(~~<br>~~Ff~~<br>~~hE~~|—<br>~~(O~~<br>~~Ff~~|525<br>~~Ff~~|MHz<br>~~Ff~~|
|||WLCSP36<br>~~Ff~~<br>~~hE~~|—<br>~~Ff~~|500<br>~~Ff~~|MHz<br>~~Ff~~|
|**Generic DDRX141 Outputs with Clock and Data Aligned at Pin(GDDRX141_TX.ECLK)**<br>~~hE~~<br>~~Pee~~||||||
|tTPBi_DOV|Data Output Valid Bit "i"<br>switching from CLK Rising Edge<br>("i" = 0 to 6, 0 aligns with CLK)|All Devices|—|0.125|ns+i*UI|
|tTPBi_DOI<br>~~es~~|Data Output Invalid Bit "i"<br>switching from CLK Rising Edge<br>("i" = 0 to 6, 0 aligns with CLK)<br>~~rs~~|All Devices<br>~~I~~|−0.125|—|ns+i*UI|
|tTPBi_skew_UI<br>~~es~~<br>~~PF~~<br>~~|~~|TX skew in UI<br>~~rs~~<br>~~Ed~~|All Devices<br>~~I~~<br>~~Ed~~|—<br>~~Ed~~|0.15<br>~~Ed~~|UI<br>~~Ed~~|
|fMAX_TX141<br>~~es~~<br>~~PF~~<br>~~|~~|DDR141 ECLK Frequency2<br>~~rs~~<br>~~Ed~~|csfBGA81,<br>ctfBGA80, ckfBGA80,<br>ucfBGA64<br>~~I~~<br>~~Ed~~|—<br>~~Ed~~|600<br>~~Ed~~|MHz<br>~~Ed~~|
|||WLCSP36<br>~~Ed~~|—<br>~~Ed~~|500<br>~~Ed~~|MHz<br>~~Ed~~|
## **Notes** :
1. Generic DDRX8, DDRX71 and DDRX141 timing numbers based on LVDS I/O.
2. Maximum clock frequencies are tested under best case conditions. System performance may vary upon the user environment.
3. These numbers are generated using best case PLL location.
4. All numbers are generated with the Lattice Diamond design software.
5. Maximum data rate for GDDRX2 mode is 500 Mbps for WLCSP36 package and 600 Mbps for all other packages.
© 2015-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02007-1.8
39
**CrossLink Family Data Sheet**
## Rx CLK (in)
## Rx DATA (in)
**==> picture [251 x 35] intentionally omitted <==**
## **Figure 4.1. Receiver RX.CLK.Centered Waveforms**
**==> picture [326 x 155] intentionally omitted <==**
## **Figure 4.2. Receiver RX.CLK.Aligned Input Waveforms**
**==> picture [457 x 136] intentionally omitted <==**
**----- Start of picture text -----**<br>
\q---------'' 1/2 UI onsen nana p ide!4 nn non nn 1/2 UI nnn p 4jig 1/2 UI .a ------------------- 1/2 UI -> }<br>!! | H' \IMl 'i ('<br>Tx CLK (out) ae1ae1\11111 i1'1Lt!!!1' 1H!HHH11t' finnNP1'Ht'' Leeee eeea 1{'11 Toon no nnn nnn nnn n mene nnn c nn cad i ';<br>------- V VEVeViA VN [at NE sateieieieieieieiaiaiaieietaiateteieted H1H anteieteteieteieieteieneientatatal vaViewsIi Nfivi 1I1 A NINININGAS<br>Tx DATA (out)<br>wo-----/ PAEVY OLINVI'! 11 1LA~--- eee tDVB weda 1 111 ! ecn cnn nene pyitPY! ' ' 1 H UATEVIVN t H HH nnn tDVB nnn eeeH vIHI nen rorccrccecncct iiveMS!1iN . ae<br>3 11 11 1 1 tDVA !H ' ' 11 ''‘¢1 H ' H1 ' 4! H ' H tDVA H! 1 '<br>**----- End of picture text -----**<br>
## **Figure 4.3. Transmit TX.CLK.Centered Output Waveforms**
© 2015-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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FPGA-DS-02007-1.8
**CrossLink Family Data Sheet**
**==> picture [278 x 112] intentionally omitted <==**
**----- Start of picture text -----**<br>
1 UI<br>Tx CLK (out)<br>Tx DATA (out)<br>tDIB tDIB<br>tDIA tDIA<br>**----- End of picture text -----**<br>
**==> picture [200 x 10] intentionally omitted <==**
**----- Start of picture text -----**<br>
Figure 4.4. Transmit TX.CLK.Aligned Waveforms<br>**----- End of picture text -----**<br>
## **Figure 4.5. DDRX71, DDRX141 Video Timing Waveforms**
© 2015-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02007-1.8
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**CrossLink Family Data Sheet**
## **4.15. sysCLOCK PLL Timing**
Over recommended operating conditions.
**Table 4.14. sysCLOCK PLL Timing**
|**Parameter**<br>~~a~~|**Descriptions**|**Conditions**|**Min**|**Max**|**Unit**|
|---|---|---|---|---|---|
|fIN<br>~~a~~|Input Clock Frequency (CLKI, CLKFB)<br>|—<br>|10<br>|400<br>|MHz<br>|
|fPD<br>~~se~~<br>~~es~~|Phase Detector Input Clock Frequency<br>~~se~~<br>~~Ga~~|—<br>~~se~~<br>~~GO~~|10<br>~~se~~<br>~~GO~~|400<br>~~se~~<br>~~GO~~|MHz<br>~~se~~<br>~~GO~~|
|fOUT<br>~~se~~<br>~~es~~|Output Clock Frequency (CLKOP, CLKOS)<br>~~se~~<br>~~Ga~~|—<br>~~se~~<br>~~GO~~<br>~~GO~~|4.6875<br>~~se~~<br>~~GO~~<br>~~GO~~|600<br>~~se~~<br>~~GO~~|MHz<br>~~se~~<br>~~GO~~|
|fVCO<br>~~es~~<br>~~a~~|PLL VCO Frequency<br>~~Ga~~<br>~~a~~|—<br>~~GO~~<br>~~a~~<br>~~GO~~|600<br>~~GO~~<br>~~a~~<br>~~GO~~|1200<br>~~GO~~<br>~~a~~|MHz<br>~~GO~~<br>~~a~~|
|**AC Characteristics**<br>~~GO~~<br>~~ee~~||||||
|tDT<br>~~ee~~<br>~~aee~~|Output Clock DutyCycle<br>~~ee~~|—<br>~~ee~~|45<br>~~ee ee~~|55<br>~~ee~~|%<br>~~ee~~|
|tPH<br>~~ee~~<br>~~aee~~|Output Phase Accuracy<br>~~ee~~|—<br>~~ee~~|−5<br>~~ee ee~~|5<br>~~ee~~|%<br>~~ee~~|
|tOPJIT1<br>~~a ee~~<br>~~—————_——EEEE~~|Output Clock Period Jitter3<br>~~ee~~|fOUT≥ 100 MHz<br>~~ee~~|—<br>~~ee ee~~|100<br>~~ee~~|psp-p<br>~~ee~~|
|||fOUT< 100 MHz<br>~~ee~~<br>~~es~~|—<br>~~ee ee~~<br>~~es~~|0.025<br>~~ee~~<br>~~es~~|UIPP<br>~~ee~~<br>~~es~~|
||Output Clock Cycle-to-Cycle Jitter3<br>~~ee ~~<br>~~OO~~<br>~~—————_——EEEE~~|fOUT≥ 100 MHz<br>~~ee~~<br>~~ee~~|—<br>~~ee ee~~<br>~~ee~~|200<br>~~ee~~<br>~~ee~~|psp-p<br>~~ee~~<br>~~ee~~|
|||fOUT< 100 MHz<br> ~~ee~~<br>~~ee~~<br>~~—————_——EEEE~~|—<br>~~ee ee~~<br>~~ee~~<br>~~—————_——EEEE~~|0.05<br>~~ee~~<br>~~ee~~<br>~~—————_——EEEE~~|UIPP<br>~~ee~~<br>~~ee~~<br>~~—————_——EEEE~~|
||Output Clock Phase Jitter<br>~~—————_——EEEE~~|fPD> 100 MHz<br>~~—————_——EEEE~~|—<br>~~—————_——EEEE~~|200<br>~~—————_——EEEE~~|psp-p<br>~~—————_——EEEE~~|
|||fPD< 100 MHz<br>~~—————_——EEEE~~<br>~~ee~~|—<br>~~—————_——EEEE~~<br>~~ee~~|0.05<br>~~—————_——EEEE~~<br>~~ee~~|UIPP<br>~~—————_——EEEE~~<br>~~ee~~|
|tSPO<br>~~—————_——EEEE~~<br>~~I~~|Static Phase Offset<br>~~—————_——EEEE~~|Divider ratio = integer<br>~~—————_——EEEE~~|—<br>~~—————_——EEEE~~|400<br>~~—————_——EEEE~~|psp-p<br>~~—————_——EEEE~~|
|tLOCK2<br>~~a~~<br>~~a~~|PLL Lock-in Time<br>|—<br>|—<br>|15<br>|ms<br>|
|tUNLOCK<br>~~a~~|PLL Unlock Time<br>|—<br>|—<br>|50<br>|ns<br>|
|tIPJIT<br>~~aa~~<br>~~a~~|Input Clock Period Jitter<br>~~a~~|fPD≥ 20 MHz<br>~~a~~|—<br>~~a~~<br>~~ee~~|500<br>~~a~~|psp-p<br>~~a~~|
|||fPD< 20 MHz<br>~~a~~<br>~~es~~|—<br>~~a~~<br>~~es~~<br>~~ee~~|0.02<br>~~a~~<br>~~es~~|UIPP<br>~~a~~<br>~~es~~|
|tHI<br>~~a~~<br>~~a~~|Input Clock High Time<br>~~a~~|90% to 90%<br>~~a~~<br>~~es~~|0.5<br>~~a~~<br>~~es~~<br>~~ee~~|—<br>~~a~~<br>~~es~~|ns<br>~~a~~<br>~~es~~|
|tLO<br>~~a~~|Input Clock Low Time|10% to 10%|0.5|—|ns|
## **Notes:**
1. Jitter sample is taken over 10,000 samples for Periodic jitter, and 2,000 samples for Cycle-to-Cycle jitter of the primary PLL output with clean reference clock with no additional I/O toggling.
2. Output clock is valid after tLOCK for PLL reset and dynamic delay adjustment.
3. Period jitter and cycle-to-cycle jitter numbers are guaranteed for fPD ≥ 10 MHz. For fPD < 10 MHz, the jitter numbers may not be met in certain conditions.
© 2015-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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**CrossLink Family Data Sheet**
## **4.16. Hardened MIPI D-PHY Performance**
Over recommended operating conditions.
**Table 4.15. 1500 Mb/s MIPI_DPHY_X8_RX/TX Timing Table (1500 Mb/s > MIPI D-PHY Data Rate > 1200 Mb/s)***
|**Parameter**<br>**Description**<br>**Min**<br>**Max**<br>**Unit**<br>tSU_MIPIX8<br>Input Data Setup before CLK<br>0.227<br>—<br>UI<br>tHD_MIPIX8<br>Input Data Hold after CLK<br>0.305<br>—<br>UI<br>tDVB_MIPIX8<br>Output Data Valid before CLK Output<br>0.200<br>—<br>UI<br>tDVA_MIPIX8<br>Output Data Valid after CLK Output<br>0.200<br>—<br>UI<br>~~Se~~|
|---|
|***Note**: For WLCSP36 package, the MIPI D-PHY fmaxis 1200 Mb/s, for other packages, fmaxis 1500 Mb/s.|
|**Table 4.16. 1200 Mb/s MIPI_DPHY_X4_RX/TX Timing Table(1200 Mb/s > MIPI D-PHY Data Rate > 1000 Mb/s)**<br>**Parameter**<br>**Description**<br>**Min**<br>**Max**<br>**Unit**<br>tSU_MIPIX4<br>Input Data Setup before CLK<br>0.200<br>—<br>UI<br>tHD_MIPIX4<br>Input Data Hold after CLK<br>0.200<br>—<br>UI<br>tDVB_MIPIX4<br>Output Data Valid before CLK Output<br>0.200<br>—<br>UI<br>tDVA_MIPIX4<br>Output Data Valid after CLK Output<br>0.200<br>—<br>UI<br>~~=SSa5>~~|
|**Table 4.17. 1000 Mb/s MIPI_DPHY_X4_RX/TX Timing Table(1000 Mb/s > MIPI D-PHY Data Rate > 10 Mb/s)**|
|**Parameter**<br>**Description**<br>**Min**<br>**Max**<br>**Unit**<br>tSU_MIPIX4<br>Input Data Setup before CLK<br>0.150<br>—<br>UI<br>tHD_MIPIX4<br>Input Data Hold after CLK<br>0.150<br>—<br>UI<br>tDVB_MIPIX4<br>Output Data Valid before CLK Output<br>0.150<br>—<br>UI<br>tDVA_MIPIX4<br>Output Data Valid after CLK Output<br>0.150<br>—<br>UI<br>~~=SSSaS>~~|
## **4.17. Internal Oscillators (HFOSC, LFOSC)**
Over recommended operating conditions.
|**Parameter**<br>~~—_——~~|**Parameter Description**<br>~~—_——~~|**Min**<br>~~—_——~~|**Typ**<br>~~—_——~~|**Max**<br>~~—_——~~|**Unit**<br>~~—_——~~|
|---|---|---|---|---|---|
|fCLKHF<br>~~—_——~~|HFOSC CLKK Clock Frequency<br>~~—_——~~|43.2<br>~~—_——~~|48<br>~~—_——~~|52.8<br>~~—_——~~|MHz<br>~~—_——~~|
|fCLKLF<br>~~—_——~~|LFOSC CLKK Clock Frequency<br>~~—_——~~|9<br>~~—_——~~|10<br>~~—_——~~|11<br>~~—_——~~|kHz<br>~~—_——~~|
|DCHCLKHF<br>~~—_——~~|HFOSC Duty Cycle (Clock High Period)<br>~~—_——~~|45<br>~~—_——~~|50<br>~~—_——~~|55<br>~~—_——~~|%<br>~~—_——~~|
|DCHCLKLF<br>~~—_——~~|LFOSC Duty Cycle (Clock High Period)<br>~~—_——~~|45<br>~~—_——~~|50<br>~~—_——~~|55<br>~~—_——~~|%<br>~~—_——~~|
© 2015-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02007-1.8
43
**CrossLink Family Data Sheet**
## **4.18. User I[2] C**
Over recommended operating conditions.
**Table 4.19. User I[2] C[1]**
|**Symbol**|**Parameter**|**STD Mode**|**STD Mode**|**STD Mode**|**FAST Mode**|**FAST Mode**|**FAST Mode**|**FAST Mode Plus2**|**FAST Mode Plus2**|**FAST Mode Plus2**|**Units**|
|---|---|---|---|---|---|---|---|---|---|---|---|
|||**Min**|**Typ**|**Max**|**Min**|**Typ**|**Max**|**Min**|**Typ**|**Max**||
|fscl|SCL Clock<br>Frequency|—|—|100|—|—|400|—|—|10002|kHz|
|TDELAY|Optional delay<br>through delayblock|—|62|—|—|62|—|—|62|—|ns|
**Notes** :
1. Refer to the I[2] C Specification for timing requirements.
2. Fast Mode Plus maximum speed may be achieved by using external pull up resistor on I[2] C bus. Internal pull up may not be sufficient to support the maximum speed.
## **4.19. CrossLink sysCONFIG Port Timing Specifications**
Over recommended operating conditions.
**Table 4.20. CrossLink sysCONFIG Port Timing Specifications**
|**Symbol**<br>~~GD~~|**Parameter**<br>~~GD~~|**Min**<br>~~GD~~|**Max**<br>~~GD~~|**Unit**<br>~~GD~~|
|---|---|---|---|---|
|**All Configuration Mode**<br>~~Pe~~|||||
|tPRGM3|Minimum CRESETB LOW pulse width required to<br>restart configuration(from fallingedge to risingedge)|290|—|ns|
|**Slave SPI1**<br>~~Pe~~|||||
|fCCLK<br>~~GO~~|SPI_SCK Input Clock Frequency<br>~~GO~~|—<br>~~GO~~|110<br>~~GO~~|MHz<br>~~GO~~|
|tSTSU<br>~~a ~~|MOSI Setup Time<br> ~~GC~~|0.5<br>~~GC~~|—<br>~~GC~~|ns<br>~~GC~~|
|tSTH<br>~~GO~~|MOSI Hold Time<br>~~GO~~|2.0<br>~~GO~~|—<br>~~GO~~|ns<br>~~GO~~|
|tSTCO<br>~~GC~~|SPI_SCK Falling Edge to Valid MISO Output<br>~~GC~~|—<br>~~GC~~|13.3<br>~~GC~~|ns<br>~~GC~~|
|tSCS<br>~~GG~~|Chip Select HIGH Time<br>~~GG~~|25<br>~~GG~~|—<br>~~GG~~|ns<br>~~GG~~|
|tSCSS<br>~~GG~~<br>~~GC~~|Chip Select Setup Time<br>~~GG~~<br>~~GC~~|0.5<br>~~GG~~<br>~~GC~~|—<br>~~GG~~<br>~~GC~~|ns<br>~~GG~~<br>~~GC~~|
|tSCSH<br>~~MG~~|Chip Select Hold Time<br>~~MG~~|0.5<br>~~MG~~|—<br>~~MG~~|ns<br>~~MG~~|
|**Master SPI**<br>~~MG~~<br>~~pe~~|||||
|fCCLK<br>~~pe~~<br>~~a ~~|MCK Output Clock Frequency<br>~~pe~~<br> ~~GD~~|—<br>~~pe~~<br>~~GD~~|52.8<br>~~pe~~<br>~~GD~~|MHz<br>~~pe~~<br>~~GD~~|
|**I2C 2**<br>~~pC~~<br>~~ee~~|||||
|fMAX<br>~~pC~~<br>~~ee~~|Maximum SCL Clock Frequency (Fast-Mode Plus)<br>~~pC~~|—<br>~~pC~~|1<br>~~pC~~|MHz<br>~~pC~~|
**Notes** :
1. Refer to CrossLink Programming and Configuration Usage Guide (FPGA-TN-02014), for timing requirements to enable CrossLink SSPI Mode.
2. Refer to the I2C specification for timing requirements when configuring with I[2] C port.
3. tPRGM minimum time does not apply when SLAVE_SPI_PORT, MASTER_SPI_PORT and I2C_PORT are disabled through Diamond Software. Contact your Lattice Sales Representatives for details.
## **4.20. SRAM Configuration Time from NVCM**
Over recommended operating conditions.
## **Table 4.21. SRAM Configuration Time from NVCM**
|**Symbol**|**Parameter**|**Typ**|**Unit**|
|---|---|---|---|
|TCONFIGURATION|POR/CRESET_B to Device I/O Active*|83|ms|
***Note** : Before and during configuration, the I/O are held in tristate with weak internal pullups enabled. I/O are released to user functionality when the device has finished configuration.
© 2015-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02007-1.8
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**CrossLink Family Data Sheet**
## **4.21. Switching Test Conditions**
Figure 4.6 shows the output test load that is used for AC testing. The specific values for resistance, capacitance, voltage, and other test conditions are listed in Table 4.22.
**==> picture [196 x 126] intentionally omitted <==**
**----- Start of picture text -----**<br>
V T<br>R1<br>DUT Test Point<br>R2 CL*<br>4<br>**----- End of picture text -----**<br>
*CL Includes Test Fixture and Probe Capacitance
**Figure 4.6. Output Test Load, LVTTL and LVCMOS Standards**
**Table 4.22. Test Fixture Required Components, Non-Terminated Interfaces***
|**Test Condition**|**R1 **|**R2 **|**CL **|**Timing Ref.**|**VT **|
|---|---|---|---|---|---|
|LVTTL and other LVCMOS settings (L ≥ H, H ≥ L)|∞|∞|0 pF|LVCMOS 3.3 = 1.5 V|—|
|||||LVCMOS 2.5 = VCCIO/2|—|
|||||LVCMOS 1.8 = VCCIO/2|—|
|||||LVCMOS 1.2 = VCCIO/2|—|
|LVCMOS 2.5 I/O (Z ≥ H)|∞|1 MΩ|0 pF|VCCIO/2|—|
|LVCMOS 2.5 I/O (Z ≥ L)|1 MΩ|∞|0 pF|VCCIO/2|VCCIO|
|LVCMOS 2.5 I/O (H ≥ Z)|∞|100|0 pF|VOH–0.10|—|
|LVCMOS 2.5 I/O (L ≥ Z)|100|∞|0 pF|VOL+ 0.10|VCCIO|
***Note** : Output test conditions for all other interfaces are determined by the respective standards.
© 2015-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02007-1.8
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**CrossLink Family Data Sheet**
## **5. Pinout Information**
The pinout tables below correspond to CrossLink LIF-MD6000 Pinout Version 1.4. GND pins are referenced as VSS in Lattice Diamond Software.
## **5.1. WLCSP36 Pinout**
**Table 5.1. WLCSP36 Pinout**
|**Pin Number**<br>~~Rs~~|**Pin Function**<br>|**Bank**<br>|**Dual Function**<br>|**Differential**<br>|
|---|---|---|---|---|
|A1<br>~~Rsee~~<br>~~es~~|GNDMU_DPHY1<br>~~ee~~|GND<br>~~ee~~|—<br>~~ee~~|—<br>~~ee~~|
|A2<br>~~ee~~<br>~~es~~<br>~~es~~|VCCMU_DPHY1<br>~~ee~~|DPHY1<br>~~ee~~|—<br>~~ee~~|—<br>~~ee~~|
|A3<br>~~es~~<br>~~es~~<br>~~es~~|DPHY1_DP2|DPHY1|—|True_OF_DPHY1_DN2|
|A4<br>~~es~~<br>~~es~~<br>~~es~~|DPHY1_DN2|DPHY1|—|Comp_OF_DPHY1_DP2|
|A5<br>~~es~~<br>~~es~~<br>~~es~~|VCCAUX|VCCAUX|—|—|
|A6<br>~~es~~<br>~~es~~<br>~~es~~|PB2C|2|MIPI_CLKT2_0|True_OF_PB2D|
|B1<br>~~es~~<br>~~es~~|DPHY1_DP0|DPHY1|—|True_OF_DPHY1_DN0|
|B2<br>~~es~~<br>~~a~~<br>~~Re~~|DPHY1_DP1|DPHY1|—|True_OF_DPHY1_DN1|
|B3<br>~~Re~~<br>~~Re~~|DPHY1_DP3|DPHY1|—|True_OF_DPHY1_DN3|
|B4<br>~~Re~~<br>~~Re~~<br>~~Re~~|DPHY1_DN3|DPHY1|—|Comp_OF_DPHY1_DP3|
|B5<br>~~Re~~<br>~~Re~~<br>~~Re~~|PB16D|2|PCLKC2_1|Comp_OF_PB16C|
|B6<br>~~Re~~<br>~~Re~~<br>~~Re~~|PB2D<br>|2<br>|MIPI_CLKC2_0<br>|Comp_OF_PB2C<br>|
|C1<br>~~Re~~<br>~~Re~~|DPHY1_DN0<br>|DPHY1<br>|—<br>|Comp_OF_DPHY1_DP0<br>|
|C2<br>~~Reee~~|DPHY1_DN1<br>~~ee~~|DPHY1<br>~~ee~~|—<br>~~ee~~|Comp_OF_DPHY1_DP1<br>~~ee~~|
|C3<br>~~ee~~<br>~~ee~~<br>~~Re~~|PB52<br>~~ee~~<br>~~ee~~|0<br>~~ee~~<br>~~ee~~<br>~~fe~~|SPI_SS/CSN/SCL<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~|
|C4<br>~~ee~~<br>~~ee~~<br>~~Re~~|VCC<br>~~ee~~<br>~~ee~~|VCC<br>~~ee~~<br>~~ee~~<br>~~fe~~|—<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~|
|C5<br>~~ee~~<br>~~Re~~<br>~~Re~~|PB16C<br>~~ee~~|2<br>~~ee~~<br>~~fe~~|PCLKT2_1<br>~~ee~~|True_OF_PB16D<br>~~ee~~|
|C6<br>~~Re~~<br>~~Re~~<br>~~Re~~|GND|GND<br>~~fe~~|—|—|
|D1<br>~~Re~~<br>~~Re~~|DPHY1_CKP|DPHY1|—|True_OF_DPHY1_CKN|
|D2<br>~~Re~~<br>~~ee~~|PB48<br>~~ee~~|0|PCLKT0_1/USER_SCL|—|
|D3<br>~~ee~~<br>~~ee~~|PB47<br>~~ee~~<br>~~ee~~|0|PCLKT0_0/USER_SDA|—|
|D4<br>~~ee~~<br>~~ee~~|CRESET_B<br>~~ee~~<br>~~ee~~|0|—|—|
|D5<br>~~ee~~<br>~~ee~~|PB16B<br>~~ee~~<br>~~ee~~|2|PCLKC2_0|Comp_OF_PB16A|
|D6<br>~~ee~~<br>~~ee~~|PB6B<br>~~ee~~<br>~~ee~~|2|—|Comp_OF_PB6A|
|E1<br>~~ee~~<br>~~ee~~|DPHY1_CKN<br>~~ee~~<br>~~ee~~|DPHY1|—|Comp_OF_DPHY1_CKP|
|E2<br>~~ee~~<br>~~De~~|VCCIO0<br>~~ee~~<br>~~De~~|0|—|—|
|E3<br>~~De~~<br>~~ee~~|GND<br>~~De~~<br>~~ee~~|GND<br>~~ee~~|—<br>~~ee~~|—<br>~~ee~~|
|E4<br>~~ee~~<br>~~ee~~|PB50<br>~~ee~~<br>~~ee~~|0<br>~~ee~~<br>~~ee~~|MOSI<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~|
|E5<br>~~ee~~<br>~~ee~~|PB16A<br>~~ee~~<br>~~ee~~|2<br>~~ee~~<br>~~ee~~|PCLKT2_0<br>~~ee~~<br>~~ee~~|True_OF_PB16B<br>~~ee~~<br>~~ee~~|
|E6<br>~~ee~~<br>~~ee~~|PB6A<br>~~ee~~<br>~~ee~~|2<br>~~ee~~<br>~~ee~~|GR_PCLK2_0<br>~~ee~~<br>~~ee~~|True_OF_PB6B<br>~~ee~~<br>~~ee~~|
|F1<br>~~ee~~<br>~~ee~~<br>~~Re~~|PB51<br>~~ee~~<br>~~ee~~<br>|0<br>~~ee~~<br>~~ee~~<br>|MISO<br>~~ee~~<br>~~ee~~<br>|—<br>~~ee~~<br>~~ee~~<br>|
|F2<br>~~ee~~<br>~~Re~~|PB49<br>~~ee~~<br>|0<br>~~ee~~<br>|PMU_WKUPN/CDONE<br>~~ee~~<br>|—<br>~~ee~~<br>|
|F3<br>~~ReeC~~|PB53<br>~~eC~~|0<br>~~eC~~|SPI_SCK/MCK/SDA<br>~~eC~~|—<br>~~eC~~|
|F4<br>~~eC~~|PB12A<br>~~eC~~|2<br>~~eC~~|GPLLT2_0<br>~~eC~~|True_OF_PB12B<br>~~eC~~|
|F5<br>~~ee~~<br>~~es~~|PB12B<br>~~ee~~|2<br>~~ee~~|GPLLC2_0<br>~~ee~~|Comp_OF_PB12A<br>~~ee~~|
|F6<br>~~ee~~<br>~~es~~|VCCIO2<br>~~ee~~|2<br>~~ee~~|—<br>~~ee~~|—<br>~~ee~~|
© 2015-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02007-1.8
46
**CrossLink Family Data Sheet**
## **5.2. ucfBGA64 Pinout**
**Table 5.2. ucfBGA64 Pinout**
|**Pin Number**<br>~~es~~<br>~~ee~~|**Pin Function**<br>~~es~~|**Bank**<br>~~es~~|**Dual Function**<br>~~GO~~|**Differential**|
|---|---|---|---|---|
|A1<br>~~es~~<br>~~ee~~<br>~~es~~|DPHY1_CKP<br>~~es~~|DPHY1<br>~~es~~|—<br>~~GO~~|True_OF_DPHY1_CKN|
|A2<br>~~ee~~<br>~~es~~<br>~~es~~|DPHY1_CKN<br>~~es~~<br>~~en~~|DPHY1<br>~~es~~|—<br>~~GO~~|Comp_OF_DPHY1_CKP|
|A3<br>~~es~~<br>~~es~~<br>~~es~~|DPHY1_DP3<br>~~en~~|DPHY1|—|True_OF_DPHY1_DN3|
|A4<br>~~es~~<br>~~es~~<br>~~es~~|DPHY1_DN3<br>~~en~~|DPHY1|—|Comp_OF_DPHY1_DP3|
|A5<br>~~es~~<br>~~es~~<br>~~es~~|DPHY0_DN2|DPHY0|—|Comp_OF_DPHY0_DP2|
|A6<br>~~es~~<br>~~es~~<br>~~Ps~~|DPHY0_DP0|DPHY0|—|True_OF_DPHY0_DN0|
|A7<br>~~es~~<br>~~Ps~~|DPHY0_CKP|DPHY0|—|True_OF_DPHY0_CKN|
|A8<br>~~Ps~~<br>~~ee~~<br>~~es~~|DPHY0_CKN<br>~~ee~~|DPHY0<br>~~ee~~|—<br>~~ee~~|Comp_OF_DPHY0_CKP<br>~~ee~~|
|B1<br>~~es~~<br>~~es~~|DPHY1_DP2|DPHY1|—|True_OF_DPHY1_DN2|
|B2<br>~~es~~<br>~~es~~<br>~~es~~|DPHY1_DN2|DPHY1|—|Comp_OF_DPHY1_DP2|
|B3<br>~~es~~<br>~~es~~<br>~~es~~|DPHY1_DP1|DPHY1|—|True_OF_DPHY1_DN1|
|B4<br>~~es~~<br>~~es~~<br>~~es~~|DPHY1_DN1|DPHY1|—|Comp_OF_DPHY1_DP1|
|B5<br>~~es~~<br>~~es~~<br>~~Ps~~|DPHY0_DP2|DPHY0|—|True_OF_DPHY0_DN2|
|B6<br>~~es~~<br>~~Ps~~<br>~~es~~|DPHY0_DN0|DPHY0|—|Comp_OF_DPHY0_DP0|
|B7<br>~~Ps~~<br>~~es~~<br>~~es~~|DPHY0_DP3<br>~~en~~|DPHY0|—|True_OF_DPHY0_DN3|
|B8<br>~~es~~<br>~~es~~<br>~~es~~|DPHY0_DN3<br>~~en~~|DPHY0|—|Comp_OF_DPHY0_DP3|
|C1<br>~~es~~<br>~~es~~<br>~~es~~|DPHY1_DP0<br>~~en~~|DPHY1|—|True_OF_DPHY1_DN0|
|C2<br>~~es~~<br>~~es~~<br>~~es~~|DPHY1_DN0|DPHY1|—|Comp_OF_DPHY1_DP0|
|C3<br>~~es~~<br>~~es~~<br>~~Ps~~|PB47|0|PCLKT0_0/USER_SDA|—|
|C4<br>~~es~~<br>~~Ps~~|VCCPLL_DPHYx|DPHY|—|—|
|C5<br>~~Ps~~<br>~~ee~~<br>~~es~~|VCCA_DPHYx<br>~~ee~~|DPHY<br>~~ee~~|—<br>~~ee~~|—<br>~~ee~~|
|C6<br>~~es~~<br>~~es~~|GNDA_DPHYx|GND|—|—|
|C7<br>~~es~~<br>~~es~~<br>~~es~~|DPHY0_DP1|DPHY0|—|True_OF_DPHY0_DN1|
|C8<br>~~es~~<br>~~es~~<br>~~es~~|DPHY0_DN1<br>~~en~~|DPHY0|—|Comp_OF_DPHY0_DP1|
|D1<br>~~es~~<br>~~es~~|PB34B<br>~~en~~|1<br>~~GO~~|—<br>~~GO~~|Comp_OF_PB34A|
|D2<br>~~es~~<br>~~ee~~|PB34A<br>~~en~~<br>~~ee~~|1<br>~~ee~~<br>~~GO~~|GR_PCLK1_0<br>~~ee~~<br>~~GO~~|True_OF_PB34B<br>~~ee~~|
|D3<br>~~ee~~<br>~~ee~~<br>~~es~~|PB52<br>~~ee~~<br>~~ee~~|0<br>~~ee~~<br>~~GO~~<br>~~ee~~|SPI_SS/CSN/SCL<br>~~ee~~<br>~~GO~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~|
|D4<br>~~es~~<br>~~es~~|GND|GND|—|—|
|D5<br>~~es~~<br>~~es~~<br>~~es~~|VCC|VCC|—|—|
|D6<br>~~es~~<br>~~es~~<br>~~es~~|VCCAUX|VCCAUX|—|—|
|D7<br>~~es~~<br>~~es~~<br>~~es~~|PB16A<br>~~en~~|2|PCLKT2_0|True_OF_PB16B|
|D8<br>~~es~~<br>~~es~~|PB12A<br>~~en~~|2|GPLLT2_0|True_OF_PB12B|
|E1<br>~~es~~<br>~~ee~~|PB51<br>~~en~~<br>~~ee~~|0<br>~~ee~~|MISO<br>~~ee~~|—<br>~~ee~~|
|E2<br>~~ee~~<br>~~es~~|CRESET_B<br>~~ee~~|0<br>~~ee~~|—<br>~~ee~~|—<br>~~ee~~|
|E3<br>~~es~~<br>~~es~~|PB48|0|PCLKT0_1/USER_SCL|—|
|E4<br>~~es~~<br>~~es~~<br>~~es~~|VCC|VCC|—|—|
|E5<br>~~es~~<br>~~es~~<br>~~es~~|GND<br>~~en~~|GND|—|—|
|E6<br>~~es~~<br>~~es~~|VCCIO2<br>~~en~~|2<br>~~GO~~|—<br>~~GO~~|—|
|E7<br>~~es~~<br>~~ee~~|PB16B<br>~~en~~<br>~~ee~~|2<br>~~ee~~<br>~~GO~~|PCLKC2_0<br>~~ee~~<br>~~GO~~|Comp_OF_PB16A<br>~~ee~~|
|E8<br>~~ee~~<br>~~ee~~|PB12B<br>~~ee~~<br>~~ee~~|2<br>~~ee~~<br>~~GO~~<br>~~ee~~|GPLLC2_0<br>~~ee~~<br>~~GO~~<br>~~ee~~|Comp_OF_PB12A<br>~~ee~~<br>~~ee~~|
|F1<br>~~ee~~<br>~~es~~|PB53<br>~~ee~~|0<br>~~ee~~|SPI_SCK/MCK/SDA<br>~~ee~~|—<br>~~ee~~|
|F2<br>~~es~~|PB50|0|MOSI|—|
© 2015-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02007-1.8
47
**CrossLink Family Data Sheet**
**Table 5.2. ucfBGA64 Pinout** _(Continued)_
|**Pin Number**<br>~~GG~~|**Pin Function**<br>~~GG~~|**Bank**<br>~~GG~~|**Dual Function**<br>~~GG~~|**Differential**<br>~~GG~~|
|---|---|---|---|---|
|F3<br>~~eG~~|VCCIO0<br>~~eG~~|0<br>~~eG~~|—<br>~~eG~~|—<br>~~eG~~|
|F4<br>~~eG~~|VCCIO1<br>~~eG~~|1<br>~~eG~~|—<br>~~eG~~|—<br>~~eG~~|
|F5<br>~~a~~|GND|GND|—<br>~~G~~|—|
|F6<br>~~eG~~|VCCIO2<br>~~eG~~|2<br>~~eG~~|—<br>~~eG~~|—<br>~~eG~~|
|F7<br>~~eG~~<br>~~Re~~|PB6A<br>~~eG~~|2<br>~~eG~~|GR_PCLK2_0<br>~~eG~~|True_OF_PB6B<br>~~eG~~|
|F8<br>~~Re~~|PB6B|2|—|Comp_OF_PB6A|
|G1<br>~~Re~~<br>~~ee~~|PB38D<br>~~ee~~|1<br>~~ee~~|—<br>~~ee~~|Comp_OF_PB38C<br>~~ee~~|
|G2<br>~~ee~~<br>~~ee~~|PB38C<br>~~ee~~<br>~~ee~~|1<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~|True_OF_PB38D<br>~~ee~~<br>~~ee~~|
|G3<br>~~ee~~<br>~~ee~~|PB49<br>~~ee~~<br>~~ee~~|0<br>~~ee~~<br>~~ee~~|PMU_WKUPN/CDONE<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~|
|G4<br>~~ee~~<br>~~ee~~|VCCGPLL<br>~~ee~~<br>~~ee~~|VCCGPLL<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~|
|G5<br>~~ee~~<br>~~ee~~|PB29B<br>~~ee~~<br>~~ee~~|1<br>~~ee~~<br>~~ee~~|PCLKC1_0<br>~~ee~~<br>~~ee~~|Comp_OF_PB29A<br>~~ee~~<br>~~ee~~|
|G6<br>~~ee~~<br>~~eG~~|PB29A<br>~~ee~~<br>~~eG~~|1<br>~~ee~~<br>~~eG~~|PCLKT1_0<br>~~ee~~<br>~~eG~~|True_OF_PB29B<br>~~ee~~<br>~~eG~~|
|G7<br>~~eG~~<br>~~eG~~|PB2D<br>~~eG~~<br>~~eG~~|2<br>~~eG~~<br>~~eG~~|MIPI_CLKC2_0<br>~~eG~~<br>~~eG~~|Comp_OF_PB2C<br>~~eG~~<br>~~eG~~|
|G8<br>~~eG~~<br>~~eG~~|PB2C<br>~~eG~~<br>~~eG~~|2<br>~~eG~~<br>~~eG~~|MIPI_CLKT2_0<br>~~eG~~<br>~~eG~~|True_OF_PB2D<br>~~eG~~<br>~~eG~~|
|H1<br>~~eG~~<br>~~eG~~|PB34D<br>~~eG~~<br>~~eG~~|1<br>~~eG~~<br>~~eG~~|MIPI_CLKC1_0<br>~~eG~~<br>~~eG~~|Comp_OF_PB34C<br>~~eG~~<br>~~eG~~|
|H2<br>~~eG~~<br>~~eG~~|PB34C<br>~~eG~~<br>~~eG~~|1<br>~~eG~~<br>~~eG~~|MIPI_CLKT1_0<br>~~eG~~<br>~~eG~~|True_OF_PB34D<br>~~eG~~<br>~~eG~~|
|H3<br>~~eG~~<br>~~eG~~|PB29C<br>~~eG~~<br>~~eG~~|1<br>~~eG~~<br>~~eG~~|PCLKT1_1<br>~~eG~~<br>~~eG~~|True_OF_PB29D<br>~~eG~~<br>~~eG~~|
|H4<br>~~eG~~<br>~~eG~~|PB29D<br>~~eG~~<br>~~eG~~|1<br>~~eG~~<br>~~eG~~|PCLKC1_1<br>~~eG~~<br>~~eG~~|Comp_OF_PB29C<br>~~eG~~<br>~~eG~~|
|H5<br>~~eG~~<br>~~eG~~|PB16D<br>~~eG~~<br>~~eG~~|2<br>~~eG~~<br>~~eG~~|PCLKC2_1<br>~~eG~~<br>~~eG~~|Comp_OF_PB16C<br>~~eG~~<br>~~eG~~|
|H6<br>~~eG~~<br>~~eG~~|PB16C<br>~~eG~~<br>~~eG~~|2<br>~~eG~~<br>~~eG~~|PCLKT2_1<br>~~eG~~<br>~~eG~~|True_OF_PB16D<br>~~eG~~<br>~~eG~~|
|H7<br>~~eG~~<br>~~eG~~|PB12D<br>~~eG~~<br>~~eG~~|2<br>~~eG~~<br>~~eG~~|—<br>~~eG~~<br>~~eG~~|Comp_OF_PB12C<br>~~eG~~<br>~~eG~~|
|H8<br>~~eG~~<br>~~DG~~|PB12C<br>~~eG~~<br>~~DG~~|2<br>~~eG~~<br>~~DG~~|—<br>~~eG~~<br>~~DG~~|True_OF_PB12D<br>~~eG~~<br>~~DG~~|
© 2015-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
48
FPGA-DS-02007-1.8
**CrossLink Family Data Sheet**
## **5.3. ctfBGA80/ckfBGA80 Pinout**
**Table 5.3. ctfBGA80/ckfBGA80 Pinout**
|**Pin Number**<br>~~es~~<br>~~ee~~|**Pin Function**<br>~~es~~|**Bank**<br>~~es~~|**Dual Function**<br>~~GO~~|**Differential**|
|---|---|---|---|---|
|A1<br>~~es~~<br>~~ee~~<br>~~es~~|DPHY1_DN2<br>~~es~~|DPHY1<br>~~es~~|—<br>~~GO~~|Comp_OF_DPHY1_DP2|
|A2<br>~~ee~~<br>~~es~~<br>~~es~~|DPHY1_DN0<br>~~es~~<br>~~en~~|DPHY1<br>~~es~~|—<br>~~GO~~|Comp_OF_DPHY1_DP0|
|A3<br>~~es~~<br>~~es~~<br>~~es~~|DPHY1_CKN<br>~~en~~|DPHY1|—|Comp_OF_DPHY1_CKP|
|A4<br>~~es~~<br>~~es~~<br>~~es~~|DPHY1_DN1<br>~~en~~|DPHY1|—|Comp_OF_DPHY1_DP1|
|A5<br>~~es~~<br>~~es~~<br>~~es~~|DPHY1_DN3|DPHY1|—|Comp_OF_DPHY1_DP3|
|A6<br>~~es~~<br>~~es~~<br>~~Ps~~|DPHY0_DN2|DPHY0|—|Comp_OF_DPHY0_DP2|
|A7<br>~~es~~<br>~~Ps~~|DPHY0_DN0|DPHY0|—|Comp_OF_DPHY0_DP0|
|A8<br>~~Ps~~<br>~~ee~~<br>~~es~~|DPHY0_CKN<br>~~ee~~|DPHY0<br>~~ee~~|—<br>~~ee~~|Comp_OF_DPHY0_CKP<br>~~ee~~|
|A9<br>~~es~~<br>~~es~~|DPHY0_DN1|DPHY0|—|Comp_OF_DPHY0_DP1|
|A10<br>~~es~~<br>~~es~~<br>~~es~~|DPHY0_DN3|DPHY0|—|Comp_OF_DPHY0_DP3|
|B1<br>~~es~~<br>~~es~~<br>~~es~~|DPHY1_DP2|DPHY1|—|True_OF_DPHY1_DN2|
|B2<br>~~es~~<br>~~es~~<br>~~es~~|DPHY1_DP0|DPHY1|—|True_OF_DPHY1_DN0|
|B3<br>~~es~~<br>~~es~~<br>~~Ps~~|DPHY1_CKP|DPHY1|—|True_OF_DPHY1_CKN|
|B4<br>~~es~~<br>~~Ps~~<br>~~es~~|DPHY1_DP1|DPHY1|—|True_OF_DPHY1_DN1|
|B5<br>~~Ps~~<br>~~es~~<br>~~es~~|DPHY1_DP3<br>~~en~~|DPHY1|—|True_OF_DPHY1_DN3|
|B6<br>~~es~~<br>~~es~~<br>~~es~~|DPHY0_DP2<br>~~en~~|DPHY0|—|True_OF_DPHY0_DN2|
|B7<br>~~es~~<br>~~es~~<br>~~es~~|DPHY0_DP0<br>~~en~~|DPHY0|—|True_OF_DPHY0_DN0|
|B8<br>~~es~~<br>~~es~~<br>~~es~~|DPHY0_CKP|DPHY0|—|True_OF_DPHY0_CKN|
|B9<br>~~es~~<br>~~es~~<br>~~Ps~~|DPHY0_DP1|DPHY0|—|True_OF_DPHY0_DN1|
|B10<br>~~es~~<br>~~Ps~~|DPHY0_DP3|DPHY0|—|True_OF_DPHY0_DN3|
|C1<br>~~Ps~~<br>~~ee~~<br>~~es~~|GND<br>~~ee~~|GND<br>~~ee~~|—<br>~~ee~~|—<br>~~ee~~|
|C2<br>~~es~~<br>~~es~~|GNDA_DPHY1|DPHY1|—|—|
|C9<br>~~es~~<br>~~es~~<br>~~es~~|GNDA_DPHY0|DPHY0|—|—|
|C10<br>~~es~~<br>~~es~~<br>~~es~~|GND<br>~~en~~|GND|—|—|
|D1<br>~~es~~<br>~~es~~|PB48<br>~~en~~|0<br>~~GO~~|PCLKT0_1/USER_SCL<br>~~GO~~|—|
|D2<br>~~es~~<br>~~ee~~|VCCPLL_DPHY1<br>~~en~~<br>~~ee~~|DPHY1<br>~~ee~~<br>~~GO~~|—<br>~~ee~~<br>~~GO~~|—<br>~~ee~~|
|D4<br>~~ee~~<br>~~ee~~<br>~~es~~|VCCA_DPHY1<br>~~ee~~<br>~~ee~~|DPHY1<br>~~ee~~<br>~~GO~~<br>~~ee~~|—<br>~~ee~~<br>~~GO~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~|
|D5<br>~~es~~<br>~~es~~|VCCAUX|VCCAUX|—|—|
|D6<br>~~es~~<br>~~es~~<br>~~es~~|GNDPLL_DPHYx|GND|—|—|
|D7<br>~~es~~<br>~~es~~<br>~~es~~|VCCPLL_DPHY0|DPHY0|—|—|
|D9<br>~~es~~<br>~~es~~<br>~~es~~|PB16A<br>~~en~~|2|PCLKT2_0|True_OF_PB16B|
|D10<br>~~es~~<br>~~es~~|PB16B<br>~~en~~|2|PCLKC2_0|Comp_OF_PB16A|
|E1<br>~~es~~<br>~~ee~~|PB34A<br>~~en~~<br>~~ee~~|1<br>~~ee~~|GR_PCLK1_0<br>~~ee~~|True_OF_PB34B<br>~~ee~~|
|E2<br>~~ee~~<br>~~es~~|PB34B<br>~~ee~~|1<br>~~ee~~|—<br>~~ee~~|Comp_OF_PB34A<br>~~ee~~|
|E4<br>~~es~~<br>~~es~~|VCC|VCC|—|—|
|E5<br>~~es~~<br>~~es~~<br>~~es~~|GND|GND|—|—|
|E6<br>~~es~~<br>~~es~~<br>~~es~~|VCC<br>~~en~~|VCC|—|—|
|E7<br>~~es~~<br>~~es~~|VCCA_DPHY0<br>~~en~~|DPHY0<br>~~GO~~|—<br>~~GO~~|—|
|E9<br>~~es~~<br>~~ee~~|PB12A<br>~~en~~<br>~~ee~~|2<br>~~ee~~<br>~~GO~~|GPLLT2_0<br>~~ee~~<br>~~GO~~|True_OF_PB12B<br>~~ee~~|
|E10<br>~~ee~~<br>~~ee~~|PB12B<br>~~ee~~<br>~~ee~~|2<br>~~ee~~<br>~~GO~~<br>~~ee~~|GPLLC2_0<br>~~ee~~<br>~~GO~~<br>~~ee~~|Comp_OF_PB12A<br>~~ee~~<br>~~ee~~|
|F1<br>~~ee~~<br>~~es~~|PB38A<br>~~ee~~|1<br>~~ee~~|—<br>~~ee~~|True_OF_PB38B<br>~~ee~~|
|F2<br>~~es~~|PB38B|1|—|Comp_OF_PB38A|
© 2015-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02007-1.8
49
**CrossLink Family Data Sheet**
**Table 5.3. ctfBGA80/ckfBGA80 Pinout** _(Continued)_
|**Pin Number**<br>~~GG~~|**Pin Function**<br>~~GG~~|**Bank**<br>~~GG~~|**Dual Function**<br>~~GG~~|**Differential**<br>~~GG~~|
|---|---|---|---|---|
|F4<br>~~eG~~|VCCIO0<br>~~eG~~|0<br>~~eG~~|—<br>~~eG~~|—<br>~~eG~~|
|F5<br>~~eG~~|VCCIO1<br>~~eG~~|1<br>~~eG~~|—<br>~~eG~~|—<br>~~eG~~|
|F6<br>~~a~~|VCCIO2|2|—<br>~~G~~|—|
|F7<br>~~eG~~|VCCIO2<br>~~eG~~|2<br>~~eG~~|—<br>~~eG~~|—<br>~~eG~~|
|F9<br>~~eG~~<br>~~Re~~|PB6A<br>~~eG~~|2<br>~~eG~~|GR_PCLK2_0<br>~~eG~~|True_OF_PB6B<br>~~eG~~|
|F10<br>~~Re~~|PB6B|2|—|Comp_OF_PB6A|
|G1<br>~~Re~~<br>~~ee~~|PB50<br>~~ee~~|0<br>~~ee~~|MOSI<br>~~ee~~|—<br>~~ee~~|
|G2<br>~~ee~~<br>~~ee~~|GND<br>~~ee~~<br>~~ee~~|GND<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~|
|G4<br>~~ee~~<br>~~ee~~|VCCIO1<br>~~ee~~<br>~~ee~~|1<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~|
|G5<br>~~ee~~<br>~~ee~~|GND<br>~~ee~~<br>~~ee~~|GND<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~|
|G6<br>~~ee~~<br>~~ee~~|VCCGPLL<br>~~ee~~<br>~~ee~~|VCCGPLL<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~|
|G7<br>~~ee~~<br>~~eG~~|GNDGPLL<br>~~ee~~<br>~~eG~~|GND<br>~~ee~~<br>~~eG~~|—<br>~~ee~~<br>~~eG~~|—<br>~~ee~~<br>~~eG~~|
|G9<br>~~eG~~<br>~~eG~~|PB2A<br>~~eG~~<br>~~eG~~|2<br>~~eG~~<br>~~eG~~|—<br>~~eG~~<br>~~eG~~|True_OF_PB2B<br>~~eG~~<br>~~eG~~|
|G10<br>~~eG~~<br>~~eG~~|PB2B<br>~~eG~~<br>~~eG~~|2<br>~~eG~~<br>~~eG~~|—<br>~~eG~~<br>~~eG~~|Comp_OF_PB2A<br>~~eG~~<br>~~eG~~|
|H1<br>~~eG~~<br>~~eG~~|PB52<br>~~eG~~<br>~~eG~~|0<br>~~eG~~<br>~~eG~~|SPI_SS/CSN/SCL<br>~~eG~~<br>~~eG~~|—<br>~~eG~~<br>~~eG~~|
|H2<br>~~eG~~<br>~~eG~~|CRESET_B<br>~~eG~~<br>~~eG~~|0<br>~~eG~~<br>~~eG~~|—<br>~~eG~~<br>~~eG~~|—<br>~~eG~~<br>~~eG~~|
|H9<br>~~eG~~<br>~~eG~~|PB2D<br>~~eG~~<br>~~eG~~|2<br>~~eG~~<br>~~eG~~|MIPI_CLKC2_0<br>~~eG~~<br>~~eG~~|Comp_OF_PB2C<br>~~eG~~<br>~~eG~~|
|H10<br>~~eG~~<br>~~eG~~|PB2C<br>~~eG~~<br>~~eG~~|2<br>~~eG~~<br>~~eG~~|MIPI_CLKT2_0<br>~~eG~~<br>~~eG~~|True_OF_PB2D<br>~~eG~~<br>~~eG~~|
|J1<br>~~eG~~<br>~~eG~~|PB53<br>~~eG~~<br>~~eG~~|0<br>~~eG~~<br>~~eG~~|SPI_SCK/MCK/SDA<br>~~eG~~<br>~~eG~~|—<br>~~eG~~<br>~~eG~~|
|J2<br>~~eG~~<br>~~eG~~|PB49<br>~~eG~~<br>~~eG~~|0<br>~~eG~~<br>~~eG~~|PMU_WKUPN/CDONE<br>~~eG~~<br>~~eG~~|—<br>~~eG~~<br>~~eG~~|
|J3<br>~~eG~~<br>~~eG~~|PB43D<br>~~eG~~<br>~~eG~~|1<br>~~eG~~<br>~~eG~~|—<br>~~eG~~<br>~~eG~~|Comp_OF_PB43C<br>~~eG~~<br>~~eG~~|
|J4<br>~~eG~~<br>~~eG~~|PB38D<br>~~eG~~<br>~~eG~~|1<br>~~eG~~<br>~~eG~~|—<br>~~eG~~<br>~~eG~~|Comp_OF_PB38C<br>~~eG~~<br>~~eG~~|
|J5<br>~~eG~~<br>~~eG~~|PB34D<br>~~eG~~<br>~~eG~~|1<br>~~eG~~<br>~~eG~~|MIPI_CLKC1_0<br>~~eG~~<br>~~eG~~|Comp_OF_PB34C<br>~~eG~~<br>~~eG~~|
|J6<br>~~eG~~<br>~~eG~~|PB29D<br>~~eG~~<br>~~eG~~|1<br>~~eG~~<br>~~eG~~|PCLKC1_1<br>~~eG~~<br>~~eG~~|Comp_OF_PB29C<br>~~eG~~<br>~~eG~~|
|J7<br>~~eG~~|PB29A<br>~~eG~~|1<br>~~eG~~|PCLKT1_0<br>~~eG~~|True_OF_PB29B<br>~~eG~~|
|J8<br>~~a~~|PB16D<br>|2<br>|PCLKC2_1<br>|Comp_OF_PB16C<br>|
|J9<br>~~aeG~~|PB6D<br>~~eG~~|2<br>~~eG~~|—<br>~~eG~~|Comp_OF_PB6C<br>~~eG~~|
|J10<br>~~eG~~|PB6C<br>~~eG~~|2<br>~~eG~~|—<br>~~eG~~|True_OF_PB6D<br>~~eG~~|
|K1<br>~~eG~~|PB51<br>~~eG~~|0<br>~~eG~~|MISO<br>~~eG~~|—<br>~~eG~~|
|K2<br>~~ee~~|PB47<br>~~ee~~|0<br>~~ee~~|PCLKT0_0/USER_SDA<br>~~ee~~|—<br>~~ee~~|
|K3<br>~~ee~~<br>~~eG~~|PB43C<br>~~ee~~<br>~~eG~~|1<br>~~ee~~<br>~~eG~~|—<br>~~ee~~<br>~~eG~~|True_OF_PB43D<br>~~ee~~<br>~~eG~~|
|K4<br>~~eG~~<br>~~eG~~|PB38C<br>~~eG~~<br>~~eG~~|1<br>~~eG~~<br>~~eG~~|—<br>~~eG~~<br>~~eG~~|True_OF_PB38D<br>~~eG~~<br>~~eG~~|
|K5<br>~~eG~~<br>~~eG~~|PB34C<br>~~eG~~<br>~~eG~~|1<br>~~eG~~<br>~~eG~~|MIPI_CLKT1_0<br>~~eG~~<br>~~eG~~|True_OF_PB34D<br>~~eG~~<br>~~eG~~|
|K6<br>~~eG~~<br>~~eG~~|PB29C<br>~~eG~~<br>~~eG~~|1<br>~~eG~~<br>~~eG~~|PCLKT1_1<br>~~eG~~<br>~~eG~~|True_OF_PB29D<br>~~eG~~<br>~~eG~~|
|K7<br>~~eG~~<br>~~eG~~|PB29B<br>~~eG~~<br>~~eG~~|1<br>~~eG~~<br>~~eG~~|PCLKC1_0<br>~~eG~~<br>~~eG~~|Comp_OF_PB29A<br>~~eG~~<br>~~eG~~|
|K8<br>~~eG~~<br>~~a~~<br>~~Re~~|PB16C<br>~~eG~~<br>~~eG~~|2<br>~~eG~~<br>~~eG~~|PCLKT2_1<br>~~eG~~<br>~~G~~<br>~~eG~~|True_OF_PB16D<br>~~eG~~<br>~~eG~~|
|K9<br>~~a~~<br>~~Re~~|PB12D<br>~~eG~~|2<br>~~eG~~|—<br>~~G~~<br>~~eG~~|Comp_OF_PB12C<br>~~eG~~|
|K10<br>~~Re~~<br>~~GG~~|PB12C<br>~~eG~~<br>~~GG~~|2<br>~~eG~~<br>~~GG~~|—<br>~~eG~~<br>~~GG~~|True_OF_PB12D<br>~~eG~~<br>~~GG~~|
© 2015-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
50
FPGA-DS-02007-1.8
**CrossLink Family Data Sheet**
## **5.4. csfBGA81 Pinout**
**Table 5.4. csfBGA81 Pinout**
|**Pin Number**<br>~~pf~~<br>~~ee~~|**Pin Function**<br>~~pf~~<br>~~GC~~|**Bank**<br>~~pf~~<br>~~GC~~|**Dual Function**<br>~~pf~~<br>~~GC~~|**Differential**<br>~~pf~~<br>~~GC~~|
|---|---|---|---|---|
|A1<br>~~ee~~|DPHY1_CKP<br>~~GC~~|DPHY1<br>~~GC~~|—<br>~~GC~~|True_OF_DPHY1_CKN<br>~~GC~~|
|A2<br>~~ee~~<br>~~a~~|DPHY1_CKN<br>~~GC~~<br>~~eG~~|DPHY1<br>~~GC~~<br>~~eG~~|—<br>~~GC~~<br>~~eG~~|Comp_OF_DPHY1_CKP<br>~~GC~~<br>~~eG~~|
|A3<br>~~a ~~<br>~~a ~~<br>~~**e**e~~|DPHY1_DP1<br> ~~eG~~<br> ~~eG~~<br>~~eG~~|DPHY1<br>~~eG~~<br>~~eG~~<br>~~eG~~|—<br>~~eG~~<br>~~eG~~<br>~~eG~~|True_OF_DPHY1_DN1<br>~~eG~~<br>~~eG~~<br>~~eG~~|
|A4<br>~~**e**e~~|DPHY1_DP3<br>~~eG~~|DPHY1<br>~~eG~~|—<br>~~eG~~|True_OF_DPHY1_DN3<br>~~eG~~|
|A5<br>~~**e**e~~<br>~~ee~~|VCCA_DPHY1<br>~~eG~~<br>~~eG~~|DPHY1<br>~~eG~~<br>~~eG~~|—<br>~~eG~~<br>~~G~~<br>~~eG~~|—<br>~~eG~~<br>~~G~~<br>~~eG~~|
|A6<br>~~ee~~|DPHY0_DN2<br>~~eG~~|DPHY0<br>~~eG~~|—<br>~~eG~~|Comp_OF_DPHY0_DP2<br>~~eG~~|
|A7<br>~~ee~~<br>~~a~~|DPHY0_DN0<br>~~eG~~<br>~~eG~~|DPHY0<br>~~eG~~<br>~~eG~~|—<br>~~eG~~<br>~~eG~~|Comp_OF_DPHY0_DP0<br>~~eG~~<br>~~eG~~|
|A8<br>~~a ~~<br>~~a ~~<br>~~ee~~|DPHY0_CKP<br> ~~eG~~<br> ~~eG~~<br>~~eG~~|DPHY0<br>~~eG~~<br>~~eG~~<br>~~eG~~|—<br>~~eG~~<br>~~eG~~<br>~~eG~~|True_OF_DPHY0_CKN<br>~~eG~~<br>~~eG~~<br>~~eG~~|
|A9<br>~~ee~~<br>~~**e**e~~|DPHY0_CKN<br>~~eG~~<br>~~eG~~|DPHY0<br>~~eG~~<br>~~eG~~|—<br>~~eG~~<br>~~eG~~|Comp_OF_DPHY0_CKP<br>~~eG~~<br>~~eG~~|
|B1<br>~~ee~~<br>~~**e**e~~|DPHY1_DP0<br>~~eG~~<br>~~eG~~|DPHY1<br>~~eG~~<br>~~eG~~|—<br>~~eG~~<br>~~eG~~|True_OF_DPHY1_DN0<br>~~eG~~<br>~~eG~~|
|B2<br>~~**e**e~~|DPHY1_DN0<br>~~eG~~|DPHY1<br>~~eG~~|—<br>~~eG~~<br>~~G~~|Comp_OF_DPHY1_DP0<br>~~eG~~<br>~~G~~|
|B3<br>~~a~~|DPHY1_DN1<br>~~eG~~|DPHY1<br>~~eG~~|—<br>~~eG~~|Comp_OF_DPHY1_DP1<br>~~eG~~|
|B4<br>~~a ~~<br>~~a ~~<br>~~ee~~|DPHY1_DN3<br> ~~eG~~<br> ~~eG~~<br>~~eG~~|DPHY1<br>~~eG~~<br>~~eG~~<br>~~eG~~|—<br>~~eG~~<br>~~eG~~<br>~~eG~~|Comp_OF_DPHY1_DP3<br>~~eG~~<br>~~eG~~<br>~~eG~~|
|B5<br>~~ee~~<br>~~**e**e~~|GNDPLL_DPHYx<br>~~eG~~<br>~~eG~~|GND<br>~~eG~~<br>~~eG~~|—<br>~~eG~~<br>~~eG~~|—<br>~~eG~~<br>~~eG~~|
|B6<br>~~ee~~<br>~~**e**e~~|DPHY0_DP2<br>~~eG~~<br>~~eG~~|DPHY0<br>~~eG~~<br>~~eG~~|—<br>~~eG~~<br>~~eG~~|True_OF_DPHY0_DN2<br>~~eG~~<br>~~eG~~|
|B7<br>~~**e**e~~|DPHY0_DP0<br>~~eG~~|DPHY0<br>~~eG~~|—<br>~~eG~~<br>~~G~~|True_OF_DPHY0_DN0<br>~~eG~~<br>~~G~~|
|B8<br>~~a~~|DPHY0_DP1<br>~~eG~~|DPHY0<br>~~eG~~|—<br>~~eG~~|True_OF_DPHY0_DN1<br>~~eG~~|
|B9<br>~~a ~~<br>~~a ~~|DPHY0_DN1<br> ~~eG~~<br> ~~eG~~|DPHY0<br>~~eG~~<br>~~eG~~|—<br>~~eG~~<br>~~eG~~|Comp_OF_DPHY0_DP1<br>~~eG~~<br>~~eG~~|
|C1<br>~~a ~~<br>~~**e**e~~|DPHY1_DP2<br> ~~eG~~<br>~~eG~~|DPHY1<br>~~eG~~<br>~~eG~~|—<br>~~eG~~<br>~~eG~~|True_OF_DPHY1_DN2<br>~~eG~~<br>~~eG~~|
|C2<br>~~**e**e~~|DPHY1_DN2<br>~~eG~~|DPHY1<br>~~eG~~|—<br>~~eG~~|Comp_OF_DPHY1_DP2<br>~~eG~~|
|C3<br>~~**e**e~~|GNDA_DPHY1<br>~~eG~~|DPHY1<br>~~eG~~|—<br>~~eG~~<br>~~G~~|—<br>~~eG~~<br>~~G~~|
|C4<br>~~a~~<br>~~ee~~|VCCPLL_DPHY1<br>~~eG~~|DPHY1<br>~~eG~~|—<br>~~eG~~|—<br>~~eG~~|
|C5<br>~~a ~~<br>~~ee~~<br>~~**e**e~~|GND<br> ~~eG~~<br>~~eG~~|GND<br>~~eG~~<br>~~eG~~|—<br>~~eG~~<br>~~eG~~|—<br>~~eG~~<br>~~eG~~|
|C6<br>~~ee~~<br>~~**e**e~~|VCCPLL_DPHY0<br>~~eG~~|DPHY0<br>~~eG~~|—<br>~~eG~~|—<br>~~eG~~|
|C7<br>~~**e**e~~<br>~~a~~|GNDA_DPHY0<br>~~eG~~|DPHY0<br>~~eG~~|—<br>~~eG~~<br>~~G~~|—<br>~~eG~~<br>~~G~~|
|C8<br>~~aa~~|DPHY0_DP3<br>~~en~~|DPHY0<br>~~Ge~~|—|True_OF_DPHY0_DN3|
|C9<br>~~aa~~<br>~~ee~~|DPHY0_DN3<br>~~en~~|DPHY0<br>~~Ge~~|—|Comp_OF_DPHY0_DP3|
|D1<br>~~a~~<br>~~ee~~<br>~~**e**e~~|PB34A<br>~~en~~<br>~~eG~~|1<br>~~Ge~~<br>~~eG~~|GR_PCLK1_0<br>~~eG~~|True_OF_PB34B<br>~~eG~~|
|D2<br>~~ee~~<br>~~**e**e~~|PB34B<br>~~eG~~|1<br>~~eG~~|—<br>~~eG~~|Comp_OF_PB34A<br>~~eG~~|
|D3<br>~~**e**e~~<br>~~a~~|VCCA_DPHY1<br>~~eG~~|DPHY1<br>~~eG~~|—<br>~~eG~~<br>~~G~~|—<br>~~eG~~<br>~~G~~|
|D4<br>~~a~~<br>~~ee~~|GND<br>~~G~~|GND<br>~~G~~|—|—|
|D5<br>~~a~~<br>~~ee~~<br>~~a~~|VCCAUX<br>~~G~~<br>~~en~~|VCCAUX<br>~~G~~<br>~~Ge~~|—|—|
|D6<br>~~ee~~<br>~~a~~<br>~~**e**e~~|GND<br>~~G~~<br>~~en~~<br>~~eG~~|GND<br>~~G~~<br>~~Ge~~<br>~~eG~~|—<br>~~eG~~|—<br>~~eG~~|
|D7<br>~~a~~<br>~~**e**e~~|VCCA_DPHY0<br>~~en~~<br>~~eG~~|DPHY0<br>~~Ge~~<br>~~eG~~|—<br>~~eG~~|—<br>~~eG~~|
|D8<br>~~**e**e~~<br>~~a~~|PB16B<br>~~eG~~|2<br>~~eG~~|PCLKC2_0<br>~~eG~~<br>~~G~~|Comp_OF_PB16A<br>~~eG~~<br>~~G~~|
|D9<br>~~a~~<br>~~ee~~|PB16A<br>~~G~~|2<br>~~G~~|PCLKT2_0|True_OF_PB16B|
|E1<br>~~a~~<br>~~ee~~<br>~~a~~|PB38A<br>~~G~~<br>~~en~~|1<br>~~G~~<br>~~Ge~~|—|True_OF_PB38B|
|E2<br>~~ee~~<br>~~a~~<br>~~**e**e~~|PB38B<br>~~G~~<br>~~en~~<br>~~eG~~|1<br>~~G~~<br>~~Ge~~<br>~~eG~~|—<br>~~eG~~|Comp_OF_PB38A<br>~~eG~~|
|E3<br>~~a~~<br>~~**e**e~~|VCC<br>~~en~~<br>~~eG~~|VCC<br>~~Ge~~<br>~~eG~~|—<br>~~eG~~|—<br>~~eG~~|
|E4<br>~~**e**e~~<br>~~ee~~|VCC<br>~~eG~~<br>~~eG~~|VCC<br>~~eG~~<br>~~eG~~|—<br>~~eG~~<br>~~G~~<br>~~eG~~|—<br>~~eG~~<br>~~G~~<br>~~eG~~|
|E5<br>~~ee~~|GND<br>~~eG~~|GND<br>~~eG~~|—<br>~~eG~~|—<br>~~eG~~|
|E6<br>~~ee~~<br>~~a~~|VCCIO2<br>~~eG~~|2<br>~~eG~~|—<br>~~eG~~|—<br>~~eG~~|
© 2015-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02007-1.8
51
**CrossLink Family Data Sheet**
**Table 5.4 csfBGA81 Pinout** _(Continued)_
|**Pin Number**<br>~~a~~|**Pin Function**<br>~~Ge~~|**Bank**<br>~~Ge~~|**Dual Function**<br>~~GO~~|**Differential**<br>~~CO~~|
|---|---|---|---|---|
|E7<br>~~a~~<br>~~GG~~|PB12B<br>~~Ge~~<br>~~GG~~|2<br>~~Ge~~<br>~~GG~~|GPLLC2_0<br>~~GO~~<br>~~GG~~|Comp_OF_PB12A<br>~~GG~~<br>~~CO~~<br>~~GO~~|
|E8<br>~~CG~~|PB6B<br>~~CG~~|2<br>~~CG~~|—<br>~~CG~~|Comp_OF_PB6A<br>~~CO~~<br>~~CG~~<br>~~GO~~|
|E9<br>~~GG~~<br>~~a~~|PB6A<br>~~GG~~<br>|2<br>~~GG~~<br>|GR_PCLK2_0<br>~~GG~~<br>|True_OF_PB6B<br>~~GO~~<br>~~GG~~<br>~~**(**~~<br>|
|F1<br>~~GG~~<br>~~a~~<br>~~a~~|PB50<br>~~GG~~<br>~~GG~~<br>|0<br>~~GG~~<br>~~GG~~<br>|MOSI<br>~~GG~~<br>~~GG~~<br>|—<br>~~GG~~<br>~~GG~~<br>~~**(**~~<br>|
|F2<br>~~a ~~<br>~~a~~|PB48<br> ~~GG~~<br>~~GG~~|0<br>~~GG~~<br>~~GG~~|PCLKT0_1/USER_SCL<br>~~GG~~<br>~~GG~~|—<br>~~GG~~<br>~~**(**~~<br>~~GG~~|
|F3<br>~~a ~~<br>~~GC~~|VCCIO1<br> ~~GG~~<br>~~GC~~|1<br>~~GG~~<br>~~GC~~|—<br>~~GG~~<br>~~GC~~|—<br>~~**(**~~<br>~~GG~~<br>~~GC~~<br>~~CO~~|
|F4<br>~~eG~~|GND<br>~~eG~~|GND<br>~~eG~~|—<br>~~eG~~|—<br>~~eG~~<br>~~CO~~<br>~~CO~~|
|F5<br>~~eG~~|GNDGPLL<br>~~eG~~|GND<br>~~eG~~|—<br>~~eG~~|—<br>~~CO~~<br>~~eG~~<br>~~CO~~<br>~~CO~~|
|F6<br>~~CG~~|VCCIO2<br>~~CG~~|2<br>~~CG~~|—<br>~~CG~~|—<br>~~CO~~<br>~~CG~~<br>~~CO~~<br>~~GO~~|
|F7<br>~~eG~~|PB12A<br>~~eG~~|2<br>~~eG~~|GPLLT2_0<br>~~eG~~|True_OF_PB12B<br>~~CO~~<br>~~eG~~<br>~~GO~~<br>~~GO~~|
|F8<br>~~eG~~|PB2B<br>~~eG~~|2<br>~~eG~~|—<br>~~eG~~|Comp_OF_PB2A<br>~~GO~~<br>~~eG~~<br>~~GO~~<br>~~CO~~|
|F9<br>~~CG~~|PB2A<br>~~CG~~|2<br>~~CG~~|—<br>~~CG~~|True_OF_PB2B<br>~~GO~~<br>~~CG~~<br>~~CO~~<br>~~CO~~|
|G1<br>~~CG~~<br>~~a~~|PB52<br>~~CG~~<br>|0<br>~~CG~~<br>|SPI_SS/CSN/SCL<br>~~CG~~<br>|—<br>~~CO~~<br>~~CG~~<br>~~CO~~<br>~~CO~~<br>|
|G2<br>~~CG~~<br>~~a~~|CRESET_B<br>~~CG~~<br>|0<br>~~CG~~<br>|—<br>~~CG~~<br>|—<br>~~CO~~<br>~~CG~~<br>~~CO~~<br>|
|G3<br>~~a GC~~<br>~~a~~|VCCIO0<br>~~GC~~<br>|0<br>~~GC~~<br>|—<br>~~GC~~<br>|—<br>~~CO~~<br>~~GC~~<br>~~**(**~~<br>|
|G4<br>~~a GC~~<br>~~a~~<br>~~a~~|VCCIO1<br>~~GC~~<br>~~GG~~<br>|1<br>~~GC~~<br>~~GG~~<br>|—<br>~~GC~~<br>~~GG~~<br>|—<br>~~CO~~<br>~~GC~~<br>~~GG~~<br>~~**(**~~<br>|
|G5<br>~~a ~~<br>~~a~~|VCCGPLL<br> ~~GG~~<br>~~GG~~|VCCGPLL<br>~~GG~~<br>~~GG~~|—<br>~~GG~~<br>~~GG~~|—<br>~~GG~~<br>~~**(**~~<br>~~GG~~|
|G6<br>~~a ~~<br>~~GC~~|PB29B<br> ~~GG~~<br>~~GC~~|1<br>~~GG~~<br>~~GC~~|PCLKC1_0<br>~~GG~~<br>~~GC~~|Comp_OF_PB29A<br>~~**(**~~<br>~~GG~~<br>~~GC~~<br>~~CO~~|
|G7<br>~~eG~~|PB29A<br>~~eG~~|1<br>~~eG~~|PCLKT1_0<br>~~eG~~|True_OF_PB29B<br>~~eG~~<br>~~CO~~<br>~~CO~~|
|G8<br>~~eG~~|PB2D<br>~~eG~~|2<br>~~eG~~|MIPI_CLKC2_0<br>~~eG~~|Comp_OF_PB2C<br>~~CO~~<br>~~eG~~<br>~~CO~~|
|G9<br>~~GC~~|PB2C<br>~~GC~~|2<br>~~GC~~|MIPI_CLKT2_0<br>~~GC~~|True_OF_PB2D<br>~~CO~~<br>~~GC~~|
|H1<br>~~GO~~|PB53<br>~~GO~~|0<br>~~GO~~|SPI_SCK/MCK/SDA<br>~~GO~~|—<br>~~GO~~|
|H2<br>~~GO~~|PB49<br>~~GO~~|0<br>~~GO~~|PMU_WKUPN/CDONE<br>~~GO~~|—<br>~~GO~~|
|H3<br>~~pf~~<br>~~es~~|PB43D<br>~~pf~~<br>~~eG~~|1<br>~~pf~~<br>~~eG~~|—<br>~~pf~~<br>~~eG~~|Comp_OF_PB43C<br>~~pf~~<br>~~eG~~|
|H4<br>~~pf~~<br>~~es~~<br>~~es~~|PB38D<br>~~pf~~<br>~~eG~~<br>~~eG~~|1<br>~~pf~~<br>~~eG~~<br>~~eG~~|—<br>~~pf~~<br>~~eG~~<br>~~eG~~|Comp_OF_PB38C<br>~~pf~~<br>~~eG~~<br>~~eG~~|
|H5<br>~~es~~<br>~~es~~|PB34D<br>~~eG~~<br>~~eG~~|1<br>~~eG~~<br>~~eG~~|MIPI_CLKC1_0<br>~~eG~~<br>~~eG~~|Comp_OF_PB34C<br>~~eG~~<br>~~eG~~|
|H6<br>~~es~~<br>~~a~~|PB29D<br>~~eG~~<br>~~GD~~|1<br>~~eG~~<br>~~GD~~|PCLKC1_1<br>~~eG~~<br>~~GD~~|Comp_OF_PB29C<br>~~eG~~<br>~~GD~~|
|H7<br>~~a ~~<br>~~a~~|PB16D<br> ~~GD~~<br>~~GC~~|2<br>~~GD~~<br>~~GC~~|PCLKC2_1<br>~~GD~~<br>~~GC~~|Comp_OF_PB16C<br>~~GD~~<br>~~GC~~|
|H8<br>~~a ~~<br>~~a~~|PB6D<br> ~~GC~~<br>~~GC~~|2<br>~~GC~~<br>~~GC~~|—<br>~~GC~~<br>~~GC~~|Comp_OF_PB6C<br>~~GC~~<br>~~GC~~|
|H9<br>~~a ~~<br>~~GC~~|PB6C<br> ~~GC~~<br>~~GC~~|2<br>~~GC~~<br>~~GC~~|—<br>~~GC~~<br>~~GC~~|True_OF_PB6D<br>~~GC~~<br>~~GC~~<br>~~GO~~|
|J1<br>~~GG~~|PB51<br>~~GG~~|0<br>~~GG~~|MISO<br>~~GG~~|—<br>~~GG~~<br>~~GO~~<br>~~GO~~|
|J2<br>~~GG~~|PB47<br>~~GG~~|0<br>~~GG~~|PCLKT0_0/USER_SDA<br>~~GG~~|—<br>~~GO~~<br>~~GG~~<br>~~GO~~<br>~~CO~~|
|J3<br>~~GG~~|PB43C<br>~~GG~~|1<br>~~GG~~|—<br>~~GG~~|True_OF_PB43D<br>~~GO~~<br>~~GG~~<br>~~CO~~|
|J4<br>~~GO~~|PB38C<br>~~GO~~|1<br>~~GO~~|—<br>~~GO~~|True_OF_PB38D<br>~~CO~~<br>~~GO~~|
|J5<br>~~GO~~|PB34C<br>~~GO~~|1<br>~~GO~~|MIPI_CLKT1_0<br>~~GO~~|True_OF_PB34D<br>~~GO~~|
|J6<br>~~pf~~<br>~~es~~|PB29C<br>~~pf~~<br>~~eG~~|1<br>~~pf~~<br>~~eG~~|PCLKT1_1<br>~~pf~~<br>~~eG~~|True_OF_PB29D<br>~~pf~~<br>~~eG~~|
|J7<br>~~pf~~<br>~~es~~<br>~~es~~|PB16C<br>~~pf~~<br>~~eG~~<br>~~eG~~|2<br>~~pf~~<br>~~eG~~<br>~~eG~~|PCLKT2_1<br>~~pf~~<br>~~eG~~<br>~~eG~~|True_OF_PB16D<br>~~pf~~<br>~~eG~~<br>~~eG~~|
|J8<br>~~es~~<br>~~es~~|PB12D<br>~~eG~~<br>~~eG~~|2<br>~~eG~~<br>~~eG~~|—<br>~~eG~~<br>~~eG~~|Comp_OF_PB12C<br>~~eG~~<br>~~eG~~|
|J9<br>~~es~~<br>~~a ~~|PB12C<br>~~eG~~<br> ~~GG~~|2<br>~~eG~~<br>~~GG~~|—<br>~~eG~~<br>~~GG~~|True_OF_PB12D<br>~~eG~~<br>~~GG~~|
© 2015-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
52
FPGA-DS-02007-1.8
**CrossLink Family Data Sheet**
## **5.5. Dual Function Pin Descriptions**
The following table describes the dual functions available to certain pins on the CrossLink device. These pins may alternatively be used as general purpose I/O when the described dual function is not enabled.
**Table 5.5. Dual Function Pin Descriptions**
|**Signal Name**<br>~~a~~|**I/O**|**Description**|
|---|---|---|
|**General Purpose**<br>~~a~~<br>~~pe~~<br>~~ee~~<br>~~a~~|||
|USER_SCL<br>~~ee~~<br>~~a~~|I/O<br>~~ee~~<br>~~ee~~<br>~~ee~~|User Slave I2C0 clock input and Master I2C0 clock output. Enables PMU<br>wake-up via I2C0.<br>~~ee~~|
|USER_SDA<br>~~ee~~<br>~~a~~|I/O<br>~~ee~~<br>~~ee~~<br>~~ee~~|User Slave I2C0 data input and Master I2C0 data output. Enables PMU<br>wakeup via I2C0.<br>~~ee~~|
|PMU_WKUPN<br>~~a~~<br>~~CG~~|—<br>~~ee~~<br>~~ee~~<br>~~CG~~|This pin wakes the PMU from sleep mode when toggled low.<br>~~CG~~|
|**Clock Functions**<br>~~CG~~<br>~~pe~~|||
|GPLL2_0[T, C]_IN|I|General Purpose PLL (GPLL) input pads: T = true and C = complement. These<br>pins can be used to input a reference clock directly to the General Purpose<br>PLL. Thesepins do notprovide direct access to theprimaryclock network.|
|GR_PCLK[Bank]0|I|These pins provide a short General Routing path to the primary clock<br>network, but should only be used when the design has used up all the PCLK<br>pins. These pins should only be used for low speed clocks that are not<br>sensitive to skew. Refer toCrossLink sysCLOCK PLL/DLL Design and Usage<br>Guide(FPGA-TN-02015) for details.|
|PCLK[T/C][Bank]_[num]|I/O|General Purpose Primary CLK pads: [T/C] = True/Complement, [Bank] = (0, 1<br>and 2). These pins provide direct access to the primary and edge clock<br>networks.|
|MIPI_CLK[T/C][Bank]_0|I/O|MIPI D-PHY Reference CLK pads: [T/C] = True/Complement, [Bank] = (0, 1<br>and 2). These pins can be used to input a reference clock directly to the<br>D-PHY PLLs. These pins do not provide direct access to the primary clock<br>network.|
|**Configuration**<br>~~pT~~|||
|CDONE<br>~~pT~~<br>~~a~~|I/O<br>~~pT~~|Open Drain pin. Indicates that the configuration sequence is complete, and<br>the startupsequence is inprogress. HoldingCDONE delays configuration.<br>~~pT~~|
|SPI_SCK<br>~~a~~<br>~~GG~~|I<br>~~GG~~|Input Configuration Clock for configuringCrossLink in Slave SPI mode(SSPI).<br>~~GG~~|
|MCK<br>~~GG~~<br>~~ee~~|O<br>~~GG~~<br>~~ee~~|Output Configuration Clock for configuring CrossLink in Master SPI mode<br>(MSPI).<br>~~GG~~<br>~~ee~~|
|SPI_SS<br>~~ee~~<br>~~GG~~|I<br>~~ee~~<br>~~GG~~|Input ChipSelect for configuringCrossLink in Slave SPI mode(SSPI).<br>~~ee~~<br>~~GG~~|
|CSN<br>~~GG~~<br>~~GG~~|O<br>~~GG~~<br>~~GG~~|Output ChipSelect for configuringCrossLink in Master SPI mode(MSPI).<br>~~GG~~<br>~~GG~~|
|MOSI<br>~~ae~~|I/O<br>~~ae~~|Data Output when configuring CrossLink in Master SPI mode (MSPI), data<br>input when configuringCrossLink in Slave SPI mode(SSPI).<br>~~ae~~|
|MISO<br>~~ae~~|I/O<br>~~ae~~|Data Input when configuring CrossLink in Master SPI mode (MSPI), data<br>output when configuringCrossLink in Slave SPI mode(SSPI).<br>~~ae~~|
|SCL<br>~~GG~~|I/O<br>~~GG~~|Slave I2C clock I/O when configuringCrossLink in I2C mode.<br>~~GG~~|
|SDA<br>~~GG~~|I/O<br>~~GG~~|Slave I2C data I/O when configuringCrossLink in I2C mode.<br>~~GG~~|
© 2015-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02007-1.8
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**CrossLink Family Data Sheet**
## **5.6. Dedicated Function Pin Descriptions**
**Table 5.6. Dedicated Function Pin Descriptions**
|**Signal Name**|**I/O**|**Description**|
|---|---|---|
|**Configuration**|||
|CRESET_B|I|Configuration Reset,active LOW.|
|**MIPI D-PHY**|||
|DPHY[num]_CK[P/N]|I/O|MIPI D-PHY Clock [num] = D-PHY 0 or 1, P = Positive, N = Negative.|
|DPHY[num]_D[P/N][lane]|I/O|MIPI D-PHY Data [num] = D-PHY 0 or 1, P = Positive, N = Negative,<br>Lane = data lane in the D-PHY block 0, 1, 2 or 3.|
© 2015-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02007-1.8
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**CrossLink Family Data Sheet**
## **5.7. Pin Information Summary**
**Table 5.7. Pin Information Summary**
|**Pin Type**<br>~~a~~|**CrossLink**<br>~~pd~~|**CrossLink**<br>~~pd~~|**CrossLink**<br>~~pd~~|**CrossLink**<br>~~pd~~|**CrossLink**<br>~~pd~~|
|---|---|---|---|---|---|
||**WLCSP36**<br>~~pd~~|**ucfBGA64**<br>~~pd~~|**ctfBGA80**<br>~~pd~~|**ckfBGA80**<br>~~pd~~|**csfBGA81**<br>~~pd~~|
|Total General Purpose I/O<br>~~DO~~|17<br>~~DO~~|29<br>~~DO~~|37<br>~~DO~~|37<br>~~DO~~|37<br>~~DO~~|
|VCC/VCCIOx/VCCAUX/VCCGPLL<br>~~DO~~<br>~~a~~|4<br>~~DO~~<br>|8<br>~~DO~~<br>|9<br>~~DO~~<br>|9<br>~~DO~~<br>|10<br>~~DO~~<br>|
|GND<br>~~a~~|2<br>|3<br>|6<br>|6<br>|6<br>|
|D-PHY Clock/Data<br>~~aGO~~|10<br>~~GO~~|20<br>~~GO~~|20<br>~~GO~~|20<br>~~GO~~|20<br>~~GO~~|
|D-PHY VCC<br>~~DO~~<br>~~a~~|1<br>~~DO~~<br>|2<br>~~DO~~<br>|4<br>~~DO~~<br>|4<br>~~DO~~<br>|4<br>~~DO~~<br>|
|D-PHY GND<br>~~a~~|1<br>|1<br>|3<br>|3<br>|3<br>|
|CRESETB<br>~~aGO~~|1<br>~~GO~~|1<br>~~GO~~|1<br>~~GO~~|1<br>~~GO~~|1<br>~~GO~~|
|**Total Balls**<br>~~pO~~|**36**<br>~~pO~~|**64**<br>~~pO~~|**80**<br>~~pO~~|**80**<br>~~pO~~|**81**<br>~~pO~~|
|**General Purpose I/Oper Bank**<br>~~pO~~<br>~~pT~~||||||
|Bank 0<br>~~pT~~<br>~~a~~|7<br>~~pT~~|7<br>~~pT~~|7<br>~~pT~~|7<br>~~pT~~|7<br>~~pT~~|
|Bank 1<br>~~GO~~|0<br>~~GO~~|10<br>~~GO~~|14<br>~~GO~~|14<br>~~GO~~|14<br>~~GO~~|
|Bank 2<br>~~GO~~<br>~~eG~~|10<br>~~GO~~<br>~~eG~~|12<br>~~GO~~<br>~~eG~~|16<br>~~GO~~<br>~~eG~~|16<br>~~GO~~<br>~~eG~~|16<br>~~GO~~<br>~~eG~~|
|**Total General Purpose Single Ended I/O**<br>~~po~~|**17**<br>~~po~~|**29**<br>~~po~~|**37**<br>~~po~~|**37**<br>~~po~~|**37**<br>~~po~~|
|**Differential I/O Pairs per Bank**<br>~~po~~||||||
|Bank 0<br>~~Re~~|0<br>~~Re~~|0<br>~~Re~~|0<br>~~Re~~|0<br>~~Re~~|0<br>~~Re~~|
|Bank 1<br>~~Re~~<br>~~ee~~|0<br>~~Re~~<br>~~ee~~|5<br>~~Re~~<br>~~ee~~|7<br>~~Re~~<br>~~ee~~|7<br>~~Re~~<br>~~ee~~|7<br>~~Re~~<br>~~ee~~|
|Bank 2<br>~~RS~~|5<br>~~RS~~|6<br>~~RS~~|8<br>~~RS~~|8<br>~~RS~~|8<br>~~RS~~|
|**Total General Purpose Differential I/O Pairs**<br>~~RS~~<br>~~a~~|**5**<br>~~RS~~|**11**<br>~~RS~~|**15**<br>~~RS~~|**15**<br>~~RS~~|**15**<br>~~RS~~|
© 2015-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02007-1.8
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**CrossLink Family Data Sheet**
LIF-MD XXXX-X XXXXX X TR
## **6. CrossLink Part Number Description**
**Device Family** CrossLink FPGA **Logic Capacity** 6000 = 6000 LUTs ~~=I~~ **Speed** 6 = Fastest
## **Tape & Reel**
<blank>=No Tape & Reel TR=Tape & Reel (see note in section 6.1)
## **Grade**
I = Industrial
## **Package**
UWG36 = 36-ball WLCSP UMG64 = 64-ball ucfBGA MG81 = 81-ball csfBGA JMG80 = 80-ball ctfBGA KMG80 = 80-ball ckfBGA
## **6.1. Ordering Part Numbers**
|**Part Number**<br>~~==S=>=~~|**Grade**<br>~~==S=>=~~|**Package**<br>~~==S=>=~~|**Pins**<br>~~==S=>=~~|**Temp.**<br>~~==S=>=~~|**LUTs (K)**<br>~~==S=>=~~|
|---|---|---|---|---|---|
|LIF-MD6000-6UWG36ITR<br>~~==S=>=~~|–6<br>~~==S=>=~~|Lead free WLCSP<br>~~==S=>=~~|36<br>~~==S=>=~~|Industrial<br>~~==S=>=~~|5.9<br>~~==S=>=~~|
|LIF-MD6000-6UMG64I<br>~~==S=>=~~|–6<br>~~==S=>=~~|Lead free ucfBGA<br>~~==S=>=~~|64<br>~~==S=>=~~|Industrial<br>~~==S=>=~~|5.9<br>~~==S=>=~~|
|LIF-MD6000-6MG81I<br>~~==S=>=~~|–6<br>~~==S=>=~~|Lead free csfBGA<br>~~==S=>=~~|81<br>~~==S=>=~~|Industrial<br>~~==S=>=~~|5.9<br>~~==S=>=~~|
|LIF-MD6000-6JMG80I<br>~~==S=>=~~|–6<br>~~==S=>=~~|Lead free ctfBGA<br>~~==S=>=~~|80<br>~~==S=>=~~|Industrial<br>~~==S=>=~~|5.9<br>~~==S=>=~~|
|LIF-MD6000-6KMG80I<br>~~==S=>=~~|-6<br>~~==S=>=~~|Lead free ckfBGA<br>~~==S=>=~~|80<br>~~==S=>=~~|Industrial<br>~~==S=>=~~|5.9<br>~~==S=>=~~|
© 2015-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02007-1.8
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**CrossLink Family Data Sheet**
## **References**
For more information, refer to the following technical notes:
- CrossLink High-Speed I/O Interface (FPGA-TN-02012)
- CrossLink Hardware Checklist (FPGA-TN-02013)
- CrossLink Programming and Configuration Usage Guide (FPGA-TN-02014)
- CrossLink sysCLOCK PLL/DLL Design and Usage Guide (FPGA-TN-02015)
- CrossLink sysI/O Usage Guide (FPGA-TN-02016)
- CrossLink Memory Usage Guide (FPGA-TN-02017)
- Power Management and Calculation for CrossLink Devices (FPGA-TN-02018)
- CrossLink I2C Hardened IP Usage Guide (FPGA-TN-02019)
- Advanced CrossLink I2C Hardened IP Reference Guide (FPGA-TN-02020)
For package information, refer to the following technical notes:
- PCB Layout Recommendations for BGA Packages (TN1074)
- Solder Reflow Guide for Surface Mount Devices (FPGA-TN-12041, previously TN1076)
- Wafer-Level Chip-Scale Package Guide (TN1242)
- Thermal Management (FPGA-TN-02044)
- Package Diagrams (FPGA-DS-02053)
For further information on interface standards refer to the following websites:
- JEDEC Standards (LVTTL, LVCMOS): www.jedec.org
- MIPI Standards (D-PHY): www.mipi.org
## **Technical Support**
For assistance, submit a technical support case at www.latticesemi.com/techsupport.
© 2015-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02007-1.8
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**CrossLink Family Data Sheet**
## **Revision History**
## **Revision 1.8, January 2021**
|**Section**|**Change Summary**|
|---|---|
|DC and Switching Characteristics|Corrected table formatting error. Removed duplicated section fromTable 4.13. CrossLink<br>External SwitchingCharacteristics.|
|**Section**|**Change Summary**|
|---|---|
|—|Added Disclaimers section.|
|Architecture Overview|Revised referenced diagram to Figure 3.12 in Edge Clocks section.|
|DC and Switching Characteristics|<br>Added Over recommended operating conditions to the following sections:<br><br>Power Supply Ramp Rates<br><br>Power-On-Reset Voltage Levels<br><br>Power Management Unit (PMU) Timing<br><br>sysI/O Recommended Operating Conditions<br><br>LVDS/subLVDS/SLVS200<br><br>CrossLink External Switching Characteristics<br><br>Hardened MIPI D-PHY Performance<br><br>User I2C<br><br>Added footnote to Table 4.9. sysI/O Single-Ended DC Electrical Characteristics1.<br><br>Revised footnote 7 in Table 4.12. CrossLink Maximum I/O Buffer Speed.<br><br>Updated footnotes in Table 4.13. CrossLink External Switching Characteristics 3,4.<br><br>Updated Table 4.20. CrossLink sysCONFIG Port Timing Specifications.<br><br>Changed tPGRM Min value.<br><br>Added footnote 3.|
|Pinout Information|In the Table 5.5. Dual Function Pin Descriptions table, added information to GR_PCLK[Bank]0<br>description.|
|References|<br>Updated document number of PCB Layout Recommendations for BGA Packages.<br><br>Fixed link to the Thermal Management document and updated document number.<br><br>Provided document number of Package Diagrams.|
|Revision History|Updated format.|
|Back Cover|Updated template.|
**Revision 1.5, July 2018**
|**Section**<br>~~a~~|**Change Summary**|
|---|---|
|DC and Switching Characteristics<br>~~a~~|<br>Updated Table 4.1. Absolute Maximum Ratings. Added footnote 4 to VCCAUXparameters.<br><br>Updated Table 4.2. Recommended Operating Conditions. Added footnote 3 to VCCAUX<br>parameters.<br><br>Updated Table 4.13. CrossLink External Switching Characteristics. Revised tSU_GDDRX_MP<br>and tHD_GDDRX_MPconditions under I/O MIPI D-PHY Rx with 1:8 or 1:16 Gearing.|
© 2015-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
58
FPGA-DS-02007-1.8
**CrossLink Family Data Sheet**
**Revision 1.4, February 2018**
|**Section**|**Change Summary**|
|---|---|
|All|Removed Application Examples section and its associated references throughout the<br>document|
|Architecture Overview|<br>General update applied to this section.<br><br>Reordered the list of features supported by the hard D-PHY quads.<br><br>Added Figure 3.3 to Figure 3.6 to the MIPI D-PHY Blocks section.<br><br>Updated the Programmable I/O Banks section.<br><br>Added Bank 0 list of features.<br><br>Added Table 3.1, Table 3.2, Table 3.3, and Table 3.4.<br><br>Updated Programmable FPGA Fabric section.<br><br>Removed FPGA Fabric Overview header.<br><br>Added PFU Blocks section.<br><br>Added Slice section.<br><br>Moved Clocking Overview as a new Clocking Structure (heading 2) section and added<br>contents.<br><br>Moved Embedded Block RAM Overview as a new (heading 2) section and added<br>contents.<br><br>Removed System Resources section.<br><br>Moved Power Management Unit section under Embedded Block RAM Overview.<br><br>Removed Device Configuration section.<br><br>Moved User I2C IP as a new (heading 2) section.<br><br>Added Programming and Configuration section.|
|DC and Switching Characteristics|<br>Updated CrossLink Maximum General Purpose I/O Buffer Speed section. Changed<br>LVTTL33/LVCMOS33 to LVCMOS33/LVTTL33.<br><br>Updated CrossLink External Switching Characteristics section (general update).|
|Pinout Information|Placed captions topinout tables.|
## **Revision 1.3, November 2017**
|**Section**|**Change Summary**|
|---|---|
|Acronyms in This Document|Added entries to the section.|
|Features|<br>Changed footprint to 80-ball ctfBGA (42 mm2).<br><br>Removed Application Examples section and its associated references throughout the<br>document.|
|Product Feature Summary|<br>Added 80-ball ckfBGA (49 mm2) package in Features section.<br><br>Updated note in Table 2.1, Table 2.2, Table 2.3, Table 2.4, Table 2.5, Table 2.6, Table<br>2.7, Table 2.8, and Table 2.9 Added 80 ckfBGA (7.0 x 7.0 mm2, 1 mm) package to Table<br>2.1. CrossLink Feature Summary.|
|Architecture Overview|<br>Updated System Resources section.<br><br>Removed LVCMOS12 (Outputs Only) from CMOS GPIO (Bank 0) section.<br><br>Added information in Device Configuration section.|
© 2015-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02007-1.8
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**CrossLink Family Data Sheet**
|**Section**|**Change Summary**|
|---|---|
|DC and Switching Characteristics|<br>Updated Table 4.1. Absolute Maximum Ratings.<br><br>Changed symbol from VCCPLL to VCCGPLL.<br><br>Removed VCC_DPHY symbol.<br><br>Updated Table 4.2. Recommended Operating Conditions.<br><br>Revised symbols to VCCGPLL.and VCCIO0.<br><br>Added row of VCCIO1/2 symbol.<br><br>Removed row of VCC_DPHYx symbol.<br><br>Removed VCC_DPHY1 from VCCMU_DPHY1parameter description.<br><br>Added notes to Table 4.8. sysI/O Recommended Operating Conditions1 and Table 4.20.<br>CrossLink sysCONFIG Port Timing Specifications.<br><br>Updated link to the LIFMD Product Family Qualification Summary reference in the ESD<br>Performance section.<br><br>Removed VCCIO= 1.2 V between 0≤VIN ≤0.65 * VCCIOcondition from Table 4.5. DC<br>Electrical Characteristics.<br><br>Updated Table 4.6. CrossLink Supply Current.<br><br>Updated ICCMLL_DPHYx, ICCMLL_DPHYx_STDBY, and ICCPLL_DPHY_SLEEP<br>parameters.<br><br>Moved ICCA_DPHY_SLEEP and updated parameter.<br><br>Updated ICCAMLL_DPHYx_SLEEP parameter and unit.<br><br>Updated footnote 4-a, 4-b, and 5-b.<br><br>Updated Table 4.12. CrossLink Maximum I/O Buffer Speed.<br><br>Added ckfBGA80 package in descriptions.<br><br>Changed LVTTL33/LVCMOS to LVTTL33/LVCMOS33.<br><br>Changed VCCIOto VCCIO1/2in LVCMOS12 description.<br><br>Updated the CrossLink External Switching Characteristics section and Table 4.13.<br>CrossLink External Switching Characteristics.<br><br>Removed “Over recommended commercial operating conditions.”<br><br>General update of information under Generic DDR Interfaces2 including the<br>addition of “Generic DDRX1 I/O with Clock and Data Centered at General Purpose<br>Pins (GDDRX1_RX/TX.ECLK.Centered)” and “Generic DDRX1 I/O with Clock and<br>Data Aligned at General Purpose Pins (GDDRX1_RX/TX.ECLK.Aligned” rows<br><br>Added ckfBGA80 package in specific conditions.<br><br>Changed TREFRESHto TCONFIGURATIONin Table 4.21. SRAM Configuration Time from NVCM.|
|Pinout Information|<br>Updated section introduction.<br><br>Updated WLCSP36 Pinout. Changed C4 bank to VCC.<br><br>Updated section to ctfBGA80/ckfBGA80 Pinout and revised pin function of C1, C2, C9,<br>C10, D6, E5, G2, G5, and G7.<br><br>Updated pin function of B5 in csfBGA81 Pinout.<br><br>Updated Pin Information Summarysection.|
|Ordering Part Number|<br>Updated CrossLink Part Number Description section.<br><br>Added LIF-MD6000-6KMG80Ipart number to OrderingPart Numbers section.|
|References|Update reference to the Solder Reflow Guide for Surface Mount Devices document.|
© 2015-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
60
FPGA-DS-02007-1.8
**CrossLink Family Data Sheet**
**Revision 1.2, June 2017**
|**Section**|**Change Summary**|
|---|---|
|Product Feature Summary|Updated Fabric Resources Used in Table 2.1, Table 2.2, Table 2.3, Table 2.4, Table 2.5, Table<br>2.6, and Table 2.9.|
|Architecture Overview|<br>Updated Figure 3.1. CrossLink Device Block Diagram.<br><br>Added row of VCCAUXfor 3.3 V in Table 4.1. Absolute Maximum Ratings and Table 4.2.<br>Recommended OperatingConditions.|
|DC and Switching Characteristics|<br>Added row of C3to Table 4.5. DC Electrical Characteristics.<br><br>Added rows of ICCAMLL_DPHYx, ICCAMLL_DPHYx_STDBY, and ICCAMLL_DPHYx_SLEEPto Table 4.6. CrossLink<br>Supply Current.<br><br>Updated Max value in Table 4.7. PMU Timing.<br><br>Updated values of subLVDS (Input only) and SLVS200 (Input only), and added row of<br>LVDS (Input only) to Table 4.8. sysI/O Recommended Operating Conditions.<br><br>Updated Table 5.10. LVDS/subLVDS1/SLVS200.<br><br>Updated parameter descriptions in Table 4.11. MIPI D-PHY.<br><br>Added row of MIPI D-PHY (LP Mode), and updated Max values of subLVDS and SLVS200<br>in Table 4.12. CrossLink Maximum I/O Buffer Speed.<br><br>Updated conditions in Table 4.13. CrossLink External Switching Characteristics.<br><br>Added rows of fPDand fVCOto Table 4.14. sysCLOCK PLL Timing.<br><br>Updated values in Table 4.15. 1500 Mb/s MIPI_DPHY_X8_RX/TX Timing Table (1500<br>Mb/s > MIPI D-PHY Data Rate > 1200 Mb/s), Table 4.16. 1200 Mb/s<br>MIPI_DPHY_X4_RX/TX Timing Table (1200 Mb/s > MIPI D-PHY Data Rate > 1000 Mb/s)<br>and Table 4.17. 1000 Mb/s MIPI_DPHY_X4_RX/TX Timing Table (1000 Mb/s > MIPI D-<br>PHY Data Rate > 10 Mb/s).<br><br>Updated Typ values of DCHCLKHFand DCHCLKLFin Table 4.18. Internal Oscillators.<br><br>Added row of TDELAY to Table 4.19. User I2C.<br><br>Updated Min value of tSCSin Table 4.20. CrossLink sysCONFIG Port Timing Specifications.<br><br>Updated symbol and parameter in Table 4.21. SRAM Configuration Time from NVCM.<br><br>Included version number in Pinout Information.|
**Revision 1.1, March 2017**
|**Section**|**Change Summary**|
|---|---|
|Architecture Overview|Updated I/O placements on banks containing MIPI interface in Programmable I/O Banks<br>section.|
|DC and Switching Characteristics|<br>Updated Table 4.4. Power-On-Reset Voltage Levels, added row of VPORDN<br><br>Added Note 5 to Table 4.5. DC Electrical Characteristics.<br><br>Updated Table 4.6. CrossLink Supply Current, added notes.<br><br>Updated max values of VTHDand VTHD(subLVDS)in Table 4.10. LVDS/subLVDS1/SLVS200.<br><br>Maximum input frequency values of subLVDS and SLVS200 are TBD in Table 4.12.<br>CrossLink Maximum I/O Buffer Speed.<br><br>Updated Table 4.13. CrossLink External Switching Characteristics.<br><br>Updated min values oftSU_MIPIX4and tHO_MIPIX4in Table 4.16. 1200 Mb/s<br>MIPI_DPHY_X4_RX/TX Timing Table (1200 Mb/s > MIPI D-PHY Data Rate > 1000 Mb/s)<br>and Table 4.17. 1000 Mb/s MIPI_DPHY_X4_RX/TX Timing Table (1000 Mb/s > MIPI D-<br>PHY Data Rate > 10 Mb/s).<br><br>Updated Table 4.20. CrossLink sysCONFIG Port Timing Specifications.<br><br>Updated Table 4.21. SRAM Configuration Time from NVCM.|
|Pinout Information|Updated this section.|
|OrderingPart Numbers|Updated CrossLink Part Number Description.|
© 2015-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02007-1.8
61
**CrossLink Family Data Sheet**
## **Revision 1.0, July 2016**
|**Section**|**Change Summary**|
|---|---|
|All|Updated document number.|
|**Revision 1.0**|**Revision 1.0**|**Revision 1.0, May 2016**|**2016**||
|---|---|---|---|---|
||**Section**|||**Change Summary**|
||All|||First preliminary release.|
© 2015-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
62
FPGA-DS-02007-1.8
www.latticesemi.com
Updated at April 17, 2026
Lattice Semiconductor is a premier developer of low-power, programmable design solutions, specializing in Field-Programmable Gate Arrays (FPGAs) and Programmable Logic Devices (PLDs). Recognized for driving innovation in cost-effective and power-efficient architectures, the company provides essential semiconductor components for consumer, mobile, and industrial design applications. Our selection of Lattice Semiconductor products is focused on their highly regarded FPGA integrated circuits. Devices from industry-leading families like the iCE40, MachXO, and LatticeECP series offer designers an exceptional combination of high system integration and industry-low power consumption. These FPGAs are engineered to handle complex tasks such as sensor management, custom connectivity, and advanced video processing while minimizing overall board footprint. To ensure seamless integration from concept to production, Lattice backs its hardware with a comprehensive support ecosystem. Engineers can accelerate their development cycles utilizing intuitive tools like the Lattice Diamond design software, paired with flexible IP cores and reference designs that reduce design risk and increase system reliability.
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