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LIA-MD6000-6JMG80E
FPGA, CrossLink, PLL37 I/O, 400 MHz, 5936 Cells, 1.14 V to 1.26 V, CTFBGA-80
⚠️ Reference pricing provided. In case of supply shortages, we will connect you with our trusted procurement partners to ensure your project's continuity.
- Manufacturer: LATTICE SEMICONDUCTOR
- Product type: FPGAs
- MSL: MSL 3 - 168 hours
- SVHC: No SVHC (25-Jun-2025)
- FPGA Type: SRAM based FPGA
- FPGA Family: CrossLink
- IC Mounting: Surface Mount
- No. of Pins: 80Pins
- Speed Grade: 6
- No. of I/O's: 37I/O's
- Product Range: CrossLink LIA-MD
- Qualification: AEC-Q100
- Total RAM Bits: 180Kbit
- No.of User I/Os: 37I/O's
- Clock Management: PLL
- Logic Case Style: CTFBGA
- IC Case / Package: CTFBGA
- No. of Macrocells: 5936Macrocells
- I/O Supply Voltage: 3.465V
- No. of Logic Cells: 5936Logic Cells
- Process Technology: 40nm
- No. of Logic Blocks: 5936
- No. of Speed Grades: 6
- Core Supply Voltage Max: 1.26V
- Core Supply Voltage Min: 1.14V
- Operating Frequency Max: 400MHz
- Operating Temperature Max: 125°C
- Operating Temperature Min: -40°C
| Delivery and price | |
|---|---|
| Units per pack | 100 |
| Price | 12.65 € |
| Current stock | 100+ |
| Lead time | 30 days |
Datasheet
## Os
## **CrossLink Automotive Family**
## **Data Sheet**
FPGA-DS-02013 Version 1.2
March 2018
**CrossLink Automotive Family Data Sheet**
## **Contents**
|**Contents**|**Contents**|**Contents**|
|---|---|---|
|Acronyms in This Document ................................................................................................................................................. 5|||
|1.|General Description ...................................................................................................................................................... 6||
||1.1.|Features ............................................................................................................................................................... 6|
|2.|Product Feature Summary ............................................................................................................................................ 7||
|3.|Architecture Overview .................................................................................................................................................. 8||
||3.1.|MIPI D-PHY Blocks ............................................................................................................................................... 9|
||3.2.|Programmable I/O Banks .................................................................................................................................. 13|
||3.3.|sysI/O Buffers .................................................................................................................................................... 15|
||3.3.1.|Programmable PULLMODE Settings ............................................................................................................. 15|
||3.3.2.|Output Drive Strength ................................................................................................................................... 15|
||3.3.3.|On-Chip Termination .................................................................................................................................... 15|
||3.4.|Programmable FPGA Fabric .............................................................................................................................. 16|
||3.4.1.|PFU Blocks ..................................................................................................................................................... 16|
||3.4.2.|Slice ............................................................................................................................................................... 17|
||3.5.|Clocking Structure ............................................................................................................................................. 20|
||3.5.1.|sysCLK PLL ..................................................................................................................................................... 20|
||3.5.2.|Primary Clocks ............................................................................................................................................... 21|
||3.5.3.|Edge Clocks ................................................................................................................................................... 21|
||3.5.4.|Dynamic Clock Enables ................................................................................................................................. 22|
||3.5.5.|Internal Oscillator (OSCI) ............................................................................................................................... 22|
||3.6.|Embedded Block RAM Overview ....................................................................................................................... 23|
||3.7.|Power Management Unit .................................................................................................................................. 23|
||3.7.1.|PMU State Machine ...................................................................................................................................... 24|
||3.8.|User I2C IP .......................................................................................................................................................... 25|
||3.9.|Programming and Configuration ....................................................................................................................... 26|
|4.|DC and Switching Characteristics ................................................................................................................................ 27||
||4.1.|Absolute Maximum Ratings .............................................................................................................................. 27|
||4.2.|Recommended Operating Conditions ............................................................................................................... 27|
||4.3.|Power Supply Ramp Rates ................................................................................................................................. 28|
||4.4.|Power-On-Reset Voltage Levels ........................................................................................................................ 28|
||4.5.|ESD Performance ............................................................................................................................................... 28|
||4.6.|DC Electrical Characteristics .............................................................................................................................. 29|
||4.7.|CrossLink Automotive Supply Current............................................................................................................... 30|
||4.8.|Power Management Unit (PMU) Timing ........................................................................................................... 31|
||4.9.|sysI/O Recommended Operating Conditions .................................................................................................... 31|
||4.10.|sysI/O Single-Ended DC Electrical Characteristics ............................................................................................. 31|
||4.11.|sysI/O Differential Electrical Characteristics ..................................................................................................... 32|
||4.11.1.<br>LVDS/subLVDS/SLVS200 ........................................................................................................................... 32||
||4.11.2.<br>Hardened MIPI D-PHY I/Os ....................................................................................................................... 33||
||4.12.|CrossLink Automotive Maximum General Purpose I/O Buffer Speed ............................................................... 34|
||4.13.|CrossLink Automotive External Switching Characteristics ................................................................................ 35|
||4.14.|sysCLOCK PLL Timing ......................................................................................................................................... 40|
||4.15.|Hardened MIPI D-PHY Performance.................................................................................................................. 41|
||4.16.|Internal Oscillators (HFOSC, LFOSC) .................................................................................................................. 41|
||4.17.|User I2C1............................................................................................................................................................. 41|
||4.18.|CrossLink Automotive sysCONFIG Port Timing Specifications .......................................................................... 42|
||4.19.|SRAM Configuration Time from NVCM ............................................................................................................. 42|
||4.20.|Switching Test Conditions ................................................................................................................................. 43|
|5.|Pinout Information ..................................................................................................................................................... 44||
||5.1.|ctfBGA80/cktBGA80 Pinout ............................................................................................................................... 44|
||5.2.|Dual Function Pin Descriptions ......................................................................................................................... 46|
||5.3.|Dedicated Function Pin Descriptions ................................................................................................................ 47|
© 2015-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
2
FPGA-DS-02013-1.2
**CrossLink Automotive Family Data Sheet**
|5.4.<br>Pin Information Summary ................................................................................................................................. 47|
|---|
|6.<br>CrossLink Automotive Part Number Description ........................................................................................................ 48|
|6.1.<br>Ordering Part Numbers ..................................................................................................................................... 48|
|References .......................................................................................................................................................................... 49|
|Technical Support ............................................................................................................................................................... 49|
|Revision History .................................................................................................................................................................. 50|
## **Figures**
|Figure 3.1. CrossLink Automotive Device Block Diagram ..................................................................................................... 8|Figure 3.1. CrossLink Automotive Device Block Diagram ..................................................................................................... 8|
|---|---|
|Figure 3.2. CrossLink Automotive sysI/O Banking ................................................................................................................ 9|Figure 3.2. CrossLink Automotive sysI/O Banking ................................................................................................................ 9|
|Figure 3.3. MIPI DSI Transmit Interface with Hard D-PHY Module ..................................................................................... 10|Figure 3.3. MIPI DSI Transmit Interface with Hard D-PHY Module ..................................................................................... 10|
|Figure 3.4. MIPI CSI-2 Transmit Interface with Hard D-PHY Module .................................................................................. 11|Figure 3.4. MIPI CSI-2 Transmit Interface with Hard D-PHY Module .................................................................................. 11|
|Figure 3.5. MIPI DSI Receive Interface with Hard D-PHY Module ...................................................................................... 12|Figure 3.5. MIPI DSI Receive Interface with Hard D-PHY Module ...................................................................................... 12|
|Figure 3.6. MIPI CSI-2 Receive Interface with Hard D-PHY Module .................................................................................... 13|Figure 3.6. MIPI CSI-2 Receive Interface with Hard D-PHY Module .................................................................................... 13|
|Figure 3.7. CrossLink Automotive Device Simplified Block Diagram (Top Level) ................................................................ 16|Figure 3.7. CrossLink Automotive Device Simplified Block Diagram (Top Level) ................................................................ 16|
|Figure 3.8. CrossLink Automotive PFU Diagram ................................................................................................................. 17|Figure 3.8. CrossLink Automotive PFU Diagram ................................................................................................................. 17|
|Figure 3.9. Slice Diagram .................................................................................................................................................... 18|Figure 3.9. Slice Diagram .................................................................................................................................................... 18|
|Figure 3.10. Connectivity Supporting LUT5, LUT6, LUT7 and LUT8 .................................................................................... 19|Figure 3.10. Connectivity Supporting LUT5, LUT6, LUT7 and LUT8 .................................................................................... 19|
|Figure 3.11. CrossLink Automotive PLL Block Diagram ....................................................................................................... 20|Figure 3.11. CrossLink Automotive PLL Block Diagram ....................................................................................................... 20|
|Figure 3.12. CrossLink Automotive Clocking Structure ....................................................................................................... 21|Figure 3.12. CrossLink Automotive Clocking Structure ....................................................................................................... 21|
|Figure 3.13. CrossLink Automotive Edge Clock Sources per Bank ...................................................................................... 22|Figure 3.13. CrossLink Automotive Edge Clock Sources per Bank ...................................................................................... 22|
|Figure 3.14. CrossLink Automotive OSCI Component Symbol ............................................................................................ 22|Figure 3.14. CrossLink Automotive OSCI Component Symbol ............................................................................................ 22|
|Figure 3.15. CrossLink Automotive MIPI D-PHY Block ........................................................................................................ 24|Figure 3.15. CrossLink Automotive MIPI D-PHY Block ........................................................................................................ 24|
|Figure 3.16. CrossLink Automotive PMU State Machine .................................................................................................... 24|Figure 3.16. CrossLink Automotive PMU State Machine .................................................................................................... 24|
|Figure 4.1. Receiver RX.CLK.Centered Waveforms ............................................................................................................. 38|Figure 4.1. Receiver RX.CLK.Centered Waveforms ............................................................................................................. 38|
|Figure 4.2. Receiver RX.CLK.Aligned Input Waveforms ...................................................................................................... 38|Figure 4.2. Receiver RX.CLK.Aligned Input Waveforms ...................................................................................................... 38|
|Figure 4.3. Transmit TX.CLK.Centered Output Waveforms ................................................................................................ 38|Figure 4.3. Transmit TX.CLK.Centered Output Waveforms ................................................................................................ 38|
|Figure 5.5. DDRX71, DDRX141 Video Timing Waveforms .................................................................................................. 39|Figure 5.5. DDRX71, DDRX141 Video Timing Waveforms .................................................................................................. 39|
|Figure 4.6. Output Test Load, LVTTL and LVCMOS Standards ............................................................................................ 43|Figure 4.6. Output Test Load, LVTTL and LVCMOS Standards ............................................................................................ 43|
© 2015-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02013-1.2
3
**CrossLink Automotive Family Data Sheet**
## **Tables**
|Table 2.1. CrossLink Automotive Feature Summary ............................................................................................................. 7|Table 2.1. CrossLink Automotive Feature Summary ............................................................................................................. 7|
|---|---|
|Table 3.1. CrossLink Automotive Output Support per Bank Basis ...................................................................................... 14|Table 3.1. CrossLink Automotive Output Support per Bank Basis ...................................................................................... 14|
|Table 3.2. CrossLink Automotive Input Support per Bank Basis ......................................................................................... 15|Table 3.2. CrossLink Automotive Input Support per Bank Basis ......................................................................................... 15|
|Table 3.3. Drive Strength Values ......................................................................................................................................... 15|Table 3.3. Drive Strength Values ......................................................................................................................................... 15|
|Table 3.4. Slice Signal Descriptions ..................................................................................................................................... 19|Table 3.4. Slice Signal Descriptions ..................................................................................................................................... 19|
|Table 3.5. CrossLink Automotive PLL Port Definition ......................................................................................................... 20|Table 3.5. CrossLink Automotive PLL Port Definition ......................................................................................................... 20|
|Table 3.6. OSCI Component Port Definition ....................................................................................................................... 22|Table 3.6. OSCI Component Port Definition ....................................................................................................................... 22|
|Table 3.7. OSCI Component Attribute Definition ............................................................................................................... 22|Table 3.7. OSCI Component Attribute Definition ............................................................................................................... 22|
|Table 3.8. sysMEM Block Configurations ............................................................................................................................ 23|Table 3.8. sysMEM Block Configurations ............................................................................................................................ 23|
|Table 3.9. CrossLink Automotive sysCONFIG Pins .............................................................................................................. 26|Table 3.9. CrossLink Automotive sysCONFIG Pins .............................................................................................................. 26|
|Table 4.1. Absolute Maximum Ratings|Table 4.1. Absolute Maximum Ratings1, 2, 3......................................................................................................................... 27|
|Table 4.2. Recommended Operating Conditions|Table 4.2. Recommended Operating Conditions1, 2............................................................................................................ 27|
|Table 4.3. Power Supply Ramp Rates|Table 4.3. Power Supply Ramp Rates1................................................................................................................................ 28|
|Table 4.4. Power-On-Reset Voltage Levels|Table 4.4. Power-On-Reset Voltage Levels1, 3, 4................................................................................................................... 28|
|Table 4.5. DC Electrical Characteristics ............................................................................................................................... 29|Table 4.5. DC Electrical Characteristics ............................................................................................................................... 29|
|Table 4.6. CrossLink Automotive Supply Current ............................................................................................................... 30|Table 4.6. CrossLink Automotive Supply Current ............................................................................................................... 30|
|Table 4.7. PMU Timing* ...................................................................................................................................................... 31|Table 4.7. PMU Timing* ...................................................................................................................................................... 31|
|Table 4.8. sysI/O Recommended Operating Conditions|Table 4.8. sysI/O Recommended Operating Conditions1.................................................................................................... 31|
|Table 5.9. sysI/O Single-Ended DC Electrical Characteristics .............................................................................................. 31|Table 5.9. sysI/O Single-Ended DC Electrical Characteristics .............................................................................................. 31|
|Table 4.10. LVDS/subLVDS|Table 4.10. LVDS/subLVDS1/SLVS2001, 2.............................................................................................................................. 32|
|Table 4.11. MIPI D-PHY ....................................................................................................................................................... 33|Table 4.11. MIPI D-PHY ....................................................................................................................................................... 33|
|Table 4.12. CrossLink Automotive Maximum I/O Buffer Speed ......................................................................................... 34|Table 4.12. CrossLink Automotive Maximum I/O Buffer Speed ......................................................................................... 34|
|Table 4.13. CrossLink Automotive External Switching Characteristics|Table 4.13. CrossLink Automotive External Switching Characteristics4, 5........................................................................... 35|
|Table 4.14. sysCLOCK PLL Timing ........................................................................................................................................ 40|Table 4.14. sysCLOCK PLL Timing ........................................................................................................................................ 40|
|Table 4.15. 1500 Mb/s MIPI_DPHY_X8_RX/TX Timing Table (1500 Mb/s > MIPI D-PHY Data Rate > 1200 Mb/s) ............ 41|Table 4.15. 1500 Mb/s MIPI_DPHY_X8_RX/TX Timing Table (1500 Mb/s > MIPI D-PHY Data Rate > 1200 Mb/s) ............ 41|
|Table 4.16. 1200 Mb/s MIPI_DPHY_X4_RX/TX Timing Table (1200 Mb/s > MIPI D-PHY Data Rate > 1000 Mb/s) ............ 41|Table 4.16. 1200 Mb/s MIPI_DPHY_X4_RX/TX Timing Table (1200 Mb/s > MIPI D-PHY Data Rate > 1000 Mb/s) ............ 41|
|Table 5.17. 1000 Mb/s MIPI_DPHY_X4_RX/TX Timing Table (1000 Mb/s > MIPI D-PHY Data Rate > 10 Mb/s) ................ 41|Table 5.17. 1000 Mb/s MIPI_DPHY_X4_RX/TX Timing Table (1000 Mb/s > MIPI D-PHY Data Rate > 10 Mb/s) ................ 41|
|Table 5.18. Internal Oscillators ........................................................................................................................................... 41|Table 5.18. Internal Oscillators ........................................................................................................................................... 41|
|Table 5.19. User I|Table 5.19. User I2C1........................................................................................................................................................... 41|
|Table 5.20. CrossLink Automotive sysCONFIG Port Timing Specifications ......................................................................... 42|Table 5.20. CrossLink Automotive sysCONFIG Port Timing Specifications ......................................................................... 42|
|Table 5.21. SRAM Configuration Time from NVCM ............................................................................................................ 42|Table 5.21. SRAM Configuration Time from NVCM ............................................................................................................ 42|
|Table 4.22. Test Fixture Required Components, Non-Terminated Interfaces .................................................................... 43|Table 4.22. Test Fixture Required Components, Non-Terminated Interfaces .................................................................... 43|
© 2015-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02013-1.2
4
**CrossLink Automotive Family Data Sheet**
## **Acronyms in This Document**
A list of acronyms used in this document.
|~~es~~||
|---|---|
|**Acronym **<br>~~es~~|**Definition**|
|AR<br>~~es~~<br>~~a~~<br>~~es~~|Augmented Reality|
|ASIC<br>~~es~~<br>~~es~~|Application-Specific Integrated Circuit|
|BGA<br>~~es~~<br>~~es~~<br>~~es~~|Ball Grid Array|
|CMOS<br>~~es~~<br>~~es~~<br>~~es~~|ComplementaryMetal Oxide Semiconductor|
|CSI<br>~~es~~<br>~~es~~|Camera Serial Interface|
|DBI<br>~~es~~<br>~~a~~<br>~~es~~|DisplayBus Interface|
|DPI<br>~~es~~<br>~~es~~|DisplayPixel Interface|
|DSI<br>~~es~~<br>~~es~~<br>~~es~~|DisplaySerial Interface|
|EBR<br>~~es~~<br>~~es~~<br>~~es~~|Embedded Block RAM|
|ECLK<br>~~es~~<br>~~es~~<br>~~es~~|Edge Clock|
|FPD<br>~~es~~<br>~~es~~|Flat Panel Display|
|FPGA<br>~~es~~<br>~~a~~<br>~~es~~|Field-Programmable Gate Array|
|GPIO<br>~~a~~<br>~~es~~<br>~~es~~|General-Purpose Input/Output|
|HFOSC<br>~~es~~<br>~~es~~<br>~~es~~|High FrequencyOscillator|
|HMI<br>~~es~~<br>~~es~~<br>~~es~~|Human Machine Interface|
|I2C<br>~~es~~<br>~~es~~|Inter-Integrated Circuit|
|ISM<br>~~es~~<br>~~a~~<br>~~es~~|Industrial, Scientific, Medical|
|LFOSC<br>~~a~~<br>~~es~~<br>~~es~~|Low FrequencyOscillator|
|LUT<br>~~es~~<br>~~es~~<br>~~es~~|Look UpTable|
|LVCMOS<br>~~es~~<br>~~es~~<br>~~es~~|Low-Voltage ComplementaryMetal Oxide Semiconductor|
|LVDS<br>~~es~~<br>~~es~~|Low-Voltage Differential Signaling|
|LVTTL<br>~~es~~<br>~~a~~<br>~~es~~|Low-Voltage Transistor-Transistor Logic|
|MIPI<br>~~a~~<br>~~es~~<br>~~es~~|Mobile IndustryProcessor Interface|
|NVCM<br>~~es~~<br>~~es~~<br>~~es~~|Non-Volatile Configuration Memory|
|OTP<br>~~es~~<br>~~es~~<br>~~es~~|One Time Programmable|
|PCLK<br>~~es~~<br>~~es~~|PrimaryClock|
|PFU<br>~~es~~<br>~~a~~<br>~~es~~|Programmable Functional Unit|
|PLL<br>~~a~~<br>~~es~~|Phase Locked Loops|
|PMU<br>~~es~~<br>~~a~~<br>~~es~~|Power Management Unit|
|RAM<br>~~a~~<br>~~es~~<br>~~es~~|Random Access Memory|
|Rx<br>~~es~~<br>~~es~~|receive|
|SLVS200<br>~~es~~<br>~~a~~|Scalable Low-Voltage Signaling|
|SPI<br>~~a~~<br>~~a~~|Serial Peripheral Interface|
|TransFR<br>~~a~~<br>~~a~~<br>~~es~~|Transparent Field Reconfiguration|
|Tx<br>~~a~~<br>~~es~~<br>~~es~~|Transmit|
|UHD<br>~~es~~<br>~~es~~|Ultra-High Definition|
|VR<br>~~es~~<br>~~a~~|Virtual Reality|
|WLCSP<br>~~a~~<br>~~a~~|Wafer Level ChipScale Packaging|
© 2015-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02013-1.2
5
**CrossLink Automotive Family Data Sheet**
## **1. General Description**
CrossLink™ Automotive from Lattice Semiconductor is a programmable video bridging device that supports a variety of protocols and interfaces for mobile image sensors and displays. The device is based on Lattice mobile FPGA 40nm technology. It combines the extreme flexibility of an FPGA with the low power, low cost and small footprint of an ASIC.
CrossLink Automotive supports video interfaces including MIPI[®] DPI, MIPI DBI, CMOS camera and display interfaces, OpenLDI, FPD-Link, FLATLINK, MIPI D-PHY, MIPI CSI-2, MIPI DSI, SLVS200, SubLVDS, HiSPi and more.
Lattice Semiconductor provides many pre-engineered IP (Intellectual Property) modules for CrossLink Automotive. By using these configurable soft core IPs as standardized blocks, designers are free to concentrate on the unique aspects of their design, increasing their productivity.
The Lattice Diamond[®] design software allows large complex designs to be efficiently implemented using CrossLink Automotive. Synthesis library support for CrossLink Automotive devices is available for popular logic synthesis tools. The Diamond tools use the synthesis tool output along with the constraints from its floor planning tools to place and route the design in the CrossLink Automotive device. The tools extract the timing from the routing and back-annotate it into the design for timing verification.
Interfaces on CrossLink Automotive provide a variety of bridging solutions for smart phone, tablets, wearables, VR, AR, Drone, Smart Home, HMI as well as adjacent ISM markets. The device is capable of supporting high-resolution, high-bandwidth content for mobile cameras and displays at 4k UHD and beyond.
- Programmable architecture
- 5936 LUTs
- 180 kb block RAM
- 47 kb distributed RAM
- Two hardened 4-lane MIPI D-PHY interfaces
- Transmit and receive
- 6 Gb/s per D-PHY interface
- Programmable source synchronous I/O
- MIPI D-PHY Rx, LVDS Rx, LVDS Tx, SubLVDS Rx, SLVS200 Rx, HiSPi Rx
- Up to 1200 Mb/s per I/O
- Four high-speed clock inputs
- Programmable CMOS I/O
- LVTTL and LVCMOS
- 3.3 V, 2.5 V, 1.8 V and 1.2 V (outputs)
- LVCMOS differential outputs
- Flexible device configuration
- One Time Programmable (OTP) non-volatile configuration memory
- Master SPI boot from external flash
- Dual image booting supported
- I[2] C programming
- SPI programming
- TransFR™ I/O for simple field updates
- Enhanced system level support
- Reveal logic analyzer
- TraceID for system tracking
- On-chip hardened I[2] C block
- Applications examples
- Dual MIPI CSI-2 to Single MIPI CSI-2 Aggregation
- Qual MIPI CSI-2 to Single MIPI CSI-2 Aggregation
- Single MIPI DSI to Single MIPI DSI Repeater
- Single MIPI CSI-2 to Single MIPI CSI-2 Repeater
- Single MIPI DSI to Dual MIPI DSI Splitter
- Single MIPI CSI-2 to Dual MIPI CSI-2 Splitter
- MIPI DSI to OpenLDI/FPD-Link/LVDS Translator
## **1.1. Features**
- Ultra-low power
- Sleep Mode Support
- Normal Operation – From 5 mW to 150 mW
- OpenLDI/FPD-Link/LVDS to MIPI DSI Translator
- MIPI DSI/CSI-2 to CMOS Translator
- CMOS to MIPI DSI-2 Translator
- SubLVDS to MIPI CSI-2 Translator
- Small footprint page
- 80-ball ctfBGA (42 mm[2] )
- 80-ball ckfBGA (49 mm[2] )
© 2015-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02013-1.2
6
**CrossLink Automotive Family Data Sheet**
## **2. Product Feature Summary**
Table 2.1 lists CrossLink Automotive device information and packages.
**Table 2.1. CrossLink Automotive Feature Summary**
|**Device**|**CrossLink Automotive**|
|---|---|
|LUTs|5936|
|sysMEM Blocks (9 kb)|20|
|Embedded Memory (kb)|180|
|Distributed RAM Bits (kb)|47|
|General Purpose PLL|1|
|NVCM|Yes|
|Embedded I2C|2|
|Oscillator (10 KHz)|1|
|Oscillator (48 MHz)|1|
|Hardened MIPI D-PHY|2*|
|**Packages(Footprint, Pitch)**|**I/O**|
|80 ctfBGA (6.5 x 6.5 mm2, 0.65 mm)|37|
|80 ckfBGA (7.0 x 7.0 mm2, 0.65 mm)|37|
***Note:** Additional D-PHY Rx interfaces are available using programmable I/O.
© 2015-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02013-1.2
7
**CrossLink Automotive Family Data Sheet**
## **3. Architecture Overview**
CrossLink Automotive is designed as a flexible, chip-to-chip bridging solution which supports a wide variety of applications. The device provides three key building blocks for these bridging applications:
- Up to two embedded Hard D-PHY blocks
- Two banks of flexible programmable I/O supporting a variety of standards including D-PHY Rx, subLVDS, SLVS200, LVDS, and CMOS
- A programmable logic core providing the LUTs, memory, and system resources to implement a wide range of bridging operations
In addition to these blocks, CrossLink Automotive also provides key system resources including a Power Management Unit, flexible configuration interface, additional CMOS GPIO, and user I[2] C blocks.
The block diagram for the device is shown in Figure 3.1.
**==> picture [426 x 320] intentionally omitted <==**
**----- Start of picture text -----**<br>
Programmable IO<br>MIPI D-PHY<br>Rx: D-PHY/SubLVDS/LVDS/<br>SLVS200/CMOS 6 Gb/s<br>Programmable FPGA Fabric Rx and Tx<br>Tx: LVDS/CMOS 5,936 LUTs<br>180 kbits block RAM 4 Data Lanes<br>Up to 1.2 Gb/s per Lane 47 kbits distributed RAM 1 Clock Lane<br>14 IO/7 Pairs<br>Enough FPGA resources to handle video:<br>Muxing<br>Merging<br>Programmable IO Demuxing<br>Arbitration MIPI D-PHY<br>Rx: D-PHY/SubLVDS/LVDS/ Splitting<br>SLVS200/CMOS Data Conversion 6 Gb/s<br>Custom Protocol Design Rx and Tx<br>Tx: LVDS/CMOS<br>4 Data Lanes<br>Up to 1.2 Gb/s per Lane 1 Clock Lane<br>16 IO/8 Pairs<br>Power Management Unit GPIOs I2C/SPI*<br>**----- End of picture text -----**<br>
**Figure 3.1. CrossLink Automotive Device Block Diagram**
***Note:** I[2] C and SPI configuration modes are supported. User mode hardened I[2] C is also supported.
© 2015-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
8
FPGA-DS-02013-1.2
**CrossLink Automotive Family Data Sheet**
## **3.1. MIPI D-PHY Blocks**
The top side of the device (Figure 3.2) includes two hard MIPI D-PHY quads. The D-PHY can be configured to support both camera interface (CSI-2) and display interface (DSI) applications. Below is a summary of the features supported by the hard D-PHY quads.
- Transmit and Receive compliant to MIPI Alliance Specification D-PHY Revision 1.1
- High-Speed (HS) and Low-Power (LP) mode support (including built-in contention detect)
- Supports continuous clock mode or low power clock mode
- Up to 6 Gb/s per quad (1500 Mb/s data rate per lane)
- Dedicated PLL for Transmit Frequency Synthesis
- Dedicated Serializer and De-Serializer blocks for fabric interfacing
Lattice Semiconductor provides a set of pre-engineered IP modules which include the full implementation and control of the hard D-PHY blocks to enable designers to focus on unique aspects of their design.
**==> picture [484 x 354] intentionally omitted <==**
**----- Start of picture text -----**<br>
Figure 3.3 to Figure 3.6 show the signals connected to the fabric and the automatic settings when the hardened D-PHY<br>is configured for the DSI/CSI-2 transmit and receive modes. Refer to CrossLink High-Speed I/O Interface (FPGA-TN-<br>02012) for more information on the Hard D-PHY quads.<br>TOP<br>MIPI D-PHY 0 MIPI D-PHY 1<br>Bank 2 Bank 1 Bank 0<br>—_<br>BOTTOM<br>Figure 3.2. CrossLink Automotive sysI/O Banking<br>GND VCCIO2 GND VCCIO1 GND VCCIO0<br>**----- End of picture text -----**<br>
© 2015-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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**CrossLink Automotive Family Data Sheet**
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**----- Start of picture text -----**<br>
MIPIDPHYA<br>Bidirectional clk and data<br>CLKP<br>CLKN<br>DP[3:1]<br>DN[3:1]<br>DP0<br>DN0<br>D0_RXLPP<br>RX - Data LP ports<br>D0_RXLPN<br>TX – Data HS ports<br>D0_TXHSEN<br>TXHSBYTECLK<br>Dy_HSTXDATA[15:0]<br>D0_TXLPEN TX – Data LP ports<br>D0_TXLPP<br>D0_TXLPN<br>Dx_TXLPP<br>Dx_TXLPN<br>TX – CLK HS ports<br>CLK_TXHSEN<br>CLK_TXHSGATE<br>TX – CLK LP ports<br>CLK_TXLPP<br>CLK_TXLPN<br>Control Ports<br>USRSTDBY<br>PDPLL<br>PLL Ports<br>REFCLK LOCK<br>* x = 1, 2, 3<br> y = 0, 1, 2, 3<br>**----- End of picture text -----**<br>
**Figure 3.3. MIPI DSI Transmit Interface with Hard D-PHY Module**
© 2015-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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**CrossLink Automotive Family Data Sheet**
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**----- Start of picture text -----**<br>
MIPIDPHYA<br>Bidirectional clk and data<br>CLKP<br>CLKN<br>DP[3:1]<br>DN[3:1]<br>DP0<br>DN0<br>D0_TXHSEN —______» TX – Data HS ports<br>TXHSBYTECLK<br>Dy_HSTXDATA[15:0] —________> |<br>TX – Data LP ports<br>D0_TXLPEN<br>TX – CLK HS ports<br>CLK_TXHSEN —______»<br>CLK_TXHSGATE _—______»<br>TX – CLK LP ports<br>CLK_TXLPP<br>—____>»<br>CLK_TXLPN<br>—_____> »<br>CLK_TXLPEN<br>Control Ports<br>USRSTDBY<br>PDPLL<br>PLL Ports<br>REFCLK LOCK<br>* x = 1, 2, 3<br> y = 0, 1, 2, 3<br>**----- End of picture text -----**<br>
**Figure 3.4. MIPI CSI-2 Transmit Interface with Hard D-PHY Module**
© 2015-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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**CrossLink Automotive Family Data Sheet**
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**----- Start of picture text -----**<br>
MIPIDPHYA<br>CLKP Bidirectional clk and data<br>CLKN<br>DPx<br>DNx<br>DP0<br>DN0<br>RX - Data HS ports<br>DO_RXHSEN Dy_HSRXDATA[15:0]<br>RXHSBYTECLK<br>RX - Data LP ports D0_RXLPP<br>D0_RXLPN<br>DO_RXLPEN<br>D0_CD<br>RX - CLK HS ports<br>CLKRXHSEN<br>CLKHSBYTE<br>RX - CLK LP ports<br>CLK_RXLPP<br>CLKRXLPEN CLK_RXLPN<br>CLK_CD<br>TX – Data LP ports<br>D0_TXLPP<br>D0_TXLPN<br>Control Ports<br>USRSTDBY<br>* x = 1, 2, 3<br> y = 0, 1, 2, 3<br>**----- End of picture text -----**<br>
**Figure 3.5. MIPI DSI Receive Interface with Hard D-PHY Module**
© 2015-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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**CrossLink Automotive Family Data Sheet**
**==> picture [376 x 422] intentionally omitted <==**
**----- Start of picture text -----**<br>
MIPIDPHYA<br>Bidirectional clk and data<br>CLKP<br>CLKN<br>DPx<br>DNx<br>DP0<br>DN0<br>RX - Data HS ports<br>Dy_HSRXDATA[15:0]<br>RXHSBYTECLK<br>RX - Data LP ports<br>D0_RXLPP<br>D0_RXLPN<br>D0_CD<br>RX - CLK HS ports<br>CLKHSBYTE<br>RX - CLK LP ports<br>CLK_RXLPP<br>CLK_RXLPN<br>CLK_CD<br>Control Ports<br>USRSTDBY<br>* x = 1, 2, 3<br> y = 0, 1, 2, 3<br>**----- End of picture text -----**<br>
**Figure 3.6. MIPI CSI-2 Receive Interface with Hard D-PHY Module**
## **3.2. Programmable I/O Banks**
CrossLink Automotive devices provide programmable I/O which can be used to interface to a variety of external standards on Banks 1 and 2. CrossLink Automotive devices also provide dedicated CMOS GPIOs on Bank 0. Bank 0 GPIOs only support Single Data Rate (SDR) interfaces, while Bank 1 and Bank 2 support both SDR and Double Data Rate (DDR) interfaces. The GPIOs on Bank 0 do not include differential signaling capabilities. The location of the three Banks and their associated supplies are shown in Figure 3.2.
Bank 0 features:
- Support the following single ended standards (ratioed to VCCIO)
- LVCMOS33
- LVCMOS25
- LVCMOS18
- LVTTL33
- Tri-state control for output
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**CrossLink Automotive Family Data Sheet**
- Input/output register blocks
- Open-drain option and programmable input hysteresis
- Internal pull-up resistors with configurable values of 3.3 kΩ, 6.8 kΩ and 10 kΩ
Bank 1 and Bank 2 features:
- Built-in support for the following differential standards
- LVDS – Tx and Rx
- SLVS200 – Rx
- SubLVDS – Rx
- MIPI – Rx (both LP and HS receive on a single differential pair)
- Support for the following single ended standards (ratioed to VCCIO)
- LVCMOS33
- LVCMOS25
- LVCMOS18
- LVCMOS12 (Outputs Only)
- LVTTL33
- Independent voltage levels per bank based on VCCIO supply
- Input/output gearboxes per LVDS pair supporting several ratios for video interface applications DDRX1, DDRX2, DDRX4, DDRX8 and DDRX71, DDRX141
- Programmable delay cells to support edge-aligned and center-aligned interfaces
- Programmable differential termination (~ 100 Ω) with dynamic enable control
- Tri-state control for output
- Input/output register blocks
- Single-ended standards support open-drain and programmable input hysteresis
- Optional weak pull-up resistors
**Table 3.1. CrossLink Automotive Output Support per Bank Basis**
|**OUTPUT**|**BANK 0**|**BANK 1**|**BANK 2**|
|---|---|---|---|
|LVCMOS12|—|||
|LVCMOS18||||
|LVCMOS25||||
|LVCMOS33||||
|LVTTL33||||
|LVDS25|—|||
© 2015-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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**CrossLink Automotive Family Data Sheet**
**Table 3.2. CrossLink Automotive Input Support per Bank Basis**
|**INPUT**|**BANK 0**|**BANK 1**|**BANK 2**|
|---|---|---|---|
|LVCMOS12||—||
|LVCMOS18||||
|LVCMOS25||||
|LVCMOS33||||
|LVTTL33||||
|LVDS25|—|||
|MIPI D-PHY|—|||
|SLVS200|—|||
|subLVDS|—|||
## **3.3. sysI/O Buffers**
The CrossLink Automotive sysI/O buffers are distributed across three banks located at the bottom of the CrossLink Automotive device as shown in Figure 3.2. The sysI/O buffers support a wide variety of standards to interface to a range of systems including LVDS, subLVDS, LVCMOS, LVTTL, SLVS200 and MIPI. CrossLink Automotive supports singleended buffers on all three banks. Differential I/O is supported on Bank 1 and Bank 2.
## **3.3.1. Programmable PULLMODE Settings**
The CrossLink Automotive sysI/O buffers offer multiple programmable value pull-up resistors on the three banks. The pull-up values are programmable on a “per-pin” basis. The default state of the I/O pins prior to configuration is tristated with a weak pull-up to VCCIOx. The I/O pins convert to the software user-defined settings after the configuration bitstream has been successfully downloaded to the device. Each sysIO buffer can be programmed with a 100 kΩ (weak pull-up), 3.3 kΩ, 6.8 kΩ, 10 kΩ or no pull-up. These pull-up options allow an I[2] C interface to be place on the majority of the pins on the device. These options are not exclusively for I[2] C protocol and may be used for other functions.
## **3.3.2. Output Drive Strength**
Each CrossLink Automotive output can have its own individual drive strength setting, but is predefined based on the VCCIOx setting. Table 3.3 lists the drive settings for the corresponding I/O type.
**Table 3.3. Drive Strength Values**
|**VCCIOx(V)**|**I/O Type **|**Drive Strength(mA)**|
|---|---|---|
|3.3|LVTTL33|8|
|3.3|LVCMOS33|8|
|2.5|LVCMOS25|6|
|1.8|LVCMOS18|4|
|1.2|LVCMOS12|2|
## **3.3.3. On-Chip Termination**
Bank 1 and bank 2 of CrossLink Automotive support LVDS, SLVS200 subLVDS and MIPI D-PHY inputs. These two banks support on-chip 100 Ω input differential termination between LVDS, SLVS200 and subLVDS pairs. For MIPI D-PHY inputs, the on-chip 100 Ω termination is dynamically enabled based on the HSSEL (High Speed Select) signal. See CrossLink High-Speed I/O Interface (FPGA-TN-02012) and CrossLink sysI/O Usage Guide (FPGA-TN-02016) for details.
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**CrossLink Automotive Family Data Sheet**
## **3.4. Programmable FPGA Fabric**
CrossLink Automotive is built around a programmable logic fabric consisting of 5936 four input lookup tables (LUT4) arranged alongside dedicated registers in Programmable Functional Units (PFU). These PFU blocks are the building blocks for logic, arithmetic, RAM and ROM functions. The PFU blocks are connected via a programmable routing network. The Lattice Diamond design software configures the PFU blocks and the programmable routing for each unique design. Interspersed between rows of PFU are rows of sysMEM™ Embedded Block RAM (EBR), with programmable I/O banks, embedded I[2] C and embedded MIPI D-PHY arranged on the top and bottom of the device as shown in Figure 3.7.
**==> picture [453 x 264] intentionally omitted <==**
**----- Start of picture text -----**<br>
MIPI D-PHY 0 MIPI D-PHY 1<br>PFU PFU PFU PFU PFU<br>4 EBR Blocks (9 kb each) 4 EBR Blocks (9 kb each) 4 EBR Blocks (9 kb each) 4 EBR Blocks (9 Kb each) 4 EBR Blocks (9 kb each)<br>PFU PFU PFU PFU PFU<br>Clocking PMU<br>Bank 2 PLL Bank 1 Bank 0<br>CONFIG<br>OSC<br>I2C0 I2C1<br>NVCM<br>DDRDLL2 DDRDLL1<br>**----- End of picture text -----**<br>
**Figure 3.7. CrossLink Automotive Device Simplified Block Diagram (Top Level)**
## **3.4.1. PFU Blocks**
The core of the CrossLink Automotive device consists of PFU blocks. Each PFU block consists of four interconnected slices numbered 0 – 3 as shown in Figure 3.8. Each slice contains two LUTs. All the interconnections to and from PFU blocks are from routing. The PFU block can be used in Distributed RAM or ROM function, or used to perform Logic, Arithmetic or ROM functions.
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**CrossLink Automotive Family Data Sheet**
**==> picture [369 x 207] intentionally omitted <==**
**----- Start of picture text -----**<br>
From<br>Routing<br>+<br>LUT4 & LUT4 & LUT4 & LUT4 & LUT4 & LUT4 & LUT4 & LUT4 &<br>CARRY CARRY CARRY CARRY CARRY CARRY CARRY CARRY<br>‘ oe - i i re ee ot<br>Slice 0 Slice 1 Slice 2 Slice 3<br>D D D D D D D D<br>FF FF FF FF FF FF FF FF<br>eee<br>To<br>Routing<br>+<br>**----- End of picture text -----**<br>
**Figure 3.8. CrossLink Automotive PFU Diagram**
## **3.4.2. Slice**
Each slice contains two LUT4s feeding two registers. Each PFU contains logic that allows the LUTs to be combined to perform functions such as LUT5, LUT6, LUT7 and LUT8. There is control logic to perform set/reset functions (programmable as synchronous/asynchronous), clock select, chip-select and wider RAM/ROM functions. Figure 3.9. shows an overview of the internal logic of the slice. The registers in the slice can be configured for positive/negative and edge triggered or level sensitive clocks.
Each slice has 14 input signals: 13 signals from routing and 1 signal from the carry-chain routed from the adjacent slice or PFU. There are five outputs: four to routing and one to carry-chain (to the adjacent PFU). There are two inter slice/PFU output signals that are used to support wider LUT functions, such as LUT6, LUT7, and LUT8. Table 3.4 and Figure 3.9. list the signals associated with all the slices. Figure 3.10 shows the connectivity of the inter-slice/PFU signals that support LUT5, LUT6, LUT7, and LUT8.
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**CrossLink Automotive Family Data Sheet**
**==> picture [169 x 397] intentionally omitted <==**
**----- Start of picture text -----**<br>
FCO<br>FXA<br>FXB<br>M1 Ly<br>M0<br>A1<br>B1 < LUT4 &<br>C1 in CARRY*<br>D1<br>a -<br>F1 in<br>F1<br>FF<br>: -<br>Q1<br>A0<br>B0 LUT4 &<br>C0 | | CARRY*<br>D0<br>og<br>F0 i<br>F0<br>FF<br>-<br>:<br>Q0CE ly<br>CLK<br>>i<br>LSR<br>FCI __ f From Different Slice/PFU<br>**----- End of picture text -----**<br>
**==> picture [282 x 44] intentionally omitted <==**
**----- Start of picture text -----**<br>
Notes : For Slices 0 and 1, memory control signals are generated from Slice 2 as follows:<br>WCK is CLK<br>WRE is from LSR<br>DI[3:2] for Slice 1 and DI[1:0] for Slice 0 data from Slice 2<br>WAD [A:D] is a 4-bit address from slice 2 LUT input<br>**----- End of picture text -----**<br>
**Figure 3.9. Slice Diagram**
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**CrossLink Automotive Family Data Sheet**
**==> picture [467 x 601] intentionally omitted <==**
**----- Start of picture text -----**<br>
PFU Col(n-1) PFU Col(n) PFU Col(n+1)<br>B1A1 F1 LUT8 B1A1 F1 LUT8 B1A1 F1 LUT8<br>C1 C1 C1<br>D1 Q1 D1 Q1 D1 Q1<br>A0 A0 A0<br>B0 LUT5 B0 LUT5 B0 LUT5<br>C0 F0 C0 F0 C0 F0<br>D0 D0 D0<br>FXB Q0 FXB Q0 FXB Q0<br>LUT7 Output FXA FXA FXA LUT7 Output<br>To Next PFU From Previous PFU<br>A1 LUT6 A1 LUT6 A1 LUT6<br>B1 F1 B1 F1 B1 F1<br>C1 C1 C1<br>D1 Q1 D1 Q1 D1 Q1<br>A0 A0 A0<br>B0 LUT5 B0 LUT5 B0 LUT5<br>C0 F0 C0 F0 C0 F0<br>D0 D0 D0<br>FXB Q0 FXB Q0 FXB Q0<br>FXA FXA FXA<br>B1A1 F1 LUT7 B1A1 F1 LUT7 B1A1 F1 LUT7<br>C1 C1 C1<br>D1 Q1 D1 Q1 D1 Q1<br>A0 A0 A0<br>B0 LUT5 B0 LUT5 B0 LUT5<br>C0 F0 C0 F0 C0 F0<br>D0 D0 D0<br>FXB Q0 FXB Q0 FXB Q0<br>FXA FXA FXA<br>GOD<br>A1 LUT6 A1 LUT6 A1 LUT6<br>B1 F1 B1 F1 B1 F1<br>C1 C1 C1<br>D1 Q1 D1 Q1 D1 Q1<br>A0 A0 A0<br>B0 LUT5 B0 LUT5 B0 LUT5<br>C0 F0 C0 F0 C0 F0<br>D0 D0 D0<br>FXB Q0 FXB Q0 FXB Q0<br>FXA FXA FXA<br>CoE<br>Figure 3.10. Connectivity Supporting LUT5, LUT6, LUT7 and LUT8<br>Table 3.4. Slice Signal Descriptions gnal Descriptions nal Descriptions ptions tions<br>Function Type Signal Names Description<br>Input Data signal A0, B0, C0, D0 Inputs to LUT4<br>Input Data signal A1, B1, C1, D1 Inputs to LUT4<br>Input Multi-purpose M0 Multipurpose Input<br>Input Multi-purpose M1 Multipurpose Input<br>Input Control signal CE Clock Enable<br>Input Control signal LSR Local Set/Reset<br>Input Control signal CLK System Clock<br>Input Inter-PFU signal FCI Fast Carry-in [1]<br>Input Inter-slice signal FXA Intermediate signal to generate LUT6, LUT7 and LUT8 [2]<br>Input Inter-slice signal FXB Intermediate signal to generate LUT6, LUT7 and LUT8 [2]<br>Output Data signals F0, F1 LUT4 output register bypass signals<br>Output Data signals Q0, Q1 Register outputs<br>Output Inter-PFU signal FCO Fast carry chain output [1]<br>3 3 3<br>SLICE SLICE SLICE<br>2 2 2<br>SLICE SLICE SLICE<br>1 1 1<br>SLICE SLICE SLICE<br>0 0 0<br>SLICE SLICE SLICE<br>**----- End of picture text -----**<br>
**Table 3.4. Slice Signal Descriptions gnal Descriptions nal Descriptions ptions tions**
**Notes** :
See Figure 3.9. for connection details.
Requires two adjacent PFUs.
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**CrossLink Automotive Family Data Sheet**
## **3.5. Clocking Structure**
The CrossLink Automotive device family provides resources to support a wide range of clocking requirements for programmable video bridging. These resources are described below. For details, refer to CrossLink sysCLOCK PLL/DLL Design and Usage Guide (FPGA-TN-02015).
## **3.5.1. sysCLK PLL**
The CrossLink Automotive sysCLK PLL provides the ability to synthesis clock frequencies (See Table 4.14 for input frequency range). The PLL provides features such as dynamic selectable clock input, clock injection delay removal, independent dynamic output enable control, and programmable output phase adjustment. The architecture of the PLL is shown in Figure 3.11 and followed by a description of the PLL blocks.
**Figure 3.11. CrossLink Automotive PLL Block Diagram**
Table 3.5 provides a description of the signals in the PLL block.
**Table 3.5. CrossLink Automotive PLL Port Definition**
|**Signal**|**I/O**|**Description**|
|---|---|---|
|CLKI|I|Input clock to PLL|
|CLKFB|I|Feedback clock|
|USRSTDBY|I|Userport toput the PLL to sleepmode|
|PHASESEL[1:0]|I|Select the output affected byDynamic Phase adjustment|
|PHASEDIR|I|Dynamicphase adjustment direction|
|PHASESTEP|I|Dynamicphase adjustment step|
|PHASELOADREG|I|Load dynamicphase adjustment values into PLL|
|RST|I|Resets the whole PLL|
|ENCLKOP|I|Enable PLL output CLKOP|
|ENCLKOS|I|Enable PLL output CLKOS|
|ENCLKOS2|I|Enable PLL output CLKOS2|
|ENCLKOS3|I|Enable PLL output CLKOS3|
|PLLWAKESYNC|I|Enable PLL switchingfrom internal to user feedbackpath when PLL wake up|
|CLKOP|O|PLL main output clock|
|CLKOS|O|PLL output clock|
|CLKOS2|O|PLL output clock|
|CLKOS3|O|PLL output clock|
|LOCK|O|PLL LOCK to CLKI, asynchronous signal. Active high indicates PLL lock|
© 2015-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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FPGA-DS-02013-1.2
**CrossLink Automotive Family Data Sheet**
## **3.5.2. Primary Clocks**
The primary clock routing network is made up of low skew clock routing resources with connectivity to every synchronous element of the device. Primary clock sources are selected in the center mux and distributed on the primary clock routing to clock the synchronous elements in the FPGA fabric. CrossLink Automotive family of devices provide up to eight unique global primary clocks. Primary clock sources are:
- LVDS PIO pins
- GPIO pins
- PLL outputs
- Clock dividers
- Fabric internally generated clock signal
- Divided down clock from DPHY
- OSCI
The routing clock structure is shown in Figure 3.12.
**==> picture [467 x 265] intentionally omitted <==**
**----- Start of picture text -----**<br>
MIPI_DPHY0 MIPI_DPHY1<br>|<br>CLK_HS_BYTE_0 HS_BYTE_CLK0 (RX and TX) HS_BYTE_CLK1 (RX and TX) CLK_HS_BYTE_0<br>2 2<br>Center Mux<br>(8 PCLKs out)<br>2 2<br>r<br>OSC_HF OSC_LF<br>OSC PLL<br>— KI +<br>CLKDIV CLKDIV CLKDIV CLKDIV<br>LL Edge Clocks beta —- Edge Clocks<br>Bank 2 Bank 1 Bank 0<br>GRPIO LVDSPIO LVDSPIO LVDSPIO LVDSPIO LVDSPIO LVDSPIO GRPIO GPIO GPIO<br>Entry Fabric Entry Fabric<br>**----- End of picture text -----**<br>
**Figure 3.12. CrossLink Automotive Clocking Structure**
## **3.5.3. Edge Clocks**
The CrossLink Automotive device has Edge Clock (ECLK) at the bottom 2 banks (Bank 1 and Bank 2) of the device (Figure 3.2). The CrossLink Automotive device has 2 edge clocks per Programmable I/O bank. These clocks, which have low injection time and skew, are used to clock I/O registers. Edge clock resources are designed for high speed I/O interfaces with high fan-out capability. The sources of edge clocks are:
- Dedicated Clock (PCLK) pins muxed with the DLLDEL output
- PLL outputs (CLKOP and CLKOS)
- Internal nodes
ELCK input MUX collects all clock sources as shown in Figure 3.13 below. There are two ECLK Input MUXs, one on each bank. It drives the ECLK SYNC modules and the ECLK Clock Divider through a 2 to 1 MUX.
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**CrossLink Automotive Family Data Sheet**
**==> picture [118 x 93] intentionally omitted <==**
**----- Start of picture text -----**<br>
Bank 1 or Bank 2 LVDS PCLK Pin<br>Bank 1 or Bank 2 DLLDEL Output<br>PLL CLKOP<br>PLL CLKOS<br>From Routing<br>**----- End of picture text -----**<br>
**==> picture [136 x 136] intentionally omitted <==**
**----- Start of picture text -----**<br>
From ECLKSYNC of<br>other bank on<br>same side<br>ECLK Tree<br>ECLKSYNCB<br>To ECLK of other<br>bank on same side<br>**----- End of picture text -----**<br>
**Figure 3.13. CrossLink Automotive Edge Clock Sources per Bank**
## **3.5.4. Dynamic Clock Enables**
Each PLL output has a user input signal to dynamically enable/disable its output to provide a glitch free clock. Then the clock enable signal is set to logic ‘0’, the corresponding output clock is held to logic ‘0’. This allows the user to save power by stopping the corresponding output clock when not in use.
## **3.5.5. Internal Oscillator (OSCI)**
The OSCI element performs multiple functions on the CrossLink Automotive device. It is used for configuration and available during user mode. OSCI element has the following features in user mode:
- Always-on low frequency clock output (LFCLKOUT) with nominal frequency of 10 kHz
- High-frequency clock output (HFCLKOUT) with nominal frequency of 48 MHz that can be enabled or disabled using HFOUTEN input
- Programmable output dividers (HFCLKDIV) for 48 MHz, 24 MHz, 12 MHz or 6 MHz HFCLKOUT output
- Both output clocks have a direct connection to primary clock routing
Figure 3.14, Table 3.6 and Table 3.7 below show the OSCI definitions
**Figure 3.14. CrossLink Automotive OSCI Component Symbol**
**Table 3.6. OSCI Component Port Definition**
|**Port Name**|**I/O**|**Description**|
|---|---|---|
|HFOUTEN|I|High frequencyclock output enable|
|HFCLKOUT|O|High frequencyclock output|
|LFCLKOUT|O|Low Frequencyclock output|
**Table 3.7. OSCI Component Attribute Definition**
|**Defparam Name**|**Description**|**Value**|**Default**|
|---|---|---|---|
|HFCLKDIV|Configure HF oscillator output divider|1, 2, 4, 8|1|
© 2015-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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FPGA-DS-02013-1.2
**CrossLink Automotive Family Data Sheet**
## **3.6. Embedded Block RAM Overview**
CrossLink Automotive devices contain sysMEM Embedded Block RAM (EBR). The EBR consists of a 9 kB RAM with memory core, dedicated input registers and output registers with separate clock and clock enable. Support for different memory configurations:
- Single Port
- True Dual Port
- Pseudo Dual Port
- ROM
- FIFO (logic wrapper added automatically by design tools)
Flexible customization features:
- Initialization of RAM/ROM
- Memory cascading (handled automatically by design tools)
- Optional parity bit support
- Byte-enable
- Multiple block size options
- RAM modes support optional Write Through or Read-Before-Write modes
For details, refer to CrossLink Memory Usage Guide (FPGA-TN-02017).
**Table 3.8. sysMEM Block Configurations**
|**Memory Mode**|**Memory Size Configurations**|
|---|---|
|Single Port|8,192 x 1<br>4,096 x 2<br>2,048 x 4<br>1,024 x 9<br>512 x 18|
|True Dual Port|8,192 x 1<br>4,096 x 2<br>2,048 x 4<br>1,024 x 9|
|Pseudo Dual Port|8,192 x 1<br>4,096 x 2<br>2,048 x 4<br>1,024 x 9<br>512 x 18|
|ROM|8,192 x 1<br>4,096 x 2<br>2,048 x 4<br>1,024 x 9<br>512 x 18|
## **3.7. Power Management Unit**
The embedded Power Management Unit (PMU) allows low-power Sleep State of the device. Figure 3.15 shows the block diagram of the PMU IP.
When instantiated in the design, PMU is always on, and uses the low-speed clock from oscillator of the device to perform its operations.
The typical use case for the PMU is through a user implemented state machine that controls the sleep and wake up of the device. The state machine implemented in the FPGA fabric identifies when the device needs to go into sleep mode, issues the command through PMU’s FPGA fabric interface, assigns the parameters for sleep (time to wake up and so on) and issues Sleep command.
© 2015-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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**CrossLink Automotive Family Data Sheet**
The device can be woken up externally using the PMU Wake-Up (USRWKUP) pin, or from the PMU Watch Dog Timer expiry or from I2C0 (address decoding detection or FIFO full in one of hardened I[2] C).
**==> picture [418 x 258] intentionally omitted <==**
**----- Start of picture text -----**<br>
Power Management Unit (PMU)<br>PMU Clock (From Oscillator)<br>(PMUCLK)<br>External User Wake-up<br>(USRWKUPN)<br>PMU Wake-up from I2C0<br>(PMUWKUP)<br>Power Control Unit<br>Watch Dog Timer<br>User Mode Signals<br>From FPGA Fabric<br>Register<br>PMU Control<br>Timer<br>Watch Dog<br>PMU Sleep Signal, SLEEP 8-bit Addressable Fabric Interface<br>**----- End of picture text -----**<br>
**Figure 3.15. CrossLink Automotive MIPI D-PHY Block**
## **3.7.1. PMU State Machine**
PMU can place the device in two mutually exclusive states – Normal State and Sleep State. Figure 3.16 shows the PMU State Machine triggers for transition from one state to the other.
- Normal state – All elements of the device are active to the extent required by the design. In this state, the device is at fully active and performing as required by the application. Note that the power consumption of the device is highest in this state.
- Sleep state – The device is power gated such that the device is not operational. The configuration of the device and the EBR contents are retained; thus in Sleep mode, the device does not lose configuration SRAM and EBR contents. When it transitions to Normal state, device operates with these contents preserved. The PMU is active along with the associated GPIOs. The power consumption of the device is lowest in this state. This helps reduce the overall power consumption for the device.
**==> picture [254 x 109] intentionally omitted <==**
**----- Start of picture text -----**<br>
User Logic Initiated<br>Sleep Mode Normal Mode<br>User I [2] C/<br>External Wake-up/<br>WDT Expiry Wake-up<br>**----- End of picture text -----**<br>
**Figure 3.16. CrossLink Automotive PMU State Machine**
For more details, refer to Power Management and Calculation for CrossLink Devices (FPGA-TN-02018).
© 2015-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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FPGA-DS-02013-1.2
**CrossLink Automotive Family Data Sheet**
## **3.8. User I[2] C IP**
CrossLink Automotive devices have two I[2] C IP cores that can be configured either as an I[2] C master or as an I[2] C slave. The I2C0 core has pre-assigned pins, and supports PMU wakeup over I[2] C. The pins for the I2C1 interface are not pre-assigned – user can use any General Purpose I/O pins.
The I[2] C cores support the following functionality:
- Master and Slave operation
- 7-bit and 10-bit addressing
- Multi-master arbitration support
- Clock stretching
- Up to 1 MHz data transfer speed
- General call support
- Optionally delaying input or output data, or both
- Optional FIFO mode
- Transmit FIFO size is 10 bits x 16 bytes, receive FIFO size is 10 bits x 32 bytes
For further information on the User I[2] C, refer to CrossLink I2C Hardened IP Usage Guide (FPGA-TN-02019).
© 2015-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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**CrossLink Automotive Family Data Sheet**
## **3.9. Programming and Configuration**
CrossLink Automotive is a SRAM-based programmable logic device that includes an internal Non-Volatile Configuration Memory (NVCM), as well as flexible SPI and I[2] C configuration modes. CrossLink Automotive provides four modes for loading the configuration data into the SRAM memory.
- Self-Download (NVCM) mode – CrossLink Automotive retrieves bitstream from internal NVCM
- Master SPI mode – CrossLink Automotive retrieves bitstream from an external SPI Flash
- Slave SPI mode – System microprocessor writes bitstream to CrossLink Automotive through SPI port
- Slave I[2] C mode – System microprocessor writes bitstream to CrossLink Automotive through I[2] C port
CrossLink Automotive provides a set of sysCONFIG I/O pins to program and configure the FPGA. The sysCONFIG pins are grouped together to create ports (I[2] C, SSPI or MSPI) that are used to interact with the FPGA for programming, configuration, and access of resources inside the FPGA. The sysCONFIG pins (Table 3.9) in a configuration group may be active and used for programming the FPGA or they can be reconfigured to act as general purpose I/Os.
**Table 3.9. CrossLink Automotive sysCONFIG Pins**
|**Pin Name**|**Associated sysCONFIG Port**|
|---|---|
|CRESETB|Self Download Mode/SSPI/MSPI/I2C|
|CDONE|Self Download Mode/SSPI/MSPI/I2C|
|SPI_SCK/MCK/SDA|SSPI/MSPI/I2C|
|SPI_SS/CSN/SCL|SSPI/MSPI/I2C|
|MOSI|SSPI/MSPI|
|MISO|SSPI/MSPI|
As external power ramps up, a Power On Reset (POR) circuit inside the FPGA becomes active. When POR conditions are met, the POR circuit releases an internal reset strobe, allowing the device to begin its initialization process. After CrossLink Automotive drives CDONE low, CrossLink Automotive enters the memory initialization phase where it clears all of the SRAM memory inside the FPGA. CrossLink Automotive remains in initialization state until the CRESETB pin is deasserted or after SSPI/SI[2] C activation code is received.
- After CRESETB goes from low to high, the Configuration Logic puts the device into master auto booting mode where it boots either from the internal NVRAM or an external SPI boot PROM.
- Holding the CRESETB low postpones the master auto booting event and allows the slave configuration ports (Slave SPI or Slave I[2] C) to detect a ‘Slave Active’ condition where the SPI or I[2] C Master sends an Activation Key code to CrossLink Automotive. An external SPI Master or I[2] C Master needs to write the Activation Key to the FPGA while CRESETB is held LOW and within 9.5 ms from Vcc min during power up to enter into one of the slave configuration modes.
- Sources should not drive output to CrossLink Automotive until configuration has been completed to ensure CrossLink Automotive is in a known state.
In addition to the flexible configuration modes, the CrossLink Automotive configuration engine supports the following special features:
- TransFR (Transparent Field Reconfiguration) allowing users to update logic in field without interrupting system operation by freezing I/O states during configuration
- Dual-Boot Support for primary and golden bitstreams provides automatic recovery from configuration failures
- Security and One-Time Programmable (OTP) modes protect bitstream integrity and prevent readback
- 64-bit unique TraceID per device
For more information, refer to CrossLink Programming and Configuration Usage Guide (FPGA-TN-02014).
© 2015-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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FPGA-DS-02013-1.2
**CrossLink Automotive Family Data Sheet**
## **4. DC and Switching Characteristics**
## **4.1. Absolute Maximum Ratings**
**Table 4.1. Absolute Maximum Ratings[1, 2, 3]**
|**Symbol**<br>~~a nO~~|**Parameter**<br>~~nO~~|**Min**<br>~~nO~~|**Max**<br>~~nO~~|**Unit**<br>~~nO~~|
|---|---|---|---|---|
|VCC<br>~~a CC~~|Core Supply Voltage<br>~~CC~~|–0.5<br>~~CC~~|1.32<br>~~CC~~|V<br>~~CC~~|
|VCCGPLL<br>~~a~~<br>~~——————~~|PLL Supply Voltage<br>~~——————~~|–0.5<br>~~——————~~|1.32<br>~~——————~~|V<br>~~——————~~|
|VCCAUX<br>~~——————~~<br>~~a~~|Auxiliary Supply Voltage for Bank 1, 2 and NVCM - @ 2.5 V<br>~~——————~~|–0.5<br>~~——————~~|2.75<br>~~——————~~|V<br>~~——————~~|
||Auxiliary Supply Voltage for Bank 1, 2 and NVCM - @ 3.3 V<br>~~——————~~<br>~~a~~|–0.5<br>~~——————~~<br>~~a~~|3.63<br>~~——————~~<br>~~a~~|V<br>~~——————~~<br>~~a~~|
|VCCIO<br>~~——————~~<br>~~a~~<br>~~a~~<br>~~es~~|I/O Driver Supply Voltage for Banks 0, 1, 2<br>~~——————~~<br>~~a~~|–0.5<br>~~——————~~<br>~~a~~|3.63<br>~~——————~~<br>~~a~~|V<br>~~——————~~<br>~~a~~|
|—<br>~~es~~|Input or I/O Transient Voltage Applied|–0.5|3.63|V|
|VCCA_DPHYx<br>VCCPLL_DPHY<br>~~es~~<br>~~es~~|MIPI D-PHY Supply Voltages|–0.5|1.32|V|
|—<br>~~es~~|Voltage Applied on MIPI D-PHY Pins|–0.5|1.32|V|
|TA<br>~~es~~<br>~~a~~<br>~~es~~|Storage Temperature (Ambient)|–65|150|°C|
|TJ<br>~~es~~|Junction Temperature (TJ)|—|+125|°C|
**Notes:**
Stress above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. Functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Compliance with the Lattice Thermal Management document is required.
All voltages referenced to GND.
3. All voltages referenced to GND. **4.2. Recommended Operating Conditions Table 4.2. Recommended Operating Conditions[[1, 2]]** ~~a~~ **Symbol Parameter Min Max Unit**
## **4.2. Recommended Operating Conditions**
**Table 4.2. Recommended Operating Conditions[[1, 2]]**
|**Symbolymbolmbol**<br>~~a~~|**Parameter**<br>~~a~~|**Min**<br>~~a~~|**Max**<br>~~a~~|**Unit**<br>~~a~~|
|---|---|---|---|---|
|VCC<br>~~a~~<br>~~a~~|Core Supply Voltage<br>~~a~~<br>~~a~~|1.14<br>~~a~~<br>~~a~~|1.26<br>~~a~~<br>~~a~~|V<br>~~a~~<br>~~a~~|
|VCCGPLL<br>~~a~~<br>~~GG~~<br>~~nnn~~|PLL Supply Voltage<br>~~a~~<br>~~GG~~<br>~~nnn~~|1.14<br>~~a~~<br>~~GG~~|1.26<br>~~a~~<br>~~GG~~|V<br>~~a~~<br>~~GG~~|
|VCCAUX3<br>~~nnn~~<br>~~es~~|Auxiliary Supply Voltage for Bank 1, 2 and NVCM - @ 2.5 V<br>~~nnn~~|2.375|2.625|V|
||Auxiliary Supply Voltage for Bank 1, 2 and NVCM - @ 3.3 V<br>~~nnn~~<br>~~Ge~~|3.135<br>~~Ge~~|3.465<br>~~Ge~~|V<br>~~Ge~~|
|VCCIO0<br>~~nnn~~<br>~~es~~|I/O Driver Supply Voltage for Bank 0<br>~~nnn~~<br>~~Ge~~|1.71<br>~~Ge~~|3.465<br>~~Ge~~|V<br>~~Ge~~|
|VCCIO1/2<br>~~es~~<br>~~a~~<br>~~ee~~|I/O Driver Supply Voltage for Bank 1, 2<br>~~Ge~~|1.14<br>~~Ge~~|3.465<br>~~Ge~~|V<br>~~Ge~~|
|TJAUTO<br>~~a~~<br>~~ee~~<br>~~I~~|Junction Temperature, Automotive Operation<br>~~I~~|–40|125|°C|
|**D-PHY External Power Supply**<br>~~ee~~<br>~~I~~<br>~~eeeeeeeeeeEDR9DANDNnN'.—~~<br>~~ee~~|||||
|VCCA_DPHYx<br>~~I~~<br>~~eeeeeeeeeeEDR9DANDNnN'.—~~<br>~~ee~~<br>~~ee~~|AnalogSupplyVoltage for D-PHY<br>~~I~~<br>~~eeeeeeeeeeEDR9DANDNnN'.—~~|1.14<br>~~eeeeeeeeeeEDR9DANDNnN'.—~~|1.26<br>~~eeeeeeeeeeEDR9DANDNnN'.—~~|V<br>~~eeeeeeeeeeEDR9DANDNnN'.—~~|
|VCCPLL_DPHYx<br>~~ee~~<br>~~ee~~|PLL Supplyvoltage for D-PHY|1.14|1.26|V|
For correct operation, all supplies must be held in their valid operation range.
Like power supplies, must be tied together if they are at the same supply voltage. Follow the noise filtering recommendations in CrossLink Hardware Checklist (FPGA-TN-02013).
VCCAUX can operate at either 2.5 V +/- 5% or 3.3 V +/- 5%.
© 2015-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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**CrossLink Automotive Family Data Sheet**
## **4.3. Power Supply Ramp Rates**
## **Table 4.3. Power Supply Ramp Rates***
|**Symbol**|**Parameter**|**Min**|**Max**|**Unit**|
|---|---|---|---|---|
|tRAMP|Power supply ramp rates for all power supplies|0.6|10|V/ms|
***Note:** Assume monotonic ramp rates.
## **4.4. Power-On-Reset Voltage Levels**
## **Table 4.4. Power-On-Reset Voltage Levels[1, 3, 4]**
|**Symbol**|**Parameter**|**Parameter**|**Min**|**Max**|**Unit**|
|---|---|---|---|---|---|
|VPORUP|Power-On-Reset ramp up trip point<br>(Monitoring VCC, VCCIO0, and VCCAUX)|VCC|0.62|0.93|V|
|||VCCIO02|0.87|1.50|V|
|||VCCAUX|0.90|1.53|V|
|VPORDN|Power-On-Reset ramp down trip point<br>(Monitoring VCC, VCCIO0, and VCCAUX)|VCC|—|0.79|V|
|||VCCIO02|—|1.50|V|
|||VCCAUX|—|1.53|V|
## **Notes:**
These POR ramp up trip points are only provided for guidance. Device operation is only characterized for power supply voltages specified under recommended operating conditions.
Only VCCIO0 (Config Bank) has a Power-On-Reset ramp up trip point. All other VCCIOs do not have Power-On-Reset ramp up detection.
VCCIO supplies should be powered-up before or together with the VCC and VCCAUX supplies.
Configuration starts after VCC, VCCIO0 and VCCAUX reach VPORUP. For details, see tCONFIGURATION time in Table 4.21.
## **4.5. ESD Performance**
Refer to LIFMD Product Family Qualification Summary for complete qualification data, including ESD performance.
© 2015-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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FPGA-DS-02013-1.2
**CrossLink Automotive Family Data Sheet**
## **4.6. DC Electrical Characteristics**
Over recommended operating conditions.
**Table 4.5. DC Electrical Characteristics**
|**Symbol**<br>~~|~~<br>~~es~~|**Parameter**<br>~~|~~|**Condition**<br>~~|~~<br>~~es~~|**Min**<br>~~|~~<br>~~es~~|**Typ**<br>~~|~~<br>~~es~~|**Max**<br>~~|~~<br>~~es~~|**Unit**<br>~~|~~<br>~~es~~|
|---|---|---|---|---|---|---|
|IIL, IIH1, 4, 5<br>~~|~~<br>~~es~~|Input or I/O Leakage<br>~~|~~|0 ≤ VIN≤ VCCIO<br>~~|~~<br>~~es~~|−10<br>~~|~~<br>~~es~~|—<br>~~|~~<br>~~es~~|+10<br>~~|~~<br>~~es~~|µA<br>~~|~~<br>~~es~~|
|IPU4<br>~~es~~<br>~~ee~~|Internal Pull-Up Current<br>~~ee~~|VCCIO= 1.8 V between 0 ≤ VIN≤ 0.65 * VCCIO<br>~~es~~<br>~~ee~~|−3<br>~~es~~<br>~~ee~~|—<br>~~es~~<br>~~ee~~|−31<br>~~es~~<br>~~ee~~|µA<br>~~es~~<br>~~ee~~|
|||VCCIO= 2.5 V between 0 ≤ VIN≤ 0.65 * VCCIO<br>~~ee~~|−8<br>~~ee~~|—<br>~~ee~~|−72<br>~~ee~~|µA<br>~~ee~~|
|||VCCIO= 3.3 V between 0 ≤ VIN≤ 0.65 * VCCIO<br>~~ee~~<br>~~ee~~|−11<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~|−128<br>~~ee~~<br>~~ee~~|µA<br>~~ee~~<br>~~ee~~|
|C12<br>~~a ee~~|I/O Capacitance2<br>~~ee~~|VCCIO= 3.3 V, 2.5 V, 1.8 V, 1.2 V,<br>VCC= 1.2 V, VIO= 0 to VIH(MAX)<br>~~ee~~|—<br>~~ee~~|6<br>~~ee~~|—<br>~~ee~~|pF<br>~~ee~~|
|C22<br>~~a~~|Dedicated Input<br>Capacitance2<br>~~ee~~|VCCIO= 3.3 V, 2.5 V, 1.8 V, 1.2 V,<br>VCC= 1.2 V, VIO= 0 to VIH(MAX)<br>~~ee~~|—<br>~~ee~~|6<br>~~ee~~|—<br>~~ee~~|pF<br>~~ee~~|
|C32<br>~~a~~<br>~~a ee~~|MIPI D-PHY High Speed IO<br>Capacitance<br>~~ee~~<br>~~ee~~|VCCIO= 2.5V,VCC= 1.2V, VCC*_DPHY= 1.2V , VIO<br>= 0 to VIH(MAX)<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~|5<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~|pF<br>~~ee~~<br>~~ee~~|
|VHYST3<br>~~a ee~~<br>~~a~~|Hysteresis for Single-<br>Ended Inputs<br>~~ee~~|VCCIO= 3.3 V, 2.5 V, 1.8 V<br>VCC= 1.2 V, VIO= 0 to VIH(MAX)<br>~~ee~~|—<br>~~ee~~|200<br>~~ee~~|—<br>~~ee~~|mV<br>~~ee~~|
## **Notes:**
Input or I/O leakage current is measured with the pin configured as an input or as an I/O with the output driver tristated. It is not measured with the output driver active. Bus maintenance circuits are disabled.
TA = 25[o] C, f = 1.0 MHz.
Hysteresis is not available for VCCIO = 1.2 V.
Weak pull-up setting. Programmable pull-up resistors on Bank 0 will see higher current. Refer to CrossLink sysI/O Usage Guide (FPGA-TN-02016) for details on programmable pull-up resistors.
Input pins are clamped to VCCIO and GND by a diode. When input is higher than VCCIO, or lower than GND, the Input Leakage current will be higher than the IIL and IIH.
© 2015-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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**CrossLink Automotive Family Data Sheet**
## **4.7. CrossLink Automotive Supply Current**
Over recommended operating conditions.
**Table 4.6. CrossLink Automotive Supply Current**
|**Symbol**<br>~~a~~|**Parameter**<br>~~a~~|**Typ**<br>~~a~~|**Unit**<br>~~a~~|
|---|---|---|---|
|**Normal Operation1**<br>~~a~~<br>~~a~~||||
|ICC<br>~~a~~|Vcc Power Supply Current<br>~~a~~|7<br>~~a~~|mA<br>~~a~~|
|ICCPLL<br>~~a~~<br>~~Rs~~|PLL Power Supply Current<br>~~a~~|50<br>~~a~~|µA<br>~~a~~|
|ICCAUX<br>~~Rs~~|Auxiliary Power Supply Current for Bank 1, 2 and NVCM Programming Supply Current|3|mA|
|ICCIOx<br>~~Rs~~<br>~~a~~|Bank x Power Supply Current (per Bank)|60|µA|
|ICCA_DPHYx<br>~~a~~|VCCA_DPHYxPower Supply Current|8.5|mA|
|ICCPLL_DPHYx<br>~~a~~|VCCPLL_DPHYxPower Supply Current<br>|1.5<br>|mA<br>|
|**Standby Current2**<br>~~ape~~||||
|ICC_STDBY<br>~~a~~|Vcc Power Supply Standby Current|4|mA|
|ICCPLL_STDBY<br>~~a~~<br>~~a~~|PLL Power Supply Standby Current|10|µA|
|ICCAUX_STDBY<br>~~a~~<br>~~a~~|Auxiliary Power Supply Current for Bank 1, 2 and NVCM Programming Supply Standby Current<br>~~a~~|0.2<br>~~a~~|mA<br>~~a~~|
|ICCIOx_STDBY<br><br>~~a~~|Bank Power Supply Standby Current (per Bank)<br>~~a~~|6<br>~~a~~|µA<br>~~a~~|
|ICCA_DPHYx_STDBY<br><br>~~a~~<br>~~a~~|VCCA_DPHYxPower Supply Standby Current<br>~~a~~|6<br>~~a~~|µA<br>~~a~~|
|ICCPLL_DPHYx_STDBY<br>~~a~~|VCCPLL_DPHYxPower Supply Standby Current<br>|4<br>|µA<br>|
|**Sleep/Power Down Mode Current3**<br>~~ape~~||||
|ICC_SLEEP<br>~~a~~|Vcc Power Supply Sleep Current|0.2|mA|
|ICCPLL_SLEEP<br>~~a~~|PLL Power Supply Current|10|µA|
|ICCAUX_SLEEP<br>~~a~~|Auxiliary Power Supply Current for Bank 1, 2 and NVCM Programming Supply Current|20|µA|
|ICCIOx_SLEEP<br>~~a~~|Bank Power Supply Current (per Bank)|6|µA|
|ICCA_DPHY_SLEEP<br>~~a~~|VCCA_DPHYxPower Supply Sleep Current|6|µA|
|ICCPLL_DPHY_SLEEP<br>~~a~~|VCCPLL_DPHYxPower Supply Sleep Current|4|µA|
**Notes:**
## **Normal Operation**
- 2:1 MIPI CSI-2 Image Sensor Aggregator Bridge design under the following conditions:
- a. TJ = 25 °C, all power supplies at nominal voltages.
- b. Typical processed device in ctfBGA80 package.
- c. To determine power for all other applications and operating conditions, use Power Calculator in Lattice Diamond design software
## **Standby Operation**
A typically processed device in ctfBGA80 package with blank pattern programmed, under the following conditions:
- a. All outputs are tri-stated, all inputs are held at either VCCIO, or GND.
- b. All clock inputs are at 0 MHz.
- c. TJ = 25 °C, all power supplies at nominal voltages.
- d. No pull-ups on I/O.
## **Sleep/Power Down Mode**
- 2:1 MIPI CSI-2 Image Sensor Aggregator Bridge design under the following conditions:
- a. Design is put into Sleep/Power Down Mode with user logic powers down D-PHY, and enters into Sleep Mode in PMU.
- b. TJ = 25 °C, all power supplies at nominal voltages.
- c. Typical processed device in ctfBGA80 package.
- To determine the CrossLink Automotive start-up peak current, use the Power Calculator tool in the Lattice Diamond design software.
© 2015-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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**CrossLink Automotive Family Data Sheet**
## **4.8. Power Management Unit (PMU) Timing**
|**Symbol**<br>~~es~~|**Parameter**<br>~~es~~|**Device**<br>~~es~~|**Max**<br>~~es~~|**Unit**<br>~~es~~|
|---|---|---|---|---|
|tPMUWAKE<br>~~es~~|Time for PMU to wake from Sleep mode<br>~~es~~|All Devices<br>~~es~~|0.5<br>~~es~~|ms<br>~~es~~|
***Note:** For details on PMU usage, refer to Power Management and Calculation for CrossLink Devices (FPGA-TN-02018).
## **4.9. sysI/O Recommended Operating Conditions**
**Table 4.8. sysI/O Recommended Operating Conditions[1]**
|**Standard**<br>~~a~~|**VCCIO**|**VCCIO**|**VCCIO**|
|---|---|---|---|
||**Min**<br>~~Ge~~|**Typ**<br>~~Ge~~|**Max**|
|LVCMOS33/LVTTL33<br>~~ee~~<br>~~a~~|3.135<br>~~ee~~<br>~~Ge~~|3.30<br>~~ee~~<br>~~Ge~~|3.465<br>~~ee~~|
|LVCMOS25<br>~~ee~~<br>~~a~~|2.375<br>~~ee~~<br>~~Ge~~|2.50<br>~~ee~~<br>~~Ge~~|2.625<br>~~ee~~|
|LVCMOS18<br>~~GO~~|1.710<br>~~GO~~|1.80<br>~~GO~~|1.890<br>~~GO~~|
|LVCMOS12 (Output only)2<br>~~GO~~<br>~~a~~|1.140<br>~~GO~~|1.20<br>~~GO~~|1.260<br>~~GO~~|
|subLVDS (Input only)<br>~~ES~~|1.710<br>~~eG~~<br>~~ES~~|1.80<br>~~eG~~<br>~~ES~~|1.890<br>~~eG~~<br>~~ES~~|
||2.375<br>~~ES~~|2.50<br>~~ES~~|2.625<br>~~ES~~|
||3.135<br>~~ES~~<br>~~eG~~|3.30<br>~~ES~~<br>~~eG~~|3.465<br>~~ES~~<br>~~eG~~|
|SLVS200 (Input only)3<br>~~SSS~~|1.140<br>~~SSS~~|1.20<br>~~SSS~~|1.260<br>~~SSS~~|
||1.710<br>~~SSS~~<br>~~eG~~|1.80<br>~~SSS~~<br>~~eG~~|1.890<br>~~SSS~~<br>~~eG~~|
||2.375<br>~~SSS~~<br>~~pf~~|2.50<br>~~SSS~~<br>~~pf~~|2.625<br>~~SSS~~<br>~~pf~~|
||3.135<br>~~SSS~~<br>~~pf~~<br>~~Ge~~|3.30<br>~~SSS~~<br>~~pf~~<br>~~Ge~~|3.465<br>~~SSS~~<br>~~pf~~<br>~~Ge~~|
|LVDS (Input only)<br>~~ee~~|1.710<br>~~ee~~|1.80<br>~~ee~~|1.890<br>~~ee~~|
||2.375<br>~~ee~~<br>~~Ge~~|2.50<br>~~ee~~<br>~~Ge~~|2.625<br>~~ee~~<br>~~Ge~~|
||3.135<br>~~ee~~<br>~~Ge~~<br>~~Ge~~|3.30<br>~~ee~~<br>~~Ge~~<br>~~Ge~~|3.465<br>~~ee~~<br>~~Ge~~<br>~~Ge~~|
|LVDS (Output only)<br>~~a~~|2.375|2.50|2.625|
|MIPI (Input only)<br>~~a~~<br>~~a~~|1.140<br>~~A~~|1.20<br>~~G~~|1.260|
**Note:**
For input voltage compatibility, refer to CrossLink sysI/O Usage Guide (FPGA-TN-02016).
For VCCIO1 and VCCIO2 only.
For SLVS200/MIPI interface I/O placement, see the Programmable I/O Banks section.
## **4.10. sysI/O Single-Ended DC Electrical Characteristics**
**Table 4.9. sysI/O Single-Ended DC Electrical Characteristics**
|**Input/Output**<br>**Standard**|**VIL**|**VIL**|**VIH**|**VIH**|**VOLMax**<br>**(V)**|**VOHMin**<br>**(V)**|**IOL**<br> **(mA)**|**IOH**<br>**(mA)**|
|---|---|---|---|---|---|---|---|---|
||**Min(V)**|**Max(V)**|**Min(V)**|**Max(V)**|||||
|LVCMOS33/<br>LVTTL33|–0.3|0.8|2.0|VCCIO+0.2|0.40|VCCIO− 0.4|8|–8|
||||||0.20|VCCIO− 0.2|0.1|–0.1|
|LVCMOS25|–0.3|0.7|1.7|VCCIO+0.2|0.40|VCCIO− 0.4|6|–6|
||||||0.20|VCCIO− 0.2|0.1|–0.1|
|LVCMOS18<br>~~|~~|–0.3<br>|0.35 VCCIO<br>|0.67 VCCIO<br>|VCCIO+0.2<br>|0.40|VCCIO− 0.4|4|–4|
||||||0.20<br>~~**e**e~~|VCCIO− 0.2<br>~~ee~~|0.1<br>~~eee~~|–0.1<br>~~eee~~<br>~~—~~|
|LVCMOS12*<br>(Output only)<br>~~|~~|—<br>~~e~~|—<br>~~e~~|—<br>~~e~~|—<br>~~e~~|0.40<br>~~**e**e~~|VCCIO− 0.4<br>~~ee~~|2<br>~~eee~~|–2<br>~~eee~~<br>~~—~~|
||||||0.20<br>~~**e**e~~|VCCIO− 0.2<br>~~ee~~|0.1<br>~~eee~~|–0.1<br>~~eee~~<br>~~—~~|
***Note:** For VCCIO1 and VCCIO2 only.
© 2015-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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**CrossLink Automotive Family Data Sheet**
## **4.11. sysI/O Differential Electrical Characteristics**
## **4.11.1. LVDS/subLVDS/SLVS200**
Over recommended operating conditions.
**Table 4.10. LVDS/subLVDS[1] /SLVS200[1, 2]**
|**Parameter**<br>~~OT~~|**Description**<br>~~OT~~|**Test Conditions**<br>~~OT~~|**Min**<br>~~OT~~|**Typ**<br>~~OT~~|**Max**<br>~~OT~~|**Unit**<br>~~OT~~|
|---|---|---|---|---|---|---|
|VINP, VINN<br>~~OT~~<br>~~a~~|Input Voltage<br>~~OT~~|—<br>~~OT~~|0.00<br>~~OT~~|—<br>~~OT~~|2.40<br>~~OT~~|V<br>~~OT~~|
|VCM<br>~~a~~|Input Common Mode Voltage<br>~~a~~|Half the sum of the two inputs<br>~~a~~|0.05<br>~~a~~|—<br>~~a~~|2.35<br>~~a~~|V<br>~~a~~|
|VTHD(LVDS)<br>~~a~~|Differential Input Threshold<br>~~a~~|ǀVINP- VINNǀ<br>~~a~~|100<br>~~a~~|—<br>~~a~~|—<br>~~a~~|mV<br>~~a~~|
|VTHD(subLVDS)<br>~~a~~|Differential Input Threshold<br>~~a~~|ǀVINP- VINNǀ<br>~~a~~|90<br>~~a~~|—<br>~~a~~|—<br>~~a~~|mV<br>~~a~~|
|VTHD(SLVS200)<br>~~a~~<br>~~ee~~|Differential Input Threshold<br>~~a~~|ǀVINP- VINNǀ<br>~~a~~<br>~~a~~|70<br>~~a~~<br>~~a~~|—<br>~~a~~<br>~~a~~|—<br>~~a~~<br>~~a~~|mV<br>~~a~~<br>~~a~~|
|IIN<br>~~ee~~|Input Current|Normal Mode<br>~~a~~|−10<br>~~a~~|—<br>~~a~~|10<br>~~a~~|µA<br>~~a~~|
|||Standby Mode<br>~~a~~|−10<br>~~a~~|—<br>~~a~~|10<br>~~a~~|µA<br>~~a~~|
|VOH<br>~~ee~~<br>~~a~~|Output High Voltage for VOPor VOM|RT = 100 Ω<br>~~a~~|—<br>~~a~~|1.43<br>~~a~~|1.60<br>~~a~~|V<br>~~a~~|
|VOL<br>~~a~~|Output Low Voltage for VOPor VOM|RT = 100 Ω|0.90|1.08|—|V|
|VOD<br>~~a~~<br>~~a~~|Output Voltage Differential||VOP- VOM|, RT = 100 Ω|250|350|450|mV|
|∆VOD<br>~~a~~|Change in VODbetween High and<br>Low|—|—|—|50|mV|
|VOS<br>~~a~~|Output Voltage Offset (Common<br>Mode Voltage)|(VOP+ VOM)/2, RT = 100 Ω|1.125|1.250|1.375|V|
|∆VOS<br>~~a~~<br>~~a~~|Change in VOSbetween H and L|—|—|—|50|mV|
|ISAB<br>~~a~~|Output Short Circuit Current|VOD= 0 V driver outputs shorted to<br>each other|—|—|12|mA|
## **Notes:**
1. Inputs only for subLVDS and SLVS200.
2. For SLVS200/MIPI interface I/O placement, see the Programmable I/O Banks section.
© 2015-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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FPGA-DS-02013-1.2
**CrossLink Automotive Family Data Sheet**
## **4.11.2. Hardened MIPI D-PHY I/Os**
**Table 4.11. MIPI D-PHY**
|**Symbol**<br>~~a~~|**Description**<br>|**Min**<br>|**Typ**<br>|**Max**<br>|**Unit**<br>|
|---|---|---|---|---|---|
|**Receiver**<br>~~aPd~~||||||
|**High Speed**<br>~~Pd~~<br>~~a~~<br>~~es~~||||||
|VCMRX<br>~~a~~<br>~~es~~<br>~~Rs~~|Common-Mode Voltage HS Receive Mode<br>~~a~~|70<br>~~a~~|—<br>~~a~~|330<br>~~a~~|mV<br>~~a~~|
|VIDTH<br>~~es~~<br>~~Rs~~<br>~~Rs~~|Differential Input High Threshold|—|—|70|mV|
|VIDTL<br>~~Rs~~<br>~~Rs~~|Differential Input Low Threshold|−70|—|—|mV|
|VIHHS<br>~~Rs~~<br>~~a~~<br>~~es~~|Single-ended input High Voltage|—|—|460|mV|
|VILHS<br>~~es~~<br>~~es~~|Single-ended Input Low Voltage<br>~~(~~|−40|—|—|mV|
|VTERM-EN<br>~~es~~<br>~~es~~|Single-ended Threshold for HS Termination Enable<br>~~(~~|—|—|450|mV|
|ZID<br>~~es~~<br>~~a ~~|Differential Input Impedance<br>~~(~~<br> ~~GO~~|80<br>~~GO~~|100<br>~~GO~~|125<br>~~GO~~|Ω<br>~~GO~~|
|**Low Power**<br>~~eee~~<br>~~es~~||||||
|VIH<br>~~eee~~<br>~~es~~|Logic 1 Input Voltage<br>~~eee~~|880<br>~~eee~~|—<br>~~eee~~|—<br>~~eee~~|mV<br>~~eee~~|
|VIL<br>~~es~~<br>~~GO~~<br>~~es~~|Logic 0 Input Voltage, not in ULP State<br>~~GO~~<br>|—<br>~~GO~~<br>|—<br>~~GO~~<br>|550<br>~~GO~~<br>|mV<br>~~GO~~<br>|
|VIL-ULPS<br>~~es~~|Logic 0 Input Voltage, in ULP State<br>|—<br>|—<br>|300<br>|mV<br>|
|VHYST<br>~~esa~~|Input Hysteresis<br>~~a~~|23.0<br>~~a~~|—<br>~~a~~|—<br>~~a~~|mV<br>~~a~~|
|**Transmitter**<br>~~a~~||||||
|**High Speed**<br>~~a~~<br>~~aE~~||||||
|VCMTX<br>~~a~~|HS Transmit Static Common Mode Voltage<br>|150<br>|200<br>|250<br>|mV<br>|
|VOD<br>~~CO~~|HS Transmit Differential Voltage<br>~~CO~~|140<br>~~CO~~|200<br>~~CO~~|270<br>~~CO~~|mV<br>~~CO~~|
|VOHHS<br>~~a~~<br>~~es~~|HS Single-ended Output High Voltage|—|—|360|mV|
|ZOS<br>~~es~~|Single-ended Output Impedance|40|50|62.5|Ω|
|ΔZOS<br>~~es~~<br>~~eG~~|Single-ended Output Impedance Mismatch<br>~~eG~~|—<br>~~eG~~|—<br>~~eG~~|10<br>~~eG~~|%<br>~~eG~~|
|**Low Power**<br>~~eee~~||||||
|VOH<br>~~eee~~<br>~~a~~<br>~~es~~|Output High Voltage<br>~~eee~~|1.1<br>~~eee~~|1.2<br>~~eee~~|1.3<br>~~eee~~|V<br>~~eee~~|
|VOL<br>~~es~~<br>~~es~~|Output Low Voltage|−50|—|50|mV|
|ZOLP<br>~~es~~<br>~~es~~|Output Impedance in LP Mode|110|—|—|Ω|
© 2015-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02013-1.2
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**CrossLink Automotive Family Data Sheet**
## **4.12. CrossLink Automotive Maximum General Purpose I/O Buffer Speed**
Over recommended operating conditions.
**Table 4.12. CrossLink Automotive Maximum I/O Buffer Speed**
|**Buffer**<br>~~a~~|**Description**<br>~~a~~<br>~~|~~|**Max**<br>~~a~~<br>~~|~~|**Unit**<br>~~a~~<br>~~|~~|
|---|---|---|---|
|**Maximum Input Frequency**<br>~~a~~<br>~~|~~<br>~~a~~||||
|LVDS25<br>~~a~~<br>~~po~~|LVDS, VCCIO= 2.5 V, VID= 200 mV<br>~~a~~<br>~~po~~|600<br>~~a~~<br>~~po~~|MHz<br>~~a~~<br>~~po~~|
|subLVDS<br>~~po~~|subLVDS, VCCIO= 2.5 V, VID= 150 mV<br>~~po~~|600<br>~~po~~|MHz<br>~~po~~|
|MIPI D-PHY (HS Mode)6<br>~~po~~<br>~~a~~<br>~~a~~|MIPI D-PHY<br>~~po~~<br>|600<br>~~po~~<br>|MHz<br>~~po~~<br>|
|MIPI D-PHY(LP Mode)<br>~~a~~|MIPI D-PHY<br>|5<br>|MHz<br>|
|SLVS200<br>~~apT~~|SLVS200, VCCIO=2.5 V<br>~~pT~~|600<br>~~pT~~|MHz<br>~~pT~~|
|LVCMOS33/LVTTL33<br>~~pT~~<br>~~a~~|LVCMOS/LVTTL, VCCIO= 3.3 V<br>~~pT~~|300<br>~~pT~~|MHz<br>~~pT~~|
|LVCMOS25D<br>~~a~~<br>~~sO~~|Differential LVCMOS, VCCIO= 2.5 V<br>~~sO~~|300<br>~~sO~~|MHz<br>~~sO~~|
|LVCMOS25<br>~~sO~~<br>~~a~~<br>~~po~~|LVCMOS, VCCIO= 2.5 V<br>~~sO~~|300<br>~~sO~~|MHz<br>~~sO~~|
|LVCMOS18<br>~~a~~<br>~~po~~<br>~~OO~~|LVCMOS, VCCIO= 1.8 V<br>~~—_SSCSCSs~~|155<br>~~—_SSCSCSs~~|MHz<br>~~—_SSCSCSs~~|
|**Maximum Output Frequency**<br>~~po~~<br>~~OO~~<br>~~—_SSCSCSs~~||||
|LVDS25<br>~~OO~~<br>~~Ge~~|LVDS, VCCIO= 2.5 V<br>~~—_SSCSCSs~~<br>~~Ge~~|555<br>~~—_SSCSCSs~~<br>~~Ge~~|MHz<br>~~—_SSCSCSs~~<br>~~Ge~~|
|LVCMOS33/LVTTL33<br>~~Ge~~<br>~~a~~|LVCMOS/LVTTL, VCCIO= 3.3 V<br>~~Ge~~|300<br>~~Ge~~|MHz<br>~~Ge~~|
|LVTTL33D<br>~~a~~<br>~~a~~|Differential LVTTL, VCCIO= 3.3 V|300|MHz|
|LVCMOS33D<br>~~a~~|Differential LVCMOS, 3.3 V|300|MHz|
|LVCMOS25<br>~~a~~<br>~~Ge~~|LVCMOS, 2.5 V<br>~~Ge~~|215<br>~~Ge~~|MHz<br>~~Ge~~|
|LVCMOS25D<br>~~GO~~|Differential LVCMOS, 2.5 V<br>~~GO~~|215<br>~~GO~~|MHz<br>~~GO~~|
|LVCMOS18<br>~~sD~~|LVCMOS, 1.8 V<br>~~sD~~|155<br>~~sD~~|MHz<br>~~sD~~|
|LVCMOS12<br>~~Gn~~|LVCMOS, VCCIO1/2= 1.2 V<br>~~Gn~~|70<br>~~Gn~~|MHz<br>~~Gn~~|
## **Notes:**
These maximum speeds are characterized but not tested on every device.
Maximum I/O speed for differential output standards emulated with resistors depends on the layout.
LVCMOS timing is measured with the load specified in Table 4.22.
Actual system operation may vary depending on user logic implementation.
- Maximum data rate equals two times the clock rate when utilizing DDR.
6. This is the maximum MIPI D-PHY input rate on the programmable I/O banks 1 and 2. The hardened MIPI D-PHY input and output rates are described in Hardened MIPI D-PHY Performance section. For SLVS200/MIPI interface I/O placement, see the Programmable I/O Banks section.
7. To ensure the MIPI Rx interface is implemented optimally in the FPGA fabric with the Programmable I/Os, follow the guidelines of assigning I/Os to the bank for the MIPI Rx inputs: When an SLVS200/MIPI Rx interface is placed in Bank 1 or 2, do not place LVCMOS outputs on both Banks 1 and 2.
© 2015-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
34
FPGA-DS-02013-1.2
**CrossLink Automotive Family Data Sheet**
## **4.13. CrossLink Automotive External Switching Characteristics**
**Table 4.13. CrossLink Automotive External Switching Characteristics[4]**[,] **[ 5]**
|**Parameter**<br>~~ee~~|**Description**<br>~~ee~~|**Conditions**<br>~~ee~~|**–6**<br>~~Po~~<br>~~ee~~|**–6**<br>~~Po~~<br>~~ee~~|**Unit**<br>~~ee~~|
|---|---|---|---|---|---|
||||**Min**<br>~~ee~~|**Max**<br>~~ee~~||
|**Clocks**<br>~~|~~||||||
|**Primary Clock**<br>~~|~~<br>~~CO~~||||||
|fMAX_PRI<br>~~a~~|Frequencyfor PrimaryClock Tree<br>~~a~~<br>~~Ga~~|—<br>~~a~~<br>~~Ga~~|—<br>~~a~~<br>~~Ga~~<br>~~CO~~|150<br>~~a~~<br>~~Ga~~<br>~~CO~~|MHz<br>~~a~~<br>~~Ga~~|
|tW_PRI<br>~~Ge~~|Clock Pulse Width for Primary Clock<br>~~Ge~~|—<br>~~Ge~~|0.8<br>~~CO~~<br>~~Ge~~|—<br>~~CO~~<br>~~Ge~~|ns<br>~~Ge~~|
|tSKEW_PRI<br>~~Ge~~<br>~~a ~~|PrimaryClock Skew Within a Clock<br>~~Ge~~<br> ~~Ge~~|—<br>~~Ge~~<br>~~Ge~~|—<br>~~Ge~~<br>~~Ge~~<br>~~CO~~|450<br>~~Ge~~<br>~~Ge~~<br>~~CO~~|ps<br>~~Ge~~<br>~~Ge~~|
|**Edge Clock**<br>~~CO~~<br>~~|~~||||||
|fMAX_EDGE<br>~~|~~<br>~~a~~|Frequencyfor Edge Clock Tree<br>~~|~~<br>~~a~~<br>~~GO~~|—<br>~~|~~<br>~~a~~<br>~~GO~~|—<br>~~|~~<br>~~a~~<br>~~GO~~|600<br>~~|~~<br>~~a~~<br>~~GO~~|MHz<br>~~|~~<br>~~a~~<br>~~GO~~|
|tW_EDGE<br>~~a~~<br>~~a~~|Clock Pulse Width for Edge Clock<br>~~a~~<br>~~GO~~<br>~~GO~~|—<br>~~a~~<br>~~GO~~<br>~~GO~~|0.783<br>~~a~~<br>~~GO~~<br>~~GO~~|—<br>~~a~~<br>~~GO~~<br>~~GO~~|ns<br>~~a~~<br>~~GO~~<br>~~GO~~|
|tSKEW_EDGE<br>~~a ~~<br>~~pO~~|Edge Clock Skew Within a Bank<br> ~~GO~~<br>~~pO~~|—<br>~~GO~~<br>~~pO~~|—<br>~~GO~~<br>~~pO~~|140<br>~~GO~~<br>~~pO~~|ps<br>~~GO~~<br>~~pO~~|
|**Generic SDR Interface1**<br>~~pO~~<br>~~|~~<br>~~OE~~<br>~~eeeeeeeeEHD''DN9AN9N9—_—_~~||||||
|**General Purpose I/O Pin Parameters Using Clock Tree Without PLL**<br>~~OE~~<br>~~eeeeeeeeEHD''DN9AN9N9—_—_~~||||||
|tCO<br>~~OE~~<br>~~eG~~|Clock to Output – PIO Input Register<br>~~OE~~<br>~~eG~~|—<br>~~OE~~<br>~~eeeeeeeeEHD''DN9AN9N9—_—_~~<br>~~eG~~|—<br>~~eeeeeeeeEHD''DN9AN9N9—_—_~~<br>~~eG~~|5.53<br>~~eeeeeeeeEHD''DN9AN9N9—_—_~~<br>~~eG~~|ns<br>~~eeeeeeeeEHD''DN9AN9N9—_—_~~<br>~~eG~~|
|tSU<br>~~OO~~|Clock to Data Setup– PIO Input<br>~~OO~~|—<br>~~OO~~|−0.93<br>~~OO~~|—<br>~~OO~~|ns<br>~~OO~~|
|tHD<br>~~OO~~<br>~~SS~~|Clock to Data Hold – PIO Input<br>~~OO~~<br>|—<br>~~OO~~<br>|1.83<br>~~OO~~<br>|—<br>~~OO~~<br>|ns<br>~~OO~~<br>|
|tSU_DELAY<br>~~SS~~|Clock to Data Setup – PIO Input<br>Register with Input Delay for zero<br>tHD<br>|With data input delay<br>for hold time = 0<br>|1.28<br>|—<br>|ns<br>|
|tHD_DELAY<br>~~SS~~|Clock to Data Hold – PIO Input<br>Register with Input Delay for zero<br>tHD<br>|With data input delay<br>for hold time = 0<br>|-0.34<br>|—<br>|ns<br>|
|**General Purpose I/O Pin Parameters Using Clock Tree With PLL**<br>~~a~~||||||
|tCO<br>~~eG~~|Clock to Output – PIO Input Register<br>~~eG~~|—<br>~~eG~~|—<br>~~eG~~|4.12<br>~~eG~~|ns<br>~~eG~~|
|tSU<br>~~eG~~|Clock to Data Setup– PIO Input<br>~~eG~~|—<br>~~eG~~|0.20<br>~~eG~~|—<br>~~eG~~|ns<br>~~eG~~|
|tHD<br>~~eG~~<br>~~eG~~|Clock to Data Hold – PIO Input<br>~~eG~~<br>~~eG~~|—<br>~~eG~~<br>~~eG~~|0.42<br>~~eG~~<br>~~eG~~|—<br>~~eG~~<br>~~eG~~|ns<br>~~eG~~<br>~~eG~~|
|tSU_DELAY<br>~~eG~~|Clock to Data Setup – PIO Input<br>Register with Input Delay for zero<br>tHD<br>~~eG~~|With data input delay<br>for hold time = 0<br>~~eG~~|1.67<br>~~eG~~|—<br>~~eG~~|ns<br>~~eG~~|
|tHD_DELAY|Clock to Data Hold – PIO Input<br>Register with Input Delay for zero<br>tHD|With data input delay<br>for hold time = 0|-1.03|—|ns|
|**Generic DDR Interfaces2**<br>~~|~~||||||
|**Generic DDRX8 or DDRX4 or DDRX2 I/O with Clock and Data Centered at General Purpose Pins (GDDRX8_RX/TX.ECLK.Centered**<br>**or GDDRX4_RX/TX.ECLK.Centered or GDDRX2_RX/TX.ECLK.Centered)**<br>~~|~~||||||
|tSU_GDDRX2_4_8_CENTERED|Input Data Set-Up Before CLK Rising<br>and Fallingedges|—|0.167|—|ns|
|tHD_GDDRX2_4_8_CENTERED|Input Data Hold After CLK Rising<br>and Fallingedges|—|0.167|—|ns|
|tDVB_GDDRX2_4_8_CENTERED<br>~~a~~|Output Data Valid Before CLK<br>Output Rising and Falling edges<br>~~a~~<br>~~a ~~|Data Rate = 1.2 Gb/s6<br>~~a~~<br>~~es~~|0.297<br>~~a~~<br>~~es~~|—<br>~~a~~<br>~~es~~|ns<br>~~a~~<br>~~es~~|
|||Other Data Rates6<br>~~a~~<br> ~~es~~|−0.120<br>~~a~~<br>~~es~~|—<br>~~a~~<br>~~es~~|ns+1/2UI<br>~~a~~<br>~~es~~|
|tDVA_GDDRX2_4_8_CENTERED<br>~~a~~|Output Data Valid After CLK Output<br>Rising and Falling edges|Data Rate = 1.2 Gb/s6<br>~~ee~~|0.297<br>~~ee~~|—<br>~~ee~~|ns<br>~~ee~~|
|||Other Data Rates6<br>~~ee~~|−0.120<br>~~ee~~|—<br>~~ee~~|ns+1/2UI<br>~~ee~~|
|fMAX_GDDRX2_4_8_CENTERED<br>~~a~~<br>~~a~~|Frequency for ECLK3<br>~~po~~|GDDRX2<br>~~ee~~<br>~~po~~|—<br>~~ee~~|300<br>~~ee~~|MHz<br>~~ee~~|
|||GDDRX4 and GDDRX8<br>~~po~~|—|600|MHz|
© 2015-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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35
**CrossLink Automotive Family Data Sheet**
**Table 4.13. CrossLink Automotive External Switching Characteristics** ( _Continued_ )
|**Parameter**<br>~~a~~|**Description**<br>|**Conditions**<br>|**–6**<br>~~Po~~<br>|**–6**<br>~~Po~~<br>|**Unit**<br>|
|---|---|---|---|---|---|
||||**Min**<br>~~Po~~<br>|**Max**<br>~~Po~~<br>||
|**Generic DDRX1 I/O with Clock and Data Centered at General Purpose Pins(GDDRX1_RX/TX.SCLK.Centered)**<br>||||||
|tSU_GDDRX1_CENTERED<br>~~a~~|Input Data Set-Up Before CLK<br>Rising and Falling edges<br>~~a~~|—<br>~~a~~|0.917<br>~~a~~|—<br>~~a~~|ns<br>~~a~~|
|tHD_GDDRX1_CENTERED<br>~~a~~<br>~~a~~|Input Data Hold After CLK Rising<br>and Fallingedges<br>~~a~~<br>~~a~~<br>~~ee~~|—<br>~~a~~<br>~~a~~<br>~~ee~~|0.917<br>~~a~~<br>~~a~~<br>~~ee~~|—<br>~~a~~<br>~~a~~<br>~~ee~~|ns<br>~~a~~<br>~~a~~<br>~~ee~~|
|tDVB_GDDRX1_CENTERED<br>~~a~~|Output Data Valid Before CLK<br>Output Rising and Falling edges|Data Rate =<br>300 Mb/s<br>~~es~~|1.217<br>~~es~~|—<br>~~es~~|ns+1/2UI<br>~~es~~|
|||Other Data Rates<br>~~es~~|−0.450<br>~~es~~|—<br>~~es~~|ns+1/2UI<br>~~es~~|
|tDVA_GDDRX1_CENTERED<br>~~a~~<br>~~es~~|Output Data Valid After CLK<br>Output Rising and Falling edges<br>~~a~~|Data Rate =<br>300 Mb/s<br>~~a~~|1.217<br>|—<br>|ns+1/2UI<br>|
|||Other Data Rates<br>~~aee~~|−0.450<br>~~ee~~|—<br>~~ee~~|ns+1/2UI<br>~~ee~~|
|fMAX_GDDRX1_CENTERED<br>~~es~~|Frequency for PCLK3<br><br>~~G~~|—<br>~~ee~~<br>~~G~~|—<br>~~ee~~|150<br>~~ee~~|MHz<br>~~ee~~|
|**Generic DDRX8 or DDRX4 or DDRX2 I/O with Clock and Data Aligned at General Purpose Pins (GDDRX8_RX/TX.ECLK.Aligned or**<br>**GDDRX4_RX/TX.ECLK.Aligned or GDDRX2_RX/TX.ECLK.Aligned)**<br>~~ee~~<br>~~es~~<br>~~G~~<br>~~ee~~||||||
|tSU_GDDRX2_4_8_ALIGNED<br>~~ee~~|Input Data Valid After CLK Rising<br>and Falling edges<br>|Data Rate =<br>1.2 Gb/s6<br>|—<br>|0.188<br>|ns<br>|
|||Other Data Rates6<br>|—<br>|−0.229<br>|ns+1/2UI<br>|
|THD_GDDRX2_4_8_ALIGNED<br>~~eees~~|Input Data Hold After CLK Rising<br>and Falling edges<br>~~es~~|Data Rate =<br>1.2 Gb/s6<br>~~es~~|0.646<br>~~es~~|—<br>~~es~~|ns<br>~~es~~|
|||Other Data Rates6<br>~~es~~<br>~~2~~|0.229<br>~~es~~<br>~~2~~|—<br>~~es~~<br>~~2~~|ns+1/2UI<br>~~es~~<br>~~2~~|
|tDIA_GDDRX2_4_8_ALIGNED<br>~~a~~|Output Data Invalid After CLK<br>Risingand Fallingedges Output|—|—|0.120|ns|
|tDIB_GDDRX2_4_8_ALIGNED<br>~~a~~|Output Data Invalid Before CLK<br>Output Risingand Fallingedges|—|—|0.120|ns|
|fMAX_GDDRX2_4_8_ALIGNED<br>~~a~~<br>~~a ~~<br>~~nn~~|Frequency for ECLK3<br> ~~ee~~|GDDRX2<br>~~e~~|—<br>~~ee~~|300<br>~~ee~~|MHz|
|||GDDRX4 and GDDRX8<br>~~e~~|—<br>~~ee~~|600<br>~~ee~~|MHz|
|**Generic DDRX1 I/O with Clock and Data Aligned at General Purpose Pins(GDDRX1_RX/TX.SCLK.Aligned)**<br> ~~eeee~~<br>~~nn~~||||||
|TSU_GDDRX1_ALIGNED<br> <br>~~nn~~|Input Data Valid After CLK Rising and<br>Falling edges<br> ~~ee~~|Input Data Valid After CLK Rising and<br>Data Rate =<br>300 Mb/s<br>~~e~~|—<br>~~ee~~|0.750<br>~~ee~~|ns|
|||Other Data Rates<br>~~e~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~|**−**0.917<br>~~ee~~<br>~~ee~~|ns+1/2UI<br>~~ee~~|
|THD_GDDRX1_ALIGNED<br> <br>~~nn~~<br>~~a~~|Input Data Hold After CLK Rising and<br>Falling edges<br> ~~ee~~|Data Rate =<br>300 Mb/s<br>~~e ~~<br>~~ee~~<br>~~pO~~|2.583<br> ~~ee~~<br>~~ee~~<br>~~pO~~|—<br>~~ee~~<br>~~ee~~<br>~~pO~~|ns<br>~~ee~~<br>~~pO~~|
|||Other Data Rates<br>~~pO~~|0.916<br>~~pO~~|—<br>~~pO~~|ns+1/2UI<br>~~pO~~|
|tDIA_GDDRX1_ALIGNED<br>~~es~~|Output Data Invalid After CLK Rising<br>and Falling edges Output<br>~~es~~|—<br>~~es~~|—<br>~~es~~|0.450<br>~~es~~|ns<br>~~es~~|
|tDIB_GDDRX1_ALIGNED<br>~~es~~<br>~~a~~<br>|and Falling edges Output<br>Output Data Invalid Before CLK<br>Output Rising and Falling edges<br>~~es~~<br>~~Se~~|—<br>~~es~~<br>~~ee~~|—<br>~~es~~<br>~~ee~~|0.450<br>~~es~~<br>~~ee~~|ns<br>~~es~~<br>~~ee~~|
|fMAX_GDDRX1_ALIGNED<br>~~a~~|Frequencyfor ECLK3<br>~~Se~~|—<br>~~ee~~|—<br>~~ee~~|150<br>~~ee~~|MHz<br>~~ee~~|
|**General Purpose I/O MIPI D-PHY Rx with 1:8 or 1:16 Gearing**<br>~~a Se~~<br>~~ee~~<br>~~ee ee~~<br>~~ee~~||||||
|tSU_GDDRX_MP|Input Data Set-Up Before CLK|900 Mb/s < Data Rate<br>≤ 1.2 Gb/s and<br>VID= 140 mV|0.200|—|UI|
|||600 Mb/s < Data Rate<br>≤ 900 Mb/s and<br>VID= 140 mV|0.150|—|UI|
|||Data Rate ≤ 600 Mb/s<br>and<br>VID= 70 mV|0.150|—|UI|
© 2015-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
36
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**CrossLink Automotive Family Data Sheet**
**Table 4.13. CrossLink Automotive External Switching Characteristics** ( _Continued_ )
|**Parameter**<br>~~ee~~|**Parameter**<br>~~ee~~|**Description**<br>~~ee~~|**Conditions**<br>~~ee~~|**–6**<br>~~CL~~<br>~~ee~~<br>~~ee~~|**–6**<br>~~CL~~<br>~~ee~~<br>~~ee~~|**Unit**<br>~~ee~~<br>~~ee~~|
|---|---|---|---|---|---|---|
|||||**Min**<br>~~ee~~|**Max**<br>~~ee~~<br>~~ee~~||
|tHO_GDDRX_MP<br>~~ee~~<br>~~es~~||Input Data Hold After CLK<br>~~ee~~<br>~~e~~|900 Mb/s < Data<br>Rate ≤ 1.2 Gb/s and<br>VID= 140 mV<br>~~ee~~|0.200<br>~~ee~~|—<br>~~ee~~<br>~~ee~~|UI<br>~~ee~~<br>~~ee~~|
||||600 Mb/s < Data<br>Rate ≤ 900 Mb/s<br>and<br>VID= 140 mV|0.150|—|UI|
||||Data Rate ≤ 600<br>Mb/s and<br>VID= 70 mV<br>~~e~~~~**s**~~<br>~~r~~|0.150<br>~~**s**~~|—<br>~~**s**~~|UI<br>~~**s**~~|
|fMAX_GDDRX_MP<br>~~es~~||Frequency for ECLK3<br>~~e~~|—<br>~~e~~~~**s**~~<br>~~r~~|—<br>~~**s**~~|600<br>~~**s**~~|MHz<br>~~**s**~~|
|**Generic DDRX71 or DDRX141 Inputs(GDDRX71_RX.ECLK or GDDRX141_RX.ECLK)**<br>~~ese~~~~**s**~~<br>~~r~~<br>~~[~~<br>~~eseea~~|||||||
|tRPBi_DVA<br>~~es~~<br>~~een~~||Input Valid Bit "i" switching from CLK<br>Rising Edge<br>("i" = 0 to 6, 0 aligns with CLK)<br>~~es~~<br>~~een~~|—<br>~~es~~|—<br>~~ee~~|0.3<br>~~a~~|UI|
||||—<br>~~es~~<br>~~i~~<br>~~een~~|—<br>~~ee~~<br>~~a~~<br>~~een~~|−0.222<br>~~a~~<br>~~ee~~|ns+<br>(i+ 1/2)*UI|
|tRPBi_DVE<br>~~es~~<br>~~een~~<br>~~ee~~||Input Hold Bit "i" switching from CLK<br>Rising Edge<br>("i" = 0 to 6, 0 aligns with CLK)<br>~~es~~<br>~~een~~<br>~~es~~|—<br>~~es ~~<br>~~i ~~<br>~~een~~<br>~~e~~~~**e**~~|0.7<br> ~~ee ~~<br> ~~a~~<br>~~een~~<br>~~ee~~|—<br> ~~a~~<br>~~ee~~<br>~~ee~~|UI<br>~~ee~~|
||||—<br>~~een~~<br>~~e~~~~**e**~~<br>~~ee~~|0.222<br>~~een~~<br>~~ee~~<br>~~es~~|—<br>~~ee~~<br>~~ee~~<br>~~es~~|ns+<br>(i+ 1/2)*UI<br>~~ee~~|
|fMAX_RX71_141<br>~~een~~<br>~~ee~~||DDR71/DDR141 ECLK Frequency3<br>~~een~~<br>~~es~~|—<br>~~een ~~<br>~~e~~~~**e**~~<br>~~ee~~|—<br> ~~een ~~<br>~~ee~~<br>~~es~~|450<br> ~~ee~~<br>~~ee~~<br>~~es~~|MHz<br>~~ee~~|
|**Generic DDRX71 Outputs with Clock and Data Aligned at Pin(GDDRX71_TX.ECLK)**<br>~~e~~~~**e** ee~~<br>~~ee~~<br>~~ee~~<br>~~es ee~~<br>~~es~~<br>~~es~~|||||||
|tTPBi_DOV||Data Output Valid Bit "i" switching from<br>CLK Rising Edge ("i" = 0 to 6, 0 aligns with<br>CLK)|—|—|0.143|ns+i*UI|
|tTPBi_DOI||Data Output Invalid Bit "i" switching from<br>CLK Rising Edge ("i" = 0 to 6, 0 aligns with<br>CLK)|—|−0.143|—|ns+i*UI|
|tTPBi_skew_UI<br>~~ee~~||Tx skew in UI<br>~~rs~~|—<br>~~eee~~|—|0.15|UI|
|fMAX_TX71<br>~~ee~~||DDR71 ECLK Frequency3<br>~~rs~~|—<br>~~eee~~|—|525|MHz|
|**Generic DDRX141 Outputs with Clock and Data Aligned at Pin(GDDRX141_TX.ECLK)**<br>~~ee~~<br>~~rs eee~~<br>~~Cs~~|||||||
|tTPBi_DOV<br>~~ns~~|Data Output Valid Bit "i" switching from CLK<br>RisingEdge("i" = 0 to 6, 0 aligns with CLK)||All Devices|—<br>~~ee~~|0.125<br>~~ee~~|ns+i*UI|
|tTPBi_DOI<br>~~ee~~<br>~~ns~~|Data Output Invalid Bit "i" switching from<br>CLK Rising Edge ("i" = 0 to 6, 0 aligns with<br>CLK)<br>~~ee~~||All Devices<br>~~ee~~|−0.125<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~|ns+i*UI<br>~~ee~~|
|tTPBi_skew_UI<br>~~ns~~<br>~~a~~|TX skew in UI<br>~~es~~||All Devices<br>~~ees~~|—<br>~~ee~~<br>~~Ps~~|0.15<br>~~ee~~<br>~~es~~|UI|
|fMAX_TX141<br>~~ns~~<br>~~a~~|DDR141 ECLK Frequency3<br>~~es~~||—<br>~~ees~~|—<br>~~ee~~<br>~~Ps~~|600<br>~~ee~~<br>~~es~~|MHz|
## **Notes:**
General I/O timing numbers based on LVCMOS 2.5, 0 pF load.
Generic DDRX8, DDRX71 and DDRX141 timing numbers based on LVDS I/O.
Maximum clock frequencies are tested under best case conditions. System performance may vary upon the user environment
These numbers are generated using best case PLL located.
All numbers are generated with the Lattice Diamond design software.
Maximum data rate for GDDRX2 mode is 600 Mbps.
© 2015-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02013-1.2
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**CrossLink Automotive Family Data Sheet**
**==> picture [43 x 56] intentionally omitted <==**
**----- Start of picture text -----**<br>
Rx CLK (in)<br>Rx DATA (in)<br>**----- End of picture text -----**<br>
**==> picture [428 x 237] intentionally omitted <==**
**----- Start of picture text -----**<br>
tSU/tDVBDQ tSU/tDVBDQ<br>tHD/tDVADQ tHD/tDVADQ<br>Figure 4.1. Receiver RX.CLK.Centered Waveforms<br>1/2 UI 1/2 UI<br>Rx CLK (in) 1 UI<br>Rx DATA (in)<br>ho n tSU da<br>tSU<br>tHD<br>tHD<br>**----- End of picture text -----**<br>
**Figure 4.2. Receiver RX.CLK.Aligned Input Waveforms**
**==> picture [449 x 137] intentionally omitted <==**
**----- Start of picture text -----**<br>
1/2 UI 1/2 UI 1/2 UI 1/2 UI<br>Tx CLK (out)<br>So<br>Tx DATA (out)<br>tDVB tDVB<br>tDVA tDVA<br>**----- End of picture text -----**<br>
**Figure 4.3. Transmit TX.CLK.Centered Output Waveforms**
© 2015-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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**CrossLink Automotive Family Data Sheet**
**==> picture [298 x 120] intentionally omitted <==**
**----- Start of picture text -----**<br>
1<br>1 UI<br>Tx CLK (out)<br>2 \ 1 1 1<br>I !<br>1<br>! [I]<br>1<br>I [1]<br>I<br>A1<br>Tx DATA (out)<br>1 I vt I<br>1 1 i tot I<br>tDIB 1 tot tDIB ttt<br>a m i<br>1 tDIA tDIA<br>**----- End of picture text -----**<br>
## **Figure 4.4. Transmit TX.CLK.Aligned Waveforms**
## **Figure 4.5. DDRX71, DDRX141 Video Timing Waveforms**
© 2015-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02013-1.2
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**CrossLink Automotive Family Data Sheet**
## **4.14. sysCLOCK PLL Timing**
Over recommended operating conditions.
## **Table 4.14. sysCLOCK PLL Timing**
|**Parameter**<br>~~pf~~<br>~~es~~|**Descriptions**<br>~~pf~~<br>|**Conditions**<br>~~pf~~<br>|**Min**<br>~~pf~~<br>|**Max**<br>~~pf~~<br>|**Unit**<br>~~pf~~<br>|
|---|---|---|---|---|---|
|fIN<br>~~es~~|Input Clock Frequency (CLKI, CLKFB)<br>|—<br>|10<br>|400<br>|MHz<br>|
|fPD<br>~~esi~~|Phase Detector Input Clock Frequency<br>~~i~~|—<br>~~i~~|10<br>~~i~~|400<br>~~i~~|MHz<br>~~i~~|
|fOUT<br>~~pe~~<br>~~es~~|Output Clock Frequency (CLKOP, CLKOS)<br>~~pe~~<br>~~GCC~~|—<br>~~pe~~<br>~~GCC~~|4.6875<br>~~pe~~<br>~~GCC~~|600<br>~~pe~~<br>~~GCC~~|MHz<br>~~pe~~<br>~~GCC~~|
|fVCO<br>~~es~~|PLL VCO Frequency<br>~~GCC~~|—<br>~~GCC~~|600<br>~~GCC~~|1200<br>~~GCC~~|MHz<br>~~GCC~~|
|**AC Characteristics**<br>~~esGCC~~<br>~~En~~||||||
|tDT<br>~~ee~~|Output Clock DutyCycle<br>~~ee~~|—<br>~~ee~~|45.0<br>~~ee~~|55.5<br>~~ee~~|%<br>~~ee~~|
|tPH<br>~~ee~~<br>~~a~~|Output Phase Accuracy<br>~~ee~~<br>|—<br>~~ee~~<br>|−5<br>~~ee~~<br>|5<br>~~ee~~<br>|%<br>~~ee~~|
|tOPJIT1<br><br>~~—————_——EEEE~~|Output Clock Period Jitter3<br>~~pp~~<br>~~_—__————EeEe~~|fOUT≥ 100 MHz<br>~~pp~~|—<br>~~pp~~|100<br>~~pp~~|psp-p|
|||fOUT< 100 MHz<br>~~pp~~<br>~~ee~~<br>~~_—__————EeEe~~|—<br>~~pp~~<br>~~ee~~<br>~~_—__————EeEe~~|0.025<br>~~pp~~<br>~~ee~~<br>~~_—__————EeEe~~|UIPP<br>~~ee~~<br>~~_—__————EeEe~~|
||Output Clock Cycle-to-Cycle Jitter3<br>~~pp~~<br>~~_—__————EeEe~~<br>~~—————_——EEEE~~|fOUT≥ 100 MHz<br>~~pp~~<br>~~ee~~<br>~~_—__————EeEe~~|—<br>~~pp~~<br>~~ee~~<br>~~_—__————EeEe~~|200<br>~~pp~~<br>~~ee~~<br>~~_—__————EeEe~~|psp-p<br>~~ee~~<br>~~_—__————EeEe~~|
|||fOUT< 100 MHz<br>~~_—__————EeEe~~<br>~~es~~<br>~~—————_——EEEE~~|—<br>~~_—__————EeEe~~<br>~~es~~<br>~~—————_——EEEE~~|0.05<br>~~_—__————EeEe~~<br>~~es~~<br>~~—————_——EEEE~~|UIPP<br>~~_—__————EeEe~~<br>~~es~~<br>~~—————_——EEEE~~|
||Output Clock Phase Jitter<br>~~_—__————EeEe~~<br>~~—————_——EEEE~~|fPD> 100 MHz<br>~~_—__————EeEe~~<br>~~—————_——EEEE~~|—<br>~~_—__————EeEe~~<br>~~—————_——EEEE~~|200<br>~~_—__————EeEe~~<br>~~—————_——EEEE~~|psp-p<br>~~_—__————EeEe~~<br>~~—————_——EEEE~~|
|||fPD< 100 MHz<br>~~—————_——EEEE~~<br>~~es~~|—<br>~~—————_——EEEE~~<br>~~es~~|0.05<br>~~—————_——EEEE~~<br>~~es~~|UIPP<br>~~—————_——EEEE~~<br>~~es~~|
|tSPO<br>~~—————_——EEEE~~<br>~~a~~|Static Phase Offset<br>~~—————_——EEEE~~<br>~~a~~|Divider ratio = integer<br>~~—————_——EEEE~~<br>~~GO~~|—<br>~~—————_——EEEE~~<br>~~GO~~|400<br>~~—————_——EEEE~~<br>~~GO~~|psp-p<br>~~—————_——EEEE~~<br>~~GO~~|
|tLOCK2<br>~~a ~~<br>~~a~~<br>~~Rs~~|PLL Lock-in Time<br> ~~a~~<br>|—<br>~~GO~~<br>|—<br>~~GO~~<br>|15<br>~~GO~~<br>|ms<br>~~GO~~<br>|
|tUNLOCK<br>~~Rs~~|PLL Unlock Time<br>|—<br>|—<br>|50<br>|ns<br>|
|tIPJIT<br>~~Rsa~~<br>~~a~~|Input Clock Period Jitter<br>~~a~~|fPD≥ 20 MHz<br>~~a~~<br>~~es~~|—<br>~~a~~<br>~~ee~~|500<br>~~a~~<br>~~ee~~|psp-p<br>~~a~~|
|||fPD< 20 MHz<br>~~a~~<br>~~es~~|—<br>~~a~~<br>~~ee~~|0.02<br>~~a~~<br>~~ee~~|UIPP<br>~~a~~|
|tHI<br>~~a~~<br>~~a~~|Input Clock High Time<br>~~a~~|90% to 90%<br>~~a~~<br>~~es ~~|0.5<br>~~a~~<br> ~~ee~~|—<br>~~a~~<br>~~ee~~|ns<br>~~a~~|
|tLO<br>~~a~~|Input Clock Low Time<br>~~a~~|10% to 10%<br>~~GO~~|0.5<br>~~GO~~|—<br>~~GO~~|ns|
## **Notes:**
Jitter sample is taken over 10,000 samples for Periodic jitter, and 2,000 samples for Cycle-to-Cycle jitter of the primary PLL output with clean reference clock with no additional I/O toggling.
Output clock is valid after tLOCK for PLL reset and dynamic delay adjustment.
Period jitter and cycle-to-cycle jitter numbers are guaranteed for fPD ≥ 10 MHz. For fPD < 10 MHz, the jitter numbers may not be met in certain conditions.
© 2015-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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**CrossLink Automotive Family Data Sheet**
## **4.15. Hardened MIPI D-PHY Performance**
**Table 4.15. 1500 Mb/s MIPI_DPHY_X8_RX/TX Timing Table (1500 Mb/s > MIPI D-PHY Data Rate > 1200 Mb/s)**
|**Parameter**<br>**Description**<br>**Min**<br>**Max**<br>**Unit**<br>tSU_MIPIX8<br>Input Data Setup before CLK<br>0.200<br>—<br>UI<br>tHO_MIPIX8<br>Input Data Hold after CLK<br>0.200<br>—<br>UI<br>tDVB_MIPIX8<br>Output Data Valid before CLK Output<br>0.300<br>—<br>UI<br>tDVA_MIPIX8<br>Output Data Valid after CLK Output<br>0.300<br>—<br>UI<br>~~=~~|
|---|
|**Table 4.16. 1200 Mb/s MIPI_DPHY_X4_RX/TX Timing Table(1200 Mb/s > MIPI D-PHY Data Rate > 1000 Mb/s)**<br>**Parameter**<br>**Description**<br>**Min**<br>**Max**<br>**Unit**<br>tSU_MIPIX4<br>Input Data Setup before CLK<br>0.200<br>—<br>UI<br>tHO_MIPIX4<br>Input Data Hold after CLK<br>0.200<br>—<br>UI<br>tDVB_MIPIX4<br>Output Data Valid before CLK Output<br>0.300<br>—<br>UI<br>tDVA_MIPIX4<br>Output Data Valid after CLK Output<br>0.300<br>—<br>UI<br>~~=SSa5>~~|
|**Table 4.17. 1000 Mb/s MIPI_DPHY_X4_RX/TX Timing Table(1000 Mb/s > MIPI D-PHY Data Rate > 10 Mb/s)**<br>**Parameter**<br>**Description**<br>**Min**<br>**Max**<br>**Unit**<br>tSU_MIPIX4<br>Input Data Setup before CLK<br>0.150<br>—<br>UI<br>tHO_MIPIX4<br>Input Data Hold after CLK<br>0.150<br>—<br>UI<br>tDVB_MIPIX4<br>Output Data Valid before CLK Output<br>0.350<br>—<br>UI<br>tDVA_MIPIX4<br>Output Data Valid after CLK Output<br>0.350<br>—<br>UI<br>~~—_——~~|
|**4.16. Internal Oscillators (HFOSC, LFOSC)**|
|**Table 4.18. Internal Oscillators**<br>**Parameter**<br>**Parameter Description**<br>**Min**<br>**Typ**<br>**Max**<br>**Unit**<br>fCLKHF<br>HFOSC CLKK Clock Frequency<br>43.2<br>48<br>52.8<br>MHz<br>fCLKLF<br>LFOSC CLKK Clock Frequency<br>9<br>10<br>11<br>kHz<br>DCHCLKHF<br>HFOSC DutyCycle (Clock High Period)<br>45<br>50<br>55<br>%<br>DCHCLKLF<br>LFOSC Duty Cycle (Clock High Period)<br>45<br>50<br>55<br>%<br>**4.17. User I2C1**<br>~~———~~<br>~~=~~|
|**Table 4.19. User I2C1**<br>**Symbol**<br>**Parameter**<br>**STD Mode**<br>**FAST Mode**<br>**FAST Mode Plus2**<br>**Units**<br>**Min**<br>**Typ**<br>**Max**<br>**Min**<br>**Typ**<br>**Max**<br>**Min**<br>**Typ**<br>**Max**<br>fscl<br>SCL Clock Frequency<br>—<br>—<br>100<br>—<br>—<br>400<br>—<br>—<br>10002<br>kHz<br>TDELAY<br>Optional delay<br>through delayblock<br>—<br>62<br>—<br>—<br>62<br>—<br>—<br>62<br>—<br>ns<br>**Notes**:<br>Refer to the I2C Specification for timing requirements.<br>Fast Mode Plus maximum speed may be achieved by using external pull up resistor on I2C bus. Internal pull up may not be<br>~~Saeesaaaaseae~~|
|sufficient to support the maximum speed.|
© 2015-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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**CrossLink Automotive Family Data Sheet**
## **4.18. CrossLink Automotive sysCONFIG Port Timing Specifications**
Over recommended operating conditions.
**Table 4.20. CrossLink Automotive sysCONFIG Port Timing Specifications**
|**Symbol**<br>~~|~~|**Parameter**<br>~~|~~|**Min**<br>~~|~~|**Max**<br>~~|~~|**Unit**<br>~~|~~|
|---|---|---|---|---|
|**All Configuration Mode**<br>~~|~~<br>~~a~~|||||
|tPRGM|Minimum CRESETB LOW pulse width required to<br>restart configuration(from fallingedge to risingedge)|145|—|ns|
|**Slave SPI1**<br>~~a~~|||||
|fCCLK<br>~~a~~|SPI_SCK Input Clock Frequency<br>~~a~~<br>~~GD~~|—<br>~~a~~<br>~~GD~~|110<br>~~a~~<br>~~GD~~|MHz<br>~~a~~<br>~~GD~~|
|tSTSU<br>~~a~~|MOSI Setup Time<br>~~GG~~|0.5<br>~~GG~~|—<br>~~GG~~|ns<br>~~GG~~|
|tSTH<br>~~a ~~<br>~~a ~~|MOSI Hold Time<br> ~~GG~~<br> ~~GC~~|2.0<br>~~GG~~<br>~~GC~~|—<br>~~GG~~<br>~~GC~~|ns<br>~~GG~~<br>~~GC~~|
|tSTCO<br>~~GG~~|SPI_SCK Falling Edge to Valid MISO Output<br>~~GG~~|—<br>~~GG~~|13.3<br>~~GG~~|ns<br>~~GG~~|
|tSCS<br>~~GG~~<br>~~a~~|Chip Select HIGH Time<br>~~GG~~<br>~~GD~~|25<br>~~GG~~<br>~~GD~~|—<br>~~GG~~<br>~~GD~~|ns<br>~~GG~~<br>~~GD~~|
|tSCSS<br>~~a ~~<br>~~a ~~|Chip Select Setup Time<br> ~~GD~~<br> ~~GC~~|0.5<br>~~GD~~<br>~~GC~~<br>~~GG~~|—<br>~~GD~~<br>~~GC~~<br>~~GG~~|ns<br>~~GD~~<br>~~GC~~|
|tSCSH<br>~~Ge~~|Chip Select Hold Time<br>~~Ge~~|0.5<br>~~Ge~~<br>~~GG~~|—<br>~~Ge~~<br>~~GG~~|ns<br>~~Ge~~|
|**Master SPI**<br>~~Ge~~<br>~~GG~~<br>~~ee~~<br>~~DO~~|||||
|fCCLK<br>~~ee~~<br>~~eG~~|MCK Output Clock Frequency<br>~~ee~~<br>~~eG~~|—<br>~~ee~~<br>~~eG~~|52.8<br>~~ee~~<br>~~eG~~<br>~~DO~~|MHz<br>~~ee~~<br>~~eG~~|
|**I2C2**<br>~~eG~~<br>~~DO~~<br>~~Oe~~|||||
|fMAX<br>~~Oe~~<br>~~a~~|Maximum SCL Clock Frequency (Fast-Mode Plus)<br>~~Oe~~|—<br>~~Oe~~|1<br>~~Oe~~|MHz<br>~~Oe~~|
**Notes** :
1. Refer to CrossLink Programming and Configuration Usage Guide (FPGA-TN-02014), for timing requirements to enable CrossLink Automotive SSPI Mode.
2. Refer to the I[2] C specification for timing requirements when configuring with I[2] C port.
## **4.19. SRAM Configuration Time from NVCM**
Over recommended operating conditions.
## **Table 4.21. SRAM Configuration Time from NVCM**
|**Symbol**|**Parameter**|**Typ**|**Unit**|
|---|---|---|---|
|TCONFIGURATION|POR/CRESET_B to Device I/O Active*|83|ms|
***Note:** Before and during configuration, the I/Os are held in tristate with weak internal pullups enabled. I/Os are released to user functionality when the device has finished configuration.
© 2015-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
42
FPGA-DS-02013-1.2
**CrossLink Automotive Family Data Sheet**
## **4.20. Switching Test Conditions**
Figure 4.6 shows the output test load that is used for AC testing. The specific values for resistance, capacitance, voltage, and other test conditions are listed in Table 4.22.
**==> picture [195 x 127] intentionally omitted <==**
**----- Start of picture text -----**<br>
V T<br>R1<br>DUT Test Point<br>R2 CL*<br>:<br>**----- End of picture text -----**<br>
*CL Includes Test Fixture and Probe Capacitance
**Figure 4.6. Output Test Load, LVTTL and LVCMOS Standards**
**Table 4.22. Test Fixture Required Components, Non-Terminated Interfaces**
|**Test Condition**|**R1 **|**R2 **|**CL **|**Timing Ref.**|**VT **|
|---|---|---|---|---|---|
|LVTTL and other LVCMOS settings (L ≥ H, H ≥ L)|∞|∞|0 pF|LVCMOS 3.3 = 1.5 V|—|
|||||LVCMOS 2.5 = VCCIO/2|—|
|||||LVCMOS 1.8 = VCCIO/2|—|
|||||LVCMOS 1.2 = VCCIO/2|—|
|LVCMOS 2.5 I/O (Z ≥ H)|∞|1 MΩ|0 pF|VCCIO/2|—|
|LVCMOS 2.5 I/O (Z ≥ L)|1 MΩ|∞|0 pF|VCCIO/2|VCCIO|
|LVCMOS 2.5 I/O (H ≥ Z)|∞|100|0 pF|VOH–0.10|—|
|LVCMOS 2.5 I/O (L ≥ Z)|100|∞|0 pF|VOL+ 0.10|VCCIO|
**Note:** Output test conditions for all other interfaces are determined by the respective standards.
© 2015-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02013-1.2
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**CrossLink Automotive Family Data Sheet**
## **5. Pinout Information**
The pinout tables below correspond to CrossLink LIF-MD6000 Pinout Version 1.4. GND pins are referenced as VSS in Lattice Diamond Software.
## **5.1. ctfBGA80/cktBGA80 Pinout**
|**Pin Number**<br>~~a~~<br>~~ee~~|**Pin Function**<br>~~eG~~|**Bank**<br>~~eG~~|**Dual Function**<br>~~eG~~|**Differential**<br>~~eG~~|
|---|---|---|---|---|
|A1<br>~~ee~~<br>~~ee~~|DPHY1_DN2<br>~~eG~~|DPHY1<br>~~eG~~|—<br>~~eG~~|Comp_OF_DPHY1_DP2<br>~~eG~~|
|A2<br>~~ee~~<br>~~ee~~<br>~~ee~~|DPHY1_DN0<br>~~eG~~<br>~~eG~~|DPHY1<br>~~eG~~<br>~~eG~~|—<br>~~eG~~<br>~~eG~~|Comp_OF_DPHY1_DP0<br>~~eG~~<br>~~eG~~|
|A3<br>~~ee~~<br>~~ee~~<br>~~ee~~|DPHY1_CKN<br>~~eG~~<br>~~eG~~|DPHY1<br>~~eG~~<br>~~eG~~|—<br>~~eG~~<br>~~eG~~|Comp_OF_DPHY1_CKP<br>~~eG~~<br>~~eG~~|
|A4<br>~~ee~~<br>~~ee~~|DPHY1_DN1<br>~~eG~~<br>~~eG~~|DPHY1<br>~~eG~~<br>~~eG~~|—<br>~~eG~~<br>~~eG~~|Comp_OF_DPHY1_DP1<br>~~eG~~<br>~~eG~~|
|A5<br>~~ee~~<br>~~a ~~<br>~~a~~|DPHY1_DN3<br>~~eG~~<br> ~~eG~~<br>|DPHY1<br>~~eG~~<br>~~eG~~<br>|—<br>~~eG~~<br>~~eG~~<br>|Comp_OF_DPHY1_DP3<br>~~eG~~<br>~~eG~~<br>|
|A6<br>~~a~~|DPHY0_DN2<br>|DPHY0<br>|—<br>|Comp_OF_DPHY0_DP2<br>|
|A7<br>~~aeG~~|DPHY0_DN0<br>~~eG~~|DPHY0<br>~~eG~~|—<br>~~eG~~|Comp_OF_DPHY0_DP0<br>~~eG~~|
|A8<br>~~eG~~<br>~~eG~~<br>~~ee~~|DPHY0_CKN<br>~~eG~~<br>~~eG~~<br>~~eG~~|DPHY0<br>~~eG~~<br>~~eG~~<br>~~eG~~|—<br>~~eG~~<br>~~eG~~<br>~~eG~~|Comp_OF_DPHY0_CKP<br>~~eG~~<br>~~eG~~<br>~~eG~~|
|A9<br>~~eG~~<br>~~ee~~|DPHY0_DN1<br>~~eG~~<br>~~eG~~|DPHY0<br>~~eG~~<br>~~eG~~|—<br>~~eG~~<br>~~eG~~|Comp_OF_DPHY0_DP1<br>~~eG~~<br>~~eG~~|
|A10<br>~~ee~~<br>~~a ~~<br>~~a~~|DPHY0_DN3<br>~~eG~~<br> ~~eG~~<br>|DPHY0<br>~~eG~~<br>~~eG~~<br>|—<br>~~eG~~<br>~~eG~~<br>|Comp_OF_DPHY0_DP3<br>~~eG~~<br>~~eG~~<br>|
|B1<br>~~a~~|DPHY1_DP2<br>|DPHY1<br>|—<br>|True_OF_DPHY1_DN2<br>|
|B2<br>~~aeG~~|DPHY1_DP0<br>~~eG~~|DPHY1<br>~~eG~~|—<br>~~eG~~|True_OF_DPHY1_DN0<br>~~eG~~|
|B3<br>~~eG~~<br>~~eG~~<br>~~ee~~|DPHY1_CKP<br>~~eG~~<br>~~eG~~<br>~~a~~|DPHY1<br>~~eG~~<br>~~eG~~<br>~~Ge~~|—<br>~~eG~~<br>~~eG~~|True_OF_DPHY1_CKN<br>~~eG~~<br>~~eG~~|
|B4<br>~~eG~~<br>~~ee~~<br>~~ee~~|DPHY1_DP1<br>~~eG~~<br>~~a~~<br>~~eG~~|DPHY1<br>~~eG~~<br>~~Ge~~<br>~~eG~~|—<br>~~eG~~<br>~~eG~~|True_OF_DPHY1_DN1<br>~~eG~~<br>~~eG~~|
|B5<br>~~ee~~<br>~~ee~~|DPHY1_DP3<br>~~a~~<br>~~eG~~|DPHY1<br>~~Ge~~<br>~~eG~~|—<br>~~eG~~|True_OF_DPHY1_DN3<br>~~eG~~|
|B6<br>~~ee~~<br>~~Ge~~|DPHY0_DP2<br>~~eG~~<br>~~Ge~~|DPHY0<br>~~eG~~<br>~~Ge~~|—<br>~~eG~~<br>~~Ge~~|True_OF_DPHY0_DN2<br>~~eG~~<br>~~Ge~~|
|B7<br>~~Ge~~<br>~~a~~|DPHY0_DP0<br>~~Ge~~|DPHY0<br>~~Ge~~|—<br>~~Ge~~|True_OF_DPHY0_DN0<br>~~Ge~~|
|B8<br>~~a~~<br>~~a~~<br>~~ee~~|DPHY0_CKP<br>~~eG~~|DPHY0<br>~~eG~~|—<br>~~eG~~|True_OF_DPHY0_CKN<br>~~eG~~|
|B9<br>~~a~~<br>~~ee~~<br>~~ee~~|DPHY0_DP1<br>~~eG~~<br>~~eG~~|DPHY0<br>~~eG~~<br>~~eG~~|—<br>~~eG~~<br>~~eG~~|True_OF_DPHY0_DN1<br>~~eG~~<br>~~eG~~|
|B10<br>~~ee~~<br>~~ee~~<br>~~ee~~|DPHY0_DP3<br>~~eG~~<br>~~eG~~<br>~~eG~~|DPHY0<br>~~eG~~<br>~~eG~~<br>~~eG~~|—<br>~~eG~~<br>~~eG~~<br>~~eG~~|True_OF_DPHY0_DN3<br>~~eG~~<br>~~eG~~<br>~~eG~~|
|C1<br>~~ee~~<br>~~ee~~|GND<br>~~eG~~<br>~~eG~~|GND<br>~~eG~~<br>~~eG~~|—<br>~~eG~~<br>~~eG~~|—<br>~~eG~~<br>~~eG~~|
|C2<br>~~ee~~<br>~~Ge~~|GNDA_DPHY1<br>~~eG~~<br>~~Ge~~|DPHY1<br>~~eG~~<br>~~Ge~~|—<br>~~eG~~<br>~~Ge~~|—<br>~~eG~~<br>~~Ge~~|
|C9<br>~~Ge~~<br>~~a~~<br>~~ee~~|GNDA_DPHY0<br>~~Ge~~<br>~~eG~~|DPHY0<br>~~Ge~~<br>~~eG~~|—<br>~~Ge~~<br>~~eG~~|—<br>~~Ge~~<br>~~eG~~|
|C10<br>~~a~~<br>~~ee~~<br>~~ee~~|GND<br>~~eG~~<br>~~eG~~|GND<br>~~eG~~<br>~~eG~~|—<br>~~eG~~<br>~~eG~~|—<br>~~eG~~<br>~~eG~~|
|D1<br>~~ee~~<br>~~ee~~<br>~~ee~~|PB48<br>~~eG~~<br>~~eG~~|0<br>~~eG~~<br>~~eG~~|PCLKT0_1/USER_SCL<br>~~eG~~<br>~~eG~~|—<br>~~eG~~<br>~~eG~~|
|D2<br>~~ee~~<br>~~ee~~|VCCPLL_DPHY1<br>~~eG~~|DPHY1<br>~~eG~~|—<br>~~eG~~|—<br>~~eG~~|
|D4<br>~~ee~~<br>~~Ge~~|VCCA_DPHY1<br>~~Ge~~|DPHY1<br>~~Ge~~|—<br>~~Ge~~|—<br>~~Ge~~|
|D5<br>~~Ge~~<br>~~eG~~|VCCAUX<br>~~Ge~~<br>~~eG~~|VCCAUX<br>~~Ge~~<br>~~eG~~|—<br>~~Ge~~<br>~~eG~~|—<br>~~Ge~~<br>~~eG~~|
|D6<br>~~eG~~<br>~~eG~~<br>~~ee~~|GNDPLL_DPHYx<br>~~eG~~<br>~~eG~~|GND<br>~~eG~~<br>~~eG~~|—<br>~~eG~~<br>~~eG~~|—<br>~~eG~~<br>~~eG~~|
|D7<br>~~ee~~<br>~~ee~~|VCCPLL_DPHY0|DPHY0|—|—|
|D9<br>~~ee~~<br>~~ee~~|PB16A|2|PCLKT2_0|True_OF_PB16B|
|D10<br>~~ee~~<br>~~Ge~~|PB16B<br>~~Ge~~|2<br>~~Ge~~|PCLKC2_0<br>~~Ge~~|Comp_OF_PB16A<br>~~Ge~~|
|E1<br>~~Ge~~<br>~~eG~~|PB34A<br>~~Ge~~<br>~~eG~~|1<br>~~Ge~~<br>~~eG~~|GR_PCLK1_0<br>~~Ge~~<br>~~eG~~|True_OF_PB34B<br>~~Ge~~<br>~~eG~~|
|E2<br>~~eG~~<br>~~eG~~|PB34B<br>~~eG~~<br>~~eG~~|1<br>~~eG~~<br>~~eG~~|—<br>~~eG~~<br>~~eG~~|Comp_OF_PB34A<br>~~eG~~<br>~~eG~~|
|E4<br>~~eG~~<br>~~eG~~|VCC<br>~~eG~~<br>~~eG~~|VCC<br>~~eG~~<br>~~eG~~|—<br>~~eG~~<br>~~eG~~|—<br>~~eG~~<br>~~eG~~|
|E5<br>~~eG~~<br>~~ee~~|GND<br>~~eG~~<br>~~eG~~|GND<br>~~eG~~<br>~~eG~~|—<br>~~eG~~<br>~~eG~~|—<br>~~eG~~<br>~~eG~~|
|E6<br>~~ee~~<br>~~ee~~|VCC<br>~~eG~~<br>~~eG~~|VCC<br>~~eG~~<br>~~eG~~|—<br>~~eG~~<br>~~eG~~|—<br>~~eG~~<br>~~eG~~|
|E7<br>~~ee~~<br>~~ee~~<br>~~ee~~|VCCA_DPHY0<br>~~eG~~<br>~~eG~~<br>~~eG~~|DPHY0<br>~~eG~~<br>~~eG~~<br>~~eG~~|—<br>~~eG~~<br>~~eG~~<br>~~eG~~|—<br>~~eG~~<br>~~eG~~<br>~~eG~~|
|E9<br>~~ee~~<br>~~ee~~<br>~~ee~~|PB12A<br>~~eG~~<br>~~eG~~<br>~~eG~~|2<br>~~eG~~<br>~~eG~~<br>~~eG~~|GPLLT2_0<br>~~eG~~<br>~~eG~~<br>~~eG~~|True_OF_PB12B<br>~~eG~~<br>~~eG~~<br>~~eG~~|
|E10<br>~~ee~~<br>~~ee~~|PB12B<br>~~eG~~<br>~~eG~~|2<br>~~eG~~<br>~~eG~~|GPLLC2_0<br>~~eG~~<br>~~eG~~|Comp_OF_PB12A<br>~~eG~~<br>~~eG~~|
|F1<br>~~ee~~<br>~~eG~~|PB38A<br>~~eG~~<br>~~eG~~|1<br>~~eG~~<br>~~eG~~|—<br>~~eG~~<br>~~eG~~|True_OF_PB38B<br>~~eG~~<br>~~eG~~|
|F2<br>~~eG~~|PB38B<br>~~eG~~|1<br>~~eG~~|—<br>~~eG~~|Comp_OF_PB38A<br>~~eG~~|
© 2015-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02013-1.2
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**CrossLink Automotive Family Data Sheet**
|**Pin Number**<br>~~a~~|**Pin Function**<br>|**Bank**<br>|**Dual Function**<br>|**Differential**<br>|
|---|---|---|---|---|
|F4<br>~~eG~~<br>~~ee~~|VCCIO0<br>~~eG~~|0<br>~~eG~~|—<br>~~eG~~|—<br>~~eG~~|
|F5<br>~~ee~~<br>~~ee~~|VCCIO1<br>~~eG~~|1<br>~~eG~~|—<br>~~eG~~|—<br>~~eG~~|
|F6<br>~~ee~~<br>~~ee~~|VCCIO2<br>~~eG~~|2<br>~~eG~~|—<br>~~eG~~|—<br>~~eG~~|
|F7<br>~~ee~~<br>~~a~~|VCCIO2<br>~~eG~~<br>~~Ge~~|2<br>~~eG~~<br>~~Ge~~|—<br>~~eG~~|—<br>~~eG~~|
|F9<br>~~a~~<br>~~ee~~|PB6A<br>~~Ge~~|2<br>~~Ge~~|GR_PCLK2_0|True_OF_PB6B|
|F10<br>~~ee~~<br>~~ee~~|PB6B|2|—|Comp_OF_PB6A|
|G1<br>~~ee~~<br>~~ee~~<br>~~ee~~|PB50|0|MOSI|—|
|G2<br>~~ee~~<br>~~ee~~<br>~~ee~~|GND<br>~~eG~~|GND<br>~~eG~~|—<br>~~eG~~|—<br>~~eG~~|
|G4<br>~~ee~~<br>~~ee~~<br>~~ee~~|VCCIO1<br>~~eG~~<br>~~eG~~|1<br>~~eG~~<br>~~eG~~|—<br>~~eG~~<br>~~eG~~|—<br>~~eG~~<br>~~eG~~|
|G5<br>~~ee~~<br>~~ee~~|GND<br>~~eG~~<br>~~eG~~|GND<br>~~eG~~<br>~~eG~~|—<br>~~eG~~<br>~~eG~~|—<br>~~eG~~<br>~~eG~~|
|G6<br>~~ee~~<br>~~a~~|VCCGPLL<br>~~eG~~<br>|VCCGPLL<br>~~eG~~<br>|—<br>~~eG~~<br>|—<br>~~eG~~<br>|
|G7<br>~~aeG~~|GNDGPLL<br>~~eG~~|GND<br>~~eG~~|—<br>~~eG~~|—<br>~~eG~~|
|G9<br>~~eG~~<br>~~eG~~<br>~~ee~~|PB2A<br>~~eG~~<br>~~eG~~<br>~~eG~~|2<br>~~eG~~<br>~~eG~~<br>~~eG~~|—<br>~~eG~~<br>~~eG~~<br>~~eG~~|True_OF_PB2B<br>~~eG~~<br>~~eG~~<br>~~eG~~|
|G10<br>~~eG~~<br>~~ee~~<br>~~ee~~|PB2B<br>~~eG~~<br>~~eG~~<br>~~eG~~|2<br>~~eG~~<br>~~eG~~<br>~~eG~~|—<br>~~eG~~<br>~~eG~~<br>~~eG~~|Comp_OF_PB2A<br>~~eG~~<br>~~eG~~<br>~~eG~~|
|H1<br>~~ee~~<br>~~ee~~|PB52<br>~~eG~~<br>~~eG~~|0<br>~~eG~~<br>~~eG~~|SPI_SS/CSN/SCL<br>~~eG~~<br>~~eG~~|—<br>~~eG~~<br>~~eG~~|
|H2<br>~~ee~~<br>~~a~~|CRESET_B<br>~~eG~~<br>|0<br>~~eG~~<br>|—<br>~~eG~~<br>|—<br>~~eG~~<br>|
|H9<br>~~aeG~~|PB2D<br>~~eG~~|2<br>~~eG~~|MIPI_CLKC2_0<br>~~eG~~|Comp_OF_PB2C<br>~~eG~~|
|H10<br>~~eG~~<br>~~eG~~<br>~~ee~~|PB2C<br>~~eG~~<br>~~eG~~<br>~~eG~~|2<br>~~eG~~<br>~~eG~~<br>~~eG~~|MIPI_CLKT2_0<br>~~eG~~<br>~~eG~~<br>~~eG~~|True_OF_PB2D<br>~~eG~~<br>~~eG~~<br>~~eG~~|
|J1<br>~~eG~~<br>~~ee~~|PB53<br>~~eG~~<br>~~eG~~|0<br>~~eG~~<br>~~eG~~|SPI_SCK/MCK/SDA<br>~~eG~~<br>~~eG~~|—<br>~~eG~~<br>~~eG~~|
|J2<br>~~ee~~<br>~~a ~~<br>~~ee~~|PB49<br>~~eG~~<br> ~~eG~~<br>~~eG~~|0<br>~~eG~~<br>~~eG~~<br>~~eG~~|PMU_WKUPN/CDONE<br>~~eG~~<br>~~eG~~<br>~~eG~~|—<br>~~eG~~<br>~~eG~~<br>~~eG~~|
|J3<br>~~ee~~|PB43D<br>~~eG~~|1<br>~~eG~~|—<br>~~eG~~|Comp_OF_PB43C<br>~~eG~~|
|J4<br>~~ee~~<br>~~a~~<br>~~ee~~|PB38D<br>~~eG~~<br>~~eG~~|1<br>~~eG~~<br>~~eG~~|—<br>~~eG~~<br>~~eG~~|Comp_OF_PB38C<br>~~eG~~<br>~~eG~~|
|J5<br>~~a~~<br>~~ee~~<br>~~**e**e~~|PB34D<br>~~eG~~<br>~~eG~~|1<br>~~eG~~<br>~~eG~~|MIPI_CLKC1_0<br>~~eG~~<br>~~eG~~|Comp_OF_PB34C<br>~~eG~~<br>~~eG~~|
|J6<br>~~ee~~<br>~~**e**e~~|PB29D<br>~~eG~~<br>~~eG~~|1<br>~~eG~~<br>~~eG~~|PCLKC1_1<br>~~eG~~<br>~~eG~~|Comp_OF_PB29C<br>~~eG~~<br>~~eG~~|
|J7<br>~~**e**e~~|PB29A<br>~~eG~~|1<br>~~eG~~|PCLKT1_0<br>~~eG~~<br>~~G~~|True_OF_PB29B<br>~~eG~~<br>~~G~~|
|J8<br>~~eG~~|PB16D<br>~~eG~~|2<br>~~eG~~|PCLKC2_1<br>~~eG~~|Comp_OF_PB16C<br>~~eG~~|
|J9<br>~~a~~<br>~~ee~~|PB6D<br>~~eG~~|2<br>~~eG~~|—<br>~~eG~~|Comp_OF_PB6C<br>~~eG~~|
|J10<br>~~a~~<br>~~ee~~<br>~~**e**e~~|PB6C<br>~~eG~~<br>~~eG~~|2<br>~~eG~~<br>~~eG~~|—<br>~~eG~~<br>~~eG~~|True_OF_PB6D<br>~~eG~~<br>~~eG~~|
|K1<br>~~ee~~<br>~~**e**e~~|PB51<br>~~eG~~<br>~~eG~~|0<br>~~eG~~<br>~~eG~~|MISO<br>~~eG~~<br>~~eG~~|—<br>~~eG~~<br>~~eG~~|
|K2<br>~~**e**e~~|PB47<br>~~eG~~|0<br>~~eG~~|PCLKT0_0/USER_SDA<br>~~eG~~<br>~~G~~|—<br>~~eG~~<br>~~G~~|
|K3<br>~~eG~~|PB43C<br>~~eG~~|1<br>~~eG~~|—<br>~~eG~~|True_OF_PB43D<br>~~eG~~|
|K4<br>~~a~~|PB38C<br>~~a~~<br>~~e~~|1<br>~~e~~|—|True_OF_PB38D|
|K5<br>~~a~~<br>~~a~~<br>~~ee~~|PB34C<br>~~a~~<br>~~e~~<br>~~aeG~~<br>|1<br>~~e~~<br>~~eG~~<br>|MIPI_CLKT1_0<br>~~eG~~<br>|True_OF_PB34D<br>~~eG~~<br>|
|K6<br>~~a~~<br>~~ee~~<br>~~ee~~|PB29C<br>~~aeG~~<br>~~eG~~<br>|1<br>~~eG~~<br>~~eG~~<br>|PCLKT1_1<br>~~eG~~<br>~~eG~~<br>|True_OF_PB29D<br>~~eG~~<br>~~eG~~<br>|
|K7<br><br>~~ee~~<br>~~ee~~<br>~~ee~~|PB29B<br>~~eG~~<br>~~eG~~<br>~~**eG**~~|1<br>~~eG~~<br>~~eG~~<br>~~**eG**~~|PCLKC1_0<br>~~eG~~<br>~~eG~~<br>~~**eG**~~|Comp_OF_PB29A<br>~~eG~~<br>~~eG~~<br>~~**eG**~~|
|K8<br><br>~~ee~~<br>~~ee~~|PB16C<br>~~eG~~<br>~~**eG**~~|2<br>~~eG~~<br>~~**eG**~~|PCLKT2_1<br>~~eG~~<br>~~**eG**~~|True_OF_PB16D<br>~~eG~~<br>~~**eG**~~|
|K9<br><br>~~ee~~<br>~~a~~<br>~~ee~~|PB12D<br>~~**eG**~~<br>~~e~~<br>~~D~~|2<br>~~**eG**~~<br>~~D~~|—<br>~~**eG**~~|Comp_OF_PB12C<br>~~**eG**~~|
|K10<br>~~a~~<br>~~ee~~|PB12C<br>~~e~~<br>~~D~~|2<br>~~D~~|—|True_OF_PB12D|
© 2015-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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**CrossLink Automotive Family Data Sheet**
## **5.2. Dual Function Pin Descriptions**
The following table describes the dual functions available to certain pins on the CrossLink Automotive device. These pins may alternatively be used as general purpose I/O when the described dual function is not enabled.
|**Signal Name**<br>~~a~~|**I/O**<br>~~a~~|**Description**<br>~~ae~~|
|---|---|---|
|**General Purpose**<br>~~a~~<br>~~aae~~<br>~~PT~~|||
|USER_SCL<br>~~ee~~|I/O<br>~~ee~~<br>~~ee~~|User Slave I2C0 clock input and Master I2C0 clock output. Enables PMU<br>wake-up via I2C0.<br>~~ee~~|
|USER_SDA<br>~~ee~~|I/O<br>~~ee~~<br>~~ee~~|User Slave I2C0 data input and Master I2C0 data output. Enables PMU<br>wakeup via I2C0.<br>~~ee~~|
|PMU_WKUPN<br>~~eG~~|—<br>~~ee~~<br>~~eG~~|This pin wakes the PMU from sleep mode when toggled low.<br>~~eG~~|
|**Clock Functions**<br>~~PT~~|||
|GPLL2_0[T, C]_IN|I|General Purpose PLL (GPLL) input pads: T = true and C = complement. These<br>pins can be used to input a reference clock directly to the General Purpose<br>PLL. Thesepins do notprovide direct access to theprimaryclock network.|
|GR_PCLK[Bank]0|I|These pins provide a short General Routing path to the primary clock<br>network. Refer toCrossLink sysCLOCK PLL/DLL Design and Usage Guide<br>(FPGA-TN-02015) for details.|
|PCLK[T/C][Bank]_[num]|I/O|General Purpose Primary CLK pads: [T/C] = True/Complement, [Bank] = (0, 1<br>and 2). These pins provide direct access to the primary and edge clock<br>networks.|
|MIPI_CLK[T/C][Bank]_0|I/O|MIPI D-PHY Reference CLK pads: [T/C] = True/Complement, [Bank] = (0, 1<br>and 2). These pins can be used to input a reference clock directly to the<br>D-PHY PLLs. These pins do not provide direct access to the primary clock<br>network.|
|**Configuration**<br>~~PT~~|||
|CDONE<br>~~ee~~|I/O<br>~~ee~~|Open Drain pin. Indicates that the configuration sequence is complete, and<br>the startupsequence is inprogress. HoldingCDONE delays configuration.<br>~~ee~~|
|SPI_SCK<br>~~a~~|I|Input Configuration Clock for configuring CrossLink Automotive in Slave SPI<br>mode(SSPI).|
|MCK<br>~~a~~|O|Output Configuration Clock for configuring CrossLink Automotive in Master<br>SPI mode(MSPI).|
|SPI_SS<br>~~a~~<br>~~>,~~|I<br>~~>,~~|Input Chip Select for configuring CrossLink Automotive in Slave SPI mode<br>(SSPI).<br>~~>,~~|
|CSN<br>~~a~~<br>~~>,~~|O<br>~~>,~~|Output Chip Select for configuring CrossLink Automotive in Master SPI mode<br>(MSPI).<br>~~>,~~|
|MOSI<br>~~>,~~<br>~~po~~|I/O<br>~~>,~~<br>~~po~~|Data Output when configuring CrossLink Automotive in Master SPI mode<br>(MSPI), data input when configuring CrossLink Automotive in Slave SPI mode<br>(SSPI).<br>~~>,~~<br>~~po~~|
|MISO<br>~~>,~~<br>~~po~~|I/O<br>~~>,~~<br>~~po~~|Data Input when configuring CrossLink Automotive in Master SPI mode<br>(MSPI), data output when configuring CrossLink Automotive in Slave SPI<br>mode(SSPI).<br>~~>,~~<br>~~po~~|
|SCL<br>~~po~~|I/O<br>~~po~~|Slave I2C clock I/O when configuringCrossLink Automotive in I2C mode.<br>~~po~~|
|SDA<br>~~po~~<br>~~a~~|I/O<br>~~po~~|Slave I2C data I/O when configuringCrossLink Automotive in I2C mode.<br>~~po~~|
© 2015-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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**CrossLink Automotive Family Data Sheet**
## **5.3. Dedicated Function Pin Descriptions**
|**Signal Name**|**I/O**|**Description**|
|---|---|---|
|**Configuration**|||
|CRESET_B|I|Configuration Reset,active LOW.|
|**MIPI D-PHY**|||
|DPHY[num]_CK[P/N]|I/O|MIPI D-PHY Clock [num] = D-PHY 0 or 1, P = Positive, N = Negative.|
|DPHY[num]_D[P/N][lane]|I/O|MIPI D-PHY Data [num] = D-PHY 0 or 1, P = Positive, N = Negative,<br>Lane = data lane in the D-PHY block 0, 1, 2 or 3.|
## **5.4. Pin Information Summary**
|**Pin Type**<br>~~———————~~|**CrossLink Automotive**<br>~~ee~~|**CrossLink Automotive**<br>~~ee~~|
|---|---|---|
||**ctfBGA80**<br>~~ee~~<br>~~eee~~|**ckfBGA80**<br>~~ee~~<br>~~eee~~|
|**Total General Purpose I/O**<br>~~———————~~<br>~~GC~~|37<br>~~ee~~<br>~~eee~~<br>~~GC~~|37<br>~~ee~~<br>~~eee~~<br>~~GC~~|
|**VCC/VCCIOx/VCCAUX/VCCGPLL**<br>~~GC~~<br>~~ee~~|9<br>~~GC~~<br>~~ee~~|9<br>~~GC~~<br>~~ee~~|
|**GND**<br>~~ee~~<br>~~a~~|6<br>~~ee~~|6<br>~~ee~~|
|**D-PHY Clock/Data**<br>~~GG~~|20<br>~~GG~~|20<br>~~GG~~|
|**D-PHY VCC**<br>~~GG~~<br>~~ee~~|4<br>~~GG~~<br>~~ee~~|4<br>~~GG~~<br>~~ee~~|
|**D-PHY GND**<br>~~ee~~<br>~~a~~|3<br>~~ee~~|3<br>~~ee~~|
|**CRESETB**<br>~~GG~~|1<br>~~GG~~|1<br>~~GG~~|
|**Total Balls**<br>~~GG~~<br>~~fe~~|**80**<br>~~GG~~<br>~~fe~~|**80**<br>~~GG~~<br>~~fe~~|
|**General Purpose I/Oper Bank**<br>~~Pe~~|||
|Bank 0<br>~~Pe~~<br>~~a~~|7<br>~~Pe~~|7<br>~~Pe~~|
|Bank 1<br>~~ee~~|14<br>~~ee~~|14<br>~~ee~~|
|Bank 2<br>~~GO~~|16<br>~~GO~~|16<br>~~GO~~|
|**Total General Purpose Single Ended I/O**<br>~~GO~~<br>~~Ne~~|**37**<br>~~GO~~<br>~~Ne~~|**37**<br>~~GO~~<br>~~Ne~~|
|**Differential I/Opairsper Bank**<br>~~Pe~~|||
|Bank 0<br>~~Pe~~<br>~~a~~|0<br>~~Pe~~|0<br>~~Pe~~|
|Bank 1<br>~~a~~<br>~~a~~<br>~~Ge~~|7<br>~~Ge~~|7<br>~~GO~~|
|Bank 2<br>~~Ge~~|8<br>~~Ge~~|8<br>~~GO~~|
|**Total General Purpose Differential I/O pairs**<br>~~Ge~~<br>~~He~~|**15**<br>~~Ge~~<br>~~He~~|**15**<br>~~GO~~<br>~~He~~|
© 2015-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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**CrossLink Automotive Family Data Sheet**
## **6. CrossLink Automotive Part Number Description**
## LIA-MD XXXX-X XXXXX X
**==> picture [432 x 105] intentionally omitted <==**
**----- Start of picture text -----**<br>
Device Family Grade<br> CrossLink Automotive FPGA E = Automotive<br>Package<br>Logic Capacity JMG80 = 80-ball ctfBGA<br> 6000 = 6000 LUTs KMG80 = 80-ball ckfBGA<br>Speed<br>6 = Fastest<br>**----- End of picture text -----**<br>
## **6.1. Ordering Part Numbers**
|**Part Number**<br>~~———————~~|**Speed**<br>~~———————~~|**Package **<br>~~———————~~|**Pins**<br>~~———————~~|**Temp. Grade**<br>~~———————~~|**LUTs(K)**<br>~~———————~~|
|---|---|---|---|---|---|
|LIA-MD6000-6JMG80E<br>~~———————~~|–6<br>~~———————~~|Lead free ctfBGA<br>~~———————~~|80<br>~~———————~~|Automotive<br>~~———————~~|5.9<br>~~———————~~|
|LIA-MD6000-6KMG80E<br>~~———————~~|–6<br>~~———————~~|Lead free ckfBGA<br>~~———————~~|80<br>~~———————~~|Automotive<br>~~———————~~|5.9<br>~~———————~~|
© 2015-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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FPGA-DS-02013-1.2
**CrossLink Automotive Family Data Sheet**
## **References**
For more information, refer to the following technical notes:
- CrossLink High-Speed I/O Interface (FPGA-TN-02012)
- CrossLink Hardware Checklist (FPGA-TN-02013)
- CrossLink Programming and Configuration Usage Guide (FPGA-TN-02014)
- CrossLink sysCLOCK PLL/DLL Design and Usage Guide (FPGA-TN-02015)
- CrossLink sysI/O Usage Guide (FPGA-TN-02016)
- CrossLink Memory Usage Guide (FPGA-TN-02017)
- Power Management and Calculation for CrossLink Devices (FPGA-TN-02018)
- CrossLink I2C Hardened IP Usage Guide (FPGA-TN-02019)
- Advanced CrossLink I2C Hardened IP Reference Guide (FPGA-TN-02020)
For package information, refer to the following technical notes:
- PCB Layout Recommendations for BGA Packages (TN1074)
- Solder Reflow Guide for Surface Mount Devices (FPGA-TN-12041, previously TN1076)
- Wafer-Level Chip-Scale Package Guide (TN1242)
- Thermal Management
- Package Diagrams
For further information on interface standards refer to the following websites:
- JEDEC Standards (LVTTL, LVCMOS): www.jedec.org
- MIPI Standards (D-PHY): www.mipi.org
## **Technical Support**
For assistance, submit a technical support case at www.latticesemi.com/techsupport.
© 2015-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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**CrossLink Automotive Family Data Sheet**
## **Revision History**
|**Date**|**Version**|**Change Summary**|
|---|---|---|
|March 2018|1.2|<br>Added entries to theAcronyms in This Documentsection.<br><br>InFeaturessection:<br><br>Changed footprint to 80-ball ctfBGA (42 mm2)<br><br>Updated Applications examples<br><br>Removed Application Examples section and its associated references throughout the<br>document<br><br>Updated packages inTable 2.1.<br><br>Updated theArchitecture Overviewsection (general update)<br><br>Revised introductory paragraph.<br><br>Reordered the list of features supported by the hard D-PHY quads<br><br>AddedFigure 3.3toFigure 3.6to theMIPI D-PHY Blockssection<br><br>Updated theProgrammable I/O Bankssection<br><br>Added Bank 0 list of features<br><br>AddedTable 3.1,Table 3.2,Table 3.3andTable 3.4<br><br>UpdatedProgrammable FPGA Fabricsection<br><br>Removed FPGA Fabric Overview header<br><br>AddedPFU Blockssection<br><br>AddedSlicesection<br><br>Moved Clocking Overview as a newClocking Structure(heading 2) section and<br>added contents<br><br>MovedEmbedded Block RAM Overviewas a new (heading 2) section and added<br>contents<br><br>Removed System Resources section<br><br>MovedPower Management Unitsection underEmbedded Block RAM Overview<br><br>Removed Device Configuration section<br><br>MovedUser I2C IPas a new (heading 2) section<br><br>AddedProgramming and Configurationsection<br><br>Revised footnotes inTable 4.6<br><br>Corrected alignment of arrows inFigure 4.4<br><br>Revised Min and Max values inTable 4.15,Table 4.16, andTable 4.17<br><br>Revised footnote inTable 4.20<br><br>Added web link inPinout Informationsection<br><br>Placed captions to pinout table|
|December 2017|1.1|<br>Changed document status from preliminary to final<br><br>Added items to Acronyms in This Document<br><br>Updated the Features section<br><br>Added 80-ball ckfBGA (49 mm2) under Small footprint<br><br>Removed LVDS under Programmable CMOS I/O<br><br>Updated note in Table 2.1, Table 2.2, Table 2.3, Table 2.4, Table 2.5, Table 2.6, Table 2.7,<br>Table 2.8, and Table 2.9<br><br>Moved Product Feature Summary from section to 2 to section 3. Added 80 ckfBGA (7.0 x<br>7.0 mm2, 1 mm) in Table 3.1. CrossLink Automotive Feature Summary<br><br>Updated System Resources section<br><br>Removed LVCMOS12 (Outputs Only) from CMOS GPIO (Bank 0) section<br><br>Added information in Device Configuration section<br><br>Updated Table 5.1. Absolute Maximum Ratings1, 2, 3<br><br>Changed symbol from VCCPLL to VCCGPLL|
© 2015-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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**CrossLink Automotive Family Data Sheet**
|**Date**|**Version**|**Change Summary**|
|---|---|---|
|||<br>Removed VCC_DPHY, VCCA_DPHY, and VCCMU_DPHY symbol; added VCCA_DPHYx<br><br>Updated Table 5.2. Recommended Operating Conditions1, 2<br><br>Revised symbols to VCCGPLL, VCCAUX, and VCCIO0<br><br>Added parameter to VCCAUX<br><br>Added row of VCCIO1/2 symbol<br><br>Removed row of VCC_DPHYx and VCCMU_DPHY1 symbol<br><br>Revised note<br><br>Updated Power-On-Reset Voltage Levels section. Added VPORDN to Table 5.4. Power-On-<br>Reset Voltage Levels1, 3, 4 and revised footnotes<br><br>Updated LIFMD Product Family Qualification Summary link in ESD Performance section<br><br>Removed VCCIO = 1.2 V between 0≤VIN≤0.65 * VCCIO condition from Table 5.5. DC<br>Electrical Characteristics<br><br>Updated Table 5.6. CrossLink Automotive Supply Current (general update)<br><br>Removed Preliminary MIPI D-PHY Supply Current section.<br><br>Added notes to Table 5.8. sysI/O Recommended Operating Conditions1<br><br>Added note to Table 5.9. sysI/O Single-Ended DC Electrical Characteristics<br><br>Added notes to Table 5.10. LVDS/subLVDS1/SLVS2001, 2<br><br>Updated Table 5.12. CrossLink Automotive Maximum I/O Buffer Speed (general update)<br><br>Updated Table 5.13. CrossLink Automotive External Switching Characteristics4, 5 (general<br>update)<br><br>Updated Figure 5.4. Transmit TX.CLK.Aligned Waveforms<br><br>Updated Table 5.20. CrossLink Automotive sysCONFIG Port Timing Specifications (general<br>update)<br><br>Changed TREFRESHto TCONFIGURATIONin Table 5.21. SRAM Configuration Time from NVCM<br><br>Updated Pinout Information section<br><br>Updated section introduction<br><br>Updated section to ctfBGA80/cktBGA80 Pinout<br><br>Updated Pin Information Summary section (general update)<br><br>Added KMG80 package to CrossLink Automotive Part Number Description section<br><br>Modified heading and added LIA-MD6000-6KMG80E part number to Ordering Part<br>Numbers section<br><br>Updated reference to the Solder Reflow Guide for Surface Mount Devices document in<br>References section|
|September 2016|1.0|First preliminary release.|
© 2015-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02013-1.2
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