LFMXO5-100T-7BBG400I

FPGA, SRAM, 291 I/O's, 100 Logic Cells, 28nm, Surface Mount, CABGA-400, MachXO5-NX Series

⚠️ Reference pricing provided. In case of supply shortages, we will connect you with our trusted procurement partners to ensure your project's continuity.
Manufacturer: LATTICE SEMICONDUCTOR
Product type: FPGAs
SVHC: No SVHC (25-Jun-2025)
FPGA Type: SRAM based FPGA
IC Mounting: Surface Mount
No. of Pins: 400Pins
Speed Grade: 7
Product Range: MachXO5-NX Series
Qualification: -
No.of User I/Os: 291I/O's
IC Case / Package: CABGA
No. of Logic Cells: 100Logic Cells
Process Technology: 28nm
Operating Temperature Max: 100°C
Operating Temperature Min: -40°C
Delivery and price
Units per pack	10
Price	149.37 €
Current stock	100+
Lead time	30 days
Datasheet
## Os 

## **MachXO5-NX Family** 

## **Data Sheet** 

FPGA-DS-02102-1.7 

September 2024 

**MachXO5-NX Family Data Sheet** 

## **Disclaimers** 

Lattice makes no warranty, representation, or guarantee regarding the accuracy of information contained in this document or the suitability of its products for any particular purpose. All information herein is provided AS IS, with all faults, and all associated risk is the responsibility entirely of the Buyer. The information provided herein is for informational purposes only and may contain technical inaccuracies or omissions, and may be otherwise rendered inaccurate for many reasons, and Lattice assumes no obligation to update or otherwise correct or revise this information. Products sold by Lattice have been subject to limited testing and it is the Buyer's responsibility to independently determine the suitability of any products and to test and verify the same. LATTICE PRODUCTS AND SERVICES ARE NOT DESIGNED, MANUFACTURED, OR TESTED FOR USE IN LIFE OR SAFETY CRITICAL SYSTEMS, HAZARDOUS ENVIRONMENTS, OR ANY OTHER ENVIRONMENTS REQUIRING FAIL-SAFE PERFORMANCE, INCLUDING ANY APPLICATION IN WHICH THE FAILURE OF THE PRODUCT OR SERVICE COULD LEAD TO DEATH, PERSONAL INJURY, SEVERE PROPERTY DAMAGE OR ENVIRONMENTAL HARM (COLLECTIVELY, "HIGH-RISK USES"). FURTHER, BUYER MUST TAKE PRUDENT STEPS TO PROTECT AGAINST PRODUCT AND SERVICE FAILURES, INCLUDING PROVIDING APPROPRIATE REDUNDANCIES, FAIL-SAFE FEATURES, AND/OR SHUT-DOWN MECHANISMS. LATTICE EXPRESSLY DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY OF FITNESS OF THE PRODUCTS OR SERVICES FOR HIGH-RISK USES. The information provided in this document is proprietary to Lattice Semiconductor, and Lattice reserves the right to make any changes to the information in this document or to any products at any time without notice. 

© 2021-2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02102-1.7 

2 

**MachXO5-NX Family Data Sheet** 

## **Contents** 

|**Contents**|**Contents**|**Contents**|
|---|---|---|
|Contents ...............................................................................................................................................................3|||
|Acronyms in This Document ............................................................................................................................. 11|||
|1.|General Description ............................................................................................................................... 13||
||1.1.|Features ............................................................................................................................................ 14|
|2.|Architecture ........................................................................................................................................... 17||
||2.1.|Overview ........................................................................................................................................... 17|
||2.2.|PFU Blocks ......................................................................................................................................... 20|
||2.3.|Routing .............................................................................................................................................. 25|
||2.4.|Clocking Structure ............................................................................................................................. 25|
||2.5.|SGMII TX/RX ...................................................................................................................................... 33|
||2.6.|sysMEM Memory .............................................................................................................................. 34|
||2.7.|Large RAM ......................................................................................................................................... 36|
||2.8.|sysDSP ............................................................................................................................................... 36|
||2.9.|Programmable I/O (PIO) ................................................................................................................... 40|
||2.10.|Programmable I/O Cell (PIC) ............................................................................................................. 40|
||2.11.|DDR Memory Support ....................................................................................................................... 45|
||2.12.|sysI/O Buffer ..................................................................................................................................... 49|
||2.13.|Analog Interface ................................................................................................................................ 55|
||2.14.|IEEE 1149.1-Compliant Boundary Scan Testability ........................................................................... 55|
||2.15.|Device Configuration ......................................................................................................................... 56|
||2.16.|Single Event Upset (SEU) Support ..................................................................................................... 57|
||2.17.|On-Chip Oscillator ............................................................................................................................. 57|
||2.18.|User I²C IP .......................................................................................................................................... 57|
||2.19.|User Flash Memory (UFM) ................................................................................................................ 58|
||2.20.|Trace ID ............................................................................................................................................. 58|
||2.21.|Pin Migration ..................................................................................................................................... 58|
||2.22.|Peripheral Component Interconnect Express (PCIe) ........................................................................ 59|
||2.23.|Cryptographic Engine ........................................................................................................................ 61|
|3.|DC and Switching Characteristics for LFMXO5-25 Commercial and Industrial ...................................... 62||
||3.1.|Absolute Maximum Ratings .............................................................................................................. 62|
||3.2.|Recommended Operating Conditions1, 2, 3........................................................................................ 62|
||3.3.|Power Supply Ramp Rates ................................................................................................................ 63|
||3.4.|Power up Sequence .......................................................................................................................... 63|
||3.5.|On-Chip Programmable Termination ................................................................................................ 63|
||3.6.|Hot Socketing Specifications ............................................................................................................. 65|
||3.7.|Programming/Erase Specifications ................................................................................................... 65|
||3.8.|ESD Performance .............................................................................................................................. 65|
||3.9.|DC Electrical Characteristics .............................................................................................................. 66|
||3.10.|Supply Currents ................................................................................................................................. 67|
||3.11.|sysI/O Recommended Operating Conditions .................................................................................... 68|
||3.12.|sysI/O Single-Ended DC Electrical Characteristics3........................................................................... 69|
||3.13.|sysI/O Differential DC Electrical Characteristics ............................................................................... 71|
||3.14.|Maximum sysI/O Buffer Speed ......................................................................................................... 80|
||3.15.|Typical Building Block Function Performance ................................................................................... 82|
||3.16.|LMMI ................................................................................................................................................. 83|
||3.17.|Derating Timing Tables ..................................................................................................................... 83|
||3.18.|External Switching Characteristics .................................................................................................... 83|



© 2021-2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02102-1.7 

3 

**MachXO5-NX Family Data Sheet** 

||3.19.|sysCLOCK PLL Timing (VCC= 1.0 V)..................................................................................................... 93|
|---|---|---|
||3.20.|Internal Oscillators Characteristics ................................................................................................... 94|
||3.21.|Flash Download Time ........................................................................................................................ 94|
||3.22.|Flash Program and Erase Current ..................................................................................................... 94|
||3.23.|User I2C Characteristics ..................................................................................................................... 94|
||3.24.|Analog-Digital Converter (ADC) Block Characteristics ...................................................................... 95|
||3.25.|Comparator Block Characteristics ..................................................................................................... 96|
||3.26.|Digital Temperature Readout Characteristics ................................................................................... 96|
||3.27.|Hardened SGMII Receiver Characteristics ........................................................................................ 96|
||3.28.|sysCONFIG Port Timing Specifications .............................................................................................. 97|
||3.29.|JTAG Port Timing Specifications ...................................................................................................... 102|
||3.30.|Switching Test Conditions ............................................................................................................... 103|
|4.|DC and Switching Characteristics for LFMXO5-55T/100T Commercial and Industrial ........................ 104|DC and Switching Characteristics for LFMXO5-55T/100T Commercial and Industrial ........................ 104|
||4.1.|Absolute Maximum Ratings ............................................................................................................ 104|
||4.2.|Recommended Operating Conditions1, 2, 3...................................................................................... 104|
||4.3.|Power Supply Ramp Rates .............................................................................................................. 105|
||4.4.|Power up Sequence ........................................................................................................................ 105|
||4.5.|On-Chip Programmable Termination .............................................................................................. 106|
||4.6.|Hot Socketing Specifications ........................................................................................................... 107|
||4.7.|Programming/Erase Specifications ................................................................................................. 107|
||4.8.|ESD Performance ............................................................................................................................ 107|
||4.9.|DC Electrical Characteristics ............................................................................................................ 108|
||4.10.|Supply Currents ............................................................................................................................... 109|
||4.11.|sysI/O Recommended Operating Conditions .................................................................................. 110|
||4.12.|sysI/O Single-Ended DC Electrical Characteristics3......................................................................... 112|
||4.13.|sysI/O Differential DC Electrical Characteristics ............................................................................. 114|
||4.14.|Maximum sysI/O Buffer Speed ....................................................................................................... 123|
||4.15.|Typical Building Block Function Performance ................................................................................. 125|
||4.16.|LMMI ............................................................................................................................................... 126|
||4.17.|Derating Timing Tables ................................................................................................................... 126|
||4.18.|External Switching Characteristics .................................................................................................. 127|
||4.19.|sysCLOCK PLL Timing (VCC= 1.0 V)................................................................................................... 136|
||4.20.|Internal Oscillators Characteristics ................................................................................................. 137|
||4.21.|Flash Download Time ...................................................................................................................... 137|
||4.22.|Flash Program and Erase Current ................................................................................................... 137|
||4.23.|User I2C Characteristics ................................................................................................................... 138|
||4.24.|Analog-Digital Converter (ADC) Block Characteristics .................................................................... 138|
||4.25.|Comparator Block Characteristics ................................................................................................... 139|
||4.26.|Digital Temperature Readout Characteristics ................................................................................. 139|
||4.27.|Hardened PCIe Characteristics ........................................................................................................ 140|
||4.28.|Hardened SGMII Receiver Characteristics ...................................................................................... 143|
||4.29.|sysCONFIG Port Timing Specifications ............................................................................................ 143|
||4.30.|JTAG Port Timing Specifications ...................................................................................................... 147|
||4.31.|Switching Test Conditions ............................................................................................................... 148|
|5.|Pinout Information ............................................................................................................................... 150||
||5.1.|Signal Descriptions .......................................................................................................................... 150|
||5.2.|Pin Information Summary ............................................................................................................... 155|
|6.|Ordering Information ........................................................................................................................... 158||
||6.1.|Part Number Description ................................................................................................................ 158|



© 2021-2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02102-1.7 

4 

**MachXO5-NX Family Data Sheet** 

|6.2.<br>Ordering Part Numbers ................................................................................................................... 159|
|---|
|Supplemental Information .............................................................................................................................. 160|
|For Further Information .............................................................................................................................. 160|
|Revision History .............................................................................................................................................. 161|



© 2021-2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02102-1.7 

5 

**MachXO5-NX Family Data Sheet** 

## **Figures** 

|Figure 2.1. Simplified Block Diagram, MachXO5-NX-25 Device (Top Level) ..................................................... 18|Figure 2.1. Simplified Block Diagram, MachXO5-NX-25 Device (Top Level) ..................................................... 18|
|---|---|
|Figure 2.2. Simplified Block Diagram, MachXO5-NX-55T Device (Top Level) ................................................... 19|Figure 2.2. Simplified Block Diagram, MachXO5-NX-55T Device (Top Level) ................................................... 19|
|Figure 2.3. Simplified Block Diagram, MachXO5-NX-100T Device (Top Level) ................................................. 20|Figure 2.3. Simplified Block Diagram, MachXO5-NX-100T Device (Top Level) ................................................. 20|
|Figure 2.4. PFU Diagram.................................................................................................................................... 21|Figure 2.4. PFU Diagram.................................................................................................................................... 21|
|Figure 2.5. Slice Diagram ................................................................................................................................... 22|Figure 2.5. Slice Diagram ................................................................................................................................... 22|
|Figure 2.6. Slice Configuration for LUT4 and LUT5 ........................................................................................... 23|Figure 2.6. Slice Configuration for LUT4 and LUT5 ........................................................................................... 23|
|Figure 2.7. General Purpose PLL Diagram ......................................................................................................... 26|Figure 2.7. General Purpose PLL Diagram ......................................................................................................... 26|
|Figure 2.8. Clocking for MachXO5-NX-25 Devices ............................................................................................ 27|Figure 2.8. Clocking for MachXO5-NX-25 Devices ............................................................................................ 27|
|Figure 2.9. Clocking for MachXO5-NX-55T/MachXO5-NX-100T Devices .......................................................... 27|Figure 2.9. Clocking for MachXO5-NX-55T/MachXO5-NX-100T Devices .......................................................... 27|
|Figure 2.10. Edge Clock Sources per Bank ........................................................................................................ 29|Figure 2.10. Edge Clock Sources per Bank ........................................................................................................ 29|
|Figure 2.11. DCS_CMUX Diagram for MachXO5-NX-25 Devices ....................................................................... 30|Figure 2.11. DCS_CMUX Diagram for MachXO5-NX-25 Devices ....................................................................... 30|
|Figure 2.12. DCS_CMUX Diagram for MachXO5-NX-55T/MachXO5-NX-100T Devices .................................... 30|Figure 2.12. DCS_CMUX Diagram for MachXO5-NX-55T/MachXO5-NX-100T Devices .................................... 30|
|Figure 2.13. DCS Waveforms ............................................................................................................................ 31|Figure 2.13. DCS Waveforms ............................................................................................................................ 31|
|Figure 2.14. DLLDEL Functional Diagram .......................................................................................................... 32|Figure 2.14. DLLDEL Functional Diagram .......................................................................................................... 32|
|Figure 2.15. DDRDLL Architecture for MachXO5-NX-25 Devices ...................................................................... 32|Figure 2.15. DDRDLL Architecture for MachXO5-NX-25 Devices ...................................................................... 32|
|Figure 2.16. DDRDLL Architecture for MachXO5-NX-55T/MachXO5-NX-100T Devices ................................... 33|Figure 2.16. DDRDLL Architecture for MachXO5-NX-55T/MachXO5-NX-100T Devices ................................... 33|
|Figure 2.17. SGMII CDR IP ................................................................................................................................. 34|Figure 2.17. SGMII CDR IP ................................................................................................................................. 34|
|Figure 2.18. Memory Core Reset ...................................................................................................................... 36|Figure 2.18. Memory Core Reset ...................................................................................................................... 36|
|Figure 2.19. Comparison of General DSP and MachXO5-NX Approaches ........................................................ 37|Figure 2.19. Comparison of General DSP and MachXO5-NX Approaches ........................................................ 37|
|Figure 2.20. DSP Functional Block Diagram ...................................................................................................... 39|Figure 2.20. DSP Functional Block Diagram ...................................................................................................... 39|
|Figure 2.21. Group of Two High Performance Programmable I/O Cells ........................................................... 41|Figure 2.21. Group of Two High Performance Programmable I/O Cells ........................................................... 41|
|Figure 2.22. Wide Range Programmable I/O Cells ............................................................................................ 41|Figure 2.22. Wide Range Programmable I/O Cells ............................................................................................ 41|
|Figure 2.23. Input Register Block for PIO on Top, Left, and Right Sides of the Device ..................................... 42|Figure 2.23. Input Register Block for PIO on Top, Left, and Right Sides of the Device ..................................... 42|
|Figure 2.24. Input Register Block for PIO on Bottom Side of the Device .......................................................... 43|Figure 2.24. Input Register Block for PIO on Bottom Side of the Device .......................................................... 43|
|Figure 2.25. Output Register Block on Top, Left, and Right Sides .................................................................... 43|Figure 2.25. Output Register Block on Top, Left, and Right Sides .................................................................... 43|
|Figure 2.26. Output Register Block on Bottom Side ......................................................................................... 44|Figure 2.26. Output Register Block on Bottom Side ......................................................................................... 44|
|Figure 2.27. Tri-state Register Block on Top, Left, and Right Sides .................................................................. 44|Figure 2.27. Tri-state Register Block on Top, Left, and Right Sides .................................................................. 44|
|Figure 2.28. Tri-state Register Block on Bottom Side ....................................................................................... 45|Figure 2.28. Tri-state Register Block on Bottom Side ....................................................................................... 45|
|Figure 2.29. DQS Grouping on the Bottom Edge .............................................................................................. 46|Figure 2.29. DQS Grouping on the Bottom Edge .............................................................................................. 46|
|Figure 2.30. DQS Control and Delay Block (DQSBUF) ....................................................................................... 47|Figure 2.30. DQS Control and Delay Block (DQSBUF) ....................................................................................... 47|
|Figure 2.31. sysI/O Banking of MachXO5-NX-25 Devices ................................................................................. 52|Figure 2.31. sysI/O Banking of MachXO5-NX-25 Devices ................................................................................. 52|
|Figure 2.32. sysI/O Banking of MachXO5-NX-55T/MachXO5-NX-100T Devices ............................................... 52|Figure 2.32. sysI/O Banking of MachXO5-NX-55T/MachXO5-NX-100T Devices ............................................... 52|
|Figure 2.33. PCIe Core ....................................................................................................................................... 59|Figure 2.33. PCIe Core ....................................................................................................................................... 59|
|Figure 2.34. PCIe Soft IP Wrapper ..................................................................................................................... 60|Figure 2.34. PCIe Soft IP Wrapper ..................................................................................................................... 60|
|Figure 2.35. Cryptographic Engine Block Diagram ............................................................................................ 61|Figure 2.35. Cryptographic Engine Block Diagram ............................................................................................ 61|
|Figure 3.1. On-Chip Termination ....................................................................................................................... 64|Figure 3.1. On-Chip Termination ....................................................................................................................... 64|
|Figure 3.2. LVDS25E Output Termination Example .......................................................................................... 72|Figure 3.2. LVDS25E Output Termination Example .......................................................................................... 72|
|Figure 3.3. SubLVDS Input Interface ................................................................................................................. 73|Figure 3.3. SubLVDS Input Interface ................................................................................................................. 73|
|Figure 3.4. SubLVDS Output Interface .............................................................................................................. 74|Figure 3.4. SubLVDS Output Interface .............................................................................................................. 74|
|Figure 3.5. SLVS Interface ................................................................................................................................. 75|Figure 3.5. SLVS Interface ................................................................................................................................. 75|
|Figure 3.6. MIPI Interface.................................................................................................................................. 76|Figure 3.6. MIPI Interface.................................................................................................................................. 76|
|Figure 3.7. Receiver RX.CLK.Centered Waveforms ........................................................................................... 90|Figure 3.7. Receiver RX.CLK.Centered Waveforms ........................................................................................... 90|
|Figure 3.8. Receiver RX.CLK.Aligned and DDR Memory Input Waveforms....................................................... 90|Figure 3.8. Receiver RX.CLK.Aligned and DDR Memory Input Waveforms....................................................... 90|
|Figure 3.9. Transmit TX.CLK.Centered and DDR Memory Output Waveforms ................................................. 90|Figure 3.9. Transmit TX.CLK.Centered and DDR Memory Output Waveforms ................................................. 90|
|Figure 3.10. Transmit TX.CLK.Aligned Waveforms ............................................................................................ 91|Figure 3.10. Transmit TX.CLK.Aligned Waveforms ............................................................................................ 91|
|Figure 3.11. DDRX71 Video Timing Waveforms ................................................................................................ 91|Figure 3.11. DDRX71 Video Timing Waveforms ................................................................................................ 91|
|Figure 3.12. Receiver DDRX71_RX Waveforms ................................................................................................. 92|Figure 3.12. Receiver DDRX71_RX Waveforms ................................................................................................. 92|



© 2021-2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02102-1.7 

6 

**MachXO5-NX Family Data Sheet** 

|Figure 3.13. Transmitter DDRX71_TX Waveforms ............................................................................................ 92|Figure 3.13. Transmitter DDRX71_TX Waveforms ............................................................................................ 92|
|---|---|
|Figure 3.14. Configuration Error Notification (1) .............................................................................................. 99|Figure 3.14. Configuration Error Notification (1) .............................................................................................. 99|
|Figure 3.15. Slave SPI/I|Figure 3.15. Slave SPI/I2C/I3C POR/REFRESH Timing ........................................................................................ 99|
|Figure 3.16. Slave SPI/I|Figure 3.16. Slave SPI/I2C/I3C PROGRAMN Timing ......................................................................................... 100|
|Figure 3.17. Slave SPI Configuration Timing ................................................................................................... 100|Figure 3.17. Slave SPI Configuration Timing ................................................................................................... 100|
|Figure 3.18. I|Figure 3.18. I2C /I3C Configuration Timing ...................................................................................................... 101|
|Figure 3.19. Slave SPI/I|Figure 3.19. Slave SPI/I2C/I3C Wake-Up Timing .............................................................................................. 101|
|Figure 3.20. JTAG Port Timing Waveforms ..................................................................................................... 102|Figure 3.20. JTAG Port Timing Waveforms ..................................................................................................... 102|
|Figure 3.21. Output Test Load, LVTTL and LVCMOS Standards ...................................................................... 103|Figure 3.21. Output Test Load, LVTTL and LVCMOS Standards ...................................................................... 103|
|Figure 4.1. On-Chip Termination ..................................................................................................................... 106|Figure 4.1. On-Chip Termination ..................................................................................................................... 106|
|Figure 4.2. LVDS25E Output Termination Example ........................................................................................ 115|Figure 4.2. LVDS25E Output Termination Example ........................................................................................ 115|
|Figure 4.3. SubLVDS Input Interface ............................................................................................................... 116|Figure 4.3. SubLVDS Input Interface ............................................................................................................... 116|
|Figure 4.4. SubLVDS Output Interface ............................................................................................................ 117|Figure 4.4. SubLVDS Output Interface ............................................................................................................ 117|
|Figure 4.5. SLVS Interface ............................................................................................................................... 118|Figure 4.5. SLVS Interface ............................................................................................................................... 118|
|Figure 4.6. MIPI Interface................................................................................................................................ 119|Figure 4.6. MIPI Interface................................................................................................................................ 119|
|Figure 4.7. Receiver RX.CLK.Centered Waveforms ......................................................................................... 133|Figure 4.7. Receiver RX.CLK.Centered Waveforms ......................................................................................... 133|
|Figure 4.8. Receiver RX.CLK.Aligned and DDR Memory Input Waveforms..................................................... 133|Figure 4.8. Receiver RX.CLK.Aligned and DDR Memory Input Waveforms..................................................... 133|
|Figure 4.9. Transmit TX.CLK.Centered and DDR Memory Output Waveforms ............................................... 134|Figure 4.9. Transmit TX.CLK.Centered and DDR Memory Output Waveforms ............................................... 134|
|Figure 4.10. Transmit TX.CLK.Aligned Waveforms .......................................................................................... 134|Figure 4.10. Transmit TX.CLK.Aligned Waveforms .......................................................................................... 134|
|Figure 4.11. DDRX71 Video Timing Waveforms .............................................................................................. 135|Figure 4.11. DDRX71 Video Timing Waveforms .............................................................................................. 135|
|Figure 4.12. Receiver DDRX71_RX Waveforms ............................................................................................... 135|Figure 4.12. Receiver DDRX71_RX Waveforms ............................................................................................... 135|
|Figure 4.13. Transmitter DDRX71_TX Waveforms .......................................................................................... 136|Figure 4.13. Transmitter DDRX71_TX Waveforms .......................................................................................... 136|
|Figure 4.14. Configuration Error Notification (2) ............................................................................................ 145|Figure 4.14. Configuration Error Notification (2) ............................................................................................ 145|
|Figure 4.15. Slave SPI/I|Figure 4.15. Slave SPI/I2C/I3C POR/REFRESH Timing ...................................................................................... 145|
|Figure 4.16. Slave SPI/I|Figure 4.16. Slave SPI/I2C/I3C PROGRAMN Timing ......................................................................................... 146|
|Figure 4.17. Slave SPI Configuration Timing ................................................................................................... 146|Figure 4.17. Slave SPI Configuration Timing ................................................................................................... 146|
|Figure 4.18. I|Figure 4.18. I2C /I3C Configuration Timing ...................................................................................................... 147|
|Figure 4.19. Slave SPI/I|Figure 4.19. Slave SPI/I2C/I3C Wake-Up Timing .............................................................................................. 147|
|Figure 4.20. JTAG Port Timing Waveforms ..................................................................................................... 148|Figure 4.20. JTAG Port Timing Waveforms ..................................................................................................... 148|
|Figure 4.21. Output Test Load, LVTTL and LVCMOS Standards ...................................................................... 149|Figure 4.21. Output Test Load, LVTTL and LVCMOS Standards ...................................................................... 149|
|Figure 6.1. Top Marking Diagram.................................................................................................................... 159|Figure 6.1. Top Marking Diagram.................................................................................................................... 159|



© 2021-2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02102-1.7 

7 

**MachXO5-NX Family Data Sheet** 

## **Tables** 

**==> picture [486 x 628] intentionally omitted <==**

**----- Start of picture text -----**<br>
||||
|---|---|---|
|Table 1.1. MachXO5-NX Commercial/Industrial Family Selection Guide ......................................................... 16|
|Table 2.1. Resources and Modes Available per Slice ........................................................................................ 21|
|Table 2.2. Slice Signal Descriptions ................................................................................................................... 23|
|Table 2.3. Number of Slices Required to Implement Distributed RAM ............................................................ 24|
|Table 2.4. sysMEM Block Configurations .......................................................................................................... 35|
|Table 2.5. Maximum Number of Elements in a sysDSP block ........................................................................... 40|
|Table 2.6. Input Block Port Description ............................................................................................................ 42|
|Table 2.7. Output Block Port Description ......................................................................................................... 44|
|Table 2.8. Tri-state Block Port Description ....................................................................................................... 45|
|Table 2.9. DQSBUF Port List Description ........................................................................................................... 48|
|Table 2.10. Single-Ended I/O Standards ........................................................................................................... 50|
|Table 2.11. Differential I/O Standards .............................................................................................................. 51|
|Table 2.12. Single-Ended I/O Standards Supported on Various Sides .............................................................. 54|
|Table 2.13. Differential I/O Standards Supported on Various Sides ................................................................. 54|
|Table 2.14. UFM Size ......................................................................................................................................... 58|
|Table 3.1. Absolute Maximum Ratings ............................................................................................................. 62|
|Table 3.2. Recommended Operating Conditions .............................................................................................. 62|
|Table 3.3. Power Supply Ramp Rates................................................................................................................ 63|
|Table 3.4. Power-On Reset ............................................................................................................................... 63|
|Table 3.5. On-Chip Termination Options for Input Modes ............................................................................... 64|
|Table 3.6. Hot Socketing Specifications for GPIO ............................................................................................. 65|
|Table 3.7. Programming/Erase Specifications .................................................................................................. 65|
|Table 3.8. DC Electrical Characteristics – Wide Range (Over Recommended Operating Conditions) .............. 66|
|Table 3.9. DC Electrical Characteristics – High Speed (Over Recommended Operating Conditions) ............... 66|
|Table 3.10. Capacitors – Wide Range (Over Recommended Operating Conditions) ....................................... 66|
|Table 3.11. Capacitors – High Performance (Over Recommended Operating Conditions) .............................. 67|
|Table 3.12. Single Ended Input Hysteresis – Wide Range (Over Recommended Operating Conditions) ......... 67|
|Table 3.13. Single Ended Input Hysteresis – High Performance (Over Recommended Operating Conditions) 67|
|Table 3.14. sysI/O Recommended Operating Conditions ................................................................................. 68|
|Table 3.15. sysI/O DC Electrical Characteristics – Wide Range I/O (Over Recommended Operating Conditions)|
|.......................................................................................................................................................................... 69|
|Table 3.16. sysI/O DC Electrical Characteristics – High Performance I/O (Over Recommended Operating|
|Conditions)|[3]|....................................................................................................................................................... 70|
|Table 3.17. I/O Resistance Characteristics (Over Recommended Operating Conditions) ................................ 70|
|Table 3.18. VIN Maximum Overshoot/Undershoot Allowance – Wide Range|[1,2]|.............................................. 71|
|Table 3.19. VIN Maximum Overshoot/Undershoot Allowance – High Performance|[1,2]|.................................... 71|
|Table 3.20. LVDS DC Electrical Characteristics (Over Recommended Operating Conditions)|[1]|......................... 71|
|Table 3.21. LVDS25E DC Conditions .................................................................................................................. 72|
|Table 3.22. SubLVDS Input DC Electrical Characteristics (Over Recommended Operating Conditions) .......... 73|
|Table 3.23. SubLVDS Output DC Electrical Characteristics (Over Recommended Operating Conditions) ....... 73|
|Table 3.24. SLVS Input DC Characteristics (Over Recommended Operating Conditions) ................................ 74|
|Table 3.25. SLVS Output DC Characteristics (Over Recommended Operating Conditions) ............................. 75|
|Table 3.26. Soft D-PHY Input Timing and Levels ............................................................................................... 77|
|Table 3.27. Soft D-PHY Output Timing and Levels ............................................................................................ 78|
|Table 3.28. Soft D-PHY Clock Signal Specification ............................................................................................. 78|
|Table 3.29. Soft D-PHY Data-Clock Timing Specifications ................................................................................. 79|
|Table 3.30. Maximum I/O Buffer Speed|[1, 2, 3, 4, 7]|................................................................................................ 80|

**----- End of picture text -----**<br>


© 2021-2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02102-1.7 

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**MachXO5-NX Family Data Sheet** 

**==> picture [486 x 656] intentionally omitted <==**

**----- Start of picture text -----**<br>
|||||
|---|---|---|---|
|Table 3.31. Pin-to-Pin Performance .................................................................................................................. 82|
|Table 3.32. Register-to-Register Performance|[1, 3, 4]|........................................................................................... 82|
|Table 3.33. LMMI FMAX Summary ...................................................................................................................... 83|
|Table 3.34. External Switching Characteristics (VCC = 1.0 V) ............................................................................. 83|
|Table 3.35. sysCLOCK PLL Timing (VCC = 1.0 V) .................................................................................................. 93|
|Table 3.36. Internal Oscillators (VCC = 1.0 V) ..................................................................................................... 94|
|Table 3.37. Flash Download Time ..................................................................................................................... 94|
|Table 3.38. Program and Erase Supply Current ................................................................................................ 94|
|Table 3.39. User I|[2]|C|Specifications (VCC = 1.0 V) ................................................................................................ 94|
|Table 3.40. ADC Specifications|[1]|........................................................................................................................ 95|
|Table 3.41. Comparator Specifications ............................................................................................................. 96|
|Table 3.42. DTR Specifications|[1, 2]|...................................................................................................................... 96|
|Table 3.43. SGMII Rx ......................................................................................................................................... 96|
|Table 3.44. sysCONFIG Port Timing Specifications ........................................................................................... 97|
|Table 3.45. JTAG Port Timing Specifications ................................................................................................... 102|
|Table 3.46. Test Fixture Required Components, Non-Terminated Interfaces ................................................ 103|
|Table 4.1. Absolute Maximum Ratings ........................................................................................................... 104|
|Table 4.2. Recommended Operating Conditions ............................................................................................ 104|
|Table 4.3. Power Supply Ramp Rates.............................................................................................................. 105|
|Table 4.4. Power-On Reset ............................................................................................................................. 106|
|Table 4.5. On-Chip Termination Options for Input Modes ............................................................................. 106|
|Table 4.6. Hot Socketing Specifications for GPIO ........................................................................................... 107|
|Table 4.7. Programming/Erase Specifications ................................................................................................ 107|
|Table 4.8. DC Electrical Characteristics – Wide Range (Over Recommended Operating Conditions) ............ 108|
|Table 4.9. DC Electrical Characteristics – High Speed (Over Recommended Operating Conditions) ............. 108|
|Table 4.10. Capacitors – Wide Range (Over Recommended Operating Conditions) ..................................... 108|
|Table 4.11. Capacitors – High Performance (Over Recommended Operating Conditions) ............................ 109|
|Table 4.12. Single Ended Input Hysteresis – Wide Range (Over Recommended Operating Conditions) ....... 109|
|Table 4.13. Single Ended Input Hysteresis – High Performance (Over Recommended Operating Conditions)|
|........................................................................................................................................................................ 109|
|Table 4.14. sysI/O Recommended Operating Conditions ............................................................................... 110|
|Table 4.15. sysI/O DC Electrical Characteristics – Wide Range I/O (Over Recommended Operating Conditions)|
|........................................................................................................................................................................ 112|
|Table 4.16. sysI/O DC Electrical Characteristics – High Performance I/O (Over Recommended Operating|
|Conditions)|[3]|..................................................................................................................................................... 113|
|Table 4.17. I/O Resistance Characteristics (Over Recommended Operating Conditions) .............................. 113|
|Table 4.18. VIN Maximum Overshoot/Undershoot Allowance – Wide Range|[1,2]|............................................ 114|
|Table 4.19. VIN Maximum Overshoot/Undershoot Allowance – High Performance|[1,2]|.................................. 114|
|Table 4.20. LVDS DC Electrical Characteristics (Over Recommended Operating Conditions)|[1]|....................... 114|
|Table 4.21. LVDS25E DC Conditions ................................................................................................................ 115|
|Table 4.22. SubLVDS Input DC Electrical Characteristics (Over Recommended Operating Conditions) ........ 116|
|Table 4.23. SubLVDS Output DC Electrical Characteristics (Over Recommended Operating Conditions) ..... 116|
|Table 4.24. SLVS Input DC Characteristics (Over Recommended Operating Conditions) .............................. 117|
|Table 4.25. SLVS Output DC Characteristics (Over Recommended Operating Conditions) ........................... 118|
|Table 4.26. Soft D-PHY Input Timing and Levels ............................................................................................. 120|
|Table 4.27. Soft D-PHY Output Timing and Levels .......................................................................................... 121|
|Table 4.28. Soft D-PHY Clock Signal Specification ........................................................................................... 121|
|Table 4.29. Soft D-PHY Data-Clock Timing Specifications ............................................................................... 122|
|Table 4.30. Maximum I/O Buffer Speed|[1, 2, 3, 4, 7]|.............................................................................................. 123|

**----- End of picture text -----**<br>


© 2021-2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02102-1.7 

**MachXO5-NX Family Data Sheet** 

|Table 4.31. Pin-to-Pin Performance ................................................................................................................ 125|Table 4.31. Pin-to-Pin Performance ................................................................................................................ 125|
|---|---|
|Table 4.32. Register-to-Register Performance|Table 4.32. Register-to-Register Performance1, 3, 4......................................................................................... 125|
|Table 4.33. LMMI F|Table 4.33. LMMI FMAXSummary .................................................................................................................... 126|
|Table 4.34. External Switching Characteristics (V|Table 4.34. External Switching Characteristics (VCC= 1.0 V) ........................................................................... 127|
|Table 4.35. sysCLOCK PLL Timing (V|Table 4.35. sysCLOCK PLL Timing (VCC= 1.0 V) ................................................................................................ 136|
|Table 4.36. Internal Oscillators (V|Table 4.36. Internal Oscillators (VCC= 1.0 V) ................................................................................................... 137|
|Table 4.37. Flash Download Time ................................................................................................................... 137|Table 4.37. Flash Download Time ................................................................................................................... 137|
|Table 4.38. Program and Erase Supply Current .............................................................................................. 137|Table 4.38. Program and Erase Supply Current .............................................................................................. 137|
|Table 4.39. User I|Table 4.39. User I2C Specifications (VCC= 1.0 V) .............................................................................................. 138|
|Table 4.40. ADC Specifications|Table 4.40. ADC Specifications1...................................................................................................................... 138|
|Table 4.41. Comparator Specifications ........................................................................................................... 139|Table 4.41. Comparator Specifications ........................................................................................................... 139|
|Table 4.42. DTR Specifications|Table 4.42. DTR Specifications1, 2.................................................................................................................... 139|
|Table 4.43. PCIe (2.5 Gbps) ............................................................................................................................. 140|Table 4.43. PCIe (2.5 Gbps) ............................................................................................................................. 140|
|Table 4.44. PCIe (5 Gbps) ................................................................................................................................ 141|Table 4.44. PCIe (5 Gbps) ................................................................................................................................ 141|
|Table 4.45. SGMII Rx ....................................................................................................................................... 143|Table 4.45. SGMII Rx ....................................................................................................................................... 143|
|Table 4.46. sysCONFIG Port Timing Specifications ......................................................................................... 143|Table 4.46. sysCONFIG Port Timing Specifications ......................................................................................... 143|
|Table 4.47. JTAG Port Timing Specifications ................................................................................................... 147|Table 4.47. JTAG Port Timing Specifications ................................................................................................... 147|
|Table 4.48. Test Fixture Required Components, Non-Terminated Interfaces ................................................ 149|Table 4.48. Test Fixture Required Components, Non-Terminated Interfaces ................................................ 149|
|Table 5.1. Signal Descriptions ......................................................................................................................... 150|Table 5.1. Signal Descriptions ......................................................................................................................... 150|
|Table 5.2. Pin Information Summary .............................................................................................................. 155|Table 5.2. Pin Information Summary .............................................................................................................. 155|



© 2021-2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02102-1.7 

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**MachXO5-NX Family Data Sheet** 

## **Acronyms in This Document** 

|**Acronym **<br>~~pe~~|**Definition**|
|---|---|
|ADC<br>~~pe~~<br>~~a~~<br>~~pe~~|Analogto Digital Converter|
|AHB-Lite<br>~~pe~~<br>~~ee~~|Advanced High-performance Bus-Lite|
|AI<br>~~pe~~<br>~~ee~~|Artificial Intelligence|
|APB<br>~~ee~~<br>~~a~~|Advanced Peripheral Bus|
|BGA<br>~~a~~<br>~~pe~~|Ball Grid Array|
|CDR<br>~~pe~~<br>~~pe~~|Clock and Data Recovery|
|CRC<br>~~pe~~<br>~~pe~~<br>~~pe~~|Cycle RedundancyCode|
|CRE<br>~~pe~~<br>~~pe~~<br>~~ee~~|Cryptographic Engine|
|CSI-2<br>~~pe~~<br>~~ee~~|Camera Serial Interface-2|
|DCC<br>~~ee~~<br>~~a~~|Dynamic Clock Control|
|DCS<br>~~ee~~|Dynamic Clock Select|
|DDR<br>~~ee~~<br>~~ee~~|Double Data Rate|
|DLL<br>~~ee~~<br>~~ee~~|DelayLocked Loops|
|D-PHY<br>~~ee~~<br>~~a~~<br>~~ee~~|DisplaySerial Interface-Physical Layer|
|DRAM<br>~~ee~~|Dynamic Random Access Memory|
|DSI<br>~~ee~~<br>~~a~~<br>~~ee~~|Digital Serial Interface|
|DSP<br>~~a~~<br>~~ee~~<br>~~ee~~|Digital Signal Processing|
|DTR<br>~~ee~~<br>~~ee~~|Digital Temperature Readout|
|EBR<br>~~ee~~<br>~~a~~<br>~~ee~~|Embedded Block RAM|
|ECC<br>~~ee~~<br>~~ee~~|Error Correction Coding|
|ECLK<br>~~ee~~<br>~~ee~~|Edge Clock|
|EMIF<br>~~ee~~<br>~~a~~<br>~~ee~~|External MemoryInterface|
|ESFB<br>~~a~~<br>~~ee~~|Embedded SecurityFunction Block|
|FD-SOI<br>~~ee~~<br>~~a~~|FullyDepleted Silicon on Insulator|
|FFT<br>~~a~~|Fast Fourier Transforms|
|FIFO<br>~~a~~<br>~~a~~|First In First Out|
|FIR<br>~~a~~|Finite Impulse Response|
|HP<br>~~a~~<br>~~a~~<br>~~pe~~|High Performance|
|HSP<br>~~a~~<br>~~pe~~|High Speed Port|
|JTAG<br>~~pe~~<br>~~a~~|Joint Test Action Group|
|LC<br>~~a~~<br>~~a~~|Logic Cell|
|LMMI<br>~~a~~|Lattice MemoryMapped Interface|
|LOL<br>~~a~~<br>~~a~~<br>~~pe~~|Loss of Lock|
|LRAM<br>~~a~~<br>~~pe~~|Large RAM|
|LVCMOS<br>~~pe~~<br>~~a~~|Low-Voltage ComplementaryMetal Oxide Semiconductor|
|LVDS<br>~~a~~|Low-Voltage Differential Signaling|
|LVPECL<br>~~a~~|Low Voltage Positive Emitter Coupled Logic|
|LVTTL<br>~~a~~<br>~~a~~|Low Voltage Transistor-Transistor Logic|
|LUT<br>~~a~~<br>~~a~~|Look UpTable|
|MIPI<br>~~a~~<br>~~a~~|Mobile IndustryProcessor Interface|
|ML<br>~~a~~|Machine Learning|
|MSPS<br>~~a~~|Million Samplesper Second|
|PCI<br>~~a~~<br>~~a~~|Peripheral Component Interconnect|
|PCS<br>~~a~~<br>~~a~~|Physical CodingSublayer|
|PCLK<br>~~a~~|PrimaryClock|



© 2021-2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02102-1.7 

11 

**MachXO5-NX Family Data Sheet** 

|**Acronym **<br>~~pe~~|**Definition**|
|---|---|
|PDPR<br>~~pe~~<br>~~a~~<br>~~pe~~|Pseudo Dual Port RAM|
|PFU<br>~~pe~~<br>~~ee~~|Programmable Functional Unit|
|PIC<br>~~pe~~<br>~~ee~~|Programmable I/O Cells|
|PLL<br>~~ee~~<br>~~a~~|Phase Locked Loops|
|POR<br>~~a~~<br>~~pe~~|Power On Reset|
|RAM<br>~~pe~~<br>~~pe~~|Random Access Memory|
|ROM<br>~~pe~~<br>~~pe~~<br>~~pe~~|Read OnlyMemory|
|SAR<br>~~pe~~<br>~~pe~~<br>~~ee~~|Successive Approximation Resistor|
|SEC<br>~~pe~~<br>~~ee~~|Soft Error Correction|
|SED<br>~~ee~~<br>~~a~~<br>~~pe~~|Soft Error Detection|
|SER<br>~~pe~~<br>~~pe~~|Soft Error Rate|
|SEU<br>~~pe~~<br>~~pe~~<br>~~a~~|Single Event Upset|
|SGMII<br>~~pe~~<br>~~a~~|Serial Gigabit Media Independent Interface|
|SLVS<br>~~a~~<br>~~a~~<br>~~ee~~|Scalable Low-Voltage Signaling|
|SPI<br>~~ee~~|Serial Peripheral Interface|
|SPR<br>~~ee~~<br>~~ee~~|Single Port RAM|
|SRAM<br>~~ee~~<br>~~ee~~|Static Random Access Memory|
|subLVDS<br>~~ee~~<br>~~ee~~|(Reduced Voltage)Low Voltage Differential Signaling|
|TAP<br>~~ee~~<br>~~a~~<br>~~ee~~|Test Access Port|
|TDM<br>~~ee~~<br>~~ee~~|Time Division Multiplexing|
|UFM<br>~~ee~~<br>~~ee~~|User Flash Memory|
|VREF<br>~~ee~~<br>~~a~~|Voltage Reference|



© 2021-2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02102-1.7 

12 

**MachXO5-NX Family Data Sheet** 

## **1. General Description** 

The MachXO5™-NX family of low-power FPGAs can be used in a wide range of applications, and are optimized for bridging, I/O expansion, and board control and management. It is built on Lattice Semiconductor Nexus FPGA platform, using low-power 28 nm FD-SOI technology. It combines the extreme flexibility of an FPGA with the low power and high reliability (due to the extreme low Soft Error Rate) of FDSOI technology, and offers small footprint package options. 

The MachXO5-NX family supports a variety of interfaces including MIPI D-PHY (CSI-2, DSI), LVDS, SLVS, subLVDS, SGMII (Gigabit Ethernet), PCI Express® (Gen1, and Gen2) and more. It includes embedded flash memory for on-chip multi-boot and UFM. 

Processing features of MachXO5-NX device include up to 96k logic cells, 156 18 × 18 multipliers, 7.3 Mb of embedded memory (consisting of EBR and LRAM blocks), distributed memory, DRAM interfaces (supporting DDR3, DDR3L, and LPDDR4 up to 1066 Mbps). 

The MachXO5-NX FPGA supports the fast configuration of its reconfigurable SRAM-based logic fabric, and ultra-fast configuration of its programmable sysI/O™ from on-chip Flash. To secure user designs, the MachXO5-NX security features include bitstream encryption, authentication, and password protection. In addition to the high reliability inherent to FD-SOI technology (due to its extreme low SER), active reliability features such as built-in frame-based SED/SEC (for SRAM-based logic fabric), and ECC (for EBR and LRAM) are also supported. Built-in ADC is available in each device for system monitoring functions. 

Lattice Radiant™ design software allows large complex user designs to be efficiently implemented on the MachXO5-NX FPGA family. Synthesis library support for MachXO5-NX devices is available for popular logic synthesis tools. Radiant tools use the synthesis tool output along with constraints from its floor planning tools, to place and route the user design in MachXO5-NX device. The tools extract timing from the routing, and back-annotate it into the design for timing verification. 

Lattice Semiconductor provides many pre-engineered Intellectual Property (IP) modules for the MachXO5-NX family. By using these configurable soft IP cores as standardized blocks, you are free to concentrate on the unique aspects of your design, increasing your productivity. 

© 2021-2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02102-1.7 

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**MachXO5-NX Family Data Sheet** 

## **1.1. Features** 

- Programmable Architecture 

   - 27k to 96k logic cells 

   - 20 to 156 18 × 18 multipliers (in sysDSP™ blocks) 

   - 1.9 Mb to 7.3 Mb of embedded memory blocks (EBR, LRAM) 

   - 200 to 300 programmable sysI/O (High Performance and Wide Range I/O) 

- Programmable sysI/O supports wide varieties of interfaces 

   - High Performance (HP) on bottom I/O dual rank 

      - Supports up to 1.8 V VCCIO 

      - Mixed voltage support (1.0 V, 1.2 V, 1.5 V, 1.8 V) 

      - High-speed differential up to 1.2 Gbps 

      - • Supports soft D-PHY (Tx/Rx), LVDS 7:1 (Tx/Rx), SLVS (Tx/Rx), subLVDS (Rx) 

      - Supports SGMII (Gb Ethernet) – two channels (Tx/Rx) at 1.25 Gbps 

      - Dedicated DDR3/DDR3L/LPDDR4 memory support with DQS logic, up to 1066 Mbps data-rate and ×16 data-width 

   - Wide Range (WR) on Left, Right and Top I/O Banks 

      - Supports up to 3.3 V VCCIO 

      - Mixed voltage support (1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.3 V) 

      - Programmable slew rate (slow, medium, fast) 

      - Controlled impedance mode 

      - Emulated LVDS support 

      - Hot socketing support 

- PCIe hard IP supports: 

   - Gen1, and Gen2 

   - Endpoint 

      - Multi-function up to four functions 

      - One single lane or two single lanes 

- Power Modes – Low-Power versus High-Performance modes 

   - User selectable 

   - Low-Power mode for power and/or thermal challenges 

   - High-Performance mode for faster processing 

- Small footprint package options 

   - 14 × 14 mm to 17 × 17 mm package options 

- Two channels of Clock Data Recovery (CDR) up to 1.25 Gbps to support SGMII using HP I/O 

   - CDR for RX 

   - 8b/10b decoding 

   - Independent Loss of Lock (LOL) detector for each CDR block 

- sysCLOCK™ analog PLLs 

   - Two for 27k LC device 

   - Six outputs per PLL 

   - Fractional N 

   - Programmable and dynamic phase control 

- sysDSP enhanced DSP blocks 

   - Hardened pre-adder 

   - Dynamic Shift for AI/ML support 

   - Four 18 × 18, eight 9 × 9, two 18 × 36, or 36 × 36  multipliers 

   - Advanced 18 × 36, two 18 × 18, or four 8 × 8 MAC 

- Flexible memory resources 

   - 1.4 Mb sysMEM™ Embedded Block RAM (EBR) 

   - Programmable width 

   - Error Correction Coding (ECC)[1] 

   - First Input First Output (FIFO) 

   - 184 to 639 kbit distributed RAM 

   - Large RAM Blocks 

      - 0.5 Mb per block 

© 2021-2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02102-1.7 

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**MachXO5-NX Family Data Sheet** 

- Internal bus interface support 

   - APB control bus 

   - AHB-Lite for data bus 

   - AXI4-streaming 

- Non-Volatile Configuration – Fast, Secure, On-chip multi-boot 

   - Embedded flash memory 

   - Single-chip, secure solution 

   - JTAG, SPI, I[2] C and I3C 

   - Ultrafast I/O configuration for instant-on support 

   - Multi-sectored UFM for customer data storage 

   - Bitstream Security 

      - Encryption 

      - Authentication 

- Cryptographic Engine 

   - Bitstream encryption – using AES-256 

   - Bitstream authentication – using ECDSA 

   - Hashing algorithms – SHA, HMAC 

   - Single Event Upset (SEU) Mitigation Support 

      - Extremely low Soft Error Rate (SER) due to FD-SOI technology 

      - Soft Error Detection – Embedded hard macro 

      - Soft Error Correction – Continuous user operation mode 

      - Soft Error Injection – Emulate SEU event to debug system error handling 

   - Dual ADC – 1 MSPS, 12-bit SAR with Simultaneous Sampling[1] 

      - Two ADCs per device 

      - Three Continuous-time Comparators 

      - Simultaneous sampling 

   - System Level Support 

      - IEEE 1149.1 and IEEE 1532 compliant 

      - Reveal Logic Analyzer 

      - On-chip oscillator for initialization and general use 

      - 1.0 V core power supply 

- True Random Number Generator 

- AES 128/256 Encryption 

## **Note:** 

1. Available in select speed grades, see Ordering Information. 

© 2021-2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02102-1.7 

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**MachXO5-NX Family Data Sheet** 

**Table 1.1. MachXO5-NX Commercial/Industrial Family Selection Guide** 

|**Device**<br>~~a~~|**LFMXO5-25**<br>~~GG~~|**LFMXO5-55T**<br>~~GG~~|**LFMXO5-100T**<br>~~GG~~|
|---|---|---|---|
|Logic Cells1<br>~~Ge~~|27k<br>~~Ge~~|53k<br>~~Ge~~|96k<br>~~Ge~~|
|Embedded Memory (EBR) Blocks<br>(18 kb)|80|166|208|
|Embedded Memory (EBR)Bits(kb)<br>~~eG~~|1,440<br>~~eG~~|2,988<br>~~eG~~|3,744<br>~~eG~~|
|Distributed RAM Bits(kb)<br>~~Ge~~<br>~~a~~|184<br>~~Ge~~<br>~~Ge~~|320<br>~~Ge~~|639<br>~~Ge~~|
|Large Memory (LRAM)Blocks<br>~~a~~<br>~~a~~|1<br>~~Ge~~<br>~~Ge~~|5|7|
|Large Memory (LRAM)Bits(kb)<br>~~a~~<br>~~a~~|512<br>~~Ge~~<br>~~Ge~~|2,560|3,584|
|18 × 18 Multipliers<br>~~a~~<br>~~eG~~|20<br>~~Ge~~<br>~~eG~~|146<br>~~eG~~|156<br>~~eG~~|
|ADC Blocks2<br>~~eG~~|2<br>~~eG~~|2<br>~~eG~~|2<br>~~eG~~|
|450 MHz High FrequencyOscillator<br>~~Ge~~<br>~~a~~|1<br>~~Ge~~<br>~~Ge~~|1<br>~~Ge~~|1<br>~~Ge~~|
|128 kHz Low Power Oscillator<br>~~a~~<br>~~a~~|1<br>~~Ge~~<br>~~Ge~~|1|1|
|GPLL<br>~~a~~<br>~~a~~|2<br>~~Ge~~<br>~~Ge~~|4|4|
|PCIe Gen2 hard IP<br>~~a~~<br>~~a~~|0<br>~~Ge~~<br>~~DO~~|1<br>~~DO~~|1<br>~~DO~~|
|SERDES(Quad/Channels)<br>~~a~~<br>~~GO~~|0<br>~~DO~~<br>~~GO~~|½<br>~~DO~~<br>~~GO~~|½<br>~~DO~~<br>~~GO~~|
|Bitstream Authentication<br>~~GO~~<br>~~Ge~~|ECDSA-256<br>~~GO~~<br>~~Ge~~|ECDSA-256<br>~~GO~~<br>~~Ge~~|ECDSA-256<br>~~GO~~<br>~~Ge~~|
|UFM(kb)<br>~~Ge~~|15,360<br>~~Ge~~|79,872<br>~~Ge~~|79,872<br>~~Ge~~|
|EMIF<br>~~Ge~~|DDR3, DDR3L<br>~~Ge~~|DDR3, DDR3L, LPDDR4<br>~~Ge~~|DDR3, DDR3L, LPDDR4<br>~~Ge~~|
|**Packages (Size, Ball Pitch)**|**SERDES Channels/Ios (Wide Range (WR) GPIOs (Top/Left/Right Banks) + High**<br>**Performance(HP) GPIOs(Bottom Banks) + ADC dedicated inputs)**|||
|256 BBG(14 × 14 mm, 0.8 mm)<br>~~a~~|0/205(159+40+6)<br>~~DO~~|—<br>~~DO~~|—<br>~~DO~~|
|400 BBG(17 × 17 mm, 0.8 mm)<br>~~a~~<br>~~Ge~~|0/305(251+48+6)<br>~~DO~~<br>~~Ge~~|2/297(159+132+6)<br>~~DO~~<br>~~Ge~~|2/297(159+132+6)<br>~~DO~~<br>~~Ge~~|



**Notes** : 

1. Logic Cells = LUTs × 1.2 effectiveness. 

2. In select speed grades. See Ordering Information. 

© 2021-2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02102-1.7 

16 

**MachXO5-NX Family Data Sheet** 

## **2. Architecture** 

## **2.1. Overview** 

Each MachXO5-NX device contains an array of logic blocks surrounded by Programmable I/O Cells (PIC). Interspersed between the rows of logic blocks are rows of sysMEM Embedded Block RAM (EBR) and rows of sysDSP Digital Signal Processing blocks, as shown in Figure 2.1. For example, The MachXO5-NX-25 device has one row of DSP blocks and contains four rows of sysMEM EBR blocks. In addition, MachXO5-NX-25 device includes one Large SRAM block. The sysMEM EBR blocks are large, dedicated 18 kbit fast memory blocks and have built-in ECC and FIFO support. Each sysMEM block can be configured to a single, pseudo dual or true dual port memory in a variety of depths and widths as RAM or ROM. Each DSP block supports variety of multiplier, adder configurations with one 108-bit or two 54-bit accumulators supported, which are the building blocks for complex signal processing capabilities. Refer to Figure 2.2 and Figure 2.3 for details of MachXO5-55T and MachXO5-100T devices. 

Each PIC block encompasses two PIO (PIO pairs) with their respective sysI/O buffers. The sysI/O buffers of the MachXO5-NX devices are arranged in up to twelve banks allowing the implementation of a wide variety of I/O standards. The Wide Range (WR) I/O banks that are located in the top, left and right sides of the device provide flexible ranges of general purpose I/O configurations up to 3.3 V VCCIOs. The banks located in the bottom side of the device are dedicated to High Performance (HP) interfaces such as LVDS, MIPI, DDR3, LPDDR4 support up to 1.8 V VCCIOs. 

The Programmable Functional Unit (PFU) contains the building blocks for logic, arithmetic, RAM and ROM functions. The PFU block is optimized for flexibility, allowing complex designs to be implemented quickly and efficiently. Logic Blocks are arranged in a two-dimensional array. The registers in PFU and sysI/O blocks in MachXO5-NX devices can be configured to be SET or RESET. After power up and the device is configured, it enters into user mode with these registers SET/RESET according to the configuration setting, allowing the device to enter to a known state for predictable system function. 

MachXO5-NX-55T and MachXO5-NX-100T FPGAs feature one hard PCIe link layer IP block which supports PCIe Gen1, Gen2 with 1 or 2 x1 configuration and internal VREF that supports LPDDR4. 

In addition, MachXO5-NX devices provide various system level hard IP functional and interface blocks such as I[2] C, SGMII/CDR, and ADC blocks. MachXO5-NX devices also provide security features to help secure user designs and deliver more robust reliability features to the user designs by using enhanced frame-based SED/SEC functions. 

Other blocks provided include PLLs, DLLs, and configuration functions. The PLL and DLL blocks are located at the corners of each device. MachXO5-NX devices also include Lattice Memory Mapped Interface (LMMI) which is a Lattice standardized interface for simple read and write operations to support controlling internal IPs. 

MachXO5-NX devices also provide multiple blocks of User Flash Memory (UFM). The UFM interfaces to the core logic and completes the routing through the LMMI interface. The UFM space also provides the User Key storage for customer security functions. The UFM can also be accessed through the SPI and JTAG ports. 

Every device in the family has a JTAG port. This family also provides an on-chip oscillator and soft error detect (SED) capability. The MachXO5-NX devices use 1.0 V as their core voltage. 

**==> picture [482 x 375] intentionally omitted <==**

**----- Start of picture text -----**<br>
MachXO5-NX Family<br>Data Sheet<br>I/O Bank (Bank 0) I/O Bank (Bank 1)<br>PLL<br>Large RAM OSC Non-volatile Configuration & Security On-chip User Flash<br>I/O Bank I/O Bank<br>(Bank 9) (Bank 2)<br>a<br>I/O Bank I/O Bank<br>(Bank 8) (Bank 3)<br>=|<br>I/O Bank<br>I/O Bank (Bank 4)<br>(Bank 7)<br>ADC<br>CDR (2Ch)<br>(2Ch)<br>eben ooe<br>I/O Bank (Bank 6) I/O Bank (Bank 5) PLL<br>**----- End of picture text -----**<br>


**Figure 2.1. Simplified Block Diagram, MachXO5-NX-25 Device (Top Level)** 

© 2021-2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

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**MachXO5-NX Family Data Sheet** 

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PLL SERDES/PCS X2 PCIe LL(X1+X1) Non-Volatile Configuration & Security On-chip User Flash LargeRAM LargeRAM LargeRAM LargeRAM I/O Bank (Bank 0) OSC PLL<br>Large<br>RAM<br>I/O Bank I/O Bank<br>(Bank 7) (Bank 1)<br>Large<br>RAM<br>I/O Bank<br>(Bank 6) Large I/O Bank<br>RAM (Bank 2)<br>ADC<br>(2Ch)<br>CDR<br>(2Ch)<br>PLL I/O Bank (Bank 5) I/O Bank (Bank 4) I/O Bank (Bank 3) PLL<br>**----- End of picture text -----**<br>


**Figure 2.2. Simplified Block Diagram, MachXO5-NX-55T Device (Top Level)** 

© 2021-2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

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**MachXO5-NX Family Data Sheet** 

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**----- Start of picture text -----**<br>
PLL SERDES/PCS X2 PCIe LL(X1+X1) Non-Volatile Configuration & Security On-chip User Flash LargeRAM LargeRAM LargeRAM LargeRAM I/O Bank (Bank 0) OSC PLL<br>Large<br>RAM<br>I/O Bank I/O Bank<br>(Bank 7) (Bank 1)<br>Large<br>RAM<br>I/O Bank<br>(Bank 6) Large I/O Bank<br>RAM (Bank 2)<br>ADC<br>(2Ch)<br>CDR<br>(2Ch)<br>PLL I/O Bank (Bank 5) I/O Bank (Bank 4) I/O Bank (Bank 3) PLL<br>**----- End of picture text -----**<br>


**Figure 2.3. Simplified Block Diagram, MachXO5-NX-100T Device (Top Level)** 

## **2.2. PFU Blocks** 

The core of the MachXO5-NX device consists of PFU blocks. Each PFU block consists of four interconnected slices numbered 0-3, as shown in Figure 2.4. Each slice contains two LUTs. All the interconnections to and from PFU blocks are from routing. 

The PFU block can be used in Distributed RAM or ROM function, or used to perform Logic, Arithmetic, or ROM functions. Table 2.1 shows the functions each slice can perform in either mode. 

© 2021-2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

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**MachXO5-NX Family Data Sheet** 

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**----- Start of picture text -----**<br>
From<br>Routing<br>SJ<br>LUT4 & LUT4 & LUT4 & LUT4 & LUT4 & LUT4 & LUT4 & LUT4 &<br>CARRY CARRY CARRY CARRY CARRY CARRY CARRY CARRY<br>p e ns e tt ry re oe a<br>Slice 0 Slice 1 Slice 2 Slice 3<br>D D D D D D D D<br>FF FF FF FF FF FF FF FF<br>EEL EL EL<br>To<br>Routing<br>ae<br>**----- End of picture text -----**<br>


**Figure 2.4. PFU Diagram** 

## **2.2.1. Slice** 

Each slice contains two LUT4s feeding two registers. In Distributed SRAM mode, Slice 0 and Slice 1 are configured as distributed memory, Slice 2 is not available as it is used to support Slice 0 and Slice 1, while Slice 3 is available as Logic or ROM. Table 2.1 shows the capability of the slices along with the operation modes they enable. In addition, each Slice contains logic that allows the LUTs to be combined to perform a LUT5 function. There is control logic to perform set/reset functions (programmable as synchronous/ asynchronous), clock select, chip-select, and wider RAM/ROM functions. 

**Table 2.1. Resources and Modes Available per Slice** 

|**Slice**|**PFU(Used in Distributed SRAM)**|**PFU(Used in Distributed SRAM)**|**PFU(Not used as Distributed SRAM)**|**PFU(Not used as Distributed SRAM)**|
|---|---|---|---|---|
||**Resources**|**Modes**|**Resources**|**Modes**|
|Slice 0|2 LUT4s and 2 Registers|RAM|2 LUT4s and 2 Registers|Logic, Ripple, ROM|
|Slice 1|2 LUT4s and 2 Registers|RAM|2 LUT4s and 2 Registers|Logic, Ripple, ROM|
|Slice 2|2 LUT4s and 2 Registers|RAM|2 LUT4s and 2 Registers|Logic, Ripple, ROM|
|Slice 3|2 LUT4s and 2 Registers|Logic, Ripple, ROM|2 LUT4s and 2 Registers|Logic, Ripple, ROM|



Figure 2.5 shows an overview of the internal logic of the slice. The registers in the slice can be configured for positive/negative edge trigger. 

Each slice has 17 input signals: 16 signals from routing and one from the carry-chain (from the adjacent slice or PFU). Three of them are used for FF control and shared between two slices (0/1 or 2/3). There are five outputs: four to routing and one to carry-chain (to the adjacent PFU). Table 2.2 and Figure 2.5 list the signals associated with all the slices. Figure 2.6 shows the slice signals that support one LUT5 or two LUT5 functions. F0 can be configured to have one LUT4 or LUT5 output while F1 is for a LUT4 output. 

© 2021-2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

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**MachXO5-NX Family Data Sheet** 

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**----- Start of picture text -----**<br>
LUT5<br>and<br>Carry<br>**----- End of picture text -----**<br>


**Figure 2.5. Slice Diagram** 

© 2021-2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

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**MachXO5-NX Family Data Sheet** 

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**----- Start of picture text -----**<br>
A1<br>F1<br>B1<br>LUT4<br>C1<br>D1<br>1<br>F0<br>0<br>SEL<br>**----- End of picture text -----**<br>


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**----- Start of picture text -----**<br>
A0<br>B0<br>LUT4<br>C0<br>D0<br>Note : In RAM mode, LUT4s use the following signals:<br>QWD0/1<br>QWDN0/1<br>QWAS00~03, QWAS10~13<br>**----- End of picture text -----**<br>


**Figure 2.6. Slice Configuration for LUT4 and LUT5** 

**Table 2.2. Slice Signal Descriptions** 

|**Function**<br>~~fe~~<br>~~eG~~|**Type **<br>~~fe~~<br>~~eG~~|**Signal Names**<br>~~fe~~<br>~~eG~~|**Description**<br>~~Ge~~<br>~~Ge~~|
|---|---|---|---|
|Input<br>~~fe~~<br>~~eG~~<br>~~Ge~~|Data signal<br>~~fe~~<br>~~eG~~<br>~~Ge~~|A0, B0, C0, D0<br>~~fe ~~<br>~~eG~~<br>~~Ge~~|Inputs to LUT4<br> ~~Ge~~<br>~~Ge~~<br>~~Ge~~|
|Input<br>~~eG~~<br>~~Ge~~|Data signal<br>~~eG~~<br>~~Ge~~|A1, B1, C1, D1<br>~~eG ~~<br>~~Ge~~|Inputs to LUT4<br> ~~Ge~~<br>~~Ge~~|
|Input<br>~~Ge~~<br>~~Ge~~|Data signal<br>~~Ge~~<br>~~Ge~~|M0, M1<br>~~Ge ~~<br>~~Ge~~|Direct input to FF from fabric<br> ~~Ge~~<br>~~Ge~~|
|Input<br>~~Ge~~<br>~~OG~~|Control signal<br>~~Ge~~<br>~~OG~~|SEL<br>~~Ge~~<br>~~OG~~|LUT5 mux control input<br>~~Ge~~<br>~~OG~~|
|Input<br>~~OG~~<br>~~OG~~<br>~~Ce~~|Data signal<br>~~OG~~<br>~~OG~~<br>~~Ce~~|DI0, DI1<br>~~OG~~<br>~~OG~~<br>~~Ce~~|Inputs to FF from LUT4 F0/F1 outputs<br>~~OG~~<br>~~OG~~<br>~~Ge~~|
|Input<br>~~OG~~<br>~~Ce~~<br>~~Ge~~|Control signal<br>~~OG~~<br>~~Ce~~<br>~~Ge~~|CE<br>~~OG~~<br>~~Ce~~<br>~~Ge~~|Clock Enable<br>~~OG~~<br>~~Ge~~<br>~~Ge~~|
|Input<br>~~Ce~~<br>~~Ge~~|Control signal<br>~~Ce~~<br>~~Ge~~|LSR<br>~~Ce ~~<br>~~Ge~~|Local Set/Reset<br> ~~Ge~~<br>~~Ge~~|
|Input<br>~~Ge~~<br>~~Ge~~|Control signal<br>~~Ge~~<br>~~Ge~~|CLKIN<br>~~Ge ~~<br>~~Ge~~|System Clock<br> ~~Ge~~<br>~~Ge~~|
|Input<br>~~Ge~~<br>~~OG~~|Inter-PFU signal<br>~~Ge~~<br>~~OG~~|FCI<br>~~Ge~~<br>~~OG~~|Fast Carry-in1<br>~~Ge~~<br>~~OG~~|
|Output<br>~~OG~~<br>~~OG~~<br>~~Ce~~|Data signals<br>~~OG~~<br>~~OG~~<br>~~Ce~~|F0<br>~~OG~~<br>~~OG~~<br>~~Ce~~|LUT4/LUT5 output signal<br>~~OG~~<br>~~OG~~<br>~~Ge~~|
|Output<br>~~OG~~<br>~~Ce~~|Data signals<br>~~OG~~<br>~~Ce~~|F1<br>~~OG~~<br>~~Ce~~|LUT4 output signal<br>~~OG~~<br>~~Ge~~|
|Output<br>~~Ce~~<br>~~GG~~|Data signals<br>~~Ce~~<br>~~GG~~|Q0, Q1<br>~~Ce ~~<br>~~GG~~|Register outputs<br> ~~Ge~~<br>~~GG~~|
|Output<br>~~a~~|Inter-PFU signal|FCO|Fast carrychain output1|



1. See Figure 2.5 for connection details. 

© 2021-2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

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**MachXO5-NX Family Data Sheet** 

## **2.2.2. Modes of Operation** 

Slices 0-2 have up to four potential modes of operation: Logic, Ripple, RAM and ROM. Slice 3 can be used in Logic, Ripple, or ROM modes, but not needed for RAM mode. 

## **Logic Mode** 

In this mode, the LUTs in each slice are configured as 4-input combinatorial lookup tables. A LUT4 can have 16 possible input combinations. Any four input logic functions can be generated by programming this lookup table. Since there are two LUT4s per slice, a LUT5 can be constructed within one slice. 

## **Ripple Mode** 

Ripple mode supports the efficient implementation of small arithmetic functions. In ripple mode, the following functions can be implemented by each slice: 

- Addition 2-bit 

- Subtraction 2-bit 

- Add/Subtract 2-bit using dynamic control 

- Up counter 2-bit 

- Down counter 2-bit 

- Up/Down counter with asynchronous clear 2-bit using dynamic control 

- Up/Down counter with preload (sync) 2-bit using dynamic control 

- Comparator functions of A and B inputs 2-bit 

   - A greater-than-or-equal-to B 

   - A not-equal-to B 

   - A less-than-or-equal-to B 

- Up/Down counter with A greater-than-or-equal-to B comparator 2-bit using dynamic control 

- Up/Down counter with A less-than-or-equal-to B comparator 2-bit using dynamic control 

- Multiplier support Ai*Bj+1 + Ai+1*Bj in one logic cell with 2 logic cells per slice 

- Serial divider 2-bit mantissa, shift 1bit/cycle 

- Serial multiplier 2-bit, shift 1bit/cycle or 2bit/cycle 

Ripple Mode includes an optional configuration that performs arithmetic using fast carry chain methods. In this configuration (also referred to as CCU2 mode), two additional signals, Carry Generate and Carry Propagate, are generated on a per slice basis to allow fast arithmetic functions to be constructed by concatenating Slices. 

## **RAM Mode** 

In this mode, a 16 × 4-bit distributed single or pseudo dual port RAM can be constructed in one PFU using each LUT block in Slice 0 and Slice 1 as a 16 × 2-bit memory in each slice. Slice 2 is used to provide memory address and control signals. MachXO5-NX devices support distributed memory initialization. 

The Lattice design tools support the creation of a variety of different size memories. Where appropriate, the software constructs these using distributed memory primitives that represent the capabilities of the PFU. Table 2.3 lists the number of slices required to implement different distributed RAM primitives. For more information about using RAM in MachXO5-NX devices, refer to Memory User Guide for Nexus Platform (FPGA-TN-02094). 

## **Table 2.3. Number of Slices Required to Implement Distributed RAM** 

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**----- Start of picture text -----**<br>
||||
|---|---|---|
|SPR 16 × 4|PDPR 16 × 4|
|Number of slices|3|3|

**----- End of picture text -----**<br>


**Note** : SPR = Single Port RAM, PDPR = Pseudo Dual Port RAM 

© 2021-2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

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**MachXO5-NX Family Data Sheet** 

## **ROM Mode** 

ROM mode uses the LUT logic; hence, Slice 0 through Slice 3 can be used in ROM mode. Preloading is accomplished through the programming interface during PFU configuration. 

For more information, refer to Memory User Guide for Nexus Platform (FPGA-TN-02094). 

## **2.3. Routing** 

There are many resources provided in the MachXO5-NX devices to route signals individually or as busses with related control signals. The routing resources consist of switching circuitry, buffers and metal interconnect (routing) segments. 

The MachXO5-NX family has an enhanced routing architecture that produces a compact design. The Lattice Radiant software tool suites take the output of the synthesis tool and places and routes the design. 

## **2.4. Clocking Structure** 

The MachXO5-NX clocking structure consists of: 

- clock synthesis blocks, sysCLOCK PLL; 

- balanced clock tree networks, PCLK and ECLK; and 

- efficient clock logic modules, Clock Dividers (PCLKDIV and ECLKDIV) and Dynamic Clock Select (DCS), Dynamic Clock Control (DCC), and DLL. 

Each of these functions is described as follow. 

## **2.4.1. Global PLL** 

The Global PLLs (GPLL) provide the ability to synthesize clock frequencies. The devices in the MachXO5-NX family support two full-featured General Purpose GPLLs. The Global PLLs provide the ability to synthesize clock frequencies. 

The architecture of the GPLL is shown in Figure 2.7. A description of the GPLL functionality follows. 

REFCLK is the reference frequency input to the PLL and its source can come from external CLK inputs or from internal routing. The CLKI input feeds into the input Clock Divider block. 

CLKFB is the feedback signal to the GPLL which can come from internal feedback path or routing. The feedback divider is used to multiply the reference frequency and thus synthesize a higher or lower frequency clock output. 

The PLL has six clock outputs CLKOP, CLKOS, CLKOS2, CLKOS3, CLKOS4, and CLKOS5. Each output has its own output divider, thus allowing the GPLL to generate different frequencies for each output. The output dividers can have a value from 1 to 128. Each GPLL output can be used to drive the primary clock or edge clock networks. 

The setup and hold times of the device can be improved by programming a phase shift into the output clocks which advances or delays the output clock with reference to the un-shifted output clock. This phase shift can either be programmed during configuration or be adjusted dynamically using the DIRSEL, DIR, DYNROTATE, and LOADREG ports. 

The LOCK signal is asserted when the GPLL determines it has achieved lock and deasserted if a loss of lock is detected. 

© 2021-2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

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**MachXO5-NX Family Data Sheet** 

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**----- Start of picture text -----**<br>
(To bypass muxes)<br>**----- End of picture text -----**<br>


**Figure 2.7. General Purpose PLL Diagram** 

For more details on the PLL, you can refer to the sysCLOCK PLL Design and User Guide for Nexus Platform (FPGA-TN-02095). 

## **2.4.2. Clock Distribution Network** 

There are two main clock distribution networks for any member of the MachXO5-NX product family, namely Primary Clock (PCLK) and Edge Clock (ECLK). These clock networks can be driven from many different sources, such as Clock Pins, PLL outputs, DLLDEL outputs, Clock divider outputs, and user logic. There are clock divider blocks (ECLKDIV and PCLKDIV) to provide a slower clock from these clock sources. 

MachXO5-NX supports glitchless Dynamic Clock Control (DCC) for the PCLK Clock to save dynamic power. There are also Dynamic Clock Selection logic to allow glitchless selection between two clocks for the PCLK network (DCS). 

Overview of Clocking Network is shown in Figure 2.8 and in Figure 2.9 for MachXO5-NX devices. 

© 2021-2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

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**MachXO5-NX Family Data Sheet** 

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**----- Start of picture text -----**<br>
PLL BANK 0 PCLK BANK 1 PCLK OSC<br>: : : :<br>TMID<br>a<br>4 Ld<br>2 |<br>® 16 DCC<br>a .<br>Primary 16 Primary Sources Primary<br>Clocks 16 Fabrici Fabricic 16 Clocks<br>x 3 12 12 Primary Sources 12 Primary Sources 12<br>og= |N T] 12 DCC MUXves| | MUXacs Dus ‘)<br>Zz<br>&<br>Ent Enti<br>18 Primary Sources<br>x3 [ 18 DCC<br>n IN<br>BMID<br>Z [| *<br>BANK 6 PCLK ECLK BANK 5 PCLK ECLK PLL<br>BANK 2 PCLK<br>RMID<br>BANK 3 PCLK<br>BANK 4 PCLK<br>LMID<br>**----- End of picture text -----**<br>


**Figure 2.8. Clocking for MachXO5-NX-25 Devices** 

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**----- Start of picture text -----**<br>
PLL SerDes BANK 0 PCLK OSC PLL<br>Lt [___ 7 —_ —_<br>TMID<br>[| 16 DCC<br>. 16 Primary Sources oe<br>Primary Primary<br>i ic 16<br>12 12 Primary Sources 12 Primary Sources 12<br>12 DCC 12 DCC<br>MUX | MUX<br>18 16<br>. Fabric Fabric .<br>Primary 18 Primary Sources Primary<br>Clocks Clocks<br>[| 18 DCC a<br>BMID<br>PLL BANK 5 PCLK ECLK BANK 4 PCLK ECLK BANK 3 PCLK ECLK PLL<br>: 8 * ‘ * * * ‘ :<br>BANK 1 PCLK<br>RMID<br>BANK 2 PCLK<br>LMID<br>**----- End of picture text -----**<br>


**Figure 2.9. Clocking for MachXO5-NX-55T/MachXO5-NX-100T Devices** 

© 2021-2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

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**MachXO5-NX Family Data Sheet** 

## **2.4.3. Primary Clocks** 

The MachXO5-NX device family provides low-skew, high fan-out clock distribution to all synchronous elements in the FPGA fabric through the Primary Clock Network. The MachXO5-NX PCLK clock network is a balanced clock structure which is designed to minimize the clock skew among all the final destination of the IPs in the FPGA core that needs a clock source. 

The primary clock network is divided into two or four clock domains depending on the device density. Each of these domains has 16 clocks that can be distributed to the fabric in the domain. 

The Lattice Radiant software can automatically route each clock to one of the domains up to a maximum of 16 clocks per domain. You can change how the clocks are routed by specifying a preference in the Lattice Radiant software to locate the clock to a specific domain. MachXO5-NX device provides you with a maximum of 64 unique clock input sources that can be routed to the primary Clock network. 

Primary clock sources are: 

- Dedicated clock input pins 

- PLL outputs 

- PCLKDIV, ECLKDIV outputs 

- Internal FPGA fabric entries (with minimum general routing) 

- SGMII-CDR clocks 

- OSC clock 

These sources are routed to each of four clock switches called a Mid Mux (LMID, RMID, TMID, BMID). The outputs of the Mid MUX are routed to the center of the FPGA where additional clock switches (DSC_CMUX) are used to route the primary clock sources to primary clock distribution to the MachXO5-NX fabric. These routing muxes are shown in Figure 2.8 and Figure 2.9. There are potentially 64 unique clock domains that can be used in the largest MachXO5-NX device. For more information about the primary clock tree and connections, refer to sysCLOCK PLL Design and User Guide for Nexus Platform (FPGA-TN-02095). 

## **2.4.4. Edge Clock** 

MachXO5-NX devices have a number of high-speed edge clocks that are intended for use with the PIO in the implementation of high-speed interfaces. There are four (4) ECLK networks per bank I/O on the Bottom side of the devices. For power management, the Edge clock network is powered by a separate power domain (to reduce power noise injection from the core and reduce overall noise induced jitter) while controlled by the same logic that gates the FPGA core and PCLK domains. 

Each Edge Clock can be sourced from the following: 

- Dedicated PIO Clock input pins (PCLK) 

- DLLDEL output (PIO Clock delayed by 90°) 

- PLL outputs (CLKOP, CLKOS, CLKOS2, CLKOS3, CLKOS4, and CLKOS5) 

- Internal Nodes 

Figure 2.10 illustrates the various ECLK sources. Bank 5 is shown in the example. Other bottom side banks are similar. 

© 2021-2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

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**MachXO5-NX Family Data Sheet** 

**==> picture [429 x 165] intentionally omitted <==**

**----- Start of picture text -----**<br>
From Banks 6<br>Bank 5 PCLK Pin (even) 2 ECLKSYNC<br>DLLDEL<br>From Fabric<br>Bank 5 ECLK Tree<br>ECLKSYNC<br>Bottom   6<br>Right GPLL ECLKDIV BMID<br>2<br>Bank 5 PCLK Pin (odd)<br>To Banks 6 Muxes<br>**----- End of picture text -----**<br>


**Figure 2.10. Edge Clock Sources per Bank** 

The edge clocks have low injection delay and low skew. They are typically used for DDR Memory or Generic DDR interfaces. For detailed information on Edge Clock connections, refer to sysCLOCK PLL Design and User Guide for Nexus Platform (FPGA-TN-02095). 

## **2.4.5. Clock Dividers** 

MachXO5-NX devices have two distinct types of clock divider, Primary and Edge.  There are from one (1) to two (2) Primary Clock Divider (PCLKDIV) and which are located in the DCS_CMUX block(s) at the center of the device. There are up to twelve (12) ECLKDIV dividers per device, locate near the bottom high-speed I/O banks. 

The PCLKDIV supports ÷2, ÷4, ÷8, ÷16, ÷32, ÷64, ÷128, and ÷1 (bypass) operation. The PCLKDIV is fed from a DCSMUX within the DCS_CMUX block. The clock divider output drives one input of the DCS Dynamic Clock Select within the DSC_CMUX block. The Reset (RST) control signal is asynchronously and forces all outputs to low. The divider output starts at next cycle after the reset is synchronously released. The PCLKDIV is shown in Figure 2.11. 

The ECLKDIV is intended to generate a slower-speed system clock from a high-speed edge clock. The block operates in a ÷2, ÷3.5, ÷4, or ÷5 mode and maintains a known phase relationship between the divided down clock and the high-speed clock based on the release of its reset signal. The ECLKDIV can be fed from selected PLL outputs, external primary clock pins (with or without DLLDEL Delay) or from routing. The clock divider outputs feed into the Bottom Mid-mux (BMID). The Reset (RST) control signal is asynchronous and forces all outputs to low. The divider output starts at next cycle after the reset is synchronously released. 

The ECLKDIV block is shown in Figure 2.10. For further information on clock dividers, refer to sysCLOCK PLL Design and User Guide for Nexus Platform (FPGA-TN-02095). 

## **2.4.6. Clock Center Multiplexor Blocks** 

All clock sources are selected and combined for primary clock routing through the Dynamic Clock Selector Center Multiplexor logic (DCS_CMUX). There are one (1) DCS_CMUX blocks per device. For 25k device, each DCS_CMUX block contains two (2) DCSMUX blocks, one (1) PCLKDIV, one (1) DCS block, and two (2) CMUX blocks. For 50T/100T device, each DCS_CMUX block contains four (4) DCSMUX blocks, two (2) PCLKDIV, two (2) DCS block, and four (4) CMUX blocks. See Figure 2.11 and Figure 2.12 for representative DCS_CMUX block diagrams. 

The heart of the DCS_CMUX is the Center Multiplexor (CMUX) block, inputs up to 64 feed clock sources [mid-muxes (RMID, LMID, TMIC, BMID) and DCC] and to drive up to 16 primary clock trunk lines. 

© 2021-2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

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Up to two (2) clock inputs to the DCS_CMUX can be routed through a Dynamic Clock Select block, and then routed to the CMUX. One (1) input to the DCS can be optionally divided by the Primary Clock Divider (PCLKDIV). For more information about the DCS_CMUX, refer to sysCLOCK PLL Design and User Guide for Nexus Platform (FPGA-TN-02095). 

**==> picture [408 x 251] intentionally omitted <==**

**----- Start of picture text -----**<br>
16 16<br>16x (partial 16x (partial<br>(16/64):1) (16/64):1)<br>CMUX CMUX<br>16 16<br>DCS_CMUX dcs2cmux0<br>DCS<br>62<br>dcs1 dcs0<br>PCLKDIV<br>DCSMUX DCSMUX<br>(62:1) (62:1)<br>62 62<br>62 62<br>62<br>**----- End of picture text -----**<br>


**Figure 2.11. DCS_CMUX Diagram for MachXO5-NX-25 Devices** 

**==> picture [448 x 185] intentionally omitted <==**

**----- Start of picture text -----**<br>
16 16 16 16<br>16x (partial 16x (partial 16x (partial 16x (partial<br>(16/64):1) (16/64):1) (16/64):1) (16/64):1)<br>CMUX CMUX CMUX CMUX<br>16 16 16 16<br>DCS_CMUX dcs2cmux0 dcs2cmux1<br>DCS DCS<br>62 dcs1 dcs0 dcs3 dcs2<br>=<br>PCLKDIV PCLKDIV<br>DCSMUX(62:1) DCSMUX(62:1) DCSMUX(62:1) DCSMUX(62:1)<br>62 62 62 62<br>62 62 62 62<br>[ sas aes<br>62<br>**----- End of picture text -----**<br>


**Figure 2.12. DCS_CMUX Diagram for MachXO5-NX-55T/MachXO5-NX-100T Devices** 

© 2021-2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02102-1.7 

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**MachXO5-NX Family Data Sheet** 

## **2.4.7. Dynamic Clock Select** 

The Dynamic Clock Select (DCS) is a smart multiplexer function available in the primary clock routing. It switches between two independent input clock sources. Depending on the operation modes, it switches between two (2) independent input clock sources either with or without any glitches. This is achieved regardless of when the select signal is toggled. Both input clocks must be running to achieve functioning glitchless DCS output clock, but running clocks are not required when used as non-glitchless normal clock multiplexer. 

There are one (1) or two (2) DCS blocks per device that feed all clock domains. The DCS blocks are located in the DCS_MUX block. The inputs to the DCS blocks come from MIDMUX outputs and user logic clocks via DCC elements. The DCS elements are located at the center of the PLC array core. The output of the DCS is connected to the inputs of Primary Clock Center MUXs (CMUX). 

Figure 2.13 shows the timing waveforms of the default DCS operating mode. The DCS block can be programmed to other modes. For more information about the DCS, refer to sysCLOCK PLL Design and User Guide for Nexus Platform (FPGA-TN-02095). 

**==> picture [419 x 185] intentionally omitted <==**

**----- Start of picture text -----**<br>
CLK0<br>clk0<br>pos<br>CLK1<br>JELLI be<br>clk1 clk1<br>pos neg<br>SEL<br>clk0<br>neg<br>DCSOUT<br>**----- End of picture text -----**<br>


**Figure 2.13. DCS Waveforms** 

## **2.4.8. Dynamic Clock Control** 

The Dynamic Clock Control (DCC), Domain Clock enable/disable feature allows internal logic control of the domain primary clock network. When a clock network is disabled, the clock signal is static and not toggle. All the logic fed by that clock does not toggle, reducing the overall power consumption of the device. The disable function is glitchless, and does not increase the clock latency to the primary clock network. 

Four additional DCC elements control the clock inputs from the MachXO5-NX domain logic to the Center MUX elements (DSC_CMUX). 

This DCC controls the clock sources from the Primary CLOCK MIDMUX before they are fed to the Primary Center MUXs that drive the domain clock network. For more information about the DCC, refer to sysCLOCK PLL Design and User Guide for Nexus Platform (FPGA-TN-02095). 

© 2021-2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

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**MachXO5-NX Family Data Sheet** 

## **2.4.9. DDRDLL** 

The MachXO5-NX device has two identical DDRDLL blocks located in the lower left and lower right corners of the device.  Each DDRDLL (master DLL block) can generate a phase shift code representing the amount of delay in a delay block that corresponding to 90-degree phase of the reference clock input, and provide this code to every individual DQS block and DLLDEL slave delay element. The reference clock can be either from PLL, or input pin. This code is used in the DQSBUF block that controls a set of DQS pin groups to interface with DDR memory (slave DLL). The DQSBUF uses this code to control the DQS input of the DDR memory to 90-degree shift to clock DQs at the center of the data eye for DDR memory interface. 

The code is also sent to another slave DLL, DLLDEL, which takes a primary clock input and generates a 90degree shift clock output to drive the clocking structure. This is useful to interface edge-aligned Generic DDR, where 90-degree clocking needs to be created. Not all primary clock inputs have associated DLLDEL control. Figure 2.14 shows DDRDLL connectivity to a DLLDEL block (connectivity to DQSBUF blocks is similar). 

**==> picture [481 x 511] intentionally omitted <==**

**----- Start of picture text -----**<br>
To both BMID and<br>ECLKINMUX<br>PCLK Input<br>+<br>- DLLDEL<br>a<br>9 Right DDRDLL<br>9<br>Left DDRDLL<br>Fee<br>=<br>Figure 2.14. DLLDEL Functional Diagram<br>Each DDRDLL can generate delay code based on the reference clock frequency. The slave DLL (DQSBUF and<br>DLLDEL) uses the code to delay the signal to create the phase shifted signal used either for DDR memory or<br>for creating 90-degree shift clock. Figure 2.15 shows the DDRDLL and the slave DLLs on the top-level view.<br>Left  Right<br>DDRDLL DDRDLL<br>Digital Delay Code (L) Digital Delay Code (R)<br>Refclk Sel Refclk Sel<br>DLLDEL DQS0 DQS1 DLLDEL DQS0 DQS1<br>az: BANK6 ECLK BANK5 ECLK<br>Figure 2.15. DDRDLL Architecture for MachXO5-NX-25 Devices<br>©  2021-2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.<br>All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.<br>code1 code2<br>**----- End of picture text -----**<br>


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**MachXO5-NX Family Data Sheet** 

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**----- Start of picture text -----**<br>
Left  Right<br>DDRDLL DDRDLL<br>=<br>Digital Delay Code (L) Digital Delay Code (R)<br>Refclk Sel Refclk Sel<br>DLLDEL DQS0 DQS1 ... DLLDEL DQS0 DQS1 ... DLLDEL DQS0 DQS1 ...<br>BANK5 ECLK BANK4 ECLK BANK3 ECLK<br>**----- End of picture text -----**<br>


**Figure 2.16. DDRDLL Architecture for MachXO5-NX-55T/MachXO5-NX-100T Devices** 

## **2.5. SGMII TX/RX** 

The MachXO5-NX device utilizes different components/resources for the transmit and receive paths of SGMII. For the SGMII transmit path, Generic DDR I/O with X5 gearing are used. For more information, refer to the GDDRX5_TX.ECLK.Aligned interface section in the MachXO5-NX High-Speed I/O Interface (FPGA-TN-02286). 

For the SGMII receive path, one of the two available hardened CDR (Clock and Data Recovery) Components can be used. There are three main blocks in each CDR: the CDR, deserializer, and FIFO. Each CDR features two loops. The first loop is locked to the reference clock. Once locked, the loop switches to the data path loop where the CDR tracks the data signals to generate the correcting signals that needed to achieve and maintain phase lock with the data. The data is then passed through a deserializer which deserializes the data to 10-bit parallel data. The 10-bit parallel data is then sent to the FIFO bridge, which allows the CDR to interface with the rest of the FPGA. 

Figure 2.17 shows a block diagram of the SGMII CDR IP. 

The two hardened blocks are located at the bottom left of the chip and uses the high speed I/O Bank 5 for the differential pair input. It is recommended that the reference clock should be entered through a GPIO that has connection to the PLL on the lower left corner as well. 

For more information on how to implement the hardened CDR for your SGMII solution, refer to the SGMII and Gb Ethernet PCS IP Core (FPGA-IPUG-02077). 

© 2021-2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

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**MachXO5-NX Family Data Sheet** 

**==> picture [428 x 265] intentionally omitted <==**

**----- Start of picture text -----**<br>
SGMII CDR IP<br>lmmi_dk<br>lmmi_request<br>lmmi_wrdn<br>lmmi_rdata[7:0]<br>lmmi_offset[3:0]<br>= : lmmi_rdata_valid<br>lmmi_wdata[7:0]<br>lmmi_ready<br>lmmi_reset<br>ip_ready<br>sgmii_cdr_icnst<1:0><br>rxd<9:0> sgmii_rxd<9:0><br>sgmii_in rxd_des<br>DUAL_LOOP<br>DESERIALIZER FIFO<br>CDR<br>rclk_des<br>dco_calib_rst<br>dco_facq_rst<br>rrst<br>sgmii_pclk<br>sgmii_refclk(125 MHz)<br>sgmii_rclk<br>**----- End of picture text -----**<br>


**Figure 2.17. SGMII CDR IP** 

## **2.6. sysMEM Memory** 

MachXO5-NX devices contain a number of sysMEM Embedded Block RAM (EBR). The EBR consists of an 18 kb RAM with memory core, dedicated input registers and output registers as well as optional pipeline registers at the outputs. Each EBR includes functionality to support true dual-port, pseudo dual-port, single-port RAM, ROM and built in FIFO. In the MachXO5-NX device, unused EBR blocks is powered down to minimize power consumption. 

## **2.6.1. sysMEM Memory Block** 

The sysMEM block can implement single port, dual port or pseudo dual port memories. Each block can be used in a variety of depths and widths as listed in Table 2.4. FIFO can be implemented using the built-in read and write address counters and programmable full, almost full, empty and almost empty flags. The EBR block facilitates parity checking by supporting an optional parity bit for each data byte. EBR blocks provide byte-enable support for configurations with 18-bit and 36-bit data widths. For more information, refer to Memory User Guide for Nexus Platform (FPGA-TN-02094). 

EBR also provides a build in ECC engine in select speed grades (see Ordering Information). The ECC engine supports a write data width of 32 bits and it can be cascaded for larger data widths such as ×64. The ECC parity generator creates and stores parity data for each 32-bit word written. When a read operation is performed, it compares the data with its associated parity data and report back if any Single Event Upset (SEU) event has disturbed the data. Any single bit data disturb is automatically corrected at the data output. In addition, two dedicated error flags indicate if a single-bit or two-bit error has occurred. 

© 2021-2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

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**MachXO5-NX Family Data Sheet** 

## **Table 2.4. sysMEM Block Configurations** 

|**Memory Mode**|**Configurations**|
|---|---|
|Single Port|16,384 × 1|
||8,192 × 2|
||4,096 × 4|
||2,048 × 9|
||1,024 × 18|
||512 × 36|
|True Dual Port|16,384 × 1|
||8,192 × 2|
||4,096 × 4|
||2,048 × 9|
||1,024 × 18|
|Pseudo Dual Port|16,384 × 1|
||8,192 × 2|
||4,096 × 4|
||2,048 × 9|
||1,024 × 18|
||512 × 36|



## **2.6.2. Bus Size Matching** 

All of the multi-port memory modes support different widths on each of the ports (except ECC mode, which only supports a write data width of 32 bits). The RAM bits are mapped LSB word 0 to MSB word 0, LSB word 1 to MSB word 1, and so on. Although the word size and number of words for each port varies, this mapping scheme applies to each port. 

## **2.6.3. RAM Initialization and ROM Operation** 

If desired, the contents of the RAM can be pre-loaded during device configuration. By preloading the RAM block during the chip configuration cycle and disabling the write controls, the sysMEM block can also be utilized as a ROM. 

## **2.6.4. Memory Cascading** 

Larger and deeper blocks of RAM can be created using EBR sysMEM Blocks. Typically, the Lattice design tools cascade memory transparently, based on specific design inputs. 

## **2.6.5. Single, Dual and Pseudo-Dual Port Modes** 

In all the sysMEM RAM modes, the input data and address for the ports are registered at the input of the memory array. The output data of the memory is optionally registered at the output. 

## **2.6.6. Memory Output Reset** 

The EBR utilizes latches at the A and B output ports. These latches can be reset asynchronously or synchronously. RSTA and RSTB are local signals, which reset the output latches associated with Port A and Port B, respectively. The Global Reset (GSRN) signal can reset both ports. The output data latches and associated resets for both ports are as shown in Figure 2.18. The optional Pipeline Registers at the outputs of both ports are also reset in the same way. 

© 2021-2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

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**MachXO5-NX Family Data Sheet** 

**==> picture [351 x 220] intentionally omitted <==**

**----- Start of picture text -----**<br>
Memory Core D SET Q Port A[17:0]<br>a LCLR<br>Output Data<br> Latches<br>D SET Q Port B[17:0]<br>LCLR<br>a<br>RSTA<br>ee<br>RSTB<br>=> ><br>GSRN<br>=C ar<br>Programmable Disable<br>**----- End of picture text -----**<br>


**Figure 2.18. Memory Core Reset** 

For further information on the sysMEM EBR block, see the list of technical documentation in Supplemental Information section. 

## **2.7. Large RAM** 

The MachXO5-NX device includes additional memory resources in the form of Large Random-Access Memory (LRAM) blocks. 

The LRAM is designed to work as Single-Port RAM, Dual-Port RAM, Pseudo Dual-Port RAM, and ROM memories. It is designed to function as additional memory resources for you beyond what is available in the EBR and PFU. 

Each individual Large RAM block contains 0.5 Mb of memory, and has a programmable data width of up to 32 bits. Cascading Large RAM blocks allows data widths up to 64 bits. Additionally, each LRAM can use either Error Correction Coding (ECC) or byte enable. 

## **2.8. sysDSP** 

The MachXO5-NX family provides an enhanced sysDSP architecture, making it ideally suitable for low-cost, high-performance Digital Signal Processing (DSP) applications. Typical functions used in these applications are Finite Impulse Response (FIR) filters, Fast Fourier Transforms (FFT) functions, Correlators, 

Reed-Solomon/Turbo/Convolution encoders and decoders. These complex signal processing functions use similar building blocks, such as multiply-adders and multiply-accumulators. 

## **2.8.1. sysDSP Approach Compared to General DSP** 

Conventional general-purpose DSP chips typically contain one to four (Multiply and Accumulate) MAC units with fixed data-width multipliers; this leads to limited parallelism and limited throughput. Their throughput is increased by higher clock speeds. In the MachXO5-NX device family, there are many DSP blocks that can be used to support different data widths. This allows you to use highly parallel implementations of the DSP functions. You can optimize DSP performance versus area by choosing appropriate levels of parallelism. Figure 2.19 compares the fully serial implementation to the mixed parallel and serial implementation. 

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**MachXO5-NX Family Data Sheet** 

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**----- Start of picture text -----**<br>
Operand  Operand  Operand<br>A A A<br>Operand  Operand  Operand<br>B B B<br>Operand  Operand<br>A B<br>X X X m/k<br>loops<br>Single  M loops Multiplier Multiplier<br>Multiplier X 0 1 1 /: Multiplierk<br>Accumulator H /<br>(k adds) +<br>Function Implemented in General<br>Purpose DSP<br>m/k<br>accumulate<br>Output<br>Function Implemented in<br>MachXO5-NX Devices<br>**----- End of picture text -----**<br>


**Figure 2.19. Comparison of General DSP and MachXO5-NX Approaches** 

## **2.8.2. sysDSP Architecture Features** 

The MachXO5-NX sysDSP Slice has been significantly enhanced to provide functions needed for advanced processing applications. These enhancements provide improved flexibility and resource utilization. 

The MachXO5-NX sysDSP Slice supports many functions that include the following: 

- Symmetry support. The primary target application is wireless. 1D Symmetry is useful for many applications that use FIR filters when their coefficients have symmetry or asymmetry characteristics. The main motivation for using 1D symmetry is cost/size optimization. The expected size reduction is up to 2x. 

   - Odd Mode – Filter with Odd number of taps 

   - Even Mode – Filter with Even number of taps 

   - Two dimensional (2D) Symmetry Mode – Supports 2D filters for mainly video applications 

- Dual-multiplier architecture. Lower accumulator overhead to half and the latency to half compared to single multiplier architecture. 

- Fully cascadable DSP across slices. Support for symmetric, asymmetric and non-symmetric filters. 

- Multiply (36 × 36, two 18 × 36, four 18 × 18 or eight 9 × 9) 

- Multiply Accumulate (supports one 18 × 36 multiplier result accumulation, two 18 × 18 multiplier result accumulation or four 9 × 9 multiplier result accumulation) 

- Two Multiplies feeding one Accumulate per cycle for increased processing with lower latency (two 18 × 18 Multiplies feed into an accumulator that can accumulate up to 54 bits) 

- Pipeline registers 

- 1D Symmetry support. The coefficients of FIR filters have symmetry or negative symmetry characteristics. 

   - Odd Mode – Filter with Odd number of taps 

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**MachXO5-NX Family Data Sheet** 

   - Even Mode – Filter with Even number of taps 

- 2D Symmetry support. The coefficients of 2D FIR filters have symmetry or negative symmetry characteristics. 

   - 3 × 3 and 3 × 5 – Internal DSP Slice support 

   - 5 × 5 and larger size 2D blocks – Semi internal DSP Slice support 

- Flexible saturation and rounding options to satisfy a diverse set of applications situations 

- Flexible cascading DSP blocks 

   - Minimizes fabric use for common DSP functions 

   - Enables implementation of FIR Filter or similar structures using dedicated sysDSP slice resources only 

   - Provides matching pipeline registers 

   - Can be configured to continue cascading from one row of sysDSP slices to another for longer cascade chains 

- RTL Synthesis friendly synchronous reset on all registers, while still supporting asynchronous reset for legacy users 

- Dynamic MUX selection to allow Time Division Multiplexing (TDM) of resources for applications that require processor-like flexibility that enables different functions for each clock cycle 

Figure 2.20 shows the diagram of sysDSP. For most cases, as shown in Figure 2.20, the MachXO5-NX sysDSP is backwards-compatible with the LatticeECP3™ sysDSP block, such that, legacy applications can be targeted to MachXO5-NX sysDSP. 

© 2021-2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

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**MachXO5-NX Family Data Sheet** 

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Input  Input  Input  Input  Input  Input  Input  Input<br>B1 B1 B1 B1 B1 B1 B1 B1<br>Pj} tj) ft J tr} try ht) tt<br>Input Input  Input Input  Input Input  Input Input  Input Input  Input Input  Input Input  Input Input<br>C B2 C B2 C B2 C B2 C B2 C B2 C B2 C B2<br>9 + 9 9 + 9 9 + 9 9 + 9 9 + 9 9 + 9 9 + 9 9 + 9<br>Input  Input  Input  Input  Input  Input  Input  Input<br>REG REG REG REG REG REG REG REG<br>A1 A1 A1 A1 A1 A1 A1 A1<br>Input  Input  Input  Input  Input  Input  Input  Input<br>SaCH} A2  eseeLE) A2 EL A2 LIL A2 eeeLL A2 ee LL A2 LL A2 LD A2<br>9 x 9 9 x 9 9 x 9 9 x 9 9 x 9 9 x 9 9 x 9 9 x 9<br>COOIOISNSISIONES<br>18 X 18 18 X 18 18 X 18 18 X 18<br>rr ee ee eee<br>18 X 36 (CSA) 18 X 36 (CSA)<br>a<br>36 X 36 (CSA)<br>Pd<br>REG 18 REG 18 REG 18 REG 18 REG 18 REG 18 REG 18 REG 18<br>[| tT tT tT tT tT Tt TJ<br>ACC54 ACC54<br>es<br>Output Register Output Register<br>eS<br>**----- End of picture text -----**<br>


## **Note : All Registers inside the DSP Block are Bypassable via Configuration Setting** 

## **Figure 2.20. DSP Functional Block Diagram** 

The MachXO5-NX sysDSP block supports the following basic elements. 

- MULT (Multiply) 

- MAC (Multiply, Accumulate) 

- MULTADDSUB (Multiply, Addition/Subtraction) 

- MULTADDSUBSUM (Multiply, Addition/Subtraction, Summation) 

© 2021-2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02102-1.7 

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**MachXO5-NX Family Data Sheet** 

Table 2.5 shows the capabilities of MachXO5-NX sysDSP block versus the above functions. 

## **Table 2.5. Maximum Number of Elements in a sysDSP block** 

|**Width of Multiply**|**×9**|**×18**|**×36**|
|---|---|---|---|
|MULT|8|4|1|
|MAC|2|2|—|
|MULTADDSUB|2|2|—|
|MULTADDSUBSUM|2|2|—|



Some options are available in the four elements. The input register in all the elements can be directly loaded or can be loaded as a shift register from previous operand registers. By selecting _dynamic operation,_ the following operations are possible: 

- In the Add/Sub option, the Accumulator can be switched between addition and subtraction on every cycle. 

- The loading of operands can switch between parallel and serial operations. 

For further information, refer to sysDSP User Guide for Nexus Platform (FPGA-TN-02096). 

## **2.9. Programmable I/O (PIO)** 

The programmable logic associated with an I/O is called a PIO. The individual PIOs are connected to their respective sysI/O buffers and pads. 

On all the MachXO5-NX devices, two adjacent PIO can be combined to provide a complementary output driver pair. 

## **2.10. Programmable I/O Cell (PIC)** 

The programmable I/O cells (PIC) provide I/O function and necessary gearing logic associated with PIO. MachXO5-NX consists of base PIC and gearing PIC. 

Base PICs contain three blocks: an input register block, output register block, and tri-state register block. These blocks contain registers for operating in a variety of modes along with the necessary clock and selection logic. Base PICs cover the top and left/right bank. Gearing PICs contain gearing logic and edge monitor used for locating the center of data window. Gearing PICs cover the bottom banks to support DDR operation. 

© 2021-2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

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**MachXO5-NX Family Data Sheet** 

**==> picture [287 x 641] intentionally omitted <==**

**----- Start of picture text -----**<br>
PIC<br>PIO A<br>Input<br>Register<br>Block<br>Output and<br>Tristate  Pin<br>Register  A<br>Block<br>Core<br>Logic/ Input and Output<br>Routing Gearbox<br>54<br>PIO B<br>Input<br>Register<br>Block<br>Output and<br>Tristate  Pin<br>Register  B<br>i Block<br>| Li}<br>|<br>Figure 2.21. Group of Two High Performance Programmable I/O Cells<br>PIC<br>PIO A<br>Input<br>Register<br>Block<br>Output and<br>Tristate  Pin<br>Register  A<br>Block<br>: |<br>Core<br>Logic/<br>Routing<br>Ell<br>PIO B<br>Input<br>Register<br>Block<br>Output and<br>T+ Tristate  Pin<br>Ce Register  B<br>— Block<br>Figure 2.22. Wide Range Programmable I/O Cells<br>**----- End of picture text -----**<br>


**Figure 2.21. Group of Two High Performance Programmable I/O Cells** 

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**MachXO5-NX Family Data Sheet** 

## **2.10.1. Input Register Block** 

The input register blocks for the PIO on all edges contain delay elements and registers that can be used to condition high-speed interface signals before they are passed to the device core. In addition, the input register blocks for the PIO on the bottom edges include the built-in FIFO logic to interface to DDR and LPDDR memory. 

The Input register block on the bottom side includes gearing logic and registers to implement IDDRX1, IDDRX2, IDDRX4, IDDRX5 gearing functions. With two PICs sharing the DDR register path, it can also implement IDDRX71 function used for 7:1 LVDS interfaces. It uses three sets of registers – shift, update, and transfer to implement gearing and the clock domain transfer. The first stage registers sample the high-speed input data by the high-speed edge clock on its rising and falling edges. The second stage registers perform data alignment based on the control signals. The third stage pipeline registers pass the data to the device core synchronized to the low-speed system clock. For more information on gearing function, refer to MachXO5-NX High-Speed I/O Interface (FPGA-TN-02286). 

## **Input FIFO** 

The MachXO5-NX PIO has dedicated input FIFO per single-ended pin for input data register for DDR Memory interfaces. The FIFO resides before the gearing logic. It transfers data from DQS domain to continuous ECLK domain. On the Write side of the FIFO, it is clocked by DQS clock, which is the delayed version of the DQS Strobe signal from DDR memory. On the Read side of FIFO, it is clocked by ECLK. ECLK may be any highspeed clock with identical frequency as DQS (the frequency of the memory chip). Each DQS group has one FIFO control block. It distributes FIFO read/write pointer to every PIC in same DQS group. DQS Grouping and DQS Control Block is described in DDR Memory Support section. 

**Table 2.6. Input Block Port Description** 

|**Name**|**Type **|**Description**|
|---|---|---|
|D|Input|High Speed Data Input|
|Q[1:0]/Q[3:0]/Q[6:0]/Q[7:0]/Q[9:0]|Output|Low Speed Data to the device core|
|RST|Input|Reset to the Output Block|
|SCLK|Input|Slow Speed System Clock|
|ECLK|Input|High Speed Edge Clock|
|DQS|Input|Clock from DQS control Block used to clock DDR memorydata|
|ALIGNWD|Input|Data Alignment signal from device core.|



Figure 2.23 shows the input register block for the PIO on the top, left, and right edges. 

**==> picture [448 x 110] intentionally omitted <==**

**----- Start of picture text -----**<br>
INCK<br>D Programmable INFF<br>Delay Cell<br>INFF Q<br>SCLK IDDRX1 Q[1:0]<br>RST<br>**----- End of picture text -----**<br>


**Figure 2.23. Input Register Block for PIO on Top, Left, and Right Sides of the Device** 

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**MachXO5-NX Family Data Sheet** 

Figure 2.24 shows the input register block for the PIO located on the bottom edge. 

**==> picture [396 x 175] intentionally omitted <==**

**----- Start of picture text -----**<br>
IN CK<br>IN FF<br>Programmable<br>D<br>Delay Cell<br>IN FF Q<br>Generic<br>IDDRX1<br>FIFO IDDRX2 Q[1:0]/<br>IDDRX4 Q[3:0]/<br>Delayed DQS ECLK IDDRX5 Q[6:0]*/<br>IDDRX71* Q[7:0]/<br>Q[9:0]<br>Memory<br>ECLK<br>IDDRX2<br>SCLK IDDRX4<br>RST<br>ALIGNWD<br>**----- End of picture text -----**<br>


*For 7:1 LVDS interface only. It is required to use PIO pair pins (PIOA/B or PIOC/D). 

## **Figure 2.24. Input Register Block for PIO on Bottom Side of the Device** 

## **2.10.2. Output Register Block** 

The output register block registers signal from the core of the device before they are passed to the sysI/O buffers. 

MachXO5-NX output data path has output programmable flip flops and output gearing logic. On the bottom side, the output register block can support 1x, 2x, x4, x5, and 7:1 gearing enabling high speed DDR interfaces and DDR memory interfaces. On the top, left, and right sides, the banks support 1x gearing. MachXO5-NX output data path diagram is shown in Figure 2.25. The programmable delay cells are also available in the output data path. 

For detailed description of the output register block modes and usage, you can refer to MachXO5-NX High-Speed I/O Interface (FPGA-TN-02286). 

**==> picture [440 x 112] intentionally omitted <==**

**----- Start of picture text -----**<br>
Programmable<br>D Delay Cell Q<br>OUTFF<br>RST<br>SCLK Generic<br>ODDRX1<br>D[1:0]<br>**----- End of picture text -----**<br>


**Figure 2.25. Output Register Block on Top, Left, and Right Sides** 

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**MachXO5-NX Family Data Sheet** 

**==> picture [433 x 183] intentionally omitted <==**

**----- Start of picture text -----**<br>
Programmable<br>D Delay Cell<br>Q<br>OUTFF<br>Sto)<br>RST Generic<br>SCLK ODD RX1/<br>ODD RX2/<br>ECLK ODD RX4<br>DQSW ODD RX5<br>ODD R71*<br>DQSW270<br>Memory<br>Q[1:0]/ ODD RX2<br>Q[3:0]/ OSHX2<br>Q[6:0]*/ ODD RX4<br>Q[7:0]/ - _ a<br>Q[9:0]<br>**----- End of picture text -----**<br>


*For 7:1 LVDS interface only.  It is required to use PIO pair pins PIOA/B. 

**Figure 2.26. Output Register Block on Bottom Side** 

**Table 2.7. Output Block Port Description** 

|**Name**|**Type**|**Description**|
|---|---|---|
|Q|Output|High Speed Data Output|
|D|Input|Data from core to output SDR register|
|Q[1:0]/Q[3:0]/Q[6:0]/Q[7:0]/Q[9:0]|Input|Low Speed Data from device core to output DDR register|
|RST|Input|Reset to the Output Block|
|SCLK|Input|Slow Speed System Clock|
|ECLK|Input|High Speed Edge Clock|
|DQSW|Input|Clock from DQS control Block used to generate DDR memory DQS output|
|DQSW270|Input|Clock from DQS control Block used to generate DDR memory DQ output|



## **2.10.3. Tri-state Register Block** 

The tri-state register block registers tri-state control signals from the core of the device before they are passed to the sysI/O buffers. The block contains a register for SDR operation. In SDR, TD input feeds one of the flip-flops and then feeds the output. In DDR, operation used mainly for DDR memory interface can be implemented on the bottom side of the device. Here, two inputs feed the tri-state registers clocked by both ECLK and SCLK. 

Figure 2.27 and Figure 2.28 show the Tri-state Register Block functions on the device. For detailed description of the 

tri-state register block modes and usage, refer to MachXO5-NX High-Speed I/O Interface (FPGA-TN-02286). 

**==> picture [298 x 74] intentionally omitted <==**

**----- Start of picture text -----**<br>
TQ<br>TD<br>RST TSFF<br>SCLK<br>i e —)-<br>**----- End of picture text -----**<br>


**Figure 2.27. Tri-state Register Block on Top, Left, and Right Sides** 

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**MachXO5-NX Family Data Sheet** 

**==> picture [330 x 238] intentionally omitted <==**

**----- Start of picture text -----**<br>
TQ<br>TD<br>TSFF<br>RST<br>SCLK<br>ECLK<br>THSX2<br>DQSW ——____»><br>DQSW270<br>T[1:0] —______»+><br>**----- End of picture text -----**<br>


**Figure 2.28. Tri-state Register Block on Bottom Side** 

**Table 2.8. Tri-state Block Port Description** 

|**Name**|**Type**|**Description**|
|---|---|---|
|TD|Input|Tri-state Input to Tri-state SDR Register|
|RST|Input|Reset to the Tri-state Block|
|T[1:0]|Input|Tri-state input to TSHX2 function|
|SCLK|Input|Slow Speed System Clock|
|ECLK|Input|High Speed Edge Clock|
|DQSW|Input|Clock from DQS control Block used to generate DDR memory DQS output|
|DQSW270|Input|Clock from DQS control Block used to generate DDR memory DQ output|
|TQ|Output|Output of the Tri-state block|



## **2.11. DDR Memory Support** 

## **2.11.1. DQS Grouping for DDR Memory** 

Some PICs have additional circuitry to allow the implementation of high-speed source synchronous and DDR3/DDR3L/LPDDR4 memory interfaces. The support varies by the edge of the device as detailed below. 

The Bottom bank PIC has fully functional elements supporting DDR3/DDR3L/LPDDR4 memory interfaces. Every 12 PIO on the bottom side are grouped into one DQS group, as shown in Figure 2.29. Within each DQS group, there are two pre-placed pins for DQS and DQS# signals. The rest of the pins in the DQS group can be used as DQ signals and DM signal. The number of the pins in each DQS group bonded out is package dependent. DQS groups with less than 11 pins bonded out can only be used for Command/Address busses. In DQS groups with more than 11 pins bonded out, up to two pre-defined pins are assigned to be used as virtual VCCIO, by driving these pins to HIGH, and connecting these pins to VCCIO power supply. These 

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45 

**MachXO5-NX Family Data Sheet** 

Og@ MBB seEuiconducTor. 

connections create soft connections to VCCIO thru these output pins, and make better connections on VCCIO to help to reduce SSO noise. For details, refer to MachXO5-NX High-Speed I/O Interface (FPGA-TN-02286). 

**==> picture [429 x 333] intentionally omitted <==**

**----- Start of picture text -----**<br>
yg gases sas4e | es es ne ns a a|<br>! 1 I 1 | | 1 I<br>\I|I| |<br>\I ] I \ \ I<br>| I I I | I |<br>! i i 1 i ! i i<br>\1II|1I| || 1 |I<br>\I ] I \ \ I<br>| I I I | I |<br>! i i 1 i ! i i<br>\1II|1I| || 1 |I<br>DQS<br>PIO B PIO A PIO B PIO B<br>sysIO Buffer sysIO Buffer sysIO Buffer sysIO Buffer Delay sysIO Buffer<br>Pad A Pad B (C) Pad B (C) Pad B Pad A (T)<br>PIO A PIO B PIO A PIO B PIO A DQSBUF PIO B PIO A PIO A<br>sysIO Buffer sysIO Buffer sysIO Buffer sysIO Buffer sysIO Buffer sysIO Buffer sysIO Buffer<br>Pad B Pad A (T) Pad B Pad A Pad A (T) Pad A Pad B (C)<br>**----- End of picture text -----**<br>


**Figure 2.29. DQS Grouping on the Bottom Edge** 

## **2.11.2. DLL Calibrated DQS Delay and Control Block (DQSBUF)** 

To support DDR memory interfaces (DDR3/DDR3L/LPDDR4), the DQS strobe signal from the memory must be used to capture the data (DQ) in the PIC registers during memory reads. This signal is output from the DDR memory device aligned to data transitions and must be time shifted before it can be used to capture data in the PIC. This time shift is achieved by using DQSBUF programmable delay line in the DQS Delay Block (DQS read circuit). The DQSBUF is implemented as a slave delay line and works in conjunction with a master DDRDLL. 

This block also includes slave delay line to generate delayed clocks used in the write side to generate DQ and DQS with correct phases within one DQS group. There is a third delay line inside this block used to provide the write-leveling feature for DDR write if needed. 

Each of the read and write side delays can be dynamically shifted using margin control signals that can be controlled by the core logic. 

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**MachXO5-NX Family Data Sheet** 

FIFO Control Block included here generates the Read and Write Pointers for the FIFO block inside the Input Register Block. These pointers are generated to control the DQS to ECLK domain crossing using the FIFO module. 

**==> picture [331 x 230] intentionally omitted <==**

**----- Start of picture text -----**<br>
DQSI BTDETECT<br>Preamble/Postamble Management<br>PAUSE BURSTDETECT<br>RDCLKSEL[3:0] | DATAVALID<br>RDDIR<br>RDLOADN FIFO Control and Data Valid DQSW<br>READ[3:0] Generation DQSWRD<br>READMOVE RDPNTR[2:0]<br>RST |<br>SCLK READCOUT<br>Slave Delay Line (RD) with  DQSR90<br>SELCLK Adjustment/Margin Test<br>WRDIR<br>|<br>WRLOAD_N DQSW270<br>WRLVDIR<br>WRCOUT<br>WRLVLOAD_N Slave Delay (WR) with<br>Adjustment/Margin Test and Write Leveling WRLVCOUT<br>WRLVMOVE<br>—<br>WRMOVE<br>ECLKIN<br>WRPNTR[2:0]<br>RSTSMCNT<br>DLLCODE[8:0]<br>**----- End of picture text -----**<br>


**Figure 2.30. DQS Control and Delay Block (DQSBUF)** 

© 2021-2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02102-1.7 

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**MachXO5-NX Family** 

**Data Sheet** 

**Table 2.9. DQSBUF Port List Description** 

|**Name**<br>~~eG~~|**Type **<br>~~eG~~|**Description**<br>~~eG~~|
|---|---|---|
|DQSI<br>~~a~~|Input<br>|DQS signal from IO through the PIC.<br>|
|PAUSE<br>~~eG~~|Input<br>~~eG~~|To stopECLK for DDR3/LPDDR4 Write levelingand DLL code update.<br>~~eG~~|
|RDCLKSEL[3:0]<br>~~a~~|Input|Select read clock source andpolaritycontrol(from CIB).|
|RDDIR|Input|0 – to increase the code.<br>1 – to decrease the code for DDR read.|
|RDLOADN|Input|1b0 – When mc1_mt_en_read=1b1 and read_load_n=1b0 the read_move<br>pulse needs to be generated to the load the preload value consisting of the<br>{mc1_sign_read, mc1_s_read [8:0]} value.<br>1b1 – When counter has preload value, read_move pulse can be used to<br>increment and decrement the counter based on the read_direction signal<br>value and mc1_mt_en_write should be set 1b1.|
|READ[3:0]<br>~~eG~~|Input<br>~~eG~~|Read signal for DDR read mode(from CIB).<br>~~eG~~|
|READMOVE|Input|Move pulse needs to be at least 1 sclk cycle and should be greater than 5ns<br>at TT corner. Pulse is used along with the eclk to generate the internal 'mov'<br>signal to update the counter by one value. The count up or down is<br>determined bythe read_directionport.|
|RST<br>~~a~~|Input|DQS reset control for both DDR/CDR modes(from CIB).|
|SCLK|Input|SCLK from SCLK tree(CIB).|
|SELCLK|Input|Select the clock to be used between the output of the read section's delay<br>cell or sclk.|
|WRDIR|Input|0 – to increase the code.<br>1 – to decrease the code for DDR write.|
|WRLOAD_N|Input|1b0 – When mc1_mt_en_write=1b1 and write_load_n=1b0 the write_move<br>pulse needs to be generated to the load the preload value consisting of the<br>{mc1_sign_write, mc1_s_write [8:0]} value.<br>1b1 – When counter has preload value, write_move pulse can be used to<br>increment and decrement the counter based on the write_direction signal<br>value and mc1_mt_en_write should be set 1b1.|
|WRLVDIR|Input|0 – to increase the code.<br>1 – to decrease the code for DDR write leveling.|
|WRLVLOAD_N|Input|1b0 – 9-bit counter in reset operation.<br>1b1 – When mc1_mt_en_write_leveling=1b1 and<br>write_leveling_load_n=1b1 the counter can be incremented/decremented<br>based on the direction signal usingthe write_leveling_move signal.|
|WRLVMOVE|Input|Move pulse needs to be at least 1 sclk cycle and should be greater than 5 ns<br>at TT corner. Pulse is used along with the eclk to generate the internal 'mov'<br>signal to update the counter by one value. The count up or down is<br>determined bythe write_leveling_directionport.|
|WRMOVE|Input|Move pulse needs to be at least 1 sclk cycle and should be greater than 5ns<br>at TT corner. Pulse is used along with the eclk to generate the internal 'mov'<br>signal to update the counter by one value. The count up or down is<br>determined bythe write_directionport.|
|ECLKIN<br>~~a~~|Input|ECLK from four different ECLK tree output.|
|RSTSMCNT|Input|Signal to reset the smoothing counters used for the Read, Write, and Write<br>levelingdelays.|
|DLLCODE[8:0]<br>~~a~~|Input<br>|DLL code selected from the DLL code routingmux.<br>|
|BTDETECT<br>~~eG~~|Output<br>~~eG~~|READ burst detect output(to CIB).<br>~~eG~~|
|BURSTDETECT|Output|The burst_det_sclk signal is generated using burst_det and is asserted on<br>the risingedge of SCLK.|
|DATAVALID<br>~~ee~~|Output<br>~~ee~~|Data Valid Flagfor READ mode(to CIB).<br>~~ee~~|
|DQSW<br>~~ee~~<br>~~a~~|Output<br>~~ee~~|ECLKphase shifted or delayed,goes to the dqsw tree through the PIC.<br>~~ee~~|



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**MachXO5-NX Family Data Sheet** 

|**Name**|**Type **|**Description**|
|---|---|---|
|DQSWRD|Output|The read training clock adjusted in the write section. The read_clk_sel[3:0]<br>determines the selected delayand read enableposition.|
|RDPNTR[2:0]|Output|FIFO control READpointer(3-bits)to FIFO in PIC(through each tree to IOL).|
|READCOUT|Output|Margin test output flagfor READ to indicate the under-flow or over-flow.|
|DQSR90|Output|DQSI phase shifted or delayed by 90-degree output (through DQSR tree to<br>IOL).|
|DQSW270|Output|ECLK phase shifted or delayed by 270-degree output (through DQSW270<br>tree to IOL).|
|WRCOUT|Output|Margin test output flagfor WRITE to indicate the under-flow or over-flow.|
|WRLVCOUT|Output|Margin test output flag for WRITE LEVELING to indicate the under-flow or<br>over-flow.|
|WRPNTR[2:0]|Output|FIFO control WRITEpointer(3-bits)to FIFO in PIC(through each tree to IOL).|



## **2.12. sysI/O Buffer** 

Each I/O is associated with a flexible buffer referred to as a sysI/O buffer. These buffers are arranged around the periphery of the device in groups referred to as banks. The sysI/O buffers allows you to implement the wide variety of standards that are found in today’s systems including LVDS, HSUL, SSTL, and LVSTL Class I and II, LVCMOS, LVTTL, and MIPI. 

The MachXO5-NX family contains multiple Programmable I/O Cell (PIC) blocks. Each PIC contains two Programmable I/O, PIOA and PIOB. Each PIO includes a sysI/O buffer and I/O logic. Two adjacent PIO can be joined to provide a differential I/O pair. These two pairs are referred to as True and Comp, where True Pad is associated with the positive side of the differential I/O, and the complement with the negative. 

The top, left and right side banks support I/O standards from 3.3 V to 1.0 V while the bottom supports I/O standards from 1.8 V to 1.0 V. Every pair of I/O on the bottom bank also have a true LVDS and SLVS Tx Driver. In addition, the bottom bank supports single-ended input termination. Both static and dynamic termination are supported. Dynamic termination is used to support the DDR/LPDDR interface standards. For more information about DDR implementation in I/O Logic and DDR memory interface support, refer to MachXO5-NX High-Speed I/O Interface (FPGA-TN-02286). 

© 2021-2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02102-1.7 

49 

**MachXO5-NX Family Data Sheet** 

## **2.12.1. Supported sysI/O Standards** 

MachXO5-NX sysI/O buffer supports both single-ended differential and differential standards. Single-ended standards can be further subdivided into internally ratioed standards, such as LVCMOS, LVTTL, and external referenced standards such as HSUL, SSTL, and LVSTL. The buffers support the LVTTL, LVCMOS 1.0 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V, and 3.3 V standards. Differential standards supported include LVDS, SLVS, differential LVCMOS, differential SSTL, differential HSUL, and differential LVSTL. For better support of video standards, subLVDS and MIPI_D-PHY are also supported. Table 2.10 and Table 2.11 provide a list of sysI/O standards supported in MachXO5-NX devices. 

**Table 2.10. Single-Ended I/O Standards** 

|**Standard**<br>~~COO~~|**Input**<br>~~COO~~|**Output**<br>~~COO~~|**Bi-directional**<br>~~COO~~|
|---|---|---|---|
|LVTTL33<br>~~CO~~|Yes<br>~~CO~~|Yes<br>~~CO~~|Yes<br>~~CO~~|
|LVCMOS33<br>~~CO~~|Yes<br>~~CO~~|Yes<br>~~CO~~|Yes<br>~~CO~~|
|LVCMOS25<br>~~a ~~|Yes<br> ~~OO~~|Yes<br>~~OO~~|Yes<br>~~OO~~|
|LVCMOS18<br>~~a~~|Yes|Yes|Yes|
|LVCMOS15<br>~~a~~<br>~~a~~|Yes|Yes|Yes|
|LVCMOS12<br>~~a~~<br>~~a~~|Yes|Yes|Yes|
|LVCMOS10<br>~~a~~<br>~~CO~~|Yes<br>~~CO~~|No<br>~~CO~~|No<br>~~CO~~|
|HTSL15 I<br>~~OO~~|Yes<br>~~OO~~|Yes<br>~~OO~~|Yes<br>~~OO~~|
|SSTL 15 I<br>~~OO~~|Yes<br>~~OO~~|Yes<br>~~OO~~|Yes<br>~~OO~~|
|SSTL 135 I<br>~~a~~|Yes|Yes|Yes|
|HSUL12<br>~~a~~<br>~~a~~|Yes|Yes|Yes|
|LVSTL_I2<br>~~a~~<br>~~CO~~|Yes<br>~~CO~~|Yes<br>~~CO~~|Yes<br>~~CO~~|
|LVSTL_II2<br>~~OO~~|Yes<br>~~OO~~|Yes<br>~~OO~~|Yes<br>~~OO~~|
|LVCMOS18H<br>~~OO~~|Yes<br>~~OO~~|Yes<br>~~OO~~|Yes<br>~~OO~~|
|LVCMOS15H<br>~~a~~|Yes|Yes|Yes|
|LVCMOS12H<br>~~a~~<br>~~a~~|Yes|Yes|Yes|
|LVCMOS10H<br>~~a~~<br>~~OO~~|Yes<br>~~OO~~|Yes<br>~~OO~~|Yes<br>~~OO~~|
|LVCMOS10R<br>~~DO~~|Yes<br>~~DO~~|—<br>~~DO~~|Yes1<br>~~DO~~|



1. Output supported by LVCMOS10H. 

2. Only supported in MachXO5-NX-55T and MachXO5-NX-100T devices. 

© 2021-2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02102-1.7 

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**MachXO5-NX Family Data Sheet** 

**Table 2.11. Differential I/O Standards** 

|**Standard**<br>~~COO~~|**Input**<br>~~COO~~|**Output**<br>~~COO~~|**Bi-directional**<br>~~COO~~|
|---|---|---|---|
|LVDS<br>~~CO~~|Yes<br>~~CO~~|Yes<br>~~CO~~|Yes<br>~~CO~~|
|SUBLVDS<br>~~CO~~|Yes<br>~~CO~~|No<br>~~CO~~|—<br>~~CO~~|
|SLVS<br>~~CO~~|Yes<br>~~CO~~|Yes<br>~~CO~~|—<br>~~CO~~|
|SUBLVDSE<br>~~a ~~|—<br> ~~OO~~|Yes<br>~~OO~~|—<br>~~OO~~|
|SUBLVDSEH<br>~~CO~~|—<br>~~CO~~|Yes<br>~~CO~~|—<br>~~CO~~|
|LVDSE<br>~~CO~~|—<br>~~CO~~|Yes<br>~~CO~~|—<br>~~CO~~|
|MIPI_D-PHY<br>~~CO~~|Yes<br>~~CO~~|Yes<br>~~CO~~|Yes<br>~~CO~~|
|HSTL15D_I<br>~~CO~~|Yes<br>~~CO~~|Yes<br>~~CO~~|Yes<br>~~CO~~|
|SSTL15D_I<br>~~a ~~|Yes<br> ~~OO~~|Yes<br>~~OO~~|Yes<br>~~OO~~|
|SSTL15D_II<br>~~a ~~|Yes<br> ~~OO~~|Yes<br>~~OO~~|Yes<br>~~OO~~|
|SSTL135D_I<br>~~OO~~|Yes<br>~~OO~~|Yes<br>~~OO~~|Yes<br>~~OO~~|
|SSTL135D_II<br>~~a~~|Yes|Yes|Yes|
|LVSTLD_I1<br>~~a~~<br>~~CO~~|—<br>~~CO~~|—<br>~~CO~~|Yes<br>~~CO~~|
|LVSTLD_II1<br>~~OO~~|—<br>~~OO~~|—<br>~~OO~~|Yes<br>~~OO~~|
|HSUL12D<br>~~OO~~|Yes<br>~~OO~~|Yes<br>~~OO~~|Yes<br>~~OO~~|
|LVTTL33D<br>~~a~~|—|Yes|—|
|LVCMOS33D<br>~~a~~<br>~~a~~|—|Yes|—|
|LVCMOS25D<br>~~a~~<br>~~DO~~|—<br>~~DO~~|Yes<br>~~DO~~|—<br>~~DO~~|



**Note** : 

1. Only supported in MachXO-NX-55T and MachXO5-NX-100T devices. 

## **2.12.2. sysI/O Banking Scheme** 

MachXO5-NX device has up to ten banks in total. There are two banks on the top, three banks each at the left and right side of the device, and two on the bottom side of the device. For MachXO-25, Bank 1 can only support VCCIO 3.3 V, Bank 0, Bank 2, Bank 3, Bank 4, Bank 7, Bank 8 and Bank 9 support up to VCCIO 3.3 V, while Bank 5 and Bank 6 can support up to VCCIO 1.8 V. In addition, Bank 5 and Bank 6 support two VREF input for its flexibility to receive two different referenced input levels on the same bank. Figure 2.31 shows the location of each bank. For MachXO-55T/100T, Bank 0 can only support VCCIO 3.3 V, Bank 1, Bank 2, Bank 6 and Bank 7 support up to VCCIO 3.3 V, while Bank 3, Bank 4 and Bank 5 can support up to VCCIO 1.8 V. In addition, Bank 3, Bank 4 and Bank 5 support two VREF input for its flexibility to receive two different referenced input levels on the same bank. Figure 2.32 shows the location of each bank. 

© 2021-2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

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**==> picture [396 x 279] intentionally omitted <==**

**----- Start of picture text -----**<br>
VCCIO(0) VCCIO(1)<br>GND GND<br>Bank 0 Bank 1<br>GND<br>GND<br>VCCIO(9) Bank 9 Bank 2 VCCIO(2)<br>GND<br>GND<br>VCCIO(8) Bank 8 Bank 3 VCCIO(3)<br>7 7<br>_<br>GND<br>GND<br>Bank 4 VCCIO(4)<br>VCCIO(7) Bank 7<br>Bank 6 Bank 5<br>ee<br>GND GND<br>™ Ml<br>VCCIO(6) VREF1(6) VREF2(6) VCCIO(5) VREF1(5) VREF2(5)<br>**----- End of picture text -----**<br>


**Figure 2.31. sysI/O Banking of MachXO5-NX-25 Devices** 

**==> picture [392 x 277] intentionally omitted <==**

**----- Start of picture text -----**<br>
VCCIO(0)<br>GND<br>Bank 0<br>GND L GND<br>VCCIO(7) Bank 7 Bank 1 VCCIO(1)<br>GND GND<br>VCCIO(6) Bank 6 Bank 2 VCCIO(2)<br>Bank 5 Bank 4 Bank 3<br>OF<br>GND GND GND<br>™<br>™ ™<br>VCCIO(5) VREF1(5) VREF2(5) VCCIO(4) VREF1(4) VREF2(4) VCCIO(3) VREF1(3) VREF2(3)<br>**----- End of picture text -----**<br>


**Figure 2.32. sysI/O Banking of MachXO5-NX-55T/MachXO5-NX-100T Devices** 

© 2021-2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

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**MachXO5-NX Family Data Sheet** 

## **Typical sysI/O I/O Behavior During Power-up** 

The internal Power-On-Reset (POR) signal is deactivated when VCC and VCCAUX have reached satisfactory levels. After the POR signal is deactivated, the FPGA core logic becomes active. It is your responsibility to ensure that all other VCCIO banks are active with valid input logic levels to properly control the output logic states of all the I/O banks that are critical to the application. For more information on controlling the output logic state with valid input logic levels during power-up in MachXO5-NX devices, refer to the list of technical documentation in Supplemental Information section. 

The VCC and VCCAUX supply the power to the FPGA core fabric, whereas the VCCIO supplies power to the I/O buffers. In order to simplify the system design while providing consistent and predictable I/O behavior, it is recommended that the I/O buffers be powered-up prior to the FPGA core fabric. For different power supply voltage level by the I/O banks, refer to sysI/O User Guide for Nexus Platform (FPGA-TN-02067) for detailed information. 

## **VREF1 and VREF2** 

Bank 5 and Bank 6 can support two separate VREF input voltage, VREF1, and VREF2. To assign a VREF driver, use IO_Type = VREF1_DRIVER or VREF2_DRIVER. To assign VREF to a buffer, use VREF1_LOAD or VREF2_LOAD. 

## **sysI/O Standards Supported by I/O Bank** 

All banks can support multiple I/O standards under the VCCIO rules discussed above. Table 2.12 and Table 2.13 summarize the I/O standards supported on various sides of the MachXO5-NX device. 

© 2021-2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

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**MachXO5-NX Family Data Sheet** 

**Table 2.12. Single-Ended I/O Standards Supported on Various Sides** 

|**Standard**<br>~~ee~~|**Top1**<br>~~C(O~~|**Left**<br>~~C(O~~|**Right**<br>~~C(O~~|**Bottom**<br>~~C(O~~|
|---|---|---|---|---|
|LVTTL33<br>~~ee~~<br>~~a~~<br>~~a~~|Yes<br>~~C(O~~|Yes<br>~~C(O~~|Yes<br>~~C(O~~|—<br>~~C(O~~|
|LVCMOS33<br>~~a~~|Yes|Yes|Yes|—|
|LVCMOS25<br>~~a~~<br>~~a~~|Yes|Yes|Yes|—|
|LVCMOS18<br>~~a~~|Yes|Yes|Yes|—|
|LVCMOS15<br>~~a~~<br>~~a~~|Yes|Yes|Yes|—|
|LVCMOS12<br>~~a~~<br>~~a~~|Yes|Yes|Yes|—|
|LVCMOS10<br>~~a~~<br>~~a~~|Yes|Yes|Yes|—|
|LVCMOS18H<br>~~a~~<br>~~a~~|—|—|—|Yes|
|LVCMOS15H<br>~~a~~|—|—|—|Yes|
|LVCMOS12H<br>~~a~~|—|—|—|Yes|
|LVCMOS10H<br>~~a~~<br>~~ne~~|—|—|—|Yes|
|LVCMOS10R<br>~~ne~~|—|—|—|Yes|
|HTSL15 I<br>~~ne~~<br>~~a~~|—|—|—|Yes|
|SSTL 15 I, II<br>~~a~~|—|—|—|Yes|
|SSTL 135 I, II<br>~~a~~|—<br>|—<br>|—<br>|Yes<br>|
|HSUL12<br>~~GG~~|—<br>~~GG~~|—<br>~~GG~~|—<br>~~GG~~|Yes<br>~~GG~~|
|LVSTL I, II2<br>~~GG~~<br>~~a~~|—<br>~~GG~~|—<br>~~GG~~|—<br>~~GG~~|Yes<br>~~GG~~|



**Notes:** 

1. For MachXO5-NX-25 device, Bank 1 can only support 3.3 V VCCIO, For MachXO5-NX-55T/MachXO5-NX-100T device, Bank 0 can only support 3.3 V VCCIO. 

2. Only available in MachXO5-NX-55T and MachXO5-NX-100T devices. 

|**Standard**<br>~~GG~~|**Top1**<br>~~GG~~|**Left**<br>~~GG~~|**Right**<br>~~GG~~|**Bottom**<br>~~GG~~|
|---|---|---|---|---|
|LVDS<br>~~GG~~<br>~~a~~|—<br>~~GG~~<br>~~a~~|—<br>~~GG~~<br>~~a~~|—<br>~~GG~~<br>~~a~~|Yes<br>~~GG~~<br>~~a~~|
|SUBLVDS<br>~~a~~<br>~~a~~|—<br>~~a~~<br>~~a~~|—<br>~~a~~<br>~~a~~|—<br>~~a~~<br>~~a~~|Yes<br>~~a~~<br>~~a~~|
|SLVS<br>~~a~~|—<br>~~a~~|—<br>~~a~~|—<br>~~a~~|Yes<br>~~a~~|
|SUBLVDSE<br>~~CO~~|Yes<br>~~CO~~|Yes<br>~~CO~~|Yes<br>~~CO~~|—<br>~~CO~~|
|SUBLVDSEH<br>~~a~~|—<br>~~GG~~|—<br>~~GG~~|—<br>~~GG~~|Yes<br>~~GG~~|
|LVDSE<br>~~a ~~<br>~~a~~|Yes<br> ~~GG~~|Yes<br>~~GG~~|Yes<br>~~GG~~|—<br>~~GG~~|
|MIPI_D-PHY<br>~~a~~<br>~~a~~|—<br>|—<br>|—<br>|Yes<br>|
|HSTL15D_I<br>~~CO~~|—<br>~~CO~~|—<br>~~CO~~|—<br>~~CO~~|Yes<br>~~CO~~|
|SSTL15D_I<br>~~CO~~|—<br>~~CO~~|—<br>~~CO~~|—<br>~~CO~~|Yes<br>~~CO~~|
|SSTL15D_II<br>~~a~~|—<br>~~GG~~|—<br>~~GG~~|—<br>~~GG~~|Yes<br>~~GG~~|
|SSTL135D_I<br>~~a ~~<br>~~a~~|—<br> ~~GG~~|—<br>~~GG~~|—<br>~~GG~~|Yes<br>~~GG~~|
|SSTL135D_II<br>~~a~~<br>~~a~~|—|—|—|Yes|
|LVSTLD_I2<br>~~a~~<br>~~a~~|—<br>|—<br>|—<br>|Yes<br>|
|LVSTLD_II2<br>~~CO~~<br>~~ee~~|—<br>~~CO~~<br>~~GG~~|—<br>~~CO~~<br>~~GG~~|—<br>~~CO~~<br>~~GG~~|Yes<br>~~CO~~<br>~~GG~~|
|HSUL12D<br>~~ee~~<br>~~ee~~|—<br>~~GG~~|—<br>~~GG~~|—<br>~~GG~~|Yes<br>~~GG~~|
|LVTTL33D<br>~~ee~~<br>~~ee~~<br>~~ee~~|Yes<br>~~GG~~|Yes<br>~~GG~~|Yes<br>~~GG~~|—<br>~~GG~~|
|LVCMOS33D<br>~~ee~~<br>~~ee~~|Yes|Yes|Yes|—|
|LVCMOS25D<br>~~ee~~<br>~~a~~|Yes|Yes|Yes|—|



**Notes:** 

1. For MachXO5-NX-25 device, Bank 1 can only support 3.3 V VCCIO, For MachXO5-NX-55T/MachXO5-NX-100T device, Bank 0 can only support 3.3 V VCCIO. 

2. Only available in MachXO5-NX-55T and MachXO5-NX-100T devices. 

© 2021-2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

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**MachXO5-NX Family Data Sheet** 

## **Hot Socketing** 

MachXO5-NX devices have been carefully designed to ensure predictable behavior during power-up and power-down. During power-up and power-down sequences, the I/O remain in tri-state until the power supply voltage is high enough to ensure reliable operation. In addition, leakage into I/O pins is controlled within specified limits. Top/Left/Right Bank wide range I/O (excluding INITN/DONE) are fully hot socketable, while Bottom Bank are not supported. 

## **2.12.3. sysI/O Buffer Configurations** 

This section describes the various sysI/O features available on the MachXO5-NX device. Refer to sysI/O User Guide for Nexus Platform (FPGA-TN-02067) for detailed information. 

## **2.13. Analog Interface** 

In select speed grades, the MachXO5-NX family provides an analog interface, consisting of two Analog to Digital Convertors (ADC), three continuous time comparators and an internal junction temperature monitoring diode. See Ordering Information for more details. The two ADCs can sample the input sequentially or simultaneously. 

## **2.13.1. Analog to Digital Converters** 

The Analog to Digital Convertor is a 12-bit, 1 MSPS SAR (Successive Approximation Resistor/capacitor) architecture converter. The ADC supports both continuous and single shot conversion modes. 

The ADC input is selected among pre-selected GPIO input pairs, dedicated analog input pair, the internal junction temperature sensing diode and internal voltage rails. The input signal can be converted in either uni-polar or bi-polar mode. 

The reference voltage is selectable between the 1.2 V internal reference generator and an external reference. The ADC can convert up to a 1.8 V input signal with a 1.8 V external reference voltage. The ADC has an auto-calibration function which calibrates the gain and offset. 

## **2.13.2. Continuous Time Comparators** 

The continuous-time comparator can be used to compare a pre-selected GPIO input pairs or one dedicated comparator input pair. The output of the comparator is provided as continuous and latched data. 

## **2.13.3. Internal Junction Temperature Monitoring Diode** 

On-die junction temperature can be monitored using the internal junction temperature monitoring diode. The PTAT (proportional to absolute temperature) diode voltage can be monitored by the ADC to provide a digital temperature readout. Refer to ADC User Guide for Nexus Platform (FPGA-TN-02129) for more details. 

## **2.14. IEEE 1149.1-Compliant Boundary Scan Testability** 

All MachXO5-NX devices have boundary scan cells that are accessed through an IEEE 1149.1 compliant Test Access Port (TAP). This allows functional testing of the circuit board on which the device is mounted through a serial scan path that can access all critical logic nodes. Internal registers are linked internally, allowing test data to be shifted in and loaded directly onto test nodes, or test data to be captured and shifted out for verification. The test access port consists of dedicated I/O: TDI, TDO, TCK, and TMS. The test access port uses VCCIO2 for power supply. The test access port is supported for VCCIO2 = 1.8 V - 3.3 V. 

For more information, refer to MachXO5-NX Programming and Configuration User Guide (FPGA-TN-02271). 

© 2021-2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

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**MachXO5-NX Family Data Sheet** 

## **2.15. Device Configuration** 

All MachXO5-NX devices contain two ports that can be used for device configuration. The Test Access Port (TAP) that supports bit-wide configuration, and the sysCONFIG port that supports serial, quad, and byte configuration. TAP supports both the IEEE Standard 1149.1 Boundary Scan specification and the IEEE Standard 1532 In-System Configuration specification. The JTAG_EN is the only dedicated pin supported by sysCONFIG. PPROGRAMN/INITN/DONE are enabled by default, but can be turned into GPIO. The remaining sysCONFIG pins are used as dual function pins. Refer to MachXO5-NX Programming and Configuration User Guide (FPGA-TN-02271) for more information about using the dual-use pins as general purpose I/O. 

There are various ways to configure a MachXO5-NX device: 

- Internal Flash Download 

- JTAG 

- Inter-Integrated Circuit Bus (I[2] C) 

- Improved Inter-Integrated Circuit Bus (I3C) 

- System microprocessor to drive a serial slave SPI port (SSPI mode) 

- Lattice Memory Mapped Interface (LMMI), refer to sysI/O User Guide for Nexus Platform (FPGA-TN-02067) for condition. 

- JTAG, SSPI, I[2] C, and I3C are supported for VCCIO = 1.8 V – 3.3 V 

On power-up, based on the voltage level (high or low) of the PROGRAMN pin, the FPGA SRAM is configured by the appropriate sysCONFIG port. If PROGRAMN pin is _low_ , the FPGA is in the Slave configuration ports (Slave SPI, Slave I[2] C or Slave I3C) and is waiting for the correct Slave Configuration port activation key. PROGRAMN pin must be driven high within 50 ns of the end of transmission of the Slave Configuration port activation key, that is, the deassertion of SCSN. If no slave port is declared active before the PROGRAMN pin is sensed HIGH, the FPGA is in self download mode. In self download mode, the FPGA boots from on-chip flash. Once a configuration port is activated, it remains active throughout that configuration cycle. The IEEE 1149.1 port can be activated any time after power-up by enabling the JTAG_EN pin and sending the appropriate command through the TAP port. 

## **2.15.1. Enhanced Configuration Options** 

MachXO5-NX devices have enhanced configuration features such as: 

- Early I/O release 

- Bitstream decryption 

- Decompression support 

- Watchdog Timer support 

- Dual and Multi-boot image support 

Early I/O release is a new configuration feature in which certain I/O banks are released earlier so that customer systems have minimal disruption. For more details, refer to MachXO5-NX Programming and Configuration User Guide (FPGA-TN-02271). 

Watchdog Timer is a new configuration feature that helps you add a programmable timer option for timeout applications. 

## **2.15.2. Dual-Boot and Multi-Boot Image Support** 

Dual-boot and multi-boot images are supported for applications requiring reliable remote updates of configuration data for the system FPGA. After the system is running with a basic configuration, a new boot image can be downloaded remotely and stored in a separate location in the configuration storage device. Any time after the update, the MachXO5-NX devices can be re-booted from this new configuration file. If there is a problem, such as corrupt data during download or incorrect version number with this new boot 

© 2021-2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

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**MachXO5-NX Family Data Sheet** 

image, the MachXO5-NX device can revert back to the original backup golden configuration and try again. This all can be done without power cycling the system. For more information, refer to MachXO5-NX Programming and Configuration User Guide (FPGA-TN-02271). 

## **2.16. Single Event Upset (SEU) Support** 

MachXO5-NX devices are unique due to the underlying technology used to build these devices, and is much more robust and less prone to soft errors. 

MachXO5-NX devices have an improved hardware implemented Soft Error Detection (SED) circuit that can be used to detect SRAM errors and thus allow the errors to be corrected. There are two layers of SED implemented in the MachXO5-NX device making it more robust and reliable. 

The SED hardware in MachXO5-NX devices is part of the Configuration block. The SED module in the MachXO5-NX device is an enhanced version as compared to the SED modules implemented in other Lattice devices. The configuration data is divided into frames so that the entire FPGA can be programmed precisely with ease. The SED hardware reads data from the FPGAs configuration memory and performs Error Correcting Code (ECC) calculation on every frame of configuration data (see Figure 2.1). Once a single bit of error is detected, Soft Error Upset (SEU), a notification is generated and SED resumes operation. For single bit errors, the corrected value is rewritten to the particular frame using ECC information. If more than one-bit error is detected within one frame of configuration data, an error message is generated. MachXO5-NX devices also have a dedicated logic to perform Cycle Redundancy Code (CRC) checks. This CRC runs in parallel for the entire bitstream along with ECC. 

After the ECC is calculated on all frames of configuration data, Cyclic Redundancy Check (CRC) is calculated for the entire configuration data (bitstream). The data that is read, and the ECC and CRC calculated, do not include EBR Big SRAM and distributed RAM memory. 

For further information on SED support, refer to Soft Error Detection (SED)/Correction (SEC) User Guide for Nexus Platform (FPGA-TN-02076). 

## **2.17. On-Chip Oscillator** 

The MachXO5-NX device features two different frequency Oscillators. One is tailored for low-power operation that runs at low frequency (LFOSC). Both Oscillators are controlled with the internally generated current. 

The LFOSC runs at nominal frequency of 128 kHz. The high frequency oscillator (HFOSC) runs at a nominal frequency of 450 MHz, and is divisible from 2 to 256 for output frequency between 1.758 MHz (div256) and 225 MHz (div2). The LFOSC always run, thus can be used to perform all always-on functions with the possible lowest power. 

## **2.18. User I²C IP** 

The MachXO5-NX device has one I²C IP core. The core can be configured either as an I²C master or as an I²C slave. The pins for the I²C interface are pre-assigned. 

The core has the option to delay either the input or the output, or both, by 50 ns nominal, using dedicated on-chip delay elements. This provides an easier interface with any external I[2] C components. In addition, 50 ns glitch filters are available for both SDA and SCL. 

When the IP core is configured as master, it can control other devices on the I[2] C bus through the pre-assigned pin interface. When the core is configured as the slave, the device can provide, for example, I/O expansion to an I²C Master. The I²C core supports the following functionalities: 

- Master and Slave operation 

© 2021-2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

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**MachXO5-NX Family Data Sheet** 

- 7-bit and 10-bit addressing 

- Multi-master arbitration support 

- Clock stretching 

- Up to 1 MHz data transfer speed (Standard-Mode, Fast-Mode, Fast-Mode Plus) 

- General Call support 

- Optional receive and transmit data FIFOs with programmable sizes 

- Optionally 50 ns delay on input or output data, or both 

- Hard-connection and Programmable I/O connection support 

- Programmable to a mode compliant with I3C requirements on legacy I[2] C Slave devices 

- Fast-Mode and Fast-Mode Plus support 

- Disabled Clock Stretching 

- 50 ns SCL and SDA Glitch Filter 

- Programmable 7-bit address 

For further information on the User I²C, refer to I[2] C Hardened IP User Guide for Nexus Platform (FPGA-TN-02142). 

## **2.19. User Flash Memory (UFM)** 

MachXO5-NX devices provide a UFM block that can be used for a variety of applications including configuration image overflow, initializing EBRs to store PROM data or, as a general purpose user Flash memory. The UFM block connects to the device core through the embedded function block LMMI interface in the MachXO5-NX devices. You can also access the UFM block through the JTAG and SPI interfaces of the device. The UFM block offers the following features: 

- Non-volatile storage up to 79,872 kb 

- Write access is performed page-wise; each page has 2048 bits (256 bytes) 

- Auto-increment addressing 

- LMMI interface 

**Table 2.14. UFM Size** 

|**Device**|**UFM0(kbit)**|**UFM1(kbit)**|**UFM2(kbit)**|**User Data(kbit)**|
|---|---|---|---|---|
|LFMXO5-25|2,048|2,048|2,048|9,216|
|LFMXO5-55T|7,680|7,680|7,680|56,832|
|LFMXO5-100T|7,680|7,680|7,680|56,832|



## **2.20. Trace ID** 

Each MachXO5-NX device contains a unique (per device) TraceID that can be used for tracking purposes or for IP security applications. The TraceID is 64 bits long. Eight out of 64 bits are user-programmable, the remaining 56 bits are factory-programmed. The TraceID is accessible through the SPI, I[2] C, or JTAG interfaces. For further information on TraceID, refer to Using TraceID (FPGA-TN-02084). 

## **2.21. Pin Migration** 

The MachXO5-NX family is designed for pin migration in specific conditions. The MachXO5-NX-55T device can be migrated to the MachXO5-NX-100T device. Furthermore, the architecture ensures a high success rate when performing design migration from lower density devices to higher density devices. In many cases, it is also possible to shift a lower utilization design targeted for a high-density device to a lower density device. 

© 2021-2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02102-1.7 

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**MachXO5-NX Family Data Sheet** 

However, the exact details of the final resource utilization impact the likelihood of success in each case. An example is that some user I/O may become No Connects in smaller devices in the same package. Refer to the MachXO5-NX Pin Migration Tables and Lattice Radiant software for specific restrictions and limitations. 

## **2.22. Peripheral Component Interconnect Express (PCIe)** 

The MachXO5-NX-55T/MachXO5-NX-100T devices feature one hardened PCIe block on the top side of the device. The PCIe block implements all the three layers defined by the PCI Express Specification: Physical, Data Link, and Transaction, as shown in Figure 2.33. Below is a summary of the features supported by the PCIe bock: 

- Gen 1 (2.5 Gbps) and Gen 2 (5.0 Gbps) speed 

- PCIe Express Base Specification 3.0 compliant including compliance with earlier PCI Express Specifications 

- x1 or x1+x1 Bifurcation mode 

- Multi-function support with up to four physical functions 

- Endpoint 

- Type 0 configuration registers in Endpoint mode 

- Complete error-handling support 

- 32-bit core data width 

- Many power management features including power budgeting 

**==> picture [408 x 290] intentionally omitted <==**

**----- Start of picture text -----**<br>
PCI Express Core<br>PHY TX<br>Tx<br>Tx  Tx  VC0_TX<br>ietetel Data<br>PHY  Trans<br>Link<br>Layer Layer<br>Layer<br>Rx<br>PHY RX Rx  Rx VC0_RX<br>Data<br>PHY Trans<br>Link<br>Layer Layer<br>Layer<br>Power Management<br>Error Reporting (AER)<br>CLK, CONFIGURATION, AND MANAGEMENT<br>LMMI<br>CONFIGURATION REGISTERS<br>PHY Interface (PIPE)<br>**----- End of picture text -----**<br>


**Figure 2.33. PCIe Core** 

© 2021-2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

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BEAL TICE 

**MachXO5-NX Family Data Sheet** 

The hardened PCIe block can be instantiated with the primitive PCIe through Lattice Radiant software, however, it is not recommended to directly instantiate the PCIe primitive itself. It is highly recommended to generate the PCIe Endpoint Soft IP through the Radiant IP Catalog and IP Block Wizard instead. In Figure 2.34, the PCIe core is configured as Endpoint using a Soft IP wrapper that provides useful functions such as bridging support for bus interfaces and DMA applications. In addition to the standard Transaction Layer Packet (TLP) interface, the data interface can also be configured to be AXI4 or AHB-Lite as well. The PCIe hardened block also features a register interface for LMMI and User Configuration Space Register Interface (UCFG). The PCIe block has many registers that contain information about the current status of the PCIe block as well as the capability to dynamically switch PCIe settings. One easy way to access these registers is through the Reveal Controller Tool. 

For more information about the PCIe soft IP, refer to the PCIe X4 IP Core — Lattice Radiant Software (FPGA-IPUG-02126) document. 

**==> picture [432 x 149] intentionally omitted <==**

**----- Start of picture text -----**<br>
Top<br>Soft Logic PCIe Hard IP rxp_i/<br>AHB-Lite Rx TLP rxn_i<br>/AXI-4<br>Data Interface Conversion Tx TLP<br>txp_o/<br>Transaction  Link Layer PHY Layer txn_o<br>Layer<br>LMMI<br>AHB-Lite<br>/APB<br>Register Interface Conversion UCFG refclkp_i/refclkn_i<br>**----- End of picture text -----**<br>


**Figure 2.34. PCIe Soft IP Wrapper** 

© 2021-2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

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**MachXO5-NX Family Data Sheet** 

## **2.23. Cryptographic Engine** 

The MachXO5-NX family of devices support several cryptographic features that helps customer secure their design. Some of the key cryptographic features include Advanced Encryption Standard (AES) and Hashing Algorithms and true random number generator (TRNG). The MachXO5-NX device also features the bitstream encryption (using AES-256) used for protecting confidential FPGA bitstream data, and the bitstream authentication (using ECDSA) maintaining the bitstream integrity and protecting the FPGA design bitstream from being copied and tampered. 

The Cryptographic Engine (CRE) is the main engine (Figure 2.35) that is responsible for the bitstream encryption as well as the authentication of the MachXO5-NX-25, MachXO5-NX-55T, and MachXO5-NX-100T devices. Once the bitstream is authenticated and the device is ready for user functions, CRE is available for you to implement various cryptographic functions in your FPGA design. To enable specific cryptographic function, CRE must be configured by setting a few registers. 

CRE supports the following user-mode features: 

- True Random Number generator (TRNG) 

- Advanced Encryption Standard (AES-CBC)-256 bit 

- Secure Hashing Algorithm (SHA)-256 bit 

- Message authentication codes (MACs) – HMAC-256 

- Lattice Memory Mapped Interface (LMMI) interface to user logic 

- High Speed Port (HSP) for FIFO-based streaming data transfer 

**==> picture [470 x 142] intentionally omitted <==**

**----- Start of picture text -----**<br>
Cryptographic Engine (CRE)<br>Unique Secret Identity (USID)<br>—<br>Control Register<br>LMMI / True Random Number Generator (TRNG)<br>—<br>FPGA  High Speed Port<br>CRE Registers<br>Fabric a Advanced Encryption Standard (AES)<br>SHA256<br>Bitstream Encryption<br>[| —_<br>HMAC SHA256<br> i<br>Bitstream Authentication<br>**----- End of picture text -----**<br>


**Figure** 2 **.** 35 **. Cryptographic Engine Block Diagram** 

© 2021-2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

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**MachXO5-NX Family Data Sheet** 

## **3. DC and Switching Characteristics for LFMXO5-25 Commercial and Industrial** 

All specifications in this section are characterized within recommended operating conditions unless otherwise specified. 

## **3.1. Absolute Maximum Ratings** 

**Table 3.1. Absolute Maximum Ratings** 

|**Symbol**<br>~~pf~~|**Parameter**<br>~~pf~~|**Min**<br>~~pf~~|**Max**<br>~~pf~~|**Unit**<br>~~pf~~|
|---|---|---|---|---|
|VCC, VCCECLK<br>~~eG~~|SupplyVoltage<br>~~eG~~|–0.5<br>~~eG~~|1.10<br>~~eG~~|V<br>~~eG~~|
|VCCAUX, VCCAUXA,<br>VCCAUXH5, VCCAUXH6<br>~~a~~|Supply Voltage|–0.5|1.98|V|
|VCCIO0, 1, 2, 3, 4, 7, 8, 9<br>~~a~~<br>~~a~~|I/O SupplyVoltage<br>|–0.5<br>|3.63<br>|V<br>|
|VCCIO5, 6<br>~~a~~<br>~~a~~|I/O SupplyVoltage<br>|–0.5<br>|1.98<br>|V<br>|
|VCCADC18<br>~~aCe~~|ADC Block 1.8 V SupplyVoltage<br>~~Ce~~|–0.5<br>~~Ce~~|1.98<br>~~Ce~~|V<br>~~Ce~~|
|VCCADC18<br>~~Ce~~|ADC Block 1.8 V SupplyVoltage<br>~~Ce~~|–0.5<br>~~Ce~~|1.98<br>~~Ce~~|V<br>~~Ce~~|
|—<br>~~a~~|Input or I/O Voltage Applied, Bank 0, Bank 1,<br>Bank 2, Bank 3, Bank 4, Bank 7, Bank 8, Bank 9|–0.5|3.63|V|
|—<br>~~Ce~~|Input or I/O Voltage Applied, Bank 5, Bank 6<br>~~Ce~~|–0.5<br>~~Ce~~|1.98<br>~~Ce~~|V<br>~~Ce~~|
|TA<br>~~a~~|Storage Temperature(Ambient)<br>|–65<br><br>~~GO~~|150<br><br>~~GO~~|°C<br>|
|TJ<br>~~aeG~~|Junction Temperature<br>~~eG~~|—<br>~~eG~~<br>~~GO~~|+125<br>~~eG~~<br>~~GO~~|°C<br>~~eG~~|



- Compliance with the Lattice Thermal Management document is required. 

- All voltages referenced to GND. 

- All VCCAUX should be connected on PCB. 

## **3.2. Recommended Operating Conditions[1, 2, 3]** 

**Table 3.2. Recommended Operating Conditions** 

|**Symbol**<br>~~DCO~~|**Parameter**<br>~~DCO~~|**Conditions**<br>~~DCO~~|**Min**<br>~~DCO~~|**Typ. **<br>~~DCO~~|**Max**<br>~~DCO~~|**Unit**<br>~~DCO~~|
|---|---|---|---|---|---|---|
|VCC,VCCECLK<br>~~DCO~~<br>~~sD~~|Core SupplyVoltage<br>~~DCO~~<br>~~sD~~|VCC= 1.0<br>~~DCO~~<br>~~sD~~|0.95<br>~~DCO~~<br>~~sD~~|1.00<br>~~DCO~~<br>~~sD~~|1.05<br>~~DCO~~<br>~~sD~~|V<br>~~DCO~~<br>~~sD~~|
|VCCAUX<br>~~sD~~|Auxiliary Supply Voltage<br>~~sD~~|Bank 0, Bank 1, Bank 2, Bank<br>3, Bank 4, Bank 7, Bank 8,<br>Bank 9<br>~~sD~~|1.746<br>~~sD~~|1.80<br>~~sD~~|1.89<br>~~sD~~|V<br>~~sD~~|
|VCCAUXH5/6<br>~~GD~~|AuxiliarySupplyVoltage<br>~~GD~~|Bank 5, Bank 6<br>~~GD~~|1.746<br>~~GD~~|1.80<br>~~GD~~|1.89<br>~~GD~~|V<br>~~GD~~|
|VCCAUXA<br>~~GD~~<br>~~a~~|Auxiliary Supply Voltage<br>for core logic<br>~~GD~~<br>~~ee~~|—<br>~~GD~~<br>~~ee~~|1.746<br>~~GD~~<br>~~ee~~|1.80<br>~~GD~~<br>~~ee~~|1.89<br>~~GD~~<br>~~ee~~|V<br>~~GD~~<br>~~ee~~|
|VCCIO<br>~~a~~<br>~~S~~|I/O Driver Supply Voltage<br>~~ee~~<br>~~S~~f|VCCIO= 3.3 V, Bank 0, Bank 1,<br>Bank 2, Bank 3, Bank 4, Bank<br>7,Bank 8,Bank 9<br>~~ee~~<br>~~es~~|3.135<br>~~ee~~<br>~~es~~|3.30<br>~~ee~~<br>~~es~~|3.465<br>~~ee~~<br>~~es~~|V<br>~~ee~~<br>~~es~~|
|||VCCIO= 2.5 V, Bank 0, Bank 2,<br>Bank 3, Bank 4, Bank 7, Bank<br>8, Bank 9<br>~~es~~|2.375<br>~~es~~|2.50<br>~~es~~|2.625<br>~~es~~|V<br>~~es~~|
|||VCCIO= 1.8 V, All Banks except<br>Bank 1<br>~~es~~|1.71<br>~~es~~<br>~~ee~~|1.80<br>~~es~~<br>~~ee~~|1.89<br>~~es~~<br>~~ee~~|V<br>~~es~~<br>~~ee~~|
|||VCCIO= 1.5 V, All Banks except<br>Bank 14<br>~~es~~|1.425<br>~~es~~<br>~~ee~~|1.50<br>~~es~~<br>~~ee~~|1.575<br>~~es~~<br>~~ee~~|V<br>~~es~~<br>~~ee~~|



62 

**MachXO5-NX Family Data Sheet** 

|**Symbol**<br>~~POPf~~|**Parameter**<br>~~Pf~~|**Conditions**<br>~~EE~~|**Min**<br>~~EE~~|**Typ. **<br>~~EE~~|**Max**|**Unit**|
|---|---|---|---|---|---|---|
|~~POPf~~|~~Pf~~|VCCIO= 1.35 V, All Banks<br>except Bank 14(For DDR3L<br>Only)<br>~~EE~~|1.2825<br>~~EE~~|1.35<br>~~EE~~|1.4175|V|
|||VCCIO= 1.2 V, All Banks except<br>Bank 14<br>~~EE~~|1.14<br>~~EE~~|1.20<br>~~EE~~|1.26|V|
|||VCCIO= 1.0 V, Bank 5, Bank 6<br>~~EE~~<br>~~es~~|0.95<br>~~EE~~<br>~~es~~|1.00<br>~~EE~~<br>~~es~~|1.05<br>~~es~~|V<br>~~es~~|
|**ADC External Power Supplies**<br>~~Pf EE~~<br>~~PT~~|||||||
|VCCADC18<br>~~GD~~|ADC 1.8 V Power Supply<br>~~GD~~|—<br>~~GD~~|1.71<br>~~GD~~|1.80<br>~~GD~~|1.89<br>~~GD~~|V<br>~~GD~~|
|**Operating Temperature**|||||||
|tJCOM<br>~~a~~|Junction Temperature,<br>Commercial Operation<br>~~a~~<br>~~a~~|—<br>~~a~~<br>~~a~~|0<br>~~a~~|—<br>~~a~~|85|°C|
|tJIND<br>~~a~~|Junction Temperature,<br>Industrial Operation<br>~~a~~|—<br>~~a~~|–40|—|100|°C|



**Notes** : 

1. For correct operation, all supplies must be held in their valid operation voltage range. 

2. All supplies with same voltage should be from the same voltage source. Proper isolation filters are needed to properly isolate noise from each other. 

3. Common supply rails must be tied together. 

4. JTAG, SSPI, I[2] C, and I3C (Bank 2) ports are supported for VCCIO = 1.8 V to 3.3 V. 

## **3.3. Power Supply Ramp Rates** 

**Table 3.3. Power Supply Ramp Rates** 

|**Symbol**|**Parameter**|**Min**|**Typ**|**Max**|**Unit**|
|---|---|---|---|---|---|
|tRAMP|Power Supplyramprates for all supplies1|0.1|—|50|V/ms|



**Notes** : 

1. Assumes monotonic ramp rates. 

2. All supplies need to be in the operating range as defined in Recommended Operating Conditions when the device has completed configuration and entering into User Mode. Supplies that are not in the operating range needs to be adjusted to faster ramp rate, or you have to delay configuration or wake up. 

## **3.4. Power up Sequence** 

Power-On-Reset (POR) puts the MachXO5-NX device into a reset state. There is no power up sequence required for the MachXO5-NX device. 

**Table 3.4. Power-On Reset** 

|**Symbol**|**Parameter**|**Parameter**|**Min**|**Typ**|**Max**|**Unit**|
|---|---|---|---|---|---|---|
|VPORUP|Power-On-Reset ramp-up trip<br>point (Monitoring VCC, VCCAUX,<br>VCCI01, and VCCI02)|VCC|0.73|—|0.83|V|
|||VCCAUX|1.34|—|1.62|V|
|||VCCIO1,VCCI02|0.89|—|1.05|V|
|VPORDN|Power-On-Reset ramp-up trip<br>point (Monitoring VCCand VCCAUX)|VCC|0.51|—|0.81|V|
|||VCCAUX|1.38|—|1.59|V|



## **3.5. On-Chip Programmab** l **e Termination** 

The MachXO5-NX devices support a variety of programmable on-chip terminations options, including: 

- Dynamically switchable Single-Ended Termination with programmable resistor values of 40 Ω, 50 Ω, 60 Ω, or 75 Ω. 

- Common mode termination of 100 Ω for differential inputs. 

© 2021-2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

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**MachXO5-NX Family Data Sheet** 

Zo = 50 

**==> picture [440 x 143] intentionally omitted <==**

**----- Start of picture text -----**<br>
V CCIO Zo = 50<br>TERM<br>Zo = 40  , 50  , 60  , or 75<br>control<br>to VCCIO  /2<br>Zo<br>Zo +<br>Zo + 2Zo -<br>- Zo<br>VREF<br>OFF-chip | ON-chip OFF-chip [|] ON-chip<br>—_ : — , <——_——_ : ——— ><br>Parallel Single-Ended Input Differential Input<br>**----- End of picture text -----**<br>


**==> picture [67 x 9] intentionally omitted <==**

**----- Start of picture text -----**<br>
Differential Input<br>**----- End of picture text -----**<br>


**Figure 3.1. On-Chip Termination** 

See Table 3.5 for termination options for input modes. 

**Table 3.5. On-Chip Termination Options for Input Modes** 

|**IO_TYPE**<br>~~a~~|**Differential Termination Resistor1, 2**|**Terminate to VCCIO/21, 2**|
|---|---|---|
|subLVDS<br>~~a~~|100, OFF|OFF|
|SLVS|100, OFF|OFF|
|MIPI_DPHY<br>~~ee~~|100<br>~~ee~~|OFF<br>~~ee~~|
|HSTL15D_I<br>~~ee~~<br>~~ee~~|100, OFF<br>~~ee~~<br>~~ee~~|OFF<br>~~ee~~<br>~~ee~~|
|SSTL15D_I<br>~~ee~~<br>~~a~~|100, OFF<br>~~ee~~|OFF<br>~~ee~~|
|SSTL135D_I<br>~~eG~~|100, OFF<br>~~eG~~|OFF<br>~~eG~~|
|HSUL12D<br>~~ee~~|100, OFF<br>~~ee~~|OFF<br>~~ee~~|
|LVCMOS15H<br>~~ee~~<br>~~ee~~|OFF<br>~~ee~~<br>~~ee~~|OFF<br>~~ee~~<br>~~ee~~|
|LVCMOS12H<br>~~ee~~<br>~~ee~~|OFF<br>~~ee~~<br>~~ee~~|OFF<br>~~ee~~<br>~~ee~~|
|LVCMOS10H<br>~~ee~~<br>~~eG~~|OFF<br>~~ee~~<br>~~eG~~|OFF<br>~~ee~~<br>~~eG~~|
|LVCMOS12H<br>~~eG~~|OFF<br>~~eG~~|OFF<br>~~eG~~|
|LVCMOS10H<br>~~ee~~|OFF<br>~~ee~~<br>~~Ge~~|OFF<br>~~ee~~|
|LVCMOS18H<br>~~ee~~<br>~~ee~~|OFF<br>~~ee~~<br>~~ee~~<br>~~Ge~~<br>~~Ge~~|OFF, 40, 50, 60, 75<br>~~ee~~<br>~~ee~~|
|HSTL15_I<br>~~ee~~<br>~~ee~~|OFF<br>~~ee~~<br>~~Ge~~<br>~~ee~~<br>~~Ge~~|50<br>~~ee~~<br>~~ee~~|
|SSTL15_I<br>~~ee~~<br>~~eG~~|OFF<br>~~ee~~<br>~~Ge~~<br>~~eG~~|OFF, 40, 50, 60, 75<br>~~ee~~<br>~~eG~~|
|SSTL135_I<br>~~a~~|OFF|OFF, 40, 50, 60, 75|
|HSUL12<br>~~a~~|OFF|OFF, 40, 50, 60, 75|
|LVSTL_I<br>~~ee~~|OFF, OFF<br>~~ee~~<br>~~Ge~~|40, 48, 60, 80, 120<br>~~ee~~|
|LVSTL_II<br>~~ee~~<br>~~ee~~|OFF, OFF<br>~~ee~~<br>~~ee~~<br>~~Ge~~|80, 120<br>~~ee~~<br>~~ee~~|



1. TERMINATE to VCCIO/2 (Single-Ended) and DIFFRENTIAL TERMINATION RESISTOR when turned on can only have one setting per bank. Only bottom bank have this feature. 

2. Use of TERMINATE to VCCIO/2 and DIFFRENTIAL TERMINATION RESISTOR are mutually exclusive in an I/O bank. On-chip termination tolerance –10%/+60%. 

Refer to sysI/O User Guide for Nexus Platform (FPGA-TN-02067) for on-chip termination usage and value ranges. 

© 2021-2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

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**MachXO5-NX Family Data Sheet** 

## **3.6. Hot Socketing Specifications** 

**Table 3.6. Hot Socketing Specifications for GPIO** 

|**Symbol**|**Parameter**|**Condition**|**Min**|**Typ**|**Max**|**Unit**|
|---|---|---|---|---|---|---|
|IDK|Input or I/O Leakage Current for<br>Wide Range I/O (excluding<br>INITN/DONE)|0 < VIN< VIH(max)<br>0 < VCC< VCC(max)<br>0 < VCCIO< VCCIO(max)<br>0 < VCCAUX< VCCAUX(max)|–1.5|—|1.5|mA|



**Notes** : 

- IDK is additive to IPU, IPD, or IBH. 

- Hot socket specification defines when the hot socketed device's junction temperature is at 85[o] C or below. When the hot socketed device's junction temperature is above 85[o] C, the IDK current can exceed the above spec. 

- Going beyond the hot socketing ranges specified here will cause exponentially higher Leakage currents and potential reliability issues. A total of 64mA per 8 I/O should not be exceeded. 

## **3.7. Programming/Erase Specifications** 

**Table 3.7. Programming/Erase Specifications** 

|**Symbol**|**Parameter**|**Min**|**Max.**|**Units**|
|---|---|---|---|---|
|NPROGCYC|Flash Programmingcyclesper tRETENTION|—|10,000|Cycles|
||Flash Write/Erase cycles|—|100,000||
|tRETENTION|Data retention at 100°Cjunction temperature|20|—|Years|
||Data retention at 85°Cjunction temperature|>20|—||



**Note** : 

A Write/Erase cycle is defined as any number of writes over time followed by one erase cycle. 

## **3.8. ESD Performance** 

Refer to the MachXO5-NX Product Family Qualification Summary for complete qualification data, including ESD performance. 

© 2021-2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

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**MachXO5-NX Family Data Sheet** 

## **3.9. DC Electrical Characteristics** 

**Table 3.8. DC Electrical Characteristics – Wide Range (Over Recommended Operating Conditions)** 

|**Symbol**<br>~~pO~~|**Parameter**|**Condition**|**Min**<br>~~ee~~|**Typ**<br>~~ee~~|**Max**|**Unit**|
|---|---|---|---|---|---|---|
|IIL, IIH1<br>~~pO~~<br>~~aee~~|Input or I/O Leakage current<br>(Commercial/Industrial)<br>~~ee~~|0 ≤ VIN≤ VCCIO<br>~~ee~~|—<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~|10<br>~~ee~~|µA<br>~~ee~~|
|IIH2<br>~~GGG~~<br>~~a~~|Input or I/O Leakage current<br>~~GGG~~<br>|VCCIO≤ VIN≤ VIH (max)<br>~~GGG~~<br>|—<br>~~ee ~~<br>~~GGG~~<br>~~ee ee~~<br>|—<br> ~~ee~~<br>~~GGG~~<br>~~ee~~<br>|100<br>~~GGG~~<br>~~ee~~<br>|µA<br>~~GGG~~<br>~~ee~~<br>|
|IPU<br>~~aee~~<br>~~a~~<br>~~a~~|I/O Weak Pull-up Resistor<br>Current<br>~~ee~~<br><br>|0 ≤ VIN≤ 0.7 × VCCIO<br>~~ee~~<br><br>|-30<br>~~ee~~<br>~~ee ee~~<br><br>~~ee ee~~<br>|—<br>~~ee~~<br>~~ee~~<br><br>~~ee~~<br>|-150<br>~~ee~~<br>~~ee~~<br><br>~~ee~~<br>|µA<br>~~ee~~<br>~~ee~~<br><br>~~ee~~<br>|
|IPD<br>~~aee~~<br>~~a~~|I/O Weak Pull-down Resistor<br>Current<br>~~ee~~<br>|VIL(max) ≤ VIN≤ VCCIO<br>~~ee~~<br>|30<br>~~ee ee~~<br>~~ee~~<br>~~ee ee~~<br>|—<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>|150<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>|µA<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>|
|IBHLS<br>~~aGG~~|Bus Hold Low SustainingCurrent<br>~~GG~~|VIN= VIL (max)<br>~~GG~~|30<br>~~ee ee~~<br>~~GG~~|—<br>~~ee~~<br>~~GG~~|—<br>~~ee~~<br>~~GG~~|µA<br>~~ee~~<br>~~GG~~|
|IBHHS<br>~~aGG~~|Bus Hold High SustainingCurrent<br>~~GG~~|VIN= 0.7 × VCCIO<br>~~GG~~|-30<br>~~GG~~|—<br>~~GG~~|—<br>~~GG~~|µA<br>~~GG~~|
|IBHLO<br>~~aGG~~|Bus hold low Overdrive Current<br>~~GG~~|0 ≤ VIN≤ VCCIO<br>~~GG~~|—<br>~~GG~~|—<br>~~GG~~|150<br>~~GG~~|µA<br>~~GG~~|
|IBHHO<br>~~GO~~|Bus hold high Overdrive Current<br>~~GO~~|0 ≤ VIN≤ VCCIO<br>~~GO~~|—<br>~~GO~~|—<br>~~GO~~|-150<br>~~GO~~|µA<br>~~GO~~|
|VBHT<br>~~GO~~<br>~~GD~~|Bus Hold TripPoints<br>~~GO~~<br>~~GD~~|—<br>~~GO~~<br>~~GD~~|VIL(max)<br>~~GO~~<br>~~GD~~|—<br>~~GO~~<br>~~GD~~|VIH(min)<br>~~GO~~<br>~~GD~~|V<br>~~GO~~<br>~~GD~~|



## **Notes** : 

1. Input or I/O leakage current is measured with the pin configured as an input or as an I/O with the output tri-stated. Bus Maintenance circuits are disabled. 

2. The input leakage current IIH is the worst case input leakage per GPIO when the pad signal is high and also higher than the bank VCCIO. This is considered a mixed mode input. 

**Table 3.9. DC Electrical Characteristics – High Speed (Over Recommended Operating Conditions)** 

|**Symbol**<br>~~pO~~|**Parameter**|**Condition**|**Min**|**Typ**|**Max**|**Unit**|
|---|---|---|---|---|---|---|
|IIL, IIH1<br>~~pO~~<br>~~a~~|Input or I/O Leakage<br>|0 ≤ VIN≤ VCCIO<br>|—<br>|—<br>|10<br>|µA<br>|
|IPU<br>~~aee~~|I/O Weak Pull-up Resistor<br>Current<br>~~ee~~|0 ≤ VIN≤ 0.7 × VCCIO<br>~~ee~~|-30<br>~~ee~~|—<br>~~ee~~|-150<br>~~ee~~|µA<br>~~ee~~|
|IPD<br>~~ee~~<br>~~ee~~|I/O Weak Pull-down Resistor<br>Current<br>~~ee~~<br>~~ee~~|VIL(max) ≤ VIN≤ VCCIO<br>~~ee~~<br>~~ee~~|30<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~|150<br>~~ee~~<br>~~ee~~|µA<br>~~ee~~<br>~~ee~~|
|IBHLS<br>~~ee~~<br>~~a OO~~|Bus Hold Low SustainingCurrent<br>~~ee~~<br>~~OO~~|VIN= VIL (max)<br>~~ee~~<br>~~OO~~|30<br>~~ee~~<br>~~OO~~|—<br>~~ee~~<br>~~OO~~|—<br>~~ee~~<br>~~OO~~|µA<br>~~ee~~<br>~~OO~~|
|IBHHS<br>~~a OO~~<br>~~a GG~~|Bus Hold High SustainingCurrent<br>~~OO~~<br>~~GG~~|VIN= 0.7 × VCCIO<br>~~OO~~<br>~~GG~~|-30<br>~~OO~~<br>~~GG~~|—<br>~~OO~~<br>~~GG~~|—<br>~~OO~~<br>~~GG~~|µA<br>~~OO~~<br>~~GG~~|
|IBHLO<br>~~a GG~~<br>~~a~~|Bus hold low Overdrive Current<br>~~GG~~<br>~~GGG~~|0 ≤ VIN≤ VCCIO<br>~~GG~~<br>~~GGG~~|—<br>~~GG~~<br>~~GGG~~|—<br>~~GG~~<br>~~GGG~~|150<br>~~GG~~<br>~~GGG~~|µA<br>~~GG~~<br>~~GGG~~|
|IBHHO<br>~~a~~|Bus hold high Overdrive Current<br>~~GG~~|0 ≤ VIN≤ VCCIO<br>~~GG~~|—<br>~~GG~~|—<br>~~GG~~|-150<br>~~GG~~|µA<br>~~GG~~|
|VBHT<br>~~a~~|Bus Hold Trip Points|—|VIL<br>(max)|—|VIH(min)|V|



## **Note:** 

1. Input or I/O leakage current is measured with the pin configured as an input or as an I/O with the output tri-stated. Bus Maintenance circuits are disabled. 

**Table 3.10. Capacitors – Wide Range (Over Recommended Operating Conditions)** 

|**Symbol**|**Parameter**|**Condition**|**Min**|**Typ**|**Max**|**Unit**|
|---|---|---|---|---|---|---|
|C11|I/O Capacitance|VCCIO = 3.3 V, 2.5 V, 1.8 V, 1.5 V, 1.2 V,<br>VCC = typ., VIO = 0 to VCCIO+ 0.2 V|—|6|—|pf|
|C21|Dedicated Input Capacitance|VCCIO = 3.3 V, 2.5 V, 1.8 V, 1.5 V, 1.2 V,<br>VCC = typ., VIO = 0 to VCCIO+ 0.2 V|—|6|—|pf|



**Note** : 

1. TA 25[o] C, f = 1.0 MHz. 

© 2021-2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

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**MachXO5-NX Family Data Sheet** 

**Table 3.11. Capacitors – High Performance (Over Recommended Operating Conditions)** 

|**Symbol**|**Parameter**|**Condition**|**Min**|**Typ**|**Max**|**Unit**|
|---|---|---|---|---|---|---|
|C11|I/O Capacitance|VCCIO = 1.8 V, 1.5 V, 1.2 V, VCC = typ.,<br>VIO = 0 to VCCIO+ 0.2 V|—|6|—|pf|
|C21|Dedicated Input Capacitance|VCCIO = 1.8 V, 1.5 V, 1.2 V, VCC = typ.,<br>VIO = 0 to VCCIO+ 0.2 V|—|6|—|pf|



**Note:** 

1. TA 25[o] C, f = 1.0 MHz. **Table 3.12. Single Ended Input Hysteresis – Wide Range (Over Recommended Operating Conditions) IO_TYPE VCCIO TYP Hysteresis** LVCMOS33 3.3 V 250 mV 3.3 V 200 mV LVCMOS25 2.5 V 250 mV LVCMOS18 1.8 V 180 mV LVCMOS15 1.5 V 50 mV LVCMOS12 1.2 V 0 LVCMOS10 1.2 V 0 **Table 3.13. Single Ended Input Hysteresis – High Performance (Over Recommended Operating Conditions) IO_TYPE VCCIO TYP Hysteresis** LVCMOS18H 1.8 V 180 mV 1.8 V 50 mV LVCMOS15H 1.5 V 150 mV LVCMOS12H 1.2 V 0 LVCMOS10H 1.0 V 0 MIPI-LP-RX 1.2 V >25 mV ~~—————_—~~ **3.10. Supply Currents** For estimating and calculating current, use Power Calculator in Lattice Design Software. This operating and peak current is design dependent, and can be calculated in Lattice Design Software. Some blocks can be placed into low current standby modes. Refer to Power Management and Calculation for Certus-NX, CertusPro-NX, and MachXO5-NX Devices (FPGA-TN-02257). ~~[=]~~ © 2021-2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

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**MachXO5-NX Family Data Sheet** 

## **3.11. sysI/O Recommended Operating Conditions** 

**Table 3.14. sysI/O Recommended Operating Conditions** 

|**Standard**<br>~~Bf~~|**Support Banks**<br>~~Bf~~|**VCCIO(Input)**<br>~~Ef~~|**VCCIO(Output)**<br>~~Ef~~|
|---|---|---|---|
|||**Typ.**<br>~~Ef~~<br>~~a~~|**Typ. **<br>~~Ef~~<br>~~a~~|
|**Single-Ended**<br>~~Bf~~<br>~~Ef~~<br>~~**G**e~~<br>~~GO~~||||
|LVCMOS33<br>~~**G**~~|0, 1, 2, 3, 4, 7, 8, 9<br>~~**G**e~~|3.3<br>~~e~~|3.3<br>~~GO~~|
|LVTTL33<br>~~**G**~~|0, 1, 2, 3, 4, 7, 8, 9<br>~~**G**e~~|3.3<br>~~e~~<br>~~G~~|3.3<br>~~GO~~<br>~~G~~|
|LVCMOS25¹,²<br>~~GG~~|0, 2, 3, 4, 7, 8, 9<br>~~GG~~|2.5, 3.3<br>~~GG~~|2.5<br>~~GG~~|
|LVCMOS18¹,²<br>~~GG~~<br>~~**G**~~|0, 2, 3, 4, 7, 8, 9<br>~~GG~~<br>~~**G**e~~|1.2, 1.5, 1.8, 2.5, 3.3<br>~~GG~~<br>~~e~~|1.8<br>~~GG~~<br>~~GO~~|
|LVCMOS18H<br>~~**G**~~|5, 6<br>~~**G**e~~|1.8<br>~~e~~|1.8<br>~~GO~~|
|LVCMOS15¹,²<br>~~**G**~~|0, 2, 3, 4, 7, 8, 9<br>~~**G**e~~|1.2, 1.5, 1.8, 2.5, 3.3<br>~~e~~<br>~~G~~|1.5<br>~~GO~~<br>~~G~~|
|LVCMOS15H¹<br>~~GG~~|5, 6<br>~~GG~~|1.5, 1.8<br>~~GG~~|1.5<br>~~GG~~|
|LVCMOS12¹,²<br>~~GG~~|0, 2, 3, 4, 7, 8, 9<br>~~GG~~|1.2, 1.5, 1.8, 2.5, 3.3<br>~~GG~~|1.2<br>~~GG~~|
|LVCMOS12H¹<br>~~DO~~|5, 6<br>~~DO~~|1.2, 1.357, 1.5, 1.8<br>~~DO~~|1.2<br>~~DO~~|
|LVCMOS10¹<br>~~DO~~<br>~~GG~~|0, 2, 3, 4, 7, 8, 9<br>~~DO~~<br>~~GG~~|1.2, 1.5, 1.8, 2.5, 3.3<br>~~DO~~<br>~~GG~~|—<br>~~DO~~<br>~~GG~~|
|LVCMOS10H¹<br>~~GG~~|5, 6<br>~~GG~~|1.0, 1.2, 1.357, 1.5, 1.8<br>~~GG~~|1.0<br>~~GG~~|
|LVCMOS10R¹<br>~~GG~~|5, 6<br>~~GG~~|1.0, 1.2, 1.357, 1.5, 1.8<br>~~GG~~|—<br>~~GG~~|
|SSTL135_I, SSTL135_II3|5, 6|1.357|1.35|
|SSTL15_I, SSTL15_II3<br>~~GOO~~|5, 6<br>~~GOO~~|1.58<br>~~GOO~~|1.58<br>~~GOO~~|
|HSTL15_I3<br>~~GOO~~<br>~~GG~~|5, 6<br>~~GOO~~<br>~~GG~~|1.58<br>~~GOO~~<br>~~GG~~|1.58<br>~~GOO~~<br>~~GG~~|
|HSUL123<br>~~GG~~|5, 6<br>~~GG~~|1.2<br>~~GG~~|1.2<br>~~GG~~|
|MIPI D-PHY LP Input6<br>~~DG~~|5, 6<br>~~DG~~|1.2<br>~~DG~~|1.2<br>~~DG~~|
|**Differential**||||
|LVDS<br>~~GOO~~|5, 6<br>~~GOO~~|1.2, 1.35, 1.5, 1.8<br>~~GOO~~|1.8<br>~~GOO~~|
|LVDSE5<br>~~GOO~~<br>~~GG~~|0, 2, 3, 4, 7, 8, 9<br>~~GOO~~<br>~~GG~~|—<br>~~GOO~~<br>~~GG~~|2.5<br>~~GOO~~<br>~~GG~~|
|subLVDS<br>~~GG~~<br>~~a~~|5, 6<br>~~GG~~|1.2, 1.35, 1.5, 1.8<br>~~GG~~|—<br>~~GG~~|
|subLVDSE5<br>~~a~~|0, 2, 3, 4, 7, 8, 9|—|1.8|
|subLVDSEH5<br>~~a~~<br>~~a~~<br>~~**G**~~|5, 6<br>~~**G**e~~|—<br>~~e~~|1.8<br>~~GO~~|
|SLVS6<br>~~a~~<br>~~**G**~~|5, 6<br>~~**G**e~~|1.0, 1.2, 1.357, 1.5, 1.84<br>~~e~~|1.2, 1.357, 1.5, 1.84<br>~~GO~~|
|MIPI D-PHY6<br>~~**G**~~|5, 6<br>~~**G**e~~|1.2<br>~~e~~<br>~~G~~|1.2<br>~~GO~~<br>~~G~~|
|LVCMOS33D5<br>~~a~~|0, 1, 2, 3, 4, 7, 8, 9|—|3.3|
|LVTTL33D5<br>~~a~~<br>~~GOO~~|0, 1, 2, 3, 4, 7, 8, 9<br>~~GOO~~|—<br>~~GOO~~|3.3<br>~~GOO~~|
|LVCMOS25D5<br>~~GOO~~<br>~~GOO~~<br>~~**G**~~|0, 2, 3, 4, 7, 8, 9<br>~~GOO~~<br>~~GOO~~<br>~~**G**e~~|—<br>~~GOO~~<br>~~GOO~~<br>~~e~~|2.5<br>~~GOO~~<br>~~GOO~~<br>~~GO~~|
|SSTL135D_I, SSTL135D_II5<br>~~GOO~~<br>~~**G**~~|5, 6<br>~~GOO~~<br>~~**G**e~~|—<br>~~GOO~~<br>~~e~~|1.357<br>~~GOO~~<br>~~GO~~|
|SSTL15D_I, SSTL15D_II5<br>~~**G**~~|5, 6<br>~~**G**e~~|—<br>~~e~~<br>~~G~~|1.5<br>~~GO~~<br>~~G~~|
|HSTL15D_I5<br>~~a~~|5, 6|—|1.5|
|HSUL12D5<br>~~a~~<br>~~DFO~~|5, 6<br>~~DFO~~|—<br>~~DFO~~|1.2<br>~~DFO~~|



**Notes** : 

1. Single-ended input can mix into I/O Banks with VCCIO different from the standard requires due to some of these input standards use internal supply voltage source (VCC, VCCAUX) to power the input buffer, which makes them to be independent of VCCIO voltage. For more details, please refer to sysI/O User Guide for Nexus Platform (FPGA-TN-02067). The following is a brief guideline to follow: 

   - a. Weak pull-up on the I/O must be set to OFF. 

   - b. Bank 5 and Bank 6 I/O can only mix into banks with VCCIO higher than the pin standard, due to clamping diode on the pin in these banks. Bank 0, Bank 1, Bank 2, Bank 3, Bank 4, Bank 7, Bank 8 and Bank 9 does not have this restriction. 

   - c. LVCMOS25 uses VCCIO supply on input buffer in Bank 0, Bank 1, Bank 2, Bank 3, Bank 4, Bank 7, Bank 8 and Bank 9. It can be supported with VCCIO = 3.3 V to meet the VIH and VIL requirements, but there is additional current drawn on VCCIO. Hysteresis has to be disabled when using 3.3 V supply voltage. 

   - d. LVCMOS15 uses VCCIO supply on input buffer in Bank 5 and Bank 6. It can be supported with VCCIO = 1.8 V to meet the VIH and VIL requirements, but there is additional current drawn on VCCIO. 

© 2021-2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

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68 

**MachXO5-NX Family Data Sheet** 

2. Single-ended LVCMOS inputs can mixed into I/O Banks with different VCCIO, providing weak pull-up is not used. For additional information on Mixed I/O in Bank VCCIO, refer to  sysI/O User Guide for Nexus Platform (FPGA-TN-02067) **.** 

3. These inputs use differential input comparator in Bank 5 and Bank 6. The differential input comparator uses VCCAUXH power supply. These inputs require the VREF pin to provide the reference voltage in the Bank. Refer to  sysI/O User Guide for Nexus Platform (FPGA-TN-02067) for details **.** 

4. All differential inputs use differential input comparator in Bank 5 and Bank 6. The differential input comparator uses VCCAUXH power supply. There is no differential input signaling supported in Bank 0, Bank 1, Bank 2, Bank 3, Bank 4, Bank 7, Bank 8 and Bank 9. 

5. These outputs are emulating differential output pair with single-ended output drivers with true and complement outputs driving on each of the corresponding true and complement output pair pins. The common mode voltage, VCM, is ½  × VCCIO. Refer to sysI/O User Guide for Nexus Platform (FPGA-TN-02067) for details **.** 

6. Soft MIPI D-PHY HS using sysI/O is supported with SLVS input and output that can be placed in banks with VCCIO voltage shown in SLVS. D-PHY with HS and LP modes supported needs to be placed in banks with VCCIO voltage = 1.2 V. Soft MIPI D-PHY LP input and output using sysI/O are supported with LVCMOS12. 

7. VCCIO = 1.35 V is only supported in Bank 5 and Bank 6, for use with DDR3L interface in the bank. These Input and Output standards can fit into the same bank with the VCCIO = 1.35 V. 

8. LVCMOS15 input uses VCCIO supply voltage. If VCCIO is 1.8 V, the DC levels for LVCMOS15 are still met, but there could be increase in input buffer current. 

## **3.12. sysI/O Single-Ended DC Electrical Characteristics[3]** 

|**Input/Output Standard**<br>~~es~~<br>~~po~~|**VIL¹ **<br>~~es~~<br>~~s~~|**VIL¹ **<br>~~es~~<br>~~s~~|**VIH¹ **<br>~~es~~|**VIH¹ **<br>~~es~~|**VOL Max (V)**|**VOH Min² (V)**|**IOL(mA)**|**IOH(mA)**|
|---|---|---|---|---|---|---|---|---|
||**Min(V)**<br>~~es~~<br>~~s~~<br>~~Ep~~|**Max(V)**<br>~~es~~<br>~~Ep~~|**Min(V)**<br>~~es~~|**Max(V)**<br>~~es~~|||||
|LVTTL33<br>LVCMOS33<br>~~es~~<br>~~po~~<br>~~es~~|—<br>~~s~~<br>~~Ep~~|0.8<br>~~Ep~~|2.0|3.4655|0.4|VCCIO– 0.4|4, 8, 12,<br>“50RS”3|–4, –8,<br>–12,<br>“50RS”3|
||—<br>~~s~~<br>~~Ep~~|0.8<br>~~Ep~~|2.0|3.4655|0.4|2.4|2|–2|
||—<br>~~Ep~~<br>~~es~~|0.8<br>~~Ep~~<br>~~es~~|2.0<br>~~es~~|3.4655<br>~~es~~|0.49<br>~~es~~|VCCIO– 0.58<br>~~es~~|16<br>~~es~~|–16<br>~~es~~|
|LVCMOS25<br>~~po ~~<br>~~es~~<br>~~|~~|—<br> ~~Ep~~<br>~~es~~<br>~~ff~~|0.7<br>~~Ep~~<br>~~es~~<br>~~ff~~|1.7<br>~~es~~<br>~~ff~~|3.4655<br>~~es~~|0.4<br>~~es~~|VCCIO– 0.45<br>~~es~~|2, 4, 8, 10,<br>“50RS”3<br>~~es~~|–2, –4, –8,<br>–10,<br>“50RS”3<br>~~es~~|
|LVCMOS18<br>~~|~~<br>~~rs es~~|—<br>~~ff~~<br>~~es~~|0.35 × VCCIO<br>~~ff~~<br>~~rs~~|0.65 × VCCIO<br>~~ff~~<br>~~rrr)~~|3.4655<br>~~rs~~|0.4<br>~~(~~|VCCIO– 0.45|2, 4, 8,<br>“50RS”3|–2, –4, –8,<br>“50RS”3|
|LVCMOS15<br>~~| ~~<br>~~rs es~~<br>~~Po~~<br>~~rti—‘<‘i~~|—<br> ~~ff~~<br>~~es~~<br>~~rti—‘<‘i~~|0.35 × VCCIO<br>~~ff~~<br>~~rs~~|0.65 × VCCIO<br>~~ff~~<br>~~rrr)~~|3.4655<br>~~rs~~|0.4<br>~~(~~|VCCIO– 0.4|2, 4|–2, –4|
|LVCMOS12<br>~~rs es~~<br>~~Po~~<br>~~rti—‘<‘i~~<br>~~Po~~<br>~~r—(_isd~~|—<br>~~es~~<br>~~rti—‘<‘i~~<br>~~r—(_isd~~|0.35 × VCCIO<br>~~rs ~~|0.65 × VCCIO<br> ~~rrr)~~|3.4655<br>~~rs~~|0.4<br>~~(~~|VCCIO– 0.4|2, 4|–2, –4|
|LVCMOS10<br>~~Po~~<br>~~rti—‘<‘i~~<br>~~Po~~<br>~~r—(_isd~~|—<br>~~rti—‘<‘i~~<br>~~r—(_isd~~|0.35 × VCCIO|0.65 × VCCIO|3.4655|No O/P Support||||



**Notes** : 

1. VCCIO for input level refers to the supply rail level associated with a given input standard. 

2. VCCIO for the output levels refer to the VCCIO of the CertusPro-NX device. 

3. Selecting “50RS” in driver strength is to select 50 Ω series impedance driver. 

4. For electro-migration, the combined DC current sourced or sinked by I/O pads between two consecutive VCCIO or GND pad connections, or between the last VCCIO or GND in an I/O bank and the end of an I/O bank, as shown in the Logic Signal Connections table (also shown as I/O grouping) shall not exceed a maximum of n × 8 mA. _n_ is the number of I/O pads between the two consecutive bank VCCIO or GND connections or between the last VCCIO and GND in a bank and the end of a bank. I/O Grouping can be found in the Data Sheet Pin Summary Tables, which can also be generated from the Lattice Radiant software. 

5. If the input clamp is OFF, VIH (Max) in Banks 0, 1, 2, 3, 4, 7, 8, and 9 can go up to 3.465 V. Otherwise, the input voltage cannot be higher than VCCIO + 0.3 V. 

© 2021-2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

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**MachXO5-NX Family Data Sheet** 

|**Input/Output Standard**<br>~~rece~~<br>~~ee~~|**VIL¹ **<br>~~a~~<br>~~rece~~<br>|**VIL¹ **<br>~~a~~<br>~~rece~~<br>|**VIH¹ **<br>~~a~~<br>~~rece~~<br>~~ees eee~~<br>|**VIH¹ **<br>~~a~~<br>~~rece~~<br>~~ees eee~~<br>|**VOL Max (V)**<br>~~rece~~<br>|**VOH Min² (V)**<br>~~rece~~<br><br>~~eee~~|**IOL (mA)**<br>~~rece~~<br><br>~~eee~~|**IOH (mA)**<br>~~rece~~<br><br>~~eee~~|
|---|---|---|---|---|---|---|---|---|
||**Min(V)**<br>~~rece~~<br><br>~~ee~~|**Max(V)**<br>~~rece~~<br>|**Min(V)**<br>~~rece~~<br>~~ees eee~~<br>|**Max(V)**<br>~~rece~~<br>~~eee~~<br>|||||
|LVCMOS18H<br>~~ee~~|—<br>~~eee~~<br>~~ee~~|0.35 × VCCIO <br>~~eee~~|0.65 × VCCIO<br>~~ees eee~~<br>~~eee~~|VCCIO+ 0.3<br>~~eee~~<br>~~eee~~|0.4<br>~~eee~~|VCCIO– 0.45<br>~~eee~~<br>~~eee~~|2, 4, 8,<br>12<br>~~eee~~<br>~~eee~~|–2, –4, –8,<br>–12<br>~~eee~~<br>~~eee~~|
||—<br><br>~~ee~~|0.35 × VCCIO <br>|0.65 × VCCIO<br>~~ees eee~~<br>|VCCIO+ 0.3<br>~~eee~~<br>|0.4<br>|VCCIO– 0.53<br><br>~~eee~~|“50RS”3<br><br>~~eee~~|“50RS”3<br><br>~~eee~~|
|LVCMOS15H<br>~~ee~~<br>~~a~~<br>~~ee~~|—<br><br>~~ee~~<br>~~a~~|0.35 × VCCIO <br><br>~~a~~|0.65 × VCCIO<br>~~ees eee~~<br><br>~~a~~|VCCIO+ 0.3<br>~~eee~~<br><br>~~a~~|0.4<br><br>~~a~~|VCCIO– 0.4<br><br>~~eee~~<br>~~a~~|2, 4, 8<br><br>~~eee~~<br>~~a~~|–2, –4, –8<br><br>~~eee~~<br>~~a~~|
|LVCMOS12H<br>~~ee~~|—|0.35 × VCCIO|0.65 × VCCIO<br>~~ee~~|VCCIO+ 0.3<br>~~ee~~|0.4<br>~~eee~~|VCCIO– 0.4<br>~~eee~~|2, 4, 8<br>~~eee~~|–2, –4, –8<br>~~eee~~|
|LVCMOS10H<br>~~ee~~<br>~~cee~~|—<br>~~cee~~|0.35 × VCCIO <br>~~cee~~|0.65 × VCCIO<br>~~cee~~<br>~~ee~~|VCCIO+ 0.3<br>~~cee~~<br>~~ee~~|0.27 × VCCIO<br>~~cee~~<br>~~eee~~|0.64 × VCCIO<br>~~cee~~<br>~~eee~~|2<br>~~cee~~<br>~~eee~~|–2<br>~~cee~~<br>~~eee~~|
||—<br>~~cee~~<br>~~a~~|0.35 × VCCIO <br>~~cee~~<br>~~a~~|0.65 × VCCIO<br>~~cee~~<br>~~ee~~<br>~~a~~|VCCIO+ 0.3<br>~~cee~~<br>~~ee~~<br>~~a~~|0.27 × VCCIO<br>~~cee~~<br>~~eee~~<br>~~a~~|0.75 × VCCIO<br>~~cee~~<br>~~eee~~<br>~~a~~|4<br>~~cee~~<br>~~eee~~<br>~~a~~|–4<br>~~cee~~<br>~~eee~~<br>~~a~~|
|SSTL15_I<br>~~a~~|—<br>~~a~~|VREF– 0.10<br>~~a~~|VREF+ 0.1<br>~~ee ~~<br>~~a~~|VCCIO+ 0.3<br> ~~ee ~~<br>~~a~~|0.30<br> ~~eee~~<br>~~a~~|VCCIO– 0.30<br>~~eee~~<br>~~a~~|7.5<br>~~eee~~<br>~~a~~|–7.5<br>~~eee~~<br>~~a~~|
|SSTL15_II<br>~~a~~|—<br>~~a~~|VREF– 0.10<br>~~a~~|VREF+ 0.1<br>~~a~~|VCCIO+ 0.3<br>~~a~~|0.30<br>~~a~~|VCCIO– 0.30<br>~~a~~|8.8<br>~~a~~|–8.8<br>~~a~~|
|HSTL15_I<br>~~a~~|—<br>~~a~~|VREF– 0.10<br>~~a~~|VREF+ 0.16<br>~~a~~|VCCIO+ 0.3<br>~~a~~|0.40<br>~~a~~|VCCIO– 0.40<br>~~a~~|8<br>~~a~~|–8<br>~~a~~|
|SSTL135_I<br>~~a~~|—<br>~~a~~|VREF– 0.09<br>~~a~~|VREF+ 0.09<br>~~a~~|VCCIO+ 0.3<br>~~a~~|0.27<br>~~a~~|VCCIO – 0.27<br>~~a~~|6.75<br>~~a~~|–6.75<br>~~a~~|
|SSTL135_II<br>~~a~~|—<br>~~a~~|VREF– 0.09<br>~~a~~|VREF+ 0.09<br>~~a~~|VCCIO+ 0.3<br>~~a~~|0.27<br>~~a~~|VCCIO– 0.27<br>~~a~~|8<br>~~a~~|–8<br>~~a~~|
|LVCMOS10R<br>~~a~~<br>~~a~~|—<br>~~a~~<br>~~a~~|VREF– 0.10<br>~~a~~<br>~~a~~|VREF+ 0.10<br>~~a~~<br>~~a~~|VCCIO+ 0.3<br>~~a~~<br>~~a~~|—<br>~~a~~<br>~~a~~|—<br>~~a~~<br>~~a~~|—<br>~~a~~<br>~~a~~|—<br>~~a~~<br>~~a~~|
|HSUL12<br>~~a~~<br>~~a~~|—<br>~~a~~<br>~~a~~<br>~~ee~~|VREF– 0.10<br>~~a~~<br>~~a~~<br>~~ee~~|VREF+ 0.10<br>~~a~~<br>~~a~~<br>~~ee~~|VCCIO+ 0.3<br>~~a~~<br>~~a~~<br>~~ee~~|0.3<br>~~a~~<br>~~a~~<br>~~ee~~|VCCIO– 0.3<br>~~a~~<br>~~a~~<br>~~ee~~|8.0, 7.5,<br>6.25, 5<br>~~a~~<br>~~a~~<br>~~ee~~|–8.0, –7.5,<br>–6.25, –5<br>~~a~~<br>~~a~~<br>~~ee~~|



3. Select “50RS” in driver strength is selecting the 50Ω series impedance driver. 

4. For electro-migration, the combined DC current sourced or sinked by I/O pads between two consecutive VCCIO or GND pad connections, or between the last VCCIO or GND in an I/O bank and the end of an I/O bank, as shown in the Logic Signal Connections table (also shown as I/O grouping) shall not exceed a maximum of n × 8 mA. n is the number of I/O pads between the two consecutive bank VCCIO or GND connections or between the last VCCIO and GND in a bank and the end of a bank. I/O Grouping can be found in the Data Sheet Pin Summary Tables, which can also be generated from the Lattice Radiant software. 

**Table 3.17. I/O Resistance Characteristics (Over Recommended Operating Conditions)** 

|**Parameter**|**Description**|**Test Conditions**|**Min**|**Typ**|**Max**|**Unit**|
|---|---|---|---|---|---|---|
|50RS|Output Drive Resistance when 50RS<br>Drive Strength Selected|VCCIO= 1.8 V, 2.5 V, or 3.3 V|—|50|—|Ω|
|RDIFF|Input Differential Termination<br>Resistance|Bank 5 and Bank 6 for I/O selected to<br>be differential|—|100|—|Ω|
|SE Input<br>Termination|Input Single Ended Termination<br>Resistance|Bank 5 and Bank 6 for I/O selected to<br>be Single Ended|36|40|64|Ω|
||||46|50|80||
||||56|60|96||
||||65|75|120||



© 2021-2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02102-1.7 

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**MachXO5-NX Family Data Sheet** 

**Table 3.18. VIN Maximum Overshoot/Undershoot Allowance – Wide Range[1,2]** 

|**AC Voltage Overshoot**|**% of UI at –40 °C to 100 °C**|**AC Voltage Undershoot**|**% of UI at –40 °C to 100 °C**|
|---|---|---|---|
|VCCIO+ 0.4|100.0%|–0.4|100.0%|
|VCCIO+ 0.5|100.0%|–0.5|44.2%|
|VCCIO+ 0.6|94.0%|–0.6|10.1%|
|VCCIO+ 0.7|21.0%|–0.7|1.3%|
|VCCIO+ 0.8|10.2%|–0.8|0.3%|
|VCCIO+ 0.9|2.5%|–0.9|0.1%|



**Notes** : 

The peak overshoot or undershoot voltage and the duration above VCCIO + 0.2 V or below GND – 0.2 V must not exceed the values in this table. 

For UI less than 20 µs. 

**Table 3.19. VIN Maximum Overshoot/Undershoot Allowance – High Performance[1,2]** 

|**AC Voltage Overshoot**|**% of UI at –40 °C to 100 °C**|**AC Voltage Undershoot**|**% of UI at –40 °C to 100 °C**|
|---|---|---|---|
|VCCIO+ 0.5|100.0%|–0.5|100.0%|
|VCCIO+ 0.6|47.3%|–0.6|47.3%|
|VCCIO+ 0.7|10.9%|–0.7|10.9%|
|VCCIO+ 0.8|2.7%|–0.8|2.7%|
|VCCIO+ 0.9|0.7%|–0.9|0.7%|



**Notes** : 

1. The peak overshoot or undershoot voltage and the duration above VCCIO + 0.2 V or below GND – 0.2 V must not exceed the values in this table. 

2. For UI less than 20 µs. 

## **3.13. sysI/O Differential DC Electrical Characteristics** 

## **3.13.1. LVDS** 

LVDS input buffer on MachXO5-NX is powered by VCCAUX = 1.8 V, and protected by the bank VCCIO. Therefore, the LVDS input voltage cannot exceed the bank VCCIO voltage. LVDS output buffer is powered by the Bank VCCIO at 1.8 V. 

LVDS can only be supported in Bank 5 and Bank 6. LVDS25 output can be emulated with LVDS25E in Bank 0, Bank 1, Bank 2, Bank 3, Bank 4, Bank 7, Bank 8 and Bank 9. This is described in LVDS25E (Output Only) section. 

**Table 3.20. LVDS DC Electrical Characteristics (Over Recommended Operating Conditions)[1 ]** 

|**Parameter**<br>~~QO~~|**Description**<br>~~QO~~|**Test Conditions**<br>~~QO~~|**Min**<br>~~QO~~|**Typ**<br>~~QO~~|**Max**<br>~~QO~~|**Unit**<br>~~QO~~|
|---|---|---|---|---|---|---|
|VINP, VINM<br>~~CO~~|Input Voltage<br>~~CO~~|—<br>~~CO~~|0<br>~~CO~~|—<br>~~CO~~<br>~~GO~~|1.603<br>~~CO~~|V<br>~~CO~~|
|VICM<br>~~a~~|Input Common Mode Voltage<br>~~GG~~|Half the sum of the two Inputs<br>~~GG~~|0.05<br>~~GG~~|—<br>~~GG~~<br>~~GO~~|1.55Z<br>~~GG~~|V<br>~~GG~~|
|VTHD<br>~~a~~<br>~~OO~~|Differential Input Threshold<br>~~GG~~<br>~~OO~~|Difference between the two Inputs<br>~~GG~~<br>~~OO~~|±100<br>~~GG~~<br>~~OO~~|—<br>~~GG~~<br>~~GO~~<br>~~OO~~|—<br>~~GG~~<br>~~OO~~|mV<br>~~GG~~<br>~~OO~~|
|IIN<br>~~OO~~<br>~~GO~~|Input Current<br>~~OO~~<br>~~GO~~|Power On or Power Off<br>~~OO~~<br>~~GO~~|—<br>~~OO~~<br>~~GO~~|—<br>~~OO~~<br>~~GO~~|±10<br>~~OO~~<br>~~GO~~|µA<br>~~OO~~<br>~~GO~~|
|VOH<br>~~GO~~<br>~~a~~|Output High Voltage for VOPor VOM<br>~~GO~~<br>|RT= 100 Ω<br>~~GO~~<br>|—<br>~~GO~~<br>~~GO~~<br>|1.425<br>~~GO~~<br>~~GO~~<br>|1.60<br>~~GO~~<br>|V<br>~~GO~~<br>|
|VOL<br>~~sO~~<br>~~a~~|Output Low Voltage for VOPor VOM<br>~~sO~~<br>|RT= 100 Ω<br>~~sO~~<br>|0.9<br>~~sO~~<br>~~GO~~<br>|1.075<br>~~sO~~<br>~~GO~~<br>|—<br>~~sO~~<br>|V<br>~~sO~~<br>|
|VOD<br>~~a GGG~~|Output Voltage Differential<br>~~GGG~~|(VOP- VOM), RT= 100 Ω<br>~~GGG~~|250<br>~~GO~~<br>~~GGG~~|350<br>~~GO~~<br>~~GGG~~|450<br>~~GGG~~|mV<br>~~GGG~~|
|VOD<br>~~a GGG~~<br>~~a~~|Change in VODBetween High and<br>Low<br>~~GGG~~<br>|—<br>~~GGG~~<br>|—<br>~~GO~~<br>~~GGG~~<br>|—<br>~~GO~~<br>~~GGG~~<br>|50<br>~~GGG~~<br>|mV<br>~~GGG~~<br>|
|VOCM<br>~~aOO~~|Output Common Mode Voltage<br>~~OO~~|(VOP+ VOM)/2, RT= 100 Ω<br>~~OO~~|1.125<br>~~OO~~|1.25<br>~~OO~~|1.375<br>~~OO~~|V<br>~~OO~~|
|VOCM<br>~~OO~~<br>~~a~~|Change in VOCM, VOCM(MAX)- VOCM(MIN)<br>~~OO~~<br>~~a~~|—<br>~~OO~~<br>~~a~~|—<br>~~OO~~<br>~~a~~|—<br>~~OO~~<br>~~a~~|50<br>~~OO~~<br>~~a~~|mV<br>~~OO~~<br>~~a~~|
|ISAB<br>~~a~~<br>~~a~~|Output Short Circuit Current<br>~~a~~<br>~~a~~|VOD= 0 V Driver outputs shorted to<br>each other<br>~~a~~<br>~~a~~|—<br>~~a~~<br>~~a~~|—<br>~~a~~<br>~~a~~|12<br>~~a~~<br>~~a~~|mA<br>~~a~~<br>~~a~~|



© 2021-2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02102-1.7 

71 

**MachXO5-NX Family Data Sheet** 

|**Parameter**|**Description**|**Test Conditions**|**Min**|**Typ**|**Max**|**Unit**|
|---|---|---|---|---|---|---|
|VOS|Change in VOSbetween H and L|—|—|—|50|mV|



## **Notes** : 

1. LVDS input or output are supported in Bank 5, and Bank 6. LVDS input uses VCCAUX on the differential input comparator, and can be located in any VCCIO voltage bank. LVDS output uses VCCIO on the differential output driver, and can only be located in bank with VCCIO = 1.8 V. 

2. VICM is depending on VID, input differential voltage, so the voltage on pin cannot exceed VINP/INM(min/max) requirements. VICM(min) = VINP/INM(min) + ½  VID, VICM(max) = VINP/INM(max) – ½  VID. Values in the table is based on minimum VID of +/- 100 mV. 

3. VINP and VINM(max) must be less than or equal to VCCIO in all cases. 

## **3.13.2. LVDS25E (Output Only)** 

Three sides of the MachXO5-NX devices, Top, Left and Right, support LVDS25 outputs with emulated complementary LVCMOS outputs in conjunction with a parallel resistor across the driver outputs. The scheme shown in Figure 3.2 is one possible solution for point-to-point signals. 

**Table 3.21. LVDS25E DC Conditions** 

|**Parameter**<br>~~a~~|**Description**<br>~~OO~~|**Typical**<br>~~OO~~|**Unit**<br>~~OO~~|
|---|---|---|---|
|VCCIO<br>~~a ~~<br>~~Ge~~|Output Driver Supply (±5%)<br> ~~OO~~<br>~~Ge~~|2.50<br>~~OO~~<br>~~Ge~~|V<br>~~OO~~<br>~~Ge~~|
|ZOUT<br>~~Ge~~<br>~~Ge~~<br>~~ee~~|Driver Impedance<br>~~Ge~~<br>~~Ge~~<br>~~eC~~|20<br>~~Ge~~<br>~~Ge~~<br>~~eC~~|Ω<br>~~Ge~~<br>~~Ge~~<br>~~eC~~|
|RS<br>~~ee~~|Driver Series Resistor (±1%)<br>~~eC~~|158<br>~~eC~~|Ω<br>~~eC~~|
|RP<br>~~ee~~<br>~~Ge~~|Driver Parallel Resistor (±1%)<br>~~eC~~<br>~~Ge~~|140<br>~~eC~~<br>~~Ge~~|Ω<br>~~eC~~<br>~~Ge~~|
|RT<br>~~Ge~~<br>~~ee~~|Receiver Termination (±1%)<br>~~Ge~~<br>~~eC~~|100<br>~~Ge~~<br>~~eC~~|Ω<br>~~Ge~~<br>~~eC~~|
|VOH<br>~~ee~~|Output High Voltage<br>~~eC~~|1.43<br>~~eC~~|V<br>~~eC~~|
|VOL<br>~~ee~~<br>~~Ge~~<br>~~ee~~|Output Low Voltage<br>~~eC~~<br>~~Ge~~<br>~~eC~~|1.07<br>~~eC~~<br>~~Ge~~<br>~~eC~~|V<br>~~eC~~<br>~~Ge~~<br>~~eC~~|
|VOD<br>~~ee~~|Output Differential Voltage<br>~~eC~~|0.35<br>~~eC~~|V<br>~~eC~~|
|VCM<br>~~ee~~<br>~~Ge~~|Output Common Mode Voltage<br>~~eC~~<br>~~Ge~~|1.25<br>~~eC~~<br>~~Ge~~|V<br>~~eC~~<br>~~Ge~~|
|ZBACK<br>~~Ge~~<br>~~Ce~~|Back Impedance<br>~~Ge~~|100.5<br>~~Ge~~|Ω<br>~~Ge~~|
|IDC<br>~~Ce~~|DC Output Current|6.03|mA|



VCCIO = 2.5 V ( ± 5%) 

**==> picture [428 x 127] intentionally omitted <==**

**----- Start of picture text -----**<br>
RS = 158<br>|  ( ±  1%)<br>8 mA<br>LVCMOS25 | [1]<br>| Ss > I +<br>VCCIO = 2.5 V ( ±  5%) RP = 140  RT = 100<br>| RS = 158  S  ( ±  1%)  ( ±  1%)<br>|  ( ±  1%) [1]<br>8 mA<br>LVCMOS25<br>| Transmission line, Zo = 100    differential<br>ON-chip | OFF-chip OFF-chip [1] ON-chip<br>**----- End of picture text -----**<br>


**Figure 3.2. LVDS25E Output Termination Example** 

## **3.13.3. SubLVDS (Input Only)** 

SubLVDS is a reduced-voltage form of LVDS signaling, very similar to LVDS. It is a standard used in many camera types of applications. Similar to LVDS, the MachXO5-NX devices can support the subLVDS input signaling with the same LVDS input buffer. The output for subLVDS is implemented in subLVDSE/subLVDSEH with a pair of LVCMOS18 output drivers. See SubLVDSE/SubLVDSEH (Output Only) section. 

© 2021-2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02102-1.7 

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**MachXO5-NX Family Data Sheet** 

**Table 3.22. SubLVDS Input DC Electrical Characteristics (Over Recommended Operating Conditions)** 

|**Parameter**|**Description**|**Test Conditions**|**Min**|**Typ**|**Max**|**Unit**|
|---|---|---|---|---|---|---|
|VID|Input Differential Threshold Voltage|Over VICMrange|70|150|200|mV|
|VICM|Input Common Mode Voltage|Half the sum of the two Inputs|0.4|0.9|1.41|V|



**Note** : 

**==> picture [471 x 291] intentionally omitted <==**

**----- Start of picture text -----**<br>
1. VICM + ½ VID cannot exceed the bank VCCIO in all cases.<br>Sub-LVDS Driver PCB Traces, Connectors or Cables<br>Z0 = 50<br>+ +<br>RT = 100<br>100    differential ±  1%*<br>– –<br>Z0 = 50<br>SEED<br>Off-chip On-chip<br>Figure 3.3. SubLVDS Input Interface<br>3.13.4. SubLVDSE/SubLVDSEH (Output Only)<br>SubLVDS output uses a pair of LVCMOS18 drivers with True and Complement outputs.  The VCCIO of the<br>bank used for subLVDSE or subLVDSEH needs to be powered by 1.8 V. SubLVDSE is for Bank 0, Bank 1,<br>Bank 2, Bank 3, Bank 4, Bank 7, Bank 8 and Bank 9; and subLVDSEH is for Bank 5 and Bank 6.<br>**----- End of picture text -----**<br>


Performance of the subLVDSE/subLVDSEH driver is limited to the performance of LVCMOS18. 

|**Parameter**<br>~~pr~~|**Description**<br>~~pr~~|**Test Conditions**<br>~~pr~~|**Min**<br>~~pr~~|**Typ**<br>~~pr~~|**Max**<br>~~pr~~|**Unit**<br>~~pr~~|
|---|---|---|---|---|---|---|
|VOD<br>~~pr~~|Output Differential Voltage Swing<br>~~pr~~|—<br>~~pr~~|—<br>~~pr~~|150<br>~~pr~~|—<br>~~pr~~|mV<br>~~pr~~|
|VOCM<br>~~pr~~|Output Common Mode Voltage<br>~~pr~~|Half the sum of the two Outputs<br>~~pr~~|—<br>~~pr~~|0.9<br>~~pr~~|—<br>~~pr~~|V<br>~~pr~~|



© 2021-2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02102-1.7 

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**MachXO5-NX Family Data Sheet** 

**==> picture [433 x 181] intentionally omitted <==**

**----- Start of picture text -----**<br>
VCCIO = +1.8 V PCB Traces, Connectors or Cables<br>Z0 = 50<br>Rs = 267   ±1%<br>+ +<br>aaa<br>SubLVDS Output<br>SubLVDSE Rp = 121   ±1% 100    differential RT  = 100   ±1% Sub-LVDS Recevier<br>SubLVDSEH<br>– –<br>Rs = 267   ±1%<br>Z0 = 50<br>0<br>On-chip Off-chip On-chip Off-chip<br>**----- End of picture text -----**<br>


**Figure 3.4. SubLVDS Output Interface** 

## **3.13.5. SLVS** 

Scalable Low-Voltage Signaling (SLVS) is based on a point-to-point signaling method defined in the JEDEC JESD8-13 (SLVS-400) standard. This standard evolved from the traditional LVDS standard with smaller voltage swings and a lower common-mode voltage. The 200 mV (400 mV p-p) SLVS swing contributes to a reduction in power. 

The MachXO5-NX devices receive SLVS differential input with the LVDS input buffer. This LVDS input buffer is designed to cover wide input common mode range that can meet the SLVS input standard specified by the JEDEC standard. 

**Table 3.24. SLVS Input DC Characteristics (Over Recommended Operating Conditions)** 

|**Parameter**|**Description**|**Test Conditions**|**Min**|**Typ**|**Max**|**Unit**|
|---|---|---|---|---|---|---|
|VID|Input Differential Threshold Voltage|Over VICMrange|70|—|—|mV|
|VICM|Input Common Mode Voltage|Half the sum of the two Inputs|70|200|330|mV|



The SLVS output on the MachXO5-NX device is supported with the LVDS drivers found in Bank 5 and Bank 6. The LVDS driver on the MachXO5-NX device is a current controlled driver. It can be configured as LVDS driver, or configured with the 100 Ω differential termination with center-tap set to VOCM at 200 mV. This means the differential output driver can be placed into bank with VCCIO = 1.2 V, 1.5 V, or 1.8 V, even if it is powered by VCCIO. 

© 2021-2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02102-1.7 

74 

**MachXO5-NX Family Data Sheet** 

**Table 3.25. SLVS Output DC Characteristics (Over Recommended Operating Conditions)** 

|**Parameter**|**Description**|**Test Conditions**|**Min**|**Typ**|**Max**|**Unit**|
|---|---|---|---|---|---|---|
|VCCIO|Bank VCCIO|—|–5%|1.2,<br>1.5,<br>1.8|+ 5%|V|
|VOD|Output Differential Voltage Swing|—|140|200|270|mV|
|VOCM|Output Common Mode Voltage|Half the sum of the two Outputs|150|200|250|mV|
|ZOS|Single-Ended Output Impedance|—|37.5|50|62.5|Ω|



**Figure 3.5. SLVS Interface** 

## **3.13.6. Soft MIPI D-PHY** 

When Soft D-PHY is implemented inside the FPGA logic, the I/O interface needs to use sysI/O buffers to connect to external D-PHY pins. 

The MachXO5-NX sysI/O provides support of SLVS, as described in SLVS section, plus the LVCMOS12 input / output buffers together to support the High Speed (HS) and Low Power (LP) mode as defined in MIPI Alliance Specification for D-PHY. 

To support MIPI D-PHY with SLVS (LVDS) and LVCMOS12, the bank VCCIO cannot be set to 1.5 V or 1.8 V. It has to connect to 1.2 V, or 1.1 V. 

All other DC parameters are the same as those listed in SLVS section. DC parameters for the LP driver and receiver are the same as those listed in LVCMOS12. 

© 2021-2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02102-1.7 

75 

**==> picture [449 x 460] intentionally omitted <==**

**----- Start of picture text -----**<br>
MachXO5-NX Family<br>Data Sheet<br>LVCMOS12<br>LP Data_P<br>LPenable<br>HSenable MIPI Receiver<br>100   Diff<br>+ +<br>HS Data  Z0=50<br>–  –<br>SLVS<br>= aS<br>LPenable<br>LP Data_N<br>LVCMOS12<br>hp<br>MIPI_LP_RX<br>On-Chip<br>RXLP_P<br>MIPI Divider<br>+ +<br>HS Data  Z0=50<br>–  –<br>LVDS<br>- -<br>MIPI_LP_RX<br>RXLP_N<br>=H<br>Figure 3.6. MIPI Interface<br>**----- End of picture text -----**<br>


© 2021-2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02102-1.7 

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**MachXO5-NX Family Data Sheet** 

**Table 3.26. Soft D-PHY Input Timing and Levels** 

|**Symbol**<br>~~a a~~|**Description**<br>~~a~~|**Conditions**<br>~~GG~~|**Min**<br>~~GG~~|**Typ**|**Max**|**Unit**|
|---|---|---|---|---|---|---|
|**High Speed(Differential) Input DC Specifications**|||||||
|VCMRX(DC)<br>~~a~~|Common-mode Voltage in High Speed Mode|—|70|—|330|mV|
|VIDTH<br>~~a~~|Differential Input HIGH Threshold|—|70|—|—|mV|
|VIDTL<br>~~a~~|Differential Input LOW Threshold|—|—|—|–70|mV|
|VIHHS<br>~~a~~|Input HIGH Voltage(for HS mode)|—|—|—|460|mV|
|VILHS<br>~~a~~|Input LOW Voltage|—|–40|—|—|mV|
|VTERM-EN<br>~~a~~|Single-ended voltage for HS Termination Enable4|—|—|—|450|mV|
|ZID<br>~~a~~|Differential Input Impedance<br>~~eG~~|—<br>~~eG~~|80<br>~~eG~~|100<br>~~eG~~|125<br>~~eG~~|Ω<br>~~eG~~|
|**High Speed(Differential) Input AC Specifications**<br>~~pt~~|||||||
|ΔVCMRX(HF)1<br>~~a~~|Common-mode Interference(>450 MHz)|—|—|—|100|mV|
|ΔVCMRX(LF)2, 3<br>~~a~~|Common-mode Interference(50 MHz – 450 MHz)|—|–50|—|50|mV|
|CCM<br>~~a~~|Common-mode Termination|—|||60|pF|
|**Low Power(Single-Ended) Input DC Specifications**<br>~~a~~|||||||
|VIH<br>~~a~~|Low Power Mode Input HIGH Voltage|—|740|—|—|mV|
|VIL<br>~~a~~|Low Power Mode Input LOW Voltage<br>|—<br>|—<br>|—<br>|480<br>|mV<br>|
|VIL-ULP<br>~~GG~~<br>~~ee~~|Ultra Low Power Input LOW Voltage<br>~~GG~~|—<br>~~GG~~|—<br>~~GG~~|—<br>~~GG~~|300<br>~~GG~~|mV<br>~~GG~~|
|VHYST<br>~~GG~~<br>~~ee~~|Low Power Mode Input Hysteresis<br>~~GG~~|—<br>~~GG~~|25<br>~~GG~~|—<br>~~GG~~|—<br>~~GG~~|mV<br>~~GG~~|
|℮SPIKE<br>~~ee~~<br>~~a~~|Input Pulse Rejection|—|—|—|300|V∙ps|
|TMIN-RX<br>~~a~~|Minimum Pulse Width Response|—|20|—|—|ns|
|VINT<br>~~a~~|Peak Interference Amplitude<br>|—<br>|—<br>|—<br>|200<br>|mV<br>|
|fINT<br>~~GG~~|Interference Frequency<br>~~GG~~|—<br>~~GG~~|450<br>~~GG~~|—<br>~~GG~~|—<br>~~GG~~|MHz<br>~~GG~~|



## **Notes** : 

1. This is peak amplitude of sine wave modulated to the receiver inputs. 

2. Input common-mode voltage difference compared to average common-mode voltage on the receiver inputs. 

3. Exclude any static ground shift of 50 mV. 

4. High Speed Differential RTERM is enabled when both DP and DN are below this voltage. 

© 2021-2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02102-1.7 

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**MachXO5-NX Family** 

**Data Sheet** 

**Table 3.27. Soft D-PHY Output Timing and Levels** 

|**Symbol**<br>~~GF~~|**Description**<br>~~GF~~|**Conditions**<br>~~GF~~|**Min**<br>~~GF~~|**Typ**<br>~~GF~~|**Max**<br>~~GF~~|**Unit**<br>~~GF~~|
|---|---|---|---|---|---|---|
|**High Speed(Differential) Output DC Specifications**|||||||
|VCMTX<br>~~a GO~~<br>~~a~~|Common-mode Voltage in High Speed Mode<br>~~GO~~<br>~~ee~~|—<br>~~GO~~<br>~~ee~~|150<br>~~GO~~<br>~~ee~~|200<br>~~GO~~<br>~~ee~~|250<br>~~GO~~<br>~~ee~~|mV<br>~~GO~~<br>~~ee~~|
||ΔVCMTX(1,0)|<br>~~a~~<br>~~a~~|VCMTXMismatch Between Differential HIGH<br>and LOW<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~|7<br>~~ee~~<br>~~ee~~|mV<br>~~ee~~<br>~~ee~~|
||VOD|<br>~~a~~<br>~~a~~<br>~~a~~|Output Differential Voltage<br>~~ee~~<br>~~ee~~<br>~~ee~~||D-PHY-P – D-PHY-<br>N|<br>~~ee~~<br>~~ee~~<br>~~ee~~|140<br>~~ee~~<br>~~ee~~<br>~~ee~~|200<br>~~ee~~<br>~~ee~~<br>~~ee~~|270<br>~~ee~~<br>~~ee~~<br>~~ee~~|mV<br>~~ee~~<br>~~ee~~<br>~~ee~~|
||ΔVOD|<br>~~a~~<br>~~a~~|VODMismatch Between Differential HIGH and<br>LOW<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~|25<br>~~ee~~<br>~~ee~~|mV<br>~~ee~~<br>~~ee~~|
|VOHHS<br>~~a~~<br>~~a GOO~~|Single-Ended Output HIGH Voltage<br>~~ee~~<br>~~GOO~~|—<br>~~ee~~<br>~~GOO~~|—<br>~~ee~~<br>~~GOO~~|—<br>~~ee~~<br>~~GOO~~|410<br>~~ee~~<br>~~GOO~~|mV<br>~~ee~~<br>~~GOO~~|
|ZOS<br>~~a GO~~<br>~~eeGD~~|Single Ended Output Impedance<br>~~GO~~<br>~~GD~~|—<br>~~GO~~<br>~~GD~~|37.5<br>~~GO~~<br>~~GD~~|50<br>~~GO~~<br>~~GD~~|80<br>~~GO~~<br>~~GD~~|Ω<br>~~GO~~<br>~~GD~~|
|ΔZOS<br>~~eeGD~~|ZOSmismatch<br>~~GD~~|—<br>~~GD~~|—<br>~~GD~~|—<br>~~GD~~|20<br>~~GD~~|%<br>~~GD~~|
|**High Speed(Differential) Output AC Specifications**<br>~~eeGD~~|||||||
|ΔVCMTX(LF)<br>~~GO~~|Common-Mode Variation, 50 MHz–450 MHz<br>~~GO~~|—<br>~~GO~~|—<br>~~GO~~|—<br>~~GO~~|25<br>~~GO~~|mVRMS<br>~~GO~~|
|ΔVCMTX(HF)<br>~~GO~~<br>~~a GG~~|Common-Mode Variation, above 450 MHz<br>~~GO~~<br>~~GG~~|—<br>~~GO~~<br>~~GG~~|—<br>~~GO~~<br>~~GG~~|—<br>~~GO~~<br>~~GG~~|15<br>~~GO~~<br>~~GG~~|mVRMS<br>~~GO~~<br>~~GG~~|
|tR|Output 20%–80% Rise Time<br>Output 80%–20% Fall Time|0.08 Gbps ≤ tR≤ 1.00<br>Gbps|—|—|0.30|UI|
|||1.00 Gbps < tR≤ 1.25<br>Gbps<br>~~a~~|—<br>~~eee~~|—<br>~~eee~~|0.434<br>~~eee~~|UI<br>~~eee~~|
|tF|Output Data Valid After CLK Output|0.08 Gbps ≤ tF≤ 1.00<br>Gbps<br>~~a ~~<br>~~a~~|—<br> ~~eee~~<br>~~ee~~|—<br>~~eee~~<br>~~eee~~|0.30<br>~~eee~~<br>~~eee~~|UI<br>~~eee~~<br>~~eee~~|
|||1.00 Gbps < tF≤ 1.25<br>Gbps<br>~~a~~|—<br>~~ee~~|—<br>~~eee~~|0.419<br>~~eee~~|UI<br>~~eee~~|
|**Low Power(Single-Ended) Output DC Specifications**<br>~~a~~<br>~~eeeee~~|||||||
|VOH<br>~~aee~~|Low Power Mode Output HIGH Voltage<br>~~ee~~|0.08 Gbps – 1.25<br>Gbps<br>~~ee~~|1.07<br>~~ee~~|1.2<br>~~ee~~|1.3<br>~~ee~~|V<br>~~ee~~|
|VOL<br>~~GO~~|Low Power Mode Input LOW Voltage<br>~~GO~~|—<br>~~GO~~|–50<br>~~GO~~|—<br>~~GO~~|50<br>~~GO~~|mV<br>~~GO~~|
|ZOLP<br>~~a GC~~|Output Impedance in Low Power Mode<br>~~GC~~|—<br>~~GC~~|110<br>~~GC~~|—<br>~~GC~~|—<br>~~GC~~|Ω<br>~~GC~~|
|**Low Power(Single-Ended) Output AC Specifications**|||||||
|tRLP<br>~~OO~~|15%–85% Rise Time<br>~~OO~~|—<br>~~OO~~|—<br>~~OO~~|—<br>~~OO~~|25<br>~~OO~~|ns<br>~~OO~~|
|tFLP<br>~~OO~~<br>~~a GOO~~<br>~~eeGOO~~|85%–15% Fall Time<br>~~OO~~<br>~~GOO~~<br>~~GOO~~|—<br>~~OO~~<br>~~GOO~~<br>~~GOO~~|—<br>~~OO~~<br>~~GOO~~<br>~~GOO~~|—<br>~~OO~~<br>~~GOO~~<br>~~GOO~~|25<br>~~OO~~<br>~~GOO~~<br>~~GOO~~|ns<br>~~OO~~<br>~~GOO~~<br>~~GOO~~|
|tREOT<br>~~eeGOO~~|HS – LP Mode Rise and Fall Time, 30%–85%<br>~~GOO~~|—<br>~~GOO~~|—<br>~~GOO~~|—<br>~~GOO~~|35<br>~~GOO~~|ns<br>~~GOO~~|
|TLP-PULSE-TX<br>~~eeGOO~~<br>~~a~~|Pulse Width of the LP Exclusive-OR Clock<br>~~GOO~~|First LP XOR Clock<br>Pulse after STOP<br>State or Last Pulse<br>before STOP State<br>~~GOO~~<br>~~eee~~|40<br>~~GOO~~<br>~~eee~~|—<br>~~GOO~~<br>~~eee~~|—<br>~~GOO~~<br>~~eee~~|ns<br>~~GOO~~<br>~~eee~~|
|||All Other Pulses<br>~~eee~~|20<br>~~eee~~|—<br>~~eee~~|—<br>~~eee~~|ns<br>~~eee~~|
|TLP-PER-TX<br>~~a~~<br>~~a GOO~~|Period of the LP Exclusive-OR Clock<br>~~GOO~~|—<br>~~eee~~<br>~~GOO~~|90<br>~~eee~~<br>~~GOO~~|—<br>~~eee~~<br>~~GOO~~|—<br>~~eee~~<br>~~GOO~~|ns<br>~~eee~~<br>~~GOO~~|
|CLOAD<br>~~a GD~~|Load Capacitance<br>~~GD~~|—<br>~~GD~~|0<br>~~GD~~|—<br>~~GD~~|70<br>~~GD~~|pF<br>~~GD~~|



**Table 3.28. Soft D-PHY Clock Signal Specification** 

© 2021-2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02102-1.7 

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**MachXO5-NX Family Data Sheet** 

**Table 3.29. Soft D-PHY Data-Clock Timing Specifications** 

|**Symbol**<br>~~POPp~~|**Description**<br>~~Pp~~|**Conditions**<br>~~Fr~~|**Min**<br>~~Fr~~|**Typ**<br>~~Fr~~|**Max**<br>~~Fr~~|**Unit**<br>~~Fr~~|
|---|---|---|---|---|---|---|
|**Data-Clock Timing Specifications**<br>~~POPp~~<br>~~Fr~~|||||||
|TSKEW[TX]<br>~~Pp~~|Data to Clock Skew<br>~~Pp~~|0.08 Gbps ≤ TSKEW[TX]<br>≤ 1.00 Gbps<br>~~Fr~~<br>~~ee~~|–0.15<br>~~Fr~~<br>~~eee~~|—<br>~~Fr~~<br>~~eee~~|0.15<br>~~Fr~~<br>~~eee~~|UIINST<br>~~Fr~~<br>~~eee~~|
|||1.00 Gbps < TSKEW[TX]<br>≤ 1.25 Gbps<br>~~Fr~~<br>~~ee~~|–0.20<br>~~Fr~~<br>~~eee~~|—<br>~~Fr~~<br>~~eee~~|0.20<br>~~Fr~~<br>~~eee~~|UIINST<br>~~Fr~~<br>~~eee~~|
|TSKEW[TLIS]<br>~~Pp~~<br>~~see~~|Data to Clock Skew<br>~~Pp~~<br>~~see~~|0.08 Gbps ≤ TSKEW[TLIS]<br>≤ 1.00 Gbps<br>~~Fr~~<br>~~ee ~~<br>~~see~~<br>~~ee~~|-0.20<br>~~Fr~~<br> ~~eee~~<br>~~see~~<br>~~eee~~|—<br>~~Fr~~<br>~~eee~~<br>~~see~~<br>~~eee~~|0.20<br>~~Fr~~<br>~~eee~~<br>~~see~~<br>~~eee~~|UIINST<br>~~Fr~~<br>~~eee~~<br>~~see~~<br>~~eee~~|
|||1.00 Gbps < TSKEW[TLIS]<br>≤ 1.25 Gbps<br>~~Fr~~<br>~~see~~<br>~~ee~~|-0.10<br>~~Fr~~<br>~~see~~<br>~~eee~~|—<br>~~Fr~~<br>~~see~~<br>~~eee~~|0.10<br>~~Fr~~<br>~~see~~<br>~~eee~~|UIINST<br>~~Fr~~<br>~~see~~<br>~~eee~~|
|TSETUP[RX]<br>~~See~~|Input Data Setup Before CLK<br>~~See~~|0.08 Gbps ≤ TSETUP[RX]<br>≤ 1.00 Gbps<br>~~ee ~~<br>~~See~~|0.15<br> ~~eee~~<br>~~See~~<br>~~tT~~|—<br>~~eee~~<br>~~See~~<br>~~tT|~~|—<br>~~eee~~<br>~~See~~<br>~~|~~|UI<br>~~eee~~<br>~~See~~|
|||1.00 Gbps < TSETUP[RX]<br>≤ 1.25 Gbps<br>~~See~~<br>~~ft~~|0.20<br>~~See~~<br>~~ft~~<br>~~tT~~|—<br>~~See~~<br>~~ft~~<br>~~tT|~~|—<br>~~See~~<br>~~ft~~<br>~~|~~|UI<br>~~See~~<br>~~ft~~|
|THOLD[RX]<br>~~PE~~|Input Data Hold After CLK<br>~~PE~~|0.08 Gbps ≤ THOLD[RX]<br>≤ 1.00 Gbps<br>~~PE~~|0.15<br>~~tT~~<br>~~PE~~|—<br>~~tT |~~<br>~~PE~~|—<br>~~|~~<br>~~PE~~|UI<br>~~PE~~|
|||1.00 Gbps < THOLD[RX]<br>≤ 1.25 Gbps<br>~~PE~~<br>~~a~~|0.20<br>~~PE~~<br>~~eee~~|—<br>~~PE~~<br>~~eee~~|—<br>~~PE~~<br>~~eee~~|UI<br>~~PE~~<br>~~eee~~|



## **3.13.8. Differential SSTL135D, SSTL15D (Output Only)** 

Differential SSTL is used for differential clock in DDR3/DDR3L memory interface. All differential SSTL outputs are implemented as a pair of complementary single-ended SSTL outputs. All allowable single-ended output classes (class I and class II) are supported. 

## **3.13.9. Differential HSUL12D (Output Only)** 

Differential HSUL is used for differential clock in LPDDR2/LPDDR3 memory interface. All differential HSUL outputs are implemented as a pair of complementary single-ended HSUL12 outputs. All allowable singleended drive strengths are supported. 

## **3.13.10. Differential LVCMOS25D, LVCMOS33D, LVTTL33D (Output Only)** 

Differential LVCMOS and LVTTL outputs are implemented as a pair of complementary single-ended outputs. All allowable single-ended output drive strengths are supported. 

© 2021-2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02102-1.7 

79 

**MachXO5-NX Family Data Sheet** 

## **3.14. Maximum sysI/O Buffer Speed** 

Over recommended operating conditions. 

**Table 3.30. Maximum I/O Buffer Speed[1, 2, 3, 4, 7 ]** 

|**Buffer**<br>~~De~~|**Description**<br>~~De~~|**Banks**<br>~~De~~|**Max**<br>~~De~~|**Unit**<br>~~De~~|
|---|---|---|---|---|
|**Maximum sysI/O Input Frequency**<br>~~pe~~|||||
|**Single-Ended**|||||
|LVCMOS33<br>~~eG~~|LVCMOS33, VCCIO= 3.3 V<br>~~eG~~|0, 1, 2, 3, 4, 7, 8, 9<br>~~eG~~|200<br>~~eG~~|MHz<br>~~eG~~|
|LVTTL33<br>~~eG~~|LVTTL33, VCCIO= 3.3 V<br>~~eG~~|0, 1, 2, 3, 4, 7, 8, 9<br>~~eG~~|200<br>~~eG~~|MHz<br>~~eG~~|
|LVCMOS25<br>~~Ge~~|LVCMOS25, VCCIO= 2.5 V<br>~~Ge~~|0, 1, 2, 3, 4, 7, 8, 9<br>~~Ge~~|200<br>~~Ge~~|MHz<br>~~Ge~~|
|LVCMOS185<br>~~eG~~|LVCMOS18, VCCIO= 1.8 V<br>~~eG~~|0, 2, 3, 4, 7, 8, 9<br>~~eG~~|200<br>~~eG~~|MHz<br>~~eG~~|
|LVCMOS18H<br>~~a~~|LVCMOS18, VCCIO= 1.8 V<br>~~G~~|5, 6<br>~~G~~|200<br>~~G~~|MHz<br>~~G~~|
|LVCMOS155<br>~~eG~~|LVCMOS15, VCCIO= 1.5 V<br>~~eG~~|0, 2, 3, 4, 7, 8, 9<br>~~eG~~|100<br>~~eG~~|MHz<br>~~eG~~|
|LVCMOS15H5<br>~~a~~|LVCMOS15, VCCIO= 1.5 V|5, 6|150|MHz|
|LVCMOS125<br>~~eG~~|LVCMOS12, VCCIO= 1.2 V<br>~~eG~~|0, 2, 3, 4, 7, 8, 9<br>~~eG~~|50<br>~~eG~~|MHz<br>~~eG~~|
|LVCMOS12H5<br>~~a~~|LVCMOS12, VCCIO= 1.2 V<br>~~GO~~|5, 6<br>~~GO~~|100<br>~~GO~~|MHz<br>~~GO~~|
|LVCMOS105<br>~~a~~|LVCMOS 1.0, VCCIO= 1.2 V|0, 2, 3, 4, 7, 8, 9|50|MHz|
|LVCMOS10H5<br>~~a~~<br>~~OO~~|LVCMOS 1.0, VCCIO= 1.0 V<br>~~OO~~|5, 6<br>~~OO~~|50<br>~~OO~~|MHz<br>~~OO~~|
|LVCMOS10R<br>~~OO~~<br>~~OO~~|LVCMOS 1.0, VCCIOindependent<br>~~OO~~<br>~~OO~~|5, 6<br>~~OO~~<br>~~OO~~|50<br>~~OO~~<br>~~OO~~|MHz<br>~~OO~~<br>~~OO~~|
|SSTL15_I, SSTL15_II<br>~~OO~~<br>~~a~~|SSTL_15, VCCIO= 1.5 V<br>~~OO~~|5, 6<br>~~OO~~|1066<br>~~OO~~|Mbps<br>~~OO~~|
|SSTL135_I, SSTL135_II<br>~~a~~|SSTL_135, VCCIO= 1.35 V<br>~~GO~~|5, 6<br>~~GO~~|1066<br>~~GO~~|Mbps<br>~~GO~~|
|HSUL12<br>~~a~~|HSUL_12, VCCIO= 1.2 V<br>~~GO~~|5, 6<br>~~GO~~|1066<br>~~GO~~|Mbps<br>~~GO~~|
|HSTL15<br>~~a~~|HSTL15, VCCIO= 1.5 V|5, 6|250|Mbps|
|MIPI D-PHY(LP Mode)<br>~~a~~<br>~~DO~~|MIPI, Low Power Mode, VCCIO= 1.2 V<br>~~DO~~|5, 6<br>~~DO~~|10<br>~~DO~~|Mbps<br>~~DO~~|
|**Differential8 **<br>~~DO~~<br>~~pn~~|||||
|LVDS<br>~~eG~~|LVDS, VCCIOindependent<br>~~eG~~|5, 6<br>~~eG~~|1250<br>~~eG~~|Mbps<br>~~eG~~|
|subLVDS<br>~~a~~|subLVDS, VCCIOindependent<br>~~DO~~|5, 6<br>~~DO~~|1250<br>~~DO~~|Mbps<br>~~DO~~|
|SLVS|SLVS similar to MIPI HS, VCCIO<br>independent|5, 6|1250|Mbps|
|MIPI D-PHY(HS Mode)<br>~~a~~|MIPI, High Speed Mode, VCCIO= 1.2 V|5, 6|1250|Mbps|
|SSTL15D<br>~~a~~<br>~~OO~~|Differential SSTL15, VCCIOindependent<br>~~OO~~|5, 6<br>~~OO~~|1066<br>~~OO~~|Mbps<br>~~OO~~|
|SSTL135D<br>~~OO~~<br>~~a~~|Differential SSTL135, VCCIOindependent<br>~~OO~~|5, 6<br>~~OO~~|1066<br>~~OO~~|Mbps<br>~~OO~~|
|HSUL12D<br>~~eG~~|Differential HSUL12, VCCIOindependent<br>~~eG~~|5, 6<br>~~eG~~|1066<br>~~eG~~|Mbps<br>~~eG~~|
|HSTL15D<br>~~Ge~~|Differential HSTL15, VCCIOindependent<br>~~Ge~~|5, 6<br>~~Ge~~|250<br>~~Ge~~|Mbps<br>~~Ge~~|
|**Maximum sysI/O Output Frequency**<br>~~pT~~|||||
|**Single-Ended**<br>~~pT~~|||||
|LVCMOS33(all drive strengths)<br>~~a~~|LVCMOS33, VCCIO= 3.3 V<br>~~OO~~|0, 1, 2, 3, 4, 7, 8, 9<br>~~OO~~|200<br>~~OO~~|MHz<br>~~OO~~|
|LVCMOS33(RS50)<br>~~a~~<br>~~a~~|LVCMOS33, VCCIO= 3.3 V, RSERIES= 50 Ω<br>~~OO~~|0, 1, 2, 3, 4, 7, 8, 9<br>~~OO~~|200<br>~~OO~~|MHz<br>~~OO~~|
|LVTTL33(all drive strengths)<br>~~eG~~|LVTTL33, VCCIO= 3.3 V<br>~~eG~~|0, 1, 2, 3, 4, 7, 8, 9<br>~~eG~~|200<br>~~eG~~|MHz<br>~~eG~~|
|LVTTL33(RS50)<br>~~a~~|LVTTL33, VCCIO= 3.3 V, RSERIES= 50 Ω|0, 1, 2, 3, 4, 7, 8, 9|200|MHz|
|LVCMOS25(all drive strengths)<br>~~a~~<br>~~a~~|LVCMOS25, VCCIO= 2.5 V<br>~~GO~~|0, 2, 3, 4, 7, 8, 9<br>~~GO~~|200<br>~~GO~~|MHz<br>~~GO~~|
|LVCMOS25(RS50)<br>~~a~~<br>~~a~~|LVCMOS25, VCCIO= 2.5 V, RSERIES= 50 Ω<br>~~GO~~<br>~~GO~~|0, 2, 3, 4, 7, 8, 9<br>~~GO~~<br>~~GO~~|200<br>~~GO~~<br>~~GO~~|MHz<br>~~GO~~<br>~~GO~~|
|LVCMOS18(all drive strengths)<br>~~a~~<br>~~a~~|LVCMOS18, VCCIO= 1.8 V<br>~~GO~~|0, 2, 3, 4, 7, 8, 9<br>~~GO~~|200<br>~~GO~~|MHz<br>~~GO~~|
|LVCMOS18(RS50)<br>~~a~~|LVCMOS18, VCCIO= 1.8 V, RSERIES= 50 Ω<br>~~Ge~~|0, 2, 3, 4, 7, 8, 9<br>~~Ge~~|200<br>~~Ge~~|MHz<br>~~Ge~~|
|LVCMOS18H(all drive strengths)<br>~~a~~|LVCMOS18, VCCIO= 1.8 V|5, 6|200|MHz|
|LVCMOS18H(RS50)<br>~~a~~<br>~~a~~|LVCMOS18, VCCIO= 1.8 V, RSERIES= 50 Ω<br>~~GO~~|5, 6<br>~~GO~~|200<br>~~GO~~|MHz<br>~~GO~~|
|LVCMOS15(all drive strengths)<br>~~a~~<br>~~a~~|LVCMOS15, VCCIO= 1.5 V<br>~~GO~~<br>~~GO~~|0, 2, 3, 4, 7, 8, 9<br>~~GO~~<br>~~GO~~|100<br>~~GO~~<br>~~GO~~|MHz<br>~~GO~~<br>~~GO~~|
|LVCMOS15H(all drive strengths)<br>~~a~~<br>~~a~~|LVCMOS15, VCCIO= 1.5 V<br>~~GO~~|5, 6<br>~~GO~~|150<br>~~GO~~|MHz<br>~~GO~~|
|LVCMOS12(all drive strengths)<br>~~eG~~|LVCMOS12, VCCIO= 1.2 V<br>~~eG~~|0, 2, 3, 4, 7, 8, 9<br>~~eG~~|50<br>~~eG~~|MHz<br>~~eG~~|



© 2021-2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02102-1.7 

80 

**MachXO5-NX Family Data Sheet** 

|**Buffer**<br>~~a~~|**Description**<br>~~GO~~|**Banks**<br>~~GO~~|**Max**<br>~~GO~~|**Unit**<br>~~GO~~|
|---|---|---|---|---|
|LVCMOS12H(all drive strengths)<br>~~a~~|LVCMOS12, VCCIO= 1.2 V<br>~~GO~~|5, 6<br>~~GO~~|100<br>~~GO~~|MHz<br>~~GO~~|
|LVCMOS10H(all drive strengths)<br>~~eG~~|LVCMOS12, VCCIO= 1.2 V<br>~~eG~~|5, 6<br>~~eG~~|50<br>~~eG~~|MHz<br>~~eG~~|
|SSTL15_I, SSTL15_II<br>~~Ge~~|SSTL_15, VCCIO= 1.5 V<br>~~Ge~~|5, 6<br>~~Ge~~|1066<br>~~Ge~~|Mbps<br>~~Ge~~|
|SSTL135_I, SSTL135_II<br>~~eG~~|SSTL_135, VCCIO= 1.35 V<br>~~eG~~|5, 6<br>~~eG~~|1066<br>~~eG~~|Mbps<br>~~eG~~|
|HSUL12(all drive strengths)<br>~~eG~~|HSUL_12, VCCIO= 1.2 V<br>~~eG~~|5, 6<br>~~eG~~|1066<br>~~eG~~|Mbps<br>~~eG~~|
|HSTL15<br>~~a~~|HSTL15, VCCIO= 1.5 V<br>~~G~~|5, 6<br>~~G~~|250<br>~~G~~|Mbps<br>~~G~~|
|MIPI D-PHY(LP Mode)<br>~~a~~|MIPI, Low Power Mode, VCCIO= 1.2 V<br>~~G~~|5, 6<br>~~G~~|10<br>~~G~~|Mbps<br>~~G~~|
|**Differential8 **|||||
|LVDS<br>~~eG~~|LVDS, VCCIO= 1.8 V<br>~~eG~~|5, 6<br>~~eG~~|1250<br>~~eG~~|Mbps<br>~~eG~~|
|LVDS25E6<br>~~eG~~|LVDS25, Emulated, VCCIO= 2.5 V<br>~~eG~~|0, 2, 3, 4, 7, 8, 9<br>~~eG~~|400<br>~~eG~~|Mbps<br>~~eG~~|
|SubLVDSE6<br>~~a~~|subLVDS, Emulated, VCCIO= 1.8 V<br>~~G~~|0, 2, 3, 4, 7, 8, 9<br>~~G~~|400<br>~~G~~|Mbps<br>~~G~~|
|SubLVDSEH6<br>~~eG~~|subLVDS, Emulated, VCCIO= 1.8 V<br>~~eG~~|5, 6<br>~~eG~~|800<br>~~eG~~|Mbps<br>~~eG~~|
|SLVS<br>~~a~~|SLVS similar to MIPI, VCCIO= 1.2 V|5, 6|1250|Mbps|
|MIPI D-PHY (HS Mode)|MIPI, High Speed Mode, VCCIO= 1.2 V|5, 6|1250|Mbps|
|SSTL15D<br>~~a~~|Differential SSTL15, VCCIO= 1.5 V<br>~~GO~~|5, 6<br>~~GO~~|1066<br>~~GO~~|Mbps<br>~~GO~~|
|SSTL135D<br>~~a~~|Differential SSTL135, VCCIO= 1.35 V<br>~~GO~~|5, 6<br>~~GO~~|1066<br>~~GO~~|Mbps<br>~~GO~~|
|HSUL12D<br>~~a~~|Differential HSUL12, VCCIO= 1.2 V|5, 6|1066|Mbps|
|HSTL15D<br>~~a~~|Differential HSTL15, VCCIO= 1.5 V|5, 6|250|Mbps|



**Notes** : 

1. Maximum I/O speed is the maximum switching rate of the I/O operating within the guidelines of the defining standard. The actual interface speed performance using the I/O also depends on other factors, such as internal and external timing. 

2. These numbers are characterized but not test on every device. 

3. Performance is specified in MHz, as defined in clock rate when the sysI/O is used as pin. For data rate performance, this can be converted to Mbps, which equals to 2 times the clock rate. 

4. LVCMOS and LVTTL are measured with load specified in Table 3.46. 

5. These LVCMOS inputs can be placed in different VCCIO voltage. Performance may vary. Please refer to Lattice Design Software 

6. These emulated outputs performance is based on externally properly terminated as described in LVDS25E (Output Only) and SubLVDSE/SubLVDSEH (Output Only). 

7. All speeds are measured with fast slew. 

8. For maximum differential I/O performance, only Differential I/O should be placed in the bottom I/O banks. If this is not possible, the following will impact on maximum performance: 

   - a. If Fast Slew Rate LVCMOS I/O are used, they should be limited to no more than nine I/O (adjacent), four I/O (same bank), 55 I/O (left/right banks) to keep degradation below 50%. 

   - b. If non-Differential I/O (SLOW SLEW) are placed on the bottom but not within the same bank as differential I/O, then the maximum Differential performance is degraded to 70% of original when 21 aggressors are toggling. 

   - c. If non-Differential I/O (SLOW SLEW) are placed within the same bank as Differential I/O then the maximum performance is degraded to 50% of original when 16 aggressor are toggling. 

   - d. No performance impact if MIPI LP and MIPI HS are in the same bank. 

   - e. If Differential RX/TX I/O are both placed within the same bank then the maximum performance is degraded to 90%. 

   - f. For DDR3/3L, LPDDR2/3/4 separate DQ/DQS groups from Address/Commands/CLK groups into separate banks. 

© 2021-2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02102-1.7 

81 

**MachXO5-NX Family Data Sheet** 

## **3.15. Typical Building Block Function Performance** 

These building block functions can be generated using Lattice Design Software Tool. Exact performance may vary with the device and the design software tool version. The design software tool uses internal parameters that have been characterized but are not tested on every device. 

**Table 3.31. Pin-to-Pin Performance** 

|**Function**|**Typ. @ VCC = 1.0 V**|**Unit**|
|---|---|---|
|16-bit Decoder(I/O configured with LVCMOS18, Top, Left and Right Banks)|5.5|ns|
|16-bit Decoder(I/O configured with HSTL15_I, Bottom Banks)|5.1|ns|
|16:1 Mux(I/O configured with LVCMOS18, Top, Left and Right Banks)|6|ns|
|16:1 Mux(I/O configured with HSTL15_I, Bottom Banks)|6.1|ns|



**Note** : These functions are generated using Lattice Radiant Design Software tool. Exact performance may vary with the device and the design software tool version. The design software tool uses internal parameters that have been characterized but are not tested on every device. 

**Table 3.32. Register-to-Register Performance[1, 3, 4]** 

|**Function**<br>~~a~~|**Typ. @ VCC = 1.0 V**<br>~~a~~<br>~~C~~|**Unit**<br>~~a~~<br>~~C~~|
|---|---|---|
|**Basic Functions**<br>~~C~~|||
|16-bit Adder<br>~~a~~|5002<br>~~a~~|MHz<br>~~a~~|
|32-bit Adder<br>~~a~~<br>~~pe~~|496<br>~~a~~|MHz<br>~~a~~|
|16-bit Counter<br>~~a~~<br>~~pe~~|402<br>~~a~~|MHz<br>~~a~~|
|32-bit Counter<br>~~pe~~<br>~~a~~|371<br>~~a~~|MHz<br>~~a~~|
|**Embedded Memory Functions**<br>~~pt~~|||
|512 × 36 Single Port RAM, with Output Register<br>~~a~~|5002<br>~~a~~|MHz<br>~~a~~|
|1024 × 18 True-Dual Port RAM usingsame clock, with EBR Output Registers<br>~~a~~<br>~~**p**e~~|5002<br>~~a~~|MHz<br>~~a~~|
|1024 × 18 True-Dual Port RAM usingasynchronous clocks, with EBR Output Registers<br>~~a~~<br>~~**p**e~~|5002<br>~~a~~|MHz<br>~~a~~|
|**Large Memory Functions**<br>~~**p**e~~<br>~~t~~|||
|32 k × 32 Single Port RAM, with Output Register<br>~~a~~|3752<br>~~a~~|MHz<br>~~a~~|
|32 k × 32 Single Port RAM with ECC, with Output Register<br>~~a~~|3502<br>~~a~~|MHz<br>~~a~~|
|32 k × 32 True-Dual Port RAM usingsame clock, with Output Registers<br>~~a~~|200<br>~~a~~|MHz<br>~~a~~|
|**Distributed Memory Functions**<br>~~a~~<br>~~PR~~|||
|16 × 4 Single Port RAM(One PFU)<br>~~PR~~<br>~~a~~|5002<br>~~PR~~<br>~~a~~|MHz<br>~~PR~~<br>~~a~~|
|16 × 2 Pseudo-Dual Port RAM(One PFU)<br>~~a~~|5002<br>~~a~~|MHz<br>~~a~~|
|16 × 4 Pseudo-Dual Port(Two PFUs)<br>~~a~~|5002<br>~~a~~|MHz<br>~~a~~|
|**DSP Functions**<br>~~pe~~|||
|9 × 9 Multiplier with Input Output Registers<br>~~pe~~|376|MHz|
|18 × 18 Multiplier with Input/Output Registers<br>~~pe~~<br>~~a~~|287<br>~~a~~|MHz<br>~~a~~|
|36 × 36 Multiplier with Input/Output Registers<br>~~a~~<br>~~a~~|200<br>~~a~~<br>~~a~~|MHz<br>~~a~~<br>~~a~~|
|MAC 18 × 18 with Input/Output Registers<br>~~a~~|203<br>~~a~~|MHz<br>~~a~~|
|MAC 18 × 18 with Input/Pipelined/Output Registers<br>~~a~~|287<br>~~a~~|MHz<br>~~a~~|
|MAC 36 × 36 with Input/Output Registers<br>~~a~~<br>~~pp~~|119<br>~~a~~<br>~~pp~~|MHz<br>~~a~~<br>~~pp~~|
|MAC 36 × 36 with Input/Pipelined/Output Registers<br>~~pp~~<br>~~a~~|155<br>~~pp~~<br>~~a~~|MHz<br>~~pp~~<br>~~a~~|



## **Notes** : 

1. The Clock port is configured with LVDS I/O type. Performance Grade: 9_High-Performance_1.0V. 

2. Limited by the Minimum Pulse Width of the component 

3. These functions are generated using Lattice Radiant Design Software tool. Exact performance may vary with the device and the design software tool version. The design software tool uses internal parameters that have been characterized but are not tested on every device. 

4. For the Pipelined designs, the number of pipeline stages used are 2. 

© 2021-2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02102-1.7 

82 

**MachXO5-NX Family Data Sheet** 

## **3.16. LMMI** 

Table 3.33 summarizes the performance of the LMMI interface with supported IPs. Additional timing requirement and constraint can be identified through the Lattice Radiance design tools. 

**Table 3.33. LMMI FMAX Summary** 

|**IP**|**FMAX (MHz)**|
|---|---|
|CDR0|73|
|CDR1|70|
|CRE|54|
|I2C|38|
|PLL_ULC|59|
|PLL_LRC|37|



## **3.17. Derating Timing Tables** 

Logic timing provided in the following sections of this data sheet and the Lattice Radiant design tools are worst case numbers in the operating range. Actual delays at nominal temperature and voltage for best case process, can be much better than the values given in the tables. The Lattice Radiant design tool can provide logic timing numbers at a particular temperature and voltage. 

## **3.18. External Switching Characteristics** 

Over recommended commercial operating conditions. 

**Table 3.34. External Switching Characteristics (VCC = 1.0 V)** 

|**Parameter**<br>~~a~~|**Description**<br>~~a~~|–**9**<br>~~a~~|–**9**<br>~~a~~|–**8**<br>~~a~~|–**8**<br>~~a~~|–**7**<br>~~a~~|–**7**<br>~~a~~|**Unit**<br>~~a~~|
|---|---|---|---|---|---|---|---|---|
|||**Min**<br>~~a~~<br>~~ee~~|**Max**<br>~~a~~<br>~~ee~~|**Min**<br>~~a~~<br>~~ee~~|**Max**<br>~~a~~<br>~~ee~~|**Min**<br>~~a~~<br>~~ee~~|**Max**<br>~~a~~<br>~~ee~~||
|**Clocks**|||||||||
|**Primary Clock**<br>~~pO~~|||||||||
|fMAX_PRI<br>~~pO~~|Frequencyfor PrimaryClock<br>|—<br>|400|—|325.2|—|276|MHz|
|tW_PRI<br>~~pOia~~|Clock Pulse Width for<br>PrimaryClock<br>~~ia~~|1.125<br>~~ia~~|—|1.384|—|1.630|—|ns|
|tSKEW_PRI6<br>~~ia~~<br>~~i~~<br>~~ee~~|Primary Clock Skew Within a<br>Device<br>~~ia~~<br>~~ia~~|—<br>~~ia~~|450|—|554|—|653|ps|
|**Edge Clock**<br>~~ia~~<br>~~ee~~|||||||||
|fMAX_EDGE<br><br>~~ee~~|Frequency for Edge Clock<br>Tree<br>~~a~~|—|800|—|650.4|—|551.7|MHz|
|tW_EDGE<br><br>~~ee~~<br>~~ia~~|Clock Pulse Width for Edge<br>Clock<br>~~a~~<br>~~ia~~|0.537<br>~~ia~~|—|0.661|—|0.779|—|ns|
|tSKEW_EDGE6<br>~~ia~~<br>~~i~~|Edge Clock Skew Within a<br>Device<br>~~ia~~<br>~~ia~~|—<br>~~ia~~<br>~~a~~|120<br>~~a~~|—<br>~~a~~|148<br>~~a~~|—<br>~~a~~|174<br>~~a~~|ps<br>~~a~~|
|**Generic SDR Input**<br>~~ia~~|||||||||
|**General I/O Pin Parameters Using Dedicated Primary Clock Input without PLL**|||||||||
|tCO<br>~~a~~|Clock to Output – PIO<br>Output Register<br>~~a~~|—<br>~~a~~|8.36<br>~~a~~|—<br>~~a~~|8.53<br>~~a~~|—<br>~~a~~|8.67<br>~~a~~|ns<br>~~a~~|
|tSU<br>~~a~~<br>~~i~~|Clock to Data Setup – PIO<br>Input Register<br>~~a~~<br>~~i~~<br>~~a~~|0.00<br>~~a~~<br>~~i~~|—<br>~~a~~<br>~~i~~|0.00<br>~~a~~<br>~~i~~|—<br>~~a~~<br>~~i~~|0.00<br>~~a~~<br>~~i~~|—<br>~~a~~<br>~~i~~|ns<br>~~a~~<br>~~i~~|
|tH(LTR)<br>~~i~~<br>~~i~~|Clock to Data Hold – PIO<br>Input Register<br>~~i~~<br>~~a~~<br>~~a~~|3.73<br>~~i~~|—<br>~~i~~|3.83<br>~~i~~|—<br>~~i~~|3.93<br>~~i~~|—<br>~~i~~|ns<br>~~i~~|



© 2021-2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02102-1.7 

83 

**MachXO5-NX Family Data Sheet** 

|**Parameter**<br>~~a~~<br>~~es~~|**Description**<br>~~a~~|–**9**<br>~~a~~<br>~~a~~<br>~~a~~<br>~~ee~~|–**9**<br>~~a~~<br>~~a~~<br>~~a~~<br>~~ee~~|–**8**<br>~~a~~<br>~~a~~<br>~~eeee~~|–**8**<br>~~a~~<br>~~a~~<br>~~eeee~~|–**7**<br>~~a~~<br>~~a~~<br>~~eeee~~|–**7**<br>~~a~~<br>~~a~~<br>~~eeee~~|**Unit**<br>~~a~~<br>~~ee~~|
|---|---|---|---|---|---|---|---|---|
|||**Min**<br>~~a~~<br>~~a~~|**Max**<br>~~a~~<br>~~a~~<br>~~ee~~|**Min**<br>~~a~~<br>~~a~~<br>~~ee~~|**Max**<br>~~a~~<br>~~a~~<br>~~ee~~|**Min**<br>~~a~~<br>~~a~~<br>~~ee~~|**Max**<br>~~a~~<br>~~a~~<br>~~ee~~||
|tH(Bottom)<br>~~es~~|Clock to Data Hold – PIO<br>Input Register|4.65<br>~~a~~|—<br>~~a~~<br>~~ee~~|4.75<br>~~a~~<br>~~ee~~|—<br>~~a~~<br>~~ee~~|4.84<br>~~a~~<br>~~ee~~|—<br>~~a~~<br>~~ee~~|ns<br>~~ee~~|
|tSU_DEL<br>~~es~~|Clock to Data Setup – PIO<br>Input Register with Data<br>Input Delay|1.84|—<br>~~ee~~|1.84<br>~~ee~~|—<br>~~ee~~|1.84<br>~~ee~~|—<br>~~ee~~|ns<br>~~ee~~|
|tH_DEL(LTR)<br>~~es~~|Clock to Data Hold – PIO<br>Input Register with Data<br>Input Delay|0.22|—<br>~~ee ~~|0.22<br> ~~ee ~~|—<br> ~~ee ~~|0.22<br> ~~ee ~~|—<br> ~~ee~~|ns<br>~~ee~~|
|tH_DEL(Bottom)|Clock to Data Hold – PIO<br>Input Register with Data<br>Input Delay|1.77|—|1.77|—|1.77|—|ns|
|**General I/O Pin Parameters Using Dedicated Primary Clock Input with PLL**<br>~~Reese~~<br>~~ee~~<br>~~eseeee~~<br>~~ee~~|||||||||
|tCOPLL<br>~~ee~~<br>~~ee~~|Clock to Output – PIO<br>Output Register<br>~~es~~<br>~~se~~|—<br>~~ee~~<br>~~se~~|4.55<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~|4.67<br>~~ee~~<br>~~ee~~|—<br>~~ee~~|5.51|ns<br>~~ee~~|
|tSUPLL(LTR except Bank1)<br>~~ee~~<br>~~ee~~<br>~~a~~|Clock to Data Setup – PIO<br>Input Register<br>~~es ~~<br>~~se~~<br>~~ee~~|1.71<br> ~~ee ~~<br>~~se~~<br>~~ee~~|—<br> ~~ee~~<br>~~ee~~<br>~~ee~~|1.71<br>~~ee~~<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~<br>~~ee~~|1.71<br>~~ee~~<br>~~ee~~|—|ns<br>~~ee~~<br>~~ee~~|
|tSUPLL(Bank1)<br>~~ee~~<br>~~a~~<br>~~a~~|Clock to Data Setup – PIO<br>Input Register<br>~~se~~<br>~~ee~~<br>~~ee~~|2.33<br>~~se ~~<br>~~ee~~<br>~~ee~~|—<br> ~~ee ~~<br>~~ee~~<br>~~ee~~|2.33<br> ~~ee ~~<br>~~ee~~<br>~~ee~~|—<br> ~~ee ~~<br>~~ee~~<br>~~ee~~|2.33<br> ~~ee~~<br>~~ee~~<br>~~ee~~|—|ns<br>~~ee~~<br>~~ee~~<br>~~ee~~|
|tSUPLL(Bottom)<br>~~a~~<br>~~a~~<br>~~a~~|Clock to Data Setup – PIO<br>Input Register<br>~~ee~~<br>~~ee~~<br>~~ee~~|1.33<br>~~ee ~~<br>~~ee~~<br>~~ee~~|—<br> ~~ee ~~<br>~~ee~~<br>~~ee~~|1.33<br> ~~ee ~~<br>~~ee~~<br>~~ee~~|—<br> ~~ee ~~<br>~~ee~~<br>~~ee~~|1.33<br> ~~ee~~<br>~~ee~~<br>~~ee~~|—|ns<br>~~ee~~<br>~~ee~~<br>~~ee~~|
|tHPLL(LTR)<br>~~a~~<br>~~a~~<br>~~es~~|Clock to Data Hold – PIO<br>Input Register<br>~~ee~~<br>~~ee~~|0.98<br>~~ee ~~<br>~~ee~~|—<br> ~~ee ~~<br>~~ee~~|1.21<br> ~~ee ~~<br>~~ee~~|—<br> ~~ee ~~<br>~~ee~~|1.42<br> ~~ee~~<br>~~ee~~|—|ns<br>~~ee~~<br>~~ee~~|
|tHPLL(Bottom)<br>~~a~~<br>~~es~~|Clock to Data Hold – PIO<br>Input Register<br>~~ee~~|1.87<br>~~ee ~~|—<br> ~~ee ~~|1.87<br> ~~ee ~~|—<br> ~~ee ~~|1.87<br> ~~ee~~|—|ns<br>~~ee~~|
|tSU_DELPLL(LTR except<br>Bank1)<br>~~es~~|Clock to Data Setup – PIO<br>Input Register with Data<br>Input Delay|4.87|—|4.87|—|4.87|—|ns|
|tSU_DELPLL(Bank1)<br>~~es~~|Clock to Data Setup – PIO<br>Input Register with Data<br>Input Delay|5.77|—|5.77|—|5.77|—|ns|
|tSU_DELPLL(Bottom)|Clock to Data Setup – PIO<br>Input Register with Data<br>Input Delay|4.74|—|4.74|—|4.74|—|ns|
|tH_DELPLL|Clock to Data Hold – PIO<br>Input Register with Data<br>Input Delay|0.00|—|0.00|—|0.00|—|ns|
|**Generic DDR Input/Output**<br>~~Ree~~|||||||||
|**Generic DDRX1 Inputs/Outputs with Clock and Data Centered at Pin (GDDRX1_RX/TX.SCLK.Centered) using PCLK Clock Input**<br>**(Left, Top, and Right Banks) –Figure 3.7and Figure 3.9**<br>~~ee~~|||||||||
|tSU_GDDR1<br>~~ee~~<br>~~a~~<br>~~ee~~<br>~~a~~|Input Data Setup Before CLK<br>~~ee~~<br>~~————EeEEEeee~~<br>~~rs~~<br>|0.917<br>~~ee~~<br>~~————EeEEEeee~~<br>~~ee~~|—<br>~~ee~~<br>~~————EeEEEeee~~<br>~~ee~~|0.917<br>~~ee~~<br>~~————EeEEEeee~~<br>~~es~~|—<br>~~ee~~<br>~~————EeEEEeee~~<br>~~es~~|0.917<br>~~ee~~<br>~~————EeEEEeee~~|—<br>~~ee~~<br>~~————EeEEEeee~~|ns<br>~~ee~~<br>~~————EeEEEeee~~|
|||0.275<br>~~————EeEEEeee~~<br>~~ee~~<br>~~rs~~<br>|—<br>~~————EeEEEeee~~<br>~~ee~~<br>~~rs~~<br>|0.275<br>~~————EeEEEeee~~<br>~~es~~<br>~~r~~~~**s**~~<br>|—<br>~~————EeEEEeee~~<br>~~es~~<br>~~I~~<br>|0.275<br>~~————EeEEEeee~~<br>|—<br>~~————EeEEEeee~~<br>|UI<br>~~————EeEEEeee~~<br>|
|tHO_GDDR1<br>~~ee~~<br>~~a~~|Input Data Hold After CLK<br>~~rs~~<br>|0.917<br>~~ee~~<br>~~rs~~<br>|—<br>~~ee~~<br>~~rs~~<br>|0.917<br>~~es~~<br>~~r~~~~**s**~~<br>|—<br>~~es~~<br>~~I~~<br>|0.917<br>|—<br>|ns<br>|
|tDVB_GDDR1<br>~~ee~~<br>~~a~~|Output Data Valid After CLK<br>Output<br>~~rs~~<br>~~——_———E—EeEEeee~~|1.217<br>~~ee ~~<br>~~rs~~<br>~~——_———E—EeEEeee~~<br>~~ee~~|—<br> ~~ee ~~<br>~~rs~~<br>~~——_———E—EeEEeee~~<br>~~ee~~|1.113<br> ~~es ~~<br>~~r~~~~**s**~~<br>~~——_———E—EeEEeee~~<br>~~e~~|—<br> ~~es~~<br>~~I~~<br>~~——_———E—EeEEeee~~<br>~~es ee~~|1.014<br>~~——_———E—EeEEeee~~<br>~~ee~~|—<br>~~——_———E—EeEEeee~~|ns<br>~~——_———E—EeEEeee~~|
|||–0.45<br>~~rs~~<br>~~——_———E—EeEEeee~~<br>~~ee~~|—<br>~~rs~~<br>~~——_———E—EeEEeee~~<br>~~ee~~|–0.554<br>~~r~~~~**s**~~<br>~~——_———E—EeEEeee~~<br>~~e~~|—<br>~~I~~<br>~~——_———E—EeEEeee~~<br>~~es ee~~|–0.653<br>~~——_———E—EeEEeee~~<br>~~ee~~|—<br>~~——_———E—EeEEeee~~|ns + ½ UI<br>~~——_———E—EeEEeee~~|
|tDQVA_GDDR1<br>~~a~~<br>~~EEE~~<br>~~ee~~<br>~~a~~|Output Data Valid After CLK<br>Output<br>~~rs~~<br>~~——_———E—EeEEeee~~<br>~~EEE~~<br>~~ns~~|1.217<br>~~rs~~<br>~~——_———E—EeEEeee~~<br>~~ee~~<br>~~EEE~~<br>~~ee~~|—<br>~~rs ~~<br>~~——_———E—EeEEeee~~<br>~~ee~~<br>~~EEE~~<br>~~ee~~|1.113<br> ~~r~~~~**s** ~~<br>~~——_———E—EeEEeee~~<br>~~e~~<br>~~EEE~~<br>~~es~~|—<br> ~~I~~<br>~~——_———E—EeEEeee~~<br>~~es ee~~<br>~~EEE~~<br>~~es~~|1.014<br>~~——_———E—EeEEeee~~<br>~~ee~~<br>~~EEE~~|—<br>~~——_———E—EeEEeee~~<br>~~EEE~~|ns<br>~~——_———E—EeEEeee~~<br>~~EEE~~|
|||–0.45<br>~~EEE~~<br>~~ee~~<br>~~(rr~~|—<br>~~EEE~~<br>~~ee~~<br>~~rs~~|–0.554<br>~~EEE~~<br>~~es~~<br>~~rs~~|—<br>~~EEE~~<br>~~es~~<br>~~I~~|–0.653<br>~~EEE~~<br>~~**I**~~|—<br>~~EEE~~|ns + ½ UI<br>~~EEE~~|
|fDATA_GDDRX1<br>~~ee~~<br>~~a~~|Input/Output Data Rate<br>~~ns~~<br>~~es~~|—<br>~~ee~~<br>~~(rr~~<br>~~RUD~~|300<br>~~ee~~<br>~~rs~~<br>~~nD Us~~|—<br>~~es~~<br>~~rs~~<br>~~Us~~|300<br>~~es~~<br>~~I~~<br>~~(OU~~|—<br>~~**I**~~|300<br>~~I~~|Mbps|
|fMAX_GDDRX1<br>~~ee~~<br>~~a~~|Frequencyof PCLK<br>~~ns~~<br>~~es~~|—<br>~~ee ~~<br>~~(rr~~<br>~~RUD~~<br>~~ee~~|150<br> ~~ee ~~<br>~~rs~~<br>~~nD Us~~<br>~~ee~~|—<br> ~~es ~~<br>~~rs~~<br>~~Us~~<br>~~es~~|150<br> ~~es~~<br>~~I~~<br>~~(OU~~<br>~~ee~~|—<br>~~**I**~~<br>~~ee~~|150<br>~~I~~|MHz|
|½  UI<br>~~a~~<br>~~es~~|Half of Data Bit Time, or 90<br>degree<br>~~ns~~<br>~~es ~~<br>~~es~~<br>~~ee~~|1.667<br>~~(rr ~~<br> ~~RUD~~<br>~~es~~<br>~~ee~~<br>~~ee~~|—<br> ~~rs ~~<br>~~nD Us~~<br>~~es~~<br>~~ee~~|1.667<br> ~~rs ~~<br>~~Us ~~<br>~~es~~<br>~~es~~|—<br> ~~I ~~<br> ~~(OU~~<br>~~es~~<br>~~ee~~|1.667<br> ~~**I**~~<br>~~es~~<br>~~ee~~|—<br>~~I~~<br>~~es~~|ns<br>~~es~~|
|Output TX to Input RX Marginper Edge<br>~~es~~<br>~~Pee~~<br>~~ee~~||0.3<br>~~es~~<br>~~ee ~~<br>~~Pee~~<br>~~ee~~|—<br>~~es~~<br> ~~ee ~~<br>~~Pee~~|0.197<br>~~es~~<br> ~~es ~~<br>~~Pee~~|—<br>~~es~~<br> ~~ee~~<br>~~Pee~~|0.097<br>~~es~~<br>~~ee~~<br>~~Pee~~|—<br>~~es~~<br>~~Pee~~|ns<br>~~es~~<br>~~Pee~~|



© 2021-2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02102-1.7 

84 

**MachXO5-NX Family Data Sheet** 

|**Parameter**<br>~~ee~~|**Description**<br>~~ee~~|–**9**<br>~~ee~~<br>~~a~~|–**9**<br>~~ee~~<br>~~a~~|–**8**<br>~~ee~~<br>~~ee~~|–**8**<br>~~ee~~<br>~~ee~~|–**7**<br>~~ee~~<br>~~ee~~|–**7**<br>~~ee~~<br>~~ee~~|**Unit**<br>~~ee~~|
|---|---|---|---|---|---|---|---|---|
|||**Min**<br>~~ee~~<br>~~a~~|**Max**<br>~~ee~~|**Min**<br>~~ee~~<br>~~ee~~|**Max**<br>~~ee~~<br>~~ee~~|**Min**<br>~~ee~~<br>~~ee~~|**Max**<br>~~ee~~||
|**Generic DDRX1 Inputs/Outputs with Clock and Data Aligned at Pin (GDDRX1_RX/TX.SCLK.Aligned) using PCLK Clock Input (Left,**<br>**Top, and Right Banks) –Figure 3.8andFigure 3.10**<br>~~ee~~<br>~~a~~<br>~~a~~|||||||||
|tDVA_GDDR1<br>~~a~~|Input Data Valid After CLK<br>~~a~~|—<br>~~a~~<br>~~—————~~|–0.917<br>~~a~~<br>~~—————~~|—<br>~~a~~<br>~~—————~~|**–**0.917<br>~~a~~<br>~~—————~~|—<br>~~a~~<br>~~—————~~|–0.917<br>~~a~~|ns + ½ UI<br>~~a~~|
|||—<br>~~a~~<br>~~—————~~<br>~~a~~|0.75<br>~~a~~<br>~~—————~~|—<br>~~a~~<br>~~—————~~|0.75<br>~~a~~<br>~~—————~~|—<br>~~a~~<br>~~—————~~|0.75<br>~~a~~|ns<br>~~a~~|
|||—<br>~~a~~<br>~~—————~~<br>~~a~~|0.225<br>~~a~~<br>~~—————~~|—<br>~~a~~<br>~~—————~~|0.225<br>~~a~~<br>~~—————~~|—<br>~~a~~<br>~~—————~~|0.225<br>~~a~~|UI<br>~~a~~|
|tDVE_GDDR1<br>~~|~~<br>~~a~~|Input Data Hold After CLK<br>~~|~~<br>~~ee~~|0.917<br>~~**a**~~|—<br>~~**a**~~|0.917<br>~~**a**~~|—<br>~~**a**~~|0.917<br>~~**a**~~|—<br>~~**a**~~|ns + ½ UI<br>~~**a**~~|
|||2.583<br>~~**a**~~|—<br>~~**a**~~|2.583<br>~~**a**~~|—<br>~~**a**~~|2.583<br>~~**a**~~|—<br>~~**a**~~|ns<br>~~**a**~~|
|||0.775<br>~~**a**~~<br>~~ee~~|—<br>~~**a**~~<br>~~ee~~|0.775<br>~~**a**~~<br>~~ee~~|—<br>~~**a**~~<br>~~ee~~|0.775<br>~~**a**~~<br>~~ee~~|—<br>~~**a**~~<br>~~ee~~|UI<br>~~**a**~~|
|tDIA_GDDR1<br>~~a~~<br>~~a~~|Output Data Invalid After<br>CLK Output<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~|0.45<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~|0.554<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~|0.653<br>~~ee~~<br>~~ee~~|ns|
|tDIB_GDDR1<br>~~a~~<br>~~a~~<br>~~Pa~~|Output Data Invalid Before<br>CLK Output<br>~~ee ~~<br>~~ee~~|—<br> ~~ee ~~<br>~~ee~~|0.45<br> ~~ee ~~<br>~~ee~~|—<br> ~~ee~~<br>~~ee~~|0.554<br>~~ee~~<br>~~ee~~|—<br>~~ee ~~<br>~~ee~~|0.653<br> ~~ee~~<br>~~ee~~|ns|
|fDATA_GDDRX1<br>~~a~~<br>~~Pa~~|Input/Output Data Rate<br>~~ee ~~|—<br> ~~ee ~~|300<br> ~~ee~~|—<br>~~ee ~~|300<br> ~~ee~~|—<br>~~ee~~|300<br>~~ee~~|Mbps|
|fMAX_GDDRX1<br>~~Pa~~<br>~~a~~|Frequency for PCLK<br>~~ee~~|—<br>~~ee~~|150<br>~~ee~~|—<br>~~ee~~|150<br>~~eee~~|—<br>~~eee~~|150<br>~~eee~~|MHz<br>~~eee~~|
|½  UI<br>~~a~~|Half of Data Bit Time, or 90<br>degree<br>~~ee~~|1.667<br>~~ee~~|—<br>~~ee~~|1.667<br>~~ee~~|—<br>~~eee~~|1.667<br>~~eee~~|—<br>~~eee~~|ns<br>~~eee~~|
|Output TX to Input RX Margin per Edge<br>~~a~~<br>~~ee~~<br>~~Pe~~||0.3<br>~~ee~~<br>~~Pe~~|—<br>~~ee~~<br>~~Pe~~|0.197<br>~~ee~~<br>~~Pe~~|—<br>~~eee~~<br>~~Pe~~|0.098<br>~~eee~~<br>~~Pe~~|—<br>~~eee~~<br>~~Pe~~|ns<br>~~eee~~<br>~~Pe~~|
|**Generic DDRX1 Inputs/Outputs with Clock and Data Centered at Pin (GDDRX1_RX/TX.SCLK.Centered) using PCLK Clock Input**<br>**(Bottom Banks) –Figure 3.7and Figure 3.9**<br>~~as~~|||||||||
|tSU_GDDR1<br>~~ee~~|Input Data Setup Before CLK<br>~~ee~~|0.55<br>~~ee~~|—<br>~~ee~~|0.55<br>~~ee~~|—<br>~~ee~~|0.648<br>~~ee~~|—<br>~~ee~~|ns<br>~~ee~~|
|||0.275<br>~~ee~~<br>~~a~~|—<br>~~ee~~<br>~~a~~|0.275<br>~~ee~~<br>~~a~~|—<br>~~ee~~<br>~~a~~|0.275<br>~~ee~~<br>~~a~~|—<br>~~ee~~<br>~~a~~|UI<br>~~ee~~<br>~~a~~|
|tHO_GDDR1<br>~~ee~~<br>~~a~~<br>~~nn~~|Input Data Hold After CLK<br>~~ee~~|0.55<br>~~ee~~<br>~~a~~<br>~~a~~|—<br>~~ee~~<br>~~a~~|0.55<br>~~ee~~<br>~~a~~|—<br>~~ee~~<br>~~a~~|0.648<br>~~ee~~<br>~~a~~|—<br>~~ee~~<br>~~a~~|ns<br>~~ee~~<br>~~a~~|
|tDVB_GDDR1<br>~~nn~~<br>~~ne~~|Output Data Valid After CLK<br>Output<br>~~ee~~|0.7<br>~~a~~|—|0.631|—|0.744|—|ns|
|||–0.300<br>~~a~~<br>~~ee~~|—<br>|–0.369<br>|—<br>|–0.435<br>|—<br>|ns + ½ UI<br>|
|tDQVA_GDDR1<br>~~nn~~<br>~~ne~~|Output Data Valid After CLK<br>Output<br>~~ee~~|0.7<br>~~a~~<br>~~ee~~|—<br>|0.631<br>|—<br>|0.744<br>|—<br>|ns<br>|
|||–0.300<br>~~eea~~|—<br>~~a~~|–0.369<br>~~a~~|—<br>~~a~~|–0.435<br>~~a~~|—<br>~~a~~|ns + ½ UI<br>~~a~~|
|fDATA_GDDRX1<br>~~ne~~<br>~~a~~|Input/Output Data Rate<br>~~ee~~|—<br>~~eea~~|500<br>~~a~~|—<br>~~a~~|500<br>~~a~~|—<br>~~a~~|424<br>~~a~~|Mbps<br>~~a~~|
|fMAX_GDDRX1<br>~~a~~<br>~~a~~<br>~~a~~|Frequencyof PCLK<br>~~ee~~<br>~~a~~|—<br>~~ee~~|250<br>~~ee~~|—<br>~~ee~~|250|—<br>~~ee~~|212<br>~~ee~~|MHz<br>~~ee~~|
|½  UI<br>~~a~~<br>~~a~~|Half of Data Bit Time, or 90<br>degree<br>~~ee~~<br>~~a~~|—<br>~~ee~~|—<br>~~ee~~|1<br>~~ee~~|—|1.179<br>~~ee~~|—<br>~~ee~~|ns<br>~~ee~~|
|Output TX to Input RX Marginper Edge<br>~~ee ~~<br>~~a~~||0.15<br> ~~ee~~|—<br>~~ee~~|0.081<br>~~ee~~|—|0.095<br>~~ee~~|—<br>~~ee~~|ns<br>~~ee~~|
|**Generic DDRX1 Inputs/Outputs with Clock and Data Aligned at Pin (GDDRX1_RX/TX.SCLK.Aligned) using PCLK Clock Input**<br>**(Bottom Banks) –Figure 3.8andFigure 3.10**<br>~~as~~<br>~~**a**~~<br>~~Bf~~|||||||||
|tDVA_GDDR1<br>~~Bf~~|Input Data Valid After CLK<br>~~Bf~~|—<br>~~**a**~~<br>~~ee~~|–0.55<br>~~**a**~~<br>~~ee~~|—<br>~~**a**~~<br>~~ee~~|–0.550<br>~~**a**~~<br>~~ee~~|—<br>~~**a**~~<br>~~ee~~|–0.648<br>~~**a**~~<br>~~ee~~|ns + ½ UI<br>~~**a**~~<br>~~ee~~|
|||—<br>~~**a**~~<br>~~ee~~|0.45<br>~~**a**~~<br>~~ee~~|—<br>~~**a**~~<br>~~ee~~|0.45<br>~~**a**~~<br>~~ee~~|—<br>~~**a**~~<br>~~ee~~|0.53<br>~~**a**~~<br>~~ee~~|ns<br>~~**a**~~<br>~~ee~~|
|||—<br>~~**a**~~<br>~~ee~~|0.225<br>~~**a**~~<br>~~ee~~|—<br>~~**a**~~<br>~~ee~~|0.225<br>~~**a**~~<br>~~ee~~|—<br>~~**a**~~<br>~~ee~~|0.225<br>~~**a**~~<br>~~ee~~|UI<br>~~**a**~~<br>~~ee~~|
|tDVE_GDDR1<br>~~Bf~~<br>~~|~~<br>~~a~~|Input Data Hold After CLK<br>~~Bf~~<br>~~|~~<br>~~es~~|0.55<br>~~**a**~~<br>~~ee~~<br>~~**a**~~|—<br>~~**a**~~<br>~~ee~~|0.55<br>~~**a**~~<br>~~ee~~|—<br>~~**a**~~<br>~~ee~~|0.648<br>~~**a**~~<br>~~ee~~|—<br>~~**a**~~<br>~~ee~~|ns + ½ UI<br>~~**a**~~<br>~~ee~~|
|||1.55<br>~~**a**~~|—|1.55|—|1.827|—|ns|
|||0.775<br>~~**a**~~<br>~~ee~~|—<br>~~es~~|0.775<br>~~es~~|—|0.775|—|UI|
|tDIA_GDDR1<br>~~a~~<br>~~a~~|Output Data Invalid After<br>CLK Output<br>~~es~~<br>~~es~~|—<br>~~ee~~<br>~~ee~~|0.3<br>~~es~~<br>~~ee~~|—<br>~~es~~|0.369|—|0.435|ns|
|tDIB_GDDR1<br>~~a~~<br>~~a~~<br>~~Pa~~|Output Data Invalid Before<br>CLK Output<br>~~es ~~<br>~~es~~|—<br> ~~ee ~~<br>~~ee~~|0.3<br> ~~es~~<br>~~ee~~|—<br>~~es~~|0.369|—|0.435|ns|
|fDATA_GDDRX1<br>~~a~~<br>~~Pa~~<br>~~es~~|Input/Output Data Rate<br>~~es ~~<br>~~es~~|—<br> ~~ee ~~<br>~~es~~|500<br> ~~ee~~|—|500|—|424|Mbps|
|fMAX_GDDRX1<br>~~Pa~~<br>~~es~~|Frequency for PCLK<br>~~es~~|—<br>~~es~~|250|—|250|—|212|MHz|



© 2021-2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02102-1.7 

85 

**MachXO5-NX Family** 

**Data Sheet** 

|**Parameter**<br>~~ce~~<br>~~a~~|**Description**<br>~~ce~~<br>|–**9**<br>~~ce~~<br>|–**9**<br>~~ce~~<br>|–**8**<br>~~ce~~<br>~~**e**eee ee~~<br>|–**8**<br>~~ce~~<br>~~**e**eee ee~~<br>|–**7**<br>~~ce~~<br>~~ee~~|–**7**<br>~~ce~~<br>~~ee~~|**Unit**<br>~~ce~~|
|---|---|---|---|---|---|---|---|---|
|||**Min**<br>~~ce~~<br>|**Max**<br>~~ce~~<br>|**Min**<br>~~ce~~<br>~~**e**e~~<br>|**Max**<br>~~ce~~<br>~~ee ee~~|**Min**<br>~~ce~~<br>~~ee~~|**Max**<br>~~ce~~<br>~~ee~~||
|½  UI<br>~~a~~<br>~~Re~~|Half of Data Bit Time, or 90<br>degree<br>~~e~~<br>~~Re~~|1<br>~~e~~<br>~~eG~~|—<br>~~e~~<br>~~eG~~|1<br>~~**e**e ~~<br>~~e~~<br>~~eG~~|—<br> ~~ee ee~~<br>~~eG~~|1.179<br>~~ee~~<br>~~eG~~|—<br>~~ee~~|ns|
|Output TX to Input RX Margin per Edge<br>~~Re~~||0.15<br>~~eG~~|—<br>~~eG~~|0.081<br>~~eG~~|—<br>~~eG~~|0.095<br>~~eG~~|—|ns|
|**Generic DDRX2 Inputs/Outputs with Clock and Data Centered at Pin (GDDRX2_RX/TX.ECLK.Centered) using PCLK Clock Input –**<br>**Figure 3.7and Figure 3.9**<br>~~Re eG~~<br>~~T_T~~|||||||||
|tSU_GDDRX2<br>~~ee~~<br>~~po~~|Data Setup before CLK Input<br>~~ee~~|—<br>~~ee~~|—<br>~~ee~~|—<br>~~ee~~|—<br>~~ee~~|—<br>~~ee~~|—<br>~~ee~~|ns<br>~~ee~~|
|||0.175<br>~~ee~~<br>~~po~~|—<br>~~ee~~<br>~~po~~|0.175<br>~~ee~~<br>~~po~~|—<br>~~ee~~<br>~~po~~|0.206<br>~~ee~~<br>~~po~~|—<br>~~ee~~<br>~~po~~|UI<br>~~ee~~<br>~~po~~|
|tHO_GDDRX2<br>~~poa~~|Data Hold after CLK Input<br>~~ce~~|0.175<br>~~po~~<br>~~ce~~|—<br>~~po~~<br>~~ee~~|0.175<br>~~po~~<br>~~ee~~|—<br>~~po~~<br>~~ee~~|0.175<br>~~po~~<br>~~ee~~|—<br>~~po~~<br>~~eee~~|ns<br>~~po~~<br>~~eee~~|
|tDVB_GDDRX2<br>~~poa~~<br>~~a~~|Output Data Valid Before<br>CLK Output<br>~~ce~~<br>~~a~~|0.177<br>~~po~~<br>~~ce~~|—<br>~~po~~<br>~~ee~~|0.177<br>~~po~~<br>~~ee~~|—<br>~~po~~<br>~~ee~~|0.206<br>~~po~~<br>~~ee~~|—<br>~~po~~<br>~~eee~~|ns<br>~~po~~<br>~~eee~~|
|||0.38<br>~~ce~~<br>~~a~~<br>~~ce~~|—<br>~~ee~~<br>~~ee~~|0.352<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee eee~~|0.415<br>~~ee~~<br>~~eee~~|—<br>~~eee~~<br>~~eee~~|ns + ½ UI<br>~~eee~~<br>~~eee~~|
|tDQVA_GDDRX2<br>~~a~~<br>~~a~~<br>~~ee~~|Output Data Valid After CLK<br>Output<br>~~ce~~<br>~~a~~<br>|–0.12<br>~~ce ~~<br>~~ce~~<br>~~ee~~<br>|—<br> ~~ee ~~<br>~~ee~~<br>~~ed~~<br>|–0.148<br> ~~ee ~~<br>~~ee~~<br>~~ed~~<br>|—<br> ~~ee~~<br>~~ee eee~~<br>|–0.174<br>~~ee ~~<br>~~eee~~<br>|—<br> ~~eee~~<br>~~eee~~<br>|Ns<br>~~eee~~<br>~~eee~~<br>|
|||0.38<br>~~ce~~<br>~~ee~~<br>|—<br>~~ee~~<br>~~ed~~<br>|0.352<br>~~ee~~<br>~~ed~~<br>|—<br>~~ee eee~~<br><br>~~GG~~|0.415<br>~~eee~~<br><br>~~GG~~|—<br>~~eee~~<br><br>~~GG~~|ns + ½ UI<br>~~eee~~<br>|
|fDATA_GDDRX2<br>~~a ~~<br>~~ee~~|Input/Output Data Rate<br> ~~a~~<br>~~GG~~|–0.12<br>~~ce ~~<br>~~ee~~<br>~~GG~~|—<br> ~~ee ~~<br>~~ed~~<br>~~GG~~|–0.148<br> ~~ee~~<br>~~ed~~<br>~~GG~~|—<br>~~ee eee~~<br>~~GG~~<br>~~GG~~|–0.174<br>~~eee~~<br>~~GG~~<br>~~GG~~|—<br>~~eee~~<br>~~GG~~<br>~~GG~~|Mbps<br>~~eee~~<br>~~GG~~|
|fMAX_GDDRX2<br>~~ee~~<br>~~po~~|Frequencyfor ECLK<br><br>~~po~~|—<br>~~ee~~<br><br>~~po~~|1000<br>~~ed~~<br><br>~~po~~|—<br>~~ed~~<br><br>~~po~~|1000<br><br>~~GG~~<br>~~po~~|—<br><br>~~GG~~<br>~~po~~|848<br><br>~~GG~~<br>~~po~~|MHz<br><br>~~po~~|
|½  UI<br>~~a~~<br>~~po~~|Half of Data Bit Time, or 90<br>degree<br>~~a~~<br>|—<br>|500<br>~~ee~~<br>|—<br>~~ee~~<br>|500<br>~~ee~~<br>|—<br>~~ee~~<br>|424<br>|ns<br>|
|fPCLK<br>~~po~~|PCLK frequency<br>|0.5<br>|—<br>|0.5<br>|—<br>|0.589<br>|—<br>|MHz<br>|
|Output TX to Input RX Marginper Edge<br>~~popT~~||0.23<br>~~pT~~|—<br>~~pT~~|0.202<br>~~pT~~|—<br>~~pT~~|0.239<br>~~pT~~|—<br>~~pT~~|ns<br>~~pT~~|
|**Generic DDRX2 Inputs/Outputs with Clock and Data Aligned at Pin (GDDRX2_RX/TX.ECLK.Aligned) using PCLK Clock Input –**<br>**Figure 3.8andFigure 3.10**<br>~~pT~~<br>~~ee~~|||||||||
|tDVA_GDDRX2<br>~~ee~~<br>~~eS!~~<br>~~Bf~~|Input Data Valid After CLK<br>~~ee~~<br>~~eS!~~<br>~~po~~<br>~~Bf~~|—<br>~~ee~~<br>~~eS!~~<br>~~po~~|–0.275<br>~~ee~~<br>~~eS!~~<br>|—<br>~~ee~~<br>~~eS!~~<br>|–0.275<br>~~ee~~<br><br>|—<br>~~ee~~<br>~~___~~<br>|–0.324<br>~~ee~~<br>~~___~~<br>|ns + ½ UI<br>~~ee~~<br>~~___~~<br>|
|||—<br>~~eS!~~<br>~~po~~|0.225<br>~~eS!~~<br>|—<br>~~eS!~~<br>|0.225<br><br>|—<br>~~___~~<br>|0.265<br>~~___~~<br>|ns<br>~~___~~<br>|
|||—<br>~~eS!~~<br>~~poee~~<br>~~ee~~|0.225<br>~~eS!~~<br>~~ee~~<br>~~ee~~|—<br>~~eS! ~~<br>~~ee~~<br>~~ee~~|0.225<br> <br>~~ee~~<br>~~ee~~|—<br> ~~___~~<br>~~ee~~<br>~~ee~~|0.225<br>~~___~~<br>~~ee~~<br>~~ee~~|UI<br>~~___~~<br>~~ee~~<br>~~ee~~|
|tDVE_GDDRX2<br>~~Bf~~<br>~~a~~|Input Data Hold After CLK<br>~~Bf~~<br>~~po~~<br>|0.275<br>~~ee~~<br>~~eee~~|—<br>~~ee~~<br>~~eee~~|0.275<br>~~ee~~<br>~~eee~~|—<br>~~ee~~<br>~~eee~~|0.324<br>~~ee~~<br>~~eee~~|—<br>~~ee~~<br>~~eee~~|ns + ½ UI<br>~~ee~~<br>~~eee~~|
|||0.775<br>~~ee~~<br>~~eee~~<br>~~po~~<br>|—<br>~~ee~~<br>~~eee~~<br>|0.775<br>~~ee~~<br>~~eee~~<br>|—<br>~~ee~~<br>~~eee~~<br>|0.914<br>~~ee~~<br>~~eee~~<br>|—<br>~~ee~~<br>~~eee~~<br>|ns<br>~~ee~~<br>~~eee~~<br>|
|||0.775<br>~~ee~~<br>~~eee~~<br>~~po~~<br>|—<br>~~ee~~<br>~~eee~~<br>|0.775<br>~~ee~~<br>~~eee~~<br>|—<br>~~ee~~<br>~~eee~~<br>|0.775<br>~~ee~~<br>~~eee~~<br>|—<br>~~ee~~<br>~~eee~~<br>|UI<br>~~ee~~<br>~~eee~~<br>|
|tDIA_GDDRX2<br>~~Bf~~<br>~~a ee~~|Output Data Invalid After<br>CLK Output<br>~~Bf~~<br>~~po~~<br>~~ee~~|—<br>~~ee~~<br>~~eee~~<br>~~po~~<br>~~ee~~|0.12<br>~~ee~~<br>~~eee~~<br>~~ee~~|—<br>~~ee~~<br>~~eee~~<br>~~ee~~|0.148<br>~~ee~~<br>~~eee~~<br>~~ee~~|—<br>~~ee~~<br>~~eee~~<br>~~ee~~|0.174<br>~~ee~~<br>~~eee~~<br>~~ee~~|ns<br>~~ee~~<br>~~eee~~<br>~~ee~~|
|tDIB_GDDRX2<br>~~a ee~~<br>~~a ee~~|Output Data Invalid Before<br>CLK Output<br>~~po~~<br>~~ee~~<br>~~ee~~|—<br>~~po~~<br>~~ee~~<br>~~ee~~|0.12<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~|0.148<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~|0.174<br>~~ee~~<br>~~ee~~|ns<br>~~ee~~<br>~~ee~~|
|fDATA_GDDRX2<br>~~a ee~~<br>~~GG~~|Input/Output Data Rate<br>~~ee~~<br>~~GG~~|—<br>~~ee~~<br>~~GG~~|1000<br>~~ee~~<br>~~GG~~|—<br>~~ee~~<br>~~GG~~|1000<br>~~ee~~<br>~~GG~~|—<br>~~ee~~<br>~~GG~~|848<br>~~ee~~<br>~~GG~~|Mbps<br>~~ee~~<br>~~GG~~|
|fMAX_GDDRX2<br>~~GG~~|Frequencyfor ECLK<br>~~GG~~|—<br>~~GG~~|500<br>~~GG~~|—<br>~~GG~~|500<br>~~GG~~|—<br>~~GG~~<br>~~ee~~|424<br>~~GG~~<br>~~ee~~|MHz<br>~~GG~~<br>~~ee~~|
|½  UI<br>~~a ee~~|Half of Data Bit Time, or 90<br>degree<br>~~ee~~|0.5<br>~~ee~~|—<br>~~ee~~|0.5<br>~~ee~~|—<br>~~ee~~|0.589<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~|ns<br>~~ee~~<br>~~ee~~|
|fPCLK<br>~~po~~|PCLK frequency<br>~~po~~|—<br>~~po~~|250<br>~~po~~|—<br>~~po~~|250<br>~~po~~|—<br>~~ee~~<br>~~po~~|212.1<br>~~ee~~<br>~~po~~|MHz<br>~~ee~~<br>~~po~~|
|Output TX to Input RX Marginper Edge<br>~~pO~~||0.105<br>~~pO~~|—<br>~~pO~~|0.077<br>~~pO~~|—<br>~~pO~~|0.091<br>~~pO~~|—<br>~~pO~~|ns<br>~~pO~~|
|**Generic DDRX4 Inputs/Outputs with Clock and Data Centered at Pin (GDDRX4_RX/TX.ECLK.Centered) using PCLK Clock Input –**<br>**Figure 3.7andFigure 3.9**<br>~~pO~~<br>~~__________~~<br>~~a~~<br>~~———————eEeEEE~~|||||||||
|tSU_GDDRX4<br>~~____~~<br>~~a~~|Input Data Set-Up Before<br>CLK<br>~~___~~<br>~~———————eEeEEE~~|0.168<br>~~_________~~<br>~~———————eEeEEE~~|—<br>~~______~~<br>~~———————eEeEEE~~|0.210<br>~~______~~<br>~~———————eEeEEE~~|—<br>~~______~~<br>~~———————eEeEEE~~|0.244<br>~~______~~<br>~~———————eEeEEE~~|—<br>~~______~~<br>~~———————eEeEEE~~|ns<br>~~______~~<br>~~———————eEeEEE~~|
|||0.252<br>~~———————eEeEEE~~<br>~~a~~|—<br>~~———————eEeEEE~~<br>~~ee~~|0.252<br>~~———————eEeEEE~~<br>~~ee~~|—<br>~~———————eEeEEE~~|0.252<br>~~———————eEeEEE~~|—<br>~~———————eEeEEE~~|UI<br>~~———————eEeEEE~~|
|tHO_GDDRX4<br>~~a~~<br>~~po~~<br>~~fp~~|Input Data Hold After CLK<br>~~———————eEeEEE~~<br>~~po~~<br>~~fp~~|0.174<br>~~———————eEeEEE~~<br>~~a~~<br>~~po~~<br>~~fp~~|—<br>~~———————eEeEEE~~<br>~~ee~~<br>~~po~~<br>~~fp~~|0.210<br>~~———————eEeEEE~~<br>~~ee~~<br>~~po~~<br>~~fp~~|—<br>~~———————eEeEEE~~<br>~~po~~|0.244<br>~~———————eEeEEE~~<br>~~po~~<br>~~ft~~|—<br>~~———————eEeEEE~~<br>~~po~~<br>~~ft~~|ns<br>~~———————eEeEEE~~<br>~~po~~<br>~~ft~~|
|tDVB_GDDRX4<br>~~fp~~|Output Data Valid Before<br>CLK Output<br>~~fp~~|0.213<br>~~fp~~<br>~~es~~|—<br>~~fp~~|0.269<br>~~fp~~|—|0.309<br>~~ft~~|—<br>~~ft~~|ns<br>~~ft~~|
|||–0.12<br>~~fp~~<br>~~es~~|—<br>~~fp~~|–0.148<br>~~fp~~|—|–0.174<br>~~ft~~|—<br>~~ft~~|ns + ½  UI<br>~~ft~~|
|tDQVA_GDDRX4<br>~~fp~~<br>~~ee~~|Output Data Valid After CLK<br>Output<br>~~fp~~<br>~~ee~~|0.213<br>~~fp~~<br>~~es~~<br>~~ee~~|—<br>~~fp~~|0.269<br>~~fp~~|—|0.309<br>~~ft~~|—<br>~~ft~~|ns<br>~~ft~~|
|||–0.12<br>~~ee~~<br>~~a~~|—|–0.148|—|–0.174|—|ns + ½  UI|
|fDATA_GDDRX4<br>~~ee~~<br>~~po~~|Input/Output Data Rate<br>~~ee~~<br>~~po~~|—<br>~~ee~~<br>~~a~~<br>~~po~~|1500<br>~~po~~|—<br>~~po~~|1200<br>~~po~~|—<br>~~po~~|1034<br>~~po~~|Mbps<br>~~po~~|
|fMAX_GDDRX4<br>~~FG~~|Frequencyfor ECLK<br>~~FG~~|—<br>~~FG~~|750<br>~~FG~~|—<br>~~FG~~|600<br>~~FG~~|—<br>~~FG~~|517<br>~~FG~~|MHz<br>~~FG~~|



© 2021-2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02102-1.7 

86 

**MachXO5-NX Family** 

**Data Sheet** 

|**Parameter**<br>~~ce~~<br>~~a~~|**Description**<br>~~ce~~<br>~~ee~~|–**9**<br>~~ce~~|–**9**<br>~~ce~~|–**8**<br>~~ce~~<br>~~eeee ee~~|–**8**<br>~~ce~~<br>~~eeee ee~~|–**7**<br>~~ce~~<br>~~ee~~|–**7**<br>~~ce~~<br>~~ee~~|**Unit**<br>~~ce~~|
|---|---|---|---|---|---|---|---|---|
|||**Min**<br>~~ce~~<br>~~ee~~<br>~~ee~~|**Max**<br>~~ce~~<br>~~ee~~<br>~~ee~~|**Min**<br>~~ce~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|**Max**<br>~~ce~~<br>~~ee ee~~<br>~~ee~~<br>~~ee~~|**Min**<br>~~ce~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|**Max**<br>~~ce~~<br>~~ee~~<br>~~ee~~<br>~~ee~~||
|½  UI<br>~~a~~|Half of Data Bit Time, or 90<br>degree<br>~~ee~~|0.333<br>~~ee~~|—<br>~~ee~~|0.417<br>~~ee ~~<br>~~ee~~|—<br> ~~ee ee~~<br>~~ee~~|0.483<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~|ns|
|fPCLK<br>~~a~~<br>~~po~~|PCLK Frequency<br>~~ee ~~<br>~~po~~|—<br> ~~ee~~<br>~~po~~|187.5<br>~~ee ~~<br>~~po~~|—<br> ~~ee~~<br>~~po~~|150<br>~~ee ~~<br>~~po~~|—<br> ~~ee~~<br>~~po~~|129.3<br>~~ee~~<br>~~po~~|MHz<br>~~po~~|
|Output TX to Input RX Marginper Edge<br>~~pO~~||0.08<br>~~pO~~|—<br>~~pO~~|0.102<br>~~pO~~|—<br>~~pO~~|0.116<br>~~pO~~|—<br>~~pO~~|ns<br>~~pO~~|
|**Generic DDRX4 Inputs/Outputs with Clock and Data Aligned at Pin (GDDRX4_RX/TX.ECLK.Aligned) using PCLK Clock Input, Left**<br>**and Right sides Only –Figure 3.8and Figure 3.10**|||||||||
|tDVA_GDDRX4|Input Data Valid After CLK|—<br>~~ee~~|–0.183<br>~~ee~~|—<br>~~ee ~~|–0.229<br> ~~ee~~|—<br>~~ee~~|–0.266|ns + ½ UI|
|||—<br>~~a~~|0.15|—|0.188|—|0.218|ns|
|||—<br>~~a~~|0.225|—|0.225|—|0.225|UI|
|tDVE_GDDRX4|Input Data Hold After CLK|0.183<br>~~a~~|—|0.229|—|0.266|—|ns + ½ UI|
|||0.517<br>~~a~~|—<br>|0.646<br>|—<br>|0.749<br>|—<br>|ns<br>|
|||0.775<br>~~es~~|—<br>~~es~~|0.775<br>~~es~~|—<br>~~es~~|0.775<br>~~es~~|—<br>~~es~~|UI<br>~~es~~|
|tDIA_GDDRX4|Output Data Invalid After<br>CLK Output|—|0.12|—|0.148|—|0.17|ns|
|tDIB_GDDRX4<br>~~ee~~|Output Data Invalid Before<br>CLK Output<br>~~GG~~|—<br>~~GG~~|0.12<br>~~GG~~|—<br>~~GG~~|0.148<br>~~GG~~|—<br>~~GG~~|0.174<br>~~GG~~|ns<br>~~GG~~|
|fDATA_GDDRX4<br>~~ee~~|Input/Output Data Rate<br>~~GG~~|—<br>~~GG~~|1500<br>~~GG~~|—<br>~~GG~~|1200<br>~~GG~~|—<br>~~GG~~|1034<br>~~GG~~|Mbps<br>~~GG~~|
|fMAX_GDDRX4<br>~~ee~~|Frequencyfor ECLK<br>~~GG~~|—<br>~~GG~~|750<br>~~GG~~|—<br>~~GG~~|600<br>~~GG~~|—<br>~~GG~~|517<br>~~GG~~|MHz<br>~~GG~~|
|½  UI<br>~~a~~<br>~~a~~|Half of Data Bit Time, or 90<br>degree<br>~~ee~~<br>~~a~~|0.333<br>~~ee~~|—<br>~~ee~~<br>~~GO~~|0.417<br>~~ee~~<br>~~GO~~|—<br>~~ee~~|0.483<br>~~ee~~<br>~~OO~~|—<br>~~ee~~<br>~~OO~~|ns<br>~~ee~~|
|fPCLK<br>~~a~~<br>~~GG~~<br>~~a~~|PCLK frequency<br>~~ee~~<br>~~GG~~<br>~~a~~|—<br>~~ee~~<br>~~GG~~|187.5<br>~~ee~~<br>~~GG~~<br>~~GO~~|—<br>~~ee~~<br>~~GG~~<br>~~GO~~|150<br>~~ee~~<br>~~GG~~|—<br>~~ee~~<br>~~GG~~<br>~~OO~~|129.3<br>~~ee~~<br>~~GG~~<br>~~OO~~|MHz<br>~~ee~~<br>~~GG~~|
|Output TX to Input RX Marginper Edge<br>~~a~~||0.03<br>~~GGG~~|—<br>~~GO~~<br>~~GGG~~|0.04<br>~~GO~~<br>~~GGG~~|—<br>~~GGG~~|0.044<br>~~OO~~<br>~~GGG~~|—<br>~~OO~~<br>~~GGG~~|ns<br>~~GGG~~|
|**Generic DDRX5 Inputs/Outputs with Clock and Data Centered at Pin (GDDRX5_RX/TX.ECLK.Centered) using PCLK Clock Input –**<br>**Figure 3.7and Figure 3.9**<br>~~Pf~~<br>~~_R~~<br>~~+~~|||||||||
|tSU_GDDRX5<br>~~Pf~~|Input Data Set-Up Before<br>CLK<br>~~Pf~~|0.179<br>~~_R~~|—|0.187<br>~~+~~|—<br>~~+~~|0.224<br>~~+~~|—<br>~~+~~|ns|
|||0.224<br>~~_R~~<br>~~a~~|—|0.224<br>~~+~~|—<br>~~+~~|0.224<br>~~+~~|—<br>~~+~~|UI|
|tHO_GDDRX5<br>~~Pf~~<br>~~po~~<br>~~po~~|Input Data Hold After CLK<br>~~Pf~~<br>~~po~~<br>|0.181<br>~~_R~~<br>~~a~~<br>~~po~~<br>|—<br>~~po~~|0.187<br>~~+~~<br>~~po~~|—<br>~~+~~<br>~~po~~|0.224<br>~~+~~<br>~~po~~|—<br>~~+~~<br>~~po~~|ns<br>~~po~~|
|tWINDOW_GDDRX5C<br>~~po~~<br>~~po~~|Input Data Valid Window<br>~~po~~<br>|0.36<br>~~po~~<br>|—<br>~~po~~|0.374<br>~~po~~|—<br>~~po~~|0.448<br>~~po~~|—<br>~~po~~|ns<br>~~po~~|
|tDVB_GDDRX5<br>~~poee~~|Output Data Valid Before<br>CLK Output<br>~~ee~~|0.28<br>~~a~~|—|0.269|—|0.326|—|ns|
|||–0.120<br>~~a~~|—|–0.148|—|–0.174|—|ns+½ UI|
|tDQVA_GDDRX5<br>~~Ge~~|Output Data Valid After CLK<br>Output<br>~~Ge~~|0.28<br>~~Ge~~|—<br>~~en~~|0.269<br>~~en~~|—|0.326|—|ns|
|||–0.120<br>~~Ge~~<br>~~a~~|—<br>~~en~~<br>~~ee~~|–0.148<br>~~en~~<br>~~ee~~|—|–0.174|—|ns+½ UI|
|fDATA_GDDRX5<br>~~Ge~~<br>~~GG~~|Input/Output Data Rate<br>~~Ge~~<br>~~GG~~|—<br>~~Ge ~~<br>~~a~~<br>~~GG~~|1250<br> ~~en~~<br>~~ee~~<br>~~GG~~|—<br>~~en~~<br>~~ee~~<br>~~GG~~|1200<br>~~GG~~|—<br>~~GG~~|1000<br>~~GG~~|Mbps<br>~~GG~~|
|fMAX_GDDRX5<br>~~GG~~|Frequencyfor ECLK<br>~~GG~~|—<br>~~GG~~|625<br>~~GG~~|—<br>~~GG~~|600<br>~~GG~~|—<br>~~GG~~<br>~~ee~~|500<br>~~GG~~<br>~~ee~~|MHz<br>~~GG~~<br>~~ee~~|
|½  UI<br>~~a ee~~|Half of Data Bit Time, or 90<br>degree<br>~~ee~~|0.4<br>~~ee~~|—<br>~~ee~~|0.417<br>~~ee~~|—<br>~~ee~~|0.5<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~|ns<br>~~ee~~<br>~~ee~~|
|fPCLK<br>~~po~~<br>~~pO~~|PCLK frequency<br>~~po~~<br>~~pO~~|—<br>~~po~~|125<br>~~po~~|—<br>~~po~~|120<br>~~po~~|—<br>~~ee~~<br>~~po~~|100<br>~~ee~~<br>~~po~~|MHz<br>~~ee~~<br>~~po~~|
|Output TX to Input RX Marginper Edge<br>~~pO~~||0.12|—|0.102|—|0.126|—|ns|
|**Generic DDRX5 Inputs/Outputs with Clock and Data Aligned at Pin (GDDRX5_RX/TX.ECLK.Aligned) using PCLK Clock Input –**<br>**Figure 3.8andFigure 3.10**<br>~~pO~~|||||||||
|tDVA_GDDRX5|Input Data Valid After CLK|—<br>~~a~~|–0.220|—|–0.229|—|–0.275|ns + ½ UI|
|||—<br>~~a~~<br>~~a~~|0.18|—|0.188|—|0.225|Ns|
|||—<br>~~a~~<br>~~a~~|0.225<br>|—<br>|0.225<br>|—<br>|0.225<br>|UI<br>|
|tDVE_GDDRX5|Input Data Hold After CLK|0.22<br>~~es~~|—<br>~~es~~|0.229<br>~~es~~|—<br>~~es~~|0.275<br>~~es~~|—<br>~~es~~|ns + ½ UI<br>~~es~~|
|||0.62<br>~~a~~|—|0.646|—|0.775|—|ns|
|||0.775<br>~~a~~<br>~~a~~|—|0.775|—|0.775|—|UI|
|tWINDOW_GDDRX5A<br>~~DG~~|Input Data Valid Window<br>~~DG~~|0.440<br>~~a~~<br>~~DG~~|—<br>~~DG~~|0.458<br>~~DG~~|—<br>~~DG~~|0.550<br>~~DG~~|—<br>~~DG~~|ns<br>~~DG~~|



© 2021-2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02102-1.7 

87 

**MachXO5-NX Family** 

**Data Sheet** 

|**Parameter**<br>~~ce~~<br>~~a~~|**Description**<br>~~ce~~<br>~~ee~~|–**9**<br>~~ce~~|–**9**<br>~~ce~~|–**8**<br>~~ce~~<br>~~eeee ee~~|–**8**<br>~~ce~~<br>~~eeee ee~~|–**7**<br>~~ce~~<br>~~ee~~|–**7**<br>~~ce~~<br>~~ee~~|**Unit**<br>~~ce~~|
|---|---|---|---|---|---|---|---|---|
|||**Min**<br>~~ce~~<br>~~ee~~<br>~~ee~~|**Max**<br>~~ce~~<br>~~ee~~<br>~~ee~~|**Min**<br>~~ce~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|**Max**<br>~~ce~~<br>~~ee ee~~<br>~~ee~~<br>~~ee~~|**Min**<br>~~ce~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|**Max**<br>~~ce~~<br>~~ee~~<br>~~ee~~<br>~~ee~~||
|tDIA_GDDRX5<br>~~a~~|Output Data Invalid After<br>CLK Output<br>~~ee~~|—<br>~~ee~~|0.12<br>~~ee~~|—<br>~~ee ~~<br>~~ee~~|0.148<br> ~~ee ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~|0.174<br>~~ee~~<br>~~ee~~|ns|
|tDIB_GDDRX5<br>~~a~~<br>~~|~~|Output Data Invalid Before<br>CLK Output<br>~~ee ~~<br>~~|~~|—<br> ~~ee~~<br>~~|~~|0.12<br>~~ee ~~<br>~~|~~|—<br> ~~ee~~<br>~~|~~|0.148<br>~~ee ~~<br>~~|~~|—<br> ~~ee~~<br>~~|~~|0.174<br>~~ee~~<br>~~|~~|ns<br>~~|~~|
|fDATA_GDDRX5<br>~~po~~|Input/Output Data Rate<br>~~po~~|—<br>~~po~~|1250<br>~~po~~|—<br>~~po~~|1200<br>~~po~~|—<br>~~po~~|1000<br>~~po~~|Mbps<br>~~po~~|
|fMAX_GDDRX5<br>~~po~~<br>~~a~~|Frequencyfor ECLK<br>~~po~~<br>~~ee~~|—<br>~~po~~<br>~~ee~~|625<br>~~po~~<br>~~ee~~|—<br>~~po~~<br>~~ee~~|600<br>~~po~~<br>~~ee~~|—<br>~~po~~<br>~~ee~~|500<br>~~po~~<br>~~ee~~|MHz<br>~~po~~<br>~~ee~~|
|½  UI<br>~~a~~<br>~~po~~|Half of Data Bit Time, or 90<br>degree<br>~~ee~~|0.4<br>~~ee~~|—<br>~~ee~~|0.417<br>~~ee~~|—<br>~~ee~~|0.5<br>~~ee~~|—<br>~~ee~~|ns<br>~~ee~~|
|fPCLK<br>~~a~~<br>~~po~~|PCLK frequency<br>~~ee~~|—<br>~~ee~~|125<br>~~ee~~|—<br>~~ee~~|120<br>~~ee~~|—<br>~~ee~~|100<br>~~ee~~|MHz<br>~~ee~~|
|Output TX to Input RX Marginper Edge<br>~~po~~<br>~~a~~||0.06<br>~~GG~~|—<br>~~GG~~|0.04<br>~~GG~~|—<br>~~DO~~|0.051<br>~~DO~~|—<br>~~DO~~|ns|
|**Soft D-PHY DDRX4 Inputs/Outputs with Clock and Data Centered at Pin, using PCLK Clock Input**<br>~~pt~~<br>~~ee eeee~~<br>~~eeeee~~|||||||||
|tSU_GDDRX4_MP<br>~~ee ee~~<br>~~ee~~<br>~~a~~|Input Data Set-Up Before<br>CLK<br>~~ee~~<br>|0.133<br>~~ee~~<br>~~ee~~<br>|—<br>~~ee~~<br>~~ed~~<br>|0.167<br>~~ee~~<br>~~ed~~<br>|—<br>~~ee~~<br>|0.193<br>~~eee~~<br>|—<br>~~eee~~<br>|ns<br>~~eee~~<br>|
|||0.2<br>~~ee~~<br>~~ee~~<br>|—<br>~~ee~~<br>~~ed~~<br>|0.2<br>~~ee~~<br>~~ed~~<br>|—<br>~~ee~~<br><br>~~GG~~|0.2<br>~~eee~~<br><br>~~GG~~|—<br>~~eee~~<br><br>~~GG~~|UI<br>~~eee~~<br>|
|tHO_GDDRX4_MP<br>~~ee ee~~<br>~~ee~~<br>~~a~~|Input Data Hold After CLK<br>~~ee ~~<br>~~GG~~|0.133<br> ~~ee~~<br>~~ee~~<br>~~GG~~|—<br>~~ee~~<br>~~ed~~<br>~~GG~~|0.167<br>~~ee~~<br>~~ed~~<br>~~GG~~|—<br>~~ee ~~<br>~~GG~~<br>~~GG~~|0.193<br> ~~eee~~<br>~~GG~~<br>~~GG~~|—<br>~~eee~~<br>~~GG~~<br>~~GG~~|ns<br>~~eee~~<br>~~GG~~|
|tDVB_GDDRX4_MP<br>~~ee~~<br>~~a~~<br>~~a~~|Output Data Valid Before<br>CLK Output<br><br>~~a~~|0.133<br>~~ee~~<br>|—<br>~~ed~~<br>|0.167<br>~~ed~~<br>|—<br><br>~~GG~~|0.193<br><br>~~GG~~|—<br><br>~~GG~~|ns<br>|
|||0.2<br>~~a~~<br>~~ce~~|—<br>~~ee~~|0.2<br>~~ee~~|—<br>~~GG~~<br>~~ee~~|0.2<br>~~GG~~<br>~~eee~~|—<br>~~GG~~<br>~~eee~~|UI<br>~~eee~~|
|tDQVA_GDDRX4_MP<br>~~a~~|Output Data Valid After CLK<br>Output<br>~~a~~|0.133<br>~~ce~~<br>~~ee~~|—<br>~~ee~~|0.167<br>~~ee~~|—<br>~~ee~~|0.193<br>~~eee~~|—<br>~~eee~~|ns<br>~~eee~~|
|||0.2<br>~~ce~~<br>~~ee~~|—<br>~~ee~~|0.2<br>~~ee~~|—<br>~~ee~~|0.2<br>~~eee~~|—<br>~~eee~~|UI<br>~~eee~~|
|fDATA_GDDRX4_MP<br>~~a ~~|Input Data Bit Rate for MIPI<br>PHY<br> ~~a~~|—<br>~~ce ~~<br>~~ee~~|1500<br> ~~ee ~~|—<br> ~~ee~~|1200<br>~~ee~~|—<br>~~eee~~|1034<br>~~eee~~|Mbps<br>~~eee~~|
|½  UI<br>~~a~~<br>~~ee~~<br>~~a~~|Half of Data Bit Time, or 90<br>degree<br>~~ee~~<br>~~GG~~<br>~~a~~|0.333<br>~~ee~~<br>~~GG~~|—<br>~~ee~~<br>~~GG~~|0.417<br>~~ee~~<br>~~GG~~|—<br>~~ee~~<br>~~GG~~|0.483<br>~~ee~~<br>~~GG~~<br>~~OO~~|—<br>~~ee~~<br>~~GG~~<br>~~OO~~|ns<br>~~ee~~<br>~~GG~~|
|fPCLK<br>~~a~~<br>~~ee~~<br>~~a~~|PCLK frequency<br>~~ee~~<br>~~GG~~<br>~~a~~|—<br>~~ee~~<br>~~GG~~|187.5<br>~~ee~~<br>~~GG~~|—<br>~~ee~~<br>~~GG~~|150<br>~~ee~~<br>~~GG~~|—<br>~~ee~~<br>~~GG~~<br>~~OO~~|129.3<br>~~ee~~<br>~~GG~~<br>~~OO~~|MHz<br>~~ee~~<br>~~GG~~|
|Output TX to Input RX Marginper Edge<br>~~eeGG~~<br>~~a~~||0.067<br>~~GG~~<br>~~GGG~~|—<br>~~GG~~<br>~~GGG~~|0.083<br>~~GG~~<br>~~GGG~~|—<br>~~GG~~<br>~~GGG~~|0.097<br>~~GG~~<br>~~OO~~<br>~~GGG~~|—<br>~~GG~~<br>~~OO~~<br>~~GGG~~|ns<br>~~GG~~<br>~~GGG~~|
|**Video DDRX71 Inputs/Outputs with Clock and Data Aligned at Pin (GDDRX71_RX.ECLK) using PLL Clock Input – Figure 3.12and**<br>**Figure 3.13**<br>~~ee~~|||||||||
|tRPBi_DVA<br>~~py~~<br>~~a~~|Input Valid Bit "i" switch<br>from CLK Rising Edge ("i" = 0<br>to 6, 0 aligns with CLK)<br>~~py~~<br>~~ee~~|—<br>~~py~~<br>~~—|~~<br>|0.264<br>~~py~~<br>~~|~~<br>~~|~~<br>|—<br>~~py~~<br>~~|~~<br>|0.264<br>~~py~~<br>~~|~~<br>|—<br>~~py~~<br>~~|~~<br>|0.3<br>~~py~~<br>~~ft~~|UI<br>~~py~~<br>~~ft~~|
|||—<br>~~py~~<br>~~—|~~<br>~~en~~|–0.250<br>~~py~~<br>~~|~~<br>~~|~~<br>~~ee~~|—<br>~~py~~<br>~~|~~<br>~~ee~~|–0.250<br>~~py~~<br>~~|~~<br>~~ee~~|—<br>~~py~~<br>~~|~~<br>~~ee~~|–0.249<br>~~py~~<br>~~ft~~<br>~~ee~~|ns+(½ +i)*UI<br>~~py~~<br>~~ft~~<br>~~ee~~|
|tRPBi_DVE<br>~~py~~<br>~~a~~|Input Hold Bit "i" switch<br>from CLK Rising Edge ("i" = 0<br>to 6, 0 aligns with CLK)<br>~~py~~<br>~~ee~~|0.722<br>~~py~~<br>~~—|~~<br>~~en~~|—<br>~~py~~<br>~~|~~<br>~~|~~<br>~~ee~~|0.722<br>~~py~~<br>~~|~~<br>~~ee~~|—<br>~~py~~<br>~~|~~<br>~~ee~~|0.7<br>~~py~~<br>~~|~~<br>~~ee~~|—<br>~~py~~<br>~~ft~~<br>~~ee~~|UI<br>~~py~~<br>~~ft~~<br>~~ee~~|
|||0.235<br>~~—|~~<br>~~en~~|—<br>~~|~~<br>~~|~~<br>~~ee~~|0.235<br>~~|~~<br>~~ee~~|—<br>~~|~~<br>~~ee~~|0.249<br>~~|~~<br>~~ee~~|—<br>~~ft~~<br>~~ee~~|ns+(½ +i)*UI<br>~~ft~~<br>~~ee~~|
|tTPBi_DOV<br>~~a ~~|Data Output Valid Bit "i"<br>switch from CLK Rising Edge<br>("i" = 0 to 6, 0 aligns with<br>CLK)<br> ~~ee ~~|—<br>~~— |~~<br> ~~en ~~|0.159<br>~~|~~<br>~~|~~<br> ~~ee ~~|—<br>~~|~~<br> ~~ee ~~|0.159<br>~~|~~<br> ~~ee~~|—<br>~~| ~~<br>~~ee~~|0.187<br> ~~ft~~<br>~~ee~~|ns+i*UI<br>~~ft~~<br>~~ee~~|
|tTPBi_DOI|Data Output Invalid Bit "i"<br>switch from CLK Rising Edge<br>("i" = 0 to 6, 0 aligns with<br>CLK)|0.159|—|0.159|—|0.187|—|ns+(i+ 1)*UI|
|tTPBi_skew_UI<br>~~po~~|TX skew in UI<br>~~po~~|—<br>~~po~~|0.15<br>~~po~~|—<br>~~po~~|0.15<br>~~po~~|—<br>~~po~~|0.15<br>~~po~~|UI<br>~~po~~|
|tB<br>~~po~~<br>~~po~~|Serial Data Bit Time, = 1UI<br>~~po~~<br>~~po~~|1.058<br>~~po~~<br>~~po~~|—<br>~~po~~<br>~~po~~|1.058<br>~~po~~<br>~~po~~|—<br>~~po~~<br>~~po~~|1.247<br>~~po~~<br>~~po~~|—<br>~~po~~<br>~~po~~|ns<br>~~po~~<br>~~po~~|
|fDATA_TX71<br>~~GG~~|DDR71 Serial Data Rate<br>~~GG~~|—<br>~~GG~~|945<br>~~GG~~|—<br>~~GG~~|945<br>~~GG~~|—<br>~~GG~~|802<br>~~GG~~|Mbps<br>~~GG~~|
|fMAX_TX71<br>~~po~~<br>~~pO~~|DDR71 ECLK Frequency<br>~~po~~<br>|—<br>~~po~~<br>|473<br>~~po~~<br>|—<br>~~po~~<br>|473<br>~~po~~<br>|—<br>~~po~~<br>|401<br>~~po~~<br>|MHz<br>~~po~~<br>|
|fCLKIN<br>~~pO~~|7:1 Clock(PCLK)Frequency<br>|—<br>|135<br>|—<br>|135<br>|—<br>|114.5<br>|MHz<br>|
|Output TX to Input RX Marginper Edge<br>~~pODG~~||0.159<br>~~DG~~|—<br>~~DG~~|0.159<br>~~DG~~|—<br>~~DG~~|0.187<br>~~DG~~|—<br>~~DG~~|ns<br>~~DG~~|



© 2021-2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02102-1.7 

88 

**MachXO5-NX Family** 

**Data Sheet** 

|**Parameter**<br>~~ee~~|**Description**<br>~~ee~~|–**9**<br>~~ee~~<br>~~reee~~|–**9**<br>~~ee~~<br>~~reee~~|–**8**<br>~~ee~~<br>~~eeee~~|–**8**<br>~~ee~~<br>~~eeee~~|–**7**<br>~~ee~~<br>~~ee~~|–**7**<br>~~ee~~<br>~~ee~~|**Unit**<br>~~ee~~|
|---|---|---|---|---|---|---|---|---|
|||**Min**<br>~~ee~~<br>~~re~~|**Max**<br>~~ee~~<br>~~ee~~|**Min**<br>~~ee~~<br>~~ee~~|**Max**<br>~~ee~~<br>~~ee~~|**Min**<br>~~ee~~<br>~~ee~~|**Max**<br>~~ee~~<br>~~ee~~||
|**Memory Interface**<br>~~re ee ee ee ee~~<br>~~RT~~|||||||||
|**DDR3/DDR3L READ(DQ Input Data are Aligned to DQS) –Figure 3.8**<br>~~En~~|||||||||
|tDVBDQ_DDR3<br>tDVBDQ_DDR3L<br>~~a~~|Data Input Valid before DQS<br>Input<br>~~ee~~|—<br>~~ee~~|–0.235<br>~~ee~~|—<br>~~ee~~|–0.235<br>~~ee~~|—<br>~~ee~~|–0.277<br>~~ee~~|ns + ½ UI<br>~~ee~~|
|tDVADQ_DDR3<br>tDVADQ_DDR3L<br>~~a~~|Data Input Valid after DQS<br>Input<br>~~ee~~|0.235<br>~~ee~~|—<br>~~ee~~|0.235|—|0.277|—|ns + ½ UI|
|fDATA_DDR3<br>fDATA_DDR3L<br>~~a~~|DDR Memory Data Rate<br>~~ee~~|—<br>~~ee~~|1066<br>~~ee~~|—|1066|—|904|Mb/s|
|fMAX_ECLK_DDR3<br>fMAX_ECLK_DDR3L<br>~~a~~|DDR Memory ECLK<br>Frequency<br>~~ee~~|—<br>~~ee~~|533<br>~~ee~~|—|533|—|452|MHz|
|fMAX_SCLK_DDR3<br>fMAX_SCLK_DDR3L<br>~~a~~|DDR Memory SCLK<br>Frequency|—|133.3|—|133.3|—|113|MHz|
|**DDR3/DDR3L WRITE(DQ Output Data are Centered to DQS) –Figure 3.11**|||||||||
|tDQVBS_DDR3<br>tDQVBS_DDR3L<br>~~a~~|Data Output Valid before<br>DQS Output<br>~~a ee~~|—<br>~~ee~~|–0.235<br>~~ee~~|—<br>~~ee~~|–0.235<br>~~ee~~|—<br>~~ee~~|–0.277<br>~~ee~~|ns + ½ UI<br>~~ee~~|
|tDQVAS_DDR3<br>tDQVAS_DDR3L<br>~~a~~|Data Output Valid after DQS<br>Output<br>~~a~~|0.235|—<br>~~ee~~|0.235<br>~~ee~~|—<br>~~ee~~|0.277<br>~~ee~~|—|ns + ½ UI|
|fDATA_DDR3<br>fDATA_DDR3L<br>~~a~~|DDR Memory Data Rate<br>~~ee~~|—<br>~~ee~~|1066<br>~~eee~~|—<br>~~eee~~|1066<br>~~eee~~|—<br>~~eee~~|904<br>~~eee~~|Mb/s<br>~~eee~~|
|fMAX_ECLK_DDR3<br>fMAX_ECLK_DDR3L<br>~~a~~|DDR Memory ECLK<br>Frequency<br>~~a~~|—|533<br>~~ee~~|—<br>~~ee~~|533<br>~~ee~~|—<br>~~ee~~|452|MHz|
|fMAX_SCLK_DDR3<br>fMAX_SCLK_DDR3L<br>~~a~~|DDR Memory SCLK<br>Frequency<br>~~a~~|—|133.3|—|133.3|—|113|MHz|



1. Commercial timing numbers are shown. Industrial numbers are typically slower and can be extracted from the Lattice Radiant software. 

2. General I/O timing numbers are based on LVCMOS 1.8, 8 mA, Fast Slew Rate, 0 pf load for all IOs except the bank1. For bank1, the number are based on LVCMOS 3.3, 12 mA, Fast Slew Rate, 0 pf load. Generic DDR timing are numbers based on LVDS I/O. 

DDR3 timing numbers are based on SSTL15. 

3. Uses LVDS I/O standard for measurements. 

4. Maximum clock frequencies are tested under best case conditions. System performance may vary upon the user environment. 

5. All numbers are generated with the Lattice Radiant software. 

6. This clock skew is not the internal clock network skew. Nexus family devices have very low internal clock network skew that can be approximated to 0 ps. These tskew values measured externally at system level includes additional skew added by the I/O, wire bonding and package ball. 

© 2021-2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02102-1.7 

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**MachXO5-NX Family Data Sheet** 

**==> picture [441 x 128] intentionally omitted <==**

**----- Start of picture text -----**<br>
Rx CLK (in)<br>rr.<br>re<br>Rx DATA (in)<br>tSU tSU<br>tHD tHD<br>**----- End of picture text -----**<br>


**Figure 3.7. Receiver RX.CLK.Centered Waveforms** 

**==> picture [423 x 154] intentionally omitted <==**

**----- Start of picture text -----**<br>
½ UI<br>½ UI<br>1 UI<br>Rx CLK (in)<br>or DQS input<br>Rx DATA (in)<br>or DQS input<br>Han n — nn<br>tDVA/tDVADQ<br>tDVA/tDVADQ<br>tDVE/tDVEDQ<br>tDVE/tDVEDQ<br>**----- End of picture text -----**<br>


**Figure 3.8. Receiver RX.CLK.Aligned and DDR Memory Input Waveforms** 

**==> picture [342 x 136] intentionally omitted <==**

**----- Start of picture text -----**<br>
1/2 UI 1/2 UI 1/2 UI 1/2 UI<br>Tx CLK (out)<br>or DQS Output<br>Tx DATA (out)<br>or DQ Output<br>tDVB/tDQVBS tDVB/tDQVBS<br>tDVA/tDQVA tDVA/tDQVAS<br>**----- End of picture text -----**<br>


**Figure 3.9. Transmit TX.CLK.Centered and DDR Memory Output Waveforms** 

© 2021-2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02102-1.7 

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**MachXO5-NX Family Data Sheet** 

**==> picture [309 x 120] intentionally omitted <==**

**----- Start of picture text -----**<br>
1 UI<br>+ t> |<br>Tx CLK (out) i<br>!<br>i}II I<br>tI<br>I<br>II<br>II<br>I 1<br>Tx DATA (out)<br>II<br>1 I 1 I<br>oe boi |<br>tDIB i iad tDIB 7<br>11I<br>1 ! I 1 I t<br>1 ! I tDIA 1 I t tDIA<br>**----- End of picture text -----**<br>


**Figure 3.10. Transmit TX.CLK.Aligned Waveforms** 

## **Receiver – Shown for one LVDS Channel** 

||12<br>3<br>4<br>5<br>67<br>8<br>9<br>10<br>11<br>1213<br>14<br>15<br>16<br>17<br>18<br>1920<br>21<br>22<br>23<br>24<br>25<br>26<br>27<br>28<br>29|
|---|---|
|# of Bits|12<br>3<br>4<br>5<br>67<br>8<br>9<br>10<br>11<br>1213<br>14<br>15<br>16<br>17<br>18<br>1920<br>21<br>22<br>23<br>24<br>25<br>26<br>27<br>28<br>29|
|Data In<br>756 Mb/s|~~MAAA@AADRAAAAAOAAAAAAOAAAAAAAD~~|
|Clock In<br>0!<br>1!<br>2!<br>3!<br>4||
|108 MHz|4|
||Bit #<br>Bit #<br>Bit #<br>Bit #<br>i<br>!<br>i<br>!<br>**1**<br>~~I~~<br>~~1~~<br>~~I~~<br>~~1~~|
||30 – 15<br>40 – 22<br>20 – 8<br>10 – 1<br>0x|
|**For each Channel:**<br>**7-bit Output Words**<br>**to FPGA Fabric**|31 – 16<br>32 – 17<br>33 – 18<br>34 – 19<br>41 – 23<br>42 – 24<br>43 – 25<br>44 – 26<br>21 – 9<br>22 – 10<br>23 – 11<br>24 – 12<br>11 – 2<br>12 – 3<br>13 – 4<br>14 – 5<br>0x<br>0x<br>0x<br>0x<br>i<br>!<br>**i**<br>!<br>**1**<br>1<br>1<br>1|
||35 – 20<br>45 – 27<br>25 – 13<br>15 – 6<br>0x|
||36 – 21<br>46 – 28<br>26 – 14<br>16 – 7<br>0x<br>i<br>1<br>I<br>1<br>1<br>1<br>1<br>i<br>1<br>1|
|**Transmitter – Shown for one LVDS Channel**||
|# of Bits|12<br>3<br>4<br>5<br>67<br>8<br>9<br>10<br>11<br>1213<br>14<br>15<br>16<br>17<br>18<br>1920<br>21<br>22<br>23<br>24<br>25<br>26<br>27<br>28<br>29|
|Clock Out<br>Data Out<br>756 Mb/s<br>~~KX DYZAEYA OCDE AEE~~<br>~~DAVEY AEE DEX AEN ELK~~<br>(2¥3V4Y5)~~(6X 0X7)~~(234X5)~~(eX 0X7)~~(23Y4X5)~~(8X 0X7)~~(2Y3Y4X5)<br>(6X2)<br>0!<br>1!<br>2)<br>3!<br>4||
|108 MHz||
||~~**1**~~<br>~~1~~<br>~~I~~<br>~~1~~<br>~~i~~<br>~~l~~|
||**1**<br>**i**<br>**1**<br>**1**|
||~~1~~|
|Bit #|Bit #<br>Bit #<br>Bit #|
|**For each Channel:**<br>00 – 1|10 – 8<br>20 – 15<br>30 – 22<br>~~!~~<br>!<br>i<br>!<br>**1**|
|**7-bit Output Words**<br>**to FPGA Fabric**<br>00 – 2<br>00 – 3<br>00 – 4|11 – 9<br>12 – 10<br>13 – 11<br>21 – 16<br>22 – 17<br>23 – 18<br>31 – 23<br>32 – 24<br>33 – 25<br>1<br>1<br>I<br>1|
|00 – 5|14 – 12<br>24 – 19<br>34 – 26<br>!<br>!<br>i<br>!<br>1<br>1<br>1<br>I<br>1<br>1|
|00 – 6|15 – 13<br>25 – 20<br>35 – 27|
|00 – 7|16 – 14<br>26 – 21<br>36 – 28|



**Figure 3.11. DDRX71 Video Timing Waveforms** 

© 2021-2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02102-1.7 

91 

**MachXO5-NX Family Data Sheet** 

**==> picture [457 x 175] intentionally omitted <==**

**----- Start of picture text -----**<br>
Bit 0 Bit 1 Bit i<br>1/2 UI 1/2 UI<br>CLK (in) 1 UI<br>een a<br>DATA (in)<br>ee tSU_0 ee) eeen<br>tHD_0<br>tSU_i<br>tHD_i<br>**----- End of picture text -----**<br>


**Figure 3.12. Receiver DDRX71_RX Waveforms** 

**==> picture [401 x 163] intentionally omitted <==**

**----- Start of picture text -----**<br>
Bit 0 Bit 1 Bit i<br>1 UI<br>CLK (out) ee a<br>DATA (out)<br>tDIB_0 aor oe<br>tDIA_0<br>tDIB_i<br>**----- End of picture text -----**<br>


**==> picture [19 x 8] intentionally omitted <==**

**----- Start of picture text -----**<br>
tDIA_i<br>**----- End of picture text -----**<br>


**Figure 3.13. Transmitter DDRX71_TX Waveforms** 

© 2021-2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02102-1.7 

92 

**MachXO5-NX Family Data Sheet** 

## **3.19. sysCLOCK PLL Timing (VCC = 1.0 V)** 

Over recommended operating conditions. 

## **Table 3.35. sysCLOCK PLL Timing (VCC = 1.0 V)** 

|**Parameter**<br>~~pf~~|**Descriptions**<br>~~pf~~|**Conditions**<br>~~pf~~|**Min**<br>~~pf~~|**Typ. **<br>~~pf~~<br>~~QO~~|**Max**<br>~~pf~~<br>~~QO~~|**Units**<br>~~pf~~|
|---|---|---|---|---|---|---|
|fIN<br>~~GG~~|Input Clock Frequency (CLKI, CLKFB)<br>~~GG~~|—<br>~~GG~~<br>~~GG~~|18<br>~~GG~~<br>~~GG~~|—<br>~~GG~~<br>~~QO~~<br>~~OO~~|500<br>~~GG~~<br>~~QO~~<br>~~OO~~|MHz<br>~~GG~~|
|fOUT<br>~~a~~|Output Clock Frequency<br>~~a~~|—<br>~~a~~<br>~~GG~~<br>~~GG~~|6.25<br>~~a~~<br>~~GG~~<br>~~GG~~|—<br>~~QO~~<br>~~a~~<br>~~OO~~<br>~~OO~~|800<br>~~QO~~<br>~~a~~<br>~~OO~~<br>~~OO~~|MHz<br>~~a~~|
|fVCO<br>~~Ce~~|PLL VCO Frequency<br>~~Ce~~|—<br>~~GG~~<br>~~Ce~~<br>~~GG~~<br>~~ee~~|800<br>~~GG ~~<br>~~Ce~~<br>~~GG~~<br>~~ee~~|—<br> ~~OO~~<br>~~Ce~~<br>~~OO~~<br>~~eee~~|1600<br>~~OO~~<br>~~Ce~~<br>~~OO~~<br>~~eee~~|MHz<br>~~Ce~~<br>~~eee~~|
|fPFD|Phase Detector Input Frequency|Without Fractional-N<br>Enabled<br>~~GG~~<br>~~ee~~<br>~~ee~~|18<br>~~GG ~~<br>~~ee~~<br>~~ee~~|—<br> ~~OO~~<br>~~eee~~<br>~~eee~~|500<br>~~OO~~<br>~~eee~~<br>~~eee~~|MHz<br>~~eee~~<br>~~eee~~|
|||With Fractional-N<br>Enabled<br>~~ee~~<br>~~ee~~|18<br>~~ee ~~<br>~~ee~~|—<br> ~~eee~~<br>~~eee~~|100<br>~~eee~~<br>~~eee~~|MHz<br>~~eee~~<br>~~eee~~|
|**AC Characteristics**<br>~~ee eee~~|||||||
|tDT<br>~~GGG~~|Output Clock DutyCycle<br>~~GGG~~<br>~~Ge~~|—<br>~~GGG~~<br>~~e~~|45<br>~~GGG~~<br>~~GO~~|—<br>~~GGG~~<br>~~GO~~|55<br>~~GGG~~<br>~~GO~~|%<br>~~GGG~~|
|tPH4<br>~~eG~~|Output Phase Accuracy<br>~~eG~~<br>~~Ge~~|—<br>~~eG~~<br>~~e~~|–5<br>~~eG~~<br>~~GO~~|—<br>~~eG~~<br>~~GO~~|5<br>~~eG~~<br>~~GO~~|%<br>~~eG~~|
|tOPJIT1<br>~~p~~<br>~~pO~~<br>~~po~~|Output Clock Period Jitter<br>~~Ge~~<br>~~pO~~|fOUT≥ 200 MHz<br>~~e~~|—<br>~~GO~~<br>~~e~~~~**e**~~|—<br>~~GO~~|250<br>~~GO~~|psp-p|
|||fOUT< 200 MHz<br>~~e~~<br>~~ee~~|—<br>~~GO~~<br>~~ee~~<br>~~e~~~~**e**~~|—<br>~~GO~~<br>~~ee~~|0.05<br>~~GO~~<br>~~ee~~|UIPP<br>~~ee~~|
||Output Clock Cycle-to-Cycle Jitter<br>~~Ge~~<br>~~pO~~|fOUT≥ 200 MHz<br>~~e~~<br>~~ee~~<br>~~——ry———~~|—<br>~~GO~~<br>~~ee~~<br>~~e~~~~**e**~~<br>~~——ry———~~<br>~~ee~~|—<br>~~GO~~<br>~~ee~~<br>~~——ry———~~<br>~~ee~~|250<br>~~GO~~<br>~~ee~~<br>~~——ry———~~|psp-p<br>~~ee~~<br>~~——ry———~~|
|||fOUT< 200 MHz<br>~~——ry———~~<br>~~ee~~|—<br>~~e~~~~**e**~~<br>~~——ry———~~<br>~~ee~~<br>~~ee~~|—<br>~~——ry———~~<br>~~ee~~<br>~~ee~~|0.05<br>~~——ry———~~<br>~~ee~~|UIPP<br>~~——ry———~~<br>~~ee~~|
||Output Clock Phase Jitter<br>~~pO~~<br>~~pO~~|fPFD≥ 200 MHz<br>~~e~~|—<br>~~e~~~~**e**~~<br>~~ee~~<br>~~e~~|—<br>~~ee~~|250|psp-p|
|||60 MHz ≤ fPFD< 200 MHz<br>~~ee~~<br>~~es~~|—<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~|350<br>~~ee~~<br>~~ee~~|psp-p<br>~~ee~~|
|||30 MHz ≤ fPFD< 60 MHz<br>~~es~~|—<br>~~ee~~<br>~~ee~~|—<br>~~ee~~|450<br>~~ee~~|psp-p|
|||18 MHz ≤ fPFD< 30 MHz<br>~~es~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~|650<br>~~ee~~<br>~~ee~~|psp-p<br>~~ee~~|
||Output Clock Period Jitter (Fractional-N)<br>~~pO~~<br>~~po~~|fOUT≥ 200 MHz<br>~~ee~~<br>~~——ry——~~|—<br>~~ee~~<br>~~ee~~<br>~~——ry——~~|—<br>~~ee~~<br>~~——ry——~~|350<br>~~ee~~<br>~~——ry——~~|psp-p<br>~~ee~~<br>~~——ry——~~|
|||fOUT< 200 MHz<br>~~——ry——~~<br>~~ee~~|—<br>~~ee~~<br>~~——ry——~~<br>~~ee~~|—<br>~~——ry——~~<br>~~ee~~|0.07<br>~~——ry——~~<br>~~ee~~|UIPP<br>~~——ry——~~<br>~~ee~~|
||Output Clock Cycle-to-Cycle Jitter<br>(Fractional-N)<br>~~pO~~<br>~~po~~|fOUT≥ 200 MHz<br>~~ee~~<br>~~—ry—ry—y——~~|—<br>~~ee~~<br>~~ee~~<br>~~—ry—ry—y——~~|—<br>~~ee~~<br>~~—ry—ry—y——~~|400<br>~~ee~~<br>~~—ry—ry—y——~~|psp-p<br>~~ee~~<br>~~—ry—ry—y——~~|
|||fOUT< 200 MHz<br>~~ee~~<br>~~—ry—ry—y——~~<br>~~ee~~|—<br>~~ee~~<br>~~—ry—ry—y——~~<br>~~ee~~<br>~~GO~~|—<br>~~ee~~<br>~~—ry—ry—y——~~<br>~~ee~~<br>~~OO~~|0.08<br>~~ee~~<br>~~—ry—ry—y——~~<br>~~ee~~<br>~~OO~~|UIPP<br>~~ee~~<br>~~—ry—ry—y——~~<br>~~ee~~|
|fBW3<br>~~po~~<br>~~eG~~<br>~~i~~|PLL LoopBandwidth<br>~~po~~<br>~~eG~~<br>~~i~~|—<br>~~ee~~<br>~~—ry—ry—y——~~<br>~~ee~~<br>~~eG~~|0.45<br>~~ee~~<br>~~—ry—ry—y——~~<br>~~ee~~<br>~~eG~~<br>~~GO~~|<br>~~ee~~<br>~~—ry—ry—y——~~<br>~~ee~~<br>~~eG~~<br>~~OO~~<br>~~OO~~|13<br>~~ee~~<br>~~—ry—ry—y——~~<br>~~ee~~<br>~~eG~~<br>~~OO~~<br>~~OO~~|MHz<br>~~ee~~<br>~~—ry—ry—y——~~<br>~~ee~~<br>~~eG~~|
|tLOCK2<br>~~eG~~<br>~~GG~~<br>~~i~~|PLL Lock-in Time<br>~~eG~~<br>~~GG~~<br>~~i~~|—<br>~~eG~~<br>~~GG~~|—<br>~~eG~~<br>~~GO ~~<br>~~GG~~|—<br>~~eG~~<br> ~~OO~~<br>~~GG~~<br>~~OO~~|10<br>~~eG~~<br>~~OO~~<br>~~GG~~<br>~~OO~~|ms<br>~~eG~~<br>~~GG~~|
|tUNLOCK<br>~~i~~<br>~~pe~~|PLL Unlock Time(from RESETgoes HIGH)<br>~~i~~<br>|—<br>~~GGG~~<br>|—<br>~~GGG~~<br>|—<br>~~OO~~<br>~~GGG~~<br>|50<br>~~OO~~<br>|ns<br>|
|tIPJIT<br>~~pe~~|Input Clock Period Jitter<br>~~—ry—y——y——~~|fPFD≥ 20 MHz<br>~~GGG~~<br>~~—ry—y——y——~~<br>~~es~~|—<br>~~GGG~~<br>~~—ry—y——y——~~<br>~~ee~~|—<br>~~GGG~~<br>~~—ry—y——y——~~<br>~~ee~~|500<br>~~—ry—y——y——~~<br>~~ee~~|psp-p<br>~~—ry—y——y——~~|
|||fPFD< 20 MHz<br>~~GGG~~<br>~~—ry—y——y——~~<br>~~es~~|—<br>~~GGG~~<br>~~—ry—y——y——~~<br>~~ee~~|—<br>~~GGG~~<br>~~—ry—y——y——~~<br>~~ee~~<br>~~OO~~|0.01<br>~~—ry—y——y——~~<br>~~ee~~<br>~~OO~~|UIPP<br>~~—ry—y——y——~~|
|tHI<br>~~pe ~~<br>~~GO~~|Input Clock High Time<br> ~~—ry—y——y——~~<br>~~GO~~|90% to 90%<br>~~GGG~~<br>~~—ry—y——y——~~<br>~~es~~<br>~~GO~~|0.5<br>~~GGG~~<br>~~—ry—y——y——~~<br>~~ee~~<br>~~GO~~|—<br>~~GGG~~<br>~~—ry—y——y——~~<br>~~ee~~<br>~~GO~~<br>~~OO~~<br>~~OO~~|—<br>~~—ry—y——y——~~<br>~~ee~~<br>~~GO~~<br>~~OO~~<br>~~OO~~|ns<br>~~—ry—y——y——~~<br>~~GO~~|
|tLO<br>~~GO~~<br>~~GO~~<br>~~a~~|Input Clock Low Time<br>~~GO~~<br>~~GO~~|10% to 10%<br>~~GO~~<br>~~GO~~|0.5<br>~~GO~~<br>~~GO~~|—<br>~~GO~~<br>~~OO~~<br>~~GO~~<br>~~OO~~<br>~~OO~~|—<br>~~GO~~<br>~~OO~~<br>~~GO~~<br>~~OO~~<br>~~OO~~|ns<br>~~GO~~<br>~~GO~~|
|tRST<br>~~GO~~<br>~~GG~~<br>~~a~~|RST/ Pulse Width<br>~~GO~~<br>~~GG~~|—<br>~~GO~~<br>~~GG~~|1<br>~~GO~~<br>~~GG~~|—<br>~~GO~~<br>~~OO~~<br>~~GG~~<br>~~OO~~|—<br>~~GO~~<br>~~OO~~<br>~~GG~~<br>~~OO~~|ms<br>~~GO~~<br>~~GG~~|
|fSSC_MOD<br>~~a~~|Spread Spectrum Clock Modulation<br>Frequency|—|20|—<br>~~OO~~|200<br>~~OO~~|kHz|
|fSSC_MOD_AMP<br>~~a~~|Spread Spectrum Clock Modulation<br>Amplitude Range|—|0.25|—|2.00|%|
|fSSC_MOD_STEP<br>~~a~~|Spread Spectrum Clock Modulation<br>Amplitude StepSize|—|—|0.25|—|%|



**Notes** : 

1. Jitter sample is taken over 10,000 samples for Period jitter, and 1,000 samples for Cycle-to-Cycle jitter of the primary PLL output with clean reference clock with no additional I/O toggling. 

2. Output clock is valid after tLOCK for PLL reset and dynamic delay adjustment. 

3. Result from Lattice Radiant software. 

4. CLKOS as compared to CLKOP output for one phase step at the maximum VCO frequency. 

© 2021-2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02102-1.7 

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**MachXO5-NX Family Data Sheet** 

## **3.20. Internal Oscillators Characteristics** 

**Table 3.36. Internal Oscillators (VCC = 1.0 V)** 

|**Symbol**|**Parameter Description**|**Min**|**Typ**|**Max**|**Unit**|
|---|---|---|---|---|---|
|fCLKHF|HFOSC CLKK Clock Frequency|418.5|450|481.5|MHz|
|fCLKLF|LFOSC CLKK Clock Frequency|25.6|32|38.4|kHz|
|DCHCLKHF|HFOSC DutyCycle (Clock High Period)|45|50|55|%|
|DCHCLKLF|LFOSC Duty Cycle (Clock High Period)|45|50|55|%|



## **3.21. Flash Download Time** 

## **Table 3.37. Flash Download Time** 

|**Symbol**|**Parameter**|**Device**|**Typ. **|**Units**|
|---|---|---|---|---|
|tREFRESH|POR to Device I/O Active|LFMXO5-25|46|ms|



**Notes** : 

- Assumes sysMEM EBR initialized to an all zero pattern if they are used. 

- The Flash download time is measured starting from the maximum voltage of POR trip point. 

## **3.22. Flash Program and Erase Current** 

**Table 3.38. Program and Erase Supply Current** 

**Symbol Parameter Device Typ. Units** ~~ee~~ Icc Core Power Supply LFMXO5-25 26 mA 

## **3.23. User I[2] C Characteristics** 

**Table 3.39. User I[2] C Specifications (VCC = 1.0 V)** 

|**Symbol**|**Parameter**<br>**Description**|**STD Mode**|**STD Mode**|**STD Mode**|**FAST Mode**|**FAST Mode**|**FAST Mode**|**FAST Mode Plus2**|**FAST Mode Plus2**|**FAST Mode Plus2**|**Units**|
|---|---|---|---|---|---|---|---|---|---|---|---|
|||**Min**|**Typ**|**Max**|**Min**|**Typ**|**Max**|**Min**|**Typ**|**Max**||
|fscl|SCL Clock<br>Frequency|—|—|100|—|—|400|—|—|1000|kHz|
|TDELAY1|Optional delay<br>through delayblock|—|62|—|—|62|—|—|62|—|ns|



**Notes** : 

1. Refer to the I[2] C Specification for timing requirements. User design should set constraints in Lattice Design Software to meet this industrial I[2] C Specification. 

2. Fast Mode Plus maximum speed may be achieved by using external pull up resistor on I[2] C bus. Internal pull up may not be sufficient to support the maximum speed. 

© 2021-2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02102-1.7 

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**MachXO5-NX Family Data Sheet** 

## **3.24. Analog-Digital Converter (ADC) Block Characteristics** 

**Table 3.40. ADC Specifications[1]** 

|**Symbol**<br>~~es~~|**Description**<br>~~GG~~|**Condition**<br>~~GG~~|**Min**<br>~~GG~~|**Typ**<br>~~GG~~|**Max**<br>~~GG~~|**Unit**<br>~~GG~~|
|---|---|---|---|---|---|---|
|VREFINT_ADC<br>~~es~~<br>~~aa~~|ADC Internal Reference<br>Voltage4<br>~~GG~~<br>~~aa~~|—<br>~~GG~~<br>~~aa~~|1.142<br>~~GG~~|1.2<br>~~GG~~|1.262<br>~~GG~~|V<br>~~GG~~|
|VREFEXT_ADC<br>~~a~~|ADC External Reference<br>Voltage<br>~~a~~<br>~~ee~~|—<br>~~ee~~|1.0<br>~~ee~~|—<br>~~ee~~|1.8<br>~~ee~~|V<br>~~ee~~|
|NRES_ADC<br>~~GG~~|ADC Resolution<br>~~GG~~|—<br>~~GG~~|—<br>~~GG~~|12<br>~~GG~~|—<br>~~GG~~|bits<br>~~GG~~|
|ENOBADC<br>~~a~~|Effective Number of Bits|—|9.9|11<br>~~ee~~|—<br>~~ee~~|bits<br>~~ee~~|
|VSR_ADC|ADC Input Range|Bipolar Mode, Internal VREF<br>~~ee~~<br>~~a~~|VCM_ADC ―<br>VREFINT_ADC/4<br>~~ee~~<br>|VCM_ADC<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>|VCM_ADC+<br>VREFINT_ADC/4<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>|V<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>|
|||Bipolar Mode, External VREF<br>~~ee~~<br>~~a~~<br>~~a~~|VCM_ADC ―<br>VREFEXT_ADC/4<br>~~ee~~<br>|VREFEXT_ADC<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>|VCM_ADC+<br>VREFEXT_ADC/4<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>|V<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|
|||Uni-polar Mode, Internal<br>VREF<br>~~a ~~<br>~~a~~|0<br> ~~ee~~|—<br>~~ee ~~<br>~~ee~~|VREFINT_ADC<br> ~~ee~~<br>~~ee~~|V<br>~~ee~~<br>~~eeee~~|
|||Uni-polar Mode, External<br>VREF<br><br>~~a~~|0<br><br>~~ee~~|—<br><br>~~ee~~<br>~~ee~~|VREFEXT_ADC<br><br>~~ee~~<br>~~ee~~|V<br>~~ee~~<br>~~ee~~<br>~~ee~~|
|VCM_ADC<br>~~cee~~|ADC Input Common Mode<br>Voltage (for fully differential<br>signals)<br>~~cee~~|Internal VREF<br>~~cee~~|—<br>~~cee~~<br>~~ee~~|VREFINT_ADC/2<br>~~cee~~<br>~~ee~~|—<br>~~cee~~<br>~~ee~~|V<br>~~cee~~<br>~~ee~~|
|||External VREF<br>~~cee~~<br>~~CT~~|—<br>~~cee~~<br>~~ee~~<br>~~CT~~|VREFEXT_ADC/2<br>~~cee~~<br>~~ee~~<br>~~CT~~|—<br>~~cee~~<br>~~ee~~<br>~~CT~~|V<br>~~cee~~<br>~~ee~~<br>~~CT~~|
|fCLK_ADC<br>~~a eG~~|ADC Clock Frequency<br>~~eG~~|—<br>~~eG~~|—<br>~~ee ~~<br>~~eG~~|25<br> ~~ee ~~<br>~~eG~~|50<br> ~~ee~~<br>~~eG~~|MHz<br>~~ee~~<br>~~eG~~|
|fINPUT_ADC<br>~~a~~|ADC Input Frequency|@ Sampling Frequency =<br>1 Mbps|—|—|500|kHz|
|FSADC<br>~~a~~<br>~~ee~~|ADC SamplingRate<br>~~e~~<br>|—<br>~~e~~~~**G**~~<br>|—<br>~~**G**~~|1<br>~~**G**~~|—<br>~~**G**~~|MS/s<br>~~**G**~~|
|NTRACK_ADC<br><br>~~ee~~|ADC Input TrackingTime<br>~~e~~<br>~~G~~|—<br>~~e~~~~**G**~~<br>~~G~~|4<br>~~**G**~~|—<br>~~**G**~~|—<br>~~**G**~~|cycles3<br>~~**G**~~|
|RIN_ADC<br><br>~~ee~~<br>~~a~~|ADC Input Equivalent<br>Resistance<br>~~e~~<br>~~G~~<br>~~ee~~|—<br>~~e~~~~**G**~~<br>~~G~~<br>~~ee~~|—<br>~~**G**~~<br>~~ee~~|116<br>~~**G**~~<br>~~ee~~|—<br>~~**G**~~<br>~~ee~~|KΩ<br>~~**G**~~<br>~~ee~~|
|tCAL_ADC<br>~~a~~<br>~~a~~|ADC Calibration Time<br>~~ee~~<br>~~eG~~|—<br>~~ee~~<br>~~eG~~|—<br>~~ee~~<br>~~eG~~|—<br>~~ee~~<br>~~eG~~|6500<br>~~ee~~<br>~~eG~~|cycles3<br>~~ee~~<br>~~eG~~|
|LOUTput_ADC<br>~~a~~<br>~~a~~|ADC Conversion Time<br>~~eG~~<br>~~a~~|Includes minimum tracking<br>time of four cycles<br>~~eG~~|25<br>~~eG~~|—<br>~~eG~~|—<br>~~eG~~|cycles3<br>~~eG~~|
|DNLADC<br>~~a~~<br>~~a~~|ADC Differential<br>Nonlinearity<br>~~a~~<br>~~a~~|—|–1|—|1|LSB|
|INLADC<br>~~a~~<br>~~a~~|ADC Integral Nonlinearity<br>~~a~~<br>~~a~~|—<br>~~Ge~~|–22<br>~~Ge~~|—<br>~~Ge~~|2.21<br>~~Ge~~|LSB<br>~~Ge~~|
|SFDRADC<br>~~a~~<br>~~a~~|ADC Spurious Free Dynamic<br>Range<br>~~a~~|—<br>~~Ge~~|67.7<br>~~Ge~~|77<br>~~Ge~~|—<br>~~Ge~~|dBc<br>~~Ge~~|
|THDADC<br>~~a~~<br>~~a~~|ADC Total Harmonic<br>Distortion|—|—|-76|-66.8|dB|
|SNRADC<br>~~a~~<br>~~a~~|ADC Signal to Noise Ratio<br>~~eG~~|—<br>~~eG~~|61.9<br>~~eG~~|68<br>~~eG~~|—<br>~~eG~~|dB<br>~~eG~~|
|SNDRADC<br>~~aa~~|ADC Signal to Noise Plus<br>Distortion Ratio<br>~~aa~~|—<br>~~aa~~|61.7|67|—|dB|
|ERRGAIN_ADC<br>~~aa~~<br>~~a~~|ADC Gain Error<br>~~aa~~<br>~~a~~<br>~~eG~~|—<br>~~aa~~<br>~~eG~~|–0.5<br>~~eG~~|—<br>~~eG~~|0.5<br>~~eG~~|% FSADC<br>~~eG~~|
|ERROFFSET_ADC<br>~~a~~|ADC Offset Error|—|–2|—|2|LSB|
|CIN_ADC<br>~~a~~|ADC Input Equivalent<br>Capacitance<br>~~ee~~|—<br>~~ee~~|—<br>~~ee~~|2<br>~~ee~~|—<br>~~ee~~|pF<br>~~ee~~|



**Notes** : 

1. ADC is available in select speed grades. See Ordering Information. 

2. Not tested; guaranteed by design. 

3. ADC Sample Clock cycles. See ADC User Guide for Nexus Platform (FPGA-TN-02129) for more details. 

4. Internal voltage reference is only for internal testing purpose. It is not recommended for customer design. User should always use the part with external reference voltage. 

© 2021-2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02102-1.7 

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**MachXO5-NX Family Data Sheet** 

## **3.25. Comparator Block Characteristics** 

**Table 3.41. Comparator Specifications** 

|**Symbol**<br>~~=S—s5S=~~|**Description**<br>~~=S—s5S=~~|**Min**<br>~~=S—s5S=~~|**Typ**<br>~~=S—s5S=~~|**Max**<br>~~=S—s5S=~~|**Unit**<br>~~=S—s5S=~~|
|---|---|---|---|---|---|
|fIN_COMP<br>~~=S—s5S=~~|Comparator Input Frequency<br>~~=S—s5S=~~|—<br>~~=S—s5S=~~|—<br>~~=S—s5S=~~|10<br>~~=S—s5S=~~|MHz<br>~~=S—s5S=~~|
|VIN_COMP<br>~~=S—s5S=~~|Comparator Input Voltage<br>~~=S—s5S=~~|0<br>~~=S—s5S=~~|—<br>~~=S—s5S=~~|VCCADC18<br>~~=S—s5S=~~|V<br>~~=S—s5S=~~|
|VOFFSET_COMP<br>~~=S—s5S=~~|Comparator Input Offset<br>~~=S—s5S=~~|–23<br>~~=S—s5S=~~|—<br>~~=S—s5S=~~|24<br>~~=S—s5S=~~|mV<br>~~=S—s5S=~~|
|VHYST_COMP<br>~~=S—s5S=~~|Comparator Input Hysteresis<br>~~=S—s5S=~~|10<br>~~=S—s5S=~~|—<br>~~=S—s5S=~~|31<br>~~=S—s5S=~~|mV<br>~~=S—s5S=~~|
|VLATENCY_COMP<br>~~=S—s5S=~~|Comparator Latency<br>~~=S—s5S=~~|—<br>~~=S—s5S=~~|—<br>~~=S—s5S=~~|31<br>~~=S—s5S=~~|ns<br>~~=S—s5S=~~|



## **3.26. Digital Temperature Readout Characteristics** 

|**3.26. Digital Temperature Readout Characteristics**||
|---|---|
|Digital temperature Readout (DTR) is implemented in one of the channels of ADC1.||
|**Table 3.42. DTR Specifications1, 2**<br>**Symbol**<br>**Description**<br>**Condition**<br>**Min**<br>**Typ**<br>**Max**<br>**Unit**<br>DTRRANGE<br>DTR Detect Temperature<br>Range<br>—<br>–40<br>—<br>100<br>°C<br>DTRACCURACY<br>DTR Accuracy<br>with external voltage1<br>reference range of 1.0 V<br>to 1.8 V<br>–13<br>±4<br>13<br>°C<br>DTRRESOLUTION<br>DTR Resolution<br>with external voltage<br>reference<br>–0.3<br>—<br>0.3<br>°C<br>~~Saeeeseee~~||
|**Notes**:||
|1.<br>External voltage reference (VREF) should be 0.1% accurate or better. DTR sensitivity to VREF is -4.1 °C per VREF per-cent (for||
|example, if the VREF is 1 % low, then the DTR will read +4.1 °C high).||



2. DTR is available in select speed grades. See the Ordering Information section. 

## **3.27. Hardened SGMII Receiver Characteristics** 

## **3.27.1. SGMII Rx Specifications** 

Over recommended operating conditions. 

**Table 3.43. SGMII Rx** 

**Symbol Description Test Conditions Min Typ Max Unit** fDATA SGMII Data Rate — — 1250 — MHz SGMII Reference Clock Frequency (Data fREFCLK Rate/10) — — 125 — MHz JTOL_Dj Periodic jitter Jitter Tolerance, Deterministic — — 0.1[1] UI < 300 kHz Periodic jitter JTOL_Tj Jitter Tolerance, Total < 300 kHz — — 0.3[1] UI ~~ae~~ Δf/f Data Rate and Reference Clock Accuracy — –300 — 300 ppm **Note:** 1. JTOT can meet the following jitter mask specification: 0 to 3.5 kHz: 10 UI; 3.5 to 700 kHz: log-log slope 10 UI to 0.05 UI; above 700 kHz: 0.05 UI. 

© 2021-2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. 

All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02102-1.7 

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**MachXO5-NX Family Data Sheet** 

## **3.28. sysCONFIG Port Timing Specifications** 

Over recommended operating conditions. 

## **Table 3.44. sysCONFIG Port Timing Specifications** 

|**Symbol**<br>~~ee~~|**Parameter**<br>|**Device**<br>|**Min**<br>|**Typ.**<br>|**Max**<br>|**Unit**<br>|
|---|---|---|---|---|---|---|
|**Slave SPI/I2C/I3C POR / REFRESH Timing**<br>~~eea~~|||||||
|tMSPI_INH<br>~~a~~<br>~~Ps~~|Time during POR, from VCC, VCCAUX, VCCIO0or<br>VCCIO1(whichever is the last) pass POR trip<br>voltage, or REFRESH command executed,  to<br>pull PROGRAMN LOW to prevent entering<br>MSPI mode<br>~~a~~|—<br>~~a~~|—<br>~~a~~|—<br>~~a~~|1<br>~~a~~|µs<br>~~a~~|
|tACT_PROGRAMN_H<br>~~Ps~~<br>~~a~~|Minimum time driving PROGRAMN HIGH after<br>last activation clock<br>~~ee~~|—<br>~~ee~~|50<br>~~ee~~|—<br>~~ee~~|—<br>~~ee~~|ns<br>~~ee~~|
|tCONFIG_CCLK<br>~~Ps~~<br>~~a~~<br>~~**a**~~|Minimum time to start driving CCLK (SSPI) after<br>PROGRAMN HIGH<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~|50<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~|—<br>~~ee~~|ns<br>~~ee~~|
|tCONFIG_SCL<br>~~a~~<br>~~**a**~~|Minimum time to start driving SCL (I2C/I3C)<br>after PROGRAMN HIGH<br>~~ee ~~<br>~~ee~~|—<br> ~~ee ~~<br>~~ee~~|50<br> ~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~|—<br>~~ee~~|ns<br>~~ee~~|
|**PROGRAMN Configuration Timing**<br>~~**a**~~<br>~~ee~~<br>~~ee ee~~|||||||
|tPROGRAMN<br>~~a~~|PROGRAMN LOW pulse accepted<br>~~a~~|—<br>~~a~~|50<br>~~a~~|—<br>~~a~~|—<br>~~a~~|ns<br>~~a~~|
|tPROGRAMN_RJ<br>~~a~~|PROGRAMN LOW pulse rejected<br>~~a~~|—<br>~~a~~|—<br>~~a~~|—<br>~~a~~|25<br>~~a~~|ns<br>~~a~~|
|tINIT_LOW<br>~~a~~<br>~~a~~|PROGRAMN LOW to INITN LOW<br>~~a~~<br>~~a~~|—<br>~~a~~<br>~~a~~|—<br>~~a~~<br>~~a~~|—<br>~~a~~<br>~~a~~|100<br>~~a~~<br>~~a~~|ns<br>~~a~~<br>~~a~~|
|tINIT_HIGH<br>~~a~~<br>~~a~~|PROGRAMN LOW to INITN HIGH<br>~~a~~<br>~~a~~|—<br>~~a~~<br>~~a~~|—<br>~~a~~<br>~~a~~|—<br>~~a~~<br>~~a~~|40<br>~~a~~<br>~~a~~|µs<br>~~a~~<br>~~a~~|
|tDONE_LOW<br>~~a~~|PROGRAMN LOW to DONE LOW<br>~~a~~|—<br>~~a~~|—<br>~~a~~|—<br>~~a~~|55<br>~~a~~|µs<br>~~a~~|
|tDONE_HIGH1<br>~~a~~<br>~~a~~|PROGRAMN HIGH to DONE HIGH<br>~~a~~<br>~~a~~|—<br>~~a~~<br>~~a~~|—<br>~~a~~<br>~~a~~|—<br>~~a~~<br>~~a~~|2<br>~~a~~<br>~~a~~|s<br>~~a~~<br>~~a~~|
|tIODISS<br>~~a~~|PROGRAMN LOW to I/O Disabled<br>~~a~~|—<br>~~a~~|—<br>~~a~~|—<br>~~a~~|125<br>~~a~~|ns<br>~~a~~|
|**Slave SPI**<br>~~a~~<br>~~a~~|||||||
|fCCLK_W<br>~~a~~<br>~~a~~|CCLK input clock frequency (For write<br>transaction)2<br>~~a~~|—<br>~~a~~|—<br>~~a~~<br>~~ee~~|—<br>~~a~~<br>~~ee~~|135<br>~~a~~|MHz<br>~~a~~|
|fCCLK_R<br>~~ee~~<br>~~a~~|CCLK input clock frequency (For read<br>transaction)3<br>~~ee~~|—<br>~~ee~~|—<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~|—4<br>~~ee~~|MHz<br>~~ee~~|
|tCCLKH<br>~~a~~|CCLK input clockpulse width HIGH|—|3.5<br>~~ee~~|—<br>~~ee~~|—|ns|
|tCCLKL<br>~~a~~<br>~~a~~<br>~~pf}~~|CCLK input clock pulse width LOW<br>~~pf}____|__|_|_|_}~~|—<br>~~____|__|_|_|_}~~|3.5<br>~~ee~~<br>~~____|__|_|_|_}~~|—<br>~~ee~~<br>~~____|__|_|_|_}~~|—<br>~~____|__|_|_|_}~~|ns<br>~~____|__|_|_|_}—~~|
|tVMC_SLAVE<br>~~pf}~~|Time from rising edge of INITN to Slave CCLK<br>driven<br>~~pf}____|__|_|_|_}~~|—<br>~~____|__|_|_|_}~~|50<br>~~____|__|_|_|_}~~|—<br>~~____|__|_|_|_}~~|—<br>~~____|__|_|_|_}~~|ns<br>~~____|__|_|_|_}—~~|
|tVMC_MASTER<br>~~pf}~~|CCLK input clock dutycycle<br>~~pf}____|__|_|_|_}~~|—<br>~~____|__|_|_|_}~~|40<br>~~____|__|_|_|_}~~|—<br>~~____|__|_|_|_}~~|60<br>~~____|__|_|_|_}~~|%<br>~~____|__|_|_|_}—~~|
|tSU_SSI<br>~~pf}~~<br>~~a~~|SSI to CCLK setup time<br>~~pf} ____|__|_|_|_}~~<br>~~a~~|—<br>~~____|__|_|_|_}~~<br>~~a~~|3.2<br>~~____|__|_|_|_}~~<br>~~a~~|—<br>~~____|__|_|_|_}~~<br>~~a~~|—<br>~~____|__|_|_|_}~~<br>~~a~~|ns<br>~~____|__|_|_|_} —~~<br>~~a~~|
|tHD_SSI<br>~~a~~|SSI to CCLK hold time<br>~~a~~|—<br>~~a~~|1.9<br>~~a~~|—<br>~~a~~|—<br>~~a~~|ns<br>~~a~~|
|tCO_SSO<br>~~a~~|CCLK fallingedge to valid SSO output<br>~~a~~|—<br>~~a~~|3.05<br>~~a~~|—<br>~~a~~|165<br>~~a~~|ns<br>~~a~~|
|tEN_SSO<br>~~a~~<br>~~a~~|CCLK falling edge to SSO output enabled<br>~~a~~<br>~~a~~|—<br>~~a~~<br>~~a~~|3.05<br>~~a~~<br>~~a~~|—<br>~~a~~<br>~~a~~|165<br>~~a~~<br>~~a~~|ns<br>~~a~~<br>~~a~~|
|tDIS_SSO<br>~~a~~|CCLK falling edge to SSO output disabled<br>~~a~~|—<br>~~a~~|3.05<br>~~a~~|—<br>~~a~~|165<br>~~a~~|ns<br>~~a~~|
|tHIGH_SCSN<br>~~a~~<br>~~a~~|SCSN HIGH time<br>~~a~~<br>~~a~~|—<br>~~a~~<br>~~a~~|74<br>~~a~~<br>~~a~~|—<br>~~a~~<br>~~a~~|—<br>~~a~~<br>~~a~~|ns<br>~~a~~<br>~~a~~|
|tSU_SCSN<br>~~a~~<br>~~a~~|SCSN to CCLK setuptime<br>~~a~~<br>~~a~~|—<br>~~a~~<br>~~a~~|3.5<br>~~a~~<br>~~a~~|—<br>~~a~~<br>~~a~~|—<br>~~a~~<br>~~a~~|ns<br>~~a~~<br>~~a~~|
|tHD_SCSN<br>~~a~~|SCSN to CCLK hold time<br>~~a~~|—<br>~~a~~|1.6<br>~~a~~|—<br>~~a~~|—<br>~~a~~|ns<br>~~a~~|
|**I2C/I3C**<br>~~a~~<br>~~a~~|||||||
|fSCL_I2C<br>~~a~~|SCL input clock frequency for I2C<br>~~a~~|—<br>~~a~~|—<br>~~a~~|—<br>~~a~~|1<br>~~a~~|MHz<br>~~a~~|
|fSCL_I3C<br>~~a~~<br>~~a~~|SCL input clock frequency for I3C<br>~~a~~<br>~~a~~|—<br>~~a~~<br>~~a~~|—<br>~~a~~<br>~~a~~|—<br>~~a~~<br>~~a~~|12<br>~~a~~<br>~~a~~|MHz<br>~~a~~<br>~~a~~|
|tSCLH_I2C<br>~~a~~<br>~~a~~|SCL input clock pulse width HIGH for I2C<br>~~a~~<br>~~a~~|—<br>~~a~~<br>~~a~~|400<br>~~a~~<br>~~a~~|—<br>~~a~~<br>~~a~~|—<br>~~a~~<br>~~a~~|ns<br>~~a~~<br>~~a~~|
|tSCLL_I2C<br>~~a~~|SCL input clock pulse width LOW for I2C<br>~~a~~<br>~~a~~|—<br>~~a~~<br>~~a~~|400<br>~~a~~<br>~~a~~|—<br>~~a~~<br>~~a~~|—<br>~~a~~<br>~~a~~|ns<br>~~a~~<br>~~a~~|
|tSU_SDA_I2C<br>~~a~~<br>~~a~~|SDA to SCL setup time for I2C<br>~~a~~<br>~~a~~|—<br>~~a~~<br>~~a~~|250<br>~~a~~<br>~~a~~|—<br>~~a~~<br>~~a~~|—<br>~~a~~<br>~~a~~|ns<br>~~a~~<br>~~a~~|
|tHD_SDA_I2C<br>~~a~~|SDA to SCL hold time for I2C|—|50|—|—|ns|



© 2021-2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

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**MachXO5-NX Family Data Sheet** 

|**Symbol**<br>~~PO~~<br>~~ee~~|**Parameter**<br><br>|**Device**<br><br>|**Min**<br><br>~~GG~~<br>|**Typ.**<br><br>~~GG~~<br>|**Max**<br><br>|**Unit**<br><br>|
|---|---|---|---|---|---|---|
|tSU_SDA_I3C<br>~~POeG~~<br>~~ee~~|SDA to SCL setup time for I3C<br>~~eG~~<br>|—<br>~~eG~~<br>|30<br>~~eG~~<br>~~GG~~<br>|—<br>~~eG~~<br>~~GG~~<br>|—<br>~~eG~~<br>|ns<br>~~eG~~<br>|
|tHD_SDA_I3C<br>~~ee~~<br>~~ee~~|SDA to SCL hold time for I3C<br>~~GG~~<br>|—<br>~~GG~~<br>|30<br>~~GG~~<br>~~GG~~<br>|—<br>~~GG~~<br>~~GG~~<br>|—<br>~~GG~~<br>|ns<br>~~GG~~<br>|
|tCO_SDA<br>~~ee~~<br>~~ee~~<br>~~ee~~|SCL falling edge to valid SDA output<br>~~GG~~<br>~~**GG**~~<br>|—<br>~~GG~~<br>~~**GG**~~<br>|—<br>~~GG~~<br>~~GG~~<br>~~**GG**~~<br>|—<br>~~GG~~<br>~~GG~~<br>~~**GG**~~<br>|200<br>~~GG~~<br>~~**GG**~~<br>|ns<br>~~GG~~<br>~~**GG**~~<br>|
|tEN_SDA<br><br>~~ee~~<br>~~ee~~|SCL falling edge to SDA output enabled<br>~~GG~~<br>~~**GG**~~<br>|—<br>~~GG~~<br>~~**GG**~~<br>|—<br>~~GG~~<br>~~**GG**~~<br>|—<br>~~GG~~<br>~~**GG**~~<br>|200<br>~~GG~~<br>~~**GG**~~<br>|ns<br>~~GG~~<br>~~**GG**~~<br>|
|tDIS_SDA<br><br>~~eeGG~~|SCL falling edge to SDA output disabled<br>~~**GG**~~<br>~~GG~~|—<br>~~**GG**~~<br>~~GG~~|—<br>~~**GG**~~<br>~~GG~~|—<br>~~**GG**~~<br>~~GG~~|200<br>~~**GG**~~<br>~~GG~~|ns<br>~~**GG**~~<br>~~GG~~|
|**Wake-Up Timing**<br>~~PR~~|||||||
|tDONE_HIGH<br>~~a~~|Last configuration clock cycle to DONE going<br>HIGH<br>~~ee~~|—|—|—|60|µs|
|tFIO_EN1<br>~~a~~|User I/O enabled in Fast I/O Mode<br>~~ee~~|—|—|31.104|—|M<br>cycles|
|tIOEN1<br>~~GG~~|Config clock to user I/O enabled<br>~~ee~~<br>~~GG~~|—<br>~~GG~~|130<br>~~GG~~|—<br>~~GG~~|—<br>~~GG~~|ns<br>~~GG~~|



**Notes** : 

1. Based on 30k uncompressed/unauthenticated/default MCLK timing (3.5 MHz)/×1. Other permutations result in different values. 

2. Supported input clock frequency for bursting in configuration bitstream to the device. 

3. Supported input clock frequency for reading out data transactions from the device. 

4. Refer to the following equations to determine the supported input clock frequency for read transaction. Assumption: The skew between CCLK and SSO on board is zero. 

**==> picture [129 x 9] intentionally omitted <==**

**==> picture [122 x 9] intentionally omitted <==**

CCLK – Input clock period. fCCLK_R = 1/CCLK. 

tCO (max) – Equivalent to tCO_SSO or tEN_SSO max value. 

Tsu – Setup time requirement for host controller I/O. 

For customer that can only use single clock for read/write operation, the Fmax is limited by the Fmax for read operation. For example: tCO (max) = 30 ns and Tsu = 2 ns. 

**==> picture [122 x 10] intentionally omitted <==**

**==> picture [104 x 9] intentionally omitted <==**

**==> picture [60 x 7] intentionally omitted <==**

**==> picture [118 x 20] intentionally omitted <==**

For the customer that wants to do the programming at 135 MHz or faster than Fmax for read operation: 

   - Have a mechanism in the host controller to switch between read clock and write clock for read/write transaction. For example, refer to SPI specification to switch between read and write clock by changing the SPI Baud Rate Register (SPIBR) if standard SPI controller is used as the host. 

   - Implementing a mechanism to adjust/calibrate the sampling clock edge when the valid data becomes available. 

5. Based on SLOW (default) slew rate control on Config output pins. 

© 2021-2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

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**MachXO5-NX Family Data Sheet** 

**==> picture [455 x 118] intentionally omitted <==**

**----- Start of picture text -----**<br>
tINIT_HIGH tPROGRAM_H MSPI<br>Configuration<br>PROGRAMN tPROGRAM_L SSPI/I2C/I3C<br>tIN ITL Configuration tINIT_HI GH Configuration<br>Error<br>INITN tINIT_HIGH Restart<br>Configuration<br>Configuration<br>DONE Started<br>tIN ITL = SRAM memory initialization period<br>**----- End of picture text -----**<br>


**Figure 3.14. Configuration Error Notification (1)** 

**==> picture [421 x 228] intentionally omitted <==**

**----- Start of picture text -----**<br>
REFRESH<br>Command<br>VCC/VCCAUX/<br>VCCIO0/VCCIO1<br>INITN<br>DONE<br>tMSPI_INH Slave Activation tACT_PROGRAMN_H<br>PROGRAMN<br>fCCLK tCONFIG_CCLK<br>CCLK<br>SSI<br>fSCL tACT_PROGRAMN_H<br>tCONFIG_SCL<br>SCL<br>eee ene YAY AN AV A UAY ee ___ RI<br>SDA<br>**----- End of picture text -----**<br>


**Figure 3.15. Slave SPI/I[2] C/I3C POR/REFRESH Timing** 

© 2021-2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

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**MachXO5-NX Family Data Sheet** 

**==> picture [443 x 569] intentionally omitted <==**

**----- Start of picture text -----**<br>
tPROGRAMN<br>PROGRAMN<br>tINIT_HIGH<br>tINIT_LOW<br>INITN<br>——<br>DONE tDONE_LOW tACT_PROGRAMN_H<br>fCCLK tCONFIG_CCLK<br>CCLK<br>SSI<br>fSCL tACT_PROGRAMN_H<br>SCL tCONFIG_SCL<br>=i<br>SDA<br>Slave Activation<br>tIODISS<br>USER I/O<br>| )<br>Figure 3.16. Slave SPI/I [2] C/I3C PROGRAMN Timing<br>fCCLK<br>tCCLKH<br>CCLK<br>tCCLKL<br>tSU_SSI tHD_SSI<br>SSI<br>=<br>tSU_SCSN tHD_SCSN<br>SCSN<br>py<br>tHIGH_SCS N<br>tCO_SSO<br>SSO<br>a<br>tEN_SSO tDIS_SSO<br>SSO<br>Ne ee ae<br>**----- End of picture text -----**<br>


**Figure 3.17. Slave SPI Configuration Timing** 

© 2021-2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

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**==> picture [464 x 581] intentionally omitted <==**

**----- Start of picture text -----**<br>
MachXO5-NX Family<br>Data Sheet<br>fSCL<br>tSCLH<br>SCL<br>tSCLL<br>tSU_SDA tHD_SDA<br>SDA (input)<br>tCO_SDA<br>SDA (output)<br>tDIS_SDA<br>tEN_SDA<br>SDA (output)<br>=a<br>Figure 3.18. I [2] C /I3C Configuration Timing<br>CRESET_B<br>INITN<br>tDONE_HIGH Device Wake-Up<br>DONE<br>CONFIG<br>Starts<br>CCLK/SCL<br>tFIO_EN<br>tIOEN<br>USER I/O<br>(FAST I/O)<br>tIOEN<br>=<br>USER I/O<br>Ee<br>Figure 3.19. Slave SPI/I [2] C/I3C Wake-Up Timing<br>**----- End of picture text -----**<br>


© 2021-2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

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**MachXO5-NX Family Data Sheet** 

## **3.29. JTAG Port Timing Specifications** 

Over recommended operating conditions. 

## **Table 3.45. JTAG Port Timing Specifications** 

|**Symbol**|**Parameter**|**Min**|**Typ. **|**Max**|**Units**|
|---|---|---|---|---|---|
|fMAX|TCK clock frequency|—|—|25|MHz|
|tBTCPH|TCK clockpulse width high|20|—|—|ns|
|tBTCPL|TCK clockpulse width low|20|—|—|ns|
|tBTS|TCK TAP setuptime|5|—|—|ns|
|tBTH|TCK TAP hold time|5|—|—|ns|
|tBTRF|TAP controller TDO rise/fall time1|1000|—|—|mV/ns|
|tBTCO|TAP controller fallingedge of clock to valid output|—|—|14|ns|
|tBTCODIS|TAP controller fallingedge of clock to valid disable|—|—|14|ns|
|tBTCOEN|TAP controller fallingedge of clock to valid enable|—|—|14|ns|
|tBTCRS|BSCAN test capture register setuptime|8|—|—|ns|
|tBTCRH|BSCAN test capture register hold time|25|—|—|ns|
|tBUTCO|BSCAN test update register, fallingedge of clock to valid output|—|—|25|ns|
|tBTUODIS|BSCAN test update register, fallingedge of clock to valid disable|—|—|25|ns|
|tBTUPOEN|BSCAN test update register, fallingedge of clock to valid enable|—|—|25|ns|



**Note:** 

1. Based on default I/O setting of slow slew rate. 

**==> picture [426 x 313] intentionally omitted <==**

**----- Start of picture text -----**<br>
TMS<br>TDI<br>tBTS tBTH<br>tBTCPH tBTCPL tBTCP<br>TCK<br>tBTCOEN tBTCO tBTCODIS<br>TDO V  dilaD aat V  dilaD aat<br>tBTCRH<br>tBTCRS<br>Data to be<br>Captured Data Captured<br>from I/O<br>tBTUPOEN tBUTCO tBTUODIS<br>Data to be<br>driven out V  dilaD aat V  dilaD aat<br>to I/O<br>**----- End of picture text -----**<br>


**Figure 3.20. JTAG Port Timing Waveforms** 

© 2021-2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

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**MachXO5-NX Family Data Sheet** 

## **3.30. Switching Test Conditions** 

Figure 3.21 shows the output test load that is used for AC testing. The specific values for resistance, capacitance, voltage, and other test conditions are listed in Table 3.46. 

**==> picture [203 x 138] intentionally omitted <==**

**----- Start of picture text -----**<br>
V T<br>R1<br>DUT Test Point<br>R2 CL*<br>: L<br>**----- End of picture text -----**<br>


*CL Includes Test Fixture and Probe Capacitance 

**Figure 3.21. Output Test Load, LVTTL and LVCMOS Standards** 

**Table 3.46. Test Fixture Required Components, Non-Terminated Interfaces** 

|**Test Condition**|**R1**|**R2**|**CL**|**Timing Ref.**|**VT**|
|---|---|---|---|---|---|
|LVTTL and other LVCMOS settings (L ≥ H, H ≥ L)|||0 pF|LVCMOS 3.3 = 1.5 V|—|
|||||LVCMOS 2.5 = VCCIO/2|—|
|||||LVCMOS 1.8 = VCCIO/2|—|
|||||LVCMOS 1.5 = VCCIO/2|—|
|||||LVCMOS 1.2 = VCCIO/2|—|
|LVCMOS 2.5 I/O(Z ≥ H)||1 MΩ|0pF|VCCIO/2|—|
|LVCMOS 2.5 I/O(Z ≥ L)|1 MΩ||0pF|VCCIO/2|VCCIO|
|LVCMOS 2.5 I/O(H ≥ Z)||100|0pF|VOH– 0.10|—|
|LVCMOS 2.5 I/O(L ≥ Z)|100||0pF|VOL+ 0.10|VCCIO|



**Note** : Output test conditions for all other interfaces are determined by the respective standards. 

© 2021-2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

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**MachXO5-NX Family Data Sheet** 

## **4. DC and Switching Characteristics for LFMXO5-55T/100T Commercial and Industrial** 

All specifications in this section are characterized within recommended operating conditions unless otherwise specified. 

## **4.1. Absolute Maximum Ratings** 

**Table 4.1. Absolute Maximum Ratings** 

|**Symbol**<br>~~a~~|**Parameter**<br>~~a~~|**Min**<br>~~a ~~|**Max**<br> ~~a~~|**Unit**|
|---|---|---|---|---|
|VCC, VCCECLK<br>~~a~~|SupplyVoltage<br>|–0.5<br>~~ee~~<br>|1.10<br>~~eee~~<br>|V<br>~~eee~~<br>|
|VCCAUX, VCCAUXA,<br>VCCAUXH3,VCCAUXH4,<br>VCCAUXH5<br>~~ee~~<br>~~a~~|Supply Voltage<br>~~ee~~<br>|–0.5<br>~~ee~~<br>~~ee~~<br>|1.98<br>~~ee~~<br>~~eee~~<br>|V<br>~~ee~~<br>~~eee~~<br>|
|VCCIO0, 1, 2,  6, 7<br>~~a a~~|I/O SupplyVoltage<br>~~a~~|–0.5<br>~~ee ~~<br>~~a~~|3.63<br> ~~eee~~<br>~~a~~|V<br>~~eee~~<br>~~a~~|
|VCCIO3, 4, 5<br>~~a~~|I/O SupplyVoltage<br>~~a~~|–0.5<br>~~a~~|1.98<br>~~a~~|V<br>~~a~~|
|VCCPLLSD*<br>~~a~~<br>~~a~~|SERDES Block PLL SupplyVoltage<br>~~a~~<br>~~a~~|–0.5<br>~~a~~<br>~~a~~|1.98<br>~~a~~<br>~~a~~|V<br>~~a~~<br>~~a~~|
|VCCSD*<br>~~a~~<br>~~a~~|SERDES SupplyVoltage<br>~~a~~<br>~~a~~|–0.5<br>~~a~~<br>~~a~~|1.10<br>~~a~~<br>~~a~~|V<br>~~a~~<br>~~a~~|
|VCCSDCK<br>~~a~~<br>~~a~~|SERDES Clock Buffer SupplyVoltage<br>~~a~~<br>~~a~~<br>~~a~~|–0.5<br>~~a~~<br>~~a~~|1.10<br>~~a~~<br>~~a~~|V<br>~~a~~<br>~~a~~|
|VCCADC18<br>~~a~~|ADC Block 1.8 V SupplyVoltage<br>~~a~~<br>~~a~~|–0.5<br>~~a~~<br>~~a~~|1.98<br>~~a~~<br>~~a~~|V<br>~~a~~<br>~~a~~|
|VCCAUXSDQ*<br>~~a~~<br>~~a~~|SERDES AUX SupplyVoltage<br>~~a~~|–0.5<br>~~a~~|1.98<br>~~a~~<br>~~ee~~|V<br>~~a~~|
|—<br>~~a~~<br>~~a~~<br>~~a~~|Input or I/O Voltage Applied, Bank 0, Bank 1,<br>Bank 2, Bank 6, Bank 7<br>~~a~~<br>~~a~~<br>~~ee~~<br>~~ee~~|–0.5<br>~~a~~<br>~~a~~<br>~~ee~~<br>~~ee~~|3.63<br>~~a~~<br>~~a~~<br>~~ee~~<br>~~ee~~|V<br>~~a~~<br>~~a~~<br>~~ee~~|
|—<br>~~a~~<br>~~a~~|Input or I/O Voltage Applied, Bank 3, Bank 4,<br>Bank 5<br>~~a~~<br>~~ee~~<br>~~ee~~|–0.5<br>~~a~~<br>~~ee~~<br>~~ee~~|1.98<br>~~a~~<br>~~ee~~<br>~~ee~~|V<br>~~a~~<br>~~ee~~|
|TA<br>~~a~~|Storage Temperature(Ambient)<br>~~ee ~~<br>~~a~~|–65<br> ~~ee~~<br>~~a~~|150<br>~~a~~|°C<br>~~a~~|
|TJ<br>~~a~~<br>~~a~~|Junction Temperature<br>~~a~~<br>~~a~~|—<br>~~a~~<br>~~a~~|+125<br>~~a~~<br>~~a~~|°C<br>~~a~~<br>~~a~~|



**Notes** : 

- Stress above those listed under the _Absolute Maximum Ratings_ may cause permanent damage to the device. Functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. 

- Compliance with the Lattice Thermal Management document is required. 

- All voltages referenced to GND. 

- All VCCAUX should be connected on PCB. 

## **4.2. Recommended Operating Conditions[1, 2, 3]** 

**Table 4.2. Recommended Operating Conditions** 

|**Symbol**|**Parameter**|**Conditions**|**Min**|**Typ. **|**Max**|**Unit**|
|---|---|---|---|---|---|---|
|VCC,VCCECLK|Core SupplyVoltage|VCC= 1.0|0.95|1.00|1.05|V|
|VCCAUX|Auxiliary Supply Voltage|Bank 0, Bank 1, Bank 2, Bank 6,<br>Bank 7|1.71|1.80|1.89|V|
|VCCAUXH3/4/5|AuxiliarySupplyVoltage|Bank 3, Bank 4, Bank 5|1.71|1.80|1.89|V|
|VCCAUXA|Auxiliary Supply Voltage for<br>core logic|—|1.71|1.80|1.89|V|



© 2021-2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02102-1.7 

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**MachXO5-NX Family Data Sheet** 

|**Symbol**<br>~~a ~~|**Parameter**<br> ~~GG~~|**Conditions**<br>~~GG~~<br>~~es~~|**Min**<br>~~GG~~<br>~~ee~~<br>|**Typ. **<br>~~GG~~<br>~~ee~~<br>|**Max**<br>~~GG~~<br>~~ee~~<br>|**Unit**<br>~~GG~~<br>~~ee~~<br>|
|---|---|---|---|---|---|---|
|VCCIO|I/O Driver Supply Voltage|VCCIO= 3.3 V, Bank 0, Bank 1,<br>Bank 2, Bank 6, Bank 7<br>~~a~~<br>~~es ee~~<br>~~es~~|3.135<br>~~a~~<br>~~ee~~<br>~~ee~~<br>|3.30<br>~~a~~<br>~~ee~~<br>~~ee~~<br>|3.465<br>~~a~~<br>~~ee~~<br>~~ee~~<br>|V<br>~~a~~<br>~~ee~~<br>~~ee~~<br>|
|||VCCIO= 2.5 V, Bank 1, Bank 2,<br>Bank 6, Bank 7<br>~~es ee~~<br>~~es ee~~<br>~~es~~|2.375<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>|2.50<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>|2.625<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>|V<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>|
|||VCCIO= 1.8 V, All Banks except<br>Bank 0<br>~~es ee~~<br>~~es ee~~<br>~~es ee~~<br>~~es~~|1.71<br>~~ee ~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>|1.80<br> ~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>|1.89<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>|V<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>|
|||VCCIO= 1.5 V, All Banks except<br>Bank 04<br>~~ee~~<br>~~es ee~~<br>~~es ee~~<br>~~es~~<br>~~es~~|1.425<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~**ee**~~|1.50<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~**ee**~~|1.575<br>~~ee ~~<br>~~ee~~<br>~~ee~~<br>~~**ee**~~|V<br> ~~ee~~<br>~~ee~~<br>~~ee~~<br>~~**ee**~~|
|||VCCIO= 1.35 V, All Banks except<br>Bank 04 (For DDR3L Only)<br>~~ee~~<br>~~es ee~~<br>~~es~~<br>~~es~~|1.2825<br>~~ee~~<br>~~ee~~<br>~~**ee**~~|1.35<br>~~ee~~<br>~~ee~~<br>~~**ee**~~|1.4175<br>~~ee ~~<br>~~ee~~<br>~~**ee**~~|V<br> ~~ee~~<br>~~ee~~<br>~~**ee**~~|
|||VCCIO= 1.2 V, All Banks except<br>Bank 04<br>~~ee~~<br>~~es ~~<br>~~es~~|1.14<br>~~ee~~<br> ~~**ee**~~<br>~~ee~~|1.20<br>~~ee~~<br>~~**ee**~~<br>~~ee~~|1.26<br>~~ee ~~<br>~~**ee**~~<br>~~ee~~|V<br> ~~ee~~<br>~~**ee**~~<br>~~ee~~|
|||VCCIO= 1.0 V, Bank 3, Bank 4,<br>Bank 5<br> <br>~~es~~<br>~~a~~|0.95<br> ~~**ee**~~<br>~~a~~<br>~~ee~~|1.00<br>~~**ee**~~<br>~~a~~<br>~~ee~~|1.05<br>~~**ee** ~~<br>~~a~~<br>~~ee~~|V<br> ~~**ee**~~<br>~~a~~<br>~~ee~~|
|**ADC External Power Supplies**<br>~~ee ee ee~~|||||||
|VCCADC18<br>~~ee~~|ADC 1.8 V Power Supply<br>~~ee~~|—<br>~~ee~~|1.71<br>~~ee~~|1.80<br>~~ee~~|1.89<br>~~ee~~|V<br>~~ee~~|
|**SERDES Block External Power Supplies**<br>~~ee~~|||||||
|VCCSD*<br>~~a~~|Supply Voltage for SERDES<br>Block and SerDes I/O|—|0.95|1.00|1.05|V|
|VCCSDCK<br>~~a~~<br>~~a~~|Supply Voltage for SERDES<br>Clock Buffer|—|0.95|1.00|1.05|V|
|VCCPLLSD*<br>~~a~~<br>~~a~~|SERDES Block PLL Supply<br>Voltage|—|1.71|1.80|1.89|V|
|VCCAUXSDQ*<br>~~a~~<br>~~a~~|SERDES Block Auxiliary<br>SupplyVoltage<br>~~a~~|—|1.71|1.80|1.89|V|
|**Operating Temperature**<br>~~a~~<br>~~a~~|||||||
|tJCOM<br>~~a~~|Junction Temperature,<br>Commercial Operation|—|0|—|85|°C|
|tJIND<br>~~a~~<br>~~a~~|Junction Temperature,<br>Industrial Operation|—|–40|—|100|°C|



**Notes** : 

1. For correct operation, all supplies must be held in their valid operation voltage range. 

2. All supplies with same voltage should be from the same voltage source. Proper isolation filters are needed to properly isolate noise from each other. 

3. Common supply rails must be tied together. 

4. JTAG, SSPI, I[2] C, and I3C (Bank 2) ports are supported for VCCIO = 1.8 V to 3.3 V. 

## **4.3. Power Supply Ramp Rates** 

**Table 4.3. Power Supply Ramp Rates** 

|**Table 4.3. Power Supply Ramp Ratespply Ramp Ratesly Ramp Ratesy Ramp Rates Ramp Ratesp Rates Rates**|**Table 4.3. Power Supply Ramp Ratespply Ramp Ratesly Ramp Ratesy Ramp Rates Ramp Ratesp Rates Rates**|**Table 4.3. Power Supply Ramp Ratespply Ramp Ratesly Ramp Ratesy Ramp Rates Ramp Ratesp Rates Rates**|**Table 4.3. Power Supply Ramp Ratespply Ramp Ratesly Ramp Ratesy Ramp Rates Ramp Ratesp Rates Rates**|**Table 4.3. Power Supply Ramp Ratespply Ramp Ratesly Ramp Ratesy Ramp Rates Ramp Ratesp Rates Rates**|**Table 4.3. Power Supply Ramp Ratespply Ramp Ratesly Ramp Ratesy Ramp Rates Ramp Ratesp Rates Rates**|
|---|---|---|---|---|---|
|**Symbol**<br>**Parameter**<br>**Min**<br>**Typ**<br>**Max**<br>**Unit**<br>tRAMP<br>Power Supplyramprates for all supplies1<br>0.1<br>—<br>50<br>V/ms<br>~~Se~~||||||
|**Notes**:||||||
|1.<br>Assumes monotonic ramp rates.||||||



2. All supplies need to be in the operating range as defined in Recommended Operating Conditions when the device has completed configuration and entering into User Mode. Supplies that are not in the operating range needs to be adjusted to faster ramp rate, or you have to delay configuration or wake up. 

## **4.4. Power up Sequence** 

Power-On-Reset (POR) puts the MachXO5-NX device into a reset state. There is no power up sequence required for the MachXO5-NX device. 

© 2021-2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02102-1.7 

105 

**MachXO5-NX Family Data Sheet** 

**Table 4.4. Power-On Reset** 

|**Symbol**|**Parameter**|**Parameter**|**Min**|**Typ**|**Max**|**Unit**|
|---|---|---|---|---|---|---|
|VPORUP|Power-On-Reset ramp-up trip<br>point (Monitoring VCC, VCCAUX,<br>VCCI00, and VCCI01)|VCC|0.73|—|0.83|V|
|||VCCAUX|1.34|—|1.62|V|
|||VCCIO0,VCCI01|0.89|—|1.05|V|
|VPORDN|Power-On-Reset ramp-up trip<br>point (Monitoring VCCand VCCAUX)|VCC|0.51|—|0.81|V|
|||VCCAUX|1.38|—|1.59|V|



## **4.5. On-Chip Programmab** l **e Termination** 

The MachXO5-NX devices support a variety of programmable on-chip terminations options, including: 

- Dynamically switchable Single-Ended Termination with programmable resistor values of 40 Ω, 50 Ω, 60 Ω, or 75 Ω. 

- Common mode termination of 100 Ω for differential inputs. 

**==> picture [473 x 144] intentionally omitted <==**

**----- Start of picture text -----**<br>
V CCIO Zo = 50<br>TERM<br>Zo = 40  , 50  , 60  , or 75<br>control<br>to VCCIO  /2<br>Zo<br>| Zo +<br>Zo + 2Zo -<br>- Zo<br>VREF<br>GS Sip<br>OFF-chip ON-chip OFF-chip ON-chip<br>Parallel Single-Ended Input Differential Input<br>**----- End of picture text -----**<br>


**Figure 4.1. On-Chip Termination** 

See Table 4.5 for termination options for input modes. 

**Table 4.5. On-Chip Termination Options for Input Modes** 

|**IO_TYPE**<br>~~I~~<br>~~ee~~|**Differential Termination Resistor1, 2**|**Terminate to VCCIO/21, 2**|
|---|---|---|
|subLVDS<br>~~I~~<br>~~ee~~|100, OFF|OFF|
|SLVS<br>~~ee~~<br>~~I~~|100, OFF<br>~~I~~|OFF|
|MIPI_DPHY<br>~~a~~|100|OFF|
|HSTL15D_I<br>~~a~~<br>~~a~~|100, OFF|OFF|
|SSTL15D_I<br>~~a~~<br>~~a~~<br>~~a~~|100, OFF|OFF|
|SSTL135D_I<br>~~a~~<br>~~a~~|100, OFF|OFF|
|HSUL12D<br>~~a~~<br>~~I~~<br>~~a~~|100, OFF|OFF|
|LVCMOS15H<br>~~a~~|OFF|OFF|
|LVCMOS12H<br>~~a~~<br>~~a~~|OFF|OFF|
|LVCMOS10H<br>~~a~~<br>~~a~~<br>~~a~~|OFF<br>|OFF<br>|
|LVCMOS12H<br>~~a~~<br>~~a~~|OFF<br>|OFF<br>|
|LVCMOS10H<br>~~aee~~<br>~~es~~|OFF<br>~~ee~~|OFF<br>~~ee~~|
|LVCMOS18H<br>~~es~~|OFF|OFF, 40, 50, 60, 75|
|HSTL15_I<br>~~es~~<br>~~a~~|OFF|50|
|SSTL15_I<br>~~a~~<br>~~a~~<br>~~ee~~|OFF|OFF, 40, 50, 60, 75|
|SSTL135_I<br>~~a~~<br>~~ee~~|OFF|OFF, 40, 50, 60, 75|



© 2021-2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02102-1.7 

106 

**MachXO5-NX Family Data Sheet** 

|**IO_TYPE**|**Differential Termination Resistor1, 2**|**Terminate to VCCIO/21, 2**|
|---|---|---|
|HSUL12|OFF|OFF, 40, 50, 60, 75|
|LVSTL_I|OFF|OFF, 40, 48, 60, 80, 120|
|LVSTL_II|OFF|OFF, 80, 120|



**Notes** : 

1. Single-ended Terminate Resistor (to ground for LPDDR4, to VCCIO/2 for all other non-LPDDR4) and Differential Resistor when turned on can only have one setting per bank. Only bottom banks have this feature. 

2. Use of Single-ended Terminate Resistor (to ground for LPDDR4, to VCCIO/2 for all other non-LPDDR4) and Differential Termination Resistor are mutually exclusive in an I/O bank. 

3. Tolerance for single-ended termination resistor is -10/60%, while for differential termination resistor is -15/15%. 

Refer to sysI/O User Guide for Nexus Platform (FPGA-TN-02067) for on-chip termination usage and value ranges. 

## **4.6. Hot Socketing Specifications** 

**Table 4.6. Hot Socketing Specifications for GPIO** 

**Symbol Parameter Condition Min Typ Max Unit** 0 < VIN < VIH(max) Input or I/O Leakage Current for 0 < VCC < VCC(max) IDK Wide Range I/O (excluding –1.5 — 1.5 mA 0 < VCCIO < VCCIO(max) INITN/DONE) ~~TET~~ 0 < VCCAUX < VCCAUX(max) **Notes** : ~~pf~~ • IDK is additive to IPU, IPD, or IBH. ~~|~~ • Hot socket specification defines when the hot socketed device's junction temperature is at 85[o] C or below. When the hot socketed device's junction temperature is above 85[o] C, the IDK current can exceed the above spec. 

- Going beyond the hot socketing ranges specified here will cause exponentially higher Leakage currents and potential reliability issues. A total of 64mA per 8 I/O should not be exceeded. 

## **4.7. Programming/Erase Specifications** 

**Table 4.7. Programming/Erase Specifications** 

|**Symbol**|**Parameter**|**Min**|**Max.**|**Units**|
|---|---|---|---|---|
|NPROGCYC|Flash Programmingcyclesper tRETENTION|—|10,000|Cycles|
||Flash Write/Erase cycles|—|100,000||
|tRETENTION|Data retention at 100°Cjunction temperature|20|—|Years|
||Data retention at 85°Cjunction temperature|>20|—||



**Note** : 

A Write/Erase cycle is defined as any number of writes over time followed by one erase cycle. 

## **4.8. ESD Performance** 

Refer to the MachXO5-NX Product Family Qualification Summary for complete qualification data, including ESD performance. 

© 2021-2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02102-1.7 

107 

**MachXO5-NX Family Data Sheet** 

## **4.9. DC Electrical Characteristics** 

**Table 4.8. DC Electrical Characteristics – Wide Range (Over Recommended Operating Conditions)** 

|**Symbol**<br>~~pO~~|**Parameter**|**Condition**|**Min**<br>~~ee~~|**Typ**<br>~~ee~~|**Max**|**Unit**|
|---|---|---|---|---|---|---|
|IIL, IIH1<br>~~pO~~<br>~~aee~~|Input or I/O Leakage current<br>(Commercial/Industrial)<br>~~ee~~|0 ≤ VIN≤ VCCIO<br>~~ee~~|—<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~|10<br>~~ee~~|µA<br>~~ee~~|
|IIH2<br>~~GGG~~<br>~~a~~|Input or I/O Leakage current<br>~~GGG~~<br>|VCCIO≤ VIN≤ VIH (max)<br>~~GGG~~<br>|—<br>~~ee ~~<br>~~GGG~~<br>~~ee ee~~<br>|—<br> ~~ee~~<br>~~GGG~~<br>~~ee~~<br>|100<br>~~GGG~~<br>~~ee~~<br>|µA<br>~~GGG~~<br>~~ee~~<br>|
|IPU<br>~~aee~~<br>~~a~~<br>~~a~~|I/O Weak Pull-up Resistor<br>Current<br>~~ee~~<br><br>|0 ≤ VIN≤ 0.7 × VCCIO<br>~~ee~~<br><br>|–30<br>~~ee~~<br>~~ee ee~~<br><br>~~ee ee~~<br>|—<br>~~ee~~<br>~~ee~~<br><br>~~ee~~<br>|–150<br>~~ee~~<br>~~ee~~<br><br>~~ee~~<br>|µA<br>~~ee~~<br>~~ee~~<br><br>~~ee~~<br>|
|IPD<br>~~aee~~<br>~~a~~|I/O Weak Pull-down Resistor<br>Current<br>~~ee~~<br>|VIL(max) ≤ VIN≤ VCCIO<br>~~ee~~<br>|30<br>~~ee ee~~<br>~~ee~~<br>~~ee ee~~<br>|—<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>|150<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>|µA<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>|
|IBHLS<br>~~aGG~~|Bus Hold Low SustainingCurrent<br>~~GG~~|VIN= VIL (max)<br>~~GG~~|30<br>~~ee ee~~<br>~~GG~~|—<br>~~ee~~<br>~~GG~~|—<br>~~ee~~<br>~~GG~~|µA<br>~~ee~~<br>~~GG~~|
|IBHHS<br>~~aGG~~|Bus Hold High SustainingCurrent<br>~~GG~~|VIN= 0.7 × VCCIO<br>~~GG~~|–30<br>~~GG~~|—<br>~~GG~~|—<br>~~GG~~|µA<br>~~GG~~|
|IBHLO<br>~~aGG~~|Bus hold low Overdrive Current<br>~~GG~~|0 ≤ VIN≤ VCCIO<br>~~GG~~|—<br>~~GG~~|—<br>~~GG~~|150<br>~~GG~~|µA<br>~~GG~~|
|IBHHO<br>~~GO~~|Bus hold high Overdrive Current<br>~~GO~~|0 ≤ VIN≤ VCCIO<br>~~GO~~|—<br>~~GO~~|—<br>~~GO~~|–150<br>~~GO~~|µA<br>~~GO~~|
|VBHT<br>~~GO~~<br>~~GD~~|Bus Hold TripPoints<br>~~GO~~<br>~~GD~~|—<br>~~GO~~<br>~~GD~~|VIL(max)<br>~~GO~~<br>~~GD~~|—<br>~~GO~~<br>~~GD~~|VIH(min)<br>~~GO~~<br>~~GD~~|V<br>~~GO~~<br>~~GD~~|



## **Notes** : 

1. Input or I/O leakage current is measured with the pin configured as an input or as an I/O with the output tri-stated. Bus Maintenance circuits are disabled. 

2. The input leakage current IIH is the worst case input leakage per GPIO when the pad signal is high and also higher than the bank VCCIO. This is considered a mixed mode input. 

**Table 4.9. DC Electrical Characteristics – High Speed (Over Recommended Operating Conditions)** 

|**Symbol**<br>~~pO~~|**Parameter**|**Condition**|**Min**|**Typ**|**Max**|**Unit**|
|---|---|---|---|---|---|---|
|IIL, IIH1<br>~~pO~~<br>~~a~~|Input or I/O Leakage<br>|0 ≤ VIN≤ VCCIO<br>|—<br>|—<br>|10<br>|µA<br>|
|IPU<br>~~aee~~|I/O Weak Pull-up Resistor<br>Current<br>~~ee~~|0 ≤ VIN≤ 0.7 × VCCIO<br>~~ee~~|–30<br>~~ee~~|—<br>~~ee~~|–150<br>~~ee~~|µA<br>~~ee~~|
|IPD<br>~~ee~~<br>~~ee~~|I/O Weak Pull-down Resistor<br>Current<br>~~ee~~<br>~~ee~~|VIL(max) ≤ VIN≤ VCCIO<br>~~ee~~<br>~~ee~~|30<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~|150<br>~~ee~~<br>~~ee~~|µA<br>~~ee~~<br>~~ee~~|
|IBHLS<br>~~ee~~<br>~~a OO~~|Bus Hold Low SustainingCurrent<br>~~ee~~<br>~~OO~~|VIN= VIL (max)<br>~~ee~~<br>~~OO~~|30<br>~~ee~~<br>~~OO~~|—<br>~~ee~~<br>~~OO~~|—<br>~~ee~~<br>~~OO~~|µA<br>~~ee~~<br>~~OO~~|
|IBHHS<br>~~a OO~~<br>~~a GG~~|Bus Hold High SustainingCurrent<br>~~OO~~<br>~~GG~~|VIN= 0.7 × VCCIO<br>~~OO~~<br>~~GG~~|–30<br>~~OO~~<br>~~GG~~|—<br>~~OO~~<br>~~GG~~|—<br>~~OO~~<br>~~GG~~|µA<br>~~OO~~<br>~~GG~~|
|IBHLO<br>~~a GG~~<br>~~a~~|Bus hold low Overdrive Current<br>~~GG~~<br>~~GGG~~|0 ≤ VIN≤ VCCIO<br>~~GG~~<br>~~GGG~~|—<br>~~GG~~<br>~~GGG~~|—<br>~~GG~~<br>~~GGG~~|150<br>~~GG~~<br>~~GGG~~|µA<br>~~GG~~<br>~~GGG~~|
|IBHHO<br>~~a~~|Bus hold high Overdrive Current<br>~~GG~~|0 ≤ VIN≤ VCCIO<br>~~GG~~|—<br>~~GG~~|—<br>~~GG~~|–150<br>~~GG~~|µA<br>~~GG~~|
|VBHT<br>~~a~~|Bus Hold Trip Points|—|VIL<br>(max)|—|VIH(min)|V|



## **Note:** 

1. Input or I/O leakage current is measured with the pin configured as an input or as an I/O with the output tri-stated. Bus Maintenance circuits are disabled. 

**Table 4.10. Capacitors – Wide Range (Over Recommended Operating Conditions)** 

|**Symbol**|**Parameter**|**Condition**|**Min**|**Typ**|**Max**|**Unit**|
|---|---|---|---|---|---|---|
|C11|I/O Capacitance|VCCIO = 3.3 V, 2.5 V, 1.8 V, 1.5 V, 1.2 V,<br>VCC = typ., VIO = 0 to VCCIO+ 0.2 V|—|6|—|pf|
|C21|Dedicated Input Capacitance|VCCIO = 3.3 V, 2.5 V, 1.8 V, 1.5 V, 1.2 V,<br>VCC = typ., VIO = 0 to VCCIO+ 0.2 V|—|6|—|pf|



**Note** : 

1. TA 25[o] C, f = 1.0 MHz. 

© 2021-2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02102-1.7 

108 

**MachXO5-NX Family Data Sheet** 

**Table 4.11. Capacitors – High Performance (Over Recommended Operating Conditions)** 

|**Symbol**|**Parameter**|**Condition**|**Min**|**Typ**|**Max**|**Unit**|
|---|---|---|---|---|---|---|
|C11|I/O Capacitance|VCCIO = 1.8 V, 1.5 V, 1.2 V, VCC = typ.,<br>VIO = 0 to VCCIO+ 0.2 V|—|6|—|pf|
|C21|Dedicated Input Capacitance|VCCIO = 1.8 V, 1.5 V, 1.2 V, VCC = typ.,<br>VIO = 0 to VCCIO+ 0.2 V|—|6|—|pf|
|C31|SERDES I/O Capacitance|VCCSD* = 1.0 V, VCC = typ., VIO = 0 to<br>VCCSD * + 0.2 V|—|5|—|pf|



**Note:** 

|1.<br>TA25oC, f = 1.0 MHz.|
|---|
|**Table 4.12. Single Ended Input Hysteresis – Wide Range (Over Recommended Operating Conditions)**<br>**IO_TYPE**<br>**VCCIO**<br>**TYP Hysteresis**<br>LVCMOS33<br>3.3 V<br>250 mV<br>LVCMOS25<br>3.3 V<br>200 mV<br>2.5 V<br>250 mV<br>LVCMOS18<br>1.8 V<br>180 mV<br>LVCMOS15<br>1.5 V<br>50 mV<br>LVCMOS12<br>1.2 V<br>0<br>LVCMOS10<br>1.2 V<br>0<br>**Table 4.13. Single Ended Input Hysteresis – High Performance(Over Recommended Operating Conditions)**<br>**IO_TYPE**<br>**VCCIO**<br>**TYP Hysteresis**<br>LVCMOS18H<br>1.8 V<br>180 mV<br>LVCMOS15H<br>1.8 V<br>50 mV<br>1.5 V<br>150 mV<br>LVCMOS12H<br>1.2 V<br>0<br>LVCMOS10H<br>1.0 V<br>0<br>MIPI-LP-RX<br>1.2 V<br>>25 mV<br>**4.10. Supply Currents**<br>For estimating and calculating current, use Power Calculator in Lattice Design Software.<br>This operating and peak current is design dependent, and can be calculated in Lattice Design Software. Some<br>blocks can be placed into low current standby modes. Refer toPower Management and Calculation for<br>Certus-NX, CertusPro-NX, and MachXO5-NX Devices (FPGA-TN-02257).<br> ~~=~~<br>~~—~~|
|© 2021-2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed atwww.latticesemi.com/legal.|
|All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.|



This operating and peak current is design dependent, and can be calculated in Lattice Design Software. Some blocks can be placed into low current standby modes. Refer to Power Management and Calculation for Certus-NX, CertusPro-NX, and MachXO5-NX Devices (FPGA-TN-02257). 

FPGA-DS-02102-1.7 

109 

**MachXO5-NX Family Data Sheet** 

## **4.11. sysI/O Recommended Operating Conditions** 

**Table 4.14. sysI/O Recommended Operating Conditions** 

|**Standard**<br>~~Bf~~|**Support Banks**<br>~~Bf~~|**VCCIO(Input)**<br>~~Ef~~|**VCCIO(Output)**<br>~~Ef~~|
|---|---|---|---|
|||**Typ.**<br>~~Ef~~<br>~~a~~|**Typ. **<br>~~Ef~~<br>~~a~~|
|**Single-Ended**<br>~~Bf~~<br>~~Ef~~<br>~~**G**e~~<br>~~GO~~||||
|LVCMOS33<br>~~**G**~~|0, 1, 2, 6, 7<br>~~**G**e~~|3.3<br>~~e~~|3.3<br>~~GO~~|
|LVTTL33<br>~~**G**~~|0, 1, 2, 6, 7<br>~~**G**e~~|3.3<br>~~e~~<br>~~G~~|3.3<br>~~GO~~<br>~~G~~|
|LVCMOS25¹,²<br>~~GG~~|1, 2, 6, 7<br>~~GG~~|2.5, 3.3<br>~~GG~~|2.5<br>~~GG~~|
|LVCMOS18¹,²<br>~~GG~~<br>~~**G**~~|1, 2, 6, 7<br>~~GG~~<br>~~**G**e~~|1.2, 1.5, 1.8, 2.5, 3.3<br>~~GG~~<br>~~e~~|1.8<br>~~GG~~<br>~~GO~~|
|LVCMOS18H<br>~~**G**~~|3, 4, 5<br>~~**G**e~~|1.8<br>~~e~~|1.8<br>~~GO~~|
|LVCMOS15¹,²<br>~~**G**~~|1, 2, 6, 7<br>~~**G**e~~|1.2, 1.5, 1.8, 2.5, 3.3<br>~~e~~<br>~~G~~|1.5<br>~~GO~~<br>~~G~~|
|LVCMOS15H¹<br>~~GG~~|3, 4, 5<br>~~GG~~|1.5, 1.8<br>~~GG~~|1.5<br>~~GG~~|
|LVCMOS12¹,²<br>~~GG~~|1, 2, 6, 7<br>~~GG~~|1.2, 1.5, 1.8, 2.5, 3.3<br>~~GG~~|1.2<br>~~GG~~|
|LVCMOS12H¹<br>~~DO~~|3, 4, 5<br>~~DO~~|1.2, 1.357, 1.5, 1.8<br>~~DO~~|1.2<br>~~DO~~|
|LVCMOS10¹<br>~~DO~~<br>~~GG~~|1, 2, 6, 7<br>~~DO~~<br>~~GG~~|1.2, 1.5, 1.8, 2.5, 3.3<br>~~DO~~<br>~~GG~~|—<br>~~DO~~<br>~~GG~~|
|LVCMOS10H¹<br>~~GG~~|3, 4, 5<br>~~GG~~|1.0, 1.2, 1.357, 1.5, 1.8<br>~~GG~~|1.0<br>~~GG~~|
|LVCMOS10R¹<br>~~GG~~|3, 4, 5<br>~~GG~~|1.0, 1.2, 1.357, 1.5, 1.8<br>~~GG~~|—<br>~~GG~~|
|SSTL135_I, SSTL135_II3<br>~~a~~|3, 4, 5|1.357|1.35|
|SSTL15_I, SSTL15_II3<br>~~a~~<br>~~GOO~~|3, 4, 5<br>~~GOO~~|1.58<br>~~GOO~~|1.58<br>~~GOO~~|
|HSTL15_I3<br>~~GOO~~<br>~~GG~~|3, 4, 5<br>~~GOO~~<br>~~GG~~|1.58<br>~~GOO~~<br>~~GG~~|1.58<br>~~GOO~~<br>~~GG~~|
|HSUL123<br>~~GG~~|3, 4, 5<br>~~GG~~|1.2<br>~~GG~~|1.2<br>~~GG~~|
|LVSTL_I9<br>~~GG~~|3, 4, 5<br>~~GG~~|1.1<br>~~GG~~|1.1<br>~~GG~~|
|LVSTL_II9<br>~~a~~|3, 4, 5|1.1|1.1|
|MIPI D-PHY LP Input6<br>~~a~~<br>~~DDO~~|3, 4, 5<br>~~DDO~~|1.2<br>~~DDO~~|1.2<br>~~DDO~~|
|**Differential**<br>~~DDO~~||||
|LVDS<br>~~DG~~|3, 4, 5<br>~~DG~~|1.2, 1.35, 1.5, 1.8<br>~~DG~~|1.8<br>~~DG~~|
|LVDSE5<br>~~GG~~|1, 2, 6, 7<br>~~GG~~|—<br>~~GG~~|2.5<br>~~GG~~|
|subLVDS<br>~~a~~<br>~~Ge~~|3, 4, 5<br>~~Ge~~|1.2, 1.35, 1.5, 1.8<br>~~Ge~~|—<br>~~GO~~|
|subLVDSE5<br>~~a~~<br>~~Ge~~|1, 2, 6, 7<br>~~Ge~~|—<br>~~Ge~~|1.8<br>~~GO~~|
|subLVDSEH5<br>~~Ge~~<br>~~a~~|3, 4, 5<br>~~Ge~~|—<br>~~Ge~~|1.8<br>~~GO~~|
|SLVS6<br>~~a~~|3, 4, 5|1.0, 1.2, 1.357, 1.5, 1.84|1.2, 1.357, 1.5, 1.84|
|MIPI D-PHY6<br>~~a~~<br>~~GOO~~|3, 4, 5<br>~~GOO~~|1.2<br>~~GOO~~|1.2<br>~~GOO~~|
|LVCMOS33D5<br>~~GOO~~<br>~~GOO~~<br>~~**G**~~|1, 2, 6, 7<br>~~GOO~~<br>~~GOO~~<br>~~**G**e~~|—<br>~~GOO~~<br>~~GOO~~<br>~~e~~|3.3<br>~~GOO~~<br>~~GOO~~<br>~~GO~~|
|LVTTL33D5<br>~~GOO~~<br>~~**G**~~|1, 2, 6, 7<br>~~GOO~~<br>~~**G**e~~|—<br>~~GOO~~<br>~~e~~|3.3<br>~~GOO~~<br>~~GO~~|
|LVCMOS25D5<br>~~**G**~~|1, 2, 6, 7<br>~~**G**e~~|—<br>~~e~~<br>~~G~~|2.5<br>~~GO~~<br>~~G~~|
|SSTL135D_I, SSTL135D_II5<br>~~a~~|3, 4, 5|—|1.357|
|SSTL15D_I, SSTL15D_II5<br>~~a~~<br>~~GOO~~|3, 4, 5<br>~~GOO~~|—<br>~~GOO~~|1.5<br>~~GOO~~|
|HSTL15D_I5<br>~~GOO~~<br>~~GOO~~<br>~~**G**~~|3, 4, 5<br>~~GOO~~<br>~~GOO~~<br>~~**G**e~~|—<br>~~GOO~~<br>~~GOO~~<br>~~e~~|1.5<br>~~GOO~~<br>~~GOO~~<br>~~GO~~|
|HSUL12D5<br>~~GOO~~<br>~~**G**~~|3, 4, 5<br>~~GOO~~<br>~~**G**e~~|—<br>~~GOO~~<br>~~e~~|1.2<br>~~GOO~~<br>~~GO~~|
|LVSTLD_I5<br>~~**G**~~|3, 4, 5<br>~~**G**e~~|—<br>~~e~~<br>~~G~~|1.1<br>~~GO~~<br>~~G~~|
|LVSTLD_II5<br>~~a~~|3, 4, 5|—|1.1|



**Notes** : 

1. Single-ended input can mix into I/O Banks with VCCIO different from the standard requires due to some of these input standards use internal supply voltage source (VCC, VCCAUX) to power the input buffer, which makes them to be independent of VCCIO voltage. For more details, please refer to sysI/O User Guide for Nexus Platform (FPGA-TN-02067). The following is a brief guideline to follow: 

   - a. Weak pull-up on the I/O must be set to OFF. 

   - b. Bank 3, Bank 4, and Bank 5 I/O can only mix into banks with VCCIO higher than the pin standard, due to clamping diode on the pin in these banks. Bank 0, Bank 1, Bank 2, Bank 6, and Bank 7 do not have this restriction. 

© 2021-2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02102-1.7 

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**MachXO5-NX Family Data Sheet** 

   - c. LVCMOS25 uses VCCIO supply on input buffer in Bank 0, Bank 1, Bank 2, Bank 6, and Bank 7. It can be supported with VCCIO = 3.3 V to meet the VIH and VIL requirements, but there is additional current drawn on VCCIO. Hysteresis has to be disabled when using 3.3 V supply voltage. 

   - d. LVCMOS15 uses VCCIO supply on input buffer in Bank 3, Bank 4, and Bank 5. It can be supported with VCCIO = 1.8 V to meet the VIH and VIL requirements, but there is additional current drawn on VCCIO. 

2. Single-ended LVCMOS inputs can mixed into I/O Banks with different VCCIO, providing weak pull-up is not used. For additional information on Mixed I/O in Bank VCCIO, refer to  sysI/O User Guide for Nexus Platform (FPGA-TN-02067) **.** 

3. These inputs use differential input comparator in Bank 3, Bank 4, and Bank 5. The differential input comparator uses VCCAUXH power supply. These inputs require the VREF pin to provide the reference voltage in the Bank. Refer to  sysI/O User Guide for Nexus Platform (FPGA-TN-02067) for details **.** 

4. All differential inputs use differential input comparator in Bank 3, Bank 4, and Bank 5. The differential input comparator uses VCCAUXH power supply. There is no differential input signaling supported in Bank 0, Bank 1, Bank 2, Bank 6, and Bank 7. 

5. These outputs are emulating differential output pair with single-ended output drivers with true and complement outputs driving on each of the corresponding true and complement output pair pins. The common mode voltage, VCM, is ½  × VCCIO. Refer to sysI/O User Guide for Nexus Platform (FPGA-TN-02067) for details **.** 

6. Soft MIPI D-PHY HS using sysI/O is supported with SLVS input and output that can be placed in banks with VCCIO voltage shown in SLVS. D-PHY with HS and LP modes supported needs to be placed in banks with VCCIO voltage = 1.2 V. Soft MIPI D-PHY LP input and output using sysI/O are supported with LVCMOS12. 

7. VCCIO = 1.35 V is only supported in Bank 3, Bank 4, and Bank 5, for use with DDR3L interface in the bank. These Input and Output standards can fit into the same bank with the VCCIO = 1.35 V. 

8. LVCMOS15 input uses VCCIO supply voltage. If VCCIO is 1.8 V, the DC levels for LVCMOS15 are still met, but there could be increase in input buffer current. 

9. These inputs use differential input comparator in Bank 3, Bank 4, and Bank 5. The differential input comparator uses VCCAUXH power supply. These inputs require the VREF pin to provide the reference voltage in the Bank. Refer to  sysI/O User Guide for Nexus Platform (FPGA-TN-02067) for details **.** 

© 2021-2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02102-1.7 

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**MachXO5-NX Family Data Sheet** 

## **4.12. sysI/O Single-Ended DC Electrical Characteristics[3]** 

## **Table 4.15. sysI/O DC Electrical Characteristics – Wide Range I/O (Over Recommended Operating Conditions)** 

|**Input/Output Standard**|**VIL¹ **<br>~~|~~|**VIL¹ **<br>~~|~~|**VIH¹ **<br>~~|siz~~|**VIH¹ **<br>~~|siz~~|**VOL Max (V)**|**VOH Min² (V)**|**IOL(mA)**|**IOH(mA)**|
|---|---|---|---|---|---|---|---|---|
||**Min(V)**|**Max(V)**<br>~~|~~|**Min(V)**<br>~~|~~|**Max(V)**<br>|||||
|LVTTL33<br>LVCMOS33|—|0.8|2.0|3.4655|0.4|VCCIO– 0.4|2, 4, 8, 12,<br>16,<br>“50RS”3|-2, –4, –8,<br>–12,  -16,<br>“50RS”3|
|LVCMOS25|—|0.7|1.7|3.4655|0.4|VCCIO– 0.45|2, 4, 8, 10,<br>“50RS”3|–2, –4, –8,<br>–10,<br>“50RS”3|
|LVCMOS18<br>~~| ~~<br>~~PoC~~|—<br> ~~Ft~~|0.35 × VCCIO<br>~~Ft~~|0.65 × VCCIO<br>~~Ft~~|3.4655|0.4|VCCIO– 0.45|2, 4, 8,<br>“50RS”3|–2, –4, –8,<br>“50RS”3|
|LVCMOS15<br>~~PoC~~<br>~~ee~~|—<br>~~ee~~|0.35 × VCCIO|0.65 × VCCIO<br>~~GG~~|3.4655<br>~~GG~~|0.4<br>~~GG~~|VCCIO– 0.4|2, 4<br>~~I~~|–2, –4|
|LVCMOS12<br>~~PoC~~<br>~~ee~~|—<br>~~ee~~|0.35 × VCCIO|0.65 × VCCIO<br>~~GG~~|3.4655<br>~~GG~~|0.4<br>~~GG~~|VCCIO– 0.4|2, 4<br>~~I~~|–2, –4|
|LVCMOS10<br>~~ee~~<br>~~eG~~|—<br>~~ee~~<br>~~eG~~|0.35 × VCCIO<br>~~eG~~|0.65 × VCCIO<br>~~GG~~<br>~~GF~~|3.4655<br>~~GG~~<br>~~GF~~|No O/P Support<br>~~GG~~<br>~~I~~<br>~~GF~~||||



**Notes** : 

1. VCCIO for input level refers to the supply rail level associated with a given input standard. 

2. VCCIO for the output levels refer to the VCCIO of the CertusPro-NX device. 

3. Selecting “50RS” in driver strength is to select 50 Ω series impedance driver. 

4. For electro-migration, the combined DC current sourced or sinked by I/O pads between two consecutive VCCIO or GND pad connections, or between the last VCCIO or GND in an I/O bank and the end of an I/O bank, as shown in the Logic Signal Connections table (also shown as I/O grouping) shall not exceed a maximum of n × 8 mA. _n_ is the number of I/O pads between the two consecutive bank VCCIO or GND connections or between the last VCCIO and GND in a bank and the end of a bank. I/O Grouping can be found in the Data Sheet Pin Summary Tables, which can also be generated from the Lattice Radiant software. 

5. If the input clamp is OFF, VIH (Max) in Banks 0, 1, 2, 6, 7 can go up to 3.465 V. Otherwise, the input voltage cannot be higher than VCCIO + 0.3 V. 

© 2021-2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02102-1.7 

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|**Input/Output Standard**<br>~~ll~~<br>~~pt~~|**VIL¹ **<br>~~ll ———aT~~|**VIL¹ **<br>~~ll ———aT~~|**VIH¹ **<br>~~———aT~~|**VIH¹ **<br>~~———aT~~|**VOL Max (V)**<br>~~———aT Ta~~|**VOH Min² (V)**<br>~~Ta~~|**IOL (mA)**<br>~~Ta~~|**IOH (mA)**<br>~~Ta~~|
|---|---|---|---|---|---|---|---|---|
||**Min(V)**<br>~~ll ———aT~~<br>~~pt~~<br>~~|~~|**Max(V)**<br>~~———aT~~<br>~~EE~~|**Min(V)**<br>~~———aT~~<br>~~EE~~|**Max(V)**<br>~~———aT~~<br>~~EE~~|||||
|LVCMOS18H<br>~~ll~~<br>~~pt~~<br>~~a~~|—<br>~~ll ———aT~~<br>~~pt~~<br>~~|~~|0.35 × VCCIO <br>~~———aT~~<br>~~EE~~<br>~~ee~~|0.65 × VCCIO<br>~~———aT~~<br>~~EE~~<br>~~ee~~|VCCIO+ 0.3<br>~~———aT~~<br>~~EE~~<br>~~ee~~|0.4<br>~~———aT Ta~~<br>~~ee~~|VCCIO– 0.45<br>~~Ta~~|2, 4, 8,<br>12,<br>“50RS”3<br>~~Ta~~<br>~~ee~~|–2, –4, –8,<br>–12,<br>“50RS”3<br>~~Ta~~<br>~~ee~~|
|LVCMOS15H<br>~~pt~~<br>~~a~~<br>~~**a**~~|—<br>~~pt~~<br>~~| ~~|0.35 × VCCIO <br> ~~EE~~<br>~~ee~~<br>~~ee~~|0.65 × VCCIO<br>~~EE~~<br>~~ee~~<br>~~ee~~|VCCIO+ 0.3<br>~~EE~~<br>~~ee~~<br>~~ee~~|0.4<br>~~ee~~<br>~~ee~~|VCCIO– 0.4|2, 4, 8,<br>“50RS”3<br>~~ee~~<br>~~ee~~|–2, –4, –8,<br>“50RS”3<br>~~ee~~<br>~~ee~~|
|LVCMOS12H<br>~~a~~<br>~~**a**~~|—|0.35 × VCCIO <br>~~ee~~<br>~~ee~~|0.65 × VCCIO<br>~~ee ~~<br>~~ee~~|VCCIO+ 0.3<br> ~~ee~~<br>~~ee~~|0.4<br>~~ee~~<br>~~ee~~|VCCIO– 0.4|2, 4, 8,<br>“50RS”3<br>~~ee~~<br>~~ee~~|–2, –4, –8,<br>“50RS”3<br>~~ee~~<br>~~ee~~|
|LVCMOS10H<br>~~**a**~~|—|0.35 × VCCIO <br>~~ee~~|0.65 × VCCIO<br>~~ee ~~|VCCIO+ 0.3<br> ~~ee~~|0.27 × VCCIO<br>~~ee~~|0.75 × VCCIO|2, 4<br>~~ee~~|–2, -4<br>~~ee~~|
|SSTL15_I<br>~~a~~|—<br>~~a~~|VREF– 0.10<br>~~a~~|VREF+ 0.1<br>~~a~~|VCCIO+ 0.3<br>~~a~~|0.30<br>~~a~~|VCCIO– 0.30<br>~~a~~|7.5<br>~~a~~|–7.5<br>~~a~~|
|SSTL15_II<br>~~a~~|—<br>~~a~~|VREF– 0.10<br>~~a~~|VREF+ 0.1<br>~~a~~|VCCIO+ 0.3<br>~~a~~|0.30<br>~~a~~|VCCIO– 0.30<br>~~a~~|8.8<br>~~a~~|–8.8<br>~~a~~|
|HSTL15_I<br>~~a~~|—<br>~~a~~|VREF– 0.10<br>~~a~~|VREF+ 0.1<br>~~a~~|VCCIO+ 0.3<br>~~a~~|0.40<br>~~a~~|VCCIO– 0.40<br>~~a~~|8<br>~~a~~|–8<br>~~a~~|
|SSTL135_I<br>~~a~~|—<br>~~a~~|VREF– 0.09<br>~~a~~|VREF+ 0.09<br>~~a~~|VCCIO+ 0.3<br>~~a~~|0.27<br>~~a~~|VCCIO – 0.27<br>~~a~~|6.75<br>~~a~~|–6.75<br>~~a~~|
|SSTL135_II<br>~~a~~|—<br>~~a~~|VREF– 0.09<br>~~a~~|VREF+ 0.09<br>~~a~~|VCCIO+ 0.3<br>~~a~~|0.27<br>~~a~~|VCCIO– 0.27<br>~~a~~|8<br>~~a~~|–8<br>~~a~~|
|LVCMOS10R<br>~~a~~<br>~~a~~|—<br>~~a~~<br>~~a~~|VREF– 0.10<br>~~a~~<br>~~a~~|VREF+ 0.10<br>~~a~~<br>~~a~~|VCCIO+ 0.3<br>~~a~~<br>~~a~~|—<br>~~a~~<br>~~a~~|—<br>~~a~~<br>~~a~~|—<br>~~a~~<br>~~a~~|—<br>~~a~~<br>~~a~~|
|HSUL12<br>~~a~~<br>~~pot~~|—<br>~~a~~<br>~~potTE~~|VREF– 0.10<br>~~a~~<br>~~TE~~|VREF+ 0.10<br>~~a~~<br>~~TE~~|VCCIO+ 0.3<br>~~a~~|0.3<br>~~a~~|VCCIO– 0.3<br>~~a~~|8.0, 7.5,<br>6.25, 5<br>~~a~~|–8.0, –7.5,<br>–6.25, –5<br>~~a~~|
|LVSTL_I<br>~~pot~~|–0.2<br>~~potTE~~|0.35 ×<br>VCCIO<br>~~TE~~|0.65 ×<br>VCCIO<br>~~TE~~|VCCIO+ 0.2|0.1 × VCCIO|0.3 × VCCIO<br>~~ee~~|2, 4, 6, 8,<br>10<br>~~ee~~|–2, –4,<br>–6, –8,<br>–10<br>~~ee~~|
|LVSTL_II<br>~~pot~~<br>~~a ee~~|–0.2<br>~~pot TE~~<br>~~ee~~|0.35 ×<br>VCCIO<br>~~TE~~<br>~~ee~~|0.65 ×<br>VCCIO<br>~~TE~~<br>~~ee~~|VCCIO+ 0.2<br>~~ee~~|0.1 × VCCIO<br>~~ee~~|0.36 × VCCIO<br>~~ee~~<br>~~ee~~|4, 6<br>~~ee~~<br>~~ee~~|–4, –6<br>~~ee~~<br>~~ee~~|



## **Notes:** 

1. VCCIO for input level refers to the supply rail level associated with a given input standard or the upstream driver VCCIO rail levels. 

2. VCCIO for the output levels refer to the VCCIO of the MachXO5-NX device. 

3. Select “50RS” in driver strength is selecting the 50Ω series impedance driver. 

4. For electro-migration, the combined DC current sourced or sinked by I/O pads between two consecutive VCCIO or GND pad connections, or between the last VCCIO or GND in an I/O bank and the end of an I/O bank, as shown in the Logic Signal Connections table (also shown as I/O grouping) shall not exceed a maximum of n × 8 mA. n is the number of I/O pads between the two consecutive bank VCCIO or GND connections or between the last VCCIO and GND in a bank and the end of a bank. I/O Grouping can be found in the Data Sheet Pin Summary Tables, which can also be generated from the Lattice Radiant software. 

**Table 4.17. I/O Resistance Characteristics (Over Recommended Operating Conditions)** 

|**Parameter**|**Description**|**Test Conditions**|**Min**|**Typ**|**Max**|**Unit**|
|---|---|---|---|---|---|---|
|50RS|Output Drive Resistance when 50RS<br>Drive Strength Selected|VCCIO= 1.8 V, 2.5 V, or 3.3 V|—|50|—|Ω|
|RDIFF|Input Differential Termination<br>Resistance|Bank 3, Bank 4 and Bank 5 for I/O<br>selected to be differential|—|100|—|Ω|
|SE Input<br>Termination|Input Single Ended Termination<br>Resistance|Bank 3, Bank 4 and Bank 5 for I/O<br>selected to be Single Ended|36|40|64|Ω|
||||46|50|80||
||||56|60|96||
||||71|75|120||



© 2021-2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02102-1.7 

113 

**MachXO5-NX Family Data Sheet** 

**Table 4.18. VIN Maximum Overshoot/Undershoot Allowance – Wide Range[1,2]** 

|**AC Voltage Overshoot**|**% of UI at –40 °C to 100 °C**|**AC Voltage Undershoot**|**% of UI at –40 °C to 100 °C**|
|---|---|---|---|
|VCCIO+ 0.4|100.0%|–0.4|100.0%|
|VCCIO+ 0.5|100.0%|–0.5|44.2%|
|VCCIO+ 0.6|94.0%|–0.6|10.1%|
|VCCIO+ 0.7|21.0%|–0.7|1.3%|
|VCCIO+ 0.8|10.2%|–0.8|0.3%|
|VCCIO+ 0.9|2.5%|–0.9|0.1%|



**Notes** : 

1. The peak overshoot or undershoot voltage and the duration above VCCIO + 0.2 V or below GND – 0.2 V must not exceed the values in this table. 

2. For UI less than 20 µs. 

**Table 4.19. VIN Maximum Overshoot/Undershoot Allowance – High Performance[1,2]** 

|**AC Voltage Overshoot**|**% of UI at –40 °C to 100 °C**|**AC Voltage Undershoot**|**% of UI at –40 °C to 100 °C**|
|---|---|---|---|
|VCCIO+ 0.5|100.0%|–0.5|100.0%|
|VCCIO+ 0.6|47.3%|–0.6|47.3%|
|VCCIO+ 0.7|10.9%|–0.7|10.9%|
|VCCIO+ 0.8|2.7%|–0.8|2.7%|
|VCCIO+ 0.9|0.7%|–0.9|0.7%|



**Notes** : 

1. The peak overshoot or undershoot voltage and the duration above VCCIO + 0.2 V or below GND – 0.2 V must not exceed the values in this table. 

2. For UI less than 20 µs. 

## **4.13. sysI/O Differential DC Electrical Characteristics** 

## **4.13.1. LVDS** 

LVDS input buffer on MachXO5-NX is powered by VCCAUX = 1.8 V, and protected by the bank VCCIO. Therefore, the LVDS input voltage cannot exceed the bank VCCIO voltage. LVDS output buffer is powered by the Bank VCCIO at 1.8 V. 

LVDS can only be supported in Bank 3, Bank 4, and Bank 5. LVDS25 output can be emulated with LVDS25E in Bank 1, Bank 2,  Bank 6 and Bank 7. This is described in LVDS25E (Output Only) section. 

**Table 4.20. LVDS DC Electrical Characteristics (Over Recommended Operating Conditions)[1 ]** 

|**Parameter**<br>~~GO~~|**Description**<br>~~GO~~|**Test Conditions**<br>~~GO~~|**Min**<br>~~GO~~|**Typ**<br>~~GO~~|**Max**<br>~~GO~~|**Unit**<br>~~GO~~|
|---|---|---|---|---|---|---|
|VINP, VINM<br>~~a GG~~|Input Voltage<br>~~GG~~|—<br>~~GG~~|0<br>~~GG~~|—<br>~~GG~~|1.603<br>~~GG~~|V<br>~~GG~~|
|VICM<br>~~a GG~~<br>~~OO~~|Input Common Mode Voltage<br>~~GG~~<br>~~OO~~|Half the sum of the two Inputs<br>~~GG~~<br>~~OO~~|0.05<br>~~GG~~<br>~~OO~~|—<br>~~GG~~<br>~~OO~~|1.55Z<br>~~GG~~<br>~~OO~~|V<br>~~GG~~<br>~~OO~~|
|VTHD<br>~~OO~~<br>~~OO~~|Differential Input Threshold<br>~~OO~~<br>~~OO~~|Difference between the two Inputs<br>~~OO~~<br>~~OO~~|±100<br>~~OO~~<br>~~OO~~|—<br>~~OO~~<br>~~OO~~|—<br>~~OO~~<br>~~OO~~|mV<br>~~OO~~<br>~~OO~~|
|IIN<br>~~OO~~<br>~~sO~~|Input Current<br>~~OO~~<br>~~sO~~|Power On or Power Off<br>~~OO~~<br>~~sO~~<br>~~GO~~|—<br>~~OO~~<br>~~sO~~<br>~~GO~~|—<br>~~OO~~<br>~~sO~~<br>~~GO~~|±10<br>~~OO~~<br>~~sO~~|µA<br>~~OO~~<br>~~sO~~|
|VOH<br>~~se~~|Output High Voltage for VOPor VOM<br>~~se~~|RT= 100 Ω<br>~~se~~<br>~~GO~~|—<br>~~se~~<br>~~GO~~|1.425<br>~~se~~<br>~~GO~~|1.60<br>~~se~~|V<br>~~se~~|
|VOL<br>~~GO~~|Output Low Voltage for VOPor VOM<br>~~GO~~|RT= 100 Ω<br>~~GO~~<br>~~GO~~|0.9<br>~~GO~~<br>~~GO~~|1.075<br>~~GO~~<br>~~GO~~|—<br>~~GO~~|V<br>~~GO~~|
|VOD<br>~~a GG~~|Output Voltage Differential<br>~~GG~~|(VOP- VOM), RT= 100 Ω<br>~~GG~~|250<br>~~GG~~|350<br>~~GG~~|450<br>~~GG~~|mV<br>~~GG~~|
|VOD<br>~~a GG~~<br>~~a~~|Change in VODBetween High and<br>Low<br>~~GG~~<br>~~ee~~|—<br>~~GG~~<br>~~ee~~|—<br>~~GG~~<br>~~ee~~|—<br>~~GG~~<br>~~ee~~|50<br>~~GG~~<br>~~ee~~|mV<br>~~GG~~<br>~~ee~~|
|VOCM<br>~~a~~<br>~~DO~~|Output Common Mode Voltage<br>~~ee~~<br>~~DO~~|(VOP+ VOM)/2, RT= 100 Ω<br>~~ee~~<br>~~DO~~|1.125<br>~~ee~~<br>~~DO~~|1.25<br>~~ee~~<br>~~DO~~|1.375<br>~~ee~~<br>~~DO~~|V<br>~~ee~~<br>~~DO~~|
|VOCM<br>~~DO~~<br>~~a~~|Change in VOCM, VOCM(MAX)- VOCM(MIN)<br>~~DO~~<br>~~a~~<br>~~a~~|—<br>~~DO~~|—<br>~~DO~~|—<br>~~DO~~|50<br>~~DO~~|mV<br>~~DO~~|
|ISAB<br>~~a~~|Output Short Circuit Current<br>~~aee~~|VOD= 0 V Driver outputs shorted to<br>each other<br>~~ee~~|—<br>~~ee~~|—<br>~~ee~~|12<br>~~ee~~|mA<br>~~ee~~|
|VOS<br>~~a~~|Change in VOSbetween H and L|—|—|—|50|mV|



© 2021-2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

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**MachXO5-NX Family Data Sheet** 

**Notes** : 

1. LVDS input or output are supported in Bank 3, Bank 4, and Bank 5. LVDS input uses VCCAUX on the differential input comparator, and can be located in any VCCIO voltage bank. LVDS output uses VCCIO on the differential output driver, and can only be located in bank with VCCIO = 1.8 V. 

2. VICM is depending on VID, input differential voltage, so the voltage on pin cannot exceed VINP/INM(min/max) requirements. VICM(min) = VINP/INM(min) + ½  VID, VICM(max) = VINP/INM(max) – ½  VID. Values in the table is based on minimum VID of +/- 100 mV. 

3. VINP and VINM(max) must be less than or equal to VCCIO in all cases. 

## **4.13.2. LVDS25E (Output Only)** 

Three sides of the MachXO5-NX devices, Top, Left and Right, support LVDS25 outputs with emulated complementary LVCMOS outputs in conjunction with a parallel resistor across the driver outputs. The scheme shown in Figure 4.2Figure 3.2 is one possible solution for point-to-point signals. 

**Table 4.21. LVDS25E DC Conditions** 

**==> picture [486 x 336] intentionally omitted <==**

**----- Start of picture text -----**<br>
(eG Parameter  Description  Typical  Unit<br>VCCIO GO Output Driver Supply (±5%)  2.50  V<br>es (O<br>a ZOUT Driver Impedance  20  Ω<br>GO RS Driver Series Resistor (±1%)  158  Ω<br>eG RP Driver Parallel Resistor (±1%)  140  Ω<br>a RT Receiver Termination (±1%)  100  ( Ω<br>GO VOH Output High Voltage  1.43  V<br>a VOL Output Low Voltage  1.07  V<br>GG VOD Output Differential Voltage  0.35  V<br>VCM Output Common Mode Voltage  1.25  V<br>ee<br>GG ZBACK Back Impedance  100.5  Ω<br>Fe IDC DC Output Current  6.03  DO mA<br>VCCIO = 2.5 V (±5%) ||<br>RS = 158<br>| (±1%)<br>8 mA a a<br>> LVCMOS25 |<br>RS = 140     RS = 100<br>VCCIO = 2.5 V (±5%) (±1%) (±1%)<br>RS = 158<br>(±1%)<br>8 mA<br>> LVCMOS25 a r<br>Transmission line, Zo = 100   differential<br>| |<br>ON-chip OFF-chip ON-chip OFF-chip<br>**----- End of picture text -----**<br>


**Figure 4.2. LVDS25E Output Termination Example** 

## **4.13.3. SubLVDS (Input Only)** 

SubLVDS is a reduced-voltage form of LVDS signaling, very similar to LVDS. It is a standard used in many camera types of applications. Similar to LVDS, the MachXO5-NX devices can support the subLVDS input signaling with the same LVDS input buffer. The output for subLVDS is implemented in subLVDSE/subLVDSEH with a pair of LVCMOS18 output drivers. See SubLVDSE/SubLVDSEH (Output Only) section. 

© 2021-2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

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**MachXO5-NX Family Data Sheet** 

**Table 4.22. SubLVDS Input DC Electrical Characteristics (Over Recommended Operating Conditions)** 

|**Parameter**|**Description**|**Test Conditions**|**Min**|**Typ**|**Max**|**Unit**|
|---|---|---|---|---|---|---|
|VID|Input Differential Threshold Voltage|Over VICMrange|70|150|200|mV|
|VICM|Input Common Mode Voltage|Half the sum of the two Inputs|0.4|0.9|1.41|V|



**Note** : 

**==> picture [471 x 291] intentionally omitted <==**

**----- Start of picture text -----**<br>
1. VICM + ½ VID cannot exceed the bank VCCIO in all cases.<br>Sub-LVDS Driver PCB Traces, Connectors or Cables<br>Z0 = 50<br>+ +<br>RT = 100<br>100    differential ±  1%*<br>– –<br>Z0 = 50<br>SEED<br>Off-chip On-chip<br>Figure 4.3. SubLVDS Input Interface<br>4.13.4. SubLVDSE/SubLVDSEH (Output Only)<br>SubLVDS output uses a pair of LVCMOS18 drivers with True and Complement outputs.  The VCCIO of the<br>bank used for subLVDSE or subLVDSEH needs to be powered by 1.8 V. SubLVDSE is for Bank 1,<br>Bank 2, Bank 6 and Bank 7, and subLVDSEH is for Bank 3, Bank 4 and Bank 5.<br>**----- End of picture text -----**<br>


Performance of the subLVDSE/subLVDSEH driver is limited to the performance of LVCMOS18. 

|**Parameter**<br>~~i~~|**Description**<br>~~i~~|**Test Conditions**<br>~~i~~|**Min**<br>~~i~~|**Typ**<br>~~i~~|**Max**<br>~~i~~|**Unit**<br>~~i~~|
|---|---|---|---|---|---|---|
|VOD<br>~~i~~|Output Differential Voltage Swing<br>~~i~~|—<br>~~i~~|—<br>~~i~~|150<br>~~i~~|—<br>~~i~~|mV<br>~~i~~|
|VOCM<br>~~i~~|Output Common Mode Voltage<br>~~i~~|Half the sum of the two Outputs<br>~~i~~|—<br>~~i~~|0.9<br>~~i~~|—<br>~~i~~|V<br>~~i~~|



© 2021-2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

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**MachXO5-NX Family Data Sheet** 

**==> picture [435 x 181] intentionally omitted <==**

**----- Start of picture text -----**<br>
VCCIO = +1.8 V PCB Traces, Connectors or Cables<br>Z0 = 50<br>Rs = 267   ±1%<br>+ +<br>aa<br>SubLVDS Output<br>SubLVDSE Rp = 121   ±1% 100    differential RT  = 100   ±1% Sub-LVDS Recevier<br>SubLVDSEH<br>– –<br>Rs = 267   ±1%<br>Z0 = 50<br>0<br>On-chip Off-chip On-chip Off-chip<br>**----- End of picture text -----**<br>


**Figure 4.4. SubLVDS Output Interface** 

## **4.13.5. SLVS** 

Scalable Low-Voltage Signaling (SLVS) is based on a point-to-point signaling method defined in the JEDEC JESD8-13 (SLVS-400) standard. This standard evolved from the traditional LVDS standard with smaller voltage swings and a lower common-mode voltage. The 200 mV (400 mV p-p) SLVS swing contributes to a reduction in power. 

The MachXO5-NX devices receive SLVS differential input with the LVDS input buffer. This LVDS input buffer is designed to cover wide input common mode range that can meet the SLVS input standard specified by the JEDEC standard. 

**Table 4.24. SLVS Input DC Characteristics (Over Recommended Operating Conditions)** 

|**Parameter**|**Description**|**Test Conditions**|**Min**|**Typ**|**Max**|**Unit**|
|---|---|---|---|---|---|---|
|VID|Input Differential Threshold Voltage|Over VICMrange|70|—|—|mV|
|VICM|Input Common Mode Voltage|Half the sum of the two Inputs|70|200|330|mV|



The SLVS output on the MachXO5-NX device is supported with the LVDS drivers found in Bank 3, Bank 4 and Bank 5. The LVDS driver on the MachXO5-NX device is a current controlled driver. It can be configured as LVDS driver, or configured with the 100 Ω differential termination with center-tap set to VOCM at 200 mV. This means the differential output driver can be placed into bank with VCCIO = 1.2 V, 1.5 V, or 1.8 V, even if it is powered by VCCIO. 

© 2021-2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

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**MachXO5-NX Family Data Sheet** 

**Table 4.25. SLVS Output DC Characteristics (Over Recommended Operating Conditions)** 

|**Parameter**|**Description**|**Test Conditions**|**Min**|**Typ**|**Max**|**Unit**|
|---|---|---|---|---|---|---|
|VCCIO|Bank VCCIO|—|–5%|1.2,<br>1.5,<br>1.8|+ 5%|V|
|VOD|Output Differential Voltage Swing|—|140|200|270|mV|
|VOCM|Output Common Mode Voltage|Half the sum of the two Outputs|150|200|250|mV|
|ZOS|Single-Ended Output Impedance|—|37.5|50|62.5|Ω|



**Figure 4.5. SLVS Interface** 

## **4.13.6. Soft MIPI D-PHY** 

When Soft D-PHY is implemented inside the FPGA logic, the I/O interface needs to use sysI/O buffers to connect to external D-PHY pins. 

The MachXO5-NX sysI/O provides support of SLVS, as described in SLVS section, plus the LVCMOS12 input / output buffers together to support the High Speed (HS) and Low Power (LP) mode as defined in MIPI Alliance Specification for D-PHY. 

To support MIPI D-PHY with SLVS (LVDS) and LVCMOS12, the bank VCCIO cannot be set to 1.5 V or 1.8 V. It has to connect to 1.2 V, or 1.1 V. 

All other DC parameters are the same as those listed in SLVS section. DC parameters for the LP driver and receiver are the same as those listed in LVCMOS12. 

© 2021-2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

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**==> picture [449 x 460] intentionally omitted <==**

**----- Start of picture text -----**<br>
MachXO5-NX Family<br>Data Sheet<br>LVCMOS12<br>LP Data_P<br>LPenable<br>HSenable MIPI Receiver<br>100   Diff<br>+ +<br>HS Data  Z0=50<br>–  –<br>SLVS<br>= aS<br>LPenable<br>LP Data_N<br>LVCMOS12<br>hp<br>MIPI_LP_RX<br>On-Chip<br>RXLP_P<br>MIPI Divider<br>+ +<br>HS Data  Z0=50<br>–  –<br>LVDS<br>- -<br>MIPI_LP_RX<br>RXLP_N<br>=H<br>Figure 4.6. MIPI Interface<br>**----- End of picture text -----**<br>


© 2021-2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

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**MachXO5-NX Family Data Sheet** 

**Table 4.26. Soft D-PHY Input Timing and Levels** 

|**Symbol**<br>~~a ~~|**Description**<br> ~~a~~|**Conditions**<br>~~(OD~~|**Min**<br>~~(OD~~|**Typ**<br>~~(OD~~|**Max**<br>~~(OD~~|**Unit**<br>~~(OD~~|
|---|---|---|---|---|---|---|
|**High Speed(Differential) Input DC Specifications**|||||||
|VCMRX(DC)<br>~~a eG~~|Common-mode Voltage in High Speed Mode<br>~~eG~~|—<br>~~eG~~|70<br>~~eG~~|—<br>~~eG~~|330<br>~~eG~~|mV<br>~~eG~~|
|VIDTH<br>~~a~~|Differential Input HIGH Threshold<br>~~eG~~|—<br>~~eG~~|70<br>~~eG~~|—<br>~~eG~~|—<br>~~eG~~|mV<br>~~eG~~|
|VIDTL<br>~~a~~<br>~~a~~|Differential Input LOW Threshold|—|—<br>~~GO~~|—<br>~~GO~~|–70|mV|
|VIHHS<br>~~a~~<br>~~a~~|Input HIGH Voltage(for HS mode)<br>~~eG~~|—<br>~~eG~~|—<br>~~eG~~<br>~~GO~~|—<br>~~eG~~<br>~~GO~~|460<br>~~eG~~|mV<br>~~eG~~|
|VILHS<br>~~a~~|Input LOW Voltage|—|–40<br>~~GO~~|—<br>~~GO~~|—|mV|
|VTERM-EN<br>~~a~~|Single-ended voltage for HS Termination Enable4|—|—<br>~~GO~~|—<br>~~GO~~|450|mV|
|ZID<br>~~a eG~~|Differential Input Impedance<br>~~eG~~|—<br>~~eG~~|80<br>~~eG~~<br>~~GO~~|100<br>~~eG~~<br>~~GO~~|125<br>~~eG~~|Ω<br>~~eG~~|
|**High Speed(Differential) Input AC Specifications**<br>~~GO~~<br>~~a~~<br>~~G~~|||||||
|ΔVCMRX(HF)1<br>~~a~~|Common-mode Interference(>450 MHz)|—|—<br>~~G~~|—<br>~~G~~|100|mV|
|ΔVCMRX(LF)2, 3<br>~~a~~<br>~~a eG~~<br>~~ee~~|Common-mode Interference(50 MHz – 450 MHz)<br>~~eG~~|—<br>~~eG~~|–50<br>~~G~~<br>~~eG~~|—<br>~~G~~<br>~~eG~~|50<br>~~eG~~|mV<br>~~eG~~|
|CCM<br>~~ee~~|Common-mode Termination|—|||60|pF|
|**Low Power(Single-Ended) Input DC Specifications**<br>~~ee~~|||||||
|VIH<br>~~a~~|Low Power Mode Input HIGH Voltage<br>~~eG~~|—<br>~~eG~~|740<br>~~eG~~|—<br>~~eG~~|—<br>~~eG~~|mV<br>~~eG~~|
|VIL<br>~~eG~~|Low Power Mode Input LOW Voltage<br>~~eG~~|—<br>~~eG~~|—<br>~~eG~~|—<br>~~eG~~|480<br>~~eG~~|mV<br>~~eG~~|
|VIL-ULP<br>~~GGG~~|Ultra Low Power Input LOW Voltage<br>~~GGG~~|—<br>~~GGG~~|—<br>~~GGG~~|—<br>~~GGG~~|300<br>~~GGG~~|mV<br>~~GGG~~|
|VHYST<br>~~GGG~~<br>~~a~~|Low Power Mode Input Hysteresis<br>~~GGG~~|—<br>~~GGG~~|25<br>~~GGG~~|—<br>~~GGG~~|—<br>~~GGG~~|mV<br>~~GGG~~|
|℮SPIKE<br>~~a~~<br>~~a~~|Input Pulse Rejection<br>|—<br>|—<br>|—<br>|300<br>|V∙ps<br>|
|TMIN-RX<br>~~eG~~|Minimum Pulse Width Response<br>~~eG~~|—<br>~~eG~~|20<br>~~eG~~|—<br>~~eG~~|—<br>~~eG~~|ns<br>~~eG~~|
|VINT<br>~~eG~~|Peak Interference Amplitude<br>~~eG~~|—<br>~~eG~~|—<br>~~eG~~|—<br>~~eG~~|200<br>~~eG~~|mV<br>~~eG~~|
|fINT<br>~~GD~~|Interference Frequency<br>~~GD~~|—<br>~~GD~~|450<br>~~GD~~|—<br>~~GD~~|—<br>~~GD~~|MHz<br>~~GD~~|



## **Notes** : 

1. This is peak amplitude of sine wave modulated to the receiver inputs. 

2. Input common-mode voltage difference compared to average common-mode voltage on the receiver inputs. 

3. Exclude any static ground shift of 50 mV. 

4. High Speed Differential RTERM is enabled when both DP and DN are below this voltage. 

© 2021-2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

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**MachXO5-NX Family** 

**Data Sheet** 

**Table 4.27. Soft D-PHY Output Timing and Levels** 

|**Symbol**<br>~~GF~~|**Description**<br>~~GF~~|**Conditions**<br>~~GF~~|**Min**<br>~~GF~~|**Typ**<br>~~GF~~|**Max**<br>~~GF~~|**Unit**<br>~~GF~~|
|---|---|---|---|---|---|---|
|**High Speed(Differential) Output DC Specifications**|||||||
|VCMTX<br>~~a GO~~<br>~~a~~|Common-mode Voltage in High Speed Mode<br>~~GO~~<br>~~ee~~|—<br>~~GO~~<br>~~ee~~|150<br>~~GO~~<br>~~ee~~|200<br>~~GO~~<br>~~ee~~|250<br>~~GO~~<br>~~ee~~|mV<br>~~GO~~<br>~~ee~~|
||ΔVCMTX(1,0)|<br>~~a~~<br>~~a~~|VCMTXMismatch Between Differential HIGH<br>and LOW<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~|7<br>~~ee~~<br>~~ee~~|mV<br>~~ee~~<br>~~ee~~|
||VOD|<br>~~a~~<br>~~a~~<br>~~a~~|Output Differential Voltage<br>~~ee~~<br>~~ee~~<br>~~ee~~||D-PHY-P – D-PHY-<br>N|<br>~~ee~~<br>~~ee~~<br>~~ee~~|140<br>~~ee~~<br>~~ee~~<br>~~ee~~|200<br>~~ee~~<br>~~ee~~<br>~~ee~~|270<br>~~ee~~<br>~~ee~~<br>~~ee~~|mV<br>~~ee~~<br>~~ee~~<br>~~ee~~|
||ΔVOD|<br>~~a~~<br>~~a~~|VODMismatch Between Differential HIGH and<br>LOW<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~|25<br>~~ee~~<br>~~ee~~|mV<br>~~ee~~<br>~~ee~~|
|VOHHS<br>~~a~~<br>~~a GOO~~|Single-Ended Output HIGH Voltage<br>~~ee~~<br>~~GOO~~|—<br>~~ee~~<br>~~GOO~~|—<br>~~ee~~<br>~~GOO~~|—<br>~~ee~~<br>~~GOO~~|410<br>~~ee~~<br>~~GOO~~|mV<br>~~ee~~<br>~~GOO~~|
|ZOS<br>~~a GO~~<br>~~eeGD~~|Single Ended Output Impedance<br>~~GO~~<br>~~GD~~|—<br>~~GO~~<br>~~GD~~|37.5<br>~~GO~~<br>~~GD~~|50<br>~~GO~~<br>~~GD~~|80<br>~~GO~~<br>~~GD~~|Ω<br>~~GO~~<br>~~GD~~|
|ΔZOS<br>~~eeGD~~|ZOSmismatch<br>~~GD~~|—<br>~~GD~~|—<br>~~GD~~|—<br>~~GD~~|20<br>~~GD~~|%<br>~~GD~~|
|**High Speed(Differential) Output AC Specifications**<br>~~eeGD~~|||||||
|ΔVCMTX(LF)<br>~~GO~~|Common-Mode Variation, 50 MHz–450 MHz<br>~~GO~~|—<br>~~GO~~|—<br>~~GO~~|—<br>~~GO~~|25<br>~~GO~~|mVRMS<br>~~GO~~|
|ΔVCMTX(HF)<br>~~GO~~<br>~~a GG~~|Common-Mode Variation, above 450 MHz<br>~~GO~~<br>~~GG~~|—<br>~~GO~~<br>~~GG~~|—<br>~~GO~~<br>~~GG~~|—<br>~~GO~~<br>~~GG~~|15<br>~~GO~~<br>~~GG~~|mVRMS<br>~~GO~~<br>~~GG~~|
|tR|Output 20%–80% Rise Time<br>Output 80%–20% Fall Time|0.08 Gbps ≤ tR≤ 1.00<br>Gbps|—|—|0.30|UI|
|||1.00 Gbps < tR≤ 1.25<br>Gbps<br>~~a~~|—<br>~~eee~~|—<br>~~eee~~|0.434<br>~~eee~~|UI<br>~~eee~~|
|tF|Output Data Valid After CLK Output|0.08 Gbps ≤ tF≤ 1.00<br>Gbps<br>~~a ~~<br>~~a~~|—<br> ~~eee~~<br>~~ee~~|—<br>~~eee~~<br>~~eee~~|0.30<br>~~eee~~<br>~~eee~~|UI<br>~~eee~~<br>~~eee~~|
|||1.00 Gbps < tF≤ 1.25<br>Gbps<br>~~a~~|—<br>~~ee~~|—<br>~~eee~~|0.419<br>~~eee~~|UI<br>~~eee~~|
|**Low Power(Single-Ended) Output DC Specifications**<br>~~a~~<br>~~eeeee~~|||||||
|VOH<br>~~aee~~|Low Power Mode Output HIGH Voltage<br>~~ee~~|0.08 Gbps – 1.25<br>Gbps<br>~~ee~~|1.07<br>~~ee~~|1.2<br>~~ee~~|1.3<br>~~ee~~|V<br>~~ee~~|
|VOL<br>~~GO~~|Low Power Mode Input LOW Voltage<br>~~GO~~|—<br>~~GO~~|–50<br>~~GO~~|—<br>~~GO~~|50<br>~~GO~~|mV<br>~~GO~~|
|ZOLP<br>~~a GC~~|Output Impedance in Low Power Mode<br>~~GC~~|—<br>~~GC~~|110<br>~~GC~~|—<br>~~GC~~|—<br>~~GC~~|Ω<br>~~GC~~|
|**Low Power(Single-Ended) Output AC Specifications**|||||||
|tRLP<br>~~OO~~|15%–85% Rise Time<br>~~OO~~|—<br>~~OO~~|—<br>~~OO~~|—<br>~~OO~~|25<br>~~OO~~|ns<br>~~OO~~|
|tFLP<br>~~OO~~<br>~~a GOO~~<br>~~eeGOO~~|85%–15% Fall Time<br>~~OO~~<br>~~GOO~~<br>~~GOO~~|—<br>~~OO~~<br>~~GOO~~<br>~~GOO~~|—<br>~~OO~~<br>~~GOO~~<br>~~GOO~~|—<br>~~OO~~<br>~~GOO~~<br>~~GOO~~|25<br>~~OO~~<br>~~GOO~~<br>~~GOO~~|ns<br>~~OO~~<br>~~GOO~~<br>~~GOO~~|
|tREOT<br>~~eeGOO~~|HS – LP Mode Rise and Fall Time, 30%–85%<br>~~GOO~~|—<br>~~GOO~~|—<br>~~GOO~~|—<br>~~GOO~~|35<br>~~GOO~~|ns<br>~~GOO~~|
|TLP-PULSE-TX<br>~~eeGOO~~<br>~~a~~|Pulse Width of the LP Exclusive-OR Clock<br>~~GOO~~|First LP XOR Clock<br>Pulse after STOP<br>State or Last Pulse<br>before STOP State<br>~~GOO~~<br>~~eee~~|40<br>~~GOO~~<br>~~eee~~|—<br>~~GOO~~<br>~~eee~~|—<br>~~GOO~~<br>~~eee~~|ns<br>~~GOO~~<br>~~eee~~|
|||All Other Pulses<br>~~eee~~|20<br>~~eee~~|—<br>~~eee~~|—<br>~~eee~~|ns<br>~~eee~~|
|TLP-PER-TX<br>~~a~~<br>~~a GOO~~|Period of the LP Exclusive-OR Clock<br>~~GOO~~|—<br>~~eee~~<br>~~GOO~~|90<br>~~eee~~<br>~~GOO~~|—<br>~~eee~~<br>~~GOO~~|—<br>~~eee~~<br>~~GOO~~|ns<br>~~eee~~<br>~~GOO~~|
|CLOAD<br>~~a GD~~|Load Capacitance<br>~~GD~~|—<br>~~GD~~|0<br>~~GD~~|—<br>~~GD~~|70<br>~~GD~~|pF<br>~~GD~~|



**Table 4.28. Soft D-PHY Clock Signal Specification** 

© 2021-2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02102-1.7 

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**MachXO5-NX Family Data Sheet** 

**Table 4.29. Soft D-PHY Data-Clock Timing Specifications** 

|**Symbol**<br>~~PoPp~~|**Description**<br>~~Pp~~|**Conditions**<br>~~Fr~~|**Min**<br>~~Fr~~|**Typ**<br>~~Fr~~|**Max**<br>~~Fr~~|**Unit**<br>~~Fr~~|
|---|---|---|---|---|---|---|
|**Data-Clock Timing Specifications**<br>~~PoPp~~<br>~~Fr~~|||||||
|TSKEW[TX]<br>~~Pp~~|Data to Clock Skew<br>~~Pp~~|0.08 Gbps ≤ TSKEW[TX]<br>≤ 1.00 Gbps<br>~~Fr~~<br>~~ee~~|–0.15<br>~~Fr~~<br>~~eee~~|—<br>~~Fr~~<br>~~eee~~|0.15<br>~~Fr~~<br>~~eee~~|UIINST<br>~~Fr~~<br>~~eee~~|
|||1.00 Gbps < TSKEW[TX]<br>≤ 1.25 Gbps<br>~~Fr~~<br>~~ee~~|–0.20<br>~~Fr~~<br>~~eee~~|—<br>~~Fr~~<br>~~eee~~|0.20<br>~~Fr~~<br>~~eee~~|UIINST<br>~~Fr~~<br>~~eee~~|
|TSKEW[TLIS]<br>~~Pp~~<br>~~see~~|Data to Clock Skew<br>~~Pp~~<br>~~see~~|0.08 Gbps ≤ TSKEW[TLIS]<br>≤ 1.00 Gbps<br>~~Fr~~<br>~~ee ~~<br>~~see~~<br>~~ee~~|-0.20<br>~~Fr~~<br> ~~eee~~<br>~~see~~<br>~~eee~~|—<br>~~Fr~~<br>~~eee~~<br>~~see~~<br>~~eee~~|0.20<br>~~Fr~~<br>~~eee~~<br>~~see~~<br>~~eee~~|UIINST<br>~~Fr~~<br>~~eee~~<br>~~see~~<br>~~eee~~|
|||1.00 Gbps < TSKEW[TLIS]<br>≤ 1.25 Gbps<br>~~Fr~~<br>~~see~~<br>~~ee~~|-0.10<br>~~Fr~~<br>~~see~~<br>~~eee~~|—<br>~~Fr~~<br>~~see~~<br>~~eee~~|0.10<br>~~Fr~~<br>~~see~~<br>~~eee~~|UIINST<br>~~Fr~~<br>~~see~~<br>~~eee~~|
|TSETUP[RX]<br>~~See~~|Input Data Setup Before CLK<br>~~See~~|0.08 Gbps ≤ TSETUP[RX]<br>≤ 1.00 Gbps<br>~~ee ~~<br>~~See~~|0.15<br> ~~eee~~<br>~~See~~<br>~~tT~~|—<br>~~eee~~<br>~~See~~<br>~~tT|~~|—<br>~~eee~~<br>~~See~~<br>~~|~~|UI<br>~~eee~~<br>~~See~~|
|||1.00 Gbps < TSETUP[RX]<br>≤ 1.25 Gbps<br>~~See~~<br>~~ft~~|0.20<br>~~See~~<br>~~ft~~<br>~~tT~~|—<br>~~See~~<br>~~ft~~<br>~~tT|~~|—<br>~~See~~<br>~~ft~~<br>~~|~~|UI<br>~~See~~<br>~~ft~~|
|THOLD[RX]<br>~~PE~~|Input Data Hold After CLK<br>~~PE~~|0.08 Gbps ≤ THOLD[RX]<br>≤ 1.00 Gbps<br>~~PE~~|0.15<br>~~tT~~<br>~~PE~~|—<br>~~tT |~~<br>~~PE~~|—<br>~~|~~<br>~~PE~~|UI<br>~~PE~~|
|||1.00 Gbps < THOLD[RX]<br>≤ 1.25 Gbps<br>~~PE~~<br>~~a~~|0.20<br>~~PE~~<br>~~eee~~|—<br>~~PE~~<br>~~eee~~|—<br>~~PE~~<br>~~eee~~|UI<br>~~PE~~<br>~~eee~~|



## **4.13.8. Differential SSTL135D, SSTL15D (Output Only)** 

Differential SSTL is used for differential clock in DDR3/DDR3L memory interface. All differential SSTL outputs are implemented as a pair of complementary single-ended SSTL outputs. All allowable single-ended output classes (class I and class II) are supported. 

## **4.13.9. Differential HSUL12D (Output Only)** 

Differential HSUL is used for differential clock in LPDDR2/LPDDR3 memory interface. All differential HSUL outputs are implemented as a pair of complementary single-ended HSUL12 outputs. All allowable singleended drive strengths are supported. 

## **4.13.10. Differential LVCMOS25D, LVCMOS33D, LVTTL33D (Output Only)** 

Differential LVCMOS and LVTTL outputs are implemented as a pair of complementary single-ended outputs. All allowable single-ended output drive strengths are supported. 

## **4.13.11. Differential LVSTLD (Output Only)** 

Differential LVSTL is used for differential clock in LPDDR4 memory interface. All differential LVSTL outputs are implemented as a pair of complementary single-ended LVSTL outputs. All allowable single-ended drive strengths are supported. 

© 2021-2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02102-1.7 

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**MachXO5-NX Family Data Sheet** 

## **4.14. Maximum sysI/O Buffer Speed** 

Over recommended operating conditions. 

**Table 4.30. Maximum I/O Buffer Speed[1, 2, 3, 4, 7 ]** 

|**Buffer**<br>~~a~~|**Description**<br>~~De~~|**Banks**<br>~~De~~|**Max**<br>~~De~~|**Unit**<br>~~De~~|
|---|---|---|---|---|
|**Maximum sysI/O Input Frequency**<br>~~pe~~|||||
|**Single-Ended**|||||
|LVCMOS33<br>~~a~~|LVCMOS33, VCCIO= 3.3 V<br>~~GO~~|0, 1, 2, 6, 7<br>~~GO~~|200<br>~~GO~~|MHz<br>~~GO~~|
|LVTTL33<br>~~a~~|LVTTL33, VCCIO= 3.3 V<br>~~G~~|0, 1, 2, 6, 7<br>~~G~~|200<br>~~G~~|MHz<br>~~G~~|
|LVCMOS25<br>~~a~~|LVCMOS25, VCCIO= 2.5 V<br>~~GO~~|1, 2, 6, 7<br>~~GO~~|200<br>~~GO~~|MHz<br>~~GO~~|
|LVCMOS185<br>~~GO~~|LVCMOS18, VCCIO= 1.8 V<br>~~GO~~|1, 2, 6, 7<br>~~GO~~|200<br>~~GO~~|MHz<br>~~GO~~|
|LVCMOS18H<br>~~eG~~|LVCMOS18, VCCIO= 1.8 V<br>~~eG~~|3, 4, 5<br>~~eG~~|200<br>~~eG~~|MHz<br>~~eG~~|
|LVCMOS155<br>~~a~~|LVCMOS15, VCCIO= 1.5 V<br>~~G~~|1, 2, 6, 7<br>~~G~~|100<br>~~G~~|MHz<br>~~G~~|
|LVCMOS15H5<br>~~eG~~|LVCMOS15, VCCIO= 1.5 V<br>~~eG~~|3, 4, 5<br>~~eG~~|150<br>~~eG~~|MHz<br>~~eG~~|
|LVCMOS125<br>~~GO~~|LVCMOS12, VCCIO= 1.2 V<br>~~GO~~|1, 2, 6, 7<br>~~GO~~|50<br>~~GO~~|MHz<br>~~GO~~|
|LVCMOS12H5<br>~~a~~|LVCMOS12, VCCIO= 1.2 V<br>~~GO~~|3, 4, 5<br>~~GO~~|100<br>~~GO~~|MHz<br>~~GO~~|
|LVCMOS105<br>~~a~~<br>~~ee~~|LVCMOS 1.0, VCCIO= 1.2 V<br>~~D~~|1, 2, 6, 7<br>~~D~~|50|MHz|
|LVCMOS10H5<br>~~a~~<br>~~ee~~<br>~~ee~~|LVCMOS 1.0, VCCIO= 1.0 V<br>~~D~~<br>~~D~~|3, 4, 5<br>~~D~~<br>~~D~~|50|MHz|
|LVCMOS10R<br>~~ee~~<br>~~ee~~|LVCMOS 1.0, VCCIOindependent<br>~~D~~<br>~~D~~|3, 4, 5<br>~~D~~<br>~~D~~|50|MHz|
|SSTL15_I, SSTL15_II<br>~~ee~~<br>~~a~~|SSTL_15, VCCIO= 1.5 V<br>~~D~~|3, 4, 5<br>~~D~~|1066|Mbps|
|SSTL135_I, SSTL135_II<br>~~a~~|SSTL_135, VCCIO= 1.35 V<br>~~GO~~|3, 4, 5<br>~~GO~~|1066<br>~~GO~~|Mbps<br>~~GO~~|
|LVSTL_I, LVSTL_II<br>~~a~~|LVSTL, VCCIO = 1.1 V<br>~~GO~~|3, 4, 5<br>~~GO~~|1066<br>~~GO~~|Mbps<br>~~GO~~|
|HSUL12<br>~~a~~<br>~~ee~~|HSUL_12, VCCIO= 1.2 V<br>~~D~~|3, 4, 5<br>~~D~~|1066|Mbps|
|HSTL15<br>~~a~~<br>~~ee~~|HSTL15, VCCIO= 1.5 V<br>~~D~~|3, 4, 5<br>~~D~~|250|Mbps|
|MIPI D-PHY(LP Mode)<br>~~ee~~<br>~~a~~|MIPI, Low Power Mode, VCCIO= 1.2 V<br>~~D~~|3, 4, 5<br>~~D~~|10|Mbps|
|**Differential8 **<br>~~pt~~|||||
|LVDS<br>~~eG~~|LVDS, VCCIOindependent<br>~~eG~~|3, 4, 5<br>~~eG~~|1250<br>~~eG~~|Mbps<br>~~eG~~|
|subLVDS|subLVDS, VCCIOindependent<br>~~ee~~|3, 4, 5|1250|Mbps|
|SLVS<br>~~a~~|SLVS similar to MIPI HS, VCCIO<br>independent<br>~~a~~<br>~~ee~~|3, 4, 5<br>~~a~~|1250<br>~~a~~|Mbps<br>~~a~~|
|MIPI D-PHY(HS Mode)<br>~~a~~<br>~~OO~~|MIPI, High Speed Mode, VCCIO= 1.2 V<br>~~a~~<br>~~ee~~<br>~~OO~~|3, 4, 5<br>~~a~~<br>~~OO~~|1250<br>~~a~~<br>~~OO~~|Mbps<br>~~a~~<br>~~OO~~|
|SSTL15D<br>~~OO~~<br>~~a~~|Differential SSTL15, VCCIOindependent<br>~~OO~~|3, 4, 5<br>~~OO~~|1066<br>~~OO~~|Mbps<br>~~OO~~|
|SSTL135D<br>~~a~~|Differential SSTL135, VCCIOindependent<br>~~Ge~~|3, 4, 5<br>~~Ge~~|1066<br>~~Ge~~|Mbps<br>~~Ge~~|
|LVSTLD_I, LVSTLD_II<br>~~a~~|Differential LVSTL, VCCIOindependent<br>~~Ge~~|3, 4, 5<br>~~Ge~~|1066<br>~~Ge~~|Mbps<br>~~Ge~~|
|HSUL12D<br>~~a~~|Differential HSUL12, VCCIOindependent<br>~~eG~~|3, 4, 5<br>~~eG~~<br>~~D~~|1066<br>~~eG~~|Mbps<br>~~eG~~|
|HSTL15D<br>~~a~~<br>~~a~~|Differential HSTL15, VCCIOindependent<br>~~eG~~<br>~~a~~|3, 4, 5<br>~~eG~~<br>~~a~~<br>~~D~~|250<br>~~eG~~<br>~~a~~|Mbps<br>~~eG~~<br>~~a~~|
|**Maximum sysI/O Output Frequency**<br>~~a~~<br>~~D~~|||||
|**Single-Ended**|||||
|LVCMOS33(all drive strengths)<br>~~Ge~~|LVCMOS33, VCCIO= 3.3 V<br>~~Ge~~|0, 1, 2, 6, 7<br>~~Ge~~|200<br>~~Ge~~|MHz<br>~~Ge~~|
|LVCMOS33(RS50)<br>~~a~~|LVCMOS33, VCCIO= 3.3 V, RSERIES= 50 Ω<br>~~eG~~|0, 1, 2, 6, 7<br>~~eG~~|200<br>~~eG~~|MHz<br>~~eG~~|
|LVTTL33(all drive strengths)<br>~~a ~~<br>~~DO~~|LVTTL33, VCCIO= 3.3 V<br> ~~eG~~<br>~~DO~~|0, 1, 2, 6, 7<br>~~eG~~<br>~~DO~~|200<br>~~eG~~<br>~~DO~~|MHz<br>~~eG~~<br>~~DO~~|
|LVTTL33(RS50)<br>~~DO~~<br>~~a~~|LVTTL33, VCCIO= 3.3 V, RSERIES= 50 Ω<br>~~DO~~|0, 1, 2, 6, 7<br>~~DO~~|200<br>~~DO~~|MHz<br>~~DO~~|
|LVCMOS25(all drive strengths)<br>~~a~~<br>~~eG~~|LVCMOS25, VCCIO= 2.5 V<br>~~eG~~|1, 2, 6, 7<br>~~eG~~|200<br>~~eG~~|MHz<br>~~eG~~|
|LVCMOS25(RS50)<br>~~eG~~|LVCMOS25, VCCIO= 2.5 V, RSERIES= 50 Ω<br>~~eG~~|1, 2, 6, 7<br>~~eG~~|200<br>~~eG~~|MHz<br>~~eG~~|
|LVCMOS18(all drive strengths)<br>~~a~~|LVCMOS18, VCCIO= 1.8 V|1, 2, 6, 7|200|MHz|
|LVCMOS18(RS50)<br>~~a~~<br>~~a~~|LVCMOS18, VCCIO= 1.8 V, RSERIES= 50 Ω|1, 2, 6, 7|200|MHz|
|LVCMOS18H(all drive strengths)<br>~~a~~<br>~~a~~|LVCMOS18, VCCIO= 1.8 V|3, 4, 5|200|MHz|
|LVCMOS18H(RS50)<br>~~a~~<br>~~De~~|LVCMOS18, VCCIO= 1.8 V, RSERIES= 50 Ω<br>~~De~~|3, 4, 5<br>~~De~~|200<br>~~De~~|MHz<br>~~De~~|
|LVCMOS15(all drive strengths)<br>~~a~~|LVCMOS15, VCCIO= 1.5 V<br>~~D~~|1, 2, 6, 7<br>~~D~~|100<br>~~D~~|MHz<br>~~D~~|



© 2021-2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02102-1.7 

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**MachXO5-NX Family Data Sheet** 

|**Buffer**<br>~~a~~|**Description**<br>~~GO~~|**Banks**<br>~~GO~~|**Max**<br>~~GO~~|**Unit**<br>~~GO~~|
|---|---|---|---|---|
|LVCMOS15H(all drive strengths)<br>~~eG~~|LVCMOS15, VCCIO= 1.5 V<br>~~eG~~|3, 4, 5<br>~~eG~~|150<br>~~eG~~|MHz<br>~~eG~~|
|LVCMOS12(all drive strengths)<br>~~a~~|LVCMOS12, VCCIO= 1.2 V<br>~~G~~|1, 2, 6, 7<br>~~G~~|50<br>~~G~~|MHz<br>~~G~~|
|LVCMOS12H(all drive strengths)<br>~~a~~|LVCMOS12, VCCIO= 1.2 V<br>~~GO~~|3, 4, 5<br>~~GO~~|100<br>~~GO~~|MHz<br>~~GO~~|
|LVCMOS10H(all drive strengths)<br>~~GO~~|LVCMOS12, VCCIO= 1.2 V<br>~~GO~~|3, 4, 5<br>~~GO~~|50<br>~~GO~~|MHz<br>~~GO~~|
|SSTL15_I, SSTL15_II<br>~~GO~~|SSTL_15, VCCIO= 1.5 V<br>~~GO~~|3, 4, 5<br>~~GO~~|1066<br>~~GO~~|Mbps<br>~~GO~~|
|SSTL135_I, SSTL135_II<br>~~eG~~|SSTL_135, VCCIO= 1.35 V<br>~~eG~~|3, 4, 5<br>~~eG~~|1066<br>~~eG~~|Mbps<br>~~eG~~|
|LVSTL_I, LVSTL_II<br>~~a~~|LVSTL, VCCIO = 1.1 V<br>~~G~~|3, 4, 5<br>~~G~~|1066<br>~~G~~|Mbps<br>~~G~~|
|HSUL12(all drive strengths)<br>~~a~~|HSUL_12, VCCIO= 1.2 V<br>~~G~~|3, 4, 5<br>~~G~~|1066<br>~~G~~|Mbps<br>~~G~~|
|HSTL15<br>~~a~~|HSTL15, VCCIO= 1.5 V<br>~~GO~~|3, 4, 5<br>~~GO~~|250<br>~~GO~~|Mbps<br>~~GO~~|
|MIPI D-PHY(LP Mode)<br>~~eG~~|MIPI, Low Power Mode, VCCIO= 1.2 V<br>~~eG~~|3, 4, 5<br>~~eG~~|10<br>~~eG~~|Mbps<br>~~eG~~|
|**Differential8 **|||||
|LVDS<br>~~a~~|LVDS, VCCIO= 1.8 V<br>~~GO~~|5, 6<br>~~GO~~|1250<br>~~GO~~|Mbps<br>~~GO~~|
|LVDS25E6<br>~~eG~~|LVDS25, Emulated, VCCIO= 2.5 V<br>~~eG~~|1, 2, 6, 7<br>~~eG~~|400<br>~~eG~~|Mbps<br>~~eG~~|
|SubLVDSE6<br>~~GO~~|subLVDS, Emulated, VCCIO= 1.8 V<br>~~GO~~|1, 2, 6, 7<br>~~GO~~|400<br>~~GO~~|Mbps<br>~~GO~~|
|SubLVDSEH6<br>~~a~~|subLVDS, Emulated, VCCIO= 1.8 V<br>~~GO~~|3, 4, 5<br>~~GO~~|800<br>~~GO~~|Mbps<br>~~GO~~|
|SLVS<br>~~a~~|SLVS similar to MIPI, VCCIO= 1.2 V|3, 4, 5|1250|Mbps|
|MIPI D-PHY (HS Mode)<br>~~a~~<br>~~ee~~|MIPI, High Speed Mode, VCCIO= 1.2 V<br>~~D~~|3, 4, 5<br>~~D~~|1250|Mbps|
|SSTL15D<br>~~a~~<br>~~ee~~<br>~~ee~~|Differential SSTL15, VCCIO= 1.5 V<br>~~D~~<br>~~D~~|3, 4, 5<br>~~D~~<br>~~D~~|1066|Mbps|
|SSTL135D<br>~~ee~~<br>~~ee~~|Differential SSTL135, VCCIO= 1.35 V<br>~~D~~<br>~~D~~|3, 4, 5<br>~~D~~<br>~~D~~|1066|Mbps|
|LVSTLD<br>~~ee~~<br>~~a~~|Differential LVSTL, VCCIO= 1.1 V<br>~~D~~|3, 4, 5<br>~~D~~|1066|Mbps|
|HSUL12D<br>~~a~~|Differential HSUL12, VCCIO= 1.2 V<br>~~GO~~|3, 4, 5<br>~~GO~~|1066<br>~~GO~~|Mbps<br>~~GO~~|
|HSTL15D<br>~~a~~|Differential HSTL15, VCCIO= 1.5 V<br>~~ee~~|3, 4, 5<br>~~ee~~|250<br>~~ee~~|Mbps<br>~~ee~~|



**Notes** : 

1. Maximum I/O speed is the maximum switching rate of the I/O operating within the guidelines of the defining standard. The actual interface speed performance using the I/O also depends on other factors, such as internal and external timing. 

2. These numbers are characterized but not test on every device. 

3. Performance is specified in MHz, as defined in clock rate when the sysI/O is used as pin. For data rate performance, this can be converted to Mbps, which equals to 2 times the clock rate. 

4. LVCMOS and LVTTL are measured with load specified in Table 4.46. 

5. These LVCMOS inputs can be placed in different VCCIO voltage. Performance may vary. Please refer to Lattice Design Software 

6. These emulated outputs performance is based on externally properly terminated as described in LVDS25E (Output Only) and SubLVDSE/SubLVDSEH (Output Only). 

7. All speeds are measured with fast slew. 

8. For maximum differential I/O performance, only Differential I/O should be placed in the bottom I/O banks. If this is not possible, the following will impact on maximum performance: 

   - a. If Fast Slew Rate LVCMOS I/O are used, they should be limited to no more than nine I/O (adjacent), four I/O (same bank), 55 I/O (left/right banks) to keep degradation below 50%. 

   - b. If non-Differential I/O (SLOW SLEW) are placed on the bottom but not within the same bank as differential I/O, then the maximum Differential performance is degraded to 70% of original when 21 aggressors are toggling. 

   - c. If non-Differential I/O (SLOW SLEW) are placed within the same bank as Differential I/O then the maximum performance is degraded to 50% of original when 16 aggressor are toggling. 

   - d. No performance impact if MIPI LP and MIPI HS are in the same bank. 

   - e. If Differential RX/TX I/O are both placed within the same bank then the maximum performance is degraded to 90%. 

   - f. For DDR3/3L, LPDDR2/3/4 separate DQ/DQS groups from Address/Commands/CLK groups into separate banks. 

© 2021-2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02102-1.7 

124 

**MachXO5-NX Family Data Sheet** 

## **4.15. Typical Building Block Function Performance** 

These building block functions can be generated using Lattice Design Software Tool. Exact performance may vary with the device and the design software tool version. The design software tool uses internal parameters that have been characterized but are not tested on every device. 

**Table 4.31. Pin-to-Pin Performance** 

|**Function**|**Typ. @ VCC = 1.0 V**|**Unit**|
|---|---|---|
|16-bit Decoder(I/O configured with LVCMOS18, Top, Left and Right Banks)|5.5|ns|
|16-bit Decoder(I/O configured with HSTL15_I, Bottom Banks)|5.1|ns|
|16:1 Mux(I/O configured with LVCMOS18, Top, Left and Right Banks)|6|ns|
|16:1 Mux(I/O configured with HSTL15_I, Bottom Banks)|6.1|ns|



**Note** : These functions are generated using Lattice Radiant Design Software tool. Exact performance may vary with the device and the design software tool version. The design software tool uses internal parameters that have been characterized but are not tested on every device. 

**Table 4.32. Register-to-Register Performance[1, 3, 4]** 

|**Function**<br>~~a~~|**Typ. @ VCC = 1.0 V**<br>~~a~~<br>~~C~~|**Unit**<br>~~a~~<br>~~C~~|
|---|---|---|
|**Basic Functions**<br>~~C~~|||
|16-bit Adder<br>~~a~~|5002<br>~~a~~|MHz<br>~~a~~|
|32-bit Adder<br>~~a~~<br>~~pe~~|496<br>~~a~~|MHz<br>~~a~~|
|16-bit Counter<br>~~a~~<br>~~pe~~|402<br>~~a~~|MHz<br>~~a~~|
|32-bit Counter<br>~~pe~~<br>~~a~~|371<br>~~a~~|MHz<br>~~a~~|
|**Embedded Memory Functions**<br>~~pt~~|||
|512 × 36 Single Port RAM, with Output Register<br>~~a~~|5002<br>~~a~~|MHz<br>~~a~~|
|1024 × 18 True-Dual Port RAM usingsame clock, with EBR Output Registers<br>~~a~~<br>~~**p**e~~|5002<br>~~a~~|MHz<br>~~a~~|
|1024 × 18 True-Dual Port RAM usingasynchronous clocks, with EBR Output Registers<br>~~a~~<br>~~**p**e~~|5002<br>~~a~~|MHz<br>~~a~~|
|**Large Memory Functions**<br>~~**p**e~~<br>~~t~~|||
|32 k × 32 Single Port RAM, with Output Register<br>~~a~~|3752<br>~~a~~|MHz<br>~~a~~|
|32 k × 32 Single Port RAM with ECC, with Output Register<br>~~a~~|3502<br>~~a~~|MHz<br>~~a~~|
|32 k × 32 True-Dual Port RAM usingsame clock, with Output Registers<br>~~a~~|200<br>~~a~~|MHz<br>~~a~~|
|**Distributed Memory Functions**<br>~~a~~<br>~~PR~~|||
|16 × 4 Single Port RAM(One PFU)<br>~~PR~~<br>~~a~~|5002<br>~~PR~~<br>~~a~~|MHz<br>~~PR~~<br>~~a~~|
|16 × 2 Pseudo-Dual Port RAM(One PFU)<br>~~a~~|5002<br>~~a~~|MHz<br>~~a~~|
|16 × 4 Pseudo-Dual Port(Two PFUs)<br>~~a~~|5002<br>~~a~~|MHz<br>~~a~~|
|**DSP Functions**<br>~~pe~~|||
|9 × 9 Multiplier with Input Output Registers<br>~~pe~~|376|MHz|
|18 × 18 Multiplier with Input/Output Registers<br>~~pe~~<br>~~a~~|287<br>~~a~~|MHz<br>~~a~~|
|36 × 36 Multiplier with Input/Output Registers<br>~~a~~<br>~~a~~|200<br>~~a~~<br>~~a~~|MHz<br>~~a~~<br>~~a~~|
|MAC 18 × 18 with Input/Output Registers<br>~~a~~|203<br>~~a~~|MHz<br>~~a~~|
|MAC 18 × 18 with Input/Pipelined/Output Registers<br>~~a~~|287<br>~~a~~|MHz<br>~~a~~|
|MAC 36 × 36 with Input/Output Registers<br>~~a~~<br>~~pp~~|119<br>~~a~~<br>~~pp~~|MHz<br>~~a~~<br>~~pp~~|
|MAC 36 × 36 with Input/Pipelined/Output Registers<br>~~pp~~<br>~~a~~|155<br>~~pp~~<br>~~a~~|MHz<br>~~pp~~<br>~~a~~|



## **Notes** : 

1. The Clock port is configured with LVDS I/O type. Performance Grade: 9_High-Performance_1.0V. 

2. Limited by the Minimum Pulse Width of the component 

3. These functions are generated using Lattice Radiant Design Software tool. Exact performance may vary with the device and the design software tool version. The design software tool uses internal parameters that have been characterized but are not tested on every device. 

4. For the Pipelined designs, the number of pipeline stages used are 2. 

© 2021-2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02102-1.7 

125 

**MachXO5-NX Family Data Sheet** 

## **4.16. LMMI** 

Table 4.33 summarizes the performance of the LMMI interface with supported IPs. Additional timing requirement and constraint can be identified through the Lattice Radiance design tools. 

**Table 4.33. LMMI FMAX Summary** 

|**IP**|**FMAX (MHz)**|
|---|---|
|CDR0|73|
|CDR1|70|
|CRE|54|
|I2C|38|
|PLL_ULC|59|
|PLL_LRC|37|



## **4.17. Derating Timing Tables** 

Logic timing provided in the following sections of this data sheet and the Lattice Radiant design tools are worst case numbers in the operating range. Actual delays at nominal temperature and voltage for best case process, can be much better than the values given in the tables. The Lattice Radiant design tool can provide logic timing numbers at a particular temperature and voltage. 

© 2021-2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02102-1.7 

126 

**MachXO5-NX Family Data Sheet** 

## **4.18. External Switching Characteristics** 

Over recommended commercial operating conditions. 

## **Table 4.34. External Switching Characteristics (VCC = 1.0 V)** 

|**Parameter**|**Description**|–**9**|–**9**|–**8**|–**8**|–**7**|–**7**|**Unit**|
|---|---|---|---|---|---|---|---|---|
|||**Min**<br>~~a~~|**Max**|**Min**|**Max**|**Min**|**Max**||
|**Clocks**<br>~~RT~~|||||||||
|**Primary Clock**<br>~~RE~~|||||||||
|fMAX_PRI<br>~~a~~|Frequency for Primary<br>Clock|—|400|—|325.2|—|276|MHz|
|tW_PRI<br>~~a~~|Clock Pulse Width for<br>PrimaryClock<br>~~ee~~|1.125<br>~~ee~~|—<br>~~ee~~|1.325<br>~~ee~~|—<br>~~ee~~|1.594<br>~~ee~~|—<br>~~ee~~|ns<br>~~ee~~|
|tSKEW_PRI6<br>~~a~~|Primary Clock Skew Within<br>a Device<br>~~ee~~|—<br>~~ee~~|450<br>~~ee~~|—<br>~~ee~~|554<br>~~ee~~|—|653|ps|
|**Edge Clock**|||||||||
|fMAX_EDGE<br>~~a~~|Frequency for Edge Clock<br>Tree|—|800|—|650.4|—|551.7|MHz|
|tW_EDGE<br>~~a~~<br>~~a~~|Clock Pulse Width for Edge<br>Clock|0.513|—|0.65|—|0.743|—|ns|
|tSKEW_EDGE6<br>~~a~~<br>~~a~~|Edge Clock Skew Within a<br>Device<br>~~ee~~|—<br>~~ee~~|120<br>~~ee~~|—<br>~~ee~~|148<br>~~ee~~|—<br>~~ee~~|174<br>~~ee~~|ps<br>~~ee~~|
|**Generic SDR Input**<br>~~aee~~<br>~~Re~~|||||||||
|**General I/O Pin Parameters Using Dedicated Primary Clock Input without PLL**<br>~~Re~~|||||||||
|tCO(Except Bank0)<br>~~a~~|Clock to Output – PIO<br>Output Register|—|8.36|—|8.53|—|8.67|ns|
|tCO(Bank0)<br>~~a~~|Clock to Output – PIO<br>Output Register<br>~~a ee~~|—<br>~~ee~~|9.54<br>~~ee~~|—<br>~~ee~~|9.54<br>~~ee~~|—<br>~~ee~~|9.54<br>~~ee~~|ns<br>~~ee~~|
|tSU<br>~~a ee~~|Clock to Data Setup – PIO<br>Input Register<br>~~ee~~|0.00<br>~~ee~~|—<br>~~ee~~|0.00<br>~~ee~~|—<br>~~ee~~|0.00<br>~~ee~~|—<br>~~ee~~|ns<br>~~ee~~|
|tH(LTR)(Except<br>Bank0)<br>~~a~~|Clock to Data Hold – PIO<br>Input Register|3.73|—|3.83|—|3.93|—|ns|
|tH(LTR)(Bank0)<br>~~a ~~|Clock to Data Hold – PIO<br>Input Register<br> ~~a ~~|4.20<br> ~~ee~~|—<br>~~ee~~|4.20<br>~~ee~~|—<br>~~ee~~|4.20<br>~~ee~~|—<br>~~ee~~|ns<br>~~ee~~|
|tH(Bottom)|Clock to Data Hold – PIO<br>Input Register|4.65|—|4.75|—|4.84|—|ns|
|tSU_DEL|Clock to Data Setup – PIO<br>Input Register with Data<br>Input Delay|1.84|—|1.84|—|1.84|—|ns|
|tH_DEL(LTR)(Except<br>Bank0)|Clock to Data Hold – PIO<br>Input Register with Data<br>Input Delay|0.22|—|0.22|—|0.22|—|ns|
|tH_DEL(LTR)(Bank0)|Clock to Data Hold – PIO<br>Input Register with Data<br>Input Delay|0.31|—|0.31|—|0.31|—|ns|
|tH_DEL(Bottom)|Clock to Data Hold – PIO<br>Input Register with Data<br>Input Delay|1.77|—|1.77|—|1.77|—|ns|
|**General I/O Pin Parameters Using Dedicated Primary Clock Input with PLL**<br>~~|~~|||||||||
|tCOPLL<br>~~a~~|Clock to Output – PIO<br>Output Register<br>~~a~~|—<br>~~a~~|4.55<br>~~a~~|—<br>~~a~~|4.67<br>~~a~~|—<br>~~a~~|5.51<br>~~a~~|ns<br>~~a~~|
|tSUPLL(LTR except Bank0)<br>~~a~~|Clock to Data Setup – PIO<br>Input Register<br>~~a~~|1.33<br>~~a~~|—<br>~~a~~|1.33<br>~~a~~|—<br>~~a~~|1.33<br>~~a~~|—<br>~~a~~|ns<br>~~a~~|



© 2021-2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02102-1.7 

All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

127 

**MachXO5-NX Family Data Sheet** 

|**Parameter**<br>~~ee~~<br>~~a~~<br>~~a~~|**Description**<br>~~ee~~<br>~~**a**~~|–**9**<br>~~ee~~<br>~~a~~|–**9**<br>~~ee~~<br>~~a~~|–**8**<br>~~ee~~<br>~~ee ee~~|–**8**<br>~~ee~~<br>~~ee ee~~|–**7**<br>~~ee~~<br>~~ee ee~~|–**7**<br>~~ee~~<br>~~ee ee~~|**Unit**<br>~~ee~~<br>~~ee~~<br>~~ee~~|
|---|---|---|---|---|---|---|---|---|
|||**Min**<br>~~ee~~<br>~~a~~<br>~~**ee**~~|**Max**<br>~~ee~~<br>~~**ee**~~|**Min**<br>~~ee~~<br>~~ee ee~~<br>~~ee~~|**Max**<br>~~ee~~<br>~~ee~~<br>~~ee~~|**Min**<br>~~ee~~<br>~~ee ee~~<br>~~ee~~|**Max**<br>~~ee~~<br>~~ee~~<br>||
|tSUPLL(Bank0)<br>~~a ~~<br>~~a~~|Clock to Data Setup – PIO<br>Input Register<br> ~~**a**~~|2.10<br>~~a~~<br>~~**ee**~~|—<br>~~**ee**~~|2.10<br>~~ee ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~|2.10<br>~~ee ee~~<br>~~ee~~|—<br>~~ee~~<br>|ns<br>~~ee~~<br>~~ee~~|
|tSUPLL(Bottom)<br> <br>~~a~~|Clock to Data Setup – PIO<br>Input Register<br> ~~**a**~~|1.33<br>~~**ee**~~|—<br>~~**ee** ~~|1.33<br> ~~ee~~<br>~~eee~~|—<br>~~ee~~<br>~~eee~~|1.33<br>~~ee ~~<br>~~eee~~|—<br> <br>~~eee~~|ns<br> ~~ee~~<br>~~eee~~|
|tHPLL(LTR)<br>~~a ~~|Clock to Data Hold – PIO<br>Input Register<br> ~~a~~|0.98<br>~~ee~~|—<br>~~ee~~|1.21<br>~~eee~~|—<br>~~eee~~|1.42<br>~~eee~~|—<br>~~eee~~|ns<br>~~eee~~|
|tHPLL(Bottom)<br>~~ee~~|Clock to Data Hold – PIO<br>Input Register<br>~~ee~~|1.87<br>|—<br>~~eee~~|1.87<br>~~eee~~|—<br>~~eee~~|1.87<br>~~eee~~|—<br>~~eee~~|ns<br>~~eee~~|
|tSU_DELPLL(LTR except<br>Bank1)<br>~~ee~~|Clock to Data Setup – PIO<br>Input Register with Data<br>Input Delay<br>~~ee~~|4.74<br>|—<br>~~eee~~|4.74<br>~~eee~~|—<br>~~eee~~|4.74<br>~~eee~~|—<br>~~eee~~|ns<br>~~eee~~|
|tSU_DELPLL(Bank1)<br>~~ee~~|Clock to Data Setup – PIO<br>Input Register with Data<br>Input Delay<br>~~ee ~~|5.50<br>|—<br> ~~eee~~|5.50<br>~~eee~~|—<br>~~eee~~|5.50<br>~~eee~~|—<br>~~eee~~|ns<br>~~eee~~|
|tSU_DELPLL(Bottom)|Clock to Data Setup – PIO<br>Input Register with Data<br>Input Delay|4.74|—|4.74|—|4.74|—|ns|
|tH_DELPLL|Clock to Data Hold – PIO<br>Input Register with Data<br>Input Delay|0.00|—|0.00|—|0.00|—|ns|
|**Generic DDR Input/Output**<br>~~pT~~|||||||||
|**Generic DDRX1 Inputs/Outputs with Clock and Data Centered at Pin (GDDRX1_RX/TX.SCLK.Centered) using PCLK Clock Input**<br>**(Left, Top and Right Banks) –Figure 4.7 andFigure 4.9**<br>~~pT~~<br>~~ee~~|||||||||
|tSU_GDDR1<br>~~ee~~<br>~~rrr~~<br>~~po~~|Input Data Setup Before<br>CLK<br>~~ee~~<br>~~rrr~~|0.917<br>~~ee~~<br>~~rrr~~|—<br>~~ee~~<br>~~rrr~~|0.917<br>~~ee~~<br>~~rrr~~|—<br>~~ee~~<br>~~rrr~~|0.917<br>~~ee~~<br>~~rrr~~|—<br>~~ee~~<br>~~rrr~~|ns<br>~~ee~~<br>~~rrr~~|
|||0.275<br>~~rrr~~<br>~~a~~|—<br>~~rrr~~|0.275<br>~~rrr~~|—<br>~~rrr~~|0.275<br>~~rrr~~|—<br>~~rrr~~|UI<br>~~rrr~~|
|tHO_GDDR1<br>~~po~~<br>~~ee~~|Input Data Hold After CLK<br>~~ee~~|0.917<br>~~a~~<br>~~ee~~|—<br>~~ee~~|0.917<br>~~ee~~|—<br>~~ee~~|0.917<br>~~ee~~|—<br>~~eee~~|ns<br>~~eee~~|
|tDVB_GDDR1<br>~~po~~<br>~~ee~~<br>~~es~~|Output Data Valid After<br>CLK Output<br>~~ee~~<br>~~es~~|1.134<br>~~a~~<br>~~ee~~|—<br>~~ee~~|1.113<br>~~ee~~|—<br>~~ee~~|1.014<br>~~ee~~|—<br>~~eee~~|ns<br>~~eee~~|
|||–0.533<br>~~ee~~<br>~~a~~<br>~~es~~|—<br>~~ee~~|–0.554<br>~~ee~~|—<br>~~ee~~<br>~~eee~~|–0.653<br>~~ee~~<br>~~eee~~|—<br>~~eee~~<br>~~eee~~|ns + ½ UI<br>~~eee~~<br>~~eee~~|
|tDQVA_GDDR1<br>~~ee~~<br>~~es~~<br>~~po~~|Output Data Valid After<br>CLK Output<br>~~ee~~<br>~~es~~|1.217<br>~~ee~~<br>~~a~~<br>~~es~~|—<br>~~ee ~~|1.113<br> ~~ee ~~|—<br> ~~ee~~<br>~~eee~~|1.014<br>~~ee ~~<br>~~eee~~|—<br> ~~eee~~<br>~~eee~~|ns<br>~~eee~~<br>~~eee~~|
|||–0.45<br>~~es~~<br>~~a~~|—|–0.554|—<br>~~eee~~|–0.653<br>~~eee~~|—<br>~~eee~~|ns + ½ UI<br>~~eee~~|
|fDATA_GDDRX1<br>~~es~~<br>~~po~~<br>~~po~~|Input/Output Data Rate<br>~~es~~|—<br>~~es~~<br>~~a~~|300|—|300<br>~~eee~~|—<br>~~eee~~|300<br>~~eee~~|Mbps<br>~~eee~~|
|fMAX_GDDRX1<br>~~po~~<br>~~po~~|Frequencyof PCLK|—<br>~~a~~|150|—|150|—|150|MHz|
|½  UI<br>~~po~~<br>~~a~~|Half of Data Bit Time, or 90<br>degree<br>~~ee~~|1.667<br>~~ee~~|—|1.667|—|1.667|—|ns|
|Output TX to Input RX Marginper Edge<br>~~pO~~||0.3<br>~~pO~~|—<br>~~pO~~|0.197<br>~~pO~~|—<br>~~pO~~|0.097<br>~~pO~~|—<br>~~pO~~|ns<br>~~pO~~|
|**Generic DDRX1 Inputs/Outputs with Clock and Data Aligned at Pin (GDDRX1_RX/TX.SCLK.Aligned) using PCLK Clock Input (Left,**<br>**Top and Right Banks) –Figure 4.8 andFigure 4.10**<br>~~pO~~<br>~~_______~~|||||||||
|tDVA_GDDR1<br>~~__~~<br>~~Bf~~<br>~~Bf~~|Input Data Valid After CLK<br>~~_______~~<br>~~Bf ~~<br>~~Bf~~|—<br>~~_____~~<br>~~ep~~|–0.917<br>~~_____~~<br>~~ep~~|—<br>~~_____~~<br>~~ep~~|**–**0.917<br>~~_____~~<br>~~ep~~|—<br>~~_____~~<br>~~ep~~|–0.917<br>~~_____~~<br>~~ep~~|ns + ½ UI<br>~~_____~~<br>~~ep~~|
|||—<br>~~ep~~<br>~~a~~|0.75<br>~~ep~~|—<br>~~ep~~|0.75<br>~~ep~~|—<br>~~ep~~|0.75<br>~~ep~~|ns<br>~~ep~~|
|||—<br> ~~ep~~<br>~~a~~<br>~~a~~<br>~~ee~~|0.225<br>~~ep~~<br>~~ee~~|—<br>~~ep~~<br>~~ee~~|0.225<br>~~ep~~<br>~~ee~~|—<br>~~ep~~<br>~~ee~~|0.225<br>~~ep~~<br>~~ee~~|UI<br>~~ep~~<br>~~ee~~|
|tDVE_GDDR1<br>~~Bf~~|Input Data Hold After CLK<br>~~Bf~~|0.917<br>~~ee~~|—<br>~~ee~~|0.917<br>~~ee~~|—<br>~~ee~~|0.917<br>~~ee~~|—<br>~~ee~~|ns + ½ UI<br>~~ee~~|
|||2.583<br>~~ee~~<br>~~a~~|—<br>~~ee~~|2.583<br>~~ee~~|—<br>~~ee~~|2.583<br>~~ee~~|—<br>~~ee~~|ns<br>~~ee~~|
|||0.775<br>~~ee~~<br>~~a~~|—<br>~~ee~~|0.775<br>~~ee~~|—<br>~~ee~~|0.775<br>~~ee~~|—<br>~~ee~~|UI<br>~~ee~~|
|tDIA_GDDR1<br>~~Bf~~<br>~~a~~|Output Data Invalid After<br>CLK Output<br>~~Bf~~|—<br>~~ee~~<br>~~a~~|0.554<br>~~ee~~|—<br>~~ee~~|0.554<br>~~ee~~|—<br>~~ee~~|0.653<br>~~ee~~|ns<br>~~ee~~|
|tDIB_GDDR1<br>~~a~~<br>~~a~~<br>~~po~~|Output Data Invalid Before<br>CLK Output|—|0.45|—|0.554|—|0.653|ns|
|fDATA_GDDRX1<br>~~a~~<br>~~po~~<br>~~po~~|Input/Output Data Rate|—|300|—|300|—|300|Mbps|
|fMAX_GDDRX1<br>~~po~~<br>~~po~~|Frequencyfor PCLK|—|150|—|150|—|150|MHz|



© 2021-2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02102-1.7 

128 

**MachXO5-NX Family Data Sheet** 

|**Parameter**<br>~~a~~<br>~~a~~|**Description**<br>~~a~~<br>~~a~~|–**9**<br>~~a~~<br>~~ee~~|–**9**<br>~~a~~<br>~~ee~~|–**8**<br>~~a~~<br>~~eeee~~|–**8**<br>~~a~~<br>~~eeee~~|–**7**<br>~~a~~<br>~~ee ee~~<br>~~ee~~|–**7**<br>~~a~~<br>~~ee ee~~<br>~~ee~~|**Unit**<br>~~a~~<br>~~ee~~<br>~~ee~~|
|---|---|---|---|---|---|---|---|---|
|||**Min**<br>~~a~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|**Max**<br>~~a~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|**Min**<br>~~a~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|**Max**<br>~~a~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|**Min**<br>~~a~~<br>~~ee ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|**Max**<br>~~a~~<br>~~ee~~<br>~~ee~~||
|½  UI<br>~~a ~~<br>~~pO~~|Half of Data Bit Time, or 90<br>degree<br> ~~a~~<br>~~pO~~|1.667<br>~~ee~~<br>~~ee~~|—<br>~~ee ~~<br>~~ee~~|1.667<br> ~~ee ~~<br>~~ee~~|—<br> ~~ee~~<br>~~ee~~|1.667<br>~~ee ee~~<br>~~ee~~<br>~~ee~~|—<br>~~ee~~|ns<br>~~ee~~<br>~~ee~~|
|Output TX to Input RX Marginper Edge<br> ~~a~~<br>~~pO~~||0.300<br>~~ee~~|—<br>~~ee~~|0.197<br>~~ee~~|—<br>~~ee~~|0.097<br>~~ee~~|—|ns<br>~~ee~~|
|**Generic DDRX1 Inputs/Outputs with Clock and Data Centered at Pin (GDDRX1_RX/TX.SCLK.Centered) using PCLK Clock Input**<br>**(Bottom Banks) –Figure 4.7 and Figure 4.9**<br>~~pO~~<br>~~ee~~<br>~~ceeeeeeee~~<br>~~a~~|||||||||
|tSU_GDDR1<br>~~ce~~|Input Data Setup Before<br>CLK<br>~~ce~~|0.917<br>~~ce~~<br>~~a~~|—<br>~~ce~~<br>~~ce~~|0.917<br>~~ce~~<br>~~ee~~|—<br>~~ce~~<br>~~ee~~|0.917<br>~~ce~~<br>~~ee~~|—<br>~~ce~~<br>~~eee~~|ns<br>~~ce~~<br>~~eee~~|
|||0.275<br>~~ce~~<br>~~a~~|—<br>~~ce~~<br>~~ce~~|0.275<br>~~ce~~<br>~~ee~~|—<br>~~ce~~<br>~~ee~~|0.275<br>~~ce~~<br>~~ee~~|—<br>~~ce~~<br>~~eee~~|UI<br>~~ce~~<br>~~eee~~|
|tHO_GDDR1<br>~~po~~|Input Data Hold After CLK<br>~~po~~|0.917<br>~~a~~<br>~~po~~|—<br>~~ce ~~<br>~~po~~|0.917<br> ~~ee ~~<br>~~po~~|—<br> ~~ee~~<br>~~po~~|0.917<br>~~ee ~~<br>~~po~~|—<br> ~~eee~~<br>~~po~~|ns<br>~~eee~~<br>~~po~~|
|fDATA_IN_GDDRX1<br>~~po~~|Input Data Rate<br>~~po~~|—<br>~~po~~|300<br>~~po~~|—<br>~~po~~|300<br>~~po~~|—<br>~~po~~|300<br>~~po~~|Mbps<br>~~po~~|
|tDVB_GDDR1<br>~~po~~<br>~~ee~~|Output Data Valid After<br>CLK Output<br>~~po~~<br>~~ee~~|0.670<br>~~po~~<br>~~ee~~|—<br>~~po~~<br>~~ee~~|0.631<br>~~po~~<br>~~ee~~|—<br>~~po~~<br>~~ee~~|0.744<br>~~po~~<br>~~ee~~|—<br>~~po~~<br>~~ee~~|ns<br>~~po~~<br>~~ee~~|
|||–0.330<br>~~ee~~<br>~~a~~|—<br>~~ee~~|–0.369<br>~~ee~~|—<br>~~ee~~|–0.435<br>~~ee~~|—<br>~~ee~~|ns + ½ UI<br>~~ee~~|
|tDQVA_GDDR1<br>~~rrr~~<br>~~pO~~|Output Data Valid After<br>CLK Output<br>~~rrr~~|0.700<br>~~rrr~~|—<br>~~rrr~~|0.631<br>~~rrr~~|—<br>~~rrr~~|0.744<br>~~rrr~~|—<br>~~rrr~~|ns<br>~~rrr~~|
|||–0.300<br>~~rrr~~<br>~~a~~|—<br>~~rrr~~|–0.369<br>~~rrr~~|—<br>~~rrr~~|–0.435<br>~~rrr~~|—<br>~~rrr~~|ns + ½ UI<br>~~rrr~~|
|fDATA_GDDRX1<br>~~pO~~|Input/Output Data Rate|—<br>~~a~~|500|—|500|—|424|Mbps|
|fMAX_GDDRX1<br>~~pO~~<br>~~a~~|Frequencyof PCLK<br>~~Gs~~|—<br>~~a~~<br>~~Gs~~|250<br>~~Gs~~|—<br>~~GO~~|250<br>~~GO~~|—<br>~~GO~~|212<br>~~GO~~|MHz|
|½  UI<br>~~a~~<br>~~a~~|Half of Data Bit Time, or 90<br>degree<br>~~Gs~~<br>|1.000<br>~~Gs~~<br>|—<br>~~Gs~~<br>|1<br>~~GO~~<br>|—<br>~~GO~~<br>|1.179<br>~~GO~~<br>|—<br>~~GO~~<br>|ns<br>|
|Output TX to Input RX Marginper Edge<br>~~aGO~~||0.150<br>~~GO~~|—<br>~~GO~~|0.081<br>~~GO~~|—<br>~~GO~~|0.095<br>~~GO~~|—<br>~~GO~~|ns<br>~~GO~~|
|**Generic DDRX1 Inputs/Outputs with Clock and Data Aligned at Pin (GDDRX1_RX/TX.SCLK.Aligned) using PCLK Clock Input**<br>**(Bottom Banks) –Figure 4.8 andFigure 4.10**<br>~~GO~~<br>~~_______~~|||||||||
|tDVA_GDDR1<br>~~__~~<br>~~Bf~~|Input Data Valid After CLK<br>~~_______~~<br>~~Bf~~<br>~~po~~|—<br>~~_____~~<br>~~po~~|–0.917<br>~~_____~~|—<br>~~_____~~|–0.917<br>~~_____~~|—<br>~~_____~~|–0.917<br>~~_____~~|ns + ½ UI<br>~~_____~~|
|||—<br>~~po~~|0.75|—|0.75|—|0.75|ns|
|||—<br>~~po~~<br>~~a~~|0.225|—|0.225|—|0.225|UI|
|tDVE_GDDR1<br>~~Sf~~<br>~~a~~|Input Data Hold After CLK<br>~~Sf~~<br>~~en~~|0.917<br>~~**a**~~|—|0.917|—|0.917|—|ns + ½ UI|
|||2.583<br>~~**a**~~|—|2.583|—|2.583|—|ns|
|||0.775<br>~~**a**~~<br>~~GG~~|—<br>~~GG~~|0.775<br>~~GG~~|—|0.775<br>~~GO~~|—<br>~~GO~~|UI|
|fDATA_IN_GDDRX1<br>~~Sf~~<br>~~a~~|Input Data Rate<br>~~Sf~~<br>~~en~~|—<br>~~**a**~~<br>~~GG~~|300<br>~~GG~~|—<br>~~GG~~|300|—<br>~~GO~~|300<br>~~GO~~|Mbps|
|tDIA_GDDR1<br>~~a~~<br>~~a~~|Output Data Invalid After<br>CLK Output<br>~~en~~|—<br>~~GG~~|0.3<br>~~GG~~|—<br>~~GG~~|0.369|—<br>~~GO~~|0.435<br>~~GO~~|ns|
|tDIB_GDDR1<br>~~a~~|Output Data Invalid Before<br>CLK Output<br>|—<br>|0.3<br>|—<br>|0.369<br>|—<br>|0.435<br>|ns<br>|
|fDATA_GDDRX1<br>~~pO~~<br>~~pO~~|Input/Output Data Rate<br>~~pO~~|—<br>~~pO~~|500<br>~~pO~~|—<br>~~pO~~|500<br>~~pO~~|—<br>~~pO~~|424<br>~~pO~~|Mbps<br>~~pO~~|
|fMAX_GDDRX1<br>~~pO~~|Frequencyfor PCLK|—|250|—|250|—|212|MHz|
|½  UI<br>~~pO~~<br>~~a~~|Half of Data Bit Time, or 90<br>degree<br>~~ee~~|1<br>~~ee~~|—<br>~~ee~~|1<br>~~ee~~|—<br>~~ee~~|1.179<br>~~ee~~|—<br>~~ee~~|ns<br>~~ee~~|
|Output TX to Input RX Marginper Edge<br>~~pO~~<br>~~ee~~||0.15<br>~~pO~~<br>~~ee~~|—<br>~~pO~~<br>~~_______~~|0.081<br>~~pO~~<br>~~_______~~|—<br>~~pO~~<br>~~_______~~|0.095<br>~~pO~~<br>~~_______~~|—<br>~~pO~~<br>~~_______~~|ns<br>~~pO~~<br>~~_______~~|
|**Generic DDRX2 Inputs/Outputs with Clock and Data Centered at Pin (GDDRX2_RX/TX.ECLK.Centered) using PCLK Clock Input –**<br>**Figure 4.7 and Figure 4.9**<br>~~pO~~<br>~~ee_______~~<br>~~_———————EeEEE~~|||||||||
|tSU_GDDRX2<br>~~ee~~<br>~~_———————EeEEE~~|Data Setup before CLK<br>Input<br>~~ee~~<br>~~_———————EeEEE~~<br>~~po~~|0.209<br>~~ee ~~<br>~~_———————EeEEE~~<br>~~po~~|—<br> ~~_______~~<br>~~_———————EeEEE~~<br>~~po~~|0.209<br>~~_______~~<br>~~_———————EeEEE~~|—<br>~~_______~~<br>~~_———————EeEEE~~|0.206<br>~~_______~~<br>~~_———————EeEEE~~|—<br>~~_______~~<br>~~_———————EeEEE~~|ns<br>~~_______~~<br>~~_———————EeEEE~~|
|||0.209<br>~~_———————EeEEE~~<br>~~po~~|—<br>~~_———————EeEEE~~<br>~~po~~|0.209<br>~~_———————EeEEE~~|—<br>~~_———————EeEEE~~|0.175<br>~~_———————EeEEE~~|—<br>~~_———————EeEEE~~|UI<br>~~_———————EeEEE~~|
|tHO_GDDRX2<br>~~_———————EeEEE~~<br>~~pO~~|Data Hold after CLK Input<br>~~_———————EeEEE~~<br>~~po~~<br>~~pO~~|0.213<br>~~_———————EeEEE~~<br>~~po~~<br>~~pO~~<br>~~a~~|—<br>~~_———————EeEEE~~<br>~~po~~<br>~~pO~~|0.213<br>~~_———————EeEEE~~<br>~~pO~~|—<br>~~_———————EeEEE~~<br>~~pO~~<br>~~ee~~|0.206<br>~~_———————EeEEE~~<br>~~pO~~<br>~~ee~~|—<br>~~_———————EeEEE~~<br>~~pO~~<br>~~eee~~|ns<br>~~_———————EeEEE~~<br>~~pO~~<br>~~eee~~|
|tDVB_GDDRX2<br>~~a ee~~|Output Data Valid Before<br>CLK Output<br>~~ee~~|0.360<br>~~ee~~<br>~~a~~|—<br>~~ee~~|0.352<br>~~ee~~|—<br>~~ee~~<br>~~ee~~|0.415<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~eee~~|ns<br>~~ee~~<br>~~eee~~|
|||–0.140<br>~~ee~~<br>~~a~~|—<br>~~ee~~|–0.148<br>~~ee~~|—<br>~~ee~~<br>~~ee~~|–0.174<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~eee~~|ns + ½ UI<br>~~ee~~<br>~~eee~~|
|tDQVA_GDDRX2<br>~~a ee~~<br>~~a~~|Output Data Valid After<br>CLK Output<br>~~ee~~<br>~~a~~<br>~~po~~|0.38<br>~~ee~~<br>~~a~~<br>~~a~~<br>~~po~~|—<br>~~ee~~<br>~~a~~|0.352<br>~~ee~~<br>~~a~~|—<br>~~ee~~<br>~~ee ~~<br>~~a~~|0.415<br>~~ee~~<br> ~~ee ~~<br>~~a~~|—<br>~~ee~~<br> ~~eee~~|ns<br>~~ee~~<br>~~eee~~|
|||–0.12<br>~~a~~<br>~~po~~|—<br>~~a~~|–0.148<br>~~a~~|—<br>~~a~~|–0.174<br>~~a~~|—|ns + ½ UI|
|fDATA_GDDRX2<br>~~a~~<br>~~pO~~|Input/Output Data Rate<br>~~a~~<br>~~po~~<br>~~pO~~|—<br>~~a~~<br>~~po~~<br>~~pO~~|1000<br>~~a~~<br>~~pO~~|—<br>~~a~~<br>~~pO~~|1000<br>~~a~~<br>~~pO~~|—<br>~~a~~<br>~~pO~~|848<br>~~pO~~|Mbps<br>~~pO~~|
|fMAX_GDDRX2<br>~~pO~~|Frequencyfor ECLK<br>~~pO~~|—<br>~~pO~~|500<br>~~pO~~|—<br>~~pO~~|500<br>~~pO~~|—<br>~~pO~~|424<br>~~pO~~|MHz<br>~~pO~~|
|½  UI<br>~~a~~|Half of Data Bit Time, or 90<br>degree<br>~~ee~~|0.5<br>~~ee~~|—<br>~~ee~~|0.5|—|0.589|—|ns|



© 2021-2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02102-1.7 

129 

|**Parameter**<br>~~a~~<br>~~pO~~|**Description**<br>~~a~~<br>|–**9**<br>~~a~~<br>~~ee~~|–**9**<br>~~a~~<br>~~ee~~|–**8**<br>~~a~~<br>~~eeee~~|–**8**<br>~~a~~<br>~~eeee~~|–**7**<br>~~a~~<br>~~ee ee~~<br>~~ee~~|–**7**<br>~~a~~<br>~~ee ee~~<br>~~ee~~|**Unit**<br>~~a~~<br>~~ee~~|
|---|---|---|---|---|---|---|---|---|
|||**Min**<br>~~a~~<br>~~ee~~<br>~~ee~~|**Max**<br>~~a~~<br>~~ee~~<br>~~ee~~|**Min**<br>~~a~~<br>~~ee~~<br>~~ee~~|**Max**<br>~~a~~<br>~~ee~~<br>~~ee~~|**Min**<br>~~a~~<br>~~ee ee~~<br>~~ee~~<br>~~ee~~|**Max**<br>~~a~~<br>~~ee~~<br>~~ee~~||
|fPCLK<br>~~pOa~~|PCLK frequency<br>~~a~~|—<br>~~ee~~<br>~~GG~~|250<br>~~ee ~~<br>~~GG~~|—<br> ~~ee ~~<br>~~GG~~|250<br> ~~ee~~|—<br>~~ee ee~~<br>~~ee~~<br>~~GO~~|212.1<br>~~ee~~<br>~~GO~~|MHz<br>~~ee~~|
|Output TX to Input RX Marginper Edge<br>~~pOa~~||0.23<br>~~GG~~|—<br>~~GG~~|0.202<br>~~GG~~|—|0.239<br>~~ee~~<br>~~GO~~|—<br>~~GO~~|ns|
|**Generic DDRX2 Inputs/Outputs with Clock and Data Aligned at Pin (GDDRX2_RX/TX.ECLK.Aligned) using PCLK Clock Input –**<br>**Figure 4.8 andFigure 4.10**<br>~~a~~<br>~~GG~~<br>~~GO~~<br>~~ee~~|||||||||
|tDVA_GDDRX2<br>~~Bf~~<br>~~pf~~|Input Data Valid After CLK<br>~~Bf~~<br>~~pf~~|—<br>~~a~~|–0.275|—|–0.275|—|–0.324|ns + ½ UI|
|||—<br>~~a~~|0.225|—|0.225|—|0.265|ns|
|||—<br>~~aa~~|0.225|—|0.225|—|0.225|UI|
|tDVE_GDDRX2<br>~~pf~~|Input Data Hold After CLK<br>~~pf~~|0.275<br>~~a~~|—|0.275|—|0.324|—|ns + ½ UI|
|||0.775<br>~~a~~<br>~~a~~|—|0.775|—|0.914|—|ns|
|||0.775<br>~~a~~<br>~~a~~|—|0.775|—|0.775|—|UI|
|tDIA_GDDRX2<br>~~pf~~<br>~~a~~|Output Data Invalid After<br>CLK Output<br>~~pf~~|—<br>~~a~~|0.12|—|0.148|—|0.174|ns|
|tDIB_GDDRX2<br>~~a~~|Output Data Invalid Before<br>CLK Output<br>|—<br>|0.12<br>|—<br>|0.148<br>|—<br>|0.174<br>|ns<br>|
|fDATA_GDDRX2<br>~~po~~|Input/Output Data Rate<br>~~po~~|—<br>~~po~~|1000<br>~~po~~|—<br>~~po~~|1000<br>~~po~~|—<br>~~po~~|848<br>~~po~~|Mbps<br>~~po~~|
|fMAX_GDDRX2<br>~~pO~~|Frequencyfor ECLK<br>~~pO~~|—<br>~~pO~~|500<br>~~pO~~|—<br>~~pO~~|500<br>~~pO~~|—<br>~~pO~~|424<br>~~pO~~|MHz<br>~~pO~~|
|½  UI<br>~~a~~<br>~~pO~~|Half of Data Bit Time, or 90<br>degree<br>|0.5<br>|—<br>|0.5<br>|—<br>|0.589<br>|—<br>|ns<br>|
|fPCLK<br>~~pO~~|PCLK frequency<br>|—<br>|250<br>|—<br>|250<br>|—<br>|212.1<br>|MHz<br>|
|Output TX to Input RX Marginper Edge<br>~~pOGO~~||0.105<br>~~GO~~|—<br>~~GO~~|0.077<br>~~GO~~|—<br>~~GO~~|0.091<br>~~GO~~|—<br>~~GO~~|ns<br>~~GO~~|
|**Generic DDRX4 Inputs/Outputs with Clock and Data Centered at Pin (GDDRX4_RX/TX.ECLK.Centered) using PCLK Clock Input –**<br>**Figure 4.7 andFigure 4.9**<br>~~GO~~<br>~~_______~~|||||||||
|tSU_GDDRX4<br>~~_______~~<br>~~rrr~~|Input Data Set-Up Before<br>CLK<br>~~_______~~<br>~~rrr~~|0.210<br>~~_______~~<br>~~rrr~~|—<br>~~_______~~<br>~~rrr~~|0.210<br>~~_______~~<br>~~rrr~~|—<br>~~_______~~<br>~~rrr~~|0.244<br>~~_______~~<br>~~rrr~~|—<br>~~_______~~<br>~~rrr~~|ns<br>~~_______~~<br>~~rrr~~|
|||0.315<br>~~rrr~~<br>~~a~~|—<br>~~rrr~~|0.252<br>~~rrr~~|—<br>~~rrr~~|0.252<br>~~rrr~~|—<br>~~rrr~~|UI<br>~~rrr~~|
|tHO_GDDRX4<br>~~po~~<br>~~ff~~|Input Data Hold After CLK<br>~~po~~<br>~~ff~~|0.254<br>~~po~~<br>~~J~~|—<br>~~po~~<br>~~J~~|0.254<br>~~po~~|—<br>~~po~~<br>~~—t—~~|0.244<br>~~po~~<br>~~—t—~~|—<br>~~po~~<br>~~-——~~|ns<br>~~po~~<br>~~-——~~|
|tDVB_GDDRX4<br>~~ff~~|Output Data Valid Before<br>CLK Output<br>~~ff~~|0.193<br>~~J~~|—<br>~~J~~|0.269|—<br>~~—t—~~|0.309<br>~~—t—~~|—<br>~~-——~~|ns<br>~~-——~~|
|||–0.140<br>~~J~~<br>~~a~~<br>~~a~~|—<br>~~J~~<br>~~ce~~|–0.148<br>~~ee~~|—<br>~~—t—~~<br>~~ee~~|–0.174<br>~~—t—~~<br>~~ee~~|—<br>~~-——~~<br>~~eee~~|ns + ½  UI<br>~~-——~~<br>~~eee~~|
|tDQVA_GDDRX4<br>~~ff~~<br>~~ce~~|Output Data Valid After<br>CLK Output<br>~~ff~~<br>~~ce~~|0.213<br>~~J~~<br>~~a~~<br>~~ce~~<br>~~a~~|—<br>~~J~~<br>~~ce~~<br>~~ce~~|0.269<br>~~ce~~<br>~~ee~~|—<br>~~—t—~~<br>~~ce~~<br>~~ee~~|0.309<br>~~—t—~~<br>~~ce~~<br>~~ee~~|—<br>~~-——~~<br>~~ce~~<br>~~eee~~|ns<br>~~-——~~<br>~~ce~~<br>~~eee~~|
|||–0.12<br>~~ce~~<br>~~a~~|—<br>~~ce~~<br>~~ce~~|–0.148<br>~~ce~~<br>~~ee~~|—<br>~~ce~~<br>~~ee~~|–0.174<br>~~ce~~<br>~~ee~~|—<br>~~ce~~<br>~~eee~~|ns + ½  UI<br>~~ce~~<br>~~eee~~|
|fDATA_GDDRX4<br>~~pO~~<br>~~pO~~|Input/Output Data Rate<br>~~pO~~|—<br>~~a~~<br>~~pO~~|1500<br>~~ce~~<br>~~pO~~|—<br>~~ee ~~<br>~~pO~~|1200<br> ~~ee~~<br>~~pO~~|—<br>~~ee ~~<br>~~pO~~|1034<br> ~~eee~~<br>~~pO~~|Mbps<br>~~eee~~<br>~~pO~~|
|fMAX_GDDRX4<br>~~pO~~|Frequencyfor ECLK|—|750|—|600|—|517|MHz|
|½  UI<br>~~pO~~<br>~~a~~<br>~~po~~|Half of Data Bit Time, or 90<br>degree|0.333|—|0.417|—|0.483|—|ns|
|fPCLK<br>~~a~~<br>~~po~~<br>~~ee~~|PCLK Frequency<br>~~ee~~|—<br>~~ee~~|187.5<br>|—<br>|150<br>|—<br>~~DO~~<br>|129.3<br>~~DO~~<br>|MHz<br>|
|Output TX to Input RX Marginper Edge<br>~~po~~<br>~~Ge~~<br>~~ee~~<br>~~Bf~~||0.08<br>~~Ge~~<br>~~ee~~|—<br>~~Ge~~<br>~~_______~~|0.102<br>~~Ge~~<br>~~_______~~|—<br>~~Ge~~<br>~~_______~~|0.116<br>~~Ge~~<br>~~DO~~<br>~~_______~~|—<br>~~Ge~~<br>~~DO~~<br>~~_______~~|ns<br>~~Ge~~<br>~~_______~~|
|**Generic DDRX4 Inputs/Outputs with Clock and Data Aligned at Pin (GDDRX4_RX/TX.ECLK.Aligned) using PCLK Clock Input, Left**<br>**and Right sides Only –Figure 4.8 and Figure 4.10**<br>~~Ge~~<br>~~DO~~<br>~~ee_______~~<br>~~Bf~~|||||||||
|tDVA_GDDRX4<br>~~ee~~<br>~~Bf~~|Input Data Valid After CLK<br>~~ee~~<br>~~Bf~~|—<br>~~ee ~~|–0.216<br> ~~_______~~|—<br>~~_______~~|–0.229<br>~~_______~~|—<br>~~DO~~<br>~~_______~~|–0.266<br>~~DO~~<br>~~_______~~|ns + ½ UI<br>~~_______~~|
|||—<br> <br>~~a~~|0.117<br> ~~_______~~|—<br>~~_______~~|0.188<br>~~_______~~|—<br>~~_______~~|0.218<br>~~_______~~|ns<br>~~_______~~|
|||—<br> <br>~~a~~|0.176<br> ~~_______~~|—<br>~~_______~~|0.225<br>~~_______~~|—<br>~~_______~~|0.225<br>~~_______~~|UI<br>~~_______~~|
|tDVE_GDDRX4<br>~~Bf~~|Input Data Hold After CLK<br>~~Bf ~~|0.227<br>~~ee~~|—<br>~~ee~~|0.229<br>~~ee~~|—<br>~~ee~~|0.266<br>~~ee~~|—<br>~~ee~~|ns + ½ UI<br>~~ee~~|
|||0.560<br>~~ee~~<br>~~a~~|—<br>~~ee~~|0.646<br>~~ee~~|—<br>~~ee~~|0.749<br>~~ee~~|—<br>~~ee~~|ns<br>~~ee~~|
|||0.840<br> ~~ee~~<br>~~a~~<br>~~a~~|—<br>~~ee~~|0.775<br>~~ee~~|—<br>~~ee~~|0.775<br>~~ee~~|—<br>~~ee~~|UI<br>~~ee~~|
|tDIA_GDDRX4<br>~~a~~|Output Data Invalid After<br>CLK Output|—|0.12|—|0.148|—|0.17|ns|
|tDIB_GDDRX4<br>~~a~~<br>~~a~~|Output Data Invalid Before<br>CLK Output<br>|—<br>|0.12<br>|—<br>|0.148<br>|—<br>|0.174<br>|ns<br>|
|fDATA_GDDRX4<br>~~apO~~|Input/Output Data Rate<br>~~pO~~|—<br>~~pO~~|1500<br>~~pO~~|—<br>~~pO~~|1200<br>~~pO~~|—<br>~~pO~~|1034<br>~~pO~~|Mbps<br>~~pO~~|
|fMAX_GDDRX4<br>~~po~~|Frequencyfor ECLK<br>~~po~~|—<br>~~po~~|750<br>~~po~~|—<br>~~po~~|600<br>~~po~~|—<br>~~po~~|517<br>~~po~~|MHz<br>~~po~~|



© 2021-2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02102-1.7 

130 

|**Parameter**<br>~~a~~<br>~~a~~<br>~~pO~~|**Description**<br>~~a~~<br>~~a~~<br>|–**9**<br>~~a~~<br>~~ee~~|–**9**<br>~~a~~<br>~~ee~~|–**8**<br>~~a~~<br>~~eeee~~|–**8**<br>~~a~~<br>~~eeee~~|–**7**<br>~~a~~<br>~~ee ee~~<br>~~ee~~|–**7**<br>~~a~~<br>~~ee ee~~<br>~~ee~~|**Unit**<br>~~a~~<br>~~ee~~<br>~~ee~~<br>|
|---|---|---|---|---|---|---|---|---|
|||**Min**<br>~~a~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>|**Max**<br>~~a~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>|**Min**<br>~~a~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>|**Max**<br>~~a~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>|**Min**<br>~~a~~<br>~~ee ee~~<br>~~ee~~<br>~~ee~~<br>|**Max**<br>~~a~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>||
|½  UI<br>~~a ~~<br>~~pO~~|Half of Data Bit Time, or 90<br>degree<br> ~~a~~<br>|0.333<br>~~ee~~<br>~~ee~~<br>|—<br>~~ee ~~<br>~~ee~~<br>|0.417<br> ~~ee ~~<br>~~ee~~<br>|—<br> ~~ee~~<br>~~ee~~<br>|0.483<br>~~ee ee~~<br>~~ee~~<br>|—<br>~~ee~~<br>~~ee~~<br>|ns<br>~~ee~~<br>~~ee~~<br>|
|fPCLK<br> <br>~~pO~~|PCLK frequency<br> ~~a~~<br>|—<br>~~ee~~<br>|187.5<br>~~ee~~<br>|—<br>~~ee~~<br>|150<br>~~ee~~<br>|—<br>|129.3<br>~~ee~~<br>|MHz<br>~~ee~~<br>|
|Output TX to Input RX Marginper Edge<br> ~~a~~<br>~~pOpO~~||0.03<br>~~ee ~~<br>~~pO~~|—<br> ~~ee~~<br>~~pO~~|0.04<br>~~ee~~<br>~~pO~~|—<br>~~ee~~<br>~~pO~~|0.044<br>~~pO~~|—<br>~~ee~~<br>~~pO~~|ns<br>~~ee~~<br>~~pO~~|
|**Generic DDRX5 Inputs/Outputs with Clock and Data Centered at Pin (GDDRX5_RX/TX.ECLK.Centered) using PCLK Clock Input –**<br>**Figure 4.7 and Figure 4.9**<br>~~a~~<br>~~eeee~~<br>~~eee~~|||||||||
|tSU_GDDRX5<br>~~a~~|Input Data Set-Up Before<br>CLK<br>~~ee~~|0.231<br>~~ee~~|—<br>~~ee~~|0.231|—|0.224<br>~~eee~~|—<br>~~eee~~|ns<br>~~eee~~|
|||0.289<br>~~ee~~<br>~~a~~|—<br>~~ee~~|0.277|—|0.224<br>~~eee~~|—<br>~~eee~~|UI<br>~~eee~~|
|tHO_GDDRX5<br>~~a~~<br>~~po~~|Input Data Hold After CLK<br>~~ee ~~<br>~~po~~|0.229<br> ~~ee~~<br>~~po~~|—<br>~~ee~~<br>~~po~~|0.229<br>~~po~~|—<br>~~po~~|0.224<br>~~eee~~<br>~~po~~|—<br>~~eee~~<br>~~po~~|ns<br>~~eee~~<br>~~po~~|
|tWINDOW_GDDRX5C<br>~~po~~<br>~~es~~|Input Data Valid Window<br>~~po~~<br>~~es~~|—<br>~~po~~<br>~~es~~|—<br>~~po~~<br>~~ee~~|—<br>~~po~~<br>~~ee~~|—<br>~~po~~|—<br>~~po~~<br>~~eee~~|—<br>~~po~~<br>~~eee~~|ns<br>~~po~~<br>~~eee~~|
|tDVB_GDDRX5<br>~~es~~|Output Data Valid Before<br>CLK Output<br>~~es~~|0.249<br>~~es~~|—<br>~~ee~~|0.269<br>~~ee~~|—|0.326<br>~~eee~~|—<br>~~eee~~|ns<br>~~eee~~|
|||–0.151<br>~~es~~<br>~~a~~|—<br>~~ee~~|–0.148<br>~~ee~~|—|–0.174<br>~~eee~~|—<br>~~eee~~|Ns + ½ UI<br>~~eee~~|
|tDQVA_GDDRX5<br>~~es~~<br>~~fp~~<br>~~a~~|Output Data Valid After<br>CLK Output<br>~~es~~<br>~~fp~~|0.249<br>~~es ~~<br>~~fp~~|—<br> ~~ee ~~<br>~~fp~~|0.269<br> ~~ee~~<br>~~fp~~|—<br>~~fp~~|0.326<br>~~eee~~<br>~~fp~~|—<br>~~eee~~|ns<br>~~eee~~|
|||–0.151<br>~~fp~~<br>~~pT~~|—<br>~~fp~~<br>~~pT~~|–0.148<br>~~fp~~|—<br>~~fp~~<br>~~GO~~|–0.174<br>~~fp~~<br>~~GO~~|—<br>~~GO~~|Ns + ½ UI|
|fDATA_GDDRX5<br>~~fp~~<br>~~a~~<br>~~a~~|Input/Output Data Rate<br>~~fp~~<br>~~GG~~|—<br>~~fp~~<br>~~pT~~<br>~~GG~~|1250<br>~~fp~~<br>~~pT~~<br>~~GG~~|—<br>~~fp~~<br>~~GG~~|1200<br>~~fp~~<br>~~GG~~<br>~~GO~~|—<br>~~fp~~<br>~~GG~~<br>~~GO~~|1000<br>~~GG~~<br>~~GO~~|Mbps<br>~~GG~~|
|fMAX_GDDRX5<br>~~a ~~<br>~~a~~|Frequencyfor ECLK<br> ~~GG~~<br>~~Gs~~|—<br>~~GG~~<br>~~Gs~~|625<br>~~GG~~<br>~~Gs~~|—<br>~~GG~~<br>~~GO~~|600<br>~~GG~~<br>~~GO~~<br>~~GO~~|—<br>~~GG~~<br>~~GO~~<br>~~GO~~|500<br>~~GG~~<br>~~GO~~<br>~~GO~~|MHz<br>~~GG~~|
|½  UI<br>~~a~~<br>~~a~~<br>~~**p**o~~|Half of Data Bit Time, or 90<br>degree<br>~~Gs~~|0.4<br>~~Gs~~|—<br>~~Gs~~|0.417<br>~~GO~~|—<br>~~GO~~<br>~~GO~~|0.5<br>~~GO~~<br>~~GO~~|—<br>~~GO~~<br>~~GO~~|ns|
|fPCLK<br>~~a~~<br>~~**p**o~~|PCLK frequency|—|125|—|120|—|100|MHz|
|Output TX to Input RX Marginper Edge<br>~~**p**o~~||0.12|—<br>~~O~~|0.102<br>~~O~~|—<br>~~O~~|0.126<br>~~O~~|—<br>~~O~~|ns<br>~~O~~|
|**Generic DDRX5 Inputs/Outputs with Clock and Data Aligned at Pin (GDDRX5_RX/TX.ECLK.Aligned) using PCLK Clock Input –**<br>**Figure 4.8 andFigure 4.10**|||||||||
|tDVA_GDDRX5|Input Data Valid After CLK|—<br>~~a~~|–0.220|—|–0.229|—|–0.275|ns + ½ UI|
|||—<br>~~a~~|0.18|—|0.188|—|0.225|ns|
|||—<br>~~a~~<br>~~a~~|0.225|—|0.225|—|0.225|UI|
|tDVE_GDDRX5<br>~~pO~~|Input Data Hold After CLK|0.22<br>~~a~~<br>~~a~~|—|0.229|—|0.275|—|ns + ½ UI|
|||0.62<br>~~a~~<br>~~a~~|—|0.646|—|0.775|—|ns|
|||0.775<br>~~a~~|—|0.775|—|0.775|—|UI|
|tWINDOW_GDDRX5A<br>~~pO~~|Input Data Valid Window|—|—|—|—|—|—|ns|
|tDIA_GDDRX5<br>~~pO~~<br>~~a~~|Output Data Invalid After<br>CLK Output|—|0.12|—|0.148|—|0.174|ns|
|tDIB_GDDRX5<br>~~a~~<br>~~a~~<br>~~a~~|Output Data Invalid Before<br>CLK Output<br>|—<br>|0.12<br>|—<br>|0.148<br>~~GO~~<br>|—<br>~~GO~~<br>|0.174<br>~~GO~~<br>|ns<br>|
|fDATA_GDDRX5<br>~~a~~<br>~~a~~<br>~~a~~<br>~~a~~|Input/Output Data Rate<br>~~Ge~~<br>|—<br>~~Ge~~<br>|1250<br>~~Ge~~<br>|—<br>~~Ge~~<br>|1200<br>~~Ge~~<br>~~GO~~<br><br>~~GO~~|—<br>~~Ge~~<br>~~GO~~<br><br>~~GO~~|1000<br>~~Ge~~<br>~~GO~~<br><br>~~GO~~|Mbps<br>~~Ge~~<br>|
|fMAX_GDDRX5<br>~~a~~<br>~~a~~<br>~~a~~|Frequencyfor ECLK<br>~~Ge~~<br>~~Ge~~|—<br>~~Ge~~<br>~~Ge~~|625<br>~~Ge~~<br>~~Ge~~|—<br>~~Ge~~<br>~~Ge~~|600<br>~~Ge~~<br>~~GO~~<br>~~Ge~~<br>~~GO~~|—<br>~~Ge~~<br>~~GO~~<br>~~Ge~~<br>~~GO~~|500<br>~~Ge~~<br>~~GO~~<br>~~Ge~~<br>~~GO~~|MHz<br>~~Ge~~<br>~~Ge~~|
|½  UI<br>~~a ~~<br>~~a~~<br>~~**p**O~~|Half of Data Bit Time, or 90<br>degree<br> ~~Ge~~|0.4<br>~~Ge~~|—<br>~~Ge~~|0.417<br>~~Ge~~|—<br>~~GO~~<br>~~Ge~~<br>~~GO~~|0.5<br>~~GO~~<br>~~Ge~~<br>~~GO~~|—<br>~~GO~~<br>~~Ge~~<br>~~GO~~|ns<br>~~Ge~~|
|fPCLK<br>~~a~~<br>~~**p**O~~|PCLK frequency|—|125|—|120<br>~~GO~~|—<br>~~GO~~|100<br>~~GO~~|MHz|
|Output TX to Input RX Marginper Edge<br>~~**p**O~~||0.06|—<br>~~o~~|0.04<br>~~o~~|—<br>~~o~~|0.051<br>~~o~~|—<br>~~o~~|ns<br>~~o~~|
|**Soft D-PHY DDRX4 Inputs/Outputs with Clock and Data Centered at Pin, using PCLK Clock Input**|||||||||
|tSU_GDDRX4_MP<br>~~a~~|Input Data Set-Up Before<br>CLK<br>~~a~~|0.133<br>~~a~~|—<br>~~a~~|0.167<br>~~a~~|—<br>~~a~~|0.193<br>~~a~~|—<br>~~a~~|ns<br>~~a~~|
|||0.2<br>~~a~~<br>~~a~~|—<br>~~a~~|0.2<br>~~a~~|—<br>~~a~~|0.2<br>~~a~~<br>~~GO~~|—<br>~~a~~<br>~~GO~~|UI<br>~~a~~|
|tHO_GDDRX4_MP<br>~~a~~<br>~~GG~~|Input Data Hold After CLK<br>~~a~~<br>~~GG~~|0.133<br>~~a~~<br>~~a~~<br>~~GG~~|—<br>~~a~~<br>~~GG~~|0.167<br>~~a~~<br>~~GG~~|—<br>~~a~~<br>~~GG~~|0.193<br>~~a~~<br>~~GG~~<br>~~GO~~|—<br>~~a~~<br>~~GG~~<br>~~GO~~|ns<br>~~a~~<br>~~GG~~|
|tDVB_GDDRX4_MP<br>~~GG~~<br>~~Pp~~|Output Data Valid Before<br>CLK Output<br>~~GG~~<br>~~Pp~~|0.133<br>~~GG~~<br>~~Pp~~|—<br>~~GG~~<br>~~Pp~~|0.167<br>~~GG~~<br>~~Pp~~|—<br>~~GG~~<br>~~Pp~~|0.193<br>~~GG~~<br>~~GO~~<br>~~Pp~~|—<br>~~GG~~<br>~~GO~~<br>~~Pp~~|ns<br>~~GG~~|
|||0.2<br>~~Pp~~<br>~~a~~|—<br>~~Pp~~|0.2<br>~~Pp~~|—<br>~~Pp~~|0.2<br>~~Pp~~|—<br>~~Pp~~|UI|
|tDQVA_GDDRX4_MP<br>~~fe~~|Output Data Valid After<br>CLK Output<br>~~fe~~|0.133<br>~~fe~~|—<br>~~fe~~|0.167<br>~~fe~~|—<br>~~fe~~|0.193<br>~~fe~~|—<br>~~fe~~|ns<br>~~fe~~|
|||0.2<br>~~fe~~<br>~~a~~|—<br>~~fe~~|0.2<br>~~fe~~|—<br>~~fe~~|0.2<br>~~fe~~|—<br>~~fe~~|UI<br>~~fe~~|



© 2021-2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. 

All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02102-1.7 

131 

|**Parameter**<br>~~a~~<br>~~a~~|**Description**<br>~~a~~<br>~~a~~|–**9**<br>~~a~~<br>~~ee~~|–**9**<br>~~a~~<br>~~ee~~|–**8**<br>~~a~~<br>~~eeee~~|–**8**<br>~~a~~<br>~~eeee~~|–**7**<br>~~a~~<br>~~ee ee~~|–**7**<br>~~a~~<br>~~ee ee~~|**Unit**<br>~~a~~<br>~~ee~~<br>~~ee~~|
|---|---|---|---|---|---|---|---|---|
|||**Min**<br>~~a~~<br>~~ee~~<br>~~a~~<br>~~ee~~|**Max**<br>~~a~~<br>~~ee~~<br>~~a~~<br>~~ee~~|**Min**<br>~~a~~<br>~~ee~~<br>~~a~~<br>~~ee~~|**Max**<br>~~a~~<br>~~ee~~<br>~~a~~<br>~~ee~~|**Min**<br>~~a~~<br>~~ee ee~~<br>~~a~~|**Max**<br>~~a~~<br>~~ee~~<br>~~a~~<br>~~ee~~||
|fDATA_GDDRX4_MP<br>~~a~~<br>~~a~~|Input Data Bit Rate for<br>MIPI PHY<br>~~a~~<br>~~a~~|—<br>~~ee~~<br>~~ee~~<br>~~ee~~|1500<br>~~ee ~~<br>~~ee~~<br>~~ee~~|—<br> ~~ee ~~<br>~~ee~~<br>~~ee~~|1200<br> ~~ee~~<br>~~ee~~<br>~~ee~~|—<br>~~ee ee~~<br>~~ee~~|1034<br>~~ee~~<br>~~ee~~|Mbps<br>~~ee~~<br>~~ee~~<br>~~ee~~|
|½  UI<br>~~a ~~<br>~~a~~|Half of Data Bit Time, or 90<br>degree<br> ~~a~~<br>~~a~~|0.333<br>~~ee ~~<br>~~ee~~|—<br> ~~ee~~<br>~~ee~~|0.417<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~|0.483<br>~~ee~~|—<br>~~ee~~|ns<br>~~ee~~<br>~~ee~~|
|fPCLK<br>~~a ~~<br>~~po~~|PCLK frequency<br> ~~a~~<br>~~po~~|—<br>~~ee~~<br>~~po~~|187.5<br>~~ee~~<br>~~po~~|—<br>~~ee~~<br>~~po~~|150<br>~~ee~~<br>~~po~~|—<br>~~ee~~<br>~~po~~|129.3<br>~~po~~|MHz<br>~~ee~~<br>~~po~~|
|Output TX to Input RX Marginper Edge<br>~~po~~||0.067<br>~~po~~|—<br>~~po~~|0.083<br>~~po~~|—<br>~~po~~|0.097<br>~~po~~|—<br>~~po~~|ns<br>~~po~~|
|**Video DDRX71 Inputs/Outputs with Clock and Data Aligned at Pin (GDDRX71_RX.ECLK) using PLL Clock Input –Figure 4.12 and**<br>**Figure 4.13**<br>~~ee~~<br>~~eseeee~~|||||||||
|tRPBi_DVA<br>~~es~~<br>~~Bf~~|Input Valid Bit "i" switch<br>from CLK Rising Edge ("i" =<br>0 to 6, 0 aligns with CLK)<br>~~ee~~<br>~~f~~|—<br>~~ee~~|0.264<br>~~ee~~|—<br>~~ee~~|0.264<br>~~ee~~|—|0.3|UI|
|||—<br>~~ee~~<br>~~|~~<br>|–0.250<br>~~ee~~<br>~~|~~<br>|—<br>~~ee~~<br>~~|~~<br>|–0.250<br>~~ee~~<br>~~|~~<br>|—<br>~~|~~<br>|–0.249<br>~~}~~<br>|ns+(½ +i)*UI<br>|
|tRPBi_DVE<br>~~es ~~<br>~~Bfrr~~|Input Hold Bit "i" switch<br>from CLK Rising Edge ("i" =<br>0 to 6, 0 aligns with CLK)<br> ~~ee~~<br>~~frr~~|0.761<br>~~ee ~~<br>~~|~~<br>|—<br> ~~ee~~<br>~~|~~<br>|0.761<br>~~ee~~<br>~~|~~<br>|—<br>~~ee~~<br>~~|~~<br>|0.7<br>~~|~~<br>|—<br>~~}~~<br>|UI<br>|
|||0.276<br>~~|~~<br>~~rr~~|—<br>~~|~~<br>~~rr~~|0.276<br>~~|~~<br>~~rr~~|—<br>~~|~~<br>~~rr~~|0.249<br>~~|~~<br>~~rr~~|—<br>~~}~~<br>~~rr~~|ns+(½ +i)*UI<br>~~rr~~|
|tTPBi_DOV<br>~~Bfrr~~|Data Output Valid Bit "i"<br>switch from CLK Rising<br>Edge ("i" = 0 to 6, 0 aligns<br>with CLK)<br>~~frr~~|—<br>~~|~~<br>~~rr~~|0.159<br>~~|~~<br>~~rr~~|—<br>~~|~~<br>~~rr~~|0.159<br>~~|~~<br>~~rr~~|—<br>~~|~~<br>~~rr~~|0.187<br>~~}~~<br>~~rr~~|ns+i*UI<br>~~rr~~|
|tTPBi_DOI<br>~~rr~~|Data Output Invalid Bit "i"<br>switch from CLK Rising<br>Edge ("i" = 0 to 6, 0 aligns<br>with CLK)<br>~~rr~~|0.159<br>~~rr~~|—<br>~~rr~~|0.159<br>~~rr~~|—<br>~~rr~~|0.187<br>~~rr~~|—<br>~~rr~~|ns+(i+ 1)*UI<br>~~rr~~|
|tTPBi_skew_UI|TX skew in UI|—|0.15|—|0.15|—|0.15|UI|
|tB<br>~~a~~|Serial Data Bit Time, = 1UI<br>~~a~~|1.058<br>~~a~~|—<br>~~a~~|1.058<br>~~a~~|—<br>~~a~~|1.247<br>~~a~~|—<br>~~a~~|ns<br>~~a~~|
|fDATA_TX71<br>~~a~~<br>~~i~~|DDR71 Serial Data Rate<br>~~a~~<br>~~i~~|—<br>~~a~~<br>~~i~~|945<br>~~a~~<br>~~i~~|—<br>~~a~~<br>~~i~~|945<br>~~a~~<br>~~i~~|—<br>~~a~~<br>~~i~~|802<br>~~a~~<br>~~i~~|Mbps<br>~~a~~<br>~~i~~|
|fMAX_TX71<br>~~a~~|DDR71 ECLK Frequency<br>~~a~~|—<br>~~a~~|473<br>~~a~~|—<br>~~a~~|473<br>~~a~~|—<br>~~a~~|401<br>~~a~~|MHz<br>~~a~~|
|fCLKIN<br>~~a~~<br>~~ee~~|7:1 Clock(PCLK)Frequency<br>~~a~~<br>~~ee~~|—<br>~~a~~|135<br>~~a~~|—<br>~~a~~|135<br>~~a~~|—<br>~~a~~|114.5<br>~~a~~|MHz<br>~~a~~|
|Output TX to Input RX Marginper Edge<br>~~ee~~||0.159|—|0.159|—|0.187|—|ns|
|**Memory Interface**<br>~~ee~~<br>~~a~~|||||||||
|**DDR3/DDR3L READ(DQ Input Data are Aligned to DQS) –Figure 4.8**<br>~~a~~<br>~~a~~|||||||||
|tDVBDQ_DDR3<br>tDVBDQ_DDR3L<br>~~a~~|Data Input Valid before<br>DQS Input<br>~~a~~|—<br>~~a~~|–0.235<br>~~a~~|—<br>~~a~~|–0.235<br>~~a~~|—<br>~~a~~|–0.277<br>~~a~~|ns + ½ UI<br>~~a~~|
|tDVADQ_DDR3<br>tDVADQ_DDR3L<br>~~a~~<br>~~a~~|Data Input Valid after DQS<br>Input<br>~~a~~<br>~~a~~|0.235<br>~~a~~<br>~~a~~|—<br>~~a~~<br>~~a~~|0.235<br>~~a~~<br>~~a~~|—<br>~~a~~<br>~~a~~|0.277<br>~~a~~<br>~~a~~|—<br>~~a~~<br>~~a~~|ns + ½ UI<br>~~a~~<br>~~a~~|
|fDATA_DDR3<br>fDATA_DDR3L<br>~~a~~<br>~~a~~|DDR Memory Data Rate<br>~~a~~<br>~~a~~|—<br>~~a~~<br>~~a~~|1066<br>~~a~~<br>~~a~~|—<br>~~a~~<br>~~a~~|1066<br>~~a~~<br>~~a~~|—<br>~~a~~<br>~~a~~|904<br>~~a~~<br>~~a~~|Mb/s<br>~~a~~<br>~~a~~|
|fMAX_ECLK_DDR3<br>fMAX_ECLK_DDR3L<br>~~a~~<br>~~a~~|DDR Memory ECLK<br>Frequency<br>~~a~~<br>~~a~~|—<br>~~a~~<br>~~a~~|533<br>~~a~~<br>~~a~~|—<br>~~a~~<br>~~a~~|533<br>~~a~~<br>~~a~~|—<br>~~a~~<br>~~a~~|452<br>~~a~~<br>~~a~~|MHz<br>~~a~~<br>~~a~~|
|fMAX_SCLK_DDR3<br>fMAX_SCLK_DDR3L<br>~~a~~<br>~~a~~|DDR Memory SCLK<br>Frequency<br>~~a~~<br>~~a~~<br>~~ee~~|—<br>~~a~~<br>~~a~~<br>~~ee~~|133.3<br>~~a~~<br>~~a~~<br>~~ee~~|—<br>~~a~~<br>~~a~~<br>~~ee~~|133.3<br>~~a~~<br>~~a~~<br>~~ee~~|—<br>~~a~~<br>~~a~~<br>~~ee~~|113<br>~~a~~<br>~~a~~<br>~~ee~~|MHz<br>~~a~~<br>~~a~~<br>~~ee~~|
|**DDR3/DDR3L WRITE(DQ Output Data are Centered to DQS) –Figure 4.11**<br>~~a~~<br>~~ee~~<br>~~a~~|||||||||
|tDQVBS_DDR3<br>tDQVBS_DDR3L<br>~~a~~|Data Output Valid before<br>DQS Output<br>~~a~~<br>~~ee~~|—<br>~~a~~<br>~~ee~~|–0.235<br>~~a~~<br>~~ee~~|—<br>~~a~~<br>~~ee~~|–0.235<br>~~a~~<br>~~ee~~|—<br>~~a~~<br>~~ee~~|–0.277<br>~~a~~<br>~~ee~~|ns + ½ UI<br>~~a~~<br>~~ee~~|
|tDQVAS_DDR3<br>tDQVAS_DDR3L<br>~~a~~|Data Output Valid after<br>DQS Output|0.235|—|0.235|—|0.277|—|ns + ½ UI|
|fDATA_DDR3<br>fDATA_DDR3L<br>~~a~~<br>~~a~~|DDR Memory Data Rate|—|1066|—|1066|—|904|Mb/s|
|fMAX_ECLK_DDR3<br>fMAX_ECLK_DDR3L<br>~~a~~|DDR Memory ECLK<br>Frequency<br>~~ee~~|—<br>~~ee~~|533|—|533|—|452|MHz|
|fMAX_SCLK_DDR3<br>fMAX_SCLK_DDR3L<br>~~a~~|DDR Memory SCLK<br>Frequency<br>~~ee~~|—<br>~~ee~~|133.3<br>~~ee~~|—|133.3|—|113|MHz|



© 2021-2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02102-1.7 

132 

**MachXO5-NX Family Data Sheet** 

## **Notes** : 

1. Commercial timing numbers are shown. Industrial numbers are typically slower and can be extracted from the Lattice Radiant software. 

2. General I/O timing numbers are based on LVCMOS 1.8, 8 mA, Fast Slew Rate, 0 pf load for all IOs except the bank0. For bank0, the number are based on LVCMOS 3.3, 12 mA, Fast Slew Rate, 0 pf load. Generic DDR timing are numbers based on LVDS I/O. DDR3 timing numbers are based on SSTL15. 

3. Uses LVDS I/O standard for measurements. 

4. Maximum clock frequencies are tested under best case conditions. System performance may vary upon the user environment. 

5. All numbers are generated with the Lattice Radiant software. 

6. This clock skew is not the internal clock network skew. Nexus family devices have very low internal clock network skew that can be approximated to 0 ps. These tskew values measured externally at system level includes additional skew added by the I/O, wire bonding and package ball. 

**==> picture [297 x 128] intentionally omitted <==**

**----- Start of picture text -----**<br>
Rx CLK (in)<br>rn rs<br>Rx DATA (in)<br>tSU tSU<br>tHD tHD<br>**----- End of picture text -----**<br>


**Figure 4.7. Receiver RX.CLK.Centered Waveforms** 

**==> picture [421 x 154] intentionally omitted <==**

**----- Start of picture text -----**<br>
½ UI<br>½ UI<br>1 UI<br>Rx CLK (in)<br>or DQS input<br>Rx DATA (in)<br>or DQS input<br>Ano n nn y on<br>tDVA/tDVADQ<br>tDVA/tDVADQ<br>tDVE/tDVEDQ<br>tDVE/tDVEDQ<br>**----- End of picture text -----**<br>


**Figure 4.8. Receiver RX.CLK.Aligned and DDR Memory Input Waveforms** 

© 2021-2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02102-1.7 

133 

**MachXO5-NX Family Data Sheet** 

**==> picture [342 x 137] intentionally omitted <==**

**----- Start of picture text -----**<br>
1/2 UI 1/2 UI 1/2 UI 1/2 UI<br>Tx CLK (out)<br>or DQS Output<br>Tx DATA (out)<br>or DQ Output<br>" a<br>tDVB/tDQVBS tDVB/tDQVBS<br>tDVA/tDQVA tDVA/tDQVAS<br>**----- End of picture text -----**<br>


**Figure 4.9. Transmit TX.CLK.Centered and DDR Memory Output Waveforms** 

**==> picture [309 x 126] intentionally omitted <==**

**----- Start of picture text -----**<br>
1 UI<br>Tx CLK (out)<br>Tx DATA (out)<br>| a |<br>tDIB tDIB<br>tDIA tDIA<br>**----- End of picture text -----**<br>


**Figure 4.10. Transmit TX.CLK.Aligned Waveforms** 

© 2021-2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02102-1.7 

134 

**MachXO5-NX Family Data Sheet** 

## **Receiver – Shown for one LVDS Channel** 

|0!<br>~~ia~~|0x<br>0x<br>0x<br>0x<br>0x<br>0x<br>0x<br>~~XOX 7X 2X 3K 4X SK XOX~~<br>0!<br>1!<br>~~ia~~<br>**1**<br>**1**<br>**1**<br>**1**<br>1<br>!<br>1<br>1|Bit #<br>10 – 1<br>11 – 2<br>12 – 3<br>13 – 4<br>14 – 5<br>15 – 6<br>16 – 7<br>~~XOX 1X 2K SK 4X SK OX~~<br>1!<br>2)<br>~~ia~~<br>**1**<br>**1**<br>**1**<br>**1**<br>**1**<br>**1**<br>1<br>!<br>1<br>1<br>1|Bit #<br>20 – 8<br>21 – 9<br>22 – 10<br>23 – 11<br>24 – 12<br>25 – 13<br>26 – 14<br>~~OX ON 1X 2K 3X 4X 5K SX~~<br>2)<br>3}<br>**1**<br>**1**<br>**1**<br>**1**<br>**1**<br>1<br>1<br>!<br>1<br>1|Bit #<br>30 – 15<br>31 – 16<br>32 – 17<br>33 – 18<br>34 – 19<br>35 – 20<br>36 – 21<br>~~SX OX 1X 2K SX 4X SX 8X~~<br>3}<br>4)<br>**1**<br>**1**<br>**1**<br>**1**<br>**1**<br>1<br>!<br>1<br>1<br>1|Bit #<br>40 – 22<br>41 – 23<br>42 – 24<br>43 – 25<br>44 – 26<br>45 – 27<br>46 – 28<br>~~8X 0)~~<br>4)<br>**1**<br>**1**<br>**1**<br>1<br>1<br>1|
|---|---|---|---|---|---|
|**For each Channel:**<br>**7-bit Output Words**<br>~~ia~~||||||



## **Transmitter – Shown for one LVDS Channel** 

|~~CONT~~<br>0}|Bit #<br>10 – 8<br>11 – 9<br>12 – 10<br>13 – 11<br>14 – 12<br>15 – 13<br>16 – 14<br>~~CONT ZX SX AEE ~~<br>i}<br>1<br>~~**1**~~<br>~~1~~<br>**1**<br>~~1~~<br>!<br>!<br>1<br>1<br>!<br>!<br>1<br>1|Bit #<br>20 – 15<br>21 – 16<br>22 – 17<br>23 – 18<br>24 – 19<br>25 – 20<br>26 – 21<br> ~~YAY AAA~~<br>i}<br>i}<br>1<br>2<br>|<br>~~**1**~~<br>~~1~~<br>~~1~~<br>**1**<br>**1**<br>~~1~~<br>!<br>!<br>**1**<br>1<br>1<br>!<br>!<br>**1**<br>1<br>1|Bit #<br>30 – 22<br>31 – 23<br>32 – 24<br>33 – 25<br>34 – 26<br>35 – 27<br>36 – 28<br>~~AAA~~<br>~~ADAYA~~<br>i}<br>1<br>|<br>3<br>~~**1**~~<br>~~1~~<br>~~1~~<br>~~1~~<br>**1**<br>**1**<br>~~1~~<br>!<br>**1**<br>!<br>1<br>1<br>1<br>!<br>**1**<br>!<br>1<br>1<br>1|~~ADAYA~~<br>~~AALS~~<br>1<br>3<br>4<br>~~**1**~~<br>~~1~~<br>~~1~~<br>~~1~~<br>~~1~~<br>**1**<br>**1**<br>~~1~~<br>!<br>!<br>**1**<br>1<br>1<br>1<br>!<br>!<br>**1**<br>1<br>1<br>1|~~AALS~~<br>4<br>~~**1**~~<br>~~1~~<br>~~1~~<br>~~1~~<br>~~1~~<br>**1**<br>~~1~~<br>!<br>**1**<br>1<br>1<br>1<br>!<br>**1**<br>1<br>1<br>1|
|---|---|---|---|---|---|
|Bit #<br>00 – 1<br>00 – 2<br>00 – 3<br>00 – 4<br>00 – 5<br>00 – 6<br>00 – 7<br>~~**1**~~<br>~~1~~<br>!<br>1<br>!<br>1||||||



**Figure 4.11. DDRX71 Video Timing Waveforms** 

**==> picture [442 x 167] intentionally omitted <==**

**----- Start of picture text -----**<br>
Bit 0 Bit 1 Bit i<br>1/2 UI 1/2 UI<br>CLK (in) 1 UI<br>DATA (in)<br>tSU_0<br>tHD_0<br>1 tSU_i ' H<br>tHD_i<br>**----- End of picture text -----**<br>


**Figure 4.12. Receiver DDRX71_RX Waveforms** 

© 2021-2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02102-1.7 

135 

**MachXO5-NX Family Data Sheet** 

**==> picture [401 x 200] intentionally omitted <==**

**----- Start of picture text -----**<br>
Bit 0 Bit 1 Bit i<br>1 UI<br>CLK (out)<br>DATA (out)<br>tDIB_0 X00 8000 U<br>tDIA_0<br>tDIB_i<br>tDIA_i<br>**----- End of picture text -----**<br>


**Figure 4.13. Transmitter DDRX71_TX Waveforms** 

## **4.19. sysCLOCK PLL Timing (VCC = 1.0 V)** 

Over recommended operating conditions. 

**Table 4.35. sysCLOCK PLL Timing (VCC = 1.0 V)** 

|**Parameter**<br>~~a~~|**Descriptions**<br>~~a~~|**Conditions**<br>~~a~~|**Min**<br>~~a~~|**Typ. **<br>~~a~~|**Max**<br>~~a~~|**Units**<br>~~a~~|
|---|---|---|---|---|---|---|
|fIN<br>~~a~~|Input Clock Frequency (CLKI, CLKFB)<br>~~a~~|—<br>~~a~~|18<br>~~a~~|—<br>~~a~~|500<br>~~a~~|MHz<br>~~a~~|
|fOUT<br>~~a~~<br>~~i~~|Output Clock Frequency<br>~~a~~<br>~~i~~<br>~~A~~|—<br>~~a~~<br>~~i~~|6.25<br>~~a~~<br>~~i~~|—<br>~~a~~<br>~~i~~|800<br>~~a~~<br>~~i~~|MHz<br>~~a~~<br>~~i~~|
|fVCO<br>~~i~~|PLL VCO Frequency<br>~~i~~<br>~~A~~|—<br>~~i~~|800<br>~~i~~|—<br>~~i~~|1600<br>~~i~~|MHz<br>~~i~~|
|fPFD<br>~~—-=—-2—~~|Phase Detector Input Frequency<br>~~—-=—-2—~~|Without Fractional-N<br>Enabled<br>~~—-=—-2—~~|18<br>~~—-=—-2—~~|—<br>~~—-=—-2—~~|500<br>~~—-=—-2—~~|MHz<br>~~—-=—-2—~~|
|||With Fractional-N<br>Enabled<br>~~—-=—-2—~~<br>~~ee~~|18<br>~~—-=—-2—~~<br>~~ee~~<br>~~ee~~|—<br>~~—-=—-2—~~<br>~~ee~~<br>~~ee~~|100<br>~~—-=—-2—~~<br>~~ee~~|MHz<br>~~—-=—-2—~~<br>~~ee~~|
|**AC Characteristics**<br>~~ee~~|||||||
|tDT<br>~~ee~~|Output Clock DutyCycle<br>~~ee~~|—<br>~~ee~~<br>~~ee~~|45<br>~~ee~~<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~|55<br>~~ee~~|%<br>~~ee~~|
|tPH4<br>~~ee~~|Output Phase Accuracy<br>~~ee~~|—<br>~~ee~~<br>~~ee~~|–5<br>~~ee~~<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~|5<br>~~ee~~|%<br>~~ee~~|
|tOPJIT1<br>~~ee~~|Output Clock Period Jitter<br>~~ee~~<br>~~ee~~|fOUT≥ 200 MHz<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>|250<br>~~ee~~<br>~~ee~~<br>~~ee~~|psp-p<br>~~ee~~<br>~~ee~~<br>~~ee~~|
|||fOUT< 200 MHz<br>~~ee~~<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~<br>|0.05<br>~~ee~~<br>~~ee~~|UIPP<br>~~ee~~<br>~~ee~~|
||Output Clock Cycle-to-Cycle Jitter<br>~~es~~|fOUT≥ 200 MHz<br>~~ee~~<br>~~es~~<br>~~ee~~|—<br>~~ee~~<br>~~es~~<br>~~ee~~|—<br>~~es~~<br>|250<br>~~es~~<br>~~ee~~|psp-p<br>~~es~~<br>~~ee~~|
|||fOUT< 200 MHz<br>~~ee~~<br>~~es~~<br>~~ee~~|—<br>~~ee~~<br>~~es~~<br>~~ee~~|—<br>~~es~~<br>|0.05<br>~~es~~<br>~~ee~~|UIPP<br>~~es~~<br>~~ee~~|
||Output Clock Phase Jitter<br>~~———-_-_—~~|fPFD≥ 200 MHz<br>~~ee~~<br>~~———-_-_—~~|—<br>~~ee~~<br>~~———-_-_—~~|—<br><br>~~———-_-_—~~|250<br>~~ee~~<br>~~———-_-_—~~|psp-p<br>~~ee~~<br>~~———-_-_—~~|
|||60 MHz ≤ fPFD< 200 MHz<br>~~ee~~<br>~~———-_-_—~~|—<br>~~ee ~~<br>~~———-_-_—~~|—<br> <br>~~———-_-_—~~|350<br> ~~ee~~<br>~~———-_-_—~~|psp-p<br>~~ee~~<br>~~———-_-_—~~|
|||30 MHz ≤ fPFD< 60 MHz<br>~~———-_-_—~~<br>~~a~~|—<br>~~———-_-_—~~<br>~~a~~|—<br>~~———-_-_—~~<br>~~a~~|450<br>~~———-_-_—~~<br>~~a~~|psp-p<br>~~———-_-_—~~<br>~~a~~|
|||18 MHz ≤ fPFD< 30 MHz<br>~~———-_-_—~~<br>~~a~~|—<br>~~———-_-_—~~<br>~~a~~|—<br>~~———-_-_—~~<br>~~a~~|650<br>~~———-_-_—~~<br>~~a~~|psp-p<br>~~———-_-_—~~<br>~~a~~|
||Output Clock Period Jitter (Fractional-N)<br>~~ee~~|fOUT≥ 200 MHz<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~|—<br>~~ee~~|350<br>~~ee~~|psp-p<br>~~ee~~|
|||fOUT< 200 MHz<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~|—<br>~~ee~~|0.07<br>~~ee~~|UIPP<br>~~ee~~|
||Output Clock Cycle-to-Cycle Jitter<br>(Fractional-N)<br>~~ee~~<br>~~es~~|fOUT≥ 200 MHz<br>~~ee~~<br>~~es~~<br>~~ee~~|—<br>~~ee~~<br>~~es~~<br>~~ee~~|—<br>~~ee~~<br>~~es~~|400<br>~~ee~~<br>~~es~~|psp-p<br>~~ee~~<br>~~es~~|
|||fOUT< 200 MHz<br>~~es~~<br>~~ee~~|—<br>~~es~~<br>~~ee~~|—<br>~~es~~|0.08<br>~~es~~|UIPP<br>~~es~~|
|fBW3<br>~~GOO~~|PLL LoopBandwidth<br>~~es~~<br>~~GOO~~|—<br>~~es~~<br>~~ee~~<br>~~GOO~~|0.45<br>~~es~~<br>~~ee~~<br>~~GOO~~|<br>~~es~~<br>~~GOO~~|13<br>~~es~~<br>~~GOO~~|MHz<br>~~es~~<br>~~GOO~~|
|tLOCK2<br>~~a~~|PLL Lock-in Time<br>~~a~~|—<br>~~ee~~<br>~~a~~|—<br>~~ee~~<br>~~a~~|—<br>~~a~~|10<br>~~a~~|ms<br>~~a~~|
|tUNLOCK<br>~~a~~|PLL Unlock Time(from RESETgoes HIGH)<br>~~a~~|—<br>~~a~~|—<br>~~a~~|—<br>~~a~~|50<br>~~a~~|ns<br>~~a~~|



© 2021-2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02102-1.7 

All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

136 

**MachXO5-NX Family Data Sheet** 

|**Parameter**|**Descriptions**|**Conditions**|**Min**|**Typ. **|**Max**|**Units**|
|---|---|---|---|---|---|---|
|tIPJIT|Input Clock Period Jitter|fPFD≥ 20 MHz|—|—|500|psp-p|
|||fPFD< 20 MHz|—|—|0.01|UIPP|
|tHI|Input Clock High Time|90% to 90%|0.5|—|—|ns|
|tLO|Input Clock Low Time|10% to 10%|0.5|—|—|ns|
|tRST|RST/ Pulse Width|—|1|—|—|ms|
|fSSC_MOD|Spread Spectrum Clock Modulation<br>Frequency|—|20|—|200|kHz|
|fSSC_MOD_AMP|Spread Spectrum Clock Modulation<br>Amplitude Range|—|0.25|—|2.00|%|
|fSSC_MOD_STEP|Spread Spectrum Clock Modulation<br>Amplitude StepSize|—|—|0.25|—|%|



**Notes** : 

1. Jitter sample is taken over 10,000 samples for Period jitter, and 1,000 samples for Cycle-to-Cycle jitter of the primary PLL output with clean reference clock with no additional I/O toggling. 

2. Output clock is valid after tLOCK for PLL reset and dynamic delay adjustment. 

3. Result from Lattice Radiant software. 

4. CLKOS as compared to CLKOP output for one phase step at the maximum VCO frequency. 

## **4.20. Internal Oscillators Characteristics** 

**Table 4.36. Internal Oscillators (VCC = 1.0 V)** 

|**Symbol**|**Parameter Description**|**Min**|**Typ**|**Max**|**Unit**|
|---|---|---|---|---|---|
|fCLKHF|HFOSC CLKK Clock Frequency|418.5|450|481.5|MHz|
|fCLKLF|LFOSC CLKK Clock Frequency|25.6|32|38.4|kHz|
|DCHCLKHF|HFOSC DutyCycle (Clock High Period)|45|50|55|%|
|DCHCLKLF|LFOSC Duty Cycle (Clock High Period)|45|50|55|%|



## **4.21. Flash Download Time** 

**Table 4.37. Flash Download Time** 

**Symbol Parameter Device Typ. Units** LFMXO5-25 46 ms tREFRESH POR to Device I/O Active LFMXO5-55T — ms LFMXO5-100T — ms ~~Pf~~ **Notes** : • Assumes sysMEM EBR initialized to an all zero pattern if they are used. 

- The Flash download time is measured starting from the maximum voltage of POR trip point. 

## **4.22. Flash Program and Erase Current** 

**Table 4.38. Program and Erase Supply Current Symbol Parameter Device Typ. Units** LFMXO5-25 26 mA Icc Core Power Supply LFMXO5-55T — mA LFMXO5-100T — mA ~~<<>>~~ 

© 2021-2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02102-1.7 

137 

**MachXO5-NX Family Data Sheet** 

## **4.23. User I[2] C Characteristics** 

**Table 4.39. User I[2] C Specifications (VCC = 1.0 V)** 

|**Symbol**|**Parameter**<br>**Description**|**STD Mode**|**STD Mode**|**STD Mode**|**FAST Mode**|**FAST Mode**|**FAST Mode**|**FAST Mode Plus2**|**FAST Mode Plus2**|**FAST Mode Plus2**|**Units**|
|---|---|---|---|---|---|---|---|---|---|---|---|
|||**Min**|**Typ**|**Max**|**Min**|**Typ**|**Max**|**Min**|**Typ**|**Max**||
|fscl|SCL Clock<br>Frequency|—|—|100|—|—|400|—|—|1000|kHz|
|TDELAY1|Optional delay<br>through delayblock|—|62|—|—|62|—|—|62|—|ns|



**Notes** : 

1. Refer to the I[2] C Specification for timing requirements. User design should set constraints in Lattice Design Software to meet this industrial I[2] C Specification. 

2. Fast Mode Plus maximum speed may be achieved by using external pull up resistor on I[2] C bus. Internal pull up may not be sufficient to support the maximum speed. 

## **4.24. Analog-Digital Converter (ADC) Block Characteristics** 

**Table 4.40. ADC Specifications[1]** 

|**Symbol**<br>~~es~~<br>~~a~~|**Description**<br>~~es ns~~<br>~~ee~~|**Condition**<br>~~ns~~<br>~~es~~|**Min**<br>~~I~~<br>~~es~~|**Typ**<br>~~ee~~|**Max**<br>~~ee~~|**Unit**<br>~~ee~~|
|---|---|---|---|---|---|---|
|VREFINT_ADC<br>~~es ~~<br>~~a~~<br>~~a~~|ADC Internal Reference<br>Voltage4<br> ~~es ns~~<br>~~ee~~<br>~~ee~~|—<br>~~ns ~~<br>~~es~~<br>~~ee~~|1.142<br> ~~I~~<br>~~es~~<br>~~es~~|1.2<br>~~ee~~<br>~~ee~~|1.262<br>~~ee~~<br>~~ee~~|V<br>~~ee~~<br>~~ee~~|
|VREFEXT_ADC<br>~~a ~~<br>~~a~~<br>~~es~~<br>~~fe~~|ADC External Reference<br>Voltage<br> ~~ee~~<br>~~ee~~<br>~~ns~~<br>|—<br>~~es~~<br>~~ee~~<br>~~ns~~|1.0<br>~~es~~<br>~~es~~<br>~~ns~~<br>~~I~~|—<br>~~ee~~<br>~~ee~~<br>~~ns~~|1.8<br>~~ee ~~<br>~~ee~~<br>~~ns~~|V<br> ~~ee~~<br>~~ee~~<br>~~ns~~|
|NRES_ADC<br>~~a ~~<br>~~es~~<br>~~fe~~|ADC Resolution<br> ~~ee ~~<br>~~ns~~<br>~~en~~|—<br> ~~ee~~<br>~~ns~~|—<br>~~es ~~<br>~~ns~~<br>~~I~~|12<br> ~~ee ~~<br>~~ns~~|—<br> ~~ee ~~<br>~~ns~~|bits<br> ~~ee~~<br>~~ns~~|
|ENOBADC<br>~~es~~<br>~~fe~~<br>~~)|~~|Effective Number of Bits<br>~~ns~~<br>~~en~~<br>~~)|~~|—<br>~~ns~~<br>~~Se~~|9.9<br>~~ns~~<br>~~I~~<br>~~Se~~~~**e**~~|11<br>~~ns~~<br>~~**e**~~|—<br>~~ns~~<br>~~**e**r~~|bits<br>~~ns~~<br>~~r~~|
|VSR_ADC<br>~~fe ~~<br>~~)|~~<br>~~ee~~|ADC Input Range<br> ~~en~~<br>~~)|~~<br>~~ee~~|Bipolar Mode, Internal VREF<br>~~Se~~|VCM_ADC ―<br>VREFINT_ADC/4<br>~~I~~<br>~~Se~~~~**e**~~|VCM_ADC<br>~~**e**~~|VCM_ADC+<br>VREFINT_ADC/<br>4<br>~~**e**r~~|V<br>~~r~~|
|||Bipolar Mode, External VREF<br>~~Se~~|VCM_ADC ―<br>VREFEXT_ADC/4<br>~~I~~<br>~~Se~~~~**e**~~|VREFEXT_ADC<br>~~**e**~~|VCM_ADC+<br>VREFEXT_ADC/<br>4<br>~~**e**r~~|V<br>~~r~~|
|||Uni-polar Mode, Internal<br>VREF<br>~~Se~~<br><br>|0<br>~~Se~~~~**e**~~<br>~~ee~~<br>|—<br>~~**e**~~<br>~~ee~~<br>|VREFINT_ADC<br>~~**e**r~~<br>~~ee~~<br>|V<br>~~r~~<br>~~**ee**~~|
|||Uni-polar Mode, External<br>VREF<br>~~Se~~<br>~~e~~<br>~~ees~~|0<br>~~Se~~~~**e**~~<br>~~eee~~<br>~~es~~|—<br>~~**e**~~<br>~~ee~~<br>~~ee~~|VREFEXT_ADC<br>~~**e**r~~<br>~~ee~~<br>~~ee~~|V<br>~~r~~<br>~~**ee**~~|
|VCM_ADC<br>~~)|~~<br>~~ee~~<br>~~es~~<br>~~a~~|ADC Input Common Mode<br>Voltage (for fully differential<br>signals)<br>~~)| ~~<br>~~ee~~<br>~~ns~~|Internal VREF<br> ~~Se~~<br>~~e~~<br>~~ees~~|—<br>~~Se~~~~**e**~~<br>~~eee~~<br>~~es~~<br>~~ee~~|VREFINT_ADC/2<br>~~**e**~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|—<br>~~**e**r~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|V<br>~~r~~<br>~~**ee**~~<br>~~ee~~|
|||External VREF<br><br>~~ees~~<br>~~ee~~<br>~~tS~~|—<br>~~ee~~<br>~~es~~<br>~~ee~~<br>~~ee~~<br>~~I~~|VREFEXT_ADC/2<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|V<br>~~**ee**~~<br>~~ee~~<br>~~ee~~|
|fCLK_ADC<br>~~ee ~~<br>~~es~~<br>~~a~~<br>~~es~~|ADC Clock Frequency<br> ~~ee ~~<br>~~ns~~<br>~~ee~~<br>|—<br><br> ~~ees ~~<br>~~ee~~<br>~~tS~~<br>~~ee~~<br>|—<br>~~ee ~~<br> ~~es ~~<br>~~ee~~<br>~~ee~~<br>~~I~~<br>~~es~~<br>|25<br> ~~ee ~~<br> ~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|40<br> ~~ee ~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|MHz<br> ~~**ee**~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|
|fINPUT_ADC<br>~~es~~<br>~~a~~<br>~~es~~<br>~~es~~|ADC Input Frequency<br>~~ns~~<br>~~ee~~<br>~~es~~|@ Sampling Frequency =<br>1 Mbps<br>~~tS~~<br>~~ee~~<br>~~ts I~~|—<br>~~ee ~~<br>~~I~~<br>~~es~~<br>~~I~~|—<br> ~~ee ~~<br>~~ee~~<br>~~I~~|500<br> ~~ee ~~<br>~~ee~~<br>~~I~~|kHz<br> ~~ee~~<br>~~ee~~|
|FSADC<br>~~a~~<br>~~es~~<br>~~es~~<br>~~a~~|ADC SamplingRate<br>~~ns~~<br>~~ee~~<br>~~es~~<br>~~nD~~|—<br>~~tS ~~<br>~~ee~~<br>~~ts I~~<br>~~nD~~|—<br> ~~I~~<br>~~es~~<br>~~I~~<br>~~I~~|1<br>~~ee~~<br>~~I~~|—<br>~~ee~~<br>~~I~~|MS/s<br>~~ee~~|
|NTRACK_ADC<br>~~es~~<br>~~es~~<br>~~a~~<br>~~es~~|ADC Input TrackingTime<br>~~ee~~<br>~~es~~<br>~~nD~~<br>~~ee ee~~|—<br>~~ee ~~<br>~~ts I~~<br>~~nD~~<br>~~ee~~|4<br> ~~es ~~<br>~~I~~<br>~~I~~<br>~~es~~|—<br> ~~ee ~~<br>~~I~~<br>~~ee~~|—<br> ~~ee ~~<br>~~I~~<br>~~ee~~|cycles3<br> ~~ee~~<br>~~ee~~|
|RIN_ADC<br><br>~~es~~<br>~~a~~<br>~~es~~<br>~~a~~|ADC Input Equivalent<br>Resistance<br>~~es~~<br>~~nD~~<br>~~ee ee~~<br>~~ny nD~~|—<br>~~ts I~~<br>~~nD ~~<br>~~ee~~<br>~~nD~~|—<br>~~I~~<br> ~~I~~<br>~~es~~<br>~~I~~|116<br>~~I ~~<br>~~ee~~<br>~~I~~|—<br> ~~I~~<br>~~ee~~|KΩ<br>~~ee~~|
|tCAL_ADC<br>~~es~~<br>~~a~~<br>~~a~~|ADC Calibration Time<br>~~ee ee~~<br>~~ny nD~~<br>~~ee ee~~|—<br>~~ee~~<br>~~nD~~<br>~~ee~~|—<br>~~es~~<br>~~I~~<br>~~es ee~~|—<br>~~ee~~<br>~~I~~<br>~~ee~~|6500<br>~~ee~~<br>~~ee~~|cycles3<br>~~ee~~<br>~~ee~~|
|LOUTput_ADC<br>~~es~~<br>~~a~~<br>~~a~~<br>~~ee~~|ADC Conversion Time<br>~~ee ee~~<br>~~ny nD~~<br>~~ee ee~~<br>~~ee~~|Includes minimum tracking<br>time of four cycles<br>~~ee ~~<br>~~nD ~~<br>~~ee~~<br>~~ee~~|25<br> ~~es ~~<br> ~~I ~~<br>~~es ee~~<br>~~es~~|—<br> ~~ee ~~<br> ~~I~~<br>~~ee~~<br>~~ee~~|—<br> ~~ee ~~<br>~~ee~~<br>~~ee~~|cycles3<br> ~~ee~~<br>~~ee~~<br>~~ee~~|
|DNLADC<br>~~a~~<br>~~ee~~|ADC Differential<br>Nonlinearity<br>~~ee ee~~<br>~~ee~~|—<br>~~ee ~~<br>~~ee~~|–1<br> ~~es ee~~<br>~~es~~|—<br>~~ee ~~<br>~~ee~~|1<br> ~~ee ~~<br>~~ee~~|LSB<br> ~~ee~~<br>~~ee~~|
|INLADC<br>~~ee~~|ADC Integral Nonlinearity<br>~~ee~~|—<br>~~ee~~|–22<br>~~es~~<br>~~es~~|—<br>~~ee~~<br>~~ee~~|2.21<br>~~ee~~<br>~~es~~|LSB<br>~~ee~~|
|SFDRADC<br>~~ee~~<br>~~a ee~~|ADC Spurious Free Dynamic<br>Range<br>~~ee~~<br>~~ee~~|—<br>~~ee ~~<br>~~ee~~|67.7<br> ~~es ~~<br>~~ee~~<br>~~es~~|77<br> ~~ee ~~<br>~~ee~~<br>~~ee~~|—<br> ~~ee ~~<br>~~ee~~<br>~~es~~|dBc<br> ~~ee~~<br>~~ee~~|



138 

**MachXO5-NX Family Data Sheet** 

|**Symbol**<br>~~pf~~|**Description**<br>~~pf~~|**Condition**<br>~~pf~~|**Min**<br>~~pf~~|**Typ**<br>~~pf~~|**Max**<br>~~pf~~|**Unit**<br>~~pf~~|
|---|---|---|---|---|---|---|
|THDADC<br>~~a~~|ADC Total Harmonic<br>Distortion<br>|—<br>|—<br>|–76<br>|–66.8<br>|dB<br>|
|SNRADC<br>~~GO~~|ADC Signal to Noise Ratio<br>~~GO~~|—<br>~~GO~~|61.9<br>~~GO~~<br>~~ee~~|68<br>~~GO~~|—<br>~~GO~~|dB<br>~~GO~~|
|SNDRADC<br>~~a~~|ADC Signal to Noise Plus<br>Distortion Ratio<br>~~ee~~|—<br>~~ee~~|61.7<br>~~ee~~<br>~~ee~~|67<br>~~ee~~|—<br>~~ee~~|dB<br>~~ee~~|
|ERRGAIN_ADC<br>~~GO~~|ADC Gain Error<br>~~GO~~|—<br>~~GO~~|–0.5<br>~~ee~~<br>~~GO~~|—<br>~~GO~~|0.5<br>~~GO~~|% FSADC<br>~~GO~~|
|ERROFFSET_ADC<br>~~GO~~|ADC Offset Error<br>~~GO~~|—<br>~~GO~~|–2<br>~~GO~~|—<br>~~GO~~|2<br>~~GO~~|LSB<br>~~GO~~|
|CIN_ADC<br>~~a~~|ADC Input Equivalent<br>Capacitance|—|—|2|—|pF|



**Notes** : 

1. ADC is available in select speed grades. See Ordering Information. 

2. Not tested; guaranteed by design. 

3. ADC Sample Clock cycles. See ADC User Guide for Nexus Platform (FPGA-TN-02129) for more details. 

4. Internal voltage reference is only for internal testing purpose. It is not recommended for customer design. User should always use the part with external reference voltage. 

## **4.25. Comparator Block Characteristics** 

**Table 4.41. Comparator Specifications** 

|**Symbol**|**Description**|**Min**|**Typ**|**Max**|**Unit**|
|---|---|---|---|---|---|
|fIN_COMP|Comparator Input Frequency|—|—|10|MHz|
|VIN_COMP|Comparator Input Voltage|0|—|VCCADC18|V|
|VOFFSET_COMP|Comparator Input Offset|–23|—|24|mV|
|VHYST_COMP|Comparator Input Hysteresis|10|—|31|mV|
|VLATENCY_COMP|Comparator Latency|—|—|31|ns|



**Note** : Comparator is available in select speed grades.  See Ordering Information. 

## **4.26. Digital Temperature Readout Characteristics** 

Digital temperature Readout (DTR) is implemented in one of the channels of ADC1. 

**Table 4.42. DTR Specifications[1, 2]** 

|**Symbol**|**Description**|**Condition**|**Min**|**Typ**|**Max**|**Unit**|
|---|---|---|---|---|---|---|
|DTRRANGE|DTR Detect Temperature<br>Range|—|–40|—|100|°C|
|DTRACCURACY|DTR Accuracy|with external voltage1<br>reference range of 1.0 V<br>to 1.8 V|–13|±4|13|°C|
|DTRRESOLUTION|DTR Resolution|with external voltage<br>reference|–0.3|—|0.3|°C|



**Notes** : 

1. External voltage reference (VREF) should be 0.1% accurate or better. DTR sensitivity to VREF is -4.1 °C per VREF per-cent (for example, if the VREF is 1 % low, then the DTR will read +4.1 °C high). 

2. DTR is available in select speed grades. See the Ordering Information section. 

© 2021-2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02102-1.7 

139 

**MachXO5-NX Family Data Sheet** 

## **4.27. Hardened PCIe Characteristics** 

## **4.27.1. PCIe (2.5 Gbps)** 

**Table 4.43. PCIe (2.5 Gbps)** 

|**Symbol**<br>~~Po~~|**Description**<br>~~eae~~|**Condition**<br>~~eae~~<br>~~et~~|**Min.**<br>~~et~~|**Typ. **|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|**Transmitter1**<br>~~Po~~<br>~~eae~~<br>~~et~~<br>~~es~~<br>~~rs(~~|||||||
|UI<br>~~es~~<br>~~es~~<br>~~ee~~|Unit Interval<br>~~rs~~<br>~~es~~|—<br>~~(~~<br>~~es~~<br>~~(OO~~|399.88<br>~~es~~<br>~~(OO~~|400<br>~~es~~<br>~~(OO~~|400.12<br>~~es~~<br>~~I~~|ps<br>~~es~~|
|BWTX<br>~~es~~<br>~~es~~<br>~~ee~~<br>~~ee~~|Tx PLL bandwidth<br>~~rs~~<br>~~es~~<br>~~ee~~|—<br>~~(~~<br>~~es~~<br>~~(OO~~<br>~~es~~|1.5<br>~~es~~<br>~~(OO~~<br>~~es~~|—<br>~~es~~<br>~~(OO~~<br>~~ee~~|22<br>~~es~~<br>~~I~~|MHz<br>~~es~~|
|VTX-DIFF-PP<br>~~es~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|Differential p-p Tx voltage<br>swing<br>~~es~~<br>~~ee~~<br>~~ee~~|—<br>~~es~~<br>~~(OO~~<br>~~es~~<br>~~es~~|0.8<br>~~es~~<br>~~(OO~~<br>~~es~~<br>~~es~~|—<br>~~es~~<br>~~(OO~~<br>~~ee~~<br>~~ee~~|1.2<br>~~es~~<br>~~I~~|Vp-p<br>~~es~~|
|VTX-DIFF-PP-LOW<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~es~~|Low power differential p-p Tx<br>voltage swing<br>~~ee~~<br>~~ee~~<br>~~re~~|—<br>~~(OO~~<br>~~es~~<br>~~es~~<br>~~es~~|0.4<br>~~(OO~~<br>~~es~~<br>~~es~~<br>~~es~~|—<br>~~(OO~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|1.2<br>~~I~~|Vp-p|
|VTX-DE-RATIO-3.5dB<br>~~ee~~<br>~~ee~~<br>~~es~~|Tx de-emphasis level ratio at<br>3.5 dB<br>~~ee~~<br>~~ee~~<br>~~re~~<br>~~nr~~|—<br>~~es ~~<br>~~es~~<br>~~es~~<br>~~GR~~|3<br> ~~es ~~<br>~~es~~<br>~~es~~|—<br> ~~ee~~<br>~~ee~~<br>~~ee~~|4|dB|
|TTX-RISE-FALL<br>~~ee~~<br>~~es~~|Transmitter rise and fall time<br>~~ee~~<br>~~re~~<br>~~nr~~|—<br>~~es ~~<br>~~es~~<br>~~GR~~|0.125<br> ~~es ~~<br>~~es~~|—<br> ~~ee~~<br>~~ee~~|—|UI|
|TTX-EYE<br>~~es~~<br>~~EE~~|Transmitter Eye, including all<br>jitter sources<br>~~re~~<br>~~nr~~<br>~~EE~~|—<br>~~es ~~<br>~~GR~~<br>~~EEE~~|0.75<br> ~~es ~~<br>~~EEE~~|—<br> ~~ee~~<br>~~EEE~~|—<br>~~EEE~~|UI<br>~~EEE~~|
|TTX-EYE-MEDIAN-to-MAX-<br>JITTER<br>~~EE~~<br>~~ee~~|Max. time between jitter<br>median and max deviation<br>from the median<br>~~EE ~~<br>~~ee es~~|—<br> ~~EEE~~<br>~~es~~|—<br>~~EEE~~<br>~~es~~|—<br>~~EEE~~<br>~~ee~~|0.125<br>~~EEE~~<br>~~ee~~|UI<br>~~EEE~~<br>~~ee~~|
|RLTX-DIFF<br>~~ee~~<br>~~ee~~|Tx Differential Return Loss,<br>including pkgand silicon<br>~~ee es~~<br>~~ee es~~|—<br>~~es~~<br>~~es~~|10<br>~~es~~<br>~~es~~|—<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~|dB<br>~~ee~~<br>~~ee~~|
|RLTX-CM<br>~~ee~~<br>~~ee~~<br>~~es~~|Tx Common Mode Return Loss,<br>including pkgand silicon<br>~~ee es~~<br>~~ee es~~<br>~~nr~~|50 MHz < freq < 2.5 GHz<br>~~es ~~<br>~~es~~<br>~~GR~~|6<br> ~~es ~~<br>~~es~~|—<br> ~~ee ~~<br>~~ee~~|—<br> ~~ee ~~<br>~~ee~~|dB<br> ~~ee~~<br>~~ee~~|
|ZTX-DIFF-DC<br>~~ee~~<br>~~es~~<br>~~ee~~|DC differential Impedance<br>~~ee es~~<br>~~nr~~<br>~~ee~~|—<br>~~es ~~<br>~~GR~~<br>~~es~~|80<br> ~~es ~~<br>~~es~~|—<br> ~~ee ~~<br>~~ee~~|120<br> ~~ee ~~<br>~~ee~~|Ω<br> ~~ee~~|
|VTX-CM-AC-P<br>~~es~~<br>~~ee~~<br>~~ee~~|Tx AC peak common mode<br>voltage, RMS<br>~~nr~~<br>~~ee~~<br>~~ee~~|—<br>~~GR~~<br>~~es~~<br>~~es~~|—<br>~~es~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~|20<br>~~ee~~<br>~~ee~~|mV,<br>RMS<br>~~ee~~|
|ITX-SHORT<br>~~ee~~<br>~~ee~~<br>~~ae~~|Transmitter short-circuit<br>current<br>~~ee ~~<br>~~ee~~<br>~~ee~~|—<br> ~~es ~~<br>~~es~~<br>~~es~~|—<br> ~~es ~~<br>~~ee~~<br>~~es~~|—<br> ~~ee ~~<br>~~ee~~<br>~~ee~~|90<br> ~~ee~~<br>~~ee~~<br>~~ee~~|mA<br>~~ee~~<br>~~ee~~|
|VTX-DC-CM<br>~~ee~~<br>~~ae~~<br>~~ae~~|Transmitter DC common-mode<br>voltage<br>~~ee~~<br>~~ee~~<br>~~ee~~|—<br>~~es ~~<br>~~es~~<br>~~es~~|0<br> ~~ee ~~<br>~~es~~<br>~~es~~|—<br> ~~ee ~~<br>~~ee~~<br>~~ee~~|1.2<br> ~~ee~~<br>~~ee~~<br>~~ee~~|V<br>~~ee~~<br>~~ee~~<br>~~ee~~|
|VTX-IDLE-DIFF-AC-p<br>~~ae~~<br>~~ae~~<br>~~ae~~|Electrical Idle Output peak<br>voltage<br>~~ee ~~<br>~~ee~~<br>~~ee~~|—<br> ~~es ~~<br>~~es~~<br>~~es~~|—<br> ~~es ~~<br>~~es~~<br>~~es~~|—<br> ~~ee ~~<br>~~ee~~<br>~~ee~~|20<br> ~~ee~~<br>~~ee~~<br>~~ee~~|mV<br>~~ee~~<br>~~ee~~<br>~~ee~~|
|VTX-RCV-DETECT<br>~~ae~~<br>~~ae~~<br>~~es~~|Voltage change allowed during<br>Receiver Detect<br>~~ee ~~<br>~~ee~~<br>~~rs~~|—<br> ~~es ~~<br>~~es~~<br>~~GR~~|—<br> ~~es ~~<br>~~es~~|—<br> ~~ee ~~<br>~~ee~~|600<br> ~~ee~~<br>~~ee~~|mV<br>~~ee~~<br>~~ee~~|
|TTX-IDLE-MIN<br>~~ae~~<br>~~es~~<br>~~ae~~|Min. time in Electrical Idle<br>~~ee ~~<br>~~rs~~<br>~~ee~~|—<br> ~~es ~~<br>~~GR~~<br>~~es~~|20<br> ~~es ~~<br>~~es~~|—<br> ~~ee ~~<br>~~ee~~|—<br> ~~ee~~<br>~~ee~~|ns<br>~~ee~~<br>~~ee~~|
|TTX-IDLE-SET-TO-IDLE<br>~~es~~<br>~~ae~~<br>~~ae~~|Max. time from EI Order Set to<br>valid Electrical Idle<br>~~rs~~<br>~~ee~~<br>~~ee~~|—<br>~~GR~~<br>~~es~~<br>~~es~~|—<br>~~es~~<br>~~es~~|—<br>~~ee~~<br>~~ee~~|8<br>~~ee~~<br>~~ee~~|ns<br>~~ee~~<br>~~ee~~|
|TTX-IDLE-TO-DIFF-DATA<br>~~ae~~<br>~~ae~~<br>~~ae~~|Max. time from Electrical Idle<br>to valid differential output<br>~~ee ~~<br>~~ee~~<br>~~ee~~|—<br> ~~es ~~<br>~~es~~<br>~~es~~|—<br> ~~es ~~<br>~~es~~<br>~~ee~~|—<br> ~~ee ~~<br>~~ee~~<br>~~ee~~|8<br> ~~ee~~<br>~~ee~~<br>~~ee~~|ns<br>~~ee~~<br>~~ee~~|
|LTX-SKEW<br>~~ae~~<br>~~ae~~|Lane-to-Lane output skew<br>~~ee ~~<br>~~ee~~|—<br> ~~es ~~<br>~~es~~|—<br> ~~es ~~<br>~~ee~~|—<br> ~~ee ~~<br>~~ee~~|500 ps<br>+ 2 UI<br> ~~ee~~<br>~~ee~~|ps<br>~~ee~~|
|**Receiver2**<br>~~ae~~<br>~~ee~~<br>~~es ee ee ee~~<br>~~eses~~<br>~~UD~~<br>~~ee~~|||||||
|UI<br>~~es~~<br>~~ee~~<br>~~es~~|Unit Interval<br>~~es~~<br>~~ee~~<br>|—<br>~~es~~<br>~~UD~~<br>~~es~~|399.88<br>~~es~~<br>~~es~~|400<br>~~es~~<br>~~ee~~|400.12<br>~~es~~<br>~~ee~~|ps<br>~~es~~|
|VRX-DIFF-PP<br>~~es~~<br>~~ee~~<br>~~es~~<br>~~ee~~|Differential Rx peak-peak<br>voltage<br>~~es~~<br>~~ee~~<br>~~es~~|—<br>~~es~~<br>~~UD~~<br>~~es~~|0.175<br>~~es~~<br>~~es~~|—<br>~~es~~<br>~~ee~~|1.2<br>~~es~~<br>~~ee~~|Vp-p<br>~~es~~|
|TRX-EYE3<br>~~ee ~~<br>~~es~~<br>~~ee~~|Receiver eye openingtime<br> ~~ee~~<br>~~es~~|—<br>~~UD~~<br>~~es~~|0.4<br>~~es~~|—<br>~~ee~~|—<br>~~ee~~|UI|
|TRX-EYE-MEDIAN-to-MAX-<br>JITTER3<br> <br>~~es~~<br>~~ee~~|Max time delta between<br>median and deviation from<br>median<br> ~~ee~~<br>~~es~~<br>~~ee~~|—<br>~~es~~<br>~~es~~|—<br>~~es~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~|0.3<br>~~ee~~<br>~~ee~~|UI|
|RLRX-DIFF<br> <br>~~es ~~<br>~~ee~~|Receiver differential Return<br>Loss,packageplus silicon<br> ~~ee ~~<br> ~~es~~<br>~~ee~~|—<br> ~~es ~~<br>~~es~~|10<br> ~~es~~<br>~~ee~~|—<br>~~ee ~~<br>~~ee~~|—<br> ~~ee~~<br>~~ee~~|dB|



140 

**MachXO5-NX Family Data Sheet** 

|**Symbol**<br>~~ee~~<br>~~ee~~|**Description**<br>~~rs~~<br>~~es~~|**Condition**<br>~~(Rt~~<br>~~ee~~|**Min.**<br>~~(OO~~<br>~~ee~~|**Typ. **<br>~~(OO~~|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|RLRX-CM<br>~~ee~~<br>~~ee~~<br>~~es~~|Receiver common mode Return<br>Loss,packageplus silicon<br>~~rs~~<br>~~es~~<br>~~ee~~|—<br>~~(Rt~~<br>~~ee~~<br>~~ee~~|6<br>~~(OO~~<br>~~ee~~<br>~~ee~~|—<br>~~(OO~~|—|dB|
|ZRX-DC<br>~~ee~~<br>~~es~~|Receiver DC single ended<br>impedance<br>~~es ~~<br>~~ee~~|—<br> ~~ee ~~<br>~~ee~~|40<br> ~~ee~~<br>~~ee~~|—|60|Ω|
|ZRX-DIFF-DC<br>~~es ~~<br>~~EO~~|Receiver DC differential<br>impedance<br> ~~ee ~~<br>~~EO~~|—<br> ~~ee~~<br>~~EO~~|80<br>~~ee~~<br>~~EO~~|—<br>~~EO~~|120<br>~~EO~~|Ω<br>~~EO~~|
|ZRX-HIGH-IMP-DC<br>~~EO~~<br>~~es~~|Receiver DC single ended<br>impedance when powered<br>down<br>~~EO~~<br>~~ee~~|—<br>~~EO~~<br>~~ee~~|200k<br>~~EO~~<br>~~ee~~|—<br>~~EO~~|—<br>~~EO~~|Ω<br>~~EO~~|
|VRX-CM-AC-P3<br>~~es~~<br>~~es~~<br>~~Po~~|Rx AC peak common mode<br>voltage<br>~~ee~~<br>~~es~~|—<br>~~ee~~<br>~~es~~<br>~~(OO~~|~~ee~~<br>~~es~~<br>~~(OO~~|—<br>~~es~~<br>~~(OO~~|150<br>~~es~~<br>~~I~~|mV,<br>peak<br>~~es~~|
|VRX-IDLE-DET-DIFF-PP<br>~~es ~~<br>~~es~~<br>~~Po~~|Electrical Idle Detect Threshold<br> ~~ee ~~<br>~~es~~<br>~~ee~~|—<br> ~~ee~~<br>~~es~~<br>~~(OO~~<br>~~ee~~|65<br>~~ee~~<br>~~es~~<br>~~(OO~~|—<br>~~es~~<br>~~(OO~~|175<br>~~es~~<br>~~I~~|mVp-p<br>~~es~~|
|LRX-SKEW<br>~~es~~<br>~~Po~~|Receiver –lane-lane skew<br>~~es~~<br>~~ee~~|—<br>~~es~~<br>~~(OO~~<br>~~ee~~|~~es~~<br>~~(OO~~|—<br>~~es~~<br>~~(OO~~|20<br>~~es~~<br>~~I~~|ps<br>~~es~~|



## **Notes:** 

1. Refer to PCI Express Base Specification Revision 3.0 Table 4.18 test condition and requirement for respective parameters. 

2. Refer to PCI Express Base Specification Revision 3.0 Table 4.24 test condition and requirement for respective parameters. 

3. Spec compliant requirement. 

## **4.27.2. PCIe (5 Gbps)** 

**Table 4.44. PCIe (5 Gbps)** 

|**Symbol**<br>~~Pr~~|**Description**<br>~~ee~~|**Test Conditions**<br>~~ee~~<br>~~ee~~|**Min**<br>~~ee~~|**Typ**|**Max**|**Unit**|
|---|---|---|---|---|---|---|
|**Transmit1**<br>~~Pr~~<br>~~ee~~<br>~~ee~~<br>~~Ree~~<br>~~esen~~<br>~~(GO~~<br>~~a~~|||||||
|UI<br>~~Ree~~<br>~~esen~~<br>~~a~~<br>~~a~~|Unit Interval<br>~~Ree~~<br>~~en~~<br>~~ee ee~~|—<br>~~Ree~~<br>~~en~~<br>~~ee~~|199.94<br>~~Ree~~<br>~~en~~<br>~~(GO~~<br>~~ee~~|200<br>~~Ree~~<br>~~en~~<br>~~(GO~~<br>~~ee~~|200.06<br>~~Ree~~<br>~~en~~<br>~~ee~~|ps<br>~~Ree~~<br>~~en~~<br>~~ee~~|
|BWTX-PKG-PLL1<br>~~esen~~<br>~~a~~<br>~~a~~<br>~~a~~|Tx PLL bandwidth<br>correspondingto PKGTX-PLL1<br>~~en~~<br>~~ee ee~~<br>~~ee ee~~|—<br>~~en~~<br>~~ee~~<br>~~ee~~|8<br>~~en~~<br>~~(GO~~<br>~~ee~~<br>~~ee~~|—<br>~~en~~<br>~~(GO~~<br>~~ee~~<br>~~ee~~|16<br>~~en~~<br>~~ee~~<br>~~ee~~|MHz<br>~~en~~<br>~~ee~~<br>~~ee~~|
|BWTX-PKG-PLL2<br>~~a~~<br>~~a~~<br>~~a~~<br>~~a~~|Tx PLL bandwidth<br>correspondingto PKGTX-PLL2<br>~~ee ee~~<br>~~ee ee~~<br>~~ee ee~~|—<br>~~ee~~<br>~~ee~~<br>~~ee~~|5<br>~~(GO~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|—<br>~~(GO~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|16<br>~~ee~~<br>~~ee~~<br>~~ee~~|MHz<br>~~ee~~<br>~~ee~~<br>~~ee~~|
|PKGTX-PLL1<br>~~a~~<br>~~a~~<br>~~a~~<br>~~a~~|Tx PLL Peaking<br>correspondingto PKGTX-PLL1<br>~~ee ee~~<br>~~ee ee~~<br>~~ee ee~~<br>~~ee~~|—<br>~~ee ~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|—<br> ~~ee ~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|—<br> ~~ee ~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|3<br> ~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|dB<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|
|PKGTX-PLL2<br>~~a~~<br>~~a~~<br>~~a~~<br>~~a~~|Tx PLL Peaking<br>correspondingto PKGTX-PLL2<br>~~ee ee~~<br>~~ee ee~~<br>~~ee~~<br>~~ee ee~~|—<br>~~ee ~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|—<br> ~~ee ~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|—<br> ~~ee ~~<br>~~ee~~<br>~~ee~~|1<br> ~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|dB<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|
|VTX-DIFF-PP<br>~~a~~<br>~~a~~<br>~~a~~<br>~~a~~|Differential p-p Tx voltage<br>swing<br>~~ee ee~~<br>~~ee~~<br>~~ee ee~~<br>~~ee ee~~|—<br>~~ee ~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|0.8<br> ~~ee ~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|—<br> ~~ee ~~<br>~~ee~~|1.2<br> ~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|V, p-p<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|
|VTX-DIFF-PP-LOW<br>~~a~~<br>~~a~~<br>~~a~~<br>~~a~~|Low power differential p-p Tx<br>voltage swing<br>~~ee~~<br>~~ee ee~~<br>~~ee ee~~<br>~~ee ee~~|—<br>~~ee ~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|0.4<br> ~~ee ~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|—<br> ~~ee ~~|1.2<br> ~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|V, p-p<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|
|VTX-DE-RATIO-3.5dB<br>~~a~~<br>~~a~~<br>~~a~~<br>~~es~~|Tx de-emphasis level ratio at<br>3.5 dB<br>~~ee ee~~<br>~~ee ee~~<br>~~ee ee~~<br>~~ee ee~~<br>|—<br>~~ee ~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|3<br> ~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|—|4<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|dB<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|
|VTX-DE-RATIO-6dB<br>~~a~~<br>~~a~~<br>~~es~~<br>~~es~~|Tx de-emphasis level ratio at<br>6 dB<br>~~ee ee~~<br>~~ee ee~~<br>~~ee ee~~<br>~~Se~~<br>~~D~~|—<br>~~ee ~~<br>~~ee~~<br>~~ee~~<br>~~(~~|5.5<br> ~~ee~~<br>~~ee~~<br>~~ee~~<br>~~(~~|—|6.5<br>~~ee~~<br>~~ee~~<br>~~ee~~|dB<br>~~ee~~<br>~~ee~~<br>~~ee~~|
|TMIN-PULSE<br>~~a~~<br>~~es~~<br>~~es~~<br>~~ae~~|Instantaneous lonepulse width<br>~~ee ee~~<br>~~ee ee~~<br>~~Se~~<br>~~D~~<br>~~nD~~|—<br>~~ee ~~<br>~~ee~~<br>~~(~~<br>~~I~~|0.9<br> ~~ee~~<br>~~ee~~<br>~~(~~<br>~~(US~~|—<br>~~I~~|—<br>~~ee~~<br>~~ee~~<br>~~I~~|UI<br>~~ee~~<br>~~ee~~|
|TTX-RISE-FALL<br>~~es~~<br>~~es~~<br>~~ae~~<br>~~a~~|Transmitter rise and fall time<br>~~ee ee~~<br>~~Se~~<br>~~D~~<br>~~nD~~<br>~~ee~~|—<br>~~ee ~~<br>~~(~~<br>~~I~~<br>~~ee Ge~~|0.15<br> ~~ee~~<br>~~(~~<br>~~(US~~<br>~~Ge~~|—<br>~~I~~<br>~~es~~|—<br>~~ee~~<br>~~I~~<br>~~ee~~|UI<br>~~ee~~<br>~~ee~~|
|TTX-EYE<br><br>~~es~~<br>~~ae~~<br>~~a~~<br>~~a~~|Transmitter Eye, including all<br>jitter sources<br>~~Se~~<br>~~D~~<br>~~nD~~<br>~~ee~~<br>~~ee~~|—<br>~~(~~<br>~~I~~<br>~~ee Ge~~<br>~~ee~~|0.75<br>~~(~~<br>~~(US~~<br>~~Ge~~<br>~~ee~~|—<br>~~I~~<br>~~es~~<br>~~ee~~|—<br>~~I~~<br>~~ee~~<br>~~ee~~|UI<br>~~ee~~<br>~~ee~~|
|TTX-DJ<br>~~ae~~<br>~~a~~<br>~~a~~<br>~~es~~|Tx deterministic jitter > 1.5<br>MHz<br>~~nD~~<br>~~ee ~~<br>~~ee~~<br>~~ee~~<br>|—<br>~~I~~<br> ~~ee Ge~~<br>~~ee~~<br>~~ee~~<br>|—<br>~~(US ~~<br>~~Ge ~~<br>~~ee~~<br>~~ee~~<br>|—<br> ~~I ~~<br> ~~es ~~<br>~~ee~~<br>~~ee~~<br>|0.15<br> ~~I~~<br> ~~ee~~<br>~~ee~~<br>~~ee~~<br>|UI<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>|
|TTX-RJ<br>~~a~~<br>~~es~~<br>~~ee~~|Tx RMS jitter < 1.5 MHz<br>~~ee~~<br>~~ee~~<br>~~nD~~<br>~~ee~~|—<br>~~ee ~~<br>~~ee~~<br>~~nD~~|—<br> ~~ee ~~<br>~~ee~~<br>~~nD~~|—<br> ~~ee ~~<br>~~ee~~<br>~~nD~~<br>~~ID~~|3<br> ~~ee~~<br>~~ee~~<br>~~nD~~|ps,<br>RMS<br>~~ee~~<br>~~ee~~<br>~~nD~~|
|TRF-MISMATCH<br>~~es~~<br>~~ee~~|Tx rise/fall time mismatch<br>~~ee~~<br>~~nD~~<br>~~ee~~|—<br>~~ee~~<br>~~nD~~|—<br>~~ee~~<br>~~nD~~|—<br>~~ee~~<br>~~nD~~<br>~~ID~~|0.1<br>~~ee~~<br>~~nD~~|UI<br>~~ee~~<br>~~nD~~|
|RLTX-DIFF<br>~~es ~~<br>~~ee~~|Tx Differential Return Loss,<br>including package and silicon<br>~~ee~~<br> ~~nD~~<br>~~ee~~|50 MHz < freq< 1.25 GHz<br>~~ee ~~<br>~~nD~~|10<br> ~~ee ~~<br>~~nD~~<br>~~Ge~~|—<br> ~~ee~~<br>~~nD~~<br>~~ID~~<br>~~es~~|—<br>~~ee~~<br>~~nD~~<br>~~es~~|dB<br>~~ee~~<br>~~nD~~|
|||1.25 GHz < freq< 2.5 GHz<br>~~rs~~|8<br>~~rs~~<br>~~Ge~~|—<br>~~ID~~<br>~~rs~~<br>~~es~~|—<br>~~rs~~<br>~~es~~|dB<br>~~rs~~|



© 2021-2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02102-1.7 

141 

**MachXO5-NX Family Data Sheet** 

|**Symbol**<br>~~es~~<br>~~ee~~|**Description**<br>~~nD I~~<br>~~ee~~|**Test Conditions**<br>~~I~~<br>~~ee~~|**Min**<br>~~(S~~<br>~~ee~~|**Typ**<br>~~es~~|**Max**<br>~~ee~~|**Unit**<br>~~ee~~|
|---|---|---|---|---|---|---|
|RLTX-CM<br>~~es~~<br>~~ee~~<br>~~Po~~|Tx Common Mode Return Loss,<br>including package and silicon<br>~~nD I~~<br>~~ee~~|50 MHz < freq < 2.5 GHz<br>~~I~~<br>~~ee~~|6<br>~~(S~~<br>~~ee~~|—<br>~~es~~|—<br>~~ee~~|dB<br>~~ee~~|
|ZTX-DIFF-DC<br>~~ee ~~<br>~~Po~~|DC differential Impedance<br> ~~ee~~|—<br>~~ee ~~|—<br> ~~ee ~~|—<br> ~~es ~~|120<br> ~~ee~~|Ω<br>~~ee~~|
|VTX-CM-AC-PP<br>~~Po~~<br>~~a ~~<br>~~a~~|Tx AC peak common mode<br>voltage, peak-peak<br> ~~eee~~<br>~~ee ee~~|—<br>~~eee~~<br>~~ee~~|—<br>~~eee~~<br>~~ee~~|—<br>~~eee~~<br>~~ee~~|150<br>~~eee~~<br>~~ee~~|mV,<br>p-p<br>~~eee~~<br>~~ee~~|
|ITX-SHORT<br>~~a~~<br>~~a~~|Transmitter short-circuit<br>current<br>~~ee ee~~<br>~~ee ee~~|—<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~|90<br>~~ee~~<br>~~ee~~|mA<br>~~ee~~<br>~~ee~~|
|VTX-DC-CM<br>~~a ~~<br>~~a~~<br>~~a~~|Transmitter DC common-mode<br>voltage<br> ~~ee ee~~<br>~~ee ee~~<br>~~ee ee~~|—<br>~~ee ~~<br>~~ee~~<br>~~ee~~|0<br> ~~ee ~~<br>~~ee~~<br>~~ee~~|—<br> ~~ee~~<br>~~ee~~<br>~~ee~~|1.2<br>~~ee~~<br>~~ee~~<br>~~ee~~|V<br>~~ee~~<br>~~ee~~<br>~~ee~~|
|VTX-IDLE-DIFF-DC<br>~~a ~~<br>~~a~~<br>~~a~~|Electrical Idle Output DC<br>voltage<br> ~~ee ee~~<br>~~ee ee~~<br>~~ee~~|—<br>~~ee ~~<br>~~ee~~<br>~~ee~~|0<br> ~~ee ~~<br>~~ee~~<br>~~ee~~|—<br> ~~ee~~<br>~~ee~~<br>~~ee~~|5<br>~~ee~~<br>~~ee~~<br>~~ee~~|mV<br>~~ee~~<br>~~ee~~<br>~~ee~~|
|VTX-IDLE-DIFF-AC-p<br>~~a ~~<br>~~a~~<br>~~a~~|Electrical Idle Differential<br>Outputpeak voltage<br> ~~ee ee~~<br>~~ee~~<br>~~ee~~|—<br>~~ee ~~<br>~~ee~~<br>~~ee~~|—<br> ~~ee ~~<br>~~ee~~<br>~~ee~~|—<br> ~~ee~~<br>~~ee~~<br>~~ee~~|20<br>~~ee~~<br>~~ee~~<br>~~eee~~|mV<br>~~ee~~<br>~~ee~~<br>~~eee~~|
|VTX-RCV-DETECT<br>~~a ~~<br>~~a~~<br>~~es~~|Voltage change allowed during<br>Receiver Detect<br> ~~ee ~~<br>~~ee~~<br>~~(GO~~|—<br> ~~ee ~~<br>~~ee~~<br>~~(GO~~|—<br> ~~ee ~~<br>~~ee~~<br>~~(GO~~|—<br> ~~ee~~<br>~~ee~~<br>~~(GO~~|600<br>~~ee~~<br>~~eee~~<br>~~(GO~~|mV<br>~~ee~~<br>~~eee~~<br>~~(GO~~|
|TTX-IDLE-MIN<br>~~a ~~<br>~~es~~<br>~~a~~|Min. time in Electrical Idle<br> ~~ee~~<br>~~(GO~~<br>~~ee ee~~|—<br>~~ee ~~<br>~~(GO~~<br>~~ee~~|20<br> ~~ee~~<br>~~(GO~~<br>~~ee~~|—<br>~~ee~~<br>~~(GO~~<br>~~ee~~|—<br>~~eee~~<br>~~(GO~~<br>~~ee~~|ns<br>~~eee~~<br>~~(GO~~<br>~~ee~~|
|TTX-IDLE-SET-TO-IDLE<br>~~es~~<br>~~a~~<br>~~a~~|Max. time from EI Order Set to<br>valid Electrical Idle<br>~~(GO~~<br>~~ee ee~~<br>~~ee~~|—<br>~~(GO~~<br>~~ee~~<br>~~ee~~|—<br>~~(GO~~<br>~~ee~~<br>~~ee~~|—<br>~~(GO~~<br>~~ee~~<br>~~ee~~|8<br>~~(GO~~<br>~~ee~~<br>~~ee~~|ns<br>~~(GO~~<br>~~ee~~<br>~~ee~~|
|TTX-IDLE-TO-DIFF-DATA<br>~~a~~<br>~~a~~|Max. time from Electrical Idle<br>to valid differential output<br>~~ee ee~~<br>~~ee~~|—<br>~~ee ~~<br>~~ee~~|—<br> ~~ee ~~<br>~~ee~~|—<br> ~~ee~~<br>~~ee~~|8<br>~~ee~~<br>~~ee~~|ns<br>~~ee~~<br>~~ee~~|
|**Receive2**<br>~~a~~<br>~~ee ee ee ee~~<br>~~ee~~<br>~~Pee~~<br>~~a~~<br>~~ee~~<br>~~eeee~~|||||||
|LTX-SKEW<br>~~Pee~~<br>~~a~~<br>~~es~~<br>~~a~~|Lane-to-Lane output skew<br>~~Pee~~<br>~~ee~~<br>~~ts~~|—<br>~~Pee~~<br>~~ee~~<br>~~ts~~|—<br>~~Pee~~<br>~~ee~~<br>~~ts~~<br>~~(US~~|—<br>~~Pee~~<br>~~ee~~<br>~~ts~~|500 + 4<br>UI<br>~~Pee~~<br>~~ee~~<br>~~ts~~|ps<br>~~Pee~~<br>~~ee~~<br>~~ts~~|
|UI<br>~~a~~<br>~~es~~<br>~~a~~<br>~~a~~|Unit Interval<br>~~ee~~<br>~~ts~~<br>~~ee~~|—<br>~~ee~~<br>~~ts~~<br>~~**ee**~~|199.94<br>~~ee~~<br>~~ts~~<br>~~(US~~<br>~~**ee**~~|200<br>~~ee ~~<br>~~ts~~<br>~~**ee**~~|200.06<br> ~~ee~~<br>~~ts~~<br>~~**ee**~~|ps<br>~~ee~~<br>~~ts~~<br>~~**ee**~~|
|VRX-DIFF-PP<br>~~es~~<br>~~a~~<br>~~a~~|Differential Rx peak-peak<br>voltage<br>~~ts~~<br>~~ee~~<br>~~ee~~|—<br>~~ts~~<br>~~**ee**~~|0.343<br>~~ts~~<br>~~(US~~<br>~~**ee**~~|—<br>~~ts~~<br>~~**ee**~~|1.2<br>~~ts~~<br>~~**ee**~~|V, p-p<br>~~ts~~<br>~~**ee**~~|
|TRX-RJ-RMS<br>~~a~~<br>~~ef~~|Receiver random jitter<br>tolerance(RMS)<br>~~ee~~<br>~~ee~~<br>~~ef~~|1.5 MHz – 100 MHz<br>Random noise<br>~~**ee** ~~<br>~~ee~~|—<br> ~~**ee**~~<br>~~ee~~|—<br>~~**ee**~~<br>~~ee~~|4.2<br>~~**ee**~~<br>~~ee~~|ps,<br>RMS<br>~~**ee**~~<br>~~ee~~|
|TRX-DJ<br>~~ee~~<br>~~ef~~<br>~~a~~|Receiver deterministic jitter<br>tolerance<br>~~ee~~<br>~~ee~~<br>~~ef~~|—<br>~~ee~~<br>~~ee~~<br>~~ff~~|—<br>~~ee~~<br>~~ee~~<br>~~ff~~|—<br>~~ee~~<br>~~ee~~<br>—+|88<br>~~ee~~<br>~~ee~~<br>+—+|ps<br>~~ee~~<br>~~ee~~<br>+|
|RLRX-DIFF<br>~~ee~~<br>~~ef~~<br>~~a~~|Receiver differential Return<br>Loss, package plus silicon<br>~~ee~~<br>~~ef~~|50 MHz < freq< 1.25 GHz<br>~~ee~~<br>~~ee~~<br>~~ff~~|10<br>~~ee~~<br>~~ee~~<br>~~ff~~|—<br>~~ee~~<br>~~ee~~<br>—+|—<br>~~ee~~<br>~~ee~~<br>+—+|dB<br>~~ee~~<br>~~ee~~<br>+|
|||1.25 GHz < freq< 2.5 GHz<br>~~ee~~<br>~~ff~~|8<br>~~ee~~<br>~~ff~~|—<br>~~ee~~<br>—+|—<br>~~ee~~<br>+—+|dB<br>~~ee~~<br>+|
|RLRX-CM<br>~~ef~~<br>~~a~~<br>~~es~~|Receiver common mode<br>Return Loss, package plus<br>silicon<br>~~ef~~|—<br>~~ee ~~<br>~~ff~~|6<br> ~~ee~~<br>~~ff~~|—<br>~~ee ~~<br> — +|—<br> ~~ee~~<br>+ — +|dB<br>~~ee~~<br>+|
|ZRX-DC<br>~~es~~|Receiver DC single ended<br>impedance|—|40|—|60|Ω|
|ZRX-HIGH-IMP-DC<br>~~es~~<br>~~ee~~|Receiver DC single ended<br>impedance when powered<br>down<br>~~ee~~|—<br>~~ee~~|200K<br>~~ee~~|—<br>~~ee~~|—<br>~~ee~~|Ω<br>~~ee~~|
|VRX-CM-AC-P3<br>~~es~~<br>~~ee~~<br>~~es~~|Rx AC peak common mode<br>voltage<br>~~ee~~<br>~~tn~~|—<br>~~ee~~<br>~~Ts~~|—<br>~~ee~~<br>~~(OS~~|—<br>~~ee~~<br>~~(OO~~|150<br>~~ee~~|mV,<br>peak<br>~~ee~~|
|VRX-IDLE-DET-DIFF-PP<br>~~ee~~<br>~~es~~<br>~~es~~|Electrical Idle Detect Threshold<br>~~ee~~<br>~~tn~~<br>~~ty~~|—<br>~~ee ~~<br>~~Ts~~<br>~~ns UD~~|65<br> ~~ee~~<br>~~(OS~~<br>~~UD~~|—<br>~~ee~~<br>~~(OO~~<br>~~UI~~|1753<br>~~ee~~|mv,pp<br>~~ee~~|
|LRX-SKEW<br>~~es~~<br>~~es~~|Receiver –lane-lane skew<br>~~tn~~<br>~~ty~~|—<br>~~Ts~~<br>~~ns UD~~|—<br>~~(OS ~~<br>~~UD~~|—<br> ~~(OO~~<br>~~UI~~|8|ns|



## **Notes:** 

1. Refer to PCI Express Base Specification Revision 3.0 Table 4.18 test condition and requirement for respective parameters. 

2. Refer to PCI Express Base Specification Revision 3.0 Table 4.24 test condition and requirement for respective parameters. 

3. Spec compliant requirement. 

© 2021-2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02102-1.7 

142 

**MachXO5-NX Family Data Sheet** 

## **4.28. Hardened SGMII Receiver Characteristics** 

## **4.28.1. SGMII Rx Specifications** 

Over recommended operating conditions. 

**Table 4.45. SGMII Rx** 

|**Symbol**|**Description**|**Test Conditions**|**Min**|**Typ**|**Max**|**Unit**|
|---|---|---|---|---|---|---|
|fDATA|SGMII Data Rate|—|—|1250|—|MHz|
|fREFCLK|SGMII Reference Clock Frequency (Data<br>Rate/10)|—|—|125|—|MHz|
|JTOL_Dj|Jitter Tolerance, Deterministic|Periodic jitter<br>< 300 kHz|—|—|0.11|UI|
|JTOL_Tj|Jitter Tolerance, Total|Periodic jitter<br>< 300 kHz|—|—|0.31|UI|
|Δf/f|Data Rate and Reference Clock Accuracy|—|–300|—|300|ppm|



## **Note:** 

1. JTOT can meet the following jitter mask specification: 0 to 3.5 kHz: 10 UI; 3.5 to 700 kHz: log-log slope 10 UI to 0.05 UI; above 700 kHz: 0.05 UI. 

## **4.29. sysCONFIG Port Timing Specifications** 

Over recommended operating conditions. 

**Table 4.46. sysCONFIG Port Timing Specifications** 

|**Symbol**<br>~~sD~~|**Parameter**<br>~~sD~~|**Device**<br>~~sD~~|**Min**<br>~~sD~~|**Typ.**<br>~~sD~~|**Max**<br>~~sD~~|**Unit**<br>~~sD~~|
|---|---|---|---|---|---|---|
|**Slave SPI/I2C/I3C POR / REFRESH Timing**<br>~~sD~~<br>~~Pe~~|||||||
|tMSPI_INH|Time during POR, from VCC, VCCAUX, VCCIO0or<br>VCCIO1(whichever is the last) pass POR trip<br>voltage, or REFRESH command executed,  to<br>pull PROGRAMN LOW to prevent entering<br>MSPI mode|—|—|—|1|µs|
|tACT_PROGRAMN_H<br>~~a~~|Minimum time driving PROGRAMN HIGH after<br>last activation clock|—|50|—|—|ns|
|tCONFIG_CCLK<br>~~a~~|Minimum time to start driving CCLK (SSPI) after<br>PROGRAMN HIGH|—|50|—|—|ns|
|tCONFIG_SCL<br>~~a~~|Minimum time to start driving SCL (I2C/I3C)<br>after PROGRAMN HIGH<br>|—<br>|50<br>|—<br>|—<br>|ns<br>|
|**PROGRAMN Configuration Timing**<br>~~aPR~~|||||||
|tPROGRAMN<br>~~PR~~<br>~~a Ge~~<br>~~es~~|PROGRAMN LOWpulse accepted<br>~~PR~~<br>~~Ge~~<br>~~GO~~|—<br>~~PR~~<br>~~Ge~~<br>~~GO~~|50<br>~~PR~~<br>~~Ge~~<br>~~GO~~|—<br>~~PR~~<br>~~Ge~~<br>~~GO~~|—<br>~~PR~~<br>~~Ge~~<br>~~GO~~|ns<br>~~PR~~<br>~~Ge~~<br>~~GO~~|
|tPROGRAMN_RJ<br>~~es~~<br>~~Do~~|PROGRAMN LOW pulse rejected<br>~~GO~~|—<br>~~GO~~<br>~~ee~~|—<br>~~GO~~<br>~~ee~~|—<br>~~GO~~<br>~~ee~~|25<br>~~GO~~<br>~~ee~~|ns<br>~~GO~~|
|tINIT_LOW<br>~~es~~<br>~~a Ge~~<br>~~Do~~|PROGRAMN LOW to INITN LOW<br>~~GO~~<br>~~Ge~~|—<br>~~GO~~<br>~~Ge~~<br>~~ee~~|—<br>~~GO~~<br>~~Ge~~<br>~~ee~~|—<br>~~GO~~<br>~~Ge~~<br>~~ee~~|100<br>~~GO~~<br>~~Ge~~<br>~~ee~~|ns<br>~~GO~~<br>~~Ge~~|
|tINIT_HIGH<br>~~Do~~|PROGRAMN LOW to INITN HIGH|—<br>~~ee~~|—<br>~~ee~~|—<br>~~ee~~|50<br>~~ee~~|µs|
|||—<br>~~ee~~|—<br>~~ee~~|—<br>~~ee~~|55<br>~~ee~~|µs|
|tDONE_LOW<br>~~Do~~<br>~~a eG~~|PROGRAMN LOW to DONE LOW<br>~~eG~~|—<br>~~ee~~<br>~~eG~~|—<br>~~ee~~<br>~~eG~~|—<br>~~ee~~<br>~~eG~~|2<br>~~ee~~<br>~~eG~~|µs<br>~~eG~~|
|tDONE_HIGH<br>~~Do~~<br>~~Ge~~|PROGRAMN HIGH to DONE HIGH<br>~~Ge~~|—<br>~~ee ~~<br>~~Ge~~|—<br> ~~ee ~~<br>~~Ge~~|—<br> ~~ee ~~<br>~~Ge~~|125<br> ~~ee~~<br>~~Ge~~|s<br>~~Ge~~|
|tIODISS<br>~~Ge~~<br>~~a ~~|PROGRAMN LOW to I/O Disabled<br>~~Ge~~<br> ~~a~~|—<br>~~Ge~~<br>~~G~~|50<br>~~Ge~~|—<br>~~Ge~~|—<br>~~Ge~~|ns<br>~~Ge~~|
|**Slave SPI**<br>~~pn~~|||||||
|fCCLK_W<br>~~pn~~<br>~~a~~|CCLK input clock frequency (For write<br>transaction)2<br>~~pn~~|—<br>~~pn~~|—<br>~~pn~~|—<br>~~pn~~|120<br>~~pn~~|MHz<br>~~pn~~|
|fCCLK_R<br>~~a~~<br>~~a~~|CCLK input clock frequency (For read<br>transaction)3<br>|—<br>|—<br>|—<br>|—4<br>|MHz<br>|
|tCCLKH<br>~~aGG~~|CCLK input clock pulse width HIGH<br>~~GG~~|—<br>~~GG~~|3.5<br>~~GG~~|—<br>~~GG~~|—<br>~~GG~~|ns<br>~~GG~~|



© 2021-2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02102-1.7 

143 

**MachXO5-NX Family Data Sheet** 

|**Symbol**<br>~~PO~~<br>~~a~~|**Parameter**<br>|**Device**<br>|**Min**<br><br>~~GG~~|**Typ.**<br><br>~~GG~~|**Max**<br>|**Unit**<br>|
|---|---|---|---|---|---|---|
|tCCLKL<br>~~POeG~~<br>~~a~~|CCLK input clockpulse width LOW<br>~~eG~~|—<br>~~eG~~|3.5<br>~~eG~~<br>~~GG~~|—<br>~~eG~~<br>~~GG~~|—<br>~~eG~~|ns<br>~~eG~~|
|tVMC_SLAVE<br>~~a~~<br>~~ee~~|Time from rising edge of INITN to Slave CCLK<br>driven<br>~~GG~~|—<br>~~GG~~|50<br>~~GG~~<br>~~GG~~|—<br>~~GG~~<br>~~GG~~|—<br>~~GG~~|ns<br>~~GG~~|
|tVMC_MASTER<br>~~ee~~<br>~~ee~~|CCLK input clock dutycycle<br>~~GG~~<br>~~GG~~|—<br>~~GG~~<br>~~GG~~|40<br>~~GG~~<br>~~GG~~|—<br>~~GG~~<br>~~GG~~|60<br>~~GG~~<br>~~GG~~|%<br>~~GG~~<br>~~GG~~|
|tSU_SSI<br>~~ee~~<br>~~ee~~<br>~~ee~~|SSI to CCLK setuptime<br>~~GG~~<br>~~GG~~<br>~~GG~~|—<br>~~GG~~<br>~~GG~~<br>~~GG~~|3.2<br>~~GG~~<br>~~GG~~<br>~~GG~~|—<br>~~GG~~<br>~~GG~~<br>~~GG~~|—<br>~~GG~~<br>~~GG~~<br>~~GG~~|ns<br>~~GG~~<br>~~GG~~<br>~~GG~~|
|tHD_SSI<br>~~ee~~<br>~~ee~~<br>~~ee~~|SSI to CCLK hold time<br>~~GG~~<br>~~GG~~<br>~~GG~~|—<br>~~GG~~<br>~~GG~~<br>~~GG~~|1.9<br>~~GG~~<br>~~GG~~<br>~~GG~~|—<br>~~GG~~<br>~~GG~~<br>~~GG~~|—<br>~~GG~~<br>~~GG~~<br>~~GG~~|ns<br>~~GG~~<br>~~GG~~<br>~~GG~~|
|tCO_SSO<br>~~ee~~<br>~~ee~~<br>~~ee~~|CCLK falling edge to valid SSO output<br>~~GG~~<br>~~GG~~<br>~~GG~~|—<br>~~GG~~<br>~~GG~~<br>~~GG~~|3.05<br>~~GG~~<br>~~GG~~<br>~~GG~~|—<br>~~GG~~<br>~~GG~~<br>~~GG~~|305<br>~~GG~~<br>~~GG~~<br>~~GG~~|ns<br>~~GG~~<br>~~GG~~<br>~~GG~~|
|tEN_SSO<br>~~ee~~<br>~~ee~~|CCLK falling edge to SSO output enabled<br>~~GG~~<br>~~GG~~|—<br>~~GG~~<br>~~GG~~|3.05<br>~~GG~~<br>~~GG~~|—<br>~~GG~~<br>~~GG~~|305<br>~~GG~~<br>~~GG~~|ns<br>~~GG~~<br>~~GG~~|
|tDIS_SSO<br>~~ee~~<br>~~GG~~<br>~~ee~~|CCLK fallingedge to SSO output disabled<br>~~GG~~<br>~~GG~~<br>~~GG~~|—<br>~~GG~~<br>~~GG~~<br>~~GG~~|3.05<br>~~GG~~<br>~~GG~~<br>~~GG~~|—<br>~~GG~~<br>~~GG~~<br>~~GG~~|305<br>~~GG~~<br>~~GG~~<br>~~GG~~|ns<br>~~GG~~<br>~~GG~~<br>~~GG~~|
|tHIGH_SCSN<br>~~ee~~<br>~~ee~~|SCSN HIGH time<br>~~GG~~<br>~~GG~~|—<br>~~GG~~<br>~~GG~~|74<br>~~GG~~<br>~~GG~~|—<br>~~GG~~<br>~~GG~~|—<br>~~GG~~<br>~~GG~~|ns<br>~~GG~~<br>~~GG~~|
|tSU_SCSN<br>~~ee~~<br>~~ee~~<br>~~ee~~|SCSN to CCLK setuptime<br>~~GG~~<br>~~GG~~<br>~~GG~~|—<br>~~GG~~<br>~~GG~~<br>~~GG~~|3.5<br>~~GG~~<br>~~GG~~<br>~~GG~~|—<br>~~GG~~<br>~~GG~~<br>~~GG~~|—<br>~~GG~~<br>~~GG~~<br>~~GG~~|ns<br>~~GG~~<br>~~GG~~<br>~~GG~~|
|tHD_SCSN<br>~~ee~~<br>~~ee~~|SCSN to CCLK hold time<br>~~GG~~<br>~~GG~~|—<br>~~GG~~<br>~~GG~~|1.6<br>~~GG~~<br>~~GG~~|—<br>~~GG~~<br>~~GG~~|—<br>~~GG~~<br>~~GG~~|ns<br>~~GG~~<br>~~GG~~|
|**I2C/I3C**<br>~~eeGG~~|||||||
|fSCL_I2C<br>~~a eG~~<br>~~ee~~|SCL input clock frequency for I2C<br>~~eG~~<br>~~GG~~|—<br>~~eG~~<br>~~GG~~|—<br>~~eG~~<br>~~GG~~|—<br>~~eG~~<br>~~GG~~|1<br>~~eG~~<br>~~GG~~|MHz<br>~~eG~~<br>~~GG~~|
|fSCL_I3C<br>~~a eG~~<br>~~ee~~<br>~~ee~~|SCL input clock frequency for I3C<br>~~eG~~<br>~~GG~~<br>~~GG~~|—<br>~~eG~~<br>~~GG~~<br>~~GG~~|—<br>~~eG~~<br>~~GG~~<br>~~GG~~|—<br>~~eG~~<br>~~GG~~<br>~~GG~~|12<br>~~eG~~<br>~~GG~~<br>~~GG~~|MHz<br>~~eG~~<br>~~GG~~<br>~~GG~~|
|tSCLH_I2C<br>~~ee~~<br>~~ee~~|SCL input clock pulse width HIGH for I2C<br>~~GG~~<br>~~GG~~|—<br>~~GG~~<br>~~GG~~|400<br>~~GG~~<br>~~GG~~|—<br>~~GG~~<br>~~GG~~|—<br>~~GG~~<br>~~GG~~|ns<br>~~GG~~<br>~~GG~~|
|tSCLL_I2C<br>~~ee~~<br>~~a~~<br>~~ee~~|SCL input clock pulse width LOW for I2C<br>~~GG~~<br>~~eG~~<br>~~GG~~|—<br>~~GG~~<br>~~eG~~<br>~~GG~~|400<br>~~GG~~<br>~~eG~~<br>~~GG~~|—<br>~~GG~~<br>~~eG~~<br>~~GG~~|—<br>~~GG~~<br>~~eG~~<br>~~GG~~|ns<br>~~GG~~<br>~~eG~~<br>~~GG~~|
|tSU_SDA_I2C<br>~~a ~~<br>~~ee~~|SDA to SCL setup time for I2C<br> ~~eG~~<br>~~GG~~|—<br>~~eG~~<br>~~GG~~|250<br>~~eG~~<br>~~GG~~|—<br>~~eG~~<br>~~GG~~|—<br>~~eG~~<br>~~GG~~|ns<br>~~eG~~<br>~~GG~~|
|tHD_SDA_I2C<br>~~ee~~<br>~~GG~~|SDA to SCL hold time for I2C<br>~~GG~~<br>~~GG~~|—<br>~~GG~~<br>~~GG~~|50<br>~~GG~~<br>~~GG~~|—<br>~~GG~~<br>~~GG~~|—<br>~~GG~~<br>~~GG~~|ns<br>~~GG~~<br>~~GG~~|
|tSU_SDA_I3C<br>~~a~~<br>~~ee~~|SDA to SCL setup time for I3C<br>~~eG~~<br>~~GG~~|—<br>~~eG~~<br>~~GG~~|30<br>~~eG~~<br>~~GG~~|—<br>~~eG~~<br>~~GG~~|—<br>~~eG~~<br>~~GG~~|ns<br>~~eG~~<br>~~GG~~|
|tHD_SDA_I3C<br>~~a ~~<br>~~ee~~|SDA to SCL hold time for I3C<br> ~~eG~~<br>~~GG~~|—<br>~~eG~~<br>~~GG~~|30<br>~~eG~~<br>~~GG~~|—<br>~~eG~~<br>~~GG~~|—<br>~~eG~~<br>~~GG~~|ns<br>~~eG~~<br>~~GG~~|
|tCO_SDA<br>~~ee~~<br>~~GG~~|SCL falling edge to valid SDA output<br>~~GG~~<br>~~GG~~|—<br>~~GG~~<br>~~GG~~|—<br>~~GG~~<br>~~GG~~|—<br>~~GG~~<br>~~GG~~|200<br>~~GG~~<br>~~GG~~|ns<br>~~GG~~<br>~~GG~~|
|tEN_SDA<br>~~a~~<br>~~ee~~|SCL falling edge to SDA output enabled<br>~~eG~~<br>~~GG~~|—<br>~~eG~~<br>~~GG~~|—<br>~~eG~~<br>~~GG~~|—<br>~~eG~~<br>~~GG~~|200<br>~~eG~~<br>~~GG~~|ns<br>~~eG~~<br>~~GG~~|
|tDIS_SDA<br>~~a ~~<br>~~ee~~|SCL falling edge to SDA output disabled<br> ~~eG~~<br>~~GG~~|—<br>~~eG~~<br>~~GG~~|—<br>~~eG~~<br>~~GG~~|—<br>~~eG~~<br>~~GG~~|200<br>~~eG~~<br>~~GG~~|ns<br>~~eG~~<br>~~GG~~|
|**Wake-Up Timing**<br>~~eeGG~~<br>~~pT~~|||||||
|tDONE_HIGH<br>~~pT~~<br>~~a~~|Last configuration clock cycle to DONE going<br>HIGH<br>~~pT~~<br>~~ee~~|—<br>~~pT~~<br>~~ee~~|—<br>~~pT~~<br>~~ee~~|—<br>~~pT~~<br>~~ee~~|60<br>~~pT~~<br>~~ee~~|µs<br>~~pT~~<br>~~ee~~|
|tFIO_EN1<br>~~a~~|User I/O enabled in Fast I/O Mode|—|—|31.104|—|M<br>cycles|
|tIOEN1<br>~~a a~~|Config clock to user I/O enabled<br>~~a~~|—<br>~~G~~|130|—|—|ns|



**Notes** : 

1. Based on 30k uncompressed/unauthenticated/default MCLK timing (3.5 MHz)/x1. Other permutations result in different values. 

2. Supported input clock frequency for bursting in configuration bitstream to the device. 

3. Supported input clock frequency for reading out data transactions from the device. 

4. Refer to the following equations to determine the supported input clock frequency for read transaction. Assumption: The skew between CCLK and SSO on board is zero. 

½ 𝐶𝐶𝐿𝐾 –  𝑡𝐶𝑂(𝑚𝑎𝑥) –  𝑇𝑠𝑢 >  0 

𝐶𝐶𝐿𝐾 >  2(𝑡𝐶𝑂(𝑚𝑎𝑥) +  𝑇𝑠𝑢) 

CCLK – Input clock period. fCCLK_R = 1/CCLK. 

tCO (max) – Equivalent to tCO_SSO or tEN_SSO max value. 

Tsu – Setup time requirement for host controller I/O. 

For customer that can only use single clock for read/write operation, the Fmax is limited by the Fmax for read operation. For example: tCO (max) = 30 ns and Tsu = 2 ns. 

𝐶𝐶𝐿𝐾 >  2(𝑡𝐶𝑂(𝑚𝑎𝑥) +  𝑇𝑠𝑢) 

𝐶𝐶𝐿𝐾 >  2(30 𝑛𝑠 +  2 𝑛𝑠) 

𝐶𝐶𝐿𝐾 >  64 𝑛𝑠 

© 2021-2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

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1 𝑓𝐶𝐶𝐿𝐾𝑅 = = 15.62𝑀𝐻𝑧 64 𝑛𝑠 

For the customer that wants to do the programming at 135 MHz or faster than Fmax for read operation: 

   - Have a mechanism in the host controller to switch between read clock and write clock for read/write transaction. For example, refer to SPI specification to switch between read and write clock by changing the SPI Baud Rate Register (SPIBR) if standard SPI controller is used as the host. 

   - Implementing a mechanism to adjust/calibrate the sampling clock edge when the valid data becomes available. 

5. Based on SLOW (default) slew rate control on Config output pins. 

**==> picture [476 x 96] intentionally omitted <==**

**----- Start of picture text -----**<br>
tINIT_HIGH tPROGRAM_H MSPI<br>Configuration<br>PROGRAMN<br>tPROGRAM_L SSPI/I2C/I3C<br>tIN ITL Configuration tINIT_HI GH Configuration<br>Error<br>INITN<br>tINIT_HIGH Restart<br>Configuration<br>Configuration<br>DONE Started<br>**----- End of picture text -----**<br>


tIN ITL = SRAM memory initialization period 

**Figure 4.14. Configuration Error Notification (2)** 

**==> picture [425 x 228] intentionally omitted <==**

**----- Start of picture text -----**<br>
REFRESH<br>Command<br>VCC/VCCAUX/<br>VCCIO0/VCCIO1<br>INITN<br>DONE<br>tMSPI_INH Slave Activation tACT_PROGRAMN_H<br>PROGRAMN<br>fCCLK tCONFIG_CCLK<br>CCLK<br>SSI<br>fSCL tACT_PROGRAMN_H<br>tCONFIG_SCL<br>SCL<br>eee nee AY NAV ACY ee RI<br>SDA<br>**----- End of picture text -----**<br>


**Figure 4.15. Slave SPI/I[2] C/I3C POR/REFRESH Timing** 

© 2021-2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

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**==> picture [455 x 573] intentionally omitted <==**

**----- Start of picture text -----**<br>
tPROGRAMN<br>PROGRAMN<br>tINIT_HIGH<br>tINIT_LOW<br>INITN<br>DONE tDONE_LOW tACT_PROGRAMN_H<br>ee<br>fCCLK tCONFIG_CCLK<br>CCLK<br>SSI<br>fSCL tACT_PROGRAMN_H<br>SCL tCONFIG_SCL<br>SDA<br>USER I/O<br>| )<br>Figure 4.16. Slave SPI/I [2] C/I3C PROGRAMN Timing<br>fCCLK<br>tCCLKH<br>CCLK<br>tCCLKL<br>tSU_SSI tHD_SSI<br>SSI<br>oy<br>tSU_SCSN tHD_SCSN<br>SCSN<br>py tHIGH_SCS N<br>tCO_SSO<br>——<br>SSO<br>> Ge ee,<br>tEN_SSO tDIS_SSO<br>SSO<br>ee<br>**----- End of picture text -----**<br>


**Figure 4.17. Slave SPI Configuration Timing** 

© 2021-2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

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**==> picture [455 x 542] intentionally omitted <==**

**----- Start of picture text -----**<br>
MachXO5-NX Family<br>Data Sheet<br>fSCL<br>tSCLH<br>SCL<br>tSCLL<br>tSU_SDA tHD_SDA<br>SDA (input)<br>tCO_SDA<br>SDA (output)<br>tDIS_SDA<br>tEN_SDA<br>SDA (output)<br>—<br>Figure 4.18. I [2] C /I3C Configuration Timing<br>CRESET_B<br>INITN<br>tDONE_HIGH Device Wake-Up<br>DONE<br>CONFIG<br>Starts<br>CCLK/SCL<br>tFIO_EN<br>USER I/O tIOEN<br>(FAST I/O)<br>tIOEN<br>USER I/O<br>nt<br>**----- End of picture text -----**<br>


## **Figure 4.19. Slave SPI/I[2] C/I3C Wake-Up Timing** 

## **4.30. JTAG Port Timing Specifications** 

Over recommended operating conditions. 

|**Symbol**<br>~~SSeS~~|**Parameter**<br>~~SSeS~~|**Min**<br>~~SSeS~~|**Typ. **<br>~~SSeS~~|**Max**<br>~~SSeS~~|**Units**<br>~~SSeS~~|
|---|---|---|---|---|---|
|fMAX<br>~~SSeS~~|TCK clock frequency<br>~~SSeS~~|—<br>~~SSeS~~|—<br>~~SSeS~~|25<br>~~SSeS~~|MHz<br>~~SSeS~~|
|tBTCPH<br>~~SSeS~~|TCK clockpulse width high<br>~~SSeS~~|20<br>~~SSeS~~|—<br>~~SSeS~~|—<br>~~SSeS~~|ns<br>~~SSeS~~|
|tBTCPL<br>~~SSeS~~|TCK clockpulse width low<br>~~SSeS~~|20<br>~~SSeS~~|—<br>~~SSeS~~|—<br>~~SSeS~~|ns<br>~~SSeS~~|
|tBTS<br>~~SSeS~~|TCK TAP setuptime<br>~~SSeS~~|5<br>~~SSeS~~|—<br>~~SSeS~~|—<br>~~SSeS~~|ns<br>~~SSeS~~|



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|**Symbol**|**Parameter**|**Min**|**Typ. **|**Max**|**Units**|
|---|---|---|---|---|---|
|tBTH|TCK TAP hold time|5|—|—|ns|
|tBTRF|TAP controller TDO rise/fall time1|1000|—|—|mV/ns|
|tBTCO|TAP controller fallingedge of clock to valid output|—|—|14|ns|
|tBTCODIS|TAP controller fallingedge of clock to valid disable|—|—|14|ns|
|tBTCOEN|TAP controller fallingedge of clock to valid enable|—|—|14|ns|
|tBTCRS|BSCAN test capture register setuptime|8|—|—|ns|
|tBTCRH|BSCAN test capture register hold time|25|—|—|ns|
|tBUTCO|BSCAN test update register, fallingedge of clock to valid output|—|—|25|ns|
|tBTUODIS|BSCAN test update register, fallingedge of clock to valid disable|—|—|25|ns|
|tBTUPOEN|BSCAN test update register, fallingedge of clock to valid enable|—|—|25|ns|



**Note:** 

1. Based on default I/O setting of slow slew rate. 

**==> picture [426 x 313] intentionally omitted <==**

**----- Start of picture text -----**<br>
TMS<br>TDI<br>tBTS tBTH<br>tBTCPH tBTCPL tBTCP<br>TCK<br>tBTCOEN tBTCO tBTCODIS<br>TDO V  dilaD aat V  dilaD aat<br>tBTCRH<br>tBTCRS<br>Data to be<br>Captured Data Captured<br>from I/O<br>tBTUPOEN tBUTCO tBTUODIS<br>Data to be<br>driven out V  dilaD aat V  dilaD aat<br>to I/O<br>**----- End of picture text -----**<br>


**Figure 4.20. JTAG Port Timing Waveforms** 

## **4.31. Switching Test Conditions** 

Figure 4.21 shows the output test load that is used for AC testing. The specific values for resistance, capacitance, voltage, and other test conditions are listed in Table 4.48. 

© 2021-2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

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**MachXO5-NX Family Data Sheet** 

**==> picture [203 x 138] intentionally omitted <==**

**----- Start of picture text -----**<br>
V T<br>R1<br>DUT Test Point<br>R2 CL*<br>: L<br>**----- End of picture text -----**<br>


*CL Includes Test Fixture and Probe Capacitance 

## **Figure 4.21. Output Test Load, LVTTL and LVCMOS Standards** 

**Table 4.48. Test Fixture Required Components, Non-Terminated Interfaces** 

|**Test Condition**|**R1**|**R2**|**CL**|**Timing Ref.**|**VT**|
|---|---|---|---|---|---|
|LVTTL and other LVCMOS settings (L ≥ H, H ≥ L)|||0 pF|LVCMOS 3.3 = 1.5 V|—|
|||||LVCMOS 2.5 = VCCIO/2|—|
|||||LVCMOS 1.8 = VCCIO/2|—|
|||||LVCMOS 1.5 = VCCIO/2|—|
|||||LVCMOS 1.2 = VCCIO/2|—|
|LVCMOS 2.5 I/O(Z ≥ H)||1 MΩ|0pF|VCCIO/2|—|
|LVCMOS 2.5 I/O(Z ≥ L)|1 MΩ||0pF|VCCIO/2|VCCIO|
|LVCMOS 2.5 I/O(H ≥ Z)||100|0pF|VOH– 0.10|—|
|LVCMOS 2.5 I/O(L ≥ Z)|100||0pF|VOL+ 0.10|VCCIO|



**Note** : Output test conditions for all other interfaces are determined by the respective standards. 

© 2021-2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

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**MachXO5-NX Family Data Sheet** 

## **5. Pinout Information** 

## **5.1. Signal Descriptions** 

**Table 5.1. Signal Descriptions** 

|**Signal Name**<br>~~De~~|**Bank**<br>~~De~~|**Type **<br>~~De~~|**Description**<br>~~De~~|
|---|---|---|---|
|**Power and GND**||||
|VSS<br>~~a~~|—|GND|Ground for internal FPGA logic and I/O|
|VSSSD<br>~~a~~|—<br>~~G~~|GND<br>~~G~~|Ground for the SERDES block.|
|VSSADC<br>~~a~~|—<br>~~De~~|GND<br>~~De~~|Ground for the ADC block.|
|VCC, VCCECLK|—|Power|Power supply pins for core logic. VCCis connected to 1.0 V (nom.)<br>supplyvoltage. Power On Reset(POR)monitors this supplyvoltage.|
|VCCAUXA|—|Power|Auxiliary power supply pin for internal analog circuitry. This supply is<br>connected to 1.8 V (nom.) supply voltage. POR monitors this supply<br>voltage.|
|VCCAUX|—|Power|Auxiliary power supply pin for I/O Bank 0, Bank 1, Bank 2, Bank 3, Bank<br>4, Bank 7, Bank 8 and Bank 9. This supply is connected to 1.8 V (nom.)<br>supply voltage, and is used for generating stable drive current for the<br>I/O.|
|VCCAUXHx|—|Power|Auxiliary power supply pin for I/O Bank 5 and Bank 6. This supply is<br>connected to 1.8 V (nom.) supply voltage, and is used for generating<br>stable current for the differential input comparators.|
|VCCIOx|0-9|Power|Power supply pins for I/O bank x.<br>LFMXO5-25:<br>Bank 1: 3.3 V only<br>Banks 0, 2, 3, 4, 7, 8, 9: 1.2 V, 1.35 V, 1.5 V, 1.8 V, 2.5 V, and 3.3 V<br>Banks 5, 6: 1.0 V, 1.2 V, 1.35 V, 1.5 V, and 1.8 V<br>LFMXO5-55T/100T:<br>Bank 0: 3.3 V only<br>Banks 1, 2, 6, 7: 1.2 V, 1.35 V, 1.5 V, 1.8 V, 2.5 V, and 3.3 V<br>Banks 3, 4, 5: 1.0 V, 1.2 V, 1.35 V, 1.5 V, and 1.8 V<br>There are dedicated and shared configuration pins in different banks as<br>follows:<br>•<br>LFMXO5-25: Banks 1 and 2;<br>•<br>LFMXO5-55T/100T: Banks 0 and 1.<br>POR monitors these banks supplyvoltages.|
|VCCADC18|—|Power|1.8 V(nom.) power supplyfor the ADC block.|
|VCCSDx<br>~~eG~~|—<br>~~eG~~|Power<br>~~eG~~|1.0 V(nom.) power supplyfor the SERDES block.<br>~~eG~~|
|VCCSDCK<br>~~eG~~<br>~~a~~|—<br>~~eG~~<br>~~G~~|Power<br>~~eG~~<br>~~G~~|1.0 V(nom.) power supplyfor SERDES clock buffer.<br>~~eG~~|
|VCCPLLSDx<br>~~a~~<br>~~a~~|—<br>~~G~~<br>~~G~~|Power<br>~~G~~<br>~~G~~|1.8 V(nom.) power supplyfor the PLL in the SERDES block.|
|VCCAUXSDQx<br>~~a~~<br>~~Ge~~|—<br>~~G~~<br>~~Ge~~|Power<br>~~G~~<br>~~Ge~~|1.8 V(nom.)auxiliary power supplyfor the SERDES block.<br>~~Ge~~|
|**Dedicated Pins**||||
|**Dedicated Configuration I/O Pin**||||
|JTAG_EN|2/1|Input|LVCMOS input pin. This input selects the JTAG shared GPIO to be used<br>for JTAG<br>0 = GPIO<br>1 = JTAG<br>On Bank 2 for MachXO5-NX 25 devices<br>On Bank 1 for MachXO5-NX 55T/100T devices|
|**Dedicated ADC I/O Pins**||||
|ADC_REF[0, 1]<br>~~a~~|—|Input|ADC reference voltage, for each of the 2 ADC converters. If not used,<br>tie to ground.|



All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

© 2021-2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. 

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|**Signal Name**|**Bank**|**Type **|**Description**|
|---|---|---|---|
|ADC_DP/N[0, 1]|—|Input|Dedicated ADC input pairs, for each of the 2 ADC converters. If not|
||||used, tie to ground.|
|**Misc Pins**||||
|NC|—|—|No connect.|
|RESERVED|—|—|This pin is reserved and should not be connected to anything on the|
|**General Purpose I/O Pins**||||
|P[T/B/L/R] [Number]_[A/B]|Top,|Input,|Programmable User I/O:|
||Bottom,|Output,|[T/B/L/R] indicates the package pin/ball is in T (Top), B (Bottom), L|
||Left,|Bi-Dir|(Left), or R (Right) edge of the device.|
||Right||[Number] identifies the PIO [A/B] pair.|
||||[A/B] shows the package pin/ball is A or B signal in the pair. PIO A and|
||||PIO B are grouped as a pair.|
||||Each A/B pair in the bottom banks supports true differential input and|
||||output buffers.   When configured as differential input, differential|
||||termination of 100 Ω can be selected.|
||||Each A/B pair in the top, left and right banks does not support true|
||||differential input or output buffer.  It supports all single-ended inputs|
||||and outputs, and can be used for emulated differential output buffer.|
||||Some of these user-programmable I/O are used during configuration,|
||||depending on the configuration mode. You need to make appropriate|
||||connection on the board to isolate the 2 different functions|
||||before/after configuration.|
||||Some of these user-programmable I/O are shared with special function|
||||pins. These pins, when not used as special purpose pins, can be|
||||programmed as I/O for user logic.|
||||During configuration the user-programmable I/O are tri-stated with an|
||||internal weak pull-down resistor enabled. If any pin is not used (or not|
||||bonded to a package pin), it is tri-stated and default to have weak pull-|
||||down enabled after configuration.|



## **Shared Configuration Pins[1, 2 ]** 

**1. These pins can be used for configuration during configuration mode. When configuration is completed, these pins can be used as GPIO, or shared function in GPIO. When these pins are used in dual function, you need to isolate the signal paths for the dual functions on the board.** 

**2. The pins used are defined by the configuration modes detected. Slave SPI or I[2] C/I3C modes are detected during slave activation. Pins that are not used in the configuration mode selected are tri-stated during configuration, and can connect directly as GPIO in user’s function.** 

|PRxxx /SDA/USER_SDA|Right|Input,|Configuration:|
|---|---|---|---|
|||Output,|I2C/I3C Mode: SDA signal|
|||Bi-Dir|User Mode:|
||||PRxxx: GPIO|
||||User_SDA: SDA signal for I2C/I3C interface|
|PRxxx /SCL/USER_SCL|Right|Input,|Configuration:|
|||Output,|I2C/I3C Mode: SCL signal|
|||Bi-Dir|User Mode:|
||||PRxxx: GPIO|
||||User_SDA: SCL signal for I2C/I3C interface|
|PRxxx/TDO/SSO|Right|Input,|Configuration:|
|||Output,|Slave SPI Mode: Slave Serial Output|
|||Bi-Dir|User Mode:|
||||PRxxx: GPIO|
||||TDO: When JTAG_EN = 1, used as TDO signal for JTAG|



© 2021-2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02102-1.7 

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**MachXO5-NX Family Data Sheet** 

|**Signal Name**|**Bank**|**Type **|**Description**|
|---|---|---|---|
|PRxxx/TDI/SSI|Right|Input,<br>Output,<br>Bi-Dir|Configuration:<br>Slave SPI Mode: Slave Serial Input<br>User Mode:<br>PRxxx: GPIO<br>TDI: When JTAG_EN = 1, used as TDI signal for JTAG|
|PRxxx/TMS/SCSN|Right|Input,<br>Output,<br>Bi-Dir|Configuration:<br>Slave SPI Mode: Slave Chip Select<br>User Mode:<br>PRxxx: GPIO<br>TMS: When JTAG_EN = 1,used as TMS signal for JTAG|
|PRxxx/TCK/SCLK|Right|Input,<br>Output,<br>Bi-Dir|Configuration:<br>Slave SPI Mode: Slave Clock Input<br>User Mode:<br>PRxxx: GPIO<br>TCK: When JTAG_EN = 1,used as TCK signal for JTAG|
|PTxxx/MCSNO|Top|Input,<br>Output,<br>Bi-Dir|Configuration:<br>Flow-through Daisy Chain Mode: Chip Select Output<br>User Mode:<br>PTxxx: GPIO|
|PTxxx/PROGRAMN|Top|Input,<br>Output,<br>Bi-Dir|Configuration:<br>PROGRAMN: Initiate configuration sequence when asserted LOW.<br>User Mode:<br>PTxxx: GPIO|
|PTxxx/INITN|Top|Input,<br>Output,<br>Bi-Dir|Configuration:<br>INITN: Open Drain I/O pin. This signal is driven to LOW when<br>configuration sequence is started, to indicate the device is in<br>initialization state. This signal is released after initialization is<br>completed, and the configuration download can start. You can keep<br>drive this signal LOW to delay configuration download to start.<br>User Mode:<br>PTxxx: GPIO|
|PTxxx/DONE|Top|Input,<br>Output,<br>Bi-Dir|Configuration:<br>DONE: Open Drain I/O pin. This signal is driven to LOW during<br>configuration time. It is released to indicate the device has completed<br>configuration. You can keep drive this signal LOW to delay the device to<br>wake up from configuration.<br>User Mode:<br>PTxxx: GPIO|
|**Shared User GPIO Pins1, 2, 3, 4**<br>**1. Shared User GPIO pins are pins that can be used as GPIO, or functional pins that connect directly to specific functional**<br>**blocks, when device enters into User Mode.**<br>**2.**<br>**Declaring on assigning the pin as GPIO or specific functional pin is done by configuration bitstream, except JTAG pins.**<br>**3.**<br>**JTAG pins are controlled by JTAG_EN signal. When JTAG_EN = 1, the pins are used for JTAG interface. When JTAG = 0, the**<br>**pins are used as GPIO or specific functional pin defined by configuration bitstream.**<br>**4.**<br>**Refer to package pin file.**||||
|**Shared JTAG Pins**||||
|PRxxx/TDO/ yyyy|Right|Input,<br>Output,<br>Bi-Dir|User Mode:<br>PRxxx: GPIO<br>TDO: When JTAG_EN = 1, used as TDO signal for JTAG<br>yyyy: Other possible selectable specific functional|



## **Shared User GPIO Pins[1, 2, 3, 4 ]** 

**1. Shared User GPIO pins are pins that can be used as GPIO, or functional pins that connect directly to specific functional blocks, when device enters into User Mode.** 

**2. Declaring on assigning the pin as GPIO or specific functional pin is done by configuration bitstream, except JTAG pins.** 

**3. JTAG pins are controlled by JTAG_EN signal. When JTAG_EN = 1, the pins are used for JTAG interface. When JTAG = 0, the pins are used as GPIO or specific functional pin defined by configuration bitstream.** 

**4. Refer to package pin file.** 

## **Shared JTAG Pins** 

PRxxx/TDO/ yyyy Right Input, User Mode: Output, PRxxx: GPIO Bi-Dir TDO: When JTAG_EN = 1, used as TDO signal for JTAG yyyy: Other possible selectable specific functional 

© 2021-2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02102-1.7 

152 

**MachXO5-NX Family Data Sheet** 

|**Signal Name**|**Bank**|**Type **|**Description**|
|---|---|---|---|
|PRxxx/TDI/yyyy|Right|Input,<br>Output,<br>Bi-Dir|User Mode:<br>PRxxx: GPIO<br>TDI:  When JTAG_EN = 1, used as TDI signal for JTAG<br>yyyy: Other possible selectable specific functional|
|PRxxx/TMS/ yyyy|Right|Input,<br>Output,<br>Bi-Dir|User Mode:<br>PRxxx: GPIO<br>TMS: When JTAG_EN = 1, used as TMS signal for JTAG<br>yyyy: Other possible selectable specific functional|
|PRxxx/TCK/ yyyy|Right|Input,<br>Output,<br>Bi-Dir|User Mode:<br>PRxxx: GPIO<br>TCK: When JTAG_EN = 1, used as TCK signal for JTAG<br>Yyyy: Other possible selectable specific functional|
|**Shared CLOCK Pins1**<br>**1.**<br>**Some PCLK pins can also be used as GPLL reference clock input pin. Refer tosysCLOCK PLL/DLL Design and User Guide for**<br>**Nexus Platform (FPGA-TN-02095). **||||
|PBxxx/PCLK[T,C][X-Y]_[0-<br>3]/yyyy|Bottom|Input,<br>Output,<br>Bi-Dir|User Mode:<br>PBxxx: GPIO<br>PCLK: Primary Clock or GPLL Refclk signal<br>[T,C] = True/Complement when using differential signaling<br>[0-3] Up to 4 signals in the bank<br>yyyy: Other possible selectable specific functional|
|PTxxx/PCLKT[0,1]_[ X-Y]/yyyy|Top|Input,<br>Output,<br>Bi-Dir|User Mode:<br>PTxxx: GPIO<br>PCLKT: Primary Clock or GPLL Refclk signal (Only Single Ended)<br>[0-1] Up to 2 signals in the bank<br>yyyy: Other possible selectable specific functional|
|PRxxx/PCLKT[X-Y]_[0-2]/yyyy|Right|Input,<br>Output,<br>Bi-Dir|User Mode:<br>PRxxx: GPIO<br>PCLKT: Primary Clock or GPLL Refclk signal (Only Single Ended)<br>[0-2] Up to 3 signals in the bank<br>yyyy: Other possible selectable specific functional|
|PLxxx/PCLKT[X-Y]_[0-2]/yyyy|Left|Input,<br>Output,<br>Bi-Dir|User Mode:<br>PLxxx:  GPIO<br>PCLKT:  Primary Clock or GPLL Refclk signal (Only Single Ended)<br>[0-2] Up to 3 signals in the bank<br>yyyy: Other possible selectable specific functional|
|PBxxx/LRC_GPLL[T,C]_IN/yyyy|Bottom|Input,<br>Output,<br>Bi-Dir|User Mode:<br>PBxxx: GPIO<br>LRC_GPLL: Lower Right GPLL Refclk signal (PLLCK)<br>[T,C] = True/Complement when using differential signaling<br>yyyy: Other possible selectable specific functional|
|PLxxx/ULC_GPLLT_IN/yyyy|Left|Input,<br>Output,<br>Bi-Dir|User Mode:<br>PLxxx: GPIO<br>ULC_GPLL: Upper Left GPLL Refclk signal (Only Single Ended) (PLLCK)<br>yyyy: Other possible selectable specific functional|



© 2021-2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02102-1.7 

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**MachXO5-NX Family Data Sheet** 

|**Signal Name**|**Bank**|**Type **|**Description**|
|---|---|---|---|
|**Shared VREF Pins**||||
|PBxxx/VREF[5,6]_[1-2]/yyyy|Bottom|Input,<br>Output,<br>Bi-Dir|User Mode:<br>PBxxx: GPIO<br>VREF: Reference Voltage for DDR memory function<br>[1-2] Up to VREFs for each bank<br>yyyy: Other possible selectable specific functional|
|**Shared ADC Pins**||||
|PBxxx/ADC_C[P,N]nn/yyyy|Bottom|Input,<br>Output,<br>Bi-Dir|User Mode:<br>PBxxx: GPIO<br>ADC_C: ADC Channel Inputs<br>[P,N] = Positive or Negative Input<br>nn = ADC Channel number (0 – 15)<br>yyyy: Other possible selectable specific functional|
|**Shared Comparator Pins**||||
|PBxxx/COMP[1-3][P,N]/yyyy|Bottom|Input,<br>Output,<br>Bi-Dir|User Mode:<br>PBxxx: GPIO<br>COMP: Differential Comparator Input<br>[P,N] = Positive or Negative Input<br>[1-3] = Input to Comparators 1-3<br>yyyy: Other possible selectable specific functional|
|**Shared SGMII Pins**||||
|PBxxx/SGMII_RX[P,N][0-<br>1]/yyyy|Bottom|Input,<br>Output,<br>Bi-Dir|User Mode:<br>PBxxx: GPIO<br>SGMII_RX: Differential SGMII RX Inputs<br>[P,N] = Positive or Negative Input<br>[0-1] = Input to SGMII RX0 or RX1<br>yyyy: Other possible selectable specific functional|



**Note:** Not all signals are available as external pins in all packages. Refer to the Pinout List file for various package details. 

© 2021-2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02102-1.7 

154 

**MachXO5-NX Family Data Sheet** 

## **5.2. Pin Information Summary** 

**Table 5.2. Pin Information Summary** 

|**Pin**<br>~~ee~~|**Pin**<br>~~ee~~|**LFMXO5-25**<br>~~ee~~<br>~~esee~~<br>~~es~~|**LFMXO5-25**<br>~~ee~~<br>~~esee~~<br>~~es~~|**LFMXO5-55T**<br>~~ee~~<br>~~ee~~|**LFMXO5-100T**<br>~~ee~~<br>~~eee~~|
|---|---|---|---|---|---|
|||**256 BBG**<br>~~ee~~<br>~~es~~<br>~~es~~|**400 BBG**<br>~~ee~~<br>~~ee~~|**400 BBG**<br>~~ee~~<br>~~ee~~|**400 BBG**<br>~~ee~~<br>~~eee~~|
|**User I/O Pins**<br>~~es ee ee eee~~<br>~~es~~<br>~~|~~<br>~~O~~||||||
|General Purpose<br>Inputs/Outputs per<br>Bank|Bank 0<br>~~ee~~|24<br>~~ee~~|40<br>~~ee~~<br>~~O~~|18<br>~~ee~~|18<br>~~ee~~|
||Bank 1<br>~~sO~~|32<br>~~sO~~|36<br>~~O~~<br>~~sO~~|39<br>~~sO~~|39<br>~~sO~~|
||Bank 2<br>~~sO~~|23<br>~~sO~~|31<br>~~sO~~|32<br>~~sO~~|32<br>~~sO~~|
||Bank 3<br>~~Ge~~|16<br>~~Ge ~~|32<br> ~~GO~~|48<br>~~GO~~|48<br>~~GO~~|
||Bank 4<br>~~GG~~|12<br>~~GG~~|24<br>~~GG~~|48<br>~~GG~~|48<br>~~GG~~|
||Bank 5<br>~~GG~~|20<br>~~GG~~|24<br>~~GG~~|36<br>~~GG~~|36<br>~~GG~~|
||Bank 6<br>~~GG~~|20<br>~~GG~~|24<br>~~GG~~|32<br>~~GG~~|32<br>~~GG~~|
||Bank 7<br>~~eG~~|12<br>~~eG~~|24<br>~~eG~~|38<br>~~eG~~|38<br>~~eG~~|
||Bank 8<br>~~sO~~|16<br>~~sO~~|32<br>~~sO~~|0<br>~~sO~~|0<br>~~sO~~|
||Bank 9<br>~~fe~~|24<br>~~fe~~|32<br>~~fe~~|0<br>~~fe~~|0<br>~~fe~~|
|Total Single-Ended User I/O<br>~~GG~~||199<br>~~GG~~|299<br>~~GG~~|291<br>~~GG~~|291<br>~~GG~~|
|Differential Input/<br>Output Pairs|Bank 0<br>~~a~~|12<br>|20<br>|9<br>|9<br>|
||Bank 1<br>~~aee~~|16<br>~~ee~~|18<br>~~ee~~|19<br>~~ee~~|19<br>~~ee~~|
||Bank 2<br>~~ee~~<br>~~ee~~|11<br>~~ee~~<br>~~ee~~|15<br>~~ee~~<br>~~ee~~|16<br>~~ee~~<br>~~ee~~|16<br>~~ee~~<br>~~ee~~|
||Bank 3<br>~~ee~~<br>~~ee~~|8<br>~~ee~~<br>~~ee~~|16<br>~~ee~~<br>~~ee~~|24<br>~~ee~~<br>~~ee~~|24<br>~~ee~~<br>~~ee~~|
||Bank 4<br>~~ee~~<br>~~ee~~|6<br>~~ee~~<br>~~ee~~|12<br>~~ee~~<br>~~ee~~|24<br>~~ee~~<br>~~ee~~|24<br>~~ee~~<br>~~ee~~|
||Bank 5<br>~~ee~~<br>~~eG~~|10<br>~~ee~~<br>~~eG~~|12<br>~~ee~~<br>~~eG~~|18<br>~~ee~~<br>~~eG~~|18<br>~~ee~~<br>~~eG~~|
||Bank 6<br>~~eG~~|10<br>~~eG~~|12<br>~~eG~~|16<br>~~eG~~|16<br>~~eG~~|
||Bank 7<br>~~eG~~|6<br>~~eG~~|12<br>~~eG~~|19<br>~~eG~~|19<br>~~eG~~|
||Bank 8<br>~~eG~~|8<br>~~eG~~|16<br>~~eG~~|0<br>~~eG~~|0<br>~~eG~~|
||Bank 9<br>~~Ce~~|12<br>~~Ce~~|16<br>~~Ce~~|0<br>~~Ce~~|0<br>~~Ce~~|
|Total Differential I/O<br>~~De~~||99<br>~~De~~|149<br>~~De~~|145<br>~~De~~|145<br>~~De~~|
|**Power Pins**<br>~~De~~<br>~~Rn~~<br>~~OO~~||||||
|VCC,VCCECLK<br>~~Rn~~<br>~~eG~~||4<br>~~Rn~~<br>~~eG~~|6<br>~~Rn~~<br>~~eG~~<br>~~OO~~|10<br>~~Rn~~<br>~~eG~~<br>~~OO~~|10<br>~~Rn~~<br>~~eG~~|
|VCCAUXA<br>~~eG~~<br>~~GG~~||2<br>~~eG~~<br>~~GG~~|2<br>~~eG~~<br>~~OO~~<br>~~GG~~|1<br>~~eG~~<br>~~OO~~<br>~~GG~~|1<br>~~eG~~<br>~~GG~~|
|VCCAUX<br>~~GG~~||2<br>~~GG~~|3<br>~~GG~~|2<br>~~GG~~|2<br>~~GG~~|
|VCCAUXHx<br>~~GG~~||2<br>~~GG~~|2<br>~~GG~~|3<br>~~GG~~|3<br>~~GG~~|
|VCCAUXSDQx<br>~~GO~~<br>~~a~~||0<br>~~GO~~<br>|0<br>~~GO~~<br>|1<br>~~GO~~<br>|1<br>~~GO~~<br>|
|VCCIO<br>~~a~~|Bank 0<br>~~a~~|2<br>|3<br>|1<br>|1<br>|
||Bank 1<br>~~aeG~~|2<br>~~eG~~|3<br>~~eG~~|2<br>~~eG~~|2<br>~~eG~~|
||Bank 2<br>~~eG~~<br>~~eG~~|2<br>~~eG~~<br>~~eG~~|2<br>~~eG~~<br>~~eG~~|1<br>~~eG~~<br>~~eG~~|1<br>~~eG~~<br>~~eG~~|
||Bank 3<br>~~eG~~<br>~~eG~~|1<br>~~eG~~<br>~~eG~~|2<br>~~eG~~<br>~~eG~~|3<br>~~eG~~<br>~~eG~~|3<br>~~eG~~<br>~~eG~~|
||Bank 4<br>~~eG~~<br>~~eG~~<br>~~es~~|1<br>~~eG~~<br>~~eG~~|2<br>~~eG~~<br>~~eG~~|3<br>~~eG~~<br>~~eG~~|3<br>~~eG~~<br>~~eG~~|
||Bank 5<br>~~eG~~<br>~~es~~|2<br>~~eG~~|2<br>~~eG~~|2<br>~~eG~~|2<br>~~eG~~|
||Bank 6<br>~~es~~<br>~~eG~~|2<br>~~eG~~|2<br>~~eG~~|1<br>~~eG~~|1<br>~~eG~~|
||Bank 7<br>~~eG~~|1<br>~~eG~~|2<br>~~eG~~|2<br>~~eG~~|2<br>~~eG~~|
||Bank 8<br>~~eG~~|1<br>~~eG~~|2<br>~~eG~~|0<br>~~eG~~|0<br>~~eG~~|
||Bank 9<br>~~GG~~|2<br>~~GG~~|2<br>~~GG~~|0<br>~~GG~~|0<br>~~GG~~|
|VCCSDx<br>~~Ge~~||0<br>~~Ge~~|0<br>~~GC~~|3<br>~~GC~~|3<br>~~GC~~|
|VCCPLLSDx<br>~~Ge~~<br>~~GC~~||0<br>~~Ge~~<br>~~GC~~|0<br>~~GC~~<br>~~GC~~|2<br>~~GC~~<br>~~GC~~|2<br>~~GC~~<br>~~GC~~|
|VCCADC18<br>~~GC~~<br>~~GG~~||1<br>~~GC~~<br>~~GG~~|1<br>~~GC~~<br>~~GG~~|1<br>~~GC~~<br>~~GG~~|1<br>~~GC~~<br>~~GG~~|
|Total Power Pins<br>~~pf~~||27<br>~~pf~~|36<br>~~pf~~|38<br>~~pf~~|38<br>~~pf~~|
|**GND Pins**<br>~~|~~||||||
|Vss<br>~~eG~~||22<br>~~eG~~|30<br>~~GG~~|23<br>~~GG~~|23<br>~~GG~~|
|VSSADC<br>~~CO~~||1<br>~~CO~~|1<br>~~CO~~<br>~~OO~~|1<br>~~CO~~<br>~~OO~~|1<br>~~CO~~|
|VSSSDQ<br>~~CO~~<br>~~eG~~||0<br>~~CO~~<br>~~eG~~|0<br>~~CO~~<br>~~eG~~<br>~~OO~~<br>~~FO~~|22<br>~~CO~~<br>~~eG~~<br>~~OO~~<br>~~FO~~|22<br>~~CO~~<br>~~eG~~|
|Total GND Pins<br>~~eG~~<br>~~eG~~||23<br>~~eG~~<br>~~eG~~|31<br>~~eG~~<br>~~OO~~<br>~~eG~~<br>~~FO~~|46<br>~~eG~~<br>~~OO~~<br>~~eG~~<br>~~FO~~|46<br>~~eG~~<br>~~eG~~|



© 2021-2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02102-1.7 

155 

**MachXO5-NX Family Data Sheet** 

|**Pin**<br>~~ee~~|**Pin**<br>~~ee~~|**LFMXO5-25**<br>~~ee~~<br>~~ce~~~~**e**e~~|**LFMXO5-25**<br>~~ee~~<br>~~ce~~~~**e**e~~|**LFMXO5-55T**<br>~~ee~~<br>~~ee~~|**LFMXO5-100T**<br>~~ee~~<br>~~eee~~|
|---|---|---|---|---|---|
|||**256 BBG**<br>~~ee~~<br>~~ce~~<br>~~es~~|**400 BBG**<br>~~ee~~<br>~~**e**e~~<br>~~es~~|**400 BBG**<br>~~ee~~<br>~~ee~~<br>~~es~~|**400 BBG**<br>~~ee~~<br>~~eee~~<br>~~es~~|
|**Dedicated Pins**<br>~~ce ~~~~**e**e~~<br>~~ee eee~~<br>~~R~~||||||
|Dedicated ADC Channels(pairs)<br>~~GG~~||2<br>~~GG~~|2<br>~~GG~~|2<br>~~GG~~|2<br>~~GG~~|
|Dedicated ADC Reference Voltage Pins<br>~~a~~||2<br>~~GG~~|2<br>~~GG~~|2<br>~~GG~~|2<br>~~GG~~|
|Dedicated SERDES Pins<br>~~Ga~~||0<br>~~Ga~~|0<br>~~Fe~~|18<br>~~Fe~~|18<br>~~Fe~~|
|**Dedicated Misc Pins**<br>~~RT~~||||||
|JTAGEN<br>~~GG~~||1<br>~~GG~~|1<br>~~GG~~<br>~~GO~~|1<br>~~GG~~<br>~~GO~~|1<br>~~GG~~|
|NC<br>~~eG~~||0<br>~~eG~~|27<br>~~eG~~<br>~~GO~~|0<br>~~eG~~<br>~~GO~~|0<br>~~eG~~|
|RESERVED<br>~~GG~~||0<br>~~GG~~|0<br>~~GO~~<br>~~GG~~|0<br>~~GO~~<br>~~GG~~|0<br>~~GG~~|
|Total Dedicated Pins<br>~~Ge~~||13<br>~~Ge~~|34<br>~~FG~~|25<br>~~FG~~|25<br>~~FG~~|
|**Shared Pins**<br>~~ET~~<br>~~G~~||||||
|Shared Configuration<br>Pins|Bank 0<br>~~fe~~|0<br>~~fe~~|0<br>~~fe~~<br>~~G~~|4<br>~~fe~~|4<br>~~fe~~|
||Bank 1<br>~~eG~~|4<br>~~eG~~|4<br>~~G~~<br>~~eG~~|6<br>~~eG~~|6<br>~~eG~~|
||Bank 2<br>~~sO~~|6<br>~~sO~~|6<br>~~sO~~|0<br>~~sO~~|0<br>~~sO~~|
||Bank 3<br>~~eG~~|0<br>~~eG~~|0<br>~~eG~~|0<br>~~eG~~|0<br>~~eG~~|
||Bank 4<br>~~eG~~|0<br>~~eG~~|0<br>~~eG~~|0<br>~~eG~~|0<br>~~eG~~|
||Bank 5<br>~~a~~|0<br>|0<br>|0<br>|0<br>|
||Bank 6<br>~~aee~~|0<br>~~ee~~|0<br>~~ee~~|0<br>~~ee~~|0<br>~~ee~~|
||Bank 7<br>~~ee~~<br>~~ee~~|0<br>~~ee~~<br>~~ee~~|0<br>~~ee~~<br>~~ee~~|0<br>~~ee~~<br>~~ee~~|0<br>~~ee~~<br>~~ee~~|
||Bank 8<br>~~ee~~<br>~~ee~~<br>~~ee~~|0<br>~~ee~~<br>~~ee~~|0<br>~~ee~~<br>~~ee~~|0<br>~~ee~~<br>~~ee~~|0<br>~~ee~~<br>~~ee~~|
||Bank 9<br>~~ee~~<br>~~ee~~|0<br>~~ee~~|0<br>~~ee~~|0<br>~~ee~~|0<br>~~ee~~|
|Shared JTAG Pins|Bank 0<br>~~ee~~<br>~~eG~~|0<br>~~eG~~|0<br>~~eG~~|0<br>~~eG~~|0<br>~~eG~~|
||Bank 1<br>~~eG~~|0<br>~~eG~~|0<br>~~eG~~|4<br>~~eG~~|4<br>~~eG~~|
||Bank 2<br>~~eG~~|4<br>~~eG~~|4<br>~~eG~~|0<br>~~eG~~|0<br>~~eG~~|
||Bank 3<br>~~eG~~|0<br>~~eG~~|0<br>~~eG~~|0<br>~~eG~~|0<br>~~eG~~|
||Bank 4<br>~~eG~~|0<br>~~eG~~|0<br>~~eG~~|0<br>~~eG~~|0<br>~~eG~~|
||Bank 5<br>~~a~~|0<br>|0<br>|0<br>|0<br>|
||Bank 6<br>~~aee~~|0<br>~~ee~~|0<br>~~ee~~|0<br>~~ee~~|0<br>~~ee~~|
||Bank 7<br>~~ee~~<br>~~eG~~|0<br>~~ee~~<br>~~eG~~|0<br>~~ee~~<br>~~eG~~|0<br>~~ee~~<br>~~eG~~|0<br>~~ee~~<br>~~eG~~|
||Bank 8<br>~~eG~~<br>~~eG~~|0<br>~~eG~~<br>~~eG~~|0<br>~~eG~~<br>~~eG~~|0<br>~~eG~~<br>~~eG~~|0<br>~~eG~~<br>~~eG~~|
||Bank 9<br>~~eG~~<br>~~eG~~|0<br>~~eG~~<br>~~eG~~|0<br>~~eG~~<br>~~eG~~|0<br>~~eG~~<br>~~eG~~|0<br>~~eG~~<br>~~eG~~|
|Shared PCLK Pins|Bank 0<br>~~eG~~|2<br>~~eG~~|2<br>~~eG~~|0<br>~~eG~~|0<br>~~eG~~|
||Bank 1<br>~~eG~~|2<br>~~eG~~|2<br>~~eG~~|3<br>~~eG~~|3<br>~~eG~~|
||Bank 2<br>~~eG~~|3<br>~~eG~~|3<br>~~eG~~|3<br>~~eG~~|3<br>~~eG~~|
||Bank 3<br>~~eG~~|2<br>~~eG~~|2<br>~~eG~~|8<br>~~eG~~|8<br>~~eG~~|
||Bank 4<br>~~a~~|2<br>|2<br>|8<br>|8<br>|
||Bank 5<br>~~aeG~~|8<br>~~eG~~|8<br>~~eG~~|8<br>~~eG~~|8<br>~~eG~~|
||Bank 6<br>~~eG~~<br>~~eG~~|8<br>~~eG~~<br>~~eG~~|8<br>~~eG~~<br>~~eG~~|3<br>~~eG~~<br>~~eG~~|3<br>~~eG~~<br>~~eG~~|
||Bank 7<br>~~eG~~<br>~~eG~~|2<br>~~eG~~<br>~~eG~~|2<br>~~eG~~<br>~~eG~~|3<br>~~eG~~<br>~~eG~~|3<br>~~eG~~<br>~~eG~~|
||Bank 8<br>~~eG~~<br>~~eG~~|2<br>~~eG~~<br>~~eG~~|2<br>~~eG~~<br>~~eG~~|0<br>~~eG~~<br>~~eG~~|0<br>~~eG~~<br>~~eG~~|
||Bank 9<br>~~eG~~<br>~~eG~~|0<br>~~eG~~<br>~~eG~~|3<br>~~eG~~<br>~~eG~~|0<br>~~eG~~<br>~~eG~~|0<br>~~eG~~<br>~~eG~~|
|Shared GPLL Pins|Bank 0<br>~~eG~~|0<br>~~eG~~|0<br>~~eG~~|0<br>~~eG~~|0<br>~~eG~~|
||Bank 1<br>~~eG~~|0<br>~~eG~~|0<br>~~eG~~|2<br>~~eG~~|2<br>~~eG~~|
||Bank 2<br>~~CG~~|0<br>~~CG~~|0<br>~~CG~~|0<br>~~CG~~|0<br>~~CG~~|
||Bank 3<br>~~CO~~|0<br>~~CO~~|0<br>~~CO~~|2<br>~~CO~~|2<br>~~CO~~|
||Bank 4<br>~~CO~~<br>~~eG~~|0<br>~~CO~~<br>~~eG~~|0<br>~~CO~~<br>~~eG~~|2<br>~~CO~~<br>~~eG~~|2<br>~~CO~~<br>~~eG~~|
||Bank 5<br>~~eG~~<br>~~eG~~|2<br>~~eG~~<br>~~eG~~|2<br>~~eG~~<br>~~eG~~|2<br>~~eG~~<br>~~eG~~|2<br>~~eG~~<br>~~eG~~|
||Bank 6<br>~~eG~~<br>~~eG~~|0<br>~~eG~~<br>~~eG~~|0<br>~~eG~~<br>~~eG~~|0<br>~~eG~~<br>~~eG~~|0<br>~~eG~~<br>~~eG~~|
||Bank 7<br>~~eG~~<br>~~eG~~|0<br>~~eG~~<br>~~eG~~|0<br>~~eG~~<br>~~eG~~|0<br>~~eG~~<br>~~eG~~|0<br>~~eG~~<br>~~eG~~|
||Bank 8<br>~~eG~~<br>~~eG~~|0<br>~~eG~~<br>~~eG~~|0<br>~~eG~~<br>~~eG~~|0<br>~~eG~~<br>~~eG~~|0<br>~~eG~~<br>~~eG~~|
||Bank 9<br>~~CG~~|1<br>~~CG~~|1<br>~~CG~~|0<br>~~CG~~|0<br>~~CG~~|



© 2021-2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

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**MachXO5-NX Family Data Sheet** 

|**Pin**<br>~~c~~|**Pin**<br>~~c~~|**LFMXO5-25**<br>~~c~~~~**e**~~<br>~~e~~~~**e**~~<br>~~ee~~|**LFMXO5-25**<br>~~c~~~~**e**~~<br>~~e~~~~**e**~~<br>~~ee~~|**LFMXO5-55T**<br>~~**e**~~<br>~~ee~~|**LFMXO5-100T**<br>~~**e**~~<br>~~eee~~|
|---|---|---|---|---|---|
|||**256 BBG**<br>~~c~~~~**e**~~<br>~~ee~~|**400 BBG**<br>~~**e**~~<br>~~e~~~~**e**~~|**400 BBG**<br>~~**e**~~<br>~~ee~~<br>~~s~~|**400 BBG**<br>~~**e**~~<br>~~eee~~<br>~~s~~|
|Shared VREF Pins|Bank 0<br>~~f~~|0<br>~~ee~~<br>~~f~~|0<br>~~e~~~~**e**~~<br>~~f~~|0<br>~~ee~~|0<br>~~eee~~|
||Bank 1<br>~~GG~~|0<br>~~GG~~|0<br>~~GG~~|0<br>~~GG~~|0<br>~~GG~~|
||Bank 2<br>~~GG~~|0<br>~~GG~~|0<br>~~GG~~|0<br>~~GG~~|0<br>~~GG~~|
||Bank 3<br>~~eG~~|0<br>~~eG~~|0<br>~~eG~~|2<br>~~eG~~|2<br>~~eG~~|
||Bank 4<br>~~sO~~|0<br>~~sO~~|0<br>~~sO~~|2<br>~~sO~~|2<br>~~sO~~|
||Bank 5<br>~~sO~~|2<br>~~sO~~|2<br>~~sO~~|2<br>~~sO~~|2<br>~~sO~~|
||Bank 6<br>~~sO~~|2<br>~~sO~~|2<br>~~sO~~|0<br>~~sO~~|0<br>~~sO~~|
||Bank 7<br>~~sO~~|0<br>~~sO~~|0<br>~~sO~~|0<br>~~sO~~|0<br>~~sO~~|
||Bank 8<br>~~Ge~~|0<br>~~Ge ~~|0<br> ~~GO~~|0<br>~~GO~~|0<br>~~GO~~|
||Bank 9<br>~~eG~~|0<br>~~eG~~|0<br>~~eG~~|0<br>~~eG~~|0<br>~~eG~~|
|Shared ADC Channels<br>(Pairs)|Bank 0<br>~~fe~~|0<br>~~fe~~|0<br>~~fe~~|0<br>~~fe~~|0<br>~~fe~~|
||Bank 1<br>~~GG~~|0<br>~~GG~~|0<br>~~GG~~|0<br>~~GG~~|0<br>~~GG~~|
||Bank 2<br>~~eG~~|0<br>~~eG~~|0<br>~~eG~~|0<br>~~eG~~|0<br>~~eG~~|
||Bank 3<br>~~eG~~|0<br>~~eG~~|0<br>~~eG~~|8<br>~~eG~~|8<br>~~eG~~|
||Bank 4<br>~~eG~~|0<br>~~eG~~|0<br>~~eG~~|4<br>~~eG~~|4<br>~~eG~~|
||Bank 5<br>~~eG~~|5<br>~~eG~~|7<br>~~eG~~|4<br>~~eG~~|4<br>~~eG~~|
||Bank 6<br>~~eG~~|8<br>~~eG~~|9<br>~~eG~~|0<br>~~eG~~|0<br>~~eG~~|
||Bank 7<br>~~a~~|0<br>|0<br>|0<br>|0<br>|
||Bank 8<br>~~aee~~<br>~~ee~~|0<br>~~ee~~|0<br>~~ee~~|0<br>~~ee~~|0<br>~~ee~~|
||Bank 9<br>~~ee~~<br>~~ee~~<br>~~ee~~|0<br>~~ee~~|0<br>~~ee~~|0<br>~~ee~~|0<br>~~ee~~|
|Shared Comparator<br>Channels (Pairs)|Bank 0<br>~~ee~~<br>~~ee~~|0|0|0|0|
||Bank 1<br>~~ee~~<br>~~ee~~|0<br>~~ee~~|0<br>~~ee~~|0<br>~~ee~~|0<br>~~ee~~|
||Bank 2<br>~~ee~~<br>~~eG~~|0<br>~~ee~~<br>~~eG~~|0<br>~~ee~~<br>~~eG~~|0<br>~~ee~~<br>~~eG~~|0<br>~~ee~~<br>~~eG~~|
||Bank 3<br>~~eG~~|0<br>~~eG~~|0<br>~~eG~~|3<br>~~eG~~|3<br>~~eG~~|
||Bank 4<br>~~eG~~|0<br>~~eG~~|0<br>~~eG~~|0<br>~~eG~~|0<br>~~eG~~|
||Bank 5<br>~~eG~~|3<br>~~eG~~|3<br>~~eG~~|3<br>~~eG~~|3<br>~~eG~~|
||Bank 6<br>~~a~~|3<br>|3<br>|0<br>|0<br>|
||Bank 7<br>~~aeG~~|0<br>~~eG~~|0<br>~~eG~~|0<br>~~eG~~|0<br>~~eG~~|
||Bank 8<br>~~eG~~<br>~~eG~~|0<br>~~eG~~<br>~~eG~~|0<br>~~eG~~<br>~~eG~~|0<br>~~eG~~<br>~~eG~~|0<br>~~eG~~<br>~~eG~~|
||Bank 9<br>~~eG~~<br>~~eG~~<br>~~ee~~|0<br>~~eG~~<br>~~eG~~<br>~~D~~|0<br>~~eG~~<br>~~eG~~<br>~~D~~|0<br>~~eG~~<br>~~eG~~|0<br>~~eG~~<br>~~eG~~|
|Shared SGMII<br>Channels (Pairs)|Bank 0<br>~~eG~~<br>~~ee~~<br>~~es~~|0<br>~~eG~~<br>~~D~~|0<br>~~eG~~<br>~~D~~|0<br>~~eG~~|0<br>~~eG~~|
||Bank 1<br>~~ee~~<br>~~es~~|0<br>~~D~~|0<br>~~D~~|0|0|
||Bank 2<br>~~es~~<br>~~eG~~|0<br>~~eG~~|0<br>~~eG~~|0<br>~~eG~~|0<br>~~eG~~|
||Bank 3<br>~~eG~~|0<br>~~eG~~|0<br>~~eG~~|0<br>~~eG~~|0<br>~~eG~~|
||Bank 4<br>~~eG~~|0<br>~~eG~~|0<br>~~eG~~|0<br>~~eG~~|0<br>~~eG~~|
||Bank 5<br>~~eG~~|0<br>~~eG~~|0<br>~~eG~~|2<br>~~eG~~|2<br>~~eG~~|
||Bank 6<br>~~a~~|2<br>|2<br>|0<br>|0<br>|
||Bank 7<br>~~aeG~~|0<br>~~eG~~|0<br>~~eG~~|0<br>~~eG~~|0<br>~~eG~~|
||Bank 8<br>~~eG~~<br>~~eG~~|0<br>~~eG~~<br>~~eG~~|0<br>~~eG~~<br>~~eG~~|0<br>~~eG~~<br>~~eG~~|0<br>~~eG~~<br>~~eG~~|
||Bank 9<br>~~eG~~<br>~~a~~|0<br>~~eG~~|0<br>~~eG~~|0<br>~~eG~~|0<br>~~eG~~|



© 2021-2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

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**MachXO5-NX Family Data Sheet** 

## **6. Ordering Information** 

Lattice Semiconductor provides a wide variety of services for its products including custom marking, factory programming, known good die, and application specific testing. Contact your local sales representatives for more details. 

## **6.1. Part Number Description** 

**==> picture [482 x 568] intentionally omitted <==**

**----- Start of picture text -----**<br>
LFMXO5 - XXX X - X XXXXXX X<br>Grade<br>Base Device<br>      C = Commercial<br>Name<br>       I = Industrial<br>Logic Capacity<br>    25 = 25k Logic Cells Package<br>    55 = 55k Logic Cells     BBG256 = 256-ball caBGA<br>   100 = 100k Logic Cells       BBG400 = 400-ball caBGA<br>    B = BGA<br>    B = 0.8 mm pitch<br>    G = Ball Composition (ROHS 6/6)<br>Features<br>    T = Transceiver<br>Speed (same number for HP and LP) 1<br>   7 = Slowest<br>     8<br>     9 = Fastest<br>Note :<br>1. Input Comparator, ADC, EBR ECC, and DTR are only available in -8 (-C/I) and -9 (-C/I) speed and grade.<br>[SE]<br>©  2021-2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.<br>All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.<br>**----- End of picture text -----**<br>


FPGA-DS-02102-1.7 

158 

**MachXO5-NX Family Data Sheet** 

## **6.2. Ordering Part Numbers** 

MachXO5-NX devices have either of the top-side markings as shown in the examples below. 

**==> picture [313 x 99] intentionally omitted <==**

**----- Start of picture text -----**<br>
MachXO5 - NX MachXO5 - NX<br>LFMXO5-25<br>8BBG400C<br>Lot ID Lot ID<br>Barcode Barcode<br>COO COO<br>**----- End of picture text -----**<br>


**Figure 6.1. Top Marking Diagram** 

**6.2.1. Commercial** 

|**Part Number**<br>~~GG~~|**Speed**<br>~~GG~~|**Package **<br>~~GG~~|**Pins**<br>~~GG~~|**Temp. **<br>~~GG~~|**Logic Cells(k)**<br>~~GG~~|
|---|---|---|---|---|---|
|LFMXO5-25-7BBG256C<br>~~a~~|–7|Lead free caBGA|256|Commercial|25|
|LFMXO5-25-8BBG256C<br>~~pT~~<br>~~**p**o~~|–8<br>~~pT~~|Lead free caBGA<br>~~pT~~|256<br>~~pT~~|Commercial<br>~~pT~~|25<br>~~pT~~|
|LFMXO5-25-9BBG256C<br>~~**p**o~~|–9|Lead free caBGA|256|Commercial|25|
|LFMXO5-25-7BBG400C<br>~~**p**o~~|–7|Lead free caBGA<br>~~o~~|400<br>~~o~~|Commercial<br>~~o~~|25<br>~~o~~|
|LFMXO5-25-8BBG400C<br>~~po~~|–8<br>~~po~~|Lead free caBGA<br>~~o~~<br>~~po~~|400<br>~~o~~<br>~~po~~|Commercial<br>~~o~~<br>~~po~~|25<br>~~o~~<br>~~po~~|
|LFMXO5-25-9BBG400C<br>~~pT~~|–9<br>~~pT~~|Lead free caBGA<br>~~pT~~|400<br>~~pT~~|Commercial<br>~~pT~~|25<br>~~pT~~|
|LFMXO5-55T-7BBG400C<br>~~ss~~|–7<br>~~ss~~|Lead free caBGA<br>~~ss~~|400<br>~~ss~~|Commercial<br>~~ss~~|55<br>~~ss~~|
|LFMXO5-55T-8BBG400C<br>~~a~~|–8|Lead free caBGA|400|Commercial|55|
|LFMXO5-55T-9BBG400C<br>~~a~~<br>~~po~~|–9<br>~~po~~|Lead free caBGA<br>~~po~~|400<br>~~po~~|Commercial<br>~~po~~|55<br>~~po~~|
|LFMXO5-100T-7BBG400C<br>~~po~~<br>~~po~~|–7<br>~~po~~<br>~~po~~|Lead free caBGA<br>~~po~~<br>~~po~~|400<br>~~po~~<br>~~po~~|Commercial<br>~~po~~<br>~~po~~|100<br>~~po~~<br>~~po~~|
|LFMXO5-100T-8BBG400C<br>~~po~~<br>~~DG~~|–8<br>~~po~~<br>~~DG~~|Lead free caBGA<br>~~po~~<br>~~DG~~|400<br>~~po~~<br>~~DG~~|Commercial<br>~~po~~<br>~~DG~~|100<br>~~po~~<br>~~DG~~|
|LFMXO5-100T-9BBG400C<br>~~Po~~|–9<br>~~Po~~|Lead free caBGA<br>~~Po~~|400<br>~~Po~~|Commercial<br>~~Po~~|100<br>~~Po~~|



|**Part Number**<br>~~**p**O~~|**Speed**|**Package **|**Pins**|**Temp. **|**Logic Cells(k)**|
|---|---|---|---|---|---|
|LFMXO5-25-7BBG256I<br>~~**p**O~~|–7|Lead free caBGA<br>~~o~~|256<br>~~o~~|Industrial<br>~~o~~|25<br>~~o~~|
|LFMXO5-25-8BBG256I<br>~~DG~~<br>~~po~~|–8<br>~~DG~~|Lead free caBGA<br>~~o~~<br>~~DG~~|256<br>~~o~~<br>~~DG~~|Industrial<br>~~o~~<br>~~DG~~|25<br>~~o~~<br>~~DG~~|
|LFMXO5-25-9BBG256I<br>~~po~~<br>~~po~~|–9|Lead free caBGA|256|Industrial|25|
|LFMXO5-25-7BBG400I<br>~~po~~<br>~~po~~|–7|Lead free caBGA|400|Industrial|25|
|LFMXO5-25-8BBG400I<br>~~po~~<br>~~GD~~|–8<br>~~GD~~|Lead free caBGA<br>~~GD~~|400<br>~~GD~~|Industrial<br>~~GD~~|25<br>~~GD~~|
|LFMXO5-25-9BBG400I<br>~~GD~~<br>~~po~~|–9<br>~~GD~~<br>~~po~~|Lead free caBGA<br>~~GD~~<br>~~po~~|400<br>~~GD~~<br>~~po~~|Industrial<br>~~GD~~<br>~~po~~|25<br>~~GD~~<br>~~po~~|
|LFMXO5-55T-7BBG400I<br>~~po~~<br>~~po~~<br>~~po~~|–7<br>~~po~~<br>~~po~~|Lead free caBGA<br>~~po~~<br>~~po~~|400<br>~~po~~<br>~~po~~|Industrial<br>~~po~~<br>~~po~~|55<br>~~po~~<br>~~po~~|
|LFMXO5-55T-8BBG400I<br>~~po~~<br>~~po~~<br>~~a~~|–8<br>~~po~~|Lead free caBGA<br>~~po~~|400<br>~~po~~|Industrial<br>~~po~~|55<br>~~po~~|
|LFMXO5-55T-9BBG400I<br>~~po~~<br>~~a~~~~**p**o~~|–9|Lead free caBGA|400|Industrial|55|
|LFMXO5-100T-7BBG400I<br>~~a~~~~**p**o~~|–7|Lead free caBGA|400|Industrial|100|
|LFMXO5-100T-8BBG400I<br>~~**p**o~~|–8|Lead free caBGA<br>~~o~~|400<br>~~o~~|Industrial<br>~~o~~|100<br>~~o~~|
|LFMXO5-100T-9BBG400I<br>~~DG~~|–9<br>~~DG~~|Lead free caBGA<br>~~o~~<br>~~DG~~|400<br>~~o~~<br>~~DG~~|Industrial<br>~~o~~<br>~~DG~~|100<br>~~o~~<br>~~DG~~|



© 2021-2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. 

All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02102-1.7 

159 

**MachXO5-NX Family Data Sheet** 

## **Supplemental Information** 

## **For Further Information** 

A variety of technical notes for the MachXO5-NX family are available. 

- ADC User Guide for Nexus Platform (FPGA-TN-02129) 

- Advanced Embedded Security and Function Block User Guide for MachXO5-NX Devices (FPGA-TN-02320) 

- I[2] C Hardened IP User Guide for Nexus Platform (FPGA-TN-02142) 

- Lattice Memory Mapped Interface and Lattice Interrupt Interface User Guide (FPGA-UG-02039) 

- MachXO5-NX Hardware Checklist (FPGA-TN-02274) 

- MachXO5-NX High-Speed I/O Interface (FPGA-TN-02286) 

- MachXO5-NX Programming and Configuration UG (FPGA-TN-02271) 

- Memory User Guide for Nexus Platform (FPGA-TN-02094) 

- Multi-Boot User Guide for Nexus Platform (FPGA-TN-02145) 

- Single Event Upset (SEU) Report for Nexus Platform (FPGA-TN-02174) 

- Soft Error Detection (SED)/Correction (SEC) User Guide for Nexus Platform (FPGA-TN-02076) 

- sub-LVDS Signaling Using Lattice Devices (FPGA-TN-02028) 

- sysCLOCK PLL Design and User Guide for Nexus Platform (FPGA-TN-02095) 

- sysDSP User Guide for Nexus Platform (FPGA-TN-02096) 

- sysI/O User Guide for Nexus Platform (FPGA-TN-02067) 

- Power Management and Calculation for Certus-NX, CertusPro-NX and MachXO5-NX Devices (FPGA-TN-02257) 

- Thermal Management (FPGA-TN-02044) 

- Using TraceID (FPGA-TN-02084) 

For further information on interface standards refer to the following websites: 

- JEDEC Standards (LVTTL, LVCMOS, SSTL) – www.jedec.org 

© 2021-2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02102-1.7 

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**MachXO5-NX Family Data Sheet** 

## **Revision History** 

## **Revision 1.7, September 2024** 

|**Section**|**Change Summary**|
|---|---|
|All|Changed SerDes to SERDES across the document.|
|DC and Switching Characteristics<br>for LFMXO5-25 Commercial and<br>Industrial|•<br>Newly addedFigure 3.14. Configuration Error Notification (1).<br>•<br>Figure 3.15. Slave SPI/I2C/I3C POR/REFRESH Timing:<br>•<br>removed tICFGparameter;<br>•<br>changed tACT_CRESETB_Hto tACT_PROGRAMN_H.<br>•<br>Updated the following symbol names inFigure 3.17. Slave SPI Configuration Timing:<br>•<br>from tCO_MISOto tCO_SSO;<br>•<br>from tEN_MISOto tEN_SSO;<br>•<br>from tDIS_MISOto tDIS_SSO;<br>•<br>from tSU_MOSIto tSU_SSI;<br>•<br>from tHD_MOSIto tHD_SSI.<br>•<br>Table 3.44. sysCONFIG Port Timing Specifications:<br>•<br>updated the Min value of tCO_SSO, tEN_SSO, and tDIS_SSOto 3.0;<br>•<br>updated the Max value of tCO_SSO, tEN_SSO, and tDIS_SSOto 16;<br>•<br>removed the original fCCLKsymbol and its related data;<br>•<br>newly added fCCLK_Wand fCCLK_Rsymbols and their related data;<br>•<br>newlyadded Notes 1, 2, 3, 4, and 5.|
|DC and Switching Characteristics<br>for LFMXO5-55T/100T<br>Commercial and Industrial|•<br>Removed a Note about preliminary data from the introductory paragraph of this<br>section.<br>•<br>Table 4.14. sysI/O Recommended Operating Conditions:<br>Corrected wrong bank information in Notes 1, 3, 4, and 7.<br>•<br>Table 4.46. sysCONFIG Port Timing Specifications:<br>•<br>updated the Min value of tCO_SSO, tEN_SSO, and tDIS_SSOto 3.0;<br>•<br>updated the Max value of tCO_SSO, tEN_SSO, and tDIS_SSOto 30;<br>•<br>removed the original fCCLKsymbol and its related data;<br>•<br>newly added fCCLK_Wand fCCLK_Rsymbols and their related data;<br>•<br>newly added Notes 1, 2, 3, 4, and 5.<br>•<br>Updated tINIT_HIGHTyp. value to 50 inTable 4.48. Test Fixture Required Components,<br>Non-Terminated Interfaces.<br>•<br>Newly addedFigure 4.14. Configuration Error Notification (2).<br>•<br>Figure 4.15. Slave SPI/I2C/I3C POR/REFRESH Timing:<br>•<br>removed tICFGparameter;<br>•<br>changed tACT_CRESETB_Hto tACT_PROGRAMN_H.<br>•<br>Updated the following symbol names inFigure 4.17. Slave SPI Configuration Timing:<br>•<br>from tCO_MISOto tCO_SSO;<br>•<br>from tEN_MISOto tEN_SSO;<br>•<br>from tDIS_MISOto tDIS_SSO;<br>•<br>from tSU_MOSIto tSU_SSI;<br>•<br>from tHD_MOSIto tHD_SSI.|
|Pinout Information|Updated bank information for VCCIOx inTable 5.1. Signal Descriptions.|



## **Revision 1.6, May 2024** 

|**Section**|**Change Summary**|
|---|---|
|General Description|Changed_Endpoint and Root complex_to_Endpoint_in the Features section.|
|Architecture|Changed_Endpoint and Root complex_to_Endpoint_in the Peripheral Component Interconnect<br>Express(PCIe)section.|



© 2021-2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02102-1.7 

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**MachXO5-NX Family Data Sheet** 

|**Section**|**Change Summary**|
|---|---|
|DC and Switching Characteristics<br>for LFMXO5-25 Commercial and<br>Industrial|•<br>Removed_and follow the SMIA 1.0, Part 2: CCP2 Specification_from the SubLVDS (Input<br>Only) section.<br>•<br>Table 3.34. External Switching Characteristics (VCC = 1.0 V):<br>•<br>updated the unit for tDVB_GDDRX4symbol;<br>•<br>updated description and unit for tDQVA_GDDRX4symbol;<br>•<br>updated description for fMAX_GDDRX4symbol;<br>•<br>updated description for fPCLKsymbol.<br>•<br>Table 3.40. ADC Specifications1:<br>•<br>removed DCCLK_ADCsymbol from the table;<br>•<br>for fINPUT_ADCsymbol, changed the condition to @ Sampling Frequency = 1 Mbps;<br>•<br>for RIN_ADCsymbol, changed the condition to —;<br>•<br>newly added Note 4_Internal voltage reference is only for internal testing purpose._<br>_It is not recommended for customer design. User should always use the part with_<br>_external reference voltage_.|
|DC and Switching Characteristics<br>for LFMXO5-55T/100T<br>Commercial and Industrial|•<br>Removed_and follow the SMIA 1.0, Part 2: CCP2 Specification_from the SubLVDS (Input<br>Only) section.<br>•<br>Table 4.34. External Switching Characteristics (VCC= 1.0 V):<br>•<br>updated the unit for tDVB_GDDRX4symbol;<br>•<br>updated description and unit for tDQVA_GDDRX4symbol;<br>•<br>updated description for fMAX_GDDRX4symbol;<br>•<br>updated description for fPCLKsymbol.<br>•<br>Table 4.40. ADC Specifications1:<br>•<br>removed DCCLK_ADCsymbol from the table;<br>•<br>for fINPUT_ADCsymbol, changed the condition to @ Sampling Frequency = 1 Mbps.<br>•<br>for RIN_ADCsymbol, changed the condition to —.<br>•<br>newly added Note 4_Internal voltage reference is only for internal testing purpose._<br>_It is not recommended for customer design. User should always use the part with_<br>_external reference voltage_.|
|Pinout Information|Added_Total Differential I/O_area and related data to Table 5.2. Pin Information Summary.|



## **Revision 1.5, October 2023** 

|**Section**|**Change Summary**|
|---|---|
|Disclaimers|Updated disclaimers.|
|DC and Switching Characteristics<br>for LFMXO5-25 Commercial and<br>Industrial|Updated tINIT_HIGH, tDONE_LOW, tDONE_HIGH, and tIODISSspecifications in Table 3.44. sysCONFIG Port<br>Timing Specifications.|



## **Revision 1.4, May 2023** 

|**Section**|**Change Summary**|
|---|---|
|All|Separated the contents and data for LFMXO5-25 and LFMXO55/100T devices support.|
|General Description|Updated Table 1.1. MachXO5-NX Commercial/Industrial Family Selection Guide changing<br>Packages Sizes for LFMXO5-25, LFMXO5-55T, LFMXO5-100T devices by reducing 1 for not<br>countingJTAG_EN.|
|DC and Switching Characteristics<br>for LFMXO5-25 Commercial and<br>Industrial|•<br>Changed the section title to the current.<br>•<br>Removed the Note regarding subject to change without prior notice.<br>•<br>Updated contents and data whole section wise for the LFMXO5-25 support only.<br>•<br>Removed the original Differential LVSTLD (Output Only), Hardened PCIe Characteristics<br>section.|
|DC and Switching Characteristics<br>for LFMXO5-55T/100T<br>Commercial and Industrial|Newly added section.|



© 2021-2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

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**==> picture [403 x 23] intentionally omitted <==**

**----- Start of picture text -----**<br>
|||
|---|---|
|Section|Change Summary|
|Pinout Information|Updated bank information for JTAG_EN in Table 5.1. Signal Descriptions.|

**----- End of picture text -----**<br>


**Revision 1.3, April 2023** 

**==> picture [478 x 523] intentionally omitted <==**

**----- Start of picture text -----**<br>
||||
|---|---|---|
|Section|Change Summary|
|All|Added LPDDR4 for the MachXO5-NX-55T and MachXO5-NX-100T devices support.|
|Acronyms in This Document|Added EMIF to the list.|
|General Description|Added LPDDR4 to the description and to the Features section.|
|Added EMIF and relevant DDR and LPDDR support to Table 1.1. MachXO5-NX|
|Commercial/Industrial Family Selection Guide.|
|Architecture|•|Added LPDDR4 and Internal VREF support for LPDDR4 to the Overview section.|
|•|Added LPDDR4 to the DDR Memory Support section including Table 2.9. DQSBUF Port|
|List Description.|
|•|sysI/O Buffer section:|
|•|added LVSTL and differential LVSTL  to the description;|
|•|Table 2.10. Single-Ended I/O Standards: added LVSTL_I and LVSTL_II standards and|
|their related data;|
|•|Table 2.11. Differential I/O Standards: added LVSTLD_I and LVSTLD_II standards|
|and their related data;|
|•|Table 2.12. Single-Ended I/O Standards Supported on Various Sides: added|
|LVSTL I,  II standard and the related data;|
|Table 2.13. Differential I/O Standards Supported on Various Sides: added LVSTLD_I and|
|LVSTLD_II standards and their related data.|
|DC and Switching Characteristics|•|Table 3.1. Absolute Maximum Ratings: added VCCSD*, VCCSDCK, VCCADC18, and VCCAUXSDQ*|
|for Commercial and Industrial|symbols and the related data.|
|•|Table 3.2. Recommended Operating Conditions: added SerDes Block External Power|
|Supplies including VCCSD*, VCCSDCK, VCCPLLSD*, and VCCAUXSDQ* symbols and the related data.|
|•|Table 3.5. On-Chip Termination Options for Input Modes: added LVSTL_I and LVSTL_II|
|I/O Type and the related data.|
|•|Table 3.14. sysI/O Recommended Operating Conditions:|
|•|added LVSTL_I and LVSTL_II to the Single-ended standard and the related data, and|
|also added Note 9 for these two standards;|
|•|added LVSTLD_I and LVSTLD_II to the Differential standard, as well as all the|
|related data, and pointed to Note 5.|
|•|Table 3.16. sysI/O DC Electrical Characteristics – High Performance I/O (Over|
|Recommended Operating Conditions)|[3]|: added LVSTL_I and LVSTL_II to the Input/Output|
|Standard as well as the related data.|
|•|Newly added the Differential LVSTLD (Output Only) section.|
|•|Table 3.30. Maximum I/O Buffer Speed1, 2, 3, 4, 7:|
|•|added LVSTL_I and LVSTL_II to the Single-Ended Maximum sysI/O Input Frequency|
|buffer as well as the related data;|
|•|added LVSTLD_I and LVSTLD_II to the Differential Maximum sysI/O Input|
|Frequency buffer as well as the related data;|
|•|added LVSTL_I and LVSTL_II to the Single-Ended Maximum sysI/O Output|
|Frequency buffer as well as the related data;|
|•|added LVSTLD to the Differential Maximum sysI/O Output Frequency buffer as well|
|as the related data;|
|Added LPDDR4 to Note 8.|

**----- End of picture text -----**<br>


**Revision 1.2, February 2023** 

**Section Change Summary** ~~ee~~ All This version is mainly based on the previous internal-released Version 1.1.1. 

© 2021-2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02102-1.7 

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**MachXO5-NX Family Data Sheet** 

|**Section**|**Change Summary**|
|---|---|
|Acronyms in This Document|Removed MLVDS from the list.|
|General Description|•<br>Removed LPDDR2 and LPDDR3 from the introductory description.<br>•<br>Features:<br>•<br>Programmable Architecture: updated to_27k_ _to 96k_logic cells,_20 to 156_18×18<br>multipliers (in sysDSP blocks), 1.9 Mb to 7.3 Mb of embedded memory blocks (EBR,<br>LRAM), and removed LPDDR2/LPDDR3;<br>•<br>Newly added PCIe hard IP support features;<br>•<br>Flexible memory resources: updated to_184 to 639_kbit distributed RAM;<br>Table 1.1. MachXO5-NX Commercial/Industrial Family Selection Guide: newly added<br>LFMXO5-55T and LFMXO5-100T and their related data.|
|Architecture|•<br>Overview:<br>•<br>newly added_The MachXO5-NX- 55T and MachXO5-NX-100T FPGAs feature one_<br>_hard PCIe link layer IP block which supports PCIe Gen1, Gen2 with 1 or 2 x1_<br>_configuration_.<br>•<br>newly added Figure 2.2. Simplified Block Diagram, MachXO5-NX-55T Device (Top<br>•<br>Level) and Figure 2.3. Simplified Block Diagram, MachXO5-NX-100T Device (Top<br>•<br>Level).<br>•<br>• removed LPDDR2/LPDDR3 support.<br>•<br>Clocking Structure:<br>•<br>newly added Figure 2.9. Clocking for MachXO5-NX-55T/MachXO5-NX-100T<br>Devices.<br>•<br>Primary Clocks: updated to_The primary clock network is divided into two or four_<br>_clock domains depending on the device density_.<br>•<br>Edge Clock: updated to_Other bottom side banks are similar_.<br>•<br>Clock Dividers: updated to_There are from one (1) to two (2) Primary Clock Divider_<br>_(PCLKDIV) and which are located in the DCS_CMUX block(s) at the center of the_<br>_device. There are up to twelve (12) ECLKDIV dividers per device, locate near the_<br>_bottom high-speed I/O banks_.<br>•<br>Clock Center Multiplexer Blocks:<br>• newly added_For 50T/100T device, each DCS_CMUX block contains four (4)_<br>_DCSMUX blocks, two (2) PCLKDIV, two (2) DCS block, and four (4) CMUX blocks._<br>• newly added Figure 2.12. DCS_CMUX Diagram for MachXO5-NX-55T/MachXO5-<br>NX-100T Devices and Figure 2.16. DDRDLL Architecture for MachXO5-NX-<br>55T/MachXO5-NX-100T Devices.<br>•<br>DDR Memory Support: removed LPDDR2/LPDDR3 support.<br>•<br>sysI/O Buffer:<br>•<br>sysI/O Banking Scheme:<br>• newly added contents for MachXO5-NX-55T/MachXO-NX-100T support;<br>• newly added Figure 2.32. sysI/O Banking of MachXO5-NX-55T/MachXO5-NX-<br>100T Devices;<br>• newly added Note contents of MachXO5-NX-55T/MachXO5-NX-100T to<br>Table 2.12. Single-Ended I/O Standards Supported on Various Sides and<br>Table 2.13. Differential I/O Standards Supported on Various Sides.<br>• Hot Socketing: updated the original bank related description to_Top/Left/Right_<br>_Bank wide range I/O (excluding INITN/DONE) are fully hot socketable, while_<br>_Bottom Bank are not supported_.<br>•<br>User Flash Memory (UFM):<br>•<br>removed I2C Interface from the description;<br>•<br>Table 2.14. UFM Size: newly added MachXO5-NX-55T and MachXO5-NX-100T<br>related data.<br>•<br>Pin Migration: newly added_The MachXO5-NX-55T device can be migrated to the_<br>_MachXO5-NX-100T device_.<br>•<br>Peripheral Component Interconnect Express(PCIe): newlyadded section.|



© 2021-2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

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**MachXO5-NX Family Data Sheet** 

**==> picture [478 x 338] intentionally omitted <==**

**----- Start of picture text -----**<br>
||||
|---|---|---|
|Section|Change Summary|
|•|Cryptographic Engine: modified the description of the CRE main engine support for|
|MachXO5-NX-55T and MachXO5-NX-100T devices.|
|DC and Switching Characteristics|•|External Switching Characteristics,:|
|for Commercial and Industrial|•|removed LPDDR2/LPDDR3, tDVBDQ_LPDDR2, tDVBDQ_LPDDR3, tDVADQ_LPDDR2, tDVADQ_LPDDR3,|
|fDATA_LPDDR2, fDATA_LPDDR3, fMAX_ECLK_LPDDR2, fMAX_ECLK_LPDDR3, fMAX_SCLK_LPDDR2,|
|fMAX_SCLK_LPDDR3, tDQVBS_LPDDR2, tDQVBS_LPDDR3, tDQVAS_LPDDR2, and tDQVAS_LPDDR3 from|
|Memory Interface of Table 3.34. External Switching Characteristics (VCC = 1.0 V);|
|•|removed LPDDR2 and LPDDR3 timing support from Note 2 of Table 3.34. External|
|Switching Characteristics (VCC = 1.0 V) .|
|•|Flash Download Time: newly added data for LMFXO5-55T and LFMXO5-100T to|
|Table 3.37. Flash Download Time.|
|•|Flash Program and Erase Current: newly added data for LMVXO5-55T and LFMXO5-100T|
|to Table 3.38. Program and Erase Supply Current.|
|•|sysCONFIG Port Timing Specifications: removed tACT_CCLK and tACT_SCL from|
|Figure 3.14. Slave SPI/I2C/I3C POR/REFRESH Timing and Figure 3.15. Slave SPI/I2C/I3C|
|PROGRAMN Timing.|
|Pinout Information|•|Table 4.1. Signal Descriptions:|
|•|newly added VSSSD, VSSADC, VCCSDx, VCCSDCK, VCCPLLSDx, VCCAUXSDQx;|
|•|changed VCC to VCC, VCCECLK.|
|•|Table 4.2. Pin Information Summary:|
|•|newly added LFMXO5-55T 400 BBG and LFMXO5-100T 400 BBG families and their|
|related data;|
|newly added power pins VCCAUXSDQx, VCCSDx, and VCCPLLSDx, and GND pin VSSSDQz, and Dedicated|
|SerDes Pins to both LFMXO5-25 256 BBG and LFMXO5-25 400 BBG.|
|Ordering Information|•|Part Number Description: updated reflecting the most recent part number.|
|•|Ordering Part Numbers: added available LFMX5-55T and LFMXO5-100T parts to both|
|Commercial and Industrial tables.|

**----- End of picture text -----**<br>


**Revision 1.0, October 2022** 

**==> picture [474 x 272] intentionally omitted <==**

**----- Start of picture text -----**<br>
||||||
|---|---|---|---|---|
|Section|Change Summary|
|General Description|Updated processing features to include 27k logic cells in general description, Features, and|
|in Table 1.1. MachXO5-NX Commercial/Industrial Family Selection Guide.|
|Architecture|Removed|100 k write cycles|from the User Flash Memory|(UFM) section.|
|DC and Switching Characteristics|•|In the Power up Sequence section:|
|for Commercial and Industrial|•|Table 3.4. Power-On Reset: updated all the values for both VPORUP and VPORDN|
|symbols.|
|•|Newly added the Programming /Erase Specifications section and Table 3.7.|
|Programming/Erase Specifications.|
|•|In the sysI/O Single-Ended DC Electrical Characteristics3 section:|
|•|Table 3.15. sysI/O DC Electrical Characteristics – Wide Range I/O (Over|
|Recommended Operating Conditions): updated the LVTTL33/LVCMOS33 data.|
|•|Table 3.16. sysI/O DC Electrical Characteristics – High Performance I/O (Over|
|Recommended Operating Conditions)3: updated LVCMOS18H and LVCMOS10H|
|data.|
|•|Table 3.17. I/O Resistance Characteristics (Over Recommended Operating|
|Conditions): updated the Min value to 65 for SE Input Termination.|
|•|Newly added Table 3.18. VIN Maximum Overshoot/Undershoot Allowance – Wide|
|Range1,2 and Table 3.19. VIN Maximum Overshoot/Undershoot Allowance – High|
|Performance1,2.|
|•|In the sysI/O Differential DC Electrical Characteristics section:|
|•|Table 3.21. LVDS25E DC Conditions: updated the Typical value to 6.03 for IDC|
|parameter.|

**----- End of picture text -----**<br>


© 2021-2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02102-1.7 

165 

**MachXO5-NX Family Data Sheet** 

|**Section**|**Change Summary**|
|---|---|
||•<br>Table 3.29. Soft D-PHY Data-Clock Timing Specifications: updated Min and Max<br>value for TSKEW[TLIS]and THOLD[RX]symbols.<br>•<br>In the Maximum sysI/O Buffer Speed section:<br>•<br>Table 3.30. Maximum I/O Buffer Speed1, 2, 3, 4, 7: updated the Max value to 250<br>for the HSTL15 buffer, changed to HSUL12D buffer in both Maximum sysI/O Input<br>Frequency and Maximum sysI/O Output Frequency.<br>•<br>In the Typica Building Function Performance section:<br>•<br>Table 3.31. Pin-to-Pin Performance: updated Typ.@ VCC= 1.0 V values for all the<br>functions.<br>•<br>Table 3.32. Register-to-Register Performance1, 3, 4: updated Typ.@ VCC= 1.0 V<br>values for all the Basic, Embedded Memory, Large Memory, Distributed Memory<br>functions.<br>•<br>In the LMMI section:<br>•<br>Table 3.33. LMMI FMAX Summary: updated all the fMAXvalues.<br>•<br>In the External Switching Characteristics section:<br>•<br>Table 3.34. External Switching Characteristics (VCC = 1.0 V):<br>• global change to all the values for all the parameters;<br>• changed to tH(LTR)parameter;<br>• newly added tH(Bottom), tH_DEL(LTR), tH_DEL(Bottom)parameters;<br>• changed to tSUPLL(LTF except Bank1) parameter;<br>• newly added tSUPLL(Bank1), tSUPLL(Bottom), tHPLL(LTR) parameters;<br>• changed to tHPLL(Bottom) parameter;<br>• newly added Generic DDRX1 Inputs/Outputs with Clock and Data Centered at<br>Pin (GDDRX1_RX/TX.SCLK.Centered) using PCLK Clock Input – Figure 3.7 and<br>Figure 3.9 Bottom and Generic DDRX1 Inputs/Outputs with Clock and Data<br>Aligned at Pin (GDDRX1_RX/TX.SCLK.Aligned) using PCLK Clock Input – Figure<br>3.8 and Figure 3.10 Bottom parameters and their related values;<br>• updated Note 2;<br>• newly added Note 6 for tSKEW_PRI and tSKEW_EDGE parameters.<br>•<br>In the sysCLOCK PLL Timing (VCC = 1.0 V) section:<br>•<br>Table 3.35. sysCLOCK PLL Timing (VCC = 1.0 V):<br>• removed footnote from fPFD parameter;<br>• indicated tPH to Note 4;<br>• removed and added conditions in tOPJIT parameter to accurately reflect PLL<br>jitter performance;<br>• updated all the values for all the parameters.<br>•<br>In the Internal Oscillators Characteristics section:<br>•<br>Table 3.36. Internal Oscillators (VCC = 1.0 V): updated all the values for all the<br>symbols.<br>•<br>In the Flash Download Time section:<br>•<br>Table 3.37. Flash Download Time: updated typ. value for the tREFRESH symbol.<br>•<br>Newly added the Flash Program and Erase Current section and Table 3.38. Program and<br>Erase Supply Current.<br>•<br>In the User I2C Characteristics section:<br>•<br>Table 3.39. User I2C Specifications (VCC = 1.0 V): updated all the values for all the<br>symbols.<br>•<br>In the sysCONFIG Port Timing Specifications section:<br>•<br>Table 3.44. sysCONFIG Port Timing Specifications: updated all the values for all the<br>symbols.<br>•<br>In the JTAG Port Timing Specifications section:<br>Table 3.45. JTAG Port TimingSpecifications: updated all the values for all the symbols.|
|Pinout Information|•<br>Table 4.2. Pin Information Summary:<br>•<br>updated all the values for VCCIO LFMXO5-25 400 BBG;<br>updated the number of Bank 1 user I/Opins for LFMXO5-25 256 BBG.|



© 2021-2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02102-1.7 

166 

**MachXO5-NX Family Data Sheet** 

## **Revision 0.82, September 2022** 

||**Section**|**Change Summary**|**Change Summary**|
|---|---|---|---|
||Pinout Information|•|In Table 4.1. Signal Descriptions:|
||||•<br>changed the Bank to 2 for PRxxx/TDO/SSO, PRxxx/TDI/SSI, PRxxx/TMS/SCSN, and|
||||PRxxx/TCK/SCLK signals;|
||||•<br>changed the Bank to 1 for PTxxx/PROGRAMN, PTxxx/INITN and PTxxx/DONE|
||||signals.|
|**Revision 0.81, August 2022**||||
|**Section**<br>Architecture<br>DC and Switching Characteristics<br>for Commercial and Industrial<br>All<br>**Revision 0.80, May 2022**<br>**Section**<br>~~So~~||**Change Summary**<br>Changed section header to SGMII TX/RX and updated contents.<br>•<br>Updated Table 3.30. Maximum I/O Buffer Speed1, 2, 3, 4, 7. Corrected footnote<br>reference of Differential to_8_.<br>•<br>Added DSP functions and adjusted footnotes in Table 3.32. Register-to-Register<br>Performance1, 3, 4.<br>Corrected tPH parameter footnote in Table 3.35. sysCLOCK PLL Timing (VCC = 1.0 V).<br>•<br>Added links to referenced documents.<br>•<br>Removed product name from headings and captions of figures and tables.<br>•<br>Minor changes in style and formatting.<br>**Change Summary**||
||All|Globallychanged Control Jedi-D6 to MachXO5-NX.||
||General Description|•|Newly changed to Dual ADC – 1 MSPS, 12-bit SAR with Simultaneous Sampling.|
|||•|Newly added note.|
||||Updated UFM value in Table 1.1. MachXO5-NX Commercial/Industrial Family Selection|
||||Guide.|
||Architecture|•|In the sysMEM Memory section:|
||||•<br>Changed to EBR also provides a build in ECC engine in select speed grades.|
||||•<br>Updated Figure 2.25. DQS Control and Delay Block (DQSBUF).|
||||•<br>Globally updated Table 2.9. DQSBUF Port List Description.|
|||•|In the Analog Interface section:|
||||•<br>Changed to In select speed grades, the MachXO5-NX family provides an analog|
||||interface….|
|||•|In the Device Configuration section:|
||||•<br>Changed the Master SPI booting sequence to self-download mode.|
||||•<br>Changed to In self-download mode, the FPGA boots from an external SPI boots|
||||from on-chip flash.|
|||•|In the User Flash Memory (UFM) section:|
||||•<br>Updated the non-volatile storage data to 15,360 kb.|
||||•<br>Updated all the values in Table 2.14. MachXO5-NX UFM Size.|
|||•|In the Pin Migration section:|
|||•|Changed the section title from DensityShiftingto_Pin Migration_.|
||DC and Switching Characteristics|•|Removed Bank 10 and Bank 11 from Table 3.1. Absolute Maximum Ratings and Table|
||for Commercial and Industrial||3.2. Recommended Operating Conditions.|
|||•|Updated Note 1 contents of Table 3.5. On-Chip Termination Options for Input Modes.|
|||•|General update to Table 3.6. Hot Socketing Specifications for GPIO.|
|||•|General value update for Min., Typ. and Max. in Table 3.7. DC Electrical Characteristics|
||||– Wide Range (Over Recommended Operating Conditions) and Table 3.8. DC Electrical|
||||Characteristics – High Speed(Over Recommended OperatingConditions).|



© 2021-2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02102-1.7 

167 

**MachXO5-NX Family Data Sheet** 

|**Section**|**Change Summary**|
|---|---|
||•<br>Updated Note format in Table 3.9. Capacitors – Wide Range (Over Recommended<br>Operating Conditions) and Table 3.10. Capacitors – High Performance (Over<br>Recommended Operating Conditions).<br>•<br>General update to Table 3.13. sysI/O Recommended Operating Conditions, Table 3.14.<br>sysI/O DC Electrical Characteristics – Wide Range I/O (Over Recommended Operating<br>Conditions), and Table 3.15. sysI/O DC Electrical Characteristics – High Performance I/O<br>(Over Recommended Operating Conditions).<br>•<br>In the sysI/O Differential DC Electrical Characteristics section:<br>•<br>General update to the LVDS, SubLVDSE/SubLVDSEH (Output Only) sections.<br>•<br>General update to:<br>•<br>Table 3.17. LVDS DC Electrical Characteristics (Over Recommended Operating<br>Conditions)<br>•<br>Table 3.18. LVDS25E DC Conditions<br>•<br>Table 3.19. SubLVDS Input DC Electrical Characteristics (Over Recommended<br>Operating Conditions)<br>•<br>Table 3.20. SubLVDS Output DC Electrical Characteristics (Over Recommended<br>Operating Conditions)<br>•<br>Table 3.21. SLVS Input DC Characteristics (Over Recommended Operating<br>Conditions)<br>•<br>Table 3.22. SLVS Output DC Characteristics (Over Recommended Operating<br>Conditions)<br>•<br>Table 3.23. Soft D-PHY Input Timing and Levels<br>•<br>Table 3.24. Soft D-PHY Output Timing and Levels<br>•<br>Table 3.25. Soft D-PHY Clock Signal Specification<br>•<br>Table 3.26. Soft D-PHY Data-Clock Timing Specifications<br>•<br>Table 3.27. MachXO5-NX Maximum I/O Buffer Speed<br>•<br>Table 3.28. Pin-to-Pin Performance<br>•<br>Table 3.37. ADC Specifications<br>•<br>Table 3.38. Comparator Specifications<br>•<br>Table 3.39. DTR Specifications<br>•<br>Table 3.40. SGMII Rx<br>•<br>Table 3.41. MachXO5-NX sysCONFIG Port Timing Specifications<br>•<br>Removed the original Figure 3.14. Master SPI PRO/REFRESH Timing, Figure 3.16. Master<br>SPI PROGRAMN Timing, Figure 3.20. Master SPI Wake-UpTiming,|
|Pinout Information|•<br>Updated the Bank and description for VCCAUX and VCCIOx in In the Signal Descriptions<br>section.|
|Ordering Information|•<br>Newly added note to the MachXO5-NX Part Number Description section.<br>•<br>Updated the topmarkingdiagram in the OrderingPart Number section.|
|Supplemental Information|•<br>Updated document list.|



## **Revision 0.72, December 2021** 

|**Section**|**Change Summary**|
|---|---|
|General Description|•<br>Removed_52k_logic cells support and related contents.<br>•<br>In the Features section:<br>•<br>changed the programmable sysI/O (High Performance and Wide Range I/O) range<br>to “_200 to 300_”;<br>•<br>changed the small footprint package option to “_14 × 14 mm to 17 × 17 mm_”;<br>•<br>changed to “_up to 1.4 Mb sysMEM Embedded Block RAM (EBR)_” in Flexible<br>memory resources;<br>changed to “_80 kbit distributed RAM_” in Flexible memoryresources.|
|Architecture|Removed the original Figure 2.2 Simplified Block Diagram, Control Jedi-D6-55 Device<br>(TopLevel)from the Overview section.|



© 2021-2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

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**MachXO5-NX Family Data Sheet** 

|**Section**|**Change Summary**|
|---|---|
|Pinout Information|Removed all LFMXO5-55 information from the Pin Information Summarysection.|
|Ordering Information|•<br>Removed 55k logic cells capacity from the Part Number Description section.<br>Removed 484package from the Part Number Description section.|



## **Revision 0.71, October 2021** 

|**Section**|**Change Summary**|
|---|---|
|General Description|Changed_Configuration_to_Non-volatile Configuration_in the Features section.|
|Architecture|•<br>Added description regarding DSP blocks and sysMEM EBR blocks for Jedi-D6 25 device<br>to the Overview section.<br>•<br>Updated Figure 2.1. Simplified Block Diagram, MachXO5-NX-25 Device (Top Level) to<br>show non-volatile configuration and security, and on-chip user flash.<br>Updated description regardingimage configuration in the User Flash Memory (UFM)section.|
|Pinout Information|Added “if not used, tie to ground” to the description for Dedicated ADC I/O Pins, both<br>ADC_REF and ADC_DP/N, in the Signal Descriptions section.|
|DC and Switching Characteristics<br>for Commercial and Industrial|Removed the hyperlink of the D6-Control Product Family Qualification Summary in the ESD<br>Performance section.|



## **Revision 0.70, October 2021** 

|**Section**|**Change Summary**|
|---|---|
|All|Initial Advance release|



© 2021-2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

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169 

www.latticesemi.com
Updated at April 17, 2026
Lattice Semiconductor is a premier developer of low-power, programmable design solutions, specializing in Field-Programmable Gate Arrays (FPGAs) and Programmable Logic Devices (PLDs). Recognized for driving innovation in cost-effective and power-efficient architectures, the company provides essential semiconductor components for consumer, mobile, and industrial design applications. Our selection of Lattice Semiconductor products is focused on their highly regarded FPGA integrated circuits. Devices from industry-leading families like the iCE40, MachXO, and LatticeECP series offer designers an exceptional combination of high system integration and industry-low power consumption. These FPGAs are engineered to handle complex tasks such as sensor management, custom connectivity, and advanced video processing while minimizing overall board footprint. To ensure seamless integration from concept to production, Lattice backs its hardware with a comprehensive support ecosystem. Engineers can accelerate their development cycles utilizing intuitive tools like the Lattice Diamond design software, paired with flexible IP cores and reference designs that reduce design risk and increase system reliability.
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