LFMXO4-025HE-6TSG100I

## Os 

## **MachXO4 Family** 

## **Data Sheet** 

FPGA-DS-02125-1.0 

December 2025 

**MachXO4 Family Data Sheet** 

## **Disclaimers** 

Lattice makes no warranty, representation, or guarantee regarding the accuracy of information contained in this document or the suitability of its products for any particular purpose. All information herein is provided AS IS, with all faults, and all associated risk is the responsibility entirely of the Buyer. The information provided herein is for informational purposes only and may contain technical inaccuracies or omissions, and may be otherwise rendered inaccurate for many reasons, and Lattice assumes no obligation to update or otherwise correct or revise this information. Products sold by Lattice have been subject to limited testing and it is the Buyer's responsibility to independently determine the suitability of any products and to test and verify the same. LATTICE PRODUCTS AND SERVICES ARE NOT DESIGNED, MANUFACTURED, OR TESTED FOR USE IN LIFE OR SAFETY CRITICAL SYSTEMS, HAZARDOUS ENVIRONMENTS, OR ANY OTHER ENVIRONMENTS REQUIRING FAIL-SAFE PERFORMANCE, INCLUDING ANY APPLICATION IN WHICH THE FAILURE OF THE PRODUCT OR SERVICE COULD LEAD TO DEATH, PERSONAL INJURY, SEVERE PROPERTY DAMAGE OR ENVIRONMENTAL HARM (COLLECTIVELY, "HIGH-RISK USES"). FURTHER, BUYER MUST TAKE PRUDENT STEPS TO PROTECT AGAINST PRODUCT AND SERVICE FAILURES, INCLUDING PROVIDING APPROPRIATE REDUNDANCIES, FAIL-SAFE FEATURES, AND/OR SHUT-DOWN MECHANISMS. LATTICE EXPRESSLY DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY OF FITNESS OF THE PRODUCTS OR SERVICES FOR HIGH-RISK USES. The information provided in this document is proprietary to Lattice Semiconductor, and Lattice reserves the right to make any changes to the information in this document or to any products at any time without notice. 

## **Inclusive Language** 

This document was created consistent with Lattice Semiconductor’s inclusive language policy. In some cases, the language in underlying tools and other items may not yet have been updated. Please refer to Lattice’s inclusive language FAQ 6878 for a cross reference of terms. Note in some cases such as register names and state names it has been necessary to continue to utilize older terminology for compatibility. 

© 2025 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02125-1.0 

2 

**MachXO4 Family Data Sheet** 

## **Contents** 

|**Contents**|**Contents**|**Contents**|
|---|---|---|
|Contents ............................................................................................................................................................................... 3|||
|Abbreviations in This Document........................................................................................................................................... 8|||
|1.|Introduction .................................................................................................................................................................. 9||
||1.1.|Features ............................................................................................................................................................ 11|
||1.1.1.|Low Power and Programmable Architecture ............................................................................................... 11|
||1.1.2.|High Performance, Flexible I/O Buffer ......................................................................................................... 11|
||1.1.3.|Pre-Engineered Source Synchronous I/O ..................................................................................................... 11|
||1.1.4.|Broad Range of Advanced Packaging ........................................................................................................... 11|
||1.1.5.|Non-volatile, Multi-time Reconfigurable...................................................................................................... 11|
||1.1.6.|Optimizable On-Chip Clocking ...................................................................................................................... 11|
||1.1.7.|Enhanced System-Level Support .................................................................................................................. 11|
||1.1.8.|State-of-the-Art Design Software ................................................................................................................. 11|
|2.|Architecture ................................................................................................................................................................ 13||
||2.1.|Architecture Overview ...................................................................................................................................... 13|
||2.2.|PFU Blocks ......................................................................................................................................................... 14|
||2.2.1.|Slices ............................................................................................................................................................. 15|
||2.2.2.|Modes of Operation ..................................................................................................................................... 16|
||2.2.3.|RAM Mode ................................................................................................................................................... 16|
||2.2.4.|ROM Mode ................................................................................................................................................... 17|
||2.3.|Routing .............................................................................................................................................................. 17|
||2.4.|Clock/Control Distribution Network .................................................................................................................. 17|
||2.4.1.|sysCLOCK Phase Locked Loops (PLLs) ........................................................................................................... 19|
||2.5.|sysMEM Embedded Block RAM Memory .......................................................................................................... 22|
||2.5.1.|sysMEM Memory Block ................................................................................................................................ 22|
||2.5.2.|Bus Size Matching ......................................................................................................................................... 22|
||2.5.3.|RAM Initialization and ROM Operation ........................................................................................................ 22|
||2.5.4.|Memory Cascading ....................................................................................................................................... 22|
||2.5.5.|Single, Dual, Pseudo-Dual Port and FIFO Modes .......................................................................................... 23|
||2.5.6.|FIFO Configuration ....................................................................................................................................... 24|
||2.5.7.|Memory Core Reset...................................................................................................................................... 24|
||2.5.8.|EBR Asynchronous Reset .............................................................................................................................. 25|
||2.6.|Programmable I/O Cells (PIC) ............................................................................................................................ 26|
||2.7.|PIO ..................................................................................................................................................................... 27|
||2.7.1.|Input Register Block ..................................................................................................................................... 28|
||2.7.2.|Output Register Block................................................................................................................................... 28|
||2.7.3.|Tri-state Register Block ................................................................................................................................. 29|
||2.8.|Input Gearbox ................................................................................................................................................... 29|
||2.9.|Output Gearbox ................................................................................................................................................ 31|
||2.10.|sysI/O Buffer ..................................................................................................................................................... 33|
||2.10.1. Typical I/O Behavior during Power-up ......................................................................................................... 33||
||2.10.2. Supported Standards .................................................................................................................................... 33||
||2.10.3. sysI/O Buffer Banks ...................................................................................................................................... 35||
||2.11.|Hot Socketing .................................................................................................................................................... 36|
||2.12.|On-chip Oscillator .............................................................................................................................................. 36|
||2.13.|Embedded Hardened IP Functions .................................................................................................................... 36|
||2.13.1. Hardened I2C IP Core ................................................................................................................................... 37||
||2.13.2. Hardened SPI IP Core.................................................................................................................................... 38||
||2.13.3. Hardened Timer/Counter ............................................................................................................................. 40||
||2.14.|User Flash Memory (UFM) ................................................................................................................................ 41|
||2.15.|Stand-by Mode and Power Saving Options ....................................................................................................... 41|
||2.16.|Power On Reset ................................................................................................................................................. 42|
||2.17.|Configuration and Testing ................................................................................................................................. 42|



© 2025 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02125-1.0 

3 

**MachXO4 Family Data Sheet** 

||2.17.1. IEEE 1149.1-Compliant Boundary Scan Testability ....................................................................................... 42|
|---|---|
||2.17.2. Device Configuration .................................................................................................................................... 42|
||2.18.<br>TraceID .............................................................................................................................................................. 44|
||2.19.<br>Density Shifting ................................................................................................................................................. 44|
|3.|DC and Switching Characteristics ............................................................................................................................... 45|
||3.1.<br>Absolute Maximum Rating ................................................................................................................................ 45|
||3.2.<br>Recommended Operating Conditions ............................................................................................................... 45|
||3.3.<br>Power Supply Ramp Rates ................................................................................................................................ 45|
||3.4.<br>Power-On-Reset Voltage Levels ........................................................................................................................ 46|
||3.5.<br>Hot Socketing Specifications ............................................................................................................................. 46|
||3.6.<br>Programming/Erase Specifications ................................................................................................................... 47|
||3.7.<br>ESD Performance .............................................................................................................................................. 47|
||3.8.<br>DC Electrical Characteristics .............................................................................................................................. 47|
||3.9.<br>Static Supply Current – HC/HE Devices ............................................................................................................. 49|
||3.10.<br>Programming and Erase Supply Current – HC/HE Devices ................................................................................ 50|
||3.11.<br>sysI/O Recommended Operating Conditions ..................................................................................................... 50|
||3.12.<br>sysI/O Single-Ended DC Electrical Characteristics ............................................................................................. 51|
||3.13.<br>sysI/O Differential Electrical Characteristics ..................................................................................................... 52|
||3.13.1. LVDS ............................................................................................................................................................. 52|
||3.13.2. LVDS Emulation ............................................................................................................................................ 53|
||3.13.3. BLVDS ........................................................................................................................................................... 53|
||3.13.4. LVPECL .......................................................................................................................................................... 54|
||3.13.5. MIPI D-PHY Emulation .................................................................................................................................. 55|
||3.13.6. Comparator Function ................................................................................................................................... 58|
||3.14.<br>Typical Building Block Function Performance – HC/HE Devices ....................................................................... 59|
||3.14.1. Pin-to-Pin Performance (LVCMOS25 12 mA Drive) ...................................................................................... 59|
||3.14.2. Register-to-Register Performance ................................................................................................................ 59|
||3.15.<br>Derating Logic Timing ........................................................................................................................................ 59|
||3.16.<br>Maximum sysI/O Buffer Performance .............................................................................................................. 60|
||3.17.<br>External Switching Characteristics – HC/HE Devices ......................................................................................... 61|
||3.18.<br>sysCLOCK PLL Timing ......................................................................................................................................... 69|
||3.19.<br>Oscillator Output Frequency ............................................................................................................................. 70|
||3.20.<br>Flash Download Time ........................................................................................................................................ 70|
||3.21.<br>JTAG Port Timing Specifications ........................................................................................................................ 71|
||3.22.<br>sysCONFIG Port Timing Specifications .............................................................................................................. 72|
||3.23.<br>I2C Port Timing Specifications ........................................................................................................................... 73|
||3.24.<br>SPI Port Timing Specifications ........................................................................................................................... 73|
||3.25.<br>Switching Test Conditions ................................................................................................................................. 73|
|4.|Signal Descriptions ...................................................................................................................................................... 74|
||4.1.<br>Pin Information Summary ................................................................................................................................. 75|
|5.|MachXO4 Part Number Description ........................................................................................................................... 81|
|6.|Ordering Information ................................................................................................................................................. 82|
||6.1.<br>MachXO4 High Performance Commercial Grade Devices, Packaging ............................................................... 82|
||6.2.<br>MachXO4 High Performance Industrial Grade Devices, Packaging ................................................................... 85|
||6.3.<br>MachXO4 High Performance Automotive Grade Devices, Packaging ............................................................... 87|
|References .......................................................................................................................................................................... 89||
|Technical Support Assistance ............................................................................................................................................. 90||
|Revision History .................................................................................................................................................................. 91||



© 2025 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02125-1.0 

4 

**MachXO4 Family Data Sheet** 

## **Figures** 

Figure 2.1. Top View of the LFMXO4-015 Part ................................................................................................................... 13 Figure 2.2. Top View of the LFMXO4-050 Part ................................................................................................................... 13 Figure 2.3. PFU Block Diagram ............................................................................................................................................ 14 Figure 2.4. Slice Diagram .................................................................................................................................................... 15 Figure 2.5. Primary Clocks for MachXO4 Devices ............................................................................................................... 18 Figure 2.6. Secondary High Fanout Nets for MachXO4 Devices ......................................................................................... 19 Figure 2.7. PLL Diagram ...................................................................................................................................................... 20 Figure 2.8. sysMEM Memory Primitives ............................................................................................................................. 23 Figure 2.9. Memory Core Reset .......................................................................................................................................... 25 Figure 2.10. EBR Asynchronous Reset (Including GSR) Timing Diagram ............................................................................. 25 Figure 2.11. Group of Four Programmable I/O Cells .......................................................................................................... 27 Figure 2.12. Output Register Block Diagram (PIO on the Left, Top and Bottom Edges) ..................................................... 29 Figure 2.13. Input Gearbox ................................................................................................................................................. 30 Figure 2.14. Output Gearbox .............................................................................................................................................. 32 Figure 2.15. LFMXO4-015 in 256 Ball Packages, LFMXO4-025, LFMXO4-050, LFMXO4-080, and LFMXO4-110  I/O Banks ............................................................................................................................................................................................ 35 Figure 2.16.LFMXO4-010 and LFMXO4-015 in Non-256 Ball Packages I/O Banks .............................................................. 35 Figure 2.17. Embedded Function Block Interface ............................................................................................................... 37 Figure 2.18. I2C Core Block Diagram .................................................................................................................................. 37 Figure 2.19. SPI Core Block Diagram ................................................................................................................................... 39 Figure 2.20. Timer/Counter Block Diagram ........................................................................................................................ 40 Figure 3.1. LVDS Using External Resistors (LVDS25E) ......................................................................................................... 53 Figure 3.2. BLVDS Multi-point-Output Example ................................................................................................................. 54 Figure 3.3. Differential LVPECL ........................................................................................................................................... 55 Figure 3.4. MIPI D-PHY Input Using External Resistors ....................................................................................................... 56 Figure 3.5. MIPI D-PHY Output Using External Resistors .................................................................................................... 57 Figure 3.6. Comparator Function Using Referenced Input Buffers .................................................................................... 58 Figure 3.7.Receiver GDDR71_RX. Waveforms .................................................................................................................... 68 Figure 3.8. Transmitter GDDR71_TX. Waveforms .............................................................................................................. 68 Figure 3.9. JTAG Port Timing Waveforms ........................................................................................................................... 71 Figure 3.10. Output Test Load, LVTTL and LVCMOS Standards .......................................................................................... 73 

© 2025 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02125-1.0 

5 

**MachXO4 Family Data Sheet** 

## **Tables** 

|Table 1.1. Specification Status for MachXO4 Family Devices ............................................................................................. 10|Table 1.1. Specification Status for MachXO4 Family Devices ............................................................................................. 10|
|---|---|
|Table 1.2. MachXO4 Family Selection Guide ...................................................................................................................... 12|Table 1.2. MachXO4 Family Selection Guide ...................................................................................................................... 12|
|Table 2.1. Resources and Modes Available per Slice .......................................................................................................... 15|Table 2.1. Resources and Modes Available per Slice .......................................................................................................... 15|
|Table 2.2. Slice Signal Descriptions ..................................................................................................................................... 16|Table 2.2. Slice Signal Descriptions ..................................................................................................................................... 16|
|Table 2.3. Number of Slices Required For Implementing Distributed RAM ....................................................................... 17|Table 2.3. Number of Slices Required For Implementing Distributed RAM ....................................................................... 17|
|Table 2.4. PLL Signal Descriptions ....................................................................................................................................... 21|Table 2.4. PLL Signal Descriptions ....................................................................................................................................... 21|
|Table 2.5. sysMEM Block Configurations ............................................................................................................................ 22|Table 2.5. sysMEM Block Configurations ............................................................................................................................ 22|
|Table 2.6. EBR Signal Descriptions ...................................................................................................................................... 23|Table 2.6. EBR Signal Descriptions ...................................................................................................................................... 23|
|Table 2.7. Programmable FIFO Flag Ranges ....................................................................................................................... 24|Table 2.7. Programmable FIFO Flag Ranges ....................................................................................................................... 24|
|Table 2.8. PIO Signal List ..................................................................................................................................................... 28|Table 2.8. PIO Signal List ..................................................................................................................................................... 28|
|Table 2.9. Input Gearbox Signal List ................................................................................................................................... 29|Table 2.9. Input Gearbox Signal List ................................................................................................................................... 29|
|Table 2.10. Output Gearbox Signal List .............................................................................................................................. 31|Table 2.10. Output Gearbox Signal List .............................................................................................................................. 31|
|Table 2.11. Supported Input Standards .............................................................................................................................. 34|Table 2.11. Supported Input Standards .............................................................................................................................. 34|
|Table 2.12. Supported Output Standards ........................................................................................................................... 34|Table 2.12. Supported Output Standards ........................................................................................................................... 34|
|Table 2.13. Available MCLK Frequencies ............................................................................................................................ 36|Table 2.13. Available MCLK Frequencies ............................................................................................................................ 36|
|Table 2.14. I2C Core Signal Description .............................................................................................................................. 38|Table 2.14. I2C Core Signal Description .............................................................................................................................. 38|
|Table 2.15. SPI Core Signal Description .............................................................................................................................. 39|Table 2.15. SPI Core Signal Description .............................................................................................................................. 39|
|Table 2.16. Timer/Counter Signal Description .................................................................................................................... 40|Table 2.16. Timer/Counter Signal Description .................................................................................................................... 40|
|Table 2.17. MachXO4 Power Saving Features Description ................................................................................................. 41|Table 2.17. MachXO4 Power Saving Features Description ................................................................................................. 41|
|Table 3.1. Absolute Maximum Rating|Table 3.1. Absolute Maximum Rating1, 2, 3.......................................................................................................................... 45|
|Table 3.2. Recommended Operating Conditions|Table 3.2. Recommended Operating Conditions1.............................................................................................................. 45|
|Table 3.3. Power Supply Ramp Rates ................................................................................................................................. 45|Table 3.3. Power Supply Ramp Rates ................................................................................................................................. 45|
|Table 3.4. Power-On Reset Voltage Levels ......................................................................................................................... 46|Table 3.4. Power-On Reset Voltage Levels ......................................................................................................................... 46|
|Table 3.5. Hot Socketing Specifications .............................................................................................................................. 46|Table 3.5. Hot Socketing Specifications .............................................................................................................................. 46|
|Table 3.6. Programming/Erase Specifications .................................................................................................................... 47|Table 3.6. Programming/Erase Specifications .................................................................................................................... 47|
|Table 3.7. DC Electrical Characteristics ............................................................................................................................... 47|Table 3.7. DC Electrical Characteristics ............................................................................................................................... 47|
|Table 3.8. Static Supply Current – HC/HE Devices|Table 3.8. Static Supply Current – HC/HE Devices1, 2, 3, 6..................................................................................................... 49|
|Table 3.9. Programming and Erase Supply Current – HC/HE Devices|Table 3.9. Programming and Erase Supply Current – HC/HE Devices1, 2, 3, 4....................................................................... 50|
|Table 3.10. sysI/O Recommended Operating Conditions ................................................................................................... 50|Table 3.10. sysI/O Recommended Operating Conditions ................................................................................................... 50|
|Table 3.11. sysI/O Single-Ended DC Electrical Charateristics|Table 3.11. sysI/O Single-Ended DC Electrical Charateristics1, 2, 4....................................................................................... 51|
|Table 3.12. LVDS ................................................................................................................................................................. 52|Table 3.12. LVDS ................................................................................................................................................................. 52|
|Table 3.13. LVDS25E DC Conditions .................................................................................................................................... 53|Table 3.13. LVDS25E DC Conditions .................................................................................................................................... 53|
|Table 3.14. BLVDS DC Condition ......................................................................................................................................... 54|Table 3.14. BLVDS DC Condition ......................................................................................................................................... 54|
|Table 3.15. LVPECL DC Conditions ...................................................................................................................................... 55|Table 3.15. LVPECL DC Conditions ...................................................................................................................................... 55|
|Table 3.16. MIPI DC Conditions .......................................................................................................................................... 56|Table 3.16. MIPI DC Conditions .......................................................................................................................................... 56|
|Table 3.17. MIPI D-PHY Output DC Conditions ................................................................................................................... 58|Table 3.17. MIPI D-PHY Output DC Conditions ................................................................................................................... 58|
|Table 3.18. Comparator Specifications|Table 3.18. Comparator Specifications1.............................................................................................................................. 59|
|Table 3.19. Pin-to-Pin Performance (LVCMOS25 12 mA Drive) .......................................................................................... 59|Table 3.19. Pin-to-Pin Performance (LVCMOS25 12 mA Drive) .......................................................................................... 59|
|Table 3.20. Register-to-Register Performance ................................................................................................................... 59|Table 3.20. Register-to-Register Performance ................................................................................................................... 59|
|Table 3.21. Maximum sysI/O Buffer Performance ............................................................................................................. 60|Table 3.21. Maximum sysI/O Buffer Performance ............................................................................................................. 60|
|Table 3.22. MachXO4 External Switching Characteristics – HC/HE Devices|Table 3.22. MachXO4 External Switching Characteristics – HC/HE Devices1, 2, 3, 4, 5, 6, 10..................................................... 61|
|Table 3.23. sysCLOCK PLL Timing ........................................................................................................................................ 69|Table 3.23. sysCLOCK PLL Timing ........................................................................................................................................ 69|
|Table 3.24. Oscillator Output Frequency ............................................................................................................................ 70|Table 3.24. Oscillator Output Frequency ............................................................................................................................ 70|
|Table 3.25. Flash Download Time ....................................................................................................................................... 70|Table 3.25. Flash Download Time ....................................................................................................................................... 70|
|Table 3.26. JTAG Port Timing Specifications ....................................................................................................................... 71|Table 3.26. JTAG Port Timing Specifications ....................................................................................................................... 71|
|Table 3.27. sysCONFIG Port Timing Specifications ............................................................................................................. 72|Table 3.27. sysCONFIG Port Timing Specifications ............................................................................................................. 72|
|Table 3.28. I2C Port Timing Specification ........................................................................................................................... 73|Table 3.28. I2C Port Timing Specification ........................................................................................................................... 73|
|Table 3.29. SPI Port Timing Specifications .......................................................................................................................... 73|Table 3.29. SPI Port Timing Specifications .......................................................................................................................... 73|
|Table 3.30. Test Fixture Required Components, Non-Terminated Interfaces .................................................................... 73|Table 3.30. Test Fixture Required Components, Non-Terminated Interfaces .................................................................... 73|
|Table 4.1. Signal Descriptions ............................................................................................................................................. 74|Table 4.1. Signal Descriptions ............................................................................................................................................. 74|
|Table 4.2. LFMXO4-010 and LFMXO4-015 Pin Summary .................................................................................................... 75|Table 4.2. LFMXO4-010 and LFMXO4-015 Pin Summary .................................................................................................... 75|
|Table 4.3. LFMXO4-025 Pin Summary ................................................................................................................................ 76|Table 4.3. LFMXO4-025 Pin Summary ................................................................................................................................ 76|



© 2025 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02125-1.0 

6 

**MachXO4 Family Data Sheet** 

|Table 4.4. LFMXO4-050 Pin Summary ................................................................................................................................ 78|Table 4.4. LFMXO4-050 Pin Summary ................................................................................................................................ 78|Table 4.4. LFMXO4-050 Pin Summary ................................................................................................................................ 78|Table 4.4. LFMXO4-050 Pin Summary ................................................................................................................................ 78|
|---|---|---|---|
|Table 4.5. LFMXO4-080 Pin Summary ................................................................................................................................ 79|Table 4.5. LFMXO4-080 Pin Summary ................................................................................................................................ 79|Table 4.5. LFMXO4-080 Pin Summary ................................................................................................................................ 79|Table 4.5. LFMXO4-080 Pin Summary ................................................................................................................................ 79|
|Table 4.6. LFMXO4-110 Pin Summary ................................................................................................................................ 80|Table 4.6. LFMXO4-110 Pin Summary ................................................................................................................................ 80|Table 4.6. LFMXO4-110 Pin Summary ................................................................................................................................ 80|Table 4.6. LFMXO4-110 Pin Summary ................................................................................................................................ 80|



© 2025 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02125-1.0 

7 

**MachXO4 Family Data Sheet** 

**Abbreviations in This Document** A list of abbreviations used in this document. **Abbreviation Definition** ~~a a~~ AES Advanced Encryption Standard ~~ee~~ BGA Ball Grid Array ~~Ce~~ caBGA ChipArray Ball Grill Array ~~Ce~~ csfBGA Chip Scale Flip-Chip Ball Grid Array CE Clock Enable ~~a a~~ CLK System clock ~~a~~ CMOS Complementary Metal Oxide Semiconductor DDR Double Data Rate ~~ee~~ EBR Embedded Block RAM ~~Ce Ce~~ ECDSA Elliptic Curve Digital Signature Algorithm ~~a~~ ECLK Edge Clock ~~a a~~ FCIN Fast Carry In ~~a~~ FCO Fast Carry Out I2C Inter-Integrated Circuit ~~a~~ IP Intellectual Property ~~a~~ I/O Input/Output ~~a~~ JTAG Joint Test Action Group ~~a~~ LED Light-emitting Diode ~~a~~ LSR Local Set/Reset ~~a~~ LUT Look-Up Table ~~a~~ LVCMOS Low-Voltage CMOS ~~a~~ LVDS Low-Voltage Differential Signaling ~~eG~~ LVPECL Low-Voltage Positive/Pseudo Emitter-Coupled Logic ~~a~~ LVTTL Low Voltage Transistor to Transistor Logic ~~a~~ MIPI Mobile Industry Processor Interface ~~a~~ MLVDS Multipoint Low-Voltage Differential Signaling ~~a~~ PCI Peripheral Component Interconnect ~~a~~ PCLK Primary Clock PDPR Pseudo Dual Port RAM ~~a a~~ PFU Programmable Functional Unit ~~a~~ PIC Programmable Interface Controllers ~~a~~ PIO Programmed Input/Output ~~a~~ PLD Programmable Logic Device ~~a~~ PLL Phase Locked Loop ~~a~~ RAM Random Access Memory ~~a~~ ROM Read-only Memory ~~a~~ SDR Single Data Rate SHA Secure Hash Algorithm ~~ee~~ SPI Serial Peripheral Interface ~~ee a~~ SPR Single Port Random Access Memory ~~a~~ SRAM Static Random Access Memory ~~a~~ TransFR™ Transparent Field Reconfiguration ~~a~~ UFM User Flash Memory ~~=Ge~~ WLCSP Wafer Level Chip Scale Package © 2025 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02125-1.0 

8 

**MachXO4 Family Data Sheet** 

## **1. Introduction** 

The MachXO4™ family of ultra-low-density and low-power FPGAs support advanced programmable bridging and I/O expansion, making it ideal for a variety of applications in consumer electronics, computing and storage, wireless communications, industrial control, and automotive systems. It offers exceptional I/O density and a wide range of programmability options with integrated support for the latest industry-standard I/O interfaces. 

The MachXO4 family consists of low-power, instant-on, non-volatile, and Flash-based FPGAs with six devices, featuring densities ranging from 896 to 9400 Look-Up Tables (LUTs). These devices include LUT-based programmable logic, Embedded Block RAM (EBR), Distributed RAM, User Flash Memory (UFM), Phase Locked Loops (PLLs), pre-engineered source synchronous I/O support, advanced configuration support including dual-boot capability, and hardened versions of commonly used functions such as SPI controller, I2C controller, and timer/counter. 

Built on a 65 nm non-volatile low-power process, MachXO4 devices offer several architectural features to manage static and dynamic power consumption including programmable low swing differential I/O, the ability to turn off I/O banks, and dynamically controlled on-chip PLLs and oscillators. 

The MachXO4 devices come in high-performance version, HC and HE. The high-performance devices are available in two speed grades, –5 and –6, with –6 being faster. HC devices have an internal linear voltage regulator supporting external VCC supply voltages of 3.3 V or 2.5 V, while HE devices accept only 1.2 V as the external VCC supply voltage. All HC and HE parts  are functionally and pin-compatible. 

These FPGAs are available in a range of advanced halogen-free packages, from the compact 2.5 x 2.5 mm WLCSP to the 20 x 20 mm TQFP, supporting density migration within the same package. Table 1.2 shows the logic densities, package, and I/O options, along with other key parameters. 

The MachXO4 devices also provide enhanced I/O features such as drive strength control, slew rate control, PCI compatibility, bus-keeper latches, pull-up resistors, pull-down resistors, open drain outputs, and hot socketing. Pull-up, pull-down, and bus-keeper features are controllable on a per-pin basis. 

Additionally, a user-programmable internal oscillator is included in MachXO4 devices. The clock output from this oscillator may be divisible by the timer/counter and can be used as a clock input in functions such as LED control, keyboard scanning, and similar state machines. 

These devices also offer flexible, reliable, and secure configuration from on-chip Flash with encryption and authentication options. They can configure themselves from external SPI Flash or be configured by an external master through the JTAG test access port or the SPI/I2C port. Moreover, MachXO4 devices support dual-boot capability using external Flash memory and remote field upgrade TransFR capability. 

Meanwhile, Lattice Radiant™ design software allows large complex user designs to be efficiently implemented on the MachXO4 FPGA family. Synthesis library support for these devices is available for popular logic synthesis tools. Radiant tools use the synthesis tool output along with constraints from its floor planning tools, to place and route the user design in a MachXO4 device. The tools extract timing from the routing and back-annotate it into the design for timing verification. Lattice Semiconductor provides many pre-engineered Intellectual Property (IP) modules for the MachXO4 family. By using these configurable soft IP cores as standardized blocks, designers can concentrate on the unique aspects of their design, increasing productivity. 

© 2025 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02125-1.0 

9 

**MachXO4 Family Data Sheet** 

**Table 1.1. Specification Status for MachXO4 Family Devices** 

|**Device**<br>~~GC~~<br>~~oe~~|**Variant**<br>~~GC~~<br>~~oe~~|**Package **<br>~~GC~~<br>~~oe~~|**Grade**<br>~~GC~~<br>~~oe~~|**Status**<br>~~GC~~<br>~~oe~~|
|---|---|---|---|---|
|LFMXO4-010<br>~~oe~~|HC<br>~~oe~~|TSG100, BSG132, and TSG144<br>~~oe~~|Commercial/Industrial/Automotive<br>~~oe~~|Production<br>~~oe~~|
||HE<br>~~oe~~<br>~~a~~|TSG100, BSG132, and TSG144<br>~~oe~~|Commercial/Industrial/Automotive<br>~~oe~~|Production<br>~~oe~~|
|LFMXO4-015<br>~~oe~~<br>~~a~~|HC<br>~~oe~~<br>~~a~~|TSG100, BSG132, TSG144,<br>BBG256, and BFG256<br>~~oe~~<br>~~ee~~|Commercial/Industrial/Automotive<br>~~oe~~|Production<br>~~oe~~|
||HE<br>~~a~~|TSG100, BSG132, TSG144,<br>BBG256, BFG256, and UUG36<br>~~ee~~|Commercial/Industrial/Automotive|Production|
|LFMXO4-025<br>~~a~~<br>~~a~~<br>~~——————~~|HC<br>~~a~~<br>~~a~~|TSG100, BSG132, TSG144,<br>BBG256, and BFG256<br>~~ee~~<br>~~ee~~|Commercial/Industrial/Automotive|Production|
||HE<br>~~a~~<br>~~——————~~|TSG100, BSG132, TSG144,<br>BBG256, BFG256, and UUG49<br>~~ee~~<br>~~——————~~|Commercial/Industrial/Automotive<br>~~——————~~|Production<br>~~——————~~|
|LFMXO4-050<br>~~a~~<br>~~——————~~<br>~~ee~~|HC<br>~~a~~<br>~~——————~~|BSG132, TSG144, BBG256,<br>BBG400, and BFG256<br>~~ee~~<br>~~——————~~|Commercial/Industrial/Automotive<br>~~——————~~|Production<br>~~——————~~|
||HE<br>~~——————~~<br>~~**a**~~<br>|BSG132, TSG144, BBG256,<br>BBG400, BFG256, and UUG81<br>~~——————~~<br>~~ee~~<br>|Commercial/Industrial/Automotive<br>~~——————~~<br>~~ee~~|Production<br>~~——————~~<br>~~ee~~|
|LFMXO4-080<br>~~——————~~<br>~~eeeS~~|HC<br>~~——————~~<br>~~**a**~~<br>|BBG256 and BBG400<br>~~——————~~<br>~~ee~~<br>|Commercial/Industrial<br>~~——————~~<br>~~ee~~|Production<br>~~——————~~<br>~~ee~~|
||HE<br>~~**a**~~<br>~~eS~~|BBG256 and BBG400<br>~~ee~~<br>~~eS~~|Commercial/Industrial<br>~~ee~~|Production<br>~~ee~~<br>~~eee~~|
|LFMXO4-110<br>~~eeeS~~|HC<br>~~**a**~~<br>~~eS~~|BBG256, BBG400, and BBG484<br>~~ee~~<br>~~eS~~|Commercial/Industrial<br>~~ee~~|Production<br>~~ee~~<br>~~eee~~|
||HE<br>~~eS~~<br>~~a~~|BBG256, BBG400, and BBG484<br>~~eS~~<br>~~a~~|Commercial/Industrial|Production<br>~~eee~~|



© 2025 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02125-1.0 

10 

**MachXO4 Family Data Sheet** 

## **1.1. Features** 

## **1.1.1. Low Power and Programmable Architecture** 

- Logic density ranging from 896 to 9.4k LUT4 

- 64 to 432 kb of Embedded Block Memory (EBR) 

- Up to 54 kb of Distributed RAM 

- Dedicated FIFO control logic 

- Advanced 65 nm low power process 

- Programmable low swing differential I/O 

- Stand-by mode and other power-saving options 

## **1.1.2. High Performance, Flexible I/O Buffer** 

- Programmable sysI/O™ buffer supports a wide range of interfaces: 

   - LVCMOS 3.3/2.5/1.8/1.5/1.2/1.0 

   - LVTTL 

   - LVDS, Bus-LVDS, MLVDS, LVPECL 

   - MIPI D-PHY Emulated 

   - Schmitt trigger inputs, up to 0.5 V hysteresis 

- I/O support hot socketing 

- On-chip differential termination 

- Programmable pull-up or pull-down mode 

## **1.1.3. Pre-Engineered Source Synchronous I/O** 

- DDR registers in I/O cells 

- Dedicated gearing logic 

- 7:1 Gearing for Display I/O 

- Generic DDR, DDRx2, DDRx4 

## **1.1.5. Non-volatile, Multi-time Reconfigurable** 

- Instant-on; Powers up in milliseconds 

- Optional dual boot with external SPI memory 

- Single-chip, secure solution 

- Programmable through JTAG, SPI or I2C 

- Reconfigurable Flash up to 100,000 write/erase cycles for commercial/industrial devices and 10,000 write/erase cycles for automotive devices 

- Supports background programming of non-volatile memory 

- In-field logic update while I/O holds the system state through TransFR reconfiguration 

## **1.1.6. Optimizable On-Chip Clocking** 

- On-chip oscillator with 5.5% accuracy for commercial/industrial devices 

- Eight primary clocks 

- Up to two edge clocks for high-speed I/O interfaces, top and bottom sides only 

- Up to two analog PLLs per device with fractional-n frequency synthesis 

- Wide input frequency range, 7 MHz to 400 MHz 

## **1.1.7. Enhanced System-Level Support** 

- On-chip hardened functions: SPI, I2C, and timer/counter 

- Unique TraceID for system tracking 

- Single power supply with extended operating range 

- IEEE Standard 1149.1 boundary scan 

## **1.1.4. Broad Range of Advanced Packaging** 

- Compact packages with high I/O-to-LUT ratio up to 382 I/O pins 

- 0.4 mm pitch: 1280 to 4320 LUTs in very small footprint WLCSP (2.5 × 2.5 mm to 3.8 × 3.8 mm) with 27 to 62 I/O 

- 0.5 mm pitch: 896 to 4320 LUTs in 8 x 8 mm BGA to 20 x 20 mm TQFP packages with up to 112 I/O 

- 0.8 mm pitch: 1280 to 9400 LUTs in 14 x 14 mm to 19 x 19 mm BGA packages with up to 382 I/O 

- IEEE 1532 compliant in-system programming 

## **1.1.8. State-of-the-Art Design Software** 

   - MachXO4 device is supported in Lattice Radiant 

   - • Industry-leading RTL language support for VHDL, VHDL-2008, Verilog, and SystemVerilog 

   - Advanced scripting capability on command-line and TCL design flow 

   - One-click compilation flow and cross-probing between analysis tools 

   - Embedded timing and logic analyzer 

- 1.0 mm pitch: 1280 to 4320 LUTs in 17 x 17 mm BGA package with 204 I/O 

© 2025 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02125-1.0 

11 

**MachXO4 Family Data Sheet** 

**Table 1.2. MachXO4 Family Selection Guide** 

|**Features**<br>**LFMXO4-010**<br>**LFMXO4-015**<br>**LFMXO4-025**<br>**LFMXO4-050**<br>**LFMXO4-080**<br>**LFMXO4-110**<br>~~a~~||
|---|---|
|LUTs<br>896<br>1280<br>2112<br>4320<br>68644<br>94004<br>~~a~~||
|Logic Cells<br>1100<br>1600<br>2600<br>5200<br>8300<br>11300<br>~~a~~||
|Distributed RAM(kb)<br>10<br>10<br>16<br>34<br>54<br>73<br>~~a~~||
|Embedded RAM(kb)<br>64<br>64<br>74<br>92<br>240<br>432<br>Embedded RAM<br>(M9k Blocks)<br>7<br>7<br>8<br>10<br>26<br>48<br>User Flash Memory (kb)<br>64<br>64<br>80<br>96<br>256<br>448<br>Device<br>Options<br>HC1<br>Yes<br>Yes<br>Yes<br>Yes<br>Yes<br>Yes<br>HE2<br>Yes<br>Yes<br>Yes<br>Yes<br>Yes<br>Yes<br>Number of PLLs<br>1<br>1<br>1<br>2<br>2<br>2<br>~~a~~<br>~~es eeee~~<br>~~a~~<br>~~0~~<br>~~ee ee ee~~<br>~~ee~~<br>~~a~~<br>~~a~~<br>~~a~~||
|Hardened<br>Functions<br>I2C<br>2<br>2<br>2<br>2<br>2<br>2<br>SPI<br>1<br>1<br>1<br>1<br>1<br>1<br>Timer/Counter<br>1<br>1<br>1<br>1<br>1<br>1<br>Oscillator<br>1<br>1<br>1<br>1<br>1<br>1<br>~~a~~<br>~~a~~<br>~~SSS SS~~<br>~~a~~||
|MIPI D-PHY Support<br>Yes<br>Yes<br>Yes<br>Yes<br>Yes<br>Yes<br>~~a~~||
|Automotive Qualified<br>Yes<br>Yes<br>Yes<br>Yes<br>No<br>No<br>~~a~~||
|**Packages**<br>**Total I/O Count**<br>36-ball WLCSP3<br>(2.5 mm x 2.5 mm, 0.4 mm)<br>27<br>49-ball WLCSP3<br>(3.2 mm x 3.2 mm, 0.4 mm)<br>37<br>81-ball WLCSP3<br>(3.8 mm x 3.8 mm, 0.4 mm)<br>62<br>100-pin TQFP<br>(14 mm x 14 mm, 0.5 mm)<br>785<br>785<br>785<br>~~a~~<br>~~a~~<br>~~ee~~<br>~~a~~<br>~~ee~~<br>~~ee ee~~<br>~~a~~<br>~~ee ee ee~~<br>~~a a~~<br>~~a ee~~||
|132-ball csBGA<br>(8 mm x 8 mm, 0.5 mm)<br>1025<br>1025<br>1025<br>1025<br>144-pin TQFP<br>(20 mm x 20 mm, 0.5 mm)<br>105<br>105<br>109<br>112<br>256-ball caBGA<br>(14 mm x 14 mm, 0.8 mm)<br>2045<br>2045<br>2045<br>204<br>204<br>~~eee~~<br>~~|S~~<br>~~ess~~||
|400-ball caBGA<br>(17 mm x 17 mm, 0.8 mm)<br>333<br>333<br>333<br>484-ball caBGA<br>(19 mm x 19 mm, 0.8 mm)<br>382<br>256-ball ftBGA<br>(17 mm x 17 mm, 1.0 mm)<br>204<br>204<br>204<br>~~rr~~<br>~~ee eee eee~~<br>~~a~~<br>~~ee ee~~<br>~~ee~~<br>~~a~~||



**Notes:** 

1. High performance with regulator, VCC = 2.5 V/3.3 V. 

2. High performance without regulator, VCC = 1.2 V. 

3. Package is only available for E = 1.2 V devices. 

4. Refer to Power and Thermal Estimation and Management for MachXO4 Devices (FPGA-TN-02409) for determination of safe ambient operating conditions. 

5. Package is available for automotive devices, HC and HE variants. 

© 2025 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02125-1.0 

12 

**MachXO4 Family Data Sheet** 

## **2. Architecture** 

## **2.1. Architecture Overview** 

The MachXO4 family architecture contains an array of logic blocks surrounded by Programmable I/O (PIO). All logic density devices in this family have sysCLOCK™ PLLs and blocks of sysMEM Embedded Block RAM (EBRs). Figure 2.1 and Figure 2.2 show the block diagrams of the various family members. 

**==> picture [450 x 137] intentionally omitted <==**

**----- Start of picture text -----**<br>
Embedded Function Block (EFB)<br>User Flash Memory (UFM)<br>es<br>sysCLOCK PLL<br>sysMEM Embedded Block RAM (EBR)<br>On-chip Configuration Flash<br>Memory<br>Programmable Function Units with<br>Distributed RAM (PFUs)<br>PIOs Arranged into<br>sysI/O Banks<br>**----- End of picture text -----**<br>


## **Figure 2.1. Top View of the LFMXO4-015 Part** 

**Notes:** 

- LFMXO4-010 part is similar to LFMXO4-015 part. 

- LFMXO4-010 has a lower LUT count. 

**==> picture [57 x 89] intentionally omitted <==**

**----- Start of picture text -----**<br>
sysCLOCK PLL<br>Configuration<br>Flash<br>PIOs Arranged Into<br>sysIO Banks<br>**----- End of picture text -----**<br>


**==> picture [88 x 150] intentionally omitted <==**

**----- Start of picture text -----**<br>
Embedded<br>Function Block (EFB)<br>UFM<br>sysMEM Embedded<br>Block (EBR)<br>Programmable Function Units<br>with Distributed RAM (PFUs)<br>**----- End of picture text -----**<br>


**Notes** : 

MachXO4-025, MachXO4-080 and MachXO4-110 are similar to MachXO4-050. MachXO4-025 has a lower LUT count, one PLL, and eight EBR blocks. 

MachXO4-080 has a higher LUT count, two PLLs, and 26 EBR blocks. MachXO4-110 has a higher LUT count, two PLLs, and 48 EBR blocks. 

**Figure 2.2. Top View of the LFMXO4-050 Part** 

© 2025 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02125-1.0 

13 

**MachXO4 Family Data Sheet** 

The logic blocks, Programmable Functional Unit (PFU) and sysMEM EBR blocks, are arranged in a two-dimensional grid with rows and columns. Each row has either the logic blocks or the EBR blocks. The PIO cells are located at the periphery of the device, arranged in banks. The PFU contains the building blocks for logic, arithmetic, RAM, ROM, and register functions. The PIOs utilize a flexible I/O buffer referred to as a sysI/O buffer that supports operation with a variety of interface standards. The blocks are connected with many vertical and horizontal routing channel resources. The place and route software tool automatically allocates these routing resources. 

In the MachXO4 family, the number of sysI/O banks varies by device. There are different types of I/O buffers on the different banks. Refer to the details in later sections of this document. The sysMEM EBRs are large, dedicated fast memory blocks. These blocks can be configured as RAM, ROM or FIFO. FIFO support includes dedicated FIFO pointer and flag “hard” control logic to minimize LUT usage. 

The MachXO4 registers in PFU and sysI/O can be configured to be SET or RESET. After power up and device is configured, the device enters into user mode with these registers SET/RESET according to the configuration set-ting, allowing device entering to a known state for predictable system function. 

The MachXO4 architecture also provides up to two sysCLOCK Phase Locked Loop (PLL) blocks. These blocks are located at the ends of the on-chip Flash block. The PLLs have multiply, divide, and phase shifting capabilities that are used to manage the frequency and phase relationships of the clocks. 

MachXO4 devices provide commonly used hardened functions such as SPI controller, I[2] C controller and timer/ counter. MachXO4 devices also provide User Flash Memory (UFM). These hardened functions and the UFM interface to the core logic and routing through a WISHBONE interface. The UFM can also be accessed through the SPI, I[2] C and JTAG ports. 

Every device in the family has a JTAG port that supports programming and configuration of the device as well as access to the user logic. The MachXO4 devices are available for operation from 3.3 V, 2.5 V and 1.2 V power supplies, providing easy integration into the overall system. 

## **2.2. PFU Blocks** 

The core of the MachXO4 device consists of PFU blocks, which can be programmed to perform logic, arithmetic, distributed RAM and distributed ROM functions. Each PFU block consists of four interconnected slices numbered 0 to 3 as shown in Figure 2.3. Each slice contains two LUTs and two registers. There are 53 inputs and 25 outputs associated with each PFU block. 

**==> picture [438 x 222] intentionally omitted <==**

**----- Start of picture text -----**<br>
From<br>Routing<br>sb<br>LUT4 & LUT4 & LUT4 & LUT4 & LUT4 & LUT4 & LUT4 & LUT4 &<br>FCIN CARRY CARRY CARRY CARRY CARRY CARRY CARRY CARRY FCO<br>Slice 0 Slice 1 Slice 2 Slice 3<br>D D D D D D D D<br>FF FF FF FF FF FF FF FF<br>To<br>Routing<br>==<br>**----- End of picture text -----**<br>


**Figure 2.3. PFU Block Diagram** 

© 2025 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02125-1.0 

14 

**MachXO4 Family Data Sheet** 

## **2.2.1. Slices** 

Slices 0-3 contain two LUT4s feeding two registers. Slices 0-2 can be configured as distributed memory. Table 2.1 shows the capability of the slices in PFU blocks along with the operation modes they enable. The control logic performs set/reset functions (programmable as synchronous/ asynchronous), clock select, chip select and wider RAM/ROM functions. 

|**Table 2.1. Resources and Modes Availableper Slice**|
|---|
|**Slice**<br>**PFU Block**<br>**Resources**<br>**Modes**<br>Slice 0<br>2 LUT4s and 2 Registers<br>Logic,Ripple,RAM,ROM<br>Slice 1<br>2 LUT4s and 2 Registers<br>Logic,Ripple,RAM,ROM<br>Slice 2<br>2 LUT4s and 2 Registers<br>Logic, Ripple, RAM, ROM<br>Slice 3<br>2 LUT4s and 2 Registers<br>Logic,Ripple,ROM<br>~~a~~|
|Figure 2.4shows an overview of the internal logic of the slice. The registers in the slice can be configured for positive/|
|negative and edge triggered or level sensitive clocks. All slices have 15 inputs from routing and one from the|
|carry-chain (from the adjacent slice or PFU). There are seven outputs: six for routing and one to carry-chain (to the|
|adjacent PFU).Table 2.2lists the signals associated with Slices 0-3.|



**==> picture [403 x 379] intentionally omitted <==**

**----- Start of picture text -----**<br>
FCO to Different Slice/PFU<br>Slice<br>FXB<br>OFX1<br>FXA<br>F1<br>A1 CO<br>F/SUM<br>B1<br>D1C1 LUT4 &  D Q1<br>Carry<br>Flip-flop<br>CI To<br>Routing<br>M1<br>M0 LUT5<br>Mux<br>From<br>Routing OFX0<br>A0 ave CO<br>B0<br>F0<br>C0<br>LUT4 &<br>D0<br>Carry<br>F/SUM D Q0<br>== CI Flip-flop<br>CE<br>CLK<br>LSR<br>Bian<br>Memory &  FCI from<br>Control Signals Different<br>E<br>Slice/PFU<br>For Slices 0 and 1, memory control signals are generated from Slice 2 as follows:<br>•  WCK is CLK<br>•  WRE is from LSR<br>•  DI [3:2] for Slice 1 and DI [1:0] for Slice 0 data from Slice 2<br>•  WAD [A:D] is a 4-bit address from slice 2 LUT input<br>**----- End of picture text -----**<br>


**Figure 2.4. Slice Diagram** 

© 2025 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02125-1.0 

15 

**MachXO4 Family Data Sheet** 

**Table 2.2. Slice Signal Descriptions** 

|**Function**<br>~~es~~|**Type **<br>~~QO~~|**Signal Names**<br>~~QO~~|**Description**<br>~~QO~~|
|---|---|---|---|
|Input<br>~~es~~<br>~~a~~<br>~~es~~|Data signal<br>~~QO~~<br>|A0, B0, C0, D0<br>~~QO~~<br>~~G~~<br>~~G~~|Inputs to LUT4<br>~~QO~~<br>~~G~~<br>~~G~~|
|Input<br>~~es~~<br>~~es~~|Data signal<br><br>|A1,B1,C1,D1<br>~~G~~<br>~~G~~|Inputs to LUT4<br>~~G~~<br>~~G~~|
|Input<br>~~es ~~<br>~~es~~<br>~~ee~~|Multi-purpose<br> <br>|M0/M1<br> ~~G~~<br>~~G~~|Multi-purpose input<br>~~G~~<br>~~G~~|
|Input<br>~~es ~~<br>~~ee~~<br>~~ne~~|Control signal<br> <br>~~OO~~|CE<br> ~~G~~<br>~~OO~~|Clock enable<br>~~G~~<br>~~OO~~|
|Input<br>~~ee~~<br>~~ne~~<br>~~ne~~|Control signal<br>~~OO~~<br>~~OO~~|LSR<br>~~OO~~<br>~~OO~~|Local set/reset<br>~~OO~~<br>~~OO~~|
|Input<br>~~ne~~<br>~~ne~~<br>~~ne~~|Control signal<br>~~OO~~<br>~~OO~~<br>~~OO~~|CLK<br>~~OO~~<br>~~OO~~<br>~~OO~~|System clock<br>~~OO~~<br>~~OO~~<br>~~OO~~|
|Input<br>~~ne~~<br>~~ne~~<br>~~es~~|Inter-PFU signal<br>~~OO~~<br>~~OO~~<br>~~Ge~~|FCIN<br>~~OO~~<br>~~OO~~<br>~~Ge~~|Fast carryin1<br>~~OO~~<br>~~OO~~<br>~~Ge~~|
|Output<br>~~ne~~<br>~~es~~<br>~~es~~|Data signals<br>~~OO~~<br>~~Ge~~<br>|F0,F1<br>~~OO~~<br>~~Ge~~<br>~~G~~|LUT4 output register bypass signals<br>~~OO~~<br>~~Ge~~<br>~~G~~|
|Output<br>~~es~~<br>~~es~~<br>~~es~~|Data signals<br>~~Ge~~<br><br>|Q0,Q1<br>~~Ge~~<br>~~G~~<br>~~G~~|Register outputs<br>~~Ge~~<br>~~G~~<br>~~G~~|
|Output<br>~~es ~~<br>~~es~~<br>~~ee~~|Data signals<br> <br>|OFX0<br> ~~G~~<br>~~G~~|Output of a LUT5 MUX<br>~~G~~<br>~~G~~|
|Output<br>~~es ~~<br>~~ee~~<br>~~Rn~~|Data signals<br> <br>~~FO~~|OFX1<br> ~~G~~<br>~~FO~~|Output of a LUT6, LUT7, LUT82MUX dependingon the slice<br>~~G~~<br>~~FO~~|
|Output<br>~~ee~~<br>~~Rn~~|Inter-PFU signal<br>~~FO~~|FCO<br>~~FO~~|Fast carryout1<br>~~FO~~|



1. See Figure 2.3 for connection details. 

2. Requires two PFUs. 

## **2.2.2. Modes of Operation** 

Each slice has up to four potential modes of operation: Logic, Ripple, RAM and ROM. 

## **2.2.2.1. Logic Mode** 

In this mode, the LUTs in each slice are configured as 4-input combinatorial lookup tables. A LUT4 can have 16 possible input combinations. Any four input logic functions can be generated by programming this lookup table. Since there are two LUT4s per slice, a LUT5 can be constructed within one slice. Larger look-up tables such as LUT6, LUT7 and LUT8 can be constructed by concatenating other slices. Note LUT8 requires more than four slices. 

## **2.2.2.2. Ripple Mode** 

Ripple mode supports the efficient implementation of small arithmetic functions. In Ripple mode, the following functions can be implemented by each slice: 

- Addition 2-bit 

- Subtraction 2-bit 

- Add/subtract 2-bit using dynamic control 

- Up counter 2-bit 

- Down counter 2-bit 

- Up/down counter with asynchronous clear 

- Up/down counter with preload (sync) 

- Ripple mode multiplier building block 

- Multiplier support 

- Comparator functions of A and B inputs 

- A greater-than-or-equal-to B 

- A not-equal-to B 

- A less-than-or-equal-to B 

Ripple mode includes an optional configuration that performs arithmetic using fast carry chain methods. In this configuration (also referred to as CCU2 mode) two additional signals, Carry Generate and Carry Propagate, are generated on a per-slice basis to allow fast arithmetic functions to be constructed by concatenating slices. 

## **2.2.3. RAM Mode** 

In this mode, a 16x4-bit distributed single port RAM (SPR) can be constructed by using each LUT block in Slice 0 and Slice 1 as a 16x1-bit memory. Slice 2 is used to provide memory address and control signals. 

MachXO4 devices support distributed memory initialization. 

© 2025 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02125-1.0 

16 

**MachXO4 Family Data Sheet** 

The Lattice design tools support the creation of a variety of different size memories. Where appropriate, the software constructs these using distributed memory primitives that represent the capabilities of the PFU. Table 2.3 shows the number of slices required to implement different distributed RAM primitives. For more information about using RAM in MachXO4 devices, see MachXO4 Memory User Guide (FPGA-TN-02402). 

**Table 2.3. Number of Slices Required For Implementing Distributed RAM** 

||**SPR 16 x 4**|**SPR 16 x 4**|**SPR 16 x 4**|**SPR 16 x 4**|**PDPR 16 x 4**|**PDPR 16 x 4**|**PDPR 16 x 4**|**PDPR 16 x 4**|
|---|---|---|---|---|---|---|---|---|
|Number of slices|3||||3||||



**Note** : SPR = Single Pot RAM, PDPR = Pseudo Dual Port RAM 

## **2.2.4. ROM Mode** 

ROM mode uses the LUT logic; hence, slices 0-3 can be used in ROM mode. Preloading is accomplished through the programming interface during PFU configuration. 

For more information on the RAM and ROM modes, refer to MachXO4 Memory User Guide (FPGA-TN-02402). 

## **2.3. Routing** 

There are many resources provided in the MachXO4 devices to route signals individually or as buses with related control signals. The routing resources consist of switching circuitry, buffers and metal interconnect (routing) segments. The inter-PFU connections are made with three different types of routing resources: x1 (spans two PFUs), x2 (spans three PFUs) and x6 (spans seven PFUs). The x1, x2, and x6 connections provide fast and efficient connections in the horizontal and vertical directions. 

The design tools take the output of the synthesis tool and places and routes the design. Generally, the place and route tool is completely automatic, although an interactive routing editor is available to optimize the design. 

## **2.4. Clock/Control Distribution Network** 

Each MachXO4 device has eight clock inputs (PCLK [T, C] [Banknum]_[2..0]) – three pins on the left side, two pins each on the bottom and top sides and one pin on the right side. These clock inputs drive the clock nets. These eight inputs can be differential or single-ended and may be used as general purpose I/O if they are not used to drive the clock nets. When using a single-ended clock input, only the PCLKT input can drive the clock tree directly. 

The MachXO4 architecture has three types of clocking resources: edge clocks, primary clocks and secondary high fanout nets. MachXO4 devices have two edge clocks each on the top and bottom edges. Edge clocks are used to clock I/O registers and have low injection time and skew. Edge clock inputs are from PLL outputs, primary clock pads, edge clock bridge outputs and CIB sources. 

The eight primary clock lines in the primary clock network drive throughout the entire device and can provide clocks for all resources within the device including PFUs, EBRs and PICs. In addition to the primary clock signals, MachXO4 devices also have eight secondary high fanout signals which can be used for global control signals, such as clock enables, synchronous or asynchronous clears, presets, output enables, etc. Internal logic can drive the global clock network for internally-generated global clocks and control signals. 

The maximum frequency for the primary clock network is shown in the MachXO4 External Switching Characteristics table. 

Primary clock signals for the LFMXO4-015 part and larger devices are generated from eight 27:1 muxes The available clock sources include eight I/O sources, 11 routing inputs, eight clock divider inputs and up to eight sysCLOCK PLL outputs. 

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**MachXO4 Family Data Sheet** 

**==> picture [341 x 463] intentionally omitted <==**

**----- Start of picture text -----**<br>
Up to 8 8 11 8<br>Dynamic<br>27:1 Clock Primary Clock 0<br>Enable<br>mi<br>Dynamic<br>27:1 Clock Primary Clock 1<br>Enable<br>renee<br>Dynamic<br>27:1 Clock Primary Clock 2<br>Enable<br>Cy RH<br>Dynamic<br>27:1 Clock Primary Clock 3<br>Enable<br>Cyfore<br>Dynamic<br>27:1 Clock Primary Clock 4<br>Enable<br>PP RH<br>Dynamic<br>27:1 Clock Primary Clock 5<br>Enable<br>ieee<br>27:1<br>Dynamic<br>Clock<br>Enable Primary Clock 6<br>Bima<br>27:1 Clock<br>Switch<br>mani<br>27:1<br>Dynamic<br>Clock<br>imi<br>Enable Primary Clock 7<br>27:1 Clock<br>Switch<br>PLL Outputs Clock Pads Routing Edge Clock Divider<br>**----- End of picture text -----**<br>


**Figure 2.5. Primary Clocks for MachXO4 Devices** 

Eight secondary high fanout nets are generated from eight 8:1 muxes as shown in Figure 2.6. One of the eight inputs to the secondary high fanout net input mux comes from dual function clock pins and the remaining seven come from internal routing. The maximum frequency for the secondary clock network is shown in MachXO4 External Switching Characteristics table. 

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**MachXO4 Family Data Sheet** 

**==> picture [245 x 398] intentionally omitted <==**

**----- Start of picture text -----**<br>
1 7<br>Secondary High<br>8:1<br>Fanout Net 0<br>Secondary High<br>8:1<br>Fanout Net 1<br>Secondary High<br>8:1<br>Fanout Net 2<br>Secondary High<br>8:1<br>Fanout Net 3<br>Secondary High<br>8:1<br>Fanout Net 4<br>Secondary High<br>8:1<br>Fanout Net 5<br>Secondary High<br>8:1<br>Fanout Net 6<br>8:1 Secondary High<br>Fanout Net 7<br>Clock Pads Routing<br>**----- End of picture text -----**<br>


**Figure 2.6. Secondary High Fanout Nets for MachXO4 Devices** 

## **2.4.1. sysCLOCK Phase Locked Loops (PLLs)** 

The sysCLOCK PLLs provide the ability to synthesize clock frequencies. All MachXO4 devices have one or more sysCLOCK PLL. CLKI is the reference frequency input to the PLL and its source can come from an external I/O pin or from internal routing. CLKFB is the feedback signal to the PLL which can come from internal routing or an external I/O pin. The feedback divider is used to multiply the reference frequency and thus synthesize a higher frequency clock output. 

The MachXO4 sysCLOCK PLLs support high resolution (16-bit) fractional-N synthesis. Fractional-N frequency synthesis allows the user to generate an output clock which is a non-integer multiple of the input frequency. For more information about using the PLL with Fractional-N synthesis, see MachXO4 sysCLOCK PLL Design User Guide (FPGA-TN-02391). 

Each output has its own output divider, thus allowing the PLL to generate different frequencies for each output. The output dividers can have a value from 1 to 128. The output dividers may also be cascaded together to generate low frequency clocks. The CLKOP, CLKOS, CLKOS2, and CLKOS3 outputs can all be used to drive the MachXO4 clock distribution network directly or general purpose routing resources can be used. 

The LOCK signal is asserted when the PLL determines it has achieved lock and de-asserted if a loss of lock is detected. A block diagram of the PLL is shown in Figure 2.7. 

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**MachXO4 Family Data Sheet** 

The setup and hold times of the device can be improved by programming a phase shift into the CLKOS, CLKOS2, and CLKOS3 output clocks which advance or delay the output clock with reference to the CLKOP output clock. 

This phase shift can be either programmed during configuration or can be adjusted dynamically. In dynamic mode, the PLL may lose lock after a phase adjustment on the output used as the feedback source and not relock until the tLOCK parameter has been satisfied. 

The MachXO4 also has a feature that allows the user to select between two different reference clock sources dynamically. This feature is implemented using the PLLREFCS primitive. The timing parameters for the PLL are shown in the sysCLOCK PLL Timing table. 

The MachXO4 PLL contains a WISHBONE port feature that allows the PLL settings, including divider values, to be dynamically changed from the user logic. When using this feature the EFB block must also be instantiated in the design to allow access to the WISHBONE ports. Similar to the dynamic phase adjustment, when PLL settings are updated through the WISHBONE port the PLL may lose lock and not relock until the tLOCK parameter has been satisfied. The timing parameters for the PLL are shown in the sysCLOCK PLL Timing table. 

For more details on the PLL and the WISHBONE interface, see MachXO4 sysCLOCK PLL Design User Guide (FPGA-TN-02391). 

**==> picture [429 x 282] intentionally omitted <==**

**----- Start of picture text -----**<br>
DPHSRC<br>PHASESEL[1:0]<br>PHASEDIR Dynamic<br>Phase<br>PHASESTEP Adjust<br>CLKOP  Phase  CLKOP<br>A2 ClkEn<br>STDBY A0 (1 - 128)Divider Edge TrimAdjust/  Mux Synch<br>REFCLK<br>CLKOS<br>CLKI REFCLK Divider Phase detector, B0 (1 - 128)CLKOS Divider Edge TrimAdjust/ Phase  MuxB2 SynchClkEn<br>M (1 - 40) VCO, and<br> loop filter.<br>CLKFB FBKSEL CLKOS2<br>CLKOS2<br>Phase  C2 ClkEn<br>FBKCLK  Fractional-N C0 Divider Adjust Mux Synch<br>Divider Synthesizer (1 - 128)<br>N (1 - 40)<br>CLKOS3<br>CLKOS3<br>D1 Phase  D2 ClkEn<br>D0 Divider<br>Mux Adjust Mux Synch<br>Internal Feedback (1 - 128)<br>CLKOP, CLKOS, CLKOS2, CLKOS3<br>LOCK<br>4 Lock<br>RST, RESETM, RESETC, RESETD Detect<br>ENCLKOP, ENCLKOS, ENCLKOS2, ENCLKOS3<br>PLLDATO[7:0] , PLLACK<br>PLLCLK, PLLRST, PLLSTB, PLLWE, PLLDATI[7:0], PLLADDR[4:0]<br>**----- End of picture text -----**<br>


**Figure 2.7. PLL Diagram** 

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**MachXO4 Family Data Sheet** 

Table 2.4 provides signal descriptions of the PLL block. 

**Table 2.4. PLL Signal Descriptions** 

|**Port Name**<br>~~a ~~|**I/O**<br> ~~G~~|**Description**<br>~~G~~|
|---|---|---|
|CLKI<br>~~a~~|I|Input clock to PLL|
|CLKFB<br>~~a~~|I|Feedback clock|
|PHASESEL[1:0]<br>~~a~~<br>~~ee~~|I|Select which output is affected byDynamic Phase adjustmentports|
|PHASEDIR<br>~~ee~~|I|Dynamic Phase adjustment direction|
|PHASESTEP<br>~~ee~~<br>~~a~~|I|Dynamic Phase step –toggle shifts VCOphase adjust byone step.|
|CLKOP<br>~~a~~<br>~~a~~|O|PrimaryPLL output clock(withphase shift adjustment)|
|CLKOS<br>~~a~~|O|SecondaryPLL output clock(withphase shift adjust)|
|CLKOS2<br>~~a~~<br>~~a~~|O|SecondaryPLL output clock2(withphase shift adjust)|
|CLKOS3|O|SecondaryPLL output clock3(withphrase shift adjust)|
|LOCK<br>~~a~~|O|PLL LOCK, asynchronous signal. Active high indicates PLL is locked to input and<br>feedback signals.|
|DPHSRC<br>~~a~~|O|Dynamic Phase source– ports or WISHBONE is active|
|STDBY<br>~~a~~|I|Stand-bysignal topower down the PLL|
|RST<br>~~Ge~~|I<br>~~Ge~~|PLL reset without resettingthe M-driver. Active high reset.<br>~~Ge~~|
|RESETM<br>~~Ge~~<br>~~ee~~|I<br>~~Ge~~<br>~~ee~~|PLL rest–includes resettingthe M-divider. Active high reset.<br>~~Ge~~<br>~~G~~|
|RESETC<br>~~ee~~<br>~~a~~|I<br>~~ee~~|Reset for CLKOS2 output divider only. Active high reset.<br>~~G~~|
|RESETD<br>~~a~~|I|Reset for CLKOS3 output divider only. Active high reset.|
|ENCLKOP<br>~~a~~|I<br>|Enable PLL output CLKOP<br>|
|ENCLKOS<br>~~Ge~~|I<br>~~Ge~~|Enable PLL output CLKOS whenport is active<br>~~Ge~~|
|ENCLKOS2<br>~~Ge~~<br>~~ee~~|I<br>~~Ge~~<br>~~ee~~|Enable PLL output CLKOS2 whenport is active<br>~~Ge~~<br>~~G~~|
|ENCLKOS3<br>~~ee~~<br>~~ee~~|I<br>~~ee~~<br>~~ee~~|Enable PLL output CLKOS3 whenport is active<br>~~G~~<br>~~G~~|
|PLLCLK<br>~~ee~~<br>~~a~~|I<br>~~ee~~|PLL data bus clock input signal<br>~~G~~|
|PLLRST<br>~~a~~|I<br>|PLL data bus reset. This resets onlythe data bus not anyregister values.<br>|
|PLLSTB<br>~~Ge~~|I<br>~~Ge~~|PLL data bus strobe signal<br>~~Ge~~|
|PLLWE<br>~~Ge~~<br>~~eG~~|I<br>~~Ge~~<br>~~eG~~|PLL data bus write enable signal<br>~~Ge~~<br>~~eG~~|
|PLLADDR[4:0]<br>~~eG~~<br>~~a~~<br>~~ee~~|I<br>~~eG~~|PLL data bus address<br>~~eG~~|
|PLLDATI[7:0]<br>~~a~~<br>~~ee~~|I|PLL data bus data input|
|PLLDATO[7:0]<br>~~ee~~<br>~~a~~<br>~~ee~~|O|PLL data bus data output|
|PLLACK<br>~~ee~~|O|PLL data bus acknowledge signal|



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FPGA-DS-02125-1.0 

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**MachXO4 Family Data Sheet** 

## **2.5. sysMEM Embedded Block RAM Memory** 

The MachXO4 devices contain sysMEM Embedded Block RAMs (EBRs). The EBR consists of a 9-Kbit RAM, with dedicated input and output registers. This memory can be used for a wide variety of purposes including data buffering, PROM for the soft processor and FIFO. 

## **2.5.1. sysMEM Memory Block** 

The sysMEM block can implement single port, dual port, pseudo dual port, or FIFO memories. Each block can be used in a variety of depths and widths as shown in Table 2.5. 

**Table 2.5. sysMEM Block Configurations** 

|**Memory Mode**|**Configurations**|
|---|---|
|Single Port|8,192 x 1<br>4,096 x 2<br>2,048 x 4<br>1,024 x 9|
|True Dual Port|8,192 x 1<br>4,096 x 2<br>2,048 x 4<br>1,024 x 9|
|Pseudo Dual Port|8,192 x 1<br>4,096 x 2<br>2,048 x 4<br>1,024 x 9<br>512 x 18|
|FIFO|8,192 x 1<br>4,096 x 2<br>2,048 x 4<br>1,024 x 9<br>512 x 18|



## **2.5.2. Bus Size Matching** 

All of the multi-port memory modes support different widths on each of the ports. The RAM bits are mapped LSB word 0 to MSB word 0, LSB word 1 to MSB word 1, and so on. Although the word size and number of words for each port varies, this mapping scheme applies to each port. 

## **2.5.3. RAM Initialization and ROM Operation** 

If desired, the contents of the RAM can be pre-loaded during device configuration. EBR initialization data can be loaded from the Configuration Flash. 

MachXO4 EBR initialization data can also be loaded from the UFM. To maximize the number of UFM bits, initialize the EBRs used in your design to an all-zero pattern. Initializing to an all-zero pattern does not use up UFM bits. MachXO4 devices have been designed such that multiple EBRs share the same initialization memory space if they are initialized to the same pattern. 

By preloading the RAM block during the chip configuration cycle and disabling the write controls, the sysMEM block can also be utilized as a ROM. 

## **2.5.4. Memory Cascading** 

Larger and deeper blocks of RAM can be created using EBR sysMEM Blocks. Typically, the Lattice design tools cascade memory transparently, based on specific design inputs. 

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**MachXO4 Family Data Sheet** 

## **2.5.5. Single, Dual, Pseudo-Dual Port and FIFO Modes** 

Figure 2.8 shows the five basic memory configurations and their input/output names. In all the sysMEM RAM modes, the input data and addresses for the ports are registered at the input of the memory array. The output data of the memory is optionally registered at the memory array output. 

**==> picture [461 x 297] intentionally omitted <==**

**----- Start of picture text -----**<br>
AD[12:0] DIA[8:0] DI[8:0]<br>DI[8:0] ADW[8:0]<br>ADA[12:0] ADB[12:0] DI[17:0] ADR[12:0]<br>CLK CLKA CLKB BE[1:0] CLKR<br>CE CEA CEB CLKW<br>OCE CER<br>EBR DO[8:0] RSTA EBR RSTB CEW EBR<br>RST WEA WEB RST DO[17:0]<br>WE CSA[2:0] CSB[2:0] OCER<br>CS[2:0] OCEA OCEB CSW[2:0] CSR[2:0]<br>DOA[8:0] DOB[8:0]<br>i<br>Single Port RAM True Dual Port RAM Pseudo Dual Port RAM<br>AFF AD[12:0]<br>DI[17:0] FF<br>AEF<br>CLKW EF CLK<br>WE DO[17:0] CE<br>RST EBR ORE OCE EBR DO[17:0]<br>CLKR<br>FULLI RE RST<br>CSW[1:0] EMPTYI<br>CSR[1:0] CS[2:0]<br>RPRST<br>T<br>FIFO RAM ROM<br>**----- End of picture text -----**<br>


**Figure 2.8. sysMEM Memory Primitives** 

**Table 2.6. EBR Signal Descriptions** 

|**Port Name**|**Description**|**Active State**|
|---|---|---|
|CLK|Clock|RisingClock Edge|
|CE|Clock Enable|Active High|
|OCE1|Output Clock Enable|Active High|
|RST|Reset|Active High|
|BE1|Byte Enable|Active High|
|WE|Write Enable|Active High|
|AD|Address Bus|—|
|DI|Data In|—|
|DO|Data Out|—|
|CS|ChipSelect|Active High|
|AFF|FIFO RAM Almost Full Flag|—|
|FF|FIFO RAM Full Flag|—|
|AEF|FIFO RAM Almost EmptyFlag|—|
|EF|FIFO RAM EmptyFlag|—|
|RPRST|FIFO RAM Read Pointer Reset|—|



**Notes:** 

1. Optional signals. 

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**MachXO4 Family Data Sheet** 

2. For dual port EBR primitives a trailing ‘A’ or ‘B’ in the signal name specifies the EBR port A or port B respectively. 

3. For FIFO RAM mode primitive, a trailing ‘R’ or ‘W’ in the signal name specifies the FIFO read port or write port respectively. 

4. For FIFO RAM mode primitive, FULLI has the same function as CSW(2) and EMPTYI has the same function as CSR(2). 

5. In FIFO mode, CLKW is the write port clock, CSW is the write port chip select, CLKR is the read port clock, CSR is the read port chip select, ORE is the output read enable. 

The EBR memory supports three forms of write behavior for single or dual port operation: 

- Normal – Data on the output appears only during the read cycle. During a write cycle, the data (at the current address) does not appear on the output. This mode is supported for all data widths. 

- Write Through – A copy of the input data appears at the output of the same port. This mode is supported for all data widths. 

- Read-Before-Write – When new data is being written, the old contents of the address appears at the output. 

## **2.5.6. FIFO Configuration** 

The FIFO has a write port with data-in, CEW, WE and CLKW signals. There is a separate read port with data-out, RCE, RE and CLKR signals. The FIFO internally generates Almost Full, Full, Almost Empty and Empty Flags. The Full and Almost Full flags are registered with CLKW. The Empty and Almost Empty flags are registered with CLKR. Table 2.7 shows the range of programming values for these flags. 

**Table 2.7. Programmable FIFO Flag Ranges** 

|**Flag Name**|**Programming Range **|
|---|---|
|Full(FF)|1 to max(upto 2N-1)|
|Almost Full(AF)|1 to Full-1|
|Almost Empty (AE)|1 to Full-1|
|Empty (EF)|0|



N = Address bit width. 

The FIFO state machine supports two types of reset signals: RST and RPRST. The RST signal is a global reset that clears the contents of the FIFO by resetting the read/write pointer and puts the FIFO flags in their initial reset state. The RPRST signal is used to reset the read pointer. The purpose of this reset is to retransmit the data that is in the FIFO. In these applications it is important to keep careful track of when a packet is written into or read from the FIFO. 

## **2.5.7. Memory Core Reset** 

The memory core contains data output latches for ports A and B. These are simple latches that can be reset synchronously or asynchronously. RSTA and RSTB are local signals, which reset the output latches associated with port A and port B respectively. The Global Reset (GSRN) signal resets both ports. The output data latches and associated resets for both ports are as shown in Figure 2.9. 

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FPGA-DS-02125-1.0 

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**MachXO4 Family Data Sheet** 

**==> picture [303 x 166] intentionally omitted <==**

**----- Start of picture text -----**<br>
Memory Core | Port A [18:0]<br>Output Data<br>Latches<br>| Port B [18:0]<br>RSTA = fe<br>RSTB<br>=> ><br>GSRN<br>**----- End of picture text -----**<br>


## **Figure 2.9. Memory Core Reset** 

For further information on the sysMEM EBR block, refer to MachXO4 Memory User Guide (FPGA-TN-02402) 

## **2.5.8. EBR Asynchronous Reset** 

EBR asynchronous reset or GSR (if used) can only be applied if all clock enables are low for a clock cycle before the reset is applied and released a clock cycle after the reset is released, as shown in Figure 2.10. The GSR input to the EBR is always asynchronous. 

**==> picture [26 x 150] intentionally omitted <==**

**----- Start of picture text -----**<br>
Reset<br>Clock<br>Clock<br>Enable<br>**----- End of picture text -----**<br>


**Figure 2.10. EBR Asynchronous Reset (Including GSR) Timing Diagram** 

If all clock enables remain enabled, the EBR asynchronous reset or GSR may only be applied and released after the EBR read and write clock inputs are in a steady state condition for a minimum of 1/fMAX (EBR clock). The reset release must adhere to the EBR synchronous reset setup time before the next active read or write clock edge. 

If an EBR is pre-loaded during configuration, the GSR input must be disabled or the release of the GSR during device wake up must occur before the release of the device I/O becoming active. 

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**MachXO4 Family Data Sheet** 

These instructions apply to all EBR RAM, ROM and FIFO implementations. For the EBR FIFO mode, the GSR signal is always enabled and the WE and RE signals act like the clock enable signals in Figure 2.10. The reset timing rules apply to the RPReset input versus the RE input and the RST input versus the WE and RE inputs. Both RST and RPReset are always asynchronous EBR inputs. For more details refer to MachXO4 Memory User Guide (FPGA-TN-02402). Note that there are no reset restrictions if the EBR synchronous reset is used and the EBR GSR input is disabled. 

## **2.6. Programmable I/O Cells (PIC)** 

The programmable logic associated with an I/O is called a PIO. The individual PIO are connected to their respective sysI/O buffers and pads. On the MachXO4 devices, the PIO cells are assembled into groups of four PIO cells called a Programmable I/O Cell or PIC. The PICs are placed on all four sides of the device. 

On all the MachXO4 devices, two adjacent PIOs can be combined to provide a complementary output driver pair. All PIO pairs can implement differential receivers. Half of the PIO pairs on the top edge of these devices can be configured as true LVDS transmit pairs. The PIO pairs on the bottom edge of these devices have on-chip differential termination. 

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**MachXO4 Family Data Sheet** 

**==> picture [365 x 538] intentionally omitted <==**

**----- Start of picture text -----**<br>
1 PIC<br>PIO A<br>Input Register<br>Block<br>- 4<br>Output Register<br>Block and  Pin<br>Tristate Register  A<br>Block<br>PIO B<br>He<br>Input Register<br>Block<br>Output Register<br>Block and  Pin<br>Tristate Register  B<br>1 Output  - Block  4<br>Core Logic/  Input  Gearbox<br>Routing Gearbox<br>PIO C<br>= |He<br>Input Register<br>Block<br>i | m Output Register  =<br>Block and  Pin<br>Tristate Register  C<br>Block<br>[He<br>PIO D<br>Tf <a e<br>Input Register<br>Block<br>Output Register<br>Block and  Pin<br>Tristate Register  D<br>Block<br>T | Hea<br>Let<br>**----- End of picture text -----**<br>


## **Figure 2.11. Group of Four Programmable I/O Cells** 

## **2.7. PIO** 

The PIO contains three blocks: an input register block, output register block and tri-state register block. These blocks contain registers for operating in a variety of modes along with the necessary clock and selection logic. 

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27 

**MachXO4 Family Data Sheet** 

**Table 2.8. PIO Signal List** 

|**Pin Name**|**I/O Type **|**Description**|
|---|---|---|
|CE|Input|Clock Enable|
|D|Input|Pin input from sysI/O buffer|
|INDD|Output|Register bypassed input|
|INCK|Output|Clock input|
|Q0|Output|DDRpositive edge input|
|Q1|Output|Registered input/DDR negative edge input|
|D0|Input|Output signal from the core(SDR and DDR)|
|D1|Input|Output signal from the core(DDR)|
|TD|Input|Tri-state signal from the core|
|Q|Output|Data output signals to sysI/O Buffer|
|TQ|Output|Tri-state output signals to sysI/O Buffer|
|SCLK|Input|System clock for input and output/tri-state blocks|
|RST|Input|Local set reset signal|



## **2.7.1. Input Register Block** 

The input register blocks for the PIOs on all edges contain delay elements and registers that can be used to condition high-speed interface signals before they are passed to the device core. 

## **2.7.1.1. Left, Top, Bottom Edges** 

Input signals are fed from the sysI/O buffer to the input register block (as signal D). If desired, the input signal can bypass the register and delay elements and be used directly as a combinatorial signal (INDD), and a clock (INCK). If an input delay is desired, users can select a fixed delay. I/O on the bottom edge also have a dynamic delay, DEL[4:0]. The delay, if selected, reduces input register hold time requirements when using a global clock. The input block allows two modes of operation. In single data rate (SDR) the data is registered with the system clock (SCLK) by one of the registers in the single data rate sync register block. In Generic DDR mode, two registers are used to sample the data on the positive and negative edges of the system clock (SCLK) signal, creating two data streams. 

## **2.7.2. Output Register Block** 

The output register block registers signals from the core of the device before they are passed to the sysI/O buffers. 

## **2.7.2.1. Left, Top, Bottom Edges** 

In SDR mode, D0 feeds one of the flip-flops that then feeds the output. 

In DDR generic mode, D0 and D1 inputs are fed into registers on the positive edge of the clock. At the next falling edge the registered D1 input is registered into the register Q1. A multiplexer running off the same clock is used to switch the mux between the outputs of registers Q0 and Q1 that then feed the output. 

Figure 2.12 shows the output register block on the left, top and bottom edges. 

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FPGA-DS-02125-1.0 

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**==> picture [461 x 298] intentionally omitted <==**

**----- Start of picture text -----**<br>
MachXO4 Family<br>Data Sheet<br>|<br>| |<br>| Q0  Q<br>| D0 D/L  Q |<br>|<br>| |<br>|<br>| |<br>|<br>Q1<br>| D1 D Q  D Q  |<br>|<br>| |<br>|<br>| |<br>| SCLK<br>| Output path  |<br>|<br>] TD  |<br>] D/L Q  TQ<br>| |<br>|<br>| |<br>| Tri-state path<br>**----- End of picture text -----**<br>


**Figure 2.12. Output Register Block Diagram (PIO on the Left, Top and Bottom Edges)** 

## **2.7.3. Tri-state Register Block** 

The tri-state register block registers tri-state control signals from the core of the device before they are passed to the sysI/O buffers. The block contains a register for SDR operation. In SDR, TD input feeds one of the flip-flops that then feeds the output. 

## **2.8. Input Gearbox** 

Each PIC on the bottom edge has a built-in 1:8 input gearbox. Each of these input gearboxes may be programmed as a 1:7 de-serializer or as one IDDRX4 (1:8) gearbox or as two IDDRX2 (1:4) gearboxes. Table 2.9 shows the gearbox signals. 

**Table 2.9. Input Gearbox Signal List** 

|**Name**|**I/O Type **|**Description**|
|---|---|---|
|D|Input|High-speed data input afterprogrammable delayin PIO A input register block|
|ALIGNWD|Input|Data alignment signal from device core|
|SCLK|Input|Slow-speed system clock|
|ECLK[1:0]|Input|High-speed edge clock|
|RST|Input|Reset|
|Q[7:0]|Output|Low-speed data to device core:<br>Video RX(1:7): Q[6:0]<br>GDDRX4(1:8): Q[7:0]<br>GDDRX2(1:4)(IOL-A): Q4, Q5, Q6, Q7<br>GDDRX2(1:4)(IOL-C): Q0, Q1, Q2, Q3|



## **Note:** 

These gearboxes have three stage pipeline registers. The first stage registers sample the high-speed input data by the high-speed edge clock on its rising and falling edges. The second stage registers perform data alignment based on the control signals UPDATE and SEL0 from the control block. The third stage pipeline registers pass the data to the device core synchronized to the low-speed system clock. Figure 2.13 shows a block diagram of the input gearbox. 

© 2025 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02125-1.0 

29 

**MachXO4 Family Data Sheet** 

**==> picture [405 x 552] intentionally omitted <==**

**----- Start of picture text -----**<br>
Q0<br>Q21  D   Q Q0_ D   Q S0  D   Q T0<br>Q10  CE<br>Q43  LP D   Q Q21  PS D   Q S2  a D   Q T T2  Q2<br>Q32  CE<br>Q65  Q43  S4  T4  Q4<br>D   Q D   Q D   Q<br>Q54  CE<br>cdn cdn<br>Q65  S6  T6 Q6<br>D   Q D   Q D   Q<br>Q_6  CE<br>D<br>Q_6  S7  T7  Q7<br>D   Q D   Q D   Q<br>Q0_(x4)<br>CE<br>Q43_(x2)<br>Q_6  Q54<br>S5  T5  Q5<br>D   Q D   Q D<br>Q65  CE<br>Q54<br>Q32  S3  T3  Q3<br>D   Q D   Q D<br>Q43  CE<br>Q32  Q10  S1  T1  Q1<br>D   Q D   Q D<br>Q21  CE<br>ECLK0/1  SCLK<br>SEL0<br>UPDATE<br>**----- End of picture text -----**<br>


**Figure 2.13. Input Gearbox** 

More information on the input gearbox is available in Implementing High-Speed Interfaces with MachXO4 Devices (FPGA-TN-02410). 

© 2025 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02125-1.0 

30 

**MachXO4 Family Data Sheet** 

## **2.9. Output Gearbox** 

Each PIC on the top edge has a built-in 8:1 output gearbox. Each of these output gearboxes may be programmed as a 7:1 serializer or as one ODDRX4 (8:1) gearbox or as two ODDRX2 (4:1) gearboxes. Table 2.10 shows the gearbox signals. 

**Table 2.10. Output Gearbox Signal List** 

|**Name**|**I/O Type **|**Description**|
|---|---|---|
|Q|Output|High-speed data output|
|D[7:0]|Input|Low-speed data from device core|
|Video TX(7:1): D[6:0]|—|—|
|GDDRX4(8:1): D[7:0]|—|—|
|GDDRX2(4:1)(IOL-A): D[3:0]|—|—|
|GDDRX2(4:1)(IOL-C): D[7:4]|—|—|
|SCLK|Input|Slow-speed system clock|
|ECLK[1:0]|Input|High-speed edge clock|
|RST|Input|Reset|



The gearboxes have three stage pipeline registers. The first stage registers sample the low-speed input data on the low-speed system clock. The second stage registers transfer data from the low-speed clock registers to the high-speed clock registers. The third stage pipeline registers controlled by high-speed edge clock shift and mux the high-speed data out to the sysI/O buffer. Figure 2.14 shows the output gearbox block diagram. 

© 2025 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02125-1.0 

31 

**MachXO4 Family Data Sheet** 

**==> picture [19 x 6] intentionally omitted <==**

**----- Start of picture text -----**<br>
G ND<br>**----- End of picture text -----**<br>


**Figure 2.14. Output Gearbox** 

More information on the output gearbox is available in Implementing High-Speed Interfaces with MachXO4 Devices (FPGA-TN-02410). 

© 2025 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02125-1.0 

32 

**MachXO4 Family Data Sheet** 

## **2.10. sysI/O Buffer** 

Each I/O is associated with a flexible buffer referred to as a sysI/O buffer. These buffers are arranged around the periphery of the device in groups referred to as banks. The sysI/O buffers allow you to implement a wide variety of standards that are found in today’s systems including LVCMOS, TTL, LVDS, BLVDS, MLVDS, and LVPECL. 

Each bank is capable of supporting multiple I/O standards. In the MachXO4 devices, single-ended output buffers, ratioed input buffers (LVTTL and LVCMOS), and differential (LVDS) input buffers are powered using I/O supply voltage (VCCIO). Each sysI/O bank has its own VCCIO. 

MachXO4 devices contain three types of sysI/O buffer pairs. 

- Left and Right sysI/O Buffer Pairs 

   - The sysI/O buffer pairs in the left and right banks of the device consist of two single-ended output drivers and two single-ended input buffers (for ratioed inputs such as LVCMOS and LVTTL). The I/O pairs on the left and right of the devices also have differential input buffers. 

- Bottom sysI/O Buffer Pairs 

The sysI/O buffer pairs in the bottom bank of the device consist of two single-ended output drivers and two single-ended input buffers (for ratioed inputs such as LVCMOS and LVTTL). The I/O pairs on the bottom also have differential input buffers. 

- Top sysI/O Buffer Pairs 

The sysI/O buffer pairs in the top bank of the device consist of two single-ended output drivers and two single-ended input buffers (for ratioed inputs such as LVCMOS and LVTTL). The I/O pairs on the top also have differential I/O buffers. Half of the sysI/O buffer pairs on the top edge have true differential outputs. The sysI/O buffer pair comprising of the A and B PIOs in every PIC on the top edge have a differential output driver. 

## **2.10.1. Typical I/O Behavior during Power-up** 

The internal power-on-reset (POR) signal is deactivated when VCC and VCCIO0 have reached VPORUP level defined in the Power-On-Reset Voltage table in the DC and Switching Characteristics section of this data sheet. After the POR signal is deactivated, the FPGA core logic becomes active. It is the user’s responsibility to ensure that all VCCIO banks are active with valid input logic levels to properly control the output logic states of all the I/O banks that are critical to the application. The default configuration of the I/O pins in a blank device is tri-state with a weak pull-down to GND (some pins such as PROGRAMN and the JTAG pins have weak pull-up to VCCIO as the default functionality). The I/O pins maintain the blank configuration until VCC and VCCIO (for I/O banks containing configuration I/O) have reached VPORUP levels at which time the I/O takes on the user-configured settings only after a proper download/configuration. 

## **2.10.2. Supported Standards** 

The MachXO4 sysI/O buffer supports both single-ended and differential standards. Single-ended standards can be further subdivided into LVCMOS and LVTTL. The buffer supports the LVTTL, LVCMOS 1.2 V, 1.5 V, 1.8 V, 2.5 V, and 3.3 V standards. In the LVCMOS and LVTTL modes, the buffer has individually configurable options for drive strength, bus maintenance (weak pull-up, weak pull-down, bus-keeper latch or none) and open drain. BLVDS, MLVDS and LVPECL output emulation is supported on all devices. The MachXO4 devices support on-chip LVDS output buffers on approximately 50% of the I/O on the top bank. Differential receivers for LVDS, BLVDS, MLVDS and LVPECL are supported on all banks of MachXO4 devices. PCI compatibility is supported in the bottom bank of the MachXO4 devices. PCI compatibility is provided by: 

- Selecting the LVTTL33 buffer standard 

- Enabling the clamp feature 

- Setting 16 mA drive strength (PCI output only). 

Table 2.11 shows the I/O standards (together with their supply and reference voltages) supported by the MachXO4 devices. For further information on utilizing the sysI/O buffer to support a variety of standards, see MachXO4 sysI/O User Guide (FPGA-TN-02398). 

© 2025 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02125-1.0 

33 

**MachXO4 Family Data Sheet** 

## **Table 2.11. Supported Input Standards** 

|**Table 2.11. Supported Input Standards**||||||
|---|---|---|---|---|---|
||**VCCIO (Typ.)**<br>~~pT~~|||||
|**Input Standard**<br>~~De~~|**3.3 V**<br>~~pT~~<br>~~De~~|**2.5 V**<br>~~pT~~<br>~~De~~|**1.8 V**<br>~~pT~~<br>~~De~~|**1.5 V**<br>~~pT~~<br>~~De~~|**1.2 V**<br>~~pT~~<br>~~De~~|
|**Single-Ended Interfaces**<br>~~|~~||||||
|LVTTL<br>~~Ge~~|Yes<br>~~Ge~~|Yes2<br>~~Ge~~|Yes2<br>~~Ge~~|Yes2<br>~~Ge~~|—<br>~~Ge~~|
|LVCMOS33<br>~~Qs~~|Yes<br>~~Qs~~|Yes2<br>~~Qs~~|Yes2<br>~~Qs~~|Yes2<br>~~Qs~~|—<br>~~Qs~~|
|LVCMOS25<br>~~Qs~~<br>~~Gs~~|Yes2<br>~~Qs~~<br>~~Gs~~|Yes<br>~~Qs~~<br>~~Gs~~|Yes2<br>~~Qs~~<br>~~Gs~~|Yes2<br>~~Qs~~<br>~~Gs~~|—<br>~~Qs~~<br>~~Gs~~|
|LVCMOS18<br>~~Gs~~<br>~~Gs~~|Yes2<br>~~Gs~~<br>~~Gs~~|Yes2<br>~~Gs~~<br>~~Gs~~|Yes<br>~~Gs~~<br>~~Gs~~|Yes2<br>~~Gs~~<br>~~Gs~~|—<br>~~Gs~~<br>~~Gs~~|
|LVCMOS15<br>~~Gs~~<br>~~Gs~~|Yes2<br>~~Gs~~<br>~~Gs~~|Yes2<br>~~Gs~~<br>~~Gs~~|Yes2<br>~~Gs~~<br>~~Gs~~|Yes<br>~~Gs~~<br>~~Gs~~|Yes2<br>~~Gs~~<br>~~Gs~~|
|LVCMOS12<br>~~Gs~~<br>~~Ge~~|Yes2<br>~~Gs~~<br>~~Ge~~|Yes2<br>~~Gs~~<br>~~Ge~~|Yes2<br>~~Gs~~<br>~~Ge~~|Yes2<br>~~Gs~~<br>~~Ge~~|Yes<br>~~Gs~~<br>~~Ge~~|
|**Differential Interfaces**<br>~~|~~||||||
|LVDS<br>~~Ge~~|Yes<br>~~Ge~~|Yes<br>~~Ge~~|—<br>~~Ge~~|—<br>~~Ge~~|—<br>~~Ge~~|
|BLVDS, MLVDS, LVPECL<br>~~Qs~~|Yes<br>~~Qs~~|Yes<br>~~Qs~~|—<br>~~Qs~~|—<br>~~Qs~~|—<br>~~Qs~~|
|MIPI1<br>~~Qs~~<br>~~Ge~~|Yes<br>~~Qs~~<br>~~Ge~~|Yes<br>~~Qs~~<br>~~Ge~~|—<br>~~Qs~~<br>~~Ge~~|—<br>~~Qs~~<br>~~Ge~~|—<br>~~Qs~~<br>~~Ge~~|
|LVTTLD<br>~~Ge~~|Yes<br>~~Ge~~|—<br>~~Ge~~|—<br>~~Ge~~|—<br>~~Ge~~|—<br>~~Ge~~|
|LVCMOS33D<br>~~Ge~~<br>~~De~~|Yes<br>~~Ge~~<br>~~De~~|—<br>~~Ge~~<br>~~De~~|—<br>~~Ge~~<br>~~De~~|—<br>~~Ge~~<br>~~De~~|—<br>~~Ge~~<br>~~De~~|
|LVCMOS25D<br>~~De~~<br>~~De~~|—<br>~~De~~<br>~~De~~|Yes<br>~~De~~<br>~~De~~|—<br>~~De~~<br>~~De~~|—<br>~~De~~<br>~~De~~|—<br>~~De~~<br>~~De~~|
|LVCMOS18D<br>~~De~~<br>~~nd~~|—<br>~~De~~<br>~~nd~~|—<br>~~De~~<br>~~nd~~|Yes<br>~~De~~<br>~~nd~~|—<br>~~De~~<br>~~nd~~|—<br>~~De~~<br>~~nd~~|



## **Notes:** 

1. These interfaces can be emulated with external resistors in all devices. 

2. Reduced functionality. Refer to MachXO4 sysI/O User Guide (FPGA-TN-02398) for more details. 

## **Table 2.12. Supported Output Standards** 

|**Output Standard**|**VCCIO(Typ.)**|
|---|---|
|**Single-Ended Interfaces**||
|LVTTL|3.3|
|LVCMOS33|3.3|
|LVCMOS25|2.5|
|LVCMOS18|1.8|
|LVCMOS15|1.5|
|LVCMOS12|1.2|
|LVCMOS33,Open Drain|—|
|LVCMOS25, Open Drain|—|
|LVCMOS18,Open Drain|—|
|LVCMOS15,Open Drain|—|
|LVCMOS12, Open Drain|—|
|**Differential Interfaces**||
|LVDS1|2.5,3.3|
|BLVDS,MLVDS|2.5|
|LVPECL1|3.3|
|MIPI1|2.5|
|LVTTLD|3.3|
|LVCMOS33D|3.3|
|LVCMOS25D|2.5|
|LVCMOS18D|1.8|



## **Note:** 

1. These interfaces can be emulated with external resistors in all devices. 

© 2025 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02125-1.0 

34 

**MachXO4 Family Data Sheet** 

## **2.10.3. sysI/O Buffer Banks** 

The numbers of banks vary between the devices of this family. LFMXO4-015 in the 256 Ball packages and the LFMXO4-025 and higher density devices have six I/O banks (one bank on the top, right and bottom side and three banks on the left side). The LFMXO4-015 and lower density devices have four banks (one bank per side). Figure 2.15 and Figure 2.16 show the sysI/O banks and their associated supplies for all devices. 

**==> picture [284 x 249] intentionally omitted <==**

**----- Start of picture text -----**<br>
GND VCCIO0<br>Bank 0<br>VCCIO5<br>GND<br>VCCIO1<br>VCCIO4<br>GND<br>GND<br>VCCIO3<br>GND<br>Bank 2<br>GND VCCIO2<br>Bank 1<br>Bank 5<br>Bank 4<br>Bank 3<br>**----- End of picture text -----**<br>


**Figure 2.15. LFMXO4-015 in 256 Ball Packages, LFMXO4-025, LFMXO4-050, LFMXO4-080, and LFMXO4-110 I/O Banks** 

**==> picture [264 x 232] intentionally omitted <==**

**----- Start of picture text -----**<br>
GND VCCIO0<br>Bank 0<br>VCCIO3 VCCIO1<br>GND GND<br>Bank 2<br>GND VCCIO2<br>Bank 3 Bank 1<br>**----- End of picture text -----**<br>


**Figure 2.16.LFMXO4-010 and LFMXO4-015 in Non-256 Ball Packages I/O Banks** 

© 2025 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02125-1.0 

35 

**MachXO4 Family Data Sheet** 

## **2.11. Hot Socketing** 

The MachXO4 devices have been carefully designed to ensure predictable behavior during power-up and power-down. Leakage into I/O pins is controlled to within specified limits. This allows for easy integration with the rest of the system. These capabilities make the MachXO4 ideal for many multiple power supply and hot-swap applications. 

## **2.12. On-chip Oscillator** 

Every MachXO4 device has an internal CMOS oscillator. The oscillator output can be routed as a clock to the clock tree or as a reference clock to the sysCLOCK PLL using general routing resources. The oscillator frequency can be divided by internal logic. There is a dedicated programming bit and a user input to enable/disable the oscillator. The oscillator frequency ranges from 2.08 MHz to 133 MHz. The software default value of the Master Clock (MCLK) is nominally 2.08 MHz. When a different MCLK is selected during the design process, the following sequence takes place: 

Device powers up with a nominal MCLK frequency of 2.08 MHz. 

During configuration, users select a different master clock frequency. 

The MCLK frequency changes to the selected frequency once the clock configuration bits are received. If the user does not select a master clock frequency, then the configuration bitstream defaults to the MCLK frequency of 2.08 MHz. 

Table 2.13 lists all the available MCLK frequencies. 

**Table 2.13. Available MCLK Frequencies** 

|**MCLK(MHz, Nominal)**|**MCLK(MHz, Nominal)**|**MCLK(MHz, Nominal)**|
|---|---|---|
|2.08(default)|9.17|33.25|
|2.46|10.23|38|
|3.17|13.3|44.33|
|4.29|14.78|53.2|
|5.54|20.46|66.5|
|7|26.6|88.67|
|8.31|29.56|133|



## **2.13. Embedded Hardened IP Functions** 

All MachXO4 devices provide embedded hardened functions such as SPI, I[2] C and Timer/Counter. MachXO4 devices also provide User Flash Memory (UFM). These embedded blocks interface through the WISHBONE interface with routing as shown in Figure 2.17. 

© 2025 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02125-1.0 

36 

**MachXO4 Family Data Sheet** 

**==> picture [369 x 216] intentionally omitted <==**

**----- Start of picture text -----**<br>
Configuration  Power<br>Logic Control<br>ae<br>Embedded Function Block (EFB)<br>I2C (Primary) I/Os for I2C<br>(Primary)<br>EFB  fd 2 I/Os for I2C<br>Core Logic/ WISHBONE  I C (Secondary) (Secondary)<br>Routing Interface<br>SPI I/Os for SPI<br>a<br>= Timer/Counter<br>Indicates connection<br>PLL0 PLL1 UFM through core logic/routing.<br>**----- End of picture text -----**<br>


**Figure 2.17. Embedded Function Block Interface** 

## **2.13.1. Hardened I2C IP Core** 

Every MachXO4 device contains two I2C IP cores. These are the primary and secondary I2C IP cores. Either of the two cores can be configured either as an I2C master or as an I2C slave. The only difference between the two IP cores is that the primary core has pre-assigned I/O pins whereas users can assign I/O pins for the secondary core. 

When the IP core is configured as a master it is able to control other devices on the I2C bus through the interface. When the core is configured as the slave, the device is able to provide I/O expansion to an I2C Master. The I2C cores support the following functionality: 

- Master and Slave operation 

- 7-bit and 10-bit addressing 

- Multi-master arbitration support 

- Up to 400 kHz data transfer speed 

- General call support 

- Interface to custom logic through 8-bit WISHBONE interface 

**Figure 2.18. I2C Core Block Diagram** 

Table 2.14 describes the signals interfacing with the I2C cores. 

© 2025 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02125-1.0 

37 

**MachXO4 Family Data Sheet** 

**Table 2.14. I2C Core Signal Description** 

|**Signal Name**|**I/O**|**Description**|
|---|---|---|
|i2c_scl|Bi-directional|Bi-directional clock line of the I2C core. The signal is an output if the I2C core is in master<br>mode. The signal is an input if the I2C core is in slave mode. MUST be routed directly to the<br>pre-assigned I/O of the chip. Refer to the Pinout Information section of this document for<br>detailedpad andpin locations of I2Cports in each MachXO4 device.|
|i2c_sda|Bi-directional|Bi-directional data line of the I2C core. The signal is an output when data is transmitted from<br>the I2C core. The signal is an input when data is received into the I2C core. MUST be routed<br>directly to the pre-assigned I/O of the chip. Refer to the Pinout Information section of this<br>document for detailedpad andpin locations of I2Cports in each MachXO4 device.|
|i2c_irqo|Output|Interrupt request output signal of the I2C core. The intended usage of this signal is for it to be<br>connected to the WISHBONE master controller (for example, a microcontroller or state<br>machine) and request an interrupt when a specific condition is met. These conditions are<br>described with the I2C register definitions.|
|cfg_wake|Output|Wake-up signal – To be connected only to the power module of the MachXO4 device. The<br>signal is enabled only if the “Wakeup Enable” feature has been set within the EFB GUI, I2C<br>Tab.|
|cfg_stdby|Output|Stand-by signal – To be connected only to the power module of the MachXO4 device. The<br>signal is enabled only if the “Wakeup Enable” feature has been set within the EFB GUI, I2C<br>Tab.|



## **2.13.2. Hardened SPI IP Core** 

Every MachXO4 device has a hard SPI IP core that can be configured as a SPI master or slave. When the IP core is configured as a master it is able to control other SPI enabled chips connected to the SPI bus. When the core is configured as the slave, the device is able to interface to an external SPI master. The SPI IP core on MachXO4 devices supports the following functions: 

- Configurable Master and Slave modes 

- Full-Duplex data transfer 

- Mode fault error flag with CPU interrupt capability 

- Double-buffered data register 

- Serial clock with programmable polarity and phase 

- LSB First or MSB First Data Transfer 

- Interface to custom logic through 8-bit WISHBONE interface 

© 2025 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02125-1.0 

38 

**MachXO4 Family Data Sheet** 

There are some limitations on the use of the hardened user SPI. These are defined in the following technical notes: 

- Minimizing System Interruption During Configuration Using TransFR Technology (FPGA-TN-02198) (Appendix B) 

- MachXO4 Hardened Control Functions User Guide (FPGA-TN-02403) 

**==> picture [467 x 522] intentionally omitted <==**

**----- Start of picture text -----**<br>
|||||
|---|---|---|---|
|Configuration|
|Logic|
|EFB|
|SPI Function|
|MISO|
|Core|
|Logic/|MOSI|
|Routing|
|EFB|
|WISHBONE|SPI|Control|SCK|
|Interface|Registers|Logic|
|MCSN|
|SCSN|
|Figure 2.19. SPI Core Block Diagram|
|Table 2.15 describes the signals interfacing with the SPI cores.  describes the signals interfacing with the SPI cores.|
|Table 2.15. SPI Core Signal Description gnal Description nal Description ption tion|
|Signal Name|I/O|Master/Slave|Description|
|spi_csn[0]|O|Master|SPI master chip-select output|
|spi_csn[1..7]|O|Master|Additional SPI chip-select outputs (total up to eight slaves)|
|spi_scsn|I|Slave|SPI slave chip-select input|
|spi_irq|O|Master/Slave|Interrupt request|
|spi_clk|I/O|Master/Slave|SPI clock. Output in master mode. Input in slave mode.|
|spi_miso|I/O|Master/Slave|SPI data. Input in master mode. Output in slave mode.|
|spi_mosi|I/O|Master/Slave|SPI data. Output in master mode. Input in slave mode.|
|Configuration Slave Chip Select (active low), dedicated for selecting the|
|sn|I|Slave|
|Configuration Logic.|
|–|
|Stand-by signal|To be connected only to the power module of the MachXO4|
|cfg_stdby|O|Master/Slave|device. The signal is enabled only if the “Wakeup Enable” feature has been set|
|within the EFB GUI, SPI Tab.|
|–|
|Wake-up signal|To be connected only to the power module of the MachXO4|
|cfg_wake|O|Master/Slave|device. The signal is enabled only if the “Wakeup Enable” feature has been set|
|within the EFB GUI, SPI Tab.|

**----- End of picture text -----**<br>


Table 2.15 describes the signals interfacing with the SPI cores.  describes the signals interfacing with the SPI cores. 

**Table 2.15. SPI Core Signal Description gnal Description nal Description ption tion** 

© 2025 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02125-1.0 

39 

**MachXO4 Family Data Sheet** 

## **2.13.3. Hardened Timer/Counter** 

MachXO4 devices provide a hard Timer/Counter IP core. This Timer/Counter is a general purpose, bidirectional, 16-bit timer/counter module with independent output compare units and PWM support. The Timer/Counter supports the following functions: 

- Supports the following modes of operation: 

- Watchdog timer 

- Clear timer on compare match 

- Fast PWM 

- Phase and Frequency Correct PWM 

- Programmable clock input source 

- Programmable input clock prescaler 

- One static interrupt output to routing 

- One wake-up interrupt to on-chip stand-by mode controller 

- Three independent interrupt sources: overflow, output compare match, and input capture 

- Auto reload 

- Time-stamping support on the input capture unit 

- Waveform generation on the output 

- Glitch-free PWM waveform generation with variable PWM period 

- Internal WISHBONE bus access to the control and status registers 

- Stand-alone mode with preloaded control registers and direct reset input 

**==> picture [366 x 105] intentionally omitted <==**

**----- Start of picture text -----**<br>
EFB Timer/Counter<br>Core  EFB  Timer/<br>| ' Control<br>Logic  WISHBONE  Counter  PWM<br>Logic<br>Routing Interface Registers<br>**----- End of picture text -----**<br>


**Figure 2.20. Timer/Counter Block Diagram** 

**Table 2.16. Timer/Counter Signal Description** 

|**Port**|**I/O **|**Description**|
|---|---|---|
|tc_clki|I|Timer/Counter input clock signal|
|tc_rstn|I|Register tc_rstn_ena ispreloaded byconfiguration to always keepthispin enabled.|
|tc_ic|I|Input capture trigger event, applicable for non-pwm modes with WISHBONE interface. If enabled,<br>a rising edge of this signal is detected and synchronized to capture tc_cnt value into tc_icr for<br>time-stamping.|
|tc_int|O|Without WISHBONE–Can be used as overflow flag With WISHBONE–Controlled by three IRQ<br>registers.|
|tc_oc|O|Timer counter output signal|



For more details on these embedded functions, refer to MachXO4 Hardened Control Functions User Guide (FPGA-TN-02403). 

© 2025 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02125-1.0 

40 

**MachXO4 Family Data Sheet** 

## **2.14. User Flash Memory (UFM)** 

MachXO4 devices provide a User Flash Memory block, which can be used for a variety of applications including storing a portion of the configuration image, initializing EBRs, to store PROM data or, as a general purpose user Flash memory. The UFM block connects to the device core through the embedded function block WISHBONE interface. Users can also access the UFM block through the JTAG, I2C and SPI interfaces of the device. The UFM block offers the following features: 

- Non-volatile storage up to 448 kbits 

- 100,000 write/erase cycles for commercial/industrial devices and 10,000 for automotive devices 

- Write access is performed page-wise; each page has 128 bits (16 bytes) 

- Auto-increment addressing 

- WISHBONE interface 

For more information on the UFM, refer to MachXO4 Hardened Control Functions User Guide (FPGA-TN-02403). 

## **2.15. Stand-by Mode and Power Saving Options** 

MachXO4 devices are available in two options for maximum flexibility: HC and HE devices. The HC devices have a built-in voltage regulator to allow for 2.5 V VCC and 3.3 V VCC while the HE devices operate at 1.2 V VCC. 

MachXO4 devices have been designed with features that allow users to meet the static and dynamic power requirements of their applications by controlling various device subsystems such as the bandgap, power-on-reset circuitry, I/O bank controllers, power guard, on-chip oscillator, PLLs, etc. In order to maximize power savings, MachXO4 devices support a low power stand-by mode. 

In the stand-by mode, the MachXO4 devices are powered on and configured. Internal logic, I/O and memories are switched on and remain operational, as the user logic waits for an external input. The device enters this mode when the stand-by input of the stand-by controller is toggled or when an appropriate I2C or JTAG instruction is issued by an external master. Various subsystems in the device such as the band gap, power-on-reset circuitry can be configured such that they are automatically turned “off” or go into a low power consumption state to save power when the device enters this state. Note that the MachXO4 devices are powered on when in stand-by mode and all power supplies should remain in the Recommended Operating Conditions. 

**Table 2.17. MachXO4 Power Saving Features Description** 

|**Device Subsystem**|**Feature Description**|
|---|---|
|Bandgap|The bandgap can be turned off in stand-by mode. When the Bandgap is turned off, analog<br>circuitry such as the POR, PLLs, on-chip oscillator, and differential I/O buffers are also<br>turned off. Bandgapcan onlybe turned off for 1.2 V devices.|
|Power-On-Reset (POR)|The POR can be turned off in stand-by mode. This monitors VCC levels. In the event of<br>unsafe VCC drops, this circuit reconfigures the device. When the POR circuitry is turned<br>off, limited power detector circuitry is still active. This option is only recommended for<br>applications in which thepower supplyrails are reliable.|
|On-Chip Oscillator|The on-chip oscillator has two power saving features. It may be switched off if it is not<br>needed inyour design. It can also be turned off in stand-bymode.|
|PLL|Similar to the on-chip oscillator, the PLL also has two power saving features. It can be<br>statically switched off if it is not needed in a design. It can also be turned off in stand-by<br>mode. The PLL waits until all output clocks from the PLL are driven low before powering<br>off.|
|I/O Bank Controller|Differential I/O buffers (used to implement standards such as LVDS) consume more than<br>ratioed single-ended I/O such as LVCMOS and LVTTL. The I/O bank controller allows the<br>user to turn these I/O off dynamicallyon aper bank selection.|
|Dynamic Clock Enable for Primary<br>Clock Nets|Each primary clock net can be dynamically disabled to save power.|



© 2025 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02125-1.0 

41 

**MachXO4 Family Data Sheet** 

|**Device Subsystem**|**Feature Description**|
|---|---|
|Power Guard|Power Guard is a feature implemented in input buffers. This feature allows users to switch<br>off the input buffer when it is not needed. This feature can be used in both clock and data<br>paths. Its biggest impact is that in the stand-by mode it can be used to switch off clock<br>inputs that are distributed using general routingresources.|



For more details on the stand-by mode, refer to Power and Thermal Estimation and Management for MachXO4 Devices (FPGA-TN-02409). 

## **2.16. Power On Reset** 

MachXO4 devices have power-on reset circuitry to monitor VCCINT and VCCIO voltage levels during power-up and operation. At power-up, the POR circuitry monitors VCCINT and VCCIO0 (controls configuration) voltage levels. It then triggers download from the on-chip configuration Flash memory after reaching the VPORUP level specified in the Power-On-Reset Voltage table in the DC and Switching Characteristics section of this data sheet. For “E” devices without voltage regulators, VCCINT is the same as the VCC supply voltage. For “C” devices with voltage regulators, VCCINT is regulated from the VCC supply voltage. From this voltage reference, the time taken for configuration and entry into user mode is specified as Flash Download Time (tREFRESH) in the DC and Switching Characteristics section of this data sheet. Before and during configuration, the I/O are held in tri-state. I/O are released to user functionality once the device has finished configuration. Note that for “C” devices, a separate POR circuit monitors external VCC voltage in addition to the POR circuit that monitors the internal post-regulated power supply voltage level. 

Once the device enters into user mode, the POR circuitry can optionally continue to monitor VCCINT levels. If VCCINT drops below VPORDNBG level (with the bandgap circuitry switched on) or below VPORDNSRAM level (with the bandgap circuitry switched off to conserve power) device functionality cannot be guaranteed. In such a situation the POR issues a reset and begins monitoring the VCCINT and VCCIO voltage levels. VPORDNBG and VPORDNSRAM are both specified in the Power-On-Reset Voltage table in the DC and Switching Characteristics section of this data sheet. 

Note that once an “E” device enters user mode, users can switch off the bandgap to conserve power. When the bandgap circuitry is switched off, the POR circuitry also shuts down. The device is designed such that a minimal, low power POR circuit is still operational (this corresponds to the VPORDNSRAM reset point described in the paragraph above). However this circuit is not as accurate as the one that operates when the bandgap is switched on. The low power POR circuit emulates an SRAM cell and is biased to trip before the vast majority of SRAM cells flip. If users are concerned about the VCC supply dropping below VCC (min), they should not shut down the bandgap or POR circuit. 

## **2.17. Configuration and Testing** 

This section describes the configuration and testing features of the MachXO4 family. 

## **2.17.1. IEEE 1149.1-Compliant Boundary Scan Testability** 

All MachXO4 devices have boundary scan cells that are accessed through an IEEE 1149.1 compliant test access port (TAP). This allows functional testing of the circuit board, on which the device is mounted, through a serial scan path that can access all critical logic nodes. Internal registers are linked internally, allowing test data to be shifted in and loaded directly onto test nodes, or test data to be captured and shifted out for verification. The test access port consists of dedicated I/O: TDI, TDO, TCK and TMS. The test access port shares its power supply with VCCIO Bank 0 and can operate with LVCMOS3.3, 2.5, 1.8, 1.5, and 1.2 standards. 

For more details on boundary scan test, see Boundary Scan Testability with Lattice sysI/O Capability (AN8066) and Minimizing System Interruption During Configuration Using TransFR Technology (FPGA-TN-02198). 

## **2.17.2. Device Configuration** 

All MachXO4 devices contain two ports that can be used for device configuration. The Test Access Port (TAP), which supports bit-wide configuration and the sysCONFIG port which supports serial configuration through I2C or SPI. The TAP supports both the IEEE Standard 1149.1 Boundary Scan specification and the IEEE Standard 1532 In-System Configuration specification. There are various ways to configure a MachXO4 device: 

- Internal Flash Download 

© 2025 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02125-1.0 

42 

**MachXO4 Family Data Sheet** 

- JTAG 

- Standard Serial Peripheral Interface (Master SPI mode) – interface to boot PROM memory 

- System microprocessor to drive a serial slave SPI port (SSPI mode) 

- Standard I2C Interface to system microprocessor 

Upon power-up, the configuration SRAM is ready to be configured using the selected sysCONFIG port. Once a configuration port is selected, it remains active throughout that configuration cycle. The IEEE 1149.1 port can be activated any time after power-up by sending the appropriate command through the TAP port. Optionally, the device can run a CRC check upon entering the user mode. This ensures that the device is configured correctly. 

The sysCONFIG port has 10 dual-function pins which can be used as general purpose I/O if they are not required for configuration. See MachXO4 Programming and Configuration User Guide (FPGA-TN-02393) for more information about using the dual-use pins as general purpose I/O. 

Lattice design software uses proprietary compression technology to compress bit-streams for use in MachXO4 devices. Use of this technology allows Lattice to provide a lower cost solution. In the unlikely event that this technology is unable to compress bitstreams to fit into the amount of on-chip Flash, there are a variety of techniques that can be utilized to allow the bitstream to fit in the on-chip Flash. For more details, refer to MachXO4 Programming and Configuration User Guide (FPGA-TN-02393). 

The Test Access Port (TAP) has five dual purpose pins (TDI, TDO, TMS, TCK and JTAGENB). These pins are dual function pins - TDI, TDO, TMS and TCK can be used as general purpose I/O if desired. For more details, refer to MachXO4 Programming and Configuration User Guide (FPGA-TN-02393). 

## **2.17.2.1. TransFR (Transparent Field Reconfiguration)** 

TransFR is a unique Lattice technology that allows users to update their logic in the field without interrupting system operation using a simple push-button solution. For more details, refer to Minimizing System Interruption During Configuration Using TransFR Technology (FPGA-TN-02198) for details. 

## **2.17.2.2. Security and One-Time Programmable Mode (OTP)** 

For applications where security is important, the lack of an external bitstream provides a solution that is inherently more secure than SRAM-based FPGAs. This is further enhanced by device locking. MachXO4 devices contain security bits that, when set, prevent the readback of the SRAM configuration and Flash spaces. The device can be in one of two modes: 

- Unlocked – Readback of the SRAM configuration and Flash spaces is allowed. 

- Permanently Locked – The device is permanently locked. 

Once set, the only way to clear the security bits is to erase the device. To further complement the security of the device, a One Time Programmable (OTP) mode is available. Once the device is set in this mode it is not possible to erase or re-program the Flash and SRAM OTP portions of the device. For more details, refer to MachXO4 Programming and Configuration User Guide (FPGA-TN-02393). 

## **2.17.2.3. Password** 

The MachXO4 supports a password-based security access feature also known as Flash Protect Key. Optionally, the MachXO4 device can be ordered with a custom specification (c-spec) to support this feature. The Flash Protect Key feature provides a method of controlling access to the Configuration and Programming modes of the device. When enabled, the Configuration and Programming edit mode operations (including Write, Verify and Erase operations) are allowed only when coupled with a Flash Protect Key which matches that expected by the device. Without a valid Flash Protect Key, the user can perform only rudimentary non-configuration operations such as Read Device ID. For more details, refer to Using Password Security with MachXO4 Devices (FPGA-TN-02408). 

## **2.17.2.4. Dual Boot** 

MachXO4 devices can optionally boot from two patterns, a primary bitstream and a golden bitstream. If the primary bitstream is found to be corrupt while being downloaded into the SRAM, the device shall then automatically re-boot from the golden bitstream. Note that the primary bitstream must reside in the external SPI Flash. The golden image MUST reside in an on-chip Flash. For more details, refer to MachXO4 Programming and Configuration User Guide (FPGA-TN-02393). 

© 2025 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02125-1.0 

43 

**MachXO4 Family Data Sheet** 

## **2.17.2.5. Soft Error Detection** 

The SED feature is a CRC check of the SRAM cells after the device is configured. This check ensures that the SRAM cells were configured successfully. This feature is enabled by a configuration bit option. The Soft Error Detection can also be initiated in user mode via an input to the fabric. The clock for the Soft Error Detection circuit is generated using a dedicated divider. The undivided clock from the on-chip oscillator is the input to this divider. For low power applications users can switch off the Soft Error Detection circuit. For more details, refer to MachXO4 Soft Error Detection (SED)/Correction (SEC) User Guide (FPGA-TN-02406). 

## **2.17.2.6. Soft Error Correction** 

The MachXO4 device supports Soft Error Correction (SEC).  When BACKGROUND_RECONFIG is enabled using the Lattice Radiant Software in a design, asserting the PROGRAMN pin or issuing the REFRESH sysConfig command refreshes the SRAM array from configuration memory. Only the detected error bit is corrected. No other SRAM cells are changed, allowing the user design to function uninterrupted. 

During the project design phase, if the overall system cannot guarantee containment of the error or its subsequent effects on downstream data or control paths, Lattice recommends using SED only. The MachXO4 can be then be soft-reset by asserting PROGRAMN or issuing the Refresh command over a sysConfig port in response to SED. Soft-reset additionally erases the SRAM array prior to the SRAM refresh, and asserts internal Reset circuitry to guarantee a known state. For more details, refer to MachXO4 Soft Error Detection (SED)/Correction (SEC) User Guide (FPGA-TN-02406). 

## **2.18. TraceID** 

Each MachXO4 device contains a unique (per device), TraceID that can be used for tracking purposes or for IP security applications. The TraceID is 64 bits long. Eight out of 64 bits are user-programmable, the remaining 56 bits are factoryprogrammed. The TraceID is accessible through the EFB WISHBONE interface and can also be accessed through the SPI, I2C, or JTAG interfaces. 

## **2.19. Density Shifting** 

The MachXO4 family has been designed to enable density migration within the same package. Furthermore, the architecture ensures a high success rate when performing design migration from lower density devices to higher density devices. In many cases, it is also possible to shift a lower utilization design targeted for a high-density device to a lower density device. However, the exact details of the final resource utilization impact the likely success in each case. When migrating from lower to higher density or higher to lower density, ensure to review all the power supplies and NC pins of the chosen devices. 

© 2025 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02125-1.0 

44 

**MachXO4 Family Data Sheet** 

## **3. DC and Switching Characteristics** 

## **3.1. Absolute Maximum Rating** 

## **Table 3.1. Absolute Maximum Rating[1, 2, 3]** 

||**MachXO4 E(1.2 V)**|**MachXO4 C(2.5 V/3.3 V)6**|
|---|---|---|
|SupplyVoltage VCC|–0.5 V to 1.32 V|–0.5 V to 3.75 V|
|Output SupplyVoltage VCCIO|–0.5 V to 3.75 V|–0.5 V to 3.75 V|
|I/O Tri-state Voltage Applied4, 5|–0.5 V to 3.75 V|–0.5 V to 3.75 V|
|Dedicated Input Voltage Applied4|–0.5 V to 3.75 V|–0.5 V to 3.75 V|
|Storage Temperature(Ambient)|–55 °C to 125 °C|–55 °C to 125 °C|
|Junction Temperature(TJ)|–40 °C to 125 °C|–40 °C to 125 °C|



## **Notes:** 

1. Stress above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. Functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. 

2. Compliance with the Lattice Thermal Management document is required. 

3. All voltages referenced to GND. 

4. Overshoot and undershoot of –2 V to (VIHMAX + 2) volts is permitted for a duration of <20 ns. 

5. The dual function I2C pins SCL and SDA are limited to –0.25 V to 3.75 V or to –0.3 V with a duration of <20 ns. 

6. Refer to Power and Thermal Estimation and Management for MachXO4 Devices (FPGA-TN-02409) for determination of safe ambient operating conditions. 

## **3.2. Recommended Operating Conditions** 

**Table 3.2. Recommended Operating Conditions[1]** 

|**Symbol**|**Parameter**|**Min.**|**Max.**|**Unit**|
|---|---|---|---|---|
|VCC1|Core SupplyVoltage for 1.2 V Devices|1.14|1.26|V|
||Core SupplyVoltage for 2.5 V/3.3 V Devices|2.375|3.465|V|
|VCCIO1, 2, 3|I/O Driver SupplyVoltage|1.14|3.465|V|
|tJCOM|Junction Temperature Commercial Operation|0|85|°C|
|tJIND|Junction Temperature Industrial Operation|–40|100|°C|
|tJAUTO|Junction Temperature Automotive Operation|–40|125|°C|



## **Notes:** 

1. Like power supplies must be tied together. For example, if VCCIO and VCC are both the same voltage, they must also be the same supply. 

2. See recommended voltages by I/O standard in subsequent table. 

3. VCCIO pins of unused I/O banks should be connected to the VCC power supply on boards. 

## **3.3. Power Supply Ramp Rates** 

**Table 3.3. Power Supply Ramp Rates** 

|**Symbol**|**Symbol**|**Parameter**|**Min.**|**Typ. **|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|tRAMP|Commercial/Industrial|Power supply ramp rates for all power supplies.|0.01|—|100|V/ms|
||Automotive||0.01|—|40|V/ms|



**Note:** Assumes monotonic ramp rates. 

© 2025 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02125-1.0 

45 

**MachXO4 Family Data Sheet** 

## **3.4. Power-On-Reset Voltage Levels** 

## **Table 3.4. Power-On Reset Voltage Levels** 

|**Symbol**<br>~~a ~~|**Parameter**<br> ~~ee~~|**Commercial/Industrial**<br>~~es~~<br>~~ee~~|**Commercial/Industrial**<br>~~es~~<br>~~ee~~|**Commercial/Industrial**<br>~~es~~<br>~~ee~~|**Automotive**<br>~~es~~<br>~~ee~~|**Automotive**<br>~~es~~<br>~~ee~~|**Automotive**<br>~~es~~<br>~~ee~~|**Unit**<br>~~ee~~|
|---|---|---|---|---|---|---|---|---|
|||**Min.**<br>~~es~~|**Typ. **<br>~~es~~|**Max.**<br>~~es~~<br>~~ee~~|**Min.**<br>~~es~~<br>~~ee~~|**Typ. **<br>~~es~~<br>~~ee~~|**Max.**<br>~~es~~<br>~~ee~~||
|VPORUP<br>|Power-On-Reset ramp up trip point (band gap<br>based circuit monitoringVCCINT and VCCIO0)<br> ~~ee~~|0.9|—|1.06<br>~~ee~~|0.9<br>~~ee~~|—<br>~~ee~~|1.06<br>~~ee~~|V<br>~~ee~~|
|VPORUPEXT|Power-On-Reset ramp up trip point (band gap<br>based circuit monitoring external VCCpower<br>supply)|1.5|—|2.1|1.5|—|2.1|V|
|VPORDNBG<br>~~a~~|Power-On-Reset ramp down trip point (band gap<br>based circuit monitoringVCCINT)|0.75|—|0.93|0.75|—|1.06|V|
|VPORDNBGEXT<br>~~a~~<br>~~a~~|Power-On-Reset ramp down trip point (band gap<br>based circuit monitoringVCC)|0.98|—|1.33|0.98|—|1.47|V|
|VPORDNSRAM<br>~~a~~<br>~~a~~|Power-On-Reset ramp down trip point (SRAM<br>based circuit monitoringVCCINT)|—|0.6|—|—|0.84|—|V|
|VPORDNSRAMEXT<br>~~a~~<br>~~a~~|Power-On-Reset ramp down trip point (SRAM<br>based circuit monitoringVCC)|—|0.96|—|—|1.16|—|V|



## **Notes:** 

- These POR trip points are only provided for guidance. Device operation is only characterized for power supply voltages specified under recommended operating conditions. 

- For devices without voltage regulators VCCINT is the same as the VCC supply voltage. For devices with voltage regulators, VCCINT is regulated from the VCC supply voltage. 

- Note that VPORUP (min.) and VPORDNBG (max.) are in different process corners. For any given process corner VPORDNBG (max.) is always 12.0 mV below VPORUP (min.). 

- VPORUPEXT is for HC devices only. In these devices, a separate POR circuit monitors the external VCC power supply. 

- VCCIO0 does not have a Power-On-Reset ramp down trip point. VCCIO0 must remain within the Recommended Operating Conditions to ensure proper operation. 

## **3.5. Hot Socketing Specifications** 

**Table 3.5. Hot Socketing Specifications** 

|**Symbol**|**Parameter**|**Condition**|**Commercial/Industrial**|**Automotive**|**Unit**|
|---|---|---|---|---|---|
||||**Max.**|||
|IDK|Input or I/O leakage Current|0 < VIN< VIH(MAX)|±350|±400|µA|



**Notes** : 

1. Insensitive to sequence of VCC and VCCIO. However, assumes monotonic rise/fall rates for VCC and VCCIO. 

2. 0 < VCC < VCC (MAX), 0 < VCCIO < VCCIO (MAX). 

3. IDK is additive to IPU, IPD or IBH. 

4. Clamp option is set to OFF 

© 2025 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02125-1.0 

46 

**MachXO4 Family Data Sheet** 

## **3.6. Programming/Erase Specifications** 

**Table 3.6. Programming/Erase Specifications** 

|**Symbol**|**Parameter**|**Commercial/Industrial**|**Commercial/Industrial**|**Automotive**|**Automotive**|**Unit**|
|---|---|---|---|---|---|---|
|||**Min.**|**Max.1**|**Min.**|**Max.1**||
|NPROGCYC|Flash Programmingcyclesper tRETENTION|—|10,000|—|1,000|Cycle|
||Flash Write/Erase cycles2|—|100,000|—|10,000||
|tRETENTION|Data retention at 125°Cjunction temperature|—|—|2|—|Year|
||Data retention at 100°Cjunction temperature|10|—|10|—||
||Data retention at 85°Cjunction temperature|20|—|20|—||



**Notes:** 

1. Maximum Flash memory reads are limited to 7.5E13 cycles over the lifetime of the product. 

2. A Write/Erase cycle is defined as any number of writes over time followed by any erase cycle. 

## **3.7. ESD Performance** 

Refer to the MachXO4 Product Family Qualification Summary for complete qualification data, including ESD performance. The MachXO4 Family Qualification Summary can be requested from Lattice Semiconductor Quality and Reliability Team. 

## **3.8. DC Electrical Characteristics** 

Over recommended operating conditions. 

**Table 3.7. DC Electrical Characteristics** 

|**Symbol**<br>~~ee~~|**Parameter**<br>~~ee~~|**Condition**<br>~~ee~~<br>~~a~~|**Commercial/Industrial**<br>~~ee~~<br>~~ee~~~~**e**~~|**Commercial/Industrial**<br>~~ee~~<br>~~ee~~~~**e**~~|**Commercial/Industrial**<br>~~ee~~<br>~~ee~~~~**e**~~|**Automotive**<br>~~ee~~<br>~~**e** eee~~|**Automotive**<br>~~ee~~<br>~~**e** eee~~|**Automotive**<br>~~ee~~<br>~~**e** eee~~|**Unit**<br>~~ee~~<br>~~eee~~|
|---|---|---|---|---|---|---|---|---|---|
||||**Min.**<br>~~ee~~<br>~~ee~~|**Typ. **<br>~~ee~~<br>~~ee~~|**Max.**<br>~~ee~~<br>~~ee~~~~**e**~~|**Min.**<br>~~ee~~<br>~~**e** eee~~|**Typ. **<br>~~ee~~<br>~~eee~~|**Max.**<br>~~ee~~<br>~~eee~~||
|IIL, IIH1, 4|Input or I/O Leakage<br>~~pO~~|Clamp OFF and VCCIO< VIN<<br>VIH (MAX)<br>~~a~~|—<br>~~ee~~|—<br>~~ee~~<br>~~e~~|+175<br>~~ee~~~~**e**~~<br>~~e~~|—<br>~~**e** eee~~|—<br>~~eee~~<br>~~ee~~|+175<br>~~eee~~<br>~~ee~~|µA<br>~~eee~~<br>~~ee~~|
|||ClampOFF and VIN= VCCIO<br>~~a~~<br>~~GG~~|–10<br>~~ee~~<br>~~GG~~|—<br>~~ee~~<br>~~e~~<br>~~GG~~|10<br>~~ee~~~~**e**~~<br>~~e~~<br>~~GG~~|–10<br>~~**e** eee~~<br>~~GG~~|—<br>~~eee~~<br>~~ee~~<br>~~GG~~|11<br>~~eee~~<br>~~ee~~<br>~~GG~~|µA<br>~~eee~~<br>~~ee~~<br>~~GG~~|
|||Clamp OFF and VCCIO- 0.97 V<br>< VIN< VCCIO<br>~~GG~~<br>~~a~~<br>~~pO~~|–175<br>~~GG~~<br>|—<br>~~GG~~<br>~~ee~~<br>|—<br>~~GG~~<br>~~ee~~<br>|–175<br>~~GG~~<br>~~ee~~<br>|—<br>~~GG~~<br>~~ee~~<br>|—<br>~~GG~~<br>~~ee~~<br>|µA<br>~~GG~~<br>~~ee~~<br>|
|||Clamp OFF and 0 V < VIN<<br>VCCIO– 0.97 V<br>~~a~~<br>~~ee~~<br>~~pO~~|—<br>~~ee~~<br>|—<br>~~ee~~<br>~~ee~~<br>|10<br>~~ee~~<br>~~ee~~<br>|—<br>~~ee~~<br>~~ee~~<br>|—<br>~~ee~~<br>~~ee~~<br>|10<br>~~ee~~<br>~~ee~~<br>|µA<br>~~ee~~<br>~~ee~~<br>|
|||ClampOFF and VIN= GND<br>~~ee~~<br>~~pO~~|—<br>~~ee~~<br>|—<br>~~ee~~<br>~~ee~~<br>|10<br>~~ee~~<br>~~ee~~<br>|—<br>~~ee~~<br>~~ee~~<br>|—<br>~~ee~~<br>~~ee~~<br>|10<br>~~ee~~<br>~~ee~~<br>|µA<br>~~ee~~<br>~~ee~~<br>|
|||Clamp ON and 0 V < VIN<<br>VCCIO<br>~~pOee~~|—<br>~~ee~~|—<br>~~ee~~<br>~~ee~~|10<br>~~ee~~<br>~~ee~~|—<br>~~ee ~~<br>~~ee~~|—<br> ~~ee~~<br>~~ee~~|11<br>~~ee~~<br>~~ee~~|µA<br>~~ee~~<br>~~ee~~|
|IPU<br>~~a~~|I/O Active Pull-up<br>Current<br><br>~~a~~|0 < VIN< 0.7 VCCIO<br>~~ee~~<br>~~a~~|–309<br>~~ee~~<br>~~a~~|—<br>~~ee~~<br>~~a~~|–26<br>~~ee~~<br>~~a~~|–309<br>~~ee~~<br>~~a~~|—<br>~~ee~~<br>~~a~~|–26<br>~~ee~~<br>~~a~~|µA<br>~~ee~~<br>~~a~~|
|IPD<br>~~a~~<br>~~a~~|I/O Active Pull-down<br>Current<br>~~a~~<br>~~a~~|VIL(MAX) < VIN< VCCIO<br>~~a~~<br>~~a~~|30<br>~~a~~<br>~~a~~|—<br>~~a~~<br>~~a~~|305<br>~~a~~<br>~~a~~|30<br>~~a~~<br>~~a~~|—<br>~~a~~<br>~~a~~|305<br>~~a~~<br>~~a~~|µA<br>~~a~~<br>~~a~~|
|IBHLS<br>~~a~~<br>~~a~~|Bus Hold Low<br>sustainingcurrent<br>~~a~~<br>~~a~~|VIN= VIL(MAX)<br>~~a~~<br>~~a~~|30<br>~~a~~<br>~~a~~|—<br>~~a~~<br>~~a~~|—<br>~~a~~<br>~~a~~|30<br>~~a~~<br>~~a~~|—<br>~~a~~<br>~~a~~|—<br>~~a~~<br>~~a~~|µA<br>~~a~~<br>~~a~~|
|IBHHS<br>~~a~~<br>~~ee~~|Bus Hold High<br>sustainingcurrent<br>~~a~~<br>~~ee~~|VIN= 0.7VCCIO<br>~~a~~<br>~~ee~~|–30<br>~~a~~<br>~~ee~~|—<br>~~a~~<br>~~ee~~|—<br>~~a~~<br>~~ee~~|–27<br>~~a~~<br>~~ee~~|—<br>~~a~~<br>~~ee~~|—<br>~~a~~<br>~~ee~~|µA<br>~~a~~<br>~~ee~~|
|IBHLO<br>~~ee~~<br>~~a~~|Bus Hold Low<br>Overdrive current<br>~~ee~~<br>~~a~~|0 ≤ VIN≤ VCCIO<br>~~ee~~|—<br>~~ee~~|—<br>~~ee~~|305<br>~~ee~~|—<br>~~ee~~|—<br>~~ee~~|305<br>~~ee~~|µA<br>~~ee~~|
|IBHHO<br>~~a~~<br>~~a~~<br>~~Ps~~|Bus Hold High<br>Overdrive current<br>~~a~~<br>~~a~~|0 ≤ VIN≤ VCCIO|—|—|–309|—|—|–309|µA|
|VBHT3<br>~~a~~<br>~~Ps~~|Bus Hold Trip Points<br>~~a~~|—|VIL<br>(MAX)|—|VIH<br>(MIN)|VIL<br>(MAX)|—|VIH<br>(MIN)|V|



© 2025 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02125-1.0 

47 

|**Symbol**<br>~~cas~~|**Parameter**<br>~~cas~~|**Condition**<br>~~SEE~~|**Commercial/Industrial**<br>~~SEE~~|**Commercial/Industrial**<br>~~SEE~~|**Commercial/Industrial**<br>~~SEE~~|**Automotive**<br>~~cae LATTICE~~<br>~~SEE~~|**Automotive**<br>~~cae LATTICE~~<br>~~SEE~~|**Automotive**<br>~~cae LATTICE~~<br>~~SEE~~|**Unit**<br>~~LATTICE~~<br>~~SEE~~|
|---|---|---|---|---|---|---|---|---|---|
||||**Min.**<br>~~SEE~~|**Typ. **<br>~~SEE~~|**Max.**<br>~~SEE~~|**Min.**<br>~~cae~~<br>~~SEE~~|**Typ. **<br>~~cae LATTICE~~<br>~~SEE~~|**Max.**<br>~~LATTICE~~<br>~~SEE~~||
|C1<br>~~cas~~|I/O Capacitance2<br>~~cas~~|VCCIO= 3.3 V, 2.5 V, 1.8 V, 1.5<br>V, 1.2 V<br>VCC= Typ., VIO= 0 to VIH<br>(MAX)<br>~~SEE~~|3<br>~~SEE~~<br>~~ee~~|5<br>~~SEE~~<br>~~ee~~|9<br>~~SEE~~<br>~~ee~~|3<br>~~cae~~<br>~~SEE~~|5<br>~~cae LATTICE~~<br>~~SEE~~|9<br>~~LATTICE~~<br>~~SEE~~|pf<br>~~LATTICE~~<br>~~SEE~~|
|VHYST<br>~~cas~~|Hysteresis for Schmitt<br>Trigger Inputs5<br>~~cas~~|VCCIO= 3.3 V, Hysteresis =<br>Large<br>~~SEE~~<br>~~es~~|—<br>~~SEE~~<br>~~es~~<br>~~ee~~<br>~~ee~~|450<br>~~SEE~~<br>~~es~~<br>~~ee~~<br>~~ee~~|—<br>~~SEE~~<br>~~es~~<br>~~ee~~<br>~~ee~~|—<br>~~cae~~<br>~~SEE~~<br>~~es~~|450<br>~~cae LATTICE~~<br>~~SEE~~<br>~~es~~|—<br>~~LATTICE~~<br>~~SEE~~<br>~~es~~|mV<br>~~LATTICE~~<br>~~SEE~~<br>~~es~~|
|||VCCIO= 2.5 V, Hysteresis =<br>Large<br><br>~~es~~<br>~~ee~~|—<br><br>~~es~~<br>~~ee ~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|250<br><br>~~es~~<br> ~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|—<br><br>~~es~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|—<br>~~cae~~<br><br>~~es~~<br>~~ee~~<br>~~eee~~|250<br>~~cae LATTICE~~<br><br>~~es~~<br>~~ee~~<br>~~eee~~|—<br>~~LATTICE~~<br><br>~~es~~<br>~~ee~~<br>~~eee~~|mV<br>~~LATTICE~~<br><br>~~es~~<br>~~ee~~<br>~~eee~~|
|||VCCIO= 1.8 V, Hysteresis =<br>Large<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee ~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|125<br>~~ee~~<br> ~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~<br>~~eee~~|125<br>~~ee~~<br>~~ee~~<br>~~eee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~<br>~~eee~~<br>~~ee~~|mV<br>~~ee~~<br>~~ee~~<br>~~eee~~<br>~~ee~~|
|||VCCIO= 1.5 V, Hysteresis =<br>Large<br>~~ee~~|—<br>~~ee ~~<br>~~ee~~<br>~~ee~~|100<br> ~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~|—<br>~~eee~~<br>~~ee~~|100<br>~~eee~~<br>~~ee~~<br>~~ee~~|—<br>~~eee~~<br>~~ee~~<br>~~ee~~|mV<br>~~eee~~<br>~~ee~~<br>~~ee~~|
|||VCCIO= 3.3 V, Hysteresis =<br>Small<br>~~ee~~|—<br>~~ee ~~<br>~~ee~~<br>~~ee~~|250<br> ~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee eee~~|—<br>~~ee~~<br>~~ee~~<br>~~eee~~|—<br>~~ee~~<br>~~eee~~|250<br>~~ee~~<br>~~ee~~<br>~~eee~~|—<br>~~ee~~<br>~~ee~~<br>~~eee~~|mV<br>~~ee~~<br>~~ee~~<br>~~eee~~|
|||VCCIO= 2.5 V, Hysteresis =<br>Small<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|150<br>~~ee~~<br>~~ee ~~<br>~~ee~~<br>~~ee eee~~<br>~~ee eee~~|—<br>~~ee~~<br> ~~ee~~<br>~~ee~~<br>~~eee~~<br>~~eee~~|—<br>~~ee~~<br>~~ee~~<br>~~eee~~<br>~~eee~~|150<br>~~ee~~<br>~~ee~~<br>~~eee~~<br>~~eee~~|—<br>~~ee~~<br>~~ee~~<br>~~eee~~<br>~~eee~~|mV<br>~~ee~~<br>~~ee~~<br>~~eee~~<br>~~eee~~|
|||VCCIO= 1.8 V, Hysteresis =<br>Small<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee ~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|60<br>~~ee~~<br> ~~ee eee~~<br>~~ee~~<br>~~ee eee~~<br>~~ee~~|—<br>~~ee~~<br>~~eee~~<br>~~ee~~<br>~~eee~~<br>~~ee~~|—<br>~~ee~~<br>~~eee~~<br>~~ee~~<br>~~eee~~|60<br>~~ee~~<br>~~eee~~<br>~~ee~~<br>~~eee~~|—<br>~~ee~~<br>~~eee~~<br>~~ee~~<br>~~eee~~|mV<br>~~ee~~<br>~~eee~~<br>~~ee~~<br>~~eee~~|
|||VCCIO= 1.5 V, Hysteresis =<br>Small<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee ~~<br>~~ee~~<br>~~ee~~|40<br>~~ee~~<br> ~~ee eee~~<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~eee~~<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~eee~~<br>~~ee~~|40<br>~~ee~~<br>~~eee~~<br>~~ee~~|—<br>~~ee~~<br>~~eee~~<br>~~ee~~|mV<br>~~ee~~<br>~~eee~~<br>~~ee~~|



## **Notes:** 

1. Input or I/O leakage current is measured with the pin configured as an input or as an I/O with the output driver tri-stated. It is not measured with the output driver active. Bus maintenance circuits are disabled. 

2. TA 25 °C, f = 1.0 MHz. 

3. Refer to VIL and VIH in the sysI/O Single-Ended DC Electrical Characteristics table of this document. 

4. When VIH is higher than VCCIO, a transient current typically of 30 ns in duration or less with a peak current of 6 mA can occur on the high-to-low transition. For true LVDS output pins in MachXO4 devices, VIH must be less than or equal to VCCIO. 

5. With bus keeper circuit turned on. For more details, refer to MachXO4 sysI/O User Guide (FPGA-TN-02398). 

© 2025 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02125-1.0 

48 

**MachXO4 Family Data Sheet** 

## **3.9. Static Supply Current – HC/HE Devices** 

**Table 3.8. Static Supply Current – HC/HE Devices[1, 2, 3, 6]** 

|**Symbol**<br>~~a~~|**Parameter**<br>~~eG~~|**Device**<br>~~eG~~|**Typ.4**<br>~~eG~~|**Unit**<br>~~eG~~|
|---|---|---|---|---|
|ICC|Core Power Supply<br>~~i~~|LFMXO4-010HC<br>~~a~~|3.49<br>~~a~~|mA<br>~~a~~|
|||LFMXO4-015HC<br>~~a~~|3.49<br>~~a~~|mA<br>~~a~~|
|||LFMXO4-015HC 256 Ball Package<br>~~a~~|4.8<br>~~a~~|mA<br>~~a~~|
|||LFMXO4-025HC<br>~~a~~<br>~~a~~|4.8<br>~~a~~<br>~~a~~|mA<br>~~a~~<br>~~a~~|
|||LFMXO4-050HC<br>~~a~~<br>~~a~~|8.45<br>~~a~~<br>~~a~~|mA<br>~~a~~<br>~~a~~|
|||LFMXO4-050HC 400 Ball Package<br>~~a~~<br>~~pf~~|12.87<br>~~a~~<br>~~pf~~|mA<br>~~a~~<br>~~pf~~|
|||LFMXO4-080HC<br>~~a~~|12.87<br>~~a~~|mA<br>~~a~~|
|||LFMXO4-110HC<br>~~a~~|17.86<br>~~a~~|mA<br>~~a~~|
|||LFMXO4-010HE<br>~~a~~|1.00<br>~~a~~|mA<br>~~a~~|
|||LFMXO4-015HE<br>~~a~~<br>~~a~~|1.00<br>~~a~~<br>~~a~~|mA<br>~~a~~<br>~~a~~|
|||LFMXO4-015HE 256 Ball Package<br>~~a~~<br>~~es~~|1.39<br>~~a~~<br>~~es~~|mA<br>~~a~~<br>~~es~~|
|||LFMXO4-025HE<br>~~es~~<br>~~i~~|1.39<br>~~es~~<br>|mA<br>~~es~~<br>|
|||LFMXO4-050HE<br>~~i~~|2.55<br>|mA<br>|
|||LFMXO4-050HE 400 Ball Package<br>~~i~~|4.06<br>|mA<br>|
|||LFMXO4-080HE<br>|4.06<br>|mA<br>|
|||LFMXO4-110HE<br>~~ee~~|5.66<br>~~ee~~|mA<br>~~ee~~|
|ICCIO<br>~~eG~~|Bank Power Supply5VCCIO= 2.5 V<br><br>~~eG~~|All devices<br>~~ee~~<br>~~eG~~|0<br>~~ee~~<br>~~eG~~|mA<br>~~ee~~<br>~~eG~~|



## **Notes:** 

1. For further information on supply current, refer to Power and Thermal Estimation and Management for MachXO4 Devices (FPGA-TN-02409). 

2. Assumes a test pattern with the following characteristics: all outputs are tri-stated, all inputs are configured as LVCMOS and held at VCCIO or GND, on-chip oscillator is off, on-chip PLL is off. 

3. Frequency = 0 MHz. 

4. TJ = 25 °C, power supplies at nominal voltage. 

5. Does not include pull-up/pull-down. 

6. To determine the MachXO4 peak start-up current data, use the Power Calculator tool. 

© 2025 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02125-1.0 

49 

**MachXO4 Family Data Sheet** 

## **3.10. Programming and Erase Supply Current – HC/HE Devices** 

**Table 3.9. Programming and Erase Supply Current – HC/HE Devices[1, 2, 3, 4]** 

|**Symbol**<br>~~a~~|**Parameter**|**Device**|**Typ.4**|**Unit**|
|---|---|---|---|---|
|ICC<br>~~es~~|Core Power Supply<br>~~aa~~<br>~~a~~<br>~~a~~<br>~~aaaa~~<br>~~a~~<br>~~a~~|LFMXO4-010HC<br>~~ee~~<br>~~a~~|18.8<br>~~ee~~|mA<br>~~ee~~|
|||LFMXO4-015HC<br>~~aa~~|18.8|mA|
|||LFMXO4-015HC 256 Ball Package<br>~~aa~~<br>~~a~~|22.1|mA|
|||LFMXO4-025HC<br>~~a~~<br>~~a~~<br>~~a~~|22.1<br>|mA<br>|
|||LFMXO4-050HC<br>~~a~~<br>~~a~~|26.8<br>|mA<br>|
|||LFMXO4-050HC 400 Ball Package<br>~~aes~~<br>~~aa~~|33.2<br>~~es~~|mA<br>~~es~~|
|||LFMXO4-080HC<br>~~aa~~|33.2|mA|
|||LFMXO4-110HC<br>~~aaa~~|39.6|mA|
|||LFMXO4-010HE<br>~~aaaa~~|17.7|mA|
|||LFMXO4-015HE<br>~~aa~~|17.7|mA|
|||LFMXO4-015HE 256 Ball Package<br>~~a~~<br>~~a~~|18.3<br>|mA<br>|
|||LFMXO4-025HE<br>~~a~~|18.3<br>|mA<br>|
|||LFMXO4-050HE<br>~~aa~~|20.4<br>~~a~~<br>~~ee~~|mA<br>~~a~~|
|||LFMXO4-050HE 400 Ball Package<br>~~a~~<br>~~es~~<br>~~a~~|23.9<br>~~a~~<br>~~es~~<br>~~ee~~<br>~~ee~~|mA<br>~~a~~<br>~~es~~|
|||LFMXO4-080HE<br>~~es~~<br>~~es~~<br>~~a~~|23.9<br>~~es~~<br>~~ee~~<br>~~es~~<br>~~ee~~|mA<br>~~es~~<br>~~es~~|
|||LFMXO4-110HE<br>~~es~~<br>~~a~~|28.5<br>~~es~~<br>~~ee~~|mA<br>~~es~~|
|ICCIO<br>~~es~~|Bank Power Supply5VCCIO= 2.5 V All devices<br>~~a~~|= 2.5 V All devices<br>~~a~~|0<br>~~ee~~|mA|



## **Notes:** 

1. For further information on supply current, refer to Power and Thermal Estimation and Management for MachXO4 Devices (FPGA-TN-02409). 

2. Assumes all inputs are held at VCCIO or GND and all outputs are tri-stated. 

3. Typical user pattern. 

4. JTAG programming is at 25 MHz. 

5. TJ = 25 °C, power supplies at nominal voltage. 

6. Per bank. VCCIO = 2.5 V. Does not include pull-up/pull-down. 

## **3.11. sysI/O Recommended Operating Conditions** 

**Table 3.10. sysI/O Recommended Operating Conditions** 

|**Standard**<br>~~a~~<br>~~gp~~<br>~~ee~~|**VCCIO (V)**<br>~~a~~<br>~~gp~~|**VCCIO (V)**<br>~~a~~<br>~~gp~~|**VCCIO (V)**<br>~~a~~<br>~~gp~~|**VREF (V)**|**VREF (V)**|**VREF (V)**|
|---|---|---|---|---|---|---|
||**Min.**<br>~~a~~<br>~~gp~~<br>~~ee~~|**Typ. **<br>~~gp~~<br>~~ee~~|**Max.**<br>~~gp~~|**Min.**|**Typ. **<br>~~eee~~|**Max.**<br>~~eee~~|
|LVCMOS 3.3<br>~~gp~~<br>~~ee~~|3.135<br>~~gp~~<br>~~ee~~|3.3<br>~~gp~~<br>~~ee~~|3.465<br>~~gp~~|—|—<br>~~eee~~|—<br>~~eee~~|
|LVCMOS 2.5<br>~~ee~~<br>~~pp~~<br>~~ee~~|2.375<br>~~ee~~<br>~~pp~~<br>~~ee~~|2.5<br>~~ee~~<br>~~pp~~<br>~~ee~~|2.625<br>~~pp~~<br>~~ee~~|—|—<br>~~eee~~<br>~~ee~~|—<br>~~eee~~<br>~~ee~~|
|LVCMOS 1.8<br>~~ee ~~<br>~~pp~~<br>~~ee~~<br>~~op~~|1.71<br> ~~ee~~<br>~~pp~~<br>~~ee~~<br>~~op~~|1.8<br>~~ee~~<br>~~pp~~<br>~~ee~~<br>~~ph~~|1.89<br>~~pp~~<br>~~ee~~<br>~~phhp~~|—<br>~~hp~~|—<br>~~eee~~<br>~~ee~~<br>~~hp~~|—<br>~~eee~~<br>~~ee~~|
|LVCMOS 1.5<br>~~ee~~<br>~~op~~|1.425<br>~~ee~~<br>~~op~~|1.5<br>~~ee~~<br>~~ph~~|1.575<br>~~ee~~<br>~~phhp~~|—<br>~~hp~~|—<br>~~ee~~<br>~~hp~~|—<br>~~ee~~|
|LVCMOS 1.2<br>~~ee~~<br>~~op~~<br>~~ee~~|1.14<br>~~ee~~<br>~~op~~<br>~~ee~~|1.2<br>~~ee~~<br>~~ph~~<br>~~ee~~|1.26<br>~~ee~~<br>~~phhp~~|—<br>~~hp~~|—<br>~~ee~~<br>~~hp~~|—<br>~~ee~~|
|LVTTL<br>~~op~~<br>~~ee~~<br>~~a~~|3.135<br>~~op~~<br>~~ee~~<br>~~a~~|3.3<br>~~ph~~<br>~~ee~~|3.465<br>~~ph hp~~|—<br>~~hp~~|—<br>~~hp~~|—|
|LVDS251, 2<br>~~a~~<br>~~en~~<br>~~ee~~|2.375<br>~~a~~<br>~~en~~<br>~~ee~~|2.5<br>~~en~~<br>~~a~~|2.625<br>~~en~~<br>~~a~~|—|—|—|
|LVDS331, 2<br>~~en~~<br>~~ee~~|3.135<br>~~en~~<br>~~ee~~|3.3<br>~~en~~<br>~~a~~|3.465<br>~~en~~<br>~~a~~|—|—|—|
|LVPECL1<br>~~ee~~<br>~~SY~~<br>~~————————————~~|3.135<br>~~ee~~<br>~~SY~~<br>~~————————————~~|3.3<br>~~a~~<br>~~SY~~<br>~~————————————~~|3.465<br>~~a~~<br>~~SY~~<br>~~————————————~~|—<br>~~SY~~<br>~~————————————~~|—<br>~~SY~~<br>~~————————————~~|—<br>~~SY~~<br>~~————————————~~|
|BLVDS1<br>~~ee~~<br>~~SY~~<br>~~————————————~~<br>~~ee~~|2.375<br>~~ee ~~<br>~~SY~~<br>~~————————————~~<br>~~ee~~|2.5<br> ~~a ~~<br>~~SY~~<br>~~————————————~~<br>~~a~~|2.625<br> ~~a~~<br>~~SY~~<br>~~————————————~~<br>~~a~~|—<br>~~SY~~<br>~~————————————~~|—<br>~~SY~~<br>~~————————————~~|—<br>~~SY~~<br>~~————————————~~|
|MIPI3<br>~~SY~~<br>~~————————————~~<br>~~ee~~<br>~~pf~~|2.375<br>~~SY~~<br>~~————————————~~<br>~~ee~~<br>~~pf~~|2.5<br>~~SY~~<br>~~————————————~~<br>~~a~~<br>~~pf~~|2.625<br>~~SY~~<br>~~————————————~~<br>~~a~~|—<br>~~SY~~<br>~~————————————~~|—<br>~~SY~~<br>~~————————————~~|—<br>~~SY~~<br>~~————————————~~|
|MIPI_LP3<br>~~————————————~~<br>~~ee~~<br>~~pf~~|1.14<br>~~————————————~~<br>~~ee~~<br>~~pf~~|1.2<br>~~————————————~~<br>~~a~~<br>~~pf~~|1.26<br>~~————————————~~<br>~~a~~|—<br>~~————————————~~|—<br>~~————————————~~|—<br>~~————————————~~|
|LVCMOS25R33<br>~~ee~~<br>~~pf~~<br>~~a~~<br>~~es~~|3.135<br>~~ee ~~<br>~~pf~~<br>~~a~~|3.3<br> ~~a ~~<br>~~pf~~<br>~~a~~<br>~~ee~~|3.6<br> ~~a~~<br>~~a~~<br>~~A~~|1.1<br>~~a~~<br>~~A~~|1.25|1.4|
|LVCMOS18R33<br>~~pf~~<br>~~a~~<br>~~ga~~<br>~~es~~|3.135<br>~~pf~~<br>~~a~~<br>~~ga~~|3.3<br>~~pf~~<br>~~a~~<br>~~ee~~|3.6<br>~~a~~<br>~~A~~|0.75<br>~~a~~<br>~~A~~|0.9|1.05<br>~~Y~~|
|LVCMOS18R25<br>~~ga~~<br>~~es~~|2.375<br>~~ga~~|2.5<br>~~ee~~|2.625<br>~~A~~|0.75<br>~~A~~|0.9|1.05<br>~~Y~~|



© 2025 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02125-1.0 

50 

**MachXO4 Family Data Sheet** 

|**Standard**<br>~~es~~<br>~~a~~|**VCCIO (V)**<br>~~a~~<br>~~es~~<br>~~ee~~|**VCCIO (V)**<br>~~a~~<br>~~es~~<br>~~ee~~|**VCCIO (V)**<br>~~a~~<br>~~es~~<br>~~ee~~|**VREF (V)**<br>~~a~~<br>~~es~~<br>~~eeeeee~~|**VREF (V)**<br>~~a~~<br>~~es~~<br>~~eeeeee~~|**VREF (V)**<br>~~a~~<br>~~es~~<br>~~eeeeee~~|
|---|---|---|---|---|---|---|
||**Min.**<br>~~es~~|**Typ.**<br>~~es~~|**Max.**<br>~~es~~<br>~~ee~~|**Min.**<br>~~es~~<br>~~eee~~|**Typ.**<br>~~es~~<br>~~eee~~|**Max.**<br>~~es~~<br>~~eee~~|
|LVCMOS15R33<br>~~es~~<br>~~a~~|3.135<br>~~es~~|3.3<br>~~es~~|3.6<br>~~es~~<br>~~ee~~|0.6<br>~~es~~<br>~~eee~~|0.75<br>~~es~~<br>~~eee~~|0.9<br>~~es~~<br>~~eee~~|
|LVCMOS15R25<br>~~a~~<br>~~a a~~<br>~~ee~~|2.375<br>~~a~~|2.5<br>~~a~~|2.625<br>~~ee ~~<br>~~a~~|0.6<br> ~~eee~~<br>~~a~~|0.75<br>~~eee ~~<br>~~a~~|0.9<br> ~~eee~~<br>~~a~~|
|LVCMOS12R33<br>~~a a~~<br>~~ee~~<br>~~ee~~|3.135<br>~~a~~<br>|3.3<br>~~a~~<br>|3.6<br>~~a~~<br>|0.45<br>~~a~~<br>|0.6<br>~~a~~<br>|0.75<br>~~a~~<br>|
|LVCMOS12R25<br>~~ee~~<br>~~ee~~|2.375<br>|2.5<br>|2.625<br>|0.45<br>|0.6<br>|0.75<br>|
|LVCMOS10R33<br>~~eea~~|3.135<br>~~a~~|3.3<br>~~a~~|3.6<br>~~a~~|0.35<br>~~a~~|0.5<br>~~a~~|0.65<br>~~a~~|
|LVCMOS10R25<br>~~a~~<br>~~a~~|2.375<br>~~a~~<br>~~a~~|2.5<br>~~a~~<br>~~a~~|2.625<br>~~a~~<br>~~a~~|0.35<br>~~a~~<br>~~a~~|0.5<br>~~a~~<br>~~a~~|0.65<br>~~a~~<br>~~a~~|



## **Notes:** 

1. Inputs on-chip. Outputs are implemented with the addition of external resistors. 

2. For the dedicated LVDS buffers. 

3. Requires the addition of external resistors. 

## **3.12. sysI/O Single-Ended DC Electrical Characteristics** 

**Table 3.11. sysI/O Single-Ended DC Electrical Charateristics[1, 2, 4]** 

|**Standard**<br>~~eres~~|**VIL**<br>~~ee~~<br>~~eres~~|**VIL**<br>~~ee~~<br>~~eres~~|**VIH**<br>~~ee~~<br>~~eres~~|**VIH**<br>~~ee~~<br>~~eres~~|**VOL Max.**<br>**(V)**<br>~~eres~~|**VOH Min.**<br>**(V)**<br>~~eres~~|**IOL Max.5**<br>**(mA)**<br>~~eres~~|**IOH Max.5 **<br>**(mA)**<br>~~eres~~|
|---|---|---|---|---|---|---|---|---|
||**Min.(V)3**<br>~~ee~~<br>~~eres~~|**Max.(V)**<br>~~ee~~<br>~~eres~~|**Min.(V)**<br>~~ee~~<br>~~eres~~|**Max.(V)**<br>~~ee~~<br>~~eres~~|||||
|LVCMOS 3.3<br>LVTTL<br>~~eres~~|–0.3<br>~~eres~~|0.8<br>~~eres~~|2.0<br>~~eres~~|3.6<br>~~eres~~|0.4<br>~~eres~~<br>~~ee~~|VCCIO – 0.4<br>~~eres~~|4<br>~~eres~~<br>~~a~~|–4<br>~~eres~~<br>~~a~~|
||||||||8<br>~~a~~<br>~~7~~|–8<br>~~a~~<br>~~7~~|
||||||||12<br>~~7~~<br>~~7~~|–12<br>~~7~~<br>~~7~~|
||||||||16<br>~~7~~<br>~~7~~<br>~~———~~|–16<br>~~7~~<br>~~7~~<br>~~———~~|
||||||0.2<br>~~ee~~|VCCIO – 0.2 0.1|VCCIO – 0.2 0.1<br>~~7~~<br>~~———~~|–0.1<br>~~7~~<br>~~———~~|
|LVCMOS 2.5|–0.3|0.7|1.7|3.6|0.4<br>~~ee~~|VCCIO – 0.4|4<br>~~———~~|–4<br>~~———~~|
||||||||8<br>~~———~~<br>~~——)—~~|–8<br>~~———~~<br>~~——)—~~|
||||||||12<br>~~——)—~~<br>~~7~~|–12<br>~~——)—~~<br>~~7~~|
||||||0.2<br>~~—~~|VCCIO – 0.2 0.1|VCCIO – 0.2 0.1<br>~~7~~|–0.1<br>~~7~~|
|LVCMOS 1.8|–0.3|0.35<br>VCCIO|0.65 VCCIO|3.6|0.4<br>~~—~~<br>~~ee~~|VCCIO – 0.4|4<br>~~7~~|–4<br>~~7~~|
||||||||8<br>~~7~~<br>~~7~~|–8<br>~~7~~<br>~~7~~|
||||||||12<br>~~7~~<br>~~——T—~~|–12<br>~~7~~<br>~~——T—~~|
||||||0.2<br>~~ee~~|VCCIO – 0.2 0.1|VCCIO – 0.2 0.1<br>~~——T—~~|–0.1<br>~~——T—~~|
|LVCMOS 1.5|–0.3|0.35<br>VCCIO|0.65 VCCIO|3.6|0.4<br>~~ee~~<br>~~J~~|VCCIO – 0.4<br>~~SE~~|4<br>~~——T—~~|–4<br>~~——T—~~|
||||||||8<br>~~SE~~|–8<br>~~SE~~|
||||||0.2<br>~~J~~|VCCIO – 0.2 0.1<br>~~SE~~|VCCIO – 0.2 0.1<br>~~SE~~|–0.1<br>~~SE~~|
|LVCMOS 1.2|–0.3|0.35<br>VCCIO|0.65 VCCIO|3.6|0.4<br>~~J~~<br>~~ee~~|VCCIO – 0.4<br>~~SE~~|4<br>~~SE~~|–2<br>~~SE~~|
||||||||8<br>~~SE~~|–6<br>~~SE~~|
||||||0.2<br>~~ee~~|VCCIO – 0.2 0.1|VCCIO – 0.2 0.1|–0.1|
|LVCMOS25R33<br>~~a~~|–0.3<br>~~a~~|VREF – 0.1 VREF+0.1<br>~~a~~|VREF – 0.1 VREF+0.1<br>~~a~~|3.6<br>~~a~~|NA<br>~~ee~~<br>~~a~~|NA<br>~~a~~|NA<br>~~a~~|NA<br>~~a~~|
|LVCMOS18R33<br>~~a~~<br>~~a~~|–0.3<br>~~a~~<br>~~a~~|VREF – 0.1 VREF+0.1<br>~~a~~<br>~~a~~|VREF – 0.1 VREF+0.1<br>~~a~~<br>~~a~~|3.6<br>~~a~~<br>~~a~~|NA<br>~~a~~<br>~~a~~|NA<br>~~a~~<br>~~a~~|NA<br>~~a~~<br>~~a~~|NA<br>~~a~~<br>~~a~~|
|LVCMOS18R25<br>~~a~~<br>~~a~~|–0.3<br>~~a~~<br>~~a~~|VREF – 0.1 VREF+0.1<br>~~a~~<br>~~a~~|VREF – 0.1 VREF+0.1<br>~~a~~<br>~~a~~|3.6<br>~~a~~<br>~~a~~|NA<br>~~a~~<br>~~a~~|NA<br>~~a~~<br>~~a~~|NA<br>~~a~~<br>~~a~~|NA<br>~~a~~<br>~~a~~|
|LVCMOS15R33<br>~~a~~<br>~~a~~|–0.3<br>~~a~~<br>~~a~~|VREF – 0.1 VREF+0.1<br>~~a~~<br>~~a~~|VREF – 0.1 VREF+0.1<br>~~a~~<br>~~a~~|3.6<br>~~a~~<br>~~a~~|NA<br>~~a~~<br>~~a~~|NA<br>~~a~~<br>~~a~~|NA<br>~~a~~<br>~~a~~|NA<br>~~a~~<br>~~a~~|
|LVCMOS15R25<br>~~a~~<br>~~a~~<br>~~a~~|–0.3<br>~~a~~<br>~~a~~<br>|VREF – 0.1 VREF+0.1<br>~~a~~<br>~~a~~<br>|VREF – 0.1 VREF+0.1<br>~~a~~<br>~~a~~<br>|3.6<br>~~a~~<br>~~a~~<br>|NA<br>~~a~~<br>~~a~~<br>~~ee~~<br>|NA<br>~~a~~<br>~~a~~<br>~~ee~~<br>|NA<br>~~a~~<br>~~a~~<br>~~ee~~<br>|NA<br>~~a~~<br>~~a~~<br>~~ee~~<br>|
|LVCMOS12R33<br>~~a~~<br>~~a~~<br>~~a~~<br>~~a~~|–0.3<br>~~a~~<br>~~a~~<br>~~ee~~<br>~~ee~~<br>|VREF – 0.1 VREF+0.1<br>~~a~~<br>~~a~~<br>~~ee~~<br>~~ee~~<br>|VREF – 0.1 VREF+0.1<br>~~a~~<br>~~a~~<br>~~ee~~<br>~~ee~~<br>|3.6<br>~~a~~<br>~~a~~<br>~~ee~~<br>~~ee~~<br>|0.40<br>~~a~~<br>~~a~~<br>~~ee~~<br>~~ee~~<br>~~**e**~~|NA Open<br>Drain<br>~~a~~<br>~~a~~<br>~~ee~~<br>~~ee~~<br>~~**e**e~~|24, 16, 12,<br>8,4<br>~~a~~<br>~~a~~<br>~~ee~~<br>~~ee~~<br>~~e~~|NA Open<br>Drain<br>~~a~~<br>~~a~~<br>~~ee~~<br>~~ee~~<br>~~e~~|
|LVCMOS12R25<br>~~a~~<br>~~a~~<br>~~a~~|–0.3<br>~~a~~<br>~~ee~~<br>~~ee~~<br>|VREF – 0.1 VREF+0.1<br>~~a~~<br>~~ee~~<br>~~ee~~<br>|VREF – 0.1 VREF+0.1<br>~~a~~<br>~~ee~~<br>~~ee~~<br>|3.6<br>~~a~~<br>~~ee~~<br>~~ee~~<br>|0.40<br>~~a~~<br>~~ee~~<br>~~ee~~<br>~~**e**~~|NA Open<br>Drain<br>~~a~~<br>~~ee~~<br>~~ee~~<br>~~**e**e~~|16, 12, 8, 4<br>~~a~~<br>~~ee~~<br>~~ee~~<br>~~e~~|NA Open<br>Drain<br>~~a~~<br>~~ee~~<br>~~ee~~<br>~~e~~|
|LVCMOS10R33<br>~~a ~~<br>~~a e~~|–0.3<br> ~~ee~~<br>~~e~~|VREF – 0.1 VREF+0.1<br>~~ee~~<br>~~e~~|VREF – 0.1 VREF+0.1<br>~~ee~~<br>~~e~~|3.6<br>~~ee~~<br>~~e~~|0.40<br>~~ee~~<br>~~**e**~~|NA Open<br>Drain<br>~~ee ~~<br>~~**e**e~~|24, 16, 12,<br>8,4<br> ~~ee~~<br>~~e~~|NA Open<br>Drain<br>~~ee~~<br>~~e~~|



© 2025 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02125-1.0 

51 

**MachXO4 Family Data Sheet** 

|**Standard**|**VIL**|**VIL**|**VIH**|**VIH**|**VOL Max.**<br>**(V)**|**VOH Min.**<br>**(V)**|**IOL Max.5**<br>**(mA)**|**IOH Max.5 **<br>**(mA)**|
|---|---|---|---|---|---|---|---|---|
||**Min.(V)3**|**Max.(V)**|**Min.(V)**|**Max.(V)**|||||
|LVCMOS10R25|-0.3|VREF – 0.1 VREF+0.1|VREF – 0.1 VREF+0.1|3.6|0.40|NA Open<br>Drain|16, 12, 8, 4|NA Open<br>Drain|



**Notes:** 

1. MachXO4 devices allow LVCMOS inputs to be placed in I/O banks where VCCIO is different from what is specified in the applicable JEDEC specification. This is referred to as a ratioed input buffer. In a majority of cases this operation follows or exceeds the applicable JEDEC specification. The cases where MachXO4 devices do not meet the relevant JEDEC specification are documented in the table below. 

2. MachXO4 devices allow for LVCMOS referenced I/O, which follow applicable JEDEC specifications. For more details about mixed mode operation please refer to MachXO4 sysI/O User Guide (FPGA-TN-02398). 

3. The dual function I2C pins SCL and SDA are limited to a VIL min of –0.25 V or to –0.3 V with a duration of <10 ns. 

4. For I/O with mixed voltage support, VOH follows respective sysI/O bank VCCIO supply voltage, and VIL / VIH follows the I/O signaling standard. 

5. For electromigration, the average DC current sourced or sinked by I/O pads between two consecutive VCCIO or GND pad connections, or between the last VCCIO or GND in an I/O bank and the end of an I/O bank, shall not exceed a maximum of n * 8 mA. “n” is the number of I/O pads between the two consecutive bank VCCIO or GND connections or between the last VCCIO and GND in a bank and the end of a bank. I/O Grouping can be found in the Data Sheet Pin Tables, which can also be generated from the Lattice Radiant software. 

## **3.13. sysI/O Differential Electrical Characteristics** 

The LVDS differential output buffers are available on the top side of the MachXO4 PLD family. 

## **3.13.1. LVDS** 

Over recommended operating conditions. 

**Table 3.12. LVDS** 

|**Parameter Symbol**<br>~~PO~~<br>~~os~~|**Parameter Description**<br>~~PO~~<br>~~——————e~~|**Test Condition**<br>~~PO~~<br>~~——————e~~|**Min.**<br>~~PO~~<br>~~——————e~~|**Typ. **<br>~~PO~~<br>~~——————e~~|**Max.**<br>~~PO~~<br>~~——————e~~|**Unit**<br>~~PO~~|
|---|---|---|---|---|---|---|
|VINP, VINM<br>~~PO~~<br>~~os~~<br>~~Sa~~|Input Voltage<br>(Commercial/Industrial)<br>~~PO~~<br>~~——————e~~|VCCIO= 3.3 V<br>~~PO~~<br>~~——————e~~|0<br>~~PO~~<br>~~——————e~~|—<br>~~PO~~<br>~~——————e~~|2.605<br>~~PO~~<br>~~——————e~~|V<br>~~PO~~|
|||VCCIO= 2.5 V<br>~~——————e~~|0<br>~~——————e~~|—<br>~~——————e~~|2.05<br>~~——————e~~|V|
||Input Voltage<br>(Automotive)<br>~~——————e~~<br>~~ooo~~|VCCIO= 3.3 V<br>~~——————e~~<br>~~ooo~~|0<br>~~——————e~~<br>~~ooo~~<br>~~es es~~|—<br>~~——————e~~<br>~~ooo~~<br>~~es ee~~|2.6<br>~~——————e~~<br>~~ooo~~<br>~~ee~~|V<br>~~ooo~~|
|||VCCIO= 2.5 V<br>~~——————e~~<br>~~es es~~<br>~~ooo~~<br>~~ee~~|0<br>~~——————e~~<br>~~es~~<br>~~ooo~~<br>~~ee~~<br>~~es es~~|—<br>~~——————e~~<br>~~ooo~~<br>~~ee~~<br>~~es ee~~|2.0<br>~~——————e~~<br>~~ooo~~<br>~~ee~~<br>~~ee~~|V<br>~~ooo~~<br>~~ee~~|
|VTHD<br>~~os~~<br>~~Sa~~|Differential Input Threshold<br>~~——————e~~<br>~~ooo~~|—<br>~~——————e~~<br>~~es es~~<br>~~ooo~~<br>~~ee~~|±100<br>~~——————e~~<br>~~es~~<br>~~ooo~~<br>~~ee~~<br>~~es es~~|—<br>~~——————e~~<br>~~ooo~~<br>~~ee~~<br>~~es ee~~|—<br>~~——————e~~<br>~~ooo~~<br>~~ee~~<br>~~ee~~|mV<br>~~ooo~~<br>~~ee~~|
|VCM<br>~~Sa~~<br>~~ree~~|Input Common Mode Voltage<br>~~ree~~|VCCIO= 3.3 V<br>~~es es~~<br>~~ree~~|0.05<br>~~es~~<br>~~es es~~<br>~~ree~~|—<br>~~es ee~~<br>~~ree~~|2.6<br>~~ee~~<br>~~ree~~|V<br>~~ree~~|
|||VCCIO= 2.5 V<br>~~ree~~|0.05<br>~~es es~~<br>~~ree~~|—<br>~~es ee~~<br>~~ree~~|2.0<br>~~ee~~<br>~~ree~~|V<br>~~ree~~|
|IIN<br>~~ree~~<br>~~**e**~~<br>~~s~~|Input current<br>~~ree~~<br>~~**e**e~~<br>~~rs~~|Power on<br>~~ree~~<br>~~e~~|—<br>~~ree~~<br>~~e~~|—<br>~~ree~~<br>~~e~~|±10<br>~~ree~~<br>~~e~~|µA<br>~~ree~~|
|VOH<br>~~**e**~~<br>~~s~~<br>~~re~~|Output high voltage for VOPor VOM<br>~~**e**e~~<br>~~rs~~<br>~~er~~|RT= 100 Ω<br>~~e~~<br>~~er~~|—<br>~~e~~<br>~~er~~|1.375<br>~~e~~<br>~~er~~|—<br>~~e~~<br>~~er~~|V<br>~~er~~|
|VOL<br>~~**e**~~<br>~~s~~<br>~~re~~<br>~~re~~|Output low voltage for VOPor VOM<br>~~**e**e~~<br>~~rs~~<br>~~er~~<br>~~er~~|RT= 100 Ω<br>~~e~~<br>~~er~~<br>~~er~~|0.90<br>~~e~~<br>~~er~~<br>~~er~~|1.025<br>~~e~~<br>~~er~~<br>~~er~~|—<br>~~e~~<br>~~er~~<br>~~er~~|V<br>~~er~~<br>~~er~~|
|VOD<br>~~re~~<br>~~re~~<br>~~es~~|Output voltage differential<br>~~er~~<br>~~er~~<br>|(VOP- VOM),RT= 100 Ω<br>~~er~~<br>~~er~~<br>|250<br>~~er~~<br>~~er~~<br>|350<br>~~er~~<br>~~er~~<br>|450<br>~~er~~<br>~~er~~<br>|mV<br>~~er~~<br>~~er~~<br>|
|VOD<br>~~re~~<br>~~esee~~|Change in VODbetween high and low<br>~~er~~<br>~~ee~~|—<br>~~er~~<br>~~ee~~|—<br>~~er~~<br>~~ee~~|—<br>~~er~~<br>~~ee~~|50<br>~~er~~<br>~~ee~~|mV<br>~~er~~<br>~~ee~~|
|VOS<br>~~esee~~<br>~~ss~~<br>~~a~~|Output voltage offset<br>(Commercial/Industrial)<br>~~ee~~<br>~~ss~~|(VOP- VOM)/2, RT= 100 Ω<br>~~ee~~<br>~~ee~~<br>|1.125<br>~~ee~~<br>~~ee~~<br>|1.20<br>~~ee~~<br>~~ee~~|1.395<br>~~ee~~|V<br>~~ee~~|
||Output voltage offset<br>(Automotive)<br>~~ee~~<br>~~ee~~<br>~~ss~~<br>|(VOP- VOM)/2, RT= 100 Ω<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~QUO~~<br>|1.10<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~QUO~~<br>|1.20<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>|1.395<br>~~ee~~<br>~~ee~~<br>|V<br>~~ee~~<br>~~ee~~<br>|
|VOS<br>~~ee~~<br>~~ss~~<br>~~a~~|Change in VOSbetween H and L<br>~~ee ~~<br>~~ee~~<br>~~ss~~<br>|—<br> ~~ee~~<br>~~ee~~<br>~~ee~~<br>~~QUO~~<br>|—<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~QUO~~<br>|—<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>|50<br>~~ee~~<br>~~ee~~<br>|mV<br>~~ee~~<br>~~ee~~<br>|
|IOSD<br>~~ss~~<br>~~a~~|Output short circuit current<br>~~ss~~<br>~~ee~~|VOD= 0 V driver outputs<br>shorted<br>~~ee~~<br>~~QUO~~<br>~~ee~~|—<br>~~ee~~<br>~~QUO~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~|24<br>~~ee~~|mA<br>~~ee~~|



52 

**MachXO4 Family Data Sheet** 

## **3.13.2. LVDS Emulation** 

MachXO4 devices can support LVDS outputs via emulation (LVDS25E). The output is emulated using complementary LVCMOS outputs in conjunction with resistors across the driver outputs on all devices. The scheme shown in Figure 3.1 is one possible solution for LVDS standard implementation. Resistor values in Figure 3.1 are industry standard values for 1% resistors. 

**==> picture [340 x 139] intentionally omitted <==**

**----- Start of picture text -----**<br>
VCCIO = 2.5<br>158<br>8mA<br>Zo = 100<br>+<br>VCCIO = 2.5  158 140 100 –<br>8mA<br>On-chip Off-chip Off-chip On-chip<br>Emulated<br>LVDS<br>Buffer<br>**----- End of picture text -----**<br>


**==> picture [84 x 6] intentionally omitted <==**

**----- Start of picture text -----**<br>
Note: All resistors are ±1%.<br>**----- End of picture text -----**<br>


**Figure 3.1. LVDS Using External Resistors (LVDS25E)** 

Over recommended operating conditions. 

**Table 3.13. LVDS25E DC Conditions** 

|**Parameter**|**Description**|**Typ. **|**Unit**|
|---|---|---|---|
|ZOUT|Output impedance|20|Ω|
|RS|Driver series resistor|158|Ω|
|RP|Driverparallel resistor|140|Ω|
|RT|Receiver termination|100|Ω|
|VOH|Output high voltage|1.43|V|
|VOL|Output low voltage|1.07|V|
|VOD|Output differential voltage|0.35|V|
|VCM|Output common mode voltage|1.25|V|
|ZBACK|Back impedance|100.5|Ω|
|IDC|DC output current|6.03|mA|



## **3.13.3. BLVDS** 

The MachXO4 family supports the BLVDS standard through emulation. The output is emulated using complementary LVCMOS outputs in conjunction with resistors across the driver outputs. The input standard is supported by the LVDS differential input buffer. BLVDS is intended for use when multi-drop and bi-directional multi-point differential signaling is required. The scheme shown in Figure 3.2 is one possible solution for bi-directional multi-point differential signals. 

© 2025 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02125-1.0 

53 

**==> picture [459 x 301] intentionally omitted <==**

**----- Start of picture text -----**<br>
MachXO4 Family<br>Data Sheet<br>Heavily loaded backplane, effective Zo ~ 45 to 90   differential<br>2.5 V 2.5 V<br>80 45-90    45-90<br>16 mA 16 mA<br>80<br>2.5 V 2.5 V<br>80<br>16 mA 16 mA<br>80 80 80 80<br>.  . .<br>– –<br>eso f<br>– –<br>2.5 V 2.5 V 2.5 V 2.5 V<br>16 mA 16 mA 16 mA 16 mA<br>KA Y AL Y<br>Figure 3.2. BLVDS Multi-point-Output Example<br>Over recommended operating conditions.<br>+ +<br>+ +<br>**----- End of picture text -----**<br>


**Table 3.14. BLVDS DC Condition** 

**Nominal Symbol Description Unit Zo = 45 Zo = 90** ZOUT Output impedance 20 20 Ω RS Driver series resistance 80 80 Ω RTLEFT Left end termination 45 90 Ω RTRIGHT Right end termination 45 90 Ω VOH Output high voltage 1.376 1.480 V VOL Output low voltage 1.124 1.020 V VOD Output differential voltage 0.253 0.459 V ~~Ce Ce[oo]~~ VCM Output common mode voltage ~~oo~~ 1.250 1.250 V IDC DC output current 11.236 10.204 mA ~~Ce~~ 

**Note:** For input buffer, see LVDS table. 

## **3.13.4. LVPECL** 

The MachXO4 family supports the differential LVPECL standard through emulation. This output standard is emulated using complementary LVCMOS outputs in conjunction with resistors across the driver outputs on all the devices. The LVPECL input standard is supported by the LVDS differential input buffer. The scheme shown in Differential LVPECL is one possible solution for point-to-point signals. 

© 2025 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

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**MachXO4 Family Data Sheet** 

**==> picture [357 x 139] intentionally omitted <==**

**----- Start of picture text -----**<br>
V CCIO  = 3.3 V<br>|I<br>93<br>16 mA<br>a" a"<br>> V CCIO  = 3.3 V | I +<br>196    100<br>–<br>93<br>16 mA<br>Transmission line, Zo = 100    differential<br>| I<br>On-chip Off-chip  Off-chip  On-chip<br><—__ |____> <—__ _|__><br>**----- End of picture text -----**<br>


**Figure 3.3. Differential LVPECL** 

Over recommended operating conditions. 

**Table 3.15. LVPECL DC Conditions** 

|**Symbol**|**Description**|**Nominal**|**Unit**|
|---|---|---|---|
|ZOUT|Output impedance|20||
|RS|Driver series resistor|93||
|RP|Driverparallel resistor|196||
|RT|Receiver termination|100||
|VOH|Output high voltage|2.05|V|
|VOL|Output low voltage|1.25|V|
|VOD|Output differential voltage|0.80|V|
|VCM|Output common mode voltage|1.65|V|
|ZBACK|Back impedance|100.5||
|IDC|DC output current|12.11|mA|



**Note** : For input buffer, see LVDS table. 

For further information on LVPECL, BLVDS and other differential interfaces, see details of additional technical documentation at the end of the data sheet. 

## **3.13.5. MIPI D-PHY Emulation** 

MachXO4 devices can support MIPI D-PHY unidirectional HS (High Speed) and bidirectional LP (Low Power) inputs and outputs via emulation. In conjunction with external resistors High Speed I/O use the LVDS25E buffer and Low Power I/O use the LVCMOS buffers. The scheme shown in Figure 3.4 is one possible solution for MIPI D-PHY Receiver implementation. The scheme shown in Figure 3.5 is one possible solution for MIPI D-PHY Transmitter implementation. 

© 2025 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

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**MachXO4 Family Data Sheet** 

**==> picture [149 x 279] intentionally omitted <==**

**----- Start of picture text -----**<br>
| MIPI D-PHY Input<br>|<br>|<br>| LVCMOS<br>|<br>|<br>LVCMOS<br>|<br>|<br>|<br>|<br>Dp<br>| LVDS<br>Dn<br>|<br>|<br>|<br>|<br>| LVCMOS<br>|<br>| LVCMOS<br>RT<br>RT<br>**----- End of picture text -----**<br>


**Figure 3.4. MIPI D-PHY Input Using External Resistors** 

Over recommended operating conditions. 

**Table 3.16. MIPI DC Conditions** 

|**Symbol**<br>~~a~~|**Description**|**Min.**|**Typ. **|**Max.**|**Unit**|
|---|---|---|---|---|---|
|**Receiver**<br>~~a~~||||||
|**External Termination**<br>~~eee~~||||||
|RT<br>~~a~~|1% external resistor with VCCIO=2.5 V<br>~~eee~~|—<br>~~eee~~|50<br>~~eee~~|—<br>~~eee~~|Ω<br>~~eee~~|
||1% external resistor with VCCIO=3.3 V<br>~~eee~~<br>~~pT~~|—<br>~~eee~~<br>~~pT~~|50<br>~~eee~~<br>~~pT~~|—<br>~~eee~~<br>~~pT~~|Ω<br>~~eee~~<br>~~pT~~|
|**High Speed**<br>~~eee~~<br>~~eeeeee~~||||||
|VCCIO<br>~~ee~~|VCCIOof the Bank with LVDS Emulated input buffer<br>~~ee~~|—<br>~~ee~~|2.5<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~|V<br>~~ee~~<br>~~ee~~|
||VCCIOof the Bank with LVDS Emulated input buffer<br>~~ee~~<br>~~a~~|—<br>~~ee~~<br>~~a~~|3.3<br>~~ee~~<br>~~ee~~<br>~~a~~|—<br>~~ee~~<br>~~ee~~<br>~~a~~<br>~~CO~~|V<br>~~ee~~<br>~~ee~~<br>~~a~~|
|VCMRX<br>~~ee~~<br>~~GG~~|Common-mode voltage HS receive mode<br>~~ee~~<br>~~a~~<br>~~GG~~|150<br>~~ee~~<br>~~a~~<br>~~GG~~|200<br>~~ee~~<br>~~ee ~~<br>~~a~~<br>~~GG~~|250<br>~~ee~~<br> ~~ee ~~<br>~~a~~<br>~~GG~~<br>~~CO~~<br>~~CO~~|mV<br>~~ee~~<br> ~~ee~~<br>~~a~~<br>~~GG~~|
|VIDTH<br>~~eG~~|Differential input high threshold<br>~~eG~~|—<br>~~eG~~|—<br>~~eG~~|100<br>~~CO~~<br>~~eG~~<br>~~CO~~<br>~~CO~~|mV<br>~~eG~~|
|VIDTL<br>~~eG~~|Differential input low threshold<br>~~eG~~|–100<br>~~eG~~|—<br>~~eG~~|—<br>~~CO~~<br>~~eG~~<br>~~CO~~|mV<br>~~eG~~|
|VIHHS<br>~~GO~~|Single-ended input high voltage<br>~~GO~~|—<br>~~GO~~|—<br>~~GO~~|400<br>~~CO~~<br>~~GO~~|mV<br>~~GO~~|
|VILHS<br>~~GO~~<br>~~CG~~|Single-ended input low voltage<br>~~GO~~<br>~~CG~~|0<br>~~GO~~<br>~~CG~~|—<br>~~GO~~<br>~~CG~~|—<br>~~GO~~<br>~~CG~~|mV<br>~~GO~~<br>~~CG~~|
|ZID<br>~~CG~~<br>~~GG~~|Differential input impedance<br>~~CG~~<br>~~GG~~|80<br>~~CG~~<br>~~GG~~|100<br>~~CG~~<br>~~GG~~|120<br>~~CG~~<br>~~GG~~|Ω<br>~~CG~~<br>~~GG~~|
|**Low Power**||||||
|VCCIO|VCCIOof the Bank with LVCMOS12D 6 mA drive<br>bidirectional I/O buffer|—|1.2|—|V|
|VIH<br>~~Ce~~|Logic 1 input voltage<br>~~Ce~~|—<br>~~GO~~|—<br>~~GO~~|0.88<br>~~GO~~|V|
|VIL<br>~~GG~~|Logic 0 input voltage, not in ULP State<br>~~GG~~|0.55<br>~~GG~~|—<br>~~GG~~|—<br>~~GG~~|V<br>~~GG~~|
|VHYST<br>~~GG~~<br>~~eG~~|Input hysteresis<br>~~GG~~<br>~~eG~~|25<br>~~GG~~<br>~~eG~~|—<br>~~GG~~<br>~~eG~~|—<br>~~GG~~<br>~~eG~~|mV<br>~~GG~~<br>~~eG~~|



© 2025 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. 

All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

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**MachXO4 Family Data Sheet** 

**==> picture [196 x 273] intentionally omitted <==**

**----- Start of picture text -----**<br>
MIPI D-PHY Output<br>|<br>|<br>|<br>LVCMOS<br>|<br>RL<br>LVCMOS<br>|<br>|<br>|<br>RH Dp<br>LVDS<br>|<br>RH Dn<br>|<br>|<br>LVCMOS<br>RL<br>LVCMOS<br>Bol<br>**----- End of picture text -----**<br>


**Figure 3.5. MIPI D-PHY Output Using External Resistors** 

© 2025 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

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**MachXO4 Family Data Sheet** 

Over recommended operating conditions. 

**Table 3.17. MIPI D-PHY Output DC Conditions** 

|**Symbol**<br>~~se~~|**Description**<br>~~se~~|**Min.**<br>~~se~~|**Typ. **<br>~~se~~|**Max.**<br>~~se~~|**Unit**<br>~~se~~|
|---|---|---|---|---|---|
|**Transmitter**<br>~~Rn~~||||||
|**External Termination**<br>~~CR~~<br>~~ee esee~~||||||
|RL<br>~~ee es~~<br>~~pf~~|1% external resistor with VCCIO= 2.5 V<br>~~es~~|—<br>~~ee~~|50|—|Ω|
||1% external resistor with VCCIO= 3.3 V<br>~~es~~<br>~~pf——}~~|—<br>~~ee~~<br>~~ee~~<br>~~——}+}~~|50<br>~~ee~~<br>~~+}~~|—<br>~~{—~~|~~{—~~|
|RH<br>~~ee es~~<br>~~pf~~|1% external resistor with performance up to 800<br>Mbps or with performance up 900 Mbps when<br>VCCIO= 2.5 V<br>~~es ~~<br>~~ee~~<br>~~pf——}~~|—<br> ~~ee~~<br>~~ee~~<br>~~ee~~<br>~~——}+}~~|330<br>~~ee~~<br>~~ee~~<br>~~+}~~|—<br>~~ee~~<br>~~{—~~|Ω<br>~~ee~~<br>~~{—~~|
||1% external resistor with performance between<br>800 Mbps to 900 Mbps when VCCIO= 3.3 V<br>~~pf——}~~|—<br>~~ee~~<br>~~——}+}~~|464<br>~~ee~~<br>~~+}~~|—<br>~~{—~~|Ω<br>~~{—~~|
|**High Speed**<br>~~ee~~<br>~~pf ——} +} {—~~<br>~~Ce~~||||||
|VCCIO<br>~~a~~<br>~~es~~|VCCIOof the Bank with LVDS Emulated output<br>buffer<br>~~ee~~|—<br>~~ee~~<br>~~ee~~|2.5<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~|V<br>~~ee~~|
||VCCIOof the Bank with LVDS Emulated output<br>buffer<br>~~ee~~|—<br>~~ee~~<br>~~ee~~|3.3<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~|V<br>~~ee~~|
|VCMTX<br>~~a~~<br>~~es~~<br>~~I~~|HS transmit static common mode voltage<br>~~ee~~<br>|150<br>~~ee~~<br>~~ee~~<br>|200<br>~~ee~~<br>~~ee~~<br>|250<br>~~ee~~<br>~~ee~~<br>|mV<br>~~ee~~<br>|
|VOD<br>~~es~~<br>~~I~~|HS transmit differential voltage<br>|140<br>~~ee~~<br>|200<br>~~ee~~<br>|270<br>~~ee~~<br>|mV<br>|
|VOHHS<br>~~IGe~~|HS output high voltage<br>~~Ge~~|—<br>~~Ge~~|—<br>~~Ge~~|360<br>~~Ge~~|mV<br>~~Ge~~|
|ZOS<br>~~Ge~~<br>~~se~~|Single ended output impedance<br>~~Ge~~<br>~~se~~|—<br>~~Ge~~<br>~~se~~|50<br>~~Ge~~<br>~~se~~|—<br>~~Ge~~<br>~~se~~|Ω<br>~~Ge~~<br>~~se~~|
|ZOS<br>~~se~~<br>~~i~~<br>~~Ce~~|Single ended output impedance mismatch<br>~~se~~<br>~~es~~<br>|—<br>~~se~~<br>~~es~~<br>|—<br>~~se~~<br>~~es~~<br>|10<br>~~se~~<br>~~es~~<br>|%<br>~~se~~<br>~~es~~<br>|
|**Low Power**<br>~~ies~~<br>~~Ce~~<br>~~ee ee~~<br>~~I~~||||||
|VCCIO<br>~~Cea ee~~<br>~~I~~|VCCIOof the Bank with LVCMOS12D 6 mA drive<br>bidirectional I/O buffer<br>~~ee~~|—<br>~~ee~~<br>~~ee ee~~|1.2<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~|V<br>~~ee~~|
|VOH<br>~~I~~<br>~~I~~|Output high level<br>|1.1<br>~~ee ee~~<br>|1.2<br>~~ee~~<br>|1.3<br>~~ee~~<br>|V<br>|
|VOL<br>~~I~~<br>~~I~~|Output low level<br>|–50<br>~~ee ee~~<br>|0<br>~~ee~~<br>|50<br>~~ee~~<br>|mV<br>|
|ZOLP<br>~~IDe~~|Output impedance of LP transmitter<br>~~De~~|110<br>~~De~~|—<br>~~De~~|—<br>~~De~~|Ω<br>~~De~~|



## **3.13.6. Comparator Function** 

MachXO4 devices can support a limited comparator function using the 3.3 V referenced input buffers. The scheme is shown in Figure 3.6. 

**==> picture [184 x 141] intentionally omitted <==**

**----- Start of picture text -----**<br>
VREF<br>|<br>LVCMOSxxR33<br>|<br>+<br>–<br>|<br>|<br><+<—_ Off-chip  __!—_» On-chip<br>**----- End of picture text -----**<br>


**Figure 3.6. Comparator Function Using Referenced Input Buffers** 

© 2025 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02125-1.0 

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**MachXO4 Family Data Sheet** 

Over recommended operating conditions. 

**Table 3.18. Comparator Specifications[1]** 

|**Parameter**<br>~~oj~~|**Description**<br>~~oj~~<br>~~|~~|**Test Condition**|**–6/–5**<br>**(Commercial/Industrial)**|**–6/–5**<br>**(Commercial/Industrial)**|**–5**<br>**(Automotive)**|**–5**<br>**(Automotive)**|**Unit**|
|---|---|---|---|---|---|---|---|
||||**Min.**|**Max.**|**Min.**|**Max.**||
|VIH<br>~~oj~~<br>~~rr~~<br>~~ae~~|Single-Ended input<br>~~oj~~<br>~~|~~<br>~~rr~~<br>~~ae~~<br>~~Ge~~|VCCIO= 3.3 V<br>~~rr~~|VREF+ 0.1<br>~~rr~~<br>~~ee~~|3.6<br>~~rr~~<br>~~ee~~|VREF+ 0.1<br>~~rr~~<br>~~ee~~|3.6<br>~~rr~~<br>~~ee~~|V<br>~~rr~~|
|VIL<br>~~oj~~<br>~~rr~~<br>~~ae~~<br>~~es~~|||–0.3<br>~~rr~~<br>~~ee~~|VREF– 0.1<br>~~rr~~<br>~~ee~~|–0.3<br>~~rr~~<br>~~ee~~|VREF– 0.1<br>~~rr~~<br>~~ee~~||
|Vref<br>~~ae~~<br>~~es~~<br>~~es~~|Voltage Ref input<br>~~ae~~<br>~~Ge~~<br>~~Ge~~|VCCIO= 3.3 V|0.05<br>~~ee~~|2.605<br>~~ee~~|0.05<br>~~ee~~|2.605<br>~~ee~~|V|
|tW_PRI<br>~~es~~<br>~~es~~|Propagation Delay<br>~~Ge~~<br>~~Ge~~|VCCIO= 3.3 V|—|10|—|10|ns|
|VOS<br>~~es~~<br>~~Ge~~|Input Offset Voltage<br>~~Ge~~<br>~~Ge~~|VCCIO= 3.3 V<br>~~Ge~~|–100<br>~~Ge~~|100<br>~~Ge~~|–105<br>~~Ge~~|105<br>~~Ge~~|mV<br>~~Ge~~|



## **Note** : 

1. Comparator function supported for 3.3 V Referenced Input Buffer types LVCMOS25R33, LVCMOS18R33, LVCMOS15R33, LVCMOS12R33, and LVCMOS10R33. 

## **3.14. Typical Building Block Function Performance – HC/HE Devices** 

## **3.14.1. Pin-to-Pin Performance (LVCMOS25 12 mA Drive)** 

**Table 3.19. Pin-to-Pin Performance (LVCMOS25 12 mA Drive)** 

|**Function**|**–6 Timing**|**Unit**|
|---|---|---|
|**Basic Functions**|||
|16-bit decoder|8.9|ns|
|4:1 MUX|7.5|ns|
|16:1 MUX|8.3|ns|



## **3.14.2. Register-to-Register Performance** 

**Table 3.20. Register-to-Register Performance** 

|**Function**|**–6 Timing**|**Unit**|
|---|---|---|
|**Basic Functions**|||
|16:1 MUX|412|MHz|
|16-bit adder|297|MHz|
|16-bit counter|324|MHz|
|64-bit counter|161|MHz|
|**Embedded Memory Functions**|||
|1024x9 True-Dual Port RAM<br>(Write Through or Normal,EBR output registers)|183|MHz|
|**Distributed Memory Functions**|||
|16x4 Pseudo-Dual Port RAM(one PFU)|500|MHz|



**Note** : The above timing numbers are generated using the Radiant design tool. Exact performance may vary with device and tool version. The tool uses internal parameters that have been characterized but are not tested on every device. Commercial timing numbers are shown at 85 °C and 1.14 V. Other operating conditions, including industrial, can be extracted from the Radiant software. 

## **3.15. Derating Logic Timing** 

Logic timing provided in the following sections of the data sheet and the Lattice design tools are worst case numbers in the operating range. Actual delays may be much faster. Lattice design tools can provide logic timing numbers at a particular temperature and voltage. 

© 2025 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02125-1.0 

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**MachXO4 Family Data Sheet** 

## **3.16. Maximum sysI/O Buffer Performance** 

**Table 3.21. Maximum sysI/O Buffer Performance** 

|**I/O Standard**<br>~~Se~~|**Max. Speed**<br>**(Commercial/Industrial)**|**Max. Speed**<br>**(Automotive)**|**Unit**|
|---|---|---|---|
|MIPI<br>~~Se~~<br>~~ee~~|450|—|MHz|
|LVDS25<br>~~Se~~<br>~~ee~~<br>~~S$~~|400<br>~~S$~~|—|MHz|
|LVDS25E<br>~~Se~~<br>~~ee~~<br>~~S$~~|150<br>~~S$~~|—|MHz|
|BLVDS25<br>~~ee~~<br>~~S$~~<br>~~a~~<br>~~es~~|150<br>~~S$~~<br>~~a~~<br>~~es~~|—<br>~~eee~~|MHz<br>~~eee~~|
|BLVDS25E<br>~~S$~~<br>~~a~~<br>~~es~~<br>~~es~~|150<br>~~S$~~<br>~~a~~<br>~~es~~<br>~~es~~|—<br>~~eee~~<br>~~eee~~|MHz<br>~~eee~~<br>~~eee~~|
|MLVDS25<br>~~es~~<br>~~es~~<br>~~ee~~|150<br>~~es~~<br>~~es~~<br>~~ee~~|—<br>~~eee~~<br>~~eee~~<br>~~ee~~|MHz<br>~~eee~~<br>~~eee~~<br>~~ee~~|
|MLVDS25E<br>~~es~~<br>~~es~~<br>~~ee~~<br>~~Se~~|150<br>~~es~~<br>~~es~~<br>~~ee~~|—<br>~~eee~~<br>~~eee~~<br>~~ee~~|MHz<br>~~eee~~<br>~~eee~~<br>~~ee~~|
|LVPECL33<br>~~es~~<br>~~ee~~<br>~~Se~~<br>~~S$]~~|150<br>~~es~~<br>~~ee~~<br>~~S$]~~|—<br>~~eee~~<br>~~ee~~<br>~~S$]~~|MHz<br>~~eee~~<br>~~ee~~|
|LVPECL33E<br>~~ee~~<br>~~Se~~<br>~~S$]~~<br>~~Sa~~|150<br>~~ee~~<br>~~S$]~~<br>~~nn~~|—<br>~~ee~~<br>~~S$]~~|MHz<br>~~ee~~|
|LVTTL33<br>~~Se~~<br>~~S$]~~<br>~~Sa~~<br>~~ee~~|150<br>~~S$]~~<br>~~nn~~|—<br>~~S$]~~|MHz|
|LVTTL33D<br>~~S$]~~<br>~~Sa~~<br>~~ee~~<br>~~es~~|150<br>~~S$]~~<br>~~nn~~<br>~~es~~|—<br>~~S$]~~<br>~~ee~~|MHz<br>~~ee~~|
|LVCMOS33<br>~~Sa ~~<br>~~ee~~<br>~~es~~|150<br> ~~nn~~<br>~~es~~|—<br>~~ee~~|MHz<br>~~ee~~|
|LVCMOS33D<br>~~ee~~<br>~~es~~<br>~~Se~~<br>~~es~~|150<br>~~es~~<br>~~Se~~<br>~~eee~~|—<br>~~ee~~<br>~~Se~~<br>~~eee~~|MHz<br>~~ee~~<br>~~Se~~<br>~~ee~~|
|LVCMOS25<br>~~es~~<br>~~Se~~<br>~~es~~|150<br>~~es~~<br>~~Se~~<br>~~eee~~|—<br>~~ee~~<br>~~Se~~<br>~~eee~~|MHz<br>~~ee~~<br>~~Se~~<br>~~ee~~|
|LVCMOS25D<br>~~Se~~<br>~~es~~<br>~~ph~~|150<br>~~Se~~<br>~~eee~~<br>~~ph~~|—<br>~~Se~~<br>~~eee~~<br>~~ph~~|MHz<br>~~Se~~<br>~~ee~~|
|LVCMOS18<br>~~es ~~<br>~~ph~~<br>~~ph~~|150<br> ~~eee~~<br>~~ph~~<br>~~ph~~|—<br>~~eee~~<br>~~ph~~<br>~~ph~~|MHz<br>~~ee~~|
|LVCMOS18D<br>~~ph~~<br>~~ph~~<br>~~ee~~|150<br>~~ph~~<br>~~ph~~|—<br>~~ph~~<br>~~ph~~|MHz|
|LVCMOS15<br>~~ph~~<br>~~ee~~<br>~~es~~|150<br>~~ph~~<br>~~es~~|—<br>~~ph~~<br>~~ee~~|MHz<br>~~ee~~|
|LVCMOS15D<br>~~ee~~<br>~~es~~|150<br>~~es~~|—<br>~~ee~~|MHz<br>~~ee~~|
|LVCMOS12<br>~~ee~~<br>~~es~~<br>~~I~~|91<br>~~es~~<br>~~I~~|—<br>~~ee~~<br>~~I~~|MHz<br>~~ee~~<br>~~I~~|
|LVCMOS12D<br>~~es~~<br>~~I~~<br>~~ee~~|91<br>~~es~~<br>~~I~~<br>~~ee~~|—<br>~~ee~~<br>~~I~~<br>~~ee~~|MHz<br>~~ee~~<br>~~I~~|



© 2025 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02125-1.0 

60 

**MachXO4 Family Data Sheet** 

## **3.17. External Switching Characteristics – HC/HE Devices** 

Over recommended operating conditions. 

**Table 3.22. MachXO4 External Switching Characteristics – HC/HE Devices[1, 2, 3, 4, 5, 6, 10]** 

|**Parameter**<br>~~ee~~<br>~~Re~~|**Description**<br>~~ee~~<br>~~Re~~|**Device**<br>~~ee~~|**–6**<br>**(Commercial/Industrial)**<br>~~ee~~<br>~~ee~~|**–6**<br>**(Commercial/Industrial)**<br>~~ee~~<br>~~ee~~|**–5**<br>**(Commercial/Industrial)**<br>~~ee~~|**–5**<br>**(Commercial/Industrial)**<br>~~ee~~|**–5**<br>**(Automotive)**<br>~~ee~~|**–5**<br>**(Automotive)**<br>~~ee~~|**Unit**<br>~~ee~~|
|---|---|---|---|---|---|---|---|---|---|
||||**Min.**<br>~~ee~~<br>~~ee~~|**Max.**<br>~~ee~~|**Min.**<br>~~ee~~|**Max.**<br>~~ee~~|**Min.**<br>~~ee~~|**Max.**<br>~~ee~~||
|**Clocks**<br>~~ee~~<br>~~Re~~||||||||||
|**Primary Clocks**<br>~~ee~~<br>~~Re~~<br>~~|~~<br>~~ee~~||||||||||
|fMAX_PRI7<br>~~|~~<br>~~ee~~|Frequency for<br>PrimaryClock Tree<br>~~|~~<br>~~ee~~|All MachXO4<br>devices<br>~~|~~<br>~~ee~~|—<br>~~|~~<br>~~ee~~|388<br>~~|~~<br>~~ee~~|—<br>~~|~~<br>~~ee~~<br>~~ee~~|323<br>~~|~~<br>~~ee~~<br>~~ee~~|—<br>~~|~~<br>~~ee~~<br>~~ee~~|323<br>~~|~~<br>~~ee~~|MHz<br>~~|~~<br>~~ee~~|
|tW_PRI<br>~~ee~~<br>~~ss~~|Clock Pulse Width<br>for PrimaryClock<br>~~ee~~<br>~~ss~~|All MachXO4<br>devices<br>~~ee~~<br>~~ss~~<br>~~ee~~|0.5<br>~~ee~~<br>~~ss~~<br>~~ss~~|—<br>~~ee~~<br>~~ss~~<br>~~ss~~|0.6<br>~~ee~~<br>~~ee~~<br>~~ss~~<br>~~ss~~|—<br>~~ee~~<br>~~ee~~<br>~~ss~~<br>~~ss~~|0.6<br>~~ee~~<br>~~ee~~<br>~~ss~~<br>~~ss~~|—<br>~~ee~~<br>~~ss~~<br>~~ss~~|ns<br>~~ee~~<br>~~ss~~<br>~~ss~~|
|tSKEW_PRI<br>~~ss~~|Primary Clock<br>Skew Within a<br>Device<br>~~ss~~|LFMXO4-010 HC/HE<br>~~ss~~<br>~~ee~~<br>~~ee~~|—<br>~~ss~~<br>~~ss~~<br>~~es~~|867<br>~~ss~~<br>~~ss~~<br>~~es~~|—<br>~~ss~~<br>~~ss~~<br>~~es~~|897<br>~~ss~~<br>~~ss~~|—<br>~~ss~~<br>~~ss~~|952<br>~~ss~~<br>~~ss~~|ps<br>~~ss~~<br>~~ss~~|
|||LFMXO4-015 HC/HE<br>~~ee~~<br>~~ee~~|—<br>~~ss~~<br>~~es~~|867<br>~~ss~~<br>~~es~~|—<br>~~ss~~<br>~~es~~|897<br>~~ss~~|—<br>~~ss~~|952<br>~~ss~~|ps<br>~~ss~~|
|||LFMXO4-025 HC/HE<br>~~ee~~<br>~~ee~~<br>~~ee es~~|—<br>~~es ~~<br>~~ee~~<br>~~es~~|867<br> ~~es~~<br>~~ee~~<br>~~es~~|—<br>~~es~~<br>~~ee~~<br>~~es~~|897<br>~~ee~~|—<br>~~ee~~|952<br>~~ee~~|ps<br>~~ee~~|
|||LFMXO4-050 HC/HE<br>~~ee~~<br>~~ee es~~<br>~~ee es~~|—<br>~~ee~~<br>~~es~~<br>~~es~~|865<br>~~ee~~<br>~~es~~<br>~~es~~|—<br>~~ee~~<br>~~es~~<br>~~es~~|892<br>~~ee~~|—<br>~~ee~~|986<br>~~ee~~|ps<br>~~ee~~|
|||LFMXO4-080 HC/HE<br>~~ee es~~<br>~~ee es~~<br>~~ee~~|—<br>~~es ~~<br>~~es~~<br>~~ee~~|902<br> ~~es~~<br>~~es~~<br>~~ee~~|—<br>~~es~~<br>~~es~~<br>~~es~~|942<br>~~ee~~|—<br>~~ee~~|—|ps|
|||LFMXO4-110 HC/HE<br>~~ee es~~<br>~~ee~~|—<br>~~es ~~<br>~~ee~~|908<br> ~~es~~<br>~~ee~~|—<br>~~es~~<br>~~es~~|950<br>~~ee~~|—<br>~~ee~~|—|ps|
|**Edge Clock**<br>~~eeee ee es ee~~<br>~~Ce~~||||||||||
|fMAX_EDGE7<br>~~Ce~~<br>~~ee~~|Frequency for<br>Edge Clock<br>~~Ce~~<br>~~ee~~|All MachXO4<br>devices<br>~~Ce~~<br>~~ee~~|—<br>~~Ce~~<br>~~ee~~|400<br>~~Ce~~<br>~~ee~~|—<br>~~Ce~~<br>~~ee~~|333<br>~~Ce~~<br>~~ee~~|—<br>~~Ce~~<br>~~ee~~|333<br>~~Ce~~<br>~~ee~~|MHz<br>~~Ce~~<br>~~ee~~|
|**Pin-LUT-Pin Propagation Delay**<br>~~ee~~<br>~~Ce~~||||||||||
|tPD<br>~~Ce~~|Best case<br>propagation delay<br>through one LUT-4<br>~~Ce~~|All MachXO4<br>devices<br>~~Ce~~|—<br>~~Ce~~|6.72<br>~~Ce~~|—<br>~~Ce~~|6.96<br>~~Ce~~|—<br>~~Ce~~|6.96<br>~~Ce~~|ns<br>~~Ce~~|
|**General I/O Pin Parameters(Using Primary Clock without PLL)**<br>~~Ce~~<br>~~es~~||||||||||
|tCO<br>~~Ce~~|Clock to Output –<br>PIO Output<br>Register<br>~~Ce~~|LFMXO4-010 HC/HE<br>~~Ce~~<br>~~es~~<br>~~ee~~|—<br>~~Ce~~<br>~~es~~|7.46<br>~~Ce~~|—<br>~~Ce~~|7.66<br>~~Ce~~|—<br>~~Ce~~|7.66<br>~~Ce~~|ns<br>~~Ce~~|
|||LFMXO4-015 HC/HE<br>~~es~~<br>~~ee~~|—<br>~~es~~|7.46|—|7.66|—|7.66|ns|
|||LFMXO4-025 HC/HE<br>~~ee ~~<br>~~se~~|—<br> ~~es~~<br>~~se~~|7.46<br>~~se~~<br>~~es~~|—<br>~~se~~<br>~~es~~|7.66<br>~~se~~|—<br>~~se~~|7.66<br>~~se~~|ns<br>~~se~~|
|||LFMXO4-050 HC/HE<br>~~se~~<br>~~es~~|—<br>~~se~~<br>~~es~~|7.51<br>~~se~~<br>~~es~~<br>~~es~~<br>~~es~~|—<br>~~se~~<br>~~es~~<br>~~es~~<br>~~es~~|7.71<br>~~se~~<br>~~es~~|—<br>~~se~~<br>~~es~~|7.71<br>~~se~~<br>~~es~~|ns<br>~~se~~<br>~~es~~|
|||LFMXO4-080 HC/HE<br>~~es~~<br>~~es~~<br>~~ee~~|—<br>~~es~~<br>~~es~~<br>|7.54<br>~~es~~<br>~~es~~<br>~~es~~<br>~~es~~<br>~~es~~<br>|—<br>~~es~~<br>~~es~~<br>~~es~~<br>~~es~~<br>~~es~~<br>|7.75<br>~~es~~<br>~~es~~<br>~~es~~|—<br>~~es~~<br>~~es~~|—<br>~~es~~<br>~~es~~|ns<br>~~es~~<br>~~es~~|
|||LFMXO4-110 HC/HE<br>~~es~~<br>~~es~~<br>~~ee~~<br>~~ee~~|—<br>~~es~~<br>~~es~~<br>~~es~~<br>|7.53<br>~~es~~<br>~~es~~<br>~~es~~<br>~~es~~<br>~~es~~<br>|—<br>~~es~~<br>~~es~~<br>~~es~~<br>~~es~~<br>~~es~~<br>|7.83<br>~~es~~<br>~~es~~<br>~~es~~|—<br>~~es~~<br>~~es~~|—<br>~~es~~<br>~~es~~|ns<br>~~es~~<br>~~es~~|
|tSU|Clock to Data<br>Setup – PIO Input<br>Register|LFMXO4-010 HC/HE<br>~~es~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|–0.20<br>~~es~~<br>~~es~~<br>~~**es**~~|—<br>~~es~~<br>~~es~~<br>~~es~~<br>~~**es**~~|–0.20<br>~~es~~<br>~~es~~<br>~~es~~<br>~~**es**~~|—<br>~~es~~<br>~~es~~|–0.20<br>~~es~~|—<br>~~es~~|ns<br>~~es~~|
|||LFMXO4-015 HC/HE<br>~~ee ~~<br>~~ee~~<br>~~ee~~|–0.20<br> ~~es~~<br>~~**es**~~|—<br>~~es~~<br>~~es~~<br>~~**es**~~|–0.20<br>~~es~~<br>~~es~~<br>~~**es**~~|—<br>~~es~~|–0.20|—|ns|
|||LFMXO4-025 HC/HE<br> <br>~~ee ~~<br>~~ee~~|–0.20<br> ~~es ~~<br> ~~**es**~~|—<br> ~~es~~<br>~~**es**~~|–0.20<br>~~es~~<br>~~**es**~~|—|–0.20|—|ns|
|||LFMXO4-050 HC/HE<br> <br>~~ee~~<br>~~se~~|–0.23<br> ~~**es** ~~<br>~~se~~|—<br> ~~**es** ~~<br>~~se~~<br>~~es~~|–0.23<br> ~~**es**~~<br>~~se~~<br>~~es~~|—<br>~~se~~|–0.23<br>~~se~~|—<br>~~se~~|ns<br>~~se~~|
|||LFMXO4-080 HC/HE<br>~~se~~<br>~~es~~<br>~~ee~~|–0.23<br>~~se~~<br>~~es~~<br>|—<br>~~se~~<br>~~es~~<br>~~es~~<br>~~es~~<br>|–0.23<br>~~se~~<br>~~es~~<br>~~es~~<br>~~es~~<br>|—<br>~~se~~<br>~~es~~<br>~~es~~|—<br>~~se~~<br>~~es~~|—<br>~~se~~<br>~~es~~|ns<br>~~se~~<br>~~es~~|
|||LFMXO4-110 HC/HE<br>~~es~~<br>~~es~~<br>~~ee~~<br>~~ee~~|–0.24<br>~~es~~<br>~~es~~<br>~~es~~<br>|—<br>~~es~~<br>~~es~~<br>~~es~~<br>~~es~~<br>~~es~~<br>|–0.24<br>~~es~~<br>~~es~~<br>~~es~~<br>~~es~~<br>~~es~~<br>|—<br>~~es~~<br>~~es~~<br>~~es~~|—<br>~~es~~<br>~~es~~|—<br>~~es~~<br>~~es~~|ns<br>~~es~~<br>~~es~~|
|tH|Clock to Data Hold<br>– PIO Input<br>Register|LFMXO4-010 HC/HE<br>~~es~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|1.89<br>~~es~~<br>~~es~~<br>~~**es**~~|—<br>~~es~~<br>~~es~~<br>~~es~~<br>~~**es**~~|2.13<br>~~es~~<br>~~es~~<br>~~es~~<br>~~**es**~~|—<br>~~es~~<br>~~es~~|2.58<br>~~es~~|—<br>~~es~~|ns<br>~~es~~|
|||LFMXO4-015 HC/HE<br>~~ee ~~<br>~~ee~~<br>~~ee~~|1.89<br> ~~es~~<br>~~**es**~~|—<br>~~es~~<br>~~es~~<br>~~**es**~~|2.13<br>~~es~~<br>~~es~~<br>~~**es**~~|—<br>~~es~~|2.58|—|ns|
|||LFMXO4-025 HC/HE<br> <br>~~ee ~~<br>~~ee~~|1.89<br> ~~es ~~<br> ~~**es**~~|—<br> ~~es~~<br>~~**es**~~|2.13<br>~~es~~<br>~~**es**~~|—|2.58|—|ns|
|||LFMXO4-050 HC/HE<br> <br>~~ee~~<br>~~De~~|1.94<br> ~~**es** ~~<br>~~De~~|—<br> ~~**es** ~~<br>~~De~~<br>~~ee~~|2.18<br> ~~**es**~~<br>~~De~~<br>~~es~~|—<br>~~De~~<br>~~ee~~|2.49<br>~~De~~<br>~~ee~~|—<br>~~De~~|ns<br>~~De~~|
|||LFMXO4-080 HC/HE<br>~~De~~<br>~~es~~|1.98<br>~~De~~<br>~~es~~|—<br>~~De~~<br>~~es~~<br>~~ee~~<br>~~ee~~|2.23<br>~~De~~<br>~~es~~<br>~~es~~<br>~~es~~|—<br>~~De~~<br>~~es~~<br>~~ee~~|—<br>~~De~~<br>~~es~~<br>~~ee~~|—<br>~~De~~<br>~~es~~|ns<br>~~De~~<br>~~es~~|
|||LFMXO4-110 HC/HE<br>~~es~~<br>~~es~~<br>~~ee~~|1.99<br>~~es~~<br>~~es~~<br>|—<br>~~es~~<br>~~ee ~~<br>~~es~~<br>~~ee~~<br>~~ee~~<br>|2.24<br>~~es~~<br> ~~es ~~<br>~~es~~<br>~~es~~<br>~~se~~<br>|—<br>~~es~~<br> ~~ee~~<br>~~es~~<br>~~se~~<br>|—<br>~~es~~<br>~~ee~~<br>~~es~~<br>|—<br>~~es~~<br>~~es~~<br>|ns<br>~~es~~<br>~~es~~<br>|
|tSU_DEL|Clock to Data<br>Setup – PIO Input<br>Register with Data<br>Input Delay|LFMXO4-010 HC/HE<br>~~es~~<br>~~es~~<br>~~ee~~|1.61<br>~~es~~<br>~~es~~<br>|—<br>~~es~~<br>~~ee~~<br>~~es~~<br>~~ee~~<br>|1.76<br>~~es~~<br>~~es~~<br>~~es~~<br>~~se~~<br>|—<br>~~es~~<br>~~es~~<br>~~se~~<br>|1.76<br>~~es~~<br>~~es~~<br>|—<br>~~es~~<br>~~es~~<br>|ns<br>~~es~~<br>~~es~~<br>|
|||LFMXO4-015 HC/HE<br>~~es~~<br>~~ee~~<br>~~es es~~<br>~~es~~|1.61<br>~~es~~<br>~~ss~~<br>~~es~~<br>|—<br>~~es~~<br>~~ee~~<br>~~ss~~<br>~~es~~<br>|1.76<br>~~es~~<br>~~se~~<br>~~ss~~<br>~~ss~~<br>|—<br>~~es~~<br>~~se~~<br>~~ss~~<br>~~ss~~<br>|1.76<br>~~es~~<br>~~ss~~|—<br>~~es~~<br>~~ss~~|ns<br>~~es~~<br>~~ss~~|
|||LFMXO4-025 HC/HE<br>~~ee~~<br>~~es es~~<br>~~es es~~<br>~~rs~~|1.61<br>~~ss~~<br>~~es~~<br>~~es~~<br>|—<br>~~ee ~~<br>~~ss~~<br>~~es~~<br>~~es~~|1.76<br> ~~se~~<br>~~ss~~<br>~~ss~~<br>~~ds~~|—<br>~~se~~<br>~~ss~~<br>~~ss~~<br>~~ds~~|1.76<br>~~ss~~|—<br>~~ss~~|ns<br>~~ss~~|
|||LFMXO4-050 HC/HE<br><br>~~es es~~<br>~~es es~~<br>~~rs~~|1.66<br>~~ss~~<br>~~es~~<br>~~es~~<br>~~ee~~|—<br>~~ss~~<br>~~es~~<br>~~es~~|1.81<br>~~ss~~<br>~~ss~~<br>~~ds~~|—<br>~~ss~~<br>~~ss~~<br>~~ds~~|1.81<br>~~ss~~|—<br>~~ss~~|ns<br>~~ss~~|
|||LFMXO4-080 HC/HE<br>~~es~~<br>~~es es~~<br>~~rs~~|1.53<br>~~es ~~<br>~~es~~<br>~~ee~~|—<br> ~~es ~~<br>~~es~~<br>~~ee~~|1.67<br> ~~ss~~<br>~~ds~~<br>~~se~~|—<br>~~ss~~<br>~~ds~~<br>~~se~~|—|—|ns|
|||LFMXO4-110 HC/HE<br>~~es~~<br>~~rs~~<br>~~es~~|1.65<br>~~es ~~<br>~~ee~~<br>~~es~~|—<br> ~~es ~~<br>~~es~~<br>~~ee~~|1.80<br> ~~ds~~<br>~~es~~<br>~~se~~|—<br>~~ds~~<br>~~es~~<br>~~se~~|—<br>~~es~~|—<br>~~es~~|ns<br>~~es~~|



© 2025 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02125-1.0 

61 

**MachXO4 Family Data Sheet** 

|**Parameter**<br>~~ef~~|**Description**<br>~~ef~~|**Device**<br>~~ef~~|**–6**<br>**(Commercial/Industrial)**<br>~~ef~~|**–6**<br>**(Commercial/Industrial)**<br>~~ef~~|**–5**<br>**(Commercial/Industrial)**<br>~~ef~~|**–5**<br>**(Commercial/Industrial)**<br>~~ef~~|**–5**<br>**(Automotive)**<br>~~ef~~|**–5**<br>**(Automotive)**<br>~~ef~~|**Unit**<br>~~ef~~|
|---|---|---|---|---|---|---|---|---|---|
||||**Min.**<br>~~ef~~|**Max.**<br>~~ef~~|**Min.**<br>~~ef~~|**Max.**<br>~~ef~~|**Min.**<br>~~ef~~|**Max.**<br>~~ef~~||
|tH_DEL<br>~~ef~~|Clock to Data Hold<br>– PIO Input<br>Register with<br>Input Data Delay<br>~~ef~~|LFMXO4-010 HC/HE<br>~~ef~~<br>~~Ge~~|–0.23<br>~~ef~~<br>~~Ge~~|—<br>~~ef~~<br>~~Ge~~<br>~~eG~~|–0.23<br>~~ef~~<br>~~Ge~~<br>~~eG~~|—<br>~~ef~~<br>~~Ge~~|–0.19<br>~~ef~~<br>~~Ge~~|—<br>~~ef~~<br>~~Ge~~|ns<br>~~ef~~<br>~~Ge~~|
|||LFMXO4-015 HC/HE<br>~~Ge~~<br>~~ef~~|–0.23<br>~~Ge~~<br>~~ef~~|—<br>~~Ge~~<br>~~ef~~<br>~~eG~~|–0.23<br>~~Ge~~<br>~~ef~~<br>~~eG~~|—<br>~~Ge~~<br>~~ef~~|–0.19<br>~~Ge~~<br>~~ef~~|—<br>~~Ge~~<br>~~ef~~|ns<br>~~Ge~~<br>~~ef~~|
|||LFMXO4-025 HC/HE<br>~~eG~~|–0.23<br>~~eG~~|—<br>~~eG~~<br>~~eG~~|–0.23<br>~~eG~~<br>~~eG~~|—<br>~~eG~~|–0.19<br>~~eG~~|—<br>~~eG~~|ns<br>~~eG~~|
|||LFMXO4-050 HC/HE<br>~~eG~~<br>~~ed~~|–0.25<br>~~eG~~|—<br>~~eG~~|–0.25<br>~~eG~~|—<br>~~eG~~|–0.22<br>~~eG~~|—<br>~~eG~~|ns<br>~~eG~~|
|||LFMXO4-080 HC/HE<br>~~ed~~|–0.21|—|–0.21|—|—|—|ns|
|||LFMXO4-110 HC/HE<br>~~ed~~|–0.24|—|–0.24|—|—|—|ns|
|fMAX_I/O<br>~~eee~~|Clock Frequency of<br>I/O and PFU<br>Register<br>~~eee~~|All MachXO4<br>devices<br>~~eee~~|—<br>~~eee~~|388<br>~~eee~~|—<br>~~eee~~|323<br>~~eee~~|—<br>~~eee~~|323<br>~~eee~~|MHz<br>~~eee~~|
|**General I/O Pin Parameters(Using Edge Clock without PLL)**<br>~~Rn~~||||||||||
|tCOE<br>~~Rn~~|Clock to Output–<br>PIO Output<br>Register<br>~~Rn~~|LFMXO4-010 HC/HE<br>~~Rn~~<br>~~ed~~|—<br>~~Rn~~<br>~~ed~~|7.53<br>~~Rn~~<br>~~ed~~|—<br>~~Rn~~<br>~~ed~~|7.76<br>~~Rn~~<br>~~ed~~|—<br>~~Rn~~<br>~~ed~~|7.76<br>~~Rn~~<br>~~ed~~|ns<br>~~Rn~~<br>~~ed~~|
|||LFMXO4-015 HC/HE<br>~~ed~~<br>~~ed~~<br>~~es~~|—<br>~~ed~~<br>~~ed~~|7.53<br>~~ed~~<br>~~ed~~|—<br>~~ed~~<br>~~ed~~<br>~~es~~|7.76<br>~~ed~~<br>~~ed~~|—<br>~~ed~~<br>~~ed~~|7.76<br>~~ed~~<br>~~ed~~|ns<br>~~ed~~<br>~~ed~~|
|||LFMXO4-025 HC/HE<br>~~ed~~<br>~~es~~<br>~~es~~|—<br>~~ed~~<br>~~es~~|7.53<br>~~ed~~<br>~~es~~|—<br>~~ed~~<br>~~es~~<br>~~es~~|7.76<br>~~ed~~<br>~~es~~|—<br>~~ed~~<br>~~es~~|7.76<br>~~ed~~<br>~~es~~|ns<br>~~ed~~<br>~~es~~|
|||LFMXO4-050 HC/HE<br>~~es~~<br>~~es~~<br>~~es~~|—<br>~~es~~|7.45<br>~~es~~|—<br>~~es~~<br>~~es~~|7.68<br>~~es~~|—<br>~~es~~|7.68<br>~~es~~|ns<br>~~es~~|
|||LFMXO4-080 HC/HE<br>~~es~~<br>~~es~~<br>~~es~~|—|7.53|—<br>~~es~~|7.76|—|—|ns|
|||LFMXO4-110 HC/HE<br>~~es~~<br>~~es~~<br>~~es~~|—|8.93|—|9.35|—|—|ns|
|tSUE|Clock to Data<br>Setup–PIO Input<br>Register|LFMXO4-010 HC/HE<br>~~es~~<br>~~es~~<br>~~ed~~|–0.19|—|–0.19|—|–0.19|—|ns|
|||LFMXO4-015 HC/HE<br>~~es~~<br>~~ed~~<br>~~ed~~|–0.19|—|–0.19|—|–0.19|—|ns|
|||LFMXO4-025 HC/HE<br>~~ed~~<br>~~ed~~<br>~~es~~|–0.19|—|–0.19<br>~~es~~|—|–0.19|—|ns|
|||LFMXO4-050 HC/HE<br>~~ed~~<br>~~es~~<br>~~es~~|–0.16<br>~~es~~|—<br>~~es~~|–0.16<br>~~es~~<br>~~es~~|—<br>~~es~~|–0.16<br>~~es~~|—<br>~~es~~|ns<br>~~es~~|
|||LFMXO4-080 HC/HE<br>~~es~~<br>~~es~~<br>~~es~~|–0.19<br>~~es~~|—<br>~~es~~|–0.19<br>~~es~~<br>~~es~~|—<br>~~es~~|—<br>~~es~~|—<br>~~es~~|ns<br>~~es~~|
|||LFMXO4-110 HC/HE<br>~~es~~<br>~~es~~<br>~~es~~|–0.20|—|–0.20<br>~~es~~|—|—|—|ns|
|tHE|Clock to Data Hold<br>–PIO Input<br>Register|LFMXO4-010 HC/HE<br>~~es~~<br>~~es~~<br>~~ed~~|1.97|—|2.24|—|2.24|—|ns|
|||LFMXO4-015 HC/HE<br>~~es~~<br>~~ed~~<br>~~ed~~|1.97|—|2.24|—|2.24|—|ns|
|||LFMXO4-025 HC/HE<br>~~ed~~<br>~~ed~~<br>~~ee~~|1.97|—|2.24|—|2.24|—|ns|
|||LFMXO4-050 HC/HE<br>~~ed~~<br>~~ee~~|1.89|—|2.16|—|2.16|—|ns|
|||LFMXO4-080 HC/HE<br>~~ee~~<br>~~sd~~|1.97<br>~~sd~~|—<br>~~sd~~|2.24<br>~~sd~~|—<br>~~sd~~|—<br>~~sd~~|—<br>~~sd~~|ns<br>~~sd~~|
|||LFMXO4-110 HC/HE<br>~~sd~~<br>~~sd~~<br>~~ed~~|1.98<br>~~sd~~<br>~~sd~~|—<br>~~sd~~<br>~~sd~~|2.25<br>~~sd~~<br>~~sd~~|—<br>~~sd~~<br>~~sd~~|—<br>~~sd~~<br>~~sd~~|—<br>~~sd~~<br>~~sd~~|ns<br>~~sd~~<br>~~sd~~|
|tSU_DELE|Clock to Data<br>Setup–PIO Input<br>Register with Data<br>Input Delay|LFMXO4-010 HC/HE<br>~~sd~~<br>~~ed~~<br>~~es~~|1.56<br>~~sd~~|—<br>~~sd~~|1.69<br>~~sd~~|—<br>~~sd~~|1.69<br>~~sd~~|—<br>~~sd~~|ns<br>~~sd~~|
|||LFMXO4-015 HC/HE<br>~~ed~~<br>~~es~~<br>~~ee~~|1.56|—|1.69|—|1.69|—|ns|
|||LFMXO4-025 HC/HE<br>~~es~~<br>~~ee~~<br>~~ee~~|1.56|—|1.69|—|1.69|—|ns|
|||LFMXO4-050 HC/HE<br>~~ee~~<br>~~ee~~<br>~~ee~~|1.74|—|1.88|—|1.88|—|ns|
|||LFMXO4-080 HC/HE<br>~~ee~~<br>~~ee~~|1.66|—|1.81|—|—|—|ns|
|||LFMXO4-110 HC/HE<br>~~ee~~<br>~~sd~~<br>~~ed~~|1.71<br>~~sd~~|—<br>~~sd~~|1.85<br>~~sd~~|—<br>~~sd~~|—<br>~~sd~~|—<br>~~sd~~|ns<br>~~sd~~|
|tH_DELE|Clock to Data Hold<br>–PIO Input<br>Register with<br>Input Data Delay<br>~~po~~|LFMXO4-010 HC/HE<br>~~sd~~<br>~~ed~~<br>~~es~~|–0.23<br>~~sd~~|—<br>~~sd~~|–0.23<br>~~sd~~|—<br>~~sd~~|–0.23<br>~~sd~~|—<br>~~sd~~|ns<br>~~sd~~|
|||LFMXO4-015 HC/HE<br>~~ed~~<br>~~es~~<br>~~ee~~|–0.23|—|–0.23|—|–0.23|—|ns|
|||LFMXO4-025 HC/HE<br>~~es~~<br>~~ee~~<br>~~ee~~|–0.23|—|–0.23|—|–0.23|—|ns|
|||LFMXO4-050 HC/HE<br>~~ee~~<br>~~ee~~<br>~~po~~|–0.34|—|–0.34|—|–0.34|—|ns|
|||LFMXO4-080 HC/HE<br>~~ee~~<br>~~po~~<br>~~ee~~|–0.29|—|–0.29|—|—|—|ns|
|||LFMXO4-110 HC/HE<br>~~po~~<br>~~ee~~|–0.30|—|–0.30|—|—|—|ns|
|**General I/O Pin Parameters(Using Primary Clock with PLL)**<br>~~ee~~<br>~~Re~~||||||||||
|tCOPLL<br>~~Re~~|Clock to Output–<br>PIO Output<br>Register<br>~~Re~~|LFMXO4-010 HC/HE<br>~~Re~~<br>~~es~~|—<br>~~Re~~|5.98<br>~~Re~~|—<br>~~Re~~|6.01<br>~~Re~~|—<br>~~Re~~|6.01<br>~~Re~~|ns<br>~~Re~~|
|||LFMXO4-015 HC/HE<br>~~es~~<br>~~es~~|—|5.98|—|6.01|—|6.01|ns|
|||LFMXO4-025 HC/HE<br>~~es~~<br>~~es~~<br>~~es~~|—|5.98|—|6.01|—|6.01|ns|
|||LFMXO4-050 HC/HE<br>~~es~~<br>~~es~~|—|5.99|—|6.02|—|6.02|ns|
|||LFMXO4-080 HC/HE<br>~~es~~<br>~~dd~~|—<br>~~dd~~|6.02<br>~~dd~~|—<br>~~dd~~|6.06<br>~~dd~~|—<br>~~dd~~|—<br>~~dd~~|ns<br>~~dd~~|
|||LFMXO4-110 HC/HE<br>~~dd~~<br>~~nd~~|—<br>~~dd~~<br>~~nd~~|5.55<br>~~dd~~<br>~~nd~~|—<br>~~dd~~<br>~~nd~~|6.13<br>~~dd~~<br>~~nd~~|—<br>~~dd~~<br>~~nd~~|—<br>~~dd~~<br>~~nd~~|ns<br>~~dd~~<br>~~nd~~|



© 2025 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02125-1.0 

62 

**MachXO4 Family Data Sheet** 

|**Parameter**<br>~~|~~<br>~~7~~|**Description**<br>~~|~~<br>~~2~~|**Device**<br>~~-_~~<br>~~ESE~~|**–6**<br>**(Commercial/Industrial)**<br>~~-_+~~<br>~~eeee~~<br>|**–6**<br>**(Commercial/Industrial)**<br>~~-_+~~<br>~~eeee~~<br>|**–5**<br>**(Commercial/Industrial)**<br>~~+]~~<br>~~ee~~<br>|**–5**<br>**(Commercial/Industrial)**<br>~~+]~~<br>~~ee~~<br>|**–5**<br>**(Automotive)**<br>~~+]~~<br>~~ee~~<br>|**–5**<br>**(Automotive)**<br>~~+]~~<br>~~ee~~<br>|**Unit**<br>~~©~~<br>~~ESEEr~~|
|---|---|---|---|---|---|---|---|---|---|
||||**Min.**<br>~~-_~~<br>~~ee~~<br>~~ESE ESEEr~~|**Max.**<br>~~+~~<br>~~ee~~<br>~~ESEEr~~|**Min.**<br>~~ee~~<br>~~ESEEr~~|**Max.**<br>~~+]~~<br>~~ee~~<br>~~ESEEr~~|**Min.**<br>~~+]~~<br>~~ee~~<br>~~ESEEr~~|**Max.**<br>~~+]~~<br>~~ee~~<br>~~ESEEr~~||
|tSUPLL<br>~~|~~<br>~~7~~<br>~~(|)~~|Clock to Data<br>Setup–PIO Input<br>Register<br>~~|~~<br>~~2~~<br>~~(|)~~|LFMXO4-010 HC/HE<br>~~-_~~<br>~~ESE~~<br>~~es~~|0.36<br>~~-_ ~~<br>~~ee~~<br>~~ESE ESEEr~~<br>~~es~~|—<br> ~~+~~<br>~~ee~~<br>~~ESEEr~~<br>~~es~~|0.36<br>~~ee~~<br>~~ESEEr~~<br>~~ed~~|—<br>~~+]~~<br>~~ee~~<br>~~ESEEr~~|0.36<br>~~+]~~<br>~~ee~~<br>~~ESEEr~~|—<br>~~+] ~~<br>~~ee~~<br>~~ESEEr~~|ns<br> ~~©~~<br>~~ESEEr~~|
|||LFMXO4-015 HC/HE<br>~~ESE~~<br>~~es~~<br>~~es ee~~|0.36<br>~~ee~~<br>~~ESE ESEEr~~<br>~~es~~<br>~~ee~~|—<br>~~ee~~<br>~~ESEEr~~<br>~~es~~<br>~~es~~|0.36<br>~~ee~~<br>~~ESEEr~~<br>~~ed~~<br>~~ss~~|—<br>~~ee~~<br>~~ESEEr~~<br>~~ss~~|0.36<br>~~ee~~<br>~~ESEEr~~|—<br>~~ee~~<br>~~ESEEr~~|ns<br>~~ESEEr~~|
|||LFMXO4-025 HC/HE<br>~~ESE~~<br>~~es ~~<br>~~es ee~~<br>~~es ee~~|0.36<br>~~ee~~<br>~~ESE ESEEr~~<br> ~~es~~<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ESEEr~~<br>~~es~~<br>~~es~~<br>~~es~~|0.36<br>~~ee~~<br>~~ESEEr~~<br>~~ed~~<br>~~ss~~<br>~~ss~~|—<br>~~ee~~<br>~~ESEEr~~<br>~~ss~~<br>~~ss~~|0.36<br>~~ee~~<br>~~ESEEr~~|—<br>~~ee~~<br>~~ESEEr~~|ns<br>~~ESEEr~~|
|||LFMXO4-050 HC/HE<br>~~ESE~~<br>~~es ee~~<br>~~es ee~~<br>~~rs es~~|0.35<br>~~ee~~<br>~~ESE ESEEr~~<br>~~ee~~<br>~~ee~~<br>~~es~~|—<br>~~ee~~<br>~~ESEEr~~<br>~~es ~~<br>~~es~~<br>~~es~~|0.35<br>~~ee~~<br>~~ESEEr~~<br> ~~ss~~<br>~~ss~~<br>~~es~~|—<br>~~ee~~<br>~~ESEEr~~<br>~~ss~~<br>~~ss~~|0.42<br>~~ee~~<br>~~ESEEr~~|—<br>~~ee~~<br>~~ESEEr~~|ns<br>~~ESEEr~~|
|||LFMXO4-080 HC/HE<br>~~ESE~~<br>~~es ee~~<br>~~rs es~~<br>~~rs~~|0.34<br>~~ee~~<br>~~ESE ESEEr~~<br>~~ee~~<br>~~es~~<br>~~ns~~|—<br>~~ee~~<br>~~ESEEr~~<br>~~es ~~<br>~~es~~<br>~~ns~~|0.34<br>~~ee~~<br>~~ESEEr~~<br> ~~ss~~<br>~~es~~|—<br>~~ee~~<br>~~ESEEr~~<br>~~ss~~|—<br>~~ee~~<br>~~ESEEr~~|—<br>~~ee~~<br>~~ESEEr~~|ns<br>~~ESEEr~~|
|||LFMXO4-110 HC/HE<br>~~ESE~~<br>~~rs es~~<br>~~rs~~|0.33<br>~~ee~~<br>~~ESE ESEEr~~<br>~~es~~<br>~~ns~~|—<br>~~ee~~<br>~~ESEEr~~<br>~~es~~<br>~~ns~~|0.33<br>~~ee~~<br>~~ESEEr~~<br>~~es~~|—<br>~~ee~~<br>~~ESEEr~~|—<br>~~ee~~<br>~~ESEEr~~|—<br>~~ee~~<br>~~ESEEr~~|ns<br>~~ESEEr~~|
|tHPLL<br>~~7~~<br>~~(|)~~|Clock to Data Hold<br>–PIO Input<br>Register<br>~~2 ~~<br>~~(|)~~|LFMXO4-110 HC/HE<br> ~~ESE~~<br>~~rs~~<br>~~|S~~<br>~~es~~|0.42<br>~~ee~~<br>~~ESE ESEEr~~<br>~~ns~~<br>~~|S~~<br>~~es~~|—<br>~~ee~~<br>~~ESEEr~~<br>~~ns~~<br>~~Reerer~~<br>~~es~~|0.49<br>~~ee~~<br>~~ESEEr~~<br>~~Reerer~~<br>~~ed~~|—<br>~~ee~~<br>~~ESEEr~~<br>~~Reerer~~|0.49<br>~~ee~~<br>~~ESEEr~~<br>~~Reerer~~|—<br>~~ee~~<br>~~ESEEr~~<br>~~Reerer~~|ns<br>~~ESEEr~~<br>~~Reerer~~|
|||LFMXO4-015 HC/HE<br>~~rs~~<br>~~|S~~<br>~~es~~<br>~~es ee~~|0.42<br>~~ns~~<br>~~|S ~~<br>~~es~~<br>~~ee~~|—<br>~~ns~~<br> ~~Reerer~~<br>~~es~~<br>~~es~~|0.49<br>~~Reerer~~<br>~~ed~~<br>~~ss~~|—<br>~~Reerer~~<br>~~ss~~|0.49<br>~~Reerer~~|—<br>~~Reerer~~|ns<br>~~Reerer~~|
|||LFMXO4-025 HC/HE<br>~~rs~~<br>~~es ~~<br>~~es ee~~<br>~~es ee~~|0.42<br>~~ns~~<br> ~~es~~<br>~~ee~~<br>~~ee~~|—<br>~~ns~~<br>~~es~~<br>~~es~~<br>~~es~~|0.49<br>~~ed~~<br>~~ss~~<br>~~ss~~|—<br>~~ss~~<br>~~ss~~|0.49|—|ns|
|||LFMXO4-050 HC/HE<br>~~rs~~<br>~~es ee~~<br>~~es ee~~<br>~~rs~~|0.43<br>~~ns~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|—<br>~~ns~~<br>~~es ~~<br>~~es~~<br>~~es~~|0.50<br> ~~ss~~<br>~~ss~~<br>~~es~~|—<br>~~ss~~<br>~~ss~~<br>~~es~~|0.51<br>~~es~~|—|ns|
|||LFMXO4-080 HC/HE<br>~~rs~~<br>~~es ee~~<br>~~rs~~<br>~~rd~~|0.46<br>~~ns~~<br>~~ee~~<br>~~ee~~<br>|—<br>~~ns~~<br>~~es ~~<br>~~es~~<br>|0.54<br> ~~ss~~<br>~~es~~<br>~~rs~~<br>|—<br>~~ss~~<br>~~es~~|—<br>~~es~~|—|ns|
|||LFMXO4-110 HC/HE<br>~~rs~~<br>~~rs ~~<br>~~es~~<br>~~rd~~<br>~~re~~|0.47<br>~~ns~~<br> ~~ee ~~<br>~~es~~<br>~~rs~~<br>|—<br>~~ns~~<br> ~~es~~<br>~~es~~<br>~~rs~~<br>|0.55<br>~~es~~<br>~~es~~<br>~~rs~~<br>~~td~~<br>|—<br>~~es~~<br>~~es~~|—<br>~~es~~<br>~~es~~|—<br>~~es~~|ns<br>~~es~~|
|tSU_DELPLL<br>~~(|)~~<br>~~ESSE~~|Clock to Data<br>Setup–PIO Input<br>Register with Data<br>Input Delay<br>~~(|)~~<br>~~ESSE~~|LFMXO4-010 HC/HE<br>~~rs~~<br>~~es~~<br>~~rd~~<br>~~re~~<br>~~ESSE~~|2.87<br>~~ns~~<br>~~es~~<br>~~rs~~<br>~~rs~~<br>~~ESSE~~|—<br>~~ns~~<br>~~es~~<br>~~rs~~<br>~~rs~~<br>~~ESSE~~|3.18<br>~~es~~<br>~~rs~~<br>~~td~~<br>~~rd~~<br>~~ESSE SESS~~|—<br>~~es~~<br>~~SESS~~|3.38<br>~~es~~<br>~~SESS~~|—<br>~~es~~<br>~~SESS~~|ns<br>~~es~~<br>~~SESS~~|
|||LFMXO4-015 HC/HE<br>~~rd ~~<br>~~re~~<br>~~ESSE~~|2.87<br> ~~rs~~<br>~~rs~~<br>~~ESSE~~|—<br>~~rs~~<br>~~rs~~<br>~~ESSE~~|3.18<br>~~rs~~<br>~~td~~<br>~~rd~~<br>~~ESSE SESS~~|—<br>~~SESS~~|3.38<br>~~SESS~~|—<br>~~SESS~~|ns<br>~~SESS~~|
|||LFMXO4-025 HC/HE<br> <br>~~re ~~<br>~~ESSE~~|2.87<br> ~~rs~~<br> ~~rs~~<br>~~ESSE~~|—<br>~~rs ~~<br>~~rs ~~<br>~~ESSE~~|3.18<br> ~~td~~<br> ~~rd~~<br>~~ESSE SESS~~|—<br>~~SESS~~|3.38<br>~~SESS~~|—<br>~~SESS~~|ns<br>~~SESS~~|
|||LFMXO4-050 HC/HE<br>~~ESSE~~<br>~~se~~|2.96<br>~~ESSE~~<br>~~se~~|—<br>~~ESSE~~<br>~~se~~|3.28<br>~~ESSE SESS~~<br>~~se~~|—<br>~~SESS~~<br>~~se~~|3.66<br>~~SESS~~<br>~~se~~|—<br>~~SESS~~<br>~~se~~|ns<br>~~SESS~~<br>~~se~~|
|||LFMXO4-080 HC/HE<br>~~ESSE~~<br>~~se~~<br>~~se~~<br>~~re~~|3.05<br>~~ESSE~~<br>~~se~~<br>~~se~~<br>~~ss~~|—<br>~~ESSE~~<br>~~se~~<br>~~se~~<br>~~ss~~|3.35<br>~~ESSE SESS~~<br>~~se~~<br>~~se~~<br>~~ss~~|—<br>~~SESS~~<br>~~se~~<br>~~se~~|—<br>~~SESS~~<br>~~se~~<br>~~se~~|—<br>~~SESS~~<br>~~se~~<br>~~se~~|ns<br>~~SESS~~<br>~~se~~<br>~~se~~|
|||LFMXO4-110 HC/HE<br>~~ESSE~~<br>~~se~~<br>~~re~~<br>~~rd~~|3.06<br>~~ESSE~~<br>~~se~~<br>~~ss~~<br>~~rs~~|—<br>~~ESSE~~<br>~~se~~<br>~~ss~~<br>~~rs~~|3.37<br>~~ESSE SESS~~<br>~~se~~<br>~~ss~~<br>~~td~~|—<br>~~SESS~~<br>~~se~~|—<br>~~SESS~~<br>~~se~~|—<br>~~SESS~~<br>~~se~~|ns<br>~~SESS~~<br>~~se~~|
|tH_DELPLL<br>~~ESSE~~<br>~~ESSE~~|Clock to Data Hold<br>–PIO Input<br>Register with<br>Input Data Delay<br>~~ESSE~~<br>~~ESSE~~|LFMXO4-010 HC/HE<br>~~ESSE~~<br>~~re~~<br>~~rd~~<br>~~re~~<br>~~ESSE~~|–0.83<br>~~ESSE~~<br>~~ss~~<br>~~rs~~<br>~~rs~~<br>~~ESSE~~|—<br>~~ESSE~~<br>~~ss~~<br>~~rs~~<br>~~rs~~<br>~~ESSE~~|–0.83<br>~~ESSE SESS~~<br>~~ss~~<br>~~td~~<br>~~rd~~<br>~~ESSE SESS~~|—<br>~~SESS~~<br>~~SESS~~|–0.83<br>~~SESS~~<br>~~SESS~~|—<br>~~SESS~~<br>~~SESS~~|ns<br>~~SESS~~<br>~~SESS~~|
|||LFMXO4-015 HC/HE<br>~~rd~~<br>~~re~~<br>~~ESSE~~|–0.83<br>~~rs~~<br>~~rs~~<br>~~ESSE~~|—<br>~~rs~~<br>~~rs~~<br>~~ESSE~~|–0.83<br>~~td~~<br>~~rd~~<br>~~ESSE SESS~~|—<br>~~SESS~~|–0.83<br>~~SESS~~|—<br>~~SESS~~|ns<br>~~SESS~~|
|||LFMXO4-025 HC/HE<br>~~re ~~<br>~~ESSE~~|–0.83<br> ~~rs~~<br>~~ESSE~~|—<br>~~rs ~~<br>~~ESSE~~|–0.83<br> ~~rd~~<br>~~ESSE SESS~~|—<br>~~SESS~~|–0.83<br>~~SESS~~|—<br>~~SESS~~|ns<br>~~SESS~~|
|||LFMXO4-050 HC/HE<br>~~ESSE~~<br>~~se~~|–0.87<br>~~ESSE~~<br>~~se~~|—<br>~~ESSE~~<br>~~se~~|–0.87<br>~~ESSE SESS~~<br>~~se~~|—<br>~~SESS~~<br>~~se~~|–0.87<br>~~SESS~~<br>~~se~~|—<br>~~SESS~~<br>~~se~~|ns<br>~~SESS~~<br>~~se~~|
|||LFMXO4-080 HC/HE<br>~~ESSE~~<br>~~se~~<br>~~se~~|–0.91<br>~~ESSE~~<br>~~se~~<br>~~se~~|—<br>~~ESSE~~<br>~~se~~<br>~~se~~|–0.91<br>~~ESSE SESS~~<br>~~se~~<br>~~se~~|—<br>~~SESS~~<br>~~se~~<br>~~se~~|—<br>~~SESS~~<br>~~se~~<br>~~se~~|—<br>~~SESS~~<br>~~se~~<br>~~se~~|ns<br>~~SESS~~<br>~~se~~<br>~~se~~|
|||LFMXO4-110 HC/HE<br>~~ESSE~~<br>~~se~~<br>~~es~~|–0.93<br>~~ESSE~~<br>~~se~~<br>~~es~~|—<br>~~ESSE~~<br>~~se~~<br>~~es~~|–0.93<br>~~ESSE SESS~~<br>~~se~~<br>~~es~~|—<br>~~SESS~~<br>~~se~~<br>~~es~~|—<br>~~SESS~~<br>~~se~~<br>~~es~~|—<br>~~SESS~~<br>~~se~~<br>~~es~~|ns<br>~~SESS~~<br>~~se~~<br>~~es~~|
|**Generic DDRX1 Inputs with Clock and Data Aligned at Pin Using PCLK Pin for Clock Input– GDDRX1_RX.SCLK.Aligned8, 9 **<br>~~ESSE SESS~~<br>~~es~~<br>~~|~~<br>~~_|~~<br>~~|~~<br>~~|~~<br>~~|~~<br>~~|~~<br>~~rTrT~~||||||||||
|tDVA<br>~~|~~<br>~~_|~~<br>~~_|~~|Input Data Valid<br>After CLK<br>~~|~~<br>~~|~~<br>~~|~~|All MachXO4<br>devices,<br>all sides<br>~~|~~|—<br>~~|~~<br>~~|~~<br>~~a~~|0.317<br>~~|~~<br>~~|~~<br>~~a eee~~|—<br>~~|~~<br>~~|~~<br>~~eee~~|0.344<br>~~|~~<br>~~rT~~<br>~~eee~~|—<br>~~|~~<br>~~rTrT~~<br>~~eee~~|0.344<br>~~|~~<br>~~rT~~<br>~~eee~~|UI<br>~~|~~<br>~~eee~~|
|tDVE<br>~~_ |~~<br>~~_|~~<br>~~_|~~|Input Data Hold<br>After CLK<br>~~|~~<br>~~|~~||0.742<br>~~|~~<br>~~a~~<br>~~ee~~|—<br>~~|~~<br>~~a eee~~<br>~~ee~~|0.702<br>~~|~~<br>~~eee~~<br>~~ee~~|—<br>~~rT~~<br>~~eee~~<br>~~ee~~|0.702<br>~~rT rT~~<br>~~eee~~|—<br>~~rT~~<br>~~eee~~<br>~~ee~~|UI<br>~~eee~~<br>~~ee~~|
|fDATA<br>~~_ |~~<br>~~_|~~<br>~~_~~<br>~~|~~|DDRX1 Input Data<br>Speed<br>~~|~~||—<br>~~a ~~<br>~~ee~~<br>~~a eee~~|300<br> ~~a eee~~<br>~~ee~~<br>~~eee~~|—<br>~~eee~~<br>~~ee~~<br>~~eee~~|250<br>~~eee~~<br>~~ee~~<br>~~eee~~|—<br>~~eee~~<br>~~eee~~|250<br>~~eee~~<br>~~ee~~<br>~~eee~~|Mbps<br>~~eee~~<br>~~ee~~<br>~~eee~~|
|fDDRX1<br>~~_ |~~<br>~~_~~<br>~~|~~<br>~~RC~~|DDRX1 SCLK<br>Frequency||—<br>~~ee~~<br>~~a eee~~|150<br>~~ee~~<br>~~eee~~|—<br>~~ee ~~<br>~~eee~~|125<br> ~~ee~~<br>~~eee~~|—<br>~~eee~~|125<br>~~ee~~<br>~~eee~~|MHz<br>~~ee~~<br>~~eee~~|
|**Generic DDRX1 Inputs with Clock and Data Centered at Pin Using PCLK Pin for Clock Input – GDDRX1_RX.SCLK.Centered8, 9 **<br>~~_~~<br>~~|~~<br>~~a eee~~<br>~~RC~~<br>~~_|~~<br>~~|~~<br>~~|~~<br>~~|~~<br>~~|rT~~||||||||||
|tSU<br>~~RC~~<br>~~_|~~<br>~~_|~~|Input Data Setup<br>Before CLK|All MachXO4<br>devices,<br>all sides|0.566<br>~~|~~<br>~~ee~~|—<br>~~|~~<br>~~ee~~|0.565<br>~~|~~<br>~~ee~~|—<br>~~|~~<br>~~ee~~|0.565<br>~~rT~~|—<br>~~rT~~<br>~~ee~~|Ns<br>~~ee~~|
|tHO<br>~~_ |~~<br>~~_|~~<br>~~_|~~|Input Data Hold<br>After CLK||0.778<br>~~|~~<br>~~ee~~<br>~~ee~~|—<br>~~|~~<br>~~ee~~|0.879<br>~~|~~<br>~~ee~~<br>~~ee~~|—<br>~~| ~~<br>~~ee~~<br>~~ee~~|0.879<br> ~~rT~~<br>~~eee~~|—<br>~~rT~~<br>~~ee~~<br>~~eee~~|ns<br>~~ee~~<br>~~eee~~|
|fDATA<br>~~_ |~~<br>~~_|~~<br>~~_|~~|DDRX1 Input Data<br>Speed||—<br>~~ee~~<br>~~ee~~<br>~~ee~~|300<br>~~ee~~<br>~~ee~~|—<br>~~ee ~~<br>~~ee~~<br>~~ee~~|250<br> ~~ee~~<br>~~ee~~<br>~~ee~~|—<br>~~eee~~<br>~~ee~~|250<br>~~ee~~<br>~~eee~~<br>~~ee~~|Mbps<br>~~ee~~<br>~~eee~~<br>~~ee~~|
|fDDRX1<br>~~_ |~~<br>~~_|~~|DDRX1 SCLK<br>Frequency||—<br>~~ee~~<br>~~ee~~|150<br>~~ee~~|—<br>~~ee~~<br>~~ee~~|125<br>~~ee ~~<br>~~ee~~|—<br> ~~eee~~<br>~~ee~~|125<br>~~eee~~<br>~~ee~~|MHz<br>~~eee~~<br>~~ee~~|



© 2025 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02125-1.0 

63 

**MachXO4 Family Data Sheet** 

|**Parameter**|**Description**|**Device**|**–6**<br>**(Commercial/Industrial)**|**–6**<br>**(Commercial/Industrial)**|**–5**<br>**(Commercial/Industrial)**|**–5**<br>**(Commercial/Industrial)**|**–5**<br>**(Automotive)**|**–5**<br>**(Automotive)**|**Unit**|
|---|---|---|---|---|---|---|---|---|---|
||||**Min.**|**Max.**|**Min.**|**Max.**|**Min.**|**Max.**||
|**Generic DDRX2 Inputs with Clock and Data Aligned at Pin Using PCLK Pin for Clock Input– GDDRX2_RX.ECLK.Aligned8, 9 **<br>~~pf~~<br>~~|~~<br>~~Ff~~<br>~~|~~<br>~~ft~~<br>~~ft~~||||||||||
|tDVA<br>~~pf~~<br>~~pf~~|Input Data Valid<br>After CLK<br>~~pf~~<br>~~pf~~|MachXO4 devices,<br>bottom side only|—<br>~~|~~<br>~~|~~|0.316<br>~~Ff~~<br>~~Ff~~|—<br>~~Ff~~<br>~~|~~<br>~~Ff~~<br>~~|~~|0.342<br>~~ft~~<br>~~ff~~|—<br>~~ft~~<br>~~ft~~<br>~~ff~~<br>~~ft~~|0.342<br>~~ft~~<br>~~ft~~|UI|
|tDVE<br>~~pf~~<br>~~pf~~<br>~~pf~~|Input Data Hold<br>After CLK<br>~~pf~~<br>~~pf~~<br>~~pf~~||0.710<br>~~|~~<br>~~|~~<br>~~|~~|—<br>~~Ff~~<br>~~Ff~~<br>~~Ff~~|0.675<br>~~Ff~~<br>~~|~~<br>~~Ff~~<br>~~|~~<br>~~Ff~~<br>~~|~~|—<br>~~ft~~<br>~~ff~~<br>~~ff~~|0.675<br>~~ft~~<br>~~ft~~<br>~~ff~~<br>~~ft~~<br>~~ff~~<br>~~ft~~|—<br>~~ft~~<br>~~ft~~<br>~~ft~~|UI|
|fDATA<br>~~pf~~<br>~~pf~~<br>~~pf~~|DDRX2 Serial Input<br>Data Speed<br>~~pf~~<br>~~pf~~<br>~~pf~~||—<br>~~|~~<br>~~|~~<br>~~|~~|664<br>~~Ff~~<br>~~Ff~~<br>~~Ff~~|—<br>~~Ff~~<br>~~|~~<br>~~Ff~~<br>~~|~~<br>~~Ff~~<br>~~|~~|554<br>~~ff~~<br>~~ff~~<br>~~ff~~|—<br>~~ff~~<br>~~ft~~<br>~~ff~~<br>~~ft~~<br>~~ff~~<br>~~ft~~|554<br>~~ft~~<br>~~ft~~<br>~~ft~~|Mbps|
|fDDRX2<br>~~pf~~<br>~~pf~~<br>~~Oo~~|DDRX2 ECLK<br>Frequency<br>~~pf~~<br>~~pf~~<br>~~Oo~~||—<br>~~|~~<br>~~|~~|332<br>~~Ff~~<br>~~Ff~~|—<br>~~Ff~~<br>~~|~~<br>~~Ff~~<br>~~|~~|277<br>~~ff~~<br>~~ff~~|—<br>~~ff~~<br>~~ft~~<br>~~ff~~<br>~~ft~~|277<br>~~ft~~<br>~~ft~~|MHz|
|fSCLK<br>~~pf~~<br>~~Oo~~|SCLK Frequency<br>~~pf~~<br>~~Oo~~||—<br>~~|~~|166<br>~~Ff~~|—<br>~~Ff~~<br>~~|~~|139<br>~~ff~~|—<br>~~ff~~<br>~~ft~~|139<br>~~ft~~|MHz|
|**Generic DDRX2 Inputs with Clock and Data Centered at Pin Using PCLK Pin for Clock Input– GDDRX2_RX.ECLK.Centered8, 9 **<br>~~Oo~~<br>~~pf~~<br>~~|~~<br>~~f~~<br>~~|~~<br>~~ft~~<br>~~ft~~||||||||||
|tSU<br>~~Oo~~<br>~~pf~~<br>~~pf~~|Input Data Setup<br>Before CLK<br>~~Oo~~<br>~~pf~~<br>~~pf~~|MachXO4 devices,<br>bottom side only<br>~~On~~|0.233<br>~~|~~<br>~~|~~|—<br>~~f~~<br>~~tf~~|0.233<br>~~|~~<br>~~tf~~<br>~~|~~|—<br>~~ft~~<br>~~|~~|0.233<br>~~ft~~<br>~~ft~~<br>~~ft~~|—<br>~~ft~~<br>~~ft|~~|ns<br>~~|~~|
|tHO<br>~~pf~~<br>~~pf~~<br>~~pf~~|Input Data Hold<br>After CLK<br>~~pf~~<br>~~pf~~<br>~~pf~~||0.287<br>~~|~~<br>~~|~~<br>~~|~~|—<br>~~f~~<br>~~tf~~<br>~~tf~~|0.287<br>~~|~~<br>~~tf~~<br>~~|~~<br>~~tf~~<br>~~|~~|—<br>~~ft~~<br>~~|~~<br>~~|~~|0.287<br>~~ft~~<br>~~ft~~<br>~~ft~~<br>~~ft~~|—<br>~~ft~~<br>~~ft|~~<br>~~ft|~~|ns<br>~~|~~<br>~~|~~|
|fDATA<br>~~pf~~<br>~~pf~~<br>~~pf~~|DDRX2 Serial Input<br>Data Speed<br>~~pf~~<br>~~pf~~<br>~~pf~~||—<br>~~|~~<br>~~|~~<br>~~|~~|664<br>~~tf~~<br>~~tf~~<br>~~tf~~|—<br>~~tf~~<br>~~|~~<br>~~tf~~<br>~~|~~<br>~~tf~~<br>~~|~~|554<br>~~|~~<br>~~|~~<br>~~|~~|—<br>~~ft~~<br>~~ft~~<br>~~ft~~|554<br>~~ft |~~<br>~~ft|~~<br>~~ft|~~|Mbps<br>~~|~~<br>~~|~~<br>~~|~~|
|fDDRX2<br>~~pf~~<br>~~pf~~|DDRX2 ECLK<br>Frequency<br>~~pf~~<br>~~pf~~||—<br>~~|~~<br>~~|~~|332<br>~~tf~~<br>~~tf~~|—<br>~~tf~~<br>~~|~~<br>~~tf~~<br>~~|~~|277<br>~~|~~<br>~~|~~|—<br>~~ft~~<br>~~ft~~|277<br>~~ft |~~<br>~~ft|~~|MHz<br>~~|~~<br>~~|~~|
|fSCLK<br>~~pf~~<br>~~On~~|SCLK Frequency<br>~~pf~~<br>~~On~~||—<br>~~|~~<br>~~On~~|166<br>~~tf~~<br>~~On~~|—<br>~~tf~~<br>~~|~~<br>~~On~~|139<br>~~|~~<br>~~On~~|—<br>~~ft~~<br>~~On~~|139<br>~~ft |~~<br>~~On~~|MHz<br>~~|~~<br>~~On~~|
|**Generic DDR4 Inputs with Clock and Data Aligned at Pin Using PCLK Pin for Clock Input – GDDRX4_RX.ECLK.Aligned8**<br>~~On~~<br>~~|~~<br>~~—|~~<br>~~|~~<br>~~|~~<br>~~ft~~<br>~~|~~||||||||||
|tDVA<br>~~On~~<br>~~|~~<br>~~pf~~|Input Data Valid<br>After ECLK<br>~~On~~<br>~~|~~<br>~~pf~~|MachXO4 devices,<br>bottom side only<br>~~On~~|—<br>~~On~~<br>~~—|~~<br>~~|~~|0.307<br>~~On~~<br>~~|~~<br>~~|~~<br>~~|~~|—<br>~~On~~<br>~~|~~<br>~~|~~|0.320<br>~~On~~<br>~~ft~~<br>~~|~~|—<br>~~On~~<br>~~ft~~<br>~~|~~<br>~~ft~~|0.320<br>~~On~~<br>~~ft|~~|UI<br>~~On~~<br>~~|~~|
|tDVE<br>~~|~~<br>~~pf~~<br>~~pf~~|Input Data Hold<br>After ECLK<br>~~|~~<br>~~pf~~<br>~~pf~~||0.782<br>~~— |~~<br>~~|~~<br>~~tf~~|—<br>~~|~~<br>~~|~~<br>~~|~~<br>~~tf~~<br>~~ft~~|0.699<br>~~|~~<br>~~|~~<br>~~ft~~<br>~~|~~|—<br>~~ft~~<br>~~|~~<br>~~|~~|0.699<br>~~ft~~<br>~~|~~<br>~~ft~~<br>~~ft~~|—<br>~~ft|~~<br>~~ft~~|UI<br>~~|~~|
|fDATA<br>~~pf~~<br>~~pf~~<br>~~pf~~|DDRX4 Serial Input<br>Data Speed<br>~~pf~~<br>~~pf~~<br>~~pf~~||—<br>~~|~~<br>~~tf~~<br>~~tf~~|800<br>~~|~~<br>~~tf~~<br>~~ft~~<br>~~tf~~<br>~~ft~~|—<br>~~|~~<br>~~ft~~<br>~~|~~<br>~~ft~~<br>~~|~~|630<br>~~|~~<br>~~|~~<br>~~|~~|—<br>~~ft~~<br>~~ft~~<br>~~ft~~|630<br>~~ft |~~<br>~~ft~~<br>~~ft~~|Mbps<br>~~|~~|
|fDDRX4<br>~~pf~~<br>~~pf~~<br>~~ee~~|DDRX4 ECLK<br>Frequency<br>~~pf~~<br>~~pf~~||—<br>~~tf~~<br>~~tf~~<br>~~a~~|400<br>~~tf~~<br>~~ft~~<br>~~tf~~<br>~~ft~~<br>~~a~~|—<br>~~ft~~<br>~~|~~<br>~~ft~~<br>~~|~~<br>~~a~~|315<br>~~|~~<br>~~|~~<br>~~a~~|—<br>~~ft~~<br>~~ft~~<br>~~a~~|315<br>~~ft~~<br>~~ft~~<br>~~a~~|MHz<br>~~a~~|
|fSCLK<br>~~pf~~<br>~~ee~~|SCLK Frequency<br>~~pf~~||—<br>~~tf~~<br>~~a~~|100<br>~~tf~~<br>~~ft~~<br>~~a~~|—<br>~~ft~~<br>~~|~~<br>~~a~~|79<br>~~|~~<br>~~a~~|—<br>~~ft~~<br>~~a~~|79<br>~~ft~~<br>~~a~~|MHz<br>~~a~~|
|**Generic DDR4 Inputs with Clock and Data Centered at Pin Using PCLK Pin for Clock Input – GDDRX4_RX.ECLK.Centered8**<br>~~ee~~<br>~~a~~<br>~~|~~<br>~~—|~~<br>~~|~~<br>~~ft~~<br>~~ft|~~||||||||||
|tSU<br>~~|~~<br>~~pf~~|Input Data Setup<br>Before ECLK<br>~~|~~<br>~~pf~~|MachXO4 devices,<br>bottom side only|0.233<br>~~—|~~<br>~~tf~~|—<br>~~|~~<br>~~|~~<br>~~tf~~<br>~~ft~~|0.233<br>~~ft~~<br>~~ft~~<br>~~|~~|—<br>~~ft~~<br>~~ft~~<br>~~|~~|0.233<br>~~ft|~~<br>~~ft~~|—<br>~~ft~~|ns|
|tHO<br>~~|~~<br>~~pf~~<br>~~pf~~|Input Data Hold<br>After ECLK<br>~~|~~<br>~~pf~~<br>~~pf~~||0.287<br>~~— |~~<br>~~tf~~<br>~~tf~~|—<br>~~|~~<br>~~|~~<br>~~tf~~<br>~~ft~~<br>~~tf~~<br>~~ft~~|0.287<br>~~ft~~<br>~~ft~~<br>~~|~~<br>~~ft~~<br>~~|~~|—<br>~~ft~~<br>~~ft~~<br>~~|~~<br>~~|~~|0.287<br>~~ft |~~<br>~~ft~~<br>~~ft~~|—<br>~~ft~~<br>~~ft~~|ns|
|fDATA<br>~~pf~~<br>~~pf~~<br>~~pf~~|DDRX4 Serial Input<br>Data Speed<br>~~pf~~<br>~~pf~~<br>~~pf~~||—<br>~~tf~~<br>~~tf~~<br>~~tf~~|800<br>~~tf~~<br>~~ft~~<br>~~tf~~<br>~~ft~~<br>~~tf~~<br>~~ft~~|—<br>~~ft~~<br>~~|~~<br>~~ft~~<br>~~|~~<br>~~ft~~<br>~~|~~|630<br>~~|~~<br>~~|~~<br>~~|~~|—<br>~~ft~~<br>~~ft~~<br>~~ft~~|630<br>~~ft~~<br>~~ft~~<br>~~ft~~|Mbps|
|fDDRX4<br>~~pf~~<br>~~pf~~<br>~~a~~|DDRX4 ECLK<br>Frequency<br>~~pf~~<br>~~pf~~||—<br>~~tf~~<br>~~tf~~<br>~~ee~~|400<br>~~tf~~<br>~~ft~~<br>~~tf~~<br>~~ft~~|—<br>~~ft~~<br>~~|~~<br>~~ft~~<br>~~|~~|315<br>~~|~~<br>~~|~~|—<br>~~ft~~<br>~~ft~~|315<br>~~ft~~<br>~~ft~~|MHz|
|fSCLK<br>~~pf~~<br>~~a~~|SCLK Frequency<br>~~pf~~||—<br>~~tf~~<br>~~ee~~|100<br>~~tf~~<br>~~ft~~|—<br>~~ft~~<br>~~|~~|79<br>~~|~~|—<br>~~ft~~|79<br>~~ft~~|MHz|



© 2025 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02125-1.0 

64 

**MachXO4 Family Data Sheet** 

|**Parameter**<br>~~ef~~|**Description**<br>~~ef~~|**Device**<br>~~ef~~|**–6**<br>**(Commercial/Industrial)**<br>~~ef~~|**–6**<br>**(Commercial/Industrial)**<br>~~ef~~|**–5**<br>**(Commercial/Industrial)**<br>~~ef~~|**–5**<br>**(Commercial/Industrial)**<br>~~ef~~|**–5**<br>**(Automotive)**<br>~~ef~~|**–5**<br>**(Automotive)**<br>~~ef~~|**Unit**<br>~~ef~~|
|---|---|---|---|---|---|---|---|---|---|
||||**Min.**<br>~~ef~~<br>~~a~~|**Max.**<br>~~ef~~|**Min.**<br>~~ef~~|**Max.**<br>~~ef~~|**Min.**<br>~~ef~~|**Max.**<br>~~ef~~||
|**7:1 LVDS Inputs(GDDR71_RX.ECLK.7:1)9**<br>~~ef~~<br>~~a~~<br>~~|~~<br>~~|~~<br>~~|~~<br>~~|~~<br>~~ft~~<br>~~ft|~~||||||||||
|tDVA<br>~~|~~<br>~~|~~|Input Data Valid<br>After ECLK<br>~~|~~<br>~~|~~|MachXO4 devices,<br>bottom side only|—<br>~~|~~<br>~~|~~|0.290<br>~~|~~<br>~~|~~|—<br>~~|~~<br>~~|~~|0.320<br>~~ft~~<br>~~|~~|—<br>~~ft~~<br>~~ft~~<br>~~ft~~|0.257<br>~~ft|~~<br>~~ft~~|UI|
|tDVE<br>~~|~~<br>~~|~~<br>~~|~~|Input Data Hold<br>After ECLK<br>~~|~~<br>~~|~~<br>~~|~~||0.739<br>~~|~~<br>~~|~~<br>~~|~~|—<br>~~|~~<br>~~|~~<br>~~|~~|0.699<br>~~|~~<br>~~|~~<br>~~|~~|—<br>~~ft~~<br>~~|~~<br>~~|~~|0.699<br>~~ft~~<br>~~ft~~<br>~~ft~~<br>~~ft~~|—<br>~~ft |~~<br>~~ft~~<br>~~ft~~|UI|
|fDATA<br>~~|~~<br>~~|~~|DDR71 Serial Input<br>Data Speed<br>~~|~~<br>~~|~~||—<br>~~|~~<br>~~|~~|756<br>~~|~~<br>~~|~~|—<br>~~|~~<br>~~|~~|630<br>~~|~~<br>~~|~~|—<br>~~ft~~<br>~~ft~~|630<br>~~ft~~<br>~~ft~~|Mbps|
|fDDR71<br>~~|~~|DDR71 ECLK<br>Frequency<br>~~|~~||—<br>~~|~~|378<br>~~|~~|—<br>~~|~~|315<br>~~|~~|—<br>~~ft~~|315<br>~~ft~~|MHz|
|fCLKIN|7:1 Input Clock<br>Frequency (SCLK)<br>(minimum limited<br>byPLL)||—|108|—|90|—|90|MHz|
|**MIPI D-PHY Inputs with Clock and Data Centered at Pin Using PCLK Pin for Clock Input - GDDRX4_RX.ECLK.Centered10, 11, 12 **<br>~~En~~<br>~~|~~<br>~~|~~<br>~~|~~<br>~~|~~<br>~~ftff~~||||||||||
|tSU15<br>~~En~~<br>~~|~~|Input Data Setup<br>Before ECLK<br>~~En~~<br>~~|~~|All MachXO4<br>devices,<br>bottom side only<br>~~En~~|0.200<br>~~En~~<br>~~|~~|—<br>~~En~~<br>~~|~~|0.200<br>~~En~~<br>~~|~~|—<br>~~En~~<br>~~ft~~|0.295<br>~~En~~<br>~~ftff~~|—<br>~~En~~<br>~~ff~~|UI<br>~~En~~|
|tHO15<br>~~|~~<br>~~|~~|Input Data Hold<br>After ECLK<br>~~|~~<br>~~|~~||0.200<br>~~|~~<br>~~|~~|—<br>~~|~~<br>~~|~~|0.200<br>~~|~~<br>~~|~~|—<br>~~ft~~<br>~~ff~~|0.312<br>~~ft ff~~<br>~~ff~~|—<br>~~ff~~<br>~~|~~|UI|
|fDATA14<br>~~|~~<br>~~|~~|MIPI D-PHY Input<br>Data Speed<br>~~|~~<br>~~|~~||—<br>~~|~~<br>~~|~~|900<br>~~|~~<br>~~|~~|—<br>~~|~~<br>~~|~~|900<br>~~ff~~<br>~~ff~~|—<br>~~ff~~<br>~~ff~~|900<br>~~|~~<br>~~|~~|Mbps|
|fDDRX414<br>~~|~~<br>~~|~~|MIPI D-PHY ECLK<br>Frequency<br>~~|~~<br>~~|~~||—<br>~~|~~<br>~~|~~|450<br>~~|~~<br>~~|~~|—<br>~~|~~<br>~~|~~|450<br>~~ff~~<br>~~ff~~|—<br>~~ff~~<br>~~ff~~|450<br>~~|~~<br>~~|~~|MHz|
|fSCLK14<br>~~|~~<br>~~a~~|SCLK Frequency<br>~~|~~||—<br>~~|~~<br>~~se~~|112.5<br>~~|~~<br>~~se~~|—<br>~~|~~<br>~~se~~|112.5<br>~~ff~~<br>~~se~~|—<br>~~ff~~<br>~~se~~|112.5<br>~~|~~<br>~~se~~|MHz<br>~~se~~|
|**Generic DDR Outputs with Clock and Data Aligned at Pin Using PCLK Pin for Clock Input – GDDRX1_TX.SCLK.Aligned8 **<br>~~a~~<br>~~se~~<br>~~En~~||||||||||
|tDIA<br>~~En~~<br>~~ae~~|Output Data<br>Invalid After CLK<br>Output<br>~~En~~<br>~~ae~~|All MachXO4<br>devices,<br>all sides<br>~~En~~<br>~~ae~~|—<br>~~En~~<br>~~ae~~|0.520<br>~~En~~<br>~~ae~~|—<br>~~En~~<br>~~ae~~|0.550<br>~~En~~<br>~~ae~~|—<br>~~En~~<br>~~ae~~|0.550<br>~~En~~<br>~~ae~~|ns<br>~~En~~<br>~~ae~~|
|tDIB<br>~~ae~~|Output Data<br>Invalid Before CLK<br>Output<br>~~ae~~||—<br>~~ae~~|0.520<br>~~ae~~|—<br>~~ae~~|0.550<br>~~ae~~|—<br>~~ae~~|0.550<br>~~ae~~|ns<br>~~ae~~|
|fDATA<br>~~ae~~<br>~~|~~<br>~~|~~|DDRX1 Output<br>Data Speed<br>~~ae~~||—<br>~~ae~~<br>~~fF~~|300<br>~~ae~~<br>~~fF~~<br>~~|~~|—<br>~~ae~~<br>~~|~~|250<br>~~ae~~<br>~~TT~~|—<br>~~ae~~<br>~~TT~~|250<br>~~ae~~<br>~~TT~~|Mbps<br>~~ae~~<br>~~TT~~|
|fDDRX1<br>~~ae~~<br>~~|~~<br>~~|~~|DDRX1 SCLK<br>frequency<br>~~ae~~||—<br>~~ae~~<br>~~fF~~|150<br>~~ae~~<br>~~fF~~<br>~~|~~|—<br>~~ae~~<br>~~|~~|125<br>~~ae~~<br>~~TT~~|—<br>~~ae~~<br>~~TT~~|125<br>~~ae~~<br>~~TT~~|MHz<br>~~ae~~<br>~~TT~~|
|**Generic DDR Outputs with Clock and Data Centered at Pin Using PCLK Pin for Clock Input– GDDRX1_TX.SCLK.Centered8 **<br>~~ae~~<br>~~|~~<br>~~|~~<br>~~fF~~<br>~~|~~<br>~~|TT~~<br>~~|~~<br>~~|~~<br>~~|~~<br>~~|~~<br>~~fTft~~||||||||||
|tDVB<br>~~|~~<br>~~|~~|Output Data Valid<br>Before CLK Output<br>~~|~~<br>~~|~~|All MachXO4<br>devices,<br>all sides|1.210<br>~~|~~<br>~~|~~|—<br>~~|~~<br>~~|~~|1.510<br>~~|~~<br>~~|~~|—<br>~~fT~~<br>~~|~~|1.510<br>~~fTft~~<br>~~ft~~|—<br>~~ft~~<br>~~ft~~|ns|
|tDVA<br>~~|~~<br>~~|~~|Output Data Valid<br>After CLK Output<br>~~|~~<br>~~|~~||1.210<br>~~|~~<br>~~|~~|—<br>~~|~~<br>~~|~~|1.510<br>~~|~~<br>~~|~~|—<br>~~fT~~<br>~~|~~|1.510<br>~~fT ft~~<br>~~ft~~|—<br>~~ft~~<br>~~ft~~|ns|
|fDATA<br>~~|~~|DDRX1 Output<br>Data Speed<br>~~|~~||—<br>~~|~~|300<br>~~|~~|—<br>~~|~~|250<br>~~|~~|—<br>~~ft~~|250<br>~~ft~~|Mbps|
|fDDRX1|DDRX1 SCLK<br>Frequency<br>(minimum limited<br>byPLL)||—|150|—|125|—|125|MHz|



© 2025 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02125-1.0 

65 

**MachXO4 Family** 

**Data Sheet** 

|**Parameter**<br>~~ee~~<br>~~Rn~~|**Description**<br>~~ee~~<br>~~Rn~~|**Device**<br>~~ee~~|**–6**<br>**(Commercial/Industrial)**<br>~~ee~~<br>~~ee~~|**–6**<br>**(Commercial/Industrial)**<br>~~ee~~<br>~~ee~~|**–5**<br>**(Commercial/Industrial)**<br>~~ee~~|**–5**<br>**(Commercial/Industrial)**<br>~~ee~~|**–5**<br>**(Automotive)**<br>~~ee~~|**–5**<br>**(Automotive)**<br>~~ee~~|**Unit**<br>~~ee~~|
|---|---|---|---|---|---|---|---|---|---|
||||**Min.**<br>~~ee~~<br>~~ee~~|**Max.**<br>~~ee~~|**Min.**<br>~~ee~~|**Max.**<br>~~ee~~|**Min.**<br>~~ee~~|**Max.**<br>~~ee~~||
|**Generic DDRX2 Outputs with Clock and Data Aligned at Pin Using PCLK Pin for Clock Input– GDDRX2_TX.ECLK.Aligned8 **<br>~~ee~~<br>~~ee~~<br>~~Rn~~||||||||||
|tDIA<br>~~Rn~~|Output Data<br>Invalid After CLK<br>Output<br>~~Rn~~|MachXO4 devices,<br>top side only|—<br>~~ee~~|0.200|—|0.215|—|0.215|ns|
|tDIB|Output Data<br>Invalid Before CLK<br>Output||—|0.200|—|0.215|—|0.215|ns|
|fDATA<br>~~|~~|DDRX2 Serial<br>Output Data Speed<br>~~|~~||—<br>~~|~~|664<br>||—<br>||554<br>lm|—<br>lm|554|Mbps|
|fDDRX2<br>~~|~~<br>~~ee~~|DDRX2 ECLK<br>frequency<br>~~|~~<br>~~eee~~||—<br>~~|~~<br>~~es~~|332<br>|<br>~~es~~|—<br>|<br>~~es~~|277<br>lm<br>~~ee~~|—<br>lm|277|MHz|
|fSCLK<br>~~ee~~<br>~~Re~~|SCLK Frequency<br>~~eee~~<br>~~Re~~||—<br>~~es~~|166<br>~~es~~|—<br>~~es~~|139<br>~~ee~~|—|139|MHz|
|**Generic DDRX2 Outputs with Clock and Data Centered at Pin Using PCLK Pin for Clock Input – GDDRX2_TX.ECLK.Centered8, 9**<br>~~ee eee~~<br>~~es~~<br>~~es~~<br>~~es ee~~<br>~~Re~~<br>~~_|~~<br>~~eseee~~||||||||||
|tDVB<br>~~Re~~<br>~~_|~~<br>~~_|~~|Output Data Valid<br>Before CLK Output<br>~~Re~~|MachXO4 devices,<br>top side only<br>~~eee~~|0.535<br>~~es~~<br>~~eee~~|—<br>~~eee~~<br>~~eee~~|0.670<br>~~eee~~<br>~~eee~~|—<br>~~eee~~<br>~~eee~~|0.670<br>~~eee~~<br>~~eee~~|—<br>~~eee~~<br>~~eee~~|ns<br>~~eee~~<br>~~eee~~|
|tDVA<br>~~_ |~~<br>~~_|~~|Output Data Valid<br>After CLK Output||0.535<br>~~es~~<br>~~eee~~|—<br>~~eee~~<br>~~eee~~|0.670<br>~~eee~~<br>~~eee~~|—<br>~~eee~~<br>~~eee~~|0.658<br>~~eee~~<br>~~eee~~|—<br>~~eee~~<br>~~eee~~|ns<br>~~eee~~<br>~~eee~~|
|fDATA<br>~~_ |~~<br>~~|~~|DDRX2 Serial<br>Output Data Speed||—<br>~~eee~~<br>~~CEE~~|664<br>~~eee~~<br>~~CEE~~|—<br>~~eee~~<br>~~CEE~~|554<br>~~eee~~<br>~~CEE~~|—<br>~~eee~~<br>~~CEE~~|554<br>~~eee~~<br>~~CEE~~|Mbps<br>~~eee~~<br>~~CEE~~|
|fDDRX2<br>~~|~~<br>~~ee~~|DDRX2 ECLK<br>Frequency<br>(minimum limited<br>byPLL)<br>~~eee~~||—<br>~~CEE~~<br>~~ee~~|332<br>~~CEE~~<br>~~es~~|—<br>~~CEE~~<br>~~ee~~|277<br>~~CEE~~|—<br>~~CEE~~|277<br>~~CEE~~|MHz<br>~~CEE~~|
|fSCLK<br>~~|~~<br>~~ee~~|SCLK Frequency<br>~~eee~~||—<br>~~CEE~~<br>~~ee~~|166<br>~~CEE~~<br>~~es~~|—<br>~~CEE~~<br>~~ee~~|139<br>~~CEE~~|—<br>~~CEE~~|139<br>~~CEE~~|MHz<br>~~CEE~~|
|**Generic DDRX4 Outputs with Clock and Data Aligned at Pin Using PCLK Pin for Clock Input– GDDRX4_TX.ECLK.Aligned8, 9 **<br>~~ee eee~~<br>~~ee es ee~~<br>~~Re~~||||||||||
|tDIA<br>~~Re~~|Output Data<br>Invalid After CLK<br>Output<br>~~Re~~|MachXO4 devices,<br>top side only<br>~~Re~~<br>~~eee~~|—<br>~~Re~~|0.200<br>~~Re~~|—<br>~~Re~~|0.215<br>~~Re~~|—<br>~~Re~~|0.215<br>~~Re~~|ns<br>~~Re~~|
|tDIB<br>~~_|~~|Output Data<br>Invalid Before CLK<br>Output<br>~~|~~||—<br>~~a~~|0.200<br>~~a eee~~|—<br>~~eee~~|0.215<br>~~eee~~|—<br>~~eee~~|0.215<br>~~eee~~|ns<br>~~eee~~|
|fDATA<br>~~_|~~<br>~~_|~~|DDRX4 Serial<br>Output Data Speed<br>~~|~~||—<br>~~a~~<br>~~ee~~|800<br>~~a eee~~<br>~~ee~~|—<br>~~eee~~<br>~~ee~~|630<br>~~eee~~<br>~~ee~~|—<br>~~eee~~|630<br>~~eee~~<br>~~ee~~|Mbps<br>~~eee~~<br>~~ee~~|
|fDDRX4<br>~~_ |~~<br>~~_|~~<br>~~ee~~|DDRX4 ECLK<br>Frequency<br>~~|~~<br>~~eee~~||—<br>~~a ~~<br>~~ee~~<br>~~ee~~|400<br> ~~a eee~~<br>~~ee~~<br>~~ee~~|—<br>~~eee~~<br>~~ee~~<br>~~ee~~|315<br>~~eee~~<br>~~ee~~<br>~~se~~|—<br>~~eee~~<br>~~se~~|315<br>~~eee~~<br>~~ee~~<br>~~ee~~|MHz<br>~~eee~~<br>~~ee~~|
|fSCLK<br>~~_ |~~<br>~~ee~~<br>~~RC~~|SCLK Frequency<br>~~eee~~<br>~~RC~~||—<br>~~ee~~<br>~~ee~~|100<br>~~ee~~<br>~~ee~~|—<br>~~ee ~~<br>~~ee~~|79<br> ~~ee~~<br>~~se~~|—<br>~~se~~|79<br>~~ee~~<br>~~ee~~|MHz<br>~~ee~~|
|**Generic DDRX4 Outputs with Clock and Data Centered at Pin Using PCLK Pin for Clock Input – GDDRX4_TX.ECLK.Centered8, 9**<br>~~ee eee~~<br>~~ee ee ee~~<br>~~se ee~~<br>~~RC~~<br>~~_|~~<br>~~|~~<br>~~|~~<br>~~|~~<br>~~|~~<br>~~rTrT~~||||||||||
|tDVB<br>~~RC~~<br>~~_|~~<br>~~_|~~|Output Data Valid<br>Before CLK Output<br>~~RC~~<br>~~|~~<br>~~|~~|MachXO4 devices,<br>top side only<br>~~eee~~|0.455<br>~~|~~<br>~~ee~~|—<br>~~|~~<br>~~ee~~|0.570<br>~~|~~<br>~~ee~~|—<br>~~rT~~<br>~~ee~~|0.570<br>~~rTrT~~<br>~~eee~~|—<br>~~rT~~<br>~~eee~~|ns<br>~~eee~~|
|tDVA<br>~~_ |~~<br>~~_|~~|Output Data Valid<br>After CLK Output<br>~~|~~<br>~~|~~||0.455<br>~~|~~<br>~~ee~~|—<br>~~|~~<br>~~ee~~|0.570<br>~~|~~<br>~~ee~~|—<br>~~rT~~<br>~~ee~~|0.549<br>~~rT rT~~<br>~~eee~~|—<br>~~rT~~<br>~~eee~~|ns<br>~~eee~~|
|fDATA<br>~~_ |~~<br>~~|~~|DDRX4 Serial<br>Output Data Speed<br>~~|~~||—<br>~~ee~~<br>~~CEE~~|800<br>~~ee~~<br>~~CEE~~|—<br>~~ee ~~<br>~~CEE~~|630<br> ~~ee~~<br>~~CEE~~|—<br>~~eee~~<br>~~CEE~~|630<br>~~eee~~<br>~~CEE~~|Mbps<br>~~eee~~<br>~~CEE~~|
|fDDRX4<br>~~|~~<br>~~ee~~|DDRX4 ECLK<br>Frequency<br>(minimum limited<br>byPLL)<br>~~eee~~||—<br>~~CEE~~<br>~~ee~~|400<br>~~CEE~~<br>~~es~~|—<br>~~CEE~~<br>~~ee~~|315<br>~~CEE~~<br>~~ee~~|—<br>~~CEE~~|315<br>~~CEE~~|MHz<br>~~CEE~~|
|fSCLK<br>~~|~~<br>~~ee~~|SCLK Frequency<br>~~eee~~||—<br>~~CEE~~<br>~~ee~~|100<br>~~CEE~~<br>~~es~~|—<br>~~CEE~~<br>~~ee~~|79<br>~~CEE~~<br>~~ee~~|—<br>~~CEE~~|79<br>~~CEE~~|MHz<br>~~CEE~~|



© 2025 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02125-1.0 

66 

**MachXO4 Family Data Sheet** 

|**Parameter**<br>~~ee~~|**Description**<br>~~ee~~|**Device**<br>~~ee~~|**–6**<br>**(Commercial/Industrial)**<br>~~ee~~|**–6**<br>**(Commercial/Industrial)**<br>~~ee~~|**–5**<br>**(Commercial/Industrial)**<br>~~ee~~|**–5**<br>**(Commercial/Industrial)**<br>~~ee~~|**–5**<br>**(Automotive)**<br>~~ee~~|**–5**<br>**(Automotive)**<br>~~ee~~|**Unit**<br>~~ee~~|
|---|---|---|---|---|---|---|---|---|---|
||||**Min.**<br>~~ee~~<br>~~a~~|**Max.**<br>~~ee~~|**Min.**<br>~~ee~~|**Max.**<br>~~ee~~|**Min.**<br>~~ee~~|**Max.**<br>~~ee~~||
|**7:1 LVDS Outputs – GDDR71_TX.ECLK.7:18, 9**<br>~~ee~~<br>~~a~~||||||||||
|tDIB|Output Data<br>Invalid Before CLK<br>Output|MachXO4 devices,<br>top side only|—|0.160|—|0.180|—|0.180|ns|
|tDIA|Output Data<br>Invalid After CLK<br>Output||—|0.160|—|0.180|—|0.201|ns|
|fDATA<br>~~es~~|DDR71 Serial<br>Output Data Speed<br>~~es~~||—<br>~~OO~~|756<br>~~OO~~|—<br>~~OO~~|630<br>~~OO~~|—<br>~~OO~~|630<br>~~OO~~|Mbps<br>~~OO~~|
|fDDR71|DDR71 ECLK<br>Frequency||—|378|—|315|—|315|MHz|
|fCLKOUT|7:1 Output Clock<br>Frequency (SCLK)<br>(minimum limited<br>byPLL)||—|108|—|90|—|90|MHz|
|**MIPI D-PHY Outputs with Clock and Data Centered at Pin Using PCLK Pin for Clock Input– GDDRX4_TX.ECLK.Centered10, 11, 12 **||||||||||
|tDVB<br>~~a~~|Output Data Valid<br>Before CLK Output<br>~~a~~|All MachXO4<br>devices, top side<br>only|0.200|—|0.200|—|0.200|—|UI|
|tDVA<br>~~a~~<br>~~i~~|Output Data Valid<br>After CLK Output<br>~~a~~<br>~~i~~||0.200|—|0.200|—|0.200|—|UI|
|fDATA<br>~~i~~|MIPI D-PHY Output<br>Data Speed<br>~~i~~||—|900|—|900|—|900|Mbps|
|FDDRX4|MIPI D-PHY ECLK<br>Frequency<br>(minimum limited<br>byPLL)||—|450|—|450|—|450|MHz|
|fSCLK<br>~~a~~|SCLK Frequency<br>~~a~~||—<br>~~a~~|112.5|—|112.5|—|112.5|MHz|



**Notes** : 

1. Exact performance may vary with device and design implementation. Commercial timing numbers are shown at 85 °C and 1.14 V. Other operating conditions, including industrial, can be extracted from the Radiant software. 

2. General I/O timing numbers based on LVCMOS 2.5, 8 mA, 0pf load, fast slew rate. 

3. Generic DDR timing numbers based on LVDS I/O (for input, output, and clock ports). 

4. 7:1 LVDS (GDDR71) uses the LVDS I/O standard (for input, output, and clock ports). 

5. For Generic DDRX1 mode tSU = tHO = (tDVE - tDVA - 0.03 ns)/2. 

6. The tSU_DEL and tH_DEL values use the SCLK_ZERHOLD default step size. Each step is 105 ps (–6), 113 ps (–5), 120 ps (–4). 

7. This number for general purpose usage. Duty cycle tolerance is +/–10%. 

8. Duty cycle is +/– 5% for system usage. 

9. Performance is calculated with 0.225 UI. 

10. Performance is calculated with 0.20 UI. 

11. Performance for Industrial devices are only supported with VCC between 1.16 V to 1.24 V. 

12. Performance for Industrial devices and –5 devices are not modeled in the Radiant design tool. 

13. The above timing numbers are generated using the Radiant design tool. Exact performance may vary with the device selected. 

14. Above 800 Mbps is only supported with WLCSP and csfBGA packages. 

15. Between 800 Mbps to 900 Mbps: 

   - VIDTH exceeds the MIPI D-PHY Input DC Conditions (Table 3.16) and can be calculated with the equation tSU or tH = –0.0005*VIDTH + 0.3284 

   - Example calculations: 

   - tSU and tHO = 0.28 with VIDTH = 100 mV 

   - tSU and tHO = 0.25 with VIDTH = 170 mV 

   - tSU and tHO = 0.20 with VIDTH = 270 mV 

© 2025 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02125-1.0 

67 

**MachXO4 Family Data Sheet** 

**==> picture [301 x 159] intentionally omitted <==**

**----- Start of picture text -----**<br>
CLK<br>l<br>Data XX 0 _XYXXX 1 XXX _XXAXX 2 3 XXX 4 XXX 5 XXX 6 XXX 0 YX<br>(4-6 bits)<br>|— tDVA<br>tDVE<br>Figure 3.7.Receiver GDDR71_RX. Waveforms<br>CLK<br>oe<br>Data | ]<br>(4-6 bits) 0 1 2 3 4 5 6 0<br>j Xo ANAX AXA AANA XA WA t X DIB<br>tDIA<br>**----- End of picture text -----**<br>


**Figure 3.8. Transmitter GDDR71_TX. Waveforms** 

© 2025 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02125-1.0 

68 

**MachXO4 Family Data Sheet** 

## **3.18. sysCLOCK PLL Timing** 

Over recommended operating conditions. 

**Table 3.23. sysCLOCK PLL Timing** 

|**Parameter**<br>~~To~~<br>~~a~~|**Descriptions**<br>~~To~~<br>|**Condition**<br>~~To~~<br>|**–6**<br>**(Commercial/Industrial)**<br>~~To~~<br>~~ee~~<br>|**–6**<br>**(Commercial/Industrial)**<br>~~To~~<br>~~ee~~<br>|**–5**<br>**(Automotive)**<br>~~To~~<br>~~eeee~~<br>|**–5**<br>**(Automotive)**<br>~~To~~<br>~~eeee~~<br>|**Unit**<br>~~To~~<br>|
|---|---|---|---|---|---|---|---|
||||**Min.**<br>~~To~~<br>~~es~~<br>|**Max.**<br>~~To~~<br>~~es~~<br>~~ee~~<br>|**Min.**<br>~~To~~<br>~~es~~<br>~~ee~~<br>|**Max.**<br>~~To~~<br>~~es~~<br>~~ee~~<br>||
|fIN<br>~~a ee~~|Input Clock Frequency<br>(CLKI,CLKFB)<br>~~ee~~|—<br>~~ee~~|7<br>~~ee~~|400<br>~~ee~~ <br>~~ee~~|7<br> ~~ee~~ <br>~~ee~~|400<br> ~~ee~~<br>~~ee~~|MHz<br>~~ee~~|
|fOUT<br>~~a ee~~|Output Clock Frequency<br>(CLKOP,CLKOS,CLKOS2)<br>~~ee~~|—<br>~~ee~~|1.5625<br>~~ee~~|400<br>~~ee~~|1.5625<br>~~ee~~|400<br>~~ee~~|MHz<br>~~ee~~|
|fOUT2<br>~~a ee~~<br>~~a~~|Output Frequency (CLKOS3<br>cascaded from CLKOS2)<br>~~ee~~<br>|—<br>~~ee~~<br>|0.0122<br>~~ee~~<br>~~GQ~~<br>|400<br>~~ee~~<br>~~GQ~~<br>|0.0122<br>~~ee~~<br>|400<br>~~ee~~<br>|MHz<br>~~ee~~<br>|
|fVCO<br>~~eG~~<br>~~a~~|PLL VCO Frequency<br>~~eG~~<br>|—<br>~~eG~~<br>|200<br>~~eG~~<br>~~GQ~~<br>|800<br>~~eG~~<br>~~GQ~~<br>|200<br>~~eG~~<br>|800<br>~~eG~~<br>|MHz<br>~~eG~~<br>|
|fPFD<br>~~a~~|Phase Detector Input<br>Frequency<br>~~ee~~|—<br>~~ee~~|7<br>~~GQ~~<br>~~ee~~|400<br>~~GQ~~<br>~~ee~~|7<br>~~ee~~|400<br>~~ee~~|MHz<br>~~ee~~|
|**AC Characteristics**<br>~~|~~||||||||
|tDT<br>~~a~~|Output Clock Duty Cycle<br>~~a~~<br>~~ee~~|Without duty trim<br>selected3<br>~~a~~<br>~~ee~~|45<br>~~a~~<br>~~ee~~|55<br>~~a~~<br>~~ee~~|45<br>~~a~~<br>~~ee~~|55<br>~~a~~<br>~~ee~~|%<br>~~a~~<br>~~ee~~|
|tDT_TRIM7<br>~~GGG~~<br>~~i ee~~|Edge DutyTrim Accuracy<br>~~GGG~~<br>~~ee~~|—<br>~~GGG~~<br>~~Qs~~|–75<br>~~GGG~~<br>~~Qs~~|75<br>~~GGG~~<br>~~Qs~~|N/A<br>~~GGG~~<br>~~Qs~~|N/A<br>~~GGG~~<br>~~Qs~~|%<br>~~GGG~~<br>~~Qs~~|
|tPH4<br>~~i ee~~|Output Phase Accuracy<br>~~ee~~|—<br>~~Qs~~|–6<br>~~Qs~~<br>~~ee~~|6<br>~~Qs~~<br>~~ee~~|–6<br>~~Qs~~<br>~~eee~~|6<br>~~Qs~~<br>~~eee~~|%<br>~~Qs~~<br>~~eee~~|
|tOPJIT1, 8<br>~~i ee~~|Output Clock Period Jitter<br>~~ee~~<br>~~ee~~<br>~~es~~|fOUT > 100 MHz<br>~~Qs~~<br>~~ee~~<br>~~s~~|—<br>~~Qs~~<br>~~ee~~<br>~~ee~~<br>~~es~~<br>|150<br>~~Qs~~<br>~~ee~~<br>~~ee~~<br>~~es~~<br>|—<br>~~Qs~~<br>~~ee~~<br>~~eee~~|150<br>~~Qs~~<br>~~ee~~<br>~~eee~~|psp-p<br>~~Qs~~<br>~~ee~~<br>~~eee~~|
|||fOUT < 100 MHz<br>~~ee~~<br>~~es~~<br>~~s~~|—<br>~~ee~~<br>~~ee~~<br>~~es~~<br>~~es~~<br>~~GEnEenE~~|0.007<br>~~ee~~<br>~~ee~~<br>~~es~~<br>~~es~~<br>~~GEnEenE~~|—<br>~~ee~~<br>~~eee~~<br>~~es~~|0.010<br>~~ee~~<br>~~eee~~<br>~~es~~|UIPP<br>~~ee~~<br>~~eee~~<br>~~es~~|
||Output Clock Cycle-to-cycle<br>Jitter<br>~~es~~<br>~~es~~|fOUT > 100 MHz<br>~~s~~<br>~~s~~|—<br>~~ee~~<br>~~es~~<br>~~GEnEenE~~<br>~~es~~|180<br>~~ee ~~<br>~~es~~<br>~~GEnEenE~~<br>~~es~~|—<br> ~~eee~~|180<br>~~eee~~|psp-p<br>~~eee~~|
|||fOUT < 100 MHz<br>~~s~~<br>~~es~~<br>~~s~~|—<br>~~es~~<br>~~GEnEenE~~<br>~~es~~<br>~~es~~|0.009<br>~~es~~<br>~~GEnEenE~~<br>~~es~~<br>~~es~~|—<br>~~es~~|0.015<br>~~es~~|UIPP<br>~~es~~|
||Output Clock Phase Jitter<br>~~es~~<br>~~es~~<br>~~_——————EE~~|fPFD > 100 MHz<br>~~s ~~<br>~~s~~|—<br>~~es~~<br> ~~GEnEenE~~<br>~~es~~|160<br>~~es~~<br>~~GEnEenE~~<br>~~es~~|—|160|psp-p|
|||fPFD < 100 MHz<br>~~s~~<br>~~es~~<br>~~—————EE~~|—<br>~~es~~<br>~~es~~<br>~~—————EE~~|0.011<br>~~es~~<br>~~es~~<br>~~—————EE~~|—<br>~~es~~<br>~~—————EE~~|0.011<br>~~es~~<br>~~—————EE~~|UIPP<br>~~es~~<br>~~—————EE~~|
||Output Clock Period Jitter<br>(Fractional-N)<br>~~es~~<br>~~_——————EE~~<br>~~Bf~~|fOUT > 100 MHz<br>~~s~~<br>~~es~~<br>~~—————EE~~<br>~~Bf~~|—<br>~~es~~<br>~~es~~<br>~~—————EE~~<br>~~es~~|230<br>~~es~~<br>~~es~~<br>~~—————EE~~<br>~~es~~|—<br>~~es~~<br>~~—————EE~~|TBD<br>~~es~~<br>~~—————EE~~|psp-p<br>~~es~~<br>~~—————EE~~|
|||fOUT < 100 MHz<br>~~—————EE~~<br>~~es~~<br>~~Bf~~|—<br>~~—————EE~~<br>~~es~~<br>~~es~~|0.12<br>~~—————EE~~<br>~~es~~<br>~~es~~|—<br>~~—————EE~~<br>~~es~~|TBD<br>~~—————EE~~<br>~~es~~|UIPP<br>~~—————EE~~<br>~~es~~|
||Output Clock Cycle-to-cycle<br>Jitter (Fractional-N)<br>~~_——————EE~~<br>~~Bf~~|fOUT > 100 MHz<br>~~—————EE~~<br>~~Bf~~|—<br>~~—————EE~~<br>~~es~~|230<br>~~—————EE~~<br>~~es~~|—<br>~~—————EE~~|TBD<br>~~—————EE~~|psp-p<br>~~—————EE~~|
|||fOUT < 100 MHz<br>~~Bf~~<br>~~es~~|—<br>~~es~~<br>~~es~~|0.12<br>~~es~~<br>~~es~~|—<br>~~es~~|TBD<br>~~es~~|UIPP<br>~~es~~|
|tSPO<br>~~GGG~~|Static Phase Offset<br>~~Bf~~<br>~~GGG~~|Divider ratio = integer<br>~~Bf~~<br>~~es~~<br>~~GGG~~|–120<br>~~es~~<br>~~es~~<br>~~GGG~~|120<br>~~es~~<br>~~es~~<br>~~GGG~~|–141<br>~~es~~<br>~~GGG~~|141<br>~~es~~<br>~~GGG~~|ps<br>~~es~~<br>~~GGG~~|
|tW<br>~~GGG~~<br>~~GGG~~|Output Clock Pulse Width<br>~~GGG~~<br>~~GGG~~|At 90% or 10%3<br>~~GGG~~<br>~~GGG~~|0.9<br>~~GGG~~<br>~~GGG~~|—<br>~~GGG~~<br>~~GGG~~|—<br>~~GGG~~<br>~~GGG~~|—<br>~~GGG~~<br>~~GGG~~|ns<br>~~GGG~~<br>~~GGG~~|
|tLOCK2, 5<br>~~GGG~~<br>~~ss~~<br>~~es~~|PLL Lock-in Time<br>~~GGG~~<br>~~ss~~<br>~~GQ~~|—<br>~~GGG~~<br>~~GQ~~<br>~~GQ~~|—<br>~~GGG~~<br>~~GQ~~<br>~~GQ~~|15<br>~~GGG~~<br>~~GQ~~<br>~~GQ~~|—<br>~~GGG~~<br>~~GQ~~|17.5<br>~~GGG~~<br>~~GQ~~|ms<br>~~GGG~~<br>~~GQ~~|
|tUNLOCK<br>~~es~~|PLL Unlock Time<br>~~GQ~~|—<br>~~GQ~~|—<br>~~GQ~~|50<br>~~GQ~~|—<br>~~GQ~~|50<br>~~GQ~~|ns<br>~~GQ~~|
|tIPJIT6<br>~~es~~<br>~~i~~|Input Clock Period Jitter<br>~~GQ~~<br>~~i~~|fPFD ≥ 20 MHz<br>~~GQ~~<br>~~ee~~|—<br>~~GQ~~<br>~~ee~~|1,000<br>~~GQ~~<br>~~ee~~|—<br>~~GQ~~|1,000<br>~~GQ~~|psp-p<br>~~GQ~~|
|||fPFD < 20 MHz<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~|0.02<br>~~ee~~<br>~~ee~~|0.8<br>~~ee~~|0.02<br>~~ee~~|UIPP<br>~~ee~~|
|tHI<br>~~i~~<br>~~GGG~~|Input Clock High Time<br>~~i~~<br>~~GGG~~|90% to 90%<br>~~ee~~<br>~~ee~~<br>~~GGG~~|0.5<br>~~ee~~<br>~~ee~~<br>~~GGG~~|—<br>~~ee~~<br>~~ee~~<br>~~GGG~~|0.8<br>~~ee~~<br>~~GGG~~|—<br>~~ee~~<br>~~GGG~~|ns<br>~~ee~~<br>~~GGG~~|
|tLO<br>~~GGG~~<br>~~ss~~<br>~~es~~|Input Clock Low Time<br>~~GGG~~<br>~~ss~~<br>~~GQ~~|10% to 10%<br>~~GGG~~<br>~~GQ~~<br>~~GQ~~|0.5<br>~~GGG~~<br>~~GQ~~<br>~~GQ~~|—<br>~~GGG~~<br>~~GQ~~<br>~~GQ~~|0.5<br>~~GGG~~<br>~~GQ~~|—<br>~~GGG~~<br>~~GQ~~|ns<br>~~GGG~~<br>~~GQ~~|
|tSTABLE5<br>~~es~~<br>~~es~~|STANDBY High to PLL Stable<br>~~GQ~~<br>~~GQ~~|—<br>~~GQ~~<br>~~GQ~~|—<br>~~GQ~~<br>~~GQ~~|15<br>~~GQ~~<br>~~GQ~~|—<br>~~GQ~~<br>~~GQ~~|15<br>~~GQ~~<br>~~GQ~~|ms<br>~~GQ~~<br>~~GQ~~|
|tRST<br>~~es~~<br>~~es~~<br>~~Re ee~~|RST/RESETM Pulse Width<br>~~GQ~~<br>~~GQ~~<br>~~ee~~|—<br>~~GQ~~<br>~~GQ~~<br>~~QO~~|1<br>~~GQ~~<br>~~GQ~~<br>~~QO~~|—<br>~~GQ~~<br>~~GQ~~<br>~~QO~~|1<br>~~GQ~~<br>~~GQ~~|—<br>~~GQ~~<br>~~GQ~~|ns<br>~~GQ~~<br>~~GQ~~|
|tRSTREC<br>~~es~~<br>~~Re ee~~|RST RecoveryTime<br>~~GQ~~<br>~~ee~~|—<br>~~GQ~~<br>~~QO~~|1<br>~~GQ~~<br>~~QO~~|—<br>~~GQ~~<br>~~QO~~|2.46<br>~~GQ~~|—<br>~~GQ~~|ns<br>~~GQ~~|
|tRST_DIV<br>~~Re ee~~<br>~~GGG~~<br>~~es~~|RESETC/D Pulse Width<br>~~ee~~<br>~~GGG~~<br>~~es~~|—<br>~~QO~~<br>~~GGG~~<br>~~GG~~|10<br>~~QO~~<br>~~GGG~~<br>~~GG~~|—<br>~~QO~~<br>~~GGG~~<br>~~GG~~|10<br>~~GGG~~<br>~~GG~~|—<br>~~GGG~~<br>~~GG~~|ns<br>~~GGG~~<br>~~GG~~|
|tRSTREC_DIV<br>~~GGG~~<br>~~es~~<br>~~es~~|RESETC/D RecoveryTime<br>~~GGG~~<br>~~es~~<br>~~GG~~|—<br>~~GGG~~<br>~~GG~~<br>~~GG~~|1<br>~~GGG~~<br>~~GG~~<br>~~GG~~|—<br>~~GGG~~<br>~~GG~~<br>~~GG~~|2.33<br>~~GGG~~<br>~~GG~~<br>~~GG~~|—<br>~~GGG~~<br>~~GG~~<br>~~GG~~|ns<br>~~GGG~~<br>~~GG~~<br>~~GG~~|
|tROTATE-SETUP<br>~~es ~~<br>~~es~~<br>~~es~~|PHASESTEP SetupTime<br> ~~es~~<br>~~GG~~|—<br>~~GG~~<br>~~GG~~|10<br>~~GG~~<br>~~GG~~|—<br>~~GG~~<br>~~GG~~|10<br>~~GG~~<br>~~GG~~|—<br>~~GG~~<br>~~GG~~|ns<br>~~GG~~<br>~~GG~~|
|tROTATE_WD<br>~~es~~<br>~~es~~|PHASESTEP Pulse Width<br>~~GG~~|—<br>~~GG~~|4<br>~~GG~~|—<br>~~GG~~|4<br>~~GG~~|—<br>~~GG~~|VCO<br>Cycles<br>~~GG~~|



1. Period jitter sample is taken over 10,000 samples of the primary PLL output with a clean reference clock. Cycle-to-cycle jitter is taken over 1000 cycles. Phase jitter is taken over 2000 cycles. All values per JESD65B. 

2. Output clock is valid after tLOCK for PLL reset and dynamic delay adjustment. 

© 2025 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02125-1.0 

69 

**MachXO4 Family Data Sheet** 

3. Using LVDS output buffers. 

4. CLKOS as compared to CLKOP output for one phase step at the maximum VCO frequency. See MachXO4 sysCLOCK PLL Design User Guide (FPGA-TN-02391) for more details. 

5. At minimum fPFD. As the fPFD increases the time decreases to approximately 60% the value listed. 

6. Maximum allowed jitter on an input clock. PLL unlock may occur if the input jitter exceeds this specification. Jitter on the input clock may be transferred to the output clocks, resulting in jitter measurements outside the output specifications listed in this table. 

7. Edge Duty Trim Accuracy is a percentage of the setting value. Settings available are 70 ps, 140 ps, and 280 ps in addition to the default value of none. 

Edge Duty Trim Accuracy does not apply to Automotive. 

8. Jitter values measured with the internal oscillator operating. The jitter values increase with loading of the PLD fabric and in the presence of SSO noise. 

## **3.19. Oscillator Output Frequency** 

**Table 3.24. Oscillator Output Frequency** 

|**Symbol**<br>~~eee~~|**Parameter**<br>~~eee~~|**–6**<br>**(Commercial/Industrial)**<br>~~ee~~<br>~~eee~~|**–6**<br>**(Commercial/Industrial)**<br>~~ee~~<br>~~eee~~|**–6**<br>**(Commercial/Industrial)**<br>~~ee~~<br>~~eee~~|**–5**<br>**(Automotive)**<br>~~ee~~<br>~~eee~~|**–5**<br>**(Automotive)**<br>~~ee~~<br>~~eee~~|**–5**<br>**(Automotive)**<br>~~ee~~<br>~~eee~~|**Unit**<br>~~ee~~|
|---|---|---|---|---|---|---|---|---|
|||**Min.**<br>~~ee~~<br>~~eee~~|**Typ.**<br>~~ee~~<br>~~eee~~|**Max**<br>~~ee~~<br>~~eee~~|**Min.**<br>~~ee~~<br>~~eee~~|**Typ.**<br>~~ee~~<br>~~eee~~|**Max**<br>~~ee~~<br>~~eee~~||
|fMAX<br>~~a~~|Oscillator Output Frequency (Commercial<br>Grade Devices, 0 to 85°C)<br>~~ee~~|125.685<br>~~ee~~|133<br>~~ee~~|140.315<br>~~ee~~|—<br>~~ee~~|—<br>~~ee~~|—<br>~~ee~~|MHz<br>~~ee~~|
||Oscillator Output Frequency (Industrial Grade<br>Devices, –40 °C to 100 °C)<br>~~ee~~|124.355<br>~~ee~~|133<br>~~ee~~|141.645<br>~~ee~~|—<br>~~ee~~|—<br>~~ee~~|—<br>~~ee~~|MHz<br>~~ee~~|
||Oscillator Output Frequency (Automotive<br>Grade Devices, -40 to 125°C)<br>~~ee~~<br>~~a~~|—<br>~~ee~~<br>~~GG~~|—<br>~~ee~~<br>~~GG~~|—<br>~~ee~~<br>~~Gs~~|122.360<br>~~ee~~<br>~~GO~~|133<br>~~ee~~<br>~~GO~~|143.640<br>~~ee~~|MHz<br>~~ee~~|
|tDT<br>~~a~~<br>~~a~~|Output Clock DutyCycle<br>~~a~~<br>~~a~~|43<br>~~GG~~<br>~~GG~~|50<br>~~GG~~<br>~~GG~~|57<br>~~Gs~~<br>~~Gs~~|43<br>~~GO~~<br>~~GO~~|50<br>~~GO~~<br>~~GO~~|57|%|
|tOPJIT<br>~~a ~~<br>~~a~~|Output Clock Period Jitter<br> ~~a~~<br>~~a~~|—<br>~~GG~~<br>~~GG~~|—<br>~~GG ~~<br>~~GG~~|0.02<br> ~~Gs~~<br>~~Gs~~|—<br>~~GO~~<br>~~GO~~|—<br>~~GO~~<br>~~GO~~|0.02|UIPP|
|tSTABLEOSC<br>~~a ~~<br>~~GOGO~~|STDBY Low to Oscillator Stable<br> ~~a~~<br>~~GOGO~~|—<br>~~GG~~<br>~~GOGO~~|—<br>~~GG ~~<br>~~GOGO~~|0.1<br> ~~Gs~~<br>~~GOGO~~|—<br>~~GO~~<br>~~GOGO~~|—<br>~~GO~~<br>~~GOGO~~|0.1<br>~~GOGO~~|µs<br>~~GOGO~~|



**Note:** Output Clock Period Jitter specified at 133 MHz. The values for lower frequencies are smaller UIPP. The typical value for 133 MHz is 95 ps and for 2.08 MHz the typical value is 1.54 ns. 

## **3.20. Flash Download Time** 

**Table 3.25. Flash Download Time** 

|**Symbol**|**Parameter**|**Device**|**Typ. **|**Unit**|
|---|---|---|---|---|
|tREFRESH|POR to Device I/O Active|LFMXO4-010|1.9|ms|
|||LFMXO4-015|1.9|ms|
|||LFMXO4-015 256-Ball Package|1.4|ms|
|||LFMXO4-025|1.4|ms|
|||LFMXO4-050|2.4|ms|
|||LFMXO4-050 400-Ball Package|3.8|ms|
|||LFMXO4-080|3.8|ms|
|||LFMXO4-110C|5.2|ms|



**Notes** : 

- Assumes sysMEM EBR initialized to an all zero pattern if they are used. 

- The Flash download time is measured starting from the maximum voltage of POR trip point. 

- The worst case can be up to 1.75 times the Typ value. 

© 2025 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02125-1.0 

70 

**MachXO4 Family Data Sheet** 

## **3.21. JTAG Port Timing Specifications** 

**Table 3.26. JTAG Port Timing Specifications** 

|**Symbol**|**Parameter**|**Commercial/Industrial**|**Commercial/Industrial**|**Automotive**|**Automotive**|**Unit**|
|---|---|---|---|---|---|---|
|||**Min.**|**Max.**|**Min.**|**Max.**||
|fMAX|TCK clock frequency|—|25|—|25|MHz|
|tBTCPH|TCK[BSCAN]clockpulse width high|20|—|20|—|ns|
|tBTCPL|TCK[BSCAN]clockpulse width low|20|—|20|—|ns|
|tBTS|TCK[BSCAN]setuptime|10|—|10|—|ns|
|tBTH|TCK[BSCAN]hold time|8|—|10|—|ns|
|tBTCO|TAP controller fallingedge of clock to valid output|—|10|—|10|ns|
|tBTCODIS|TAP controller fallingedge of clock to valid disable|—|10|—|12|ns|
|tBTCOEN|TAP controller fallingedge of clock to valid enable|—|10|—|12|ns|
|tBTCRS|BSCAN test capture register setuptime|8|—|8|—|ns|
|tBTCRH|BSCAN test capture register hold time|20|—|20|—|ns|
|tBUTCO|BSCAN test update register, falling edge of clock to<br>valid output|—|25|—|25|ns|
|tBTUODIS|BSCAN test update register, falling edge of clock to<br>valid disable|—|25|—|27|ns|
|tBTUPOEN|BSCAN test update register, falling edge of clock to<br>valid enable|—|25|—|25|ns|



**Figure 3.9. JTAG Port Timing Waveforms** 

© 2025 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02125-1.0 

71 

**MachXO4 Family Data Sheet** 

## **3.22. sysCONFIG Port Timing Specifications** 

**Table 3.27. sysCONFIG Port Timing Specifications** 

|**Symbol**<br>~~a se~~|**Parameter**<br>~~se~~|**Parameter**<br>~~se~~|**Commercial/Industrial**<br>~~se~~<br>~~ee~~|**Commercial/Industrial**<br>~~se~~<br>~~ee~~|**Automotive**<br>~~se~~<br>~~ee~~<br>~~ee~~|**Automotive**<br>~~se~~<br>~~ee~~<br>~~ee~~|**Unit**<br>~~se~~<br>~~ee~~|
|---|---|---|---|---|---|---|---|
||||**Min.**<br>~~se~~<br>~~rs~~|**Max.**<br>~~se~~<br>~~rs~~<br>~~ee~~|**Min.**<br>~~se~~<br>~~rs~~<br>~~ee~~|**Max.**<br>~~se~~<br>~~rs~~<br>~~ee~~||
|**All Configuration Modes**<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~pt~~||||||||
|tPRGM<br>~~a~~|PROGRAMN lowpulse accept<br>~~a~~||55<br>~~GO~~|—<br>~~GO~~|55|—|ns|
|tPRGMJ<br>~~a ~~|PROGRAMN lowpulse rejection<br> ~~GO~~||—<br>~~GO~~|25<br>~~GO~~|—<br>~~GO~~|25<br>~~GO~~|ns<br>~~GO~~|
|tINITL<br>~~| ~~|INITN low time<br>|LCMXO4-010/<br>LCMXO4-015<br>~~EBRRR~~|—<br>~~EBRRR~~|55<br>~~EBRRR~~|—<br>~~EBRRR~~|93<br>~~EBRRR~~|us<br>~~EBRRR~~|
|||LCMXO4-015 256-Ball<br>Package/ LCMXO4-<br>025<br>~~EBRRR~~|—<br>~~EBRRR~~|70<br>~~EBRRR~~|—<br>~~EBRRR~~|93<br>~~EBRRR~~|us<br>~~EBRRR~~|
|||LCMXO4-050<br>~~EBRRR~~|—<br>~~EBRRR~~|105<br>~~EBRRR~~|—<br>~~EBRRR~~|130<br>~~EBRRR~~|us<br>~~EBRRR~~|
|||LCMXO4-050 400-Ball<br>Package/LCMXO4-<br>080<br>~~EBRRR~~|—<br>~~EBRRR~~|130<br>~~EBRRR~~|—<br>~~EBRRR~~|—<br>~~EBRRR~~|us<br>~~EBRRR~~|
|||LCMXO4-110C<br> ~~EBRRR~~<br>~~pT~~|—<br>~~EBRRR~~<br>~~pT~~|175<br>~~EBRRR~~<br>~~pT~~|—<br>~~EBRRR~~<br>~~pT~~|—<br>~~EBRRR~~<br>~~pT~~|us<br>~~EBRRR~~<br>~~pT~~|
|tDPPINIT<br>~~a~~|PROGRAMN low to INITN low<br>~~a~~||—<br>~~G~~|150<br>~~G~~|—|150|ns|
|tDPPDONE<br>~~Ge~~|PROGRAMN low to DONE low<br>~~Ge~~||—<br>~~Ge~~|150<br>~~Ge~~|—<br>~~Ge~~|150<br>~~Ge~~|ns<br>~~Ge~~|
|tIODISS<br>~~Ge~~<br>~~DO~~|PROGRAMN low to I/O disable<br>~~Ge~~<br>~~DO~~||—<br>~~Ge~~<br>~~DO~~|120<br>~~Ge~~<br>~~DO~~|—<br>~~Ge~~<br>~~DO~~|120<br>~~Ge~~<br>~~DO~~|ns<br>~~Ge~~<br>~~DO~~|
|**Slave SPI**<br>~~DO~~||||||||
|fMAX<br>~~a ~~|CCLK clock frequency<br> ~~GO~~||—<br>~~GO~~|66<br>~~GO~~|—<br>~~GO~~|66<br>~~GO~~|MHz<br>~~GO~~|
|tCCLKH<br>~~GO~~|CCLK clockpulse width high<br>~~GO~~||7.5<br>~~GO~~|—<br>~~GO~~|7.5<br>~~GO~~|—<br>~~GO~~|ns<br>~~GO~~|
|tCCLKL<br>~~Ge~~|CCLK clockpulse width low<br>~~Ge~~||7.5<br>~~Ge~~|—<br>~~Ge~~|7.5<br>~~Ge~~|—<br>~~Ge~~|ns<br>~~Ge~~|
|tSTSU<br>~~Ge~~<br>~~OO~~|CCLK setuptime<br>~~Ge~~<br>~~OO~~||2<br>~~Ge~~<br>~~OO~~|—<br>~~Ge~~<br>~~OO~~|2<br>~~Ge~~<br>~~OO~~|—<br>~~Ge~~<br>~~OO~~|ns<br>~~Ge~~<br>~~OO~~|
|tSTH<br>~~OO~~<br>~~a ~~|CCLK hold time<br>~~OO~~<br> ~~eG~~||0<br>~~OO~~<br>~~eG~~|—<br>~~OO~~<br>~~eG~~|0<br>~~OO~~<br>~~eG~~|—<br>~~OO~~<br>~~eG~~|ns<br>~~OO~~<br>~~eG~~|
|tSTCO<br>~~eG~~<br>~~ee~~|CCLK fallingedge to valid output<br>~~eG~~<br>~~eG~~||—<br>~~eG~~<br>~~eG~~|10<br>~~eG~~<br>~~eG~~|—<br>~~eG~~<br>~~eG~~|14<br>~~eG~~<br>~~eG~~|ns<br>~~eG~~<br>~~eG~~|
|tSTOZ<br>~~ee~~<br>~~a~~|CCLK fallingedge to valid disable<br>~~eG~~<br>||—<br>~~eG~~<br>~~GG~~<br>|10<br>~~eG~~<br>~~GG~~<br>|—<br>~~eG~~<br>~~GG~~<br>|12<br>~~eG~~<br>~~GG~~<br>|ns<br>~~eG~~<br>|
|tSTOV<br>~~ee~~<br>~~Ge~~<br>~~a~~|CCLK fallingedge to valid enable<br>~~eG~~<br>~~Ge~~<br>||—<br>~~eG~~<br>~~Ge~~<br>~~GG~~<br>|10<br>~~eG~~<br>~~Ge~~<br>~~GG~~<br>|—<br>~~eG~~<br>~~Ge~~<br>~~GG~~<br>|14<br>~~eG~~<br>~~Ge~~<br>~~GG~~<br>|ns<br>~~eG~~<br>~~Ge~~<br>|
|tSCS<br>~~Ge~~<br>~~a~~|Chipselect high time<br>~~Ge~~<br>~~OO~~||25<br>~~Ge~~<br>~~GG~~<br>~~OO~~|—<br>~~Ge~~<br>~~GG~~<br>~~OO~~|25<br>~~Ge~~<br>~~GG~~<br>~~OO~~|—<br>~~Ge~~<br>~~GG~~<br>~~OO~~|ns<br>~~Ge~~<br>~~OO~~|
|tSCSS<br>~~a ~~<br>~~a ~~|Chipselect setuptime<br> ~~OO~~<br> ~~GO~~||3<br>~~GG~~<br>~~OO~~<br>~~GO~~|—<br>~~GG~~<br>~~OO~~<br>~~GO~~|3<br>~~GG~~<br>~~OO~~<br>~~GO~~|—<br>~~GG~~<br>~~OO~~<br>~~GO~~|ns<br>~~OO~~<br>~~GO~~|
|tSCSH<br>~~a~~|Chipselect hold time<br>~~a~~||3|—<br>~~G~~|3|—|ns|
|**Master SPI**<br>~~GG~~<br>~~a~~||||||||
|fMAX<br>~~Ge~~<br>~~a~~|MCLK clock frequency<br>~~Ge~~<br>||—<br>~~Ge~~<br>~~GG~~<br>|133<br>~~Ge~~<br>~~GG~~<br>|—<br>~~Ge~~<br>~~GG~~<br>|66<br>~~Ge~~<br>~~GG~~<br>|MHz<br>~~Ge~~<br>|
|tMCLKH<br>~~Ge~~<br>~~a~~|MCLK clockpulse width high<br>~~Ge~~<br>~~OO~~||3.75<br>~~Ge~~<br>~~GG~~<br>~~OO~~|—<br>~~Ge~~<br>~~GG~~<br>~~OO~~|7.5<br>~~Ge~~<br>~~GG~~<br>~~OO~~|—<br>~~Ge~~<br>~~GG~~<br>~~OO~~|ns<br>~~Ge~~<br>~~OO~~|
|tMCLKL<br>~~a ~~<br>~~a~~|MCLK clockpulse width low<br> ~~OO~~<br>~~OO~~||3.75<br>~~GG~~<br>~~OO~~<br>~~OO~~|—<br>~~GG~~<br>~~OO~~<br>~~OO~~|7.5<br>~~GG~~<br>~~OO~~<br>~~OO~~|—<br>~~GG~~<br>~~OO~~<br>~~OO~~|ns<br>~~OO~~<br>~~OO~~|
|tSTSU<br>~~a ~~<br>~~a ~~|MCLK setuptime<br> ~~OO~~<br> ~~GO~~||5<br>~~OO~~<br>~~GO~~|—<br>~~OO~~<br>~~GO~~|6<br>~~OO~~<br>~~GO~~|—<br>~~OO~~<br>~~GO~~|ns<br>~~OO~~<br>~~GO~~|
|tSTH<br>~~a ~~|MCLK hold time<br> ~~GO~~||1<br>~~GO~~<br>~~GG~~|—<br>~~GO~~<br>~~GG~~|3<br>~~GO~~<br>~~GG~~|—<br>~~GO~~<br>~~GG~~|ns<br>~~GO~~|
|tCSSPI<br>~~Ge~~|INITN high to chipselect low<br>~~Ge~~||100<br>~~Ge~~<br>~~GG~~|200<br>~~Ge~~<br>~~GG~~|100<br>~~Ge~~<br>~~GG~~|200<br>~~Ge~~<br>~~GG~~|ns<br>~~Ge~~|
|tMCLK<br>~~Ge~~<br>~~DO~~|INITN high to first MCLK edge<br>~~Ge~~<br>~~DO~~||0.75<br>~~Ge~~<br>~~GG~~<br>~~DO~~|1<br>~~Ge~~<br>~~GG~~<br>~~DO~~|0.75<br>~~Ge~~<br>~~GG~~<br>~~DO~~|1<br>~~Ge~~<br>~~GG~~<br>~~DO~~|us<br>~~Ge~~<br>~~DO~~|



© 2025 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02125-1.0 

72 

**MachXO4 Family Data Sheet** 

## **3.23. I2C Port Timing Specifications** 

**Table 3.28. I2C Port Timing Specification Symbol Parameter Min. Max. Unit** ~~ee~~ fMAX Maximum SCL clock frequency — 400 kHz **Notes:** • MachXO4 supports the following modes: 

   - Standard-mode (Sm), with a bit rate up to 100 kb/s (user and configuration mode) 

   - Fast-mode (Fm), with a bit rate up to 400 kb/s (user and configuration mode) 

- Refer to the I2C specification for timing requirements. 

## **3.24. SPI Port Timing Specifications** 

**Table 3.29. SPI Port Timing Specifications Symbol Parameter Min. Max. Units** fMAX Maximum SCK clock frequency — 45 MHz ~~ee~~ **Note:** Applies to user mode only. For configuration mode timing specifications, refer to sysCONFIG Port Timing Specifications table in this data sheet. 

## **3.25. Switching Test Conditions** 

Figure 3.9 shows the output test load used for AC testing. The specific values for resistance, capacitance, voltage, and other test conditions are shown in Table 3.29. 

**==> picture [163 x 72] intentionally omitted <==**

**----- Start of picture text -----**<br>
V T<br>R1<br>DUT  Test Point<br>CL<br>**----- End of picture text -----**<br>


**Figure 3.10. Output Test Load, LVTTL and LVCMOS Standards** 

**Table 3.30. Test Fixture Required Components, Non-Terminated Interfaces** 

|**Test Condition**|**R1**|**CL**|**Timing Ref.**|**VT**|
|---|---|---|---|---|
|LVTTL and LVCMOS settings (L -> H, H -> L)||0 pF|LVTTL, LVCMOS 3.3 = 1.5 V|—|
||||LVCMOS 2.5 = VCCIO/2|—|
||||LVCMOS 1.8 = VCCIO/2|—|
||||LVCMOS 1.5 = VCCIO/2|—|
||||LVCMOS 1.2 = VCCIO/2|—|
|LVTTL and LVCMOS 3.3 (Z -> H)|188|0 pF|1.5|VOL|
|LVTTL and LVCMOS 3.3 (Z -> L)|||1.5|VOH|
|Other LVCMOS (Z -> H)|||VCCIO/2|VOL|
|Other LVCMOS (Z -> L)|||VCCIO/2|VOH|
|LVTTL + LVCMOS (H -> Z)|||VOH – 0.15|VOL|
|LVTTL + LVCMOS (L -> Z)|||VOL – 0.15|VOH|



**Note** : Output test conditions for all other interfaces are determined by the respective standards. 

© 2025 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02125-1.0 

73 

**MachXO4 Family Data Sheet** 

## **4. Signal Descriptions** 

|**Signal Name**<br>~~eG~~|**I/O **<br>~~eG~~|**Description**<br>~~eG~~|
|---|---|---|
|**General Purpose**<br>~~Re~~<br>~~lz~~|||
|P[Edge] [Row/Column<br>Number]_[A/B/C/D]<br>~~Re~~<br>~~lz~~|I/O<br>~~Re~~<br>~~lz~~|[Edge] indicates the edge of the device on which the pad is located. Valid edge designations<br>are L (Left), B (Bottom), R (Right), T (Top).<br>[Row/Column Number] indicates the PFU row or the column of the device on which the PIO<br>Group exists. When Edge is T (Top) or (Bottom), only need to specify Row Number. When<br>Edge is L (Left) or R (Right), only need to specify Column Number.<br>[A/B/C/D] indicates the PIO within the group to which the pad is connected.<br>Some of these user-programmable pins are shared with special function pins. When not used<br>as special function pins, these pins can be programmed as I/O for user logic.<br>During configuration of the user-programmable I/O, the user has an option to tri-state the<br>I/O and enable an internal pull-up, pull-down or buskeeper resistor. This option also applies<br>to unused pins (or those not bonded to a package pin). The default during configuration is for<br>user-programmable I/O to be tri-stated with an internal pull-down resistor enabled. When<br>the device is erased, I/O is tri-stated with an internal pull-down resistor enabled. Some pins,<br>such as PROGRAMN and JTAG pins, default to tri-stated I/O with pull-up resistors enabled<br>when the device is erased.<br>~~Re~~<br>~~lz~~|
|NC<br>~~lz~~<br>~~ee~~|—<br>~~lz~~|No connect.<br>~~lz~~|
|GND<br>~~lz~~<br>~~ee~~|—<br>~~lz~~|GND – Ground. Dedicatedpins. It is recommended that all GNDs are tied together.<br>~~lz~~|
|VCC<br>~~ee~~<br>~~a~~|—|VCC– The power supply pins for core logic. Dedicated pins. It is recommended that all VCCs are<br>tied to the same supply.|
|VCCIOx<br>~~a~~<br>~~a~~|—|VCCIO– The power supply pins for I/O Bank x. Dedicated pins. It is recommended that all VCCIOs<br>located in the same bank are tied to the same supply.|
|**PLL and Clock Functions** (Used as user-programmable I/Opins when not used for PLL or clockpins)<br>~~PR~~|||
|[LOC]_GPLL[T, C]_IN<br>~~PR~~<br>~~a ee~~|—<br>~~PR~~<br>~~ee~~|Reference Clock (PLL) input pads: [LOC] indicates location. Valid designations are L (Left PLL)<br>and R(Right PLL). T = true and C = complement.<br>~~PR~~<br>~~ee~~|
|[LOC]_GPLL[T, C]_FB<br>~~a ee~~<br>~~a~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~|Optional Feedback (PLL) input pads: [LOC] indicates location. Valid designations are L (Left<br>PLL)and R(Right PLL). T = true and C = complement.<br>~~ee~~<br>~~Ge~~|
|PCLK[n]_[2:0]<br>~~a~~<br>~~ee~~|—<br>~~ee~~|PrimaryClockpads. One to three clockpadsper side.<br>~~Ge~~|
|**Test and Programming** (Dual functionpins used for test accessport and duringsysCONFIG™)<br>~~eeeeGe~~<br>~~ee~~|||
|TMS<br>~~ee~~|I|Test Mode Select inputpin,used to control the 1149.1 state machine.|
|TCK<br>~~ee~~<br>~~Ge~~|I<br>~~Ge~~|Test Clock inputpin, used to clock the 1149.1 state machine.<br>~~Ge~~|
|TDI<br>~~Ge~~<br>~~es~~|I<br>~~Ge~~<br>~~es~~|Test Data inputpin,used to load data into the device usingan 1149.1 state machine.<br>~~Ge~~<br>~~es~~|
|TDO<br>~~es~~|O<br>~~es~~|Outputpin – Test Data outputpin used to shift data out of the device using1149.1.<br>~~es~~|
|JTAGENB|I|Optionally controls behavior of TDI, TDO, TMS, TCK. If the device is configured to use the<br>JTAG pins (TDI, TDO, TMS, TCK) as general purpose I/O, then:<br>If JTAGENB is low: TDI, TDO, TMS and TCK can function a general purpose I/O.<br>If JTAGENB is high: TDI, TDO, TMS and TCK function as JTAG pins.<br>For more details, refer toMachXO4 Programming and Configuration Usage Guide<br>(FPGA-TN-02393).|
|**Configuration**(Dual functionpins used duringsysCONFIG)<br>~~Pe~~|||
|PROGRAMN<br>~~Pe~~<br>~~a ee~~|I<br>~~Pe~~<br>~~ee~~|Initiates configuration sequence when asserted low. This pin is single-ended and always has<br>an activepull-up.<br>~~Pe~~<br>~~ee~~|
|INITN<br>~~a ee~~<br>~~ee~~|I/O<br>~~ee~~<br>~~ee~~|Open Drain pin. Indicates the FPGA is ready to be configured. During configuration, a pull-up<br>is enabled. Thispin is single-ended.<br>~~ee~~<br>~~ee~~|
|DONE<br>~~ee~~<br>~~a~~|I/O<br>~~ee~~|Open Drain pin. Indicates that the configuration sequence is complete, and the start-up<br>sequence is inprogress. Thispin is single-ended.<br>~~ee~~|
|MCLK/CCLK<br>~~a~~<br>~~a~~<br>~~**e**e~~|I/O|Input Configuration Clock for configuring an FPGA in Slave SPI mode. Output Configuration<br>Clock for configuringan FPGA in SPI and SPIm configuration modes.|
|SN<br>~~a~~<br>~~**e**e~~|I|Slave SPI active low chipselect input.|
|CSSPIN<br>~~**e**e~~|I/O|Master SPI active low chipselect output.<br>~~G~~|



© 2025 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. 

All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02125-1.0 

74 

**MachXO4 Family Data Sheet** 

|**Signal Name**|**I/O **|**Description**|
|---|---|---|
|SI/SPISI|I/O|Slave SPI serial data input and master SPI serial data output.|
|SO/SPISO|I/O|Slave SPI serial data output and master SPI serial data input.|
|SCL|I/O|Slave I2C clock input and master I2C clock output.|
|SDA|I/O|Slave I2C data input and master I2C data output.|



## **4.1. Pin Information Summary** 

**Table 4.2. LFMXO4-010 and LFMXO4-015 Pin Summary** 

|~~po~~|**LFMXO4-010**<br>~~eG~~<br>~~po~~|**LFMXO4-010**<br>~~eG~~<br>~~po~~|**LFMXO4-010**<br>~~eG~~<br>~~po~~|**LFMXO4-015**<br>~~eG~~|**LFMXO4-015**<br>~~eG~~|**LFMXO4-015**<br>~~eG~~|**LFMXO4-015**<br>~~eG~~|**LFMXO4-015**<br>~~eG~~|**LFMXO4-015**<br>~~eG~~|
|---|---|---|---|---|---|---|---|---|---|
||**TSG100**<br>~~po~~|**BSG132**|**TSG144**|**UUG36**|**TSG100**|**BSG132**|**TSG144**|**BBG256**|**BFG256**|
|**General Purpose I/Oper Bank**<br>~~po~~||||||||||
|Bank 0<br>~~po~~|18<br>~~po~~|24<br>~~po~~|26<br>~~po~~|15<br>~~po~~|18<br>~~po~~|24<br>~~po~~|26<br>~~po~~|49<br>~~po~~|49<br>~~po~~|
|Bank 1<br>~~GG~~<br>~~po~~|21<br>~~GG~~|26<br>~~GG~~|26<br>~~GG~~|0<br>~~GG~~|21<br>~~GG~~|26<br>~~GG~~|26<br>~~GG~~|52<br>~~GG~~|52<br>~~GG~~|
|Bank 2<br>~~po~~<br>~~pO~~|20|28|28|9|20|28|28|52|52|
|Bank 3<br>~~po~~<br>~~pO~~|20|25|26|4|20|25|26|16|16|
|Bank 4<br>~~pO~~<br>~~ee~~|0<br>~~ee~~|0<br>~~GOD~~|0<br>~~GOD~~|0<br>~~GOD~~|0<br>~~GOD~~|0<br>~~GOD~~|0<br>~~GOD~~|16<br>~~GOD~~|16<br>~~GOD~~|
|Bank 5<br>~~ee~~|0<br>~~ee~~|0<br>~~GOD~~|0<br>~~GOD~~|0<br>~~GOD~~|0<br>~~GOD~~|0<br>~~GOD~~|0<br>~~GOD~~|20<br>~~GOD~~|20<br>~~GOD~~|
|Total General<br>Purpose Single<br>Ended I/O<br>~~|~~|79<br>~~|~~|103<br>~~|~~|106<br>~~tet~~|28<br>~~tet~~|79<br>~~tet~~|103|106|205|205|
|Minimum<br>Reserved for<br>Configuration*<br>~~|~~|1<br>~~|~~|1<br>~~|~~|1<br>~~tet~~|1<br>~~tet~~|1<br>~~tet~~|1|1|1|1|
|Maximum<br>Programmable<br>Single Ended<br>I/O|78|102|105|27|78|102|105|204|204|
|**Differential I/Oper Bank**<br>~~pn~~||||||||||
|Bank 0<br>~~po~~<br>~~po~~|8<br>~~po~~<br>~~po~~|11<br>~~po~~|12<br>~~po~~|7<br>~~po~~|8<br>~~po~~|11<br>~~po~~|12<br>~~po~~|23<br>~~po~~|23<br>~~po~~|
|Bank 1<br>~~po~~<br>~~po~~|10<br>~~po~~|13|13|0|10|13|13|26|26|
|Bank 2<br>~~po~~<br>~~po~~<br>~~po~~|10<br>~~po~~|14|14|4|10|14|14|26|26|
|Bank 3<br>~~po~~<br>~~po~~|10|12|13|2|10|12|13|8|8|
|Bank 4<br>~~po~~<br>~~Ge~~|0<br>~~Ge~~|0<br>~~GG~~|0<br>~~GG~~|0<br>~~GG~~|0<br>~~GG~~|0<br>~~GG~~|0<br>~~GG~~|8<br>~~GG~~|8<br>~~GG~~|
|Bank 5|0|0|0|0|0|0|0|10|10|
|Total General<br>Purpose<br>Differential<br>I/O|38|50|52|13|38|50|52|101|101|
|Dual Function<br>I/O|31|33|33|25|31|33|33|33|33|



© 2025 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02125-1.0 

75 

**MachXO4 Family Data Sheet** 

|~~po~~|**LFMXO4-010**<br>~~Ge~~<br>~~po~~|**LFMXO4-010**<br>~~Ge~~<br>~~po~~|**LFMXO4-010**<br>~~Ge~~<br>~~po~~|**LFMXO4-015**<br>~~Ge~~|**LFMXO4-015**<br>~~Ge~~|**LFMXO4-015**<br>~~Ge~~|**LFMXO4-015**<br>~~Ge~~|**LFMXO4-015**<br>~~Ge~~|**LFMXO4-015**<br>~~Ge~~|
|---|---|---|---|---|---|---|---|---|---|
||**TSG100**<br>~~po~~|**BSG132**|**TSG144**|**UUG36**|**TSG100**|**BSG132**|**TSG144**|**BBG256**|**BFG256**|
|**Number 7:1 or 8:1 Gearboxes**<br>~~po~~||||||||||
|Number of 7:1<br>or 8:1 Output<br>Gearbox<br>Available<br>(Bank 0)|3|5|5|2|3|5|5|12|12|
|Number of 7:1<br>or 8:1 Input<br>Gearbox<br>Available<br>(Bank 2)|5|7|7|2|5|7|7|14|14|
|**High-speed Differential Outputs**<br>~~po~~||||||||||
|Bank 0<br>~~po~~|3<br>|5<br>|5<br>|2<br>|3<br>|5<br>|5<br>|12<br>|12<br>|
|**VCCIO Pins**<br>~~popn~~<br>~~po~~||||||||||
|Bank 0<br>~~po~~<br>~~po~~|3|4|4|2|3|4|4|5|5|
|Bank 1<br>~~po~~<br>~~po~~<br>~~pO~~|2|3|3|0|2|3|3|4|4|
|Bank 2<br>~~po~~<br>~~pO~~|2|3|3|1|2|3|3|4|4|
|Bank 3<br>~~pO~~<br>~~ee~~|3<br>~~ee~~|3<br>~~GOD~~|3<br>~~GOD~~|1<br>~~GOD~~|3<br>~~GOD~~|3<br>~~GOD~~|3<br>~~GOD~~|1<br>~~GOD~~|1<br>~~GOD~~|
|Bank 4<br>~~ee~~<br>~~ee~~<br>~~po~~|0<br>~~ee~~<br>~~ee~~|0<br>~~GOD~~<br>~~GOD~~|0<br>~~GOD~~<br>~~GOD~~|0<br>~~GOD~~<br>~~GOD~~|0<br>~~GOD~~<br>~~GOD~~|0<br>~~GOD~~<br>~~GOD~~|0<br>~~GOD~~<br>~~GOD~~|2<br>~~GOD~~<br>~~GOD~~|2<br>~~GOD~~<br>~~GOD~~|
|Bank 5<br>~~ee~~<br>~~po~~<br>~~po~~|0<br>~~ee~~|0<br>~~GOD~~|0<br>~~GOD~~|0<br>~~GOD~~|0<br>~~GOD~~|0<br>~~GOD~~|0<br>~~GOD~~|1<br>~~GOD~~|1<br>~~GOD~~|
|VCC<br>~~po~~<br>~~po~~<br>~~pO~~|2|4|4|2|2|4|4|8|8|
|GND<br>~~po~~<br>~~pO~~|8|11|13|2|8|11|13|25|25|
|NC<br>~~pO~~<br>~~ee~~|1<br>~~ee~~|1<br>~~GOD~~|8<br>~~GOD~~|0<br>~~GOD~~|1<br>~~GOD~~|1<br>~~GOD~~|8<br>~~GOD~~|1<br>~~GOD~~|1<br>~~GOD~~|
|Total Count of<br>Bonded Pins<br>~~ee~~<br>~~a~~|100<br>~~ee~~|132<br>~~GOD~~|144<br>~~GOD~~|36<br>~~GOD~~|100<br>~~GOD~~|132<br>~~GOD~~|144<br>~~GOD~~|256<br>~~GOD~~|256<br>~~GOD~~|



***Note:** One pin for JTAGENB or four pins for JTAG. 

**Table 4.3. LFMXO4-025 Pin Summary** 

||**LFMXO4-025**<br>~~es~~|**LFMXO4-025**<br>~~es~~|**LFMXO4-025**<br>~~es~~|**LFMXO4-025**<br>~~es~~|**LFMXO4-025**<br>~~es~~|**LFMXO4-025**<br>~~es~~|
|---|---|---|---|---|---|---|
||**UUG49**<br>~~es~~|**TSG100**|**BSG132**|**TSG144**|**BBG256**|**BFG256**|
|**General Purpose I/Oper Bank**<br>~~es~~<br>~~po~~|||||||
|Bank 0<br>~~po~~|19|18|24<br>~~CO~~|26<br>~~CO~~|49<br>~~CO~~|49|
|Bank 1<br>~~po~~<br>~~GG~~|0<br>~~GG~~|21<br>~~GG~~|26<br>~~GG~~<br>~~CO~~<br>~~CO~~|28<br>~~GG~~<br>~~CO~~<br>~~CO~~|52<br>~~GG~~<br>~~CO~~<br>~~CO~~|52<br>~~GG~~|
|Bank 2<br>~~GG~~<br>~~GG~~<br>~~pO~~|13<br>~~GG~~<br>~~GG~~|20<br>~~GG~~<br>~~GG~~|28<br>~~GG~~<br>~~CO~~<br>~~GG~~<br>~~CO~~<br>~~Ge~~|28<br>~~GG~~<br>~~CO~~<br>~~GG~~<br>~~CO~~<br>~~Ge~~|52<br>~~GG~~<br>~~CO~~<br>~~GG~~<br>~~CO~~<br>~~Ge~~|52<br>~~GG~~<br>~~GG~~|
|Bank 3<br>~~GG~~<br>~~GG~~<br>~~pO~~|0<br>~~GG~~<br>~~GG~~|6<br>~~GG~~<br>~~GG~~|7<br>~~GG~~<br>~~CO~~<br>~~GG~~<br>~~Ge~~|8<br>~~GG~~<br>~~CO~~<br>~~GG~~<br>~~Ge~~|16<br>~~GG~~<br>~~CO~~<br>~~GG~~<br>~~Ge~~|16<br>~~GG~~<br>~~GG~~|
|Bank 4<br>~~pO~~<br>~~pO~~|0|6|8<br>~~Ge~~|10<br>~~Ge~~|16<br>~~Ge~~|16|
|Bank 5<br>~~pO~~<br>~~pO~~|6|8|10<br>~~Ge~~|10<br>~~Ge~~|20<br>~~Ge~~|20|
|Total General Purpose<br>Single Ended I/O<br>~~pO~~<br>~~a~~<br>~~a~~|38<br>~~ee~~<br>~~ee~~|79<br>~~ee~~<br>~~ee ee~~|103<br>~~ee~~<br>~~ee~~|110<br>~~ee~~|205<br>~~ee~~|205<br>~~ee~~|
|Minimum Reserved for<br>Configuration*<br>~~a~~<br>~~a~~|1<br>~~ee~~<br>~~ee~~|1<br>~~ee~~<br>~~ee ee~~|1<br>~~ee~~<br>~~ee~~|1<br>~~ee~~|1<br>~~ee~~|1<br>~~ee~~|
|Maximum Programmable<br>Single Ended I/O<br>~~a~~<br>~~a~~|37<br>~~ee~~|78<br>~~ee ee~~|102<br>~~ee~~|109|204|204|



© 2025 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02125-1.0 

76 

**MachXO4 Family Data Sheet** 

||**LFMXO4-025**<br>~~pT~~<br>~~es~~|**LFMXO4-025**<br>~~pT~~<br>~~es~~|**LFMXO4-025**<br>~~pT~~<br>~~es~~|**LFMXO4-025**<br>~~pT~~<br>~~es~~|**LFMXO4-025**<br>~~pT~~<br>~~es~~|**LFMXO4-025**<br>~~pT~~<br>~~es~~|
|---|---|---|---|---|---|---|
||**UUG49**<br>~~es~~|**TSG100**|**BSG132**|**TSG144**|**BBG256**|**BFG256**|
|**Differential I/Oper Bank**<br>~~es~~<br>~~pC~~<br>~~GO~~|||||||
|Bank 0<br>~~GG~~|9<br>~~GG~~|8<br>~~GG~~<br>~~Ge~~|11<br>~~GG~~<br>~~GO~~<br>~~GO~~|12<br>~~GG~~<br>~~GO~~<br>~~GO~~|23<br>~~GG~~<br>~~GO~~|23<br>~~GG~~|
|Bank 1<br>~~eG~~<br>~~po~~|0<br>~~eG~~|10<br>~~eG~~<br>~~Ge~~<br>~~Ge~~|13<br>~~GO~~<br>~~eG~~<br>~~GO~~<br>~~GO~~|14<br>~~GO~~<br>~~eG~~<br>~~GO~~<br>~~GO~~|26<br>~~GO~~<br>~~eG~~|26<br>~~eG~~|
|Bank 2<br>~~eG~~<br>~~po~~|6<br>~~eG~~|10<br>~~Ge~~<br>~~eG~~<br>~~Ge~~|14<br>~~GO~~<br>~~eG~~<br>~~GO~~|14<br>~~GO~~<br>~~eG~~<br>~~GO~~|26<br>~~eG~~|26<br>~~eG~~|
|Bank 3<br>~~po~~<br>~~pO~~|0|3<br>~~Ge~~|3<br>~~GO~~|4<br>~~GO~~|8|8|
|Bank 4<br>~~po~~<br>~~pO~~|0|3<br>~~Ge~~|4<br>~~GO~~|5<br>~~GO~~|8|8|
|Bank 5<br>~~pO~~|3|4|5|5|10|10|
|Total General Purpose<br>Differential I/O<br>~~a ~~|18<br> ~~ee~~|38<br>~~ee~~<br>~~Fe~~|50<br>~~ee~~<br>~~GO~~|54<br>~~ee~~<br>~~GO~~|101<br>~~ee~~|101<br>~~ee~~|
|Dual Function I/O<br>~~eG~~|25<br>~~eG~~|31<br>~~eG~~<br>~~Fe~~|33<br>~~eG~~<br>~~GO~~|33<br>~~eG~~<br>~~GO~~|33<br>~~eG~~|33<br>~~eG~~|
|**Number 7:1 or 8:1 Gearboxes**<br>~~Fe~~<br>~~GO~~<br>~~pt~~|||||||
|Number of 7:1 or 8:1<br>Output Gearbox Available<br>(Bank 0)|4|3|6|7|12|12|
|Number of 7:1 or 8:1 Input<br>Gearbox Available(Bank 2)|6|10|14|14|14|14|
|**High-speed Differential Outputs**|||||||
|Bank 0<br>~~pO~~|4<br>~~pO~~|3<br>~~pO~~|6<br>~~pO~~|7<br>~~pO~~|12<br>~~pO~~|12<br>~~pO~~|
|**VCCIO Pins**<br>~~rsGOO~~|||||||
|Bank 0<br>~~rs~~<br>~~po~~|2<br>~~GOO~~|3<br>~~GOO~~|4<br>~~GOO~~|4<br>~~GOO~~|5<br>~~GOO~~|5<br>~~GOO~~|
|Bank 1<br>~~rs~~<br>~~po~~<br>~~po~~|0<br>~~GOO~~|2<br>~~GOO~~|3<br>~~GOO~~|3<br>~~GOO~~|4<br>~~GOO~~|4<br>~~GOO~~|
|Bank 2<br>~~po~~<br>~~po~~<br>~~po~~|1|2|3|3|4|4|
|Bank 3<br>~~po~~<br>~~po~~<br>~~pO~~|0|1|1|1|1|1|
|Bank 4<br>~~po~~<br>~~pO~~|0|1|1<br>~~OO~~|1<br>~~OO~~|2<br>~~OO~~|2|
|Bank 5<br>~~pO~~<br>~~eC~~|1<br>~~eC~~|1<br>~~eC~~|1<br>~~eC~~<br>~~OO~~<br>~~GO~~|1<br>~~eC~~<br>~~OO~~<br>~~GO~~|1<br>~~eC~~<br>~~OO~~<br>~~GO~~|1<br>~~eC~~|
|VCC<br>~~eC~~<br>~~eG~~<br>~~pO~~|2<br>~~eC~~<br>~~eG~~|2<br>~~eC~~<br>~~eG~~|4<br>~~eC~~<br>~~OO~~<br>~~eG~~<br>~~GO~~<br>~~GO~~|4<br>~~eC~~<br>~~OO~~<br>~~eG~~<br>~~GO~~<br>~~GO~~|8<br>~~eC~~<br>~~OO~~<br>~~eG~~<br>~~GO~~|8<br>~~eC~~<br>~~eG~~|
|GND<br>~~eG~~<br>~~eG~~<br>~~pO~~|5<br>~~eG~~<br>~~eG~~|8<br>~~eG~~<br>~~eG~~|11<br>~~eG~~<br>~~GO~~<br>~~eG~~<br>~~GO~~|13<br>~~eG~~<br>~~GO~~<br>~~eG~~<br>~~GO~~|25<br>~~eG~~<br>~~GO~~<br>~~eG~~|25<br>~~eG~~<br>~~eG~~|
|NC<br>~~pO~~<br>~~po~~|0|1|1<br>~~GO~~|4<br>~~GO~~|1|1|
|Total Count of Bonded Pins<br>~~pO~~<br>~~po~~|49|100|132<br>~~GO~~|144<br>~~GO~~|256|256|



***Note:** One pin for JTAGENB or four pins for JTAG. 

© 2025 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02125-1.0 

77 

**MachXO4 Family Data Sheet** 

**Table 4.4. LFMXO4-050 Pin Summary** 

|~~pO~~|**LFMXO4-050**<br>~~pe~~<br>~~pO~~|**LFMXO4-050**<br>~~pe~~<br>~~pO~~|**LFMXO4-050**<br>~~pe~~<br>~~pO~~|**LFMXO4-050**<br>~~pe~~<br>~~pO~~|**LFMXO4-050**<br>~~pe~~<br>~~pO~~|**LFMXO4-050**<br>~~pe~~<br>~~pO~~|
|---|---|---|---|---|---|---|
||**UUG81**<br>~~pO~~|**BSG132**|**TSG144**|**BBG256**|**BFG256**|**BBG400**|
|**General Purpose I/Oper Bank**<br>~~pO~~<br>~~Pe~~<br>~~Ge~~<br>~~ee~~|||||||
|Bank 0<br>~~eG~~<br>~~ee~~|28<br>~~eG~~<br>|24<br>~~eG~~<br>|26<br>~~eG~~<br>~~Ge~~|49<br>~~eG~~<br>~~Ge~~|49<br>~~eG~~|82<br>~~eG~~|
|Bank 1<br>~~ee~~<br>~~ee~~|0<br>~~GG~~<br>|26<br>~~GG~~<br>|29<br>~~Ge~~<br>~~GO~~|52<br>~~Ge~~<br>~~GO~~|52|84|
|Bank 2<br>~~ee~~<br>~~ee~~<br>~~po~~|20<br>~~GG~~<br>~~GG~~|28<br>~~GG~~<br>~~GG~~|29<br>~~Ge~~<br>~~GO~~<br>~~GO~~|52<br>~~Ge~~<br>~~GO~~<br>~~GO~~|52|84|
|Bank 3<br><br>~~ee~~<br>~~po~~<br>~~ee~~|7<br>~~GG~~<br>~~GG~~<br>|7<br>~~GG~~<br>~~GG~~<br>|9<br>~~GO~~<br>~~GO~~<br>~~GO~~|16<br>~~GO~~<br>~~GO~~<br>~~GO~~|16|28|
|Bank 4<br><br>~~po~~<br>~~eG~~<br>~~ee~~|0<br>~~GG~~<br>~~eG~~<br>|8<br>~~GG~~<br>~~eG~~<br>|10<br>~~GO~~<br>~~eG~~<br>~~GO~~|16<br>~~GO~~<br>~~eG~~<br>~~GO~~|16<br>~~eG~~|24<br>~~eG~~|
|Bank 5<br>~~ee~~|7<br>~~eG~~|10<br>~~eG~~|10<br>~~GO~~<br>~~GO~~|20<br>~~GO~~<br>~~GO~~|20|32|
|Total General Purpose<br>Single Ended I/O<br>~~ee~~<br>~~a~~|62<br><br>~~ee~~|103<br><br>~~ee~~|113<br>~~GO~~<br>~~ee~~|205<br>~~GO~~|205|334|
|Minimum Reserved for<br>Configuration*<br>~~a~~|1|1|1|1|1|1|
|Maximum Programmable<br>Single Ended I/O<br>~~a~~|61<br>~~ee~~|102<br>~~ee~~|112|204|204|333|
|**Differential I/Oper Bank**<br>~~Re~~<br>~~eeGG~~|||||||
|Bank 0<br>~~ee~~<br>~~po~~|13<br>~~GG~~|11<br>~~GG~~|12<br>~~GG~~|23<br>~~GG~~|23<br>~~GG~~|40<br>~~GG~~|
|Bank 1<br>~~ee~~<br>~~po~~|0<br>~~GG~~|13<br>~~GG~~|14<br>~~GG~~<br>~~GO~~|26<br>~~GG~~<br>~~GO~~|26<br>~~GG~~<br>~~GO~~|42<br>~~GG~~|
|Bank 2<br>~~po~~<br>~~eG~~<br>~~ee~~|10<br>~~eG~~<br>|14<br>~~eG~~<br>~~Ge~~<br>|14<br>~~eG~~<br>~~GO~~<br>~~GO~~|26<br>~~eG~~<br>~~GO~~<br>~~GO~~|26<br>~~eG~~<br>~~GO~~|42<br>~~eG~~|
|Bank 3<br>~~eG~~<br>~~eG~~<br>~~ee~~|3<br>~~eG~~<br>~~eG~~<br>|3<br>~~eG~~<br>~~eG~~<br>~~Ge~~<br>|4<br>~~eG~~<br>~~GO~~<br>~~eG~~<br>~~GO~~|8<br>~~eG~~<br>~~GO~~<br>~~eG~~<br>~~GO~~|8<br>~~eG~~<br>~~GO~~<br>~~eG~~|14<br>~~eG~~<br>~~eG~~|
|Bank 4<br>~~ee~~<br>~~ee~~|0<br>~~Ge~~|4<br>~~Ge~~<br>~~Ge~~|5<br>~~GO~~<br>~~GO~~|8<br>~~GO~~<br>~~GO~~|8|12|
|Bank 5<br>~~ee ~~<br>~~ee~~|3<br> ~~Ge~~<br>~~Ge~~|5<br>~~Ge~~<br>~~Ge~~<br>~~Ge~~|5<br>~~GO~~<br>~~GO~~<br>~~GO~~|10<br>~~GO~~<br>~~GO~~<br>~~GO~~|10|16|
|**Total General Purpose**<br>**Differential I/O**<br> <br>~~ee~~<br>~~a~~<br>~~es~~|29<br> ~~Ge~~|50<br>~~Ge~~|54<br>~~GO~~<br>~~(O~~|101<br>~~GO~~<br>~~(O~~|101|166|
|**Dual Function I/O**<br>~~a~~<br>~~es~~|25|37|37<br>~~(O~~|37<br>~~(O~~|37|37|
|**Number 7:1 or 8:1 Gearboxes**<br>~~es~~<br>~~(O~~|||||||
|Number of 7:1 or 8:1<br>Output Gearboxes<br>Available(Bank 0)|8|6|7|16|16|19|
|Number of 7:1 or 8:1 Input<br>Gearboxes Available (Bank<br>2)|10|14|14|18|18|21|
|**High-speed Differential Outputs**<br>~~|~~<br>~~ee (O~~|||||||
|Bank 0<br>~~|~~<br>~~ee~~|8<br>~~|~~<br>~~ee~~|6<br>~~|~~<br>~~(O~~|7<br>~~|~~<br>~~(O~~|16<br>~~|~~<br>~~(O~~|16<br>~~|~~|19<br>~~|~~|
|**VCCIO Pins**<br>~~ee  (O~~<br>~~pn~~<br>~~**e**e~~<br>~~Ge~~<br>~~GO~~|||||||
|Bank 0<br>~~**e**e~~<br>~~po~~|4<br>~~Ge~~|4<br>~~Ge~~|4<br>~~GO~~<br>~~Ge~~|5<br>~~GO~~<br>~~Ge~~|5|6|
|Bank 1<br>~~**e**e~~<br>~~po~~|0<br>~~Ge~~|3<br>~~Ge~~|3<br>~~GO~~<br>~~G~~<br>~~Ge~~|4<br>~~GO~~<br>~~G~~<br>~~Ge~~|4<br>~~G~~|5<br>~~G~~|
|Bank 2<br>~~po~~<br>~~**e**e~~|2|3|3<br>~~Ge~~<br>~~GO~~|4<br>~~Ge~~<br>~~GO~~|4<br>~~GO~~|5|
|Bank 3<br>~~po~~<br>~~eG~~<br>~~**e**e~~|1<br>~~eG~~|1<br>~~eG~~|1<br>~~Ge~~<br>~~eG~~<br>~~GO~~|1<br>~~Ge~~<br>~~eG~~<br>~~GO~~|1<br>~~eG~~<br>~~GO~~|2<br>~~eG~~|
|Bank 4<br>~~eG~~<br>~~**e**e~~|0<br>~~eG~~<br>~~Ge~~|1<br>~~eG~~<br>~~Ge~~|1<br>~~eG~~<br>~~GO~~<br>~~GO~~<br>~~GO~~|2<br>~~eG~~<br>~~GO~~<br>~~GO~~<br>~~GO~~|2<br>~~eG~~<br>~~GO~~|2<br>~~eG~~|
|Bank 5<br>~~**e**e~~<br>~~pO~~|1|1|1<br>~~GO~~<br>~~G~~<br>~~GO~~<br>~~GO~~|1<br>~~GO~~<br>~~G~~<br>~~GO~~<br>~~GO~~|1<br>~~GO~~<br>~~G~~|2<br>~~G~~|
|VCC<br>~~eG~~<br>~~pO~~|4<br>~~eG~~|4<br>~~eG~~|4<br>~~GO~~<br>~~eG~~<br>~~GO~~|8<br>~~GO~~<br>~~eG~~<br>~~GO~~|8<br>~~eG~~|10<br>~~eG~~|
|GND<br>~~pO~~<br>~~ee~~|7<br>~~GG~~|11<br>~~GG~~|13<br>~~GO~~<br>~~GG~~|25<br>~~GO~~<br>~~GG~~|25<br>~~GG~~|34<br>~~GG~~|
|NC<br>~~pO~~<br>~~ee~~|0<br>~~GG~~|1<br>~~GG~~|1<br>~~GO~~<br>~~GG~~<br>~~DG~~|1<br>~~GO~~<br>~~GG~~<br>~~DG~~|1<br>~~GG~~|0<br>~~GG~~|
|Total Count of Bonded Pins<br>~~ee~~<br>~~Ge~~|81<br>~~GG~~<br>~~Ge~~|132<br>~~GG~~<br>~~Ge~~|144<br>~~GG~~<br>~~Ge~~<br>~~DG~~|256<br>~~GG~~<br>~~Ge~~<br>~~DG~~|256<br>~~GG~~<br>~~Ge~~|400<br>~~GG~~<br>~~Ge~~|



***Note:** One pin for JTAGENB or four pins for JTAG. 

© 2025 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02125-1.0 

78 

> **MachXO4 Family** mLATTICE **Data Sheet Table 4.5. LFMXO4-080 Pin Summary LFMXO4-080** ~~pT~~ **BBG256 BBG400** ~~pf Pe~~ **General Purpose I/O per Bank** Bank 0 49 82 ~~Ge~~ Bank 1 52 84 ~~eG~~ Bank 2 52 84 ~~eG~~ Bank 3 16 28 ~~a~~ Bank 4 16 24 ~~Ge~~ Bank 5 20 32 ~~eG eG~~ Total General Purpose Single Ended I/O 205 334 ~~eG~~ Minimum Reserved for Configuration* 1 1 ~~Ge~~ Maximum Programmable Single Ended I/O 204 333 ~~RT~~ **Differential I/O per Bank** Bank 0 23 40 ~~eG~~ Bank 1 26 42 ~~eG~~ Bank 2 26 42 ~~eG~~ Bank 3 8 14 Bank 4 8 12 ~~eG~~ Bank 5 10 16 ~~eG eG~~ Total General Purpose Differential I/O 101 166 ~~Ge~~ Dual Function I/O 37 37 **Number 7:1 or 8:1 Gearboxes** ~~pT~~ Number of 7:1 or 8:1 Output Gearbox Available 18 19 (Bank 0) Number of 7:1 or 8:1 Input Gearbox Available 20 21 (Bank 2) ~~pT~~ **High-speed Differential Outputs** Bank 0 18 19 ~~eG~~ **VCCIO Pins** Bank 0 5 6 ~~Ge~~ Bank 1 4 5 ~~Ge~~ Bank 2 4 5 ~~a~~ Bank 3 1 2 ~~pf~~ Bank 4 2 2 ~~a G~~ Bank 5 1 2 ~~Ge~~ VCC 8 10 ~~Ge~~ GND 25 34 ~~a~~ NC 1 0 ~~pf~~ Total Count of Bonded Pins 256 400 ~~a ==~~ ***Note:** One pin for JTAGENB or four pins for JTAG. © 2025 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02125-1.0 

79 

**MachXO4 Family Data Sheet** 

## **Table 4.6. LFMXO4-110 Pin Summary** 

|~~po~~|**LFMXO4-110**<br>~~pT~~<br>~~po~~|**LFMXO4-110**<br>~~pT~~<br>~~po~~|**LFMXO4-110**<br>~~pT~~<br>~~po~~|
|---|---|---|---|
||**BBG256**<br>~~po~~|**BBG400**|**BBG484**|
|**General Purpose I/Oper Bank**<br>~~po~~<br>~~Pe~~||||
|Bank 0<br>~~Ge~~|49<br>~~Ge~~|82<br>~~Ge~~|94<br>~~Ge~~|
|Bank 1<br>~~Ge~~|52<br>~~Ge~~|84<br>~~Ge~~|96<br>~~Ge~~|
|Bank 2<br>~~Ge~~|52<br>~~Ge~~|84<br>~~Ge~~|96<br>~~Ge~~|
|Bank 3<br>~~GC~~|16<br>~~GC~~|28<br>~~GC~~|36<br>~~GC~~|
|Bank 4<br>~~Ge~~|16<br>~~Ge~~|24<br>~~Ge~~|24<br>~~Ge~~|
|Bank 5<br>~~Ge~~|20<br>~~Ge~~|32<br>~~Ge~~|36<br>~~Ge~~|
|Total General Purpose Single Ended I/O<br>~~Ge~~|205<br>~~Ge~~|334<br>~~Ge~~|382<br>~~Ge~~|
|Minimum Reserved for Configuration*<br>~~Ge~~|1<br>~~Ge~~|1<br>~~Ge~~|1<br>~~Ge~~|
|Maximum Programmable Single Ended I/O<br>~~De~~|204<br>~~De~~|333<br>~~De~~|381<br>~~De~~|
|**Differential I/Oper Bank**<br>~~Re~~||||
|Bank 0<br>~~GO~~|23<br>~~GO~~|40<br>~~GO~~|46<br>~~GO~~|
|Bank 1<br>~~GO~~<br>~~Ge~~|26<br>~~GO~~<br>~~Ge~~|42<br>~~GO~~<br>~~Ge~~|48<br>~~GO~~<br>~~Ge~~|
|Bank 2<br>~~Ge~~|26<br>~~Ge~~|42<br>~~Ge~~|48<br>~~Ge~~|
|Bank 3|8|14|18|
|Bank 4<br>~~Ge~~|8<br>~~Ge~~|12<br>~~Ge~~|12<br>~~Ge~~|
|Bank 5<br>~~Ge~~<br>~~Ge~~|10<br>~~Ge~~<br>~~Ge~~|16<br>~~Ge~~<br>~~Ge~~|18<br>~~Ge~~<br>~~Ge~~|
|Total General Purpose Differential I/O<br>~~Ge~~<br>~~Ge~~|101<br>~~Ge~~<br>~~Ge~~|166<br>~~Ge~~<br>~~Ge~~|190<br>~~Ge~~<br>~~Ge~~|
|Dual Function I/O<br>~~De~~|37<br>~~De~~|37<br>~~De~~|45<br>~~De~~|
|**Number 7:1 or 8:1 Gearboxes**<br>~~pe~~||||
|Number of 7:1 or 8:1 Output Gearbox<br>Available(Bank 0)<br>~~pe~~|18<br>~~pe~~|20<br>~~pe~~|22<br>~~pe~~|
|Number of 7:1 or 8:1 Input Gearbox Available<br>(Bank 2)|20|22|24|
|**High-speed Differential Outputs**<br>~~pn~~||||
|Bank 0<br>~~pn~~<br>~~De~~|18<br>~~pn~~<br>~~De~~|20<br>~~pn~~<br>~~De~~|22<br>~~pn~~<br>~~De~~|
|**VCCIO Pins**<br>~~De~~||||
|Bank 0<br>~~Ge~~|5<br>~~Ge~~|6<br>~~Ge~~|10<br>~~Ge~~|
|Bank 1<br>~~Ge~~|4<br>~~Ge~~|5<br>~~Ge~~|9<br>~~Ge~~|
|Bank 2<br>~~a~~|4|5|9|
|Bank 3<br>~~a~~<br>~~eG~~|1<br>~~eG~~|2<br>~~eG~~|3<br>~~eG~~|
|Bank 4<br>~~eG~~<br>~~Ge~~|2<br>~~eG~~<br>~~Ge~~|2<br>~~eG~~<br>~~Ge~~|3<br>~~eG~~<br>~~Ge~~|
|Bank 5<br>~~Ge~~|1<br>~~Ge~~|2<br>~~Ge~~|3<br>~~Ge~~|
|VCC<br>~~Ge~~|8<br>~~Ge~~|10<br>~~Ge~~|12<br>~~Ge~~|
|GND<br>~~a~~|25|34|53|
|NC<br>~~a~~<br>~~eG~~|1<br>~~eG~~|0<br>~~eG~~|0<br>~~eG~~|
|Total Count of Bonded Pins<br>~~eG~~<br>~~Ge~~|256<br>~~eG~~<br>~~Ge~~|400<br>~~eG~~<br>~~Ge~~|484<br>~~eG~~<br>~~Ge~~|



***Note:** One pin for JTAGENB or four pins for JTAG. 

© 2025 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02125-1.0 

80 

**MachXO4 Family Data Sheet** 

## **5. MachXO4 Part Number Description** 

## LFMXO4 – XXX X X – X XXXXXX X XX 

**Device Family:** MachXO4 FPGA 

**Logic Capacity:** 010 = 896 LUTs 015 = 1280 LUTs 025 = 2112 LUTs 050 = 4320 LUTs 080 = 6864 LUTs 110 = 9400 LUTs 

**Shipping Method:** Blank = Trays TR = Tape and Reel TR1K =  1000 parts per reel 

## **Grade:** 

C = Commercial I = Industrial A = Automotive 

## **Power/Performance:** 

H = High Performance 

**Supply Voltage:** 

C = 2.5 V / 3.3 V E = 1.2 V 

**Speed:** 5 = Slow High Performance 6 = Fast } 

## **Package:** 

UUG36 = 36-Ball WLCSP (0.4 mm pitch) UUG49 = 49-Ball  WLCSP (0.4 mm pitch) UUG81 = 81-Ball  WLCSP (0.4 mm pitch) TSG100 = 100-Pin TQFP (0.5 mm pitch) BSG132 = 132-Ball csBGA (0.5 mm pitch) TSG144 = 144-Pin  TQFP (0.5 mm pitch) BBG256 = 256-Ball  caBGA (0.8 mm pitch) BBG400 = 400-Ball  caBGA (0.8 mm pitch) BBG484 = 484-Ball  caBGA (0.8 mm pitch) BFG256 = 256-Ball ftBGA (1.0 mm pitch) 

© 2025 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02125-1.0 

81 

**MachXO4 Family Data Sheet** 

## **6. Ordering Information** 

- For all MachXO4 devices in 100-TQFP and 132-csBGA packages, the top-side marking below is used. 

**==> picture [107 x 70] intentionally omitted <==**

**----- Start of picture text -----**<br>
MachXO4<br>Lot -ID<br>2D Barcode ID COO Datecode<br>**----- End of picture text -----**<br>


- For all MachXO4 devices in WLCSP packages, the markings are abbreviated and adhered to the sample format shown below. 

**==> picture [102 x 260] intentionally omitted <==**

**----- Start of picture text -----**<br>
XO4-015<br>LFMXO4-110HC6BG256C 5UUGC<br>LOT-IDLOT-ID<br>COO<br>LATTICE<br>LFMXO4-015HC<br>5BBG256C<br>LOT-ID<br>COO YYWW<br>ASSY LOT<br>**----- End of picture text -----**<br>


- Other MachXO4 devices have a topside marking format as shown below. 

## **6.1. MachXO4 High Performance Commercial Grade Devices, Packaging** 

|**Part Number**<br>~~a~~<br>~~po~~|**LUTs**<br>~~OC~~|**Supply Voltage **<br>~~OC~~|**Speed**<br>~~OC~~|**Package **|**Pins**|**Temp. **|
|---|---|---|---|---|---|---|
|LFMXO4-010HE-5TSG100C<br>~~po~~<br>~~po~~|896|1.2 V|5|TSG100|100|COM|
|LFMXO4-010HE-6TSG100C<br>~~po~~<br>~~po~~<br>~~po~~|896|1.2 V|6|TSG100|100|COM|
|LFMXO4-010HE-5BSG132C<br>~~po~~<br>~~po~~<br>~~po~~|896|1.2 V|5|BSG132|132|COM|
|LFMXO4-010HE-6BSG132C<br>~~po~~<br>~~po~~|896|1.2 V|6|BSG132|132|COM|
|LFMXO4-010HE-5TSG144C<br>~~po~~<br>~~Gs~~|896<br>~~Gs~~|1.2 V<br>~~Gs~~|5<br>~~Gs~~|TSG144<br>~~Gs~~|144<br>~~Gs~~|COM<br>~~Gs~~|
|LFMXO4-010HE-6TSG144C<br>~~po~~|896<br>~~po~~|1.2 V<br>~~po~~|6<br>~~po~~|TSG144<br>~~po~~|144<br>~~po~~|COM<br>~~po~~|



All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

© 2025 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02125-1.0 

82 

**MachXO4 Family Data Sheet** 

|**Part Number**<br>**LUTs**<br>**Supply Voltage **<br>**Speed**<br>**Package **<br>**Pins**<br>**Temp. **<br>LFMXO4-010HC-5TSG100C<br>896<br>2.5 V / 3.3 V<br>5<br>TSG100<br>100<br>COM<br>LFMXO4-010HC-6TSG100C<br>896<br>2.5 V / 3.3 V<br>6<br>TSG100<br>100<br>COM<br>~~pO~~<br>~~ee~~<br>~~GG~~<br>~~eG~~|
|---|
|LFMXO4-010HC-5BSG132C<br>896<br>2.5 V / 3.3 V<br>5<br>BSG132<br>132<br>COM<br>~~GG~~|
|LFMXO4-010HC-6BSG132C<br>896<br>2.5 V / 3.3 V<br>6<br>BSG132<br>132<br>COM<br>~~eeGG~~|
|LFMXO4-010HC-5TSG144C<br>896<br>2.5 V / 3.3 V<br>5<br>TSG144<br>144<br>com<br>~~eeGG~~|
|LFMXO4-010HC-6TSG144C<br>896<br>2.5 V / 3.3 V<br>6<br>TSG144<br>144<br>COM<br>~~po~~|
|**Part Number**<br>**LUTs**<br>**Supply Voltage **<br>**Speed**<br>**Package **<br>**Pins**<br>**Temp. **<br>LFMXO4-015HE-5UUG36C<br>1280<br>1.2 V<br>5<br>UUG36<br>36<br>COM<br>~~pO~~<br>~~GO~~|
|LFMXO4-015HE-5UUG36CTR1K<br>1280<br>1.2 V<br>5<br>UUG36<br>36<br>COM<br>~~eeGG~~|
|LFMXO4-015HE-5TSG100C<br>1280<br>1.2 V<br>5<br>TSG100<br>100<br>COM<br>~~CO~~|
|LFMXO4-015HE-6TSG100C<br>1280<br>1.2 V<br>6<br>TSG100<br>100<br>COM<br>~~eG~~|
|LFMXO4-015HE-5BSG132C<br>1280<br>1.2 V<br>5<br>BSG132<br>132<br>COM<br>~~eG~~|
|LFMXO4-015HE-6BSG132C<br>1280<br>1.2 V<br>6<br>BSG132<br>132<br>COM<br>~~GG~~|
|LFMXO4-015HE-5TSG144C<br>1280<br>1.2 V<br>5<br>TSG144<br>144<br>COM<br>~~eG~~|
|LFMXO4-015HE-6TSG144C<br>1280<br>1.2 V<br>6<br>TSG144<br>144<br>COM<br>~~Ge~~<br>~~GO~~|
|LFMXO4-015HE-5BBG256C<br>1280<br>1.2 V<br>5<br>BBG256<br>256<br>COM<br>~~ee~~|
|LFMXO4-015HE-6BBG256C<br>1280<br>1.2 V<br>6<br>BBG256<br>256<br>COM<br>~~ee~~|
|LFMXO4-015HE-5BFG256C<br>1280<br>1.2 V<br>5<br>BFG256<br>256<br>COM<br>~~eeGG~~|
|LFMXO4-015HE-6BFG256C<br>1280<br>1.2 V<br>6<br>BFG256<br>256<br>COM<br>~~eG~~|
|LFMXO4-015HC-5TSG100C<br>1280<br>2.5 V / 3.3 V<br>5<br>TSG100<br>100<br>COM<br>~~eG~~|
|LFMXO4-015HC-6TSG100C<br>1280<br>2.5 V / 3.3 V<br>6<br>TSG100<br>100<br>COM<br>~~Ge~~<br>~~GO~~|
|LFMXO4-015HC-5BSG132C<br>1280<br>2.5 V / 3.3 V<br>5<br>BSG132<br>132<br>COM<br>~~ee~~|
|LFMXO4-015HC-6BSG132C<br>1280<br>2.5 V / 3.3 V<br>6<br>BSG132<br>132<br>COM<br>~~eeGG~~|
|LFMXO4-015HC-5TSG144C<br>1280<br>2.5 V / 3.3 V<br>5<br>TSG144<br>144<br>COM<br>~~eG~~|
|LFMXO4-015HC-6TSG144C<br>1280<br>2.5 V / 3.3 V<br>6<br>TSG144<br>144<br>COM<br>~~eG~~|
|LFMXO4-015HC-5BBG256C<br>1280<br>2.5 V / 3.3 V<br>5<br>BBG256<br>256<br>COM<br>~~eC~~<br>~~GG~~|
|LFMXO4-015HC-6BBG256C<br>1280<br>2.5 V / 3.3 V<br>6<br>BBG256<br>256<br>COM<br>~~GO~~|
|LFMXO4-015HC-5BFG256C<br>1280<br>2.5 V / 3.3 V<br>5<br>BFG256<br>256<br>COM<br>LFMXO4-015HC-6BFG256C<br>1280<br>2.5 V / 3.3 V<br>5<br>BFG256<br>256<br>COM<br>~~eeSG~~<br>~~po~~|
|**Part Number**<br>**LUTs**<br>**Supply Voltage **<br>**Speed**<br>**Package **<br>**Pins**<br>**Temp. **<br>~~pT~~|
|LFMXO4-025HE-5UUG49C<br>2112<br>1.2 V<br>5<br>UUG49<br>49<br>COM<br>~~GO~~|
|LFMXO4-025HE-5UUG49CTR1K<br>2112<br>1.2 V<br>5<br>UUG49<br>49<br>COM<br>~~eeSG~~|
|LFMXO4-025HE-5TSG100C<br>2112<br>1.2 V<br>5<br>TSG100<br>100<br>COM<br>~~GG~~|
|LFMXO4-025HE-6TSG100C<br>2112<br>1.2 V<br>6<br>TSG100<br>100<br>COM<br>~~GG~~|
|LFMXO4-025HE-5BSG132C<br>2112<br>1.2 V<br>5<br>BSG132<br>132<br>COM<br>~~eG~~<br>~~GG~~|
|LFMXO4-025HE-6BSG132C<br>2112<br>1.2 V<br>6<br>BSG132<br>132<br>COM<br>~~GO~~|
|LFMXO4-025HE-5TSG144C<br>2112<br>1.2 V<br>5<br>TSG144<br>144<br>COM<br>LFMXO4-025HE-6TSG144C<br>2112<br>1.2 V<br>6<br>TSG144<br>144<br>COM<br>LFMXO4-025HE-5BBG256C<br>2112<br>1.2 V<br>5<br>BBG256<br>256<br>COM<br>LFMXO4-025HE-6BBG256C<br>2112<br>1.2 V<br>6<br>BBG256<br>256<br>COM<br>~~OO~~<br>~~ee~~<br>~~GG~~<br>~~ee~~<br>~~GG~~<br>~~eG~~<br>~~GC~~|
|LFMXO4-025HE-5BFG256C<br>2112<br>1.2 V<br>5<br>BFG256<br>256<br>COM<br>~~CO~~|
|LFMXO4-025HE-6BFG256C<br>2112<br>1.2 V<br>6<br>BFG256<br>256<br>COM<br>~~CO~~|
|LFMXO4-025HC-5TSG100C<br>2112<br>2.5 V / 3.3 V<br>5<br>TSG100<br>100<br>COM<br>~~eG~~|
|LFMXO4-025HC-6TSG100C<br>2112<br>2.5 V / 3.3 V<br>6<br>TSG100<br>100<br>COM<br>~~GG~~|
|LFMXO4-025HC-5BSG132C<br>2112<br>2.5 V / 3.3 V<br>5<br>BSG132<br>132<br>COM<br>~~GC~~|
|LFMXO4-025HC-6BSG132C<br>2112<br>2.5 V / 3.3 V<br>6<br>BSG132<br>132<br>COM<br>~~DO~~|



© 2025 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02125-1.0 

All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

83 

**MachXO4 Family Data Sheet** 

|**Part Number**<br>**LUTs**<br>**Supply Voltage **<br>**Speed**<br>**Package **<br>**Pins**<br>**Temp. **<br>LFMXO4-025HC-5TSG144C<br>2112<br>2.5 V / 3.3 V<br>5<br>TSG144<br>144<br>COM<br>LFMXO4-025HC-6TSG144C<br>2112<br>2.5 V / 3.3 V<br>6<br>TSG144<br>144<br>COM<br>~~pO~~<br>~~ee~~<br>~~GG~~<br>~~eG~~|
|---|
|LFMXO4-025HC-5BBG256C<br>2112<br>2.5 V / 3.3 V<br>5<br>BBG256<br>256<br>COM<br>~~GG~~|
|LFMXO4-025HC-6BBG256C<br>2112<br>2.5 V / 3.3 V<br>6<br>BBG256<br>256<br>COM<br>~~eeGG~~|
|LFMXO4-025HC-5BFG256C<br>2112<br>2.5 V / 3.3 V<br>5<br>BFG256<br>256<br>COM<br>~~eeGG~~|
|LFMXO4-025HC-6BFG256C<br>2112<br>2.5 V / 3.3 V<br>6<br>BFG256<br>256<br>COM<br>~~po~~|
|**Part Number**<br>**LUTs**<br>**Supply Voltage **<br>**Speed**<br>**Package **<br>**Pins**<br>**Temp. **<br>LFMXO4-050HE-5UUG81C<br>4320<br>1.2 V<br>5<br>UUG81<br>81<br>COM<br>~~pO~~<br>~~GO~~|
|LFMXO4-050HE-5UUG81CTR1K<br>4320<br>1.2 V<br>5<br>UUG81<br>81<br>COM<br>~~eeGG~~|
|LFMXO4-050HE-5BSG132C<br>4320<br>1.2 V<br>5<br>BSG132<br>132<br>COM<br>~~CO~~|
|LFMXO4-050HE-6BSG132C<br>4320<br>1.2 V<br>6<br>BSG132<br>132<br>COM<br>~~eG~~|
|LFMXO4-050HE-5TSG144C<br>4320<br>1.2 V<br>5<br>TSG144<br>144<br>COM<br>~~eG~~|
|LFMXO4-050HE-6TSG144C<br>4320<br>1.2 V<br>6<br>TSG144<br>144<br>COM<br>~~GG~~|
|LFMXO4-050HE-5BBG256C<br>4320<br>1.2 V<br>5<br>BBG256<br>256<br>COM<br>~~eG~~|
|LFMXO4-050HE-6BBG256C<br>4320<br>1.2 V<br>6<br>BBG256<br>256<br>COM<br>~~Ge~~<br>~~GO~~|
|LFMXO4-050HE-5BBG400C<br>4320<br>1.2 V<br>5<br>BBG400<br>400<br>COM<br>~~ee~~|
|LFMXO4-050HE-6BBG400C<br>4320<br>1.2 V<br>6<br>BBG400<br>400<br>COM<br>~~ee~~|
|LFMXO4-050HE-5BFG256C<br>4320<br>1.2 V<br>5<br>BFG256<br>256<br>COM<br>~~eeGG~~|
|LFMXO4-050HE-6BFG256C<br>4320<br>1.2 V<br>6<br>BFG256<br>256<br>COM<br>~~eG~~|
|LFMXO4-050HC-5BSG132C<br>4320<br>2.5 V / 3.3 V<br>5<br>BSG132<br>132<br>COM<br>~~eG~~|
|LFMXO4-050HC-6BSG132C<br>4320<br>2.5 V / 3.3 V<br>6<br>BSG132<br>132<br>COM<br>~~Ge~~<br>~~GO~~|
|LFMXO4-050HC-5TSG144C<br>4320<br>2.5 V / 3.3 V<br>5<br>TSG144<br>144<br>COM<br>~~ee~~|
|LFMXO4-050HC-6TSG144C<br>4320<br>2.5 V / 3.3 V<br>6<br>TSG144<br>144<br>COM<br>~~eeGG~~|
|LFMXO4-050HC-5BBG256C<br>4320<br>2.5 V / 3.3 V<br>5<br>BBG256<br>256<br>COM<br>~~eG~~|
|LFMXO4-050HC-6BBG256C<br>4320<br>2.5 V / 3.3 V<br>6<br>BBG256<br>256<br>COM<br>~~eG~~|
|LFMXO4-050HC-5BBG400C<br>4320<br>2.5 V / 3.3 V<br>5<br>BBG400<br>400<br>COM<br>~~eC~~<br>~~GG~~|
|LFMXO4-050HC-6BBG400C<br>4320<br>2.5 V / 3.3 V<br>6<br>BBG400<br>400<br>COM<br>~~GO~~|
|LFMXO4-050HC-5BFG256C<br>4320<br>2.5 V / 3.3 V<br>5<br>BFG256<br>256<br>COM<br>LFMXO4-050HC-6BFG256C<br>4320<br>2.5 V / 3.3 V<br>6<br>BFG256<br>256<br>COM<br>~~eeSG~~<br>~~po~~|
|**Part Number**<br>**LUTs**<br>**Supply Voltage **<br>**Speed**<br>**Package **<br>**Pins**<br>**Temp. **<br>~~pT~~|
|LFMXO4-080HE-5BBG256C<br>6864<br>1.2 V<br>5<br>BBG256<br>256<br>COM<br>~~GO~~|
|LFMXO4-080HE-6BBG256C<br>6864<br>1.2 V<br>6<br>BBG256<br>256<br>COM<br>~~eeSG~~|
|LFMXO4-080HE-5BBG400C<br>6864<br>1.2 V<br>5<br>BBG400<br>400<br>COM<br>~~GG~~|
|LFMXO4-080HE-6BBG400C<br>6864<br>1.2 V<br>6<br>BBG400<br>400<br>COM<br>~~GG~~|
|LFMXO4-080HC-5BBG256C<br>6864<br>2.5 V / 3.3 V<br>5<br>BBG256<br>256<br>COM<br>~~eG~~<br>~~GG~~|
|LFMXO4-080HC-6BBG256C<br>6864<br>2.5 V / 3.3 V<br>6<br>BBG256<br>256<br>COM<br>~~GO~~|
|LFMXO4-080HC-5BBG400C<br>6864<br>2.5 V / 3.3 V<br>5<br>BBG400<br>400<br>COM<br>~~OO~~|
|LFMXO4-080HC-6BBG400C<br>6864<br>2.5 V / 3.3 V<br>6<br>BBG400<br>400<br>COM<br>~~DF~~|
||
|**Part Number**<br>**LUTs**<br>**Supply Voltage **<br>**Speed**<br>**Package **<br>**Pins**<br>**Temp. **<br>~~GOO~~|
|LFMXO4-110HE-5BBG256C<br>9400<br>1.2 V<br>5<br>BBG256<br>256<br>COM<br>~~GG~~|
|LFMXO4-110HE-6BBG256C<br>9400<br>1.2 V<br>6<br>BBG256<br>256<br>COM<br>~~CO~~|
|LFMXO4-110HE-5BBG400C<br>9400<br>1.2 V<br>5<br>BBG400<br>400<br>COM<br>~~eG~~|
|LFMXO4-110HE-6BBG400C<br>9400<br>1.2 V<br>6<br>BBG400<br>400<br>COM<br>~~GG~~|
|LFMXO4-110HE-5BBG484C<br>9400<br>1.2 V<br>5<br>BBG484<br>484<br>COM<br>~~GC~~|
|LFMXO4-110HE-6BBG484C<br>9400<br>1.2 V<br>6<br>BBG484<br>484<br>COM<br>~~DO~~|



© 2025 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02125-1.0 

84 

**MachXO4 Family Data Sheet** 

**Part Number LUTs Supply Voltage Speed Package Pins Temp.** ~~pO ee~~ LFMXO4-110HC-5BBG256C 9400 ~~GG~~ 2.5 V / 3.3 V 5 BBG256 256 COM ~~eG~~ LFMXO4-110HC-6BBG256C 9400 2.5 V / 3.3 V 6 BBG256 256 COM ~~GG~~ LFMXO4-110HC-5BBG400C 9400 2.5 V / 3.3 V 5 BBG400 400 COM ~~ee~~ LFMXO4-110HC-6BBG400C 9400 ~~GG~~ 2.5 V / 3.3 V 6 BBG400 400 COM ~~ee~~ LFMXO4-110HC-5BBG484C 9400 ~~GG~~ 2.5 V / 3.3 V 5 BBG484 484 COM ~~po~~ LFMXO4-110HC-6BBG484C 9400 2.5 V / 3.3 V 6 BBG484 484 COM 

**6.2. MachXO4 High Performance Industrial Grade Devices, Packaging** 

**==> picture [487 x 508] intentionally omitted <==**

**----- Start of picture text -----**<br>
|||||||||||
|---|---|---|---|---|---|---|---|---|---|
|pO|Part Number|LUTs|Supply Voltage|Speed|Package|Pins|Temp.|
|LFMXO4-010HE-5TSG100I|896|1.2 V|5|TSG100|100|IND|
|eeGG|
|LFMXO4-010HE-6TSG100I|896|1.2 V|6|TSG100|100|IND|
|OO|
|LFMXO4-010HE-5BSG132I|896|1.2 V|5|BSG132|132|IND|
|ee|
|LFMXO4-010HE-6BSG132I|896|1.2 V|6|BSG132|132|IND|
|eeGG|
|LFMXO4-010HE-5TSG144I|896|1.2 V|5|TSG144|144|IND|
|eG|
|LFMXO4-010HE-6TSG144I|896|1.2 V|6|TSG144|144|IND|
|Ge|GO|
|ee|LFMXO4-010HC-5TSG100I|896|2.5 V / 3.3 V|5|TSG100|100|IND|
|ee|LFMXO4-010HC-6TSG100I|896|2.5 V / 3.3 V|6|TSG100|100|IND|
|ee|LFMXO4-010HC-5BSG132I|896|GG|2.5 V / 3.3 V|5|BSG132|132|IND|
|eG|LFMXO4-010HC-6BSG132I|896|2.5 V / 3.3 V|6|BSG132|132|IND|
|Ge|LFMXO4-010HC-5TSG144I|896|2.5 V / 3.3 V|GO|5|TSG144|144|IND|
|RF|LFMXO4-010HC-6TSG144I|896|2.5 V / 3.3 V|6|TSG144|144|IND|
|Part Number|LUTs|Supply Voltage|Speed|Package|Pins|Temp.|
|pO|
|LFMXO4-015HE-5UUG36I|1280|1.2 V|5|UUG36|36|IND|
|eG|CG|
|LFMXO4-015HE-5UUG36ITR1K|1280|1.2 V|5|UUG36|36|IND|
|GO|
|LFMXO4-015HE-5TSG100I|1280|1.2 V|5|TSG100|100|IND|
|GO|
|LFMXO4-015HE-6TSG100I|1280|1.2 V|6|TSG100|100|IND|
|eeSG|
|LFMXO4-015HE-5BSG132I|1280|1.2 V|5|BSG132|132|IND|
|GG|
|LFMXO4-015HE-6BSG132I|1280|1.2 V|6|BSG132|132|IND|
|eG|GG|
|LFMXO4-015HE-5TSG144I|1280|1.2 V|5|TSG144|144|IND|
|GO|
|LFMXO4-015HE-6TSG144I|1280|1.2 V|6|TSG144|144|IND|
|GO|
|LFMXO4-015HE-5BBG256I|1280|1.2 V|5|BBG256|256|IND|
|eeSG|
|LFMXO4-015HE-6BBG256I|1280|1.2 V|6|BBG256|256|IND|
|GG|
|LFMXO4-015HE-5BFG256I|1280|1.2 V|5|BFG256|256|IND|
|GG|
|LFMXO4-015HE-6BFG256I|1280|1.2 V|6|BFG256|256|IND|
|eG|GG|
|OO|LFMXO4-015HC-5TSG100I|1280|2.5 V / 3.3 V|5|TSG100|100|IND|
|ee|LFMXO4-015HC-6TSG100I|1280|GG|2.5 V / 3.3 V|6|TSG100|100|IND|
|ee|LFMXO4-015HC-5BSG132I|1280|GG|2.5 V / 3.3 V|5|BSG132|132|IND|
|ee|LFMXO4-015HC-6BSG132I|1280|2.5 V / 3.3 V|6|BSG132|132|IND|
|eG|LFMXO4-015HC-5TSG144I|1280|GG|2.5 V / 3.3 V|GC|5|TSG144|144|IND|
|CO|LFMXO4-015HC-6TSG144I|1280|2.5 V / 3.3 V|6|TSG144|144|IND|
|GG|LFMXO4-015HC-5BBG256I|1280|2.5 V / 3.3 V|5|BBG256|256|IND|
|ee|LFMXO4-015HC-6BBG256I|1280|GG|2.5 V / 3.3 V|6|BBG256|256|IND|
|GG|LFMXO4-015HC-5BFG256I|1280|2.5 V / 3.3 V|5|BFG256|256|IND|
|LFMXO4-015HC-6BFG256I|1280|2.5 V / 3.3 V|6|BFG256|256|IND|
|po|

**----- End of picture text -----**<br>


© 2025 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02125-1.0 

85 

**MachXO4 Family Data Sheet** 

|**Part Number**<br>**LUTs**<br>**Supply Voltage **<br>**Speed**<br>**Package **<br>**Pins**<br>**Temp. **<br>~~pO~~|
|---|
|LFMXO4-025HE-5UUG49I<br>2112<br>1.2 V<br>5<br>UUG49<br>49<br>IND<br>~~ee~~<br>~~GO~~|
|LFMXO4-025HE-5UUG49ITR1K<br>2112<br>1.2 V<br>5<br>UUG49<br>49<br>IND<br>~~CO~~|
|LFMXO4-025HE-5TSG100I<br>2112<br>1.2 V<br>5<br>TSG100<br>100<br>IND<br>~~eG~~|
|LFMXO4-025HE-6TSG100I<br>2112<br>1.2 V<br>6<br>TSG100<br>100<br>IND<br>~~GG~~|
|LFMXO4-025HE-5BSG132I<br>2112<br>1.2 V<br>5<br>BSG132<br>132<br>IND<br>~~eeGG~~|
|LFMXO4-025HE-6BSG132I<br>2112<br>1.2 V<br>6<br>BSG132<br>132<br>IND<br>~~eeGG~~|
|LFMXO4-025HE-5TSG144I<br>2112<br>1.2 V<br>5<br>TSG144<br>144<br>IND<br>~~CO~~|
|LFMXO4-025HE-6TSG144I<br>2112<br>1.2 V<br>6<br>TSG144<br>144<br>IND<br>~~eG~~|
|LFMXO4-025HE-5BBG256I<br>2112<br>1.2 V<br>5<br>BBG256<br>256<br>IND<br>~~GG~~|
|LFMXO4-025HE-6BBG256I<br>2112<br>1.2 V<br>6<br>BBG256<br>256<br>IND<br>~~eeGG~~|
|LFMXO4-025HE-5BFG256I<br>2112<br>1.2 V<br>5<br>BFG256<br>256<br>IND<br>~~eeGG~~|
|LFMXO4-025HE-6BFG256I<br>2112<br>1.2 V<br>6<br>BFG256<br>256<br>IND<br>~~GO~~|
|LFMXO4-025HC-5TSG100I<br>2112<br>2.5 V / 3.3 V<br>5<br>TSG100<br>100<br>IND<br>~~OO~~|
|LFMXO4-025HC-6TSG100I<br>2112<br>2.5 V / 3.3 V<br>6<br>TSG100<br>100<br>IND<br>~~eeGG~~|
|LFMXO4-025HC-5BSG132I<br>2112<br>2.5 V / 3.3 V<br>5<br>BSG132<br>132<br>IND<br>~~eG~~|
|LFMXO4-025HC-6BSG132I<br>2112<br>2.5 V / 3.3 V<br>6<br>BSG132<br>132<br>IND<br>~~eG~~|
|LFMXO4-025HC-5TSG144I<br>2112<br>2.5 V / 3.3 V<br>5<br>TSG144<br>144<br>IND<br>~~Ge~~<br>~~GO~~|
|LFMXO4-025HC-6TSG144I<br>2112<br>2.5 V / 3.3 V<br>6<br>TSG144<br>144<br>IND<br>~~ee~~|
|LFMXO4-025HC-5BBG256I<br>2112<br>2.5 V / 3.3 V<br>5<br>BBG256<br>256<br>IND<br>~~ee~~|
|LFMXO4-025HC-6BBG256I<br>2112<br>2.5 V / 3.3 V<br>6<br>BBG256<br>256<br>IND<br>~~eeGG~~|
|LFMXO4-025HC-5BFG256I<br>2112<br>2.5 V / 3.3 V<br>5<br>BFG256<br>256<br>IND<br>~~eG~~|
|LFMXO4-025HC-6BFG256I<br>2112<br>2.5 V / 3.3 V<br>6<br>BFG256<br>256<br>IND<br>~~ef~~<br>~~DO~~|
|**Part Number**<br>**LUTs**<br>**Supply Voltage **<br>**Speed**<br>**Package **<br>**Pins**<br>**Temp. **<br>LFMXO4-050HE-5UUG81I<br>4320<br>1.2 V<br>5<br>UUG81<br>81<br>IND<br>LFMXO4-050HE-5UUG81ITR1K<br>4320<br>1.2 V<br>5<br>UUG81<br>81<br>IND<br>~~pf~~<br>~~ee~~<br>~~SG~~<br>~~eC~~<br>~~GG~~|
|LFMXO4-050HE-5BSG132I<br>4320<br>1.2 V<br>5<br>BSG132<br>132<br>IND<br>~~GO~~|
|LFMXO4-050HE-6BSG132I<br>4320<br>1.2 V<br>6<br>BSG132<br>132<br>IND<br>~~GO~~|
|LFMXO4-050HE-5TSG144I<br>4320<br>1.2 V<br>5<br>TSG144<br>144<br>IND<br>~~eeSG~~|
|LFMXO4-050HE-6TSG144I<br>4320<br>1.2 V<br>6<br>TSG144<br>144<br>IND<br>~~GG~~|
|LFMXO4-050HE-5BBG256I<br>4320<br>1.2 V<br>5<br>BBG256<br>256<br>IND<br>~~eG~~<br>~~GG~~|
|LFMXO4-050HE-6BBG256I<br>4320<br>1.2 V<br>6<br>BBG256<br>256<br>IND<br>~~GO~~|
|LFMXO4-050HE-5BBG400I<br>4320<br>1.2 V<br>5<br>BBG400<br>400<br>IND<br>~~GO~~|
|LFMXO4-050HE-6BBG400I<br>4320<br>1.2 V<br>6<br>BBG400<br>400<br>IND<br>~~eeSG~~|
|LFMXO4-050HE-5BFG256I<br>4320<br>1.2 V<br>5<br>BFG256<br>256<br>IND<br>~~GG~~|
|LFMXO4-050HE-6BFG256I<br>4320<br>1.2 V<br>6<br>BFG256<br>256<br>IND<br>~~eG~~<br>~~GG~~|
|LFMXO4-050HC-5BSG132I<br>4320<br>2.5 V / 3.3 V<br>5<br>BSG132<br>132<br>IND<br>~~GO~~|
|LFMXO4-050HC-6BSG132I<br>4320<br>2.5 V / 3.3 V<br>6<br>BSG132<br>132<br>IND<br>LFMXO4-050HC-5TSG144I<br>4320<br>2.5 V / 3.3 V<br>5<br>TSG144<br>144<br>IND<br>LFMXO4-050HC-6TSG144I<br>4320<br>2.5 V / 3.3 V<br>6<br>TSG144<br>144<br>IND<br>LFMXO4-050HC-5BBG256I<br>4320<br>2.5 V / 3.3 V<br>5<br>BBG256<br>256<br>IND<br>LFMXO4-050HC-6BBG256I<br>4320<br>2.5 V / 3.3 V<br>6<br>BBG256<br>256<br>IND<br>~~OO~~<br>~~ee~~<br>~~GG~~<br>~~ee~~<br>~~GG~~<br>~~ee~~<br>~~GG~~<br>~~eG~~<br>~~GC~~|
|LFMXO4-050HC-5BBG400I<br>4320<br>2.5 V / 3.3 V<br>5<br>BBG400<br>400<br>IND<br>~~CO~~|
|LFMXO4-050HC-6BBG400I<br>4320<br>2.5 V / 3.3 V<br>6<br>BBG400<br>400<br>IND<br>~~GC~~|
|LFMXO4-050HC-5BFG256I<br>4320<br>2.5 V / 3.3 V<br>5<br>BFG256<br>256<br>IND<br>~~GO~~|
|LFMXO4-050HC-6BFG256I<br>4320<br>2.5 V / 3.3 V<br>6<br>BFG256<br>256<br>IND<br>~~FC~~|



© 2025 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. 

All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02125-1.0 

86 

**MachXO4 Family Data Sheet** 

|**Part Number**<br>**LUTs**<br>**Supply Voltage **<br>**Speed**<br>**Package **<br>**Pins**<br>**Temp. **<br>LFMXO4-080HE-5BBG256I<br>6864<br>1.2 V<br>5<br>BBG256<br>256<br>IND<br>LFMXO4-080HE-6BBG256I<br>6864<br>1.2 V<br>6<br>BBG256<br>256<br>IND<br>~~pO~~<br>~~ee~~<br>~~GG~~<br>~~eG~~|
|---|
|LFMXO4-080HE-5BBG400I<br>6864<br>1.2 V<br>5<br>BBG400<br>400<br>IND<br>~~GG~~|
|LFMXO4-080HE-6BBG400I<br>6864<br>1.2 V<br>6<br>BBG400<br>400<br>IND<br>~~eeGG~~|
|LFMXO4-080HC-5BBG256I<br>6864<br>2.5 V / 3.3 V<br>5<br>BBG256<br>256<br>IND<br>~~eeGG~~|
|LFMXO4-080HC-6BBG256I<br>6864<br>2.5 V / 3.3 V<br>6<br>BBG256<br>256<br>IND<br>~~CO~~|
|LFMXO4-080HC-5BBG400I<br>6864<br>2.5 V / 3.3 V<br>5<br>BBG400<br>400<br>IND<br>LFMXO4-080HC-6BBG400I<br>6864<br>2.5 V / 3.3 V<br>6<br>BBG400<br>400<br>IND<br>~~eG~~<br>~~eG~~<br>~~CO~~|
|**Part Number**<br>**LUTs**<br>**Supply Voltage **<br>**Speed**<br>**Package **<br>**Pins**<br>**Temp. **<br>LFMXO4-110HE-5BBG256I<br>9400<br>1.2 V<br>5<br>BBG256<br>256<br>IND<br>LFMXO4-110HE-6BBG256I<br>9400<br>1.2 V<br>6<br>BBG256<br>256<br>IND<br>~~pO~~<br>~~ee~~<br>~~GG~~<br>~~eG~~|
|LFMXO4-110HE-5BBG400I<br>9400<br>1.2 V<br>5<br>BBG400<br>400<br>IND<br>~~eG~~|
|LFMXO4-110HE-6BBG400I<br>9400<br>1.2 V<br>6<br>BBG400<br>400<br>IND<br>~~GG~~|
|LFMXO4-110HE-5BBG484I<br>9400<br>1.2 V<br>5<br>BBG484<br>484<br>IND<br>~~eG~~|
|LFMXO4-110HE-6BBG484I<br>9400<br>1.2 V<br>6<br>BBG484<br>484<br>IND<br>~~Ge~~<br>~~GO~~|
|LFMXO4-110HC-5BBG256I<br>9400<br>2.5 V / 3.3 V<br>5<br>BBG256<br>256<br>IND<br>~~ee~~|
|LFMXO4-110HC-6BBG256I<br>9400<br>2.5 V / 3.3 V<br>6<br>BBG256<br>256<br>IND<br>~~ee~~|
|LFMXO4-110HC-5BBG400I<br>9400<br>2.5 V / 3.3 V<br>5<br>BBG400<br>400<br>IND<br>~~eeGG~~|
|LFMXO4-110HC-6BBG400I<br>9400<br>2.5 V / 3.3 V<br>6<br>BBG400<br>400<br>IND<br>~~eG~~|
|LFMXO4-110HC-5BBG484I<br>9400<br>2.5 V / 3.3 V<br>5<br>BBG484<br>484<br>IND<br>~~eG~~|
|LFMXO4-110HC-6BBG484I<br>9400<br>2.5 V / 3.3 V<br>6<br>BBG484<br>484<br>IND<br>~~ef~~<br>~~DO~~|



## **6.3. MachXO4 High Performance Automotive Grade Devices, Packaging** 

|**Part Number**<br>**LUTs**<br>**Supply Voltage **<br>**Speed**<br>**Package **<br>**Pins**<br>**Temp. **|
|---|
|LFMXO4-010HE-5TSG100A<br>896<br>1.2 V<br>5<br>TSG100<br>100<br>AUTO|
|LFMXO4-010HE-5BSG132A<br>896<br>1.2 V<br>5<br>BSG132<br>132<br>AUTO|
|LFMXO4-010HC-5TSG100A<br>896<br>2.5 V/3.3 V<br>5<br>TSG100<br>100<br>AUTO|
|LFMXO4-010HC-5BSG132A<br>896<br>2.5 V/3.3 V<br>5<br>BSG132<br>132<br>AUTO|
||
|**Part Number**<br>**LUTs**<br>**Supply Voltage **<br>**Speed**<br>**Package **<br>**Pins**<br>**Temp. **<br>LFMXO4-015HE-5TSG100A<br>1280<br>1.2 V<br>5<br>TSG100<br>100<br>AUTO<br>LFMXO4-015HE-5BSG132A<br>1280<br>1.2 V<br>5<br>BSG132<br>132<br>AUTO<br>~~pO~~<br>~~ee~~<br>~~**G**O~~<br>~~eG~~<br>~~G~~|
|LFMXO4-015HE-5BBG256A<br>1280<br>1.2 V<br>5<br>BBG256<br>256<br>AUTO<br>~~GO~~|
|LFMXO4-015HC-5TSG100A<br>1280<br>2.5 V/3.3 V<br>5<br>TSG100<br>100<br>AUTO<br>~~eeSG~~|
|LFMXO4-015HC-5BSG132A<br>1280<br>2.5 V/3.3 V<br>5<br>BSG132<br>132<br>AUTO<br>LFMXO4-015HC-5BBG256A<br>1280<br>2.5 V/3.3 V<br>5<br>BBG256<br>256<br>AUTO<br>~~GG~~<br>~~pO~~|
|**Part Number**<br>**LUTs**<br>**Supply Voltage **<br>**Speed**<br>**Package **<br>**Pins**<br>**Temp. **<br>LFMXO4-025HE-5TSG100A<br>2112<br>1.2 V<br>5<br>TSG100<br>100<br>AUTO<br>LFMXO4-025HE-5BSG132A<br>2112<br>1.2 V<br>5<br>BSG132<br>132<br>AUTO<br>LFMXO4-025HE-5BBG256A<br>2112<br>1.2 V<br>5<br>BBG256<br>256<br>AUTO<br>LFMXO4-025HC-5TSG100A<br>2112<br>2.5 V/3.3 V<br>5<br>TSG100<br>100<br>AUTO<br>~~a~~<br>~~(~~<br>~~ee~~<br>~~GG~~<br>~~ee~~<br>~~GG~~<br>~~ee~~<br>~~GG~~<br>~~eG~~<br>~~GC~~|
|LFMXO4-025HC-5BSG132A<br>2112<br>2.5 V/3.3 V<br>5<br>BSG132<br>132<br>AUTO<br>~~CO~~|
|LFMXO4-025HC-5BBG256A<br>2112<br>2.5 V/3.3 V<br>5<br>BBG256<br>256<br>AUTO<br>~~RC~~|



© 2025 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02125-1.0 

87 

**MachXO4 Family Data Sheet** 

|**Part Number**|**LUTs**|**Supply Voltage **|**Speed**|**Package **|**Pins**|**Temp. **|
|---|---|---|---|---|---|---|
|LFMXO4-050HE-5BSG132A|4320|1.2 V|5|BSG132|132|AUTO|
|LFMXO4-050HE-5BBG256A|4320|1.2 V|5|BBG256|256|AUTO|
|LFMXO4-050HC-5BSG132A|4320|2.5 V/3.3 V|5|BSG132|132|AUTO|
|LFMXO4-050HC-5BBG256A|4320|2.5 V/3.3 V|5|BBG256|256|AUTO|



© 2025 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02125-1.0 

88 

**MachXO4 Family Data Sheet** 

## **References** 

- MachXO4 sysCLOCK PLL Design User Guide (FPGA-TN-02391) 

- MachXO4 Implementing High-Speed I/O Interface User Guide (FPGA-TN-02410) 

- MachXO4 sysI/O User Guide (FPGA-TN-02398) 

- MachXO4 Programming and Configuration User Guide (FPGA-TN-02393) 

- MachXO4 Hardened Control Functions User Guide (FPGA-TN-02403) 

- MachXO4 Soft Error Detection (SED)/Correction (SEC) User Guide (FPGA-TN-02406) 

- Using Password Security with MachXO4 Devices (FPGA-TN-02408) 

- Power and Thermal Estimation and Management for MachXO4 Devices (FPGA-TN-02409) 

- PCB Layout Recommendations for BGA Packages (FPGA-TN-02024) 

- Minimizing System Interruption During Configuration Using TransFR Technology (FPGA-TN-02198) 

- • Boundary Scan Testability with Lattice sysI/O Capability (AN8066) 

- MachXO4 Device Pinout Files 

- Thermal Management (FPGA-TN-02044) 

- Lattice Design Tools 

- MachXO4 Family Web Page 

- Boards, Demos, IP Cores and Reference Designs for MachXO4 Family Devices 

- Lattice Insights for Training Series and Learning Plans 

© 2025 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02125-1.0 

89 

**MachXO4 Family Data Sheet** 

## **Technical Support Assistance** 

- Submit a technical support case through www.latticesemi.com/techsupport. 

- For frequently asked questions, please refer to the Lattice Answer Database at www.latticesemi.com/Support/AnswerDatabase. 

© 2025 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02125-1.0 

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**MachXO4 Family Data Sheet** 

## **Revision History** 

## **Revision 1.0, December 2025** 

|**Section**|**Change Summary**|
|---|---|
|All|•<br>Performed minor grammatical and typographical edits.<br>•<br>Provided URL to all the references in this document.<br>•<br>Removed NVCM globally.<br>•<br>Made the following global changes:<br>•<br>from MachXO4-010 to LFMXO4-010;<br>•<br>from MachXO4-015 to LFMXO4-015;<br>•<br>from MachXO4-020 to LFMXO4-020;<br>•<br>from MachXO4-050 to LFMXO4-050;<br>•<br>from MachXO4-080 to LFMXO4-080;<br>•<br>from MachXO4-110 to LFMXO4-110.|
|Introduction|•<br>Updated to_The MachXO4 family consists of low-power, instant-on, non-volatile, and_<br>_Flash-based FPGAs with six devices_in the description.<br>•<br>Removed –1 speed grade from the description.<br>•<br>Updated to_milliseconds_inNon-volatile, Multi-time Reconfigurableof theFeatures<br>section.<br>•<br>Newly addedTable 1.1. Specification Status for MachXO4 Family Devices.<br>•<br>Table 1.2. MachXO4 Family Selection Guide:<br>•<br>added note superscripts for LUTs for LFMXO4-080 and LFMXO4-110 parts;<br>•<br>removed note superscripts from 256-ball caBGA  (14 mm x 14 mm, 0.8 mm) of<br>LFMXO4-080 and LFMXO4-110;<br>•<br>changed Device Options HC for LFMXO4-110 part to_No_;<br>•<br>updated Note 3 to the current;<br>•<br>updated Note 6 addingHC and HE variants.|
|Architecture|•<br>UpdatedFigure 2.1. Top View of the LFMXO4-015 andtoFigure 2.2. Top View of the<br>LFMXO4-050 Partthe current.<br>•<br>Removed the mentioningof MachXO4 migration files from theDensityShiftingsection.|
|DC and Switching Characteristics|•<br>UpdatedTable 3.5. Hot Socketing Specificationsto the current.<br>•<br>Table 3.10. sysI/O Recommended Operating Conditions:<br>removed the original Note 4.<br>•<br>Table 3.11. sysI/O Single-Ended DC Electrical Charateristics1, 2, 4:<br>For LVCMO2.5 symbol:<br>•<br>removed 16 from IOL Max (mA);<br>•<br>removed  –16 from IOH Max(mA).|
|Signal Description|Updated all the package information to the current inTable 4.2. LFMXO4-010 and LFMXO4-<br>015 Pin Summary, Table 4.3. LFMXO4-025 Pin Summary, Table 4.4. LFMXO4-050 Pin<br>Summary, Table 4.5. LFMXO4-080 Pin Summary,andTable 4.6. LFMXO4-110 Pin Summary.|
|MachXO4 Part Number<br>Description|Updated the part number description to the current.|
|Ordering Information|•<br>Updated the three marking diagrams to the current.<br>•<br>Newly added LFMXO4-015HE-5UUG36CTR1K, LFMXO4-025HE-5UUG49CTR1K, and<br>LFMXO4-050HE-5UUG81CTR1K parts and their related information to theMachXO4<br>High Performance Commercial Grade Devices, Packagingsection.<br>•<br>Newly added  LFMXO4-015HE-5UUG36ITR1K, LFMXO4-050HE-5UUG81ITR1K,<br>LFMXO4-050HE-5UUG81ITR1K parts and their related information to theMachXO4<br>High Performance Industrial Grade Devices,Packagingsection.|
|References|Updated the document title of_MachXO4 Implementing High-Speed I/O Interface User Guide_<br>_(FPGA-TN-02410)_to the current.|



© 2025 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02125-1.0 

91 

**MachXO4 Family Data Sheet** 

## **Revision 0.80, June 2025** 

|**Section**|**Change Summary**|
|---|---|
|All|Initial Preliminaryrelease.|
|Introduction|Table 1.2. MachXO4 Family Selection Guide:<br>Updated MIPI D-PHY Support for LFMXO4-080 and LFMXO4-110parts to_No_.|
|DC and Switching Characteristics|Table 3.18. Comparator Specifications1:<br>Updated the Unit to V for VIH parameter.|
|MachXO4 Part Number<br>Description|Updated the Slowest and the Highest Speed for High Performance parts.|
|Ordering Information|•<br>MachXO4 Low Power Commercial Grade Devices, Packaging section:<br>Adjusted LUTs for the following parts:<br>LFMXO4-080ZC-1BBG256C<br>LFMXO4-080ZC-2BBG256C<br>LFMXO4-080ZC-3BBG256C<br>LFMXO4-080ZC-1BBG400C<br>LFMXO4-080ZC-2BBG400C<br>LFMXO4-080ZC-3BBG400C<br>•<br>MachXO4 High Performance Industrial Grade Devices, Packaging section:<br>Adjusted LUTs for the following parts:<br>LFMXO4-025HE-5UUG49I<br>LFMXO4-025HE-5TSG100I<br>LFMXO4-025HE-6TSG100I<br>LFMXO4-025HE-5BSG132I<br>LFMXO4-025HE-6BSG132I<br>LFMXO4-025HE-5TSG144I<br>LFMXO4-025HE-6TSG144I<br>LFMXO4-025HE-5BBG256I<br>LFMXO4-025HE-6BBG256I<br>LFMXO4-025HE-5BFG256I<br>LFMXO4-025HE-6BFG256I<br>LFMXO4-025HC-5TSG100I<br>LFMXO4-025HC-6TSG100I<br>LFMXO4-025HC-5BSG132I<br>LFMXO4-025HC-6BSG132I<br>LFMXO4-025HC-5TSG144I<br>LFMXO4-025HC-6TSG144I<br>LFMXO4-025HC-5BBG256I<br>LFMXO4-025HC-6BBG256I<br>LFMXO4-025HC-5BFG256I<br>LFMXO4-025HC-6BFG256I|



## **Revision 0.70, March 2025** 

|**Section**|**Change Summary**|
|---|---|
|All|Initial Advance  release.|



© 2025 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02125-1.0 

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