LFE5U-45F-7BG256I

FPGA, ECP5, PLL, 197 I/O's, 44000 Cell, 1.045 V to 1.155 V in, CABGA-256

⚠️ Reference pricing provided. In case of supply shortages, we will connect you with our trusted procurement partners to ensure your project's continuity.
Manufacturer: LATTICE SEMICONDUCTOR
Product type: FPGAs
MSL: MSL 3 - 168 hours
SVHC: No SVHC (25-Jun-2025)
FPGA Type: SRAM based FPGA
FPGA Family: ECP5
IC Mounting: Surface Mount
No. of Pins: 256Pins
Speed Grade: 7
No. of I/O's: 197I/O's
Product Range: -
Qualification: -
Total RAM Bits: 351Kbit
No.of User I/Os: 197I/O's
Clock Management: PLL
Logic Case Style: CABGA
IC Case / Package: CABGA
No. of Macrocells: 44000Macrocells
I/O Supply Voltage: 3.465V
No. of Logic Cells: 44000Logic Cells
Process Technology: 40nm
No. of Logic Blocks: 44000
No. of Speed Grades: 7
Core Supply Voltage Max: 1.155V
Core Supply Voltage Min: 1.045V
Operating Frequency Max: 350MHz
Operating Temperature Max: 100°C
Operating Temperature Min: -40°C
Delivery and price
Units per pack	50
Price	24.98 €
Current stock	100+
Lead time	30 days
Datasheet
## Os 

## **ECP5 and ECP5-5G Family** 

## **Data Sheet** 

FPGA-DS-02012-2.2 

October 2020 

**ECP5 and ECP5-5G Family Data Sheet** 

## **Disclaimers** 

Lattice makes no warranty, representation, or guarantee regarding the accuracy of information contained in this document or the suitability of its products for any particular purpose. All information herein is provided AS IS and with all faults, and all risk associated with such information is entirely with Buyer. Buyer shall not rely on any data and performance specifications or parameters provided herein. Products sold by Lattice have been subject to limited testing and it is the Buyer's responsibility to independently determine the suitability of any products and to test and verify the same. No Lattice products should be used in conjunction with mission- or safety-critical or any other application in which the failure of Lattice’s product could create a situation where personal injury, death, severe property or environmental damage may occur. The information provided in this document is proprietary to Lattice Semiconductor, and Lattice reserves the right to make any changes to the information in this document or to any products at any time without notice. 

© 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

2 

FPGA-DS-02012-2.2 

**ECP5 and ECP5-5G Family Data Sheet** 

## **Contents** 

|**Contents**|**Contents**|
|---|---|
|Acronyms in This Document ................................................................................................................................................. 9||
|1.|General Description .................................................................................................................................................... 10|
||1.1.<br>Features ............................................................................................................................................................ 10|
|2.|Architecture ................................................................................................................................................................ 12|
||2.1.<br>Overview ........................................................................................................................................................... 12|
||2.2.<br>PFU Blocks ......................................................................................................................................................... 13|
||2.2.1.<br>Slice ............................................................................................................................................................... 14|
||2.2.2.<br>Modes of Operation ...................................................................................................................................... 17|
||2.3.<br>Routing .............................................................................................................................................................. 18|
||2.4.<br>Clocking Structure ............................................................................................................................................. 18|
||2.4.1.<br>sysCLOCK PLL ................................................................................................................................................ 18|
||2.5.<br>Clock Distribution Network ............................................................................................................................... 20|
||2.5.1.<br>Primary Clocks .............................................................................................................................................. 20|
||2.5.2.<br>Edge Clock ..................................................................................................................................................... 21|
||2.6.<br>Clock Dividers .................................................................................................................................................... 22|
||2.7.<br>DDRDLL .............................................................................................................................................................. 23|
||2.8.<br>sysMEM Memory .............................................................................................................................................. 24|
||2.8.1.<br>sysMEM Memory Block ................................................................................................................................ 24|
||2.8.2.<br>Bus Size Matching ......................................................................................................................................... 25|
||2.8.3.<br>RAM Initialization and ROM Operation ........................................................................................................ 25|
||2.8.4.<br>Memory Cascading ....................................................................................................................................... 25|
||2.8.5.<br>Single, Dual and Pseudo-Dual Port Modes ................................................................................................... 25|
||2.8.6.<br>Memory Core Reset ...................................................................................................................................... 26|
||2.9.<br>sysDSP™ Slice .................................................................................................................................................... 26|
||2.9.1.<br>sysDSP Slice Approach Compared to General DSP ....................................................................................... 26|
||2.9.2.<br>sysDSP Slice Architecture Features ............................................................................................................... 27|
||2.10.<br>Programmable I/O Cells .................................................................................................................................... 31|
||2.11.<br>PIO..................................................................................................................................................................... 33|
||2.11.1. Input Register Block ...................................................................................................................................... 33|
||2.11.2. Output Register Block ................................................................................................................................... 34|
||2.12.<br>Tristate Register Block ....................................................................................................................................... 35|
||2.13.<br>DDR Memory Support ....................................................................................................................................... 36|
||2.13.1. DQS Grouping for DDR Memory ................................................................................................................... 36|
||2.13.2. DLL Calibrated DQS Delay and Control Block (DQSBUF) ............................................................................... 37|
||2.14.<br>sysI/O Buffer...................................................................................................................................................... 39|
||2.14.1. sysI/O Buffer Banks ....................................................................................................................................... 39|
||2.14.2. Typical sysI/O I/O Behavior during Power-up ............................................................................................... 40|
||2.14.3. Supported sysI/O Standards ......................................................................................................................... 40|
||2.14.4. On-Chip Programmable Termination ............................................................................................................ 41|
||2.14.5. Hot Socketing ................................................................................................................................................ 42|
||2.15.<br>SERDES and Physical Coding Sublayer ............................................................................................................... 42|
||2.15.1. SERDES Block ................................................................................................................................................ 44|
||2.15.2. PCS ................................................................................................................................................................ 44|
||2.15.3. SERDES Client Interface Bus .......................................................................................................................... 45|
||2.16.<br>Flexible Dual SERDES Architecture .................................................................................................................... 45|
||2.17.<br>IEEE 1149.1-Compliant Boundary Scan Testability............................................................................................ 45|
||2.18.<br>Device Configuration ......................................................................................................................................... 46|
||2.18.1. Enhanced Configuration Options .................................................................................................................. 46|
||2.18.2. Single Event Upset (SEU) Support ................................................................................................................. 46|
||2.18.3. On-Chip Oscillator ......................................................................................................................................... 47|
||2.19.<br>Density Shifting ................................................................................................................................................. 47|
|3.|DC and Switching Characteristics ............................................................................................................................... 48|



© 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02012-2.2 

3 

**ECP5 and ECP5-5G Family Data Sheet** 

||3.1.|Absolute Maximum Ratings .............................................................................................................................. 48|
|---|---|---|
||3.2.|Recommended Operating Conditions ............................................................................................................... 48|
||3.3.|Power Supply Ramp Rates ................................................................................................................................. 49|
||3.4.|Power-On-Reset Voltage Levels ........................................................................................................................ 49|
||3.5.|Power up Sequence ........................................................................................................................................... 49|
||3.6.|Hot Socketing Specifications ............................................................................................................................. 49|
||3.7.|Hot Socketing Requirements ............................................................................................................................. 50|
||3.8.|ESD Performance ............................................................................................................................................... 50|
||3.9.|DC Electrical Characteristics .............................................................................................................................. 50|
||3.10.|Supply Current (Static) ...................................................................................................................................... 51|
||3.11.|SERDES Power Supply Requirements1, 2, 3.......................................................................................................... 52|
||3.12.|sysI/O Recommended Operating Conditions .................................................................................................... 54|
||3.13.|sysI/O Single-Ended DC Electrical Characteristics ............................................................................................. 55|
||3.14.|sysI/O Differential Electrical Characteristics ..................................................................................................... 56|
||3.14.1. LVDS .............................................................................................................................................................. 56||
||3.14.2. SSTLD ............................................................................................................................................................. 56||
||3.14.3. LVCMOS33D .................................................................................................................................................. 56||
||3.14.4. LVDS25E ........................................................................................................................................................ 57||
||3.14.5. BLVDS25 ........................................................................................................................................................ 58||
||3.14.6. LVPECL33 ....................................................................................................................................................... 59||
||3.14.7. MLVDS25 ....................................................................................................................................................... 60||
||3.14.8. SLVS ............................................................................................................................................................... 61||
||3.15.|Typical Building Block Function Performance ................................................................................................... 62|
||3.16.|Derating Timing Tables ...................................................................................................................................... 63|
||3.17.|Maximum I/O Buffer Speed .............................................................................................................................. 64|
||3.18.|External Switching Characteristics .................................................................................................................... 65|
||3.19.|sysCLOCK PLL Timing ......................................................................................................................................... 72|
||3.20.|SERDES High-Speed Data Transmitter ............................................................................................................... 73|
||3.21.|SERDES/PCS Block Latency ................................................................................................................................ 74|
||3.22.|SERDES High-Speed Data Receiver .................................................................................................................... 75|
||3.23.|Input Data Jitter Tolerance ................................................................................................................................ 75|
||3.24.|SERDES External Reference Clock ...................................................................................................................... 76|
||3.25.|PCI Express Electrical and Timing Characteristics .............................................................................................. 77|
||3.25.1. PCIe (2.5 Gb/s) AC and DC Characteristics .................................................................................................... 77||
||3.25.2. PCIe (5 Gb/s) – Preliminary AC and DC Characteristics ................................................................................. 78||
||3.26.|CPRI LV2 E.48 Electrical and Timing Characteristics – Preliminary .................................................................... 80|
||3.27.|XAUI/CPRI LV E.30 Electrical and Timing Characteristics .................................................................................. 81|
||3.27.1. AC and DC Characteristics ............................................................................................................................. 81||
||3.28.|CPRI LV E.24/SGMII (2.5 Gbps) Electrical and Timing Characteristics ............................................................... 81|
||3.28.1. AC and DC Characteristics ............................................................................................................................. 81||
||3.29.|Gigabit Ethernet/SGMII (1.25 Gbps)/CPRI LV E.12 Electrical and Timing Characteristics ................................. 82|
||3.29.1. AC and DC Characteristics ............................................................................................................................. 82||
||3.30.|SMPTE SD/HD-SDI/3G-SDI (Serial Digital Interface) Electrical and Timing Characteristics ............................... 83|
||3.30.1. AC and DC Characteristics ............................................................................................................................. 83||
||3.31.|sysCONFIG Port Timing Specifications ............................................................................................................... 84|
||3.32.|JTAG Port Timing Specifications ........................................................................................................................ 89|
||3.33.|Switching Test Conditions ................................................................................................................................. 90|
|4.|Pinout Information ..................................................................................................................................................... 92||
||4.1.|Signal Descriptions ............................................................................................................................................ 92|
||4.2.|PICs and DDR Data (DQ) Pins Associated with the DDR Strobe (DQS) Pin ........................................................ 95|
||4.3.|Pin Information Summary ................................................................................................................................. 95|
||4.3.1.|LFE5UM/LFE5UM5G ..................................................................................................................................... 95|
||4.3.2.|LFE5U ............................................................................................................................................................ 97|
|5.|Ordering Information .................................................................................................................................................. 99||



© 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02012-2.2 

4 

**ECP5 and ECP5-5G Family Data Sheet** 

|5.1.<br>ECP5/ECP5-5G Part Number Description .......................................................................................................... 99|
|---|
|5.2.<br>Ordering Part Numbers ................................................................................................................................... 100|
|5.2.1.<br>Commercial ................................................................................................................................................. 100|
|5.2.2.<br>Industrial ..................................................................................................................................................... 102|
|Supplemental Information ............................................................................................................................................... 105|
|For Further Information ................................................................................................................................................ 105|
|Revision History ................................................................................................................................................................ 106|



© 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02012-2.2 

5 

**ECP5 and ECP5-5G Family Data Sheet** 

## **Figures** 

|Figure 2.1. Simplified Block Diagram, LFE5UM/LFE5UM5G-85 Device (Top Level) ............................................................ 13|Figure 2.1. Simplified Block Diagram, LFE5UM/LFE5UM5G-85 Device (Top Level) ............................................................ 13|
|---|---|
|Figure 2.2. PFU Diagram ..................................................................................................................................................... 14|Figure 2.2. PFU Diagram ..................................................................................................................................................... 14|
|Figure 2.3. Slice Diagram .................................................................................................................................................... 15|Figure 2.3. Slice Diagram .................................................................................................................................................... 15|
|Figure 2.4. Connectivity Supporting LUT5, LUT6, LUT7, and LUT8 ..................................................................................... 16|Figure 2.4. Connectivity Supporting LUT5, LUT6, LUT7, and LUT8 ..................................................................................... 16|
|Figure 2.5. General Purpose PLL Diagram ........................................................................................................................... 19|Figure 2.5. General Purpose PLL Diagram ........................................................................................................................... 19|
|Figure 2.6. LFE5UM/LFE5UM5G-85 Clocking ...................................................................................................................... 20|Figure 2.6. LFE5UM/LFE5UM5G-85 Clocking ...................................................................................................................... 20|
|Figure 2.7. DCS Waveforms ................................................................................................................................................ 21|Figure 2.7. DCS Waveforms ................................................................................................................................................ 21|
|Figure 2.8. Edge Clock Sources per Bank ............................................................................................................................ 22|Figure 2.8. Edge Clock Sources per Bank ............................................................................................................................ 22|
|Figure 2.9. ECP5/ECP5-5G Clock Divider Sources ............................................................................................................... 22|Figure 2.9. ECP5/ECP5-5G Clock Divider Sources ............................................................................................................... 22|
|Figure 2.10. DDRDLL Functional Diagram ........................................................................................................................... 23|Figure 2.10. DDRDLL Functional Diagram ........................................................................................................................... 23|
|Figure 2.11. ECP5/ECP5-5G DLL Top Level View (For LFE-45 and LFE-85) .......................................................................... 24|Figure 2.11. ECP5/ECP5-5G DLL Top Level View (For LFE-45 and LFE-85) .......................................................................... 24|
|Figure 2.12. Memory Core Reset ........................................................................................................................................ 26|Figure 2.12. Memory Core Reset ........................................................................................................................................ 26|
|Figure 2.13. Comparison of General DSP and ECP5/ECP5-5G Approaches ........................................................................ 27|Figure 2.13. Comparison of General DSP and ECP5/ECP5-5G Approaches ........................................................................ 27|
|Figure 2.14. Simplified sysDSP Slice Block Diagram ............................................................................................................ 29|Figure 2.14. Simplified sysDSP Slice Block Diagram ............................................................................................................ 29|
|Figure 2.15. Detailed sysDSP Slice Diagram ........................................................................................................................ 30|Figure 2.15. Detailed sysDSP Slice Diagram ........................................................................................................................ 30|
|Figure 2.16. Group of Four Programmable I/O Cells on Left/Right Sides ........................................................................... 32|Figure 2.16. Group of Four Programmable I/O Cells on Left/Right Sides ........................................................................... 32|
|Figure 2.17. Input Register Block for PIO on Top Side of the Device .................................................................................. 33|Figure 2.17. Input Register Block for PIO on Top Side of the Device .................................................................................. 33|
|Figure 2.18. Input Register Block for PIO on Left and Right Side of the Device .................................................................. 33|Figure 2.18. Input Register Block for PIO on Left and Right Side of the Device .................................................................. 33|
|Figure 2.19. Output Register Block on Top Side ................................................................................................................. 34|Figure 2.19. Output Register Block on Top Side ................................................................................................................. 34|
|Figure 2.20. Output Register Block on Left and Right Sides ............................................................................................... 35|Figure 2.20. Output Register Block on Left and Right Sides ............................................................................................... 35|
|Figure 2.21. Tristate Register Block on Top Side ................................................................................................................. 35|Figure 2.21. Tristate Register Block on Top Side ................................................................................................................. 35|
|Figure 2.22. Tristate Register Block on Left and Right Sides ............................................................................................... 36|Figure 2.22. Tristate Register Block on Left and Right Sides ............................................................................................... 36|
|Figure 2.23. DQS Grouping on the Left and Right Edges .................................................................................................... 37|Figure 2.23. DQS Grouping on the Left and Right Edges .................................................................................................... 37|
|Figure 2.24. DQS Control and Delay Block (DQSBUF) ......................................................................................................... 38|Figure 2.24. DQS Control and Delay Block (DQSBUF) ......................................................................................................... 38|
|Figure 2.25. ECP5/ECP5-5G Device Family Banks ............................................................................................................... 39|Figure 2.25. ECP5/ECP5-5G Device Family Banks ............................................................................................................... 39|
|Figure 2.26. On-Chip Termination ...................................................................................................................................... 41|Figure 2.26. On-Chip Termination ...................................................................................................................................... 41|
|Figure 2.27. SERDES/PCS Duals (LFE5UM/LFE5UM5G-85) ................................................................................................. 43|Figure 2.27. SERDES/PCS Duals (LFE5UM/LFE5UM5G-85) ................................................................................................. 43|
|Figure 2.28. Simplified Channel Block Diagram for SERDES/PCS Block .............................................................................. 44|Figure 2.28. Simplified Channel Block Diagram for SERDES/PCS Block .............................................................................. 44|
|Figure 3.1. LVDS25E Output Termination Example ............................................................................................................ 57|Figure 3.1. LVDS25E Output Termination Example ............................................................................................................ 57|
|Figure 3.2. BLVDS25 Multi-point Output Example .............................................................................................................. 58|Figure 3.2. BLVDS25 Multi-point Output Example .............................................................................................................. 58|
|Figure 3.3. Differential LVPECL33 ....................................................................................................................................... 59|Figure 3.3. Differential LVPECL33 ....................................................................................................................................... 59|
|Figure 3.4. MLVDS25 (Multipoint Low Voltage Differential Signaling) ............................................................................... 60|Figure 3.4. MLVDS25 (Multipoint Low Voltage Differential Signaling) ............................................................................... 60|
|Figure 3.5. SLVS Interface ................................................................................................................................................... 61|Figure 3.5. SLVS Interface ................................................................................................................................................... 61|
|Figure 3.6. Receiver RX.CLK.Centered Waveforms ............................................................................................................. 69|Figure 3.6. Receiver RX.CLK.Centered Waveforms ............................................................................................................. 69|
|Figure 3.7. Receiver RX.CLK.Aligned and DDR Memory Input Waveforms ......................................................................... 69|Figure 3.7. Receiver RX.CLK.Aligned and DDR Memory Input Waveforms ......................................................................... 69|
|Figure 3.8. Transmit TX.CLK.Centered and DDR Memory Output Waveforms ................................................................... 69|Figure 3.8. Transmit TX.CLK.Centered and DDR Memory Output Waveforms ................................................................... 69|
|Figure 3.9. Transmit TX.CLK.Aligned Waveforms ................................................................................................................ 70|Figure 3.9. Transmit TX.CLK.Aligned Waveforms ................................................................................................................ 70|
|Figure 3.10. DDRX71 Video Timing Waveforms .................................................................................................................. 70|Figure 3.10. DDRX71 Video Timing Waveforms .................................................................................................................. 70|
|Figure 3.11. Receiver DDRX71_RX Waveforms ................................................................................................................... 71|Figure 3.11. Receiver DDRX71_RX Waveforms ................................................................................................................... 71|
|Figure 3.12. Transmitter DDRX71_TX Waveforms .............................................................................................................. 71|Figure 3.12. Transmitter DDRX71_TX Waveforms .............................................................................................................. 71|
|Figure 3.13. Transmitter and Receiver Latency Block Diagram .......................................................................................... 74|Figure 3.13. Transmitter and Receiver Latency Block Diagram .......................................................................................... 74|
|Figure 3.14. SERDES External Reference Clock Waveforms ................................................................................................ 76|Figure 3.14. SERDES External Reference Clock Waveforms ................................................................................................ 76|
|Figure 3.15. sysCONFIG Parallel Port Read Cycle ................................................................................................................ 85|Figure 3.15. sysCONFIG Parallel Port Read Cycle ................................................................................................................ 85|
|Figure 3.16. sysCONFIG Parallel Port Write Cycle ............................................................................................................... 86|Figure 3.16. sysCONFIG Parallel Port Write Cycle ............................................................................................................... 86|
|Figure 3.17. sysCONFIG Slave Serial Port Timing ................................................................................................................ 86|Figure 3.17. sysCONFIG Slave Serial Port Timing ................................................................................................................ 86|
|Figure 3.18. Power-On-Reset (POR) Timing ........................................................................................................................ 87|Figure 3.18. Power-On-Reset (POR) Timing ........................................................................................................................ 87|
|Figure 3.19. sysCONFIG Port Timing ................................................................................................................................... 87|Figure 3.19. sysCONFIG Port Timing ................................................................................................................................... 87|
|Figure 3.20. Configuration from PROGRAMN Timing ......................................................................................................... 88|Figure 3.20. Configuration from PROGRAMN Timing ......................................................................................................... 88|
|Figure 3.21. Wake-Up Timing ............................................................................................................................................. 88|Figure 3.21. Wake-Up Timing ............................................................................................................................................. 88|
|Figure 3.22. Master SPI Configuration Waveforms ............................................................................................................ 89|Figure 3.22. Master SPI Configuration Waveforms ............................................................................................................ 89|
|Figure 3.23. JTAG Port Timing Waveforms ......................................................................................................................... 90|Figure 3.23. JTAG Port Timing Waveforms ......................................................................................................................... 90|
|Figure 3.24. Output Test Load, LVTTL and LVCMOS Standards .......................................................................................... 90|Figure 3.24. Output Test Load, LVTTL and LVCMOS Standards .......................................................................................... 90|



© 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02012-2.2 

6 

**ECP5 and ECP5-5G Family Data Sheet** 

## **Tables** 

|Table 1.1. ECP5 and ECP5-5G Family Selection Guide ........................................................................................................ 11|Table 1.1. ECP5 and ECP5-5G Family Selection Guide ........................................................................................................ 11|
|---|---|
|Table 2.1. Resources and Modes Available per Slice .......................................................................................................... 14|Table 2.1. Resources and Modes Available per Slice .......................................................................................................... 14|
|Table 2.2. Slice Signal Descriptions ..................................................................................................................................... 16|Table 2.2. Slice Signal Descriptions ..................................................................................................................................... 16|
|Table 2.3. Number of Slices Required to Implement Distributed RAM .............................................................................. 17|Table 2.3. Number of Slices Required to Implement Distributed RAM .............................................................................. 17|
|Table 2.4. PLL Blocks Signal Descriptions ............................................................................................................................ 19|Table 2.4. PLL Blocks Signal Descriptions ............................................................................................................................ 19|
|Table 2.5. DDRDLL Ports List ............................................................................................................................................... 23|Table 2.5. DDRDLL Ports List ............................................................................................................................................... 23|
|Table 2.6. sysMEM Block Configurations ............................................................................................................................ 25|Table 2.6. sysMEM Block Configurations ............................................................................................................................ 25|
|Table 2.7. Maximum Number of Elements in a Slice .......................................................................................................... 31|Table 2.7. Maximum Number of Elements in a Slice .......................................................................................................... 31|
|Table 2.8. Input Block Port Description .............................................................................................................................. 34|Table 2.8. Input Block Port Description .............................................................................................................................. 34|
|Table 2.9. Output Block Port Description ........................................................................................................................... 35|Table 2.9. Output Block Port Description ........................................................................................................................... 35|
|Table 2.10. Tristate Block Port Description ........................................................................................................................ 36|Table 2.10. Tristate Block Port Description ........................................................................................................................ 36|
|Table 2.11. DQSBUF Port List Description .......................................................................................................................... 38|Table 2.11. DQSBUF Port List Description .......................................................................................................................... 38|
|Table 2.12. On-Chip Termination Options for Input Modes ............................................................................................... 41|Table 2.12. On-Chip Termination Options for Input Modes ............................................................................................... 41|
|Table 2.13. LFE5UM/LFE5UM5G SERDES Standard Support .............................................................................................. 43|Table 2.13. LFE5UM/LFE5UM5G SERDES Standard Support .............................................................................................. 43|
|Table 2.14. Available SERDES Duals per LFE5UM/LFE5UM5G Devices ............................................................................... 44|Table 2.14. Available SERDES Duals per LFE5UM/LFE5UM5G Devices ............................................................................... 44|
|Table 2.15. LFE5UM/LFE5UM5G Mixed Protocol Support ................................................................................................. 45|Table 2.15. LFE5UM/LFE5UM5G Mixed Protocol Support ................................................................................................. 45|
|Table 2.16. Selectable Master Clock (MCLK) Frequencies during Configuration (Nominal) ............................................... 47|Table 2.16. Selectable Master Clock (MCLK) Frequencies during Configuration (Nominal) ............................................... 47|
|Table 3.1. Absolute Maximum Ratings ............................................................................................................................... 48|Table 3.1. Absolute Maximum Ratings ............................................................................................................................... 48|
|Table 3.2. Recommended Operating Conditions ................................................................................................................ 48|Table 3.2. Recommended Operating Conditions ................................................................................................................ 48|
|Table 3.3. Power Supply Ramp Rates ................................................................................................................................. 49|Table 3.3. Power Supply Ramp Rates ................................................................................................................................. 49|
|Table 3.4. Power-On-Reset Voltage Levels ......................................................................................................................... 49|Table 3.4. Power-On-Reset Voltage Levels ......................................................................................................................... 49|
|Table 3.5. Hot Socketing Specifications .............................................................................................................................. 49|Table 3.5. Hot Socketing Specifications .............................................................................................................................. 49|
|Table 3.6. Hot Socketing Requirements ............................................................................................................................. 50|Table 3.6. Hot Socketing Requirements ............................................................................................................................. 50|
|Table 3.7. DC Electrical Characteristics ............................................................................................................................... 50|Table 3.7. DC Electrical Characteristics ............................................................................................................................... 50|
|Table 3.8. ECP5/ECP5-5G Supply Current (Static) ............................................................................................................... 51|Table 3.8. ECP5/ECP5-5G Supply Current (Static) ............................................................................................................... 51|
|Table 3.9. ECP5UM ............................................................................................................................................................. 52|Table 3.9. ECP5UM ............................................................................................................................................................. 52|
|Table 3.10. ECP5-5G ........................................................................................................................................................... 53|Table 3.10. ECP5-5G ........................................................................................................................................................... 53|
|Table 3.11. sysI/O Recommended Operating Conditions ................................................................................................... 54|Table 3.11. sysI/O Recommended Operating Conditions ................................................................................................... 54|
|Table 3.12. Single-Ended DC Characteristics ...................................................................................................................... 55|Table 3.12. Single-Ended DC Characteristics ...................................................................................................................... 55|
|Table 3.13. LVDS ................................................................................................................................................................. 56|Table 3.13. LVDS ................................................................................................................................................................. 56|
|Table 3.14. LVDS25E DC Conditions .................................................................................................................................... 57|Table 3.14. LVDS25E DC Conditions .................................................................................................................................... 57|
|Table 3.15. BLVDS25 DC Conditions ................................................................................................................................... 58|Table 3.15. BLVDS25 DC Conditions ................................................................................................................................... 58|
|Table 3.16. LVPECL33 DC Conditions .................................................................................................................................. 59|Table 3.16. LVPECL33 DC Conditions .................................................................................................................................. 59|
|Table 3.17. MLVDS25 DC Conditions .................................................................................................................................. 60|Table 3.17. MLVDS25 DC Conditions .................................................................................................................................. 60|
|Table 3.18. Input to SLVS .................................................................................................................................................... 61|Table 3.18. Input to SLVS .................................................................................................................................................... 61|
|Table 3.19. Pin-to-Pin Performance .................................................................................................................................... 62|Table 3.19. Pin-to-Pin Performance .................................................................................................................................... 62|
|Table 3.20. Register-to-Register Performance ................................................................................................................... 63|Table 3.20. Register-to-Register Performance ................................................................................................................... 63|
|Table 3.21. ECP5/ECP5-5G Maximum I/O Buffer Speed ..................................................................................................... 64|Table 3.21. ECP5/ECP5-5G Maximum I/O Buffer Speed ..................................................................................................... 64|
|Table 3.22. ECP5/ECP5-5G External Switching Characteristics ........................................................................................... 65|Table 3.22. ECP5/ECP5-5G External Switching Characteristics ........................................................................................... 65|
|Table 3.23. sysCLOCK PLL Timing ........................................................................................................................................ 72|Table 3.23. sysCLOCK PLL Timing ........................................................................................................................................ 72|
|Table 3.24. Serial Output Timing and Levels ...................................................................................................................... 73|Table 3.24. Serial Output Timing and Levels ...................................................................................................................... 73|
|Table 3.25. Channel Output Jitter ....................................................................................................................................... 73|Table 3.25. Channel Output Jitter ....................................................................................................................................... 73|
|Table 3.26. SERDES/PCS Latency Breakdown ..................................................................................................................... 74|Table 3.26. SERDES/PCS Latency Breakdown ..................................................................................................................... 74|
|Table 3.27. Serial Input Data Specifications ....................................................................................................................... 75|Table 3.27. Serial Input Data Specifications ....................................................................................................................... 75|
|Table 3.28. Receiver Total Jitter Tolerance Specification ................................................................................................... 75|Table 3.28. Receiver Total Jitter Tolerance Specification ................................................................................................... 75|
|Table 3.29. External Reference Clock Specification (refclkp/refclkn) ................................................................................. 76|Table 3.29. External Reference Clock Specification (refclkp/refclkn) ................................................................................. 76|
|Table 3.30. PCIe (2.5 Gb/s) ................................................................................................................................................. 77|Table 3.30. PCIe (2.5 Gb/s) ................................................................................................................................................. 77|
|Table 3.31. PCIe (5 Gb/s) .................................................................................................................................................... 78|Table 3.31. PCIe (5 Gb/s) .................................................................................................................................................... 78|
|Table 3.32. CPRI LV2 E.48 Electrical and Timing Characteristics ........................................................................................ 80|Table 3.32. CPRI LV2 E.48 Electrical and Timing Characteristics ........................................................................................ 80|
|Table 3.33. Transmit ........................................................................................................................................................... 81|Table 3.33. Transmit ........................................................................................................................................................... 81|
|Table 3.34. Receive and Jitter Tolerance ............................................................................................................................ 81|Table 3.34. Receive and Jitter Tolerance ............................................................................................................................ 81|
|Table 3.35. Transmit ........................................................................................................................................................... 81|Table 3.35. Transmit ........................................................................................................................................................... 81|



© 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02012-2.2 

7 

**ECP5 and ECP5-5G Family Data Sheet** 

|Table 3.36. Receive and Jitter Tolerance ............................................................................................................................ 82|Table 3.36. Receive and Jitter Tolerance ............................................................................................................................ 82|
|---|---|
|Table 3.37. Transmit ........................................................................................................................................................... 82|Table 3.37. Transmit ........................................................................................................................................................... 82|
|Table 3.38. Receive and Jitter Tolerance ............................................................................................................................ 82|Table 3.38. Receive and Jitter Tolerance ............................................................................................................................ 82|
|Table 3.39. Transmit ........................................................................................................................................................... 83|Table 3.39. Transmit ........................................................................................................................................................... 83|
|Table 3.40. Receive ............................................................................................................................................................. 83|Table 3.40. Receive ............................................................................................................................................................. 83|
|Table 3.41|Table 3.41_._Reference Clock ............................................................................................................................................... 83|
|Table 3.42. ECP5/ECP5-5G sysCONFIG Port Timing Specifications ..................................................................................... 84|Table 3.42. ECP5/ECP5-5G sysCONFIG Port Timing Specifications ..................................................................................... 84|
|Table 3.43. JTAG Port Timing Specifications ....................................................................................................................... 89|Table 3.43. JTAG Port Timing Specifications ....................................................................................................................... 89|
|Table 3.44. Test Fixture Required Components, Non-Terminated Interfaces .................................................................... 91|Table 3.44. Test Fixture Required Components, Non-Terminated Interfaces .................................................................... 91|



© 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

8 

FPGA-DS-02012-2.2 

**ECP5 and ECP5-5G Family Data Sheet** 

## **Acronyms in This Document** 

A list of acronyms used in this document. 

|**Acronym **<br>~~Pe~~|**Definition**|
|---|---|
|ALU<br>~~Pe~~<br>~~a~~|Arithmetic Logic Unit<br>|
|BGA<br>~~Ce~~|Ball Grid Array<br>~~Ce~~|
|CDR|Clock and Data Recovery|
|CRC<br>~~ee~~|Cycle RedundancyCode<br>~~ee~~|
|DCC<br>~~a~~|Dynamic Clock Control|
|DCS<br>~~a~~|Dynamic Clock Select<br>|
|DDR<br>~~Ce~~|Double Data Rate<br>~~Ce~~|
|DLL<br>~~pe~~|Delay-Locked Loops<br>|
|DSP<br>~~pe~~|Digital Signal Processing<br>|
|EBR<br>~~peee~~|Embedded Block RAM<br>~~ee~~|
|ECLK<br>~~a~~|Edge Clock<br>|
|FFT<br>~~Ce~~|Fast Fourier Transforms<br>~~Ce~~|
|FIFO<br>~~Ce~~|First In First Out<br>~~Ce~~|
|FIR|Finite Impulse Response|
|LVCMOS<br>~~ee~~|Low-Voltage ComplementaryMetal Oxide Semiconductor<br>~~ee~~|
|LVDS<br>~~a~~|Low-Voltage Differential Signaling<br>|
|LVPECL<br>~~Ce~~|Low Voltage Positive Emitter Coupled Logic<br>~~Ce~~|
|LVTTL<br>~~Ce~~|Low Voltage Transistor-Transistor Logic<br>~~Ce~~|
|LUT|Look UpTable|
|MLVDS<br>~~ee~~|Multipoint Low-Voltage Differential Signaling<br>~~ee~~|
|PCI<br>~~a~~|Peripheral Component Interconnect<br>|
|PCS<br>~~Ce~~|Physical CodingSublayer<br>~~Ce~~|
|PCLK<br>~~a~~<br>~~ee~~|PrimaryClock|
|PDPR<br>~~a~~<br>~~ee~~<br>~~**e**e~~|Pseudo Dual Port RAM|
|PFU<br>~~ee~~<br>~~**e**e~~|Programmable Functional Unit|
|PIC<br>~~**e**e~~|Programmable I/O Cells<br>~~e~~|
|PLL<br>~~a~~|Phase-Locked Loops|
|POR<br>~~a~~<br>~~ee~~|Power On Reset|
|SCI<br>~~a~~<br>~~ee~~<br>~~ee~~|SERDES Client Interface|
|SERDES<br>~~ee~~<br>~~ee~~<br>~~**e**e~~|Serializer/Deserializer|
|SEU<br>~~ee~~<br>~~**e**e~~|Single Event Upset|
|SLVS<br>~~**e**e~~|Scalable Low-Voltage Signaling<br>~~e~~|
|SPI<br>~~a~~<br>~~ee~~|Serial Peripheral Interface|
|SPR<br>~~a~~<br>~~ee~~<br>~~ee~~|Single Port RAM|
|SRAM<br>~~ee~~<br>~~ee~~<br>~~ee~~|Static Random-Access Memory|
|TAP<br>~~ee~~<br>~~ee~~|Test Access Port|
|TDM<br>~~ee~~<br>~~a~~|Time Division Multiplexing|



© 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02012-2.2 

9 

**ECP5 and ECP5-5G Family Data Sheet** 

## **1. General Description** 

The ECP5™/ECP5-5G™ family of FPGA devices is optimized to deliver high performance features such as an enhanced DSP architecture, high speed SERDES (Serializer/Deserializer), and high speed source synchronous interfaces, in an economical FPGA fabric. This combination is achieved through advances in device architecture and the use of 40 nm technology making the devices suitable for high-volume, highspeed, and low-cost applications. 

The ECP5/ECP5-5G device family covers look-up-table (LUT) capacity to 84K logic elements and supports up to 365 user I/O. The ECP5/ECP5-5G device family also offers up to 156 18 x 18 multipliers and a wide range of parallel I/O standards. 

The ECP5/ECP5-5G FPGA fabric is optimized high performance with low power and low cost in mind. The ECP5/ ECP5-5G devices utilize reconfigurable SRAM logic technology and provide popular building blocks such as LUT-based logic, distributed and embedded memory, Phase-Locked Loops (PLLs), Delay-Locked Loops (DLLs), pre-engineered source synchronous I/O support, enhanced sysDSP slices and advanced configuration support, including encryption and dual-boot capabilities. 

The pre-engineered source synchronous logic implemented in the ECP5/ECP5-5G device family supports a broad range of interface standards including DDR2/3, LPDDR2/3, XGMII, and 7:1 LVDS. The ECP5/ECP5-5G device family also features high speed SERDES with dedicated Physical Coding Sublayer (PCS) functions. High jitter tolerance and low transmit jitter allow the SERDES plus PCS blocks to be configured to support an array of popular data protocols including PCI Express, Ethernet (XAUI, GbE, and SGMII) and CPRI. Transmit De-emphasis with pre- and post-cursors, and Receive Equalization settings make the SERDES suitable for transmission and reception over various forms of media. 

The ECP5/ECP5-5G devices also provide flexible, reliable and secure configuration options, such as dual-boot capability, bit-stream encryption, and TransFR field upgrade features. 

ECP5-5G family devices have made some enhancement in the SERDES compared to ECP5UM devices. These enhancements increase the performance of the SERDES to up to 5 Gb/s data rate. 

The ECP5-5G family devices are pin-to-pin compatible with the ECP5UM devices. These allows a migration path for you to port designs from ECP5UM to ECP5-5G devices to get higher performance. 

The Lattice Diamond™ design software allows large complex designs to be efficiently implemented using the ECP5/ECP5-5G FPGA family. Synthesis library support for ECP5/ECP5-5G devices is available for popular logic synthesis tools. The Diamond tools use the synthesis tool output along with the constraints from its floor planning tools to place and route the design in the ECP5/ECP5-5G device. The tools extract the timing from the routing and back-annotate it into the design for timing verification. 

Lattice provides many pre-engineered IP (Intellectual Property) modules for the ECP5/ECP5-5G family. By using these configurable soft core IPs as standardized blocks, designers are free to concentrate on the unique aspects of their design, increasing their productivity. 

## **1.1. Features** 

- Higher Logic Density for Increased System Integration 

   - 12K to 84K LUTs 

   - 197 to 365 user programmable I/O 

- Embedded SERDES 

   - 270 Mb/s, up to 3.2 Gb/s, SERDES interface (ECP5) 

   - 270 Mb/s, up to 5.0 Gb/s, SERDES interface (ECP5-5G) 

   - Supports eDP in RDR (1.62 Gb/s) and HDR 

   - (2.7 Gb/s) 

   - Up to four channels per device: PCI Express, Ethernet (1GbE, SGMII, XAUI), and CPRI 

- sysDSP™ 

   - Fully cascadable slice architecture 

   - 12 to 160 slices for high performance multiply and accumulate 

   - Powerful 54-bit ALU operations 

   - Time Division Multiplexing MAC Sharing 

   - Rounding and truncation 

   - Each slice supports 

      - Half 36 x 36, two 18 x 18 or four 9 x 9 multipliers 

      - Advanced 18 x 36 MAC and 18 x 18 Multiply-Multiply-Accumulate (MMAC) operations 

- Flexible Memory Resources 

   - Up to 3.744 Mb sysMEM™ Embedded Block 

   - RAM (EBR) 

   - 194K to 669K bits distributed RAM 

© 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

10 

FPGA-DS-02012-2.2 

**ECP5 and ECP5-5G Family Data Sheet** 

- sysCLOCK Analog PLLs and DLLs 

   - Four DLLs and four PLLs in LFE5-45 and LFE5-85; two DLLs and two PLLs in LFE5-25 and LFE5-12 

- Pre-Engineered Source Synchronous I/O 

   - DDR registers in I/O cells 

   - Dedicated read/write levelling functionality 

   - Dedicated gearing logic 

   - Source synchronous standards support 

   - ADC/DAC, 7:1 LVDS, XGMII 

   - High Speed ADC/DAC devices 

   - Dedicated DDR2/DDR3 and LPDDR2/LPDDR3 memory support with DQS logic, up to 800 Mb/s data-rate 

- Programmable sysI/O™ Buffer Supports Wide Range of Interfaces 

   - On-chip termination 

   - LVTTL and LVCMOS 33/25/18/15/12 

   - SSTL 18/15 I, II 

   - Flexible Device Configuration 

      - Shared bank for configuration I/O 

      - SPI boot flash interface 

      - Dual-boot images supported 

      - Slave SPI 

      - TransFR™ I/O for simple field updates 

   - Single Event Upset (SEU) Mitigation Support 

      - Soft Error Detect – Embedded hard macro 

      - Soft Error Correction – Without stopping user operation 

      - Soft Error Injection – Emulate SEU event to debug system error handling 

   - System Level Support 

      - IEEE 1149.1 and IEEE 1532 compliant 

      - Reveal Logic Analyzer 

      - On-chip oscillator for initialization and general use 

      - V core power supply for ECP5, 1.2 V core power supply for ECP5UM5G 

- HSUL12 

- LVDS, Bus-LVDS, LVPECL, RSDS, MLVDS 

- subLVDS and SLVS, SoftIP MIPI D-PHY receiver/transmitter interfaces 

**Table 1.1. ECP5 and ECP5-5G Family Selection Guide** 

|**Device**<br>~~a~~<br>~~po~~|**LFE5UM-25**<br>**LFE5UM5G-25**<br>~~a~~|**LFE5UM-45**<br>**LFE5UM5G-45**<br>~~ee~~|**LFE5UM-85**<br>**LFE5UM5G-85**<br>~~ee~~|**LFE5U-**<br>**12**<br>~~ee~~|**LFE5U-**<br>**25**<br>~~ee~~|**LFE5U-**<br>**45**|**LFE5U-**<br>**85**|
|---|---|---|---|---|---|---|---|
|LUTs(K)<br>~~a~~<br>~~po~~|24<br>~~a~~|44<br>~~ee~~|84<br>~~ee~~|12<br>~~ee~~|24<br>~~ee~~|44|84|
|sysMEM Blocks(18 Kb)<br>~~po~~<br>~~Ge~~<br>~~po~~|56<br>~~Ge~~|108<br>~~GCG~~|208<br>~~GCG~~|32<br>~~GCG~~|56<br>~~GCG~~|108|208|
|Embedded Memory (Kb)<br>~~po~~<br>~~Ge~~|1,008<br>~~Ge~~|1944<br>~~GO~~|3744<br>~~GO~~|576<br>~~GO~~|1,008|1944|3744|
|Distributed RAM Bits(Kb)<br>~~po~~<br>~~Ge~~<br>~~Ge~~|194<br>~~Ge~~<br>~~Ge~~|351<br>~~Ge~~<br>~~GO~~|669<br>~~Ge~~<br>~~GO~~|97<br>~~Ge~~<br>~~GO~~|194<br>~~Ge~~|351<br>~~Ge~~|669<br>~~Ge~~|
|18 X 18 Multipliers<br>~~Ge~~<br>~~Ge~~|28<br>~~Ge~~<br>~~Ge~~|72<br>~~Ge~~<br>~~GO~~|156<br>~~Ge~~<br>~~GO~~<br>~~GG~~|28<br>~~Ge~~<br>~~GO~~<br>~~GG~~|28<br>~~Ge~~<br>~~GG~~|72<br>~~Ge~~|156<br>~~Ge~~|
|SERDES(Dual/Channels)<br>~~Ge~~<br>~~Oe~~|1/2<br>~~Ge~~<br>~~Oe~~|2/4<br>~~GO~~<br>~~GGG~~|2/4<br>~~GO~~<br>~~GG~~<br>~~GGG~~|0<br>~~GO~~<br>~~GG~~<br>~~GGG~~|0<br>~~GG~~<br>~~GGG~~|0|0|
|PLLs/DLLs<br>~~Oe~~<br>~~I~~|2/2<br>~~Oe~~<br>~~I~~|4/4<br>~~GGG~~<br>~~I~~|4/4<br>~~GGG~~<br>~~I~~|2/2<br>~~GGG~~<br>~~I~~|2/2<br>~~GGG~~<br>~~I~~|4/4<br>~~I~~|4/4<br>~~I~~|
|**Packages(SERDES Channels/I/O Count)**<br>~~I~~||||||||
|144 TQFP<br>(10 x 10 mm, 0.5 mm)<br>~~I~~<br>~~a~~|—<br>~~I~~<br>~~a~~<br>~~a~~|—<br>~~I~~<br>~~a~~<br>~~ee~~|—<br>~~I~~<br>~~a~~<br>~~ee~~|0/96<br>~~I~~<br>~~a~~<br>~~ee~~|0/96<br>~~I~~<br>~~a~~|0/96<br>~~I~~<br>~~a~~|—<br>~~I~~<br>~~a~~|
|256 caBGA<br>(14 x 14 mm, 0.8 mm)<br>~~a ee~~<br>~~es~~|—<br>~~ee~~<br>~~ee~~|—<br>~~ee~~|—<br>~~ee~~<br>~~ee~~|0/197<br>~~ee~~<br>~~ee~~|0/197<br>~~ee~~<br>~~ee~~|0/197<br>~~ee~~<br>~~ee~~|—<br>~~ee~~|
|285 csfBGA<br>(10 x 10 mm, 0.5 mm)<br>~~es~~<br>~~a~~<br>~~a~~|2/118<br>~~ee~~<br>~~ee~~<br>|2/118<br>~~ee~~<br>|2/118<br>~~ee~~<br>~~ee~~<br>|0/118<br>~~ee~~<br>~~ee~~|0/118<br>~~ee~~<br>~~ee~~<br>~~ee~~|0/118<br>~~ee~~<br>~~ee~~<br>~~ee~~|0/118<br>~~ee~~|
|381 caBGA<br>(17 x 17 mm, 0.8 mm)<br>~~es ~~<br>~~a~~<br>~~a~~<br>~~a~~|2/197<br> ~~ee~~<br>~~ee~~<br>~~ee~~<br>|4/203<br>~~ee~~<br>~~ee~~<br>|4/205<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>|0/197<br>~~ee ~~<br>~~ee~~<br>|0/197<br> ~~ee ~~<br>~~ee~~<br>~~ee~~<br>|0/203<br> ~~ee~~<br>~~ee~~<br>~~ee~~<br>|0/205<br>~~ee~~<br>|
|554 caBGA<br>(23 x 23 mm, 0.8 mm)<br>~~a~~<br>~~a~~<br>~~a~~|—<br>~~ee~~<br>~~ee~~<br>|4/245<br>~~ee~~<br>~~ee~~<br>|4/259<br>~~ee~~<br>~~ee~~<br>|—<br>~~ee~~<br>|—<br>~~ee~~<br>~~ee~~<br>|0/245<br>~~ee~~<br>~~ee~~<br>|0/259<br>~~ee~~<br>|
|756 caBGA<br>(27 x 27 mm, 0.8 mm)<br>~~a ~~<br>~~a ~~|—<br> ~~ee~~<br> ~~ee~~|—<br>~~ee ~~<br>~~ee~~|4/365<br> ~~ee~~<br>~~ee~~|—<br>~~ee~~|—<br>~~ee ~~<br>~~ee~~|—<br> ~~ee~~<br>~~ee~~|0/365<br>~~ee~~|



© 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02012-2.2 

11 

**ECP5 and ECP5-5G Family Data Sheet** 

## **2. Architecture** 

## **2.1. Overview** 

Each ECP5/ECP5-5G device contains an array of logic blocks surrounded by Programmable I/O Cells (PIC). Interspersed between the rows of logic blocks are rows of sysMEM™ Embedded Block RAM (EBR) and rows of sysDSP™ Digital Signal Processing slices, as shown in Figure 2.1. The LFE5-85 devices have three rows of DSP slices, the LFE5-45 devices have two rows, and both LFE5-25 and LFE5-12 devices have one. In addition, the LFE5UM/LFE5UM5G devices contain SERDES Duals on the bottom of the device. 

The Programmable Functional Unit (PFU) contains the building blocks for logic, arithmetic, RAM, and ROM functions. The PFU block is optimized for flexibility, allowing complex designs to be implemented quickly and efficiently. Logic Blocks are arranged in a two-dimensional array. 

The ECP5/ECP5-5G devices contain one or more rows of sysMEM EBR blocks. sysMEM EBRs are large, dedicated 18 Kb fast memory blocks. Each sysMEM block can be configured in a variety of depths and widths as RAM or ROM. In addition, ECP5/ECP5-5G devices contain up to three rows of DSP slices. Each DSP slice has multipliers and adder/accumulators, which are the building blocks for complex signal processing capabilities. 

The ECP5 devices feature up to four embedded 3.2 Gb/s SERDES channels, and the ECP5-5G devices feature up to four embedded 5 Gb/s SERDES channels. Each SERDES channel contains independent 8b/10b encoding / decoding, polarity adjust and elastic buffer logic. Each group of two SERDES channels, along with its Physical Coding Sublayer (PCS) block, creates a dual DCU (Dual Channel Unit). The functionality of the SERDES/PCS duals can be controlled by SRAM cell settings during device configuration or by registers that are addressable during device operation. The registers in every dual can be programmed via the SERDES Client Interface (SCI). These DCUs (up to two) are located at the bottom of the devices. 

Each PIC block encompasses two PIOs (PIO pairs) with their respective sysI/O buffers. The sysI/O buffers of the ECP5/ECP5-5G devices are arranged in seven banks (eight banks for LFE5-85 devices in caBGA756 and caBGA554 packages), allowing the implementation of a wide variety of I/O standards. One of these banks (Bank 8) is shared with the programming interfaces. Half of the PIO pairs on the left and right edges of the device can be configured as LVDS transmit pairs, and all pairs on left and right can be configured as LVDS receive pairs. The PIC logic in the left and right banks also includes pre-engineered support to aid in the implementation of high speed source synchronous standards such as XGMII, 7:1 LVDS, along with memory interfaces including DDR3 and LPDDR3. 

The ECP5/ECP5-5G registers in PFU and sysI/O can be configured to be SET or RESET. After power up and the device is configured, it enters into user mode with these registers SET/RESET according to the configuration setting, allowing the device entering to a known state for predictable system function. 

Other blocks provided include PLLs, DLLs and configuration functions. The ECP5/ECP5-5G architecture provides up to four Delay-Locked Loops (DLLs) and up to four Phase-Locked Loops (PLLs). The PLL and DLL blocks are located at the corners of each device. 

The configuration block that supports features such as configuration bit-stream decryption, transparent updates and dual-boot support is located at the bottom of each device, to the left of the SERDES blocks. Every device in the ECP5/ECP5-5G family supports a sysCONFIG™ ports located in that same corner, powered by VCCIO8, allowing for serial or parallel device configuration. 

In addition, every device in the family has a JTAG port. This family also provides an on-chip oscillator and soft error detect capability. The ECP5 devices use 1.1 V and ECP5UM5G devices use 1.2 V as their core voltage. 

© 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

12 

FPGA-DS-02012-2.2 

**ECP5 and ECP5-5G Family Data Sheet** 

**Figure 2.1. Simplified Block Diagram, LFE5UM/LFE5UM5G-85 Device (Top Level)** 

## **2.2. PFU Blocks** 

The core of the ECP5/ECP5-5G device consists of PFU blocks. Each PFU block consists of four interconnected slices numbered 0-3, as shown in Figure 2.2. Each slice contains two LUTs. All the interconnections to and from PFU blocks are from routing. There are 50 inputs and 23 outputs associated with each PFU block. 

The PFU block can be used in Distributed RAM or ROM function, or used to perform Logic, Arithmetic, or ROM functions. Table 2.1 shows the functions each slice can perform in either mode. 

© 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02012-2.2 

13 

**ECP5 and ECP5-5G Family Data Sheet** 

**Figure 2.2. PFU Diagram** 

## **2.2.1. Slice** 

Each slice contains two LUT4s feeding two registers. In Distributed SRAM mode, Slice 0 through Slice 2 are configured as distributed memory, and Slice 3 is used as Logic or ROM. Table 2.1 shows the capability of the slices along with the operation modes they enable. In addition, each PFU contains logic that allows the LUTs to be combined to perform functions such as LUT5, LUT6, LUT7 and LUT8. There is control logic to perform set/reset functions (programmable as synchronous/ asynchronous), clock select, chip-select and wider RAM/ROM functions. 

**Table 2.1. Resources and Modes Available per Slice** 

|**Slice**|**PFU(Used in Distributed SRAM)**|**PFU(Used in Distributed SRAM)**|**PFU(Not used as Distributed SRAM)**|**PFU(Not used as Distributed SRAM)**|
|---|---|---|---|---|
||**Resources**|**Modes**|**Resources**|**Modes**|
|Slice 0|2 LUT4s and 2 Registers|RAM|2 LUT4s and 2 Registers|Logic, Ripple, ROM|
|Slice 1|2 LUT4s and 2 Registers|RAM|2 LUT4s and 2 Registers|Logic, Ripple, ROM|
|Slice 2|2 LUT4s and 2 Registers|RAM|2 LUT4s and 2 Registers|Logic, Ripple, ROM|
|Slice 3|2 LUT4s and 2 Registers|Logic, Ripple, ROM|2 LUT4s and 2 Registers|Logic, Ripple, ROM|



Figure 2.3 shows an overview of the internal logic of the slice. The registers in the slice can be configured for positive/negative and edge triggered or level sensitive clocks. 

Each slice has 14 input signals, 13 signals from routing and one from the carry-chain (from the adjacent slice or PFU). There are five outputs, four to routing and one to carry-chain (to the adjacent PFU). There are two inter slice/ PFU output signals that are used to support wider LUT functions, such as LUT6, LUT7, and LUT8. Table 2.2 and Figure 2.3 list the signals associated with all the slices. Figure 2.4 shows the connectivity of the inter-slice/PFU signals that support LUT5, LUT6, LUT7, and LUT8. 

© 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02012-2.2 

14 

**ECP5 and ECP5-5G Family Data Sheet** 

**==> picture [177 x 428] intentionally omitted <==**

**----- Start of picture text -----**<br>
FCO<br>FXA<br>FXB F<br>M1 id<br>M0<br>A1<br>B1 LUT4 &<br>C1 i<< CARRY*<br>D1<br>a 7<br>F1 ie<br>F1<br>FF<br>: 7<br>Q1<br>A0<br>B0 LUT4 &<br>C0 [| {lg CARRY*<br>D0<br>ob<br>F0 i<br>F0<br>FF<br>7<br>:<br>Q0 4<br>CE id<br>CLK id<br>LSR<br>FCI From Different Slice/PFU<br>**----- End of picture text -----**<br>


**Notes** : For Slices 0 and 1, memory control signals are generated from Slice 2 as follows: WCK is CLK WRE is from LSR DI[3:2] for Slice 1 and DI[1:0] for Slice 0 data from Slice 2 WAD [A:D] is a 4-bit address from slice 2 LUT input 

**Figure 2.3. Slice Diagram** 

© 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02012-2.2 

15 

**ECP5 and ECP5-5G Family Data Sheet** 

**==> picture [474 x 347] intentionally omitted <==**

**----- Start of picture text -----**<br>
PFU Col(n-1) PFU Col(n) PFU Col(n+1)<br>B1A1 F1 LUT8 B1A1 F1 LUT8 B1A1 F1 LUT8<br>C1 C1 C1<br>D1 Q1 D1 Q1 D1 Q1<br>A0 A0 A0<br>B0 LUT5 B0 LUT5 B0 LUT5<br>C0 F0 C0 F0 C0 F0<br>D0 D0 D0<br>FXB Q0 FXB Q0 FXB Q0<br>LUT7 Output  FXA FXA FXA LUT7 Output<br>To Next PFU From Previous PFU<br>A1 LUT6 A1 LUT6 A1 LUT6<br>B1 F1 B1 F1 B1 F1<br>C1 C1 C1<br>D1 Q1 D1 Q1 D1 Q1<br>A0 A0 A0<br>B0 LUT5 B0 LUT5 B0 LUT5<br>C0 F0 C0 F0 C0 F0<br>D0 D0 D0<br>FXB Q0 FXB Q0 FXB Q0<br>FXA FXA FXA<br>B1A1 F1 LUT7 B1A1 F1 LUT7 B1A1 F1 LUT7<br>C1 C1 C1<br>D1 Q1 D1 Q1 D1 Q1<br>A0 A0 A0<br>B0 LUT5 B0 LUT5 B0 LUT5<br>C0 F0 C0 F0 C0 F0<br>D0 D0 D0<br>FXB Q0 FXB Q0 FXB Q0<br>FXA FXA FXA<br>A1 LUT6 A1 LUT6 A1 LUT6<br>B1 F1 B1 F1 B1 F1<br>C1 C1 C1<br>D1 Q1 D1 Q1 D1 Q1<br>A0 A0 A0<br>B0 LUT5 B0 LUT5 B0 LUT5<br>C0 F0 C0 F0 C0 F0<br>D0 D0 D0<br>FXB Q0 FXB Q0 FXB Q0<br>FXA FXA FXA<br>3 3 3<br>SLICE SLICE SLICE<br>2 2 2<br>SLICE SLICE SLICE<br>1 1 1<br>SLICE SLICE SLICE<br>0 0 0<br>SLICE SLICE SLICE<br>**----- End of picture text -----**<br>


**Figure 2.4. Connectivity Supporting LUT5, LUT6, LUT7, and LUT8** 

**Table 2.2. Slice Signal Descriptions** 

|**Function**|**Type**|**Signal Names**|**Description**|
|---|---|---|---|
|Input|Data signal|A0, B0, C0, D0|Inputs to LUT4|
|Input|Data signal|A1, B1, C1, D1|Inputs to LUT4|
|Input|Multi-purpose|M0|Multipurpose Input|
|Input|Multi-purpose|M1|Multipurpose Input|
|Input|Control signal|CE|Clock Enable|
|Input|Control signal|LSR|Local Set/Reset|
|Input|Control signal|CLK|System Clock|
|Input|Inter-PFU signal|FCI|Fast Carry-in1|
|Input|Inter-slice signal|FXA|Intermediate signal to generate LUT6, LUT7 and LUT82|
|Input|Inter-slice signal|FXB|Intermediate signal to generate LUT6, LUT7 and LUT82|
|Output|Data signals|F0, F1|LUT4 output register bypass signals|
|Output|Data signals|Q0, Q1|Register outputs|
|Output|Inter-PFU signal|FCO|Fast carry chain output1|



## **Notes** : 

1. See Figure 2.3 for connection details. 

2. Requires two adjacent PFUs. 

© 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02012-2.2 

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**ECP5 and ECP5-5G Family Data Sheet** 

## **2.2.2. Modes of Operation** 

Slices 0-2 have up to four potential modes of operation: Logic, Ripple, RAM, and ROM. Slice 3 is not needed for RAM mode, it can be used in Logic, Ripple, or ROM modes. 

## **2.2.2.1. Logic Mode** 

In this mode, the LUTs in each slice are configured as 4-input combinatorial lookup tables. A LUT4 can have 16 possible input combinations. Any four input logic functions can be generated by programming this lookup table. Since there are two LUT4s per slice, a LUT5 can be constructed within one slice. Larger look-up tables such as LUT6, LUT7, and LUT8 can be constructed by concatenating other slices. Note that LUT8 requires more than four slices. 

## **2.2.2.2. Ripple Mode** 

Ripple mode supports the efficient implementation of small arithmetic functions. In ripple mode, the following functions can be implemented by each slice: 

- Addition 2-bit 

- Subtraction 2-bit 

- Add/Subtract 2-bit using dynamic control 

- Up counter 2-bit 

- Down counter 2-bit 

- Up/Down counter with asynchronous clear 

- Up/Down counter with preload (sync) 

- Ripple mode multiplier building block 

- Multiplier support 

- Comparator functions of A and B inputs 

   - A greater-than-or-equal-to B 

   - A not-equal-to B 

   - A less-than-or-equal-to B 

Ripple Mode includes an optional configuration that performs arithmetic using fast carry chain methods. In this configuration (also referred to as CCU2 mode) two additional signals, Carry Generate and Carry Propagate, are generated on a per slice basis to allow fast arithmetic functions to be constructed by concatenating Slices. 

## **2.2.2.3. RAM Mode** 

In this mode, a 16 x 4-bit distributed single port RAM (SPR) can be constructed in one PFU using each LUT block in Slice 0 and Slice 1 as a 16 x 2-bit memory in each slice. Slice 2 is used to provide memory address and control signals. A 16 x 2-bit pseudo dual port RAM (PDPR) memory is created in one PFU by using one Slice as the read-write port and the other companion slice as the read-only port. The slice with the read-write port updates the SRAM data contents in both slices at the same write cycle. 

ECP5/ECP5-5G devices support distributed memory initialization. 

The Lattice design tools support the creation of a variety of different size memories. Where appropriate, the software constructs these using distributed memory primitives that represent the capabilities of the PFU. Table 2.3 lists the number of slices required to implement different distributed RAM primitives. For more information about using RAM in ECP5/ECP5-5G devices, refer to ECP5 and ECP5-5G Memory Usage Guide (FPGA-TN-02204). 

**Table 2.3. Number of Slices Required to Implement Distributed RAM** 

|**RAM**|**Number of Slices**|
|---|---|
|SPR 16 X 4|3|
|PDPR 16 X 4|6|



**Note** : SPR = Single Port RAM, PDPR = Pseudo Dual Port RAM 

© 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02012-2.2 

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**ECP5 and ECP5-5G Family Data Sheet** 

## **2.2.2.4. ROM Mode** 

ROM mode uses the LUT logic; hence, Slices 0 through 3 can be used in ROM mode. Preloading is accomplished through the programming interface during PFU configuration. 

For more information, refer to ECP5 and ECP5-5G Memory Usage Guide (FPGA-TN-02204). 

## **2.3. Routing** 

There are many resources provided in the ECP5/ECP5-5G devices to route signals individually or as busses with related control signals. The routing resources consist of switching circuitry, buffers and metal interconnect (routing) segments. The ECP5/ECP5-5G family has an enhanced routing architecture that produces a compact design. The Diamond design software tool suites take the output of the synthesis tool and places and routes the design. 

## **2.4. Clocking Structure** 

ECP5/ECP5-5G clocking structure consists of clock synthesis blocks (sysCLOCK PLL); balanced clock tree networks (PCLK and ECLK trees); and efficient clock logic modules (CLOCK DIVIDER and Dynamic Clock Select (DCS), Dynamic Clock Control (DCC) and DLL). All of these functions are described below. 

## **2.4.1. sysCLOCK PLL** 

The sysCLOCK PLLs provide the ability to synthesize clock frequencies. The devices in the ECP5/ECP5-5G family support two to four full-featured General Purpose PLLs. The sysCLOCK PLLs provide the ability to synthesize clock frequencies. 

The architecture of the PLL is shown in Figure 2.5. A description of the PLL functionality follows. 

CLKI is the reference frequency input to the PLL and its source can come from two different external CLK inputs or from internal routing. A non-glitchless 2-to-1 input multiplexor is provided to dynamically select between two different external reference clock sources. The CLKI input feeds into the input Clock Divider block. 

CLKFB is the feedback signal to the PLL which can come from internal feedback path, routing or an external I/O pin. The feedback divider is used to multiply the reference frequency and thus synthesize a higher frequency clock output. 

The PLL has four clock outputs CLKOP, CLKOS, CLKOS2 and CLKOS3. Each output has its own output divider, thus allowing the PLL to generate different frequencies for each output. The output dividers can have a value from 1 to 128. The CLKOP, CLKOS, CLKOS2, and CLKOS3 outputs can all be used to drive the primary clock network. Only CLKOP and CLKOS outputs can go to the edge clock network. 

The setup and hold times of the device can be improved by programming a phase shift into the CLKOS, CLKOS2, and CLKOS3 output clocks which advances or delays the output clock with reference to the CLKOP output clock. This phase shift can be either programmed during configuration or can be adjusted dynamically using the PHASESEL, PHASEDIR, PHASESTEP, and PHASELOADREG ports. 

The LOCK signal is asserted when the PLL determines it has achieved lock and de-asserted if a loss of lock is detected. 

© 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

18 

FPGA-DS-02012-2.2 

**ECP5 and ECP5-5G Family Data Sheet** 

**==> picture [445 x 223] intentionally omitted <==**

**----- Start of picture text -----**<br>
PHASESEL[1:0] Dynamic<br>PHASEDIR Phase<br>PHASESTEP Adjust<br>PHASELOADREG =<br>PLLREFCS<br>CLKOP<br>SEL VCO<br>Refclk Divider  CLKOP<br>CLK0<br>CLKI PLLCSOUT (1-128)<br>CLKI2 CLK1 CLKI Refclk Divider M Detector,Phase  VCO Divider CLKOS  CLKOS<br>VCO, and (1-128)<br>Loop Filter<br>mad _ T He<br>FBKSEL VCO CLKOS2<br>CLKFB Feedback  Divider  CLKOS2<br>Clock Divider (1-128)<br>VCO CLKOS3<br>Internal Feedback Divider  CLKOS3<br>CLKOP, CLKOS, CLKOS2, CLKOS3 (1-128)<br>ENCLKOP<br>ENCLKOS<br>ENCLKOS2<br>ENCLKOS3<br>RST Lock  LOCK<br>STDBY Detect<br>——a P<br>Figure 2.5. General Purpose PLL Diagram<br>**----- End of picture text -----**<br>


Table 2.4 provides a description of the signals in the PLL blocks. 

**Table 2.4. PLL Blocks Signal Descriptions** 

|**Signal**|**Type**|**Description**|
|---|---|---|
|CLKI|Input|Clock Input to PLL from external pin or routing|
|CLKI2|Input|Mixed clock input to PLL|
|SEL|Input|Input Clock select, selecting from CLKI and CLKI2 inputs|
|CLKFB|Input|PLL Feedback Clock|
|PHASESEL[1:0]|Input|Select which output to be adjusted on Phase by PHASEDIR, PHASESTEP, PHASELODREG|
|PHASEDIR|Input|Dynamic Phase adjustment direction.|
|PHASESTEP|Input|Dynamic Phase adjustment step.|
|PHASELOADREG|Input|Load dynamic phase adjustment values into PLL.|
|CLKOP|Output|Primary PLL output clock (with phase shift adjustment)|
|CLKOS|Output|Secondary PLL output clock (with phase shift adjust)|
|CLKOS2|Output|Secondary PLL output clock2 (with phase shift adjust)|
|CLKOS3|Output|Secondary PLL output clock3 (with phase shift adjust)|
|LOCK|Output|PLL LOCK to CLKI, Asynchronous signal. Active high indicates PLL lock|
|STDBY|Input|Standby signal to power down the PLL|
|RST|Input|Resets the PLL|
|ENCLKOP|Input|Enable PLL output CLKOP|
|ENCLKOS|Input|Enable PLL output CLKOS|
|ENCLKOS2|Input|Enable PLL output CLKOS2|
|ENCLKOS3|Input|Enable PLL output CLKOS3|



For more details on the PLL, you can refer to the ECP5 and ECP5-5G sysClock PLL/DLL Design and Usage Guide (FPGATN-02200). 

© 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02012-2.2 

19 

**ECP5 and ECP5-5G Family Data Sheet** 

## **2.5. Clock Distribution Network** 

There are two main clock distribution networks for any member of the ECP5/ECP5-5G product family, namely Primary Clock (PCLK) and Edge Clock (ECLK). These clock networks have the clock sources come from many different sources, such as Clock Pins, PLL outputs, DLLDEL outputs, Clock divider outputs, SERDES/PCS clocks and some on chip generated clock signal. There are clock dividers (CLKDIV) blocks to provide the slower clock from these clock sources. ECP5/ECP5-5G also supports glitchless dynamic enable function (DCC) for the PCLK Clock to save dynamic power. There are also some logics to allow dynamic glitchless selection between two clocks for the PCLK network (DCS). Overview of Clocking Network is shown in Figure 2.6 for LFE5UM/LFE5UM5G-85 device. 

**==> picture [473 x 212] intentionally omitted <==**

**----- Start of picture text -----**<br>
PIO PIO PIO PIO<br>DLL Bank 0 | {| Mid  | | | Bank 1 DLL<br>MUX<br>PLL _ PLL<br>|| 12 DCC<br>Quadrant TL 12 Primary Sources Quadrant TR<br>Primary  Primary<br>Clocks 16 FabricEntry FabricEntry 16 Clocks<br>' | [<br>CLKCLKDIV MUXMid  14 14 DCC 14 Primary Sources Center MUX 14 Primary Sources 14 DCC 14 MUXMid  CLKCLKDIV<br>DIV DIV<br>HR a a o<br>16 16<br>i Primary  | FabricEntry FabricEntry Primary  i<br>Clocks 16 Primary Sources Clocks<br>Quadrant BL 16 DCC Quadrant BR<br>[|<br>PLL Mid  PLL<br>MUX<br>DLL Bank 8 | [|] PCSCLKDIV - PCSCLKDIV Bank 4 DLL<br>SERDES DCU0 SERDES DCU1<br>ee<br>PIO<br>PIO<br>PIO<br>PIO<br>Bank 2<br>Bank 3<br>Edge Clocks<br>Edge Clocks<br>Edge Clocks<br>Edge Clocks<br>Bank 7<br>Bank 6<br>PIO<br>PIO<br>PIO<br>PIO<br>**----- End of picture text -----**<br>


**Figure 2.6. LFE5UM/LFE5UM5G-85 Clocking** 

## **2.5.1. Primary Clocks** 

The ECP5/ECP5-5G device family provides low-skew, high fan-out clock distribution to all synchronous elements in the FPGA fabric through the Primary Clock Network. 

The primary clock network is divided into four clocking quadrants: Top Left (TL), Bottom Left (BL), Top Right (TR), and Bottom Right (BR). Each of these quadrants has 16 clocks that can be distributed to the fabric in the quadrant. 

The Lattice Diamond software can automatically route each clock to one of the four quadrants up to a maximum of 16 clocks per quadrant. You can change how the clocks are routed by specifying a preference in the Lattice Diamond software to locate the clock to specific. The ECP5/ECP5-5G device provides you with a maximum of 64 unique clock input sources that can be routed to the primary Clock network. 

Primary clock sources are: 

- Clock input pins 

- PLL outputs 

- CLKDIV outputs 

- Internal FPGA fabric entries (with minimum general routing) 

- SERDES/PCS/PCSDIV clocks 

- OSC clock 

These sources are routed to one of four clock switches called a Mid Mux. The outputs of the Mid MUX are routed to the center of the FPGA where another clock switch, called the Center MUX, is used to route the primary clock sources to primary clock distribution to the ECP5/ECP5-5G fabric. These routing muxes are shown in Figure 2.6. Since there is a maximum of 60 unique clock input sources to the clocking quadrants, there are potentially 64 unique clock domains that can be used in the ECP5/ECP5-5G Device. For more information about the primary clock tree and connections, refer to ECP5 and ECP5-5G sysClock PLL/DLL Design and Usage Guide (FPGA-TN-02200). 

© 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

20 

FPGA-DS-02012-2.2 

**ECP5 and ECP5-5G Family Data Sheet** 

## **2.5.1.1. Dynamic Clock Control** 

The Dynamic Clock Control (DCC), Quadrant Clock enable/disable feature allows internal logic control of the quadrant primary clock network. When a clock network is disabled, the clock signal is static and not toggle. All the logic fed by that clock does not toggle, reducing the overall power consumption of the device. The disable function does not create glitch and increase the clock latency to the primary clock network. 

This DCC controls the clock sources from the Primary CLOCK MIDMUX before they are fed to the Primary Center MUXs that drive the quadrant clock network. For more information about the DCC, refer to ECP5 and ECP5-5G sysClock PLL/DLL Design and Usage Guide (FPGA-TN-02200). 

## **2.5.1.2. Dynamic Clock Select** 

The Dynamic Clock Select (DCS) is a smart multiplexer function available in the primary clock routing. It switches between two independent input clock sources. Depending on the operation modes, it switches between two (2) independent input clock sources either with or without any glitches. This is achieved regardless of when the select signal is toggled. Both input clocks must be running to achieve functioning glitch-less DCS output clock, but it is not required running clocks when used as non-glitch-less normal clock multiplexer. 

There are two DCS blocks per device that are fed to all quadrants. The inputs to the DCS block come from all the output of MIDMUXs and Clock from CIB located at the center of the PLC array core. The output of the DCS is connected to one of the inputs of Primary Clock Center MUX. 

Figure 2.7 shows the timing waveforms of the default DCS operating mode. The DCS block can be programmed to other modes. For more information about the DCS, refer to ECP5 and ECP5-5G sysClock PLL/DLL Design and Usage Guide (FPGA-TN-02200). 

**==> picture [20 x 156] intentionally omitted <==**

**----- Start of picture text -----**<br>
CLK0<br>CLK1<br>SEL<br>CLKO<br>**----- End of picture text -----**<br>


**Figure 2.7. DCS Waveforms** 

## **2.5.2. Edge Clock** 

ECP5/ECP5-5G devices have a number of high-speed edge clocks that are intended for use with the PIOs in the implementation of high-speed interfaces. There are two ECLK networks per bank I/O on the Left and Right sides of the devices. 

Each Edge Clock can be sourced from the following: 

- Dedicated Clock input pins (PCLK) 

- DLLDEL output (Clock delayed by 90o) 

- PLL outputs (CLKOP and CLKOS) 

- ECLKBRIDGE 

- Internal Nodes 

© 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02012-2.2 

21 

**ECP5 and ECP5-5G Family Data Sheet** 

**==> picture [466 x 213] intentionally omitted <==**

**----- Start of picture text -----**<br>
Top Left / Right PCLK Pin From ECLK of<br>other bank on<br>Top Left / Right DLLDEL Output same side<br>Top Right / Left PLL CLKOP<br>From<br>Top Right / Left PLL CLKOS ECLKBRIDGE<br>ECLK Tree<br>ECLKSYNC<br>Bottom Right / Left PLL CLKOP<br>Bottom Right / Left PLL CLKOS<br>Bottom Left / Right PCLK Pin<br>To ECLK of other<br>Bottom Left / Right DLLDEL Output bank on same side<br>To ECLKBRIDGE<br>to go to other side<br>From Routing<br>**----- End of picture text -----**<br>


**Figure 2.8. Edge Clock Sources per Bank** 

The edge clocks have low injection delay and low skew. They are used for DDR Memory or Generic DDR interfaces. For detailed information on Edge Clock connections, refer to ECP5 and ECP5-5G sysClock PLL/DLL Design and Usage Guide (FPGA-TN-02200). 

## **2.6. Clock Dividers** 

ECP5/ECP5-5G devices have two clock dividers, one on the left side and one on the right side of the device. These are intended to generate a slower-speed system clock from a high-speed edge clock. The block operates in a ÷2, ÷3.5 mode and maintains a known phase relationship between the divided down clock and the high-speed clock based on the release of its reset signal. 

The clock dividers can be fed from selected PLL outputs, external primary clock pins multiplexed with the DDRDEL Slave Delay or from routing. The clock divider outputs serve as primary clock sources and feed into the clock distribution network. The Reset (RST) control signal resets input and asynchronously forces all outputs to low. The SLIP signal slips the outputs one cycle relative to the input clock. For further information on clock dividers, refer to ECP5 and ECP5-5G sysClock PLL/DLL Design and Usage Guide (FPGA-TN-02200). Figure 2.9 shows the clock divider connections. 

**==> picture [451 x 119] intentionally omitted <==**

**----- Start of picture text -----**<br>
Primary Clock Pin OR<br>DLLDEL output clock<br>PLL clock output CLKDIV To Primary Clock Tree<br>(CLKOP/CLKOS) (/2 or /3.5) OR Routing<br>Primary<br>Clock Tree<br>OR Routing RST<br>SLIP<br>**----- End of picture text -----**<br>


**Figure 2.9. ECP5/ECP5-5G Clock Divider Sources** 

© 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

22 

FPGA-DS-02012-2.2 

**ECP5 and ECP5-5G Family Data Sheet** 

## **2.7. DDRDLL** 

Every DDRDLL (master DLL block) can generate phase shift code representing the amount of delay in a delay block that corresponding to 90° phase of the reference clock input. The reference clock can be either from PLL, or input pin. This code is used in the DQSBUF block that controls a set of DQS pin groups to interface with DDR memory (slave DLL). There are two DDRDLLs that supply two sets of codes (for two different reference clock frequencies) to each side of the I/O (at each of the corners). The DQSBUF uses this code to controls the DQS input of the DDR memory to 90° shift to clock DQs at the center of the data eye for DDR memory interface. 

The code is also sent to another slave DLL, DLLDEL, that takes a clock input and generates a 90° shift clock output to drive the clocking structure. This is useful to interface edge-aligned Generic DDR, where 90° clocking needs to be created. Figure 2.10 shows DDRDLL functional diagram. 

**==> picture [311 x 93] intentionally omitted <==**

**----- Start of picture text -----**<br>
DDRDLL<br>CLK — ><br>DDRDEL<br>RST — ><br>LOCK<br>UDDCNTLN —> -<br>DCNTL[7:0]<br>FREEZE — ><br>**----- End of picture text -----**<br>


**Figure 2.10. DDRDLL Functional Diagram** 

**Table 2.5. DDRDLL Ports List** 

|**Port Name**|**Type**|**Description**|
|---|---|---|
|CLK|Input|Reference clock input to the DDRDLL. Should run at the same frequencyas the clock to the delaycode.|
|RST|Input|Reset Input to the DDRDLL.|
|UDDCNTLN|Input|Update Control to update the delay code. The code is the DCNTL[7:0] outputs. These outputs are<br>updated when the UDDCNTLN signal is LOW.|
|FREEZE|Input|FREEZE goes high and, without a glitch, turns off the DLL internal clock and the ring oscillator output<br>clock. When FREEZEgoes low,it turns them back on.|
|DDRDEL|Output|The delay codes from the DDRDLL to be used in DQSBUF or DLLDEL.|
|LOCK|Output|Lock output to indicate the DDRDLL has valid delay output.|
|DCNTL [7:0]|Output|The delay codes from the DDRDLL available for the user IP.|



There are four identical DDRDLLs, one in each of the four corners in LFE5-85 and LFE5-45 devices, and two DDRDLLs in both LFE5-25 and LFE5-12 devices in the upper two corners. Each DDRDLL can generate delay code based on the reference frequency. The slave DLL (DQSBUF and DLLDEL) use the code to delay the signal, to create the phase shifted signal used for either DDR memory, to create 90° shift clock. Figure 2.11 shows the DDRDLL and the slave DLLs on the top level view. 

© 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02012-2.2 

23 

**ECP5 and ECP5-5G Family Data Sheet** 

**==> picture [223 x 133] intentionally omitted <==**

**----- Start of picture text -----**<br>
LFE5 Device<br>DLLDEL<br>|<br>fw] Pc|<br>5 ||<br>Ig<br>Q<br>|<br>ee ee<br>Config I/O<br>DDFDLL _ SERDES<br>**----- End of picture text -----**<br>


**Figure 2.11. ECP5/ECP5-5G DLL Top Level View (For LFE-45 and LFE-85)** 

## **2.8. sysMEM Memory** 

ECP5/ECP5-5G devices contain a number of sysMEM Embedded Block RAM (EBR). The EBR consists of an 18 Kb RAM with memory core, dedicated input registers and output registers with separate clock and clock enable. Each EBR includes functionality to support true dual-port, pseudo dual-port, single-port RAM, ROM and FIFO buffers (via external PFUs). 

## **2.8.1. sysMEM Memory Block** 

The sysMEM block can implement single port, dual port or pseudo dual port memories. Each block can be used in a variety of depths and widths as listed in Table 2.6. FIFOs can be implemented in sysMEM EBR blocks by implementing support logic with PFUs. The EBR block facilitates parity checking by supporting an optional parity bit for each data byte. EBR blocks provide byte-enable support for configurations with 18-bit and 36-bit data widths. For more information, refer to ECP5 and ECP5-5G Memory Usage Guide (FPGA-TN-02204). 

© 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

24 

FPGA-DS-02012-2.2 

**ECP5 and ECP5-5G Family Data Sheet** 

**Table 2.6. sysMEM Block Configurations** 

|**Memory Mode**|**Configurations**|
|---|---|
||16,384 x 1|
||8,192 x 2|
|Single Port|4,096 x 4<br>2,048 x 9|
||1,024 x 18|
||512 x 36|
||16,384 x 1|
||8,192 x 2|
|True Dual Port|4,096 x 4|
||2,048 x 9|
||1,024 x 18|
||16,384 x 1|
||8,192 x 2|
|Pseudo Dual Port|4,096 x 4|
||2,048 x 9|
||1,024 x 18|
||512 x 36|



## **2.8.2. Bus Size Matching** 

All of the multi-port memory modes support different widths on each of the ports. The RAM bits are mapped LSB word 0 to MSB word 0, LSB word 1 to MSB word 1, and so on. Although the word size and number of words for each port varies, this mapping scheme applies to each port. 

## **2.8.3. RAM Initialization and ROM Operation** 

If desired, the contents of the RAM can be pre-loaded during device configuration. By preloading the RAM block during the chip configuration cycle and disabling the write controls, the sysMEM block can also be utilized as a ROM. 

## **2.8.4. Memory Cascading** 

Larger and deeper blocks of RAM can be created using EBR sysMEM Blocks. Typically, the Lattice design tools cascade memory transparently, based on specific design inputs. 

## **2.8.5. Single, Dual and Pseudo-Dual Port Modes** 

In all the sysMEM RAM modes the input data and address for the ports are registered at the input of the memory array. The output data of the memory is optionally registered at the output. 

EBR memory supports the following forms of write behavior for single port or dual port operation: 

- Normal – Data on the output appears only during a read cycle. During a write cycle, the data (at the current address) does not appear on the output. This mode is supported for all data widths. 

- Write Through – A copy of the input data appears at the output of the same port during a write cycle. This mode is supported for all data widths. 

- Read-Before-Write – When new data is written, the old content of the address appears at the output. This mode is supported for x9, x18, and x36 data widths. 

© 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02012-2.2 

25 

**ECP5 and ECP5-5G Family Data Sheet** 

## **2.8.6. Memory Core Reset** 

The memory array in the EBR utilizes latches at the A and B output ports. These latches can be reset asynchronously or synchronously. RSTA and RSTB are local signals, which reset the output latches associated with Port A and Port B, respectively. The Global Reset (GSRN) signal can reset both ports. The output data latches and associated resets for both ports are as shown in Figure 2.12. 

**==> picture [351 x 190] intentionally omitted <==**

**----- Start of picture text -----**<br>
Memory Core D SET Q Port A[17:0]<br>a LCLR<br>Output Data<br> Latches<br>D SET Q Port B[17:0]<br>LCLR<br>a<br>RSTA<br>— ) ><br>RSTB<br>GSRN Ee<br>**----- End of picture text -----**<br>


Programmable Disable 

**Figure 2.12. Memory Core Reset** 

For further information on the sysMEM EBR block, see the list of technical documentation in Supplemental Information section. 

## **2.9. sysDSP™ Slice** 

The ECP5/ECP5-5G family provides an enhanced sysDSP architecture, making it ideally suited for low-cost, high-performance Digital Signal Processing (DSP) applications. Typical functions used in these applications are Finite Impulse Response (FIR) filters, Fast Fourier Transforms (FFT) functions, Correlators, Reed-Solomon/Turbo/Convolution encoders and decoders. These complex signal processing functions use similar building blocks such as multiply-adders and multiply-accumulators. 

## **2.9.1. sysDSP Slice Approach Compared to General DSP** 

Conventional general-purpose DSP chips typically contain one to four (Multiply and Accumulate) MAC units with fixed data-width multipliers; this leads to limited parallelism and limited throughput. Their throughput is increased by higher clock speeds. In the ECP5/ECP5-5G device family, there are many DSP slices that can be used to support different data widths. This allows designers to use highly parallel implementations of DSP functions. Designers can optimize DSP performance vs. area by choosing appropriate levels of parallelism. Figure 2.13 compares the fully serial implementation to the mixed parallel and serial implementation. 

© 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

26 

FPGA-DS-02012-2.2 

**ECP5 and ECP5-5G Family Data Sheet** 

**==> picture [455 x 264] intentionally omitted <==**

**----- Start of picture text -----**<br>
Operand Operand Operand<br>A A A<br>Operand Operan d Operand<br>B B B<br>Operand Operand<br>A B<br>x x x m/kloops<br>Single M loops Multiplier Multiplier<br>Multiplier<br>Multiplier x 0 1 k<br>Accumulator<br>(k adds) +<br>Function Implemented in<br>General Purpose DSP<br>m/k<br>accumulate<br>Output<br>Function Implemented in ECP5/ECP5-5G<br>**----- End of picture text -----**<br>


**Figure 2.13. Comparison of General DSP and ECP5/ECP5-5G Approaches** 

## **2.9.2. sysDSP Slice Architecture Features** 

The ECP5/ECP5-5G sysDSP Slice has been significantly enhanced to provide functions needed for advanced processing applications. These enhancements provide improved flexibility and resource utilization. 

The ECP5/ECP5-5G sysDSP Slice supports many functions that include the following: 

- Symmetry support. The primary target application is wireless. 1D Symmetry is useful for many applications that use FIR filters when their coefficients have symmetry or asymmetry characteristics. The main motivation for using 1D symmetry is cost/size optimization. The expected size reduction is up to 2x. 

   - Odd mode – Filter with Odd number of taps 

   - Even mode – Filter with Even number of taps 

   - Two dimensional (2D) symmetry mode – supports 2D filters for mainly video applications 

- Dual-multiplier architecture. Lower accumulator overhead to half and the latency to half compared to single multiplier architecture 

- Fully cascadable DSP across slices. Support for symmetric, asymmetric and non-symmetric filters. 

- Multiply (one 18 x 36, two 18 x 18 or four 9 x 9 Multiplies per Slice) 

- Multiply (36 x 36 by cascading across two sysDSP slices) 

- Multiply Accumulate (supports one 18 x 36 multiplier result accumulation or two 18 x 18 multiplier result accumulation) 

- Two Multiplies feeding one Accumulate per cycle for increased processing with lower latency (two 18 x 18 Multiplies feed into an accumulator that can accumulate up to 52 bits) 

- Pipeline registers 

- 1D Symmetry support. The coefficients of FIR filters have symmetry or negative symmetry characteristics. 

   - Odd mode – Filter with Odd number of taps 

   - Even mode – Filter with Even number of taps 

© 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02012-2.2 

27 

**ECP5 and ECP5-5G Family Data Sheet** 

- 2D Symmetry support. The coefficients of 2D FIR filters have symmetry or negative symmetry characteristics. 

   - 3*3 and 3*5 – Internal DSP Slice support 

   - 5*5 and larger size 2D blocks – Semi internal DSP Slice support 

- Flexible saturation and rounding options to satisfy a diverse set of applications situations 

- Flexible cascading across DSP slices 

   - Minimizes fabric use for common DSP and ALU functions 

   - Enables implementation of FIR Filter or similar structures using dedicated sysDSP slice resources only 

   - Provides matching pipeline registers 

   - Can be configured to continue cascading from one row of sysDSP slices to another for longer cascade chains 

- Flexible and Powerful Arithmetic Logic Unit (ALU) Supports: 

   - Dynamically selectable ALU OPCODE 

   - Ternary arithmetic (addition/subtraction of three inputs) 

   - Bit-wise two-input logic operations (AND, OR, NAND, NOR, XOR and XNOR) 

   - Eight flexible and programmable ALU flags that can be used for multiple pattern detection scenarios, such as, overflow, underflow and convergent rounding. 

   - Flexible cascading across slices to get larger functions 

- RTL Synthesis friendly synchronous reset on all registers, while still supporting asynchronous reset for legacy users 

- Dynamic MUX selection to allow Time Division Multiplexing (TDM) of resources for applications that require processor-like flexibility that enables different functions for each clock cycle 

For most cases, as shown in Figure 2.14, the ECP5/ECP5-5G sysDSP slice is backwards-compatible with the LatticeECP2™ and LatticeECP3™ sysDSP block, such that, legacy applications can be targeted to the ECP5/ ECP5-5G sysDSP slice. Figure 2.14 shows the diagram of sysDSP, and Figure 2.15 shows the detailed diagram. 

© 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

28 

FPGA-DS-02012-2.2 

**ECP5 and ECP5-5G Family Data Sheet** 

**==> picture [443 x 364] intentionally omitted <==**

**----- Start of picture text -----**<br>
SLICE 0 SLICE 1<br>CIN[53:0] (hardwired COUT[53:0] (hardwired<br>cascade from left DSP) AUUGOUUU cascade to right DSP)<br>Accumulator/ALU (54) Accumulator/ALU (54)<br>ALU24 ALU24 ALU24 ALU24<br>SS SS<br>Flags[7:0]<br>PR0 (36) PR1 (36) PR2 (36) =) PR3 (36)<br>CLK[3:0]<br>CE[3:0] == 9x9 9x9 9x9 9x9 9x9 9x9 9x9 9x9 SIGNEDA[3:0]<br>SIGNEDB[3:0]<br>RST[3:0]<br>Mult18-0 Mult18-1 Mult18-2 Mult18-1 SOURCEA[3:0]<br>SOURCEB[3:0]<br>DYNOP0[10:0], 36x36 (Mult36) GSR<br>DYNOP1[10:0]SRIA[17:0] 1818 In Reg A 0 In Reg A 1 CascA0 In Reg A 0 In Reg A 1 CascA1 1818 SROA[17:0]<br>SRIB[17:0] In Reg B 0 In Reg B 1 In Reg B 0 In Reg B 1 SROB[17:0]<br>Hardwired from DSP<br>Block on Left 9+/-9 9+/-9 9+/-9 9+/-9 9+/-9 9+/-9 9+/-9 9+/-9 To DSP<br>Block on<br>18+/-18 18+/-18 18+/-18 18+/-18 Right and to<br>Ss<br>CIB Outputs<br>tf 7 i tf<br>Figure 2.14. Simplified sysDSP Slice Block Diagram<br>MUP0[17:0] MUP0[35:18] MUP1[17:0] MUP1[35:18] MUP2[17:0] MUP2[35:18] MUP3[17:0] MUP3[35:18]<br>OutA0 (18) OutB0 (18) OutA1 (18) OutB1 (18) OutA2 (18) OutB2 (18) OutA3 (18) OutB3 (18)<br>One of these<br>One of these<br>One of these<br>C0[53:0] MUA0[17:0] MUB0[17:0] MUA1[17:0] MUB1[17:0] MUA2[17:0] MUB2[17:0] MUA3[17:0] MUB3[17:0] C0[53:0]<br>**----- End of picture text -----**<br>


© 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02012-2.2 

29 

**ECP5 and ECP5-5G Family Data Sheet** 

**==> picture [456 x 587] intentionally omitted <==**

**----- Start of picture text -----**<br>
MUIA0 MUIB0 OPCODE_PA MUIA1 MUIB1<br>INT_A INT_B<br>IR<br>INT_B SRIBK_PA<br>IR<br>IR<br>INT_A<br>IR  IR<br>DSP<br>+/-= +/- PreAdder<br>Logic<br>C OPA0 DYNOP OPA1<br>SROA<br>SRIA<br>IR  IR  IR<br>IR  IR<br>SRIB<br>SROB<br>MULTA MULTB<br>IR  IR<br>PR PR PR<br>A ALU B ALU<br>0<br>0<br>Shift 18L<br>AMUX BMUX<br>C_ALU R= A ± B ± C<br>COUT<br>CIN R = Logic (B, C)<br>ALU<br>=<br>=<br>OR OR FR OR<br>DSP<br>Core<br>Logic<br>MUOP0 R FLAGS MUOP1<br>DSP SLICE<br>CMUX<br>**----- End of picture text -----**<br>


**Figure 2.15. Detailed sysDSP Slice Diagram** 

© 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

30 

FPGA-DS-02012-2.2 

**ECP5 and ECP5-5G Family Data Sheet** 

In Figure 2.15, note that A_ALU, B_ALU, and C_ALU are internal signals generated by combining bits from AA, AB, BA BB and C inputs. For further information, refer to ECP5 and ECP5-5G sysDSP Usage Guide (FPGA-TN-02205). The ECP5/ECP5-5G sysDSP block supports the following basic elements. 

- MULT (Multiply) 

- MAC (Multiply, Accumulate) 

- MULTADDSUB (Multiply, Addition/Subtraction) 

- MULTADDSUBSUM (Multiply, Addition/Subtraction, Summation) 

Table 2.7 shows the capabilities of each of the ECP5/ECP5-5G slices versus the above functions. 

**Table 2.7. Maximum Number of Elements in a Slice** 

|**Width of Multiply**|**x9**|**x18**|**x36**|
|---|---|---|---|
|MULT|4|2|1/2|
|MAC|1|1|—|
|MULTADDSUB|2|1|—|
|MULTADDSUBSUM|*|*|—|



> ***Note** : Two slices are required for two m9x9addsubsum, and two slices are required for one m18x18addsubsum. 

Some options are available in the four elements. The input register in all the elements can be directly loaded or can be loaded as a shift register from previous operand registers. By selecting _dynamic operation,_ the following operations are possible: 

- In the Add/Sub option the Accumulator can be switched between addition and subtraction on every cycle. 

- The loading of operands can switch between parallel and serial operations. 

For further information, refer to ECP5 and ECP5-5G sysDSP Usage Guide (FPGA-TN-02205). 

## **2.10. Programmable I/O Cells** 

The programmable logic associated with an I/O is called a PIO. The individual PIO are connected to their respective sysI/O buffers and pads. On the ECP5/ECP5-5G devices, the Programmable I/O cells (PIC) are assembled into groups of four PIO cells called a Programmable I/O Cell or PIC. The PICs are placed on all four sides of the device. 

On all the ECP5/ECP5-5G devices, two adjacent PIOs can be combined to provide a complementary output driver pair. All PIO pairs can implement differential receivers. Half of the PIO pairs on the left and right edges of these devices can be configured as true LVDS transmit pairs. 

© 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02012-2.2 

31 

**ECP5 and ECP5-5G Family Data Sheet** 

**==> picture [320 x 598] intentionally omitted <==**

**----- Start of picture text -----**<br>
1 PIC<br>PIO A<br>Input<br>Register<br>Block<br>-_ <<br>Output and<br>Tristate<br>Pin A<br>Register<br>Block<br>is.<br>PIO B<br>ima Input<br>Register<br>Block<br>Output and<br>Tristate<br>Pin B<br>Register<br>Input Output<br>Block<br>Gearbox Gearbox<br>1oo eee<br>Core<br>Logic / PIO C<br>Routing Input<br>Register<br>Block<br>Output and<br>Tristate<br>Pin C<br>Register<br>Block<br>i | ea<br>PIO D<br>| ae. Input<br>Register<br>Block<br>Output and<br>| Tristate<br>Pin D<br>Register<br>Block<br>| Hs<br>Figure 2.16. Group of Four Programmable I/O Cells on Left/Right Sides<br>**----- End of picture text -----**<br>


© 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

32 

FPGA-DS-02012-2.2 

**ECP5 and ECP5-5G Family Data Sheet** 

## **2.11. PIO** 

The PIO contains three blocks: an input register block, output register block, and tristate register block. These blocks contain registers for operating in a variety of modes along with the necessary clock and selection logic. 

## **2.11.1. Input Register Block** 

The input register blocks for the PIOs on all edges contain delay elements and registers that can be used to condition high-speed interface signals before they are passed to the device core. In addition, the input register blocks for the PIOs on the left and right edges include built-in FIFO logic to interface to DDR and LPDDR memory. 

The Input register block on the right and left sides includes gearing logic and registers to implement IDDRX1 and IDDRX2 functions. With two PICs sharing the DDR register path, it can also implement IDDRX71 function used for 7:1 LVDS interfaces. It uses three sets of registers to shift, update, and transfer to implement gearing and the clock domain transfer. The first stage registers samples the high-speed input data by the high-speed edge clock on its rising and falling edges. The second stage registers perform data alignment based on the control signals. The third stage pipeline registers pass the data to the device core synchronized to the low-speed system clock. The top side of the device supports IDDRX1 gearing function. For more information on gearing function, refer to ECP5 and ECP5-5G High-Speed I/O Interface (FPGA-TN-02035). 

Figure 2.17 shows the input register block for the PIOs on the top edge. 

**==> picture [442 x 111] intentionally omitted <==**

**----- Start of picture text -----**<br>
INCK<br>D Programmable INFF<br>Delay Cell<br>INFF Q<br>SCLK IDDRX1 Q[1:0]<br>RST<br>**----- End of picture text -----**<br>


**Figure 2.17. Input Register Block for PIO on Top Side of the Device** 

Figure 2.18 shows the input register block for the PIOs located on the left and right edges. 

**==> picture [464 x 159] intentionally omitted <==**

**----- Start of picture text -----**<br>
INCK<br>Programmable INFF<br>D Delay Cell<br>INFF Q<br>Generic<br>IDDRX1<br>FIFO IDDRX2 Q[1:0]/<br>Delayed DQS ECLK IDDRX71* Q[3:0]/<br>Q[6:0]*<br>Memory<br>ECLK<br>IDDRX2<br>SCLK<br>RST<br>ALIGNWD<br>**----- End of picture text -----**<br>


*For 7:1 LVDS interface only. It is required to use PIO pair pins (PIOA/B or PIOC/D). 

**Figure 2.18. Input Register Block for PIO on Left and Right Side of the Device** 

© 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02012-2.2 

33 

**ECP5 and ECP5-5G Family Data Sheet** 

## **2.11.1.1. Input FIFO** 

The ECP5/ECP5-5G PIO has dedicated input FIFO per single-ended pin for input data register for DDR Memory interfaces. The FIFO resides before the gearing logic. It transfers data from DQS domain to continuous ECLK domain. On the Write side of the FIFO, it is clocked by DQS clock which is the delayed version of the DQS Strobe signal from DDR memory. On the Read side of FIFO, it is clocked by ECLK. ECLK may be any high speed clock with identical frequency as DQS (the frequency of the memory chip). Each DQS group has one FIFO control block. It distributes FIFO read/write pointer to every PIC in same DQS group. DQS Grouping and DQS Control Block is described in DDR Memory Support section. 

**Table 2.8. Input Block Port Description** 

|**Name**|**Type**|**Description**|
|---|---|---|
|D|Input|High Speed Data Input|
|Q[1:0]/Q[3:0]/Q[6:0]|Output|Low Speed Data to the device core|
|RST|Input|Reset to the Output Block|
|SCLK|Input|Slow Speed System Clock|
|ECLK|Input|High Speed Edge Clock|
|DQS|Input|Clock from DQS control Block used to clock DDR memory data|
|ALIGNWD|Input|Data Alignment signal from device core.|



## **2.11.2. Output Register Block** 

The output register block registers signal from the core of the device before they are passed to the sysI/O buffers. 

ECP5/ECP5-5G output data path has output programmable flip flops and output gearing logic. On the left and right sides, the output register block can support 1x, 2x, and 7:1 gearing enabling high speed DDR interfaces and DDR memory interfaces. On the top side, the banks support 1x gearing. ECP5/ECP5-5G output data path diagram is shown in Figure 2.19. The programmable delay cells are also available in the output data path. 

For detailed description of the output register block modes and usage, refer to ECP5 and ECP5-5G High-Speed I/O Interface (FPGA-TN-02035). 

**==> picture [435 x 112] intentionally omitted <==**

**----- Start of picture text -----**<br>
Programmable<br>D Delay Cell Q<br>OUTFF<br>RST<br>SCLK Generic<br>ODDRX1<br>D[1:0]<br>**----- End of picture text -----**<br>


**Figure 2.19. Output Register Block on Top Side** 

© 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

34 

FPGA-DS-02012-2.2 

**ECP5 and ECP5-5G Family** 

**Data Sheet** 

**==> picture [472 x 200] intentionally omitted <==**

**----- Start of picture text -----**<br>
Programmable<br>D Delay Cell<br>Q<br>OUTFF<br>RST Generic<br>SCLK ODDRX1/<br>ECLK ODDRX2/<br>DQSW ODDR71*<br>DQSW270<br>Memory<br>D[1:0]/ ODDRX2<br>D[3:0]/ OSHX2<br>D[6:0]* a) Te)<br>**----- End of picture text -----**<br>


*For 7:1 LVDS interface only.  It is required to use PIO pair pins PIOA/B. 

**Figure 2.20. Output Register Block on Left and Right Sides** 

**Table 2.9. Output Block Port Description** 

|**Name**|**Type**|**Description**|
|---|---|---|
|Q|Output|High Speed Data Output|
|D|Input|Data from core to output SDR register|
|D[1:0]/D[3:0]/ D[6:0]|Input|Low Speed Data from device core to output DDR register|
|RST|Input|Reset to the Output Block|
|SCLK|Input|Slow Speed System Clock|
|ECLK|Input|High Speed Edge Clock|
|DQSW|Input|Clock from DQS control Block used to generate DDR memory DQS output|
|DQSW270|Input|Clock from DQS control Block used to generate DDR memory DQ output|



## **2.12. Tristate Register Block** 

The tristate register block registers tristate control signals from the core of the device before they are passed to the sysI/O buffers. The block contains a register for SDR operation. In SDR, TD input feeds one of the flip-flops that then feeds the output. In DDR, operation used mainly for DDR memory interface can be implemented on the left and right sides of the device. Here two inputs feed the tristate registers clocked by both ECLK and SCLK. 

Figure 2.21 and Figure 2.22 show the Tristate Register Block functions on the device. For detailed description of the tristate register block modes and usage, refer to ECP5 and ECP5-5G High-Speed I/O Interface (FPGA-TN-02035). 

**==> picture [284 x 62] intentionally omitted <==**

**----- Start of picture text -----**<br>
TQ<br>TD<br>RST TSFF<br>SCLK =—)-<br>**----- End of picture text -----**<br>


**Figure 2.21. Tristate Register Block on Top Side** 

© 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02012-2.2 

35 

**ECP5 and ECP5-5G Family Data Sheet** 

**==> picture [336 x 246] intentionally omitted <==**

**----- Start of picture text -----**<br>
TQ<br>TD<br>TSFF<br>RST<br>SCLK<br>ECLK<br>THSX2<br>DQSW —______»<br>DQSW270 ————><br>T[1:0] ———><br>**----- End of picture text -----**<br>


**Figure 2.22. Tristate Register Block on Left and Right Sides** 

**Table 2.10. Tristate Block Port Description** 

|**Name**|**Type**|**Description**|
|---|---|---|
|TD|Input|Tristate Input to Tristate SDR Register|
|RST|Input|Reset to the Tristate Block|
|TD[1:0]|Input|Tristate input to TSHX2 function|
|SCLK|Input|Slow Speed System Clock|
|ECLK|Input|High Speed Edge Clock|
|DQSW|Input|Clock from DQS control Block used to generate DDR memory DQS output|
|DQSW270|Input|Clock from DQS control Block used to generate DDR memory DQ output|
|TQ|Output|Output of the Tristate block|



## **2.13. DDR Memory Support** 

## **2.13.1. DQS Grouping for DDR Memory** 

Certain PICs have additional circuitry to allow the implementation of high-speed source synchronous and DDR2, DDR3, LPDDR2 or LPDDR3 memory interfaces. The support varies by the edge of the device as detailed below. 

The left and right sides of the PIC have fully functional elements supporting DDR2, DDR3, LPDDR2, or LPDDR3 memory interfaces. Every 16 PIOs on the left and right sides are grouped into one DQS group, as shown in Figure 2.23. Within each DQS group, there are two pre-placed pins for DQS and DQS# signals. The rest of the pins in the DQS group can be used as DQ signals and DM signal. The number of pins in each DQS group bonded out is package dependent. DQS groups with less than 11 pins bonded out can only be used for LPDDR2/3 Command/ Address busses. In DQS groups with more than 11 pins bonded out, up to two pre-defined pins are assigned to be used as _virtual_ VCCIO, by driving these pins to HIGH, with the user connecting these pins to VCCIO power supply. These connections create _soft_ connections to VCCIO thru these output pins, and make better connections on VCCIO to help to reduce SSO noise. For details, refer to ECP5 and ECP5-5G High-Speed I/O Interface (FPGA-TN-02035). 

© 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

36 

FPGA-DS-02012-2.2 

**ECP5 and ECP5-5G Family Data Sheet** 

||PIO A||sysI/O Buffer|sysI/O Buffer|||Pad A (T)|
|---|---|---|---|---|---|---|---|
|||||||||
||PIO B||sysI/O Buffer||||Pad B (C)|
|||||||||
|||||||||
||PIO C||sysI/O Buffer||||Pad C|
|||||||||
||PIO D||sysI/O Buffer||||Pad D|
|||||||||
|||||||||
||PIO A||sysI/O Buffer||||Pad A (T)|
|||||||||
||PIO B||sysI/O Buffer||||Pad B (C)|
|||||||||
|||||||||
||PIO C||sysI/O Buffer||||Pad C|
|||||||||
||PIO D||sysI/O Buffer||||Pad D|
|||||||||
|DQS|DQSBUF|~~|~~|~~Delay~~|||||
|||||||||
||PIO A||sysI/O Buffer||||Pad A (T)|
|||||||||
||PIO B||sysI/O Buffer||||Pad B (C)|
|||||||||
|||||||||
||PIO C||sysI/O Buffer||||Pad C|
|||||||||
||PIO D||sysI/O Buffer||||Pad D|
|||||||||
|||||||||
||PIO A||sysI/O Buffer||||Pad A (T)|
|||||||||
||PIO B||sysI/O Buffer||||Pad B (C)|
|||||||||
|||||||||
||PIO C||sysI/O Buffer||||Pad C|
|||||||||
||PIO D||sysI/O Buffer||||Pad D|



**Figure 2.23. DQS Grouping on the Left and Right Edges** 

## **2.13.2. DLL Calibrated DQS Delay and Control Block (DQSBUF)** 

To support DDR memory interfaces (DDR2/3, LPDDR2/3), the DQS strobe signal from the memory must be used to capture the data (DQ) in the PIC registers during memory reads. This signal is output from the DDR memory device aligned to data transitions and must be time shifted before it can be used to capture data in the PIC. This time shifted is achieved by using DQSDEL programmable delay line in the DQS Delay Block (DQS read circuit). The DQSDEL is implemented as a slave delay line and works in conjunction with a master DDRDLL. 

This block also includes slave delay line to generate delayed clocks used in the write side to generate DQ and DQS with correct phases within one DQS group. There is a third delay line inside this block used to provide write leveling feature for DDR write if needed. 

Each of the read and write side delays can be dynamically shifted using margin control signals that can be controlled by the core logic. 

FIFO Control Block shown in Figure 2.24 generates the Read and Write Pointers for the FIFO block inside the Input Register Block. These pointers are generated to control the DQS to ECLK domain crossing using the FIFO module. 

© 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02012-2.2 

37 

**ECP5 and ECP5-5G Family Data Sheet** 

**==> picture [440 x 240] intentionally omitted <==**

**----- Start of picture text -----**<br>
DQS Preamble/Postamble Management BURSTDET<br>&<br>READ[1:0] Burst Detect DATAVALID<br>a<br>READCLKSEL[1:0]<br>ECLK FIFO Control & Datavalid RDPNTR[2:0]<br>SCLK Generation WRPNTR[2:0]<br>[od<br>DQSDEL<br>(90 Deg. Delay Code<br>from DDRDLL)<br>Read Side Slave Delay with DQSR90 (Read Side)<br>RDLOADN, RDMOVE, RDDIRECTION Dynamic Margin Control<br>(Read Side Dynamic Margin Control) [od<br>DQSW (Write Side)<br>WRLOADN, WRMOVE, WRDIRECTION DQSW270 (Write Side)<br>Write Side Slave Delay with<br>(Write Side Dynamic Margin Control)<br>Dynamic Margin Control RDCFLAG<br>[od<br>WRCFLAG<br>PAUSE<br>DYNDELAY[7:0] Write<br>(Write Leveling delay) Leveling<br>a<br>**----- End of picture text -----**<br>


**Figure 2.24. DQS Control and Delay Block (DQSBUF)** 

**Table 2.11. DQSBUF Port List Description** 

|**Name**|**Type**|**Description**|
|---|---|---|
|DQS|Input|DDR memory DQS strobe|
|READ[1:0]|Input|Read Input from DDR Controller|
|READCLKSEL[1:0]|Input|Read pulse selection|
|SCLK|Input|Slow System Clock|
|ECLK|Input|High Speed Edge Clock (same frequency as DDR memory)|
|DQSDEL|Input|90° Delay Code from DDRDLL|
|RDLOADN, RDMOVE, RDDIRECTION|Input|Dynamic Margin Control ports for Read delay|
|WRLOADN, WRMOVE, WRDIRECTION|Input|Dynamic Margin Control ports for Write delay|
|PAUSE|Input|Used by DDR Controller to Pause write side signals during<br>DDRDLL Code update or Write Leveling|
|DYNDELAY[7:0]|Input|Dynamic Write Leveling Delay Control|
|DQSR90|Output|90° delay DQS used for Read|
|DQSW270|Output|90° delay clock used for DQ Write|
|DQSW|Output|Clock used for DQS Write|
|RDPNTR[2:0]|Output|Read Pointer for IFIFO module|
|WRPNTR[2:0]|Output|Write Pointer for IFIFO module|
|DATAVALID|Output|Signal indicating start of valid data|
|BURSTDET|Output|Burst Detect indicator|
|RDFLAG|Output|Read Dynamic Margin Control output to indicate max value|
|WRFLAG|Output|Write Dynamic Margin Control output to indicate max value|



© 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

38 

FPGA-DS-02012-2.2 

**ECP5 and ECP5-5G Family Data Sheet** 

## **2.14. sysI/O Buffer** 

Each I/O is associated with a flexible buffer referred to as a sysI/O buffer. These buffers are arranged around the periphery of the device in groups referred to as banks. The sysI/O buffers allow you to implement the wide variety of standards that are found in today’s systems including LVDS, HSUL, BLVDS, SSTL Class I and II, LVCMOS, LVTTL, LVPECL, and MIPI. 

## **2.14.1. sysI/O Buffer Banks** 

ECP5/ECP5-5G devices have seven sysI/O buffer banks, two banks per side at Top, Left and Right, plus one at the bottom left side. The bottom left side bank (Bank 8) is a shared I/O bank. The I/O in that bank contains both dedicated and shared I/O for sysConfig function. When a shared pin is not used for configuration, it is available as a user I/O. For LFE5-85 devices, there is an additional I/O bank (Bank 4) that is not available in other device in the family. 

In ECP5/ECP5-5G devices, the Left and Right sides are tailored to support high performance interfaces, such as DDR2, DDR3, LPDDR2, LPDDR3 and other high speed source synchronous standards. The banks on the Left and Right sides of the devices feature LVDS input and output buffers, data-width gearing, and DQSBUF block to support DDR2/3 and LPDDR2/3 interfaces. The I/O on the top and bottom banks do not have LVDS input and output buffer, and gearing logic, but can use LVCMOS to emulate most of differential output signaling. 

Each sysI/O bank has its own I/O supply voltage (VCCIO). In addition, the banks on the Left and Right sides of the device, have voltage reference input (shared I/O pin), VREF1 per bank, which allow it to be completely independent of each other. The VREF voltage is used to set the threshold for the referenced input buffers, such as SSTL. Figure 2.25 shows the seven banks and their associated supplies. 

In ECP5/ECP5-5G devices, single-ended output buffers and ratioed input buffers (LVTTL and LVCMOS) are powered using VCCIO. LVTTL, LVCMOS33, LVCMOS25, and LVCMOS12 can also be set as fixed threshold inputs independent of VCCIO. 

**==> picture [333 x 324] intentionally omitted <==**

**----- Start of picture text -----**<br>
TOP<br>Bank 0 Bank 1<br>ls<br>SERDES<br>_—<br>BOTTOM<br>*Note: Only 85K device has this bank.<br>Bank 8<br>CONFIG BANK Bank 4*<br>VREF1(7) GND<br>VCCIO7 V<br>CCIO2<br>GND V REF1(2)<br>VREF1(6) GND<br>VCCIO6 V CCIO3<br>GND V REF1(3)<br>LEFT<br>Bank 7<br>Bank 6<br>Bank 2<br>Bank 3<br>RIGHT<br>GND VCCIO0 GND VCCIO1<br>VREF1(0)V VREF1(1)V<br>VCCIO8 GND VCCIO4 GND<br>**----- End of picture text -----**<br>


**Figure 2.25. ECP5/ECP5-5G Device Family Banks** 

© 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02012-2.2 

39 

**ECP5 and ECP5-5G Family Data Sheet** 

ECP5/ECP5-5G devices contain two types of sysI/O buffer pairs: 

- Top (Bank 0 and Bank 1) and Bottom (Bank 8 and Bank 4) sysI/O Buffer Pairs (Single-Ended Only) 

The sysI/O buffers in the Banks at top and bottom of the device consist of ratioed single-ended output drivers and single-ended input buffers. The I/O in these banks are not usually used as a pair, except when used as emulated differential output pair. They are used as individual I/O and be configured as different I/O modes, as long as they are compatible with the VCCIO voltage in the bank. When used as emulated differential outputs, the pair can be used together. 

The top and bottom side I/O also support hot socketing. They support I/O standards from 3.3 V to 1.2 V. They are ideal for general purpose I/O, or as ADDR/CMD bus for DDR2/DDR3 applications, or for used as emulated differential signaling. 

Bank 4 I/O only exists in the LFE5-85 device. 

Bank 8 is a bottom bank that shares with sysConfig I/O. During configuration, these I/O are used for programming the device. Once the configuration is completed, these I/O can be released and you can use these I/O for functional signals in his design. 

The top and bottom side pads can be identified by the Lattice Diamond tool. 

- Left and Right (Bank 2, Bank 3, Bank 6, and Bank 7) sysI/O Buffer Pairs (50% Differential and 100% Single-Ended Outputs) 

The sysI/O buffer pairs in the left and right banks of the device consist of two single-ended output drivers, two single-ended input buffers (both ratioed and referenced) and half of the sysI/O buffer pairs (PIOA/B pairs) also has a high-speed differential output driver. One of the referenced input buffers can also be configured as a differential input. In these banks the two pads in the pair are described as _true_ and _comp_ , where the true pad is associated with the positive side of the differential I/O, and the comp (complementary) pad is associated with the negative side of the differential I/O. 

In addition, programmable on-chip input termination (parallel or differential, static or dynamic) is supported on these sides, which is required for DDR3 interface. However, there is no support for hot-socketing for the I/O pins located on the left and right side of the device as the PCI clamp is always enabled on these pins. 

LVDS differential output drivers are available on 50% of the buffer pairs on the left and right banks. 

## **2.14.2. Typical sysI/O I/O Behavior during Power-up** 

The internal Power-On-Reset (POR) signal is deactivated when VCC, VCCIO8 and VCCAUX have reached satisfactory levels. After the POR signal is deactivated, the FPGA core logic becomes active. It is your responsibility to ensure that all other VCCIO banks are active with valid input logic levels to properly control the output logic states of all the I/O banks that are critical to the application. For more information about controlling the output logic state with valid input logic levels during power-up in ECP5/ECP5-5G devices, see the list of technical documentation in Supplemental Information section. 

The VCC and VCCAUX supply the power to the FPGA core fabric, whereas the VCCIO supplies power to the I/O buffers. In order to simplify system design while providing consistent and predictable I/O behavior, it is recommended that the I/O buffers be powered-up prior to the FPGA core fabric. VCCIO supplies should be powered-up before or together with the VCC and VCCAUX supplies. 

## **2.14.3. Supported sysI/O Standards** 

The ECP5/ECP5-5G sysI/O buffer supports both single-ended and differential standards. Single-ended standards can be further subdivided into LVCMOS, LVTTL and other standards. The buffers support the LVTTL, LVCMOS 1.2 V, 1.5 V, 1.8V, 2.5 V and 3.3 V standards. In the LVCMOS and LVTTL modes, the buffer has individual configuration options for drive strength, slew rates, bus maintenance (weak pull-up or weak pull-down) and open drain. Other single-ended standards supported include SSTL and HSUL. Differential standards supported include LVDS, differential SSTL and differential HSUL. For further information on utilizing the sysI/O buffer to support a variety of standards, refer to ECP5 and ECP55G sysI/O Usage Guide (FPGA-TN-02032). 

© 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

40 

FPGA-DS-02012-2.2 

**ECP5 and ECP5-5G Family Data Sheet** 

## **2.14.4. On-Chip Programmab** l **e Termination** 

The ECP5/ECP5-5G devices support a variety of programmable on-chip terminations options, including: 

- Dynamically switchable Single-Ended Termination with programmable resistor values of 50 Ω, 75 Ω, or 150 Ω. 

- Common mode termination of 100 Ω for differential inputs. 

**==> picture [430 x 141] intentionally omitted <==**

**----- Start of picture text -----**<br>
V CCIO Zo = 50<br>TERM<br>Zo = 50 Ω, 75 Ω, or 150 Ω<br>control<br>to V CCIO  /2<br>Zo<br>Zo +<br>Zo + 2Zo -<br>- Zo<br>VREF<br>OFF-chip ON-chip OFF-chip ON-chip<br>Parallel Single-Ended Input Differential Input<br>**----- End of picture text -----**<br>


**Figure 2.26. On-Chip Termination** 

See Table 2.12 for termination options for input modes. 

**Table 2.12. On-Chip Termination Options for Input Modes** 

|**IO_TYPE**|**Terminate to VCCIO/2***|**Differential Termination Resistor***|
|---|---|---|
|LVDS25|—|100|
|BLVDS25|—|100|
|MLVDS|—|100|
|LVPECL33|—|100|
|subLVDS|—|100|
|SLVS|—|100|
|HSUL12|50, 75, 150|—|
|HSUL12D|—|100|
|SSTL135_I / II|50, 75, 150|—|
|SSTL135D_I / II|—|100|
|SSTL15_I / II|50, 75, 150|—|
|SSTL15D_I / II|—|100|
|SSTL18_I / II|50, 75, 150|—|
|SSTL18D_I / II|—|100|



*** Notes** : 

- TERMINATE to VCCIO/2 (Single-Ended) and DIFFRENTIAL TERMINATION RESISTOR when turned on can only have one setting per bank. Only left and right banks have this feature. 

- Use of TERMINATE to VCCIO/2 and DIFFRENTIAL TERMINATION RESISTOR are mutually exclusive in an I/O bank. On-chip termination tolerance ±20%. 

Refer to ECP5 and ECP5-5G sysI/O Usage Guide (FPGA-TN-02032) for on-chip termination usage and value ranges. 

© 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02012-2.2 

41 

**ECP5 and ECP5-5G Family Data Sheet** 

## **2.14.5. Hot Socketing** 

ECP5/ECP5-5G devices have been carefully designed to ensure predictable behavior during power-up and power-down. During power-up and power-down sequences, the I/O remain in tristate until the power supply voltage is high enough to ensure reliable operation. In addition, leakage into I/O pins is controlled within specified limits. See the Hot Socketing Specifications section. 

## **2.15. SERDES and Physical Coding Sublayer** 

LFE5UM/LFE5UM5G devices feature up to four channels of embedded SERDES/PCS arranged in dual-channel blocks at the bottom of the devices. Each channel supports up to 3.2 Gb/s (ECP5), or up to 5 Gb/s (ECP5-5G) data rate. Figure 2.27 shows the position of the dual blocks for the LFE5-85. Table 2.13 shows the location of available SERDES Duals for all devices. The LFE5UM/LFE5UM5G SERDES/PCS supports a range of popular serial protocols, including: 

- PCI Express Gen1 and Gen2 (2.5 Gb/s) on ECP5UM; Gen 1, Gen2 (2.5 Gb/s and 5 Gb/s) on ECP5-5G 

- Ethernet (XAUI, GbE – 1000 Base CS/SX/LX and SGMII) 

- SMPTE SDI (3G-SDI, HD-SDI, SD-SDI) 

- CPRI (E.6.LV: 614.4 Mb/s, E.12.LV: 1228.8 Mb/s, E.24.LV: 2457.6 Mb/s, E.30.LV: 3072 Mb/s), also E.48.LV2:4915 Mb/s in ECP5-5G 

- JESD204A/B – ADC and DAC converter interface: 312.5 Mb/s to 3.125 Gb/s (ECP5) / 5 Gb/s (ECP5-5G) 

Each dual contains two dedicated SERDES for high speed, full duplex serial data transfer. Each dual also has a PCS block that interfaces to the SERDES channels and contains protocol specific digital logic to support the standards listed above. The PCS block also contains interface logic to the FPGA fabric. All PCS logic for dedicated protocol support can also be bypassed to allow raw 8-bit or 10-bit interfaces to the FPGA fabric. 

Even though the SERDES/PCS blocks are arranged in duals, multiple baud rates can be supported within a dual with the use of dedicated, per channel /1, /2 and /11 rate dividers. Additionally, two duals can be arranged together to form x4 channel link. 

ECP5UM devices and ECP5-5G devices are pin-to-pin compatible. But, the ECP5UM devices require 1.1 V on VCCA, VCCHRX and VCCHTX supplies. ECP5-5G devices require 1.2 V on these supplies. When designing either family device with migration in mind, these supplies need to be connected such that it is possible to adjust the voltage level on these supplies. 

When a SERDES Dual in a 2-Dual device is not used, the power VCCA power supply for that Dual should be connected. It is advised to connect the VCCA of unused channel to VCC core power supply if you do not use the Dual at all, or it should be connected to a different regulated supply, if that Dual may be used in the future. 

For an unused channel in a Dual, it is advised to connect the VCCHTX to VCCA, and you can leave VCCHRX unconnected. For information on how to use the SERDES/PCS blocks to support specific protocols, as well on how to combine multiple protocols and baud rates within a device, refer to ECP5 and ECP5-5G SERDES/PCS Usage Guide ( FPGA-TN02206). 

© 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

42 

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**ECP5 and ECP5-5G Family Data Sheet** 

**==> picture [487 x 552] intentionally omitted <==**

**----- Start of picture text -----**<br>
|||||||
|---|---|---|---|---|---|
|sysI/O Bank 0|sysI/O Bank 1|
|SERDES/|SERDES/|
|PCS|PCS|
|Dual 0|Dual 1|
|sysI/O Bank 8|sysI/O Bank 4|
|||||
|Figure 2.27. SERDES/PCS Duals (LFE5UM/LFE5UM5G-85)|
|Table 2.13. LFE5UM/LFE5UM5G SERDES Standard Support|
|Standard|Data Rate (Mb/s)|Number of General/Link Width|Encoding Style|
|PCI Express 1.1 and 2.0|2500|x1, x2, x4|8b10b|
|2.02|5000|[2]|x1, x2|8b10b|
|I|Gigabit Ethernet|———————|1250|x1|8b10b|
|SGMII|1250|x1|8b10b|
|2500|x1|8b10b|
|XAUI|3125|x4|8b10b|
|ER|——|
|CPRI-1|614.4|x1, x2, x4|8b10b|
|CPRI-2|1228.8|
|CPRI-3|2457.6|
|x1|8b10b|
|CPRI-4|3072.0|
|CPRI-5|4915.2|[2]|
|——|SD-SDI (259M, 344M)|[1]|270|x1|NRZI/Scrambled|
|1483.5|
|HD-SDI (292M)|x1|NRZI/Scrambled|
|1485|
|a|||
|2967|
|x1|NRZI/Scrambled|
|3G-SDI (424M)|2970|
|5000|—|—|
|POF EE|
|JESD204A/B|3125|x1|8b/10b|

**----- End of picture text -----**<br>


**Notes** : 

1. For SD-SDI rate, the SERDES is bypassed and SERDES input signals are directly connected to the FPGA routing. 

2. For ECP5-5G family devices only. 

© 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02012-2.2 

43 

**ECP5 and ECP5-5G Family Data Sheet** 

**Table 2.14. Available SERDES Duals per LFE5UM/LFE5UM5G Devices** 

|**Package**|**LFE5UM/LFE5UM5G-25**|**LFE5UM/LFE5UM5G-45**|**LFE5UM/LFE5UM5G-85**|
|---|---|---|---|
|285 csfBGA|1|1|1|
|381 caBGA|1|2|2|
|554 caBGA|—|2|2|
|756 caBGA|—|—|2|



## **2.15.1. SERDES Block** 

A SERDES receiver channel may receive the serial differential data stream, equalize the signal, perform Clock and Data Recovery (CDR) and de-serialize the data stream before passing the 8- or 10-bit data to the PCS logic. The SERDES transmitter channel may receive the parallel 8- or 10-bit data, serialize the data and transmit the serial bit stream through the differential drivers. Figure 2.28 shows a single-channel SERDES/PCS block. Each SERDES channel provides a recovered clock and a SERDES transmit clock to the PCS block and to the FPGA core logic. 

Each transmit channel, receiver channel, and SERDES PLL shares the same power supply (VCCA). The output and input buffers of each channel have their own independent power supplies (VCCHTX and VCCHRX). 

**==> picture [481 x 178] intentionally omitted <==**

**----- Start of picture text -----**<br>
SERDES PCS FPGA Core<br>Recovered Clock*<br>RX_REFCLK Recovered Clock<br>HDINNHDINP Equalizer Clock/DataRecovery Deserializer1:8/1:10 Polarity Adjust Word Alignment8b/10b Decoder FIFOCTC DownsamFIFO ple Receive Data<br>a Receiver ae [hoe] Bypass [C] Bypass [o] [pter] Bypass op H Receive Clock<br>TX REFCLK TX PLL SERDES Tx Clock<br>(Per Dual)<br>De-emphasisTx Driver Polarity Encoder8b/10b UpsampleFIFO Transmit Data<br>HDOUTP Serializer Adjust<br>HDOUTN 8:1/10:1 Bypass Transmit Clock<br>ee Bypass<br>* 1/8 or 1/10 line rate<br>**----- End of picture text -----**<br>


**Figure 2.28. Simplified Channel Block Diagram for SERDES/PCS Block** 

## **2.15.2. PCS** 

As shown in Figure 2.28, the PCS receives the parallel digital data from the deserializer and selects the polarity, performs word alignment, decodes (8b/10b), provides Clock Tolerance Compensation and transfers the clock domain from the recovered clock to the FPGA clock via the Down Sample FIFO. 

For the transmit channel, the PCS block receives the parallel data from the FPGA core, encodes it with 8b/10b, selects the polarity and passes the 8/10-bit data to the transmit SERDES channel. 

The PCS also provides bypass modes that allow a direct 8-bit or 10-bit interface from the SERDES to the FPGA logic. The PCS interface to the FPGA can also be programmed to run at 1/2 speed for a 16-bit or 20-bit interface to the FPGA logic. Some of the enhancements in LFE5UM/LFE5UM5G SERDES/PCS include: 

- Higher clock/channel granularity: Dual channel architecture provides more clock resource per channel. 

- Enhanced Tx de-emphasis: Programmable pre- and post-cursors improves Tx output signaling 

- Bit-slip function in PCS: Improves logic needed to perform Word Alignment function 

Refer to ECP5 and ECP5-5G SERDES/PCS Usage Guide (FPGA-TN-02206) for more information. 

© 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02012-2.2 

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**ECP5 and ECP5-5G Family Data Sheet** 

## **2.15.3. SERDES Client Interface Bus** 

The SERDES Client Interface (SCI) is an IP interface that allows you to change the configuration thru this interface. This is useful when you need to fine-tune some settings, such as input and output buffer that need to be optimized based on the channel characteristics. It is a simple register configuration interface that allows SERDES/PCS configuration without power cycling the device. 

The Diamond design tools support all modes of the PCS. Most modes are dedicated to applications associated with a specific industry standard data protocol. Other more general purpose modes allow you to define their own operation. With these tools, you can define the mode for each dual in a design. 

Popular standards such as 10 Gb Ethernet, x4 PCI Express and 4x Serial RapidIO can be implemented using IP (available through Lattice), with two duals (Four SERDES channels and PCS) and some additional logic from the core. 

The LFE5UM/LFE5UM5G devices support a wide range of protocols. Within the same dual, the LFE5UM/ LFE5UM5G devices support mixed protocols with semi-independent clocking as long as the required clock frequencies are integer x1, x2, or x11 multiples of each other. Table 2.15 lists the allowable combination of primary and secondary protocol combinations. 

## **2.16. Flexible Dual SERDES Architecture** 

The LFE5UM/LFE5UM5G SERDES architecture is a dual channel-based architecture. For most SERDES settings and standards, the whole dual (consisting of two SERDES channels) is treated as a unit. This helps in silicon area savings, better utilization, higher granularity on clock/SERDES channel and overall lower cost. 

However, for some specific standards, the LFE5UM/LFE5UM5G dual-channel architecture provides flexibility; more than one standard can be supported within the same dual. 

Table 2.15 lists the standards that can be mixed and matched within the same dual. In general, the SERDES standards whose nominal data rates are either the same or a defined subset of each other, can be supported within the same dual. The two Protocol columns of the table define the different combinations of protocols that can be implemented together within a Dual. 

**Table 2.15. LFE5UM/LFE5UM5G Mixed Protocol Support** 

|**Protocol**||**Protocol**|
|---|---|---|
|PCI Express 1.1|with|SGMII|
|PCI Express 1.1|with|Gigabit Ethernet|
|CPRI-3|with|CPRI-2 and CPRI-1|
|3G-SDI|with|HD-SDI and SD-SDI|



There are some restrictions to be aware of when using spread spectrum clocking. When a dual shares a PCI Express x1 channel with a non-PCI Express channel, ensure that the reference clock for the dual is compatible with all protocols within the dual. For example, a PCI Express spread spectrum reference clock is not compatible with most Gigabit Ethernet applications because of tight CTC ppm requirements. 

While the LFE5UM/LFE5UM5G architecture allows the mixing of a PCI Express channel and a Gigabit Ethernet, or SGMII channel within the same dual, using a PCI Express spread spectrum clocking as the transmit reference clock causes a violation of the Gigabit Ethernet, and SGMII transmit jitter specifications. 

For further information on SERDES, refer to ECP5 and ECP5-5G SERDES/PCS Usage Guide (FPGA-TN-02206). 

## **2.17. IEEE 1149.1-Compliant Boundary Scan Testability** 

All ECP5/ECP5-5G devices have boundary scan cells that are accessed through an IEEE 1149.1 compliant Test Access Port (TAP). This allows functional testing of the circuit board on which the device is mounted through a serial scan path that can access all critical logic nodes. Internal registers are linked internally, allowing test data to be shifted in and loaded directly onto test nodes, or test data to be captured and shifted out for verification. The test access port consists of dedicated I/O: TDI, TDO, TCK, and TMS. The test access port uses VCCIO8 for power supply. 

For more information, refer to ECP5 and ECP5-5G sysCONFIG Usage Guide (FPGA-TN-02039). 

© 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02012-2.2 

45 

**ECP5 and ECP5-5G Family Data Sheet** 

## **2.18. Device Configuration** 

All ECP5/ECP5-5G devices contain two ports that can be used for device configuration. The Test Access Port (TAP), which supports bit-wide configuration, and the sysCONFIG port, support dual-byte, byte and serial configuration. The TAP supports both the IEEE Standard 1149.1 Boundary Scan specification and the IEEE Standard 1532 In-System Configuration specification. There are 11 dedicated pins for TAP and sysConfig supports (TDI, TDO, TCK, TMS, CFG[2:0], PROGRAMN, DONE, INITN, and CCLK). The remaining sysCONFIG pins are used as dual function pins. Refer to ECP5 and ECP5-5G sysCONFIG Usage Guide (FPGA-TN-02039) for more information about using the dual-use pins as general purpose I/O. 

There are various ways to configure an ECP5/ECP5-5G device: 

- JTAG 

- Standard Serial Peripheral Interface (SPI) – Interface to boot PROM Support x1, x2, x4 wide SPI memory interfaces. 

- System microprocessor to drive a x8 CPU port SPCM mode 

- System microprocessor to drive a serial slave SPI port (SSPI mode) 

- Slave Serial model (SCM) 

On power-up, the FPGA SRAM is ready to be configured using the selected sysCONFIG port. Once a configuration port is selected, it remains active throughout that configuration cycle. The IEEE 1149.1 port can be activated any time after power-up by sending the appropriate command through the TAP port. 

ECP5/ECP5-5G devices also support the Slave SPI Interface. In this mode, the FPGA behaves like a SPI Flash device (slave mode) with the SPI port of the FPGA to perform read-write operations. 

## **2.18.1. Enhanced Configuration Options** 

ECP5/ECP5-5G devices have enhanced configuration features such as: decryption support, decompression support, TransFR™ I/O and dual-boot and multi-boot image support. 

## **2.18.1.1. TransFR (Transparent Field Reconfiguration)** 

TransFR I/O (TFR) is a unique Lattice technology that allows you to update their logic in the field without interrupting system operation using a single ispVM command. TransFR I/O allows I/O states to be frozen during device configuration. This allows the device to be field updated with a minimum of system disruption and downtime. Refer to Minimizing System Interruption During Configuration Using TransFR Technology (FPGA-TN-02198) for details. 

## **2.18.1.2. Dual-Boot and Multi-Boot Image Support** 

Dual-boot and multi-boot images are supported for applications requiring reliable remote updates of configuration data for the system FPGA. After the system is running with a basic configuration, a new boot image can be downloaded remotely and stored in a separate location in the configuration storage device. Any time after the update the ECP5/ECP5-5G devices can be re-booted from this new configuration file. If there is a problem, such as corrupt data during download or incorrect version number with this new boot image, the ECP5/ECP5-5G device can revert back to the original backup golden configuration and try again. This all can be done without power cycling the system. For more information, refer to ECP5 and ECP5-5G sysCONFIG Usage Guide (FPGA-TN-02039). 

## **2.18.2. Single Event Upset (SEU) Support** 

ECP5/ECP5-5G devices support SEU mitigation with three supporting functions: 

- SED – Soft Error Detect 

- SEC – Soft Error Correction 

- SEI – Soft Error Injection 

ECP5/ECP5-5G devices have dedicated logic to perform Cycle Redundancy Code (CRC) checks. During configuration, the configuration data bitstream can be checked with the CRC logic block. In addition, the ECP5/ECP5-5G device can also be programmed to utilize a Soft Error Detect (SED) mode that checks for soft errors in configuration SRAM. The SED operation can be run in the background during user mode. If a soft error occurs, during user mode (normal operation) the device can be programmed to generate an error signal. 

© 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02012-2.2 

46 

**ECP5 and ECP5-5G Family Data Sheet** 

When an error is detected, and your error handling software determines the error did not create any risk to the system operation, the SEC tool allows the device to be re-configured in the background to correct the affected bit. This operation allows the user functions to continue to operate without stopping the system function. 

Additional SEI tool is also available in the Diamond Software, by creating a frame of data to be programmed into the device in the background with one bit changed, without stopping the user functions on the device. This emulates an SEU situation, allowing you to test and monitor its error handling software. 

For further information on SED support, refer to LatticeECP3, ECP5 and ECP5-5G Soft Error Detection (SED)/Correction (SEC) Usage Guide ( FPGA-TN-02207). 

## **2.18.3. On-Chip Oscillator** 

Every ECP5/ECP5-5G device has an internal CMOS oscillator which is used to derive a Master Clock (MCLK) for configuration. The oscillator and the MCLK run continuously and are available to user logic after configuration is completed. The software default value of the MCLK is nominally 2.4 MHz. Table 2.16 lists all the available MCLK frequencies. When a different Master Clock is selected during the design process, the following sequence takes place: 

1. Device powers up with a nominal Master Clock frequency of 2.4 MHz. 

2. During configuration, you can select a different master clock frequency. 

3. The Master Clock frequency changes to the selected frequency once the clock configuration bits are received. 

4. If you do not select a master clock frequency, then the configuration bitstream defaults to the MCLK frequency of 2.4 MHz. 

This internal oscillator is available to you by routing it as an input clock to the clock tree. For further information on the use of this oscillator for configuration or user mode, refer to ECP5 and ECP5-5G sysCONFIG Usage Guide (FPGA-TN02039) and ECP5 and ECP5-5G sysClock PLL/DLL Design and Usage Guide (FPGA-TN-02200). 

**Table 2.16. Selectable Master Clock (MCLK) Frequencies during Configuration (Nominal)** 

**MCLK Frequency (MHz)** 2.4 4.8 9.7 19.4 38.8 62 

## **2.19. Density Shifting** 

The ECP5/ECP5-5G family is designed to ensure that different density devices in the same family and in the same package have the same pinout. Furthermore, the architecture ensures a high success rate when performing design migration from lower density devices to higher density devices. In many cases, it is also possible to shift a lower utilization design targeted for a high-density device to a lower density device. However, the exact details of the final resource utilization impacts the likelihood of success in each case. An example is that some user I/O may become No Connects in smaller devices in the same package. Refer to the ECP5/ECP5-5G Pin Migration Tables and Diamond software for specific restrictions and limitations. 

© 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02012-2.2 

47 

**ECP5 and ECP5-5G Family Data Sheet** 

## **3. DC and Switching Characteristics** 

## **3.1. Absolute Maximum Ratings** 

**Table 3.1. Absolute Maximum Ratings** 

|**Symbol**<br>~~a~~|**Parameter**|**Min**|**Max**|**Unit**|
|---|---|---|---|---|
|VCC<br>~~a~~|SupplyVoltage|–0.5|1.32|V|
|VCCA<br>~~a~~|SupplyVoltage|–0.5|1.32|V|
|VCCAUX, VCCAUXA<br>~~a~~|SupplyVoltage|–0.5|2.75|V|
|VCCIO<br>~~a~~|SupplyVoltage|–0.5|3.63|V|
|—<br>~~a~~<br>~~a~~|Input or I/O Transient Voltage Applied|–0.5|3.63|V|
|VCCHRX, VCCHTX<br>~~a~~|SERDES RX/TX Buffer SupplyVoltages|–0.5|1.32|V|
|—<br>~~a~~|Voltage Applied on SERDES Pins|–0.5|1.80|V|
|TA<br>~~a~~|Storage Temperature(Ambient)|–65|150|°C|
|TJ<br>~~a~~|Junction Temperature|—|+125|°C|



## **Notes** : 

1. Stress above those listed under the _Absolute Maximum Ratings_ may cause permanent damage to the device. Functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. 

2. Compliance with the Lattice Thermal Management document is required. 

3. All voltages referenced to GND. 

## **3.2. Recommended Operating Conditions** 

**Table 3.2. Recommended Operating Conditions** 

|**Symbol**<br>~~Ge~~|**Parameter**<br>~~Ge~~|~~Ge~~|**Min**<br>~~Ge~~<br>~~GO~~|**Max**<br>~~Ge~~<br>~~GO~~|**Unit**<br>~~Ge~~|
|---|---|---|---|---|---|
|VCC2<br>~~a~~|Core Supply Voltage<br>~~a~~|ECP5<br>~~a~~<br>~~ee~~|1.045<br>~~GO~~<br>~~a~~<br>~~ee~~|1.155<br>~~GO~~<br>~~a~~<br>~~ee~~|V<br>~~a~~<br>~~ee~~|
|||ECP5-5G<br>~~a~~<br>~~ee~~|1.14<br>~~a~~<br>~~ee~~|1.26<br>~~a~~<br>~~ee~~|V<br>~~a~~<br>~~ee~~|
|VCCAUX2, 4<br>~~a~~<br>~~(GO~~<br>~~a~~|Auxiliary Supply Voltage<br>~~a~~<br>~~(GO~~<br>|—<br>~~a~~<br>~~ee~~<br>~~(GO~~<br>|2.375<br>~~a~~<br>~~ee~~<br>~~(GO~~<br>~~GO~~<br>|2.625<br>~~a~~<br>~~ee~~<br>~~(GO~~<br>~~GO~~<br>|V<br>~~a~~<br>~~ee~~<br>~~(GO~~<br>|
|VCCIO2, 3<br>~~(GO~~<br>~~ee~~<br>~~a~~|I/O Driver Supply Voltage<br>~~(GO~~<br>~~ee~~<br>|—<br>~~(GO~~<br>~~ee~~<br>|1.14<br>~~(GO~~<br>~~ee~~<br>~~GO~~<br>|3.465<br>~~(GO~~<br>~~ee~~<br>~~GO~~<br>|V<br>~~(GO~~<br>~~ee~~<br>|
|VREF1<br>~~a~~|Input Reference Voltage<br>|—<br>|0.5<br>~~GO~~<br><br>~~GO~~|1.0<br>~~GO~~<br><br>~~GO~~|V<br>|
|tJCOM<br>~~aee~~|Junction Temperature, Commercial Operation<br>~~ee~~|—<br>~~ee~~|0<br>~~GO~~<br>~~ee~~<br>~~GO~~|85<br>~~GO~~<br>~~ee~~<br>~~GO~~|°C<br>~~ee~~|
|tJIND<br>~~GO~~|Junction Temperature, Industrial Operation<br>~~GO~~|—<br>~~GO~~|–40<br>~~GO~~<br>~~GO~~|100<br>~~GO~~<br>~~GO~~|°C<br>~~GO~~|
|**SERDES External Power Supply5**<br>~~pn~~||||||
|VCCA<br>~~pn~~<br>~~a~~|SERDES Analog Power Supply<br>~~pn~~<br>~~a~~|ECP5UM<br>~~pn~~<br>~~a~~<br>~~ee~~|1.045<br>~~pn~~<br>~~a~~<br>~~ee~~|1.155<br>~~pn~~<br>~~a~~<br>~~ee~~|V<br>~~pn~~<br>~~a~~<br>~~ee~~|
|||ECP5-5G<br>~~a~~<br>~~ee~~|1.164<br>~~a~~<br>~~ee~~<br>~~GO~~|1.236<br>~~a~~<br>~~ee~~<br>~~GO~~|V<br>~~a~~<br>~~ee~~|
|VCCAUXA<br>~~a~~<br>~~se~~|SERDES Auxiliary Supply Voltage<br>~~a~~<br>~~se~~|—<br>~~a~~<br>~~ee~~<br>~~se~~|2.374<br>~~a~~<br>~~ee ~~<br>~~se~~<br>~~GO~~|2.625<br>~~a~~<br> ~~ee~~<br>~~se~~<br>~~GO~~|V<br>~~a~~<br>~~ee~~<br>~~se~~|
|VCCHRX6<br>~~a~~<br>~~a~~|SERDES Input Buffer Power Supply<br>~~a~~|ECP5UM<br>~~a~~<br>~~ee~~|0.30<br>~~GO~~<br>~~a~~<br>~~ee~~|1.155<br>~~GO~~<br>~~a~~<br>~~ee~~|V<br>~~a~~<br>~~ee~~|
|||ECP5-5G<br>~~a~~<br>~~ee~~|0.30<br>~~a~~<br>~~ee~~|1.26<br>~~a~~<br>~~ee~~|V<br>~~a~~<br>~~ee~~|
|VCCHTX<br>~~a~~<br>~~a~~|SERDES Output Buffer Power Supply<br>~~a~~|ECP5UM<br>~~a~~<br>~~ee~~<br>~~ee~~|1.045<br>~~a~~<br>~~ee~~<br>~~ee~~|1.155<br>~~a~~<br>~~ee~~<br>~~ee~~|V<br>~~a~~<br>~~ee~~|
|||ECP5-5G<br>~~ee ~~<br>~~ee~~|1.14<br> ~~ee ~~<br>~~ee~~|1.26<br> ~~ee ~~<br>~~ee~~|V<br> ~~ee~~|



**Notes** : 

1. For correct operation, all supplies except VREF must be held in their valid operation range. This is true independent of feature usage. 

2. All supplies with same voltage, except SERDES Power Supplies, should be connected together. 

3. See recommended voltages by I/O standard in Table 3.4. 

4. VCCAUX ramp rate must not exceed 30 mV/µs during power-up when transitioning between 0 V and 3 V. 

5. Refer to ECP5 and ECP5-5G SERDES/PCS Usage Guide (FPGA-TN-02206) for information on board considerations for SERDES power supplies. 

6. VCCHRX is used for Rx termination. It can be biased to Vcm if external AC coupling is used. This voltage needs to meet all the HDin input voltage level requirements specified in the Rx section of this Data Sheet. 

© 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

48 

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**ECP5 and ECP5-5G Family Data Sheet** 

## **3.3. Power Supply Ramp Rates** 

## **Table 3.3. Power Supply Ramp Rates** 

|**Symbol**|**Parameter**|**Min**|**Typ**|**Max**|**Unit**|
|---|---|---|---|---|---|
|tRAMP|Power Supply ramp rates for all supplies|0.01|—|10|V/ms|



**Note** : Assumes monotonic ramp rates. 

## **3.4. Power-On-Reset Voltage Levels** 

**Table 3.4. Power-On-Reset Voltage Levels** 

|**Symbol**|**Parameter**|**Parameter**|**Parameter**|**Min**|**Typ**|**Max**|**Unit**|
|---|---|---|---|---|---|---|---|
|VPORUP|All Devices|Power-On-Reset ramp-up<br>trip point (Monitoring VCC,<br>VCCAUX, and VCCIO8)|VCC|0.90|—|1.00|V|
||||VCCAUX|2.00|—|2.20|V|
||||VCCIO8|0.95|—|1.06|V|
|VPORDN|All Devices|Power-On-Reset ramp-<br>down trip point (Monitoring<br>VCC, and VCCAUX|VCC|0.77|—|0.87|V|
||||VCCAUX|1.80|—|2.00|V|



## **Notes** : 

- These POR trip points are only provided for guidance. Device operation is only characterized for power supply voltages specified under recommended operating conditions. 

- Only VCCIO8 has a Power-On-Reset ramp up trip point. All other VCCIOs do not have Power-On-Reset ramp up detection. 

- VCCIO8 does not have a Power-On-Reset ramp down detection. VCCIO8 must remain within the Recommended Operating Conditions to ensure proper operation. 

## **3.5. Power up Sequence** 

Power-On-Reset (POR) puts the ECP5/ECP5-5G device in a reset state. POR is released when VCC, VCCAUX, and VCCIO8 are ramped above the VPORUP voltage, as specified above. 

VCCIO8 controls the voltage on the configuration I/O pins. If the ECP5/ECP5-5G device is using Master SPI mode to download configuration data from external SPI Flash, it is required to ramp VCCIO8 above VIH of the external SPI Flash, before at least one of the other two supplies (VCC and/or VCCAUX) is ramped to VPORUP voltage level. If the system cannot meet this power up sequence requirement, and requires the VCCIO8 to be ramped last, then the system must keep either PROGRAMN or INITN pin LOW during power up, until VCCIO8 reaches VIH of the external SPI Flash. This ensures the signals driven out on the configuration pins to the external SPI Flash meet the VIH voltage requirement of the SPI Flash. For LFE5UM/LFE5UM5G devices, it is required to power up VCCA, before VCCAUXA is powered up. 

## **3.6. Hot Socketing Specifications** 

**Table 3.5. Hot Socketing Specifications** 

|**Symbol**|**Parameter**|**Condition**|**Min**|**Typ**|**Max**|**Unit**|
|---|---|---|---|---|---|---|
|IDK_HS|Input or I/O Leakage Current<br>for Top and Bottom Banks<br>Only|0VIN VIH (Max)|—|—|±1|mA|
|IDK|Input or I/O Leakage Current<br>for Left and Right Banks Only|0VIN < VCCIO|—|—|±1|mA|
|||VCCIO VIN VCCIO + 0.5 V|—|18|—|mA|



**Notes** : 

1. VCC, VCCAUX and VCCIO should rise/fall monotonically. 

2. IDK is additive to IPU, IPW or IBH. 

3. LVCMOS and LVTTL only. 

4. Hot socket specification defines when the hot socketed device's junction temperature is at 85[o] C or below. When the hot socketed device's junction temperature is above 85[o] C, the IDK current can exceed ±1 mA. 

© 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02012-2.2 

49 

**ECP5 and ECP5-5G Family Data Sheet** 

## **3.7. Hot Socketing Requirements** 

## **Table 3.6. Hot Socketing Requirements** 

|**Description**|**Min**|**Typ**|**Max**|**Unit**|
|---|---|---|---|---|
|Input current per SERDES I/O pin when device is powered down and inputs<br>driven.|—|—|8|mA|
|Input current per HDIN pin when device power supply is off, inputs driven1, 2|—|—|15|mA|
|Current per HDIN pin when device power ramps up, input driven3|—|—|50|mA|
|Current per HDOUT pin when device power supply is off, outputs pulled up4|—|—|30|mA|



## **Notes** : 

1. Device is powered down with all supplies grounded, both HDINP and HDINN inputs driven by a CML driver with maximum allowed output VCCHTX, 8b/10b data, no external AC coupling. 

2. Each P and N input must have less than the specified maximum input current during hot plug. For a device with 2 DCU, the total input current would be 15 mA * 4 channels * 2 input pins per channel = 120 mA. 

3. Device power supplies are ramping up (VCCA and VCCAUX), both HDINP and HDINN inputs are driven by a CML driver with maximum allowed output VCCHTX, 8b/10b data, internal AC coupling. 

4. Device is powered down with all supplies grounded. Both HDOUTP and HDOUN outputs are pulled up to VCCHTX by the far end receiver termination of 50 Ω single ended. 

## **3.8. ESD Performance** 

Refer to the ECP5 and ECP5-5G Product Family Qualification Summary for complete qualification data, including ESD performance. 

## **3.9. DC Electrical Characteristics** 

Over Recommended Operating Conditions 

## **Table 3.7. DC Electrical Characteristics** 

|**Symbol**<br>~~a~~|**Parameter**<br>~~RG~~|**Condition**<br>~~RG~~|**Min**<br>~~RG~~|**Typ**<br>~~RG~~|**Max**<br>~~RG~~|**Unit**<br>~~RG~~|
|---|---|---|---|---|---|---|
|IIL, IIH1, 4<br>~~a eG~~|Input or I/O Low Leakage<br>~~eG~~|0VIN VCCIO<br>~~eG~~|—<br>~~eG~~|—<br>~~eG~~|10<br>~~eG~~|µA<br>~~eG~~|
|IIH1, 3<br>~~a~~|Input or I/O High Leakage<br>|VCCIO < VIN VIH(MAX)<br>|—<br>|—<br>|100<br>|µA<br>|
|IPU<br>~~ee~~|I/O Active Pull-up Current,<br>sustaininglogic HIGH state<br>~~ee~~|0.7 VCCIOVINVCCIO<br>~~ee~~|–30<br>~~ee~~|—<br>~~ee~~|—<br>~~ee~~|µA<br>~~ee~~|
||I/O Active Pull-up Current, pulling<br>down from logic HIGH state<br>~~ee~~<br>~~OO~~|0VIN 0.7 VCCIO<br>~~ee~~<br>~~OO~~|—<br>~~ee~~<br>~~OO~~|—<br>~~ee~~<br>~~OO~~|–150<br>~~ee~~<br>~~OO~~|µA<br>~~ee~~<br>~~OO~~|
|IPD<br>~~ee~~<br>~~ee~~|I/O Active Pull-down Current,<br>sustaining logic LOW state<br>~~ee~~<br>~~OO~~<br>~~ee~~|0VIN VIL (MAX)<br>~~ee~~<br>~~OO~~<br>~~ee~~|30<br>~~ee~~<br>~~OO~~<br>~~ee~~|—<br>~~ee~~<br>~~OO~~<br>~~ee~~|—<br>~~ee~~<br>~~OO~~<br>~~ee~~|µA<br>~~ee~~<br>~~OO~~<br>~~ee~~|
||I/O Active Pull-down Current,<br>pulling up from logic LOW state<br>~~ee~~<br>~~a~~|0VIN VCCIO<br>~~ee~~<br>~~a~~|—<br>~~ee~~<br>~~a~~|—<br>~~ee~~<br>~~a~~|150<br>~~ee~~<br>~~a~~|µA<br>~~ee~~<br>~~a~~|
|C1<br>~~a~~|I/O Capacitance2<br>~~a~~|VCCIO = 3.3 V, 2.5 V, 1.8 V, 1.5 V, 1.2 V,<br>VCC = 1.2 V, VIO = 0 toVIH(MAX)<br>~~a~~|—<br>~~a~~|5<br>~~a~~|8<br>~~a~~|pf<br>~~a~~|
|C2<br>~~a~~|Dedicated Input Capacitance2<br>~~a~~|VCCIO = 3.3 V, 2.5 V, 1.8 V, 1.5 V, 1.2 V,<br>VCC = 1.2 V, VIO = 0 toVIH(MAX)<br>~~a~~|—<br>~~a~~|5<br>~~a~~|7<br>~~a~~|pf<br>~~a~~|
|VHYST<br>~~a~~<br>~~ep~~|Hysteresis for Single-Ended<br>Inputs<br>~~a~~<br>~~ep~~|VCCIO = 3.3 V<br>~~a~~|—<br>~~a~~|300<br>~~a~~|—<br>~~a~~|mV<br>~~a~~|
|||VCCIO = 2.5 V<br>~~a~~|—<br>~~a~~|250<br>~~a~~|—<br>~~a~~|mV<br>~~a~~|



**Notes** : 

1. Input or I/O leakage current is measured with the pin configured as an input or as an I/O with the output driver tristated. It is not measured with the output driver active. Bus maintenance circuits are disabled. 

2. TA 25[o] C, f = 1.0 MHz. 

3. Applicable to general purpose I/O in top and bottom banks. 

4. When used as VREF, maximum leakage= 25 µA. 

© 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

50 

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**ECP5 and ECP5-5G Family Data Sheet** 

## **3.10. Supply Current (Static)** 

Over recommended operating conditions. 

**Table 3.8. ECP5/ECP5-5G Supply Current (Static)** 

|**Symbol**<br>~~a~~|**Parameter**|**Device**|**Typical**|**Unit**|
|---|---|---|---|---|
|ICC<br>~~ee~~|Core Power Supply Current<br>~~ee —EEEE~~|LFE5U-12F/LFE5U-25F/LFE5UM-25F<br>~~a~~|77<br>~~a~~|mA<br>~~a~~|
|||LFE5UM5G-25F<br>~~a~~|77<br>~~a~~|mA<br>~~a~~|
|||LFE5U-45F/LFE5UM-45F<br>~~a~~<br>~~a~~|116<br>~~a~~<br>~~a~~|mA<br>~~a~~<br>~~a~~|
|||LFE5UM5G-45F<br>~~a~~|116<br>~~a~~|mA<br>~~a~~|
|||LFE5U-85F/LFE5UM-85F<br>~~a~~<br>~~a~~|212<br>~~a~~<br>~~a~~|mA<br>~~a~~<br>~~a~~|
|||LFE5UM5G-85F<br>~~ee~~<br>~~—EEEE~~|212<br>~~ee~~<br>~~—EEEE~~|mA<br>~~ee~~<br>~~—EEEE~~|
|ICCAUX<br>~~ee~~<br>~~a~~|Auxiliary Power Supply Current<br>~~ee —EEEE~~<br>~~a~~|LFE5U-12F/LFE5U-25F/LFE5UM-25F/<br>LFE5UM5G-25F<br>~~ee~~<br>~~—EEEE~~|16<br>~~ee~~<br>~~—EEEE~~|mA<br>~~ee~~<br>~~—EEEE~~|
|||LFE5U-45F/LFE5UM-45F/LFE5UM5G-45F<br>~~ee~~<br>~~—EEEE~~|17<br>~~ee~~<br>~~—EEEE~~|mA<br>~~ee~~<br>~~—EEEE~~|
|||LFE5U-85F/LFE5UM-85F/LFE5UM5G-85F<br>~~ee~~<br>~~—EEEE~~<br>~~a~~<br>~~—EEEE~~|26<br>~~ee~~<br>~~—EEEE~~<br>~~a~~<br>~~—EEEE~~|mA<br>~~ee~~<br>~~—EEEE~~<br>~~a~~<br>~~—EEEE~~|
|ICCIO<br>~~ee~~<br>~~a~~|Bank Power Supply Current (Per Bank)<br>~~ee —EEEE~~<br>~~a~~|LFE5U-12F/LFE5U-25F/LFE5UM-25F/<br>LFE5UM5G-25F<br>~~ee~~<br>~~—EEEE~~<br>~~—EEEE~~|0.5<br>~~ee~~<br>~~—EEEE~~<br>~~—EEEE~~|mA<br>~~ee~~<br>~~—EEEE~~<br>~~—EEEE~~|
|||LFE5U-45F/LFE5UM-45F/LFE5UM5G-45F<br>~~—EEEE~~|0.5<br>~~—EEEE~~|mA<br>~~—EEEE~~|
|||LFE5U-85F/LFE5UM-85F/LFE5UM5G-85F<br>~~—EEEE~~<br>~~a~~|0.5<br>~~—EEEE~~<br>~~a~~|mA<br>~~—EEEE~~<br>~~a~~|
|ICCA<br>~~a~~|SERDES Power Supply Current (Per<br>Dual)<br>~~a ~~|LFE5UM-25F<br> ~~—EEEE~~<br>~~a~~|11<br>~~—EEEE~~<br>~~a~~|mA<br>~~—EEEE~~<br>~~a~~|
|||LFE5UM5G-25F<br>~~a~~|12<br>~~a~~|mA<br>~~a~~|
|||LFE5UM-45F<br>~~a~~|9.5<br>~~a~~|mA<br>~~a~~|
|||LFE5UM5G-45F<br>~~a~~|11<br>~~a~~|mA<br>~~a~~|
|||LFE5UM-85F<br>~~a~~|9.5<br>~~a~~|mA<br>~~a~~|
|||LFE5UM5G-85F<br>~~es~~|11<br>~~es~~|mA<br>~~es~~|



**Notes** : 

- For further information on supply current, see the list of technical documentation in Supplemental Information section. 

- Assumes all outputs are tristated, all inputs are configured as LVCMOS and held at the VCCIO or GND. 

- Frequency 0 Hz. 

- Pattern represents a test bitstream to consume minimum static power. 

- TJ = 85 °C, power supplies at nominal voltage. 

- To determine the ECP5/ECP5-5G peak start-up current, use the Power Calculator tool in the Lattice Diamond Design software. 

© 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02012-2.2 

51 

**ECP5 and ECP5-5G Family Data Sheet** 

## **3.11. SERDES Power Supply Requirements[1, 2, 3]** 

Over recommended operating conditions. 

**Table 3.9. ECP5UM** 

|**Symbol**<br>~~es~~|**Description**|**Typ**|**Max**|**Unit**|
|---|---|---|---|---|
|**Standby (Power Down)**<br>~~es~~<br>~~es~~|||||
|ICCA-SB<br>~~es~~<br>~~es~~|VCCAPower Supply Current (Per Channel)<br>|4<br>|9.5<br>|mA<br>|
|ICCHRX-SB4<br>~~es~~<br>~~es~~|VCCHRX, Input Buffer Current (Per Channel)<br>|—<br>|0.1<br>|mA<br>|
|ICCHTX-SB<br>~~esa~~|VCCHTX, Output Buffer Current (Per Channel)<br>~~a~~|—<br>~~a~~|0.9<br>~~a~~|mA<br>~~a~~|
|**Operating (Data Rate = 3.125 Gb/s)**<br>~~a~~<br>~~es~~|||||
|ICCA-OP<br>~~es~~|VCCAPower Supply Current (Per Channel)|43|54|mA|
|ICCHRX-OP5<br>~~es~~<br>~~a~~<br>~~es~~|VCCHRX, Input Buffer Current (Per Channel)|0.4|0.5|mA|
|ICCHTX-OP<br>~~es~~|VCCHTX, Output Buffer Current (Per Channel)|10|13|mA|
|**Operating (Data Rate = 2.5 Gb/s)**<br>~~es~~<br>~~pn~~<br>~~es~~|||||
|ICCA-OP<br>~~pn~~<br>~~es~~<br>~~es~~|VCCAPower Supply Current (Per Channel)<br>~~pn~~|40<br>~~pn~~|50<br>~~pn~~|mA<br>~~pn~~|
|ICCHRX-OP5<br>~~es~~<br>~~es~~<br>~~a~~|VCCHRX, Input Buffer Current (Per Channel)<br>|0.4<br>|0.5<br>|mA<br>|
|ICCHTX-OP<br>~~es~~<br>~~a~~|VCCHTX, Output Buffer Current (Per Channel)<br>|10<br>|13<br>|mA<br>|
|**Operating (Data Rate = 1.25 Gb/s)**<br>~~aPe~~<br>~~ee~~|||||
|ICCA-OP<br>~~ee~~<br>~~es~~|VCCAPower Supply Current (Per Channel)|34|43|mA|
|ICCHRX-OP5<br>~~ee~~<br>~~es~~<br>~~es~~|VCCHRX, Input Buffer Current (Per Channel)|0.4|0.5|mA|
|ICCHTX-OP<br>~~es~~<br>~~es~~|VCCHTX, Output Buffer Current (Per Channel)|10|13|mA|
|**Operating (Data Rate = 270 Mb/s)**<br>~~es~~<br>~~pe~~|||||
|ICCA-OP<br>~~pe~~<br>~~a~~<br>~~es~~|VCCAPower Supply Current (Per Channel)<br>~~pe~~|28<br>~~pe~~|38<br>~~pe~~|mA<br>~~pe~~|
|ICCHRX-OP5<br>~~es~~<br>~~es~~|VCCHRX, Input Buffer Current (Per Channel)|0.4|0.5|mA|
|ICCHTX-OP<br>~~es~~<br>~~es~~|VCCHTX, Output Buffer Current (Per Channel)|8|10|mA|



**Notes** : 

1. Rx Equalization enabled, Tx De-emphasis (pre-cursor and post-cursor) disabled 

2. Per Channel current is calculated with both channels on in a Dual, and divide current by two. If only one channel is on, current is higher. 

3. To calculate with Tx De-emphasis enabled, use the Diamond Power Calculator tool. 

4. For ICCHRX-SB, during Standby, input termination on Rx are disabled. 

5. For ICCHRX-OP, during operational, the max specified when external AC coupling is used. If externally DC coupled, the power is based on current pulled down by external driver when the input is driven to LOW. 

© 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

52 

FPGA-DS-02012-2.2 

**ECP5 and ECP5-5G Family Data Sheet** 

## **Table 3.10. ECP5-5G** 

|**Symbol**<br>~~es~~|**Description**|**Typ**|**Max**|**Unit**|
|---|---|---|---|---|
|**Standby (Power Down)**<br>~~es~~<br>~~pe~~|||||
|ICCA-SB<br>~~pe~~<br>~~a~~<br>~~a~~|VCCAPower Supply Current (Per Channel)<br>~~pe~~<br>~~a~~<br>~~a~~|4<br>~~pe~~<br>~~a~~<br>~~a~~|9.5<br>~~pe~~<br>~~a~~<br>~~a~~|mA<br>~~pe~~<br>~~a~~<br>~~a~~|
|ICCHRX-SB4<br>~~a~~|VCCHRX, Input Buffer Current (Per Channel)<br>~~a~~|—<br>~~a~~|0.1<br>~~a~~|mA<br>~~a~~|
|ICCHTX-SB<br>~~a~~|VCCHTX, Output Buffer Current (Per Channel)<br>~~a~~|—<br>~~a~~|0.9<br>~~a~~|mA<br>~~a~~|
|**Operating (Data Rate = 5 Gb/s)**<br>~~Pe~~|||||
|ICCA-OP<br>~~a~~|VCCAPower Supply Current (Per Channel)|58|67|mA|
|ICCHRX-OP5<br>~~a~~<br>~~a a~~|VCCHRX, Input Buffer Current (Per Channel)<br>~~a~~|0.4<br>~~a~~|0.5<br>~~a~~|mA<br>~~a~~|
|ICCHTX-OP<br>~~CO~~|VCCHTX, Output Buffer Current (Per Channel)<br>~~CO~~|10<br>~~CO~~|13<br>~~CO~~|mA<br>~~CO~~|
|**Operating (Data Rate = 3.2 Gb/s)**<br>~~CO~~<br>~~Pe~~|||||
|ICCA-OP<br>~~a a~~|VCCAPower Supply Current (Per Channel)<br>~~a~~|48<br>~~a~~|57<br>~~a~~|mA<br>~~a~~|
|ICCHRX-OP5<br>~~CO~~<br>~~ee~~|VCCHRX, Input Buffer Current (Per Channel)<br>~~CO~~|0.4<br>~~CO~~|0.5<br>~~CO~~|mA<br>~~CO~~|
|ICCHTX-OP<br>~~CO~~<br>~~ee~~|VCCHTX, Output Buffer Current (Per Channel)<br>~~CO~~|10<br>~~CO~~|13<br>~~CO~~|mA<br>~~CO~~|
|**Operating (Data Rate = 2.5 Gb/s)**<br>~~ee~~<br>~~PR~~<br>~~eea~~|||||
|ICCA-OP<br>~~ee~~|VCCAPower Supply Current (Per Channel)<br>~~a~~|44|53|mA|
|ICCHRX-OP5<br>~~ee~~<br>~~a~~|VCCHRX, Input Buffer Current (Per Channel)<br>~~a~~|0.4|0.5|mA|
|ICCHTX-OP<br>~~a~~|VCCHTX, Output Buffer Current (Per Channel)<br>|10<br>|13<br>|mA<br>|
|**Operating (Data Rate = 1.25 Gb/s)**<br>~~Pe~~|||||
|ICCA-OP<br>~~a~~<br>~~es~~|VCCAPower Supply Current (Per Channel)<br>|36<br>|46<br>|mA<br>|
|ICCHRX-OP5<br>~~a~~<br>~~es~~|VCCHRX, Input Buffer Current (Per Channel)<br>|0.4<br><br>~~GG~~|0.5<br><br>~~GG~~|mA<br>|
|ICCHTX-OP<br>~~esa~~|VCCHTX, Output Buffer Current (Per Channel)<br>~~a~~|10<br>~~a~~<br>~~GG~~|13<br>~~a~~<br>~~GG~~|mA<br>~~a~~|
|**Operating (Data Rate = 270 Mb/s)**<br>~~a~~<br>~~GG~~<br>~~Pe~~|||||
|ICCA-OP<br>~~a~~|VCCAPower Supply Current (Per Channel)|30|40|mA|
|ICCHRX-OP5<br>~~a~~|VCCHRX, Input Buffer Current (Per Channel)|0.4|0.5|mA|
|ICCHTX-OP<br>~~a~~|VCCHTX, Output Buffer Current (Per Channel)|8|10|mA|



**Notes** : 

1. Rx Equalization enabled, Tx De-emphasis (pre-cursor and post-cursor) disabled 

2. Per Channel current is calculated with both channels on in a Dual, and divide current by two. If only one channel is on, current is higher. 

3. To calculate with Tx De-emphasis enabled, use the Diamond Power Calculator tool. 

4. For ICCHRX-SB, during Standby, input termination on Rx are disabled. 

5. For ICCHRX-OP, during operational, the max specified when external AC coupling is used. If externally DC coupled, the power is based on current pulled down by external driver when the input is driven to LOW. 

© 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02012-2.2 

53 

**ECP5 and ECP5-5G Family Data Sheet** 

## **3.12. sysI/O Recommended Operating Conditions** 

**Table 3.11. sysI/O Recommended Operating Conditions** 

|**Standard**<br>~~eee~~|**VCCIO**<br>~~a~~<br>~~eee~~|**VCCIO**<br>~~a~~<br>~~eee~~|**VCCIO**<br>~~a~~<br>~~eee~~|**VREF (V)**<br>~~a~~<br>~~eee~~|**VREF (V)**<br>~~a~~<br>~~eee~~|**VREF (V)**<br>~~a~~<br>~~eee~~|
|---|---|---|---|---|---|---|
||**Min**<br>~~eee~~|**Typ**<br>~~eee~~|**Max**<br>~~eee~~|**Min**<br>~~eee~~|**Typ**<br>~~eee~~|**Max**<br>~~eee~~|
|LVCMOS331<br>~~eee~~<br>~~GG~~|3.135<br>~~eee~~<br>~~GG~~|3.3<br>~~eee~~<br>~~GG~~|3.465<br>~~eee~~<br>~~GG~~|—<br>~~eee~~<br>~~GG~~|—<br>~~eee~~<br>~~GG~~|—<br>~~eee~~<br>~~GG~~|
|LVCMOS33D Output<br>~~GG~~|3.135<br>~~GG~~|3.3<br>~~GG~~|3.465<br>~~GG~~|—<br>~~GG~~|—<br>~~GG~~|—<br>~~GG~~|
|LVCMOS25D Output<br>~~GG~~|2.375<br>~~GG~~|2.5<br>~~GG~~|2.625<br>~~GG~~|—<br>~~GG~~|—<br>~~GG~~|—<br>~~GG~~|
|LVCMOS251<br>~~GG~~<br>~~po~~|2.375<br>~~GG~~|2.5<br>~~GG~~|2.625<br>~~GG~~|—<br>~~GG~~|—<br>~~GG~~|—<br>~~GG~~|
|LVCMOS18<br>~~GG~~<br>~~po~~|1.71<br>~~GG~~|1.8<br>~~GG~~|1.89<br>~~GG~~|—<br>~~GG~~<br>~~GO~~|—<br>~~GG~~<br>~~GO~~|—<br>~~GG~~|
|LVCMOS15<br>~~po~~<br>~~a~~|1.425<br>~~GO~~|1.5<br>~~GO~~|1.575<br>~~GO~~|—<br>~~GO~~<br>~~GO~~|—<br>~~GO~~<br>~~GO~~|—<br>~~GO~~|
|LVCMOS121<br>~~a ~~<br>~~GG~~|1.14<br> ~~GO~~<br>~~GG~~|1.2<br>~~GO~~<br>~~GG~~|1.26<br>~~GO~~<br>~~GG~~|—<br>~~GO~~<br>~~GO~~<br>~~GG~~|—<br>~~GO~~<br>~~GO~~<br>~~GG~~|—<br>~~GO~~<br>~~GG~~|
|LVTTL331<br>~~GG~~|3.135<br>~~GG~~|3.3<br>~~GG~~|3.465<br>~~GG~~|—<br>~~GG~~|—<br>~~GG~~|—<br>~~GG~~|
|SSTL15_I, _II2<br>~~GG~~<br>~~pO~~|1.43<br>~~GG~~|1.5<br>~~GG~~|1.57<br>~~GG~~|0.68<br>~~GG~~|0.75<br>~~GG~~|0.9<br>~~GG~~|
|SSTL18_I, _II2<br>~~pO~~|1.71|1.8|1.89|0.833|0.9|0.969|
|SSTL135_I, _II2<br>~~pO~~<br>~~GG~~<br>~~pO~~|1.28<br>~~GG~~|1.35<br>~~GG~~|1.42<br>~~GG~~|0.6<br>~~GG~~|0.675<br>~~GG~~|0.75<br>~~GG~~|
|HSUL122<br>~~pO~~|1.14|1.2|1.26|0.588|0.6|0.612|
|MIPI D-PHY LP Input3, 5<br>~~pO~~<br>~~GG~~|1.425<br>~~GG~~|1.5<br>~~GG~~|1.575<br>~~GG~~|—<br>~~GG~~|—<br>~~GG~~|—<br>~~GG~~|
|LVDS251, 3 <br>~~GG~~<br>~~po~~|2.375<br>~~GG~~|2.5<br>~~GG~~|2.625<br>~~GG~~|—<br>~~GG~~|—<br>~~GG~~|—<br>~~GG~~|
|subLVS3 (Input only)<br>~~GG~~<br>~~po~~|—<br>~~GG~~|—<br>~~GG~~|—<br>~~GG~~|—<br>~~GG~~<br>~~GO~~|—<br>~~GG~~<br>~~GO~~|—<br>~~GG~~|
|SLVS3 (Input only)<br>~~po~~<br>~~a~~|—<br>~~GO~~|—<br>~~GO~~|—<br>~~GO~~|—<br>~~GO~~<br>~~GO~~|—<br>~~GO~~<br>~~GO~~|—<br>~~GO~~|
|LVDS25E Output<br>~~a ~~<br>~~GG~~|2.375<br> ~~GO~~<br>~~GG~~|2.5<br>~~GO~~<br>~~GG~~|2.625<br>~~GO~~<br>~~GG~~|—<br>~~GO~~<br>~~GO~~<br>~~GG~~|—<br>~~GO~~<br>~~GO~~<br>~~GG~~|—<br>~~GO~~<br>~~GG~~|
|MLVDS251, 3 <br>~~GG~~|2.375<br>~~GG~~|2.5<br>~~GG~~|2.625<br>~~GG~~|—<br>~~GG~~|—<br>~~GG~~|—<br>~~GG~~|
|MLVDS25E Output<br>~~GG~~|2.375<br>~~GG~~|2.5<br>~~GG~~|2.625<br>~~GG~~|—<br>~~GG~~<br>~~GO~~|—<br>~~GG~~<br>~~GO~~|—<br>~~GG~~|
|LVPECL331, 3 <br>~~GC~~|3.135<br>~~GC~~|3.3<br>~~GC~~|3.465<br>~~GC~~|—<br>~~GC~~<br>~~GO~~|—<br>~~GC~~<br>~~GO~~|—<br>~~GC~~|
|LVPECL33E Output<br>~~GC~~<br>~~GG~~|3.135<br>~~GC~~<br>~~GG~~|3.3<br>~~GC~~<br>~~GG~~|3.465<br>~~GC~~<br>~~GG~~|—<br>~~GC~~<br>~~GO~~<br>~~GG~~|—<br>~~GC~~<br>~~GO~~<br>~~GG~~|—<br>~~GC~~<br>~~GG~~|
|BLVDS251, 3 <br>~~GG~~<br>~~GG~~|2.375<br>~~GG~~<br>~~GG~~|2.5<br>~~GG~~<br>~~GG~~|2.625<br>~~GG~~<br>~~GG~~|—<br>~~GG~~<br>~~GG~~|—<br>~~GG~~<br>~~GG~~|—<br>~~GG~~<br>~~GG~~|
|BLVDS25E  Output<br>~~a~~|2.375<br>~~GG~~|2.5<br>~~GG~~|2.625<br>~~GG~~|—<br>~~GG~~|—<br>~~GG~~|—<br>~~GG~~|
|HSULD12D2, 3<br>~~a ~~<br>~~GG~~|1.14<br> ~~GG~~<br>~~GG~~|1.2<br>~~GG~~<br>~~GG~~|1.26<br>~~GG~~<br>~~GG~~|—<br>~~GG~~<br>~~GG~~|—<br>~~GG~~<br>~~GG~~|—<br>~~GG~~<br>~~GG~~|
|SSTL135D_I, II2, 3<br>~~GG~~|1.28<br>~~GG~~|1.35<br>~~GG~~|1.42<br>~~GG~~|—<br>~~GG~~|—<br>~~GG~~|—<br>~~GG~~|
|SSTL15D_I, II2, 3<br>~~GG~~<br>~~pO~~|1.43<br>~~GG~~|1.5<br>~~GG~~|1.57<br>~~GG~~|—<br>~~GG~~|—<br>~~GG~~|—<br>~~GG~~|
|SSTL18D_I1, 2, 3, II1, 2, 3<br>~~GG~~<br>~~pO~~|1.71<br>~~GG~~|1.8<br>~~GG~~|1.89<br>~~GG~~|—<br>~~GG~~|—<br>~~GG~~|—<br>~~GG~~|



**Notes** : 

1. For input voltage compatibility, refer to ECP5 and ECP5-5G sysI/O Usage Guide (FPGA-TN-02032). 

2. VREF is required when using Differential SSTL and HSUL to interface to DDR/LPDDR memories. 

3. These differential inputs use LVDS input comparator, which uses VCCAUX power 

4. All differential inputs and LVDS25 output are supported in the Left and Right banks only. Refer to ECP5 and ECP5-5G sysI/O Usage Guide (FPGA-TN-02032) for details. 

5. MIPI D-PHY LP input can be implemented by powering VCCIO to 1.5 V, and select MIPI LP primitive to meet MIPI Alliance spec on VIH and VIL. It can also be implemented as LVCMOS12 with VCCIO at 1.2 V, which would meet VIH/VIL spec on LVCMOS12. 

© 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02012-2.2 

54 

**ECP5 and ECP5-5G Family Data Sheet** 

## **3.13. sysI/O Single-Ended DC Electrical Characteristics** 

**Table 3.12. Single-Ended DC Characteristics** 

|**Input/Output**<br>**Standard**<br>~~a ~~<br>~~a~~|**VIL**<br>~~ee~~<br>~~ree eee~~|**VIL**<br>~~ee~~<br>~~ree eee~~|**VIH**<br>~~ee~~<br>~~eeeee~~|**VIH**<br>~~ee~~<br>~~eeeee~~|**VOL Max**<br>**(V)**|**VOH Min**<br>**(V)**|**IOL1 (mA)**|**IOH1 (mA)**|
|---|---|---|---|---|---|---|---|---|
||**Min (V)**<br>~~ee~~<br> ~~ree~~|**Max (V)**<br>~~ee~~<br>~~ree eee~~|**Min (V)**<br>~~ee~~<br>~~eee~~|**Max (V)**<br>~~ee~~<br>~~ee~~|||||
|LVCMOS33<br> <br>~~a~~<br>~~a~~|–0.3<br> ~~ree~~<br>~~Ge~~|0.8<br>~~ree eee~~<br>~~eG~~|2.0<br>~~eee ~~<br>~~eG~~|3.465<br> ~~ee~~|0.4|VCCIO– 0.4<br>~~CO~~|16, 12, 8, 4<br>~~CO~~|–16, –12,<br>–8,–4|
|LVCMOS25<br>~~a~~<br>~~ee~~<br>~~a~~|–0.3<br>~~Ge~~<br>~~eG~~|0.7<br>~~eG~~<br>~~eG~~|1.7<br>~~eG~~<br>~~eG~~|3.465<br>~~eG~~|0.4<br>~~eG~~|VCCIO– 0.4<br>~~CO~~<br>~~eG~~<br>~~GO~~|12, 8, 4<br>~~CO~~<br>~~eG~~<br>~~GO~~|–12, –8, –4<br>~~eG~~|
|LVCMOS18<br>~~a~~<br>~~ee~~<br>~~a~~|–0.3<br>~~Ge~~<br>~~eG~~|0.35 VCCIO<br>~~eG~~<br>~~eG~~|0.65 VCCIO<br>~~eG~~<br>~~eG~~|3.465<br>~~eG~~|0.4<br>~~eG~~|VCCIO– 0.4<br>~~CO~~<br>~~eG~~<br>~~GO~~|12, 8, 4<br>~~CO~~<br>~~eG~~<br>~~GO~~|–12, –8, –4<br>~~eG~~|
|LVCMOS15<br>~~ee~~<br>~~a~~<br>~~pO~~|–0.3<br>~~eG~~<br>~~pO~~|0.35 VCCIO<br>~~eG~~<br>~~eG~~|0.65 VCCIO<br>~~eG~~<br>~~eG~~|3.465<br>~~eG~~|0.4<br>~~eG~~|VCCIO– 0.4<br>~~eG~~<br>~~GO~~<br>~~CO~~|8, 4<br>~~eG~~<br>~~GO~~<br>~~CO~~|–8, –4<br>~~eG~~|
|LVCMOS12<br>~~pO~~|–0.3<br>~~pO~~|0.35 VCCIO<br>~~eG~~|0.65 VCCIO<br>~~eG~~|3.465|0.4|VCCIO– 0.4<br>~~CO~~|8, 4<br>~~CO~~|–8, –4|
|LVTTL33<br>~~pO~~<br>~~a~~|–0.3<br>~~pO~~|0.8<br>~~eG~~|2.0<br>~~eG~~|3.465|0.4|VCCIO– 0.4<br>~~CO~~|16, 12, 8, 4<br>~~CO~~|–16, –12,<br>–8,–4|
|SSTL18_I<br>(DDR2 Memory)<br>~~a~~<br>~~a~~<br>~~a~~|–0.3|VREF–<br>0.125|VREF+ 0.125|3.465|0.4<br>~~OC~~|VCCIO– 0.4<br>~~OC~~|6.7<br>~~OC~~|–6.7|
|SSTL18_II<br>~~a~~<br>~~a ~~<br>~~a~~|–0.3<br> ~~eG~~|VREF–<br>~~eG~~|VREF+ 0.125<br>~~eG~~|3.465<br>~~eG~~|0.28<br>~~eG~~<br>~~OC~~|VCCIO– 0.28<br>~~eG~~<br>~~OC~~|13.4<br>~~eG~~<br>~~OC~~|–13.4<br>~~eG~~|
|SSTL15 _I<br>(DDR3 Memory)<br>~~a~~|–0.3|VREF– 0.1|VREF+ 0.1|3.465|0.31<br>~~OC~~|VCCIO– 0.31<br>~~OC~~|7.5<br>~~OC~~|–7.5|
|SSTL15_II<br>(DDR3 Memory)<br>~~a~~|–0.3|VREF– 0.1|VREF+ 0.1|3.465|0.31|VCCIO– 0.31|8.8|–8.8|
|SSTL135_I<br>(DDR3L Memory)<br>~~a~~|–0.3|VREF– 0.09|VREF+ 0.09|3.465|0.27|VCCIO– 0.27|7|–7|
|SSTL135_II<br>(DDR3L Memory)<br>~~a~~|–0.3<br>|VREF– 0.09<br>|VREF+ 0.09<br>|3.465<br>|0.27<br>|VCCIO– 0.27<br>|8<br>|–8<br>|
|MIPI D-PHY(LP)3<br>|–0.3<br>|0.55<br><br>~~|~~|0.88<br><br>~~||~~|3.465<br><br>~~||~~|—<br><br>~~||~~|—<br><br>~~|~~<br>~~|~~|—<br><br>~~|fT~~|—<br><br>~~fT~~|
|HSUL12<br>(LPDDR2/3<br>Memory)<br>~~it~~|–0.3<br>~~it~~|VREF– 0.1<br>~~it~~<br>~~|~~|VREF+ 0.1<br>~~it~~<br>~~||~~|3.465<br>~~it~~<br>~~||~~|0.3<br>~~it~~<br>~~||~~|VCCIO– 0.3<br>~~it~~<br>~~|~~<br>~~|~~|4<br>~~it~~<br>~~|fT~~|–4<br>~~it~~<br>~~fT~~|



2. Not all I/O types are supported in all banks. Refer to ECP5 and ECP5-5G sysI/O Usage Guide (FPGA-TN-02032) for details. 

3. MIPI D-PHY LP input can be implemented by powering VCCIO to 1.5 V, and select MIPI LP primitive to meet MIPI Alliance spec on VIH and VIL. It can also be implemented as LVCMOS12 with VCCIO at 1.2 V, which would meet VIH/VIL spec on LVCMOS12. 

© 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02012-2.2 

55 

**ECP5 and ECP5-5G Family Data Sheet** 

## **3.14. sysI/O Differential Electrical Characteristics** 

## **3.14.1. LVDS** 

Over recommended operating conditions. 

**Table 3.13. LVDS** 

|**Parameter**<br>~~a~~|**Description**<br>~~a~~<br>~~a~~|**Test Conditions**<br>~~a~~<br>~~a~~|**Min**<br>~~a~~<br>~~a~~|**Typ**<br>~~a~~<br>~~a~~|**Max**<br>~~a~~<br>~~a~~|**Unit**<br>~~a~~<br>~~a~~|
|---|---|---|---|---|---|---|
|VINP, VINM<br>~~a~~|Input Voltage<br>~~a~~|—<br>~~a~~|0<br>~~a~~|—<br>~~a~~|2.4<br>~~a~~|V<br>~~a~~|
|VCM<br>~~a~~|Input Common Mode Voltage<br>~~a~~<br>~~a~~|Half the sum of the two Inputs<br>~~a~~<br>~~a~~|0.05<br>~~a~~<br>~~a~~|—<br>~~a~~<br>~~a~~|2.35<br>~~a~~<br>~~a~~|V<br>~~a~~<br>~~a~~|
|VTHD<br>~~a~~|Differential Input Threshold<br>~~a~~|Difference between the two Inputs<br>~~a~~|±100<br>~~a~~|—<br>~~a~~|—<br>~~a~~|mV<br>~~a~~|
|IIN<br>~~a~~|Input Current<br>~~a~~<br>~~a~~|Power On or Power Off<br>~~a~~|—<br>~~a~~|—<br>~~a~~|±10<br>~~a~~|µA<br>~~a~~|
|VOH<br>~~a~~<br>~~a~~|Output High Voltage for VOPor VOM<br>~~a~~<br>~~a~~<br>~~a~~<br>~~a~~|RT= 100 Ω<br>~~a~~<br>~~a~~|—<br>~~a~~|1.38<br>~~a~~|1.60<br>~~a~~|V<br>~~a~~|
|VOL<br>~~a~~|Output Low Voltage for VOPor VOM<br>~~a~~|RT= 100 Ω|0.9 V|1.03|—|V|
|VOD<br>~~a~~|Output Voltage Differential<br>~~a~~<br>~~a~~|(VOP- VOM), RT= 100 Ω|250|350|450|mV|
|VOD<br>~~a~~|Change in VODBetween High and<br>Low<br>~~a~~|—<br>~~a~~|—<br>~~a~~|—<br>~~a~~|50<br>~~a~~|mV<br>~~a~~|
|VOS<br>~~a~~|Output Voltage Offset<br>~~a~~|(VOP+ VOM)/2, RT= 100 Ω<br>~~a~~|1.125<br>~~a~~|1.25<br>~~a~~|1.375<br>~~a~~|V<br>~~a~~|
|VOS<br>~~a~~|Change in VOSBetween H and L<br>~~a~~<br>~~a~~|—<br>~~a~~|—<br>~~a~~|—<br>~~a~~|50<br>~~a~~|mV<br>~~a~~|
|ISAB<br>~~a~~<br>~~a~~|Output Short Circuit Current<br>~~a~~<br>~~a~~|VOD= 0 V Driver outputs shorted to<br>each other<br>~~a~~|—<br>~~a~~|—<br>~~a~~|12<br>~~a~~|mA<br>~~a~~|



**Note** : On the left and right sides of the device, this specification is valid only for VCCIO = 2.5 V or 3.3 V. 

## **3.14.2. SSTLD** 

All differential SSTL outputs are implemented as a pair of complementary single-ended outputs. All allowable single-ended output classes (class I and class II) are supported in this mode. 

## **3.14.3. LVCMOS33D** 

All I/O banks support emulated differential I/O using the LVCMOS33D I/O type. This option, along with the external resistor network, provides the system designer the flexibility to place differential outputs on an I/O bank with 3.3 V VCCIO. The default drive current for LVCMOS33D output is 12 mA with the option to change the device strength to 4 mA, 8 mA, 12 mA, or 16 mA. Follow the LVCMOS33 specifications for the DC characteristics of the LVCMOS33D. 

© 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02012-2.2 

56 

**ECP5 and ECP5-5G Family Data Sheet** 

## **3.14.4. LVDS25E** 

The top and bottom sides of ECP5/ECP5-5G devices support LVDS outputs via emulated complementary LVCMOS outputs in conjunction with a parallel resistor across the driver outputs. The scheme shown in Figure 3.1 is one possible solution for point-to-point signals. 

**==> picture [363 x 131] intentionally omitted <==**

**----- Start of picture text -----**<br>
VCCIO = 2.5 V (±5%) ||<br>RS = 158<br>| (±1%)<br>8 mA a r<br>> |<br>RS = 140     RS = 100<br>VCCIO = 2.5 V (±5%) (±1%) (±1%)<br>RS = 158<br>(±1%)<br>8 mA<br>> a a<br>Transmission line, Zo = 100   differential<br>| |<br>ON-chip OFF-chip ON-chip OFF-chip<br>**----- End of picture text -----**<br>


**Figure 3.1. LVDS25E Output Termination Example** 

**Table 3.14. LVDS25E DC Conditions** 

|**Parameter**<br>~~a ~~|**Description**<br> ~~DO~~|**Typical**<br>~~DO~~|**Unit**<br>~~DO~~|
|---|---|---|---|
|VCCIO<br>~~a~~<br>~~ee~~|Output Driver Supply (±5%)|2.50|V|
|ZOUT<br>~~ee~~|Driver Impedance|20||
|RS<br>~~ee~~<br>~~a~~<br>~~a~~|Driver Series Resistor (±1%)<br>|158<br>|<br>|
|RP<br>~~a~~|Driver Parallel Resistor (±1%)<br>|140<br>|<br>|
|RT<br>~~aa~~|Receiver Termination (±1%)<br>|100<br>|<br>|
|VOH<br>~~eG~~|Output High Voltage<br>~~eG~~|1.43<br>~~eG~~|V<br>~~eG~~|
|VOL<br>~~eG~~<br>~~eG~~|Output Low Voltage<br>~~eG~~<br>~~eG~~|1.07<br>~~eG~~<br>~~eG~~|V<br>~~eG~~<br>~~eG~~|
|VOD<br>~~a~~|Output Differential Voltage|0.35|V|
|VCM<br>~~a~~|Output Common Mode Voltage|1.25|V|
|ZBACK<br>~~a~~<br>~~ee~~|Back Impedance|100.5||
|IDC<br>~~ee~~|DC Output Current|6.03|mA|



**Note** : For input buffer, see Table 3.13. 

© 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02012-2.2 

57 

**ECP5 and ECP5-5G Family Data Sheet** 

## **3.14.5. BLVDS25** 

The ECP5/ECP5-5G devices support the BLVDS standard. This standard is emulated using complementary LVCMOS outputs in conjunction with a parallel external resistor across the driver outputs. BLVDS is intended for use when multi-drop and bi-directional multi-point differential signaling is required. The scheme shown in Figure 3.2 is one possible solution for bi-directional multi-point differential signals. 

**==> picture [442 x 203] intentionally omitted <==**

**----- Start of picture text -----**<br>
Heavily loaded backplane, effective Zo ~ 45 Ω  to 90 Ω  differential<br>2.5 V 2.5 V<br>R S = 90 Ω  R S  = 90 Ω<br>16 mA 16 mA<br>45 Ω – 90 Ω R TL 45 Ω – 90 Ω R TR<br>2.5 V 2.5 V<br>16 mA 16 mA<br>R S = 90 Ω  R S = 90 Ω<br>R S = 90 Ω  R S = 90 Ω  . . . R S = 90 Ω  R S = 90 Ω<br>+ +<br>– –<br>eh o e<br>2.5 V 2.5 V – 2.5 V 2.5 V –<br>16 mA 1 6 mA 1 6 mA 16 mA<br>AA SV AL Y<br>+ +<br>**----- End of picture text -----**<br>


**Figure 3.2. BLVDS25 Multi-point Output Example** 

Over recommended operating conditions. 

**Table 3.15. BLVDS25 DC Conditions** 

|**Parameter**<br>~~a ee~~<br>~~a~~|**Description**<br>~~ee~~<br>~~Ge~~|**Typical**<br>~~ee~~<br>~~ceee~~|**Typical**<br>~~ee~~<br>~~ceee~~|**Unit**<br>~~ee~~|
|---|---|---|---|---|
|||**Zo = 45**<br>~~ee~~<br>~~ce~~<br>~~GO~~|**Zo = 90**<br>~~ee~~<br>~~ee~~<br>~~GO~~||
|VCCIO<br>~~a~~|Output Driver Supply (±5%)<br>~~Ge~~|2.50<br>~~ce ~~<br>~~GO~~|2.50<br> ~~ee~~<br>~~GO~~<br>~~ee~~|V|
|ZOUT<br>~~ee~~|Driver Impedance<br>~~Ge~~<br>~~ee~~|10.00<br>~~GO~~<br>~~ee~~|10.00<br>~~GO~~<br>~~ee~~<br>~~ee~~|<br>~~ee~~|
|RS<br>~~ee~~|Driver Series Resistor (±1%)<br>~~ee~~|90.00<br>~~ee~~|90.00<br>~~ee~~<br>~~ee~~|<br>~~ee~~|
|RTL|Driver Parallel Resistor (±1%)|45.00|90.00<br>~~ee~~||
|RTR|Receiver Termination (±1%)|45.00|90.00||
|VOH|Output High Voltage|1.38|1.48<br>~~ee~~|V|
|VOL<br>~~ee~~|Output Low Voltage<br>~~ee~~|1.12<br>~~ee~~|1.02<br>~~ee~~<br>~~ee~~|V<br>~~ee~~|
|VOD<br>~~ee~~|Output Differential Voltage<br>~~ee~~|0.25<br>~~ee~~|0.46<br>~~ee~~<br>~~ee~~<br>~~ee~~|V<br>~~ee~~|
|VCM<br>~~ee~~|Output Common Mode Voltage<br>~~ee~~|1.25<br>~~ee~~|1.25<br>~~ee~~<br>~~ee~~<br>~~ee~~|V<br>~~ee~~|
|IDC<br>~~ee~~|DC Output Current<br>~~ee~~|11.24<br>~~ee~~|10.20<br>~~ee~~<br>~~ee~~|mA<br>~~ee~~|



**Note** : For input buffer, see Table 3.13. 

© 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

58 

FPGA-DS-02012-2.2 

**ECP5 and ECP5-5G Family Data Sheet** 

## **3.14.6. LVPECL33** 

The ECP5/ECP5-5G devices support the differential LVPECL standard. This standard is emulated using complementary LVCMOS outputs in conjunction with a parallel resistor across the driver outputs. The LVPECL input standard is supported by the LVDS differential input buffer. The scheme shown in Figure 3.3 is one possible solution for point-to-point signals. 

**==> picture [368 x 145] intentionally omitted <==**

**----- Start of picture text -----**<br>
VCCIO = 3.3 V<br>(±5%)<br>RS = 93.1 Ω<br>(±1%)<br>16 mA<br>> VCCIO = 3.3 V  RP = 196 Ω RT = 100 Ω  +<br>(±5%) RS = 93.1 Ω  (±1%) (±1%) –<br>(±1%)<br>16 mA =<br>Transmission line,<br>Zo = 100 Ω differential<br>><br>On-chip Off-chip Off-chip On-chip<br>**----- End of picture text -----**<br>


**Figure 3.3. Differential LVPECL33** 

Over recommended operating conditions. 

**Table 3.16. LVPECL33 DC Conditions** 

|**Parameter**<br>~~es~~|**Description**<br>~~ee~~|**Typical**<br>~~ee~~|**Unit**<br>~~ee~~|
|---|---|---|---|
|VCCIO<br>~~es~~<br>~~a~~|Output Driver Supply (±5%)<br>~~ee~~<br>|3.30<br>~~ee~~<br>|V<br>~~ee~~<br>|
|ZOUT<br>~~se~~|Driver Impedance<br>~~se~~|10<br>~~se~~|<br>~~se~~|
|RS<br>~~se~~<br>~~a~~|Driver Series Resistor (±1%)<br>~~se~~<br>|93<br>~~se~~<br>|<br>~~se~~<br>|
|RP<br>~~es~~|Driver Parallel Resistor (±1%)<br>~~es~~|196<br>~~es~~|<br>~~es~~|
|RT<br>~~es~~<br>~~a~~<br>~~ee~~|Receiver Termination (±1%)<br>~~es~~<br>~~en~~|100<br>~~es~~<br>~~en~~|<br>~~es~~<br>~~en~~|
|VOH<br>~~a ~~<br>~~ee~~<br>~~es~~|Output High Voltage<br> ~~en~~|2.05<br>~~en~~|V<br>~~en~~|
|VOL<br>~~ee~~<br>~~es~~<br>~~ee~~|Output Low Voltage|1.25|V|
|VOD<br>~~es~~<br>~~ee~~|Output Differential Voltage|0.80|V|
|VCM<br>~~ee~~<br>~~ee~~<br>~~es~~|Output Common Mode Voltage<br>~~ee~~|1.65<br>~~ee~~|V<br>~~ee~~|
|ZBACK<br>~~es~~|Back Impedance|100.5||
|IDC<br>~~es~~<br>~~a~~|DC Output Current|12.11|mA|



**Note** : For input buffer, see Table 3.13. 

© 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02012-2.2 

59 

**ECP5 and ECP5-5G Family Data Sheet** 

## **3.14.7. MLVDS25** 

The ECP5/ECP5-5G devices support the differential MLVDS standard. This standard is emulated using complementary LVCMOS outputs in conjunction with a parallel resistor across the driver outputs. The MLVDS input standard is supported by the LVDS differential input buffer. The scheme shown in Figure 3.4 is one possible solution for MLVDS standard implementation. Resistor values in the figure are industry standard values for 1% resistors. 

**==> picture [437 x 185] intentionally omitted <==**

**----- Start of picture text -----**<br>
Heavily loaded backplace, effective Zo~50 Ω to 70 Ω differential<br>2.5 V<br>2.5 V<br>R    = 35 Ω S  R    = 35 Ω S<br>16 mA 16 mA<br>OE R TL 50 Ω to 70 Ω ±1% 50 Ω to 70 Ω ±1% R TR OE<br>2.5 V<br>2.5 V<br>eT 16 mA TE T 1 6 mA<br>R    = 35 Ω S  R    = 35 Ω S<br>OE R    = 35 Ω S  R    = 35 Ω S  R    = 35 Ω S  R    = 35 Ω S  OE<br>+ +<br>–- –<br>A as a mH (<br>< | __+$—+ |<br>2.5 V OE 2.5 V OE 2.5 V OE 2.5 V OE<br>16 mA 16 mA 16 mA 16 mA<br>SESY ASZSF-> Y Lp><br>+ – + –<br>**----- End of picture text -----**<br>


**Figure 3.4. MLVDS25 (Multipoint Low Voltage Differential Signaling)** 

**Table 3.17. MLVDS25 DC Conditions** 

|**Parameter**|**Description**|**Typical**|**Typical**|**Unit**|
|---|---|---|---|---|
|||**Zo=50**|**Zo=70**||
|VCCIO|Output Driver Supply (±5%)|2.50|2.50|V|
|ZOUT<br>~~a~~|Driver Impedance<br>|10.00<br><br>~~ee~~|10.00<br><br>~~ee~~|<br>|
|RS<br>~~ee~~|Driver Series Resistor (±1%)<br>~~ee~~|35.00<br>~~ee~~<br>~~ee~~|35.00<br>~~ee~~<br>~~ee~~|<br>~~ee~~|
|RTL<br>~~ee~~|Driver Parallel Resistor (±1%)<br>~~ee~~|50.00<br>~~ee~~<br>~~ee~~|70.00<br>~~ee~~<br>~~ee~~<br>~~ee~~|<br>~~ee~~|
|RTR<br>~~ee~~<br>~~ee~~|Receiver Termination (±1%)<br>~~ee~~<br>~~ee~~|50.00<br>~~ee~~<br>~~ee ~~<br>~~ee~~|70.00<br>~~ee~~<br> ~~ee~~<br>~~ee~~<br>~~ee~~|<br>~~ee~~<br>~~ee~~|
|VOH<br>~~ee~~|Output High Voltage<br>~~ee~~|1.52<br>~~ee~~|1.60<br>~~ee~~<br>~~ee~~|V<br>~~ee~~|
|VOL<br>~~ee~~<br>~~or~~|Output Low Voltage<br>~~ee~~<br>~~or~~|0.98<br>~~ee~~<br>~~or~~|0.90<br>~~ee~~<br>~~ee~~<br>~~or~~|V<br>~~ee~~<br>~~or~~|
|VOD<br>~~or~~|Output Differential Voltage<br>~~or~~|0.54<br>~~or~~<br>~~ee~~|0.70<br>~~or~~<br>~~ee~~|V<br>~~or~~|
|VCM<br>~~or~~<br>~~ee~~|Output Common Mode Voltage<br>~~or~~<br>~~ee~~|1.25<br>~~or~~<br>~~ee~~<br>~~ee~~|1.25<br>~~or~~<br>~~ee~~<br>~~ee~~|V<br>~~or~~<br>~~ee~~|
|IDC<br>~~ee~~|DC Output Current<br>~~ee~~|21.74<br>~~ee~~<br>~~ee~~|20.00<br>~~ee~~<br>~~ee~~|mA<br>~~ee~~|



© 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

60 

FPGA-DS-02012-2.2 

**ECP5 and ECP5-5G Family Data Sheet** 

## **3.14.8. SLVS** 

Scalable Low-Voltage Signaling (SLVS) is based on a point-to-point signaling method defined in the JEDEC JESD8-13 (SLVS-400) standard. This standard evolved from the traditional LVDS standard and relies on the advantage of its use of smaller voltage swings and a lower common-mode voltage. The 200 mV (400 mV p-p) SLVS swing contributes to a reduction in power. 

The ECP5/ECP5-5G devices can receive differential input up to 800 Mb/s with its LVDS input buffer. This LVDS input buffer is used to meet the SLVS input standard specified by the JEDEC standard. The SLVS output parameters are compared to ECP5/ECP5-5G LVDS input parameters, as listed in Table 3.18. 

**Table 3.18. Input to SLVS** 

|**Parameter**<br>~~—S~~|**ECP5/ECP5-5G LVDS Input**<br>~~—S~~|**SLVS Output**<br>~~—S~~|**Unit**<br>~~—S~~|
|---|---|---|---|
|Vcm (min)<br>~~—S~~|50<br>~~—S~~|150<br>~~—S~~|mV<br>~~—S~~|
|Vcm (max)<br>~~—S~~|2350<br>~~—S~~|250<br>~~—S~~|mV<br>~~—S~~|
|Differential Voltage (min)<br>~~—S~~|100<br>~~—S~~|140<br>~~—S~~|mV<br>~~—S~~|
|Differential Voltage (max)<br>~~—S~~|—<br>~~—S~~|270<br>~~—S~~|mV<br>~~—S~~|



ECP5/ECP5-5G does not support SLVS output. However, SLVS output can be created using ECP5/ECP5-5G LVDS outputs by level shift to meet the low Vcm/Vod levels required by SLVS. Figure 3.5 shows how the LVDS output can be shifted external to meet SLVS levels. 

**==> picture [426 x 213] intentionally omitted <==**

**----- Start of picture text -----**<br>
2.5 V Typical<br>SLVDS<br>R1=220 R3=15<br>R2=47 100 Ω Diff<br>+ +<br>LVDS Z0=50<br>- –<br>R2=47<br>R1=220 R3=15<br>ECP5/ECP5-5G 2.5 V Typical<br>On Chip On Chip<br>SLVDS Peer<br>+ +<br>LVDS Z0=50<br>-– -–<br>**----- End of picture text -----**<br>


**Figure 3.5. SLVS Interface** 

© 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02012-2.2 

61 

**ECP5 and ECP5-5G Family Data Sheet** 

## **3.15. Typical Building Block Function Performance** 

## **Table 3.19. Pin-to-Pin Performance** 

|**Function**|**–8 Timing**|**Unit**|
|---|---|---|
|**Basic Functions**|||
|16-Bit Decoder|5.06|ns|
|32-Bit Decoder|6.08|ns|
|64-Bit Decoder|5.06|ns|
|4:1 Mux|4.45|ns|
|8:1 Mux|4.63|ns|
|16:1 Mux|4.81|ns|
|32:1 Mux|4.85|ns|



## **Notes** : 

1. I/O are configured with LVCMOS25 with VCCIO=2.5, 12 mA drive. 

2. These functions were generated using Lattice Diamond design software tool. Exact performance may vary with the device and the design software tool version. The design software tool uses internal parameters that have been characterized but are not tested on every device. 

3. Commercial timing numbers are shown. Industrial numbers are typically slower and can be extracted from Lattice Diamond design software tool. 

© 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

62 

FPGA-DS-02012-2.2 

**ECP5 and ECP5-5G Family Data Sheet** 

**Table 3.20. Register-to-Register Performance** 

|**Function**<br>~~a~~|**–8 Timing**<br>~~a~~|**Unit**<br>~~a~~|
|---|---|---|
|**Basic Functions**<br>~~pe~~|||
|16-Bit Decoder<br>~~a~~|441<br>~~a~~|MHz<br>~~a~~|
|32-Bit Decoder<br>~~a~~|441<br>~~a~~|MHz<br>~~a~~|
|64-Bit Decoder<br>~~a~~<br>~~pe~~|332<br>~~a~~<br>~~pe~~|MHz<br>~~a~~<br>~~pe~~|
|4:1 Mux<br>~~a~~|441<br>~~a~~|MHz<br>~~a~~|
|8:1 Mux<br>~~a~~<br>~~pe~~|441<br>~~a~~<br>~~pe~~|MHz<br>~~a~~<br>~~pe~~|
|16:1 Mux<br>~~a~~|441<br>~~a~~|MHz<br>~~a~~|
|32:1 Mux<br>~~a~~|441<br>~~a~~|MHz<br>~~a~~|
|8-Bit Adder<br>~~a~~<br>~~a~~|441<br>~~a~~<br>~~a~~|MHz<br>~~a~~<br>~~a~~|
|16-Bit Adder<br>~~a~~|441<br>~~a~~|MHz<br>~~a~~|
|64-Bit Adder<br>~~a~~|441<br>~~a~~|MHz<br>~~a~~|
|16-Bit Counter<br>~~a~~|384<br>~~a~~|MHz<br>~~a~~|
|32-Bit Counter<br>~~a~~|317<br>~~a~~|MHz<br>~~a~~|
|64-Bit Counter<br>~~a~~<br>~~a~~|263<br>~~a~~<br>~~a~~|MHz<br>~~a~~<br>~~a~~|
|64-Bit Accumulator<br>~~a~~|288<br>~~a~~|MHz<br>~~a~~|
|**Embedded Memory Functions**<br>~~pe~~|||
|1024x18 True-Dual Port RAM (Write Through or Normal), with EBR Output Registers<br>~~a~~|272<br>~~a~~|MHz<br>~~a~~|
|1024x18 True-Dual Port RAM (Read-Before-Write), with EBR Output Registers<br>~~a~~|214<br>~~a~~|MHz<br>~~a~~|
|**Distributed Memory Functions**<br>~~a~~<br>~~Pe~~|||
|16 x 2 Pseudo-Dual Port or 16 x 4 Single Port RAM (One PFU)<br>~~a~~|441<br>~~a~~|MHz<br>~~a~~|
|16 x 4 Pseudo-Dual Port (Two PFUs)<br>~~a~~<br>~~a~~|441<br>~~a~~<br>~~a~~|MHz<br>~~a~~<br>~~a~~|
|**DSP Functions**<br>~~Pe~~|||
|9 x 9 Multiplier (All Registers)<br>~~a~~|225<br>~~a~~|MHz<br>~~a~~|
|18 x 18 Multiplier (All Registers)<br>~~a~~|225<br>~~a~~|MHz<br>~~a~~|
|36 x 36 Multiplier (All Registers)<br>~~a~~|225<br>~~a~~|MHz<br>~~a~~|
|18 x 18 Multiply-Add/Sub (All Registers)<br>~~a~~<br>~~ee~~|225<br>~~a~~<br>~~ee~~|MHz<br>~~a~~<br>~~ee~~|
|18 x 18 Multiply/Accumulate (Input and Output Registers)<br>~~a~~|225<br>~~a~~|MHz<br>~~a~~|



- These functions were generated using Lattice Diamond design software tool. Exact performance may vary with the device and the design software tool version. The design software tool uses internal parameters that have been characterized but are not tested on every device. 

- Commercial timing numbers are shown. Industrial numbers are typically slower and can be extracted from Lattice Diamond design software tool. 

## **3.16. Derating Timing Tables** 

Logic timing provided in the following sections of this data sheet and the Diamond design tools are worst case numbers in the operating range. Actual delays at nominal temperature and voltage for best case process, can be much better than the values given in the tables. The Diamond design tool can provide logic timing numbers at a particular temperature and voltage. 

© 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02012-2.2 

63 

**ECP5 and ECP5-5G Family Data Sheet** 

## **3.17. Maximum I/O Buffer Speed** 

Over recommended operating conditions. 

## **Table 3.21. ECP5/ECP5-5G Maximum I/O Buffer Speed** 

|**Buffer**<br>~~Ge~~|**Description**<br>~~Ge~~|**Max**<br>~~Ge~~|**Unit**<br>~~Ge~~|
|---|---|---|---|
|**Maximum Input Frequency**<br>~~Pe~~||||
|LVDS25<br>~~Ge~~|LVDS, VCCIO = 2.5 V<br>~~Ge~~|400<br>~~Ge~~|MHz<br>~~Ge~~|
|MLVDS25<br>~~Ge~~<br>~~Ge~~|MLVDS, Emulated, VCCIO = 2.5 V<br>~~Ge~~<br>~~Ge~~|400<br>~~Ge~~<br>~~Ge~~|MHz<br>~~Ge~~<br>~~Ge~~|
|BLVDS25<br>~~GO~~|BLVDS, Emulated, VCCIO = 2.5 V<br>~~GO~~|400<br>~~GO~~|MHz<br>~~GO~~|
|MIPI D-PHY (HS Mode)<br>~~GO~~<br>~~Ge~~|MIPI Video<br>~~GO~~<br>~~Ge~~|400<br>~~GO~~<br>~~Ge~~|MHz<br>~~GO~~<br>~~Ge~~|
|SLVS<br>~~GO~~|SLVS similar to MIPI<br>~~GO~~|400<br>~~GO~~|MHz<br>~~GO~~|
|Mini LVDS<br>~~GO~~<br>~~a~~|Mini LVDS<br>~~GO~~|400<br>~~GO~~|MHz<br>~~GO~~|
|LVPECL33<br>~~a~~|LVPECL, Emulated, VCCIO = 3.3 V<br>~~Ge~~|400<br>~~Ge~~|MHz<br>~~Ge~~|
|SSTL18 (all supported classes)<br>~~Ge~~|SSTL_18 class I, II, VCCIO = 1.8 V<br>~~Ge~~|400<br>~~Ge~~|MHz<br>~~Ge~~|
|SSTL15 (all supported classes)<br>~~Ge~~|SSTL_15 class I, II, VCCIO = 1.5 V<br>~~Ge~~|400<br>~~Ge~~|MHz<br>~~Ge~~|
|SSTL135 (all supported classes)<br>~~GO~~|SSTL_135 class I, II, VCCIO = 1.35 V<br>~~GO~~|400<br>~~GO~~|MHz<br>~~GO~~|
|HSUL12 (all supported classes)<br>~~GO~~<br>~~Ge~~|HSUL_12 class I, II, VCCIO = 1.2 V<br>~~GO~~<br>~~Ge~~|400<br>~~GO~~<br>~~Ge~~|MHz<br>~~GO~~<br>~~Ge~~|
|LVTTL33<br>~~Ge~~|LVTTL, VCCIO = 3.3 V<br>~~Ge~~|200<br>~~Ge~~|MHz<br>~~Ge~~|
|LVCMOS33<br>~~Ge~~|LVCMOS, VCCIO = 3.3 V<br>~~Ge~~|200<br>~~Ge~~|MHz<br>~~Ge~~|
|LVCMOS25<br>~~Ge~~<br>~~Ge~~|LVCMOS, VCCIO = 2.5 V<br>~~Ge~~<br>~~Ge~~|200<br>~~Ge~~<br>~~Ge~~|MHz<br>~~Ge~~<br>~~Ge~~|
|LVCMOS18<br>~~Ge~~|LVCMOS, VCCIO = 1.8 V<br>~~Ge~~|200<br>~~Ge~~|MHz<br>~~Ge~~|
|LVCMOS15<br>~~Ge~~<br>~~a~~|LVCMOS 1.5, VCCIO = 1.5 V<br>~~Ge~~|200<br>~~Ge~~|MHz<br>~~Ge~~|
|LVCMOS12<br>~~Ge~~|LVCMOS 1.2, VCCIO = 1.2 V<br>~~Ge~~|200<br>~~Ge~~|MHz<br>~~Ge~~|
|**Maximum Output Frequency**<br>~~pT~~||||
|LVDS25E<br>~~Ge~~|LVDS, Emulated, VCCIO = 2.5 V<br>~~Ge~~|150<br>~~Ge~~|MHz<br>~~Ge~~|
|LVDS25<br>~~eG~~|LVDS, VCCIO = 2.5 V<br>~~eG~~|400<br>~~eG~~|MHz<br>~~eG~~|
|MLVDS25<br>~~eG~~<br>~~Ge~~|MLVDS, Emulated, VCCIO = 2.5 V<br>~~eG~~<br>~~Ge~~|150<br>~~eG~~<br>~~Ge~~|MHz<br>~~eG~~<br>~~Ge~~|
|BLVDS25<br>~~a~~|BLVDS, Emulated, VCCIO = 2.5 V<br>~~G~~|150|MHz|
|LVPECL33<br>~~a~~<br>~~Ge~~|LVPECL, Emulated, VCCIO = 3.3 V<br>~~G~~<br>~~Ge~~|150<br>~~Ge~~|MHz<br>~~Ge~~|
|SSTL18 (all supported classes)<br>~~Ge~~|SSTL_18 class I, II, VCCIO = 1.8 V<br>~~Ge~~|400<br>~~Ge~~|MHz<br>~~Ge~~|
|SSTL15 (all supported classes)<br>~~eG~~|SSTL_15 class I, II, VCCIO = 1.5 V<br>~~eG~~|400<br>~~eG~~|MHz<br>~~eG~~|
|SSTL135 (all supported classes)<br>~~eG~~<br>~~Ge~~|SSTL_135 class I, II, VCCIO = 1.35 V<br>~~eG~~<br>~~Ge~~|400<br>~~eG~~<br>~~Ge~~|MHz<br>~~eG~~<br>~~Ge~~|
|HSUL12 (all supported classes)<br>~~eG~~|HSUL12 class I, II, VCCIO = 1.2 V<br>~~eG~~|400<br>~~eG~~|MHz<br>~~eG~~|
|LVTTL33<br>~~eG~~<br>~~a~~|LVTTL, VCCIO= 3.3 V<br>~~eG~~<br>~~Ge~~|150<br>~~eG~~<br>~~Ge~~|MHz<br>~~eG~~<br>~~Ge~~|
|LVCMOS33 (For all drives)<br>~~eG~~|LVCMOS, 3.3 V<br>~~eG~~|150<br>~~eG~~|MHz<br>~~eG~~|
|LVCMOS25 (For all drives)<br>~~eG~~<br>~~Ge~~|LVCMOS, 2.5 V<br>~~eG~~<br>~~Ge~~|150<br>~~eG~~<br>~~Ge~~|MHz<br>~~eG~~<br>~~Ge~~|
|LVCMOS18 (For all drives)<br>~~Ge~~<br>~~Ge~~|LVCMOS, 1.8 V<br>~~Ge~~<br>~~Ge~~|150<br>~~Ge~~<br>~~Ge~~|MHz<br>~~Ge~~<br>~~Ge~~|
|LVCMOS15 (For all drives)<br>~~a~~|LVCMOS, 1.5 V<br>~~G~~|150|MHz|
|LVCMOS12 (For all drives)<br>~~a~~<br>~~De~~|LVCMOS, 1.2 V<br>~~G~~<br>~~De~~|150<br>~~De~~|MHz<br>~~De~~|



## **Notes** : 

- These maximum speeds are characterized but not tested on every device. 

- Maximum I/O speed for differential output standards emulated with resistors depends on the layout. 

- LVCMOS timing is measured with the load specified in Table 3.44. 

- All speeds are measured at fast slew. 

- Actual system operation may vary depending on user logic implementation. 

- Maximum data rate equals 2 times the clock rate when utilizing DDR. 

- MIPI D-PHY HS mode receiver runs 400 MHz as LVDS25. It may exceed ±0.15 UI setup/hold budget at data rate of ≤1 Gbps MIPI Alliance Specification. 

© 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02012-2.2 

64 

**ECP5 and ECP5-5G Family Data Sheet** 

## **3.18. External Switching Characteristics** 

Over recommended commercial operating conditions. 

**Table 3.22. ECP5/ECP5-5G External Switching Characteristics** 

|**Parameter**<br>~~ee~~|**Description**<br>~~ee~~|**Device**<br>~~ee~~|**–8**<br>~~ee~~|**–8**<br>~~ee~~|**–7**<br>~~ee~~|**–7**<br>~~ee~~|**–6**<br>~~ee~~|**–6**<br>~~ee~~|**Unit**<br>~~ee~~|
|---|---|---|---|---|---|---|---|---|---|
||||**Min**<br>~~ee~~|**Max**<br>~~ee~~|**Min**<br>~~ee~~|**Max**<br>~~ee~~|**Min**<br>~~ee~~|**Max**<br>~~ee~~||
|**Clocks**<br>~~ee~~<br>~~ER~~||||||||||
|**Primary Clock**<br>~~ee~~||||||||||
|fMAX_PRI<br>~~ee~~|Frequencyfor PrimaryClock Tree<br>~~ee~~|—<br>~~ee~~|—<br>~~ee~~|370<br>~~ee~~|—<br>~~ee~~|303<br>~~ee~~|—<br>~~ee~~|257<br>~~ee~~|MHz<br>~~ee~~|
|tW_PRI<br>~~a ee~~|Clock Pulse Width for Primary<br>Clock<br>~~ee~~|—<br>~~ee~~|0.8<br>~~ee~~|—<br>~~ee~~|0.9<br>~~ee~~|—<br>~~ee~~|1.0<br>~~ee~~|—<br>~~ee~~|ns<br>~~ee~~|
|tSKEW_PRI<br>~~a~~|Primary Clock Skew within a<br>Device<br>~~ee~~|—<br>~~ee~~|—<br>~~ee~~|420<br>~~ee~~|—<br>~~ee~~|462<br>~~ee~~|—<br>~~ee~~|505<br>~~ee~~|ps<br>~~ee~~|
|**Edge Clock**||||||||||
|fMAX_EDGE<br>~~po~~|Frequencyfor Edge Clock Tree<br>~~po~~|—<br>~~po~~|—<br>~~po~~|400<br>~~po~~|—<br>~~po~~|350<br>~~po~~|—<br>~~po~~|312<br>~~po~~|MHz<br>~~po~~|
|tW_EDGE<br>~~po~~<br>~~ee~~|Clock Pulse Width for Edge Clock<br>~~po~~<br>~~GGG~~|—<br>~~po~~<br>~~GGG~~|1.175<br>~~po~~<br>~~GGG~~|—<br>~~po~~<br>~~GGG~~|1.344<br>~~po~~<br>~~GGG~~<br>~~GO~~|—<br>~~po~~<br>~~GGG~~<br>~~GO~~|1.50<br>~~po~~<br>~~GGG~~<br>~~GO~~|—<br>~~po~~<br>~~GGG~~|ns<br>~~po~~<br>~~GGG~~|
|tSKEW_EDGE<br>~~ee~~|Edge Clock Skew within a Bank<br>~~GGG~~|—<br>~~GGG~~|—<br>~~GGG~~|160<br>~~GGG~~|—<br>~~GGG~~<br>~~GO~~|180<br>~~GGG~~<br>~~GO~~|—<br>~~GGG~~<br>~~GO~~|200<br>~~GGG~~|ps<br>~~GGG~~|
|**Generic SDR Input**<br>~~eeGGG~~<br>~~GO~~||||||||||
|**General I/O Pin Parameters Using Dedicated Primary Clock Input without PLL**||||||||||
|tCO<br>~~Pe~~<br>~~Ps~~|Clock to Output - PIO Output<br>Register<br>~~Pe~~|All<br>Devices<br>~~Pe~~|—<br>~~Pe~~|5.4<br>~~Pe~~|—<br>~~Pe~~|6.1<br>~~Pe~~|—<br>~~Pe~~|6.8<br>~~Pe~~|ns<br>~~Pe~~|
|tSU<br>~~Ps~~<br>~~Ss~~|Clock to Data Setup - PIO Input<br>Register|All<br>Devices|0|—|0|—|0|—|ns|
|tH<br>~~Ps~~<br>~~Ss~~|Clock to Data Hold - PIO Input<br>Register|All<br>Devices|2.7|—|3|—|3.3|—|ns|
|tSU_DEL<br>~~Ss~~<br>~~a~~|Clock to Data Setup - PIO Input<br>Register with Data Input Delay|All<br>Devices|1.2|—|1.33|—|1.46|—|ns|
|tH_DEL<br>~~a~~<br>~~a~~|Clock to Data Hold - PIO Input<br>Register with Data Input Delay|All<br>Devices|0|—|0|—|0|—|ns|
|fMAX_IO<br>~~a~~<br>~~a~~|Clock Frequency of I/O and PFU<br>Register|All<br>Devices|—|400|—|350|—|312|MHz|
|**General I/O Pin Parameters Using Dedicated Primary Clock Input with PLL**<br>~~a~~||||||||||
|tCOPLL<br>~~a~~|Clock to Output - PIO Output<br>Register<br>~~se~~|All<br>Devices<br>~~se~~|—<br>~~se~~|3.5<br>~~se~~|—<br>~~se~~|3.8<br>~~se~~|—<br>~~se~~|4.1<br>~~se~~|ns<br>~~se~~|
|tSUPLL<br>~~a~~<br>~~a~~|Clock to Data Setup - PIO Input<br>Register<br>~~se~~|All<br>Devices<br>~~se~~|0.7<br>~~se~~|—<br>~~se~~|0.78<br>~~se~~|—<br>~~se~~|0.85<br>~~se~~|—<br>~~se~~|ns<br>~~se~~|
|tHPLL<br>~~a~~<br>~~a~~|Clock to Data Hold - PIO Input<br>Register<br>|All<br>Devices<br>|0.8<br>|—<br>|0.89<br>|—<br>|0.98<br>|—<br>|ns<br>|
|tSU_DELPLL<br>~~apo~~|Clock to Data Setup - PIO Input<br>Register with Data Input Delay<br>~~po~~|All<br>Devices<br>~~po~~|1.6<br>~~po~~|—<br>~~po~~|1.78<br>~~po~~|—<br>~~po~~|1.95<br>~~po~~|—<br>~~po~~|ns<br>~~po~~|



© 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02012-2.2 

65 

**ECP5 and ECP5-5G Family Data Sheet** 

**Table 3.22. ECP5/ECP5-5G External Switching Characteristics** 

|**Parameter**<br>~~a~~|**Description**<br>~~a~~|**Description**<br>~~a~~|**Device**<br>~~ce~~|**Device**<br>~~ce~~|**–8**<br>~~ce~~|**–8**<br>~~ce~~|**–8**<br>~~ce~~|**–8**<br>~~ce~~|**–7**<br>~~ee~~|**–7**<br>~~ee~~|**–7**<br>~~ee~~|**–6**<br>~~ee~~|**–6**<br>~~ee~~|**Unit**<br>~~ee~~|
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
||||||**Min**<br>~~ce~~||**Max**<br>~~ce~~||**Min**<br>~~ee~~||**Max**<br>~~ee~~|**Min**<br>~~ee~~|**Max**<br>~~ee~~||
|tH_DELPLL<br>~~a~~|Clock to Data Hold - PIO Input<br>Register with Data Input Delay<br>~~a~~<br>~~a~~||All Devices<br>~~a~~<br>~~a~~||0<br>~~a~~<br>~~a~~||—<br>~~a~~<br>~~a~~||0<br>~~a~~<br>~~a~~||—<br>~~a~~<br>~~a~~|0<br>~~a~~<br>~~a~~|—<br>~~a~~<br>~~a~~|ns<br>~~a~~<br>~~a~~|
|**Generic DDR Input**|||||||||||||||
|**Generic DDRX1 Inputs With Clock and Data Centered at Pin (GDDRX1_RX.SCLK.Centered) Using PCLK Clock Input -Figure 3.6**<br>~~a~~|||||||||||||||
|tSU_GDDRX1_centered<br>~~a~~|Data SetupBefore CLK Input<br>~~a~~<br>~~YC~~||All Devices<br>~~a~~<br>~~YC~~||0.52<br>~~a~~||—<br>~~a~~<br>~~OO~~||0.52<br>~~a~~<br>~~OO~~||—<br>~~a~~<br>~~OO~~|0.52<br>~~a~~|—<br>~~a~~|ns<br>~~a~~|
|tHD_GDDRX1_centered<br>~~a~~|Data Hold After CLK Input<br>~~a~~||All Devices<br>~~a~~||0.52<br>~~a~~||—<br>~~a~~||0.52<br>~~a~~||—<br>~~a~~|0.52<br>~~a~~|—<br>~~a~~|ns<br>~~a~~|
|fDATA_GDDRX1_centered<br>~~a~~<br>~~a~~|GDDRX1 Data Rate<br>~~a~~<br>~~a~~||All Devices<br>~~a~~<br>~~a~~||—<br>~~a~~<br>~~a~~||500<br>~~a~~<br>~~a~~||—<br>~~a~~<br>~~a~~||500<br>~~a~~<br>~~a~~|—<br>~~a~~<br>~~a~~|500<br>~~a~~<br>~~a~~|Mb/s<br>~~a~~<br>~~a~~|
|fMAX_GDDRX1_centered<br>~~a~~<br>~~a~~|GDDRX1 CLK Frequency (SCLK)<br>~~a~~<br>~~a~~||All Devices<br>~~a~~<br>~~a~~||—<br>~~a~~<br>~~a~~||250<br>~~a~~<br>~~a~~||—<br>~~a~~<br>~~a~~||250<br>~~a~~<br>~~a~~|—<br>~~a~~<br>~~a~~|250<br>~~a~~<br>~~a~~|MHz<br>~~a~~<br>~~a~~|
|**Generic DDRX1 Inputs With Clock and Data Aligned at Pin (GDDRX1_RX.SCLK.Aligned) Using PCLK Clock Input -Figure 3.7**<br>~~a~~<br>~~pC~~|||||||||||||||
|tSU_GDDRX1_aligned<br>~~pC~~<br>~~a~~|Data Setup from CLK Input<br>~~pC~~||All Devices<br>~~pC~~||—<br>~~pC~~||–0.55<br>~~pC~~||—<br>~~pC~~||–0.55<br>~~pC~~|—<br>~~pC~~|–0.55<br>~~pC~~|ns +<br>1/2 UI<br>~~pC~~|
|tHD_GDDRX1_aligned<br>~~a~~<br>~~a~~|Data Hold from CLK Input||All Devices||0.55||—||0.55||—|0.55|—|ns +<br>1/2 UI|
|fDATA_GDDRX1_aligned<br>~~a~~<br>~~a~~|GDDRX1 Data Rate<br>~~SO~~||All Devices<br>~~SO~~||—||500||—||500|—|500|Mb/s|
|fMAX_GDDRX1_aligned<br>~~a~~|GDDRX1 CLK Frequency (SCLK)<br>~~a~~||All Devices<br>~~a~~||—<br>~~a~~||250<br>~~a~~||—<br>~~a~~||250<br>~~a~~|—<br>~~a~~|250<br>~~a~~|MHz<br>~~a~~|
|**Generic DDRX2 Inputs With Clock and Data Centered at Pin (GDDRX2_RX.ECLK.Centered) Using PCLK Clock Input, Left and**<br>**Right sides Only -Figure 3.6**<br>~~a~~<br>~~ee~~|||||||||||||||
|tSU_GDDRX2_centered<br>~~ee~~|Data Setupbefore CLK Input<br>~~ee~~||All Devices<br>~~ee~~||0.321<br>~~ee~~||—<br>~~ee~~||0.403<br>~~ee~~||—<br>~~ee~~|0.471<br>~~ee~~|—<br>~~ee~~|ns<br>~~ee~~|
|tHD_GDDRX2_centered<br>~~a ~~|Data Hold after CLK Input<br> ~~COO~~||All Devices<br>~~COO~~||0.321<br>~~COO~~||—<br>~~COO~~||0.403<br>~~COO~~||—<br>~~COO~~|0.471<br>~~COO~~|—<br>~~COO~~|ns<br>~~COO~~|
|fDATA_GDDRX2_centered<br>~~a~~|GDDRX2 Data Rate<br>~~a~~||All Devices<br>~~a~~||—<br>~~a~~||800<br>~~a~~||—<br>~~a~~||700<br>~~a~~|—<br>~~a~~|624<br>~~a~~|Mb/s<br>~~a~~|
|fMAX_GDDRX2_centered<br>~~a~~<br>~~a~~|GDDRX2 CLK Frequency (ECLK)<br>~~a~~<br>~~a~~||All Devices<br>~~a~~<br>~~a~~||—<br>~~a~~<br>~~a~~||400<br>~~a~~<br>~~a~~||—<br>~~a~~<br>~~a~~||350<br>~~a~~<br>~~a~~|—<br>~~a~~<br>~~a~~|312<br>~~a~~<br>~~a~~|MHz<br>~~a~~<br>~~a~~|
|**Generic DDRX2 Inputs With Clock and Data Aligned at Pin (GDDRX2_RX.ECLK.Aligned) Using PCLK Clock Input, Left and Right**<br>**sides Only -Figure 3.7**<br>~~a~~|||||||||||||||
|tSU_GDDRX2_aligned<br>~~a~~||Data Setup from CLK Input<br>~~a~~|All Devices<br>~~a~~|—<br>~~a~~||–0.344<br>~~a~~||—<br>~~a~~||–0.42<br>~~a~~||—<br>~~a~~|-0.495<br>~~a~~|ns + 1/2<br>UI<br>~~a~~|
|tHD_GDDRX2_aligned<br>~~a~~||Data Hold from CLK Input<br>~~a~~<br>~~ee~~|All Devices<br>~~a~~<br>~~ee~~|0.344<br>~~a~~<br>~~ee~~||—<br>~~a~~<br>~~ee~~||0.42<br>~~a~~<br>~~ee~~||—<br>~~a~~<br>~~ee~~||0.495<br>~~a~~<br>~~ee~~|—<br>~~a~~<br>~~ee~~|ns + 1/2<br>UI<br>~~a~~<br>~~ee~~|
|fDATA_GDDRX2_aligned<br>~~a~~||GDDRX2 Data Rate<br>~~a~~|All Devices|—<br>~~GG~~||800<br>~~GG~~||—<br>~~GG~~||700<br>~~GG~~||—<br>~~GG~~|624|Mb/s|
|fMAX_GDDRX2_aligned<br>~~a~~<br>~~a~~||GDDRX2 CLK Frequency<br>~~a~~<br>~~a~~|All Devices<br>~~a~~|—<br>~~GG~~<br>~~a~~||400<br>~~GG~~<br>~~a~~||—<br>~~GG~~<br>~~a~~||350<br>~~GG~~<br>~~a~~||—<br>~~GG~~<br>~~a~~|312<br>~~a~~|MHz<br>~~a~~|
|**Video DDRX71 Inputs With Clock and Data Aligned at Pin (GDDRX71_RX.ECLK) Using PLL Clock Input, Left and Right sides Only**<br>**Figure 3.11**<br>~~a~~|||||||||||||||
|tSU_LVDS71_i<br>~~a~~||Data Setup from CLK Input<br>(bit i)<br>~~a~~<br>~~ee~~|All Devices<br>~~a~~<br>~~ee~~|—<br>~~a~~||–0.271<br>~~a~~||—<br>~~a~~||–0.39<br>~~a~~||—<br>~~a~~|–0.41<br>~~a~~|ns+(1/2+i)<br>* UI<br>~~a~~|
|tHD_LVDS71_i<br>~~a~~||Data Hold from CLK Input<br>(bit i)<br>~~a~~|All Devices<br>~~a~~|0.271<br>~~a~~||—<br>~~a~~||0.39<br>~~a~~||—<br>~~a~~||0.41<br>~~a~~|—<br>~~a~~|ns+(1/2+i)<br>*  UI<br>~~a~~|
|fDATA_LVDS71<br>~~a~~||DDR71 Data Rate<br>~~a~~|All Devices<br>~~a~~|—<br>~~a~~||756<br>~~a~~||—<br>~~a~~||620<br>~~a~~||—<br>~~a~~|525<br>~~a~~|Mb/s<br>~~a~~|
|fMAX_LVDS71<br>~~a~~<br>~~a~~||DDR71 CLK Frequency (ECLK)<br>~~a~~<br>~~a~~|All Devices<br>~~a~~<br>~~a~~|—<br>~~a~~<br>~~a~~||378<br>~~a~~<br>~~a~~||—<br>~~a~~<br>~~a~~||310<br>~~a~~<br>~~a~~||—<br>~~a~~<br>~~a~~|262.5<br>~~a~~<br>~~a~~|MHz<br>~~a~~<br>~~a~~|



© 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02012-2.2 

66 

**ECP5 and ECP5-5G Family Data Sheet** 

**Table 3.22. ECP5/ECP5-5G External Switching Characteristics** 

|**Parameter**<br>~~a~~|**Description**<br>~~ee~~|**Device**<br>~~ee es~~|**Device**<br>~~ee es~~|**–8**<br>~~es~~|**–8**<br>~~es~~|**–7**|**–7**|**–6**|**–6**|**Unit**|
|---|---|---|---|---|---|---|---|---|---|---|
|||||**Min**<br>~~es~~|**Max**|**Min**|**Max**|**Min**|**Max**||
|**Generic DDR Output**<br>~~a~~<br>~~ee ee es~~<br>~~SSE~~|||||||||||
|**Generic DDRX1 Outputs With Clock and Data Centered at Pin(GDDRX1_TX.SCLK.Centered) Using PCLK Clock Input -Figure 3.6**<br>~~a~~|||||||||||
|tDVB_GDDRX1_centered<br>~~a~~|Data Output Valid before CLK<br>Output<br>~~a~~|All Devices<br>~~a~~|–0.67<br>~~a~~||—<br>~~a~~|–0.67<br>~~a~~|—<br>~~a~~|–0.67<br>~~a~~|—<br>~~a~~|ns +<br>1/2 UI<br>~~a~~|
|tDVA_GDDRX1_centered<br>~~Ss~~|Data Output Valid after CLK<br>Output<br>~~Ss~~|All Devices<br>~~Ss~~|–0.67<br>~~Ss~~||—<br>~~Ss~~|–0.67<br>~~Ss~~|—<br>~~Ss~~|–0.67<br>~~Ss~~|—<br>~~Ss~~|ns +<br>1/2 UI<br>~~Ss~~|
|fDATA_GDDRX1_centered<br>~~a~~|GDDRX1 Data Rate<br>~~a~~|All Devices<br>~~a~~|—<br>~~a~~||500<br>~~a~~|—<br>~~a~~|500<br>~~a~~|—<br>~~a~~|500<br>~~a~~|Mb/s<br>~~a~~|
|fMAX_GDDRX1_centered<br>~~a~~<br>~~Ce~~|GDDRX1 CLK Frequency (SCLK)<br>~~a~~<br>|All Devices<br>~~a~~<br>|—<br>~~a~~<br>||250<br>~~a~~<br>|—<br>~~a~~<br>|250<br>~~a~~<br>|—<br>~~a~~<br>|250<br>~~a~~<br>|MHz<br>~~a~~<br>|
|**Generic DDRX1 Outputs With Clock and Data Aligned at Pin (GDDRX1_TX.SCLK.Aligned) Using PCLK Clock Input -Figure 3.9**<br>~~a~~<br>~~Ceaeeeeeeee~~|||||||||||
|tDIB_GDDRX1_aligned<br>~~Cea~~<br>~~**a**~~|Data Output Invalid before<br>CLKOutput<br>~~ee~~<br>~~ee~~|All Devices<br>~~eee~~<br>~~ee~~|–0.3<br>~~eee~~<br>~~ee~~||—<br>~~eee~~<br>~~eee~~|–0.3<br>~~eee~~<br>~~eee~~|—<br>~~eee~~<br>~~eee ee~~|–0.3<br>~~eee~~<br>~~ee~~|—<br>~~eee~~<br>~~ee~~|ns<br>~~eee~~<br>~~ee~~|
|tDIA_GDDRX1_aligned<br>~~a ~~<br>~~**a**~~|Data Output Invalid after CLK<br>Output<br> ~~ee ~~<br>~~ee~~|All Devices<br> ~~eee~~<br>~~ee~~|—<br>~~eee~~<br>~~ee~~||0.3<br>~~eee~~<br>~~eee~~|—<br>~~eee~~<br>~~eee~~|0.3<br>~~eee~~<br>~~eee ee~~|—<br>~~eee~~<br>~~ee~~|0.3<br>~~eee~~<br>~~ee~~|ns<br>~~eee~~<br>~~ee~~|
|fDATA_GDDRX1_aligned<br>~~**a**~~|GDDRX1 Data Rate<br>~~ee ~~|All Devices<br> ~~ee~~<br>~~a~~|—<br>~~ee ~~<br>~~a~~||500<br> ~~eee~~<br>~~a~~|—<br>~~eee~~<br>~~a~~|500<br>~~eee ee~~<br>~~a~~|—<br>~~ee~~<br>~~a~~|500<br>~~ee~~<br>~~a~~|Mb/s<br>~~ee~~<br>~~a~~|
|fMAX_GDDRX1_aligned<br>~~a~~|GDDRX1 CLK Frequency (SCLK)<br>~~a~~|All Devices<br>~~a~~<br>~~a~~|—<br>~~a~~<br>~~a~~||250<br>~~a~~<br>~~a~~|—<br>~~a~~<br>~~a~~|250<br>~~a~~<br>~~a~~|—<br>~~a~~<br>~~a~~|250<br>~~a~~<br>~~a~~|MHz<br>~~a~~<br>~~a~~|
|**Generic DDRX2 Outputs With Clock and Data Centered at Pin (GDDRX2_TX.ECLK.Centered) Using PCLK Clock Input, Left and**<br>**Right sides Only -Figure 3.8**<br>~~a~~<br>~~rreeeee~~<br>~~eee~~<br>~~a~~|||||||||||
|tDVB_GDDRX2_centered<br>~~rr~~<br>~~a~~|Data Output Valid Before CLK<br>Output<br>~~ee~~|All Devices<br>~~eee~~|–<br>0.442<br>~~eee~~||—<br>~~eee~~|–0.56<br>~~eee~~|—<br>~~eee~~|–<br>0.676<br>~~eee~~<br>~~eee~~|—<br>~~eee~~<br>~~eee~~|ns +<br>1/2 UI<br>~~eee~~<br>~~eee~~|
|tDVA_GDDRX2_centered<br>~~rr ~~<br>~~a~~|Data Output Valid After CLK<br>Output<br> ~~ee ~~<br>~~ee~~|All Devices<br> ~~eee~~<br>~~ee~~|—<br>~~eee~~<br>~~ee~~||0.442<br>~~eee~~<br>~~ee~~|—<br>~~eee~~<br>~~ee~~|0.56<br>~~eee~~<br>~~ee~~|—<br>~~eee~~<br>~~eee~~<br>~~ee~~|0.676<br>~~eee~~<br>~~eee~~<br>~~ee~~|ns +<br>1/2 UI<br>~~eee~~<br>~~eee~~<br>~~ee~~|
|fDATA_GDDRX2_centered<br>~~a~~<br>~~a~~|GDDRX2 Data Rate<br>~~ee~~<br>~~a~~|All Devices<br>~~ee~~<br>~~a~~<br>~~a~~|—<br>~~ee~~<br>~~a~~<br>~~a~~||800<br>~~ee~~<br>~~a~~|—<br>~~ee~~<br>~~a~~|700<br>~~ee~~<br>~~a~~|—<br>~~eee~~<br>~~ee~~<br>~~a~~|624<br>~~eee~~<br>~~ee~~<br>~~a~~|Mb/s<br>~~eee~~<br>~~ee~~<br>~~a~~|
|fMAX_GDDRX2_centered<br>~~a~~<br>~~a~~|GDDRX2 CLK Frequency (ECLK)<br>~~a~~<br>~~a~~|All Devices<br>~~a~~<br>~~a~~<br>~~a~~|—<br>~~a~~<br>~~a~~<br>~~a~~||400<br>~~a~~<br>~~a~~|—<br>~~a~~<br>~~a~~|350<br>~~a~~<br>~~a~~|—<br>~~a~~<br>~~a~~|312<br>~~a~~<br>~~a~~|MHz<br>~~a~~<br>~~a~~|
|**Generic DDRX2 Outputs With Clock and Data Aligned at Pin (GDDRX2_TX.ECLK.Aligned) Using PCLK Clock Input, Left and Right**<br>**sides Only -Figure 3.9**<br>~~a~~<br>~~)~~|||||||||||
|tDIB_GDDRX2_aligned<br>~~a~~|Data Output Invalid before<br>CLKOutput<br>~~a~~<br>~~ee~~|All Devices<br>~~a~~<br>~~ee ~~|–0.16<br>~~a~~<br> ~~ee~~||—<br>~~a~~<br>~~ee~~|–0.18<br>~~a~~|—<br>~~a~~|–0.2<br>~~a~~|—<br>~~a~~|ns<br>~~a~~|
|tDIA_GDDRX2_aligned<br>~~a~~|Data Output Invalid after CLK<br>Output<br>~~a~~|All Devices<br>~~a~~<br>~~a~~|—<br>~~a~~<br>~~a~~||0.16<br>~~a~~<br>~~a~~|—<br>~~a~~|0.18<br>~~a~~|—<br>~~a~~|0.2<br>~~a~~|ns<br>~~a~~|
|fDATA_GDDRX2_aligned<br>~~a~~|GDDRX2 Data Rate<br>~~a~~|All Devices<br>~~a~~<br>~~a~~|—<br>~~a~~<br>~~a~~||800<br>~~a~~<br>~~a~~|—<br>~~a~~|700<br>~~a~~|—<br>~~a~~|624<br>~~a~~|Mb/s<br>~~a~~|
|fMAX_GDDRX2_aligned<br>~~rer~~|GDDRX2 CLK Frequency (ECLK)<br>~~rer~~|All Devices<br>~~a~~<br>~~rer~~|—<br>~~a~~<br>~~rer~~||400<br>~~a~~<br>~~rer~~|—<br>~~rer~~|350<br>~~rer~~|—<br>~~rer~~|312<br>~~rer~~|MHz<br>~~rer~~|
|**Video DDRX71 Outputs With Clock and Data Aligned at Pin (GDDRX71_TX.ECLK) Using PLL Clock Input, Left and Right sides Only**<br>**-Figure 3.12**<br>~~)~~<br>~~Pses~~|||||||||||
|tDIB_LVDS71_i<br>~~Pses~~|Data Output Invalid before<br>CLKOutput<br>~~es~~|All Devices<br>~~es~~|–0.16<br>~~es~~||—<br>~~es~~|–0.18<br>~~es~~|—<br>~~es~~|–0.2<br>~~es~~|—<br>~~es~~|ns +<br>(i)*UI<br>~~es~~|
|tDIA_LVDS71_i<br>~~Pses~~<br>~~Pe~~|Data Output Invalid after CLK<br>Output<br>~~es~~<br>~~Pe~~|All Devices<br>~~es~~<br>~~Pe~~|—<br>~~es~~<br>~~Pe~~||0.16<br>~~es~~<br>~~Pe~~|—<br>~~es~~<br>~~Pe~~|0.18<br>~~es~~<br>~~Pe~~|—<br>~~es~~<br>~~Pe~~|0.2<br>~~es~~<br>~~Pe~~|(i)<br>ns +<br>(i)*UI<br>~~es~~<br>~~Pe~~|
|fDATA_LVDS71<br>~~Pe~~<br>~~a~~|DDR71 Data Rate<br>~~Pe~~<br>~~a~~|All Devices<br>~~Pe~~<br>~~a~~|—<br>~~Pe~~<br>~~a~~||756<br>~~Pe~~<br>~~a~~|—<br>~~Pe~~<br>~~a~~|620<br>~~Pe~~<br>~~a~~|—<br>~~Pe~~<br>~~a~~|525<br>~~Pe~~<br>~~a~~|(i)<br>Mb/s<br>~~Pe~~<br>~~a~~|
|fMAX_LVDS71<br>~~a~~<br>~~a~~|DDR71 CLK Frequency (ECLK)<br>~~a~~<br>~~a~~|All Devices<br>~~a~~<br>~~a~~|—<br>~~a~~<br>~~a~~||378<br>~~a~~<br>~~a~~|—<br>~~a~~<br>~~a~~|310<br>~~a~~<br>~~a~~|—<br>~~a~~<br>~~a~~|262.5<br>~~a~~<br>~~a~~|MHz<br>~~a~~<br>~~a~~|
|**Memory Interface**<br>~~a~~<br>~~a~~<br>~~OEEEEE~~|||||||||||
|**DDR2/DDR3/DDR3L/LPDDR2/LPDDR3 READ(DQ Input Data are Aligned to DQS)**<br>~~a~~<br>~~OEEEEE~~|||||||||||
|tDVBDQ_DDR2<br>tDVBDQ_DDR3<br>tDVBDQ_DDR3L<br>tDVBDQ_LPDDR2<br>tDVBDQ_LPDDR3<br>~~OEE~~|Data Output Valid before DQS<br>Input<br>~~OEE~~|All Devices<br>~~OEE~~|—<br>~~E~~||–0.26<br>~~E~~|—<br>~~EEE~~|–<br>0.317<br>~~EE~~|—<br>~~EE~~|–<br>0.374<br>~~EE~~|ns + 1/2<br>UI<br>~~EE~~|
|tDVADQ_DDR2<br>tDVADQ_DDR3<br>tDVADQ_DDR3L<br>tDVADQ_LPDDR2<br>tDVADQ_LPDDR3|Data Output Valid after DQS<br>Input|All Devices|0.26||—|0.317|—|0.374|—|ns + 1/2<br>UI|



© 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02012-2.2 

67 

|**Parameter**<br>~~PTT~~|**Description**<br>~~PTT~~|**Device**<br>~~PTT~~|**–8**<br>~~PTT~~|**–8**<br>~~PTT~~|**–7**<br>~~PTT~~|**–7**<br>~~PTT~~|**–6**<br>~~PTT~~|**–6**<br>~~PTT~~|**Unit**<br>~~PTT~~|
|---|---|---|---|---|---|---|---|---|---|
||||**Min**<br>~~PTT~~|**Max**<br>~~PTT~~|**Min**<br>~~PTT~~|**Max**<br>~~PTT~~|**Min**<br>~~PTT~~|**Max**<br>~~PTT~~||
|fDATA_DDR2<br>fDATA_DDR3<br>fDATA_DDR3L<br>fDATA_LPDDR2<br>fDATA_LPDDR3<br>~~PTT~~|DDR Memory Data Rate<br>~~PTT~~|All Devices<br>~~PTT~~|—<br>~~PTT~~|800<br>~~PTT~~|—<br>~~PTT~~|700<br>~~PTT~~|—<br>~~PTT~~|624<br>~~PTT~~|Mb/s<br>~~PTT~~|
|fMAX_DDR2<br>fMAX_DDR3<br>fMAX_DDR3L<br>fMAX_LPDDR2<br>fMAX_LPDDR3|DDR Memory CLK<br>Frequency (ECLK)|All Devices|—|400|—|350|—|312|MHz|
|**DDR2/DDR3/DDR3L/LPDDR2/LPDDR3 WRITE(DQ Output Data are Centered to DQS)**||||||||||
|tDQVBS_DDR2<br>tDQVBS_DDR3<br>tDQVBS_DDR3L<br>tDQVBS_LPDDR2<br>tDQVBS_LPDDR3|Data Output Valid before<br>DQS Output|All Devices|—|–0.25|—|–0.25|—|-0.25|UI|
|tDQVAS_DDR2<br>tDQVAS_DDR3<br>tDQVAS_DDR3L<br>tDQVAS_LPDDR2<br>tDQVAS_LPDDR3|Data Output Valid after DQS<br>Output|All Devices|0.25|—|0.25|—|0.25|—|UI|
|fDATA_DDR2<br>fDATA_DDR3<br>fDATA_DDR3L<br>fDATA_LPDDR2<br>fDATA_LPDDR3|DDR Memory Data Rate|All Devices|—|800|—|700|—|624|Mb/s|
|fMAX_DDR2<br>fMAX_DDR3<br>fMAX_DDR3L<br>fMAX_LPDDR2<br>fMAX_LPDDR3|DDR Memory CLK<br>Frequency (ECLK)|All Devices|—|400|—|350|—|312|MHz|



**Notes** : 

- Commercial timing numbers are shown. Industrial numbers are typically slower and can be extracted from the Diamond software. 

- General I/O timing numbers are based on LVCMOS 2.5, 12 mA, Fast Slew Rate, 0pf load. 

- Generic DDR timing are numbers based on LVDS I/O. 

- DDR2 timing numbers are based on SSTL18. 

- DDR3 timing numbers are based on SSTL15. 

- LPDDR2 and LPDDR3 timing numbers are based on HSUL12. 

- Uses LVDS I/O standard for measurements. 

- Maximum clock frequencies are tested under best case conditions. System performance may vary upon the user environment. 

- All numbers are generated with the Diamond software. 

© 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

68 

FPGA-DS-02012-2.2 

**ECP5 and ECP5-5G Family Data Sheet** 

**==> picture [460 x 172] intentionally omitted <==**

**----- Start of picture text -----**<br>
LATTICE<br>Rx CLK (in)<br>pg<br>Rx DATA (in)<br>tSU/tDVBDQ tSU/tDVBDQ<br>tHD/tDVADQ tHD/tDVADQ<br>**----- End of picture text -----**<br>


**Figure 3.6. Receiver RX.CLK.Centered Waveforms** 

**==> picture [425 x 152] intentionally omitted <==**

**----- Start of picture text -----**<br>
1/2 UI 1/2 UI<br>Rx CLK (in)<br>1 UI<br>or DQS Input<br>Rx DATA (in)<br>or DQ Input<br>oe tSU o e<br>tSU<br>tHD<br>tHD<br>**----- End of picture text -----**<br>


**Figure 3.7. Receiver RX.CLK.Aligned and DDR Memory Input Waveforms** 

**==> picture [345 x 145] intentionally omitted <==**

**----- Start of picture text -----**<br>
1/2 UI 1/2 UI 1/2 UI 1/2 UI<br>Tx CLK (out)<br>or DQS Output<br>Tx DATA (out)<br>or DQ Output<br>tDVB/tDQVBS tDVB/tDQVBS<br>tDVA/tDQVA tDVA/tDQVAS<br>**----- End of picture text -----**<br>


**Figure 3.8. Transmit TX.CLK.Centered and DDR Memory Output Waveforms** 

© 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02012-2.2 

69 

**ECP5 and ECP5-5G Family Data Sheet** 

**==> picture [423 x 140] intentionally omitted <==**

**----- Start of picture text -----**<br>
11<br>1 1 UI I<br>|<br>Tx CLK (out) H< > | /<br>__ O T i]1t1v1 1<br>ti)<br>t 1<br>t1<br>11<br>I1<br>Tx DATA (out)<br>1t11<br>1 I1 11 ttt i)i]1 II 111<br>tDIB tig tDIB foil<br>1 O e<br>11 > I It tDIA i]1 > 1 i)1 tDIA<br>I i] I i] 1 i<br>boi | i ii<br>1 t t i] 1 1<br>**----- End of picture text -----**<br>


**Figure 3.9. Transmit TX.CLK.Aligned Waveforms** 

**Receiver – Shown for one LVDS Channel** 

**==> picture [419 x 116] intentionally omitted <==**

**----- Start of picture text -----**<br>
# of Bits 1 2 3 4 5 6 7 8 9 10 11 1213 14 15 16 17 18 1920 21 22 23 24 25 26 27 28 29<br>Data In<br>756 Mb/s KOK 1X 2X 3X 4X 5X OX OK 1K 2K 3X 4K SX OX OK 1K 2K SX 4X 5X BK ON 1K 2N 3X 4X 5X 6X 0)<br>Clock In o! 1| 2| 3| 4|<br>108 MHz<br>|<br>0x Bit #10 – 1 Bit #20 – 8 | Bit #30 – 15 Bit #40 – 22<br>For each Channel:7-bit Output Words 0x0x0x 11 – 212 – 313 – 4 21 – 922 – 1023 – 11 || 31 – 1632 – 1733 – 18 41 – 2342 – 2443 – 25<br>to FPGA Fabric 0x0x 14 – 515 – 6 | 24 – 1225 – 13 | 34 – 1935 – 20 44 – 2645 – 27<br>0x 16 – 7 26 – 14 36 – 21 46 – 28<br>**----- End of picture text -----**<br>


## **Transmitter – Shown for one LVDS Channel** 

# of Bits 1 2 3 4 5 6 7 8 9 10 11 1213 14 15 16 17 18 1920 21 Data Out 756 Mb/s ~~CVT AAA~~ Clock Out 0! 1 2 | 3) 108 MHz Bit # Bit # Bit # Bit # **For each Channel:7-bit Output Wordsto FPGA Fabric** 00 – 100 – 200 – 300 – 4 ~~|~~ 10 – 811 – 912 – 1013 – 11 20 – 1521 – 1622 – 1723 – 18 30 – 2231 – 2332 – 2433 – 25 | 00 – 5 | 14 – 12 24 – 19 34 – 26 | 00 – 6 15 – 13 25 – 20 35 – 27 00 – 7 16 – 14 26 – 21 36 – 28 

**Figure 3.10. DDRX71 Video Timing Waveforms** 

© 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

70 

FPGA-DS-02012-2.2 

**ECP5 and ECP5-5G Family Data Sheet** 

**==> picture [355 x 163] intentionally omitted <==**

**----- Start of picture text -----**<br>
Bit 0 Bit 1 Bit i<br>1/2 UI 1/2 UI<br>CLK (in) 1 UI<br>DATA (in)<br>tSU_0<br>tHD_0<br>tSU_i<br>tHD_i<br>**----- End of picture text -----**<br>


**Figure 3.11. Receiver DDRX71_RX Waveforms** 

**==> picture [462 x 200] intentionally omitted <==**

**----- Start of picture text -----**<br>
Bit 0 Bit 1 Bit i<br>1 UI<br>CLK (out) jt<br>DATA (out)<br>tDIB_0 on<br>or)<br>tDIA_0<br>tDIB_i<br>tDIA_i<br>**----- End of picture text -----**<br>


**Figure 3.12. Transmitter DDRX71_TX Waveforms** 

© 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02012-2.2 

71 

**ECP5 and ECP5-5G Family Data Sheet** 

## **3.19. sysCLOCK PLL Timing** 

Over recommended operating conditions. 

**Table 3.23. sysCLOCK PLL Timing** 

|**Parameter**<br>~~es~~|**Descriptions**|**Conditions**|**Min**|**Max**|**Units**|
|---|---|---|---|---|---|
|fIN<br>~~es~~<br>~~Ge~~|Input Clock Frequency (CLKI, CLKFB)<br>~~Ge~~|—<br>~~Ge~~|8<br>~~Ge~~|400<br>~~Ge~~|MHz<br>~~Ge~~|
|fOUT<br>~~eG~~<br>~~ee~~|Output Clock Frequency (CLKOP, CLKOS)<br>~~eG~~|—<br>~~eG~~|3.125<br>~~eG~~|400<br>~~eG~~|MHz<br>~~eG~~|
|fVCO<br>~~eG~~<br>~~ee~~|PLL VCO Frequency<br>~~eG~~|—<br>~~eG~~|400<br>~~eG~~|800<br>~~eG~~|MHz<br>~~eG~~|
|fPFD3<br>~~ee~~<br>~~a~~|Phase Detector Input Frequency<br>|—<br>|10<br>|400<br>|MHz<br>|
|**AC Characteristics**<br>~~a~~||||||
|tDT<br>~~Ge~~<br>~~es~~|Output Clock Duty Cycle<br>~~Ge~~<br>~~SS~~|—<br>~~Ge~~<br>~~SS~~|45<br>~~Ge~~<br>~~SS~~|55<br>~~Ge~~<br>~~SS~~|%<br>~~Ge~~<br>~~SS~~|
|tPH4<br>~~es~~|Output Phase Accuracy<br>~~SS~~|—<br>~~SS~~|–5<br>~~SS~~|5<br>~~SS~~|%<br>~~SS~~|
|tOPJIT1<br>~~es~~|Output Clock Period Jitter<br>~~SS~~|fOUT≥ 100 MHz<br>~~SS~~|—<br>~~SS~~<br>~~ee~~|100<br>~~SS~~<br>~~ee~~|ps p-p<br>~~SS~~|
|||fOUT< 100 MHz<br>~~SS~~<br>~~ee~~|—<br>~~SS~~<br>~~ee~~<br>~~ee~~|0.025<br>~~SS~~<br>~~ee~~<br>~~ee~~|UIPP<br>~~SS~~<br>~~ee~~|
||Output Clock Cycle-to-Cycle Jitter<br>~~SS~~<br>~~a~~|fOUT≥ 100 MHz<br>~~SS~~<br>~~ee~~<br>~~a~~|—<br>~~SS~~<br>~~ee~~<br>~~ee ~~<br>~~a~~|200<br>~~SS~~<br>~~ee~~<br> ~~ee~~<br>~~a~~|ps p-p<br>~~SS~~<br>~~ee~~<br>~~a~~|
|||fOUT< 100 MHz<br>~~a~~<br>~~ee~~|—<br>~~a~~<br>~~ee~~|0.050<br>~~a~~<br>~~ee~~|UIPP<br>~~a~~<br>~~ee~~|
||Output Clock Phase Jitter<br>~~a~~|fPFD≥ 100 MHz<br>~~a~~|—<br>~~a~~|200<br>~~a~~|ps p-p<br>~~a~~|
|||fPFD< 100 MHz<br>~~a~~<br>~~pO~~|—<br>~~a~~<br>~~pO~~|0.011<br>~~a~~<br>~~pO~~|UIPP<br>~~a~~<br>~~pO~~|
|tSPO<br>~~ee~~|Static Phase Offset|Divider ratio =<br>integer|—|400|ps p-p|
|tW<br>~~ee~~|Output Clock Pulse Width|At 90% or 10%|0.9|—|ns|
|tLOCK2<br>~~ee~~<br>~~a~~|PLL Lock-in Time<br>|—<br>|—<br>|15<br>|ms<br>|
|tUNLOCK<br>~~e~~|PLL Unlock Time<br>~~eG~~|—<br>~~G~~|—<br>~~G~~|50<br>~~G~~|ns<br>~~G~~|
|tIPJIT<br>~~e~~<br>~~a~~<br>~~es~~|Input Clock Period Jitter<br>~~eG~~<br>~~a~~|fPFD≥ 20 MHz<br>~~G~~<br>~~a~~|—<br>~~G~~<br>~~a~~|1,000<br>~~G~~<br>~~a~~|ps p-p<br>~~G~~<br>~~a~~|
|||fPFD< 20 MHz<br>~~a~~<br>~~po~~|—<br>~~a~~<br>~~po~~|0.02<br>~~a~~<br>~~po~~|UIPP<br>~~a~~<br>~~po~~|
|tHI<br>~~a~~<br>~~es~~|Input Clock High Time<br>~~a~~|90% to 90%<br>~~a~~<br>~~po~~|0.5<br>~~a~~<br>~~po~~|—<br>~~a~~<br>~~po~~|ns<br>~~a~~<br>~~po~~|
|tLO<br>~~es~~<br>~~a~~|Input Clock Low Time<br>|10% to 10%<br>~~po~~<br>|0.5<br>~~po~~<br>|—<br>~~po~~<br>|ns<br>~~po~~<br>|
|tRST<br>~~aGe~~|RST/ Pulse Width<br>~~Ge~~|—<br>~~Ge~~|1<br>~~Ge~~|—<br>~~Ge~~|ms<br>~~Ge~~|
|tRSTREC<br>~~a~~<br>~~ns~~|RST Recovery Time|—|1|—|ns|
|tLOAD_REG<br>~~ns~~|Min Pulse for CIB_LOAD_REG|—|10|—|ns|
|tROTATE-SETUP<br>~~ns~~|Min time for CIB dynamic phase controls to be stable<br>fore CIB_ROTATE|—|5|—|ns|
|tROTATE-WD<br>~~ns~~|Min pulse width for CIB_ROTATE to maintain 0 or 1|—|4|—|VCO cycles|



## **Notes** : 

1. Jitter sample is taken over 10,000 samples for Periodic jitter, and 2,000 samples for Cycle-to-Cycle jitter of the primary PLL output with clean reference clock with no additional I/O toggling. 

2. Output clock is valid after tLOCK for PLL reset and dynamic delay adjustment. 

3. Period jitter and cycle-to-cycle jitter numbers are guaranteed for fPFD > 10 MHz. For fPFD < 10 MHz, the jitter numbers may not be met in certain conditions. 

© 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

72 

FPGA-DS-02012-2.2 

**ECP5 and ECP5-5G Family Data Sheet** 

## **3.20. SERDES High-Speed Data Transmitter** 

**Table 3.24. Serial Output Timing and Levels** 

|**Symbol**<br>~~Ce~~<br>~~a~~|**Description**<br>~~Ce~~<br>|**Min**<br>~~Ce~~<br>~~GO~~<br>|**Typ**<br>~~Ce~~<br>|**Max**<br>~~Ce~~<br>|**Unit**<br>~~Ce~~<br>|
|---|---|---|---|---|---|
|VTX-DIFF-PP<br>~~Ce~~<br>~~a ~~|Peak-Peak Differential voltage on selected amplitude1, 2<br>~~Ce~~<br> ~~CC~~|–25%<br>~~Ce~~<br>~~GO~~<br>~~CC~~|—<br>~~Ce~~<br>~~CC~~|25%<br>~~Ce~~<br>~~CC~~|mV, p-p<br>~~Ce~~<br>~~CC~~|
|VTX-CM-DC<br>~~eG~~|Output common mode voltage<br>~~eG~~|—<br>~~eG~~|VCCHTX/ 2<br>~~eG~~|—<br>~~eG~~|mV, p-p<br>~~eG~~|
|TTX-R<br>~~eG~~<br>~~a ~~|Rise time (20% to 80%)<br>~~eG~~<br> ~~eC~~|50<br>~~eG~~<br>~~eC~~|—<br>~~eG~~<br>~~eC~~|—<br>~~eG~~<br>~~eC~~|ps<br>~~eG~~<br>~~eC~~|
|TTX-F<br>~~a ~~|Fall time (80% to 20%)<br> ~~CC~~|50<br>~~CC~~|—<br>~~CC~~|—<br>~~CC~~|ps<br>~~CC~~|
|TTX-CM-AC-P<br>~~eG~~|RMS AC peak common-mode output voltage<br>~~eG~~|—<br>~~eG~~|—<br>~~eG~~|20<br>~~eG~~|mV<br>~~eG~~|
|ZTX_SE<br>~~eG~~<br>~~a~~|Single ended output impedance for 50/75 Ω<br>~~eG~~<br>~~a~~|–20%<br>~~eG~~<br>~~a~~|50/75<br>~~eG~~<br>~~a~~|20%<br>~~eG~~<br>~~a~~|Ω<br>~~eG~~<br>~~a~~|
||Single ended output impedance for 6K Ω<br>~~a~~<br>~~a~~|–25%<br>~~a~~<br>~~a~~|6K<br>~~a~~<br>~~a~~|25%<br>~~a~~<br>~~a~~|Ω<br>~~a~~<br>~~a~~|
|RLTX_DIFF<br>~~a~~|Differential return loss (with package included)3<br>~~a~~<br>~~eC~~|—<br>~~a~~<br>~~eC~~|—<br>~~a~~<br>~~eC~~|–10<br>~~a~~<br>~~eC~~|dB<br>~~a~~<br>~~eC~~|
|RLTX_COM<br>~~CD~~|Common mode return loss (with package included)3<br>~~CD~~|—<br>~~CD~~|—<br>~~CD~~|–6<br>~~CD~~|dB<br>~~CD~~|



1. Measured with 50 Ω Tx Driver impedance at VCCHTX±5%. 

2. Refer to ECP5 and ECP5-5G SERDES/PCS Usage Guide (TN1261) for settings of Tx amplitude. 

3. Return los = −10 dB (differential), –6 dB (common mode) for 100 MHz ≤ f <= 1.6 GHz with 50 Ω output impedance configuration. This includes degradation due to package effects. 

**Table 3.25. Channel Output Jitter** 

|**Description**<br>~~po~~|**Frequency**<br>|**Min**<br>|**Typ**<br>|**Max**<br>|**Unit**<br>|
|---|---|---|---|---|---|
|Deterministic<br>~~poGO~~|5 Gb/s<br>~~GO~~|—<br>~~GO~~|—<br>~~GO~~|TBD<br>~~GO~~|UI, p-p<br>~~GO~~|
|Random<br>~~eC~~|5 Gb/s<br>~~eC~~|—<br>~~eC~~|—<br>~~eC~~|TBD<br>~~eC~~|UI, p-p<br>~~eC~~|
|Total<br>~~eC~~<br>~~GC~~|5 Gb/s<br>~~eC~~<br>~~GC~~|—<br>~~eC~~<br>~~GC~~|—<br>~~eC~~<br>~~GC~~|TBD<br>~~eC~~<br>~~GC~~|UI, p-p<br>~~eC~~<br>~~GC~~|
|Deterministic<br>~~eC~~|3.125 Gb/s<br>~~eC~~|—<br>~~eC~~|—<br>~~eC~~<br>~~CO~~|0.17<br>~~eC~~<br>~~CO~~|UI, p-p<br>~~eC~~|
|Random<br>~~eC~~<br>~~eG~~|3.125 Gb/s<br>~~eC~~<br>~~eG~~|—<br>~~eC~~<br>~~eG~~|—<br>~~eC~~<br>~~eG~~<br>~~CO~~|0.25<br>~~eC~~<br>~~eG~~<br>~~CO~~|UI, p-p<br>~~eC~~<br>~~eG~~|
|Total<br>~~fe~~|3.125 Gb/s<br>~~fe~~|—<br>~~fe~~|—<br>~~CO~~<br>~~fe~~|0.35<br>~~CO~~<br>~~fe~~|UI, p-p<br>~~fe~~|
|Deterministic<br>~~fe~~<br>~~DO~~|2.5 Gb/s<br>~~fe~~<br>~~DO~~|—<br>~~fe~~<br>~~DO~~|—<br>~~fe~~<br>~~DO~~<br>~~GO~~|0.17<br>~~fe~~<br>~~DO~~<br>~~GO~~|UI, p-p<br>~~fe~~<br>~~DO~~|
|Random<br>~~Ge~~|2.5 Gb/s<br>~~Ge~~|—<br>~~Ge~~|—<br>~~Ge~~<br>~~GO~~|0.20<br>~~Ge~~<br>~~GO~~|UI, p-p<br>~~Ge~~|
|Total<br>~~pf~~|2.5 Gb/s<br>~~pf~~|—<br>~~pf~~|—<br>~~GO~~<br>~~pf~~<br>~~CO~~|0.35<br>~~GO~~<br>~~pf~~<br>~~CO~~|UI, p-p<br>~~pf~~|
|Deterministic<br>~~pf~~<br>~~ee~~|1.25 Gb/s<br>~~pf~~<br>~~ee~~|—<br>~~pf~~<br>~~ee~~<br>~~Ge~~|—<br>~~pf~~<br>~~ee~~<br>~~CO~~|0.10<br>~~pf~~<br>~~ee~~<br>~~CO~~|UI, p-p<br>~~pf~~<br>~~ee~~|
|Random<br>~~Ce~~|1.25 Gb/s<br>~~Ce~~|—<br>~~Ce~~<br>~~Ge~~|—<br>~~CO~~<br>~~Ce~~|0.22<br>~~CO~~<br>~~Ce~~|UI, p-p<br>~~Ce~~|
|Total<br>~~Ce~~<br>~~BD~~|1.25 Gb/s<br>~~Ce~~<br>~~BD~~|—<br>~~Ce~~<br>~~Ge~~<br>~~BD~~|—<br>~~Ce~~<br>~~BD~~|0.24<br>~~Ce~~<br>~~BD~~|UI, p-p<br>~~Ce~~<br>~~BD~~|



**Notes** : 

- Values are measured with PRBS 27-1, all channels operating, FPGA logic active, I/O around SERDES pins quiet, reference clock @ 10X mode. 

- For ECP5-5G family devices only. 

© 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02012-2.2 

73 

**ECP5 and ECP5-5G Family Data Sheet** 

## **3.21. SERDES/PCS Block Latency** 

Table 3.26 describes the latency of each functional block in the transmitter and receiver. Latency is given in parallel clock cycles. Figure 3.13 shows the location of each block. 

## **Table 3.26. SERDES/PCS Latency Breakdown** 

|**Item**<br>~~GF~~|**Description**<br>~~GF~~|**Min**<br>~~GF~~|**Avg**<br>~~GF~~|**Max**<br>~~GF~~|**Fixed**<br>~~GF~~|**Bypass**<br>~~GF~~|**Unit3**<br>~~GF~~|
|---|---|---|---|---|---|---|---|
|**Transmit Data Latency1**<br>~~enGE~~||||||||
|T1<br>~~en~~|FPGA Bridge - Gearing disabled with same clocks<br>~~en~~|3<br>~~en~~|—<br>~~GE~~|4<br>~~GE~~|—|1|byte clk|
||FPGA Bridge - Gearing enabled<br>~~en~~<br>~~pf~~|5<br>~~en~~<br>~~pf~~<br>~~ee~~|—<br>~~GE~~<br>~~pf~~<br>~~ee~~|7<br>~~GE~~<br>~~pf~~<br>~~ee~~|—<br>~~pf~~<br>~~ee~~|—<br>~~pf~~|word clk<br>~~pf~~|
|T2<br>~~en~~<br>~~ee~~|8b10b Encoder<br>~~en~~<br>~~ee~~|—<br>~~en ~~<br>~~ee~~<br>~~ee~~|—<br> ~~GE~~<br>~~ee~~<br>~~ee~~|—<br>~~GE~~<br>~~ee~~<br>~~ee~~|2<br>~~ee~~<br>~~ee~~|1<br>~~ee~~|byte clk<br>~~ee~~|
|T3<br>~~ee~~<br>|SERDES Bridge transmit<br>~~ee~~<br>|—<br>~~ee~~<br>~~ee~~<br>|—<br>~~ee~~<br>~~ee~~<br>|—<br>~~ee~~<br>~~ee~~<br>|2<br>~~ee~~<br>~~ee~~<br>|1<br>~~ee~~<br>|byte clk<br>~~ee~~<br>~~—~~|
|T4<br>~~[HHH~~<br>~~———————~~|Serializer: 8-bit mode<br>~~[HHH~~|—<br>~~ee ~~<br>~~[HHH~~|—<br> ~~ee ~~<br>~~[HHH~~|—<br> ~~ee ~~<br>~~[HHH~~|15 +1<br> ~~ee~~<br>~~[HHH~~|—<br>~~[HHH~~|UI + ps<br>~~[HHH—~~|
||Serializer: 10-bit mode<br>~~[HHH~~<br>~~———————~~|—<br>~~[HHH~~<br>~~———————~~|—<br>~~[HHH~~<br>~~———————~~|—<br>~~[HHH~~<br>~~———————~~|18 +1<br>~~[HHH~~<br>~~———————~~|—<br>~~[HHH~~<br>~~———————~~|UI + ps<br>~~[HHH—~~<br>~~———————~~|
|T5<br>~~[HHH~~<br>~~———————~~|Pre-emphasis ON<br>~~[HHH~~<br>~~———————~~|—<br>~~[HHH~~<br>~~———————~~|—<br>~~[HHH~~<br>~~———————~~|—<br>~~[HHH~~<br>~~———————~~|1 +2<br>~~[HHH~~<br>~~———————~~|—<br>~~[HHH~~<br>~~———————~~|UI + ps<br>~~[HHH—~~<br>~~———————~~|
||Pre-emphasis OFF<br>~~———————~~<br>~~eG~~|—<br>~~———————~~<br>~~eG~~|—<br>~~———————~~<br>~~eG~~|—<br>~~———————~~<br>~~eG~~|0 +3<br>~~———————~~<br>~~eG~~|—<br>~~———————~~<br>~~eG~~|UI + ps<br>~~———————~~<br>~~eG~~|
|**Receive Data Latency2**<br>~~———————~~<br>~~eG~~||||||||
|R1<br>~~ee~~|Equalization ON|—|—|—|1|—|UI + ps|
||Equalization OFF<br>~~ee~~|—|—|—|2|—|UI + ps|
|R2<br>~~ee~~<br>~~rH~~|Deserializer: 8-bit mode<br>~~ee~~|—|—|—|10 +3|—|UI + ps|
||Deserializer: 10-bit mode<br>~~ee~~<br>~~rH~~|—<br>~~rH~~|—<br>~~rH~~|—<br>~~rH~~|12 +3<br>~~rH~~|—<br>~~rH~~|UI + ps<br>~~rH~~|
|R3<br>~~ee~~<br>~~rH~~|SERDES Bridge receive<br>~~ee~~<br>~~rH~~|—<br>~~rH~~|—<br>~~rH~~|—<br>~~rH~~|2<br>~~rH~~|—<br>~~rH~~|byte clk<br>~~rH~~|
|R4<br>~~a~~|Word alignment<br>~~Ge~~|3.1<br>~~Ge~~|—<br>~~Ge~~|4<br>~~Ge~~|—<br>~~Ge~~|1<br>~~Ge~~|byte clk<br>~~Ge~~|
|R5<br>~~ry~~|8b10b decoder<br>~~ry~~|—<br>~~ry~~|—<br>~~ry~~|—<br>~~ry~~|1<br>~~ry~~|0<br>~~ry~~|byte clk<br>~~ry~~|
|R6<br>~~ry~~<br>~~Oe~~|Clock Tolerance Compensation<br>~~ry~~<br>~~pf~~|7<br>~~ry~~<br>~~pf~~|15<br>~~ry~~<br>~~pf~~|23<br>~~ry~~<br>~~pf~~|—<br>~~ry~~<br>~~pf~~|1<br>~~ry~~<br>~~pf~~|byte clk<br>~~ry~~<br>~~pf~~|
|R7<br>~~Oe~~|FPGA Bridge - Gearing disabled with same clocks<br>~~pf~~|4<br>~~pf~~|—<br>~~pf~~|5<br>~~pf~~|—<br>~~pf~~|1<br>~~pf~~|byte clk<br>~~pf~~|
||FPGA Bridge - Gearing enabled<br>~~pf~~|7<br>~~pf~~|—<br>~~pf~~|9<br>~~pf~~|—<br>~~pf~~|—<br>~~pf~~|word clk<br>~~pf~~|



## **Notes** : 

1. 1 = –245 ps, 2 = +88 ps, 3 = +112 ps. 

2. 1 = +118 ps, 2 = +132 ps, 3 = +700 ps. 

3. byte clk = 8 UI (8-bit mode), or 10 UI (10-bit mode); word clk = 16UI (8-bit mode), or 20 UI (10-bit mode). 

**==> picture [469 x 171] intentionally omitted <==**

**----- Start of picture text -----**<br>
SERDES SERDES Bridge PCS FPGA Bridge FPGA Core<br>REFCLK Recovered Clock FPGA<br>EBRD Clock<br>R4 R5 R6<br>R1 R2 R3 R7<br>WA DEC Elastic<br>HDINPiHDINNi EQ CDR Deserializer1:8/1:10 PolarityAdjust BufferFIFO SampleDownFIFO Receive Data<br>BYPASS BYPASS<br>Receiver BYPASS BYPASS<br>FPGA<br>Receive Clock<br>REFCLK Transmit Clock<br>TX PLL<br>FPGA<br>T2 T1 Transmit Clock<br>T3<br>T5 T4 Encoder Up<br>Polarity Sample Transmit Data<br>HDOUTPi Serializer Adjust FIFO<br>HDOUTNi 8:1/10:1 BYPASS<br>Transmitter BYPASS BYPASS<br>Sep Se<br>**----- End of picture text -----**<br>


**Figure 3.13. Transmitter and Receiver Latency Block Diagram** 

© 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02012-2.2 

74 

**ECP5 and ECP5-5G Family Data Sheet** 

## **3.22. SERDES High-Speed Data Receiver** 

**Table 3.27. Serial Input Data Specifications** 

|**Symbol**<br>~~a~~|**Description**|**Min**|**Typ**|**Max**|**Unit**|
|---|---|---|---|---|---|
|VRX-DIFF-S<br>~~a~~|Differential input sensitivity|150|—|1760|mV, p-p|
|VRX-IN|Input levels|0|—|VCCA+0.52|V|
|VRX-CM-DCCM<br>~~a~~|Input common mode range (internal DC coupled<br>mode)<br>~~ee~~|0.6<br>~~ee~~|—<br>~~ee~~|VCCA<br>~~ee~~|V<br>~~ee~~|
|VRX-CM-ACCM|Input common mode range (internal AC coupled<br>mode)2|0.1|—|VCCA+0.2|V|
|TRX-RELOCK<br>~~a~~|SCDR re-lock time1|—|1000|—|Bits|
|ZRX-TERM<br>~~a~~|Input termination 50/75Ω/High Z|–20%|50/75/5 K|+20%|Ω|
|RLRX-RL<br>~~a~~|Return loss (without package)|—|—|–10|dB|



**Notes** : 

1. This is the typical number of bit times to re-lock to a new phase or frequency within ±300 ppm, assuming 8b10b encoded data. 

2. Up to 1.655 for ECP5, and 1.736 for ECP5-5G. 

## **3.23. Input Data Jitter Tolerance** 

A receiver’s ability to tolerate incoming signal jitter is very dependent on jitter type. High speed serial interface standards have recognized the dependency on jitter type and have specifications to indicate tolerance levels for different jitter types as they relate to specific protocols. Sinusoidal jitter is considered to be a worst case jitter type. 

**Table 3.28. Receiver Total Jitter Tolerance Specification** 

|**Description**<br>~~a ~~|**Frequency**<br> ~~a~~|**Condition**|**Min**|**Typ**|**Max**|**Unit**|
|---|---|---|---|---|---|---|
|Deterministic<br>~~—~~|5 Gb/s<br>~~—~~<br>~~—~~<br>~~—~~|400 mV differential eye<br>~~—~~<br>~~a~~|—<br>~~a~~|—<br>~~a~~|TBD|UI, p-p|
|Random<br>~~—~~||400 mV differential eye<br>~~—~~<br>~~a~~|—|—|TBD|UI, p-p|
|Total<br>~~—~~||400 mV differential eye<br>~~—~~<br>~~a~~|—<br>~~—~~<br>~~a~~<br>~~a~~|—<br>~~a~~<br>~~a~~|TBD<br>~~a~~<br>~~a~~|UI, p-p<br>~~a~~|
|Deterministic<br>~~a~~|3.125 Gb/s<br>~~a~~<br>~~—~~<br>~~a~~|400 mV differential eye<br>~~a~~<br>~~a~~|—<br>~~a~~|—|0.37|UI, p-p|
|Random<br>~~a~~<br>~~—~~||400 mV differential eye<br>~~a~~<br>~~a~~<br>~~—~~<br>~~a~~|—<br>~~a~~<br>~~—~~<br>~~a~~<br>~~a~~|—<br>~~a~~<br>~~a~~|0.18<br>~~a~~<br>~~a~~|UI, p-p<br>~~a~~|
|Total<br>~~a~~||400 mV differential eye<br>~~a~~<br>~~a~~|—<br>~~a~~|—|0.65|UI, p-p|
|Deterministic<br>~~a~~<br>~~—~~|2.5 Gb/s<br>~~a~~<br>~~—~~<br>~~—~~<br>~~a~~|400 mV differential eye<br>~~a~~<br>~~a~~<br>~~—~~<br>~~a~~|—<br>~~a~~<br>~~a~~|—<br>~~a~~|0.37|UI, p-p|
|Random<br>~~—~~||400 mV differential eye<br>~~—~~<br>~~a~~|—<br>~~a~~|—|0.18|UI, p-p|
|Total<br>~~a~~||400 mV differential eye<br>~~a~~<br>~~a~~|—<br>~~a~~|—<br>~~a~~|0.65|UI, p-p|
|Deterministic<br>~~a~~<br>~~—~~|1.25 Gb/s<br>~~a~~<br>~~—~~<br>~~a~~<br>~~—~~|400 mV differential eye<br>~~a~~<br>~~a~~<br>~~—~~<br>~~a~~|—<br>~~a~~<br>~~a~~|—<br>~~a~~|0.37|UI, p-p|
|Random<br>~~a~~||400 mV differential eye<br>~~a~~<br>~~a~~|—<br>~~a~~|—<br>~~a~~|0.18|UI, p-p|
|Total<br>~~a~~<br>~~—~~||400 mV differential eye<br>~~a~~<br>~~a~~<br>~~—~~<br>~~a~~|—<br>~~a~~|—<br>~~a~~|0.65|UI, p-p|



**Notes** : 

- Jitter tolerance measurements are done with protocol compliance tests: 3.125 Gb/s - XAUI Standard, 2.5 Gb/s - PCIe Standard, 1.25 Gb/s SGMII Standard. 

- For ECP5-5G family devices only. 

© 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02012-2.2 

75 

**ECP5 and ECP5-5G Family Data Sheet** 

## **3.24. SERDES External Reference Clock** 

The external reference clock selection and its interface are a critical part of system applications for this product. Table 3.29 specifies reference clock requirements, over the full range of operating conditions. 

**Table 3.29. External Reference Clock Specification (refclkp/refclkn)** 

|**Symbol**<br>~~a~~|**Description**<br>~~C(O~~|**Min**<br>~~C(O~~|**Type**<br>~~C(O~~|**Max**<br>~~C(O~~|**Unit**<br>~~C(O~~|
|---|---|---|---|---|---|
|FREF<br>~~a ~~<br>~~a ~~|Frequency range<br> ~~C(O~~<br> ~~eG~~|50<br>~~C(O~~<br>~~eG~~|—<br>~~C(O~~<br>~~eG~~|320<br>~~C(O~~<br>~~eG~~|MHz<br>~~C(O~~<br>~~eG~~|
|FREF-PPM<br>~~GO~~|Frequencytolerance1<br>~~GO~~|–1000<br>~~GO~~|—<br>~~GO~~|1000<br>~~GO~~|ppm<br>~~GO~~|
|VREF-IN-SE<br>~~GO~~<br>~~a ~~|Input swing, single-ended clock2, 4<br>~~GO~~<br> ~~eG~~|200<br>~~GO~~<br>~~eG~~|—<br>~~GO~~<br>~~eG~~|VCCA<br>~~GO~~<br>~~eG~~|mV, p-p<br>~~GO~~<br>~~eG~~|
|VREF-IN-DIFF|Input swing, differential clock|200|—|2*VCCA|mV, p-p<br>differential|
|VREF-IN<br>~~a ~~|Input levels<br> ~~GC~~|0<br>~~GC~~|—<br>~~GC~~|VCCA+ 0.4<br>~~GC~~|V<br>~~GC~~|
|DREF<br>~~a ~~|Duty cycle3<br> ~~eG~~|40<br>~~eG~~|—<br>~~eG~~|60<br>~~eG~~|%<br>~~eG~~|
|TREF-R<br>~~a ~~|Rise time (20% to 80%)<br> ~~eG~~|200<br>~~eG~~|500<br>~~eG~~|1000<br>~~eG~~|ps<br>~~eG~~|
|TREF-F<br>~~GO~~|Fall time (80% to 20%)<br>~~GO~~|200<br>~~GO~~|500<br>~~GO~~|1000<br>~~GO~~|ps<br>~~GO~~|
|ZREF-IN-TERM-DIFF<br>~~GO~~<br>~~a ~~|Differential input termination<br>~~GO~~<br> ~~eG~~|–30%<br>~~GO~~<br>~~eG~~|100/HiZ<br>~~GO~~<br>~~eG~~|+30%<br>~~GO~~<br>~~eG~~|Ω<br>~~GO~~<br>~~eG~~|
|CREF-IN-CAP<br>~~a~~|Input capacitance<br>~~a~~|—<br>~~G~~|—|7|pF|



**Notes** : 

1. Depending on the application, the PLL_LOL_SET and CDR_LOL_SET control registers may be adjusted for other tolerance values as described in ECP5 and ECP5-5G SERDES/PCS Usage Guide (FPGA-TN-02206). 

2. The signal swing for a single-ended input clock must be as large as the p-p differential swing of a differential input clock to get the same gain at the input receiver. With single-ended clock, a reference voltage needs to be externally connected to CLKREFN pin, and the input voltage needs to be swung around this reference voltage. 

3. Measured at 50% amplitude. 

4. Single-ended clocking is achieved by applying a reference voltage VREF on REFCLKN input, with the clock applied to REFCLKP input pin. VREF should be set to mid-point of the REFCLKP voltage swing. 

**==> picture [320 x 270] intentionally omitted <==**

**----- Start of picture text -----**<br>
V+<br>P<br>VREF-IN<br>MAX < VCCA+0.4V<br>N<br>VREF_IN_DIFF<br>V+<br>Min=200 mV<br>Max=2xVCCA<br>0 V<br>VREF_IN_DIFF=<br>IVp-VnI<br>V+<br>VREF-IN<br>MAX < VCCA+0.4V<br>VREF_IN_SE<br>Min=200 mV<br>Max=VCCA<br>0 V<br>**----- End of picture text -----**<br>


**Figure 3.14. SERDES External Reference Clock Waveforms** 

© 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02012-2.2 

76 

**ECP5 and ECP5-5G Family Data Sheet** 

## **3.25. PCI Express Electrical and Timing Characteristics** 

## **3.25.1. PCIe (2.5 Gb/s) AC and DC Characteristics** 

Over recommended operating conditions. 

**Table 3.30. PCIe (2.5 Gb/s)** 

|**Symbol**<br>~~a~~|**Description**|**Test Conditions**|**Min**|**Typ**|**Max**|**Unit**|
|---|---|---|---|---|---|---|
|**Transmit1**<br>~~Dd~~|||||||
|UI<br>~~a~~|Unit interval<br>~~a~~<br>~~a~~|—<br>~~a~~<br>~~a~~|399.88<br>~~a~~<br>~~a~~|400<br>~~a~~<br>~~a~~|400.12<br>~~a~~<br>~~a~~|ps<br>~~a~~<br>~~a~~|
|VTX-DIFF_P-P<br>~~a~~<br>~~a~~|Differential peak-to-peak output<br>~~a~~<br>~~a~~<br>~~a~~|—<br>~~a~~<br>~~a~~<br>~~a~~<br>~~ee~~|0.8<br>~~a~~<br>~~a~~<br>~~a~~|1.0<br>~~a~~<br>~~a~~<br>~~a~~|1.2<br>~~a~~<br>~~a~~<br>~~a~~|V<br>~~a~~<br>~~a~~<br>~~a~~|
|VTX-DE-RATIO<br>~~ee~~|De-emphasis differential output<br>voltage ratio<br>~~ee~~|—<br>~~ee~~<br>~~ee~~<br>~~ee~~|–3<br>~~ee~~|–3.5<br>~~ee~~|–4<br>~~ee~~|dB<br>~~ee~~|
|VTX-CM-AC_P<br>~~ee~~|RMS AC peak common-mode output<br>voltage<br>~~ee~~|—<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|—<br>~~ee~~|—<br>~~ee~~|20<br>~~ee~~|mV<br>~~ee~~|
|VTX-RCV-DETECT<br>~~ee~~|Amount of voltage change allowed<br>duringreceiver detection<br>~~ee~~|—<br>~~ee~~<br>~~ee~~<br>~~ee~~|—<br>~~ee~~|—<br>~~ee~~|600<br>~~ee~~|mV<br>~~ee~~|
|VTX-CM-DC<br>~~a~~|Tx DC common mode voltage<br>~~a~~|—<br>~~ee~~<br>~~a~~|0<br>~~a~~|—<br>~~a~~|VCCHTX<br>~~a~~|V<br>~~a~~|
|ITX-SHORT<br>~~es~~|Output short circuit current<br>~~es~~|VTX-D+=0.0 V<br>VTX-D-=0.0 V<br>~~es~~|—<br>~~es~~|—<br>~~es~~|90<br>~~es~~|mA<br>~~es~~|
|ZTX-DIFF-DC<br>~~a~~|Differential output impedance<br>~~a~~|—<br>~~a~~|80<br>~~a~~|100<br>~~a~~|120<br>~~a~~|Ω<br>~~a~~|
|RLTX-DIFF<br>~~a~~|Differential return loss<br>~~a~~|—<br>~~a~~|10<br>~~a~~|—<br>~~a~~|—<br>~~a~~|dB<br>~~a~~|
|RLTX-CM<br>~~a~~|Common mode return loss<br>~~a~~|—<br>~~a~~|6.0<br>~~a~~|—<br>~~a~~|—<br>~~a~~|dB<br>~~a~~|
|TTX-RISE<br>~~a~~<br>~~a~~|Tx output rise time<br>~~a~~<br>~~a~~|20% to 80%<br>~~a~~<br>~~a~~|0.125<br>~~a~~<br>~~a~~|—<br>~~a~~<br>~~a~~|—<br>~~a~~<br>~~a~~|UI<br>~~a~~<br>~~a~~|
|TTX-FALL<br>~~a~~<br>~~DR~~|Tx output fall time<br>~~a~~<br>|20% to 80%<br>~~a~~<br>|0.125<br>~~a~~<br>|—<br>~~a~~<br>|—<br>~~a~~<br>|UI<br>~~a~~<br>|
|LTX-SKEW<br>~~DR~~|Lane-to-lane static output skew for all<br>lanes inport/link<br>|—<br>|—<br>|—<br>|1.3<br>|ns<br>|
|TTX-EYE<br>~~DRa~~|Transmitter eye width<br>~~a~~|—<br>~~a~~|0.75<br>~~a~~|—<br>~~a~~|—<br>~~a~~|UI<br>~~a~~|
|TTX-EYE-MEDIAN-TO-MAX-<br>JITTER<br>~~a~~|Maximum time between jitter median<br>and maximum deviation from median<br>~~a~~|—<br>~~a~~|—<br>~~a~~|—<br>~~a~~|0.125<br>~~a~~|UI<br>~~a~~|
|**Receive1, 2**<br>~~a]~~<br>~~e~~~~**e**~~<br>~~a~~|||||||
|UI<br>~~es~~<br>~~a~~|Unit Interval<br>~~es~~<br>|—<br>~~es~~<br>~~e~~~~**e**~~<br>|399.88<br>~~es~~|400<br>~~es~~|400.12<br>~~es~~|ps<br>~~es~~|
|VRX-DIFF_P-P<br>~~a ~~|Differential peak-to-peak input<br>voltage<br> ~~e~~|—<br>~~e~~~~**e**~~<br>~~e~~|0.343|—|1.2|V|
|VRX-IDLE-DET-DIFF_P-P<br>~~eG~~<br>~~a~~|Idle detect threshold voltage<br>~~eG~~<br>~~ee~~|—<br>~~eG~~<br>~~ee~~|65<br>~~eG~~<br>~~ee~~|—<br>~~eG~~<br>~~ee~~|3403<br>~~eG~~<br>~~ee~~|mV<br>~~eG~~<br>~~ee~~|
|VRX-CM-AC_P<br>~~eG~~<br>~~a~~|RMS AC peak common-mode input<br>voltage<br>~~eG~~<br>~~ee~~|—<br>~~eG~~<br>~~ee~~|—<br>~~eG~~<br>~~ee~~|—<br>~~eG~~<br>~~ee~~|150<br>~~eG~~<br>~~ee~~|mV<br>~~eG~~<br>~~ee~~|
|ZRX-DIFF-DC<br>~~a~~<br>~~a~~<br>~~Re~~|DC differential input impedance<br>~~ee ~~<br>~~Ge~~|—<br> ~~ee~~|80<br>~~ee~~|100<br>~~ee~~|120<br>~~ee~~|Ω<br>~~ee~~|
|ZRX-DC<br>~~a~~<br>~~Re~~|DC input impedance<br>~~Ge~~|—|40|50|60|Ω|
|ZRX-HIGH-IMP-DC<br>~~Re~~<br>~~eG~~|Power-down DC input impedance<br>~~Ge~~<br>~~eG~~|—<br>~~eG~~|200K<br>~~eG~~|—<br>~~eG~~|—<br>~~eG~~|Ω<br>~~eG~~|
|RLRX-DIFF<br>~~eG~~<br>~~a~~|Differential return loss<br>~~eG~~|—<br>~~eG~~|10<br>~~eG~~|—<br>~~eG~~|—<br>~~eG~~|dB<br>~~eG~~|
|RLRX-CM<br>~~a~~<br>~~ee~~|Common mode return loss<br>~~ee~~|—<br>~~ee~~|6.0<br>~~ee~~|—<br>~~ee~~|—<br>~~ee~~|dB<br>~~ee~~|



**Notes** : 

1. Values are measured at 2.5 Gb/s. 

2. Measured with external AC-coupling on the receiver. 

3. Not in compliance with PCI Express 1.1 standard. 

© 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02012-2.2 

77 

**ECP5 and ECP5-5G Family Data Sheet** 

## **3.25.2. PCIe (5 Gb/s) – Preliminary AC and DC Characteristics** 

Over recommended operating conditions. 

**Table 3.31. PCIe (5 Gb/s)** 

|**Symbol**<br>~~a~~<br>~~a~~|**Description**<br>~~a~~<br>~~_~“_~~|**Test Conditions**<br>~~a~~<br>~~_~“____~~|**Min**<br>~~a~~<br>~~___~~|**Typ**<br>~~a~~<br>~~___~~|**Max**<br>~~a~~<br>~~___~~|**Unit**<br>~~a~~|
|---|---|---|---|---|---|---|
|**Transmit1**<br>~~a~~<br>~~Ee~~<br>~~_~“____~~<br>~~a~~|||||||
|UI<br>~~a~~<br>~~DR~~|Unit Interval<br>~~_~“_~~|—<br>~~_~“_ ___~~|199.94<br>~~___~~|200<br>~~___~~|200.06<br>~~___~~|ps|
|BWTX-PKG-PLL2<br>~~DR~~|Tx PLL bandwidth corresponding to<br>PKGTX-PLL2|—|5|—|16|MHz|
|PKGTX-PLL2<br>~~DR~~<br>~~a~~|Tx PLL Peaking|—|—|—|1|dB|
|VTX-DIFF-PP<br>~~a~~<br>~~a ~~<br>~~DR~~|Differential p-p Tx voltage swing<br> ~~a~~|—|0.8|—|1.2|V, p-p|
|VTX-DIFF-PP-LOW<br> <br>~~DR~~|Low power differential p-p Tx voltage<br>swing<br> ~~a~~|—|0.4|—|1.2|V, p-p|
|VTX-DE-RATIO-3.5dB<br> <br>~~DR~~<br>~~a~~|Tx de-emphasis level ratio at 3.5dB<br> ~~a~~|—|3|—|4|dB|
|VTX-DE-RATIO-6dB<br>~~a~~|Tx de-emphasis level ratio at 6dB|—|5.5|—|6.5|dB|
|TMIN-PULSE<br>~~a~~<br>~~a ~~|Instantaneous lone pulse width<br> ~~a~~|—||—|—|UI|
|TTX-RISE-FALL<br>~~a~~<br>~~DR~~|Transmitter rise and fall time|—||—|—|UI|
|TTX-EYE<br>~~DR~~|Transmitter Eye, including all jitter<br>sources|—|0.75|—|—|UI|
|TTX-DJ<br>~~DR~~<br>~~a ~~<br>~~DR~~|Tx deterministic jitter > 1.5 MHz<br> ~~a~~|—|—|—|0.15|UI|
|TTX-RJ<br>~~DR~~|Tx RMS jitter < 1.5 MHz|—|—|—|3|ps,<br>RMS|
|TRF-MISMATCH<br>~~DR~~<br>~~a~~|Tx rise/fall time mismatch<br>|—<br>|—|—||UI|
|RLTX-DIFF<br>~~tT~~<br>~~DR~~|Tx Differential Return Loss, including<br>package and silicon<br>~~tT~~|50 MHz < freq <<br>1.25 GHz<br>~~a~~|10|—|—|dB|
|||1.25 GHz < freq<br>< 2.5 GHz<br>~~a~~|8|—|—|dB|
|RLTX-CM<br>~~tT~~<br>~~DR~~|Tx Common Mode Return Loss,<br>including package and silicon<br>~~tT~~|50 MHz < freq <<br>2.5 GHz<br>~~a~~|6|—|—|dB|
|ZTX-DIFF-DC<br>~~DR~~<br>~~a~~|DC differential Impedance|—|—|—|120|Ω|
|VTX-CM-AC-PP<br>~~a~~|Tx AC peak common mode voltage,<br>peak-peak|—|—|—||mV,<br>p-p|
|ITX-SHORT<br>~~a~~<br>~~DR~~|Transmitter short-circuit current|—|—|—|90|mA|
|VTX-DC-CM<br>~~a~~<br>~~DR~~|Transmitter DC common-mode<br>voltage|—|0|—|1.2|V|
|VTX-IDLE-DIFF-DC<br>~~DR~~<br>~~a~~<br>~~DR~~|Electrical Idle Output DC voltage|—|0|—|5|mV|
|VTX-IDLE-DIFF-AC-p<br>~~DR~~<br>~~DR~~|Electrical Idle Differential Output<br>peak voltage|—|—|—||mV|
|VTX-RCV-DETECT<br>~~DR~~<br>~~DR~~|Voltage change allowed during<br>Receiver Detect|—|—|—|600|mV|
|TTX-IDLE-MIN<br>~~DR~~<br>~~a~~<br>~~DR~~|Min. time in Electrical Idle|—|20|—|—|ns|
|TTX-IDLE-SET-TO-IDLE<br>~~DR~~<br>~~DR~~|Max. time from EI Order Set to valid<br>Electrical Idle|—|—|—|8|ns|
|TTX-IDLE-TO-DIFF-DATA<br>~~DR~~<br>~~DR~~|Max. time from Electrical Idle to valid<br>differential output|—|—|—|8|ns|
|LTX-SKEW<br>~~DR~~<br>~~a~~|Lane-to-lane output skew|—|—|—||ps|



© 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

78 

FPGA-DS-02012-2.2 

**ECP5 and ECP5-5G Family Data Sheet** 

**Table 3.31. PCIe (5 Gb/s)** 

|**Symbol**<br>~~Po~~|**Description**<br>~~eae~~|**Test Conditions**<br>~~eae~~<br>~~et~~|**Min**<br>~~et~~|**Typ**|**Max**|**Unit**|
|---|---|---|---|---|---|---|
|**Receive1, 2**<br>~~Po~~<br>~~eae~~<br>~~et~~<br>~~nr~~<br>~~es~~<br>~~TD~~<br>~~S(O~~|||||||
|UI<br>~~es~~<br>~~ee a~~|Unit Interval<br>~~TD~~<br>~~a~~|—<br>~~S(O~~|199.94<br>~~S(O~~|200|200.06|ps|
|VRX-DIFF-PP<br>~~es~~<br>~~ee a~~|Differential Rx peak-peak voltage<br>~~TD~~<br>~~a~~|—<br>~~S(O~~|0.343<br>~~S(O~~|—|1.2|V, p-p|
|TRX-RJ-RMS<br>~~ee a~~<br>~~a~~|Receiver random jitter tolerance<br>(RMS)<br>~~a~~<br>~~rs~~|1.5 MHz – 100<br>MHz Random<br>noise<br>~~ns~~|—|—|4.2|ps,<br>RMS|
|TRX-DJ<br>~~ee a~~<br>~~a~~<br>~~ee~~|Receiver deterministic jitter tolerance<br>~~a~~<br>~~rs~~<br>~~es~~|—<br>~~ns~~<br>~~es~~|—<br>~~es~~|—<br>~~ee~~|88|ps|
|VRX-CM-AC<br>~~a~~<br>~~ee~~|Common mode noise from Rx<br>~~rs ~~<br>~~es~~|—<br> ~~ns~~<br>~~es~~|—<br>~~es~~|—<br>~~ee~~||mV,<br>p-p|
|RLRX-DIFF<br>~~ee~~<br>~~oa~~<br>~~ee~~<br>~~a~~|Receiver differential Return Loss,<br>package plus silicon<br>~~es~~<br>~~oa~~<br>~~PF~~<br>~~es~~|50 MHz < freq <<br>1.25 GHz<br>~~es ~~<br>~~oa~~<br>~~PF~~|10<br> ~~es ~~<br>~~oa~~<br>|—<br> ~~ee~~<br>~~oa~~<br>|—<br>~~oa~~<br>|dB<br>~~oa~~<br>|
|||1.25 GHz < freq<br>< 2.5 GHz<br>~~oa~~<br>~~PFEE~~<br>~~es~~|8<br>~~oa~~<br>~~EE~~<br>~~es ee~~|—<br>~~oa~~<br>~~EE~~<br>~~ee~~|—<br>~~oa~~<br>~~EE~~|dB<br>~~oa~~<br>~~EE~~|
|RLRX-CM<br>~~oa~~<br>~~ee~~<br>~~a~~<br>~~ee~~|Receiver common mode Return Loss,<br>packageplus silicon<br>~~oa~~<br>~~PF~~<br>~~es~~<br>~~rn ts~~|—<br>~~oa~~<br>~~PFEE~~<br>~~es~~<br>~~ts~~|6<br>~~oa~~<br>~~EE~~<br>~~es ee~~<br>~~I~~|—<br>~~oa~~<br>~~EE~~<br>~~ee~~|—<br>~~oa~~<br>~~EE~~|dB<br>~~oa~~<br>~~EE~~|
|ZRX-DC<br>~~ee~~<br>~~a~~<br>~~ee~~|Receiver DC single ended impedance<br><br>~~es ~~<br>~~rn ts~~<br>~~es~~|—<br>~~EE~~<br> ~~es ~~<br>~~ts~~<br>~~es~~|40<br>~~EE~~<br> ~~es ee~~<br>~~I~~<br>~~es~~|—<br>~~EE~~<br>~~ee~~<br>~~es~~|60<br>~~EE~~|Ω<br>~~EE~~|
|ZRX-HIGH-IMP-DC<br>~~ee~~|Receiver DC single ended impedance<br>whenpowered down<br>~~rn ts~~<br>~~es~~|—<br>~~ts~~<br>~~es~~|200K<br>~~I~~<br>~~es~~|—<br>~~es~~|—|Ω|
|VRX-CM-AC-P<br>~~ee~~|Rx AC peak common mode voltage<br>~~rn ts~~<br>~~es~~|—<br>~~ts ~~<br>~~es ~~|—<br> ~~I~~<br> ~~es ~~|—<br> ~~es~~||mV,<br>peak|
|VRX-IDLE-DET-DIFF-PP|Electrical Idle Detect Threshold|—<br>~~Rr~~|65<br>~~tn~~|—<br>~~I~~|3403<br>~~I~~|mv,<br>pp|
|LRX-SKEW<br>~~nner~~|Receiver lane-lane skew<br>~~nner~~|—<br>~~nner~~<br>~~Rr~~|—<br>~~nner~~<br>~~tn~~|—<br>~~nner~~<br>~~I~~|8<br>~~nner~~<br>~~I~~|ns<br>~~nner~~|



**Notes** : 

1. Values are measured at 5 Gb/s. 

2. Measured with external AC-coupling on the receiver. 

3. Not in compliance with PCI Express standard. 

© 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02012-2.2 

79 

**ECP5 and ECP5-5G Family Data Sheet** 

## **3.26. CPRI LV2 E.48 Electrical and Timing Characteristics – Preliminary** 

**Table 3.32. CPRI LV2 E.48 Electrical and Timing Characteristics** 

|**Symbol**<br>~~a~~|**Description**<br>|**Test Conditions**<br>|**Min**<br>|**Typ**<br>|**Max**<br>|**Unit**<br>|
|---|---|---|---|---|---|---|
|**Transmit**<br>~~aEE~~|||||||
|UI<br>~~a~~|Unit Interval|—|203.43|203.45|203.47|ps|
|TDCD<br>~~a~~|Duty Cycle Distortion<br>~~a~~|—|—|—|0.05|UI|
|JUBHPJ<br>~~a ~~<br>~~a ee~~|Uncorrelated Bounded High<br>ProbabilityJitter<br> ~~a~~<br>~~ee~~|—<br>~~ee~~|—<br>~~ee~~|—<br>~~ee~~|0.15<br>~~ee~~|UI<br>~~ee~~|
|JTOTAL<br>~~a ee~~<br>~~a~~|Total Jitter<br>~~ee~~|—<br>~~ee~~|—<br>~~ee~~|—<br>~~ee~~|0.3<br>~~ee~~|UI<br>~~ee~~|
|ZRX-DIFF-DC<br>~~a~~|DC differential Impedance|—|80|—|120|Ω|
|TSKEW<br>~~a ~~<br>~~pf~~|Skew between differential signals<br> ~~a~~<br>~~pf~~|—<br>~~ee~~|—<br>~~ee~~|—<br>~~ee~~|9<br>~~ee~~|ps<br>~~ee~~|
|RLTX-DIFF<br>~~pf~~|Tx Differential Return Loss (S22),<br>including package and silicon<br>~~pf~~|100 MHz < freq<br>< 3.6864 GHz<br>~~ee~~|—<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~|–8<br>~~ee~~<br>~~ee~~|dB<br>~~ee~~<br>~~ee~~|
|||3.6864 GHz < freq<br>< 4.9152 GHz<br>~~ee~~|—<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~|–8 + 16.6 *log<br>(freq/3.6864)<br>~~ee~~<br>~~ee~~|dB<br>~~ee~~<br>~~ee~~|
|RLTX-CM<br>~~pf~~|Tx Common Mode Return Loss,<br>including package and silicon<br>~~pf ~~|100 MHz < freq<br>< 3.6864 GHz<br> ~~ee~~|6<br>~~ee~~<br>~~ee ~~|—<br>~~ee~~<br> ~~ee ~~|—<br>~~ee~~<br> ~~ee~~|dB<br>~~ee~~<br>~~ee~~|
|ITX-SHORT<br>~~a~~|Transmitter short-circuit current<br>~~a~~<br>~~a~~|—<br>~~a~~|—|—|100|mA|
|TRISE_FALL-DIFF<br>~~a~~<br>~~a~~|Differential Rise and Fall Time<br>~~a~~<br>~~a~~<br>~~a~~|—<br>~~a~~||—|—|ps|
|LTX-SKEW<br>~~a~~<br>~~eee~~|Lane-to-lane output skew<br>~~a~~<br>~~eee~~|—<br>~~eee ee~~|—<br>~~ee~~|—<br>~~ee~~|~~ee~~|ps<br>~~ee~~|
|**Receive**<br>~~eee ee~~|||||||
|UI<br>~~eee~~<br>~~a~~|Unit Interval<br>~~eee~~|—<br>~~eee ee~~|203.43<br>~~ee~~|203.45<br>~~ee~~|203.47<br>~~ee~~|ps<br>~~ee~~|
|VRX-DIFF-PP<br>~~a~~<br>~~a~~|Differential Rx peak-peak voltage|—|—|—|1.2|V, p-p|
|VRX-EYE_Y1_Y2<br>~~a~~|Receiver eye opening mask, Y1 and<br>Y2<br>~~ee~~|—<br>~~ee~~|62.5<br>~~ee~~|—<br>~~ee~~|375<br>~~ee~~|mV,<br>diff<br>~~ee~~|
|VRX-EYE_X1<br>~~a~~|Receiver eye opening mask, X1<br>~~a~~<br>~~a~~|—<br>~~a~~|—|—|0.3|UI|
|TRX-TJ<br>~~a~~<br>~~a~~<br>~~Pf~~|Receiver total jitter tolerance (not<br>includingsinusoidal)<br>~~a~~<br>~~a~~<br>~~aee~~<br>~~Pf~~|—<br>~~a~~<br>~~ee~~<br>~~rr~~|—<br>~~ee~~<br>~~rr~~|—<br>~~ee~~<br>~~rr~~|0.6<br>~~ee~~<br>~~rr~~|UI<br>~~ee~~<br>~~rr~~|
|RLRX-DIFF<br>~~a~~<br>~~Pf~~|Receiver differential Return Loss,<br>package plus silicon<br>~~aee~~<br>~~Pf~~|100 MHz < freq<br>< 3.6864 GHz<br>~~ee~~<br>~~rr~~|—<br>~~ee~~<br>~~rr~~|—<br>~~ee~~<br>~~rr~~|–8<br>~~ee~~<br>~~rr~~|dB<br>~~ee~~<br>~~rr~~|
|||3.6864 GHz < freq<br>< 4.9152 GHz<br>~~rr~~|—<br>~~rr~~|—<br>~~rr~~|–8 + 16.6 *log<br>(freq/3.6864)<br>~~rr~~|dB<br>~~rr~~|
|RLRX-CM<br>~~Pf~~<br>~~a~~|Receiver common mode Return<br>Loss,packageplus silicon<br>~~Pf ~~<br>~~a~~|—<br> ~~rr~~<br>~~a~~|6<br>~~rr~~<br>~~a~~|—<br>~~rr~~<br>~~a~~|—<br>~~rr~~<br>~~a~~|dB<br>~~rr~~<br>~~a~~|
|ZRX-DIFF-DC<br>~~a~~|Receiver DC differential impedance<br>~~a~~|—<br>~~a~~|80<br>~~a~~|100<br>~~a~~|120<br>~~a~~|Ω<br>~~a~~|



© 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

80 

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## **3.27. XAUI/CPRI LV E.30 Electrical and Timing Characteristics** 

## **3.27.1. AC and DC Characteristics** 

Over recommended operating conditions. 

**Table 3.33. Transmit** 

|**Symbol**|**Description**|**Test Conditions**|**Min**|**Typ**|**Max**|**Unit**|
|---|---|---|---|---|---|---|
|TRF|Differential rise/fall time|20% to 80%|—|80|—|ps|
|ZTX_DIFF_DC|Differential impedance|—|80|100|120|Ω|
|JTX_DDJ2, 3|Output data deterministicjitter|—|—|—|0.17|UI|
|JTX_TJ1, 2, 3|Total output datajitter|—|—|—|0.35|UI|



**Notes** : 

1. Total jitter includes both deterministic jitter and random jitter. 

2. Jitter values are measured with each CML output AC coupled into a 50 Ω impedance (100 Ω differential impedance). 

3. Jitter and skew are specified between differential crossings of the 50% threshold of the reference signal. 

Over recommended operating conditions. 

**Table 3.34. Receive and Jitter Tolerance** 

|**Symbol**<br>~~pf~~<br>~~a~~|**Description**<br>~~pf~~<br>~~ee~~|**Test Conditions**<br>~~pf~~|**Min**<br>~~pf~~|**Typ**<br>~~pf~~|**Max**<br>~~pf~~|**Unit**<br>~~pf~~|
|---|---|---|---|---|---|---|
|RLRX_DIFF<br>~~a~~|Differential return loss<br>~~ee~~|From 100 MHz<br>to 3.125 GHz|10|—|—|dB|
|RLRX_CM<br>~~a~~<br>~~a~~|Common mode return loss<br>~~ee~~<br>~~ee~~|From 100 MHz<br>to 3.125 GHz<br>~~ee~~|6<br>~~ee~~|—<br>~~ee~~|—<br>~~ee~~|dB<br>~~ee~~|
|ZRX_DIFF<br>~~OG~~|Differential termination resistance<br>~~OG~~|—<br>~~OG~~|80<br>~~OG~~|100<br>~~OG~~|120<br>~~OG~~|Ω<br>~~OG~~|
|JRX_DJ1, 2, 3<br>~~a~~|Deterministicjitter tolerance(peak-to-peak)|—|—|—|0.37|UI|
|JRX_RJ1, 2, 3<br>~~a~~<br>~~a GG~~|Randomjitter tolerance(peak-to-peak)<br>~~GG~~|—<br>~~GG~~|—<br>~~GG~~|—<br>~~GG~~|0.18<br>~~GG~~|UI<br>~~GG~~|
|JRX_SJ1, 2, 3<br>~~a GG~~<br>~~a OG~~<br>~~es~~|Sinusoidaljitter tolerance(peak-to-peak)<br>~~GG~~<br>~~OG~~<br>|—<br>~~GG~~<br>~~OG~~<br>|—<br>~~GG~~<br>~~OG~~<br>|—<br>~~GG~~<br>~~OG~~<br>~~CO~~<br>|0.10<br>~~GG~~<br>~~OG~~<br>~~CO~~<br>|UI<br>~~GG~~<br>~~OG~~<br>|
|JRX_TJ1, 2, 3<br>~~a ~~<br>~~es~~|Totaljitter tolerance(peak-to-peak)<br> ~~GG~~<br>|—<br>~~GG~~<br>|—<br>~~GG~~<br>|—<br>~~GG~~<br>~~CO~~<br>|0.65<br>~~GG~~<br>~~CO~~<br>|UI<br>~~GG~~<br>|
|TRX_EYE<br>~~es~~|Receiver eye opening<br>~~G~~|—<br>~~G~~|0.35<br>~~G~~|—<br>~~CO~~<br>~~G~~|—<br>~~CO~~<br>~~G~~|UI<br>~~G~~|



1. Total jitter includes deterministic jitter, random jitter and sinusoidal jitter. 

2. Jitter values are measured with each high-speed input AC coupled into a 50 Ω impedance. 

3. Jitter and skew are specified between differential crossings of the 50% threshold of the reference signal. 

## **3.28. CPRI LV E.24/SGMII (2.5 Gbps) Electrical and Timing Characteristics** 

## **3.28.1. AC and DC Characteristics** 

**Table 3.35. Transmit** 

|**Symbol**|**Description**|**Test Conditions**|**Min**|**Typ**|**Max**|**Unit**|
|---|---|---|---|---|---|---|
|TRF1|Differential rise/fall time|20% to 80%|—|80|—|ps|
|ZTX_DIFF_DC|Differential impedance|—|80|100|120|Ω|
|JTX_DDJ3, 4|Output data deterministic jitter|—|—|—|0.17|UI|
|JTX_TJ2, 3, 4|Total output data jitter|—|—|—|0.35|UI|



**Notes** : 

1. Rise and Fall times measured with board trace, connector and approximately 2.5 pf load. 

2. Total jitter includes both deterministic jitter and random jitter. The random jitter is the total jitter minus the actual deterministic jitter. 

3. Jitter values are measured with each CML output AC coupled into a 50 Ω impedance (100 Ω differential impedance). 

4. Jitter and skew are specified between differential crossings of the 50% threshold of the reference signal. 

© 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

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**Table 3.36. Receive and Jitter Tolerance** 

|**Symbol**<br>~~a ~~|**Description**<br> ~~eG~~|**Test Conditions**<br>~~eG~~|**Min**<br>~~eG~~|**Typ**<br>~~eG~~|**Max**<br>~~eG~~|**Unit**<br>~~eG~~|
|---|---|---|---|---|---|---|
|RLRX_DIFF<br>~~a GG~~|Differential return loss<br>~~GG~~|From 100 MHz to 2.5 GHz<br>~~GG~~|10<br>~~GG~~|—<br>~~GG~~|—<br>~~GG~~|dB<br>~~GG~~|
|RLRX_CM<br>~~a GG~~|Common mode return loss<br>~~GG~~|From 100 MHz to 2.5 GHz<br>~~GG~~|6<br>~~GG~~|—<br>~~GG~~|—<br>~~GG~~|dB<br>~~GG~~|
|ZRX_DIFF<br>~~a GO~~<br>~~a~~|Differential termination resistance<br>~~GO~~<br>~~a~~|—<br>~~GO~~<br>~~GG~~|80<br>~~GO~~<br>~~GG~~|100<br>~~GO~~<br>~~GO~~|120<br>~~GO~~|Ω<br>~~GO~~|
|JRX_DJ2, 3, 4<br>~~a~~|Deterministic jitter tolerance (peak-to-peak)<br>~~a~~|—<br>~~GG~~|—<br>~~GG~~|—<br>~~GO~~|0.37|UI|
|JRX_RJ2, 3, 4<br>~~a~~<br>~~a~~|Random jitter tolerance (peak-to-peak)<br>~~a~~<br>~~CO~~|—<br>~~GG~~<br>~~CO~~|—<br>~~GG~~<br>~~CO~~|—<br>~~GO~~<br>~~CO~~|0.18<br>~~CO~~|UI<br>~~CO~~|
|JRX_SJ2, 3, 4<br>~~a ~~<br>~~a ee~~|Sinusoidal jitter tolerance (peak-to-peak)<br> ~~GO~~<br>~~ee~~|—<br>~~GO~~<br>~~GO~~|—<br>~~GO~~<br>~~GO~~|—<br>~~GO~~|0.10<br>~~GO~~|UI<br>~~GO~~|
|JRX_TJ1, 2, 3, 4<br>~~a ee~~|Total jitter tolerance (peak-to-peak)<br>~~ee~~|—<br>~~GO~~|—<br>~~GO~~|—|0.65|UI|
|TRX_EYE<br>~~a ee~~<br>~~a ~~|Receiver eye opening<br>~~ee~~<br> ~~a~~|—<br>~~GO~~<br>~~DG~~|0.35<br>~~GO~~<br>~~DG~~|—<br>~~DG~~|—<br>~~DG~~|UI<br>~~DG~~|



**Notes** : 

1. Total jitter includes deterministic jitter, random jitter and sinusoidal jitter. 

2. Jitter values are measured with each high-speed input AC coupled into a 50 Ω impedance. 

3. Jitter and skew are specified between differential crossings of the 50% threshold of the reference signal. 

4. Jitter tolerance, Differential Input Sensitivity and Receiver Eye Opening parameters are characterized when Full Rx Equalization is enabled. 

## **3.29. Gigabit Ethernet/SGMII (1.25 Gbps)/CPRI LV E.12 Electrical and Timing Characteristics** 

## **3.29.1. AC and DC Characteristics** 

**Table 3.37. Transmit** 

|**Symbol**|**Description**|**Test Conditions**|**Min**|**Typ**|**Max**|**Unit**|
|---|---|---|---|---|---|---|
|TRF|Differential rise/fall time|20% to 80%|—|80|—|ps|
|ZTX_DIFF_DC|Differential impedance|—|80|100|120|Ω|
|JTX_DDJ2, 3|Output data deterministic jitter|—|—|—|0.10|UI|
|JTX_TJ1, 2, 3|Total output data jitter|—|—|—|0.24|UI|



**Notes** : 

1. Total jitter includes both deterministic jitter and random jitter. The random jitter is the total jitter minus the actual deterministic jitter. 

2. Jitter values are measured with each CML output AC coupled into a 50 Ω impedance (100 Ω differential impedance). 

3. Jitter and skew are specified between differential crossings of the 50% threshold of the reference signal. 

**Table 3.38. Receive and Jitter Tolerance** 

|**Symbol**<br>~~GO~~|**Description**<br>~~GO~~|**Test Conditions**<br>~~GO~~|**Min**<br>~~GO~~|**Typ**<br>~~GO~~|**Max**<br>~~GO~~|**Unit**<br>~~GO~~|
|---|---|---|---|---|---|---|
|RLRX_DIFF<br>~~GO~~<br>~~a GO~~|Differential return loss<br>~~GO~~<br>~~GO~~|From 100 MHz to 1.25 GHz<br>~~GO~~<br>~~GO~~|10<br>~~GO~~<br>~~GO~~|—<br>~~GO~~<br>~~GO~~|—<br>~~GO~~<br>~~GO~~|dB<br>~~GO~~<br>~~GO~~|
|RLRX_CM<br>~~a GC~~<br>~~a~~|Common mode return loss<br>~~GC~~<br>|From 100 MHz to 1.25 GHz<br>~~GC~~<br>|6<br>~~GC~~<br>~~G~~<br>|—<br>~~GC~~<br>~~G~~<br>|—<br>~~GC~~<br>|dB<br>~~GC~~<br>|
|ZRX_DIFF<br>~~a GC~~<br>~~aa~~<br>~~a~~<br>~~a~~|Differential termination resistance<br>~~GC~~<br>~~a~~<br><br>|—<br>~~GC~~<br>~~a~~<br><br>|80<br>~~GC~~<br>~~a~~<br>~~G~~<br><br>|100<br>~~GC~~<br>~~a~~<br>~~G~~<br><br>~~CO~~<br>|120<br>~~GC~~<br>~~a~~<br><br>|Ω<br>~~GC~~<br>~~a~~<br><br>|
|JRX_DJ1, 2, 3, 4<br>~~aGG~~<br>~~a~~|Deterministic jitter tolerance (peak-to-peak)<br>~~GG~~<br>|—<br>~~GG~~<br>|—<br>~~G~~<br>~~GG~~<br>|—<br>~~G~~<br>~~GG~~<br>~~CO~~<br>|0.34<br>~~GG~~<br>|UI<br>~~GG~~<br>|
|JRX_RJ1, 2, 3, 4<br>~~aGG~~<br>~~a GO~~|Random jitter tolerance (peak-to-peak)<br>~~GG~~<br>~~GO~~|—<br>~~GG~~<br>~~GO~~|—<br>~~G~~<br>~~GG~~<br>~~GO~~|—<br>~~G~~<br>~~GG~~<br>~~CO~~<br>~~GO~~|0.26<br>~~GG~~<br>~~GO~~|UI<br>~~GG~~<br>~~GO~~|
|JRX_SJ1, 2, 3, 4<br>~~a GO~~<br>~~GO~~|Sinusoidal jitter tolerance (peak-to-peak)<br>~~GO~~<br>~~GO~~|—<br>~~GO~~<br>~~GO~~|—<br>~~GO~~<br>~~GO~~|—<br>~~CO~~<br>~~GO~~<br>~~GO~~<br>~~CO~~|0.11<br>~~GO~~<br>~~GO~~|UI<br>~~GO~~<br>~~GO~~|
|JRX_TJ1, 2, 3, 4<br>~~a GG~~|Total jitter tolerance (peak-to-peak)<br>~~GG~~|—<br>~~GG~~|—<br>~~GG~~|—<br>~~GG~~<br>~~CO~~|0.71<br>~~GG~~|UI<br>~~GG~~|
|TRX_EYE<br>~~a GG~~<br>~~DO~~|Receiver eye opening<br>~~GG~~<br>~~DO~~|—<br>~~GG~~<br>~~DO~~|0.29<br>~~GG~~<br>~~DO~~|—<br>~~GG~~<br>~~CO~~<br>~~DO~~|—<br>~~GG~~<br>~~DO~~|UI<br>~~GG~~<br>~~DO~~|



1. Total jitter includes deterministic jitter, random jitter and sinusoidal jitter. 

2. Jitter values are measured with each high-speed input AC coupled into a 50 Ω impedance. 

3. Jitter and skew are specified between differential crossings of the 50% threshold of the reference signal. 

4. Jitter tolerance, Differential Input Sensitivity and Receiver Eye Opening parameters are characterized when Full Rx Equalization is enabled. 

© 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

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## **3.30. SMPTE SD/HD-SDI/3G-SDI (Serial Digital Interface) Electrical and Timing Characteristics** 

## **3.30.1. AC and DC Characteristics** 

**Table 3.39. Transmit** 

|**Symbol**<br>~~pO~~<br>~~es~~<br>~~pO~~|**Description**<br>~~pO~~<br>~~GG~~|**Test Conditions**<br>~~pO~~<br>~~GG~~|**Min**<br>~~pO~~<br>~~GG~~|**Typ**<br>~~pO~~<br>~~GG~~<br>~~CO~~|**Max**<br>~~pO~~<br>~~GG~~<br>~~CO~~|**Unit**<br>~~pO~~<br>~~GG~~|
|---|---|---|---|---|---|---|
|BRSDO<br>~~es~~<br>~~pO~~|Serial data rate<br>~~GG~~|—<br>~~GG~~|270<br>~~GG~~|—<br>~~GG~~<br>~~CO~~|2975<br>~~GG~~<br>~~CO~~|Mb/s<br>~~GG~~|
|TJALIGNMENT2<br>~~es~~<br>~~pO~~|Serial output jitter, alignment<br>~~GG~~|270 Mb/s6<br>~~GG~~|—<br>~~GG~~|—<br>~~GG~~<br>~~CO~~|0.2<br>~~GG~~<br>~~CO~~|UI<br>~~GG~~|
|TJALIGNMENT2<br>~~pO~~<br>~~pO~~|Serial output jitter, alignment<br>~~pO~~|1485 Mb/s<br>~~pO~~|—<br>~~pO~~|—<br>~~CO~~<br>~~pO~~|0.2<br>~~CO~~<br>~~pO~~|UI<br>~~pO~~|
|TJALIGNMENT1, 2<br>~~pO~~|Serial output jitter, alignment<br>~~pO~~|2970 Mb/s<br>~~pO~~|—<br>~~pO~~|—<br>~~pO~~<br>~~CO~~|0.3<br>~~pO~~<br>~~CO~~|UI<br>~~pO~~|
|TJTIMING<br>~~I ~~<br>~~ee~~|Serial output jitter, timing<br> ~~GG~~<br>|270 Mb/s6<br>~~GG~~|—<br>~~GG~~|—<br>~~GG~~<br>~~CO~~<br>~~G~~|0.2<br>~~GG~~<br>~~CO~~<br>~~G~~~~**O**~~|UI<br>~~GG~~|
|TJTIMING<br>~~GG~~<br>~~ee~~|Serial output jitter, timing<br>~~GG~~<br>~~Ce~~|1485 Mb/s<br>~~GG~~<br>~~GG~~|—<br>~~GG~~<br>~~GG~~|—<br>~~CO~~<br>~~GG~~<br>~~G~~<br>~~D~~|1<br>~~CO~~<br>~~GG~~<br>~~G~~~~**O**~~<br>~~D~~|UI<br>~~GG~~|
|TJTIMING<br>~~ee~~|Serial output jitter, timing<br>~~Ce~~|2970 Mb/s<br>~~GG~~|—<br>~~GG~~|—<br>~~G~~<br>~~D~~|2<br>~~G~~~~**O**~~<br>~~D~~|UI|



1. Timing jitter is measured in accordance with SMPTE serial data transmission standards. 

2. Jitter is defined in accordance with SMPTE RP1 184-1996 as: jitter at an equipment output in the absence of input jitter. 

3. All Tx jitter are measured at the output of an industry standard cable driver, with the Lattice SERDES device configured to 50 Ω output impedance connecting to the external cable driver with differential signaling. 

4. The cable driver drives: RL=75 Ω, AC-coupled at 270, 1485, or 2970 Mb/s. 

5. All LFE5UM/LFE5UM5G devices are compliant with all SMPTE compliance tests, except 3G-SDI Level-A pathological compliance pattern test. 

6. 270 Mb/s is supported with Rate Divider only. 

**Table 3.40. Receive** 

|**Symbol**|**Description**|**Test Conditions**|**Min**|**Typ**|**Max**|**Unit**|
|---|---|---|---|---|---|---|
|BRSDI|Serial input data rate|—|270|—|2970|Mb/s|



**Table 3.41** _**.**_ 

**Clock** 

|**Symbol**|**Description**|**Test Conditions**|**Min**|**Typ**|**Max**|**Unit**|
|---|---|---|---|---|---|---|
|FVCLK|Video output clock frequency|—|54|—|148.5|MHz|
|DCV|Duty cycle, video clock|—|45|50|55|%|



**Note** : SD-SDI (270 Mb/s) is supported with Rate Divider only. For Single Rate: Reference Clock = 54 MHz and Rate Divider = /2. For Tri-Rate: Reference Clock = 148.5 MHz and Rate Divider = /11. 

© 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

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**ECP5 and ECP5-5G Family Data Sheet** 

## **3.31. sysCONFIG Port Timing Specifications** 

Over recommended operating conditions. 

**Table 3.42. ECP5/ECP5-5G sysCONFIG Port Timing Specifications** 

|**Symbol**<br>~~a~~|**Parameter**<br>||**Min**<br>|**Max**<br>|**Unit**<br>|
|---|---|---|---|---|---|
|**POR, Configuration Initialization, and Wakeup**<br>~~Pe~~||||||
|tICFG|Time from the Application of VCC, VCCAUXor VCCIO8<br>(whichever is the last)to the risingedge of INITN|—|—|33|ms|
|tVMC<br>~~a~~|Time from tICFGto the valid Master CCLK<br>~~a~~|—<br>~~a~~|—<br>~~a~~|5<br>~~a~~|us<br>~~a~~|
|tCZ<br>~~a~~<br>~~a~~|CCLK from Active to High-Z<br>~~a~~<br>~~a~~|—<br>~~a~~<br>~~a~~|—<br>~~a~~<br>~~a~~|300<br>~~a~~<br>~~a~~|ns<br>~~a~~<br>~~a~~|
|**Master CCLK**||||||
|fMCLK|Frequency|All selected<br>frequencies|–20|20|%|
|tMCLK-DC|Duty Cycle|All selected<br>frequencies|40|60|%|
|**All Configuration Modes**<br>~~|~~||||||
|tPRGM<br>~~a~~|PROGRAMN LOW pulse accepted<br>~~a~~<br>~~a~~|—<br>~~a~~|110<br>~~a~~|—<br>~~a~~|ns<br>~~a~~|
|tPRGMRJ<br>~~I ~~|PROGRAMN LOW pulse rejected<br> ~~eG~~|—<br>~~eG~~|—<br>~~eG~~|50<br>~~eG~~|ns<br>~~eG~~|
|tINITL<br>~~a~~|INITN LOW time<br>~~GO~~|—<br>~~GO~~|—<br>~~GO~~|55<br>~~GO~~|ns<br>~~GO~~|
|tDPPINT<br>~~a~~|PROGRAMN LOW to INITN LOW|—|—|70|ns|
|tDPPDONE<br>~~a a~~|PROGRAMN LOW to DONE LOW<br>~~a~~|—|—|80|ns|
|tIODISS<br>~~a ~~|PROGRAMN LOW to I/O Disabled<br> ~~a~~|—|—|150|ns|
|**Slave SPI**<br>~~pe~~||||||
|fCCLK<br>~~pe~~<br>~~a~~|CCLK input clock frequency<br>~~pe~~<br>~~a~~<br>~~a~~|—<br>~~pe~~<br>~~a~~<br>~~a~~|—<br>~~pe~~<br>~~a~~<br>~~a~~|60<br>~~pe~~<br>~~a~~<br>~~a~~|MHz<br>~~pe~~<br>~~a~~<br>~~a~~|
|tCCLKH<br>~~a~~|CCLK input clock pulsewidth HIGH<br>~~a~~|—<br>~~a~~|6<br>~~a~~|—<br>~~a~~|ns<br>~~a~~|
|tCCLKL<br>~~a~~<br>~~a~~|CCLK input clock pulsewidth LOW<br>~~a~~<br>~~a~~<br>~~a~~|—<br>~~a~~<br>~~a~~|6<br>~~a~~<br>~~a~~|—<br>~~a~~<br>~~a~~|ns<br>~~a~~<br>~~a~~|
|tSTSU<br>~~a~~|CCLK setup time<br>~~a~~<br>~~a~~|—|1|—|ns|
|tSTH<br>~~a~~<br>~~a~~|CCLK hold time<br>~~a~~<br>~~a~~<br>~~a~~|—|1|—|ns|
|tSTCO<br>~~a~~<br>~~a~~|CCLK falling edge to valid output<br>~~a~~<br>~~a~~<br>~~a~~|—|—|10|ns|
|tSTOZ<br>~~a Ge~~|CCLK falling edge to valid disable<br>~~Ge~~|—<br>~~Ge~~|—<br>~~Ge~~|10<br>~~Ge~~|ns<br>~~Ge~~|
|tSTOV<br>~~a Ge~~<br>~~a~~|CCLK falling edge to valid enable<br>~~Ge~~|—<br>~~Ge~~|—<br>~~Ge~~|10<br>~~Ge~~|ns<br>~~Ge~~|
|tSCS<br>~~a~~|Chip Select HIGH time<br>~~a~~|—|25|—|ns|
|tSCSS<br>~~a ~~<br>~~a~~|Chip Select setup time<br> ~~a~~|—|3|—|ns|
|tSCSH<br>~~a~~|Chip Select hold time|—|3|—|ns|
|**Master SPI**||||||
|fCCLK<br>~~a~~|Max selected CCLK output frequency<br>~~eG~~|—<br>~~eG~~|—<br>~~eG~~|62<br>~~eG~~|MHz<br>~~eG~~|
|tCCLKH<br>~~a~~|CCLK output clock pulse width HIGH|—|3.5|—|ns|
|tCCLKL<br>~~a~~<br>~~a~~|CCLK output clock pulse width LOW|—|3.5|—|ns|
|tSTSU<br>~~a~~<br>~~a a~~|CCLK setup time<br>~~a~~|—|5|—|ns|
|tSTH<br>~~a Ge~~|CCLK hold time<br>~~Ge~~|—<br>~~Ge~~|1<br>~~Ge~~|—<br>~~Ge~~|ns<br>~~Ge~~|
|tCSSPI<br>~~a Ge~~<br>~~a~~|INITN HIGH to Chip Select LOW<br>~~Ge~~|—<br>~~Ge~~|100<br>~~Ge~~|200<br>~~Ge~~|ns<br>~~Ge~~|
|tCFGX<br>~~a a~~|INITN HIGH to first CCLK edge<br>~~a~~|—<br>~~a~~|—<br>~~a~~|150<br>~~a~~|ns<br>~~a~~|
|**Slave Serial**<br>~~a a~~<br>~~|~~||||||
|fCCLK<br>~~a~~|CCLK input clock frequency<br>~~a~~<br>~~a~~|—<br>~~a~~|—<br>~~a~~|66<br>~~a~~|MHz<br>~~a~~|
|tSSCH<br>~~a~~<br>~~a~~|CCLK input clock pulse width HIGH<br>~~a~~<br>~~a~~|—<br>~~a~~|5<br>~~a~~|—<br>~~a~~|ns<br>~~a~~|
|tSSCL<br>~~a~~<br>~~a~~|CCLK input clock pulse width LOW|—|5|—|ns|
|tSUSCDI<br>~~a a~~|CCLK setup time<br>~~a~~|—|0.5|—|ns|
|tHSCDI<br>~~a~~|CCLK hold time|—|1.5|—|ns|



© 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

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**Table 3.42. ECP5/ECP5-5G sysCONFIG Port Timing Specifications** 

|**Symbol**<br>**Parameter**<br>~~a a~~|||**Min**<br>~~GG~~|**Min**<br>~~GG~~|**Min**<br>~~GG~~|**Min**<br>~~GG~~|**Min**<br>~~GG~~|**Min**<br>~~GG~~|||**Max**|**Max**|**Max**||**Unit**|
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|**Slave Parallel**<br>~~pT~~||||||||||||||||
|fCCLK<br>CCLK input clock frequency<br>~~a~~<br>~~a~~|||||—||—|||||50|||MHz|
|tBSCH<br>CCLK input clock pulsewidth HIGH<br>~~a~~<br>~~a~~|||||—||6|||||—|||ns|
|tBSCL<br>CCLK input clock pulsewidth LOW<br>~~a~~|||||—||6|||||—|||ns|
|tCORD<br>CCLK to DOUT for Read Data<br>~~a~~|||||—||—|||||12|||ns|
|tSUCBDI<br>Data Setup Time to CCLK<br>—<br>1.5<br>—<br>ns<br>~~aeG~~||||||||||||||||
|tHCBDI<br>Data Hold Time to CCLK<br>~~a~~<br>~~a~~|||||—||1.5|||||—|||ns|
|tSUCS<br>CSN, CSN1 Setup Time to CCLK<br>~~a~~|||||—||2.5|||||—|||ns|
|tHCS<br>CSN, CSN1 Hold Time to CCLK<br>~~a~~|||||—||1.5|||||—|||ns|
|tSUWD<br>WRITEN Setup Time to CCLK<br>~~a~~|||||—||45|||||—|||ns|
|tHCWD<br>WRITEN Hold Time to CCLK<br>—<br>2<br>—<br>ns<br>tDCB<br>CCLK to BUSY Delay Time<br>—<br>—<br>12<br>ns<br>~~a~~<br>~~eG~~<br>~~a~~<br>~~G~~||||||||||||||||
||tBSCL||||||tBSCYC<br>tBSCH|||||||||
|CCLK<br>CS1N<br>CSN<br>WRITEN<br>tSUCS<br>tSUWD<br>~~AES~~<br>~~oa~~<br>~~a,~~<br>~~oe~~<br>~~|~~<br>~~ee~~||||||||||||||tHCS<br>tHWD||
||||||||tDCB|||||||||
|BUSY||||||||||||||||
||tCORD|||||||||||||||
|D[0:7]<br>Byte 0|Byte 1||||||Byte 2<br>Byte n*||||Byte n*|||||



**==> picture [95 x 8] intentionally omitted <==**

**----- Start of picture text -----**<br>
*n = last byte of read cycle.<br>**----- End of picture text -----**<br>


**Figure 3.15. sysCONFIG Parallel Port Read Cycle** 

© 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

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**==> picture [464 x 468] intentionally omitted <==**

**----- Start of picture text -----**<br>
t<br>BSCYC<br>t<br>BSCL t<br>BSCH |<br>CCLK*<br>t t<br>SUCS HCS<br>CS1N<br>CSN<br>ee,<br>t t<br>SUWD HWD<br>WRITEN<br>cro<br>t<br>DCB<br>BUSY<br>ABE<br>t<br>t HCBDI<br>SUCBDI<br>D[0:7] Byte 0 Byte 1 Byte 2 Byte n<br>( kX KKXX)<br>In Master Parallel Mode the FPGA provides CCLK (MCLK). In Slave Parallel Mode the external device provides CCLK.<br>Figure 3.16. sysCONFIG Parallel Port Write Cycle<br>t t<br>SSCL SSCH<br>CCLK (input)<br>t<br>eee a t eee HSCDI  a<br>SUSCDI<br>DIN<br>t<br>esoe CODO<br>DOUT<br>Figure 3.17. sysCONFIG Slave Serial Port Timing<br>**----- End of picture text -----**<br>


***** In Master Parallel Mode the FPGA provides CCLK (MCLK). In Slave Parallel Mode the external device provides CCLK. 

© 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

86 

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**ECP5 and ECP5-5G Family Data Sheet** 

**==> picture [234 x 159] intentionally omitted <==**

**----- Start of picture text -----**<br>
VCC/VCCAUX/<br>VCCIO8 1 tICFG<br>INITN<br>DONE<br>t<br>VMC<br>2<br>CCLK<br>3<br>CFG[2:0] Valid<br>**----- End of picture text -----**<br>


1.  Time taken from VCC, VCCAUX or VCCIO8, whichever is the last to cross the POR trip point. 

2.  Device is in a Master Mode (SPI, SPIm). 

3.  The CFG pins are normally static (hardwired). 

**Figure 3.18. Power-On-Reset (POR) Timing** 

**==> picture [456 x 200] intentionally omitted <==**

**----- Start of picture text -----**<br>
Wake Up Clocks<br>tICFG tSSCH<br>tVMC tSSCL<br>VCC FE 7 in<br>tPRGM<br>tPRGMRJ<br>CCLK<br>PROGRAMN<br>tDPPINIT<br>INITN se<br>tHSCDI (tHMCDI)<br>tSUSCDI (tSUMCDI) tCODO<br>DONE<br>Atle tDPPDONE ><br>DI<br>GOE Release<br>= OOO OOS —<br>DOUT ohaass na me s<br>tIOENSS<br>sysI/O<br>tIODISS<br>**----- End of picture text -----**<br>


**Figure 3.19. sysCONFIG Port Timing** 

© 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

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**==> picture [411 x 245] intentionally omitted <==**

**----- Start of picture text -----**<br>
t PRGMRJ<br>PROGRAMN<br>INITN tDPPI NIT<br>DONE t DINITD<br>2 ee<br>CCLK<br>Anne<br>CFG[2:0]* Valid<br>es t IODISS a<br>USER I/O<br>**----- End of picture text -----**<br>


*The CFG pins are normally static (hardwired). 

**Figure 3.20. Configuration from PROGRAMN Timing** 

## PROGRAMN 

**==> picture [455 x 140] intentionally omitted <==**

**----- Start of picture text -----**<br>
INITN<br>DONE Wake-Up<br>t<br>MWC<br>eS<br>CCLK<br>Ud tIOENSS AL<br>USER I/O<br>5ANWNWTNW___<br>**----- End of picture text -----**<br>


**Figure 3.21. Wake-Up Timing** 

© 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

88 

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**ECP5 and ECP5-5G Family Data Sheet** 

**==> picture [457 x 233] intentionally omitted <==**

**----- Start of picture text -----**<br>
Capture CR0 \ 4 Capture CFGx<br>VCC<br>PROGRAMN<br>ee ee ee<br>DONE<br>INITN =i\ nfF ee<br>CSSPIN<br>0   1    2    3   …      7    8   9   10   …     31 32  33 34  …    127  128<br>CCLK<br>SISPI sth}> DE Opcode pnn=inn Address =n<br>SOSPI Ignore Valid Bitstream<br>eee eee |X<br>Figure 3.22. Master SPI Configuration Waveforms<br>**----- End of picture text -----**<br>


## **3.32. JTAG Port Timing Specifications** 

Over recommended operating conditions. 

**Table 3.43. JTAG Port Timing Specifications** 

|**Symbol**<br>~~ee~~<br>~~ee~~<br>~~es~~|**Parameter**<br>~~eS~~<br>~~nn~~<br>|**Min**<br>~~eS~~<br>~~nn~~<br>~~I~~<br>|**Max**<br>~~eS~~<br>~~nn~~<br>|**Units**<br>~~eS~~<br>~~nn~~<br>|
|---|---|---|---|---|
|fMAX<br>~~ee~~<br>~~ee~~<br>~~es~~<br>~~a~~|TCK clock frequency<br>~~eS~~<br>~~nn~~<br>|—<br>~~eS~~<br>~~nn~~<br>~~I~~<br><br>~~I~~|25<br>~~eS~~<br>~~nn~~<br>|MHz<br>~~eS~~<br>~~nn~~<br>|
|tBTCPH<br>~~ee~~<br>~~es~~<br>~~a~~<br>~~es~~|TCK [BSCAN] clock pulse width high<br>~~nn~~<br>~~nnn~~<br>|20<br>~~nn~~<br>~~I~~<br>~~nnn~~<br>~~I~~<br>~~I~~<br>|—<br>~~nn~~<br>~~nnn~~<br>~~I~~<br>|ns<br>~~nn~~<br>~~nnn~~<br>|
|tBTCPL<br>~~es~~<br>~~a~~<br>~~es~~<br>~~ee~~|TCK [BSCAN] clock pulse width low<br><br><br>|20<br>~~I~~<br><br>~~I~~<br>~~I~~<br><br>~~I~~<br>|—<br><br>~~I~~<br><br>|ns<br><br><br>|
|tBTS<br>~~es~~<br>~~ee~~<br>~~es~~|TCK [BSCAN] setup time<br>~~ns~~<br><br>|10<br>~~I~~<br>~~ns~~<br>~~I~~<br><br>~~I~~<br>|—<br>~~I~~<br>~~ns~~<br><br>|ns<br>~~ns~~<br><br>|
|tBTH<br>~~es~~<br>~~ee~~<br>~~es~~<br>~~ee~~|TCK [BSCAN] hold time<br>~~ns~~<br>~~I~~<br>|8<br>~~I ~~<br>~~ns~~<br>~~I~~<br>~~I~~<br>~~I~~<br><br>~~I~~|—<br> ~~I~~<br>~~ns~~<br>~~I~~<br>|ns<br>~~ns~~<br>~~I~~<br>|
|tBTRF<br>~~ee~~<br>~~es~~<br>~~ee~~|TCK [BSCAN] rise/fall time<br><br>~~I~~|50<br>~~I~~<br><br>~~I~~<br>~~I~~<br>~~I~~|—<br><br>~~I~~|mV/ns<br><br>~~I~~|
|tBTCO<br>~~es~~<br>~~ee~~<br>~~a~~|TAP controller falling edge of clock to valid output<br>~~I~~|—<br>~~I~~<br>~~I~~<br>~~I~~<br>~~I~~|10<br>~~I~~<br>~~I~~|ns<br>~~I~~|
|tBTCODIS<br>~~ee~~<br>~~a~~<br>~~es~~<br>~~ee~~|TAP controller falling edge of clock to valid disable<br>~~ns~~<br>|—<br>~~I~~<br>~~I~~<br>~~ns~~<br>~~I~~<br>|10<br>~~I~~<br>~~ns~~<br>|ns<br>~~ns~~<br>|
|tBTCOEN<br>~~a~~<br>~~es~~<br>~~ee~~<br>~~ee~~|TAP controller falling edge of clock to valid enable<br>~~ns~~<br><br>|—<br>~~I ~~<br>~~ns~~<br>~~I~~<br><br>~~I~~<br>|10<br> ~~I~~<br>~~ns~~<br><br>|ns<br>~~ns~~<br><br>|
|tBTCRS<br>~~es~~<br>~~ee~~<br>~~ee~~<br>~~a~~|BSCAN test capture register setup time<br>~~ns~~<br>~~nn~~<br><br>|8<br>~~ns~~<br>~~I~~<br>~~nn~~<br>~~I~~<br><br>~~I~~<br>|—<br>~~ns~~<br>~~nn~~<br><br>|ns<br>~~ns~~<br>~~nn~~<br><br>|
|tBTCRH<br>~~ee~~<br>~~ee~~<br>~~a~~|BSCAN test capture register hold time<br><br>~~I~~<br>|25<br>~~I~~<br><br>~~I~~<br>~~I~~<br>~~I~~<br>|—<br><br>~~I~~<br>|ns<br><br>~~I~~<br>|
|tBUTCO<br>~~ee~~<br>~~a I~~<br>~~a~~|BSCAN test update register, falling edge of clock to valid output<br>~~I~~<br>~~I~~|—<br>~~I~~<br>~~I~~<br>~~I~~<br>~~I~~<br>~~I~~|25<br>~~I~~<br>~~I~~|ns<br>~~I~~<br>~~I~~|
|tBTUODIS<br>~~a I~~<br>~~a I~~<br>~~a~~|BSCAN test update register, falling edge of clock to valid disable<br>~~I~~<br>~~I~~|—<br>~~I~~<br>~~I~~<br>~~I~~<br>~~I~~|25<br>~~I~~<br>~~I~~|ns<br>~~I~~<br>~~I~~|
|tBTUPOEN<br>~~a I~~<br>~~a~~|BSCAN test update register, falling edge of clock to valid enable<br>~~I~~|—<br>~~I~~<br>~~I~~|25<br>~~I~~|ns<br>~~I~~|



© 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02012-2.2 

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**ECP5 and ECP5-5G Family Data Sheet** 

**==> picture [470 x 537] intentionally omitted <==**

**----- Start of picture text -----**<br>
TMS<br>TDI<br>tBTS tBTH<br>tBTCPH tBTCPL tBTCP<br>TCK<br>tBTCOEN tBTCO tBTCODIS<br>TDO V dilaD aat V  dilaD aat<br>tBTCRH<br>tBTCRS<br>Data to be<br>Captured Data Captured<br>from I/O<br>tBTUPOEN tBUTCO tBTUODIS<br>Data to be<br>driven out V dilaD aat V dilaD aat<br>to I/O ee<br>en a<br>Figure 3.23. JTAG Port Timing Waveforms<br>Switching Test Conditions<br>Figure 3.24 shows the output test load that is used for AC testing. The specific values for resistance, capacitance, shows the output test load that is used for AC testing. The specific values for resistance, capacitance,<br>voltage, and other test conditions are listed in Table 3.44. Table 3.44. .<br>V T<br>R1<br>DUT Test Point<br>R2 CL*<br>:<br>**----- End of picture text -----**<br>


## **3.33. Switching Test Conditions** 

Figure 3.24 shows the output test load that is used for AC testing. The specific values for resistance, capacitance, shows the output test load that is used for AC testing. The specific values for resistance, capacitance, voltage, and other test conditions are listed in Table 3.44. Table 3.44. . 

*CL Includes Test Fixture and Probe Capacitance 

**Figure 3.24. Output Test Load, LVTTL and LVCMOS Standards** 

© 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

90 

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**ECP5 and ECP5-5G Family Data Sheet** 

**Table 3.44. Test Fixture Required Components, Non-Terminated Interfaces** 

|**Test Condition**|**R1**|**R2**|**CL**|**Timing Ref.**|**VT**|
|---|---|---|---|---|---|
|LVTTL and other LVCMOS settings (L ≥ H, H ≥ L)|||0 pF|LVCMOS 3.3 = 1.5 V|—|
|||||LVCMOS 2.5 = VCCIO/2|—|
|||||LVCMOS 1.8 = VCCIO/2|—|
|||||LVCMOS 1.5 = VCCIO/2|—|
|||||LVCMOS 1.2 = VCCIO/2|—|
|LVCMOS 2.5 I/O (Z ≥ H)||1 MΩ|0 pF|VCCIO/2|—|
|LVCMOS 2.5 I/O (Z ≥ L)|1 MΩ||0 pF|VCCIO/2|VCCIO|
|LVCMOS 2.5 I/O (H ≥ Z)||100|0 pF|VOH– 0.10|—|
|LVCMOS 2.5 I/O (L ≥ Z)|100||0 pF|VOL+ 0.10|VCCIO|



**Note** : Output test conditions for all other interfaces are determined by the respective standards. 

© 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02012-2.2 

91 

**ECP5 and ECP5-5G Family Data Sheet** 

## **4. Pinout Information** 

## **4.1. Signal Descriptions** 

|**Signal Name**|**I/O**|**Description**|
|---|---|---|
|**General Purpose**|||
|P[L/R] [Group Number]_[A/B/C/D]|I/O|[L/R] indicates the L (Left), or R (Right) edge of the device. [Group Number]<br>indicates the PIO [A/B/C/D] group.<br>[A/B/C/D] indicates the PIO within the PIC to which the pad is connected.<br>Some of these user-programmable pins are shared with special function pins.<br>These pins, when not used as special purpose pins, can be programmed as I/O<br>for user logic. During configuration the user-programmable I/O are tristated with<br>an internal pull-down resistor enabled. If any pin is not used (or not bonded to a<br>package pin), it is tristated and default to have pull-down enabled after<br>configuration.<br>PIO A and B are grouped as a pair, and PIO C and D are group as a pair. Each pair<br>supports true LVDS differential input buffer. Only PIO A and B pair supports true<br>LVDS differential output buffer.<br>Each A/B and C/D pair supports programmable on/off differential input<br>termination of 100 Ω.|
|P[T/B][Group Number]_[A/B]|I/O|[T/B] indicates the T (top) or B (bottom) edge of the device. [Group Number]<br>indicates the PIO [A/B] group.<br>[A/B] indicates the PIO within the PIC to which the pad is connected. Some of<br>these user-programmable pins are shared with sysConfig pins. These pins, when<br>not used as configuration pins, can be programmed as I/O for user logic. During<br>configuration, the pins not used in configuration are tristated with an internal<br>pull-down resistor enabled. If any pin is not used (or not bonded to a package<br>pin), it is tristated and default to have pull-down enabled after configuration.<br>PIOs on top and bottom do not support differential input signaling or true LVDS<br>output signaling, but it can support emulated differential output buffer.<br>PIO A/B forms apair of emulated differential output buffer.|
|GSRN|I|Global RESET signal (active low). Any I/O pin can be GSRN.|
|NC|—|No connect.|
|RESERVED|—|This pin is reserved and should not be connected to anything on the board.|
|GND|—|Ground. Dedicated pins.|
|VCC|—|Power supply pins for core logic. Dedicated pins. VCC= 1.1 V (ECP5), 1.2 V<br>(ECP5UM5G)|
|VCCAUX|—|Auxiliary power supply pin. This dedicated pin powers all the differential and<br>referenced input buffers. VCCAUX= 2.5 V.|
|VCCIOx|—|Dedicated power supply pins for I/O bank x. VCCIO8is used for configuration and<br>JTAG.|
|VREF1_x|—|Reference supply pins for I/O bank x. Pre-determined shared pin in each bank<br>are assigned as VREF1 input. When not used,theymaybe used as I/Opins.|
|**PLL, DLL and Clock Functions**|||
|[LOC][_GPLL[T, C]_IN|I|General Purpose PLL (GPLL) input pads: [LOC] = ULC, LLC, URC and LRC, T = true<br>and C = complement. These pins are shared I/O pins. When not configured as<br>GPLL input pads, they can be used as general purpose I/O pins.|
|PCLK[T/C][Bank]_[num]|I/O|General Purpose Primary CLK pads: [T/C] = True/Complement, [Bank] = (0, 1, 2,<br>3, 6 and 7). There are two in each bank ([num] = 0, 1). These are shared I/ O pins.<br>When not configured as PCLK pins, they can be used as general purpose I/O pins.|



© 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

92 

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|**Signal Name**<br>~~ee~~|**I/O**<br>~~ee~~|**Description**<br>~~ee~~|
|---|---|---|
|**PLL, DLL and Clock Functions**<br>~~ee~~<br>~~a~~|||
|[L/R]DQS[group_num]<br>~~a~~<br>~~ee~~|I/O<br>~~a~~<br>~~ee~~|DQS input/output pads: T (top), R (right), group_ num = ball number associated<br>with DQS[T] pin.<br>~~a~~<br>~~ee~~|
|[T/R]]DQ[group_num]<br>~~ee~~<br>~~a~~|I/O<br>~~ee~~<br>~~a~~|DQ input/output pads: T (top), R (right), group_ num = ball number associated<br>with DQS[T] pin.<br>~~ee~~<br>~~a~~|
|**Test and Programming (Dedicated Pins)**<br>~~a~~<br>~~a~~|||
|TMS<br>~~a~~|I<br>~~a~~|Test Mode Select input, used to control the 1149.1 state machine. Pull-up is<br>enabled duringconfiguration. This is a dedicated inputpin.<br>~~a~~|
|TCK<br>~~rs~~|I<br>~~rs~~|Test Clock input pin, used to clock the 1149.1 state machine. No pull-up enabled.<br>This is a dedicated inputpin.|
|TDI<br>~~rs~~|I<br>~~rs~~|Test Data in pin. Used to load data into device using 1149.1 state machine. After<br>power-up, this TAP port can be activated for configuration by sending<br>appropriate command. (Note: once a configuration port is selected it is locked.<br>Another configuration port cannot be selected until the power-up sequence).<br>Pull-upis enabled duringconfiguration. This is a dedicated inputpin.|
|TDO<br>~~ee~~|O<br>~~ee~~|Output pin. Test Data Out pin used to shift data out of a device using 1149.1.<br>This is a dedicated outputpin.<br>~~ee~~|
|**Configuration Pads(Used during sysCONFIG)**<br>~~a~~|||
|CFG[2:0]|I|Mode pins used to specify configuration mode values latched on rising edge of<br>INITN. During configuration, a pull-up is enabled.<br>These are dedicatedpins.|
|INITN|I/O|Open Drain pin. Indicates the FPGA is ready to be configured. During<br>configuration, a pull-up is enabled.<br>This is a dedicatedpin.|
|PROGRAMN|I|Initiates configuration sequence when asserted low. This pin always has an<br>active pull-up.<br>This is a dedicatedpin.|
|DONE|I/O|Open Drain pin. Indicates that the configuration sequence is complete, and the<br>startup sequence is in progress.<br>This is a dedicatedpin.|
|CCLK|I/O|Input Configuration Clock for configuring an FPGA in Slave SPI, Serial, and CPU<br>modes. Output Configuration Clock for configuring an FPGA in Master<br>configuration modes (Master SPI, Master Serial).<br>This is a dedicated pin.|
|HOLDN/DI/BUSY/CSSPIN/CEN|I/O|Parallel configuration mode busy indicator. SPI/SPIm mode data output.<br>This is a shared I/O pin. This is a shared I/O pin. When not in configuration, it can<br>be used asgeneralpurpose I/Opin.|
|CSN/SN|I/O|Parallel configuration mode active-low chip select. Slave SPI chip select. This is a<br>shared I/O pin. When not in configuration, it can be used as general purpose I/O<br>pin.|
|CS1N|I|Parallel configuration mode active-low chip select.<br>This is a shared I/O pin. When not in configuration, it can be used as general<br>purpose I/Opin.|
|WRITEN|I|Write enable for parallel configuration modes.<br>This is a shared I/O pin. When not in configuration, it can be used as general<br>purpose I/Opin.|
|DOUT/CSON<br>~~es~~|O<br>~~es~~|Serial data output. Chip select output. SPI/SPIm mode chip select. This is a<br>shared I/Opin. When not in configuration,it can be used asgeneralpurpose I/O<br>~~es~~|
|D0/MOSI/IO0<br>~~es~~|I/O<br>~~es~~|Parallel configuration I/O. Open drain during configuration. When in SPI modes,<br>it is an output in Master mode, and input in Slave mode.<br>This is a shared I/O pin. When not in configuration, it can be used as general<br>purpose I/Opin.<br>~~es~~|



© 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02012-2.2 

All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

93 

**ECP5 and ECP5-5G Family Data Sheet** 

|**Signal Name**<br>~~eG~~|**I/O**<br>~~eG~~|**Description**<br>~~eG~~|
|---|---|---|
|**Configuration Pads(Used during sysCONFIG)**<br>~~RT~~|||
|D1/MISO/IO1|I/O|Parallel configuration I/O. Open drain during configuration. When in SPI<br>modes, it is an input in Master mode, and output in Slave mode.<br>This is a shared I/O pin. When not in configuration, it can be used as general<br>purpose I/Opin.|
|D2/IO2|I/O|Parallel configuration I/O. Open drain during configuration. When in SPI<br>modes, it is an input in Master mode, and output in Slave mode.<br>This is a shared I/O pin. When not in configuration, it can be used as general<br>purpose I/Opin.|
|D3/IO3|I/O|Parallel configuration I/O. Open drain during configuration. When in SPI<br>modes, it is an input in Master mode, and output in Slave mode.<br>This is a shared I/O pin. When not in configuration, it can be used as general<br>purpose I/Opin.|
|D4/IO4|I/O|Parallel configuration I/O. Open drain during configuration. This is a shared<br>I/O pin. When not in configuration, it can be used as general purpose I/O<br>pin.|
|D5/IO5|I/O|Parallel configuration I/O. Open drain during configuration. This is a shared<br>I/O pin. When not in configuration, it can be used as general purpose I/O<br>pin.|
|D6/IO6|I/O|Parallel configuration I/O. Open drain during configuration. This is a shared<br>I/O pin. When not in configuration, it can be used as general purpose I/O<br>pin.|
|D7/IO7|I/O|Parallel configuration I/O. Open drain during configuration.<br>This is a shared I/O pin. When not in configuration, it can be used as general<br>purpose I/O pin|
|**SERDES Function**<br>~~po~~|||
|VCCAx<br>~~po~~|—<br>~~po~~|SERDES, transmit, receive, PLL and reference clock buffer power supply for<br>SERDES Dual x. All VCCAsupply pins must always be powered to the<br>recommended operating voltage range. If no SERDES channels are used,<br>connect VCCAto VCC. VCCAx = 1.1 V for ECP5,VCCAx = 1.2 V for ECP5-5G.<br>~~po~~|
|VCCAUXAx<br>~~po~~|—<br>~~po~~|SERDES Aux Power Supply pin for SERDES Dual x. VCCAUXAx = 2.5 V.<br>~~po~~|
|HDRX[P/N]_D[dual_num]CH[chan_num]<br>~~po~~<br>~~a~~|I<br>~~po~~|High-speed SERDES inputs, P = Positive, N = Negative, dual_num = [0, 1],<br>chan_num =[0,1]. These are dedicated SERDES inputpins.<br>~~po~~|
|HDTX[P/N]_D[dual_num]CH[chan_num]<br>~~a~~<br>~~ee~~|O|High-speed SERDES outputs, P = Positive, N = Negative, dual_num = [0, 1],<br>chan_num =[0,1]. These are dedicated SERDES outputpins.|
|REFCLK[P/N]_D[dual_num]<br>~~ee~~|I|SERDES Reference Clock inputs, P = Positive, N = Negative, dual_num = [0, 1].<br>These are dedicated SERDES inputpins.|
|VCCHRX_D[dual_num]CH[chan_num]<br>~~ee~~|—|SERDES High-Speed Inputs Termination Voltage Supplies, dual_num = [0, 1],<br>chan_num = [0, 1]. These pins should be powered to 1.1 V on ECP5, or<br>1.2 V on ECP5-5G.|
|VCCHTX_D[dual_num]CH[chan_num]<br>~~ee~~|—|SERDES High-Speed Outputs Buffer Voltage Supplies, dual_num = [0, 1],<br>chan_num = [0, 1]. These pins should be powered to 1.1 V on ECP5, or 1.2 V<br>on ECP5-5G.|



## **Notes** : 

- When placing switching I/O around these critical pins that are designed to supply the device with the proper reference or supply voltage, care must be given. 

- These pins are dedicated inputs or can be used as general purpose I/O. 

© 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

94 

FPGA-DS-02012-2.2 

**ECP5 and ECP5-5G Family Data Sheet** 

## **4.2. PICs and DDR Data (DQ) Pins Associated with the DDR Strobe (DQS) Pin** 

|**PICs Associated with DQS Strobe**|**PIO within PIC**|**DDR Strobe (DQS) and Data (DQ) Pins**|
|---|---|---|
|**For Left and Right Edges of the Device Only**|||
|P[L/R] [n−6]|A|DQ|
||B|DQ|
||C|DQ|
||D|DQ|
|P[L/R] [n−3]|A|DQ|
||B|DQ|
||C|DQ|
||D|DQ|
|P[L/R] [n]|A|DQS (P)|
||B|DQS (N)|
||C|DQ|
||D|DQ|
|P[L/R] [n+3]|A|DQ|
||B|DQ|
||C|DQ|
||D|DQ|



**Note** : _n_ is a row PIC number. 

## **4.3. Pin Information Summary** 

## **4.3.1. LFE5UM/LFE5UM5G** 

|**Pin Information Summary**|**Pin Information Summary**|**LFE5UM/**<br>**LFE5UM5G-25**|**LFE5UM/**<br>**LFE5UM5G-25**|**LFE5UM/LFE5UM5G-45**|**LFE5UM/LFE5UM5G-45**|**LFE5UM/LFE5UM5G-45**|**LFE5UM/LFE5UM5G-85**|**LFE5UM/LFE5UM5G-85**|**LFE5UM/LFE5UM5G-85**|**LFE5UM/LFE5UM5G-85**|
|---|---|---|---|---|---|---|---|---|---|---|
|**Pin Type**||**285**<br>**csfBGA**|**381**<br>**caBGA**|**285**<br>**csfBGA**|**381**<br>**caBGA**|**554**<br>**caBG**|**285**<br>**csfBGA**|**381**<br>**caBG**|**554**<br>**caBGA**|**756**<br>**caBGA**|
|General Purpose<br>Inputs/Outputs per Bank<br>~~po~~<br>~~po~~<br>~~po~~<br>~~a~~|Bank 0<br>~~se~~<br>~~po~~|6<br>~~se~~|24<br>~~se ~~|6<br> ~~eG~~|27<br>~~eG~~|32<br>~~eG~~|6<br>~~eG~~|27|32|56|
||Bank 1<br>~~po~~<br>~~poCUT~~|6<br>~~CUT~~|32|6|33|40|6|33|40|48|
||Bank 2<br>~~po~~<br>~~poCUT~~|21<br>~~CUT~~|32|21<br>~~Ge~~|32<br>~~Gs~~|32<br>~~Gs~~|21<br>~~Gs~~|34|32|48|
||Bank 3<br>~~po CUT~~<br>~~se~~|28<br>~~CUT~~<br>~~se~~|32<br>~~se~~<br>~~eG~~|28<br>~~se~~<br>~~Ge~~<br>~~eG~~|33<br>~~se~~<br>~~Gs~~<br>~~eG~~|48<br>~~se~~<br>~~Gs~~|28<br>~~se~~<br>~~Gs~~|33<br>~~se~~|48<br>~~se~~|64<br>~~se~~|
||Bank 4<br>~~Re~~<br>~~po~~|0<br>~~Re~~<br>|0<br>~~Re~~<br>~~eG~~<br>|0<br>~~Ge ~~<br>~~Re~~<br>~~eG~~<br>|0<br> ~~Gs~~<br>~~Re~~<br>~~eG~~<br>~~eG~~<br>|0<br>~~Gs~~<br>~~Re~~<br>~~eG~~<br>|0<br>~~Gs~~<br>~~Re~~<br>~~eG~~<br>|0<br>~~Re~~<br>|14<br>~~Re~~<br>|24<br>~~Re~~<br>|
||Bank 6<br>~~Re~~<br>~~ee~~<br>~~po~~|26<br>~~Re~~<br>~~ee~~<br>|32<br>~~Re~~<br>~~eG~~<br>~~ee~~<br>|26<br>~~Re~~<br>~~eG~~<br>~~ee~~<br>|33<br>~~Re~~<br>~~eG~~<br>~~ee~~<br>~~eG~~<br>|48<br>~~Re~~<br>~~ee~~<br>~~eG~~<br>|26<br>~~Re~~<br>~~ee~~<br>~~eG~~<br>|33<br>~~Re~~<br>~~ee~~<br>|48<br>~~Re~~<br>~~ee~~<br>|64<br>~~Re~~<br>~~ee~~<br>|
||Bank 7<br>~~po~~|18<br>|32<br>|18<br><br>~~Ge~~|32<br>~~eG~~<br><br>~~GG~~|32<br>~~eG~~<br><br>~~GG~~|18<br>~~eG~~<br><br>~~GG~~|32<br>|32<br>|48<br>|
||Bank 8<br>~~poee~~|13<br>~~ee~~|13<br>~~ee~~|13<br>~~ee~~<br>~~Ge~~|13<br>~~eG~~<br>~~ee~~<br>~~GG~~|13<br>~~eG~~<br>~~ee~~<br>~~GG~~|13<br>~~eG~~<br>~~ee~~<br>~~GG~~<br>~~GG~~|13<br>~~ee~~<br>~~GG~~|13<br>~~ee~~<br>~~GG~~|13<br>~~ee~~|
|Total Single-Ended User I/O<br>~~ee~~<br>~~a~~||118<br>~~ee~~<br>~~GG~~|197<br>~~ee~~<br>~~GG~~|118<br>~~ee~~<br>~~Ge~~<br>~~GG~~|203<br>~~ee~~<br>~~GG~~<br>~~GG~~|245<br>~~ee~~<br>~~GG~~<br>~~GG~~|118<br>~~ee~~<br>~~GG~~<br>~~GG~~<br>~~GG~~|205<br>~~ee~~<br>~~GG~~<br>~~GG~~|259<br>~~ee~~<br>~~GG~~<br>~~GG~~|365<br>~~ee~~<br>~~GG~~|
|VCC<br>~~a~~<br>~~po~~||13<br>~~GG~~<br>~~po~~|20<br>~~GG~~<br>~~po~~|13<br>~~Ge ~~<br>~~GG~~<br>~~po~~|20<br> ~~GG~~<br>~~GG~~<br>~~po~~|24<br>~~GG~~<br>~~GG~~<br>~~po~~|13<br>~~GG~~<br>~~GG~~<br>~~GG~~<br>~~po~~|20<br>~~GG~~<br>~~GG~~<br>~~po~~|24<br>~~GG~~<br>~~GG~~<br>~~po~~|36<br>~~GG~~<br>~~po~~|
|VCCAUX (Core)<br>~~po~~<br>~~po~~||3<br>~~po~~<br>~~po~~|4<br>~~po~~<br>~~po~~|3<br>~~po~~<br>~~po~~|4<br>~~po~~<br>~~po~~|9<br>~~po~~<br>~~po~~|3<br>~~po~~<br>~~po~~|4<br>~~po~~<br>~~po~~|9<br>~~po~~<br>~~po~~|8<br>~~po~~<br>~~po~~|
|VCCIO<br>~~po~~|Bank 0<br>~~ee~~|1<br>~~ee~~|2<br>~~ee~~|1<br>~~GG~~|2<br>~~GG~~<br>~~Ge~~|3<br>~~GG~~<br>~~Ge~~|1<br>~~GG~~<br>~~Ge~~|2<br>~~GG~~|3|4|
||Bank 1<br>~~ee~~<br>~~ee~~|1<br>~~ee~~<br>~~ee~~|2<br>~~ee~~<br>~~ee~~|1<br>~~GG~~<br>~~ee~~<br>~~Ge~~|2<br>~~GG~~<br>~~ee~~<br>~~Ge~~<br>~~Gs~~|3<br>~~GG~~<br>~~ee~~<br>~~Ge~~<br>~~Gs~~|1<br>~~GG~~<br>~~ee~~<br>~~Ge~~<br>~~Gs~~|2<br>~~GG~~<br>~~ee~~|3<br>~~ee~~|4<br>~~ee~~|
||Bank 2<br>~~se~~|2<br>~~se~~|3<br>~~se~~<br>~~eG~~|2<br>~~se~~<br>~~Ge~~<br>~~eG~~|3<br>~~Ge~~<br>~~se~~<br>~~Gs~~<br>~~eG~~|4<br>~~Ge~~<br>~~se~~<br>~~Gs~~|2<br>~~Ge~~<br>~~se~~<br>~~Gs~~|3<br>~~se~~|4<br>~~se~~|4<br>~~se~~|
||Bank 3<br>~~Re~~|2<br>~~Re~~|3<br>~~Re~~<br>~~eG~~|2<br>~~Ge ~~<br>~~Re~~<br>~~eG~~|3<br> ~~Gs~~<br>~~Re~~<br>~~eG~~<br>~~eG~~|3<br>~~Gs~~<br>~~Re~~<br>~~eG~~|2<br>~~Gs~~<br>~~Re~~<br>~~eG~~|3<br>~~Re~~|3<br>~~Re~~|4<br>~~Re~~|
||Bank 4<br>~~Re~~<br>~~ee~~|0<br>~~Re~~<br>~~ee~~|0<br>~~Re~~<br>~~eG~~<br>~~ee~~|0<br>~~Re~~<br>~~eG~~<br>~~ee~~<br>~~GG~~|0<br>~~Re~~<br>~~eG~~<br>~~ee~~<br>~~eG~~<br>~~GG~~|0<br>~~Re~~<br>~~ee~~<br>~~eG~~|0<br>~~Re~~<br>~~ee~~<br>~~eG~~|0<br>~~Re~~<br>~~ee~~|2<br>~~Re~~<br>~~ee~~|2<br>~~Re~~<br>~~ee~~|
||Bank 6<br>~~ee~~<br>~~po~~|2<br>~~ee~~|3<br>~~ee~~|2<br>~~ee~~<br>~~GG~~|3<br>~~eG~~<br>~~ee~~<br>~~GG~~<br>~~GG~~|4<br>~~eG~~<br>~~ee~~<br>~~GG~~|2<br>~~eG~~<br>~~ee~~<br>~~GG~~|3<br>~~ee~~|4<br>~~ee~~|4<br>~~ee~~|
||Bank 7<br>~~ee~~<br>~~ee~~<br>~~po~~|2<br>~~ee~~<br>~~ee~~|3<br>~~ee~~<br>~~ee~~|2<br>~~ee~~<br>~~GG~~<br>~~ee~~|3<br>~~ee~~<br>~~GG~~<br>~~ee~~<br>~~GG~~|3<br>~~ee~~<br>~~ee~~<br>~~GG~~|2<br>~~ee~~<br>~~ee~~<br>~~GG~~|3<br>~~ee~~<br>~~ee~~|3<br>~~ee~~<br>~~ee~~|4<br>~~ee~~<br>~~ee~~|
||Bank 8<br>~~po~~|2|2|2|2<br>~~GG~~|2<br>~~GG~~|2<br>~~GG~~|2|2|2|



© 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02012-2.2 

95 

**ECP5 and ECP5-5G Family Data Sheet** 

|**Pin Information Summary**|**Pin Information Summary**|**LFE5UM/**<br>**LFE5UM5G-25**|**LFE5UM/**<br>**LFE5UM5G-25**|**LFE5UM/LFE5UM5G-45**|**LFE5UM/LFE5UM5G-45**|**LFE5UM/LFE5UM5G-45**|**LFE5UM/LFE5UM5G-85**|**LFE5UM/LFE5UM5G-85**|**LFE5UM/LFE5UM5G-85**|**LFE5UM/LFE5UM5G-85**|
|---|---|---|---|---|---|---|---|---|---|---|
|**Pin Type**||**285**<br>**csfBGA**|**381**<br>**caBGA**|**285**<br>**csfBGA**|**381**<br>**caBGA**|**554**<br>**caBG**|**285**<br>**csfBGA**|**381**<br>**caBG**|**554**<br>**caBGA**|**756**<br>**caBGA**|
|TAP<br>~~po~~||4<br>~~po~~|4<br>~~po~~|4<br>~~po~~|4<br>~~po~~|4<br>~~po~~|4<br>~~po~~|4<br>~~po~~|4<br>~~po~~|4<br>~~po~~|
|Miscellaneous Dedicated Pins<br>~~po~~<br>~~po~~||7<br>~~po~~<br>~~po~~|7<br>~~po~~<br>~~po~~|7<br>~~po~~<br>~~po~~|7<br>~~po~~<br>~~po~~|7<br>~~po~~<br>~~po~~|7<br>~~po~~<br>~~po~~|7<br>~~po~~<br>~~po~~|7<br>~~po~~<br>~~po~~|7<br>~~po~~<br>~~po~~|
|GND<br>~~po~~||83<br>~~po~~|59<br>~~po~~|83<br>~~po~~|59<br>~~po~~|113<br>~~po~~|83<br>~~po~~|59<br>~~po~~|113<br>~~po~~|166<br>~~po~~|
|NC<br>~~po~~||1<br>~~po~~|8<br>~~po~~|1<br>~~po~~|2<br>~~po~~|33<br>~~po~~|1<br>~~po~~|0<br>~~po~~|17<br>~~po~~|29<br>~~po~~|
|Reserved<br>~~po~~||0<br>~~po~~|2<br>~~po~~|0<br>~~po~~|2<br>~~po~~|4<br>~~po~~|0<br>~~po~~|2<br>~~po~~|4<br>~~po~~|4<br>~~po~~|
|SERDES<br>~~po~~||14<br>~~po~~|28<br>~~po~~<br>~~ee~~|14<br>~~po~~<br>~~ee~~|28<br>~~po~~<br>~~ee~~|28<br>~~po~~<br>~~ee ee~~|14<br>~~po~~<br>~~ee~~|28<br>~~po~~<br>~~ee~~|28<br>~~po~~<br>~~ee~~|28<br>~~po~~<br>~~ee~~|
|VCCA (SERDES)<br>~~po~~<br>~~ce~~<br>~~ee~~|VCCA0<br>~~po~~<br>~~ce~~|2<br>~~po~~<br>~~ce~~|2<br>~~po~~<br>~~ce~~<br>~~ee~~|2<br>~~po~~<br>~~ce~~<br>~~ee~~|2<br>~~po~~<br>~~ce~~<br>~~ee~~|6<br>~~po~~<br>~~ce~~<br>~~ee ee~~|2<br>~~po~~<br>~~ce~~<br>~~ee~~|2<br>~~po~~<br>~~ce~~<br>~~ee~~|6<br>~~po~~<br>~~ce~~<br>~~ee~~|8<br>~~po~~<br>~~ce~~<br>~~ee~~|
||VCCA1<br>~~ce~~<br>~~GG~~<br>~~ee~~|0<br>~~ce~~<br>~~GG~~<br>~~ee~~|2<br>~~ce~~<br>~~ee~~<br>~~GG~~<br>~~ee ee~~|0<br>~~ce~~<br>~~ee~~<br>~~GG~~<br>~~ee~~|2<br>~~ce~~<br>~~ee~~<br>~~GG~~<br>~~ee~~|6<br>~~ce~~<br>~~ee ee~~<br>~~GG~~<br>~~ee~~|0<br>~~ce~~<br>~~ee~~<br>~~GG~~|2<br>~~ce~~<br>~~ee~~<br>~~GG~~<br>~~eee~~|6<br>~~ce~~<br>~~ee~~<br>~~GG~~<br>~~eee~~|9<br>~~ce~~<br>~~ee~~<br>~~GG~~<br>~~eee~~|
|VCCAUXA (SERDES)<br>~~ce~~<br>~~ee~~<br>~~po~~|VCCAUXA0<br>~~ce~~<br>~~GG~~<br>~~ee~~<br>~~po~~|2<br>~~ce~~<br>~~GG~~<br>~~ee~~|2<br>~~ce~~<br>~~ee~~<br>~~GG~~<br>~~ee ee~~|2<br>~~ce~~<br>~~ee ~~<br>~~GG~~<br>~~ee~~|2<br>~~ce~~<br> ~~ee~~<br>~~GG~~<br>~~ee~~|2<br>~~ce~~<br>~~ee ee~~<br>~~GG~~<br>~~ee~~|2<br>~~ce~~<br>~~ee~~<br>~~GG~~|2<br>~~ce~~<br>~~ee~~<br>~~GG~~<br>~~eee~~|2<br>~~ce~~<br>~~ee~~<br>~~GG~~<br>~~eee~~|2<br>~~ce~~<br>~~ee~~<br>~~GG~~<br>~~eee~~|
||VCCAUXA1<br>~~ee~~<br>~~po~~|0<br>~~ee~~|2<br>~~ee ee~~|0<br>~~ee~~|2<br>~~ee~~|2<br>~~ee~~|0|2<br>~~eee~~|2<br>~~eee~~|2<br>~~eee~~|
|GNDA (SERDES)<br>~~ee~~<br>~~po~~<br>~~po~~||26<br>~~ee~~<br>~~po~~|26<br>~~ee ee~~<br>~~po~~|26<br>~~ee~~<br>~~po~~|26<br>~~ee~~<br>~~po~~|49<br>~~ee~~<br>~~po~~|26<br>~~po~~|26<br>~~eee~~<br>~~po~~|49<br>~~eee~~<br>~~po~~|60<br>~~eee~~<br>~~po~~|
|Total Balls<br>~~pO~~<br>~~PoC~~||285<br>~~pO~~<br>~~PoC~~|381<br>~~pO~~|285<br>~~pO~~|381<br>~~pO~~|554<br>~~pO~~|285<br>~~pO~~|381<br>~~pO~~|554<br>~~pO~~|756<br>~~pO~~|
|High Speed Differential<br>Input / Output Pairs<br>~~PoC~~<br>~~po~~|Bank 0<br>~~PoC~~<br>~~poCUT~~|0<br>~~PoC~~<br>~~CUT~~|0|0|0|0|0|0|0|0|
||Bank 1<br>~~PoC~~<br>~~poCUT~~<br>~~es~~|0<br>~~PoC~~<br>~~CUT~~<br>|0<br>|0<br>~~eG~~<br>|0<br>~~eG~~<br>|0<br>~~eG~~<br>|0<br>~~eG~~<br>|0<br>|0<br>|0<br>|
||Bank 2<br>~~po CUT~~<br>~~ee~~<br>~~es~~|10/8<br>~~CUT~~<br>~~ee~~<br>|16/8<br>~~ee~~<br>|10/8<br>~~ee~~<br>~~eG~~<br>|16/8<br>~~ee~~<br>~~eG~~<br>|16/8<br>~~ee~~<br>~~eG~~<br>|10/8<br>~~ee~~<br>~~eG~~<br>|17/9<br>~~ee~~<br>|16/8<br>~~ee~~<br>|24/12<br>~~ee~~<br>|
||Bank 3<br>~~es~~|14/7<br>~~se~~|16/8<br>~~se~~|14/7<br>~~eG~~<br>~~se~~<br>~~Oe~~|16/8<br>~~eG~~<br>~~se~~<br>~~GG~~|24/1<br>~~eG~~<br>~~se~~<br>~~GG~~|14/7<br>~~eG~~<br>~~se~~<br>~~GG~~|16/8<br>~~se~~|24/12<br>~~se~~|32/16<br>~~se~~|
||Bank 4<br>~~es~~<br>~~ee~~|0<br><br>~~ee~~|0<br><br>~~ee~~|0<br>~~eG~~<br><br>~~ee~~<br>~~Oe~~|0<br>~~eG~~<br><br>~~ee~~<br>~~GG~~|0<br>~~eG~~<br><br>~~ee~~<br>~~GG~~|0<br>~~eG~~<br><br>~~ee~~<br>~~GG~~|0<br><br>~~ee~~|0<br><br>~~ee~~|0<br><br>~~ee~~|
||Bank 6<br>~~es~~|13/6<br>~~es~~|16/8<br>~~es~~|13/6<br>~~Oe ~~<br>~~es~~<br>~~Se~~|16/8<br> ~~GG~~<br>~~es~~<br>~~Gs~~|24/1<br>~~GG~~<br>~~es~~<br>~~Gs~~|13/6<br>~~GG~~<br>~~es~~<br>~~Gs~~|16/8<br>~~es~~|24/12<br>~~es~~|32/16<br>~~es~~|
||Bank 7<br>~~es~~<br>~~ee~~|8/6<br>~~es~~<br>~~ee~~|16/8<br>~~es~~<br>~~ee~~|8/6<br>~~es~~<br>~~ee~~<br>~~Se~~|16/8<br>~~es~~<br>~~ee~~<br>~~Gs~~<br>~~GG~~|16/8<br>~~es~~<br>~~ee~~<br>~~Gs~~<br>~~GG~~|8/6<br>~~es~~<br>~~ee~~<br>~~Gs~~<br>~~GG~~|16/8<br>~~es~~<br>~~ee~~|16/8<br>~~es~~<br>~~ee~~|24/12<br>~~es~~<br>~~ee~~|
||Bank 8<br>~~se~~|0<br>~~se~~|0<br>~~se~~|0<br>~~Se ~~<br>~~se~~|0<br> ~~Gs~~<br>~~se~~<br>~~GG~~|0<br>~~Gs~~<br>~~se~~<br>~~GG~~|0<br>~~Gs~~<br>~~se~~<br>~~GG~~|0<br>~~se~~|0<br>~~se~~|0<br>~~se~~|
|Total High Speed Differential I/O Pairs<br>~~se~~<br>~~po~~<br>~~po~~||45/27<br>~~se~~<br>~~po~~<br>|64/32<br>~~se~~<br>~~po~~<br>|45/27<br>~~se~~<br>~~po~~<br>|64/32<br>~~se~~<br>~~GG~~<br>~~po~~<br>|80/4<br>~~se~~<br>~~GG~~<br>~~po~~<br>|45/27<br>~~se~~<br>~~GG~~<br>~~po~~<br>|65/3<br>~~se~~<br>~~po~~<br>|80/40<br>~~se~~<br>~~po~~<br>|112/5<br>~~se~~<br>~~po~~<br>|
|DQS Groups<br>(> 11 pins in group)<br>~~po~~<br>~~po~~<br>~~po~~<br>~~po~~<br>~~po~~|Bank 0<br>~~po~~<br>~~po~~|0<br>~~po~~<br>|0<br>~~po~~<br>|0<br>~~po~~<br>|0<br>~~po~~<br>|0<br>~~po~~<br>|0<br>~~po~~<br>|0<br>~~po~~<br>|0<br>~~po~~<br>|0<br>~~po~~<br>|
||Bank 1<br>~~pose~~<br>~~poCUT~~|0<br>~~se~~<br>~~CUT~~|0<br>~~se~~|0<br>~~se~~|0<br>~~se~~|0<br>~~se~~|0<br>~~se~~|0<br>~~se~~|0<br>~~se~~|0<br>~~se~~|
||Bank 2<br>~~se~~<br>~~poCUT~~<br>~~po~~|1<br>~~se~~<br>~~CUT~~<br>|2<br>~~se~~<br>|1<br>~~se~~<br>|2<br>~~se~~<br>|2<br>~~se~~<br>|1<br>~~se~~<br>|2<br>~~se~~<br>|2<br>~~se~~<br>|3<br>~~se~~<br>|
||Bank 3<br>~~po CUT~~<br>~~po~~|2<br>~~CUT~~<br>|2<br>|2<br>|2<br>|3<br>|2<br>|2<br>|3<br>|4<br>|
||Bank 4<br>~~poss~~<br>~~poCUT~~|0<br>~~ss~~<br>~~CUTCT~~|0<br>~~ss~~<br>~~CT~~|0<br>~~ss~~|0<br>~~ss~~|0<br>~~ss~~|0<br>~~ss~~|0<br>~~ss~~|0<br>~~ss~~|0<br>~~ss~~|
||Bank 6<br>~~poCUT~~|2<br>~~CUTCT~~|2<br>~~CT~~|2<br>~~OG~~|2<br>~~OG~~|3<br>~~GG~~|2<br>~~GG~~|2<br>~~GG~~|3<br>~~GG~~|4|
||Bank 7<br>~~po CUT~~<br>~~ee~~|1<br>~~CUT CT~~<br>~~ee~~|2<br>~~CT~~<br>~~ee~~|1<br>~~ee~~<br>~~OG~~|2<br>~~ee~~<br>~~OG~~|2<br>~~ee~~<br>~~GG~~|1<br>~~ee~~<br>~~GG~~|2<br>~~ee~~<br>~~GG~~|2<br>~~ee~~<br>~~GG~~|3<br>~~ee~~|
||Bank 8<br>~~ee~~<br>~~pC~~|0<br>~~ee~~<br>~~pC~~|0<br>~~ee~~<br>~~pC~~|0<br>~~ee~~<br>~~OG~~<br>~~pC~~|0<br>~~ee~~<br>~~OG ~~<br>~~pC~~|0<br>~~ee~~<br> ~~GG~~<br>~~pC~~|0<br>~~ee~~<br>~~GG~~<br>~~pC~~|0<br>~~ee~~<br>~~GG~~<br>~~pC~~|0<br>~~ee~~<br>~~GG~~<br>~~pC~~|0<br>~~ee~~<br>~~pC~~|
|Total DQS Groups<br>~~pe~~||6<br>~~pe~~|8<br>~~pe~~|6<br>~~pe~~|8<br>~~pe~~|10<br>~~pe~~|6<br>~~pe~~|8<br>~~pe~~|10<br>~~pe~~|14<br>~~pe~~|



© 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

96 

FPGA-DS-02012-2.2 

**ECP5 and ECP5-5G Family Data Sheet** 

## **4.3.2. LFE5U** 

|**Pin Information**<br>**Summary**|**Pin Information**<br>**Summary**|**LFE5U-12**|**LFE5U-12**|**LFE5U-12**|**LFE5U-12**|**LFE5U-25**|**LFE5U-25**|**LFE5U-25**|**LFE5U-25**|**LFE5U-45**|**LFE5U-45**|**LFE5U-45**|**LFE5U-45**|**LFE5U-45**|**LFE5U-85**|**LFE5U-85**|**LFE5U-85**|**LFE5U-85**|
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|**Pin Type**<br>~~a~~||**144**<br>**TQFP**<br>|**256**<br>**caBGA**<br>|**caBGA**<br>**285**<br>**csfBGA**<br>|**381**<br>**caBGA**<br>|**144**<br>**TQFP**<br>|**256**<br>**caBGA**<br>|**285**<br>**csfBGA**<br>|**381**<br>**caBGA**<br>|**caBGA**<br>**144**<br>**TQFP**<br>|**256**<br>**caBGA**<br>~~eG~~<br>|**285**<br>**csfBGA**<br>~~eG~~<br>|**381**<br>**caBGA**<br>|**554**<br>**caBGA**<br>|**caBGA**<br>**285**<br>**csfBGA**<br>|**381**<br>**caBGA**<br>|**554**<br>**caBGA**<br>|**756**<br>**caBGA**<br>|
|General<br>Purpose<br>Inputs/Outputs<br>per Bank<br>~~poof~~<br>~~po~~|Bank 0<br>~~ee~~<br>~~a~~|~~ee~~<br>|24<br>~~ee~~<br>|6<br>~~ee~~<br>|24<br>~~ee~~<br>|~~ee~~<br>|24<br>~~ee~~<br>|6<br>~~ee~~<br>|24<br>~~ee~~<br>|~~ee~~<br>|24<br>~~ee~~<br>~~eG~~<br>|6<br>~~ee~~<br>~~eG~~<br>|27<br>~~ee~~<br>|32<br>~~ee~~<br>|6<br>~~ee~~<br>|27<br>~~ee~~<br>|32<br>~~ee~~<br>|56<br>~~ee~~<br>|
||Bank 1<br>~~a~~<br>~~poof~~|~~a~~<br>~~poof~~<br>~~|~~|32<br>~~BO~~<br>~~|~~|6<br>~~BO~~<br>~~hc~~|32<br>~~BO~~<br>~~hcTT~~|~~BO~~<br>~~TT~~|32<br>~~BO~~<br>~~TT~~|6<br>~~BO~~|32<br>~~BO~~|~~BO~~|32<br>~~eG~~<br>~~BO~~|6<br>~~eG~~<br>~~BO~~|33<br>~~BO~~|40<br>~~BO~~|6<br>~~BO~~|33<br>~~BO~~|40<br>~~BO~~|48<br>~~BO~~|
||Bank 2<br>~~a ~~<br>~~poof~~<br>~~a~~|~~a~~<br>~~poof~~<br>~~|~~<br>|32<br>~~BO~~<br>~~|~~<br>|21<br>~~BO~~<br>~~hc~~<br>|32<br>~~BO~~<br>~~hcTT~~<br>|~~BO~~<br>~~TT~~<br>|32<br>~~BO~~<br>~~TT~~<br>~~ee~~<br>|21<br>~~BO~~<br>~~ee~~<br>|32<br>~~BO~~<br>~~fe~~<br>|~~BO~~<br>~~**e**~~<br>|32<br>~~eG~~<br>~~BO~~<br>~~**e**~~|21<br>~~eG~~<br>~~BO~~<br>~~**e**e~~|32<br>~~BO~~<br>~~e~~|32<br>~~BO~~<br>~~eG~~|21<br>~~BO~~<br>~~eG~~|34<br>~~BO~~|32<br>~~BO~~|48<br>~~BO~~|
||Bank 3<br>~~poof~~<br>~~Oe~~<br>~~a~~|~~poof~~<br>~~|~~<br>~~Oe~~<br>|32<br>~~|~~<br>~~Oe~~<br>|28<br>~~hc~~<br>~~Oe~~<br>|32<br>~~hc TT~~<br>~~Oe~~<br>|~~TT~~<br>~~Oe~~<br>|32<br>~~TT~~<br>~~Oe~~<br>~~ee~~<br>|28<br>~~Oe~~<br>~~ee~~<br>|32<br>~~Oe~~<br>~~fe~~<br>|~~Oe~~<br>~~**e**~~<br>|32<br>~~Oe~~<br>~~**e**~~|28<br>~~Oe~~<br>~~**e**e~~|33<br>~~Oe~~<br>~~e~~|48<br>~~Oe~~<br>~~eG~~|28<br>~~Oe~~<br>~~eG~~|33<br>~~Oe~~|48<br>~~Oe~~|64<br>~~Oe~~|
||Bank 4<br>~~a~~<br>~~a~~|~~B~~|0<br>~~B~~|0<br>~~B~~|0<br>~~B~~|~~B~~|0<br>~~ee~~<br>~~B~~|0<br>~~ee~~<br>~~B~~<br>~~fe~~|0<br>~~fe ~~<br>~~B~~<br>~~fe~~|~~**e**~~<br>~~B~~<br>~~fe~~|0<br>~~**e**~~<br>~~ee~~|0<br>~~**e**e~~<br>~~ee~~|0<br>~~e ~~<br>~~ee~~|0<br> ~~eG~~<br>~~eG~~|0<br>~~eG~~<br>~~eG~~|0|14|24|
||Bank 6<br>~~ee~~<br>~~a~~|~~ee~~|32<br>~~ee~~|26<br>~~ee~~|32<br>~~ee~~|~~ee~~|32<br>~~ee~~|26<br>~~ee~~<br>~~fe~~|32<br>~~ee~~<br>~~fe~~|~~ee~~<br>~~fe~~|32<br>~~ee~~<br>~~ee~~|26<br>~~ee~~<br>~~ee~~|33<br>~~ee~~<br>~~ee~~|48<br>~~ee~~<br>~~eG~~|26<br>~~ee~~<br>~~eG~~|33<br>~~ee~~|48<br>~~ee~~|64<br>~~ee~~|
||Bank 7<br>~~a~~||32|18|32||32|18<br>~~fe~~|32<br>~~fe~~|~~fe ~~|32<br> ~~ee~~|18<br>~~ee~~|32<br>~~ee ~~|32<br> ~~eG~~|18<br>~~eG~~|32|32|48|
||Bank 8<br>~~a~~||13|13<br>~~ee~~|13<br>~~ee~~|~~ee~~|13<br>~~ee~~|13<br>~~ee ee~~|13<br>~~ee~~|~~ee~~|13<br>~~ee~~|13|13|13|13|13|13|13|
|Total Single-Ended User I/O<br>~~a~~<br>~~po~~||~~|~~|197<br>~~|~~|118<br>~~ee~~<br>~~|~~|197<br>~~ee~~|~~ee~~|197<br>~~ee~~|118<br>~~ee ee~~|197<br>~~ee~~|~~ee~~|197<br>~~ee~~|118|203|245|118|205|259|365|
|VCC<br>~~a~~<br>~~po~~<br>~~po~~<br>~~po~~||~~po~~<br>~~o~~|6<br>~~po~~|13<br>~~ee~~<br>~~po~~|20<br>~~ee~~<br>~~po~~|~~ee~~<br>~~po~~|6<br>~~ee~~<br>~~po~~|13<br>~~ee ee~~<br>~~po~~|20<br>~~ee~~<br>~~po~~|~~ee~~<br>~~po~~|6<br>~~ee~~<br>~~po~~|13<br>~~po~~|20<br>~~po~~|24<br>~~po~~|13<br>~~po~~|20<br>~~po~~|24<br>~~po~~|36<br>~~po~~|
|VCCAUX(Core)<br>~~po~~<br>~~po~~||~~po~~<br>~~o~~|2<br>~~po~~|3<br>~~po~~|4<br>~~po~~|~~po~~|2<br>~~po~~|3<br>~~po~~|4<br>~~po~~|~~po~~|2<br>~~po~~|3<br>~~po~~|4<br>~~po~~|9<br>~~po~~|3<br>~~po~~|4<br>~~po~~|9<br>~~po~~|8<br>~~po~~|
|VCCIO<br>~~po~~<br>~~poof~~|Bank 0<br>~~o~~<br>~~a~~<br>~~poof~~|~~o~~<br>~~poof~~<br>~~|~~|2<br>~~|~~|1<br>~~hc~~|2<br>~~hcTT~~|~~TT~~|2<br>~~TT~~|1|2||2|1|2|3|1|2|3|4|
||Bank 1<br>~~a~~<br>~~poof~~|~~poof~~<br>~~|~~|2<br>~~|~~|1<br>~~hc~~|2<br>~~hcTT~~|~~TT~~|2<br>~~TT~~|1|2||2|1|2|3|1|2|3|4|
||Bank 2<br>~~poof~~<br>~~Oe~~|~~poof~~<br>~~|~~<br>~~Oe~~|2<br>~~|~~<br>~~Oe~~|2<br>~~hc~~<br>~~Oe~~|3<br>~~hc TT~~<br>~~Oe~~|~~TT~~<br>~~Oe~~|2<br>~~TT~~<br>~~Oe~~|2<br>~~Oe~~|3<br>~~Oe~~|~~Oe~~|2<br>~~Oe~~|2<br>~~Oe~~|3<br>~~Oe~~|4<br>~~Oe~~|2<br>~~Oe~~|3<br>~~Oe~~|4<br>~~Oe~~|4<br>~~Oe~~|
||Bank 3<br>~~a~~<br>~~a~~||2<br><br>|2<br><br>|3<br><br>||2<br><br>~~ee~~<br>|2<br><br>~~ee~~<br>|3<br><br>~~fe~~<br>|~~ee~~<br>|2<br><br>~~ee~~<br>|2<br><br>~~ee~~<br>|3<br><br>~~ee~~<br>|3<br><br>~~eG~~<br>|2<br><br>~~eG~~<br>|3<br><br>|3<br><br>|4<br><br>|
||Bank 4<br>~~Oe~~<br>~~a~~|~~Oe~~<br>|0<br>~~Oe~~<br>|0<br>~~Oe~~<br>|0<br>~~Oe~~<br>|~~Oe~~<br>|0<br>~~Oe~~<br>~~ee~~<br>|0<br>~~Oe~~<br>~~ee~~<br>|0<br>~~Oe~~<br>~~fe~~<br>|~~Oe~~<br>~~ee~~<br>|0<br>~~Oe~~<br>~~ee~~<br>|0<br>~~Oe~~<br>~~ee~~<br>|0<br>~~Oe~~<br>~~ee~~<br>|0<br>~~Oe~~<br>~~eG~~<br>|0<br>~~Oe~~<br>~~eG~~<br>|0<br>~~Oe~~<br>|2<br>~~Oe~~<br>|2<br>~~Oe~~<br>|
||Bank 6<br>~~a~~|~~a~~|2<br>~~BO~~|2<br>~~BO~~|3<br>~~BO~~|~~BO~~|2<br>~~ee~~<br>~~BO~~|2<br>~~ee~~<br>~~BO~~|3<br>~~fe~~<br>~~BO~~|~~ee~~<br>~~BO~~<br>~~eG~~|2<br>~~ee~~<br>~~BO~~<br>~~eG~~|2<br>~~ee~~<br>~~BO~~<br>~~eG~~|3<br>~~ee~~<br>~~BO~~<br>~~eG~~|4<br>~~eG~~<br>~~BO~~<br>~~eG~~|2<br>~~eG~~<br>~~BO~~<br>~~eG~~|3<br>~~BO~~|4<br>~~BO~~|4<br>~~BO~~|
||Bank 7<br>~~a ~~<br>~~ef~~|~~a~~<br>~~ef~~|2<br>~~BO~~<br>~~ef~~|2<br>~~BO~~<br>~~ef~~|3<br>~~BO~~<br>~~ef~~|~~BO~~<br>~~ef~~|2<br>~~ee~~<br>~~BO~~<br>~~ef~~|2<br>~~ee~~<br>~~BO~~<br>~~ef~~|3<br>~~fe ~~<br>~~BO~~<br>~~ef~~|~~ee~~<br>~~BO~~<br>~~ef~~<br>~~eG~~|2<br>~~ee~~<br>~~BO~~<br>~~ef~~<br>~~eG~~|2<br>~~ee~~<br>~~BO~~<br>~~ef~~<br>~~eG~~|3<br>~~ee ~~<br>~~BO~~<br>~~ef~~<br>~~eG~~|3<br> ~~eG~~<br>~~BO~~<br>~~ef~~<br>~~eG~~|2<br>~~eG~~<br>~~BO~~<br>~~ef~~<br>~~eG~~|3<br>~~BO~~<br>~~ef~~|3<br>~~BO~~<br>~~ef~~|4<br>~~BO~~<br>~~ef~~|
||Bank 8<br>~~ee~~|~~ee~~|1<br>~~ee~~|2<br>~~ee~~|2<br>~~ee~~|~~ee~~|1<br>~~ee~~|2<br>~~ee~~|2<br>~~ee~~|~~eG~~<br>~~ee~~|1<br>~~eG~~<br>~~ee~~|2<br>~~eG ~~<br>~~ee~~|2<br> ~~eG~~<br>~~ee~~|2<br>~~eG~~<br>~~ee~~|2<br>~~eG~~<br>~~ee~~|2<br>~~ee~~|2<br>~~ee~~|2<br>~~ee~~|
|TAP<br>~~Eee~~||~~Eee~~|4<br>~~Eee~~|4<br>~~Eee~~|4<br>~~Eee~~|~~Eee~~|4<br>~~Eee~~|4<br>~~Eee~~|4<br>~~Eee~~|~~Eee~~|4<br>~~Eee~~|4<br>~~Eee~~|4<br>~~Eee~~|4<br>~~Eee~~|4<br>~~Eee~~|4<br>~~Eee~~|4<br>~~Eee~~|4<br>~~Eee~~|
|Miscellaneous Dedicated<br>Pins<br>~~Eee~~<br>~~po~~||~~Eee~~<br>|7<br>~~Eee~~<br>|7<br>~~Eee~~<br>|7<br>~~Eee~~<br>|~~Eee~~<br>|7<br>~~Eee~~<br>|7<br>~~Eee~~<br>|7<br>~~Eee~~<br>|~~Eee~~<br>|7<br>~~Eee~~<br>|7<br>~~Eee~~<br>|7<br>~~Eee~~<br>|7<br>~~Eee~~<br>|7<br>~~Eee~~<br>|7<br>~~Eee~~<br>|7<br>~~Eee~~<br>|7<br>~~Eee~~<br>|
|GND<br>~~po~~|||27<br>|123<br>|99<br>||27<br>|123<br>|99<br>||27<br>|123<br>|113<br>|198<br>|123<br>|113<br>|198<br>|267<br>|
|NC<br>~~popo~~<br>~~po~~||~~po~~|0<br>~~po~~|1<br>~~po~~|26<br>~~po~~|~~po~~|0<br>~~po~~|1<br>~~po~~|26<br>~~po~~|~~po~~|0<br>~~po~~|1<br>~~po~~|2<br>~~po~~|33<br>~~po~~|1<br>~~po~~|0<br>~~po~~|33<br>~~po~~|29<br>~~po~~|
|Reserved<br>~~po~~<br>~~po fe~~||~~fe~~|0<br>~~fe~~|4<br>~~fe~~|6<br>~~fe~~|~~fe~~|0<br>~~fe~~|4<br>~~fe~~|6<br>~~fe~~|~~fe~~|0<br>~~fe~~|4<br>~~fe~~|10<br>~~fe~~|12<br>~~fe~~|4<br>~~fe~~|10<br>~~fe~~|12<br>~~fe~~|12<br>~~fe~~|
|Total Balls<br>~~po~~<br>~~po fe~~<br>~~a~~||~~fe~~<br>|256<br>~~fe~~<br>|285<br>~~fe~~<br>|381<br>~~fe~~<br>|~~fe~~<br>|256<br>~~fe~~<br>|285<br>~~fe~~<br>|381<br>~~fe~~<br>|~~fe~~<br>|256<br>~~fe~~<br>~~eG~~<br>|285<br>~~fe~~<br>~~eG~~<br>|381<br>~~fe~~<br><br>|554<br>~~fe~~<br>~~OG~~<br>|285<br>~~fe~~<br>~~OG~~<br>|381<br>~~fe~~<br>|554<br>~~fe~~<br>|756<br>~~fe~~<br>|
|High Speed<br>Differential<br>Input /Output<br>Pairs<br>~~po fe~~|Bank 0<br>~~fe~~<br>~~a~~<br>~~a~~|~~fe~~<br><br>|0<br>~~fe~~<br><br>|0<br>~~fe~~<br><br>|0<br>~~fe~~<br><br>|~~fe~~<br><br>|0<br>~~fe~~<br><br>|0<br>~~fe~~<br><br>~~ee~~<br>|0<br>~~fe~~<br><br>~~ee~~<br>|~~fe~~<br><br>~~ee~~<br>|0<br>~~fe~~<br>~~eG~~<br><br>|0<br>~~fe~~<br>~~eG~~<br><br>|0<br>~~fe~~<br><br><br>|0<br>~~fe~~<br>~~OG~~<br><br>|0<br>~~fe~~<br>~~OG~~<br><br>|0<br>~~fe~~<br><br>|0<br>~~fe~~<br><br>|0<br>~~fe~~<br><br>|
||Bank 1<br>~~a~~<br>~~a~~|~~Be~~<br>|0<br>~~Be~~<br>|0<br>~~Be~~<br>|0<br>~~Be~~<br>|~~Be~~<br>|0<br>~~Be~~<br>|0<br>~~Be~~<br>~~ee~~<br>|0<br>~~Be~~<br>~~ee~~<br>|~~Be~~<br>~~ee~~<br>|0<br>~~eG~~<br>~~Be~~<br>|0<br>~~eG~~<br>~~Be~~<br>|0<br><br>~~Be~~<br>|0<br>~~OG~~<br>~~Be~~<br>|0<br>~~OG~~<br>~~Be~~<br>|0<br>~~Be~~<br>|0<br>~~Be~~<br>|0<br>~~Be~~<br>|
||Bank 2<br>~~a~~<br>~~a~~<br>~~a~~|~~Be~~<br><br>|16/8 10/8 16/8<br>~~Be~~<br><br>|16/8 10/8 16/8<br>~~Be~~<br><br>|16/8 10/8 16/8<br>~~Be~~<br><br>|~~Be~~<br><br>|16/8 10/8 16/8<br>~~Be~~<br><br>|16/8 10/8 16/8<br>~~Be~~<br>~~ee~~<br><br>|16/8 10/8 16/8<br>~~Be~~<br>~~ee~~<br><br>|~~Be~~<br>~~ee~~<br><br>|16/8 10/8 16/8<br>~~eG~~<br>~~Be~~<br><br>~~ee~~<br>|16/8 10/8 16/8<br>~~eG ~~<br>~~Be~~<br><br>~~ee~~<br>|16/8 10/8 16/8<br> <br>~~Be~~<br><br>~~ee~~<br>|16/8<br> ~~OG~~<br>~~Be~~<br><br>~~GO~~<br>|10/8 17/9<br>~~OG~~<br>~~Be~~<br><br>~~GO~~<br>|10/8 17/9<br>~~Be~~<br><br>|16/8<br>~~Be~~<br><br>|24/1<br>~~Be~~<br><br>|
||Bank 3<br>~~aee~~<br>~~a~~<br>~~a~~|~~ee~~<br><br>|16/8 14/7 16/8<br>~~ee~~<br><br>|16/8 14/7 16/8<br>~~ee~~<br><br>|16/8 14/7 16/8<br>~~ee~~<br><br>|~~ee~~<br><br>|16/8 14/7 16/8<br>~~ee~~<br><br>|16/8 14/7 16/8<br>~~ee~~<br>~~ee~~<br><br>~~ee~~<br>|16/8 14/7 16/8<br>~~ee~~<br>~~ee~~<br><br>~~ee~~<br>|~~ee~~<br>~~ee~~<br><br>~~ee~~<br>|16/8 14/7 16/8 24/12 14/7 16/8 24/12 32/1<br>~~ee~~<br>~~ee~~<br><br>|16/8 14/7 16/8 24/12 14/7 16/8 24/12 32/1<br>~~ee~~<br>~~ee~~<br><br>|16/8 14/7 16/8 24/12 14/7 16/8 24/12 32/1<br>~~ee~~<br>~~ee~~<br><br>|16/8 14/7 16/8 24/12 14/7 16/8 24/12 32/1<br>~~ee~~<br>~~GO~~<br><br>|16/8 14/7 16/8 24/12 14/7 16/8 24/12 32/1<br>~~ee~~<br>~~GO~~<br><br>|16/8 14/7 16/8 24/12 14/7 16/8 24/12 32/1<br>~~ee~~<br><br>|16/8 14/7 16/8 24/12 14/7 16/8 24/12 32/1<br>~~ee~~<br><br>|16/8 14/7 16/8 24/12 14/7 16/8 24/12 32/1<br>~~ee~~<br><br>|
||Bank 4<br>~~a~~<br>~~a~~|~~Be~~<br>|0<br>~~Be~~<br>|0<br>~~Be~~<br>|0<br>~~Be~~<br>|~~Be~~<br>|0<br>~~Be~~<br>|0<br>~~Be~~<br>~~ee~~<br>|0<br>~~Be~~<br>~~ee~~<br>|~~Be~~<br>~~ee~~<br>|0<br>~~ee~~<br>~~Be~~<br>|0<br>~~ee~~<br>~~Be~~<br>|0<br>~~ee~~<br>~~Be~~<br>|0<br>~~GO~~<br>~~Be~~<br>|0<br>~~GO~~<br>~~Be~~<br>|0<br>~~Be~~<br>|0<br>~~Be~~<br>|0<br>~~Be~~<br>|
||Bank 6<br>~~a~~<br>~~a~~<br>~~a~~|~~Be~~<br>|16/8 13/6 16/8<br>~~Be~~<br>|16/8 13/6 16/8<br>~~Be~~<br>|16/8 13/6 16/8<br>~~Be~~<br>|~~Be~~<br>|16/8 13/6 16/8<br>~~Be~~<br>|16/8 13/6 16/8<br>~~Be~~<br>~~ee~~<br>|16/8 13/6 16/8<br>~~Be~~<br>~~ee~~<br>|~~Be~~<br>~~ee~~<br>|16/8 13/6 16/8 24/12 13/6 16/8 24/12 32/1<br>~~ee~~<br>~~Be~~<br><br>~~ee~~|16/8 13/6 16/8 24/12 13/6 16/8 24/12 32/1<br>~~ee~~<br>~~Be~~<br><br>~~ee~~|16/8 13/6 16/8 24/12 13/6 16/8 24/12 32/1<br>~~ee~~<br>~~Be~~<br><br>~~ee~~|16/8 13/6 16/8 24/12 13/6 16/8 24/12 32/1<br>~~GO~~<br>~~Be~~<br><br>~~GO~~|16/8 13/6 16/8 24/12 13/6 16/8 24/12 32/1<br>~~GO~~<br>~~Be~~<br><br>~~GO~~|16/8 13/6 16/8 24/12 13/6 16/8 24/12 32/1<br>~~Be~~<br>|16/8 13/6 16/8 24/12 13/6 16/8 24/12 32/1<br>~~Be~~<br>|16/8 13/6 16/8 24/12 13/6 16/8 24/12 32/1<br>~~Be~~<br>|
||Bank 7<br>~~aee~~<br>~~a~~|~~ee~~|16/8<br>~~ee~~|8/6<br>~~ee~~|16/8<br>~~ee~~|~~ee~~|16/8<br>~~ee~~|8/6<br>~~ee~~<br>~~ee~~|16/8<br>~~ee~~<br>~~ee~~|~~ee~~<br>~~ee~~|16/8<br>~~ee~~<br>~~ee~~|8/6<br>~~ee~~<br>~~ee~~|16/8<br>~~ee~~<br>~~ee~~|16/8<br>~~ee~~<br>~~GO~~|8/6<br>~~ee~~<br>~~GO~~|16/8<br>~~ee~~|16/8<br>~~ee~~|24/1<br>~~ee~~|
||Bank 8<br>~~a~~||0|0|0||0|0|0||0<br>~~ee~~|0<br>~~ee~~|0<br>~~ee~~|0<br>~~GO~~|0<br>~~GO~~|0|0|0|
|Total High Speed<br>Differential I/O Pairs<br>~~a~~<br>~~a ~~||~~ee~~|64/32 45/27 64/32<br>~~ee~~|64/32 45/27 64/32<br>~~eee~~|64/32 45/27 64/32<br>~~eee~~|64/32 45/27 64/32<br>~~eee~~|64/32 45/27 64/32<br>~~eee~~|64/32 45/27 64/32<br>~~eee~~|64/32 45/27 64/32<br>~~eee~~|64/32 45/27 64/32<br>~~eee~~|64/32 45/27 64/32 80/40 45/27 65/33 80/40 112/56<br>~~ee~~<br>~~eee~~|64/32 45/27 64/32 80/40 45/27 65/33 80/40 112/56<br>~~ee~~<br>~~eee~~|64/32 45/27 64/32 80/40 45/27 65/33 80/40 112/56<br>~~ee~~<br>~~eee~~|64/32 45/27 64/32 80/40 45/27 65/33 80/40 112/56<br>~~GO~~<br>~~eee~~|64/32 45/27 64/32 80/40 45/27 65/33 80/40 112/56<br>~~GO~~<br>~~eee~~|64/32 45/27 64/32 80/40 45/27 65/33 80/40 112/56<br>~~eee~~|64/32 45/27 64/32 80/40 45/27 65/33 80/40 112/56<br>~~eee~~|64/32 45/27 64/32 80/40 45/27 65/33 80/40 112/56<br>~~eee~~|
|DQS Groups<br>(> 11 pins in<br>group)|Bank 0<br>~~ee~~|~~ee~~|0<br>~~ee~~|0<br>~~ee~~|0<br>~~ee~~|~~ee~~|0<br>~~ee~~|0<br>~~ee~~|0<br>~~ee~~|~~ee~~|0<br>~~ee~~|0<br>~~ee~~|0<br>~~ee~~|0<br>~~ee~~|0<br>~~ee~~|0<br>~~ee~~|0<br>~~ee~~|0<br>~~ee~~|
||Bank 1<br>~~a~~|~~a~~|0|0|0||0|0|0||0|0|0|0|0|0|0|0|
||Bank 2<br>~~a~~<br>~~a~~|~~a~~<br>~~a~~|2|1|2||2|1|2||2|1|2|2|1|2|2|3|
||Bank 3<br>~~a~~|~~a~~|2|2<br>~~ee~~|2<br>~~ee~~|~~ee~~|2|2<br>~~fe~~|2<br>~~fe~~||2<br>~~ee~~|2<br>~~ee~~|2<br>~~ee~~|3|2|2|3|4|
||Bank 4<br>~~a~~<br>~~a~~|~~BB~~<br>~~a~~|0<br>~~BB~~<br>~~a~~|0<br>~~ee~~<br>|0<br>~~ee~~<br>|~~ee~~<br>|0<br>~~ee~~<br>|0<br>~~ee~~<br>|0<br>~~ee~~<br>|~~ee~~<br>|0<br>~~ee~~<br>~~**e**G~~<br>|0<br>~~ee~~<br>~~G~~|0<br>~~ee~~|0<br>~~ee~~|0<br>~~ee~~|0<br>~~ee~~|0<br>~~ee~~|0<br>~~ee~~|
||Bank 6<br>~~a ~~<br>~~fe~~<br>~~a~~|~~BB~~<br>~~fe~~<br>~~a~~|2<br>~~BB~~<br>~~fe~~<br>~~a~~|2<br>~~ee~~<br>~~fe~~<br>|2<br>~~ee~~<br>~~fe~~<br>|~~ee~~<br>~~fe~~<br>|2<br>~~ee~~<br>~~fe~~<br>|2<br>~~ee~~<br>~~fe~~<br>|2<br>~~ee~~<br>~~fe~~<br>|~~ee~~<br>~~fe~~<br>|2<br>~~ee~~<br>~~fe~~<br>~~**e**G~~<br>|2<br>~~ee~~<br>~~fe~~<br>~~G~~|2<br>~~ee~~<br>~~fe~~|3<br>~~ee~~<br>~~fe~~|2<br>~~ee~~<br>~~fe~~|2<br>~~ee~~<br>~~fe~~|3<br>~~ee~~<br>~~fe~~|4<br>~~ee~~<br>~~fe~~|
||Bank 7<br>~~a~~|~~a~~|2<br>~~a~~|1<br>~~O~~|2<br>~~O~~|~~O~~|2<br>~~O~~|1<br>~~O~~|2<br>~~O~~|~~O~~|2<br>~~**e**G~~<br>~~O~~|1<br>~~G~~|2|2|1|2|2|3|
||Bank 8<br>~~Be~~|~~Be~~|0<br>~~Be~~|0<br>~~Be~~|0<br>~~Be~~|~~Be~~|0<br>~~Be~~|0<br>~~Be~~|0<br>~~Be~~|~~Be~~|0<br>~~Be~~|0<br>~~Be~~|0<br>~~Be~~|0<br>~~Be~~|0<br>~~Be~~|0<br>~~Be~~|0<br>~~Be~~|0<br>~~Be~~|



© 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02012-2.2 

97 

**ECP5 and ECP5-5G Family Data Sheet** 

|**Pin Information**<br>**Summary**|**LFE5U-12**|**LFE5U-12**|**LFE5U-12**|**LFE5U-12**|**LFE5U-25**|**LFE5U-25**|**LFE5U-25**|**LFE5U-25**|**LFE5U-45**|**LFE5U-45**|**LFE5U-45**|**LFE5U-45**|**LFE5U-45**|**LFE5U-85**|**LFE5U-85**|**LFE5U-85**|**LFE5U-85**|
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|Total DQS Groups||8|6|8||8|6|8||8|6|8|10|6|8|10|14|



© 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

98 

FPGA-DS-02012-2.2 

**ECP5 and ECP5-5G Family Data Sheet** 

## **5. Ordering Information** 

## **5.1. ECP5/ECP5-5G Part Number Description** 

LFE5U - XX - X XXXXX X 

Device Family LFE5U (ECP5 FPGA) Logic Capacity 12F = 12K LUTs 25F = 25K LUTs 45F = 45K LUTs 85F = 85K LUTs ~~=~~ Speed 6 = Slowest 7 

Grade 

C = Commercial I = Industrial 

## Package 

TN144 = 144-pin TQFP BG256 = 256-ball caBGA MG285 = 285-ball csfBGA BG381 = 381-ball caBGA BG554 = 554-ball caBGA BG756 = 756-ball caBGA 

8 = Fastest 

LFE5UM - XX - X XXXXX X Device Family LFE5UM (ECP5 FPGA with SERDES) Logic Capacity 25F = 25K LUTs 45F = 45K LUTs 85F = 85K LUTs ~~=~~ Speed 6 = Slowest 

Grade C = Commercial I = Industrial Package MG285 = 285-ball csfBGA BG381 = 381-ball caBGA BG554 = 554-ball caBGA BG756 = 756-ball caBGA 

7 

8 = Fastest 

© 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02012-2.2 

99 

**ECP5 and ECP5-5G Family Data Sheet** 

## LFE5UM5G - XX - X XXXXX X 

Device Family LFE5UM5G (ECP5-5G FPGA with SERDES) 

Logic Capacity 25F = 25K LUTs 45F = 45K LUTs 85F = 85K LUTs 

Speed 8 = Fastest 

Grade 

C = Commercial I = Industrial 

Package 

MG285 = 285-ball csfBGA BG381 = 381-ball caBGA BG554 = 554-ball caBGA BG756 = 756-ball caBGA 

## **5.2. Ordering Part Numbers** 

## **5.2.1. Commercial** 

|**Part number**<br>~~pO~~<br>~~po~~|**Grade**|**Package**|**Pins**|**Temp.**|**LUTs (K)**|**SERDES**|
|---|---|---|---|---|---|---|
|LFE5U-12F-6TN144C<br>~~pO~~<br>~~po~~<br>~~po~~|–6|Lead free TQFP|144|Commercial|12|No|
|LFE5U-12F-7TN144C<br>~~po~~<br>~~po~~<br>~~po~~|–7|Lead free TQFP|144|Commercial|12|No|
|LFE5U-12F-8TN144C<br>~~po~~<br>~~po~~<br>~~po~~|–8|Lead free TQFP|144|Commercial|12|No|
|LFE5U-12F-6BG256C<br>~~po~~<br>~~po~~<br>~~po~~|–6|Lead free caBGA|256|Commercial|12|No|
|LFE5U-12F-7BG256C<br>~~po~~<br>~~po~~|–7|Lead free caBGA|256|Commercial|12|No|
|LFE5U-12F-8BG256C<br>~~po~~<br>~~a~~<br>~~pO~~|–8<br>~~GG~~|Lead free caBGA<br>~~GG~~|256<br>~~GG~~|Commercial<br>~~GG~~|12<br>~~GG~~|No<br>~~GG~~|
|LFE5U-12F-6MG285C<br>~~a ~~<br>~~pO~~|–6<br> ~~GG~~|Lead free csfBGA<br>~~GG~~|285<br>~~GG~~|Commercial<br>~~GG~~|12<br>~~GG~~|No<br>~~GG~~|
|LFE5U-12F-7MG285C<br>~~pO~~<br>~~po~~<br>~~pO~~|–7<br>~~po~~|Lead free csfBGA<br>~~po~~|285<br>~~po~~|Commercial<br>~~po~~|12<br>~~po~~|No<br>~~po~~|
|LFE5U-12F-8MG285C<br>~~po~~<br>~~pO~~|–8<br>~~po~~|Lead free csfBGA<br>~~po~~|285<br>~~po~~|Commercial<br>~~po~~|12<br>~~po~~|No<br>~~po~~|
|LFE5U-12F-6BG381C<br>~~pO~~<br>~~po~~|–6<br>~~po~~|Lead free caBGA<br>~~po~~|381<br>~~po~~|Commercial<br>~~po~~|12<br>~~po~~|No<br>~~po~~|
|LFE5U-12F-7BG381C<br>~~po~~<br>~~a~~<br>~~po~~|–7<br>~~po~~<br>~~GG~~|Lead free caBGA<br>~~po~~<br>~~GG~~|381<br>~~po~~<br>~~GG~~|Commercial<br>~~po~~<br>~~GG~~|12<br>~~po~~<br>~~GG~~|No<br>~~po~~<br>~~GG~~|
|LFE5U-12F-8BG381C<br>~~a ~~<br>~~po~~|–8<br> ~~GG~~|Lead free caBGA<br>~~GG~~|381<br>~~GG~~|Commercial<br>~~GG~~|12<br>~~GG~~|No<br>~~GG~~|
|LFE5U-25F-6TN144C<br>~~po~~<br>~~pf~~<br>~~po~~|–6<br>~~pf~~|Lead free TQFP<br>~~pf~~|144<br>~~pf~~|Commercial<br>~~pf~~|24<br>~~pf~~|No<br>~~pf~~|
|LFE5U-25F-7TN144C<br>~~pf~~<br>~~po~~|–7<br>~~pf~~|Lead free TQFP<br>~~pf~~|144<br>~~pf~~|Commercial<br>~~pf~~|24<br>~~pf~~|No<br>~~pf~~|
|LFE5U-25F-8TN144C<br>~~po~~<br>~~pf~~<br>~~po~~|–8<br>~~pf~~|Lead free TQFP<br>~~pf~~|144<br>~~pf~~|Commercial<br>~~pf~~|24<br>~~pf~~|No<br>~~pf~~|
|LFE5U-25F-6BG256C<br>~~pf~~<br>~~po~~|–6<br>~~pf~~|Lead free caBGA<br>~~pf~~|256<br>~~pf~~|Commercial<br>~~pf~~|24<br>~~pf~~|No<br>~~pf~~|
|LFE5U-25F-7BG256C<br>~~po~~<br>~~po~~<br>~~pO~~|–7<br>~~po~~|Lead free caBGA<br>~~po~~|256<br>~~po~~|Commercial<br>~~po~~|24<br>~~po~~|No<br>~~po~~|
|LFE5U-25F-8BG256C<br>~~po~~<br>~~pO~~|–8<br>~~po~~|Lead free caBGA<br>~~po~~|256<br>~~po~~|Commercial<br>~~po~~|24<br>~~po~~|No<br>~~po~~|
|LFE5U-25F-6MG285C<br>~~pO~~<br>~~po~~<br>~~po~~|–6<br>~~po~~|Lead free csfBGA<br>~~po~~|285<br>~~po~~|Commercial<br>~~po~~|24<br>~~po~~|No<br>~~po~~|
|LFE5U-25F-7MG285C<br>~~po~~<br>~~po~~|–7<br>~~po~~|Lead free csfBGA<br>~~po~~|285<br>~~po~~|Commercial<br>~~po~~|24<br>~~po~~|No<br>~~po~~|
|LFE5U-25F-8MG285C<br>~~po~~<br>~~pf~~<br>~~po~~|–8<br>~~pf~~|Lead free csfBGA<br>~~pf~~|285<br>~~pf~~|Commercial<br>~~pf~~|24<br>~~pf~~|No<br>~~pf~~|
|LFE5U-25F-6BG381C<br>~~pf~~<br>~~po~~<br>~~pO~~|–6<br>~~pf~~|Lead free caBGA<br>~~pf~~|381<br>~~pf~~|Commercial<br>~~pf~~|24<br>~~pf~~|No<br>~~pf~~|
|LFE5U-25F-7BG381C<br>~~po~~<br>~~pO~~|–7|Lead free caBGA|381|Commercial|24|No|
|LFE5U-25F-8BG381C<br>~~pO~~<br>~~po~~<br>~~pO~~|–8<br>~~po~~|Lead free caBGA<br>~~po~~|381<br>~~po~~|Commercial<br>~~po~~|24<br>~~po~~|No<br>~~po~~|
|LFE5U-45F-6TN144C<br>~~po~~<br>~~pO~~|–6<br>~~po~~|Lead free TQFP<br>~~po~~|144<br>~~po~~|Commercial<br>~~po~~|44<br>~~po~~|No<br>~~po~~|
|LFE5U-45F-7TN144C<br>~~pO~~<br>~~po~~|–7<br>~~po~~|Lead free TQFP<br>~~po~~|144<br>~~po~~|Commercial<br>~~po~~|44<br>~~po~~|No<br>~~po~~|
|LFE5U-45F-8TN144C<br>~~a~~<br>~~pO~~|–8<br>~~GG~~|Lead free TQFP<br>~~GG~~|144<br>~~GG~~|Commercial<br>~~GG~~|44<br>~~GG~~|No<br>~~GG~~|
|LFE5U-45F-6BG256C<br>~~a ~~<br>~~pO~~|–6<br> ~~GG~~|Lead free caBGA<br>~~GG~~|256<br>~~GG~~|Commercial<br>~~GG~~<br>~~FO~~|44<br>~~GG~~|No<br>~~GG~~|
|LFE5U-45F-7BG256C<br>~~pO~~<br>~~GG~~|–7<br>~~GG~~|Lead free caBGA<br>~~GG~~|256<br>~~GG~~|Commercial<br>~~GG~~<br>~~FO~~|44<br>~~GG~~|No<br>~~GG~~|



© 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

100 

FPGA-DS-02012-2.2 

**ECP5 and ECP5-5G Family Data Sheet** 

|**Part number**<br>~~pO~~|**Grade**|**Package**|**Pins**|**Temp.**|**LUTs (K)**|**SERDES**|
|---|---|---|---|---|---|---|
|LFE5U-45F-8BG256C<br>~~pO~~<br>~~pf~~<br>~~po~~|–8<br>~~pf~~|Lead free caBGA<br>~~pf~~|256<br>~~pf~~|Commercial<br>~~pf~~|44<br>~~pf~~|No<br>~~pf~~|
|LFE5U-45F-6MG285C<br>~~po~~<br>~~pO~~|–6|Lead free csfBGA|285|Commercial|44|No|
|LFE5U-45F-7MG285C<br>~~po~~<br>~~pO~~<br>~~po~~|–7|Lead free csfBGA|285|Commercial|44|No|
|LFE5U-45F-8MG285C<br>~~pO~~<br>~~po~~<br>~~pO~~|–8|Lead free csfBGA|285|Commercial|44|No|
|LFE5U-45F-6BG381C<br>~~po~~<br>~~pO~~<br>~~pO~~|–6|Lead free caBGA|381|Commercial|44|No|
|LFE5U-45F-7BG381C<br>~~pO~~<br>~~pO~~<br>~~po~~|–7|Lead free caBGA|381|Commercial|44|No|
|LFE5U-45F-8BG381C<br>~~pO~~<br>~~po~~|–8|Lead free caBGA|381|Commercial|44|No|
|LFE5U-45F-6BG554C<br>~~po~~<br>~~GG~~<br>~~po~~|–6<br>~~GG~~|Lead free caBGA<br>~~GG~~|554<br>~~GG~~|Commercial<br>~~GG~~|44<br>~~GG~~|No<br>~~GG~~|
|LFE5U-45F-7BG554C<br>~~GG~~<br>~~po~~<br>~~pO~~|–7<br>~~GG~~|Lead free caBGA<br>~~GG~~|554<br>~~GG~~|Commercial<br>~~GG~~|44<br>~~GG~~|No<br>~~GG~~|
|LFE5U-45F-8BG554C<br>~~po~~<br>~~pO~~<br>~~pO~~|–8|Lead free caBGA|554|Commercial|44|No|
|LFE5U-85F-6MG285C<br>~~pO~~<br>~~pO~~<br>~~po~~|–6|Lead free csfBGA|285|Commercial|84|No|
|LFE5U-85F-7MG285C<br>~~pO~~<br>~~po~~|–7|Lead free csfBGA|285|Commercial|84|No|
|LFE5U-85F-8MG285C<br>~~po~~<br>~~GG~~<br>~~po~~|–8<br>~~GG~~|Lead free csfBGA<br>~~GG~~|285<br>~~GG~~|Commercial<br>~~GG~~|84<br>~~GG~~|No<br>~~GG~~|
|LFE5U-85F-6BG381C<br>~~GG~~<br>~~po~~<br>~~pO~~|–6<br>~~GG~~|Lead free caBGA<br>~~GG~~|381<br>~~GG~~|Commercial<br>~~GG~~|84<br>~~GG~~|No<br>~~GG~~|
|LFE5U-85F-7BG381C<br>~~po~~<br>~~pO~~<br>~~pO~~|–7|Lead free caBGA|381|Commercial|84|No|
|LFE5U-85F-8BG381C<br>~~pO~~<br>~~pO~~<br>~~pO~~|–8|Lead free caBGA|381|Commercial|84|No|
|LFE5U-85F-6BG554C<br>~~pO~~<br>~~pO~~<br>~~po~~|–6|Lead free caBGA|554|Commercial|84|No|
|LFE5U-85F-7BG554C<br>~~pO~~<br>~~po~~<br>~~po~~|–7|Lead free caBGA|554|Commercial|84|No|
|LFE5U-85F-8BG554C<br>~~po~~<br>~~po~~<br>~~po~~|–8|Lead free caBGA|554|Commercial|84|No|
|LFE5U-85F-6BG756C<br>~~po~~<br>~~po~~<br>~~pO~~|–6|Lead free caBGA|756|Commercial|84|No|
|LFE5U-85F-7BG756C<br>~~po~~<br>~~pO~~<br>~~po~~|–7|Lead free caBGA|756|Commercial|84|No|
|LFE5U-85F-8BG756C<br>~~pO~~<br>~~po~~|–8|Lead free caBGA|756|Commercial|84|No|
|LFE5UM-25F-6MG285C<br>~~po~~<br>~~GG~~<br>~~po~~|–6<br>~~GG~~|Lead free csfBGA<br>~~GG~~|285<br>~~GG~~|Commercial<br>~~GG~~|24<br>~~GG~~|Yes<br>~~GG~~|
|LFE5UM-25F-7MG285C<br>~~GG~~<br>~~po~~|–7<br>~~GG~~|Lead free csfBGA<br>~~GG~~|285<br>~~GG~~|Commercial<br>~~GG~~|24<br>~~GG~~|Yes<br>~~GG~~|
|LFE5UM-25F-8MG285C<br>~~po~~<br>~~a~~<br>~~pO~~|–8<br>~~GG~~|Lead free csfBGA<br>~~GG~~|285<br>~~GG~~|Commercial<br>~~GG~~|24<br>~~GG~~|Yes<br>~~GG~~|
|LFE5UM-25F-6BG381C<br>~~a ~~<br>~~pO~~<br>~~pO~~|–6<br> ~~GG~~|Lead free caBGA<br>~~GG~~|381<br>~~GG~~|Commercial<br>~~GG~~|24<br>~~GG~~|Yes<br>~~GG~~|
|LFE5UM-25F-7BG381C<br>~~pO~~<br>~~pO~~|–7|Lead free caBGA|381|Commercial|24|Yes|
|LFE5UM-25F-8BG381C<br>~~pO~~<br>~~GG~~<br>~~po~~|–8<br>~~GG~~|Lead free caBGA<br>~~GG~~|381<br>~~GG~~|Commercial<br>~~GG~~|24<br>~~GG~~|Yes<br>~~GG~~|
|LFE5UM-45F-6MG285C<br>~~GG~~<br>~~po~~|–6<br>~~GG~~|Lead free csfBGA<br>~~GG~~|285<br>~~GG~~|Commercial<br>~~GG~~|44<br>~~GG~~|Yes<br>~~GG~~|
|LFE5UM-45F-7MG285C<br>~~po~~<br>~~a~~<br>~~pO~~|–7<br>~~GG~~|Lead free csfBGA<br>~~GG~~|285<br>~~GG~~|Commercial<br>~~GG~~|44<br>~~GG~~|Yes<br>~~GG~~|
|LFE5UM-45F-8MG285C<br>~~a ~~<br>~~pO~~<br>~~pO~~|–8<br> ~~GG~~|Lead free csfBGA<br>~~GG~~|285<br>~~GG~~|Commercial<br>~~GG~~|44<br>~~GG~~|Yes<br>~~GG~~|
|LFE5UM-45F-6BG381C<br>~~pO~~<br>~~pO~~|–6|Lead free caBGA|381|Commercial|44|Yes|
|LFE5UM-45F-7BG381C<br>~~pO~~<br>~~GG~~<br>~~po~~|–7<br>~~GG~~|Lead free caBGA<br>~~GG~~|381<br>~~GG~~|Commercial<br>~~GG~~|44<br>~~GG~~|Yes<br>~~GG~~|
|LFE5UM-45F-8BG381C<br>~~GG~~<br>~~po~~|–8<br>~~GG~~|Lead free caBGA<br>~~GG~~|381<br>~~GG~~|Commercial<br>~~GG~~|44<br>~~GG~~|Yes<br>~~GG~~|
|LFE5UM-45F-6BG554C<br>~~po~~<br>~~pf~~<br>~~pO~~|–6<br>~~pf~~|Lead free caBGA<br>~~pf~~|554<br>~~pf~~|Commercial<br>~~pf~~|44<br>~~pf~~|Yes<br>~~pf~~|
|LFE5UM-45F-7BG554C<br>~~pf~~<br>~~pO~~|–7<br>~~pf~~|Lead free caBGA<br>~~pf~~|554<br>~~pf~~|Commercial<br>~~pf~~|44<br>~~pf~~|Yes<br>~~pf~~|
|LFE5UM-45F-8BG554C<br>~~pO~~<br>~~a~~<br>~~po~~|–8<br>~~GG~~|Lead free caBGA<br>~~GG~~|554<br>~~GG~~|Commercial<br>~~GG~~|44<br>~~GG~~|Yes<br>~~GG~~|
|LFE5UM-85F-6MG285C<br>~~a ~~<br>~~po~~<br>~~po~~|–6<br> ~~GG~~|Lead free csfBGA<br>~~GG~~|285<br>~~GG~~|Commercial<br>~~GG~~|84<br>~~GG~~|Yes<br>~~GG~~|
|LFE5UM-85F-7MG285C<br>~~po~~<br>~~po~~|–7|Lead free csfBGA|285|Commercial|84|Yes|
|LFE5UM-85F-8MG285C<br>~~po~~<br>~~pf~~<br>~~pO~~|–8<br>~~pf~~|Lead free csfBGA<br>~~pf~~|285<br>~~pf~~|Commercial<br>~~pf~~|84<br>~~pf~~|Yes<br>~~pf~~|
|LFE5UM-85F-6BG381C<br>~~pf~~<br>~~pO~~|–6<br>~~pf~~|Lead free caBGA<br>~~pf~~|381<br>~~pf~~|Commercial<br>~~pf~~|84<br>~~pf~~|Yes<br>~~pf~~|
|LFE5UM-85F-7BG381C<br>~~pO~~<br>~~pf~~<br>~~pO~~|–7<br>~~pf~~|Lead free caBGA<br>~~pf~~|381<br>~~pf~~|Commercial<br>~~pf~~|84<br>~~pf~~|Yes<br>~~pf~~|
|LFE5UM-85F-8BG381C<br>~~pf~~<br>~~pO~~<br>~~pO~~|–8<br>~~pf~~|Lead free caBGA<br>~~pf~~|381<br>~~pf~~|Commercial<br>~~pf~~|84<br>~~pf~~|Yes<br>~~pf~~|
|LFE5UM-85F-6BG554C<br>~~pO~~<br>~~pO~~<br>~~po~~|–6|Lead free caBGA|554|Commercial|84|Yes|
|LFE5UM-85F-7BG554C<br>~~pO~~<br>~~po~~|–7|Lead free caBGA|554|Commercial|84|Yes|
|LFE5UM-85F-8BG554C<br>~~po~~<br>~~po~~|–8<br>~~po~~|Lead free caBGA<br>~~po~~|554<br>~~po~~|Commercial<br>~~po~~|84<br>~~po~~|Yes<br>~~po~~|



© 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02012-2.2 

101 

**ECP5 and ECP5-5G Family Data Sheet** 

|**Part number**<br>~~pO~~|**Grade**|**Package**|**Pins**|**Temp.**|**LUTs (K)**|**SERDES**|
|---|---|---|---|---|---|---|
|LFE5UM-85F-6BG756C<br>~~pO~~<br>~~po~~<br>~~po~~|–6<br>~~po~~|Lead free caBGA<br>~~po~~|756<br>~~po~~|Commercial<br>~~po~~|84<br>~~po~~|Yes<br>~~po~~|
|LFE5UM-85F-7BG756C<br>~~po~~<br>~~pO~~|–7|Lead free caBGA|756|Commercial|84|Yes|
|LFE5UM-85F-8BG756C<br>~~po~~<br>~~pO~~<br>~~po~~|–8|Lead free caBGA|756|Commercial|84|Yes|
|LFE5UM5G-25F-8MG285C<br>~~pO~~<br>~~po~~<br>~~po~~|–8|Lead free csfBGA|285|Commercial|24|Yes|
|LFE5UM5G-25F-8BG381C<br>~~po~~<br>~~po~~<br>~~po~~|–8|Lead free caBGA|381|Commercial|24|Yes|
|LFE5UM5G-45F-8MG285C<br>~~po~~<br>~~po~~<br>~~pO~~|–8|Lead free csfBGA|285|Commercial|44|Yes|
|LFE5UM5G-45F-8BG381C<br>~~po~~<br>~~pO~~|–8|Lead free caBGA|381|Commercial|44|Yes|
|LFE5UM5G-45F-8BG554C<br>~~pO~~<br>~~GG~~<br>~~po~~|–8<br>~~GG~~|Lead free caBGA<br>~~GG~~|554<br>~~GG~~|Commercial<br>~~GG~~|44<br>~~GG~~|Yes<br>~~GG~~|
|LFE5UM5G-85F-8MG285C<br>~~GG~~<br>~~po~~<br>~~po~~|–8<br>~~GG~~|Lead free csfBGA<br>~~GG~~|285<br>~~GG~~|Commercial<br>~~GG~~|84<br>~~GG~~|Yes<br>~~GG~~|
|LFE5UM5G-85F-8BG381C<br>~~po~~<br>~~po~~<br>~~po~~|–8|Lead free caBGA|381|Commercial|84|Yes|
|LFE5UM5G-85F-8BG554C<br>~~po~~<br>~~po~~<br>~~pO~~|–8|Lead free caBGA|554|Commercial|84|Yes|
|LFE5UM5G-85F-8BG756C<br>~~po~~<br>~~pO~~|–8|Lead free caBGA|756|Commercial|84|Yes|



|**Part number**<br>~~PO~~<br>~~po~~|**Grade**|**Package**|**Pins**|**Temp.**|**LUTs (K)**|**SERDES**|
|---|---|---|---|---|---|---|
|LFE5U-12F-6TN144I<br>~~PO~~<br>~~po~~<br>~~po~~|–6|Lead free TQFP|144|Industrial|12|No|
|LFE5U-12F-7TN144I<br>~~po~~<br>~~po~~|–7|Lead free TQFP|144|Industrial|12|No|
|LFE5U-12F-8TN144I<br>~~po~~<br>~~Ce~~<br>~~po~~|–8<br>~~Ce ~~|Lead free TQFP<br> ~~GG~~|144<br>~~GG~~|Industrial<br>~~GG~~|12|No|
|LFE5U-12F-6BG256I<br>~~po~~<br>~~po~~|–6|Lead free caBGA|256|Industrial|12|No|
|LFE5U-12F-7BG256I<br>~~po~~<br>~~po~~|–7|Lead free caBGA|256|Industrial|12|No|
|LFE5U-12F-8BG256I<br>~~po~~<br>~~Ce~~<br>~~po~~|–8<br>~~Ce ~~|Lead free caBGA<br> ~~GG~~|256<br>~~GG~~|Industrial<br>~~GG~~|12|No|
|LFE5U-12F-6MG285I<br>~~po~~<br>~~pO~~|–6|Lead free csfBGA|285|Industrial|12|No|
|LFE5U-12F-7MG285I<br>~~po~~<br>~~pO~~|–7|Lead free csfBGA|285|Industrial|12|No|
|LFE5U-12F-8MG285I<br>~~pO~~<br>~~ee~~<br>~~pO~~|–8<br>~~ee~~|Lead free csfBGA<br>~~GG~~|285<br>~~GG~~|Industrial<br>~~GG~~|12|No|
|LFE5U-12F-6BG381I<br>~~ee~~<br>~~pO~~<br>~~pO~~|–6<br>~~ee~~|Lead free caBGA<br>~~GG~~|381<br>~~GG~~|Industrial<br>~~GG~~|12|No|
|LFE5U-12F-7BG381I<br>~~pO~~<br>~~pO~~|–7|Lead free caBGA|381|Industrial|12|No|
|LFE5U-12F-8BG381I<br>~~pO~~<br>~~ee~~<br>~~pO~~|–8<br>~~ee~~|Lead free caBGA<br>~~GG~~|381<br>~~GG~~|Industrial<br>~~GG~~|12|No|
|LFE5U-25F-6TN144I<br>~~ee~~<br>~~pO~~<br>~~pO~~|–6<br>~~ee~~|Lead free TQFP<br>~~GG~~|144<br>~~GG~~|Industrial<br>~~GG~~|24|No|
|LFE5U-25F-7TN144I<br>~~pO~~<br>~~pO~~|–7|Lead free TQFP|144|Industrial|24|No|
|LFE5U-25F-8TN144I<br>~~pO~~<br>~~ee~~<br>~~pO~~|–8<br>~~ee~~|Lead free TQFP<br>~~GG~~|144<br>~~GG~~|Industrial<br>~~GG~~|24|No|
|LFE5U-25F-6BG256I<br>~~ee~~<br>~~pO~~<br>~~pO~~|–6<br>~~ee~~|Lead free caBGA<br>~~GG~~|256<br>~~GG~~|Industrial<br>~~GG~~|24|No|
|LFE5U-25F-7BG256I<br>~~pO~~<br>~~pO~~|–7|Lead free caBGA|256|Industrial|24|No|
|LFE5U-25F-8BG256I<br>~~pO~~<br>~~ee~~<br>~~pO~~|–8<br>~~ee~~|Lead free caBGA<br>~~GG~~|256<br>~~GG~~|Industrial<br>~~GG~~|24|No|
|LFE5U-25F-6MG285I<br>~~ee~~<br>~~pO~~|–6<br>~~ee~~|Lead free csfBGA<br>~~GG~~|285<br>~~GG~~|Industrial<br>~~GG~~|24|No|
|LFE5U-25F-7MG285I<br>~~pO~~<br>~~pf~~<br>~~pO~~|–7<br>~~pf~~|Lead free csfBGA<br>~~pf~~<br>~~Ge~~|285<br>~~pf~~|Industrial<br>~~pf~~|24<br>~~pf~~|No<br>~~pf~~|
|LFE5U-25F-8MG285I<br>~~pf~~<br>~~Ce~~<br>~~pO~~|–8<br>~~pf~~<br>~~Ce~~|Lead free csfBGA<br>~~pf~~<br>~~Ce~~<br>~~Ge~~|285<br>~~pf~~<br>~~Ce~~|Industrial<br>~~pf~~<br>~~Ce~~|24<br>~~pf~~<br>~~Ce~~|No<br>~~pf~~<br>~~Ce~~|
|LFE5U-25F-6BG381I<br>~~Ce~~<br>~~pO~~|–6<br>~~Ce~~|Lead free caBGA<br>~~Ce~~<br>~~Ge~~|381<br>~~Ce~~|Industrial<br>~~Ce~~|24<br>~~Ce~~|No<br>~~Ce~~|
|LFE5U-25F-7BG381I<br>~~pO~~<br>~~pf~~<br>~~po~~|–7<br>~~pf~~|Lead free caBGA<br>~~Ge~~<br>~~pf~~|381<br>~~pf~~|Industrial<br>~~pf~~|24<br>~~pf~~|No<br>~~pf~~|
|LFE5U-25F-8BG381I<br>~~pf~~<br>~~po~~<br>~~pO~~|–8<br>~~pf~~|Lead free caBGA<br>~~pf~~|381<br>~~pf~~|Industrial<br>~~pf~~|24<br>~~pf~~|No<br>~~pf~~|
|LFE5U-45F-6TN144I<br>~~po~~<br>~~pO~~|–6|Lead free TQFP|144|Industrial|44|No|
|LFE5U-45F-7TN144I<br>~~pO~~<br>~~pf~~<br>~~po~~|–7<br>~~pf~~|Lead free TQFP<br>~~pf~~|144<br>~~pf~~|Industrial<br>~~pf~~|44<br>~~pf~~|No<br>~~pf~~|
|LFE5U-45F-8TN144I<br>~~pf~~<br>~~po~~|–8<br>~~pf~~|Lead free TQFP<br>~~pf~~|144<br>~~pf~~|Industrial<br>~~pf~~|44<br>~~pf~~|No<br>~~pf~~|
|LFE5U-45F-6BG256I<br>~~po~~<br>~~Ce~~<br>~~po~~|–6<br>~~Ce ~~|Lead free caBGA<br> ~~GO~~|256<br>~~GO~~|Industrial<br>~~GO~~|44|No|
|LFE5U-45F-7BG256I<br>~~po~~<br>~~pO~~|–7|Lead free caBGA|256|Industrial|44|No|
|LFE5U-45F-8BG256I<br>~~po~~<br>~~pO~~|–8|Lead free caBGA|256|Industrial|44|No|



© 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

102 

FPGA-DS-02012-2.2 

**ECP5 and ECP5-5G Family Data Sheet** 

|**Part number**<br>~~pO~~|**Grade**|**Package**|**Pins**|**Temp.**|**LUTs (K)**|**SERDES**|
|---|---|---|---|---|---|---|
|LFE5U-45F-6MG285I<br>~~pO~~<br>~~pf~~<br>~~po~~|–6<br>~~pf~~|Lead free csfBGA<br>~~pf~~|285<br>~~pf~~|Industrial<br>~~pf~~|44<br>~~pf~~|No<br>~~pf~~|
|LFE5U-45F-7MG285I<br>~~po~~<br>~~pO~~|–7|Lead free csfBGA|285|Industrial|44|No|
|LFE5U-45F-8MG285I<br>~~po~~<br>~~pO~~<br>~~po~~|–8|Lead free csfBGA|285|Industrial|44|No|
|LFE5U-45F-6BG381I<br>~~pO~~<br>~~po~~|–6|Lead free caBGA<br>~~Ge~~|381<br>~~GO~~|Industrial<br>~~GO~~|44|No|
|LFE5U-45F-7BG381I<br>~~po~~<br>~~Ge~~<br>~~pO~~|–7<br>~~Ge~~|Lead free caBGA<br>~~Ge~~<br>~~Ge~~<br>~~Ge~~|381<br>~~Ge~~<br>~~GO~~<br>~~GC~~|Industrial<br>~~Ge~~<br>~~GO~~<br>~~GC~~|44<br>~~Ge~~|No<br>~~Ge~~|
|LFE5U-45F-8BG381I<br>~~Ge~~<br>~~pO~~|–8<br>~~Ge~~|Lead free caBGA<br>~~Ge~~<br>~~Ge~~<br>~~Ge~~|381<br>~~GO~~<br>~~Ge~~<br>~~GC~~|Industrial<br>~~GO~~<br>~~Ge~~<br>~~GC~~|44<br>~~Ge~~|No<br>~~Ge~~|
|LFE5U-45F-6BG554I<br>~~Ge~~<br>~~pO~~|–6<br>~~Ge~~|Lead free caBGA<br>~~Ge~~<br>~~Ge~~|554<br>~~Ge~~<br>~~GC~~|Industrial<br>~~Ge~~<br>~~GC~~|44<br>~~Ge~~|No<br>~~Ge~~|
|LFE5U-45F-7BG554I<br>~~pO~~<br>~~OG~~|–7<br>~~OG~~|Lead free caBGA<br>~~Ge~~<br>~~OG~~<br>~~Oe~~|554<br>~~GC~~<br>~~OG~~<br>~~GC~~|Industrial<br>~~GC~~<br>~~OG~~<br>~~GC~~|44<br>~~OG~~|No<br>~~OG~~|
|LFE5U-45F-8BG554I<br>~~OG~~<br>~~Ce~~|–8<br>~~OG~~<br>~~Ce~~|Lead free caBGA<br>~~OG~~<br>~~Ce~~<br>~~Oe~~<br>~~Ge~~|554<br>~~OG~~<br>~~Ce~~<br>~~GC~~<br>~~GO~~|Industrial<br>~~OG~~<br>~~Ce~~<br>~~GC~~<br>~~GO~~|44<br>~~OG~~<br>~~Ce~~|No<br>~~OG~~<br>~~Ce~~|
|LFE5U-85F-6MG285I<br>~~Ge~~<br>~~pO~~|–6<br>~~Ge~~|Lead free csfBGA<br>~~Oe~~<br>~~Ge~~<br>~~Ge~~<br>~~Ge~~|285<br>~~GC~~<br>~~Ge~~<br>~~GO~~<br>~~GC~~|Industrial<br>~~GC~~<br>~~Ge~~<br>~~GO~~<br>~~GC~~|84<br>~~Ge~~|No<br>~~Ge~~|
|LFE5U-85F-7MG285I<br>~~Ge~~<br>~~pO~~|–7<br>~~Ge~~|Lead free csfBGA<br>~~Ge~~<br>~~Ge~~<br>~~Ge~~|285<br>~~GO~~<br>~~Ge~~<br>~~GC~~|Industrial<br>~~GO~~<br>~~Ge~~<br>~~GC~~|84<br>~~Ge~~|No<br>~~Ge~~|
|LFE5U-85F-8MG285I<br>~~Ge~~<br>~~pO~~|–8<br>~~Ge~~|Lead free csfBGA<br>~~Ge~~<br>~~Ge~~|285<br>~~Ge~~<br>~~GC~~|Industrial<br>~~Ge~~<br>~~GC~~|84<br>~~Ge~~|No<br>~~Ge~~|
|LFE5U-85F-6BG381I<br>~~pO~~<br>~~OG~~|–6<br>~~OG~~|Lead free caBGA<br>~~Ge~~<br>~~OG~~<br>~~Oe~~|381<br>~~GC~~<br>~~OG~~<br>~~GC~~|Industrial<br>~~GC~~<br>~~OG~~<br>~~GC~~|84<br>~~OG~~|No<br>~~OG~~|
|LFE5U-85F-7BG381I<br>~~OG~~<br>~~Ce~~<br>~~eG~~|–7<br>~~OG~~<br>~~Ce~~<br>~~eG~~|Lead free caBGA<br>~~OG~~<br>~~Ce~~<br>~~Oe~~<br>~~Ge~~|381<br>~~OG~~<br>~~Ce~~<br>~~GC~~<br>~~GO~~|Industrial<br>~~OG~~<br>~~Ce~~<br>~~GC~~<br>~~GO~~|84<br>~~OG~~<br>~~Ce~~|No<br>~~OG~~<br>~~Ce~~|
|LFE5U-85F-8BG381I<br>~~Ge~~<br>~~eG~~|–8<br>~~Ge~~<br>~~eG~~|Lead free caBGA<br>~~Oe~~<br>~~Ge~~<br>~~Ge~~|381<br>~~GC~~<br>~~Ge~~<br>~~GO~~|Industrial<br>~~GC~~<br>~~Ge~~<br>~~GO~~|84<br>~~Ge~~|No<br>~~Ge~~|
|LFE5U-85F-6BG554I<br>~~eG~~<br>~~pO~~|–6<br>~~eG~~|Lead free caBGA<br>~~Ge~~<br>~~GC~~|554<br>~~GO~~<br>~~GC~~|Industrial<br>~~GO~~<br>~~GC~~|84|No|
|LFE5U-85F-7BG554I<br>~~pO~~<br>~~Ce~~|–7<br>~~Ce~~|Lead free caBGA<br>~~GC~~<br>~~GG~~|554<br>~~GC~~<br>~~GG~~|Industrial<br>~~GC~~<br>~~CO~~|84|No|
|LFE5U-85F-8BG554I<br>~~pO~~<br>~~Ce~~|–8<br>~~Ce~~|Lead free caBGA<br>~~GC~~<br>~~GG~~|554<br>~~GC~~<br>~~GG~~|Industrial<br>~~GC~~<br>~~CO~~|84|No|
|LFE5U-85F-6BG756I<br>~~Ce~~<br>~~fe~~<br>~~Ce~~|–6<br>~~Ce ~~<br>~~fe ~~<br>~~Ce~~|Lead free caBGA<br> ~~GG~~<br> ~~GG~~<br>~~GG~~|756<br>~~GG ~~<br>~~GG~~<br>~~GG~~|Industrial<br> ~~CO~~<br>~~CO~~|84|No|
|LFE5U-85F-7BG756I<br>~~Ce~~<br>~~pO~~|–7<br>~~Ce~~|Lead free caBGA<br>~~GG~~<br>~~Ge~~|756<br>~~GG~~<br>~~GC~~|Industrial<br>~~CO~~<br>~~GC~~|84|No|
|LFE5U-85F-8BG756I<br>~~Ce~~<br>~~Ge~~<br>~~pO~~|–8<br>~~Ce ~~<br>~~Ge~~|Lead free caBGA<br> ~~GG~~<br>~~Ge~~<br>~~Ge~~|756<br>~~GG ~~<br>~~Ge~~<br>~~GC~~|Industrial<br> ~~CO~~<br>~~Ge~~<br>~~GC~~|84<br>~~Ge~~|No<br>~~Ge~~|
|LFE5UM-25F-6MG285I<br>~~Ge~~<br>~~pO~~|–6<br>~~Ge~~|Lead free csfBGA<br>~~Ge~~<br>~~Ge~~|285<br>~~Ge~~<br>~~GC~~|Industrial<br>~~Ge~~<br>~~GC~~|24<br>~~Ge~~|Yes<br>~~Ge~~|
|LFE5UM-25F-7MG285I<br>~~pO~~<br>~~OG~~<br>~~po~~|–7<br>~~OG~~|Lead free csfBGA<br>~~Ge~~<br>~~OG~~|285<br>~~GC~~<br>~~OG~~|Industrial<br>~~GC~~<br>~~OG~~|24<br>~~OG~~|Yes<br>~~OG~~|
|LFE5UM-25F-8MG285I<br>~~OG~~<br>~~po~~|–8<br>~~OG~~|Lead free csfBGA<br>~~OG~~|285<br>~~OG~~|Industrial<br>~~OG~~|24<br>~~OG~~|Yes<br>~~OG~~|
|LFE5UM-25F-6BG381I<br>~~po~~<br>~~GG~~<br>~~po~~|–6<br>~~GG~~|Lead free caBGA<br>~~GG~~|381<br>~~GG~~|Industrial<br>~~GG~~|24<br>~~GG~~|Yes<br>~~GG~~|
|LFE5UM-25F-7BG381I<br>~~GG~~<br>~~po~~<br>~~pO~~|–7<br>~~GG~~|Lead free caBGA<br>~~GG~~|381<br>~~GG~~|Industrial<br>~~GG~~|24<br>~~GG~~|Yes<br>~~GG~~|
|LFE5UM-25F-8BG381I<br>~~po~~<br>~~pO~~<br>~~po~~|–8|Lead free caBGA|381|Industrial|24|Yes|
|LFE5UM-45F-6MG285I<br>~~pO~~<br>~~po~~<br>~~po~~|–6|Lead free csfBGA|285|Industrial|44|Yes|
|LFE5UM-45F-7MG285I<br>~~po~~<br>~~po~~|–7|Lead free csfBGA|285|Industrial|44|Yes|
|LFE5UM-45F-8MG285I<br>~~po~~<br>~~GG~~<br>~~po~~|–8<br>~~GG~~|Lead free csfBGA<br>~~GG~~|285<br>~~GG~~|Industrial<br>~~GG~~|44<br>~~GG~~|Yes<br>~~GG~~|
|LFE5UM-45F-6BG381I<br>~~GG~~<br>~~po~~<br>~~pO~~|–6<br>~~GG~~|Lead free caBGA<br>~~GG~~|381<br>~~GG~~|Industrial<br>~~GG~~|44<br>~~GG~~|Yes<br>~~GG~~|
|LFE5UM-45F-7BG381I<br>~~po~~<br>~~pO~~<br>~~po~~|–7|Lead free caBGA|381|Industrial|44|Yes|
|LFE5UM-45F-8BG381I<br>~~pO~~<br>~~po~~<br>~~pO~~|–8|Lead free caBGA|381|Industrial|44|Yes|
|LFE5UM-45F-6BG554I<br>~~po~~<br>~~pO~~|–6|Lead free caBGA|554|Industrial|44|Yes|
|LFE5UM-45F-7BG554I<br>~~pO~~<br>~~GG~~<br>~~po~~|–7<br>~~GG~~|Lead free caBGA<br>~~GG~~|554<br>~~GG~~|Industrial<br>~~GG~~|44<br>~~GG~~|Yes<br>~~GG~~|
|LFE5UM-45F-8BG554I<br>~~GG~~<br>~~po~~|–8<br>~~GG~~|Lead free caBGA<br>~~GG~~|554<br>~~GG~~|Industrial<br>~~GG~~|44<br>~~GG~~|Yes<br>~~GG~~|
|LFE5UM-85F-6MG285I<br>~~po~~<br>~~GG~~<br>~~po~~|–6<br>~~GG~~|Lead free csfBGA<br>~~GG~~|285<br>~~GG~~|Industrial<br>~~GG~~|84<br>~~GG~~|Yes<br>~~GG~~|
|LFE5UM-85F-7MG285I<br>~~GG~~<br>~~po~~<br>~~po~~|–7<br>~~GG~~|Lead free csfBGA<br>~~GG~~|285<br>~~GG~~|Industrial<br>~~GG~~|84<br>~~GG~~|Yes<br>~~GG~~|
|LFE5UM-85F-8MG285I<br>~~po~~<br>~~po~~|–8|Lead free csfBGA|285|Industrial|84|Yes|
|LFE5UM-85F-6BG381I<br>~~po~~<br>~~GG~~<br>~~po~~|–6<br>~~GG~~|Lead free caBGA<br>~~GG~~|381<br>~~GG~~|Industrial<br>~~GG~~|84<br>~~GG~~|Yes<br>~~GG~~|
|LFE5UM-85F-7BG381I<br>~~GG~~<br>~~po~~|–7<br>~~GG~~|Lead free caBGA<br>~~GG~~|381<br>~~GG~~|Industrial<br>~~GG~~|84<br>~~GG~~|Yes<br>~~GG~~|
|LFE5UM-85F-8BG381I<br>~~po~~<br>~~GG~~|–8<br>~~GG~~|Lead free caBGA<br>~~GG~~|381<br>~~GG~~|Industrial<br>~~GG~~|84<br>~~GG~~|Yes<br>~~GG~~|
|LFE5UM-85F-6BG554I<br>~~GG~~<br>~~Ge~~<br>~~po~~|–6<br>~~GG~~<br>~~Ge~~|Lead free caBGA<br>~~GG~~<br>~~GC~~|554<br>~~GG~~<br>~~GC~~|Industrial<br>~~GG~~<br>~~GC~~|84<br>~~GG~~|Yes<br>~~GG~~|
|LFE5UM-85F-7BG554I<br>~~po~~<br>~~po~~|–7|Lead free caBGA|554|Industrial|84|Yes|
|LFE5UM-85F-8BG554I<br>~~po~~<br>~~po~~<br>~~po~~|–8|Lead free caBGA|554|Industrial|84|Yes|
|LFE5UM-85F-6BG756I<br>~~po~~<br>~~po~~|–6|Lead free caBGA|756|Industrial|84|Yes|



© 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02012-2.2 

103 

**ECP5 and ECP5-5G Family Data Sheet** 

|**Part number**<br>~~pO~~|**Grade**|**Package**|**Pins**|**Temp.**|**LUTs (K)**|**SERDES**|
|---|---|---|---|---|---|---|
|LFE5UM-85F-7BG756I<br>~~pO~~<br>~~GG~~<br>~~pO~~|–7<br>~~GG~~|Lead free caBGA<br>~~GG~~|756<br>~~GG~~|Industrial<br>~~GG~~|84<br>~~GG~~|Yes<br>~~GG~~|
|LFE5UM-85F-8BG756I<br>~~GG~~<br>~~pO~~|–8<br>~~GG~~|Lead free caBGA<br>~~GG~~|756<br>~~GG~~|Industrial<br>~~GG~~|84<br>~~GG~~|Yes<br>~~GG~~|
|LFE5UM5G-25F-8MG285I<br>~~pO~~<br>~~pf~~<br>~~po~~|–8<br>~~pf~~|Lead free csfBGA<br>~~pf~~|285<br>~~pf~~|Industrial<br>~~pf~~|24<br>~~pf~~|Yes<br>~~pf~~|
|LFE5UM5G-25F-8BG381I<br>~~pf~~<br>~~po~~|–8<br>~~pf~~|Lead free caBGA<br>~~pf~~|381<br>~~pf~~|Industrial<br>~~pf~~|24<br>~~pf~~|Yes<br>~~pf~~|
|LFE5UM5G-45F-8MG285I<br>~~po~~<br>~~pO~~<br>~~po~~|–8<br>~~pO~~|Lead free csfBGA<br>~~pO~~|285<br>~~pO~~|Industrial<br>~~pO~~|44<br>~~pO~~|Yes<br>~~pO~~|
|LFE5UM5G-45F-8BG381I<br>~~pO~~<br>~~po~~<br>~~po~~|–8<br>~~pO~~|Lead free caBGA<br>~~pO~~|381<br>~~pO~~|Industrial<br>~~pO~~|44<br>~~pO~~|Yes<br>~~pO~~|
|LFE5UM5G-45F-8BG554I<br>~~po~~<br>~~po~~<br>~~pO~~|–8|Lead free caBGA|554|Industrial|44|Yes|
|LFE5UM5G-85F-8MG285I<br>~~po~~<br>~~pO~~<br>~~po~~|–8|Lead free csfBGA|285|Industrial|84|Yes|
|LFE5UM5G-85F-8BG381I<br>~~pO~~<br>~~po~~<br>~~pO~~|–8|Lead free caBGA|381|Industrial|84|Yes|
|LFE5UM5G-85F-8BG554I<br>~~po~~<br>~~pO~~<br>~~po~~|–8|Lead free caBGA|554|Industrial|84|Yes|
|LFE5UM5G-85F-8BG756I<br>~~pO~~<br>~~po~~|–8|Lead free caBGA|756|Industrial|84|Yes|



© 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

104 

FPGA-DS-02012-2.2 

**ECP5 and ECP5-5G Family Data Sheet** 

## **Supplemental Information** 

## **For Further Information** 

A variety of technical notes for the ECP5/ECP5-5G family are available. 

- High-Speed PCB Design Considerations (FPGA-TN-02178) 

- Transmission of High-Speed Serial Signals Over Common Cable Media (FPGA-TN-02196) 

- PCB Layout Recommendations for BGA Packages (FPGA-TN-02024) 

- Minimizing System Interruption During Configuration Using TransFR Technology (FPGA-TN-02198) 

- Electrical Recommendations for Lattice SERDES (FPGA-TN-02077) 

- LatticeECP3, ECP5 and ECP5-5G Soft Error Detection (SED)/Correction (SEC) Usage Guide (FPGA-TN-02207) 

- Using TraceID (FPGA-TN-02084) 

- Sub-LVDS Signaling Using Lattice Devices (FPGA-TN-02208) 

- Advanced Security Encryption Key Programming Guide for ECP5, ECP5-5G, LatticeECP3, and LatticeECP2/MS Devices (FPGA-TN-02202) 

- LatticeECP3, LatticeECP2/M, ECP5 and ECP5-5G Dual Boot and Multiple Boot Feature (FPGA-TN-02203) 

- ECP5 and ECP5-5G sysCONFIG Usage Guide (FPGA-TN-02039) 

- ECP5 and ECP5-5G SERDES/PCS Usage Guide (FPGA-TN-02206) 

- ECP5 and ECP5-5G sysI/O Usage Guide (FPGA-TN-02032) 

- ECP5 and ECP5-5G sysClock PLL/DLL Design and Usage Guide (FPGA-TN-02200) 

- ECP5 and ECP5-5G Memory Usage Guide (FPGA-TN-02204) 

- ECP5 and ECP5-5G High-Speed I/O Interface (FPGA-TN-02035) 

- Power Consumption and Management for ECP5 and ECP5-5G Devices (FPGA-TN-02210) 

- ECP5 and ECP5-5G sysDSP Usage Guide (FPGA-TN-02205) 

- ECP5 and ECP5-5G Hardware Checklist (FPGA-TN-02038) 

- Solder Reflow Guide for Surface Mount Devices (FPGA-TN-02041) 

- ECP5 and ECP5-5G PCI Express Soft IP Ease of Use Guidelines (FPGA-TN-02045) 

- Programming External SPI Flash through JTAG for ECP5/ECP5-5G (FPGA-TN-02050) 

- Adding Scalable Power and Thermal Management to ECP5 Using L-ASC10 (FPGA-AN-02019) 

- MIPI D-PHY Bandwidth Matrix and Implementation (FPGA-TN-02090) 

For further information on interface standards, refer to the following websites: 

- JEDEC Standards (LVTTL, LVCMOS, SSTL): www.jedec.org 

- PCI: www.pcisig.com 

© 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02012-2.2 

105 

**ECP5 and ECP5-5G Family Data Sheet** 

## **Revision History** 

## **Revision 2.2, October 2020** 

|**Section**|**Change Summary**|
|---|---|
|Disclaimers|Added this section.|
|Introduction|UpdatedTable 1.1.|
|Architecture|<br>UpdatedTable 2.7.<br><br>Updated content ofSERDES and Physical Coding Sublayersection to add VCCcore<br>information.|
|DC and Switching Characteristics|<br>UpdatedFigure 3.14.<br><br>UpdatedSupply Current (Static)to change Standby to_Static_.<br><br>Updated note inTable 3.8.<br><br>UpdatedTable 3.27andTable 3.29.|
|Pinout Information|<br>Updated table inSignal Descriptionssection to remove GR_PCLK[Bank][num] row.<br><br>Updated table inLFE5UM/LFE5UM5Gto correct the Pin Type VCCAUX to_VCCAUXA_.<br><br>Updated table inLFE5Uto add column for TQFP 144 package and correct the pin count<br>for caBGA 381package.|
|Ordering Information|<br>Updated figure inECP5/ECP5-5G Part Number Description.<br><br>Updated table inCommercialandIndustrial.|



## **Revision 2.1, April 2019** 

|**Section**|**Change Summary**|
|---|---|
|General Description|In the Features section, changed feature to_subLVDS and SLVS, SoftIP MIPI D-PHY_<br>_receiver/transmitter interfaces_under Programmable sysI/O™ Buffer Supports Wide Range of<br>Interfaces.|
|Architecture|Updated the Supported sysI/O Standards section.|
|DC and Switching Characteristics|<br>Updated Table 3.11. sysI/O Recommended Operating Conditions.<br><br>Added/revised standards and values.<br><br>Corrected typo from LVCOM to LVCMOS.<br><br>Updated Table 3.12. Single-Ended DC Characteristics.<br><br>Corrected typo from LVCOM to LVCMOS.|
|Pinout Information|<br>Updated Configuration Pads (Used during sysCONFIG) in Signal Descriptions table.<br><br>Removed note 3.|
|Supplemental Information|<br>Updated document numbers of:<br><br>PCB Layout Recommendations for BGA Packages to FPGA-TN-02024<br><br>ECP5 and ECP5-5G sysI/O Usage Guide to FPGA-TN-02032<br><br>ECP5 and ECP5-5G High-Speed I/O Interface to FPGA-TN-02035<br><br>Added MIPI D-PHY Bandwidth Matrix and Implementation Technical Note.|
|All|Minor editorial changes.|



## **Revision 2.0, April 2018** 

|**Section**|**Change Summary**|
|---|---|
|Pin Information Summary|Adjusted tables in the LFE5UM/LFE5UM5G and the LFE5U sections.|
|Supplemental Information|Updated document number of ECP5 and ECP5-5G sysCONFIG Usage Guide to FPGA-TN-<br>02039.|



© 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

106 

FPGA-DS-02012-2.2 

**ECP5 and ECP5-5G Family Data Sheet** 

## **Revision 1.9, March 2018** 

|**Section**|**Change Summary**|
|---|---|
|All|Updated formatting and page referencing.|
|General Description|Updated Table 1.1. ECP5 and ECP5-5G Family Selection Guide. Added caBGA256 package in<br>LFE5U-45.|
|Architecture|Added a row for SGMII in Table 2.13. LFE5UM/LFE5UM5G SERDES Standard Support.<br>Updated footnote #1.|
|DC and Switching Characteristics|<br>Updated Table 3.2. Recommended Operating Conditions.<br><br>Added 2 rows and updated values in Table 3.7. DC Electrical Characteristics.<br><br>Updated Table 3.8. ECP5/ECP5-5G Supply Current (Standby).<br><br>Updated Table 3.11. sysI/O Recommended Operating Conditions.<br><br>Updated Table 3.12. Single-Ended DC Characteristics.<br><br>Updated Table 3.13. LVDS.<br><br>Updated Table 3.14. LVDS25E DC Conditions.<br><br>Updated Table 3.21. ECP5/ECP5-5G Maximum I/O Buffer Speed.<br><br>Updated Table 3.28. Receiver Total Jitter Tolerance Specification.<br><br>Updated header name of section 3.28 CPRI LV E.24/SGMII(2.5 Gbps) Electrical and<br>Timing Characteristics.<br><br>Updated header name of section 3.29 Gigabit Ethernet/SGMII (1.25 Gbps)/CPRI LV E.12<br>Electrical and Timing Characteristics.|
|Pinout Information|Updated table in section 4.3.2 LFE5U.|
|Ordering Information|<br>Added table rows in 5.2.1 Commercial.<br><br>Added table rows in 5.2.2 Industrial.|
|Supplemental Information|Updated For Further Information section.|



**Revision 1.8, November 2017** 

|**Section**|**Change Summary**|
|---|---|
|General Description|Updated Table 1.1. ECP5 and ECP5-5G Family Selection Guide.Added caBGA256 package in<br>LFE5U-12 and LFE5U-25.|



## **Revision 1.7, April 2017** 

|**Section**|**Change Summary**|
|---|---|
|All|Changed document number from DS1044 to FPGA-DS-02012.|
|General Description|Updated Features section. Changed 1.1 V core power supply to 1.1 V core power supply for<br>ECP5, 1.2 V corepower supplyfor ECP5UM5G.|
|Architecture|Updated Overview section.<br>Change The ECP5/ECP5-5G devices use 1.1 V as their core voltage to The ECP5 devices use<br>1.1 V, ECP5UM5G devices use 1.2 V as their core voltage.|
|DC and Switching Characteristics|<br>Updated Table 3.2. Recommended Operating Conditions.<br><br>Added ECP5-5G on VCCto be 1.2V +/- 5%.<br><br>Added ECP5-5G on VCCAto be 1.2V +/- 3%.<br><br>Updated Table 3.8. ECP5/ECP5-5G Supply Current (Standby).<br><br>Changed Core Power Supply Current for ICC on LFE5UM5G devices.<br><br>Changed SERDES Power Supply Current (Per Dual) for ICCA on LFE5UM5G devices.<br><br>Updated Table 3.20. Register-to-Register Performance.<br><br>Remove (DDR/SDR) from DSP Function.<br><br>Changed DSP functions to 225 MHz.|
|Pinout Information|Update Section 4.1 Signal Description. Revised Vcc Description to_Power supply pins for core_<br>_logic. Dedicatedpins. VCC = 1.1 V (ECP5), 1.2 V (ECP5UM5G)_.|



© 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02012-2.2 

107 

**ECP5 and ECP5-5G Family Data Sheet** 

## **Revision 1.6, February 2016** 

|**Section**|**Change Summary**|
|---|---|
|All|Changed document status from Preliminaryto Final.|
|General Description|<br>Updated Features section. Changed 24K to 84K LUTs to 12K to 84K LUTs.<br><br>Added LFE5U-12 column to Table 1.1. ECP5 and ECP5-5G FamilySelection Guide.|
|DC and Switching Characteristics|<br>Updated Power up Sequence section.<br><br>Identified typical ICC current for specific devices in Table 3.8. ECP5/ECP5-5G Supply<br>Current (Standby).<br><br>Updated values in Table 3.9. ECP5.<br><br>Updated values in Table 3.10. ECP5-5G.<br><br>Added values to –8 Timing column of Table 3.19. Pin-to-Pin Performance.<br><br>Added values to –8 Timing column of Table 3.20. Register-to-Register Performance.<br><br>Changed LFE5-45 to All Devices in Table 3.22. ECP5/ECP5-5G External Switching<br>Characteristics.<br><br>Added table notes to Table 3.31. PCIe (5 Gb/s).<br><br>Added table note to Table 3.32. CPRI LV2 E.48 Electrical and Timing Characteristics.<br><br>Added values to Max column of Table 3.39. Transmit.|
|Pinout Information|Added LFE5U-12 column to the table in LFE5U section.|
|Ordering Information|Updated LFE5U in ECP5/ECP5-5G Part Number Description section: added 12 F = 12K LUTs to<br>Logic Capacity.<br>Added LFE5U-12F information to OrderingPart Numbers section.|



## **Revision 1.5, November 2015** 

|**Section**|**Change Summary**|
|---|---|
|All|<br>Added ECP5-5G device family.<br><br>Changed document title to ECP5 and ECP5-5G Family Data Sheet.|



**Revision 1.4, November 2015** 

|**Section**|**Change Summary**|
|---|---|
|General Description|Updated Features section. Added support for eDP in RDR and HDR.|
|Architecture|<br>Updated Overview section.<br><br>Revised Figure 2.1. Simplified Block Diagram, LFE5UM/LFE5UM5G-85 Device (Top<br>Level). Modified Flexible sysI/O description and Note.<br><br>Updated SERDES and Physical Coding Sublayer section.<br><br>Changed E.24.V in CPRI protocol to E.24.LV.<br><br>Removed 1.1 V from paragraph on unused Dual.|
|DC and Switching Characteristics|<br>Updated Hot Socketing Requirements section. Revised VCCHTX in table notes 1 and 3.<br>Indicated VCCHTX in table note 4.<br><br>Updated SERDES High-Speed Data Transmitter section. Revised VCCHTX in table note 1.|
|Ordering Information|Updated ECP5/ECP5-5G Part Number Description section. Changed LFE5 FPGA under Device<br>Familyto ECP5 FPGA.|



© 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

108 

FPGA-DS-02012-2.2 

**ECP5 and ECP5-5G Family Data Sheet** 

## **Revision 1.3, August 2015** 

|**Section**|**Change Summary**|
|---|---|
|General Description|Updated Features section.<br><br>Removed SMPTE3G under Embedded SERDES.<br><br>Added Single Event Upset (SEU) Mitigation Support.<br><br>Removed SMPTEprotocol in fifthparagraph.|
|Architecture|General update.|
|DC and Switching Characteristics|General update.|
|Pinout Information|Updated Signal Descriptions section. Revised the descriptions of the following signals:<br><br>P[L/R] [Group Number]_[A/B/C/D]<br><br>P[T/B][Group Number]_[A/B]<br><br>D4/IO4 (Previously named D4/MOSI2/IO4)<br><br>D5/IO5 (Previously named D5/MISO/IO5)<br><br>VCCHRX_D[dual_num]CH[chan_num]<br><br>VCCHTX_D[dual_num]CH[chan_num]|
|Supplemental Information|Added TN1184 reference.|



## **Revision 1.2, August 2014** 

|**Section**|**Change Summary**|
|---|---|
|All|Changed document status from Advance to Preliminary.|
|General Description|<br>Updated Features section.<br><br>Deleted Serial Rapid I/O protocol under Embedded SERDES.<br><br>Corrected data rate under Pre-Engineered Source Synchronous I/O.<br><br>Changed DD3. LPDDR3 to DDR2/3, LPDDR2/3.<br><br>Mentioned transmit de-emphasispre- andpost-cursors.|
|Architecture|<br>Updated Overview section.<br><br>Revised description of PFU blocks.<br><br>Specified SRAM cell settings in describing the control of SERDES/PCS duals.<br><br>Updated SERDES and Physical Coding Sublayer section.<br><br>Changed PCI Express 2.0 to PCI Express Gen1 and Gen2.<br><br>Deleted Serial RapidIO protocol.<br><br>Updated Table 2.13. LFE5UM/LFE5UM5G SERDES Standard Support.<br><br>Updated Table 2.15. LFE5UM/LFE5UM5G Mixed Protocol Support.<br><br>Updated On-Chip Oscillator section.<br><br>Deleted_130 MHz ±15% CMOS_oscillator.<br><br>Updated Table 2.16. Selectable Master Clock (MCLK) Frequencies during<br>Configuration(Nominal)|
|DC and Switching Characteristics|<br>Updated Absolute Maximum Ratings section. Added supply voltages VCCAand VCCAUXA.<br><br>Updated sysI/O Recommended Operating Conditions section. Revised HSULD12D VCCIO<br>values and removed table note.<br><br>Updated sysI/O Single-Ended DC Electrical Characteristics section. Revised some values<br>for SSTL15 _I, SSTL15 _II, SSTL135_I, SSTL15_II, and HSUL12.<br><br>Updated External Switching Characteristics section. Changed parameters to tSKEW_PRVCCA<br>and tSKEW_EDGEand added LFE5-85 as device.<br><br>Updated ECP5 Family Timing Adders section. Added SSTL135_II buffer type data.<br>Removed LVCMOS33_20mA, LVCMOS25_20mA, LVCMOS25_16mA,<br>LVCMOS25D_16mA, and LVCMOS18_16mA buffer types. Changed buffer type to<br>LVCMOS12_4mA and LVCMOS12_8mA.<br><br>Updated Maximum I/O Buffer Speed section. Revised Max values.<br><br>Updated sysCLOCK PLL Timing section. Revised tDTMin and Max values. Revised tOPJIT<br>Max value. Revised number of samples in table note 1.|



© 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02012-2.2 

109 

**ECP5 and ECP5-5G Family Data Sheet** 

 Updated SERDES High-Speed Data Transmitter section. Updated Table 3.24. Serial Output Timing and Levels and Table 3.25. Channel Output Jitter.  In SERDES High-Speed Data Receiver section, updated Table 3.26. Serial Input Data Specifications, Table 3.28. Receiver Total Jitter Tolerance Specification, and Table 3.29. External Reference Clock Specification (refclkp/refclkn).  Modified section heading to XXAUI/CPRI LV E.30 Electrical and Timing Characteristics. Updated Table 3.33 Transmit and Table 3.34. Receive and Jitter Tolerance.  Modified section heading to CPRI LV E.24 Electrical and Timing Characteristics. Updated Table 3.35. Transmit and Table 3.36. Receive and Jitter Tolerance.  Modified section heading to Gigabit Ethernet/SGMII/CPRI LV E.12 Electrical and Timing Characteristics. Updated Table 3.37. Transmit and Table 3.38. Receive and Jitter Tolerance. 

**Revision 1.1, June 2014** 

**Section Change Summary** Ordering Information Updated ECP5/ECP5-5G Part Number Description and Ordering Part Numbers sections. **Revision 1.0, March 2014 Section Change Summary** All Initial release. ~~[ee]~~ 

© 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

110 

FPGA-DS-02012-2.2 

www.latticesemi.com
Updated at April 17, 2026
Lattice Semiconductor is a premier developer of low-power, programmable design solutions, specializing in Field-Programmable Gate Arrays (FPGAs) and Programmable Logic Devices (PLDs). Recognized for driving innovation in cost-effective and power-efficient architectures, the company provides essential semiconductor components for consumer, mobile, and industrial design applications. Our selection of Lattice Semiconductor products is focused on their highly regarded FPGA integrated circuits. Devices from industry-leading families like the iCE40, MachXO, and LatticeECP series offer designers an exceptional combination of high system integration and industry-low power consumption. These FPGAs are engineered to handle complex tasks such as sensor management, custom connectivity, and advanced video processing while minimizing overall board footprint. To ensure seamless integration from concept to production, Lattice backs its hardware with a comprehensive support ecosystem. Engineers can accelerate their development cycles utilizing intuitive tools like the Lattice Diamond design software, paired with flexible IP cores and reference designs that reduce design risk and increase system reliability.
About Novapart

Novapart is a B2B electronic component broker specialising in stock shortages and cost reduction. We source hard-to-find parts and identify compliant alternatives across a catalogue of 410,000+ components from 500+ manufacturers.
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Stock Shortage Specialist

When a component is unavailable, discontinued or has an unacceptable lead time, we tap into our network of vetted European and Asian distributors to source what you need — without compromising on quality or traceability.
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Compliant Alternatives

We identify pin-to-pin, electrically equivalent substitutes that meet the same certifications (RoHS, AEC-Q100, REACH) as your original specification — validated against datasheets, not just part numbers. Often at a lower cost.
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