LCMXO3LF-1300C-5BG256C

## Os 

## **MachXO3 Family** 

## **Data Sheet** 

FPGA-DS-02032-2.8 

January 2021 

**MachXO3 Family Data Sheet** 

## **Disclaimers** 

Lattice makes no warranty, representation, or guarantee regarding the accuracy of information contained in this document or the suitability of its products for any particular purpose. All information herein is provided AS IS and with all faults, and all risk associated with such information is entirely with Buyer. Buyer shall not rely on any data and performance specifications or parameters provided herein. Products sold by Lattice have been subject to limited testing and it is the Buyer's responsibility to independently determine the suitability of any products and to test and verify the same. No Lattice products should be used in conjunction with mission- or safety-critical or any other application in which the failure of Lattice’s product could create a situation where personal injury, death, severe property or environmental damage may occur. The information provided in this document is proprietary to Lattice Semiconductor, and Lattice reserves the right to make any changes to the information in this document or to any products at any time without notice. 

© 2014-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

2 

FPGA-DS-02032-2.8 

**MachXO3 Family Data Sheet** 

## **Contents** 

|**Contents**|**Contents**|**Contents**|
|---|---|---|
|Acronyms in This Document ................................................................................................................................................. 7|||
|1.|Introduction .................................................................................................................................................................. 9||
||1.1.|Features ............................................................................................................................................................ 10|
||1.1.1.|Solutions ....................................................................................................................................................... 10|
||1.1.2.|Flexible Architecture .................................................................................................................................... 10|
||1.1.3.|Advanced Packaging ..................................................................................................................................... 10|
||1.1.4.|Pre-Engineered Source Synchronous I/O ..................................................................................................... 10|
||1.1.5.|High Performance, Flexible I/O Buffer ......................................................................................................... 10|
||1.1.6.|Flexible On-Chip Clocking ............................................................................................................................. 10|
||1.1.7.|Non-volatile, Multi-time Programmable ...................................................................................................... 10|
||1.1.8.|TransFR Reconfiguration .............................................................................................................................. 10|
||1.1.9.|Enhanced System Level Support .................................................................................................................. 10|
||1.1.10. Applications .................................................................................................................................................. 10||
||1.1.11. Low Cost Migration Path .............................................................................................................................. 10||
|2.|Architecture ................................................................................................................................................................ 12||
||2.1.|Architecture Overview ...................................................................................................................................... 12|
||2.2.|PFU Blocks ......................................................................................................................................................... 14|
||2.2.1.|Slices ............................................................................................................................................................. 14|
||2.2.2.|Modes of Operation ..................................................................................................................................... 16|
||2.2.3.|RAM Mode ................................................................................................................................................... 16|
||2.2.4.|ROM Mode ................................................................................................................................................... 16|
||2.3.|Routing .............................................................................................................................................................. 17|
||2.4.|Clock/Control Distribution Network .................................................................................................................. 17|
||2.4.1.|sysCLOCK Phase Locked Loops (PLLs) ........................................................................................................... 19|
||2.5.|sysMEM Embedded Block RAM Memory .......................................................................................................... 22|
||2.5.1.|sysMEM Memory Block ................................................................................................................................ 22|
||2.5.2.|Bus Size Matching ......................................................................................................................................... 22|
||2.5.3.|RAM Initialization and ROM Operation ........................................................................................................ 22|
||2.5.4.|Memory Cascading ....................................................................................................................................... 22|
||2.5.5.|Single, Dual, Pseudo-Dual Port and FIFO Modes .......................................................................................... 23|
||2.5.6.|FIFO Configuration ....................................................................................................................................... 24|
||2.5.7.|Memory Core Reset...................................................................................................................................... 24|
||2.5.8.|EBR Asynchronous Reset .............................................................................................................................. 25|
||2.6.|Programmable I/O Cells (PIC) ............................................................................................................................ 26|
||2.7.|PIO ..................................................................................................................................................................... 28|
||2.7.1.|Input Register Block ..................................................................................................................................... 28|
||2.7.2.|Output Register Block ................................................................................................................................... 28|
||2.7.3.|Tri-state Register Block ................................................................................................................................. 29|
||2.8.|Input Gearbox ................................................................................................................................................... 29|
||2.9.|Output Gearbox ................................................................................................................................................ 31|
||2.10.|sysI/O Buffer...................................................................................................................................................... 33|
||2.10.1. Typical I/O Behavior during Power-up ......................................................................................................... 33||
||2.10.2. Supported Standards .................................................................................................................................... 33||
||2.10.3. sysI/O Buffer Banks ...................................................................................................................................... 35||
||2.11.|Hot Socketing .................................................................................................................................................... 36|
||2.12.|On-chip Oscillator .............................................................................................................................................. 36|
||2.13.|Embedded Hardened IP Functions .................................................................................................................... 36|
||2.13.1. Hardened I2C IP Core .................................................................................................................................... 37||
||2.13.2. Hardened SPI IP Core.................................................................................................................................... 38||
||2.13.3. Hardened Timer/Counter ............................................................................................................................. 40||
||2.14.|User Flash Memory (UFM) ................................................................................................................................ 41|
||2.15.|Standby Mode and Power Saving Options ........................................................................................................ 42|



© 2014-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02032-2.8 

**MachXO3 Family Data Sheet** 

||2.16.|Power On Reset ................................................................................................................................................. 43|
|---|---|---|
||2.17.|Configuration and Testing ................................................................................................................................. 43|
||2.17.1. IEEE 1149.1-Compliant Boundary Scan Testability ....................................................................................... 43||
||2.17.2. Device Configuration .................................................................................................................................... 43||
||2.18.|TraceID .............................................................................................................................................................. 45|
||2.19.|Density Shifting ................................................................................................................................................. 45|
||2.20.|MachXO3LF to MachXO3L Low Cost Migration Path ........................................................................................ 45|
|3.|DC and Switching Characteristics ................................................................................................................................ 46||
||3.1.|Absolute Maximum Rating ................................................................................................................................ 46|
||3.2.|Recommended Operating Conditions ............................................................................................................... 46|
||3.3.|Power Supply Ramp Rates ................................................................................................................................. 46|
||3.4.|Power-On-Reset Voltage Levels ........................................................................................................................ 47|
||3.5.|Hot Socketing Specifications ............................................................................................................................. 47|
||3.6.|Programming/Erase Specifications ................................................................................................................... 48|
||3.7.|ESD Performance ............................................................................................................................................... 48|
||3.8.|DC Electrical Characteristics .............................................................................................................................. 49|
||3.9.|Static Supply Current – C/E Devices .................................................................................................................. 50|
||3.10.|Programming and Erase Supply Current – C/E Devices ..................................................................................... 50|
||3.11.|sysI/O Recommended Operating Conditions ..................................................................................................... 51|
||3.12.|sysI/O Single-Ended DC Electrical Characteristics .............................................................................................. 52|
||3.13.|sysI/O Differential Electrical Characteristics ..................................................................................................... 53|
||3.13.1. LVDS .............................................................................................................................................................. 53||
||3.13.2. LVDS Emulation ............................................................................................................................................ 53||
||3.13.3. BLVDS ........................................................................................................................................................... 54||
||3.13.4. LVPECL .......................................................................................................................................................... 55||
||3.13.5. MIPI D-PHY Emulation .................................................................................................................................. 56||
||3.14.|Typical Building Block Function Performance – C/E Devices ............................................................................. 58|
||3.14.1. Pin-to-Pin Performance (LVCMOS25 12 mA Drive) ...................................................................................... 58||
||3.14.2. Register-to-Register Performance ................................................................................................................ 59||
||3.15.|Derating Logic Timing ........................................................................................................................................ 59|
||3.16.|Maximum sysI/O Buffer Performance ............................................................................................................... 59|
||3.17.|MachXO3L/LF External Switching Characteristics – C/E Devices ...................................................................... 60|
||3.18.|sysCLOCK PLL Timing ......................................................................................................................................... 69|
||3.19.|Oscillator Output Frequency ............................................................................................................................. 71|
||3.20.|NVCM/Flash Download Time ............................................................................................................................ 71|
||3.21.|JTAG Port Timing Specifications ........................................................................................................................ 72|
||3.22.|sysCONFIG Port Timing Specifications ............................................................................................................... 73|
||3.23.|I2C Port Timing Specifications ............................................................................................................................ 74|
||3.24.|SPI Port Timing Specifications ........................................................................................................................... 74|
||3.25.|Switching Test Conditions ................................................................................................................................. 74|
|4.|Signal Descriptions ...................................................................................................................................................... 75||
||4.1.|Pin Information Summary ................................................................................................................................. 76|
|5.|MachXO3 Part Number Description ........................................................................................................................... 81||
|6.|Ordering Information .................................................................................................................................................. 82||
||6.1.|MachXO3L Ultra Low Power Commercial and Industrial Grade Devices, Halogen Free (RoHS) Packaging ...... 82|
||6.2.|MachXO3LF Ultra Low Power Commercial and Industrial Grade Devices, Halogen Free (RoHS) Packaging .... 85|
||6.3.|MachXO3LF Ultra Low Power Automotive Grade Devices, Halogen Free (RoHS) Packaging ............................ 88|
|References .......................................................................................................................................................................... 89|||
|Revision History .................................................................................................................................................................. 90|||



© 2014-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02032-2.8 

4 

**MachXO3 Family Data Sheet** 

## **Figures** 

|Figure 2.1. Top View of the MachXO3L/LF-1300 Device .................................................................................................... 12|Figure 2.1. Top View of the MachXO3L/LF-1300 Device .................................................................................................... 12|
|---|---|
|Figure 2.2. Top View of the MachXO3L/LF-4300 Device .................................................................................................... 13|Figure 2.2. Top View of the MachXO3L/LF-4300 Device .................................................................................................... 13|
|Figure 2.3. PFU Block Diagram ............................................................................................................................................ 14|Figure 2.3. PFU Block Diagram ............................................................................................................................................ 14|
|Figure 2.4. Slice Diagram .................................................................................................................................................... 15|Figure 2.4. Slice Diagram .................................................................................................................................................... 15|
|Figure 2.5. Primary Clocks for MachXO3L/F Devices .......................................................................................................... 18|Figure 2.5. Primary Clocks for MachXO3L/F Devices .......................................................................................................... 18|
|Figure 2.6. Secondary High Fanout Nets for MachXO3L/F Devices .................................................................................... 19|Figure 2.6. Secondary High Fanout Nets for MachXO3L/F Devices .................................................................................... 19|
|Figure 2.7. PLL Diagram ...................................................................................................................................................... 20|Figure 2.7. PLL Diagram ...................................................................................................................................................... 20|
|Figure 2.8. sysMEM Memory Primitives ............................................................................................................................. 23|Figure 2.8. sysMEM Memory Primitives ............................................................................................................................. 23|
|Figure 2.9. Memory Core Reset .......................................................................................................................................... 25|Figure 2.9. Memory Core Reset .......................................................................................................................................... 25|
|Figure 2.10. EBR Asynchronous Reset (Including GSR) Timing Diagram ............................................................................. 25|Figure 2.10. EBR Asynchronous Reset (Including GSR) Timing Diagram ............................................................................. 25|
|Figure 2.11. Group of Four Programmable I/O Cells .......................................................................................................... 27|Figure 2.11. Group of Four Programmable I/O Cells .......................................................................................................... 27|
|Figure 2.12. Output Register Block Diagram (PIO on the Left, Top and Bottom Edges) ..................................................... 29|Figure 2.12. Output Register Block Diagram (PIO on the Left, Top and Bottom Edges) ..................................................... 29|
|Figure 2.13. Input Gearbox ................................................................................................................................................. 30|Figure 2.13. Input Gearbox ................................................................................................................................................. 30|
|Figure 2.14. Output Gearbox .............................................................................................................................................. 32|Figure 2.14. Output Gearbox .............................................................................................................................................. 32|
|Figure 2.15. MachXO3L/LF-1300 in 256 Ball Packages, MachXO3L/LF-2100,|Figure 2.15. MachXO3L/LF-1300 in 256 Ball Packages, MachXO3L/LF-2100,|
||MachXO3L/LF-4300, MachXO3L/LF-6900 and MachXO3L/LF-9400 Banks I/O Banks ..................................... 35|
|Figure 2.16. MachXO3L/LF-640 and MachXO3L/LF-1300 Banks ........................................................................................ 35|Figure 2.16. MachXO3L/LF-640 and MachXO3L/LF-1300 Banks ........................................................................................ 35|
|Figure 2.17. Embedded Function Block Interface ............................................................................................................... 37|Figure 2.17. Embedded Function Block Interface ............................................................................................................... 37|
|Figure 2.18. I|Figure 2.18. I2C Core Block Diagram ................................................................................................................................... 37|
|Figure 2.19. SPI Core Block Diagram ................................................................................................................................... 39|Figure 2.19. SPI Core Block Diagram ................................................................................................................................... 39|
|Figure 2.20. Timer/Counter Block Diagram ........................................................................................................................ 41|Figure 2.20. Timer/Counter Block Diagram ........................................................................................................................ 41|
|Figure 3.1. LVDS Using External Resistors (LVDS25E) ......................................................................................................... 53|Figure 3.1. LVDS Using External Resistors (LVDS25E) ......................................................................................................... 53|
|Figure 3.2. BLVDS Multi-point-Output Example ................................................................................................................. 54|Figure 3.2. BLVDS Multi-point-Output Example ................................................................................................................. 54|
|Figure 3.3. Differential LVPECL ........................................................................................................................................... 55|Figure 3.3. Differential LVPECL ........................................................................................................................................... 55|
|Figure 3.4. MIPI D-PHY Input Using External Resistors ....................................................................................................... 56|Figure 3.4. MIPI D-PHY Input Using External Resistors ....................................................................................................... 56|
|Figure 3.5. MIPI D-PHY Output Using External Resistors .................................................................................................... 57|Figure 3.5. MIPI D-PHY Output Using External Resistors .................................................................................................... 57|
|Figure 3.6.Receiver GDDR71_RX. Waveforms .................................................................................................................... 69|Figure 3.6.Receiver GDDR71_RX. Waveforms .................................................................................................................... 69|
|Figure 3.7. Transmitter GDDR71_TX. Waveforms .............................................................................................................. 69|Figure 3.7. Transmitter GDDR71_TX. Waveforms .............................................................................................................. 69|
|Figure 3.8. JTAG Port Timing Waveforms ........................................................................................................................... 72|Figure 3.8. JTAG Port Timing Waveforms ........................................................................................................................... 72|
|Figure 3.9. Output Test Load, LVTTL and LVCMOS Standards ............................................................................................ 74|Figure 3.9. Output Test Load, LVTTL and LVCMOS Standards ............................................................................................ 74|



## **Tables** 

|Table 1.1. MachXO3L/LF Family Selection Guide ............................................................................................................... 11|Table 1.1. MachXO3L/LF Family Selection Guide ............................................................................................................... 11|
|---|---|
|Table 2.1. Resources and Modes Available per Slice .......................................................................................................... 14|Table 2.1. Resources and Modes Available per Slice .......................................................................................................... 14|
|Table 2.2. Slice Signal Descriptions ..................................................................................................................................... 15|Table 2.2. Slice Signal Descriptions ..................................................................................................................................... 15|
|Table 2.3. Number of Slices Required For Implementing Distributed RAM ....................................................................... 16|Table 2.3. Number of Slices Required For Implementing Distributed RAM ....................................................................... 16|
|Table 2.4. PLL Signal Descriptions ....................................................................................................................................... 21|Table 2.4. PLL Signal Descriptions ....................................................................................................................................... 21|
|Table 2.5. sysMEM Block Configurations ............................................................................................................................ 22|Table 2.5. sysMEM Block Configurations ............................................................................................................................ 22|
|Table 2.6. EBR Signal Descriptions ...................................................................................................................................... 23|Table 2.6. EBR Signal Descriptions ...................................................................................................................................... 23|
|Table 2.7. Programmable FIFO Flag Ranges ....................................................................................................................... 24|Table 2.7. Programmable FIFO Flag Ranges ....................................................................................................................... 24|
|Table 2.8. PIO Signal List ..................................................................................................................................................... 28|Table 2.8. PIO Signal List ..................................................................................................................................................... 28|
|Table 2.9. Input Gearbox Signal List ................................................................................................................................... 29|Table 2.9. Input Gearbox Signal List ................................................................................................................................... 29|
|Table 2.10. Output Gearbox Signal List .............................................................................................................................. 31|Table 2.10. Output Gearbox Signal List .............................................................................................................................. 31|
|Table 2.11. Supported Input Standards .............................................................................................................................. 34|Table 2.11. Supported Input Standards .............................................................................................................................. 34|
|Table 2.12. Supported Output Standards ........................................................................................................................... 34|Table 2.12. Supported Output Standards ........................................................................................................................... 34|
|Table 2.13. Available MCLK Frequencies ............................................................................................................................ 36|Table 2.13. Available MCLK Frequencies ............................................................................................................................ 36|
|Table 2.14. I|Table 2.14. I2C Core Signal Description ............................................................................................................................... 38|
|Table 2.15. SPI Core Signal Description .............................................................................................................................. 40|Table 2.15. SPI Core Signal Description .............................................................................................................................. 40|
|Table 2.16. Timer/Counter Signal Description .................................................................................................................... 41|Table 2.16. Timer/Counter Signal Description .................................................................................................................... 41|



© 2014-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02032-2.8 

5 

**MachXO3 Family Data Sheet** 

|Table 2.17. MachXO3L/LF Power Saving Features Description .......................................................................................... 42|Table 2.17. MachXO3L/LF Power Saving Features Description .......................................................................................... 42|
|---|---|
|Table 3.1. Absolute Maximum Rating|Table 3.1. Absolute Maximum Rating1, 2, 3.......................................................................................................................... 46|
|Table 3.2. Recommended Operating Conditions|Table 3.2. Recommended Operating Conditions1.............................................................................................................. 46|
|Table 3.3. Power Supply Ramp Rates ................................................................................................................................. 46|Table 3.3. Power Supply Ramp Rates ................................................................................................................................. 46|
|Table 3.4. Power-On Reset Voltage Levels ......................................................................................................................... 47|Table 3.4. Power-On Reset Voltage Levels ......................................................................................................................... 47|
|Table 3.5. Hot Socketing Specifications .............................................................................................................................. 47|Table 3.5. Hot Socketing Specifications .............................................................................................................................. 47|
|Table 3.6. Programming/Erase Specifications .................................................................................................................... 48|Table 3.6. Programming/Erase Specifications .................................................................................................................... 48|
|Table 3.7. DC Electrical Characteristics ............................................................................................................................... 49|Table 3.7. DC Electrical Characteristics ............................................................................................................................... 49|
|Table 3.8. Static Supply Current – C/E Devices|Table 3.8. Static Supply Current – C/E Devices1, 2, 3, 6.......................................................................................................... 50|
|Table 3.9. Programming and Erase Supply Current – C/E Devices|Table 3.9. Programming and Erase Supply Current – C/E Devices1, 2, 3, 4............................................................................. 50|
|Table 3.10. sysI/O Recommended Operating Conditions ................................................................................................... 51|Table 3.10. sysI/O Recommended Operating Conditions ................................................................................................... 51|
|Table 3.11. sysI/O Single-Ended DC Electrical Charateristics|Table 3.11. sysI/O Single-Ended DC Electrical Charateristics1, 2, 4....................................................................................... 52|
|Table 3.12. LVDS ................................................................................................................................................................. 53|Table 3.12. LVDS ................................................................................................................................................................. 53|
|Table 3.13. LVDS25E DC Conditions .................................................................................................................................... 54|Table 3.13. LVDS25E DC Conditions .................................................................................................................................... 54|
|Table 3.14. BLVDS DC Condition ......................................................................................................................................... 55|Table 3.14. BLVDS DC Condition ......................................................................................................................................... 55|
|Table 3.15. LVPECL DC Conditions ...................................................................................................................................... 56|Table 3.15. LVPECL DC Conditions ...................................................................................................................................... 56|
|Table 3.16. MIPI DC Conditions .......................................................................................................................................... 57|Table 3.16. MIPI DC Conditions .......................................................................................................................................... 57|
|Table 3.17. MIPI D-PHY Output DC Conditions ................................................................................................................... 58|Table 3.17. MIPI D-PHY Output DC Conditions ................................................................................................................... 58|
|Table 3.18. Pin-to-Pin Performance (LVCMOS25 12 mA Drive) .......................................................................................... 58|Table 3.18. Pin-to-Pin Performance (LVCMOS25 12 mA Drive) .......................................................................................... 58|
|Table 3.19. Register-to-Register Performance.................................................................................................................... 59|Table 3.19. Register-to-Register Performance.................................................................................................................... 59|
|Table 3.20. Maximum sysI/O Buffer Performance ............................................................................................................. 59|Table 3.20. Maximum sysI/O Buffer Performance ............................................................................................................. 59|
|Table 3.21. MachXO3L/LF External Switching Characteristics – C/E Devices|Table 3.21. MachXO3L/LF External Switching Characteristics – C/E Devices1, 2, 3, 4, 5, 6, 10................................................... 60|
|Table 3.22. sysCLOCK PLL Timing ........................................................................................................................................ 69|Table 3.22. sysCLOCK PLL Timing ........................................................................................................................................ 69|
|Table 3.23. Oscillator Output Frequency ............................................................................................................................ 71|Table 3.23. Oscillator Output Frequency ............................................................................................................................ 71|
|Table 3.24. NVCM/Flash Download Time ........................................................................................................................... 71|Table 3.24. NVCM/Flash Download Time ........................................................................................................................... 71|
|Table 3.25. JTAG Port Timing Specifications ....................................................................................................................... 72|Table 3.25. JTAG Port Timing Specifications ....................................................................................................................... 72|
|Table 3.26. sysCONFIG Port Timing Specifications ............................................................................................................. 73|Table 3.26. sysCONFIG Port Timing Specifications ............................................................................................................. 73|
|Table 3.27. I|Table 3.27. I2C Port Timing Specification ............................................................................................................................ 74|
|Table 3.28. SPI Port Timing Specifications .......................................................................................................................... 74|Table 3.28. SPI Port Timing Specifications .......................................................................................................................... 74|
|Table 3.29. Test Fixture Required Components, Non-Terminated Interfaces .................................................................... 74|Table 3.29. Test Fixture Required Components, Non-Terminated Interfaces .................................................................... 74|
|Table 4.1. Signal Descriptions ............................................................................................................................................. 75|Table 4.1. Signal Descriptions ............................................................................................................................................. 75|
|Table 4.2. MachXO3L/LF-640 and MachXO3L/LF-1300 Pin Summary ................................................................................ 76|Table 4.2. MachXO3L/LF-640 and MachXO3L/LF-1300 Pin Summary ................................................................................ 76|
|Table 4.3. MachXO3L/LF-2100 Pin Summary ...................................................................................................................... 77|Table 4.3. MachXO3L/LF-2100 Pin Summary ...................................................................................................................... 77|
|Table 4.4. MachXO3L/LF-4300 Pin Summary ...................................................................................................................... 78|Table 4.4. MachXO3L/LF-4300 Pin Summary ...................................................................................................................... 78|
|Table 4.5. MachXO3L/LF-6900 Pin Summary ...................................................................................................................... 79|Table 4.5. MachXO3L/LF-6900 Pin Summary ...................................................................................................................... 79|
|Table 4.6. MachXO3L/LF-9400C Pin Summary ................................................................................................................... 80|Table 4.6. MachXO3L/LF-9400C Pin Summary ................................................................................................................... 80|



© 2014-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02032-2.8 

6 

**MachXO3 Family Data Sheet** 

## **Acronyms in This Document** 

A list of acronyms used in this document. 

~~I~~ **Acronym Definition** ~~a~~ AES Advanced Encryption Standard ~~a~~ BGA Ball Grid Array ~~Ge~~ caBGA ChipArray Ball Grill Array ~~Ge~~ csfBGA Chip Scale Flip-Chip Ball Grid Array CE Clock Enable ~~eG I~~ CLK System clock ~~a~~ CMOS Complementary Metal Oxide Semiconductor DDR Double Data Rate ~~a~~ EBR Embedded Block RAM ~~Ge a~~ ECDSA Elliptic Curve Digital Signature Algorithm ~~Ge~~ ECLK Edge Clock ~~I~~ ESB Embedded Security Block ~~a~~ FCIN Fast Carry In ~~a~~ FCO Fast Carry Out ~~a~~ I[2] C Inter-Integrated Circuit ~~Ge~~ IP Intellectual Property ~~Ge~~ I/O Input/Output ~~eG~~ JTAG Joint Test Action Group ~~I~~ LED Light-emitting Diode ~~a~~ LSR Local Set/Reset ~~a~~ LUT Look-Up Table LVCMOS Low-Voltage CMOS ~~a~~ LVDS Low-Voltage Differential Signaling ~~Ge~~ LVPECL Low-Voltage Positive/Pseudo Emitter-Coupled Logic ~~a~~ LVTTL Low Voltage Transistor to Transistor Logic ~~a~~ MIPI Mobile Industry Processor Interface ~~a~~ MLVDS ~~G~~ Multipoint Low-Voltage Differential Signaling ~~ee~~ NVCM Non Volatile Configuration Memory ~~a~~ PCI Peripheral Component Interconnect ~~ee~~ PCLK Primary Clock PDPR Pseudo Dual Port RAM ~~eG a~~ PFU Programmable Functional Unit ~~a~~ PIC Programmable Interface Controllers ~~a~~ PIO ~~G~~ Programmed Input/Output ~~ee~~ PLD Programmable Logic Device ~~a~~ PLL Phase Locked Loop ~~eG~~ RAM Random Access Memory ~~a~~ ROM Read-only Memory ~~a~~ SDR Single Data Rate ~~a~~ SHA Secure Hash Algorithm ~~a~~ SPI Serial Peripheral Interface 

© 2014-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02032-2.8 

7 

**MachXO3 Family Data Sheet** 

|**Acronym **|**Definition**|
|---|---|
|SPR|Single Port Random Access Memory|
|SRAM|Static Random Access Memory|
|TransFR™|Transparent Field Reconfiguration|
|UFM|User Flash Memory|
|WLCSP|Wafer Level ChipScale Package|



© 2014-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

8 

FPGA-DS-02032-2.8 

**MachXO3 Family Data Sheet** 

## **1. Introduction** 

MachXO3™ device family is an Ultra-Low Density family that supports the most advanced programmable bridging and I/O expansion. It has the breakthrough I/O density and the lowest cost per I/O. The device I/O features have the integrated support for latest industry standard I/O. 

The MachXO3L/LF family of low power, instant-on, non-volatile PLDs has five devices with densities ranging from 640 to 9400 Look-Up Tables (LUTs). In addition to LUT-based, low-cost programmable logic these devices feature Embedded Block RAM (EBR), Distributed RAM, Phase Locked Loops (PLLs), pre-engineered source synchronous I/O support, advanced configuration support including dual-boot capability and hardened versions of commonly used functions such as SPI controller, I[2] C controller and timer/counter. MachXO3LF devices also support User Flash Memory (UFM). These features allow these devices to be used in low cost, high volume applications such as consumer electronics, compute and storage, wireless communications, industrial control, and automotive systems. 

The MachXO3L/LF devices are designed on a 65 nm non-volatile low power process. The device architecture has several features such as programmable low swing differential I/Os and the ability to turn off I/O banks, on-chip PLLs and oscillators dynamically. These features help manage static and dynamic power consumption resulting in low static power for all members of the family. 

The MachXO3L/LF devices are available in two versions C and E with two speed grades: -5 and -6, with -6 being the fastest. C devices have an internal linear voltage regulator which supports external VCC supply voltages of 3.3 V or 2.5 V. E devices only accept 1.2 V as the external VCC supply voltage. With the exception of power supply voltage both C and E are functionally compatible with each other. 

The MachXO3L/LF devices offer enhanced I/O features such as drive strength control, slew rate control, PCI compatibility, bus-keeper latches, pull-up resistors, pull-down resistors, open drain outputs and hot socketing. Pull-up, pull-down and bus-keeper features are controllable on a “per-pin” basis. A userprogrammable internal oscillator is included in MachXO3L/LF devices. The clock output from this oscillator may be divided by the timer/counter for use as clock input in functions such as LED control, keyboard scanner and similar state machines. 

The MachXO3L/LF devices also provide flexible, reliable and secure configuration from on-chip NVCM/Flash. These devices can also configure themselves from external SPI Flash or be configured by an external master through the JTAG test access port or through the I[2] C port. Additionally, MachXO3L/LF devices support dual-boot capability (using external Flash memory) and remote field upgrade (TransFR) capability. 

Lattice provides a variety of design tools that allow complex designs to be efficiently implemented using the MachXO3L/LF family of devices. Popular logic synthesis tools provide synthesis library support for MachXO3L/LF. Lattice design tools use the synthesis tool output along with the user-specified preferences and constraints to place and route the design in the MachXO3L/LF device. These tools extract the timing from the routing and back-annotate it into the design for timing verification. 

Lattice provides many pre-engineered IP (Intellectual Property) LatticeCORE™ modules, including a number of reference designs licensed free of charge, optimized for the MachXO3L/LF PLD family. By using these configurable soft core IP cores as standardized blocks, users are free to concentrate on the unique aspects of their design, increasing their productivity. 

The MachXO3L/LF PLDs are available in a broad range of advanced halogen-free packages ranging from the space saving 2.5 x 2.5 mm WLCSP to the 19 x 19 mm caBGA. MachXO3L/LF devices support density migration within the same package. Table 1.1 shows the LUT densities, package and I/O options, along with other key parameters. 

© 2014-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02032-2.8 

9 

**MachXO3 Family Data Sheet** 

## **1.1. Features** 

## **1.1.6. Flexible On-Chip Clocking** 

- Eight primary clocks 

## **1.1.1. Solutions** 

- Smallest footprint, lowest power, high data throughput bridging solutions for mobile applications 

- Optimized footprint, logic density, I/O count, I/O performance devices for I/O management and logic applications 

- High I/O logic, lowest cost I/O, high I/O devices for I/O expansion applications 

- Up to two edge clocks for high-speed I/O interfaces (top and bottom sides only) 

- Up to two analog PLLs per device with fractional-n frequency synthesis 

   - Wide input frequency range (7 MHz to 400 MHz). 

## **1.1.7. Non-volatile, Multi-time Programmable** 

- Instant-on 

## **1.1.2. Flexible Architecture** 

- Logic Density ranging from 64 to 9.4K LUT4 

- High I/O to LUT ratio with up to 384 I/O pins 

   - Powers up in microseconds 

- Optional dual boot with external SPI memory 

- Single-chip, secure solution 

- Programmable through JTAG, SPI or I2C 

## **1.1.3. Advanced Packaging** 

- 0.4 mm pitch: 1K to 4K densities in very small footprint WLCSP (2.5 mm × 2.5 mm to 3.8 mm × 3.8 mm) with 28 to 63 I/Os 

- 0.5 mm pitch: 640 to 9.4K LUT densities in 6 mm x 6 mm to 10 mm x 10 mm BGA packages with up to 281 I/Os 

- 0.8 mm pitch: 1K to 9.4K densities with up to 384 I/Os in BGA packages 

## **1.1.4. Pre-Engineered Source Synchronous I/O** 

- DDR registers in I/O cells 

- Dedicated gearing logic 

- 7:1 Gearing for Display I/Os 

- Generic DDR, DDRx2, DDRx4 

## **1.1.5. High Performance, Flexible I/O Buffer** 

- Programmable sysI/O™ buffer supports wide range of interfaces: 

   - LVCMOS 3.3/2.5/1.8/1.5/1.2 

   - LVTTL 

   - LVDS, Bus-LVDS, MLVDS, LVPECL 

   - MIPI D-PHY Emulated 

   - Schmitt trigger inputs, up to 0.5 V hysteresis 

- Ideal for I/O bridging applications 

- I/Os support hot socketing 

- On-chip differential termination 

- Programmable pull-up or pull-down mode 

- MachXO3L includes multi-time programmable NVCM 

- MachXO3LF reconfigurable Flash includes 100,000 write/erase cycle for commercial/industrial devices and 10,000 for automotive devices 

   - Supports background programming of non volatile memory 

## **1.1.8. TransFR Reconfiguration** 

- In-field logic update while I/O holds the system state 

## **1.1.9. Enhanced System Level Support** 

- On-chip hardened functions: SPI, I2C, timer/counter 

- On-chip oscillator with 5.5% accuracy for commercial/industrial devices 

- Unique TraceID for system tracking 

- Single power supply with extended operating range 

- IEEE Standard 1149.1 boundary scan 

- IEEE 1532 compliant in-system programming 

## **1.1.10. Applications** 

- Consumer Electronics 

- Compute and Storage 

- Wireless Communications 

- Industrial Control Systems 

- Automotive System 

## **1.1.11. Low Cost Migration Path** 

- Migration from the Flash based MachXO3LF to the NVCM based MachXO3L 

- Pin compatible and equivalent timing 

© 2014-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

10 

FPGA-DS-02032-2.8 

**MachXO3 Family Data Sheet** 

**Table 1.1. MachXO3L/LF Family Selection Guide** 

**==> picture [486 x 522] intentionally omitted <==**

**----- Start of picture text -----**<br>
|||||||||||
|---|---|---|---|---|---|---|---|---|---|
|MachXO3L-|MachXO3L-|MachXO3L-|MachXO3L-|MachXO3L-|
|MachXO3L-640/|1300/|2100/|4300/|6900/|9400/|
|Features|
|MachXO3LF-640|MachXO3LF-|MachXO3LF-|MachXO3LF-|MachXO3LF-|MachXO3LF-|
|1300|2100|4300|6900|9400|
|LUTs|640|1300|2100|4300|6900|[4]|9400|[4]|
|Ca|Distributed RAM (kb)|5|OO|10|16|34|54|73|
|a|EBR SRAM (kb)|64|OO|64|74|92|240|432|
|UFM (kb, MachXO3LF only)|64|64|80|96|256|448|
|ee|Device|C|[5]|—|Yes|Yes|Yes|Yes|Yes|
|Options|E|[6]|Yes|Yes|Yes|Yes|Yes|Yes|
|eer|cere|eee|eee ee ee|e|
|Ca|Number of PLLs|1|GO|1|1|2|2|2|
|I|[2]|C|2|2|2|2|2|2|
|a|CC|
|SPI|1|1|1|1|1|1|
|Hardened|nsGO|
|Functions|Timer/|1|1|1|1|1|1|
|Counter|
|Oscillator|1|1|1|1|1|1|
|eee|ee|
|esOO|
|Ca|MIPI D-PHY Support|Yes|Yes|Yes|Yes|Yes|Yes|
|Multi Time Programmable|MachXO3L-|MachXO3L-|MachXO3L-|
|MachXO3L-640|MachXO3L-1300|MachXO3L-2100|
|NVCM|4300|6900|9400|
|ee|OO|
|MachXO3LF-|MachXO3LF-|MachXO3LF-|MachXO3LF-|MachXO3LF-|
|Programmable Flash|MachXO3LF-640|
|1300|2100|4300|6900|9400|
|ee|es|es|es|ee|
|MachXO3LF-|MachXO3LF-|MachXO3LF-|
|Automotive Qualified|—|—|—|
|1300|2100|4300|
|ee|e|s|sseee|es|
|Packages|I/O|
|es|
|36-ball WLCSP|[1]|
|28|
|(2.5 mm x 2.5 mm, 0.4 mm)|
|a|ee ee|ee|ee|
|49-ball WLCSP|[1]|
|38|
|(3.2 mm x 3.2 mm, 0.4 mm)|
|ee|81-ball WLCSP|[1]|ee|ee|
|63|
|(3.8 mm x 3.8 mm, 0.4 mm)|
|ee|121-ball csfBGA|[1]|ee|ee ee|
|100|100|100|100|
|||(6 mm x 6 mm, 0.5 mm) 256-ball csfBGA|[1]|||
|206|206|206|206|206|
||,|(9 mm x 9 mm, 0.5 mm)|
|324-ball csfBGA|[1]|
|268|268|281|
|||(256-ball caBGA 10 mm x 10 mm, 0.5 mm)|ee|||
|206|[2, 7]|206|[2, 7]|206|[2, 7]|206|[2]|206|[3]|
|ee|(14 mm x 14 mm, 0.8 mm)|
|324-ball caBGA|[2]|
|279|[7]|279|[7]|279|
|(15 mm x 15 mm, 0.8 mm)|
|ee|400-ball caBGA|eee|335|[2]|335|[2]|335|[3]|
|>|(17 mm x 17 mm, 0.8 mm)|
|484-ball caBGA|
|384|[3]|
|es|(19 mm x 19 mm, 0.8 mm)|es|

**----- End of picture text -----**<br>


**Notes:** 

1. Package is only available for E=1.2 V devices. 

2. Package is only available for C=2.5 V/3.3 V devices in 6900 LUT and smaller densities. 

3. Package is available for both E=1.2 V and C=2.5 V/3.3 V devices. 

4. Refer to Power and Thermal Estimation and Management for MachXO3 Devices (FPGA-TN-02059) for determination of safe ambient operating conditions. 

5. High Performance with regulator – VCC = 2.5 V/3.3 V. 

6. High Performance without regulator – VCC = 1.2 V. 

7. Package is available for automotive devices. 

© 2014-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02032-2.8 

11 

**MachXO3 Family Data Sheet** 

## **2. Architecture** 

## **2.1. Architecture Overview** 

The MachXO3L/LF family architecture contains an array of logic blocks surrounded by Programmable I/O (PIO). All logic density devices in this family have sysCLOCK™ PLLs and blocks of sysMEM Embedded Block RAM (EBRs). Figure 2.1 and Figure 2.2 show the block diagrams of the various family members. 

**==> picture [464 x 167] intentionally omitted <==**

**----- Start of picture text -----**<br>
Configuration UFM/User Key<br>Flash 1/2<br>+ fC—SSS Embedded Function Block (EFB)<br>sysCLOCK PLL tt _ DoOoooooooooo Embedded Security Block<br>OOOR00000000000 sboo000000R0000oo<br>OOOOCCOSRORR000 oooooooooooooo<br>OOORCC00C000000 soooooono0o00oo<br>OOOG00000000000 sao00000000n0oo<br>OOOGOCR0C000000 Sooo000000R0on0on<br>OOOG00000000000 sao0000000000oo<br>OOOGOCORCORR0oo Soooooooooooooo<br>sysMEM Embedded<br>PIOs Arranged into  Block RAM (EBR)<br>sysI/O Banks<br>OOOOCCOSCOR00R0 Seooooooecooocoo<br>OOOGO0000000000 sao000000R0000on<br>OOOGOCOSCOR0000 Sooooooooooo0oo Programmable Function Units<br>OOORC000C000000 Sooonocooo0o00Rn with Distributed RAM (PFUs)<br>**----- End of picture text -----**<br>


**Figure 2.1. Top View of the MachXO3L/LF-1300 Device** 

## **Notes:** 

- MachXO3L/LF-640 is similar to MachXO3L/LF-1300. MachXO3L/LF-640 has a lower LUT count. 

- MachXO3L devices have NVCM, MachXO3LF devices have Flash. 

© 2014-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

12 

FPGA-DS-02032-2.8 

**MachXO3 Family Data Sheet** 

**==> picture [468 x 170] intentionally omitted <==**

**----- Start of picture text -----**<br>
Embedded<br>Function Block (EFB)<br>oS Bani SEGESRRERaR NVCM1/UFM<br>sysCLOCK PLL EERE SRR<br>BEGESSEE0 SSeS eeee008<br>| eees<br>Configuration  ee<br>NVCM0/Flash BHRSSS SRSSSSSSSSSeeeH<br>BHRERREESSSESSSS SRSSSSSSSSSSSeH<br>GBORSSSSGSSERR0000 SSSGSe000e020000020<br>GBHRESSSESSSRRE000 SSSSSeeC0e0e000e020 sysMEM Embedded<br>Block (EBR)<br>PIOs Arranged Into<br>sysIO Banks<br>EEREeees PRS eeeeeeee<br>BHRESSEESSSESSRS SRSSSSSeSSeeeeaR<br>EERE PRs Programmable Function Units<br>EERE PRs with Distributed RAM (PFUs)<br>**----- End of picture text -----**<br>


Notes: 

MachXO3L/LF-1300, MachXO3L/LF-2100, MachXO3L/LF-6900 and MachXO3L/LF-9400 are similar to MachXO3L/LF-4300. MachXO3L/LF-1300 has a lower LUT count, one PLL, and seven EBR blocks. MachXO3L/LF-2100 has a lower LUT count, one PLL, and eight EBR blocks. MachXO3L/LF-6900 has a higher LUT count, two PLLs, and 26 EBR blocks. MachXO3L/LF-9400 has a higher LUT count, two PLLs, and 48 E blocks. MachXO3L devices have NVCM, MachXO3LF devices have Flash. 

## **Figure 2.2. Top View of the MachXO3L/LF-4300 Device** 

The logic blocks, Programmable Functional Unit (PFU) and sysMEM EBR blocks, are arranged in a two-dimensional grid with rows and columns. Each row has either the logic blocks or the EBR blocks. The PIO cells are located at the periphery of the device, arranged in banks. The PFU contains the building blocks for logic, arithmetic, RAM, ROM, and register functions. The PIOs utilize a flexible I/O buffer referred to as a sysI/O buffer that supports operation with a variety of interface standards. The blocks are connected with many vertical and horizontal routing channel resources. The place and route software tool automatically allocates these routing resources. 

In the MachXO3L/LF family, the number of sysI/O banks varies by device. There are different types of I/O buffers on the different banks. Refer to the details in later sections of this document. The sysMEM EBRs are large, dedicated fast memory blocks. These blocks can be configured as RAM, ROM or FIFO. FIFO support includes dedicated FIFO pointer and flag “hard” control logic to minimize LUT usage. 

The MachXO3L/LF registers in PFU and sysI/O can be configured to be SET or RESET. After power up and device is configured, the device enters into user mode with these registers SET/RESET according to the configuration set-ting, allowing device entering to a known state for predictable system function. 

The MachXO3L/LF architecture also provides up to two sysCLOCK Phase Locked Loop (PLL) blocks. These blocks are located at the ends of the on-chip NVCM/Flash block. The PLLs have multiply, divide, and phase shifting capabilities that are used to manage the frequency and phase relationships of the clocks. 

MachXO3L/LF devices provide commonly used hardened functions such as SPI controller, I[2] C controller and timer/ counter. 

MachXO3LF devices also provide User Flash Memory (UFM). These hardened functions and the UFM interface to the core logic and routing through a WISHBONE interface. The UFM can also be accessed through the SPI, I[2] C and JTAG ports. 

Every device in the family has a JTAG port that supports programming and configuration of the device as well as access to the user logic. The MachXO3L/LF devices are available for operation from 3.3 V, 2.5 V and 1.2 V power supplies, providing easy integration into the overall system. 

© 2014-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02032-2.8 

13 

**MachXO3 Family Data Sheet** 

## **2.2. PFU Blocks** 

The core of the MachXO3L/LF device consists of PFU blocks, which can be programmed to perform logic, arithmetic, distributed RAM and distributed ROM functions. Each PFU block consists of four interconnected slices numbered 0 to 3 as shown in Figure 2.3. Each slice contains two LUTs and two registers. There are 53 inputs and 25 outputs associated with each PFU block. 

**==> picture [439 x 219] intentionally omitted <==**

**----- Start of picture text -----**<br>
From<br>Routing<br>STL<br>LUT4 & LUT4 & LUT4 & LUT4 & LUT4 & LUT4 & LUT4 & LUT4 &<br>FCIN CARRY CARRY CARRY CARRY CARRY CARRY CARRY CARRY FCO<br>Slice 0 Slice 1 Slice 2 Slice 3<br>D D D D D D D D<br>FF/ FF/ FF/ FF/ FF/ FF/ FF/ FF/<br>Latch Latch Latch Latch Latch Latch Latch Latch<br>To<br>Routing<br>Jk<br>**----- End of picture text -----**<br>


**Figure 2.3. PFU Block Diagram** 

## **2.2.1. Slices** 

Slices 0-3 contain two LUT4s feeding two registers. Slices 0-2 can be configured as distributed memory. Table 2.1 shows the capability of the slices in PFU blocks along with the operation modes they enable. In addition, each PFU contains logic that allows the LUTs to be combined to perform functions such as LUT5, LUT6, LUT7 and LUT8. The control logic performs set/reset functions (programmable as synchronous/ asynchronous), clock select, chip select and wider RAM/ROM functions. 

**Table 2.1. Resources and Modes Available per Slice** 

|**Slice**|**PFU Block**|**PFU Block**|
|---|---|---|
||**Resources**|**Modes**|
|Slice 0|2 LUT4s and 2 Registers|Logic, Ripple, RAM, ROM|
|Slice 1|2 LUT4s and 2 Registers|Logic, Ripple, RAM, ROM|
|Slice 2|2 LUT4s and 2 Registers|Logic, Ripple, RAM, ROM|
|Slice 3|2 LUT4s and 2 Registers|Logic, Ripple, ROM|



Figure 2.4 shows an overview of the internal logic of the slice. The registers in the slice can be configured for positive/ negative and edge triggered or level sensitive clocks. All slices have 15 inputs from routing and one from the carrychain (from the adjacent slice or PFU). There are seven outputs: six for routing and one to carry-chain (to the adjacent PFU). Table 2.2 lists the signals associated with Slices 0-3. 

© 2014-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02032-2.8 

14 

**MachXO3 Family Data Sheet** 

**Figure 2.4. Slice Diagram** 

**Table 2.2. Slice Signal Descriptions** 

|**Function**|**Type **|**Signal Names**|**Description**|
|---|---|---|---|
|Input|Data signal|A0, B0, C0, D0|Inputs to LUT4|
|Input|Data signal|A1, B1, C1, D1|Inputs to LUT4|
|Input|Multi-purpose|M0/M1|Multi-purpose input|
|Input|Control signal|CE|Clock enable|
|Input|Control signal|LSR|Local set/reset|
|Input|Control signal|CLK|System clock|
|Input|Inter-PFU signal|FCIN|Fast carryin1|
|Output|Data signals|F0, F1|LUT4 output register bypass signals|
|Output|Data signals|Q0, Q1|Register outputs|
|Output|Data signals|OFX0|Output of a LUT5 MUX|
|Output|Data signals|OFX1|Output of a LUT6, LUT7, LUT82MUX dependingon the slice|
|Output|Inter-PFU signal|FCO|Fast carryout1|



**Notes** : 

1. See Figure 2.3 for connection details. 

2. Requires two PFUs. 

© 2014-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02032-2.8 

15 

**MachXO3 Family Data Sheet** 

## **2.2.2. Modes of Operation** 

Each slice has up to four potential modes of operation: Logic, Ripple, RAM and ROM. 

## **2.2.2.1. Logic Mode** 

In this mode, the LUTs in each slice are configured as 4-input combinatorial lookup tables. A LUT4 can have 16 possible input combinations. Any four input logic functions can be generated by programming this lookup table. Since there are two LUT4s per slice, a LUT5 can be constructed within one slice. Larger look-up tables such as LUT6, LUT7 and LUT8 can be constructed by concatenating other slices. Note LUT8 requires more than four slices. 

## **2.2.2.2. Ripple Mode** 

Ripple mode supports the efficient implementation of small arithmetic functions. In Ripple mode, the following functions can be implemented by each slice: 

- Addition 2-bit 

- Subtraction 2-bit 

- Add/subtract 2-bit using dynamic control 

- Up counter 2-bit 

- Down counter 2-bit 

- Up/down counter with asynchronous clear 

- Up/down counter with preload (sync) 

- Ripple mode multiplier building block 

- Multiplier support 

- Comparator functions of A and B inputs 

- A greater-than-or-equal-to B 

- A not-equal-to B 

- A less-than-or-equal-to B 

Ripple mode includes an optional configuration that performs arithmetic using fast carry chain methods. In this configuration (also referred to as CCU2 mode) two additional signals, Carry Generate and Carry Propagate, are generated on a per-slice basis to allow fast arithmetic functions to be constructed by concatenating slices. 

## **2.2.3. RAM Mode** 

In this mode, a 16x4-bit distributed single port RAM (SPR) can be constructed by using each LUT block in Slice 0 and Slice 1 as a 16x1-bit memory. Slice 2 is used to provide memory address and control signals. 

MachXO3L/LF devices support distributed memory initialization. 

The Lattice design tools support the creation of a variety of different size memories. Where appropriate, the software will construct these using distributed memory primitives that represent the capabilities of the PFU. Table 2.3 shows the number of slices required to implement different distributed RAM primitives. For more information about using RAM in MachXO3L/LF devices, please see Memory Usage Guide for MachXO3 Devices (TN1290). 

**Table 2.3. Number of Slices Required For Implementing Distributed RAM** 

||**SPR 16 x 4**|**SPR 16 x 4**|**SPR 16 x 4**|**SPR 16 x 4**|**PDPR 16 x 4**|**PDPR 16 x 4**|**PDPR 16 x 4**|**PDPR 16 x 4**|
|---|---|---|---|---|---|---|---|---|
|Number of slices|3||||3||||



**Note** : SPR = Single Pot RAM, PDPR = Pseudo Dual Port RAM 

## **2.2.4. ROM Mode** 

ROM mode uses the LUT logic; hence, slices 0-3 can be used in ROM mode. Preloading is accomplished through the programming interface during PFU configuration. 

For more information on the RAM and ROM modes, please refer to Memory Usage Guide for MachXO3 Devices (FPGATN-02060). 

© 2014-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02032-2.8 

16 

**MachXO3 Family Data Sheet** 

## **2.3. Routing** 

There are many resources provided in the MachXO3L/LF devices to route signals individually or as buses with related control signals. The routing resources consist of switching circuitry, buffers and metal interconnect (routing) segments. 

The inter-PFU connections are made with three different types of routing resources: x1 (spans two PFUs), x2 (spans three PFUs) and x6 (spans seven PFUs). The x1, x2, and x6 connections provide fast and efficient connections in the horizontal and vertical directions. 

The design tools take the output of the synthesis tool and places and routes the design. Generally, the place and route tool is completely automatic, although an interactive routing editor is available to optimize the design. 

## **2.4. Clock/Control Distribution Network** 

Each MachXO3L/LF device has eight clock inputs (PCLK [T, C] [Banknum]_[2..0]) – three pins on the left side, two pins each on the bottom and top sides and one pin on the right side. These clock inputs drive the clock nets. These eight inputs can be differential or single-ended and may be used as general purpose I/O if they are not used to drive the clock nets. When using a single ended clock input, only the PCLKT input can drive the clock tree directly. 

The MachXO3L/LF architecture has three types of clocking resources: edge clocks, primary clocks and secondary high fanout nets. MachXO3L/LF devices have two edge clocks each on the top and bottom edges. Edge clocks are used to clock I/O registers and have low injection time and skew. Edge clock inputs are from PLL outputs, primary clock pads, edge clock bridge outputs and CIB sources. 

The eight primary clock lines in the primary clock network drive throughout the entire device and can provide clocks for all resources within the device including PFUs, EBRs and PICs. In addition to the primary clock signals, MachXO3L/LF devices also have eight secondary high fanout signals which can be used for global control signals, such as clock enables, synchronous or asynchronous clears, presets, output enables, etc. Internal logic can drive the global clock network for internally-generated global clocks and control signals. 

The maximum frequency for the primary clock network is shown in the MachXO3L/LF External Switching Characteristics table. 

Primary clock signals for the MachXO3L/LF-1300 and larger devices are generated from eight 27:1 muxes The available clock sources include eight I/O sources, 11 routing inputs, eight clock divider inputs and up to eight sysCLOCK PLL outputs. 

© 2014-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02032-2.8 

17 

**MachXO3 Family Data Sheet** 

**==> picture [338 x 424] intentionally omitted <==**

**----- Start of picture text -----**<br>
Up to 8 8 11 8<br>eeee Dynamic<br>ee 27:1 Clock Primary Clock 0<br>Enable<br>a<br>a Dynamic<br>ee 27:1 Clock Primary Clock 1<br>Enable<br>is<br>ee Dynamic<br>ee 27:1 Clock Primary Clock 2<br>Enable<br>aPo<br>ee 27:1 DynamicClock Primary Clock 3<br>Enable<br>in<br>a<br>es 27:1 DynamicClock Primary Clock 4<br>Enable<br>a<br>re 27:1 DynamicClock Primary Clock 5<br>Enable<br>o £<br>eeee ee<br>ee 27:1<br>Dynamic<br>Clock<br>Enable Primary Clock 6<br>ee 27:1 Clock<br>Switch<br>a—<br>es 27:1<br>Dynamic<br>Clock<br>Enable<br>ee eeie ,  a Primary Clock<br>ee 27:1 Clock 7<br>Yd<br>Switch<br>**----- End of picture text -----**<br>


**Figure 2.5. Primary Clocks for MachXO3L/F Devices** 

Eight secondary high fanout nets are generated from eight 8:1 muxes as shown in Figure 2.6. One of the eight inputs to the secondary high fanout net input mux comes from dual function clock pins and the remaining seven come from internal routing. The maximum frequency for the secondary clock network is shown in MachXO3L/LF External Switching Characteristics table. 

© 2014-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

18 

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**==> picture [246 x 396] intentionally omitted <==**

**----- Start of picture text -----**<br>
1 7<br>Secondary High<br>8:1<br>Fanout Net 0<br>Secondary High<br>8:1<br>Fanout Net 1<br>Secondary High<br>8:1<br>Fanout Net 2<br>Secondary High<br>8:1<br>Fanout Net 3<br>Secondary High<br>8:1<br>Fanout Net 4<br>Secondary High<br>8:1<br>Fanout Net 5<br>Secondary High<br>8:1<br>Fanout Net 6<br>8:1 Secondary High<br>Fanout Net 7<br>Clock Pads Routing<br>**----- End of picture text -----**<br>


**Figure 2.6. Secondary High Fanout Nets for MachXO3L/F Devices** 

## **2.4.1. sysCLOCK Phase Locked Loops (PLLs)** 

The sysCLOCK PLLs provide the ability to synthesize clock frequencies. All MachXO3L/LF devices have one or more sysCLOCK PLL. CLKI is the reference frequency input to the PLL and its source can come from an external I/O pin or from internal routing. CLKFB is the feedback signal to the PLL which can come from internal routing or an external I/O pin. The feedback divider is used to multiply the reference frequency and thus synthesize a higher frequency clock output. 

The MachXO3L/LF sysCLOCK PLLs support high resolution (16-bit) fractional-N synthesis. Fractional-N frequency synthesis allows the user to generate an output clock which is a non-integer multiple of the input frequency. For more information about using the PLL with Fractional-N synthesis, please see MachXO3 sysCLOCK PLL Design and Usage Guide (FPGA-TN-02058). 

Each output has its own output divider, thus allowing the PLL to generate different frequencies for each output. The output dividers can have a value from 1 to 128. The output dividers may also be cascaded together to generate low frequency clocks. The CLKOP, CLKOS, CLKOS2, and CLKOS3 outputs can all be used to drive the MachXO3L/LF clock distribution network directly or general purpose routing resources can be used. 

The LOCK signal is asserted when the PLL determines it has achieved lock and de-asserted if a loss of lock is detected. A block diagram of the PLL is shown in Figure 2.7. 

© 2014-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02032-2.8 

19 

**MachXO3 Family Data Sheet** 

The setup and hold times of the device can be improved by programming a phase shift into the CLKOS, CLKOS2, and CLKOS3 output clocks which will advance or delay the output clock with reference to the CLKOP output clock. 

This phase shift can be either programmed during configuration or can be adjusted dynamically. In dynamic mode, the PLL may lose lock after a phase adjustment on the output used as the feedback source and not relock until the tLOCK parameter has been satisfied. 

The MachXO3L/LF also has a feature that allows the user to select between two different reference clock sources dynamically. This feature is implemented using the PLLREFCS primitive. The timing parameters for the PLL are shown in the sysCLOCK PLL Timing table. 

The MachXO3L/LF PLL contains a WISHBONE port feature that allows the PLL settings, including divider values, to be dynamically changed from the user logic. When using this feature the EFB block must also be instantiated in the design to allow access to the WISHBONE ports. Similar to the dynamic phase adjustment, when PLL settings are updated through the WISHBONE port the PLL may lose lock and not relock until the tLOCK parameter has been satisfied. The timing parameters for the PLL are shown in the sysCLOCK PLL Timing table. 

For more details on the PLL and the WISHBONE interface, see MachXO3 sysCLOCK PLL Design and Usage Guide (FPGATN-02058). 

**==> picture [426 x 282] intentionally omitted <==**

**----- Start of picture text -----**<br>
DPHSRC<br>PHASESEL[1:0]<br>PHASEDIR Dynamic<br>Phase<br>PHASESTEP Adjust<br>CLKOP  Phase  CLKOP<br>A2 ClkEn<br>STDBY A0 (1 - 128)Divider Edge TrimAdjust/  Mux Synch<br>REFCLK<br>CLKOS<br>CLKI REFCLK Divider Phase detector, B0 (1 - 128)CLKOS Divider Edge TrimAdjust/ Phase  MuxB2 SynchClkEn<br>M (1 - 40) VCO, and<br> loop filter.<br>CLKFB FBKSEL CLKOS2<br>CLKOS2<br>Phase  C2 ClkEn<br>FBKCLK  Fractional-N C0 Divider Adjust Mux Synch<br>Divider Synthesizer (1 - 128)<br>N (1 - 40)<br>CLKOS3<br>CLKOS3<br>D1 Phase  D2 ClkEn<br>D0 Divider<br>Mux Adjust Mux Synch<br>Internal Feedback (1 - 128)<br>CLKOP, CLKOS, CLKOS2, CLKOS3<br>LOCK<br>4 Lock<br>RST, RESETM, RESETC, RESETD Detect<br>ENCLKOP, ENCLKOS, ENCLKOS2, ENCLKOS3<br>PLLDATO[7:0] , PLLACK<br>PLLCLK, PLLRST, PLLSTB, PLLWE, PLLDATI[7:0], PLLADDR[4:0]<br>**----- End of picture text -----**<br>


**Figure 2.7. PLL Diagram** 

© 2014-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

20 

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**MachXO3 Family Data Sheet** 

Table 2.4 provides signal descriptions of the PLL block. 

**Table 2.4. PLL Signal Descriptions** 

|**Port Name**<br>~~eG~~|**I/O **<br>~~eG~~|**Description**<br>~~eG~~|
|---|---|---|
|CLKI<br>~~eG~~<br>~~eG~~<br>~~ee~~|I<br>~~eG~~<br>~~eG~~<br>~~eG~~|Input clock to PLL<br>~~eG~~<br>~~eG~~<br>~~eG~~|
|CLKFB<br>~~eG~~<br>~~ee~~|I<br>~~eG~~<br>~~eG~~|Feedback clock<br>~~eG~~<br>~~eG~~|
|PHASESEL[1:0]<br>~~ee~~<br>~~a~~|I<br>~~eG~~|Select which output is affected byDynamic Phase adjustmentports<br>~~eG~~|
|PHASEDIR<br>~~eG~~|I<br>~~eG~~|Dynamic Phase adjustment direction<br>~~eG~~|
|PHASESTEP<br>~~eG~~<br>~~eG~~|I<br>~~eG~~<br>~~eG~~|Dynamic Phase step –toggle shifts VCOphase adjust byone step.<br>~~eG~~<br>~~eG~~|
|CLKOP<br>~~eG~~<br>~~eG~~|O<br>~~eG~~<br>~~eG~~|PrimaryPLL output clock(withphase shift adjustment)<br>~~eG~~<br>~~eG~~|
|CLKOS<br>~~eG~~<br>~~eG~~<br>~~ee~~|O<br>~~eG~~<br>~~eG~~|SecondaryPLL output clock(withphase shift adjust)<br>~~eG~~<br>~~eG~~|
|CLKOS2<br>~~eG~~<br>~~ee~~|O<br>~~eG~~|SecondaryPLL output clock2(withphase shift adjust)<br>~~eG~~|
|CLKOS3<br>~~ee~~|O|SecondaryPLL output clock3(withphrase shift adjust)|
|LOCK<br>~~a~~|O|PLL LOCK, asynchronous signal. Active high indicates PLL is locked to input and<br>feedback signals.|
|DPHSRC<br>~~a~~<br>~~a~~|O|Dynamic Phase source– ports or WISHBONE is active|
|STDBY<br>~~eG~~|I<br>~~eG~~|Standbysignal topower down the PLL<br>~~eG~~|
|RST<br>~~eG~~<br>~~eG~~|I<br>~~eG~~<br>~~eG~~|PLL reset without resettingthe M-driver. Active high reset.<br>~~eG~~<br>~~eG~~|
|RESETM<br>~~eG~~<br>~~eG~~|I<br>~~eG~~<br>~~eG~~|PLL rest–includes resettingthe M-divider. Active high reset.<br>~~eG~~<br>~~eG~~|
|RESETC<br>~~eG~~<br>~~eG~~<br>~~ee~~|I<br>~~eG~~<br>~~eG~~|Reset for CLKOS2 output divider only. Active high reset.<br>~~eG~~<br>~~eG~~|
|RESETD<br>~~eG~~<br>~~ee~~|I<br>~~eG~~|Reset for CLKOS3 output divider only. Active high reset.<br>~~eG~~|
|ENCLKOP<br>~~ee~~<br>~~a~~<br>~~**e**e~~|I|Enable PLL output CLKOP|
|ENCLKOS<br>~~**e**e~~|I|Enable PLL output CLKOS whenport is active|
|ENCLKOS2<br>~~**e**e~~|I|Enable PLL output CLKOS2 whenport is active<br>~~G~~|
|ENCLKOS3<br>~~eG~~|I<br>~~eG~~|Enable PLL output CLKOS3 whenport is active<br>~~G~~<br>~~eG~~|
|PLLCLK<br>~~eG~~<br>~~eG~~|I<br>~~eG~~<br>~~eG~~|PLL data bus clock input signal<br>~~eG~~<br>~~eG~~|
|PLLRST<br>~~eG~~<br>~~a~~|I<br>~~eG~~|PLL data bus reset. This resets onlythe data bus not anyregister values.<br>~~eG~~|
|PLLSTB<br>~~a~~<br>~~a~~|I|PLL data bus strobe signal|
|PLLWE<br>~~a~~<br>~~eG~~|I<br>~~eG~~|PLL data bus write enable signal<br>~~eG~~|
|PLLADDR[4:0]<br>~~a~~|I|PLL data bus address|
|PLLDATI[7:0]<br>~~eG~~<br>~~ee~~|I<br>~~eG~~|PLL data bus data input<br>~~eG~~|
|PLLDATO[7:0]<br>~~eG~~<br>~~ee~~<br>~~ee~~|O<br>~~eG~~<br>~~eG~~|PLL data bus data output<br>~~eG~~<br>~~eG~~|
|PLLACK<br>~~ee~~<br>~~ee~~|O<br>~~eG~~|PLL data bus acknowledge signal<br>~~eG~~|



© 2014-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02032-2.8 

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**MachXO3 Family Data Sheet** 

## **2.5. sysMEM Embedded Block RAM Memory** 

The MachXO3L/LF devices contain sysMEM Embedded Block RAMs (EBRs). The EBR consists of a 9-Kbit RAM, with dedicated input and output registers. This memory can be used for a wide variety of purposes including data buffering, PROM for the soft processor and FIFO. 

## **2.5.1. sysMEM Memory Block** 

The sysMEM block can implement single port, dual port, pseudo dual port, or FIFO memories. Each block can be used in a variety of depths and widths as shown in Table 2.5. 

**Table 2.5. sysMEM Block Configurations** 

|**Memory Mode**|**Configurations**|
|---|---|
|Single Port|8,192 x 1<br>4,096 x 2<br>2,048 x 4<br>1,024 x 9|
|True Dual Port|8,192 x 1<br>4,096 x 2<br>2,048 x 4<br>1,024 x 9|
|Pseudo Dual Port|8,192 x 1<br>4,096 x 2<br>2,048 x 4<br>1,024 x 9<br>512 x 18|
|FIFO|8,192 x 1<br>4,096 x 2<br>2,048 x 4<br>1,024 x 9<br>512 x 18|



## **2.5.2. Bus Size Matching** 

All of the multi-port memory modes support different widths on each of the ports. The RAM bits are mapped LSB word 0 to MSB word 0, LSB word 1 to MSB word 1, and so on. Although the word size and number of words for each port varies, this mapping scheme applies to each port. 

## **2.5.3. RAM Initialization and ROM Operation** 

If desired, the contents of the RAM can be pre-loaded during device configuration. EBR initialization data can be loaded from the NVCM or Configuration Flash. 

MachXO3LF EBR initialization data can also be loaded from the UFM. To maximize the number of UFM bits, initialize the EBRs used in your design to an all-zero pattern. Initializing to an all-zero pattern does not use up UFM bits. MachXO3LF devices have been designed such that multiple EBRs share the same initialization memory space if they are initialized to the same pattern. 

By preloading the RAM block during the chip configuration cycle and disabling the write controls, the sysMEM block can also be utilized as a ROM. 

## **2.5.4. Memory Cascading** 

Larger and deeper blocks of RAM can be created using EBR sysMEM Blocks. Typically, the Lattice design tools cascade memory transparently, based on specific design inputs. 

© 2014-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

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**MachXO3 Family Data Sheet** 

## **2.5.5. Single, Dual, Pseudo-Dual Port and FIFO Modes** 

Figure 2.8 shows the five basic memory configurations and their input/output names. In all the sysMEM RAM modes, the input data and addresses for the ports are registered at the input of the memory array. The output data of the memory is optionally registered at the memory array output. 

**==> picture [464 x 295] intentionally omitted <==**

**----- Start of picture text -----**<br>
AD[12:0] DIA[8:0] DI[8:0]<br>DI[8:0] ADW[8:0]<br>ADA[12:0] ADB[12:0] DI[17:0] ADR[12:0]<br>CLK CLKA CLKB BE[1:0] CLKR<br>CE CEA CEB CLKW<br>OCE CER<br>EBR DO[8:0] RSTA EBR RSTB CEW EBR<br>RST WEA WEB RST DO[17:0]<br>WE CSA[2:0] CSB[2:0] OCER<br>CS[2:0] OCEA OCEB CSW[2:0] CSR[2:0]<br>DOA[8:0] DOB[8:0]<br>int<br>Single-Port RAM True Dual Port RAM Pseudo Dual Port RAM<br>AFF AD[12:0]<br>DI[17:0] FF<br>AEF<br>CLKW EF CLK<br>WE DO[17:0] CE<br>RST EBR ORE OCE EBR DO[17:0]<br>CLKR<br>FULLI RE RST<br>CSW[1:0] EMPTYI<br>CSR[1:0] CS[2:0]<br>RPRST<br>ul<br>FIFO RAM ROM<br>**----- End of picture text -----**<br>


**Figure 2.8. sysMEM Memory Primitives Table 2.6. EBR Signal Descriptions Port Name Description Active State** CLK Clock Rising Clock Edge CE Clock Enable Active High OCE1 Output Clock Enable Active High RST Reset Active High BE1 Byte Enable Active High WE Write Enable Active High AD Address Bus — DI Data In — DO Data Out — CS Chip Select Active High AFF FIFO RAM Almost Full Flag — FF FIFO RAM Full Flag — ~~===~~ AEF FIFO RAM Almost Empty Flag — © 2014-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02032-2.8 

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**MachXO3 Family Data Sheet** 

|**Port Name**|**Description**|**Active State**|
|---|---|---|
|EF|FIFO RAM EmptyFlag|—|
|RPRST|FIFO RAM Read Pointer Reset|—|



## **Notes:** 

1. Optional signals. 

2. For dual port EBR primitives a trailing ‘A’ or ‘B’ in the signal name specifies the EBR port A or port B respectively. 

3. For FIFO RAM mode primitive, a trailing ‘R’ or ‘W’ in the signal name specifies the FIFO read port or write port respectively. 

4. For FIFO RAM mode primitive FULLI has the same function as CSW(2) and EMPTYI has the same function as CSR(2). 

5. In FIFO mode, CLKW is the write port clock, CSW is the write port chip select, CLKR is the read port clock, CSR is the read port chip select, ORE is the output read enable. 

The EBR memory supports three forms of write behavior for single or dual port operation: 

- Normal – Data on the output appears only during the read cycle. During a write cycle, the data (at the current address) does not appear on the output. This mode is supported for all data widths. 

- Write Through – A copy of the input data appears at the output of the same port. This mode is supported for all data widths. 

- Read-Before-Write – When new data is being written, the old contents of the address appears at the output. 

## **2.5.6. FIFO Configuration** 

The FIFO has a write port with data-in, CEW, WE and CLKW signals. There is a separate read port with data-out, RCE, RE and CLKR signals. The FIFO internally generates Almost Full, Full, Almost Empty and Empty Flags. The Full and Almost Full flags are registered with CLKW. The Empty and Almost Empty flags are registered with CLKR. Table 2.7 shows the range of programming values for these flags. 

**Table 2.7. Programmable FIFO Flag Ranges** 

|**Flag Name**|**Programming Range **|
|---|---|
|Full(FF)|1 to max(upto 2N-1)|
|Almost Full(AF)|1 to Full-1|
|Almost Empty (AE)|1 to Full-1|
|Empty (EF)|0|



N = Address bit width. 

The FIFO state machine supports two types of reset signals: RST and RPRST. The RST signal is a global reset that clears the contents of the FIFO by resetting the read/write pointer and puts the FIFO flags in their initial reset state. The RPRST signal is used to reset the read pointer. The purpose of this reset is to retransmit the data that is in the FIFO. In these applications it is important to keep careful track of when a packet is written into or read from the FIFO. 

## **2.5.7. Memory Core Reset** 

The memory core contains data output latches for ports A and B. These are simple latches that can be reset synchronously or asynchronously. RSTA and RSTB are local signals, which reset the output latches associated with port A and port B respectively. The Global Reset (GSRN) signal resets both ports. The output data latches and associated resets for both ports are as shown in Figure 2.9. 

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**MachXO3 Family Data Sheet** 

**==> picture [45 x 7] intentionally omitted <==**

**----- Start of picture text -----**<br>
Memory Core<br>**----- End of picture text -----**<br>


**Figure 2.9. Memory Core Reset** 

For further information on the sysMEM EBR block, please refer to Memory Usage Guide for MachXO3 Devices (FPGATN-02060). 

## **2.5.8. EBR Asynchronous Reset** 

EBR asynchronous reset or GSR (if used) can only be applied if all clock enables are low for a clock cycle before the reset is applied and released a clock cycle after the reset is released, as shown in Figure 2.10. The GSR input to the EBR is always asynchronous. 

**==> picture [25 x 148] intentionally omitted <==**

**----- Start of picture text -----**<br>
Reset<br>Clock<br>Clock<br>Enable<br>**----- End of picture text -----**<br>


**Figure 2.10. EBR Asynchronous Reset (Including GSR) Timing Diagram** 

If all clock enables remain enabled, the EBR asynchronous reset or GSR may only be applied and released after the EBR read and write clock inputs are in a steady state condition for a minimum of 1/fMAX (EBR clock). The reset release must adhere to the EBR synchronous reset setup time before the next active read or write clock edge. 

If an EBR is pre-loaded during configuration, the GSR input must be disabled or the release of the GSR during device wake up must occur before the release of the device I/Os becoming active. 

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FPGA-DS-02032-2.8 

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**MachXO3 Family Data Sheet** 

These instructions apply to all EBR RAM, ROM and FIFO implementations. For the EBR FIFO mode, the GSR signal is always enabled and the WE and RE signals act like the clock enable signals in Figure 2.10. The reset timing rules apply to the RPReset input versus the RE input and the RST input versus the WE and RE inputs. Both RST and RPReset are always asynchronous EBR inputs. For more details refer to Memory Usage Guide for MachXO3 Devices (FPGA-TN02060). 

Note that there are no reset restrictions if the EBR synchronous reset is used and the EBR GSR input is disabled. 

## **2.6. Programmable I/O Cells (PIC)** 

The programmable logic associated with an I/O is called a PIO. The individual PIO are connected to their respective sysI/O buffers and pads. On the MachXO3L/LF devices, the PIO cells are assembled into groups of four PIO cells called a Programmable I/O Cell or PIC. The PICs are placed on all four sides of the device. 

On all the MachXO3L/LF devices, two adjacent PIOs can be combined to provide a complementary output driver pair. 

All PIO pairs can implement differential receivers. Half of the PIO pairs on the top edge of these devices can be configured as true LVDS transmit pairs. The PIO pairs on the bottom edge of these devices have on-chip differential termination and, in the MachXO3L/LF-9400 devices, also provide PCI support. 

© 2014-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

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**==> picture [19 x 7] intentionally omitted <==**

**----- Start of picture text -----**<br>
1 PIC<br>**----- End of picture text -----**<br>


**==> picture [366 x 518] intentionally omitted <==**

**----- Start of picture text -----**<br>
PIO A<br>Input Register<br>Block c<br>Output Register<br>Block and  Pin<br>Tristate Register  A<br>Block<br>PIO B<br>aE<br>Input Register<br>Block<br>Output Register<br>Block and  Pin<br>Tristate Register  B<br>1 Output  Block  <<br>Core Logic/  Input  Gearbox<br>Routing Gearbox te<br>PIO C<br>Input Register<br>Block<br>t o =.<br>Output Register<br>Block and  Pin<br>Tristate Register  C<br>Block<br>i | He<br>PIO D<br>| f me<br>Input Register<br>Block<br>Output Register<br>Block and  Pin<br>Tristate Register  D<br>Block<br>i | HEA<br>7 ALS Z<br>**----- End of picture text -----**<br>


**Figure 2.11. Group of Four Programmable I/O Cells** 

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FPGA-DS-02032-2.8 

27 

**MachXO3 Family Data Sheet** 

## **2.7. PIO** 

The PIO contains three blocks: an input register block, output register block and tri-state register block. These blocks contain registers for operating in a variety of modes along with the necessary clock and selection logic. 

**Table 2.8. PIO Signal List** 

|**Pin Name**|**I/O Type **|**Description**|
|---|---|---|
|CE|Input|Clock Enable|
|D|Input|Pin input from sysI/O buffer|
|INDD|Output|Register bypassed input|
|INCK|Output|Clock input|
|Q0|Output|DDRpositive edge input|
|Q1|Output|Registered input/DDR negative edge input|
|D0|Input|Output signal from the core(SDR and DDR)|
|D1|Input|Output signal from the core(DDR)|
|TD|Input|Tri-state signal from the core|
|Q|Output|Data output signals to sysI/O Buffer|
|TQ|Output|Tri-state output signals to sysI/O Buffer|
|SCLK|Input|System clock for input and output/tri-state blocks.|
|RST|Input|Local set reset signal|



## **2.7.1. Input Register Block** 

The input register blocks for the PIOs on all edges contain delay elements and registers that can be used to condition high-speed interface signals before they are passed to the device core. 

## **2.7.1.1. Left, Top, Bottom Edges** 

Input signals are fed from the sysI/O buffer to the input register block (as signal D). If desired, the input signal can bypass the register and delay elements and be used directly as a combinatorial signal (INDD), and a clock (INCK). If an input delay is desired, users can select a fixed delay. I/Os on the bottom edge also have a dynamic delay, DEL[4:0]. The delay, if selected, reduces input register hold time requirements when using a global clock. The input block allows two modes of operation. In single data rate (SDR) the data is registered with the system clock (SCLK) by one of the registers in the single data rate sync register block. In Generic DDR mode, two registers are used to sample the data on the positive and negative edges of the system clock (SCLK) signal, creating two data streams. 

## **2.7.2. Output Register Block** 

The output register block registers signals from the core of the device before they are passed to the sysI/O buffers. 

## **2.7.2.1. Left, Top, Bottom Edges** 

In SDR mode, D0 feeds one of the flip-flops that then feeds the output. The flip-flop can be configured as a D-type register or latch. 

In DDR generic mode, D0 and D1 inputs are fed into registers on the positive edge of the clock. At the next falling edge the registered D1 input is registered into the register Q1. A multiplexer running off the same clock is used to switch the mux between the outputs of registers Q0 and Q1 that will then feed the output. 

Figure 2.12 shows the output register block on the left, top and bottom edges. 

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**==> picture [436 x 221] intentionally omitted <==**

**----- Start of picture text -----**<br>
Q0  Q<br>| D0 D/L  Q |<br>|<br>| |<br>|<br>| |<br>|<br>Q1<br>| D1 D Q  D Q  |<br>|<br>| |<br>|<br>| |<br>| SCLK<br>|e e Output path<br>| fl<br>| TD<br>| D/L Q  TQ  |<br>|<br>| |<br>|<br>| Tri-state path  |<br>**----- End of picture text -----**<br>


**Figure 2.12. Output Register Block Diagram (PIO on the Left, Top and Bottom Edges)** 

## **2.7.3. Tri-state Register Block** 

The tri-state register block registers tri-state control signals from the core of the device before they are passed to the sysI/O buffers. The block contains a register for SDR operation. In SDR, TD input feeds one of the flip-flops that then feeds the output. 

## **2.8. Input Gearbox** 

Each PIC on the bottom edge has a built-in 1:8 input gearbox. Each of these input gearboxes may be programmed as a 1:7 de-serializer or as one IDDRX4 (1:8) gearbox or as two IDDRX2 (1:4) gearboxes. Table 2.9 shows the gearbox signals. 

**Table 2.9. Input Gearbox Signal List** 

|**Name**|**I/O Type **|**Description**|
|---|---|---|
|D|Input|High-speed data input afterprogrammable delayin PIO A input register block|
|ALIGNWD|Input|Data alignment signal from device core|
|SCLK|Input|Slow-speed system clock|
|ECLK[1:0]|Input|High-speed edge clock|
|RST|Input|Reset|
|Q[7:0]|Output|Low-speed data to device core:<br>Video RX(1:7): Q[6:0]<br>GDDRX4(1:8): Q[7:0]<br>GDDRX2(1:4)(IOL-A): Q4, Q5, Q6, Q7<br>GDDRX2(1:4)(IOL-C): Q0, Q1, Q2, Q3|



## **Note:** 

These gearboxes have three stage pipeline registers. The first stage registers sample the high-speed input data by the high-speed edge clock on its rising and falling edges. The second stage registers perform data alignment based on the control signals UPDATE and SEL0 from the control block. The third stage pipeline registers pass the data to the device core synchronized to the low-speed system clock. Figure 2.13 shows a block diagram of the input gearbox. 

© 2014-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02032-2.8 

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**MachXO3 Family Data Sheet** 

**==> picture [403 x 551] intentionally omitted <==**

**----- Start of picture text -----**<br>
Q0<br>Q21  D   Q Q0_  D   Q S0  D   Q T0<br>Q10  CE<br>Q43  Q21  S2  T2  Q2<br>LT D   Q D   Q ae D   Q<br>Q32  CE<br>Q65  Q43  S4  T4  Q4<br>D   Q D   Q D   Q<br>Q54  CE<br>cdn cdn<br>Q65  S6  T6  Q6<br>D   Q D   Q D   Q<br>Q_6  CE<br>D<br>Q_6  S7  T7  Q7<br>D   Q D   Q D   Q<br>CE<br>Q_6  Q54<br>S5  T5  Q5<br>D   Q D   Q D<br>Q65  CE<br>Q54<br>Q32  S3  T3  Q3<br>D   Q D   Q D<br>Q43  CE<br>Q32  Q10  S1  T1  Q1<br>D   Q D   Q D<br>Q21  CE<br>ECLK0/1  SCLK<br>SEL0<br>UPDATE<br>**----- End of picture text -----**<br>


**Figure 2.13. Input Gearbox** 

More information on the input gearbox is available in Implementing High-Speed Interfaces with MachXO3 Devices (FPGA-TN-02057). 

© 2014-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

30 

FPGA-DS-02032-2.8 

**MachXO3 Family Data Sheet** 

## **2.9. Output Gearbox** 

Each PIC on the top edge has a built-in 8:1 output gearbox. Each of these output gearboxes may be programmed as a 7:1 serializer or as one ODDRX4 (8:1) gearbox or as two ODDRX2 (4:1) gearboxes. Table 2.10 shows the gearbox signals. 

**Table 2.10. Output Gearbox Signal List** 

|**Name**|**I/O Type **|**Description**|
|---|---|---|
|Q|Output|High-speed data output|
|D[7:0]|Input|Low-speed data from device core|
|Video TX(7:1): D[6:0]|—|—|
|GDDRX4(8:1): D[7:0]|—|—|
|GDDRX2(4:1)(IOL-A): D[3:0]|—|—|
|GDDRX2(4:1)(IOL-C): D[7:4]|—|—|
|SCLK|Input|Slow-speed system clock|
|ECLK[1:0]|Input|High-speed edge clock|
|RST|Input|Reset|



The gearboxes have three stage pipeline registers. The first stage registers sample the low-speed input data on the lowspeed system clock. The second stage registers transfer data from the low-speed clock registers to the high- speed clock registers. The third stage pipeline registers controlled by high-speed edge clock shift and mux the high-speed data out to the sysI/O buffer. Figure 2.14 shows the output gearbox block diagram. 

© 2014-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02032-2.8 

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**MachXO3 Family Data Sheet** 

**==> picture [19 x 6] intentionally omitted <==**

**----- Start of picture text -----**<br>
G ND<br>**----- End of picture text -----**<br>


**Figure 2.14. Output Gearbox** 

More information on the output gearbox is available in Implementing High-Speed Interfaces with MachXO3 Devices (FPGA-TN-02057). 

© 2014-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

32 

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**MachXO3 Family Data Sheet** 

## **2.10. sysI/O Buffer** 

Each I/O is associated with a flexible buffer referred to as a sysI/O buffer. These buffers are arranged around the periphery of the device in groups referred to as banks. The sysI/O buffers allow users to implement a wide variety of standards that are found in today’s systems including LVCMOS, TTL, PCI (MachXO3L/LF-9400 devices only), LVDS, BLVDS, MLVDS and LVPECL. 

Each bank is capable of supporting multiple I/O standards. In the MachXO3L/LF devices, single-ended output buffers, ratioed input buffers (LVTTL, LVCMOS and PCI), differential (LVDS) input buffers are powered using I/O supply voltage (VCCIO). Each sysI/O bank has its own VCCIO. 

MachXO3L/LF devices contain three types of sysI/O buffer pairs. 

- Left and Right sysI/O Buffer Pairs 

The sysI/O buffer pairs in the left and right banks of the device consist of two single-ended output drivers and two single-ended input buffers (for ratioed inputs such as LVCMOS and LVTTL). The I/O pairs on the left and right of the devices also have differential input buffers. 

- Bottom sysI/O Buffer Pairs 

The sysI/O buffer pairs in the bottom bank of the device consist of two single-ended output drivers and two singleended input buffers (for ratioed inputs such as LVCMOS and LVTTL). The I/O pairs on the bottom also have differential input buffers. In the MachXO3L/LF-9400 devices, only the I/Os on the bottom banks have programmable PCI clamps and differential input termination. The PCI clamp is enabled after VCC and VCCIO are at valid operating levels and the device has been configured. 

- Top sysI/O Buffer Pairs 

The sysI/O buffer pairs in the top bank of the device consist of two single-ended output drivers and two single-ended input buffers (for ratioed inputs such as LVCMOS and LVTTL). The I/O pairs on the top also have differential I/O buffers. Half of the sysI/O buffer pairs on the top edge have true differential outputs. The sysI/O buffer pair comprising of the A and B PIOs in every PIC on the top edge have a differential output driver. 

## **2.10.1. Typical I/O Behavior during Power-up** 

The internal power-on-reset (POR) signal is deactivated when VCC and VCCIO0 have reached VPORUP level defined in the Power-On-Reset Voltage table in the DC and Switching Characteristics section of this data sheet. After the POR signal is deactivated, the FPGA core logic becomes active. It is the user’s responsibility to ensure that all VCCIO banks are active with valid input logic levels to properly control the output logic states of all the I/O banks that are critical to the application. The default configuration of the I/O pins in a blank device is tri-state with a weak pull-down to GND (some pins such as PROGRAMN and the JTAG pins have weak pull-up to VCCIO as the default functionality). The I/O pins will maintain the blank configuration until VCC and VCCIO (for I/O banks containing configuration I/Os) have reached VPORUP levels at which time the I/Os will take on the user-configured settings only after a proper download/configuration. 

## **2.10.2. Supported Standards** 

The MachXO3L/LF sysI/O buffer supports both single-ended and differential standards. Single-ended standards can be further subdivided into LVCMOS, LVTTL, and PCI. The buffer supports the LVTTL, PCI, LVCMOS 1.2 V, 1.5 V, 1.8 V, 2.5 V, and 3.3 V standards. In the LVCMOS and LVTTL modes, the buffer has individually configurable options for drive strength, bus maintenance (weak pull-up, weak pull-down, bus-keeper latch or none) and open drain. BLVDS, MLVDS and LVPECL output emulation is supported on all devices. The MachXO3L/LF devices support on-chip LVDS output buffers on approximately 50% of the I/Os on the top bank. Differential receivers for LVDS, BLVDS, MLVDS and LVPECL are supported on all banks of MachXO3L/LF devices. PCI compatibility is supported in the bottom bank of the MachXO3L/LF-9400 devices only. PCI support is provided by: 

- Selecting the LVTTL33 buffer standard 

- Enabling the clamp feature 

- Setting 16 mA drive strength (PCI output only). 

Table 2.11 shows the I/O standards (together with their supply and reference voltages) supported by the MachXO3L/LF devices. For further information on utilizing the sysI/O buffer to support a variety of standards please see MachXO3 sysI/O Usage Guide (FPGA-TN-02047). 

© 2014-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

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**MachXO3 Family Data Sheet** 

## **Table 2.11. Supported Input Standards** 

|**Table 2.11. Supported Input Standards**||||||
|---|---|---|---|---|---|
||**VCCIO (Typ.)**<br>~~pO~~|||||
|**Input Standard**<br>~~DO~~|**3.3 V**<br>~~pO~~<br>~~DO~~|**2.5 V**<br>~~pO~~<br>~~DO~~|**1.8 V**<br>~~pO~~<br>~~DO~~|**1.5 V**<br>~~pO~~<br>~~DO~~|**1.2 V**<br>~~pO~~<br>~~DO~~|
|**Single-Ended Interfaces**<br>~~DO~~<br>~~pn~~||||||
|LVTTL<br>~~GO~~|Yes<br>~~GO~~|Yes2<br>~~GO~~|Yes2<br>~~GO~~|Yes2<br>~~GO~~|—<br>~~GO~~|
|LVCMOS33<br>~~GO~~<br>~~GO~~|Yes<br>~~GO~~<br>~~GO~~|Yes2<br>~~GO~~<br>~~GO~~|Yes2<br>~~GO~~<br>~~GO~~|Yes2<br>~~GO~~<br>~~GO~~|—<br>~~GO~~<br>~~GO~~|
|LVCMOS25<br>~~GO~~<br>~~sD~~|Yes2<br>~~GO~~<br>~~sD~~|Yes<br>~~GO~~<br>~~sD~~|Yes2<br>~~GO~~<br>~~sD~~|Yes2<br>~~GO~~<br>~~sD~~|—<br>~~GO~~<br>~~sD~~|
|LVCMOS18<br>~~sD~~<br>~~DO~~|Yes2<br>~~sD~~<br>~~DO~~|Yes2<br>~~sD~~<br>~~DO~~|Yes<br>~~sD~~<br>~~DO~~|Yes2<br>~~sD~~<br>~~DO~~|—<br>~~sD~~<br>~~DO~~|
|LVCMOS15<br>~~DO~~<br>~~GO~~|Yes2<br>~~DO~~<br>~~GO~~|Yes2<br>~~DO~~<br>~~GO~~|Yes2<br>~~DO~~<br>~~GO~~|Yes<br>~~DO~~<br>~~GO~~|Yes2<br>~~DO~~<br>~~GO~~|
|LVCMOS12<br>~~GO~~<br>~~GO~~|Yes2<br>~~GO~~<br>~~GO~~|Yes2<br>~~GO~~<br>~~GO~~|Yes2<br>~~GO~~<br>~~GO~~|Yes2<br>~~GO~~<br>~~GO~~|Yes<br>~~GO~~<br>~~GO~~|
|PCI3<br>~~GF~~|Yes<br>~~GF~~|—<br>~~GF~~|—<br>~~GF~~|—<br>~~GF~~|—<br>~~GF~~|
|**Differential Interfaces**<br>~~Rn~~||||||
|LVDS<br>~~Rn~~<br>~~De~~|Yes<br>~~Rn~~<br>~~De~~|Yes<br>~~Rn~~<br>~~De~~|—<br>~~Rn~~<br>~~De~~|—<br>~~Rn~~<br>~~De~~|—<br>~~Rn~~<br>~~De~~|
|BLVDS, MLVDS, LVPECL, RSDS<br>~~De~~<br>~~sD~~|Yes<br>~~De~~<br>~~sD~~|Yes<br>~~De~~<br>~~sD~~|—<br>~~De~~<br>~~sD~~|—<br>~~De~~<br>~~sD~~|—<br>~~De~~<br>~~sD~~|
|MIPI1<br>~~sD~~<br>~~GO~~|Yes<br>~~sD~~<br>~~GO~~|Yes<br>~~sD~~<br>~~GO~~|—<br>~~sD~~<br>~~GO~~|—<br>~~sD~~<br>~~GO~~|—<br>~~sD~~<br>~~GO~~|
|LVTTLD<br>~~GO~~<br>~~sD~~|Yes<br>~~GO~~<br>~~sD~~|—<br>~~GO~~<br>~~sD~~|—<br>~~GO~~<br>~~sD~~|—<br>~~GO~~<br>~~sD~~|—<br>~~GO~~<br>~~sD~~|
|LVCMOS33D<br>~~sD~~<br>~~GO~~|Yes<br>~~sD~~<br>~~GO~~|—<br>~~sD~~<br>~~GO~~<br>~~GO~~|—<br>~~sD~~<br>~~GO~~<br>~~GO~~|—<br>~~sD~~<br>~~GO~~|—<br>~~sD~~<br>~~GO~~|
|LVCMOS25D<br>~~GO~~<br>~~Ge~~|—<br>~~GO~~<br>~~Ge~~|Yes<br>~~GO~~<br>~~Ge~~<br>~~GO~~|—<br>~~GO~~<br>~~Ge~~<br>~~GO~~|—<br>~~GO~~<br>~~Ge~~|—<br>~~GO~~<br>~~Ge~~|
|LVCMOS18D<br>~~Ge~~<br>~~GF~~|—<br>~~Ge~~<br>~~GF~~|—<br>~~Ge~~<br>~~GO~~<br>~~GF~~|Yes<br>~~Ge~~<br>~~GO~~<br>~~GF~~|—<br>~~Ge~~<br>~~GF~~|—<br>~~Ge~~<br>~~GF~~|



## **Notes:** 

1. These interfaces can be emulated with external resistors in all devices. 

2. Reduced functionality. Refer to MachXO3 sysI/O Usage Guide (FPGA-TN-02047) for more details. 

3. PCI input is supported for MachXO3L/LF-9400 devices, bottom bank 2 only. See the Supported Standards section. 

**Table 2.12. Supported Output Standards** 

|**Output Standard**|**VCCIO(Typ.)**|
|---|---|
|**Single-Ended Interfaces**||
|LVTTL|3.3|
|LVCMOS33|3.3|
|LVCMOS25|2.5|
|LVCMOS18|1.8|
|LVCMOS15|1.5|
|LVCMOS12|1.2|
|LVCMOS33, Open Drain|—|
|LVCMOS25, Open Drain|—|
|LVCMOS18, Open Drain|—|
|LVCMOS15, Open Drain|—|
|LVCMOS12, Open Drain|—|
|PCI332|3.3|
|**Differential Interfaces**||
|LVDS1|2.5, 3.3|
|BLVDS, MLVDS, RSDS1|2.5|
|LVPECL1|3.3|
|MIPI1|2.5|
|LVTTLD|3.3|
|LVCMOS33D|3.3|
|LVCMOS25D|2.5|
|LVCMOS18D|1.8|



## **Notes:** 

1. These interfaces can be emulated with external resistors in all devices. 

2. PCI input is supported for MachXO3L/LF-9400 devices, bottom bank 2 only. See the Supported Standards section. 

© 2014-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

34 

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## **2.10.3. sysI/O Buffer Banks** 

The numbers of banks vary between the devices of this family. MachXO3L/LF-1300 in the 256 Ball packages and the MachXO3L/LF-2100 and higher density devices have six I/O banks (one bank on the top, right and bottom side and three banks on the left side). The MachXO3L/LF-1300 and lower density devices have four banks (one bank per side). Figure 2.15 and Figure 2.16 show the sysI/O banks and their associated supplies for all devices. 

**==> picture [285 x 250] intentionally omitted <==**

**----- Start of picture text -----**<br>
GND VCCIO0<br>ST<br>Bank 0<br>VCCIO5 I<br>—<br>GND<br>VCCIO1<br>VCCIO4GND HL l. 2 |<br>lz my H<br>GND<br>VCCIO3<br>GND HnWF T Jails l||<br>J. ee Bank 2<br>pee<br>GND VCCIO2<br>**----- End of picture text -----**<br>


**Figure 2.15. MachXO3L/LF-1300 in 256 Ball Packages, MachXO3L/LF-2100, MachXO3L/LF-4300, MachXO3L/LF-6900 and MachXO3L/LF-9400 Banks I/O Banks** 

**==> picture [306 x 231] intentionally omitted <==**

**----- Start of picture text -----**<br>
GND VCCIO0<br>p-==><br>Bank 0<br>||<br>VCCIO3 l| | VCCIO1<br>@ |<br>Ig |<br>GND | l GND<br>||<br>Bank 2<br>[=I<br>GND VCCIO2<br>**----- End of picture text -----**<br>


**Figure 2.16. MachXO3L/LF-640 and MachXO3L/LF-1300** Banks 

© 2014-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02032-2.8 

35 

**MachXO3 Family Data Sheet** 

## **2.11. Hot Socketing** 

The MachXO3L/LF devices have been carefully designed to ensure predictable behavior during power-up and powerdown. Leakage into I/O pins is controlled to within specified limits. This allows for easy integration with the rest of the system. These capabilities make the MachXO3L/LF ideal for many multiple power supply and hot-swap applications. 

## **2.12. On-chip Oscillator** 

Every MachXO3L/LF device has an internal CMOS oscillator. The oscillator output can be routed as a clock to the clock tree or as a reference clock to the sysCLOCK PLL using general routing resources. The oscillator frequency can be divided by internal logic. There is a dedicated programming bit and a user input to enable/disable the oscillator. The oscillator frequency ranges from 2.08 MHz to 133 MHz. The software default value of the Master Clock (MCLK) is nominally 2.08 MHz. When a different MCLK is selected during the design process, the following sequence takes place: 

Device powers up with a nominal MCLK frequency of 2.08 MHz. 

During configuration, users select a different master clock frequency. 

The MCLK frequency changes to the selected frequency once the clock configuration bits are received. 

If the user does not select a master clock frequency, then the configuration bitstream defaults to the MCLK frequency of 2.08 MHz. 

Table 2.13 lists all the available MCLK frequencies. 

**Table 2.13. Available MCLK Frequencies** 

|**MCLK(MHz, Nominal)**|**MCLK(MHz, Nominal)**|**MCLK(MHz, Nominal)**|
|---|---|---|
|2.08(default)|9.17|33.25|
|2.46|10.23|38|
|3.17|13.3|44.33|
|4.29|14.78|53.2|
|5.54|20.46|66.5|
|7|26.6|88.67|
|8.31|29.56|133|



## **2.13. Embedded Hardened IP Functions** 

All MachXO3L/LF devices provide embedded hardened functions such as SPI, I[2] C and Timer/Counter. MachXO3LF devices also provide User Flash Memory (UFM). These embedded blocks interface through the WISHBONE interface with routing as shown in Figure 2.17. 

© 2014-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

36 

FPGA-DS-02032-2.8 

**MachXO3 Family Data Sheet** 

**Figure 2.17. Embedded Function Block Interface** 

## **2.13.1. Hardened I[2] C IP Core** 

Every MachXO3L/LF device contains two I[2] C IP cores. These are the primary and secondary I[2] C IP cores. Either of the two cores can be configured either as an I[2] C master or as an I[2] C slave. The only difference between the two IP cores is that the primary core has pre-assigned I/O pins whereas users can assign I/O pins for the secondary core. 

When the IP core is configured as a master it will be able to control other devices on the I[2] C bus through the interface. When the core is configured as the slave, the device will be able to provide I/O expansion to an I[2] C Master. The I[2] C cores support the following functionality: 

- Master and Slave operation 

- 7-bit and 10-bit addressing 

- Multi-master arbitration support 

- Up to 400 kHz data transfer speed 

- General call support 

- Interface to custom logic through 8-bit WISHBONE interface 

**Figure 2.18. I[2] C Core Block Diagram** 

Table 2.14 describes the signals interfacing with the I[2] C cores. 

© 2014-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02032-2.8 

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**MachXO3 Family Data Sheet** 

**Table 2.14. I[2] C Core Signal Description** 

|**Signal Name**|**I/O**|**Description**|
|---|---|---|
|i2c_scl|Bi-directional|Bi-directional clock line of the I2C core. The signal is an output if the I2C core is in master<br>mode. The signal is an input if the I2C core is in slave mode. MUST be routed directly to the<br>pre-assigned I/O of the chip. Refer to the Pinout Information section of this document for<br>detailedpad andpin locations of I2Cports in each MachXO3L/LF device.|
|i2c_sda|Bi-directional|Bi-directional data line of the I2C core. The signal is an output when data is transmitted from<br>the I2C core. The signal is an input when data is received into the I2C core. MUST be routed<br>directly to the pre-assigned I/O of the chip. Refer to the Pinout Information section of this<br>document for detailedpad andpin locations of I2Cports in each MachXO3L/LF device.|
|i2c_irqo|Output|Interrupt request output signal of the I2C core. The intended usage of this signal is for it to be<br>connected to the WISHBONE master controller (i.e. a microcontroller or state machine) and<br>request an interrupt when a specific condition is met. These conditions are described with the<br>I2C register definitions.|
|cfg_wake|Output|Wake-up signal – To be connected only to the power module of the MachXO3L/LF device. The<br>signal is enabled only if the “Wakeup Enable” feature has been set within the EFB GUI, I2C<br>Tab.|
|cfg_stdby|Output|Stand-by signal – To be connected only to the power module of the MachXO3L/LF device. The<br>signal is enabled only if the “Wakeup Enable” feature has been set within the EFB GUI, I2C<br>Tab.|



## **2.13.2. Hardened SPI IP Core** 

Every MachXO3L/LF device has a hard SPI IP core that can be configured as a SPI master or slave. When the IP core is configured as a master it will be able to control other SPI enabled chips connected to the SPI bus. When the core is configured as the slave, the device will be able to interface to an external SPI master. The SPI IP core on MachXO3L/LF devices supports the following functions: 

- Configurable Master and Slave modes 

- Full-Duplex data transfer 

- Mode fault error flag with CPU interrupt capability 

- Double-buffered data register 

- Serial clock with programmable polarity and phase 

- LSB First or MSB First Data Transfer 

- Interface to custom logic through 8-bit WISHBONE interface 

There are some limitations on the use of the hardened user SPI. These are defined in the following technical notes: 

- Minimizing System Interruption During Configuration Using TransFR Technology (FPGA-TN-02025) (Appendix B) 

- Using Hardened Control Functions in MachXO3 Devices (FPGA-TN-02063) 

© 2014-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

38 

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**==> picture [308 x 204] intentionally omitted <==**

**----- Start of picture text -----**<br>
Configuration<br>Logic<br>EFB<br>SPI Function<br>MISO<br>Core<br>Logic/ MOSI<br>Routing<br>EFB<br>WISHBONE SPI Control SCK<br>Interface Registers  Logic<br>MCSN<br>SCSN<br>**----- End of picture text -----**<br>


**Figure 2.19. SPI Core Block Diagram** 

© 2014-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02032-2.8 

39 

**MachXO3 Family Data Sheet** 

Table 2.15 describes the signals interfacing with the SPI cores. 

**Table 2.15. SPI Core Signal Description** 

|**Signal Name**|**I/O **|**Master/Slave**|**Description**|
|---|---|---|---|
|spi_csn[0]|O|Master|SPI master chip-select output|
|spi_csn[1..7]|O|Master|Additional SPI chip-select outputs(total upto eight slaves)|
|spi_scsn|I|Slave|SPI slave chip-select input|
|spi_irq|O|Master/Slave|Interrupt request|
|spi_clk|I/O|Master/Slave|SPI clock. Output in master mode. Input in slave mode.|
|spi_miso|I/O|Master/Slave|SPI data. Input in master mode. Output in slave mode.|
|spi_mosi|I/O|Master/Slave|SPI data. Output in master mode. Input in slave mode.|
|sn|I|Slave|Configuration Slave Chip Select (active low), dedicated for selecting the<br>Configuration Logic.|
|cfg_stdby|O|Master/Slave|Stand-by signal–To be connected only to the power module of the<br>MachXO3L/LF device. The signal is enabled only if the“Wakeup Enable”feature<br>has been set within the EFB GUI, SPI Tab.|
|cfg_wake|O|Master/Slave|Wake-up signal–To be connected only to the power module of the<br>MachXO3L/LF device. The signal is enabled only if the“Wakeup Enable”feature<br>has been set within the EFB GUI, SPI Tab.|



## **2.13.3. Hardened Timer/Counter** 

MachXO3L/LF devices provide a hard Timer/Counter IP core. This Timer/Counter is a general purpose, bidirectional, 16-bit timer/counter module with independent output compare units and PWM support. The Timer/Counter supports the following functions: 

- Supports the following modes of operation: 

- Watchdog timer 

- Clear timer on compare match 

- Fast PWM 

- Phase and Frequency Correct PWM 

- Programmable clock input source 

- Programmable input clock prescaler 

- One static interrupt output to routing 

- One wake-up interrupt to on-chip standby mode controller 

- Three independent interrupt sources: overflow, output compare match, and input capture 

- Auto reload 

- Time-stamping support on the input capture unit 

- Waveform generation on the output 

- Glitch-free PWM waveform generation with variable PWM period 

- Internal WISHBONE bus access to the control and status registers 

- Stand-alone mode with preloaded control registers and direct reset input 

© 2014-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

40 

FPGA-DS-02032-2.8 

**MachXO3 Family Data Sheet** 

**Figure 2.20. Timer/Counter Block Diagram** 

**Table 2.16. Timer/Counter Signal Description** 

|**Port**|**I/O**|**Description**|
|---|---|---|
|tc_clki|I|Timer/Counter input clock signal|
|tc_rstn|I|Register tc_rstn_ena ispreloaded byconfiguration to always keepthispin enabled.|
|tc_ic|I|Input capture trigger event, applicable for non-pwm modes with WISHBONE interface. If enabled,<br>a rising edge of this signal will be detected and synchronized to capture tc_cnt value into tc_icr<br>for time-stamping.|
|tc_int|O|Without WISHBONE–Can be used as overflow flag With WISHBONE–Controlled by three IRQ<br>registers.|
|tc_oc|O|Timer counter output signal|



For more details on these embedded functions, please refer to Using Hardened Control Functions in MachXO3 Devices (FPGA-TN-02063). 

## **2.14. User Flash Memory (UFM)** 

MachXO3LF devices provide a User Flash Memory block, which can be used for a variety of applications including storing a portion of the configuration image, initializing EBRs, to store PROM data or, as a general purpose user Flash memory. The UFM block connects to the device core through the embedded function block WISHBONE interface. Users can also access the UFM block through the JTAG, I[2] C and SPI interfaces of the device. The UFM block offers the following features: 

- Non-volatile storage up to 448 kbits 

- 100,000 write/erase cycles for commercial/industrial devices and 10,000 for automotive devices 

- Write access is performed page-wise; each page has 128 bits (16 bytes) 

- Auto-increment addressing 

- WISHBONE interface 

For more information on the UFM, please refer to Using Hardened Control Functions in MachXO3 Devices (FPGA-TN02063). 

© 2014-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02032-2.8 

41 

**MachXO3 Family Data Sheet** 

## **2.15. Standby Mode and Power Saving Options** 

MachXO3L/LF devices are available in two options, the C and E devices. The C devices have a built-in voltage regulator to allow for 2.5 V VCC and 3.3 V VCC while the E devices operate at 1.2 V VCC. 

MachXO3L/LF devices have been designed with features that allow users to meet the static and dynamic power requirements of their applications by controlling various device subsystems such as the bandgap, power-on-reset circuitry, I/O bank controllers, power guard, on-chip oscillator, PLLs, etc. In order to maximize power savings, MachXO3L/LF devices support a low power Stand-by mode. 

In the stand-by mode the MachXO3L/LF devices are powered on and configured. Internal logic, I/Os and memories are switched on and remain operational, as the user logic waits for an external input. The device enters this mode when the standby input of the standby controller is toggled or when an appropriate I[2] C or JTAG instruction is issued by an external master. Various subsystems in the device such as the band gap, power-on-reset circuitry etc. can be 

configured such that they are automatically turned “off” or go into a low power consumption state to save power when the device enters this state. Note that the MachXO3L/LF devices are powered on when in standby mode and all power supplies should remain in the Recommended Operating Conditions. 

**Table 2.17. MachXO3L/LF Power Saving Features Description** 

|**Device Subsystem**|**Feature Description**|
|---|---|
|Bandgap|The bandgap can be turned off in standby mode. When the Bandgap is turned<br>off, analog circuitry such as the POR, PLLs, on-chip oscillator, and differential I/O<br>buffers are also turned off. Bandgapcan onlybe turned off for 1.2 V devices.|
|Power-On-Reset (POR)|The POR can be turned off in standby mode. This monitors VCC levels. In the<br>event of unsafe VCC drops, this circuit reconfigures the device. When the POR<br>circuitry is turned off, limited power detector circuitry is still active. This option is<br>onlyrecommended for applications in which thepower supplyrails are reliable.|
|On-Chip Oscillator|The on-chip oscillator has two power saving features. It may be switched off if it<br>is not needed inyour design. It can also be turned off in Standbymode.|
|PLL|Similar to the on-chip oscillator, the PLL also has two power saving features. It<br>can be statically switched off if it is not needed in a design. It can also be turned<br>off in Standby mode. The PLL will wait until all output clocks from the PLL are<br>driven low beforepoweringoff.|
|I/O Bank Controller|Differential I/O buffers (used to implement standards such as LVDS) consume<br>more than ratioed single-ended I/Os such as LVCMOS and LVTTL. The I/O bank<br>controller allows the user to turn these I/Os off dynamically on a per bank<br>selection.|
|Dynamic Clock Enable for PrimaryClock Nets|Eachprimaryclock net can be dynamicallydisabled to savepower.|
|Power Guard|Power Guard is a feature implemented in input buffers. This feature allows users<br>to switch off the input buffer when it is not needed. This feature can be used in<br>both clock and data paths. Its biggest impact is that in the standby mode it can<br>be used to switch off clock inputs that are distributed using general routing<br>resources.|



For more details on the standby mode refer to Power and Thermal Estimation and Management for MachXO3 Devices (FPGA-TN-02059). 

© 2014-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

42 

FPGA-DS-02032-2.8 

**MachXO3 Family Data Sheet** 

## **2.16. Power On Reset** 

MachXO3L/LF devices have power-on reset circuitry to monitor VCCINT and VCCIO voltage levels during power-up and operation. At power-up, the POR circuitry monitors VCCINT and VCCIO0 (controls configuration) voltage levels. It then triggers download from the on-chip configuration NVCM/Flash memory after reaching the VPORUP level specified in the Power-On-Reset Voltage table in the DC and Switching Characteristics section of this data sheet. For “E” devices without voltage regulators, VCCINT is the same as the VCC supply voltage. For “C” devices with voltage regulators, VCCINT is regulated from the VCC supply voltage. From this voltage reference, the time taken for configuration and entry into user mode is specified as NVCM/Flash Download Time (tREFRESH) in the DC and Switching Characteristics section of this data sheet. Before and during configuration, the I/Os are held in tri-state. I/Os are released to user functionality once the device has finished configuration. Note that for “C” devices, a separate POR circuit monitors external VCC voltage in addition to the POR circuit that monitors the internal post-regulated power supply voltage level. 

Once the device enters into user mode, the POR circuitry can optionally continue to monitor VCCINT levels. If VCCINT drops below VPORDNBG level (with the bandgap circuitry switched on) or below VPORDNSRAM level (with the bandgap circuitry switched off to conserve power) device functionality cannot be guaranteed. In such a situation the POR issues a reset and begins monitoring the VCCINT and VCCIO voltage levels. VPORDNBG and VPORDNSRAM are both specified in the Power-On-Reset Voltage table in the DC and Switching Characteristics section of this data sheet. 

Note that once an “E” device enters user mode, users can switch off the bandgap to conserve power. When the bandgap circuitry is switched off, the POR circuitry also shuts down. The device is designed such that a minimal, low power POR circuit is still operational (this corresponds to the VPORDNSRAM reset point described in the paragraph above). However this circuit is not as accurate as the one that operates when the bandgap is switched on. The low power POR circuit emulates an SRAM cell and is biased to trip before the vast majority of SRAM cells flip. If users are concerned about the VCC supply dropping below VCC (min) they should not shut down the bandgap or POR circuit. 

## **2.17. Configuration and Testing** 

This section describes the configuration and testing features of the MachXO3L/LF family. 

## **2.17.1. IEEE 1149.1-Compliant Boundary Scan Testability** 

All MachXO3L/LF devices have boundary scan cells that are accessed through an IEEE 1149.1 compliant test access port (TAP). This allows functional testing of the circuit board, on which the device is mounted, through a serial scan path that can access all critical logic nodes. Internal registers are linked internally, allowing test data to be shifted in and loaded directly onto test nodes, or test data to be captured and shifted out for verification. The test access port consists of dedicated I/Os: TDI, TDO, TCK and TMS. The test access port shares its power supply with VCCIO Bank 0 and can operate with LVCMOS3.3, 2.5, 1.8, 1.5, and 1.2 standards. 

For more details on boundary scan test, see Boundary Scan Testability with Lattice sysI/O Capability (AN8066) and Minimizing System Interruption During Configuration Using TransFR Technology (FPGA-TN-02025). 

## **2.17.2. Device Configuration** 

All MachXO3L/LF devices contain two ports that can be used for device configuration. The Test Access Port (TAP), which supports bit-wide configuration and the sysCONFIG port which supports serial configuration through I[2] C or SPI. The TAP supports both the IEEE Standard 1149.1 Boundary Scan specification and the IEEE Standard 1532 In-System Configuration specification. There are various ways to configure a MachXO3L/LF device: 

- Internal Flash Download 

- JTAG 

- Standard Serial Peripheral Interface (Master SPI mode) – interface to boot PROM memory 

- System microprocessor to drive a serial slave SPI port (SSPI mode) 

- Standard I2C Interface to system microprocessor 

Upon power-up, the configuration SRAM is ready to be configured using the selected sysCONFIG port. Once a configuration port is selected, it will remain active throughout that configuration cycle. The IEEE 1149.1 port can be activated any time after power-up by sending the appropriate command through the TAP port. Optionally the de- vice can run a CRC check upon entering the user mode. This will ensure that the device was configured correctly. 

© 2014-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02032-2.8 

43 

**MachXO3 Family Data Sheet** 

The sysCONFIG port has 10 dual-function pins which can be used as general purpose I/Os if they are not required for configuration. See MachXO3 Programming and Configuration Usage Guide (FPGA-TN-02055) for more information about using the dual-use pins as general purpose I/Os. 

Lattice design software uses proprietary compression technology to compress bit-streams for use in MachXO3L/ LF devices. Use of this technology allows Lattice to provide a lower cost solution. In the unlikely event that this technology is unable to compress bitstreams to fit into the amount of on-chip NVCM/Flash, there are a variety of techniques that can be utilized to allow the bitstream to fit in the on-chip NVCM/Flash. For more details, refer to MachXO3 Programming and Configuration Usage Guide (FPGA-TN-02055). 

The Test Access Port (TAP) has five dual purpose pins (TDI, TDO, TMS, TCK and JTAGENB). These pins are dual function pins - TDI, TDO, TMS and TCK can be used as general purpose I/O if desired. For more details, refer to MachXO3 Programming and Configuration Usage Guide (FPGA-TN-02055). 

## **2.17.2.1. TransFR (Transparent Field Reconfiguration)** 

TransFR is a unique Lattice technology that allows users to update their logic in the field without interrupting system operation using a simple push-button solution. For more details, refer to Minimizing System Interruption During Configuration Using TransFR Technology (FPGA-TN-02025) for details. 

## **2.17.2.2. Security and One-Time Programmable Mode (OTP)** 

For applications where security is important, the lack of an external bitstream provides a solution that is inherently more secure than SRAM-based FPGAs. This is further enhanced by device locking. MachXO3L/LF devices contain security bits that, when set, prevent the readback of the SRAM configuration and NVCM/Flash spaces. The device can be in one of two modes: 

- Unlocked – Readback of the SRAM configuration and NVCM/Flash spaces is allowed. 

- Permanently Locked – The device is permanently locked. 

Once set, the only way to clear the security bits is to erase the device. To further complement the security of the device, a One Time Programmable (OTP) mode is available. Once the device is set in this mode it is not possible to erase or re-program the NVCM/Flash and SRAM OTP portions of the device. For more details, refer to MachXO3 Programming and Configuration Usage Guide (FPGA-TN-02055). 

## **2.17.2.3. Password** 

The MachXO3LF supports a password-based security access feature also known as Flash Protect Key. Optionally, the MachXO3L device can be ordered with a custom specification (c-spec) to support this feature. The Flash Protect Key feature provides a method of controlling access to the Configuration and Programming modes of the device. When enabled, the Configuration and Programming edit mode operations (including Write, Verify and Erase operations) are allowed only when coupled with a Flash Protect Key which matches that expected by the device. Without a valid Flash Protect Key, the user can perform only rudimentary non-configuration operations such as Read Device ID. For more details, refer to Using Password Security with MachXO3 Devices (FPGA-TN-02072). 

## **2.17.2.4. Dual Boot** 

MachXO3L/LF devices can optionally boot from two patterns, a primary bitstream and a golden bitstream. If the primary bitstream is found to be corrupt while being downloaded into the SRAM, the device shall then automatically re-boot from the golden bitstream. Note that the primary bitstream must reside in the external SPI Flash. The golden image MUST reside in an on-chip NVCM/Flash. For more details, refer to MachXO3 Programming and Configuration Usage Guide (FPGA-TN-02055). 

## **2.17.2.5. Soft Error Detection** 

The SED feature is a CRC check of the SRAM cells after the device is configured. This check ensures that the SRAM cells were configured successfully. This feature is enabled by a configuration bit option. The Soft Error Detection can also be initiated in user mode via an input to the fabric. The clock for the Soft Error Detection circuit is generated using a dedicated divider. The undivided clock from the on-chip oscillator is the input to this divider. For low power applications users can switch off the Soft Error Detection circuit. For more details, refer to MachXO3 Soft Error Detection Usage Guide (FPGA-TN-02062). 

© 2014-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02032-2.8 

44 

**MachXO3 Family Data Sheet** 

## **2.17.2.6. Soft Error Correction** 

The MachXO3LF device supports Soft Error Correction (SEC). Optionally, the MachXO3L device can be ordered with a custom specification (c-spec) to support this feature. When BACKGROUND_RECONFIG is enabled using the Lattice Diamond Software in a design, asserting the PROGRAMN pin or issuing the REFRESH sysConfig command refreshes the SRAM array from configuration memory. Only the detected error bit is corrected. No other SRAM cells are changed, allowing the user design to function uninterrupted. 

During the project design phase, if the overall system cannot guarantee containment of the error or its subsequent effects on downstream data or control paths, Lattice recommends using SED only. The MachXO3 can be then be soft-reset by asserting PROGRAMN or issuing the Refresh command over a sysConfig port in response to SED. Soft-reset additionally erases the SRAM array prior to the SRAM refresh, and asserts internal Reset circuitry to guarantee a known state. For more details, refer to MachXO3 Soft Error Detection (SED)/Correction (SEC) Usage Guide (FPGA-TN-02062). 

## **2.18. TraceID** 

Each MachXO3L/LF device contains a unique (per device), TraceID that can be used for tracking purposes or for IP security applications. The TraceID is 64 bits long. Eight out of 64 bits are user-programmable, the remaining 56 bits are factory-programmed. The TraceID is accessible through the EFB WISHBONE interface and can also be accessed through the SPI, I[2] C, or JTAG interfaces. 

## **2.19. Density Shifting** 

The MachXO3L/LF family has been designed to enable density migration within the same package. Furthermore, the architecture ensures a high success rate when performing design migration from lower density devices to higher density devices. In many cases, it is also possible to shift a lower utilization design targeted for a high-density device to a lower density device. However, the exact details of the final resource utilization will impact the likely success in each case. When migrating from lower to higher density or higher to lower density, ensure to review all the power supplies and NC pins of the chosen devices. For more details refer to the MachXO3 migration files. 

## **2.20. MachXO3LF to MachXO3L Low Cost Migration Path** 

To support the MachXO3LF to MachXO3L low cost migration path, the MachXO3L Migration options (JEDEC and Bitstream) are added to the Process List in Diamond. This migration path is a time saving feature as it allows you to validate functionality and timing on one project without having to recompile your design for the MachXO3L device. MachXO3L device does not support UFM, SEC, and Password Protect features. For example if a MachXO3LF design is using UFM, an error message is produced if converting this design to MachXO3L. 

© 2014-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02032-2.8 

45 

**MachXO3 Family Data Sheet** 

## **3. DC and Switching Characteristics** 

## **3.1. Absolute Maximum Rating** 

## **Table 3.1. Absolute Maximum Rating[1, 2, 3]** 

||**MachXO3L/LF E(1.2 V)**|**MachXO3L/LF C(2.5 V/3.3 V)6 **|
|---|---|---|
|SupplyVoltage VCC|–0.5 V to 1.32 V|–0.5 V to 3.75 V|
|Output SupplyVoltage VCCIO|–0.5 V to 3.75 V|–0.5 V to 3.75 V|
|I/O Tri-state Voltage Applied4, 5|–0.5 V to 3.75 V|–0.5 V to 3.75 V|
|Dedicated Input Voltage Applied4|–0.5 V to 3.75 V|–0.5 V to 3.75 V|
|Storage Temperature(Ambient)|–55 °C to 125 °C|–55 °C to 125 °C|
|Junction Temperature(TJ)|–40 °C to 125 °C|–40 °C to 125 °C|



## **Notes:** 

1. Stress above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. Functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. 

2. Compliance with the Lattice Thermal Management document is required. 

3. All voltages referenced to GND. 

4. Overshoot and undershoot of –2 V to (VIHMAX + 2) volts is permitted for a duration of <20 ns. 

5. The dual function I[2] C pins SCL and SDA are limited to –0.25 V to 3.75 V or to –0.3 V with a duration of <20 ns. 

6. Refer to Power and Thermal Estimation and Management for MachXO3 Devices (FPGA-TN-02059) for determination of safe ambient operating conditions. 

## **3.2. Recommended Operating Conditions** 

**Table 3.2. Recommended Operating Conditions[1]** 

|**Symbol**|**Parameter**|**Min.**|**Max.**|**Units**|
|---|---|---|---|---|
|VCC1|Core SupplyVoltage for 1.2 V Devices|1.14|1.26|V|
||Core SupplyVoltage for 2.5 V/3.3 V Devices|2.375|3.465|V|
|VCCIO1, 2, 3|I/O Driver SupplyVoltage|1.14|3.465|V|
|tJCOM|Junction Temperature Commercial Operation|0|85|°C|
|tJIND|Junction Temperature Industrial Operation|–40|100|°C|
|tJAUTO|Junction Temperature Automotive Operation|–40|125|°C|



## **Notes:** 

1. Like power supplies must be tied together. For example, if VCCIO and VCC are both the same voltage, they must also be the same supply. 

2. See recommended voltages by I/O standard in subsequent table. 

3. VCCIO pins of unused I/O banks should be connected to the VCC power supply on boards. 

## **3.3. Power Supply Ramp Rates** 

## **Table 3.3. Power Supply Ramp Rates** 

|**Symbol**|**Symbol**|**Parameter**|**Min.**|**Typ. **|**Max.**|**Units**|
|---|---|---|---|---|---|---|
|tRAMP|Commercial/Industrial|Power supply ramp rates for all power supplies.|0.01|—|100|V/ms|
||Automotive||0.01|—|40|V/ms|



**Note:** Assumes monotonic ramp rates. 

© 2014-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02032-2.8 

46 

**MachXO3 Family Data Sheet** 

## **3.4. Power-On-Reset Voltage Levels** 

**Table 3.4. Power-On Reset Voltage Levels** 

|**Symbol**<br>~~ee~~|**Parameter**<br>~~ee~~|**Commercial/Industrial**<br>~~ee~~<br>~~ee~~<br>~~ET~~|**Commercial/Industrial**<br>~~ee~~<br>~~ee~~<br>~~ET~~|**Commercial/Industrial**<br>~~ee~~<br>~~ee~~<br>~~ET~~|**Automotive**<br>~~ee~~<br>~~ee~~<br>~~ET~~|**Automotive**<br>~~ee~~<br>~~ee~~<br>~~ET~~|**Automotive**<br>~~ee~~<br>~~ee~~<br>~~ET~~|**Units**<br>~~ee~~|
|---|---|---|---|---|---|---|---|---|
|||**Min.**<br>~~ee~~|**Typ. **<br>~~ee~~|**Max.**<br>~~ee~~<br>~~ET~~|**Min.**<br>~~ee~~<br>~~ET~~|**Typ. **<br>~~ee~~<br>~~ET~~|**Max.**<br>~~ee~~<br>~~ET~~||
|VPORUP<br>~~ee~~|Power-On-Reset ramp up trip point (band gap<br>based circuit monitoringVCCINT and VCCIO0)<br>~~ee~~|0.9<br>~~ee~~|—<br>~~ee~~|1.06<br>~~ET~~<br>~~ee~~|0.9<br>~~ET~~<br>~~ee~~|—<br>~~ET~~<br>~~ee~~|1.06<br>~~ET~~<br>~~ee~~|V<br>~~ee~~|
|VPORUPEXT<br>~~ee~~|Power-On-Reset ramp up trip point (band gap<br>based circuit monitoring external VCCpower<br>supply)<br>~~ee~~|1.5<br>~~ee~~|—<br>~~ee~~|2.1<br>~~ee~~|1.5<br>~~ee~~|—<br>~~ee~~|2.1<br>~~ee~~|V<br>~~ee~~|
|VPORDNBG<br>~~ee~~<br>~~ee~~|Power-On-Reset ramp down trip point (band gap<br>based circuit monitoringVCCINT)<br>~~ee~~<br>~~ee~~|0.75<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~|0.93<br>~~ee~~<br>~~ee~~|0.75<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~|1.06<br>~~ee~~<br>~~ee~~|V<br>~~ee~~<br>~~ee~~|
|VPORDNBGEXT<br>~~ee~~<br>~~se~~|Power-On-Reset ramp down trip point (band gap<br>based circuit monitoringVCC)<br>~~ee~~<br>~~se~~|0.98<br>~~ee~~<br>~~se~~|—<br>~~ee~~<br>~~se~~|1.33<br>~~ee~~<br>~~se~~|0.98<br>~~ee~~<br>~~se~~|—<br>~~ee~~<br>~~se~~|1.47<br>~~ee~~<br>~~se~~|V<br>~~ee~~<br>~~se~~|
|VPORDNSRAM<br>~~se~~<br>~~se~~|Power-On-Reset ramp down trip point (SRAM<br>based circuit monitoringVCCINT)<br>~~se~~<br>~~se~~|—<br>~~se~~<br>~~se~~|0.6<br>~~se~~<br>~~se~~|—<br>~~se~~<br>~~se~~|—<br>~~se~~<br>~~se~~|0.84<br>~~se~~<br>~~se~~|—<br>~~se~~<br>~~se~~|V<br>~~se~~<br>~~se~~|
|VPORDNSRAMEXT<br>~~se~~<br>~~es~~|Power-On-Reset ramp down trip point (SRAM<br>based circuit monitoringVCC)<br>~~se~~<br>~~es~~|—<br>~~se~~<br>~~es~~|0.96<br>~~se~~<br>~~es~~|—<br>~~se~~<br>~~es~~|—<br>~~se~~<br>~~es~~|1.16<br>~~se~~<br>~~es~~|—<br>~~se~~<br>~~es~~|V<br>~~se~~<br>~~es~~|



- These POR trip points are only provided for guidance. Device operation is only characterized for power supply voltages specified under recommended operating conditions. 

- For devices without voltage regulators VCCINT is the same as the VCC supply voltage. For devices with voltage regulators, VCCINT is regulated from the VCC supply voltage. 

- Note that VPORUP (min.) and VPORDNBG (max.) are in different process corners. For any given process corner VPORDNBG (max.) is always 12.0 mV below VPORUP (min.). 

- VPORUPEXT is for C devices only. In these devices, a separate POR circuit monitors the external VCC power supply. 

- VCCIO0 does not have a Power-On-Reset ramp down trip point. VCCIO0 must remain within the Recommended Operating Conditions to ensure proper operation. 

## **3.5. Hot Socketing Specifications** 

**Table 3.5. Hot Socketing Specifications** 

|**Symbol**|**Parameter**|**Condition**|**Max.**|**Units**|
|---|---|---|---|---|
|IDK|Input or I/O leakage Current|0 < VIN< VIH (MAX)|± 1000|µA|



**Notes** : 

- Insensitive to sequence of VCC and VCCIO. However, assumes monotonic rise/fall rates for VCC and VCCIO. 

- 0 < VCC < VCC (MAX), 0 < VCCIO < VCCIO (MAX). 

- IDK is additive to IPU, IPD or IBH. 

© 2014-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02032-2.8 

47 

**MachXO3 Family Data Sheet** 

## **3.6. Programming/Erase Specifications** 

**Table 3.6. Programming/Erase Specifications** 

|**Symbol**|**Parameter**|**Commercial/Industrial**|**Commercial/Industrial**|**Automotive**|**Automotive**|**Units**|
|---|---|---|---|---|---|---|
|||**Min.**|**Max.1**|**Min.**|**Max.1**||
|NPROGCYC|NVCM CFG, UFM, and Feature Row<br>Programmingcyclesper tRETENTION|—|9|—|9|Cycles|
||Flash Programming cycles per<br>tRETENTION|—|10,000|—|1,000||
||Flash Write/Erase cycles2|—|100,000|—|10,000||
|tRETENTION|Data retention at 125°C junction<br>temperature|—|—|2|—|Years|
||Data retention at 100°C junction<br>temperature|10|—|10|—||
||Data retention at 85°C junction<br>temperature|20|—|20|—||



## **Notes:** 

1. Maximum Flash memory reads are limited to 7.5E13 cycles over the lifetime of the product. 

2. A Write/Erase cycle is defined as any number of writes over time followed by any erase cycle. 

## **3.7. ESD Performance** 

Refer to the MachXO3/MachXO3LF Product Family Qualification Summary for complete qualification data, including ESD performance. 

© 2014-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

48 

FPGA-DS-02032-2.8 

**MachXO3 Family Data Sheet** 

## **3.8. DC Electrical Characteristics** 

Over recommended operating conditions. 

**Table 3.7. DC Electrical Characteristics** 

|**Symbol**<br>~~a~~|**Parameter**<br>~~a~~|**Condition**<br>~~a~~<br>~~a~~|**Commercial/Industrial**<br>~~ee~~<br>~~a~~<br>~~eeee~~|**Commercial/Industrial**<br>~~ee~~<br>~~a~~<br>~~eeee~~|**Commercial/Industrial**<br>~~ee~~<br>~~a~~<br>~~eeee~~|**Automotive**<br>~~ee~~<br>~~a~~<br>~~eeee ee~~|**Automotive**<br>~~ee~~<br>~~a~~<br>~~eeee ee~~|**Automotive**<br>~~ee~~<br>~~a~~<br>~~eeee ee~~|**Units**<br>~~a~~<br>~~ee~~|
|---|---|---|---|---|---|---|---|---|---|
||||**Min.**<br>~~a~~<br>~~ee~~|**Typ. **<br>~~a~~<br>~~ee~~|**Max.**<br>~~a~~<br>~~ee~~|**Min.**<br>~~a~~<br>~~ee~~|**Typ. **<br>~~a~~<br>~~ee ee~~|**Max.**<br>~~a~~<br>~~ee~~||
|IIL, IIH1, 4<br>~~a~~<br>~~ee~~|Input or I/O Leakage<br>~~a~~<br>~~ee~~|ClampOFF and VCCIO< VIN< VIH (MAX)<br>~~a~~<br>~~a~~<br>~~GG~~|—<br>~~a~~<br>~~ee~~<br>~~GG~~|—<br>~~a~~<br>~~ee ~~<br>~~GG~~|+175<br>~~a~~<br> ~~ee ~~<br>~~GG~~|—<br>~~a~~<br> ~~ee ~~<br>~~GG~~|—<br>~~a~~<br> ~~ee ee~~<br>~~GG~~|+175<br>~~a~~<br>~~ee~~<br>~~GG~~|µA<br>~~a~~<br>~~ee~~<br>~~GG~~|
|||ClampOFF and VIN= VCCIO<br>~~GG~~<br>~~Gd~~|–10<br>~~GG~~<br>~~Gd~~|—<br>~~GG~~<br>~~Gd~~|10<br>~~GG~~<br>~~Gd~~|–10<br>~~GG~~<br>~~Gd~~|—<br>~~GG~~<br>~~Gd~~|11<br>~~GG~~<br>~~Gd~~|µA<br>~~GG~~<br>~~Gd~~|
|||ClampOFF and VCCIO- 0.97 V < VIN< VCCIO<br>~~Gd~~<br>~~Ge~~|–175<br>~~Gd~~<br>~~Ge~~|—<br>~~Gd~~<br>~~Ge~~|—<br>~~Gd~~<br>~~Ge~~|–175<br>~~Gd~~<br>~~Ge~~|—<br>~~Gd~~<br>~~Ge~~|—<br>~~Gd~~<br>~~Ge~~|µA<br>~~Gd~~<br>~~Ge~~|
|||ClampOFF and 0 V < VIN< VCCIO– 0.97 V<br>~~Ge~~<br>~~Ge~~|—<br>~~Ge~~<br>~~Ge~~|—<br>~~Ge~~<br>~~Ge~~|10<br>~~Ge~~<br>~~Ge~~|—<br>~~Ge~~<br>~~Ge~~|—<br>~~Ge~~<br>~~Ge~~|10<br>~~Ge~~<br>~~Ge~~|µA<br>~~Ge~~<br>~~Ge~~|
|||ClampOFF and VIN= GND<br>~~Ge~~<br>~~Ge~~|—<br>~~Ge~~<br>~~Ge~~|—<br>~~Ge~~<br>~~Ge~~|10<br>~~Ge~~<br>~~Ge~~|—<br>~~Ge~~<br>~~Ge~~|—<br>~~Ge~~<br>~~Ge~~|10<br>~~Ge~~<br>~~Ge~~|µA<br>~~Ge~~<br>~~Ge~~|
|||ClampON and 0 V < VIN< VCCIO<br>~~GO~~|—<br>~~GO~~|—<br>~~GO~~<br>~~GO~~|10<br>~~GO~~<br>~~GO~~|—<br>~~GO~~<br>~~GO~~|—<br>~~GO~~<br>~~GO~~|11<br>~~GO~~|µA<br>~~GO~~|
|IPU<br>~~eG~~<br>~~ee~~<br>~~Re~~|I/O Active Pull-upCurrent<br>~~eG~~<br>~~ee~~<br>~~Re~~|0 < VIN< 0.7 VCCIO<br>~~GO~~<br>~~eG~~<br>~~G~~~~**O**~~|–309<br>~~GO~~<br>~~eG~~<br>~~**O**O~~|—<br>~~GO~~<br>~~eG~~<br>~~GO~~<br>~~O~~|–26<br>~~GO~~<br>~~eG~~<br>~~GO~~<br>~~O~~~~**O**~~|–309<br>~~GO~~<br>~~eG~~<br>~~GO~~<br>~~**G**O~~|—<br>~~GO~~<br>~~eG~~<br>~~GO~~|–26<br>~~GO~~<br>~~eG~~|µA<br>~~GO~~<br>~~eG~~|
|IPD<br>~~eG~~<br>~~ee~~<br>~~Re~~|I/O Active Pull-down Current<br>~~eG~~<br>~~ee~~<br>~~Re~~|VIL (MAX)< VIN< VCCIO<br>~~eG~~<br>~~G~~~~**O**~~|30<br>~~eG~~<br>~~**O**O~~|—<br>~~eG~~<br>~~GO~~<br>~~O~~|305<br>~~eG~~<br>~~GO~~<br>~~O~~~~**O**~~|30<br>~~eG~~<br>~~GO~~<br>~~**G**O~~<br>~~O~~|—<br>~~eG~~<br>~~GO~~<br>~~O~~|305<br>~~eG~~|µA<br>~~eG~~|
|IBHLS<br>~~ee~~<br>~~Re~~|Bus Hold Low sustainingcurrent<br>~~ee~~<br>~~Re~~<br>~~GO~~|VIN= VIL (MAX)<br>~~G~~~~**O**~~<br>~~GO~~|30<br>~~**O**O~~<br>~~GO~~|—<br>~~GO ~~<br>~~O~~<br>~~GO~~|—<br> ~~GO ~~<br>~~O~~~~**O**~~<br>~~GO~~<br>~~GO~~|30<br> ~~GO~~<br>~~**G**O~~<br>~~O~~<br>~~GO~~|—<br>~~GO~~<br>~~O~~|—<br>~~I~~|µA|
|IBHHS<br>~~Re~~<br>~~G~~|Bus Hold High sustainingcurrent<br>~~Re~~<br>~~GO~~<br>~~G~~|VIN= 0.7VCCIO<br>~~G~~~~**O**~~<br>~~GO~~<br>~~G~~|–30<br>~~**O**O~~<br>~~GO~~|—<br>~~O ~~<br>~~GO~~|—<br> ~~O~~~~**O** ~~<br>~~GO~~<br>~~GO~~<br>~~CG~~|–27<br> ~~**G**O~~<br>~~O~~<br>~~GO~~<br>~~CG~~|—<br>~~O~~<br>~~CG~~|—<br>~~I~~|µA|
|IBHLO<br>~~G~~<br>~~GG~~|Bus Hold Low Overdrive current<br>~~G~~<br>~~GG~~|0 ≤ VIN≤ VCCIO<br>~~G~~<br>~~GG~~|—<br>~~GG~~|—<br>~~GG~~|305<br>~~GO ~~<br>~~GG~~<br>~~CG~~|—<br> ~~GO~~<br>~~GG~~<br>~~CG~~|—<br>~~GG~~<br>~~CG~~|305<br>~~I~~<br>~~GG~~|µA<br>~~GG~~|
|IBHHO<br>~~Pe~~|Bus Hold High Overdrive current|0 ≤ VIN≤ VCCIO|—|—|–309<br>~~CG~~|—<br>~~CG~~|—<br>~~CG~~|–309|µA|
|VBHT3<br>~~Pe~~|Bus Hold TripPoints|—|VIL (MAX)|—|VIH (MIN)|VIL (MAX)|—|VIH (MIN)|V|
|C1<br>~~Pe~~|I/O Capacitance2|VCCIO= 3.3 V, 2.5 V, 1.8 V, 1.5 V, 1.2 V,<br>VCC= Typ., VIO= 0 to VIH (MAX)|3|5|9|3|5|9|pf|
|VHYST|Hysteresis for Schmitt Trigger<br>Inputs5|VCCIO= 3.3 V, Hysteresis = Large<br>~~Gs~~|—<br>~~Gs~~|450<br>~~Gs~~|—<br>~~Gs~~|—<br>~~Gs~~|450<br>~~Gs~~|—<br>~~Gs~~|mV<br>~~Gs~~|
|||VCCIO= 2.5 V, Hysteresis = Large<br>~~Gs~~<br>~~Qe~~|—<br>~~Gs~~<br>~~Qe~~|250<br>~~Gs~~<br>~~Qe~~|—<br>~~Gs~~<br>~~Qe~~|—<br>~~Gs~~<br>~~Qe~~|250<br>~~Gs~~<br>~~Qe~~|—<br>~~Gs~~<br>~~Qe~~|mV<br>~~Gs~~<br>~~Qe~~|
|||VCCIO= 1.8 V, Hysteresis = Large<br>~~Qe~~<br>~~Ge~~|—<br>~~Qe~~<br>~~Ge~~|125<br>~~Qe~~<br>~~Ge~~|—<br>~~Qe~~<br>~~Ge~~|—<br>~~Qe~~<br>~~Ge~~|125<br>~~Qe~~<br>~~Ge~~|—<br>~~Qe~~<br>~~Ge~~|mV<br>~~Qe~~<br>~~Ge~~|
|||VCCIO= 1.5 V, Hysteresis = Large<br>~~Ge~~<br>~~Ge~~|—<br>~~Ge~~<br>~~Ge~~|100<br>~~Ge~~<br>~~Ge~~|—<br>~~Ge~~<br>~~Ge~~|—<br>~~Ge~~<br>~~Ge~~|100<br>~~Ge~~<br>~~Ge~~|—<br>~~Ge~~<br>~~Ge~~|mV<br>~~Ge~~<br>~~Ge~~|
|||VCCIO= 3.3 V, Hysteresis = Small<br>~~Ge~~<br>~~Gs~~|—<br>~~Ge~~<br>~~Gs~~|250<br>~~Ge~~<br>~~Gs~~|—<br>~~Ge~~<br>~~Gs~~|—<br>~~Ge~~<br>~~Gs~~|250<br>~~Ge~~<br>~~Gs~~|—<br>~~Ge~~<br>~~Gs~~|mV<br>~~Ge~~<br>~~Gs~~|
|||VCCIO= 2.5 V, Hysteresis = Small<br>~~Gs~~<br>~~GO~~|—<br>~~Gs~~<br>~~GO~~|150<br>~~Gs~~<br>~~GO~~|—<br>~~Gs~~<br>~~GO~~|—<br>~~Gs~~<br>~~GO~~|150<br>~~Gs~~<br>~~GO~~|—<br>~~Gs~~<br>~~GO~~|mV<br>~~Gs~~<br>~~GO~~|
|||VCCIO= 1.8 V, Hysteresis = Small<br>~~GO~~<br>~~GR~~|—<br>~~GO~~<br>~~GR~~|60<br>~~GO~~<br>~~GR~~|—<br>~~GO~~<br>~~GR~~|—<br>~~GO~~<br>~~GR~~|60<br>~~GO~~<br>~~GR~~|—<br>~~GO~~<br>~~GR~~|mV<br>~~GO~~<br>~~GR~~|
|||VCCIO= 1.5 V, Hysteresis = Small<br>~~GR~~<br>~~fs~~|—<br>~~GR~~<br>~~fs~~|40<br>~~GR~~<br>~~fs~~|—<br>~~GR~~<br>~~fs~~|—<br>~~GR~~<br>~~fs~~|40<br>~~GR~~<br>~~fs~~|—<br>~~GR~~<br>~~fs~~|mV<br>~~GR~~<br>~~fs~~|



## **Notes:** 

1. Input or I/O leakage current is measured with the pin configured as an input or as an I/O with the output driver tri-stated. It is not measured with the output driver active. Bus maintenance circuits are disabled. 

2. TA 25 °C, f = 1.0 MHz. 

3. Refer to VIL and VIH in the sysI/O Single-Ended DC Electrical Characteristics table of this document. 

4. When VIH is higher than VCCIO, a transient current typically of 30 ns in duration or less with a peak current of 6 mA can occur on the high-to-low transition. For true LVDS output pins in MachXO3L/LF devices, VIH must be less than or equal to VCCIO. 

5. With bus keeper circuit turned on. For more details, refer to MachXO3 sysI/O Usage Guide (FPGA-TN-02047). 

© 2014-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02032-2.8 

49 

**MachXO3 Family Data Sheet** 

## **3.9. Static Supply Current – C/E Devices** 

**Table 3.8. Static Supply Current – C/E Devices[1, 2, 3, 6]** 

|**Symbol**<br>~~a~~|**Parameter**|**Device**|**Typ.4**|**Units**|
|---|---|---|---|---|
|ICC|Core Power Supply|LCMXO3/L/LF-1300C 256 Ball Package<br>~~ee~~|4.8<br>~~ee~~|mA<br>~~ee~~|
|||LCMXO3L/LF-2100C<br>~~es~~|4.8<br>~~es~~|mA<br>~~es~~|
|||LCMXO3L/LF-2100C 324 Ball Package<br>~~es~~<br>~~es~~|8.45<br>~~es~~<br>~~es~~|mA<br>~~es~~<br>~~es~~|
|||LCMXO3L/LF-4300C<br>~~es~~<br>~~es~~|8.45<br>~~es~~<br>~~es~~|mA<br>~~es~~<br>~~es~~|
|||LCMXO3L/LF-4300C 400 Ball Package<br>~~es~~<br>~~ee~~|12.87<br>~~es~~<br>~~ee~~|mA<br>~~es~~<br>~~ee~~|
|||LCMXO3L/LF-6900C<br>~~ee~~<br>~~es~~|12.87<br>~~ee~~<br>~~es~~|mA<br>~~ee~~<br>~~es~~|
|||LCMXO3L/LF-9400C<br>~~es~~<br>~~es~~|17.86<br>~~es~~<br>~~es~~|mA<br>~~es~~<br>~~es~~|
|||LCMXO3L/LF-640E<br>~~ee~~|1.00<br>~~ee~~|mA<br>~~ee~~|
|||LCMXO3L/LF-1300E<br>~~es~~|1.00<br>~~es~~|mA<br>~~es~~|
|||LCMXO3L/LF-1300E 256 Ball Package<br>~~es~~<br>~~es~~|1.39<br>~~es~~<br>~~es~~|mA<br>~~es~~<br>~~es~~|
|||LCMXO3L/LF-2100E<br>~~es~~<br>~~es~~|1.39<br>~~es~~<br>~~es~~|mA<br>~~es~~<br>~~es~~|
|||LCMXO3L/LF-2100E 324 Ball Package<br>~~es~~<br>~~ee~~|2.55<br>~~es~~<br>~~ee~~|mA<br>~~es~~<br>~~ee~~|
|||LCMXO3L/LF-4300E<br>~~ee~~<br>~~es~~|2.55<br>~~ee~~<br>~~es~~|mA<br>~~ee~~<br>~~es~~|
|||LCMXO3L/LF-6900E<br>~~es~~<br>~~es~~|4.06<br>~~es~~<br>~~es~~|mA<br>~~es~~<br>~~es~~|
|||LCMXO3L/LF-9400E<br>~~es~~|5.66<br>~~es~~|mA<br>~~es~~|
|ICCIO<br>~~a~~|Bank Power Supply5VCCIO= 2.5 V|All devices<br>~~es~~|0<br>~~es~~|mA<br>~~es~~|



## **Notes:** 

1. For further information on supply current, refer to Power and Thermal Estimation and Management for MachXO3 Devices (FPGA-TN-02059). 

2. Assumes a test pattern with the following characteristics: all outputs are tri-stated, all inputs are configured as LVCMOS and held at VCCIO or GND, on-chip oscillator is off, on-chip PLL is off. 

3. Frequency = 0 MHz. 

4. TJ = 25 °C, power supplies at nominal voltage. 

5. Does not include pull-up/pull-down. 

6. To determine the MachXO3L/LF peak start-up current data, use the Power Calculator tool. 

## **3.10. Programming and Erase Supply Current – C/E Devices** 

**Table 3.9. Programming and Erase Supply Current – C/E Devices[1, 2, 3, 4]** 

|**Symbol**<br>~~a~~|**Parameter**<br>~~esa~~|**Device**<br>~~a~~|**Typ.4**<br>|**Units**<br>|
|---|---|---|---|---|
|ICC|Core Power Supply<br>~~esa~~<br>~~aa~~<br>~~a~~|LCMXO3L/LF-1300C 256 Ball Package<br>~~a~~|22.1<br>|mA<br>|
|||LCMXO3L/LF-2100C<br>~~aes~~|22.1<br>~~es~~|mA<br>~~es~~|
|||LCMXO3L/LF-2100C 324 Ball Package<br>~~es~~<br>~~es~~|26.8<br>~~es~~<br>~~es~~|mA<br>~~es~~<br>~~es~~|
|||LCMXO3L/LF-4300C<br>~~es~~<br>~~ee~~|26.8<br>~~es~~<br>~~ee~~|mA<br>~~es~~<br>~~ee~~|
|||LCMXO3L/LF-4300C 400 Ball Package<br>~~ee~~<br>~~es~~|33.2<br>~~ee~~<br>~~es~~|mA<br>~~ee~~<br>~~es~~|
|||LCMXO3L/LF-6900C<br>~~es~~<br>~~es~~<br>~~aa~~|33.2<br>~~es~~<br>~~es~~<br>|mA<br>~~es~~<br>~~es~~<br>|
|||LCMXO3L/LF-9400C<br>~~es~~<br>~~aa~~|39.6<br>~~es~~<br>|mA<br>~~es~~<br>|
|||LCMXO3L/LF-640E<br>~~aa~~|17.7<br>|mA<br>|
|||LCMXO3L/LF-1300E<br>~~aaes~~|17.7<br>~~es~~|mA<br>~~es~~|
|||LCMXO3L/LF-1300E 256 Ball Package<br>~~es~~<br>~~ee~~|18.3<br>~~es~~<br>~~ee~~|mA<br>~~es~~<br>~~ee~~|
|||LCMXO3L/LF-2100E<br>~~ee~~<br>~~es~~|18.3<br>~~ee~~<br>~~es~~|mA<br>~~ee~~<br>~~es~~|
|||LCMXO3L/LF-2100E 324 Ball Package<br>~~es~~<br>~~es~~<br>~~a~~|20.4<br>~~es~~<br>~~es~~<br>|mA<br>~~es~~<br>~~es~~<br>|
|||LCMXO3L/LF-4300E<br>~~es~~<br>~~a~~|20.4<br>~~es~~<br>|mA<br>~~es~~<br>|
|||LCMXO3L/LF-6900E<br>~~aes~~|23.9<br>~~es~~|mA<br>~~es~~|
|||LCMXO3L/LF-9400E<br>~~es~~<br>~~es~~|28.5<br>~~es~~<br>~~es~~|mA<br>~~es~~<br>~~es~~|
|ICCIO<br>~~a~~|Bank Power Supply5VCCIO= 2.5 V All devices|= 2.5 V All devices<br>~~es~~|0<br>~~es~~|mA<br>~~es~~|



© 2014-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

50 

FPGA-DS-02032-2.8 

**MachXO3 Family Data Sheet** 

## **Notes:** 

1. For further information on supply current, refer to Power and Thermal Estimation and Management for MachXO3 Devices (FPGA-TN-02059). 

2. Assumes all inputs are held at VCCIO or GND and all outputs are tri-stated. 

3. Typical user pattern. 

4. JTAG programming is at 25 MHz. 

5. TJ = 25 °C, power supplies at nominal voltage. 

6. Per bank. VCCIO = 2.5 V. Does not include pull-up/pull-down. 

## **3.11. sysI/O Recommended Operating Conditions** 

**Table 3.10. sysI/O Recommended Operating Conditions** 

|**Standard**<br>~~a~~<br>~~eee~~|**VCCIO (V)**<br>~~a~~<br>~~eeeee ee~~|**VCCIO (V)**<br>~~a~~<br>~~eeeee ee~~|**VCCIO (V)**<br>~~a~~<br>~~eeeee ee~~|**VREF (V)**<br>~~eeee~~|**VREF (V)**<br>~~eeee~~|**VREF (V)**<br>~~eeee~~|
|---|---|---|---|---|---|---|
||**Min.**<br>~~a~~<br>~~eee~~|**Typ.**<br>~~ee ee~~|**Max.**<br>~~ee~~|**Min.**<br>~~ee~~|**Typ.**<br>~~ee~~|**Max.**|
|LVCMOS 3.3<br>~~eee~~<br>~~GG~~|3.135<br>~~eee ~~<br>~~GG~~|3.3<br> ~~ee ee~~<br>~~GG~~|3.465<br>~~ee ~~<br>~~GG~~|—<br> ~~ee ~~<br>~~GG~~|—<br> ~~ee~~<br>~~GG~~|—<br>~~GG~~|
|LVCMOS 2.5<br>~~GG~~<br>~~po~~|2.375<br>~~GG~~<br>~~po~~|2.5<br>~~GG~~<br>~~po~~|2.625<br>~~GG~~<br>~~po~~|—<br>~~GG~~<br>~~po~~|—<br>~~GG~~<br>~~po~~|—<br>~~GG~~<br>~~po~~|
|LVCMOS 1.8<br>~~po~~<br>~~GG~~<br>~~pO~~|1.71<br>~~po~~<br>~~GG~~|1.8<br>~~po~~<br>~~GG~~|1.89<br>~~po~~<br>~~GG~~|—<br>~~po~~<br>~~GG~~|—<br>~~po~~<br>~~GG~~|—<br>~~po~~<br>~~GG~~|
|LVCMOS 1.5<br>~~GG~~<br>~~pO~~|1.425<br>~~GG~~|1.5<br>~~GG~~|1.575<br>~~GG~~|—<br>~~GG~~|—<br>~~GG~~|—<br>~~GG~~|
|LVCMOS 1.2<br>~~pO~~<br>~~ee~~|1.14<br>~~ee~~|1.2<br>~~GG~~|1.26<br>~~GG~~|—<br>~~GG~~|—|—|
|LVTTL<br>~~ee~~<br>~~po~~|3.135<br>~~ee ~~<br>~~po~~|3.3<br> ~~GG~~<br>~~po~~<br>~~DsGe~~|3.465<br>~~GG~~<br>~~po~~<br>~~DsGe~~|—<br>~~GG~~<br>~~po~~<br>~~Gs~~|—<br>~~po~~<br>~~Gs~~|—<br>~~po~~|
|LVDS251, 2<br>~~ee~~|2.375<br>~~ee~~|2.5<br>~~ee~~<br>~~DsGe~~|2.625<br>~~ee~~<br>~~DsGe~~|—<br>~~ee~~<br>~~Gs~~|—<br>~~ee~~<br>~~Gs~~|—<br>~~ee~~|
|LVDS331, 2<br>~~ee~~<br>~~GG~~<br>~~po~~|3.135<br>~~ee~~<br>~~GG~~|3.3<br>~~ee~~<br>~~DsGe~~<br>~~GG~~|3.465<br>~~ee~~<br>~~DsGe~~<br>~~GG~~|—<br>~~ee~~<br>~~Gs~~<br>~~GG~~|—<br>~~ee~~<br>~~Gs~~<br>~~GG~~|—<br>~~ee~~<br>~~GG~~|
|LVPECL1<br>~~GG~~<br>~~po~~|3.135<br>~~GG~~|3.3<br>~~GG~~|3.465<br>~~GG~~|—<br>~~GG~~|—<br>~~GG~~|—<br>~~GG~~|
|BLVDS1<br>~~po~~<br>~~ee~~|2.375<br>~~ee~~|2.5<br>~~eG~~|2.625<br>~~eG~~|—<br>~~eG~~|—|—|
|MIPI3<br>~~ee~~<br>~~po~~<br>~~ee~~|2.375<br>~~ee ~~<br>~~po~~<br>|2.5<br> ~~eG~~<br>~~po~~<br>~~eG~~<br>|2.625<br>~~eG~~<br>~~po~~<br>~~eG~~<br>|—<br>~~eG~~<br>~~po~~<br>|—<br>~~po~~<br>|—<br>~~po~~<br>|
|MIPI_LP3<br>~~ee~~<br>~~ee~~|1.14<br>~~ee~~<br>|1.2<br>~~ee~~<br>~~eG~~<br>|1.26<br>~~ee~~<br>~~eG~~<br>|—<br>~~ee~~<br>|—<br>~~ee~~<br>|—<br>~~ee~~<br>|
|LVCMOS25R33<br>~~ee~~<br>~~ee~~|3.135<br>~~ee~~<br>~~GG~~|3.3<br>~~ee~~<br>~~eG~~<br>~~GG~~|3.6<br>~~ee~~<br>~~eG~~<br>~~GG~~|1.1<br>~~ee~~<br>~~GG~~|1.25<br>~~ee~~<br>~~GG~~|1.4<br>~~ee~~<br>~~GG~~|
|LVCMOS18R33<br>~~ee~~<br>~~ee~~|3.135<br>~~GG~~<br>~~ee~~|3.3<br>~~eG~~<br>~~GG~~<br>~~GG~~|3.6<br>~~eG~~<br>~~GG~~<br>~~GG~~|0.75<br>~~GG~~<br>~~GG~~|0.9<br>~~GG~~|1.05<br>~~GG~~|
|LVCMOS18R25<br>~~ee~~<br>~~ee~~|2.375<br>~~ee~~<br>~~ee~~|2.5<br>~~GG~~<br>~~GG~~|2.625<br>~~GG~~<br>~~GG~~|0.75<br>~~GG~~<br>~~GG~~|0.9|1.05|
|LVCMOS15R33<br>~~ee~~<br>~~po~~|3.135<br>~~ee~~<br>~~po~~|3.3<br>~~GG~~<br>~~po~~|3.6<br>~~GG~~<br>~~po~~|0.6<br>~~GG~~<br>~~po~~|0.75<br>~~po~~|0.9<br>~~po~~|
|LVCMOS15R25<br>~~GG~~<br>~~ee~~|2.375<br>~~GG~~<br>~~GG~~|2.5<br>~~GG~~<br>~~GG~~|2.625<br>~~GG~~<br>~~GG~~|0.6<br>~~GG~~<br>~~GG~~|0.75<br>~~GG~~<br>~~GG~~|0.9<br>~~GG~~<br>~~GG~~|
|LVCMOS12R334<br>~~GG~~<br>~~ee~~<br>~~ee~~|3.135<br>~~GG~~<br>~~GG~~<br>~~GG~~|3.3<br>~~GG~~<br>~~GG~~<br>~~GG~~|3.6<br>~~GG~~<br>~~GG~~<br>~~GG~~|0.45<br>~~GG~~<br>~~GG~~<br>~~GG~~|0.6<br>~~GG~~<br>~~GG~~<br>~~GG~~|0.75<br>~~GG~~<br>~~GG~~<br>~~GG~~|
|LVCMOS12R254<br>~~ee~~<br>~~ee~~|2.375<br>~~GG~~<br>~~GG~~|2.5<br>~~GG~~<br>~~GG~~|2.625<br>~~GG~~<br>~~GG~~|0.45<br>~~GG~~<br>~~GG~~|0.6<br>~~GG~~<br>~~GG~~|0.75<br>~~GG~~<br>~~GG~~|
|LVCMOS10R334<br>~~ee~~<br>~~GG~~|3.135<br>~~GG~~<br>~~GG~~|3.3<br>~~GG~~<br>~~GG~~|3.6<br>~~GG~~<br>~~GG~~|0.35<br>~~GG~~<br>~~GG~~|0.5<br>~~GG~~<br>~~GG~~|0.65<br>~~GG~~<br>~~GG~~|
|LVCMOS10R254<br>~~GG~~<br>~~ee~~|2.375<br>~~GG~~<br>~~ee ~~|2.5<br>~~GG~~<br> ~~GG~~|2.625<br>~~GG~~<br>~~GG~~|0.35<br>~~GG~~<br>~~GG~~|0.5<br>~~GG~~|0.65<br>~~GG~~|



## **Notes:** 

1. Inputs on-chip. Outputs are implemented with the addition of external resistors. 

2. For the dedicated LVDS buffers. 

3. Requires the addition of external resistors. 

4. Supported only for inputs and BIDIs for –6 speed grade devices. 

© 2014-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02032-2.8 

51 

**MachXO3 Family Data Sheet** 

## **3.12. sysI/O Single-Ended DC Electrical Characteristics** 

**Table 3.11. sysI/O Single-Ended DC Electrical Charateristics[1, 2, 4]** 

|**Standard**<br>~~ee~~|**VIL**<br>~~ee~~<br>~~ee~~|**VIL**<br>~~ee~~<br>~~ee~~|**VIH**<br>~~ee~~<br>~~ee~~<br>~~ee ee~~|**VIH**<br>~~ee~~<br>~~ee~~<br>~~ee ee~~|**VOL Max.**<br>**(V)**<br>~~ee~~<br>~~ee~~|**VOH Min. (V)**<br>~~ee~~<br>~~ee~~|**IOL Max.5**<br>**(mA)**<br>~~ee~~|**IOH Max.5 **<br>**(mA)**<br>~~ee~~|
|---|---|---|---|---|---|---|---|---|
||**Min.(V)3**<br>~~ee~~<br>~~ee~~|**Max.(V)**<br>~~ee~~<br>~~ee~~|**Min.(V)**<br>~~ee~~<br>~~ee~~<br>~~ee ee~~|**Max.(V)**<br>~~ee~~<br>~~ee~~<br>~~ee~~|||||
|LVCMOS 3.3<br>LVTTL<br>~~ee~~|–0.3<br>~~ee~~|0.8<br>~~ee~~|2.0<br>~~ee~~<br>~~ee ee~~|3.6<br>~~ee~~<br>~~ee~~|0.4<br>~~ee~~<br>~~ee~~<br>~~es~~|VCCIO – 0.4<br>~~ee~~<br>~~ee~~<br>~~ee~~|4<br>~~ee~~|–4<br>~~ee~~|
||||||||8<br>~~po~~|–8<br>~~po~~|
||||||||12<br>~~po~~<br>~~po~~|–12<br>~~po~~<br>~~po~~|
||||||||16<br>~~a~~<br>~~ee~~|–16<br>~~a~~|
||||||0.2<br>~~es~~|VCCIO – 0.2<br>~~ee~~|0.1<br>~~a~~<br>~~ee~~|–0.1<br>~~a~~|
|LVCMOS 2.5|–0.3|0.7|1.7|3.6|0.4<br>~~es ~~|VCCIO – 0.4<br> ~~ee~~|4<br>~~a~~<br>~~ee~~|–4<br>~~a~~|
||||||||8<br>~~po~~|–8<br>~~po~~|
||||||||12<br>~~po~~<br>~~Po~~|–12<br>~~po~~<br>~~Po~~|
||||||||16<br>~~Po~~<br>~~ee~~|–16<br>~~Po~~<br>~~ee~~|
||||||0.2<br>~~a ee~~|VCCIO – 0.2<br>~~ee~~|0.1<br>~~ee~~|–0.1<br>~~ee~~|
|LVCMOS 1.8|–0.3|0.35 VCCIO|0.65 VCCIO|3.6|0.4<br>~~ee~~|VCCIO – 0.4<br>~~ee~~|4|–4|
||||||||8<br>~~ee~~|–8<br>~~ee~~|
||||||||12<br>~~ee~~<br>~~Po~~<br>~~ee~~|–12<br>~~ee~~<br>~~Po~~|
||||||0.2<br>~~ee~~|VCCIO – 0.2<br>~~ee~~|0.1<br>~~Po~~<br>~~ee~~|–0.1<br>~~Po~~|
|LVCMOS 1.5|–0.3|0.35 VCCIO|0.65 VCCIO|3.6|0.4<br>~~ee~~|VCCIO – 0.4<br>~~ee~~|4<br>~~Po~~<br>~~ee~~|–4<br>~~Po~~|
||||||||8|–8|
||||||0.2<br>~~a ee~~|VCCIO – 0.2<br>~~ee~~|0.1<br>~~ee~~|–0.1<br>~~ee~~|
|LVCMOS 1.2<br>~~po~~|–0.3|0.35 VCCIO|0.65 VCCIO|3.6|0.4<br>~~es~~|VCCIO – 0.4<br>~~ee~~|4|–2|
||||||||8<br>~~ee~~|–6|
||||||0.2<br>~~es~~|VCCIO – 0.2<br>~~ee~~|0.1<br>~~ee~~|–0.1|
|LVCMOS25R33<br>~~po~~<br>~~po~~|–0.3|VREF – 0.1|VREF+0.1|3.6|NA<br>~~es~~|NA<br>~~ee~~|NA<br>~~ee~~|NA|
|LVCMOS18R33<br>~~po~~<br>~~po~~|–0.3|VREF – 0.1|VREF+0.1|3.6|NA<br>~~es~~|NA<br>~~ee ~~|NA<br> ~~ee~~|NA|
|LVCMOS18R25<br>~~po~~<br>~~ee~~|–0.3<br>~~ee~~|VREF – 0.1|VREF+0.1<br>~~GG~~|3.6<br>~~GG~~|NA<br>~~GG~~|NA|NA<br>~~I~~|NA|
|LVCMOS15R33<br>~~ee~~<br>~~eG~~|–0.3<br>~~ee~~<br>~~eG~~|VREF – 0.1<br>~~eG~~|VREF+0.1<br>~~GG~~<br>~~GO~~|3.6<br>~~GG~~<br>~~GO~~|NA<br>~~GG~~<br>~~GO~~|NA|NA<br>~~I~~|NA|
|LVCMOS15R25<br>~~eG~~<br>~~ee~~|–0.3<br>~~eG~~<br>~~ee~~|VREF – 0.1<br>~~eG~~<br>~~GO~~|VREF+0.1<br>~~GO~~<br>~~GO~~|3.6<br>~~GO~~<br>~~GO~~|NA<br>~~GO~~<br>~~GO~~|NA<br>~~GO~~|NA<br>~~GO~~|NA<br>~~GO~~|
|LVCMOS12R33<br>~~ee~~<br>~~a~~<br>~~pf~~|–0.3<br>~~ee~~<br>~~pf~~<br>~~|~~|VREF – 0.1<br>~~GO~~|VREF+0.1<br>~~GO~~|3.6<br>~~GO~~|0.40<br>~~GO~~|NA Open Drain<br>~~GO~~|24, 16, 12,<br>8, 4<br>~~GO~~|NA Open<br>Drain<br>~~GO~~|
|LVCMOS12R25<br>~~a~~<br>~~pf~~|–0.3<br>~~pf~~<br>~~|~~|VREF – 0.1|VREF+0.1|3.6|0.40|NA Open Drain|16, 12, 8, 4|NA Open<br>Drain|
|LVCMOS10R33<br>~~pf~~<br>~~a~~|–0.3<br>~~pf~~<br>~~|~~|VREF – 0.1|VREF+0.1|3.6|0.40|NA Open Drain|24, 16, 12,<br>8, 4|NA Open<br>Drain|
|LVCMOS10R25<br>~~a~~<br>~~a~~|-0.3<br>~~eee~~|VREF – 0.1<br>~~eee~~|VREF+0.1<br>~~eee~~|3.6<br>~~eee~~|0.40<br>~~eee~~|NA Open Drain<br>~~eee~~|16, 12, 8, 4<br>~~eee~~|NA Open<br>Drain<br>~~eee~~|



## **Notes:** 

1. MachXO3L/LF devices allow LVCMOS inputs to be placed in I/O banks where VCCIO is different from what is specified in the applicable JEDEC specification. This is referred to as a ratioed input buffer. In a majority of cases this operation follows or exceeds the applicable JEDEC specification. The cases where MachXO3L/LF devices do not meet the relevant JEDEC specification are documented in the table below. 

2. MachXO3L/LF devices allow for LVCMOS referenced I/Os which follow applicable JEDEC specifications. For more details about mixed mode operation please refer to please refer to MachXO3 sysI/O Usage Guide (FPGA-TN-02047). 

3. The dual function I[2] C pins SCL and SDA are limited to a VIL min of –0.25 V or to –0.3 V with a duration of <10 ns. 

4. VCCIO represents the typical value as listed in the following tables for the respective I/O standard. 

5. For electromigration, the average DC current sourced or sinked by I/O pads between two consecutive VCCIO or GND pad connections, or between the last VCCIO or GND in an I/O bank and the end of an I/O bank, shall not exceed a maximum of n * 8 mA. “n” is the number of I/O pads between the two consecutive bank VCCIO or GND connections or between the last VCCIO and GND in a bank and the end of a bank. I/O Grouping can be found in the Data Sheet Pin Tables, which can also be generated from the Lattice Diamond software. 

© 2014-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

52 

FPGA-DS-02032-2.8 

**MachXO3 Family Data Sheet** 

## **3.13. sysI/O Differential Electrical Characteristics** 

The LVDS differential output buffers are available on the top side of the MachXO3L/LF PLD family. 

## **3.13.1. LVDS** 

Over recommended operating conditions. 

**Table 3.12. LVDS** 

|**Parameter Symbol**<br>~~sO~~<br>~~a~~<br>~~oe~~|**Parameter Description**<br>~~sO~~<br>~~a~~<br>~~oe~~|**Test Conditions**<br>~~sO~~<br>~~ee eee~~<br>|**Min.**<br>~~sO~~<br>~~eee~~<br>|**Typ. **<br>~~sO~~<br>~~eee~~<br>|**Max.**<br>~~sO~~<br>~~eee~~<br>|**Units**<br>~~sO~~<br>~~eee~~<br>|
|---|---|---|---|---|---|---|
|VINP, VINM<br>~~sO~~<br>~~a~~<br>~~oea~~|Input Voltage<br>(Commercial/Industrial)<br>~~sO~~<br>~~a~~<br>~~oe~~|VCCIO= 3.3 V<br>~~sO~~<br>~~ee eee~~<br>|0<br>~~sO~~<br>~~eee~~<br>|—<br>~~sO~~<br>~~eee~~<br>|2.605<br>~~sO~~<br>~~eee~~<br>|V<br>~~sO~~<br>~~eee~~<br>|
|||VCCIO= 2.5 V<br>~~ee eee~~<br>|0<br>~~eee~~<br>|—<br>~~eee~~<br>|2.05<br>~~eee~~<br>|V<br>~~eee~~<br>|
||Input Voltage<br>(Automotive)<br>~~a~~<br>~~oea~~|VCCIO= 3.3 V<br>~~ee eee~~<br>~~ee~~|0<br>~~eee~~<br>~~ee~~|—<br>~~eee~~<br>~~ee~~|2.6<br>~~eee~~<br>~~ee~~|V<br>~~eee~~<br>~~ee~~|
|||VCCIO= 2.5 V<br>~~ee~~|0<br>~~ee~~|—<br>~~ee~~|2.0<br>~~ee~~|V<br>~~ee~~|
|VTHD<br>~~oea~~<br>~~i~~<br>~~a~~|Differential Input Threshold<br>~~oea~~<br>~~i~~<br>|—<br>~~ee~~<br>~~i~~<br>|±100<br>~~ee~~<br>~~es~~<br>~~—ry——ry—r—~~<br>|—<br>~~ee~~<br>~~—ry——ry—r—~~<br>|—<br>~~ee~~<br>~~—ry——ry—r—~~<br>|mV<br>~~ee~~<br>~~—ry——ry—r—~~<br>|
|VCM<br>~~i~~<br>~~a~~|Input Common Mode Voltage<br>~~i~~<br>|VCCIO= 3.3 V<br>~~ee~~<br>~~i~~<br>|0.05<br>~~ee~~<br>~~es~~<br>~~—ry——ry—r—~~<br>|—<br>~~ee~~<br>~~—ry——ry—r—~~<br>|2.6<br>~~ee~~<br>~~—ry——ry—r—~~<br>|V<br>~~ee~~<br>~~—ry——ry—r—~~<br>|
|||VCCIO= 2.5 V<br>~~ee~~<br>~~i~~<br>|0.05<br>~~ee~~<br>~~es~~<br>~~—ry——ry—r—~~<br>|—<br>~~ee~~<br>~~—ry——ry—r—~~<br>|2.0<br>~~ee~~<br>~~—ry——ry—r—~~<br>|V<br>~~ee~~<br>~~—ry——ry—r—~~<br>|
|IIN<br>~~i~~<br>~~a~~|Input current<br>~~i~~<br>|Power on<br>~~i~~<br>|—<br>~~es~~<br>~~—ry——ry—r—~~<br>|—<br>~~—ry——ry—r—~~<br>|±10<br>~~—ry——ry—r—~~<br>|µA<br>~~—ry——ry—r—~~<br>|
|VOH<br>~~aeG~~<br>~~es~~|Output high voltage for VOPor VOM<br>~~eG~~|RT= 100 Ω<br>~~eG~~|—<br>~~—ry——ry—r—~~<br>~~eG~~|1.375<br>~~—ry——ry—r—~~<br>~~eG~~|—<br>~~—ry——ry—r—~~<br>~~eG~~|V<br>~~—ry——ry—r—~~<br>~~eG~~|
|VOL<br>~~es~~<br>~~a~~|Output low voltage for VOPor VOM|RT= 100 Ω|0.90|1.025|—|V|
|VOD<br>~~es~~<br>~~a~~|Output voltage differential|(VOP- VOM), RT= 100 Ω|250|350|450|mV|
|VOD<br>~~aa~~|Change in VODbetween high and low<br>~~G~~|—<br>~~G~~|—|—|50|mV|
|VOS<br>~~a~~<br>~~aa~~|Output voltage offset<br>(Commercial/Industrial)<br>~~G~~<br>~~a~~|(VOP- VOM)/2, RT= 100 Ω<br>~~G~~<br>~~ee~~|1.125<br>~~ee~~|1.20|1.395|V|
||Output voltage offset<br>(Automotive)<br>~~a~~|(VOP- VOM)/2, RT= 100 Ω<br>~~ee~~|1.10<br>~~ee~~|1.20|1.395|V|
|VOS<br>~~aa~~<br>~~a~~|Change in VOSbetween H and L<br>~~a~~|—<br>~~ee~~|—<br>~~ee~~|—|50|mV|
|IOSD<br>~~a~~<br>~~a~~|Output short circuit current|VOD= 0 V driver outputs<br>shorted|—|—|24|mA|



## **3.13.2. LVDS Emulation** 

MachXO3L/LF devices can support LVDS outputs via emulation (LVDS25E). The output is emulated using complementary LVCMOS outputs in conjunction with resistors across the driver outputs on all devices. The scheme shown in Figure 3.1 is one possible solution for LVDS standard implementation. Resistor values in Figure 3.1 are industry standard values for 1% resistors. 

**==> picture [338 x 155] intentionally omitted <==**

**----- Start of picture text -----**<br>
VCCIO = 2.5<br>158<br>8mA<br>Zo = 100<br>+<br>VCCIO = 2.5  158 140 100 –<br>8mA<br>On-chip Off-chip Off-chip On-chip<br>Emulated<br>LVDS<br>Buffer<br>Note: All resistors are ±1%.<br>**----- End of picture text -----**<br>


**Figure 3.1. LVDS Using External Resistors (LVDS25E)** 

© 2014-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02032-2.8 

53 

**MachXO3 Family Data Sheet** 

Over recommended operating conditions. 

**Table 3.13. LVDS25E DC Conditions** 

|**Parameter**|**Description**|**Typ. **|**Units**|
|---|---|---|---|
|ZOUT|Output impedance|20|Ω|
|RS|Driver series resistor|158|Ω|
|RP|Driverparallel resistor|140|Ω|
|RT|Receiver termination|100|Ω|
|VOH|Output high voltage|1.43|V|
|VOL|Output low voltage|1.07|V|
|VOD|Output differential voltage|0.35|V|
|VCM|Output common mode voltage|1.25|V|
|ZBACK|Back impedance|100.5|Ω|
|IDC|DC output current|6.03|mA|



## **3.13.3. BLVDS** 

**==> picture [471 x 275] intentionally omitted <==**

**----- Start of picture text -----**<br>
The MachXO3L/LF family supports the BLVDS standard through emulation. The output is emulated using<br>complementary LVCMOS outputs in conjunction with resistors across the driver outputs. The input standard is<br>supported by the LVDS differential input buffer. BLVDS is intended for use when multi-drop and bi-directional multi-<br>point differential signaling is required. The scheme shown in Figure 3.2 is one possible solution for bi-directional<br>multi-point differential signals.<br>Heavily loaded backplane, effective Zo ~ 45 to 90  Ω  differential<br>2.5 V 2.5 V<br>80 45-90  Ω 45-90  Ω<br>16 mA 16 mA<br>80<br>2.5 V 2.5 V<br>80<br>16 mA 16 mA<br>80 80 80 80<br>.  . .<br>– –<br>sh Toe<br>– –<br>2.5 V 2.5 V 2.5 V 2.5 V<br>16 mA 16 mA 16 mA 16 mA<br>AL Y KA Y<br>+<br>+<br>+<br>+<br>**----- End of picture text -----**<br>


**Figure 3.2. BLVDS Multi-point-Output Example** 

© 2014-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02032-2.8 

54 

**MachXO3 Family Data Sheet** 

Over recommended operating conditions. 

**Table 3.14. BLVDS DC Condition** 

|**Symbol**<br>~~acrs~~|**Description**<br>~~PC~~<br>~~crs~~|**Nominal**<br>~~PC~~<br>~~crs~~<br>~~eee~~|**Nominal**<br>~~PC~~<br>~~crs~~<br>~~eee~~|**Units**<br>~~crs~~|
|---|---|---|---|---|
|||**Zo = 45**<br>~~PC~~<br>~~crs~~|**Zo = 90**<br>~~crs~~<br>~~eee~~||
|ZOUT<br>~~a crs~~<br>~~ee~~|Output impedance<br>~~PC~~<br>~~crs~~<br>~~ee~~|20<br>~~PC~~<br>~~crs~~<br>~~ee~~|20<br>~~crs~~<br>~~eee~~<br>~~ee~~|Ω<br>~~crs~~<br>~~ee~~|
|RS<br>~~ee~~<br>~~Be~~|Driver series resistance<br>~~ee~~<br>~~Be~~|80<br>~~ee~~<br>~~Be~~|80<br>~~ee~~<br>~~Be~~|Ω<br>~~ee~~<br>~~Be~~|
|RTLEFT<br>~~ee~~|Left end termination<br>~~ee~~|45<br>~~ss~~|90<br>~~ss~~|Ω|
|RTRIGHT<br>~~ee~~<br>~~rs~~|Right end termination<br>~~ee~~<br>~~rs~~|45<br>~~ss~~<br>~~rs~~|90<br>~~ss~~<br>~~rs~~|Ω<br>~~rs~~|
|VOH<br>~~rs~~<br>~~a~~<br>~~ee~~|Output high voltage<br>~~rs~~|1.376<br>~~rs~~|1.480<br>~~rs~~|V<br>~~rs~~|
|VOL<br>~~a~~<br>~~ee~~<br>~~a~~|Output low voltage<br>|1.124<br>|1.020<br>|V<br>|
|VOD<br>~~ee~~<br>~~a~~|Output differential voltage<br>|0.253<br>|0.459<br>|V<br>|
|VCM<br>~~aBe~~<br>~~eeer~~|Output common mode voltage<br>~~Be~~<br>~~er~~|1.250<br>~~Be~~<br>~~er~~<br>~~rs~~|1.250<br>~~Be~~<br>~~er~~|V<br>~~Be~~<br>~~er~~|
|IDC<br>~~eeer~~|DC output current<br>~~er~~|11.236<br>~~er~~<br>~~rs~~|10.204<br>~~er~~|mA<br>~~er~~|



**Note:** For input buffer, see LVDS table. 

## **3.13.4. LVPECL** 

The MachXO3L/LF family supports the differential LVPECL standard through emulation. This output standard is emulated using complementary LVCMOS outputs in conjunction with resistors across the driver outputs on all the devices. The LVPECL input standard is supported by the LVDS differential input buffer. The scheme shown in Differential LVPECL is one possible solution for point-to-point signals. 

**==> picture [383 x 135] intentionally omitted <==**

**----- Start of picture text -----**<br>
V CCIO  = 3.3 V<br>l<br>93  Ω<br>16 mA a a<br>> l +<br>V CCIO  = 3.3 V<br>196  Ω 100  Ω<br>–<br>93  Ω<br>16 mA<br>Transmission line, Zo = 100  Ω   differential<br>C) > z= l Z<br>On-chip Off-chip  Off-chip  On-chip<br>Ps <—__ __|—__ l ><br>**----- End of picture text -----**<br>


**Figure 3.3. Differential LVPECL** 

© 2014-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02032-2.8 

55 

**MachXO3 Family Data Sheet** 

Over recommended operating conditions. 

**Table 3.15. LVPECL DC Conditions** 

|**Symbol**|**Description**|**Nominal**|**Units**|
|---|---|---|---|
|ZOUT|Output impedance|20|Ω|
|RS|Driver series resistor|93|Ω|
|RP|Driver parallel resistor|196|Ω|
|RT|Receiver termination|100|Ω|
|VOH|Output high voltage|2.05|V|
|VOL|Output low voltage|1.25|V|
|VOD|Output differential voltage|0.80|V|
|VCM|Output common mode voltage|1.65|V|
|ZBACK|Back impedance|100.5|Ω|
|IDC|DC output current|12.11|mA|



**Note** : For input buffer, see LVDS table. 

For further information on LVPECL, BLVDS and other differential interfaces, see details of additional technical documentation at the end of the data sheet. 

## **3.13.5. MIPI D-PHY Emulation** 

MachXO3L/LF devices can support MIPI D-PHY unidirectional HS (High Speed) and bidirectional LP (Low Power) inputs and outputs via emulation. In conjunction with external resistors High Speed I/Os use the LVDS25E buffer and Low Power I/Os use the LVCMOS buffers. The scheme shown in Figure 3.4 is one possible solution for MIPI D-PHY Receiver implementation. The scheme shown in Figure 3.5 is one possible solution for MIPI D-PHY Transmitter implementation. 

**==> picture [150 x 277] intentionally omitted <==**

**----- Start of picture text -----**<br>
| MIPI D-PHY Input<br>|<br>|<br>LVCMOS<br>|<br>| LVCMOS<br>|<br>|<br>|<br>Dp<br>|<br>LVDS<br>|<br>Dn<br>|<br>|<br>|<br>| LVCMOS<br>|<br>LVCMOS<br>RT<br>RT<br>**----- End of picture text -----**<br>


**Figure 3.4. MIPI D-PHY Input Using External Resistors** 

© 2014-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02032-2.8 

56 

**MachXO3 Family Data Sheet** 

Over recommended operating conditions. 

**Table 3.16. MIPI DC Conditions** 

|~~sD~~|**Description**<br>~~sD~~|**Min.**<br>~~sD~~|**Typ. **<br>~~sD~~|**Max.**<br>~~sD~~|**Units**<br>~~sD~~|
|---|---|---|---|---|---|
|**Receiver**<br>~~sD~~<br>~~Pt~~||||||
|**External Termination**<br>~~Pt~~<br>~~PT~~<br>~~aesee~~<br>~~ee~~||||||
|RT<br>~~PT~~<br>~~a~~|1% external resistor with VCCIO=2.5 V<br>~~PT~~<br>~~es~~|—<br>~~PT~~<br>~~ee~~|50<br>~~PT~~|—<br>~~PT~~<br>~~ee~~|Ω<br>~~PT~~<br>~~ee~~|
||1% external resistor with VCCIO=3.3 V<br>~~es~~<br>~~pT~~|—<br>~~ee~~<br>~~pT~~|50<br>~~pT~~|—<br>~~ee~~<br>~~pT~~|Ω<br>~~ee~~<br>~~pT~~|
|**High Speed**<br>~~a es ee~~<br>~~ee~~<br>~~pT~~<br>~~PT~~<br>~~eeee~~||||||
|VCCIO<br>~~PT~~<br>~~ee~~<br>~~a~~|VCCIOof the Bank with LVDS Emulated input buffer<br>~~PT~~<br>~~ee~~<br>~~a~~|—<br>~~PT~~<br>~~ee~~|2.5<br>~~PT~~|—<br>~~PT~~|V<br>~~PT~~|
||VCCIOof the Bank with LVDS Emulated input buffer<br>~~ee~~<br>~~a~~|—<br>~~ee~~|3.3|—|V|
|VCMRX<br>~~ee~~<br>~~a~~<br>~~I~~|Common-mode voltage HS receive mode<br>~~ee ~~<br>~~a~~<br>~~I~~|150<br> ~~ee~~<br>~~I~~|200<br>~~I~~|250<br>~~I~~|mV<br>~~I~~|
|VIDTH<br>~~I~~<br>~~sO~~|Differential input high threshold<br>~~I~~<br>~~sO~~|—<br>~~I~~<br>~~sO~~|—<br>~~I~~<br>~~sO~~|100<br>~~I~~<br>~~sO~~|mV<br>~~I~~<br>~~sO~~|
|VIDTL<br>~~ee~~<br>~~ee~~|Differential input low threshold<br>~~ee~~|–100<br>~~ee~~|—<br>~~ee~~|—<br>~~ee~~|mV<br>~~ee~~|
|VIHHS<br>~~ee~~<br>~~es~~|Single-ended input high voltage|—|—|300|mV|
|VILHS<br>~~ee~~<br>~~es~~|Single-ended input low voltage|100|—|—|mV|
|ZID<br>~~es~~<br>~~DO~~|Differential input impedance<br>~~DO~~|80<br>~~DO~~|100<br>~~DO~~|120<br>~~DO~~|Ω<br>~~DO~~|
|**Low Power**<br>~~DO~~<br>~~PT~~||||||
|VCCIO<br>~~PT~~|VCCIOof the Bank with LVCMOS12D 6 mA drive<br>bidirectional I/O buffer<br>~~PT~~|—<br>~~PT~~|1.2<br>~~PT~~|—<br>~~PT~~|V<br>~~PT~~|
|VIH<br>~~I~~|Logic 1 input voltage<br>~~I~~|—<br>~~I~~|—<br>~~I~~|0.88<br>~~I~~|V<br>~~I~~|
|VIL<br>~~I~~<br>~~sO~~|Logic 0 input voltage, not in ULP State<br>~~I~~<br>~~sO~~|0.55<br>~~I~~<br>~~sO~~|—<br>~~I~~<br>~~sO~~|—<br>~~I~~<br>~~sO~~|V<br>~~I~~<br>~~sO~~|
|VHYST<br>~~ee~~|Input hysteresis<br>~~ee~~|25<br>~~ee~~|—<br>~~ee~~|—<br>~~ee~~|mV<br>~~ee~~|



MIPI D-PHY Output 

**==> picture [163 x 197] intentionally omitted <==**

**----- Start of picture text -----**<br>
LVCMOS |<br>RL<br>LVCMOS |<br>|<br>|<br>|<br>RH Dp<br>LVDS |<br>RH Dn<br>|<br>|<br>|<br>LVCMOS<br>|<br>RL<br>LVCMOS<br>**----- End of picture text -----**<br>


**Figure 3.5. MIPI D-PHY Output Using External Resistors** 

© 2014-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02032-2.8 

57 

**MachXO3 Family Data Sheet** 

Over recommended operating conditions. 

**Table 3.17. MIPI D-PHY Output DC Conditions** 

|~~es~~|**Description**<br>|**Min.**<br>|**Typ. **<br>|**Max.**<br>|**Units**<br>|
|---|---|---|---|---|---|
|**Transmitter**<br>~~es|~~<br>~~Cn~~||||||
|**External Termination**<br>~~|~~<br>~~Cn~~<br>~~eeesee~~<br>~~ee~~||||||
|RL<br>~~Cn~~<br>~~ee~~<br>~~|~~|1% external resistor with VCCIO= 2.5 V<br>~~es~~|—<br>~~ee~~|50|—<br>~~ee~~|Ω<br>~~ee~~|
||1% external resistor with VCCIO= 3.3 V<br>~~es~~<br>~~—__}~~|—<br>~~ee~~<br>~~—__}|}~~|50<br>~~ee~~<br>~~|}~~|—<br>~~ee~~<br>~~ee~~<br>~~|_~~|~~ee~~<br>~~ee~~<br>~~|_~~|
|RH<br>~~ee ~~<br>~~|~~<br>~~Cn~~|1% external resistor with performance up to 800<br>Mbps or with performance up 900 Mbps when<br>VCCIO= 2.5 V<br> ~~es ~~<br>~~ee~~<br>~~—__}~~|—<br> ~~ee~~<br>~~ee~~<br>~~—__}|}~~|330<br>~~ee~~<br>~~ee~~<br>~~|}~~|—<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~|_~~|Ω<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~|_~~|
||1% external resistor with performance between<br>800 Mbps to 900 Mbps when VCCIO= 3.3 V<br>~~ee~~<br>~~—__}~~<br>~~Cn~~|—<br>~~ee~~<br>~~—__}|}~~|464<br>~~ee~~<br>~~ee~~<br>~~|}~~|—<br>~~ee~~<br>~~ee~~<br>~~|_~~|Ω<br>~~ee~~<br>~~ee~~<br>~~|_~~|
|**High Speed**<br>~~ee ee~~<br>~~|~~<br>~~—__} |} |_~~<br>~~Cn~~<br>~~——————EE~~||||||
|VCCIO<br>~~Cn~~<br>~~——————EE~~<br>~~ee~~|VCCIOof the Bank with LVDS Emulated output<br>buffer<br>~~Cn~~<br>~~——————EE~~<br>|—<br>~~——————EE~~<br>~~ee~~<br>|2.5<br>~~——————EE~~<br>~~ee~~<br>|—<br>~~——————EE~~<br>~~ee~~<br>|V<br>~~——————EE~~<br>~~ee~~<br>|
||VCCIOof the Bank with LVDS Emulated output<br>buffer<br>~~——————EE~~<br>~~ee~~<br>|—<br>~~——————EE~~<br>~~ee~~<br>~~ee~~<br>|3.3<br>~~——————EE~~<br>~~ee~~<br>~~ee~~<br>|—<br>~~——————EE~~<br>~~ee~~<br>~~ee~~<br>|V<br>~~——————EE~~<br>~~ee~~<br>~~ee~~<br>|
|VCMTX<br>~~——————EE~~<br>~~ee~~<br>~~rs~~|HS transmit static common mode voltage<br>~~——————EE~~<br>~~ee~~<br>~~eG~~|150<br>~~——————EE~~<br>~~ee~~<br>~~ee~~<br>~~eG~~|200<br>~~——————EE~~<br>~~ee~~<br>~~ee~~<br>~~eG~~|250<br>~~——————EE~~<br>~~ee~~<br>~~ee~~<br>~~eG~~|mV<br>~~——————EE~~<br>~~ee~~<br>~~ee~~<br>~~eG~~|
|VOD<br>~~ee~~<br>~~rs~~|HS transmit differential voltage<br>~~eG~~|140<br>~~ee~~<br>~~eG~~|200<br>~~ee~~<br>~~eG~~|270<br>~~ee~~<br>~~eG~~|mV<br>~~ee~~<br>~~eG~~|
|VOHHS<br><br>~~rs~~<br>~~ss~~<br>~~re~~|HS output high voltage<br>~~eG~~<br>~~ss~~|—<br>~~eG~~<br>~~ss~~|—<br>~~eG~~<br>~~ss~~|360<br>~~eG~~<br>~~ss~~|V<br>~~eG~~<br>~~ss~~|
|ZOS<br>~~ss~~<br>~~re~~|Single ended output impedance<br>~~ss~~|—<br>~~ss~~|50<br>~~ss~~|—<br>~~ss~~|Ω<br>~~ss~~|
|ZOS<br>~~re~~<br>~~ee~~<br>~~Cn~~|Single ended output impedance mismatch<br>~~ee~~|—<br>~~ee~~|—<br>~~ee~~|10<br>~~ee~~|%<br>~~ee~~|
|**Low Power**<br>~~ee~~<br>~~Cn~~<br>~~ee~~<br>~~ee~~||||||
|VCCIO<br>~~Cn~~<br>~~a ee~~<br>~~ee~~<br>~~es~~|VCCIOof the Bank with LVCMOS12D 6 mA drive<br>bidirectional I/O buffer<br>~~ee~~<br>~~es~~<br>|—<br>~~ee~~<br>~~ee~~<br>~~Gs~~<br>|1.2<br>~~ee~~<br>~~ee~~<br>~~Gs~~<br>|—<br>~~ee~~<br>~~ee~~<br>~~Gs~~<br>|V<br>~~ee~~<br>|
|VOH<br>~~a ee~~<br>~~ee~~<br>~~es~~|Output high level<br>~~ee~~<br>~~es~~<br>|1.1<br>~~ee~~<br>~~ee~~<br>~~Gs~~<br>|1.2<br>~~ee~~<br>~~ee~~<br>~~Gs~~<br>|1.3<br>~~ee~~<br>~~ee~~<br>~~Gs~~<br>|V<br>~~ee~~<br>|
|VOL<br>~~ee~~<br>~~es~~<br>~~a~~|Output low level<br>~~es~~<br>~~eG~~|–50<br>~~ee~~<br>~~Gs~~<br>~~eG~~|0<br>~~ee~~<br>~~Gs~~<br>~~eG~~|50<br>~~ee~~<br>~~Gs~~<br>~~eG~~|mV<br>~~eG~~|
|ZOLP<br><br>~~es~~<br>~~a~~|Output impedance of LP transmitter<br>~~es~~<br>~~eG~~|110<br>~~Gs~~<br>~~eG~~|—<br>~~Gs~~<br>~~eG~~|—<br>~~Gs~~<br>~~eG~~|Ω<br>~~eG~~|



## **3.14. Typical Building Block Function Performance – C/E Devices** 

## **3.14.1. Pin-to-Pin Performance (LVCMOS25 12 mA Drive)** 

**Table 3.18. Pin-to-Pin Performance (LVCMOS25 12 mA Drive)** 

|**Function**|**–6 Timing**|**Units**|
|---|---|---|
|**Basic Functions**|||
|16-bit decoder|8.9|ns|
|4:1 MUX|7.5|ns|
|16:1 MUX|8.3|ns|



© 2014-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

58 

FPGA-DS-02032-2.8 

**MachXO3 Family Data Sheet** 

## **3.14.2. Register-to-Register Performance** 

**Table 3.19. Register-to-Register Performance** 

|**Function**|**–6 Timing**|**Units**|
|---|---|---|
|**Basic Functions**|||
|16:1 MUX|412|MHz|
|16-bit adder|297|MHz|
|16-bit counter|324|MHz|
|64-bit counter|161|MHz|
|**Embedded Memory Functions**|||
|1024x9 True-Dual Port RAM<br>(Write Through or Normal, EBR output registers)|183|MHz|
|**Distributed Memory Functions**|||
|16x4 Pseudo-Dual Port RAM(one PFU)|500|MHz|



**Note** : The above timing numbers are generated using the Diamond design tool. Exact performance may vary with device and tool version. The tool uses internal parameters that have been characterized but are not tested on every device. Commercial timing numbers are shown at 85 °C and 1.14 V. Other operating conditions, including industrial, can be extracted from the Diamond software. 

## **3.15. Derating Logic Timing** 

Logic timing provided in the following sections of the data sheet and the Lattice design tools are worst case numbers in the operating range. Actual delays may be much faster. Lattice design tools can provide logic timing numbers at a particular temperature and voltage. 

## **3.16. Maximum sysI/O Buffer Performance** 

**Table 3.20. Maximum sysI/O Buffer Performance** 

|**I/O Standard**|**Max. Speed**<br>**(Commercial/Industrial)**|**Max. Speed**<br>**(Automotive)**|**Units**|
|---|---|---|---|
|MIPI<br>~~I~~|450<br>~~I~~|—<br>~~I~~|MHz<br>~~I~~|
|LVDS25<br>~~GO~~|400<br>~~GO~~|—<br>~~GO~~|MHz<br>~~GO~~|
|LVDS25E<br>~~ef~~|150<br>~~ef~~|—<br>~~ef~~|MHz<br>~~ef~~|
|BLVDS25<br>~~ef~~<br>~~a~~|150<br>~~ef~~|—<br>~~ef~~|MHz<br>~~ef~~|
|BLVDS25E<br>~~a~~<br>~~ef~~|150<br>~~ef~~|—<br>~~ef~~|MHz<br>~~ef~~|
|MLVDS25<br>~~ef~~<br>~~ef~~|150<br>~~ef~~<br>~~ef~~|—<br>~~ef~~<br>~~ef~~|MHz<br>~~ef~~<br>~~ef~~|
|MLVDS25E<br>~~ef~~<br>~~GR~~|150<br>~~ef~~<br>~~GR~~|—<br>~~ef~~<br>~~GR~~|MHz<br>~~ef~~<br>~~GR~~|
|LVPECL33<br>~~GR~~<br>~~GO~~|150<br>~~GR~~<br>~~GO~~|—<br>~~GR~~<br>~~GO~~|MHz<br>~~GR~~<br>~~GO~~|
|LVPECL33E<br>~~ef~~|150<br>~~ef~~|—<br>~~ef~~|MHz<br>~~ef~~|
|LVTTL33<br>~~ef~~<br>~~a~~|150<br>~~ef~~|—<br>~~ef~~|MHz<br>~~ef~~|
|LVTTL33D<br>~~a~~<br>~~a~~|150|—|MHz|
|LVCMOS33<br>~~a~~<br>~~ef~~|150<br>~~ef~~|—<br>~~ef~~|MHz<br>~~ef~~|
|LVCMOS33D<br>~~ef~~<br>~~ef~~|150<br>~~ef~~<br>~~ef~~|—<br>~~ef~~<br>~~ef~~|MHz<br>~~ef~~<br>~~ef~~|
|LVCMOS25<br>~~ef~~<br>~~GO~~|150<br>~~ef~~<br>~~GO~~|—<br>~~ef~~<br>~~GO~~|MHz<br>~~ef~~<br>~~GO~~|
|LVCMOS25D<br>~~GO~~|150<br>~~GO~~|—<br>~~GO~~|MHz<br>~~GO~~|
|LVCMOS18<br>~~ef~~|150<br>~~ef~~|—<br>~~ef~~|MHz<br>~~ef~~|
|LVCMOS18D<br>~~ef~~<br>~~a~~|150<br>~~ef~~|—<br>~~ef~~|MHz<br>~~ef~~|
|LVCMOS15<br>~~a~~<br>~~a~~|150|—|MHz|
|LVCMOS15D<br>~~a~~<br>~~a~~|150|—|MHz|
|LVCMOS12<br>~~eG~~|91<br>~~eG~~|—<br>~~eG~~|MHz<br>~~eG~~|
|LVCMOS12D<br>~~en~~|91<br>~~en~~|—<br>~~en~~|MHz<br>~~en~~|



© 2014-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02032-2.8 

59 

**MachXO3 Family Data Sheet** 

## **3.17. MachXO3L/LF External Switching Characteristics – C/E Devices** 

Over recommended operating conditions. 

**Table 3.21. MachXO3L/LF External Switching Characteristics – C/E Devices[1, 2, 3, 4, 5, 6, 10]** 

|**Parameter**<br>~~7~~|**Description**<br>~~|~~|**Device**<br>~~eT~~|**–6**<br>**(Commercial/Industrial)**<br>~~eT~~|**–6**<br>**(Commercial/Industrial)**<br>~~eT~~|**–5**<br>**(Commercial/Industrial)**<br>~~eT~~|**–5**<br>**(Commercial/Industrial)**<br>~~eT~~|**–5**<br>**(Automotive)**<br>~~eT~~|**–5**<br>**(Automotive)**<br>~~eT~~|**Units**<br>~~eT~~|
|---|---|---|---|---|---|---|---|---|---|
||||**Min.**<br>~~eT~~<br>~~a~~|**Max.**<br>~~eT~~|**Min.**<br>~~eT~~|**Max.**<br>~~eT~~|**Min.**<br>~~eT~~|**Max.**<br>~~eT~~||
|**Clocks**<br>~~7~~<br>~~|eT~~<br>~~a~~||||||||||
|**Primary Clocks**<br>~~PE~~||||||||||
|fMAX_PRI7<br>~~PE~~|Frequency for<br>Primary Clock<br>Tree<br>~~PE~~|All<br>MachXO3L/LF<br>devices<br>~~PE~~|—<br>~~PE~~|388<br>~~PE~~|—<br>~~PE~~|323<br>~~PE~~|—<br>~~PE~~|323<br>~~PE~~|MHz<br>~~PE~~|
|tW_PRI|Clock Pulse<br>Width for<br>PrimaryClock|All<br>MachXO3L/LF<br>devices|0.5|—|0.6|—|0.6|—|ns|
|tSKEW_PRI<br>~~Bn~~<br>~~es~~|Primary Clock<br>Skew Within a<br>Device<br>~~Bn~~<br>|MachXO3L/LF<br>-1300<br>~~i~~|—<br>~~i~~|867<br>~~i~~|—<br>~~i~~|897<br>~~i~~|—<br>~~i~~|952<br>~~i~~|ps<br>~~i~~|
|||MachXO3L/LF<br>-2100<br>~~i~~<br>~~a~~|—<br>~~i~~<br>~~a~~|867<br>~~i~~<br>~~a~~|—<br>~~i~~<br>~~a~~|897<br>~~i~~<br>~~a~~|—<br>~~i~~<br>~~a~~|952<br>~~i~~<br>~~a~~|ps<br>~~i~~<br>~~a~~|
|||MachXO3L/LF<br>-4300<br>~~a~~<br>~~a~~<br>~~es~~|—<br>~~a~~<br>~~a~~|865<br>~~a~~<br>~~a~~|—<br>~~a~~<br>~~a~~|892<br>~~a~~<br>~~a~~|—<br>~~a~~<br>~~a~~|986<br>~~a~~<br>~~a~~|ps<br>~~a~~<br>~~a~~|
|||MachXO3L/LF<br>-6900<br>~~a~~<br>~~es~~|—<br>~~a~~|902<br>~~a~~|—<br>~~a~~|942<br>~~a~~|—<br>~~a~~|—<br>~~a~~|ps<br>~~a~~|
|||MachXO3L/LF<br>-9400<br>~~es~~<br>~~Bn~~<br>|—<br>~~Bn~~<br>|908<br>~~Bn~~<br>|—<br>~~Bn~~<br>|950<br>~~Bn~~<br>|—<br>~~Bn~~<br>|—<br>~~Bn~~<br>|ps<br>~~Bn~~<br>|
|**Edge Clock**<br>~~Bn~~<br>~~es~~||||||||||
|fMAX_EDGE7<br>~~Bn~~<br>~~es~~|Frequency for<br>Edge Clock<br>~~Bn~~<br>|MachXO3L/LF<br>~~Bn~~<br>|—<br>~~Bn~~<br>|400<br>~~Bn~~<br>|—<br>~~Bn~~<br>|333<br>~~Bn~~<br>|—<br>~~Bn~~<br>|333<br>~~Bn~~<br>|MHz<br>~~Bn~~<br>|
|**Pin-LUT-Pin Propagation Delay**<br>~~es~~||||||||||
|tPD<br>|Best case<br>propagation<br>delay through<br>one LUT-4<br>|All<br>MachXO3L/LF<br>devices<br>|—<br>|6.72<br>|—<br>|6.96<br>|—<br>|6.96<br>|ns<br>|
|**General I/O Pin Parameters(Using Primary Clock without PLL)**<br>~~Pe~~||||||||||
|tCO<br>~~Pe~~|Clock to<br>Output – PIO<br>Output<br>Register<br>~~Pe~~|MachXO3L/LF<br>-1300<br>~~Pe~~<br>~~a~~|—<br>~~Pe~~<br>~~a~~|7.46<br>~~Pe~~<br>~~a~~|—<br>~~Pe~~<br>~~a~~|7.66<br>~~Pe~~<br>~~a~~|—<br>~~Pe~~<br>~~a~~|7.66<br>~~Pe~~<br>~~a~~|ns<br>~~Pe~~<br>~~a~~|
|||MachXO3L/LF<br>-2100<br>~~a~~<br>~~a~~|—<br>~~a~~<br>~~a~~|7.46<br>~~a~~<br>~~a~~|—<br>~~a~~<br>~~a~~|7.66<br>~~a~~<br>~~a~~|—<br>~~a~~<br>~~a~~|7.66<br>~~a~~<br>~~a~~|ns<br>~~a~~<br>~~a~~|
|||MachXO3L/LF<br>-4300<br>~~a~~<br>~~a~~|—<br>~~a~~<br>~~a~~|7.51<br>~~a~~<br>~~a~~|—<br>~~a~~<br>~~a~~|7.71<br>~~a~~<br>~~a~~|—<br>~~a~~<br>~~a~~|7.71<br>~~a~~<br>~~a~~|ns<br>~~a~~<br>~~a~~|
|||MachXO3L/LF<br>-6900<br>~~a~~<br>~~SO~~|—<br>~~a~~<br>~~SO~~|7.54<br>~~a~~<br>~~SO~~|—<br>~~a~~<br>~~SO~~|7.75<br>~~a~~<br>~~SO~~|—<br>~~a~~<br>~~SO~~|—<br>~~a~~<br>~~SO~~|ns<br>~~a~~<br>~~SO~~|
|||MachXO3L/LF<br>-9400<br>~~ee~~|—<br>~~ee~~|7.53<br>~~ee~~|—<br>~~ee~~|7.83<br>~~ee~~|—<br>~~ee~~|—<br>~~ee~~|ns<br>~~ee~~|
|tSU|Clock to Data<br>Setup – PIO<br>Input Register|MachXO3L/LF<br>-1300<br>~~ee~~|–0.20<br>~~ee~~|—<br>~~ee~~|–0.20<br>~~ee~~|—<br>~~ee~~|–0.20<br>~~ee~~|—<br>~~ee~~|ns<br>~~ee~~|
|||MachXO3L/LF<br>-2100<br>~~ee~~<br>~~es a~~|–0.20<br>~~ee~~<br>~~a~~|—<br>~~ee~~|–0.20<br>~~ee~~|—<br>~~ee~~|–0.20<br>~~ee~~|—<br>~~ee~~|ns<br>~~ee~~|
|||MachXO3L/LF<br>-4300<br>~~es a~~<br>~~ee~~|–0.23<br>~~a~~<br>~~a~~|—|–0.23|—|–0.23|—|ns|
|||MachXO3L/LF<br>-6900<br>~~es a~~<br>~~ee~~<br>~~es~~|–0.23<br>~~a~~<br>~~a~~|—|–0.23|—|—|—|ns|
|||MachXO3L/LF<br>-9400<br>~~ee ~~<br>~~es~~|–0.24<br> ~~a~~|—|–0.24|—|—|—|ns|



© 2014-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

60 

FPGA-DS-02032-2.8 

**MachXO3 Family Data Sheet** 

|**Parameter**|**Description**|**Device**<br>~~of~~|**–6**<br>**(Commercial/Industrial)**<br>~~es~~|**–6**<br>**(Commercial/Industrial)**<br>~~es~~|**–5**<br>**(Commercial/Industrial)**|**–5**<br>**(Commercial/Industrial)**|**–5**<br>**(Automotive)**|**–5**<br>**(Automotive)**|**Units**|
|---|---|---|---|---|---|---|---|---|---|
||||**Min.**<br>~~es~~<br>~~of~~<br>~~ft~~|**Max.**<br>~~ft~~<br>~~|~~|**Min.**<br>~~ff~~|**Max.**<br>~~ff~~|**Min.**<br>~~ff~~<br>~~ft~~|**Max.**<br>~~ft~~||
|tH|Clock to Data<br>Hold – PIO<br>Input Register|MachXO3L/LF<br>-1300<br>~~of~~<br>~~re~~|1.89<br>~~es~~<br>~~of~~<br>~~ft~~<br>~~ee~~|—<br>~~ft~~<br>~~|~~<br>~~ee~~|2.13<br>~~ff~~<br>~~ee~~|—<br>~~ff~~<br>~~ee~~|2.58<br>~~ff~~<br>~~ft~~<br>~~ee~~|—<br>~~ft~~<br>~~ee~~|ns<br>~~ee~~|
|||MachXO3L/LF<br>-2100<br>~~of~~<br>~~re~~<br>~~of~~|1.89<br>~~of~~<br>~~ft~~<br>~~ee~~<br>~~of~~<br>~~ft~~|—<br>~~ft~~<br>~~| ~~<br>~~ee~~<br>~~ftff~~|2.13<br> ~~ff~~<br>~~ee~~<br>~~ff~~|—<br>~~ff~~<br>~~ee~~<br>~~ft~~|2.58<br>~~ff~~<br>~~ft~~<br>~~ee~~<br>~~ft~~|—<br>~~ft~~<br>~~ee~~<br>~~ft~~|ns<br>~~ee~~|
|||MachXO3L/LF<br>-4300<br>~~re~~<br>~~of~~<br>~~of~~|1.94<br>~~ee~~<br>~~of~~<br>~~ft~~<br>~~of~~<br>~~fF~~|—<br>~~ee~~<br>~~ftff~~<br>~~fFff~~|2.18<br>~~ee~~<br>~~ff~~<br>~~ff~~|—<br>~~ee~~<br>~~ft~~<br>~~PP~~|2.49<br>~~ee~~<br>~~ft~~<br>~~PP~~|—<br>~~ee~~<br>~~ft~~<br>~~PP~~|ns<br>~~ee~~|
|||MachXO3L/LF<br>-6900<br>~~of~~<br>~~of~~<br>~~of~~|1.98<br>~~of~~<br>~~ft~~<br>~~of~~<br>~~fF~~<br>~~of~~<br>~~fF~~|—<br>~~ft ff~~<br>~~fFff~~<br>~~fF~~<br>~~|~~|2.23<br>~~ff~~<br>~~ff~~<br>~~ft~~|—<br>~~ft~~<br>~~PP~~<br>~~ft~~|—<br>~~ft~~<br>~~PP~~<br>~~ft~~|—<br>~~ft~~<br>~~PP~~|ns|
|||MachXO3L/LF<br>-9400<br>~~of~~<br>~~of~~<br>~~pf~~|1.99<br>~~of~~<br>~~fF~~<br>~~of~~<br>~~fF~~<br>~~pf~~<br>~~fF~~|—<br>~~fF ff~~<br>~~fF~~<br>~~|~~<br>~~fF~~<br>~~|~~|2.24<br>~~ff~~<br>~~ft~~<br>~~|~~|—<br>~~PP~~<br>~~ft~~|—<br>~~PP~~<br>~~ft~~|—<br>~~PP~~|ns|
|tSU_DEL|Clock to Data<br>Setup – PIO<br>Input Register<br>with Data<br>Input Delay|MachXO3L/LF<br>-1300<br>~~of~~<br>~~pf~~|1.61<br>~~of~~<br>~~fF~~<br>~~pf~~<br>~~fF~~|—<br>~~fF~~<br>~~| ~~<br>~~fF~~<br>~~|~~<br>~~ee~~|1.76<br> ~~ft~~<br>~~|~~<br>~~ee~~|—<br>~~ft~~<br>~~ee~~|1.76<br>~~ft~~<br>~~ee~~|—|ns|
|||MachXO3L/LF<br>-2100<br>~~pf~~<br>~~ee~~|1.61<br>~~pf~~<br>~~fF~~<br>~~ee~~|—<br>~~fF~~<br>~~|~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|1.76<br>~~|~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~<br>~~ee~~|1.76<br>~~ee~~<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~|ns<br>~~ee~~<br>~~ee~~|
|||MachXO3L/LF<br>-4300<br>~~ee~~|1.66<br>~~ee~~|—<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|1.81<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|—<br>~~ee ~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|1.81<br> ~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~<br>~~ee~~|ns<br>~~ee~~<br>~~ee~~<br>~~ee~~|
|||MachXO3L/LF<br>-6900<br>~~ee~~<br>~~ee~~|1.53<br>~~ee~~<br>|—<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>|1.67<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>|—<br>~~ee ~~<br>~~ee~~<br>~~ee~~<br>~~ee ee~~<br>|—<br> ~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>|—<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|ns<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|
|||MachXO3L/LF<br>-9400<br>~~ee~~<br>~~ee~~<br>~~ee~~|1.65<br>~~ee~~<br>~~ee~~<br>|—<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>|1.80<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>|—<br>~~ee ~~<br>~~ee~~<br>~~ee ee~~<br>~~ee~~<br>|—<br> ~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>|—<br>~~ee~~<br>~~ee~~<br>~~ee~~|ns<br>~~ee~~<br>~~ee~~<br>~~ee~~|
|tH_DEL<br>~~aa~~|Clock to Data<br>Hold – PIO<br>Input Register<br>with Input<br>Data Delay<br>~~aa~~|MachXO3L/LF<br>-1300<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|–0.23<br>~~ee~~<br>~~ee~~<br>~~**ee**~~<br>|—<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~**ee**~~<br>|–0.23<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~**ee**~~<br>|—<br>~~ee~~<br>~~ee ee~~<br>~~ee~~<br>~~**ee**~~<br>|–0.19<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~**ee**~~<br>|—<br>~~ee~~<br>~~ee~~<br>|ns<br>~~ee~~<br>~~ee~~<br>|
|||MachXO3L/LF<br>-2100<br>~~ee ~~<br>~~ee~~<br>~~ee~~|–0.23<br> ~~ee~~<br>~~**ee**~~<br>|—<br>~~ee ~~<br>~~ee~~<br>~~**ee**~~<br>|–0.23<br> ~~ee~~<br>~~ee~~<br>~~**ee**~~<br>|—<br>~~ee ee~~<br>~~ee~~<br>~~**ee**~~<br>|–0.19<br>~~ee~~<br>~~ee~~<br>~~**ee**~~<br>|—<br>~~ee~~<br>|ns<br>~~ee~~<br>|
|||MachXO3L/LF<br>-4300<br> <br>~~ee ~~<br>~~ee~~|–0.25<br> ~~ee~~<br> ~~**ee**~~<br>|—<br>~~ee ~~<br>~~**ee**~~<br><br>~~ee~~|–0.25<br> ~~ee~~<br>~~**ee**~~<br><br>~~ee~~|—<br>~~ee ~~<br>~~**ee**~~<br><br>~~ee~~|–0.22<br> ~~ee~~<br>~~**ee**~~<br><br>~~ee~~|—<br>|ns<br>|
|||MachXO3L/LF<br>-6900<br> <br>~~eeee~~|–0.21<br> ~~**ee**~~<br>~~ee~~|—<br>~~**ee** ~~<br>~~ee~~<br>~~ee~~|–0.21<br> ~~**ee**~~<br>~~ee~~<br>~~ee~~|—<br>~~**ee** ~~<br>~~ee~~<br>~~ee~~|—<br> ~~**ee**~~<br>~~ee~~<br>~~ee~~|—<br>~~ee~~|ns<br>~~ee~~|
|||MachXO3L/LF<br>-9400<br>~~ee~~<br>~~aa~~|–0.24<br>~~ee~~<br>~~aa~~|—<br>~~ee~~<br>~~ee~~<br>~~aa~~|–0.24<br>~~ee~~<br>~~ee~~<br>~~aa~~|—<br>~~ee~~<br>~~ee ~~<br>~~aa~~|—<br>~~ee~~<br> ~~ee~~<br>~~aa~~|—<br>~~ee~~<br>~~aa~~|ns<br>~~ee~~<br>~~aa~~|
|fMAX_I/O<br>~~aa~~|Clock<br>Frequency of<br>I/O and PFU<br>Register<br>~~aa~~|All<br>MachXO3L/LF<br>devices<br>~~aa~~|—<br>~~aa~~|388<br>~~aa~~|—<br>~~aa~~|323<br>~~aa~~|—<br>~~aa~~|323<br>~~aa~~|MHz<br>~~aa~~|
|**General I/O Pin Parameters(Using Edge Clock without PLL)**<br>~~PT~~<br>~~eeeeeee~~||||||||||
|tCOE<br>~~PT~~|Clock to<br>Output–PIO<br>Output<br>Register<br>~~PT~~|MachXO3L/LF<br>-1300<br>~~PT~~<br>~~ee~~|—<br>~~PT~~<br>~~ee~~|7.53<br>~~PT~~<br>~~ee~~<br>~~ee~~|—<br>~~PT~~<br>~~ee~~<br>~~ee~~|7.76<br>~~PT~~<br>~~ee~~<br>~~ee~~|—<br>~~PT~~<br>~~eee~~<br>~~ee~~|7.76<br>~~PT~~<br>~~eee~~<br>~~ee~~|ns<br>~~PT~~<br>~~eee~~<br>~~ee~~|
|||MachXO3L/LF<br>-2100<br>~~ee~~<br>~~ee~~|—<br>~~ee ~~<br>~~ee~~|7.53<br> ~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|7.76<br>~~ee ~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|—<br> ~~eee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|7.76<br>~~eee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|ns<br>~~eee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|
|||MachXO3L/LF<br>-4300<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~|7.45<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>|—<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~**e**~~<br>|7.68<br>~~ee ~~<br>~~ee~~<br>~~ee~~<br>~~**e**e~~|—<br> ~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|7.68<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|ns<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|
|||MachXO3L/LF<br>-6900<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~|7.53<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>|—<br>~~ee~~<br>~~ee~~<br>~~**e**~~<br>|7.76<br>~~ee ~~<br>~~ee~~<br>~~**e**e~~|—<br> ~~ee~~<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~<br>~~ee~~|ns<br>~~ee~~<br>~~ee~~<br>~~ee~~|
|||MachXO3L/LF<br>-9400<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~|8.93<br>~~ee~~<br>~~ee~~<br>~~e~~|—<br>~~ee~~<br>~~**e**~~<br>~~e~~|9.35<br>~~ee~~<br>~~**e**e~~|—<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~|ns<br>~~ee~~<br>~~ee~~|



© 2014-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02032-2.8 

61 

**MachXO3 Family Data Sheet** 

|**Parameter**|**Description**|**Device**|**–6**<br>**(Commercial/Industrial)**|**–6**<br>**(Commercial/Industrial)**|**–5**<br>**(Commercial/Industrial)**|**–5**<br>**(Commercial/Industrial)**|**–5**<br>**(Automotive)**|**–5**<br>**(Automotive)**|**Units**|
|---|---|---|---|---|---|---|---|---|---|
||||**Min.**<br>~~a~~|**Max.**|**Min.**|**Max.**|**Min.**|**Max.**||
|tSUE|Clock to Data<br>Setup–PIO<br>Input Register|MachXO3L/LF<br>-1300<br>~~||~~|–0.19<br>~~a~~<br>~~||~~|—<br>~~||~~<br>~~|~~|–0.19<br>~~||~~<br>~~|~~|—<br>~~||~~<br>~~|~~|–0.19<br>~~||~~<br>~~|~~|—<br>~~|~~|ns|
|||MachXO3L/LF<br>-2100<br>~~||~~<br>~~|~~|–0.19<br>~~||~~<br>~~|~~<br>~~|~~|—<br>~~||~~<br>~~|~~<br>~~|~~<br>~~|~~|–0.19<br>~~||~~<br>~~|~~|—<br>~~||~~<br>~~|~~|–0.19<br>~~||~~<br>~~|~~|—<br>~~|~~|ns|
|||MachXO3L/LF<br>-4300<br>~~|~~<br>~~||~~<br>~~a~~|–0.16<br>~~|~~<br>~~|~~<br>~~||~~<br>~~|~~<br>|—<br>~~|~~<br>~~|~~<br>~~||~~<br>~~|~~<br>~~fF~~<br>|–0.16<br>~~||~~<br>~~|~~<br>~~fF~~<br>|—<br>~~||~~<br>~~|~~<br>|–0.16<br>~~||~~<br>~~|~~<br>|—<br>~~|~~<br>|ns<br>|
|||MachXO3L/LF<br>-6900<br>~~||~~<br>~~|~~<br>~~a~~|–0.19<br>~~||~~<br>~~|~~<br>~~|~~<br>|—<br>~~||~~<br>~~|~~<br>~~|~~<br>~~fF~~<br>|–0.19<br>~~||~~<br>~~|~~<br>~~fF~~<br>|—<br>~~||~~<br>~~|~~<br>|—<br>~~||~~<br>~~|~~<br>|—<br>~~|~~<br>|ns<br>|
|||MachXO3L/LF<br>-9400<br>~~|~~<br>~~a ee~~<br>~~|~~|–0.20<br>~~|~~<br>~~|~~<br>~~ee~~<br>~~|~~|—<br>~~|~~<br>~~fF~~<br>~~ee~~<br>~~fF~~|–0.20<br>~~fF~~<br>~~ee~~<br>~~fF~~|—<br>~~ee~~|—<br>~~ee~~|—<br>~~ee~~|ns<br>~~ee~~|
|tHE|Clock to Data<br>Hold–PIO<br>Input Register|MachXO3L/LF<br>-1300<br>~~a ee~~<br>~~|~~<br>~~|~~|1.97<br>~~|~~<br>~~ee~~<br>~~|~~<br>~~|~~|—<br>~~fF~~<br>~~ee~~<br>~~fF~~<br>~~|~~|2.24<br>~~fF~~<br>~~ee~~<br>~~fF~~<br>~~ft~~|—<br>~~ee~~<br>~~ft~~<br>~~|~~|2.24<br>~~ee~~|—<br>~~ee~~|ns<br>~~ee~~|
|||MachXO3L/LF<br>-2100<br>~~|~~<br>~~|~~<br>~~|~~|1.97<br>~~|~~<br>~~|~~<br>~~|~~|—<br>~~fF~~<br>~~|~~<br>~~fF~~|2.24<br>~~fF~~<br>~~ft~~<br>~~fF~~|—<br>~~ft~~<br>~~|~~|2.24|—|ns|
|||MachXO3L/LF<br>-4300<br>~~|~~<br>~~|~~<br>~~|~~|1.89<br>~~|~~<br>~~|~~<br>~~|~~|—<br>~~|~~<br>~~fF~~<br>~~fF~~|2.16<br>~~ft~~<br>~~fF~~<br>~~fF~~|—<br>~~ft~~<br>~~|~~|2.16|—|ns|
|||MachXO3L/LF<br>-6900<br>~~|~~<br>~~|~~|1.97<br>~~|~~<br>~~|~~|—<br>~~fF~~<br>~~fF~~|2.24<br>~~fF~~<br>~~fF~~|—|—|—|ns|
|||MachXO3L/LF<br>-9400<br>~~|~~<br>~~|~~|1.98<br>~~|~~<br>~~|~~|—<br>~~fF~~<br>~~|~~|2.25<br>~~fF~~|—|—|—|ns|
|tSU_DELE|Clock to Data<br>Setup–PIO<br>Input Register<br>with Data<br>Input Delay|MachXO3L/LF<br>-1300<br>~~|~~<br>~~ee~~|1.56<br>~~|~~<br>~~ee~~|—<br>~~|~~<br>~~ee~~|1.69<br>~~ee~~|—<br>~~ee~~|1.69<br>~~ee~~|—<br>~~ee~~|ns<br>~~ee~~|
|||MachXO3L/LF<br>-2100<br>~~ee~~<br>~~ee~~|1.56<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~|1.69<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~|1.69<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~|ns<br>~~ee~~<br>~~ee~~|
|||MachXO3L/LF<br>-4300<br>~~ee~~<br>~~ee~~|1.74<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~|1.88<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~|1.88<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~|ns<br>~~ee~~<br>~~ee~~|
|||MachXO3L/LF<br>-6900<br>~~ee~~<br>~~a~~|1.66<br>~~ee~~|—<br>~~ee~~|1.81<br>~~ee~~|—<br>~~ee~~|—<br>~~ee~~|—<br>~~ee~~|ns<br>~~ee~~|
|||MachXO3L/LF<br>-9400<br>~~a~~<br>~~a~~<br>~~a~~|1.71<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~|1.85<br>~~ee~~<br>~~ee~~|—<br>~~ee~~|—<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~|ns<br>~~ee~~<br>~~ee~~|
|tH_DELE|Clock to Data<br>Hold–PIO<br>Input Register<br>with Input<br>Data Delay|MachXO3L/LF<br>-1300<br>~~a~~<br>~~a~~|–0.23<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~|–0.23<br>~~ee~~<br>~~ee~~|—<br>~~ee~~|–0.23<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~|ns<br>~~ee~~<br>~~ee~~|
|||MachXO3L/LF<br>-2100<br>~~a ~~<br>~~||~~|–0.23<br> ~~ee~~<br>~~||~~|—<br>~~ee~~<br>~~||~~<br>~~|~~|–0.23<br>~~ee~~<br>~~||~~<br>~~|~~|—<br>~~||~~<br>~~|~~|–0.23<br>~~ee~~<br>~~||~~<br>~~|~~|—<br>~~ee~~<br>~~|~~|ns<br>~~ee~~|
|||MachXO3L/LF<br>-4300<br>~~||~~<br>~~|~~|–0.34<br>~~||~~<br>~~|~~<br>~~|~~|—<br>~~||~~<br>~~|~~<br>~~|~~<br>~~|~~|–0.34<br>~~||~~<br>~~|~~|—<br>~~||~~<br>~~|~~|–0.34<br>~~||~~<br>~~|~~|—<br>~~|~~|ns|
|||MachXO3L/LF<br>-6900<br>~~|~~<br>~~|~~|–0.29<br>~~|~~<br>~~|~~<br>~~|~~|—<br>~~|~~<br>~~|~~<br>~~|~~|–0.29|—|—|—|ns|
|||MachXO3L/LF<br>-9400<br>~~|~~<br>~~ee~~|–0.30<br>~~|~~<br>~~ee~~|—<br>~~|~~<br>~~ee~~|–0.30<br>~~ee~~|—<br>~~eee~~|—<br>~~eee~~|—<br>~~eee~~|ns<br>~~eee~~|
|**General I/O Pin Parameters(Using Primary Clock with PLL)**<br>~~ee eee~~||||||||||
|tCOPLL|Clock to<br>Output–PIO<br>Output<br>Register|MachXO3L/LF<br>-1300<br>~~||~~|—<br>~~||~~|5.98<br>~~||~~<br>~~|~~|—<br>~~||~~<br>~~|~~|6.01<br>~~||~~<br>~~|~~|—<br>~~||~~<br>~~|~~|6.01<br>~~|~~|ns|
|||MachXO3L/LF<br>-2100<br>~~||~~<br>~~|~~<br>~~|~~|—<br>~~||~~<br>~~|~~<br>~~|~~<br>~~|~~|5.98<br>~~||~~<br>~~|~~<br>~~|~~<br>~~|~~<br>~~|~~|—<br>~~||~~<br>~~|~~<br>~~|~~|6.01<br>~~||~~<br>~~|~~<br>~~|~~|—<br>~~||~~<br>~~|~~<br>~~ft~~|6.01<br>~~|~~<br>~~ftft~~|ns<br>~~ft~~|
|||MachXO3L/LF<br>-4300<br>~~|~~<br>~~|~~|—<br>~~|~~<br>~~|~~<br>~~|~~|5.99<br>~~|~~<br>~~|~~<br>~~|~~|—<br>~~|~~|6.02<br>~~|~~|—<br>~~ft~~|6.02<br>~~ftft~~|ns<br>~~ft~~|
|||MachXO3L/LF<br>-6900<br>~~|~~<br>~~||~~|—<br>~~|~~<br>~~||~~<br>~~|~~|6.02<br>~~|~~<br>~~||~~<br>~~|~~<br>~~fF~~|—<br>~~|~~<br>~~||~~<br>~~|~~<br>~~fF~~|6.06<br>~~|~~<br>~~||~~<br>~~|~~|—<br>~~ft~~<br>~~||~~<br>~~|~~|—<br>~~ft ft~~<br>~~|~~|ns<br>~~ft~~|
|||MachXO3L/LF<br>-9400<br>~~||~~<br>~~|~~|—<br>~~||~~<br>~~|~~<br>~~|~~|5.55<br>~~||~~<br>~~|~~<br>~~|~~<br>~~fF~~|—<br>~~||~~<br>~~|~~<br>~~fF~~|6.13<br>~~||~~<br>~~|~~|—<br>~~||~~<br>~~|~~|—<br>~~|~~|ns|



© 2014-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

62 

FPGA-DS-02032-2.8 

**MachXO3 Family Data Sheet** 

|**Parameter**|**Description**|**Device**|**–6**<br>**(Commercial/Industrial)**|**–6**<br>**(Commercial/Industrial)**|**–5**<br>**(Commercial/Industrial)**|**–5**<br>**(Commercial/Industrial)**|**–5**<br>**(Automotive)**|**–5**<br>**(Automotive)**|**Units**|
|---|---|---|---|---|---|---|---|---|---|
||||**Min.**<br>~~a~~|**Max.**|**Min.**|**Max.**|**Min.**|**Max.**||
|tSUPLL|Clock to Data<br>Setup–PIO<br>Input Register|MachXO3L/LF<br>-1300<br>~~||~~|0.36<br>~~a~~<br>~~||~~|—<br>~~||~~<br>~~|~~|0.36<br>~~||~~<br>~~|~~|—<br>~~||~~<br>~~|~~|0.36<br>~~||~~<br>~~|~~|—<br>~~|~~|ns|
|||MachXO3L/LF<br>-2100<br>~~||~~<br>~~|~~|0.36<br>~~||~~<br>~~|~~<br>~~|~~|—<br>~~||~~<br>~~|~~<br>~~|~~<br>~~|~~|0.36<br>~~||~~<br>~~|~~|—<br>~~||~~<br>~~|~~|0.36<br>~~||~~<br>~~|~~|—<br>~~|~~|ns|
|||MachXO3L/LF<br>-4300<br>~~|~~<br>~~||~~<br>~~a~~|0.35<br>~~|~~<br>~~|~~<br>~~||~~<br>~~|~~<br>|—<br>~~|~~<br>~~|~~<br>~~||~~<br>~~|~~<br>~~fF~~<br>|0.35<br>~~||~~<br>~~|~~<br>~~fF~~<br>|—<br>~~||~~<br>~~|~~<br>|0.42<br>~~||~~<br>~~|~~<br>|—<br>~~|~~<br>|ns<br>|
|||MachXO3L/LF<br>-6900<br>~~||~~<br>~~|~~<br>~~a~~|0.34<br>~~||~~<br>~~|~~<br>~~|~~<br>|—<br>~~||~~<br>~~|~~<br>~~|~~<br>~~fF~~<br>|0.34<br>~~||~~<br>~~|~~<br>~~fF~~<br>|—<br>~~||~~<br>~~|~~<br>|—<br>~~||~~<br>~~|~~<br>|—<br>~~|~~<br>|ns<br>|
|||MachXO3L/LF<br>-9400<br>~~|~~<br>~~a ee~~<br>~~|~~|0.33<br>~~|~~<br>~~|~~<br>~~ee~~<br>~~|~~|—<br>~~|~~<br>~~fF~~<br>~~ee~~<br>~~fF~~|0.33<br>~~fF~~<br>~~ee~~<br>~~fF~~|—<br>~~ee~~|—<br>~~ee~~|—<br>~~ee~~|ns<br>~~ee~~|
|tHPLL|Clock to Data<br>Hold–PIO<br>Input Register|MachXO3L/LF<br>-1300<br>~~a ee~~<br>~~|~~<br>~~|~~|0.42<br>~~|~~<br>~~ee~~<br>~~|~~<br>~~|~~|—<br>~~fF~~<br>~~ee~~<br>~~fF~~<br>~~|~~|0.49<br>~~fF~~<br>~~ee~~<br>~~fF~~<br>~~ft~~|—<br>~~ee~~<br>~~ft~~<br>~~|~~|0.49<br>~~ee~~|—<br>~~ee~~|ns<br>~~ee~~|
|||MachXO3L/LF<br>-2100<br>~~|~~<br>~~|~~<br>~~|~~|0.42<br>~~|~~<br>~~|~~<br>~~|~~|—<br>~~fF~~<br>~~|~~<br>~~fF~~|0.49<br>~~fF~~<br>~~ft~~<br>~~fF~~|—<br>~~ft~~<br>~~|~~|0.49|—|ns|
|||MachXO3L/LF<br>-4300<br>~~|~~<br>~~|~~<br>~~|~~|0.43<br>~~|~~<br>~~|~~<br>~~|~~|—<br>~~|~~<br>~~fF~~<br>~~fF~~|0.50<br>~~ft~~<br>~~fF~~<br>~~fF~~|—<br>~~ft~~<br>~~|~~|0.51|—|ns|
|||MachXO3L/LF<br>-6900<br>~~|~~<br>~~|~~|0.46<br>~~|~~<br>~~|~~|—<br>~~fF~~<br>~~fF~~|0.54<br>~~fF~~<br>~~fF~~|—|—|—|ns|
|||MachXO3L/LF<br>-9400<br>~~|~~<br>~~|~~|0.47<br>~~|~~<br>~~|~~|—<br>~~fF~~<br>~~|~~|0.55<br>~~fF~~|—|—|—|ns|
|tSU_DELPLL|Clock to Data<br>Setup–PIO<br>Input Register<br>with Data<br>Input Delay|MachXO3L/LF<br>-1300<br>~~|~~<br>~~ee~~|2.87<br>~~|~~<br>~~ee~~|—<br>~~|~~<br>~~ee~~|3.18<br>~~ee~~|—<br>~~ee~~|3.38<br>~~ee~~|—<br>~~ee~~|ns<br>~~ee~~|
|||MachXO3L/LF<br>-2100<br>~~ee~~<br>~~ee~~|2.87<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~|3.18<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~|3.38<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~|ns<br>~~ee~~<br>~~ee~~|
|||MachXO3L/LF<br>-4300<br>~~ee~~<br>~~ee~~|2.96<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~|3.28<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~|3.66<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~|ns<br>~~ee~~<br>~~ee~~|
|||MachXO3L/LF<br>-6900<br>~~ee~~<br>~~a~~|3.05<br>~~ee~~|—<br>~~ee~~|3.35<br>~~ee~~|—<br>~~ee~~|—<br>~~ee~~|—<br>~~ee~~|ns<br>~~ee~~|
|||MachXO3L/LF<br>-9400<br>~~a~~<br>~~a~~<br>~~a~~|3.06<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~|3.37<br>~~ee~~<br>~~ee~~|—<br>~~ee~~|—<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~|ns<br>~~ee~~<br>~~ee~~|
|tH_DELPLL|Clock to Data<br>Hold–PIO<br>Input Register<br>with Input<br>Data Delay|MachXO3L/LF<br>-1300<br>~~a~~<br>~~a~~|–0.83<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~|–0.83<br>~~ee~~<br>~~ee~~|—<br>~~ee~~|–0.83<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~|ns<br>~~ee~~<br>~~ee~~|
|||MachXO3L/LF<br>-2100<br>~~a ~~<br>~~||~~|–0.83<br> ~~ee~~<br>~~||~~|—<br>~~ee~~<br>~~||~~<br>~~|~~|–0.83<br>~~ee~~<br>~~||~~<br>~~|~~|—<br>~~||~~<br>~~|~~|–0.83<br>~~ee~~<br>~~||~~<br>~~|~~|—<br>~~ee~~<br>~~|~~|ns<br>~~ee~~|
|||MachXO3L/LF<br>-4300<br>~~||~~<br>~~|~~|–0.87<br>~~||~~<br>~~|~~<br>~~|~~|—<br>~~||~~<br>~~|~~<br>~~|~~<br>~~|~~|–0.87<br>~~||~~<br>~~|~~|—<br>~~||~~<br>~~|~~|–0.87<br>~~||~~<br>~~|~~|—<br>~~|~~|ns|
|||MachXO3L/LF<br>-6900<br>~~|~~<br>~~|~~|–0.91<br>~~|~~<br>~~|~~<br>~~|~~|—<br>~~|~~<br>~~|~~<br>~~|~~|–0.91|—|—|—|ns|
|||MachXO3L/LF<br>-9400<br>~~|~~<br>~~ee~~|–0.93<br>~~|~~<br>~~ee~~|—<br>~~|~~<br>~~ee~~|–0.93<br>~~ee~~|—<br>~~eee~~|—<br>~~eee~~|—<br>~~eee~~|ns<br>~~eee~~|
|**Generic DDRX1 Inputs with Clock and Data Aligned at Pin Using PCLK Pin for Clock Input– GDDRX1_RX.SCLK.Aligned8, 9 **<br>~~ee eee~~<br>~~pf~~<br>~~—|~~<br>~~|~~<br>~~|~~<br>~~|~~<br>~~}~~<br>~~]~~||||||||||
|tDVA<br>~~pf~~<br>~~pf~~|Input Data<br>Valid After CLK<br>~~pf~~<br>~~pf~~|All<br>MachXO3L/LF<br>devices,<br>all sides|—<br>~~—|~~<br>~~—|~~|0.317<br>~~|~~<br>~~|~~<br>~~|~~<br>~~|~~|—<br>~~|~~<br>~~|~~|0.344<br>~~|~~<br>~~|~~|—<br>~~}~~<br>~~|~~|0.344<br>~~]~~<br>~~]~~|UI|
|tDVE<br>~~pf~~<br>~~pf~~<br>~~pe~~|Input Data<br>Hold After CLK<br>~~pf~~<br>~~pf~~<br>~~pe~~||0.742<br>~~— |~~<br>~~—|~~<br>~~—|~~|—<br>~~|~~<br>~~|~~<br>~~|~~<br>~~|~~<br>~~|~~<br>~~|~~|0.702<br>~~|~~<br>~~|~~<br>~~|~~|—<br>~~|~~<br>~~|~~<br>~~|~~|0.702<br>~~}~~<br>~~|~~<br>~~|~~|—<br>~~]~~<br>~~]~~<br>~~]~~|UI|
|fDATA<br>~~pf~~<br>~~pe~~<br>~~pe~~|DDRX1 Input<br>Data Speed<br>~~pf~~<br>~~pe~~<br>~~pe~~||—<br>~~— |~~<br>~~—|~~<br>~~—|~~|300<br>~~|~~<br>~~|~~<br>~~|~~<br>~~|~~<br>~~|~~<br>~~|~~|—<br>~~|~~<br>~~|~~<br>~~|~~|250<br>~~|~~<br>~~|~~<br>~~|~~|—<br>~~|~~<br>~~|~~<br>~~|~~|250<br>~~]~~<br>~~]~~<br>~~}~~|Mbps|
|fDDRX1<br>~~pe~~<br>~~pe~~|DDRX1 SCLK<br>Frequency<br>~~pe~~<br>~~pe~~||—<br>~~— |~~<br>~~—|~~|150<br>~~|~~<br>~~|~~<br>~~|~~<br>~~|~~|—<br>~~|~~<br>~~|~~|125<br>~~|~~<br>~~|~~|—<br>~~|~~<br>~~|~~|125<br>~~]~~<br>~~}~~|MHz|



© 2014-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02032-2.8 

63 

**MachXO3 Family Data Sheet** 

|**Parameter**<br>~~ee~~|**Description**<br>~~ee~~|**Device**<br>~~ee~~|**–6**<br>**(Commercial/Industrial)**<br>~~**e**~~<br>~~eee~~|**–6**<br>**(Commercial/Industrial)**<br>~~**e**~~<br>~~eee~~|**–5**<br>**(Commercial/Industrial)**<br>~~**e**e~~<br>~~es~~|**–5**<br>**(Commercial/Industrial)**<br>~~**e**e~~<br>~~es~~|**–5**<br>**(Automotive)**<br>~~e~~|**–5**<br>**(Automotive)**<br>~~e~~|**Units**<br>~~e~~|
|---|---|---|---|---|---|---|---|---|---|
||||**Min.**<br>~~**e**~~<br>~~e~~|**Max.**<br>~~**e**~~<br>~~ee~~|**Min.**<br>~~**e**~~<br>~~es~~|**Max.**<br>~~**e**e~~|**Min.**<br>~~e~~|**Max.**<br>~~e~~||
|**Generic DDRX1 Inputs with Clock and Data Centered at Pin Using PCLK Pin for Clock Input– GDDRX1_RX.SCLK.Centered8, 9 **<br>~~ee ee~~~~**e**e~~<br>~~e ee~~<br>~~es~~<br>~~Cee~~||||||||||
|tSU<br>~~Cee~~<br>~~Ft~~<br>~~PF~~|Input Data<br>Setup Before<br>CLK<br>~~Cee~~<br>~~Ft~~<br>|All<br>MachXO3L/LF<br>devices,<br>all sides<br>~~Cee~~|0.566<br>~~Cee~~<br>~~ee~~|—<br>~~Cee~~<br>~~ee~~|0.565<br>~~Cee~~<br>~~ee~~|—<br>~~Cee~~<br>~~ee~~|0.565<br>~~Cee~~<br>~~ee~~|—<br>~~Cee~~<br>~~ee~~<br>~~**ee**~~|Ns<br>~~Cee~~<br>~~ee~~<br>~~**ee**~~|
|tHO<br>~~Ft~~<br>~~PF ot~~|Input Data<br>Hold After CLK<br>~~Ft~~<br>~~ot~~||0.778<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~|0.879<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~|0.879<br>~~ee~~<br>~~e~~|—<br>~~ee~~<br>~~**ee**~~<br>~~e~~|ns<br>~~ee~~<br>~~**ee**~~|
|fDATA<br>~~Ft~~<br>~~PF ot~~<br>~~Fo~~|DDRX1 Input<br>Data Speed<br>~~Ft~~<br>~~ot~~<br>~~Fo~~||—<br>~~ee~~<br>~~ee~~<br>~~ee~~|300<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~<br>~~ee~~|250<br>~~ee~~<br>~~ee~~<br>~~ee eee~~|—<br>~~ee~~<br>~~e~~<br>~~eee~~|250<br>~~ee~~<br>~~**ee**~~<br>~~e~~<br>~~eee~~|Mbps<br>~~ee~~<br>~~**ee**~~<br>~~eee~~|
|fDDRX1<br>~~PF ot~~<br>~~Fo~~|DDRX1 SCLK<br>Frequency<br>~~ot~~<br>~~Fo~~||—<br>~~ee~~<br>~~ee~~|150<br>~~ee~~|—<br>~~ee~~<br>~~ee~~|125<br>~~ee ~~<br>~~ee eee~~|—<br> ~~e~~<br>~~eee~~|125<br>~~**ee**~~<br>~~e~~<br>~~eee~~|MHz<br>~~**ee**~~<br>~~eee~~|
|**Generic DDRX2 Inputs with Clock and Data Aligned at Pin Using PCLK Pin for Clock Input– GDDRX2_RX.ECLK.Aligned8, 9 **<br>~~Fo~~<br>~~ee~~<br>~~ee eee~~<br>~~Cee~~<br>~~Fo~~<br>~~ee~~<br>~~eee~~||||||||||
|tDVA<br>~~Cee~~<br>~~Fo~~|Input Data<br>Valid After CLK<br>~~Cee~~<br>~~Fo~~|MachXO3L/LF<br>devices,<br>bottom side<br>only<br>~~Cee~~|—<br>~~Cee~~<br>~~ee~~|0.316<br>~~Cee~~<br>~~ee~~|—<br>~~Cee~~<br>~~ee~~|0.342<br>~~Cee~~|—<br>~~Cee~~<br>~~eee~~|0.342<br>~~Cee~~<br>~~eee~~|UI<br>~~Cee~~<br>~~eee~~|
|tDVE<br>~~Fo~~|Input Data<br>Hold After CLK<br>~~Fo~~||0.710<br>~~ee~~|—<br>~~ee~~|0.675<br>~~ee~~|—|0.675<br>~~eee~~|—<br>~~eee~~|UI<br>~~eee~~|
|fDATA<br>~~Pf~~|DDRX2 Serial<br>Input Data<br>Speed<br>~~Pf~~||—<br>~~ee~~|664<br>~~ee~~|—<br>~~ee~~|554<br>~~ee~~|—<br>~~ee~~|554<br>~~ee~~|Mbps<br>~~ee~~|
|fDDRX2<br>~~Pf~~<br>~~PF of~~|DDRX2 ECLK<br>Frequency<br>~~Pf~~<br>~~of~~||—<br>~~ee~~<br>~~ee~~|332<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~|277<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~eee~~|277<br>~~ee~~<br>~~eee~~|MHz<br>~~ee~~<br>~~eee~~|
|fSCLK<br>~~Pf~~<br>~~PF of~~|SCLK<br>Frequency<br>~~Pf~~<br>~~of~~||—<br>~~ee ~~<br>~~ee~~|166<br> ~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~|139<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~eee~~|139<br>~~ee~~<br>~~eee~~|MHz<br>~~ee~~<br>~~eee~~|
|**Generic DDRX2 Inputs with Clock and Data Centered at Pin Using PCLK Pin for Clock Input– GDDRX2_RX.ECLK.Centered8, 9 **<br>~~PF of~~<br>~~ee~~<br>~~eee~~<br>~~Cee~~||||||||||
|tSU|Input Data<br>Setup Before<br>CLK|MachXO3L/LF<br>devices,<br>bottom side<br>only<br> <br>|0.233|—|0.233|—|0.233|—|ns|
|tHO<br>~~SS)~~|Input Data<br>Hold After CLK<br>~~SS)~~||0.287<br>~~SS~~|—<br>~~SS~~|0.287<br>~~SS~~|—<br>~~SS~~|0.287<br>~~SS~~|—<br>~~SS~~|ns<br>~~SS~~|
|fDATA<br>~~SS)~~<br>~~Fo~~|DDRX2 Serial<br>Input Data<br>Speed<br>~~SS)~~<br>~~Fo~~||—<br>~~SS~~<br>~~ee~~|664<br>~~SS~~<br>~~eee~~|—<br>~~SS~~<br>~~eee~~|554<br>~~SS~~<br>~~eee~~|—<br>~~SS~~<br>~~eee~~|554<br>~~SS~~<br>~~eee~~|Mbps<br>~~SS~~<br>~~eee~~|
|fDDRX2<br>~~SS)~~<br>~~Fo~~|DDRX2 ECLK<br>Frequency<br>~~SS) ~~<br>~~Fo~~||—<br> ~~SS~~<br>~~ee~~|332<br>~~SS~~<br>~~eee~~|—<br>~~SS~~<br>~~eee~~|277<br>~~SS~~<br>~~eee~~<br>~~ee~~|—<br>~~SS~~<br>~~eee~~<br>~~eee~~|277<br>~~SS~~<br>~~eee~~<br>~~eee~~|MHz<br>~~SS~~<br>~~eee~~<br>~~eee~~|
|fSCLK<br>~~Fo~~<br>~~Ft~~|SCLK<br>Frequency<br>~~Fo~~<br>~~Ft~~||—<br>~~ee~~<br>~~ee~~|166<br>~~eee~~<br>~~ee~~|—<br>~~eee~~<br>~~ee~~|139<br>~~eee~~<br>~~ee~~<br>~~ee~~|—<br>~~eee~~<br>~~ee~~<br>~~eee~~|139<br>~~eee~~<br>~~ee~~<br>~~eee~~|MHz<br>~~eee~~<br>~~ee~~<br>~~eee~~|
|**Generic DDR4 Inputs with Clock and Data Aligned at Pin Using PCLK Pin for Clock Input – GDDRX4_RX.ECLK.Aligned8**<br>~~Ft ee~~<br>~~ee eee~~<br>~~Cee~~<br>~~BE)EEEEEEE~~||||||||||
|tDVA<br>~~Cee~~<br>~~BE)~~|Input Data<br>Valid After<br>ECLK<br>~~Cee~~<br>~~BE)~~|MachXO3L/LF<br>devices,<br>bottom side<br>only<br>~~Cee~~<br>~~BE)~~|—<br>~~Cee~~<br>~~EEEEEEE~~|0.307<br>~~Cee~~<br>~~EEEEEEE~~|—<br>~~Cee~~<br>~~EEEEEEE~~|0.320<br>~~Cee~~<br>~~EEEEEEE~~|—<br>~~Cee~~<br>~~EEEEEEE~~|0.320<br>~~Cee~~<br>~~EEEEEEE~~|UI<br>~~Cee~~<br>~~EEEEEEE~~|
|tDVE<br>~~BE)~~|Input Data<br>Hold After<br>ECLK<br>~~BE)~~||0.782<br>~~EEEEEEE~~|—<br>~~EEEEEEE~~|0.699<br>~~EEEEEEE~~|—<br>~~EEEEEEE~~|0.699<br>~~EEEEEEE~~|—<br>~~EEEEEEE~~|UI<br>~~EEEEEEE~~|
|fDATA<br>~~BE)~~|DDRX4 Serial<br>Input Data<br>Speed<br>~~BE)~~||—<br>~~EEEEEEE~~|800<br>~~EEEEEEE~~|—<br>~~EEEEEEE~~|630<br>~~EEEEEEE~~|—<br>~~EEEEEEE~~|630<br>~~EEEEEEE~~|Mbps<br>~~EEEEEEE~~|
|fDDRX4<br>~~BE)~~<br>~~Fo~~|DDRX4 ECLK<br>Frequency<br>~~BE)~~<br>~~Fo~~||—<br>~~EEEEEEE~~<br>~~ee~~|400<br>~~EEEEEEE~~<br>~~ee~~|—<br>~~EEEEEEE~~<br>~~ee~~|315<br>~~EEEEEEE~~<br>~~eee~~|—<br>~~EEEEEEE~~<br>~~eee~~|315<br>~~EEEEEEE~~<br>~~eee~~|MHz<br>~~EEEEEEE~~<br>~~eee~~|
|fSCLK<br>~~BE)~~<br>~~Fo~~|SCLK<br>Frequency<br>~~BE)~~<br>~~Fo~~||—<br>~~EEEEEEE~~<br>~~ee~~|100<br>~~EEEEEEE~~<br>~~ee~~|—<br>~~EEEEEEE~~<br>~~ee~~|79<br>~~EEEEEEE~~<br>~~eee~~|—<br>~~EEEEEEE~~<br>~~eee~~|79<br>~~EEEEEEE~~<br>~~eee~~|MHz<br>~~EEEEEEE~~<br>~~eee~~|



FPGA-DS-02032-2.8 

64 

**MachXO3 Family** 

**Data Sheet** 

|**Parameter**<br>~~et~~|**Description**<br>~~et~~<br>~~|~~|**Device**<br>~~be~~|**–6**<br>**(Commercial/Industrial)**<br>~~be~~|**–6**<br>**(Commercial/Industrial)**<br>~~be~~|**–5**<br>**(Commercial/Industrial)**<br>~~be~~|**–5**<br>**(Commercial/Industrial)**<br>~~be~~|**–5**<br>**(Automotive)**<br>~~be~~|**–5**<br>**(Automotive)**<br>~~be~~|**Units**<br>~~be~~|
|---|---|---|---|---|---|---|---|---|---|
||||**Min.**<br>~~be~~<br>~~a~~|**Max.**<br>~~be~~|**Min.**<br>~~be~~|**Max.**<br>~~be~~|**Min.**<br>~~be~~|**Max.**<br>~~be~~||
|**Generic DDR4 Inputs with Clock and Data Centered at Pin Using PCLK Pin for Clock Input – GDDRX4_RX.ECLK.Centered8**<br>~~et~~<br>~~|be~~<br>~~a~~<br>~~Ee~~<br>~~BE)EEEEEEE~~||||||||||
|tSU<br>~~Ee~~<br>~~BE)~~|Input Data<br>Setup Before<br>ECLK<br>~~Ee~~<br>~~BE)~~|MachXO3L/LF<br>devices,<br>bottom side<br>only<br>~~Ee~~<br>~~BE)~~|0.233<br>~~Ee~~<br>~~EEEEEEE~~|—<br>~~Ee~~<br>~~EEEEEEE~~|0.233<br>~~Ee~~<br>~~EEEEEEE~~|—<br>~~Ee~~<br>~~EEEEEEE~~|0.233<br>~~Ee~~<br>~~EEEEEEE~~|—<br>~~Ee~~<br>~~EEEEEEE~~|ns<br>~~Ee~~<br>~~EEEEEEE~~|
|tHO<br>~~BE)~~|Input Data<br>Hold After<br>ECLK<br>~~BE)~~||0.287<br>~~EEEEEEE~~|—<br>~~EEEEEEE~~|0.287<br>~~EEEEEEE~~|—<br>~~EEEEEEE~~|0.287<br>~~EEEEEEE~~|—<br>~~EEEEEEE~~|ns<br>~~EEEEEEE~~|
|fDATA<br>~~BE)~~|DDRX4 Serial<br>Input Data<br>Speed<br>~~BE)~~||—<br>~~EEEEEEE~~|800<br>~~EEEEEEE~~|—<br>~~EEEEEEE~~|630<br>~~EEEEEEE~~|—<br>~~EEEEEEE~~|630<br>~~EEEEEEE~~|Mbps<br>~~EEEEEEE~~|
|fDDRX4<br>~~BE)~~|DDRX4 ECLK<br>Frequency<br>~~BE)~~||—<br>~~EEEEEEE~~|400<br>~~EEEEEEE~~|—<br>~~EEEEEEE~~|315<br>~~EEEEEEE~~|—<br>~~EEEEEEE~~|315<br>~~EEEEEEE~~|MHz<br>~~EEEEEEE~~|
|fSCLK<br>~~BE)~~<br>~~a~~|SCLK<br>Frequency<br>~~BE)~~<br>~~a~~||—<br>~~EEEEEEE~~|100<br>~~EEEEEEE~~|—<br>~~EEEEEEE~~|79<br>~~EEEEEEE~~|—<br>~~EEEEEEE~~|79<br>~~EEEEEEE~~|MHz<br>~~EEEEEEE~~|
|**7:1 LVDS Inputs(GDDR71_RX.ECLK.7:1)9**<br>~~BE) EEEEEEE~~<br>~~a~~<br>~~Pe~~||||||||||
|tDVA<br>~~Pe~~|Input Data<br>Valid After<br>ECLK<br>~~Pe~~|MaxhXO3L/LF<br>devices,<br>bottom side<br>only<br>~~Pe~~|—<br>~~Pe~~|0.290<br>~~Pe~~|—<br>~~Pe~~|0.320<br>~~Pe~~|—<br>~~Pe~~|0.257<br>~~Pe~~|UI<br>~~Pe~~|
|tDVE|Input Data<br>Hold After<br>ECLK||0.739|—|0.699|—|0.699|—|UI|
|fDATA|DDR71 Serial<br>Input Data<br>Speed||—|756|—|630|—|630|Mbps|
|fDDR71|DDR71 ECLK<br>Frequency||—|378|—|315|—|315|MHz|
|fCLKIN|7:1 Input<br>Clock<br>Frequency<br>(SCLK)<br>(minimum<br>limited byPLL)||—|108|—|90|—|90|MHz|
|**MIPI D-PHY Inputs with Clock and Data Centered at Pin Using PCLK Pin for Clock Input - GDDRX4_RX.ECLK.Centered10, 11, 12 **<br>~~ET~~||||||||||
|tSU15<br>~~BS~~|Input Data<br>Setup Before<br>ECLK<br>~~BS~~|All<br>MachXO3L/LF<br>devices,<br>bottom side<br>only<br>|0.200<br>~~BREECH~~|—<br>~~BREECH~~|0.200<br>~~BREECH~~|—<br>~~BREECH~~|0.295<br>~~BREECH~~|—<br>~~BREECH~~|UI<br>~~BREECH~~|
|tHO15<br>~~BS~~|Input Data<br>Hold After<br>ECLK<br>~~BS~~||0.200<br>~~BREECH~~|—<br>~~BREECH~~|0.200<br>~~BREECH~~|—<br>~~BREECH~~|0.312<br>~~BREECH~~|—<br>~~BREECH~~|UI<br>~~BREECH~~|
|fDATA14<br>~~BS~~|MIPI D-PHY<br>Input Data<br>Speed<br>~~BS~~||—<br>~~BREECH~~|900<br>~~BREECH~~|—<br>~~BREECH~~|900<br>~~BREECH~~|—<br>~~BREECH~~|900<br>~~BREECH~~|Mbps<br>~~BREECH~~|
|fDDRX414<br>~~BS~~|MIPI D-PHY<br>ECLK<br>Frequency<br>~~BS~~||—<br>~~BREECH~~|450<br>~~BREECH~~|—<br>~~BREECH~~|450<br>~~BREECH~~|—<br>~~BREECH~~|450<br>~~BREECH~~|MHz<br>~~BREECH~~|
|fSCLK14<br>~~BS~~|SCLK<br>Frequency<br>~~BS~~||—<br>~~BREECH~~|112.5<br>~~BREECH~~|—<br>~~BREECH~~|112.5<br>~~BREECH~~|—<br>~~BREECH~~|112.5<br>~~BREECH~~|MHz<br>~~BREECH~~|



FPGA-DS-02032-2.8 

65 

**MachXO3 Family Data Sheet** 

|**Parameter**<br>~~et~~|**Description**<br>~~et~~<br>~~|~~|**Device**<br>~~be~~|**–6**<br>**(Commercial/Industrial)**<br>~~be~~|**–6**<br>**(Commercial/Industrial)**<br>~~be~~|**–5**<br>**(Commercial/Industrial)**<br>~~be~~|**–5**<br>**(Commercial/Industrial)**<br>~~be~~|**–5**<br>**(Automotive)**<br>~~be~~|**–5**<br>**(Automotive)**<br>~~be~~|**Units**<br>~~be~~|
|---|---|---|---|---|---|---|---|---|---|
||||**Min.**<br>~~be~~<br>~~a~~|**Max.**<br>~~be~~|**Min.**<br>~~be~~|**Max.**<br>~~be~~|**Min.**<br>~~be~~|**Max.**<br>~~be~~||
|**Generic DDR Outputs with Clock and Data Aligned at Pin Using PCLK Pin for Clock Input– GDDRX1_TX.SCLK.Aligned8 **<br>~~et~~<br>~~|be~~<br>~~a~~<br>~~Ee~~||||||||||
|tDIA<br>~~Ee~~<br>~~Se~~|Output Data<br>Invalid After<br>CLK Output<br>~~Ee~~<br>~~Se~~|All<br>MachXO3L/LF<br>devices,<br>all sides<br>~~Ee~~<br> ~~eee~~|—<br>~~Ee~~<br>~~eee~~|0.520<br>~~Ee~~<br>~~eee~~|—<br>~~Ee~~<br>~~eee~~|0.550<br>~~Ee~~<br>~~eee~~|—<br>~~Ee~~<br>~~eee~~|0.550<br>~~Ee~~<br>~~eee~~|ns<br>~~Ee~~<br>~~eee~~|
|tDIB<br>~~Se~~|Output Data<br>Invalid Before<br>CLK Output<br>~~Se~~||—<br>~~eee~~|0.520<br>~~eee~~|—<br>~~eee~~|0.550<br>~~eee~~|—<br>~~eee~~|0.550<br>~~eee~~|ns<br>~~eee~~|
|fDATA<br>~~Se~~<br>~~Ss~~|DDRX1 Output<br>Data Speed<br>~~Se~~<br>~~A~~||—<br>~~eee~~|300<br>~~eee~~|—<br>~~eee~~|250<br>~~eee~~|—<br>~~eee~~|250<br>~~eee~~|Mbps<br>~~eee~~|
|fDDRX1<br>~~Se~~<br>~~Ss~~|DDRX1 SCLK<br>frequency<br>~~Se ~~<br>~~A~~||—<br>~~eee~~|150<br>~~eee~~|—<br>~~eee~~|125<br>~~eee~~|—<br>~~eee~~|125<br>~~eee~~|MHz<br>~~eee~~|
|**Generic DDR Outputs with Clock and Data Centered at Pin Using PCLK Pin for Clock Input– GDDRX1_TX.SCLK.Centered8 **<br>~~SsA~~<br>~~pn~~||||||||||
|tDVB<br>~~pn~~<br>~~BS~~|Output Data<br>Valid Before<br>CLK Output<br>~~pn~~<br>~~BS~~|All<br>MachXO3L/LF<br>devices,<br>all sides<br>~~pn~~<br>|1.210<br>~~pn~~<br>~~REECE~~|—<br>~~pn~~<br>~~REECE~~|1.510<br>~~pn~~<br>~~REECE~~|—<br>~~pn~~<br>~~REECE~~|1.510<br>~~pn~~<br>~~REECE~~|—<br>~~pn~~<br>~~REECE~~|ns<br>~~pn~~<br>~~REECE~~|
|tDVA<br>~~BS~~|Output Data<br>Valid After CLK<br>Output<br>~~BS~~||1.210<br>~~REECE~~|—<br>~~REECE~~|1.510<br>~~REECE~~|—<br>~~REECE~~|1.510<br>~~REECE~~|—<br>~~REECE~~|ns<br>~~REECE~~|
|fDATA<br>~~BS~~|DDRX1 Output<br>Data Speed<br>~~BS~~||—<br>~~REECE~~|300<br>~~REECE~~|—<br>~~REECE~~|250<br>~~REECE~~|—<br>~~REECE~~|250<br>~~REECE~~|Mbps<br>~~REECE~~|
|fDDRX1<br>~~BS~~|DDRX1 SCLK<br>Frequency<br>(minimum<br>limited byPLL)<br>~~BS ~~||—<br> ~~REECE~~|150<br>~~REECE~~|—<br>~~REECE~~|125<br>~~REECE~~|—<br>~~REECE~~|125<br>~~REECE~~|MHz<br>~~REECE~~|
|**Generic DDRX2 Outputs with Clock and Data Aligned at Pin Using PCLK Pin for Clock Input– GDDRX2_TX.ECLK.Aligned8 **<br>~~PE~~<br>~~BE)EEEEEEE~~||||||||||
|tDIA<br>~~BE)~~|Output Data<br>Invalid After<br>CLK Output<br>~~BE)~~|MachXO3L/LF<br>devices, top<br>side only<br>~~BE)~~|—<br>~~EEEEEEE~~|0.200<br>~~EEEEEEE~~|—<br>~~EEEEEEE~~|0.215<br>~~EEEEEEE~~|—<br>~~EEEEEEE~~|0.215<br>~~EEEEEEE~~|ns<br>~~EEEEEEE~~|
|tDIB<br>~~BE)~~|Output Data<br>Invalid Before<br>CLK Output<br>~~BE)~~||—<br>~~EEEEEEE~~|0.200<br>~~EEEEEEE~~|—<br>~~EEEEEEE~~|0.215<br>~~EEEEEEE~~|—<br>~~EEEEEEE~~|0.215<br>~~EEEEEEE~~|ns<br>~~EEEEEEE~~|
|fDATA<br>~~BE)~~|DDRX2 Serial<br>Output Data<br>Speed<br>~~BE)~~||—<br>~~EEEEEEE~~|664<br>~~EEEEEEE~~|—<br>~~EEEEEEE~~|554<br>~~EEEEEEE~~|—<br>~~EEEEEEE~~|554<br>~~EEEEEEE~~|Mbps<br>~~EEEEEEE~~|
|fDDRX2<br>~~BE)~~|DDRX2 ECLK<br>frequency<br>~~BE)~~||—<br>~~EEEEEEE~~|332<br>~~EEEEEEE~~|—<br>~~EEEEEEE~~|277<br>~~EEEEEEE~~|—<br>~~EEEEEEE~~|277<br>~~EEEEEEE~~|MHz<br>~~EEEEEEE~~|
|fSCLK<br>~~BE)~~<br>~~i~~|SCLK<br>Frequency<br>~~BE)~~<br>~~i~~||—<br>~~EEEEEEE~~|166<br>~~EEEEEEE~~|—<br>~~EEEEEEE~~|139<br>~~EEEEEEE~~|—<br>~~EEEEEEE~~|139<br>~~EEEEEEE~~|MHz<br>~~EEEEEEE~~|



© 2014-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02032-2.8 

66 

**MachXO3 Family** 

**Data Sheet** 

**–6 –5 –5 Parameter Description Device (Commercial/Industrial) (Commercial/Industrial) (Automotive) Units Min. Max. Min. Max. Min. Max.** ~~a Eeet~~ **Generic DDRX2 Outputs with Clock and Data Centered at Pin Usin** ~~|be~~ **g PCLK Pin for Clock Input – GDDRX2_TX.ECLK.Centered[8, 9]** Output Data tDVB Valid Before 0.535 — 0.670 — 0.670 — ns CLK Output Output Data tDVA Valid After CLK 0.535 — 0.670 — 0.658 — ns Output DDRX2 Serial MachXO3L/LF fDATA Output Data devices, top — 664 — 554 — 554 Mbps Speed side only DDRX2 ECLK fDDRX2 Frequency (minimum — 332 — 277 — 277 MHz limited by PLL) SCLK fSCLK Frequency — 166 — 139 — 139 MHz ~~He}Pe~~ **Generic DDRX4 Outputs with Clock and Data Aligned at Pin Usin** ~~EEE~~ **g PCLK Pin for Clock Input – GDDRX4_TX.ECLK.Aligned[8, 9]** Output Data tDIA Invalid After — 0.200 — 0.215 — 0.215 ns CLK Output Output Data tDIB Invalid Before — 0.200 — 0.215 — 0.215 ns CLK Output MachXO3L/LF DDRX4 Serial devices, top fDATA Output Data side only — 800 — 630 — 630 Mbps Speed DDRX4 ECLK fDDRX4 Frequency — 400 — 315 — 315 MHz SCLK ~~aBE)~~ fSCLK Frequency ~~EEEEEEE~~ — 100 — 79 — 79 MHz ~~PE~~ **Generic DDRX4 Outputs with Clock and Data Centered at Pin Using PCLK Pin for Clock Input – GDDRX4_TX.ECLK.Centered[8, 9]** Output Data tDVB Valid Before 0.455 — 0.570 — 0.570 — ns CLK Output Output Data tDVA Valid After CLK 0.455 — 0.570 — 0.549 — ns Output DDRX4 Serial MachXO3L/LF fDATA Output Data devices, top — 800 — 630 — 630 Mbps Speed side only DDRX4 ECLK fDDRX4 Frequency (minimum — 400 — 315 — 315 MHz limited by PLL) SCLK fSCLK Frequency — 100 — 79 — 79 MHz ~~Fe} EEE~~ © 2014-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02032-2.8 

67 

**MachXO3 Family Data Sheet** 

|**Parameter**<br>~~pt~~|**Description**<br>~~pt~~|**Device**|**–6**<br>**(Commercial/Industrial)**<br>~~eses~~|**–6**<br>**(Commercial/Industrial)**<br>~~eses~~|**–5**<br>**(Commercial/Industrial)**<br>~~es ee~~|**–5**<br>**(Commercial/Industrial)**<br>~~es ee~~|**–5**<br>**(Automotive)**|**–5**<br>**(Automotive)**|**Units**|
|---|---|---|---|---|---|---|---|---|---|
||||**Min.**<br>~~es~~|**Max.**<br>~~es~~|**Min.**<br>~~es ee~~|**Max.**<br>~~ee~~|**Min.**|**Max.**||
|**7:1 LVDS Outputs– GDDR71_TX.ECLK.7:18, 9 **<br>~~pt~~<br>~~es eses ee~~<br>~~Rn~~||||||||||
|tDIB<br>~~Rn~~|Output Data<br>Invalid Before<br>CLK Output<br>~~Rn~~|MachXO3L/LF<br>devices, top<br>side only<br>~~Rn~~|—<br>~~Rn~~|0.160<br>~~Rn~~|—<br>~~Rn~~|0.180<br>~~Rn~~|—<br>~~Rn~~|0.180<br>~~Rn~~|ns<br>~~Rn~~|
|tDIA|Output Data<br>Invalid After<br>CLK Output||—|0.160|—|0.180|—|0.201|ns|
|fDATA|DDR71 Serial<br>Output Data<br>Speed||—|756|—|630|—|630|Mbps|
|fDDR71|DDR71 ECLK<br>Frequency||—|378|—|315|—|315|MHz|
|fCLKOUT|7:1 Output<br>Clock<br>Frequency<br>(SCLK)<br>(minimum<br>limited byPLL)||—|108|—|90|—|90|MHz|
|**MIPI D-PHY Outputs with Clock and Data Centered at Pin Using PCLK Pin for Clock Input– GDDRX4_TX.ECLK.Centered10, 11, 12 **<br>~~Aa]EE~~||||||||||
|tDVB<br>~~Aa]~~|Output Data<br>Valid Before<br>CLK Output<br>~~Aa]~~|All<br>MachXO3L/LF<br>devices, top<br>side only<br>~~Aa]~~|0.200<br>~~EE~~|—<br>~~EE~~|0.200<br>~~EE~~|—<br>~~EE~~|0.200<br>~~EE~~|—<br>~~EE~~|UI<br>~~EE~~|
|tDVA<br>~~Aa]~~|Output Data<br>Valid After CLK<br>Output<br>~~Aa]~~||0.200<br>~~EE~~|—<br>~~EE~~|0.200<br>~~EE~~|—<br>~~EE~~|0.200<br>~~EE~~|—<br>~~EE~~|UI<br>~~EE~~|
|fDATA<br>~~Aa]~~|MIPI D-PHY<br>Output Data<br>Speed<br>~~Aa]~~||—<br>~~EE~~|900<br>~~EE~~|—<br>~~EE~~|900<br>~~EE~~|—<br>~~EE~~|900<br>~~EE~~|Mbps<br>~~EE~~|
|FDDRX4<br>~~Aa]~~|MIPI D-PHY<br>ECLK<br>Frequency<br>(minimum<br>limited byPLL)<br>~~Aa]~~||—<br>~~EE~~|450<br>~~EE~~|—<br>~~EE~~|450<br>~~EE~~|—<br>~~EE~~|450<br>~~EE~~|MHz<br>~~EE~~|
|fSCLK<br>~~Aa]~~|SCLK<br>Frequency<br>~~Aa]~~||—<br>~~EE~~|112.5<br>~~EE~~|—<br>~~EE~~|112.5<br>~~EE~~|—<br>~~EE~~|112.5<br>~~EE~~|MHz<br>~~EE~~|



2. General I/O timing numbers based on LVCMOS 2.5, 8 mA, 0pf load, fast slew rate. 

3. Generic DDR timing numbers based on LVDS I/O (for input, output, and clock ports). 

4. 7:1 LVDS (GDDR71) uses the LVDS I/O standard (for input, output, and clock ports). 

5. For Generic DDRX1 mode tSU = tHO = (tDVE - tDVA - 0.03 ns)/2. 

6. The tSU_DEL and tH_DEL values use the SCLK_ZERHOLD default step size. Each step is 105 ps (–6), 113 ps (–5), 120 ps (–4). 

7. This number for general purpose usage. Duty cycle tolerance is +/–10%. 

8. Duty cycle is +/– 5% for system usage. 

9. Performance is calculated with 0.225 UI. 

10. Performance is calculated with 0.20 UI. 

11. Performance for Industrial devices are only supported with VCC between 1.16 V to 1.24 V. 

12. Performance for Industrial devices and –5 devices are not modeled in the Diamond design tool. 

13. The above timing numbers are generated using the Diamond design tool. Exact performance may vary with the device selected. 

14. Above 800 Mbps is only supported with WLCSP and csfBGA packages. 

© 2014-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

68 

FPGA-DS-02032-2.8 

**MachXO3 Family Data Sheet** 

15. Between 800 Mbps to 900 Mbps: 

   - VIDTH exceeds the MIPI D-PHY Input DC Conditions (Table 3.16) and can be calculated with the equation tSU or tH = - 0.0005*VIDTH + 0.3284 

   - Example calculations: 

   - tSU and tHO = 0.28 with VIDTH = 100 mV 

   - tSU and tHO = 0.25 with VIDTH = 170 mV 

   - tSU and tHO = 0.20 with VIDTH = 270 mV 

**==> picture [333 x 159] intentionally omitted <==**

**----- Start of picture text -----**<br>
CLK<br>|<br>Data 0 1 2 3 4 5 6 0<br>(4-6 bits) HOEK ROHN ENO HONK ENO ENO<br>> ,<br>tDVA<br>tDVE<br>Figure 3.6.Receiver GDDR71_RX. Waveforms<br>CLK<br>a<br>|<br>Data<br>(4-6 bits) XX 0 XXXXX 1 XXX 2 XY 3 XXX 4 5 KKK 6 Kl Y 0<br>> ! ke tDIB<br>tDIA<br>**----- End of picture text -----**<br>


**Figure 3.7. Transmitter GDDR71_TX. Waveforms** 

## **3.18. sysCLOCK PLL Timing** 

Over recommended operating conditions. 

**Table 3.22. sysCLOCK PLL Timing** 

|**Parameter**<br>~~a~~|**Descriptions**<br>~~ee~~|**Conditions**<br>~~es~~|**–6**<br>**(Commercial/Industrial)**|**–6**<br>**(Commercial/Industrial)**|**–5**<br>**(Automotive)**|**–5**<br>**(Automotive)**|**Units**|
|---|---|---|---|---|---|---|---|
||||**Min.**<br>~~es~~|**Max.**|**Min.**|**Max.**||
|fIN<br>~~a~~|Input Clock Frequency<br>(CLKI, CLKFB)<br>~~ee~~|—<br>~~es~~|7<br>~~es~~|400|7|400|MHz|
|fOUT<br>~~a~~|Output Clock Frequency<br>(CLKOP, CLKOS, CLKOS2)<br>~~ee ~~|—<br> ~~es~~|1.5625<br>~~es~~|400|1.5625|400|MHz|
|fOUT2|Output Frequency (CLKOS3<br>cascaded from CLKOS2)|—|0.0122|400|0.0122|400|MHz|
|fVCO<br>~~a~~|PLL VCO Frequency<br>~~ee~~|—<br>~~ee ee~~|200<br>~~ee~~|800<br>~~ee~~|200<br>~~ee~~|800|MHz|
|fPFD<br>~~a~~<br>~~RC~~|Phase Detector Input<br>Frequency<br>~~ee~~|—<br>~~ee ee~~|7<br>~~ee~~|400<br>~~ee~~|7<br>~~ee~~|400|MHz|
|**AC Characteristics**<br>~~a~~<br>~~ee ee ee~~<br>~~ee ee~~<br>~~RC~~||||||||
|tDT<br>~~RC~~<br>~~ee~~|Output Clock Duty Cycle<br>~~nD~~|Without duty trim<br>selected3<br>~~nD~~|45<br>~~nD~~|55<br>~~nD~~|45<br>~~nD~~|55<br>~~nD~~|%<br>~~nD~~|
|tDT_TRIM7<br>~~ee~~|Edge DutyTrim Accuracy<br>~~nD~~|—<br>~~nD~~|–75<br>~~nD~~|75<br>~~nD~~|N/A<br>~~nD~~|N/A<br>~~nD~~|%<br>~~nD~~|
|tPH4<br>~~ee~~<br>~~ee~~|Output Phase Accuracy<br>~~nD~~<br>~~ee~~|—<br>~~nD~~<br>~~Df~~|–6<br>~~nD~~<br>~~Df~~|6<br>~~nD~~|–6<br>~~nD~~|6<br>~~nD~~|%<br>~~nD~~|



© 2014-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02032-2.8 

69 

**MachXO3 Family Data Sheet** 

|**Parameter**<br>~~r~~|**Descriptions**<br>~~re~~<br>~~ee~~|**Conditions**<br>~~eee~~<br>~~en~~|**–6**<br>**(Commercial/Industrial)**<br>~~eee~~|**–6**<br>**(Commercial/Industrial)**<br>~~eee~~|**–5**<br>**(Automotive)**<br>~~eee~~|**–5**<br>**(Automotive)**<br>~~eee~~|**Units**<br>~~eee~~<br>~~eee~~|
|---|---|---|---|---|---|---|---|
||||**Min.**<br>~~eee~~<br>~~en~~|**Max.**<br>~~eee~~<br>~~en~~|**Min.**<br>~~eee~~<br>~~en~~|**Max.**<br>~~eee~~||
|tOPJIT1, 8<br>~~r~~|Output Clock Period Jitter<br>~~re~~<br>~~ee~~<br>~~ee~~|fOUT > 100 MHz<br>~~eee~~<br>~~en~~|—<br>~~eee~~<br>~~en~~|150<br>~~eee~~<br>~~en~~|—<br>~~eee~~<br>~~en~~|150<br>~~eee~~|psp-p<br>~~eee~~<br>~~eee~~|
|||fOUT < 100 MHz<br>~~en~~<br>~~**e**~~<br>~~ee~~|—<br>~~en~~<br>~~**e**~~<br>~~eee~~|0.007<br>~~en~~<br>~~**e**s~~<br>~~eee~~|—<br>~~en~~<br>~~s~~<br>~~eee~~|0.010<br>~~s~~<br>~~eee~~|UIPP<br>~~eee~~<br>~~s~~<br>~~eee~~|
||Output Clock Cycle-to-cycle<br>Jitter<br>~~ee~~<br>~~ee~~|fOUT > 100 MHz<br>~~en~~<br>~~**e**~~<br>~~ee~~|—<br>~~en~~<br>~~**e**~~<br>~~eee~~|180<br>~~en~~<br>~~**e**s~~<br>~~eee~~|—<br>~~en~~<br>~~s~~<br>~~eee~~|180<br>~~s~~<br>~~eee~~|psp-p<br>~~eee~~<br>~~s~~<br>~~eee~~|
|||fOUT < 100 MHz<br>~~**e**~~<br>~~ee~~|—<br>~~**e**~~<br>~~eee~~|0.009<br>~~**e**s~~<br>~~eee~~<br>~~d~~|—<br>~~s~~<br>~~eee~~<br>~~d~~|0.015<br>~~s~~<br>~~eee~~<br>~~d~~|UIPP<br>~~s~~<br>~~eee~~<br>~~d~~|
||Output Clock Phase Jitter<br>~~ee ~~<br>~~Bf~~<br>|fPFD > 100 MHz<br>~~**e**~~<br> ~~ee~~<br>~~Bf~~|—<br>~~**e**~~<br>~~eee~~<br>~~Bf~~|160<br>~~**e**s~~<br>~~eee~~<br>~~d~~<br>~~Bf~~|—<br>~~s~~<br>~~eee ~~<br>~~d~~|160<br>~~s~~<br> ~~eee~~<br>~~d~~|psp-p<br>~~s~~<br>~~eee~~<br>~~d~~|
|||fPFD < 100 MHz<br>~~Bf~~<br>~~ed~~<br>|—<br>~~Bf~~<br>~~ed~~<br>|0.011<br>~~Bf~~<br>~~ed~~<br>|—<br>~~ed~~<br>|0.011<br>~~ed~~<br>|UIPP<br>~~ed~~<br>~~—~~|
||Output Clock Period Jitter<br>(Fractional-N)<br>~~Bf~~<br>~~rrr~~<br>~~ee~~|fOUT > 100 MHz<br>~~Bf~~<br>~~ed~~<br>~~rrr~~<br>|—<br>~~Bf~~<br>~~ed~~<br>~~rrr~~<br>~~es~~<br>|230<br>~~Bf~~<br>~~ed~~<br>~~rrr~~<br>~~ee~~<br>|—<br>~~ed~~<br>~~rrr~~<br>~~ee~~<br>|TBD<br>~~ed~~<br>~~rrr~~<br>~~ee~~<br>|psp-p<br>~~ed~~<br>~~rrr—~~<br>|
|||fOUT < 100 MHz<br>~~rrr~~<br>~~es~~<br>|—<br>~~rrr~~<br>~~es~~<br>~~es~~<br>|0.12<br>~~rrr~~<br>~~es~~<br>~~ee~~<br>|—<br>~~rrr~~<br>~~es~~<br>~~ee~~<br>|TBD<br>~~rrr~~<br>~~es~~<br>~~ee~~<br>|UIPP<br>~~rrr—~~<br>~~es~~<br>|
||Output Clock Cycle-to-cycle<br>Jitter (Fractional-N)<br>~~rrr~~<br>~~ee~~|fOUT > 100 MHz<br>~~rrr~~<br>~~es~~<br>|—<br>~~rrr~~<br>~~es~~<br>~~es~~<br>|230<br>~~rrr~~<br>~~es~~<br>~~ee~~<br>|—<br>~~rrr~~<br>~~es~~<br>~~ee~~<br>|TBD<br>~~rrr~~<br>~~es~~<br>~~ee~~<br>|psp-p<br>~~rrr—~~<br>~~es~~<br>|
|||fOUT < 100 MHz<br>~~es~~<br>~~GO~~|—<br>~~es~~<br>~~es~~<br>~~GO~~|0.12<br>~~ee~~<br>~~es~~<br>~~GD~~|—<br>~~ee~~<br>~~es~~<br>~~GD~~|TBD<br>~~ee~~<br>~~es~~<br>~~I~~|UIPP<br>~~es~~|
|tSPO<br>~~en~~<br>~~es~~|Static Phase Offset<br>~~ee~~<br>~~en~~|Divider ratio = integer<br><br>~~en~~<br>~~GO~~|–120<br>~~es ~~<br><br>~~en~~<br>~~GO~~|120<br> ~~ee~~<br><br>~~en~~<br>~~GD~~<br>~~Gs~~|–141<br>~~ee~~<br><br>~~en~~<br>~~GD~~<br>~~Gs~~|141<br>~~ee~~<br><br>~~en~~<br>~~I~~<br>~~I~~|ps<br><br>~~en~~|
|tW<br>~~en~~<br>~~Gs~~<br>~~es~~|Output Clock Pulse Width<br>~~en~~<br>~~Gs~~|At 90% or 10%3<br>~~en~~<br>~~GO~~<br>~~Gs~~|0.9<br>~~en~~<br>~~GO ~~<br>~~Gs~~|—<br>~~en~~<br> ~~GD~~<br>~~Gs~~<br>~~Gs~~|—<br>~~en~~<br>~~GD ~~<br>~~Gs~~<br>~~Gs~~|—<br>~~en~~<br> ~~I~~<br>~~Gs~~<br>~~I~~|ns<br>~~en~~<br>~~Gs~~|
|tLOCK2, 5<br>~~Gs~~<br>~~es~~<br>~~es~~|PLL Lock-in Time<br>~~Gs~~<br>|—<br>~~Gs~~<br>|—<br>~~Gs~~<br>|15<br>~~Gs~~<br>~~Gs~~<br>|—<br>~~Gs~~<br>~~Gs~~<br>|17.5<br>~~Gs~~<br>~~I~~<br>|ms<br>~~Gs~~<br>|
|tUNLOCK<br>~~es~~<br>~~esrr~~|PLL Unlock Time<br>~~rr~~|—<br>~~rr~~|—<br>~~rr —ry—ry———~~|50<br>~~Gs~~<br>~~—ry—ry———~~|—<br>~~Gs ~~<br>~~—ry—ry———~~|50<br> ~~I~~<br>~~—ry—ry———~~|ns<br>~~—ry—ry———~~|
|tIPJIT6<br>~~esrr~~|Input Clock Period Jitter<br>~~rr~~|fPFD ≥ 20 MHz<br>~~rr~~|—<br>~~rr —ry—ry———~~|1,000<br>~~—ry—ry———~~|—<br>~~—ry—ry———~~|1,000<br>~~—ry—ry———~~|psp-p<br>~~—ry—ry———~~|
|||fPFD < 20 MHz<br>~~rr~~<br>~~se~~<br>~~GO~~|—<br>~~rr —ry—ry———~~<br>~~se~~<br>~~GO~~|0.02<br>~~—ry—ry———~~<br>~~se~~<br>~~GD~~|0.8<br>~~—ry—ry———~~<br>~~se~~<br>~~GD~~|0.02<br>~~—ry—ry———~~<br>~~se~~<br>~~I~~|UIPP<br>~~—ry—ry———~~<br>~~se~~|
|tHI<br>~~rr~~<br>~~en~~|Input Clock High Time<br>~~rr~~<br>~~en~~|90% to 90%<br>~~rr~~<br>~~en~~<br>~~GO~~|0.5<br>~~rr —ry—ry———~~<br>~~en~~<br>~~GO~~|—<br>~~—ry—ry———~~<br>~~en~~<br>~~GD~~<br>~~GD~~|0.8<br>~~—ry—ry———~~<br>~~en~~<br>~~GD~~<br>~~GD~~|—<br>~~—ry—ry———~~<br>~~en~~<br>~~I~~<br>~~I~~|ns<br>~~—ry—ry———~~<br>~~en~~|
|tLO<br>~~en~~<br>~~GO~~<br>~~es~~|Input Clock Low Time<br>~~en~~<br>~~GO~~|10% to 10%<br>~~en~~<br>~~GO~~<br>~~GO~~|0.5<br>~~en~~<br>~~GO ~~<br>~~GO~~|—<br>~~en~~<br> ~~GD~~<br>~~GO~~<br>~~GD~~<br>~~Gs~~|0.5<br>~~en~~<br>~~GD ~~<br>~~GO~~<br>~~GD~~<br>~~Gs~~|—<br>~~en~~<br> ~~I~~<br>~~GO~~<br>~~I~~<br>~~I~~|ns<br>~~en~~<br>~~GO~~|
|tSTABLE5<br>~~GO~~<br>~~Gs~~<br>~~es~~|STANDBY High to PLL Stable<br>~~GO~~<br>~~Gs~~|—<br>~~GO~~<br>~~Gs~~|—<br>~~GO~~<br>~~Gs~~|15<br>~~GO~~<br>~~GD~~<br>~~Gs~~<br>~~Gs~~|—<br>~~GO~~<br>~~GD ~~<br>~~Gs~~<br>~~Gs~~|15<br>~~GO~~<br> ~~I~~<br>~~Gs~~<br>~~I~~|ms<br>~~GO~~<br>~~Gs~~|
|tRST<br>~~Gs~~<br>~~es~~<br>~~es~~|RST/RESETM Pulse Width<br>~~Gs~~<br>|—<br>~~Gs~~<br>|1<br>~~Gs~~<br>|—<br>~~Gs~~<br>~~Gs~~<br>|1<br>~~Gs~~<br>~~Gs~~<br>|—<br>~~Gs~~<br>~~I~~<br>|ns<br>~~Gs~~<br>|
|tRSTREC<br>~~es~~<br>~~es~~|RST RecoveryTime<br>|—<br>|1<br>|—<br>~~Gs~~<br>|2.46<br>~~Gs ~~<br>|—<br> ~~I~~<br>|ns<br>|
|tRST_DIV<br>~~esGG~~|RESETC/D Pulse Width<br>~~GG~~|—<br>~~GG~~|10<br>~~GG~~|—<br>~~GG~~|10<br>~~GG~~|—<br>~~GG~~|ns<br>~~GG~~|
|tRSTREC_DIV<br>~~GG~~|RESETC/D RecoveryTime<br>~~GG~~|—<br>~~GG~~|1<br>~~GG~~|—<br>~~GG~~|2.33<br>~~GG~~|—<br>~~GG~~|ns<br>~~GG~~|
|tROTATE-<br>SETUP|PHASESTEP Setup Time|—|10|—|10|—|ns|
|tROTATE_WD|PHASESTEP Pulse Width|—|4|—|4|—|VCO<br>Cycles|



## **Notes** : 

1. Period jitter sample is taken over 10,000 samples of the primary PLL output with a clean reference clock. Cycle-to-cycle jitter is taken over 1000 cycles. Phase jitter is taken over 2000 cycles. All values per JESD65B. 

2. Output clock is valid after tLOCK for PLL reset and dynamic delay adjustment. 

3. Using LVDS output buffers. 

4. CLKOS as compared to CLKOP output for one phase step at the maximum VCO frequency. See MachXO3 sysCLOCK PLL Design and Usage Guide (FPGA-TN-02058) for more details. 

5. At minimum fPFD. As the fPFD increases the time will decrease to approximately 60% the value listed. 

6. Maximum allowed jitter on an input clock. PLL unlock may occur if the input jitter exceeds this specification. Jitter on the input clock may be transferred to the output clocks, resulting in jitter measurements outside the output specifications listed in this table. 

7. Edge Duty Trim Accuracy is a percentage of the setting value. Settings available are 70 ps, 140 ps, and 280 ps in addition to the default value of none. 

Edge Duty Trim Accuracy does not apply to Automotive. 

8. Jitter values measured with the internal oscillator operating. The jitter values will increase with loading of the PLD fabric and in the presence of SSO noise. 

© 2014-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

70 

FPGA-DS-02032-2.8 

**MachXO3 Family Data Sheet** 

## **3.19. Oscillator Output Frequency** 

**Table 3.23. Oscillator Output Frequency** 

|**Symbol**<br>~~eee~~|**Parameter**<br>~~eee~~|**–6**<br>**(Commercial/Industrial)**<br>~~ee~~<br>~~eee~~|**–6**<br>**(Commercial/Industrial)**<br>~~ee~~<br>~~eee~~|**–6**<br>**(Commercial/Industrial)**<br>~~ee~~<br>~~eee~~|**–5**<br>**(Automotive)**<br>~~ee~~<br>~~eee~~|**–5**<br>**(Automotive)**<br>~~ee~~<br>~~eee~~|**–5**<br>**(Automotive)**<br>~~ee~~<br>~~eee~~|**Units**<br>~~ee~~|
|---|---|---|---|---|---|---|---|---|
|||**Min.**<br>~~ee~~<br>~~eee~~|**Typ.**<br>~~ee~~<br>~~eee~~|**Max**<br>~~ee~~<br>~~eee~~|**Min.**<br>~~ee~~<br>~~eee~~|**Typ.**<br>~~ee~~<br>~~eee~~|**Max**<br>~~ee~~<br>~~eee~~||
|fMAX<br>~~a~~|Oscillator Output Frequency (Commercial<br>Grade Devices, 0 to 85°C)<br>~~a~~|125.685<br>~~a~~|133<br>~~a~~|140.315<br>~~a~~|—<br>~~a~~|—<br>~~a~~|—<br>~~a~~|MHz<br>~~a~~|
||Oscillator Output Frequency (Industrial Grade<br>Devices, –40 °C to 100 °C)<br>~~EE~~|124.355<br>~~EE~~|133<br>~~EE~~|141.645<br>~~EE~~|—<br>~~EE~~|—<br>~~EE~~|—<br>~~EE~~|MHz<br>~~EE~~|
||Oscillator Output Frequency (Automotive<br>Grade Devices, -40 to 125°C)<br>~~EE~~<br>|—<br>~~EE~~<br>|—<br>~~EE~~<br>|—<br>~~EE~~<br>|122.360<br>~~EE~~<br>~~Gs~~<br>|122.360<br>133<br>~~EE~~<br>~~Gs~~<br>|143.640<br>~~EE~~<br>~~Gs~~<br>|143.640<br>MHz<br>~~EE~~<br>|
|tDT<br>~~GG~~<br>~~a~~<br>~~a~~|Output Clock Duty Cycle<br>~~GG~~<br><br>|43<br>~~GG~~<br><br>|50<br>~~GG~~<br><br>|57<br>~~GG~~<br><br>~~CO~~<br>|43<br>~~GG~~<br>~~Gs~~<br><br>~~CO~~<br>|50<br>~~GG~~<br>~~Gs~~<br><br>~~CO~~<br>|57<br>~~GG~~<br>~~Gs~~<br><br>|%<br>~~GG~~<br><br>|
|tOPJIT<br>~~a~~<br>~~a~~|Output Clock Period Jitter<br>~~GG~~<br>|—<br>~~GG~~<br>|—<br>~~GG~~<br>|0.02<br>~~GG~~<br>~~CO~~<br>|—<br>~~Gs~~<br>~~GG~~<br>~~CO~~<br><br>~~CO~~|—<br>~~Gs~~<br>~~GG~~<br>~~CO~~<br><br>~~CO~~|0.02<br>~~Gs~~<br>~~GG~~<br>|UIPP<br>~~GG~~<br>|
|tSTABLEOSC<br>~~a GG~~|STDBY Low to Oscillator Stable<br>~~GG~~|—<br>~~GG~~|—<br>~~GG~~|0.1<br>~~CO~~<br>~~GG~~|—<br>~~CO~~<br>~~GG~~<br>~~CO~~|—<br>~~CO~~<br>~~GG~~<br>~~CO~~|0.1<br>~~GG~~|µs<br>~~GG~~|



**Note:** Output Clock Period Jitter specified at 133 MHz. The values for lower frequencies will be smaller UIPP. The typical value for 133 MHz is 95 ps and for 2.08 MHz the typical value is 1.54 ns. 

## **3.20. NVCM/Flash Download Time** 

**Table 3.24. NVCM/Flash Download Time** 

|**Symbol**|**Parameter**|**Device**|**Typ. **|**Units**|
|---|---|---|---|---|
|tREFRESH|POR to Device I/O Active|LCMXO3L/LF-640|1.9|ms|
|||LCMXO3L/LF-1300|1.9|ms|
|||LCMXO3L/LF-1300 256-Ball Package|1.4|ms|
|||LCMXO3L/LF-2100|1.4|ms|
|||LCMXO3L/LF-2100 324-Ball Package|2.4|ms|
|||LCMXO3L/LF-4300|2.4|ms|
|||LCMXO3L/LF-4300 400-Ball Package|3.8|ms|
|||LCMXO3L/LF-6900|3.8|ms|
|||LCMXO3L/LF-9400C|5.2|ms|



**Notes** : 

- Assumes sysMEM EBR initialized to an all zero pattern if they are used. 

- The NVCM/Flash download time is measured starting from the maximum voltage of POR trip point. 

- The worst case can be up to 1.75 times the Typ value. 

© 2014-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02032-2.8 

71 

**MachXO3 Family Data Sheet** 

## **3.21. JTAG Port Timing Specifications** 

**Table 3.25. JTAG Port Timing Specifications** 

|**Symbol**|**Parameter**|**Commercial/Industrial**|**Commercial/Industrial**|**Automotive**|**Automotive**|**Units**|
|---|---|---|---|---|---|---|
|||**Min.**|**Max.**|**Min.**|**Max.**||
|fMAX|TCK clock frequency|—|25|—|25|MHz|
|tBTCPH|TCK[BSCAN]clockpulse width high|20|—|20|—|ns|
|tBTCPL|TCK[BSCAN]clockpulse width low|20|—|20|—|ns|
|tBTS|TCK[BSCAN]setuptime|10|—|10|—|ns|
|tBTH|TCK[BSCAN]hold time|8|—|10|—|ns|
|tBTCO|TAP controller fallingedge of clock to valid output|—|10|—|10|ns|
|tBTCODIS|TAP controller fallingedge of clock to valid disable|—|10|—|12|ns|
|tBTCOEN|TAP controller fallingedge of clock to valid enable|—|10|—|12|ns|
|tBTCRS|BSCAN test capture register setuptime|8|—|8|—|ns|
|tBTCRH|BSCAN test capture register hold time|20|—|20|—|ns|
|tBUTCO|BSCAN test update register, falling edge of clock to<br>valid output|—|25|—|25|ns|
|tBTUODIS|BSCAN test update register, falling edge of clock to<br>valid disable|—|25|—|27|ns|
|tBTUPOEN|BSCAN test update register, falling edge of clock to<br>valid enable|—|25|—|25|ns|



**Figure 3.8. JTAG Port Timing Waveforms** 

© 2014-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

72 

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**MachXO3 Family Data Sheet** 

## **3.22. sysCONFIG Port Timing Specifications** 

**Table 3.26. sysCONFIG Port Timing Specifications** 

|**Symbol**<br>~~a~~|**Parameter**<br>~~a~~|**Parameter**<br>~~a~~|**Commercial/Industrial**<br>~~a~~<br>~~ee~~<br>~~ee~~|**Commercial/Industrial**<br>~~a~~<br>~~ee~~<br>~~ee~~|**Automotive**<br>~~a~~|**Automotive**<br>~~a~~|**Units**<br>~~a~~|
|---|---|---|---|---|---|---|---|
||||**Min.**<br>~~a~~<br>~~ee~~|**Max.**<br>~~a~~<br>~~ee~~|**Min.**<br>~~a~~|**Max.**<br>~~a~~||
|**All Configuration Modes**<br>~~ee~~<br>~~ee~~<br>~~Re~~||||||||
|tPRGM<br>~~Re~~<br>~~aen~~|PROGRAMN lowpulse accept<br>~~Re~~||55<br>~~Re~~|—<br>~~Re~~|55<br>~~Re~~|—<br>~~Re~~|ns<br>~~Re~~|
|tPRGMJ<br>~~aen~~<br>~~|~~<br>~~|~~|PROGRAMN lowpulse rejection<br>~~FREEFE~~||—<br>~~FREEFE~~|25<br>~~FREEFE~~|—<br>~~FREEFE~~|25<br>~~FREEFE~~|ns<br>~~FREEFE~~|
|tINITL<br>~~en~~<br>~~|~~<br>~~|~~<br>~~ee~~|INITN low time<br>|LCMXO3L/LF-640/<br>LCMXO3L/LF-1300<br>~~FREEFE~~|—<br>~~FREEFE~~|55<br>~~FREEFE~~|—<br>~~FREEFE~~|—<br>~~FREEFE~~|us<br>~~FREEFE~~|
|||LCMXO3L/LF-1300<br>256-Ball Package/<br>LCMXO3L/LF-2100<br>~~FREEFE~~|—<br>~~FREEFE~~|70<br>~~FREEFE~~|—<br>~~FREEFE~~|93<br>~~FREEFE~~|us<br>~~FREEFE~~|
|||LCMXO3L/LF-2100<br>324-Ball Package/<br>LCMXO3-4300<br>~~FREEFE~~|—<br>~~FREEFE~~|105<br>~~FREEFE~~|—<br>~~FREEFE~~|130<br>~~FREEFE~~|us<br>~~FREEFE~~|
|||LCMXO3L/LF-4300<br>400-Ball Package/<br>LCMXO3-6900<br>~~FREEFE~~|—<br>~~FREEFE~~|130<br>~~FREEFE~~|—<br>~~FREEFE~~|—<br>~~FREEFE~~|us<br>~~FREEFE~~|
|||LCMXO3L/LF-9400C<br>~~FREEFE~~|—<br>~~FREEFE~~|175<br>~~FREEFE~~|—<br>~~FREEFE~~|—<br>~~FREEFE~~|us<br>~~FREEFE~~|
|tDPPINIT<br>~~|~~<br>~~| ~~<br>~~ee~~<br>~~ee~~|PROGRAMN low to INITN low<br> ~~FREEFE~~<br>~~GG~~||—<br>~~FREEFE~~<br>~~GG~~|150<br>~~FREEFE~~<br>~~GG~~|—<br>~~FREEFE~~<br>~~GG~~|150<br>~~FREEFE~~<br>~~GG~~|ns<br>~~FREEFE~~<br>~~GG~~|
|tDPPDONE<br>~~ee~~<br>~~ee~~<br>~~ee~~|PROGRAMN low to DONE low<br>~~GG~~||—<br>~~GG~~|150<br>~~GG~~|—<br>~~GG~~|150<br>~~GG~~|ns<br>~~GG~~|
|tIODISS<br>~~ee~~<br>~~ee~~|PROGRAMN low to I/O disable<br>~~GG~~||—<br>~~GG~~|120<br>~~GG~~|—<br>~~GG~~|120<br>~~GG~~|ns<br>~~GG~~|
|**Slave SPI**<br>~~ee~~<br>~~Re~~||||||||
|fMAX<br>~~Re~~<br>~~a~~<br>~~ne~~|CCLK clock frequency<br>~~Re~~||—<br>~~Re~~|66<br>~~Re~~|—<br>~~Re~~|66<br>~~Re~~|MHz<br>~~Re~~|
|tCCLKH<br>~~a~~<br>~~ne~~<br>~~ee~~|CCLK clockpulse width high||7.5|—|7.5|—|ns|
|tCCLKL<br>~~ne~~<br>~~ee~~|CCLK clockpulse width low||7.5<br>~~GG~~|—<br>~~GG~~|7.5|—|ns|
|tSTSU<br>~~ee~~<br>~~fe~~<br>~~ee~~|CCLK setuptime<br>~~fe~~||2<br>~~fe~~<br>~~GG~~<br>~~GG~~|—<br>~~fe~~<br>~~GG~~<br>~~GG~~|2<br>~~fe~~|—<br>~~fe~~|ns<br>~~fe~~|
|tSTH<br>~~Ge~~<br>~~ee~~|CCLK hold time<br>~~Ge~~||0<br>~~GG~~<br>~~Ge~~<br>~~GG~~|—<br>~~GG~~<br>~~Ge~~<br>~~GG~~|0<br>~~Ge~~|—<br>~~Ge~~|ns<br>~~Ge~~|
|tSTCO<br>~~ee~~<br>~~ee~~|CCLK fallingedge to valid output<br>~~ds~~||—<br>~~GG~~<br>~~ds~~|10<br>~~GG~~<br>~~ds~~|—<br>~~ds~~|14<br>~~ds~~|ns<br>~~ds~~|
|tSTOZ<br>~~ee~~<br>~~ee~~|CCLK fallingedge to valid disable<br>~~ds~~||—<br>~~GG~~<br>~~ds~~|10<br>~~GG~~<br>~~ds~~|—<br>~~ds~~|12<br>~~ds~~|ns<br>~~ds~~|
|tSTOV<br>~~ee~~<br>~~a~~|CCLK fallingedge to valid enable<br>~~ds~~||—<br>~~ds~~|10<br>~~ds~~|—<br>~~ds~~|14<br>~~ds~~|ns<br>~~ds~~|
|tSCS<br>~~a~~<br>~~a~~|Chipselect high time<br>||25<br><br>~~GG~~|—<br><br>~~GG~~|25<br>|—<br>|ns<br>|
|tSCSS<br>~~afe~~|Chipselect setuptime<br>~~fe~~||3<br>~~fe~~<br>~~GG~~|—<br>~~fe~~<br>~~GG~~|3<br>~~fe~~|—<br>~~fe~~|ns<br>~~fe~~|
|tSCSH<br>~~fe~~<br>~~GF~~|Chipselect hold time<br>~~fe~~<br>~~GF~~||3<br>~~fe~~<br>~~GG~~<br>~~GF~~|—<br>~~fe~~<br>~~GG~~<br>~~GF~~|3<br>~~fe~~<br>~~GF~~|—<br>~~fe~~<br>~~GF~~|ns<br>~~fe~~<br>~~GF~~|
|**Master SPI**<br>~~En~~<br>~~a~~||||||||
|fMAX<br>~~a~~|MCLK clock frequency||—|133|—|66|MHz|
|tMCLKH<br>~~a~~<br>~~a~~|MCLK clockpulse width high||3.75|—|7.5|—|ns|
|tMCLKL<br>~~a~~<br>~~a~~|MCLK clockpulse width low||3.75|—|7.5|—|ns|
|tSTSU<br>~~a~~<br>~~a~~|MCLK setuptime<br>||5<br><br>~~GG~~|—<br><br>~~GG~~|6<br>|—<br>|ns<br>|
|tSTH<br>~~afe~~<br>~~ee~~|MCLK hold time<br>~~fe~~||1<br>~~fe~~<br>~~GG~~<br>~~GG~~|—<br>~~fe~~<br>~~GG~~<br>~~GG~~|3<br>~~fe~~|—<br>~~fe~~|ns<br>~~fe~~|
|tCSSPI<br>~~fe~~<br>~~fe~~<br>~~ee~~|INITN high to chipselect low<br>~~fe~~<br>~~fe~~||100<br>~~fe~~<br>~~GG~~<br>~~fe~~<br>~~GG~~|200<br>~~fe~~<br>~~GG~~<br>~~fe~~<br>~~GG~~|100<br>~~fe~~<br>~~fe~~|200<br>~~fe~~<br>~~fe~~|ns<br>~~fe~~<br>~~fe~~|
|tMCLK<br>~~ee~~|INITN high to first MCLK edge||0.75<br>~~GG~~|1<br>~~GG~~|0.75|1|us|



© 2014-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02032-2.8 

73 

**MachXO3 Family Data Sheet** 

## **3.23. I[2] C Port Timing Specifications** 

**Table 3.27. I[2] C Port Timing Specification Symbol Parameter Min. Max. Units** fMAX Maximum SCL clock frequency — 400 kHz ~~ee~~ **Notes:**  MachXO3L/LF supports the following modes:  Standard-mode (Sm), with a bit rate up to 100 kb/s (user and configuration mode)  Fast-mode (Fm), with a bit rate up to 400 kb/s (user and configuration mode)  Refer to the I[2] C specification for timing requirements. **3.24. SPI Port Timing Specifications Table 3.28. SPI Port Timing Specifications Symbol Parameter Min. Max. Units** fMAX Maximum SCK clock frequency — 45 MHz ~~ee~~ **Note:** Applies to user mode only. For configuration mode timing specifications, refer to sysCONFIG Port Timing Specifications ~~ee~~ table in this data sheet. 

## **3.25. Switching Test Conditions** 

Figure 3.9 shows the output test load used for AC testing. The specific values for resistance, capacitance, voltage, and other test conditions are shown in Table 3.29. 

**==> picture [163 x 72] intentionally omitted <==**

**----- Start of picture text -----**<br>
V T<br>R1<br>DUT  Test Point<br>CL<br>**----- End of picture text -----**<br>


## **Figure 3.9. Output Test Load, LVTTL and LVCMOS Standards** 

**Table 3.29. Test Fixture Required Components, Non-Terminated Interfaces** 

|**Test Condition**|**R1**|**CL**|**Timing Ref.**|**VT**|
|---|---|---|---|---|
|LVTTL and LVCMOS settings (L -> H, H -> L)||0 pF|LVTTL, LVCMOS 3.3 = 1.5 V|—|
||||LVCMOS 2.5 = VCCIO/2|—|
||||LVCMOS 1.8 = VCCIO/2|—|
||||LVCMOS 1.5 = VCCIO/2|—|
||||LVCMOS 1.2 = VCCIO/2|—|
|LVTTL and LVCMOS 3.3 (Z -> H)|188|0 pF|1.5|VOL|
|LVTTL and LVCMOS 3.3 (Z -> L)|||1.5|VOH|
|Other LVCMOS (Z -> H)|||VCCIO/2|VOL|
|Other LVCMOS (Z -> L)|||VCCIO/2|VOH|
|LVTTL + LVCMOS (H -> Z)|||VOH – 0.15|VOL|
|LVTTL + LVCMOS (L -> Z)|||VOL – 0.15|VOH|



**Note** : Output test conditions for all other interfaces are determined by the respective standards. 

© 2014-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02032-2.8 

74 

**MachXO3 Family Data Sheet** 

## **4. Signal Descriptions** 

|**Signal Name**<br>~~ee~~|**I/O**<br>~~ee~~|**Descriptions**<br>~~ee~~|
|---|---|---|
|**General Purpose**<br>~~ee~~<br>~~Cn~~<br>~~lz~~|||
|P[Edge] [Row/Column<br>Number]_[A/B/C/D]<br>~~Cn~~<br>~~lz~~|I/O<br>~~Cn~~<br>~~lz~~|[Edge] indicates the edge of the device on which the pad is located. Valid edge designations<br>are L (Left), B (Bottom), R (Right), T (Top).<br>[Row/Column Number] indicates the PFU row or the column of the device on which the PIO<br>Group exists. When Edge is T (Top) or (Bottom), only need to specify Row Number. When<br>Edge is L (Left) or R (Right), only need to specify Column Number.<br>[A/B/C/D] indicates the PIO within the group to which the pad is connected.<br>Some of these user-programmable pins are shared with special function pins. When not used<br>as special function pins, these pins can be programmed as I/Os for user logic.<br>During configuration of the user-programmable I/Os, the user has an option to tri-state the<br>I/Os and enable an internal pull-up, pull-down or buskeeper resistor. This option also applies<br>to unused pins (or those not bonded to a package pin). The default during configuration is for<br>user-programmable I/Os to be tri-stated with an internal pull-down resistor enabled. When<br>the device is erased, I/Os will be tri-stated with an internal pull-down resistor enabled. Some<br>pins, such as PROGRAMN and JTAG pins, default to tri-stated I/Os with pull-up resistors<br>enabled when the device is erased.<br>~~Cn~~<br>~~lz~~|
|NC<br>~~lz~~|—<br>~~lz~~|No connect.<br>~~lz~~|
|GND<br>~~lz~~<br>~~Ge~~<br>~~a~~|—<br>~~lz~~<br>~~Ge~~<br>~~ee~~|GND – Ground. Dedicatedpins. It is recommended that all GNDs are tied together.<br>~~lz~~<br>~~Ge~~|
|VCC<br>~~Ge~~<br>~~a~~|—<br>~~Ge~~<br>~~ee~~|VCC– The power supply pins for core logic. Dedicated pins. It is recommended that all VCCs are<br>tied to the same supply.<br>~~Ge~~|
|VCCIOx<br>~~a~~<br>~~ee~~<br>~~Re~~|—<br>~~ee~~<br>~~ee~~|VCCIO– The power supply pins for I/O Bank x. Dedicated pins. It is recommended that all VCCIOs<br>located in the same bank are tied to the same supply.<br>~~ee~~|
|**PLL and Clock Functions** (Used as user-programmable I/Opins when not used for PLL or clockpins)<br>~~ee~~<br>~~Rea~~<br>~~ee~~|||
|[LOC]_GPLL[T, C]_IN<br>~~Rea~~<br>~~a~~|—<br>~~ee~~<br>~~ee~~|Reference Clock (PLL) input pads: [LOC] indicates location. Valid designations are L (Left PLL)<br>and R(Right PLL). T = true and C = complement.|
|[LOC]_GPLL[T, C]_FB<br>~~a~~<br>~~a~~<br>~~Re~~|—<br>~~ee~~<br>~~ee~~<br>|Optional Feedback (PLL) input pads: [LOC] indicates location. Valid designations are L (Left<br>PLL)and R(Right PLL). T = true and C = complement.<br>|
|PCLK[n]_[2:0]<br>~~a~~<br>~~Re~~|—<br>~~ee~~<br>|PrimaryClockpads. One to three clockpadsper side.<br>|
|**Test and Programming** (Dual functionpins used for test accessport and duringsysCONFIG™)<br>~~ReCe~~|||
|TMS<br>~~Ce~~<br>~~ee~~|I<br>~~Ce~~<br>~~ee~~|Test Mode Select inputpin, used to control the 1149.1 state machine.<br>~~Ce~~<br>~~ee~~|
|TCK<br>~~ee~~<br>~~es~~<br>~~rr~~|I<br>~~ee~~<br>~~es~~<br>~~ee~~|Test Clock inputpin, used to clock the 1149.1 state machine.<br>~~ee~~<br>~~es~~|
|TDI<br>~~es~~<br>~~rr~~|I<br>~~es~~<br>~~ee~~|Test Data inputpin, used to load data into the device usingan 1149.1 state machine.<br>~~es~~|
|TDO<br>~~rr ~~|O<br> ~~ee~~|Outputpin – Test Data outputpin used to shift data out of the device using1149.1.|
|JTAGENB|I|Optionally controls behavior of TDI, TDO, TMS, TCK. If the device is configured to use the<br>JTAG pins (TDI, TDO, TMS, TCK) as general purpose I/O, then:<br>If JTAGENB is low: TDI, TDO, TMS and TCK can function a general purpose I/O.<br>If JTAGENB is high: TDI, TDO, TMS and TCK function as JTAG pins.<br>For more details, refer toMachXO3 Programming and Configuration Usage Guide (FPGA-TN-<br>02055).|
|**Configuration**(Dual functionpins used duringsysCONFIG)<br>~~|~~<br>~~es~~<br>~~a~~|||
|PROGRAMN<br>~~|~~<br>~~a~~<br>~~a~~|I<br>~~|~~<br>~~a~~<br>~~es~~|Initiates configuration sequence when asserted low. Thispin always has an activepull-up.<br>~~|~~<br>~~a~~|
|INITN<br>~~a~~|I/O<br>~~es~~|Open Drain pin. Indicates the FPGA is ready to be configured. During configuration, a pull-up<br>is enabled.|
|DONE<br>~~a~~|I/O|Open Drain pin. Indicates that the configuration sequence is complete, and the start-up<br>sequence is inprogress.|
|MCLK/CCLK<br>~~a~~<br>~~a~~<br>~~Ge~~|I/O<br>~~ee~~<br>~~Ge~~|Input Configuration Clock for configuring an FPGA in Slave SPI mode. Output Configuration<br>Clock for configuringan FPGA in SPI and SPIm configuration modes.<br>~~ee~~<br>~~Ge~~|
|SN<br>~~a~~<br>~~Ge~~|I<br>~~ee~~<br>~~Ge~~|Slave SPI active low chipselect input.<br>~~ee~~<br>~~Ge~~|
|CSSPIN<br>~~Ge~~<br>~~Ge~~|I/O<br>~~Ge~~<br>~~Ge~~|Master SPI active low chipselect output.<br>~~Ge~~<br>~~Ge~~|
|SI/SPISI<br>~~Ge~~|I/O<br>~~Ge~~|Slave SPI serial data input and master SPI serial data output.<br>~~Ge~~|



© 2014-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02032-2.8 

75 

**MachXO3 Family Data Sheet** 

|**Signal Name**|**I/O**|**Descriptions**|
|---|---|---|
|SO/SPISO|I/O|Slave SPI serial data output and master SPI serial data input.|
|SCL|I/O|Slave I2C clock input and master I2C clock output.|
|SDA|I/O|Slave I2C data input and master I2C data output.|



## **4.1. Pin Information Summary** 

**Table 4.2. MachXO3L/LF-640 and MachXO3L/LF-1300 Pin Summary** 

|~~CE~~|**MachXO3L/**<br>**LF-640**<br>~~CE~~|**MachXO3L/LF-1300**<br>~~CE~~|**MachXO3L/LF-1300**<br>~~CE~~|**MachXO3L/LF-1300**<br>~~CE~~|**MachXO3L/LF-1300**<br>~~CE~~|
|---|---|---|---|---|---|
||**CSFBGA121**<br>~~CE~~|**WLCSP36**<br>~~CE~~|**CSFBGA121**<br>~~CE~~|**CSFBGA256**<br>~~CE~~|**CABGA256**<br>~~CE~~|
|**General Purpose I/O per Bank**<br>~~Ce~~||||||
|Bank 0<br>~~Ce~~<br>~~a~~|25<br>~~Ce~~|16<br>~~Ce~~|25<br>~~Ce~~|51<br>~~Ce~~|51<br>~~Ce~~|
|Bank 1<br>~~a~~<br>~~a~~|26|0|26|52|52|
|Bank 2<br>~~a~~<br>~~a~~|26|9|26|52|52|
|Bank 3<br>~~a~~<br>~~a~~|24|4|24|16|16|
|Bank 4<br>~~a~~<br>~~ee~~|0<br>~~ee~~|0<br>~~ee~~|0<br>~~ee~~|16<br>~~ee~~|16<br>~~ee~~|
|Bank 5<br>~~a~~|0<br>~~a~~|0<br>~~a~~|0<br>~~a~~|20<br>~~a~~|20<br>~~a~~|
|**Total General Purpose Single Ended I/O **<br>~~a~~<br>~~a~~|101<br>~~a~~<br>~~a~~|29<br>~~a~~<br>~~a~~|101<br>~~a~~<br>~~a~~|207<br>~~a~~<br>~~a~~|207<br>~~a~~<br>~~a~~|
|**Minimum Reserved for Configuration***<br>~~a~~<br>~~a~~|1<br>~~a~~<br>~~a~~|1<br>~~a~~<br>~~a~~|1<br>~~a~~<br>~~a~~|1<br>~~a~~<br>~~a~~|1<br>~~a~~<br>~~a~~|
|**Maximum Programmable Single Ended I/O **<br>~~a~~<br>~~a~~|100<br>~~a~~<br>~~a~~|28<br>~~a~~<br>~~a~~|100<br>~~a~~<br>~~a~~|206<br>~~a~~<br>~~a~~|206<br>~~a~~<br>~~a~~|
|**Differential I/O per Bank**<br>~~a~~<br>~~Ct~~||||||
|Bank 0<br>~~Ct~~<br>~~eG~~|12<br>~~Ct~~<br>~~eG~~|8<br>~~Ct~~<br>~~eG~~|12<br>~~Ct~~<br>~~eG~~|25<br>~~Ct~~<br>~~eG~~|25<br>~~Ct~~<br>~~eG~~|
|Bank 1<br>~~ee~~|13<br>~~ee~~|0<br>~~ee~~|13<br>~~ee~~|26<br>~~ee~~|26<br>~~ee~~|
|Bank 2<br>~~a~~|13<br>~~a~~|4<br>~~a~~|13<br>~~a~~|26<br>~~a~~|26<br>~~a~~|
|Bank 3<br>~~a~~<br>~~a~~|11<br>~~a~~<br>~~a~~|2<br>~~a~~<br>~~a~~|11<br>~~a~~<br>~~a~~|8<br>~~a~~<br>~~a~~|8<br>~~a~~<br>~~a~~|
|Bank 4<br>~~a~~<br>~~a~~|0<br>~~a~~<br>~~a~~|0<br>~~a~~<br>~~a~~|0<br>~~a~~<br>~~a~~|8<br>~~a~~<br>~~a~~|8<br>~~a~~<br>~~a~~|
|Bank 5<br>~~a~~<br>~~ee~~|0<br>~~a~~<br>~~ee~~|0<br>~~a~~<br>~~ee~~|0<br>~~a~~<br>~~ee~~|10<br>~~a~~<br>~~ee~~|10<br>~~a~~<br>~~ee~~|
|**Total General Purpose Differential I/O **<br>~~ee~~<br>~~ee~~<br>~~a~~|49<br>~~ee~~<br>~~ee~~|14<br>~~ee~~<br>~~ee~~|49<br>~~ee~~<br>~~ee~~|103<br>~~ee~~<br>~~ee~~|103<br>~~ee~~<br>~~ee~~|
|**Dual Function I/O**<br>~~ee~~<br>~~a~~|33<br>~~ee~~|25<br>~~ee~~|33<br>~~ee~~|33<br>~~ee~~|33<br>~~ee~~|
|**Number 7:1 or 8:1 Gearboxes**<br>~~a~~<br>~~Cn~~||||||
|Number of 7:1 or 8:1 Output Gearbox Available(Bank 0)<br>~~Cn~~<br>~~a~~|7<br>~~Cn~~|3<br>~~Cn~~|7<br>~~Cn~~|14<br>~~Cn~~|14<br>~~Cn~~|
|Number of 7:1 or 8:1 Input Gearbox Available(Bank 2)<br>~~a~~<br>~~ee~~|7<br>~~ee~~|2<br>~~ee~~|7<br>~~ee~~|14<br>~~ee~~|14<br>~~ee~~|
|**High-speed Differential Outputs**<br>~~ee~~<br>~~Cn~~||||||
|Bank 0<br>~~Cn~~<br>~~ee~~<br>~~CR~~|7<br>~~Cn~~<br>~~ee~~|3<br>~~Cn~~<br>~~ee~~|7<br>~~Cn~~<br>~~ee~~|14<br>~~Cn~~<br>~~ee~~|14<br>~~Cn~~<br>~~ee~~|
|**VCCIO Pins**<br>~~ee~~<br>~~CR~~||||||
|Bank 0<br>~~CR~~<br>~~ee~~|1<br>~~ee~~|1<br>~~ee~~|1<br>~~ee~~|4<br>~~ee~~|4<br>~~ee~~|
|Bank 1<br>~~I~~|1|0|1|3|4|
|Bank 2<br>~~I~~<br>~~a~~|1|1|1|4|4|
|Bank 3<br>~~a~~<br>~~a~~|3|1|3|2|1|
|Bank 4<br>~~a~~<br>~~ee~~|0<br>~~ee~~|0<br>~~ee~~|0<br>~~ee~~|2<br>~~ee~~|2<br>~~ee~~|
|Bank 5<br>~~ee~~<br>~~ee~~<br>~~a~~|0<br>~~ee~~<br>~~ee~~|0<br>~~ee~~<br>~~ee~~|0<br>~~ee~~<br>~~ee~~|2<br>~~ee~~<br>~~ee~~|1<br>~~ee~~<br>~~ee~~|
|**VCC**<br>~~ee~~<br>~~a~~<br>~~a~~|4<br>~~ee~~|2<br>~~ee~~|4<br>~~ee~~|8<br>~~ee~~|8<br>~~ee~~|
|**GND**<br>~~a~~<br>~~a~~|10|2|10|24|24|
|**NC**<br>~~aI~~|0|0|0|0|1|
|**Total Count of Bonded Pins**<br>~~I~~<br>~~ee~~|**121**<br>~~ee~~|**36**<br>~~ee~~|**121**<br>~~ee~~|**256**<br>~~ee~~|**256**<br>~~ee~~|



***Note:** One pin for JTAGENB or four pins for JTAG. 

© 2014-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02032-2.8 

76 

**MachXO3 Family Data Sheet** 

**Table 4.3. MachXO3L/LF-2100 Pin Summary** 

|~~ee~~|**MachXO3L/LF-2100**<br>~~pe~~<br>~~eeeeeees eee~~|**MachXO3L/LF-2100**<br>~~pe~~<br>~~eeeeeees eee~~|**MachXO3L/LF-2100**<br>~~pe~~<br>~~eeeeeees eee~~|**MachXO3L/LF-2100**<br>~~pe~~<br>~~eeeeeees eee~~|**MachXO3L/LF-2100**<br>~~pe~~<br>~~eeeeeees eee~~|**MachXO3L/LF-2100**<br>~~pe~~<br>~~eeeeeees eee~~|
|---|---|---|---|---|---|---|
||**WLCSP49**<br>~~pe~~<br>~~eee~~|**CSFBGA121**<br>~~pe~~<br>~~eee~~|**CSFBGA121**<br>**CSFBGA256**<br>~~pe~~<br>~~es eee~~|**CSFBGA324**<br>~~pe~~<br>~~eee~~|**CSFBGA324**<br>**CABGA256**<br>~~pe~~<br>~~eee~~|**CABGA324**<br>~~pe~~<br>~~eee~~|
|**General Purpose I/Oper Bank**<br>~~pe~~<br>~~ee eee eee es eee~~<br>~~Pn~~<br>~~GO~~|||||||
|Bank 0<br>~~GG~~|20<br>~~GG~~|25<br>~~GG~~|51<br>~~GG~~|72<br>~~GG~~<br>~~GO~~|51<br>~~GG~~<br>~~GO~~|72<br>~~GG~~|
|Bank 1<br>~~GG~~<br>~~GO~~|0<br>~~GG~~<br>~~GO~~|26<br>~~GG~~<br>~~GO~~|52<br>~~GG~~<br>~~GO~~|62<br>~~GG~~<br>~~GO~~<br>~~GO~~|52<br>~~GG~~<br>~~GO~~<br>~~GO~~|68<br>~~GG~~<br>~~GO~~|
|Bank 2<br>~~GO~~<br>~~dD~~|13<br>~~GO~~<br>~~dD~~|26<br>~~GO~~<br>~~dD~~|52<br>~~GO~~<br>~~dD~~|72<br>~~GO~~<br>~~dD~~|52<br>~~GO~~<br>~~dD~~|72<br>~~GO~~<br>~~dD~~|
|Bank 3<br>~~dD~~<br>~~dG~~|0<br>~~dD~~<br>~~dG~~|7<br>~~dD~~<br>~~dG~~|16<br>~~dD~~<br>~~dG~~|22<br>~~dD~~<br>~~dG~~|16<br>~~dD~~<br>~~dG~~|24<br>~~dD~~<br>~~dG~~|
|Bank 4<br>~~dG~~<br>~~dG~~|0<br>~~dG~~<br>~~dG~~|7<br>~~dG~~<br>~~dG~~|16<br>~~dG~~<br>~~dG~~|14<br>~~dG~~<br>~~dG~~|16<br>~~dG~~<br>~~dG~~|16<br>~~dG~~<br>~~dG~~|
|Bank 5<br>~~dG~~<br>~~Ge~~|6<br>~~dG~~<br>~~Ge ~~|10<br>~~dG~~<br> ~~GG~~|20<br>~~dG~~<br>~~GG~~|27<br>~~dG~~<br>~~GG~~|20<br>~~dG~~|28<br>~~dG~~|
|**Total General Purpose Single Ended I/O **<br>~~Ge~~|39<br>~~Ge ~~|101<br> ~~GG~~|207<br>~~GG~~|269<br>~~GG~~|207|280|
|**Minimum Reserved for Configuration***<br>~~dG~~|1<br>~~dG~~|1<br>~~dG~~|1<br>~~dG~~|1<br>~~dG~~<br>~~GO~~|1<br>~~dG~~<br>~~GO~~|1<br>~~dG~~|
|**Maximum Programmable Single Ended I/O **<br>~~dG~~<br>~~DD~~|38<br>~~dG~~<br>~~DD~~|100<br>~~dG~~<br>~~DD~~|206<br>~~dG~~<br>~~DD~~|268<br>~~dG~~<br>~~DD~~<br>~~GO~~|206<br>~~dG~~<br>~~DD~~<br>~~GO~~|279<br>~~dG~~<br>~~DD~~|
|**Differential I/O per Bank**<br>~~DD~~<br>~~GO~~<br>~~Rn~~<br>~~GO~~|||||||
|Bank 0<br>~~Rn~~<br>~~GG~~|10<br>~~Rn~~<br>~~GG~~|12<br>~~Rn~~<br>~~GG~~|25<br>~~Rn~~<br>~~GG~~|36<br>~~Rn~~<br>~~GG~~<br>~~GO~~|25<br>~~Rn~~<br>~~GG~~|36<br>~~Rn~~<br>~~GG~~|
|Bank 1<br>~~GG~~<br>~~GG~~|0<br>~~GG~~<br>~~GG~~|13<br>~~GG~~<br>~~GG~~|26<br>~~GG~~<br>~~GG~~|30<br>~~GG~~<br>~~GO~~<br>~~GG~~|26<br>~~GG~~<br>~~GG~~|34<br>~~GG~~<br>~~GG~~|
|Bank 2<br>~~GG~~<br>~~Ge~~|6<br>~~GG~~<br>~~Ge ~~|13<br>~~GG~~<br> ~~GG~~|26<br>~~GG~~<br>~~GG~~|36<br>~~GG~~<br>~~GG~~|26<br>~~GG~~|36<br>~~GG~~|
|Bank 3<br>~~Ge~~|0<br>~~Ge ~~|3<br> ~~GG~~|8<br>~~GG~~|10<br>~~GG~~|8|12|
|Bank 4<br>~~dG~~|0<br>~~dG~~|3<br>~~dG~~|8<br>~~dG~~|6<br>~~dG~~|8<br>~~dG~~|8<br>~~dG~~|
|Bank 5<br>~~dG~~<br>~~dD~~|3<br>~~dG~~<br>~~dD~~|5<br>~~dG~~<br>~~dD~~|10<br>~~dG~~<br>~~dD~~|13<br>~~dG~~<br>~~dD~~|10<br>~~dG~~<br>~~dD~~|14<br>~~dG~~<br>~~dD~~|
|**Total General Purpose Differential I/O **<br>~~dD~~<br>~~dG~~|19<br>~~dD~~<br>~~dG~~|49<br>~~dD~~<br>~~dG~~|103<br>~~dD~~<br>~~dG~~|131<br>~~dD~~<br>~~dG~~|103<br>~~dD~~<br>~~dG~~|140<br>~~dD~~<br>~~dG~~|
|**Dual Function I/O**<br>~~dG~~<br>~~DO~~|25<br>~~dG~~<br>~~DO~~|33<br>~~dG~~<br>~~DO~~|33<br>~~dG~~<br>~~DO~~|37<br>~~dG~~<br>~~DO~~|33<br>~~dG~~<br>~~DO~~|37<br>~~dG~~<br>~~DO~~|
|**Number 7:1 or 8:1 Gearboxes**<br>~~DO~~<br>~~Re~~|||||||
|Number of 7:1 or 8:1 Output Gearbox Available<br>(Bank 0)<br>~~Re~~|5<br>~~Re~~|7<br>~~Re~~|14<br>~~Re~~|18<br>~~Re~~|14<br>~~Re~~|18<br>~~Re~~|
|Number of 7:1 or 8:1 Input Gearbox Available<br>(Bank 2)|6|13|14|18|14|18|
|**High-speed Differential Outputs**<br>~~Rn~~|||||||
|Bank 0<br>~~Rn~~<br>~~DGC~~|5<br>~~Rn~~<br>~~DGC~~|7<br>~~Rn~~<br>~~DGC~~|14<br>~~Rn~~<br>~~DGC~~|18<br>~~Rn~~<br>~~DGC~~|14<br>~~Rn~~<br>~~DGC~~|18<br>~~Rn~~<br>~~DGC~~|
|**VCCIO Pins**<br>~~Re~~<br>~~GO~~|||||||
|Bank 0<br>~~Re~~<br>~~GO~~|2<br>~~Re~~<br>~~GO~~|1<br>~~Re~~<br>~~GO~~|4<br>~~Re~~<br>~~GO~~<br>~~GO~~|4<br>~~Re~~<br>~~GO~~<br>~~GO~~|4<br>~~Re~~<br>~~GO~~|4<br>~~Re~~<br>~~GO~~|
|Bank 1<br>~~GO~~<br>~~dG~~|0<br>~~GO~~<br>~~dG~~|1<br>~~GO~~<br>~~dG~~|3<br>~~GO~~<br>~~GO~~<br>~~dG~~|4<br>~~GO~~<br>~~GO~~<br>~~dG~~|4<br>~~GO~~<br>~~dG~~|4<br>~~GO~~<br>~~dG~~|
|Bank 2<br>~~dG~~<br>~~dG~~<br>~~Ge~~|1<br>~~dG~~<br>~~dG~~<br>~~Ge~~|1<br>~~dG~~<br>~~dG~~|4<br>~~dG~~<br>~~dG~~|4<br>~~dG~~<br>~~dG~~<br>~~DO~~|4<br>~~dG~~<br>~~dG~~<br>~~DO~~|4<br>~~dG~~<br>~~dG~~|
|Bank 3<br>~~dG~~<br>~~GG~~<br>~~Ge~~|0<br>~~dG~~<br>~~GG~~<br>~~Ge~~|1<br>~~dG~~<br>~~GG~~|2<br>~~dG~~<br>~~GG~~|2<br>~~dG~~<br>~~GG~~<br>~~DO~~|1<br>~~dG~~<br>~~GG~~<br>~~DO~~|2<br>~~dG~~<br>~~GG~~|
|Bank 4<br>~~GG~~<br>~~Ge~~|0<br>~~GG~~<br>~~Ge~~|1<br>~~GG~~<br>~~GG~~|2<br>~~GG~~<br>~~GG~~|2<br>~~GG~~<br>~~DO~~<br>~~GG~~<br>~~GO~~|2<br>~~GG~~<br>~~DO~~|2<br>~~GG~~|
|Bank 5<br>~~GG~~|1<br>~~GG~~|1<br>~~GG~~|2<br>~~GG~~|2<br>~~GG~~<br>~~GO~~|1<br>~~GG~~|2<br>~~GG~~|
|**VCC**<br>~~dG~~|2<br>~~dG~~|4<br>~~dG~~|8<br>~~dG~~|8<br>~~GO~~<br>~~dG~~|8<br>~~dG~~|10<br>~~dG~~|
|**GND**<br>~~dG~~<br>~~dG~~|4<br>~~dG~~<br>~~dG~~|10<br>~~dG~~<br>~~dG~~|24<br>~~dG~~<br>~~dG~~|16<br>~~dG~~<br>~~dG~~|24<br>~~dG~~<br>~~dG~~|16<br>~~dG~~<br>~~dG~~|
|**NC**<br>~~dG~~<br>~~dG~~|0<br>~~dG~~<br>~~dG~~|0<br>~~dG~~<br>~~dG~~|0<br>~~dG~~<br>~~dG~~|13<br>~~dG~~<br>~~dG~~<br>~~DO~~|1<br>~~dG~~<br>~~dG~~<br>~~DO~~|0<br>~~dG~~<br>~~dG~~|
|**Total Count of Bonded Pins**<br>~~dG~~<br>~~DD~~|**49**<br>~~dG~~<br>~~DD~~|**121**<br>~~dG~~<br>~~DD~~|**256**<br>~~dG~~<br>~~DD~~|**324**<br>~~dG~~<br>~~DD~~<br>~~DO~~|**256**<br>~~dG~~<br>~~DD~~<br>~~DO~~|**324**<br>~~dG~~<br>~~DD~~|



***Note:** One pin for JTAGENB or four pins for JTAG. 

© 2014-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02032-2.8 

77 

**MachXO3 Family Data Sheet** 

**Table 4.4. MachXO3L/LF-4300 Pin Summary** 

|~~re~~|**MachXO3L/LF-4300**<br>~~pT~~<br>~~receeeeeeeeeeee~~|**MachXO3L/LF-4300**<br>~~pT~~<br>~~receeeeeeeeeeee~~|**MachXO3L/LF-4300**<br>~~pT~~<br>~~receeeeeeeeeeee~~|**MachXO3L/LF-4300**<br>~~pT~~<br>~~receeeeeeeeeeee~~|**MachXO3L/LF-4300**<br>~~pT~~<br>~~receeeeeeeeeeee~~|**MachXO3L/LF-4300**<br>~~pT~~<br>~~receeeeeeeeeeee~~|**MachXO3L/LF-4300**<br>~~pT~~<br>~~receeeeeeeeeeee~~|
|---|---|---|---|---|---|---|---|
||**WLCSP81**<br>~~pT~~<br>~~re~~|**CSFBGA121**<br>~~pT~~<br>~~cee~~|**CSFBGA256**<br>~~pT~~<br>~~eee~~|**CSFBGA324**<br>~~pT~~<br>~~eee~~|**CABGA256**<br>~~pT~~<br>~~ee~~|**CABGA324**<br>~~pT~~<br>~~ee~~|**CABGA400**<br>~~pT~~|
|**General Purpose I/Oper Bank**<br>~~re cee eee eee ee ee~~<br>~~En~~||||||||
|Bank 0<br>~~ed~~|30<br>~~ed~~|25<br>~~ed~~|51<br>~~ed~~|72<br>~~ed~~|51<br>~~ed~~|72<br>~~ed~~|84<br>~~ed~~|
|Bank 1<br>~~ed~~<br>~~en~~|0<br>~~ed~~<br>~~en~~|26<br>~~ed~~<br>~~en~~|52<br>~~ed~~<br>~~en~~|62<br>~~ed~~<br>~~en~~|52<br>~~ed~~<br>~~en~~|68<br>~~ed~~<br>~~en~~|84<br>~~ed~~<br>~~en~~|
|Bank 2<br>~~en~~<br>~~ed~~|20<br>~~en~~<br>~~ed~~|26<br>~~en~~<br>~~ed~~|52<br>~~en~~<br>~~ed~~|72<br>~~en~~<br>~~ed~~|52<br>~~en~~<br>~~ed~~|72<br>~~en~~<br>~~ed~~|84<br>~~en~~<br>~~ed~~|
|Bank 3<br>~~ed~~<br>~~ed~~|7<br>~~ed~~<br>~~ed~~|7<br>~~ed~~<br>~~eG~~|16<br>~~ed~~<br>~~eG~~|22<br>~~ed~~<br>~~eG~~|16<br>~~ed~~|24<br>~~ed~~|28<br>~~ed~~|
|Bank 4<br>~~ed~~<br>~~ed~~<br>~~a~~|0<br>~~ed ~~<br>~~ed~~|7<br> ~~eG~~|16<br>~~eG~~<br>~~GG~~|14<br>~~eG~~<br>~~GG~~|16<br>~~GG~~<br>~~GO~~|16|24|
|Bank 5<br>~~ed~~<br>~~eG~~<br>~~a~~|7<br>~~ed~~<br>~~eG~~|10<br>~~eG~~|20<br>~~GG~~<br>~~eG~~|27<br>~~GG~~<br>~~eG~~|20<br>~~GG~~<br>~~eG~~<br>~~GO~~|28<br>~~eG~~|32<br>~~eG~~|
|**Total General Purpose**<br>**Single Ended I/O**<br>~~a~~|64|101|207|269|207<br>~~GO~~|280|336|
|**Minimum Reserved for**<br>**Configuration***<br>~~a~~|1|1|1|1<br>~~ee~~|1|1|1|
|**Maximum Programmable Single**<br>**Ended I/O **<br>~~a~~|63<br>~~ee~~|100<br>~~ee~~|206<br>~~ee~~|268<br>~~ee~~<br>~~ee~~|206<br>~~ee~~|279<br>~~ee~~|335<br>~~ee~~|
|**Differential I/O per Bank**<br>~~aee~~<br>~~ee~~<br>~~pn~~||||||||
|Bank 0<br>~~GO~~|15<br>~~GO~~|12<br>~~GO~~|25<br>~~GO~~|36<br>~~GO~~|25<br>~~GO~~|36<br>~~GO~~|42<br>~~GO~~|
|Bank 1<br>~~GO~~<br>~~en~~|0<br>~~GO~~<br>~~en~~|13<br>~~GO~~<br>~~en~~|26<br>~~GO~~<br>~~en~~|30<br>~~GO~~<br>~~en~~|26<br>~~GO~~<br>~~en~~|34<br>~~GO~~<br>~~en~~|42<br>~~GO~~<br>~~en~~|
|Bank 2<br>~~en~~<br>~~ed~~|10<br>~~en~~<br>~~ed~~|13<br>~~en~~<br>~~ed~~|26<br>~~en~~<br>~~ed~~|36<br>~~en~~<br>~~ed~~|26<br>~~en~~<br>~~ed~~|36<br>~~en~~<br>~~ed~~|42<br>~~en~~<br>~~ed~~|
|Bank 3<br>~~ed~~<br>~~ed~~|3<br>~~ed~~<br>~~ed~~|3<br>~~ed~~<br>~~eG~~|8<br>~~ed~~<br>~~eG~~|10<br>~~ed~~<br>~~eG~~|8<br>~~ed~~|12<br>~~ed~~|14<br>~~ed~~|
|Bank 4<br>~~ed~~<br>~~ed~~<br>~~a~~|0<br>~~ed ~~<br>~~ed~~|3<br> ~~eG~~|8<br>~~eG~~<br>~~GG~~|6<br>~~eG~~<br>~~GG~~|8<br>~~GG~~<br>~~GO~~|8|12|
|Bank 5<br>~~ed~~<br>~~eG~~<br>~~a~~|3<br>~~ed~~<br>~~eG~~|5<br>~~eG~~|10<br>~~GG~~<br>~~eG~~|13<br>~~GG~~<br>~~eG~~|10<br>~~GG~~<br>~~eG~~<br>~~GO~~|14<br>~~eG~~|16<br>~~eG~~|
|**Total General Purpose**<br>**Differential I/O**<br>~~a~~|31|49|103|131|103<br>~~GO~~<br>~~GO~~|140<br>~~GO~~|168|
|**Dual Function I/O**<br>~~eG~~|25<br>~~eG~~|37<br>~~eG~~|37<br>~~eG~~|37<br>~~eG~~|37<br>~~eG~~<br>~~GO~~|37<br>~~eG~~<br>~~GO~~|37<br>~~eG~~|
|**Number 7:1 or 8:1 Gearboxes**<br>~~eG~~<br>~~GO~~<br>~~PR~~||||||||
|Number of 7:1 or 8:1 Output<br>Gearboxes Available(Bank 0)<br>~~PR~~<br>~~a~~<br>~~PR~~|10<br>~~PR~~<br>~~a~~|7<br>~~PR~~|18<br>~~PR~~<br>~~ee~~|18<br>~~PR~~<br>~~ee~~|18<br>~~PR~~<br>~~ee~~|18<br>~~PR~~<br>~~ee~~|21<br>~~PR~~<br>~~ee~~|
|Number of 7:1 or 8:1 Input<br>Gearboxes Available(Bank 2)<br>~~a~~<br>~~ee~~<br>~~PR~~|10<br>~~ee~~<br>~~a~~|13<br>~~ee~~|18<br>~~ee~~<br>~~ee~~|18<br>~~ee~~<br>~~ee~~|18<br>~~ee~~<br>~~ee~~|18<br>~~ee~~<br>~~ee~~|21<br>~~ee~~<br>~~ee~~|
|**High-speed Differential Outputs**<br>~~ee~~<br>~~a~~<br>~~eeee~~<br>~~PR~~||||||||
|Bank 0<br>~~PR~~<br>~~en~~|10<br>~~a~~<br>~~en~~|7|18<br>~~ee~~<br>~~DO~~|18<br>~~ee~~<br>~~DO~~|18<br>~~ee~~<br>~~DO~~|18<br>~~ee ~~|21<br> ~~ee~~|
|**VCCIO Pins**<br>~~en~~<br>~~DO~~<br>~~Pn~~||||||||
|Bank 0<br>~~Pn~~<br>~~GO~~<br>~~ee~~|3<br>~~Pn~~<br>~~GO~~|1<br>~~Pn~~<br>~~GO~~<br>~~GO~~|4<br>~~Pn~~<br>~~GO~~<br>~~GO~~|4<br>~~Pn~~<br>~~GO~~<br>~~GO~~|4<br>~~Pn~~<br>~~GO~~<br>~~GO~~|4<br>~~Pn~~<br>~~GO~~|5<br>~~Pn~~<br>~~GO~~|
|Bank 1<br>~~GO~~<br>~~ee~~|0<br>~~GO~~|1<br>~~GO~~<br>~~GO~~|3<br>~~GO~~<br>~~GO~~|4<br>~~GO~~<br>~~GO~~|4<br>~~GO~~<br>~~GO~~|4<br>~~GO~~|5<br>~~GO~~|
|Bank 2<br>~~ee~~<br>~~GG~~|2<br>~~GG~~|1<br>~~GO~~<br>~~GG~~|4<br>~~GO~~<br>~~GG~~|4<br>~~GO~~<br>~~GG~~|4<br>~~GO~~<br>~~GG~~|4<br>~~GG~~|5<br>~~GG~~|
|Bank 3<br>~~es~~|1<br>~~es~~|1<br>~~es~~|2<br>~~es~~|2<br>~~es~~|1<br>~~es~~|2<br>~~es~~|2<br>~~es~~|
|Bank 4<br>~~es~~<br>~~en~~<br>~~**e**e~~|0<br>~~es~~<br>~~en~~|1<br>~~es~~<br>~~en~~<br>~~eG~~|2<br>~~es~~<br>~~en~~<br>~~eG~~|2<br>~~es~~<br>~~en~~<br>~~eG~~|2<br>~~es~~<br>~~en~~|2<br>~~es~~<br>~~en~~|2<br>~~es~~<br>~~en~~|
|Bank 5<br>~~en~~<br>~~ed~~<br>~~**e**e~~|1<br>~~en~~<br>~~ed~~|1<br>~~en~~<br>~~ed~~<br>~~eG~~|2<br>~~en~~<br>~~ed~~<br>~~eG~~|2<br>~~en~~<br>~~ed~~<br>~~eG~~|1<br>~~en~~<br>~~ed~~|2<br>~~en~~<br>~~ed~~|2<br>~~en~~<br>~~ed~~|
|**VCC**<br>~~ed~~<br>~~**e**e~~|4<br>~~ed~~|4<br>~~ed~~<br>~~eG~~|8<br>~~ed~~<br>~~eG~~<br>~~GO~~|8<br>~~ed~~<br>~~eG~~<br>~~GO~~|8<br>~~ed~~<br>~~GO~~|10<br>~~ed~~|10<br>~~ed~~|
|**GND**<br>~~**e**e~~<br>~~ee~~|6|10<br>~~eG~~<br>~~GO~~|24<br>~~eG~~<br>~~GO~~<br>~~G~~<br>~~GO~~|16<br>~~eG~~<br>~~GO~~<br>~~G~~<br>~~GO~~|24<br>~~GO~~<br>~~G~~<br>~~GO~~|16<br>~~G~~|33<br>~~G~~|
|**NC**<br>~~ee~~|0|0<br>~~GO~~|0<br>~~G~~<br>~~GO~~|13<br>~~G~~<br>~~GO~~|1<br>~~G~~<br>~~GO~~|0<br>~~G~~|0<br>~~G~~|
|**Total Count of Bonded Pins**<br>~~ee~~<br>~~DO~~|**81**<br>~~DO~~|**121**<br>~~GO~~<br>~~DO~~|**256**<br>~~GO~~<br>~~DO~~|**324**<br>~~GO~~<br>~~DO~~|**256**<br>~~GO~~<br>~~DO~~|**324**<br>~~DO~~|**400**<br>~~DO~~|



***Note:** One pin for JTAGENB or four pins for JTAG. 

© 2014-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

78 

FPGA-DS-02032-2.8 

**MachXO3 Family Data Sheet** 

**Table 4.5. MachXO3L/LF-6900 Pin Summary** 

|~~a~~|**MachXO3L/LF-6900**<br>~~reseeeeee~~|**MachXO3L/LF-6900**<br>~~reseeeeee~~|**MachXO3L/LF-6900**<br>~~reseeeeee~~|**MachXO3L/LF-6900**<br>~~reseeeeee~~|**MachXO3L/LF-6900**<br>~~reseeeeee~~|
|---|---|---|---|---|---|
||**CSFBGA256**<br>~~res~~|**CSFBGA324**<br>~~res~~|**CABGA256**<br>~~eee~~|**CABGA324**<br>~~eee~~|**CABGA400**<br>~~eee~~|
|**General Purpose I/Oper Bank**<br>~~a~~<br>~~res eee eee~~<br>~~ER~~||||||
|Bank 0<br>~~a~~|51|74|51|72|84|
|Bank 1<br>~~a~~<br>~~DG~~|52<br>~~DG~~|68<br>~~DG~~|52<br>~~DG~~|68<br>~~DG~~|84<br>~~DG~~|
|Bank 2<br>~~DG~~<br>~~ee~~|52<br>~~DG~~<br>~~ee~~|72<br>~~DG~~<br>~~ee~~|52<br>~~DG~~<br>~~ee~~|72<br>~~DG~~<br>~~ee~~|84<br>~~DG~~<br>~~ee~~|
|Bank 3<br>~~ee~~<br>~~ee~~|16<br>~~ee~~<br>~~ee~~|24<br>~~ee~~<br>~~ee~~|16<br>~~ee~~<br>~~ee~~|24<br>~~ee~~<br>~~ee~~|28<br>~~ee~~<br>~~ee~~|
|Bank 4<br>~~ee~~<br>~~ee~~|16<br>~~ee~~<br>~~ee~~|16<br>~~ee~~<br>~~ee~~|16<br>~~ee~~<br>~~ee~~|16<br>~~ee~~<br>~~ee~~|24<br>~~ee~~<br>~~ee~~|
|Bank 5<br>~~ee~~<br>~~a~~|20<br>~~ee~~<br>~~a~~|28<br>~~ee~~<br>~~a~~|20<br>~~ee~~<br>~~a~~|28<br>~~ee~~<br>~~a~~|32<br>~~ee~~<br>~~a~~|
|**Total General Purpose Single Ended I/O **<br>~~a~~|207<br>~~a~~|282<br>~~a~~|207<br>~~a~~|280<br>~~a~~|336<br>~~a~~|
|**Minimum Reserved for Configuration***<br>~~a~~<br>~~a~~|1<br>~~a~~<br>|1<br>~~a~~<br>|1<br>~~a~~<br>|1<br>~~a~~<br>|1<br>~~a~~<br>|
|**Maximum Programmable Single Ended I/O **<br>~~a~~<br>~~a~~|206<br>~~a~~<br>|281<br>~~a~~<br>|206<br>~~a~~<br>|279<br>~~a~~<br>|335<br>~~a~~<br>|
|**Differential I/O per Bank**<br>~~aRn~~||||||
|Bank 0<br>~~Rn~~<br>~~ee~~|25<br>~~Rn~~<br>~~ee~~|36<br>~~Rn~~<br>~~ee~~|25<br>~~Rn~~<br>~~ee~~|36<br>~~Rn~~<br>~~ee~~|42<br>~~Rn~~<br>~~ee~~|
|Bank 1<br>~~ee~~<br>~~ee~~|26<br>~~ee~~<br>~~ee~~|34<br>~~ee~~<br>~~ee~~|26<br>~~ee~~<br>~~ee~~|34<br>~~ee~~<br>~~ee~~|42<br>~~ee~~<br>~~ee~~|
|Bank 2<br>~~ee~~<br>~~a~~|26<br>~~ee~~<br>~~a~~|36<br>~~ee~~<br>~~a~~|26<br>~~ee~~<br>~~a~~|36<br>~~ee~~<br>~~a~~|42<br>~~ee~~<br>~~a~~|
|Bank 3<br>~~a~~|8<br>~~a~~|12<br>~~a~~|8<br>~~a~~|12<br>~~a~~|14<br>~~a~~|
|Bank 4<br>~~a~~|8<br>~~a~~|8<br>~~a~~|8<br>~~a~~|8<br>~~a~~|12<br>~~a~~|
|Bank 5<br>~~a~~<br>~~ee~~|10<br>~~a~~<br>~~ee~~|14<br>~~a~~<br>~~ee~~|10<br>~~a~~<br>~~ee~~|14<br>~~a~~<br>~~ee~~|16<br>~~a~~<br>~~ee~~|
|**Total General Purpose Differential I/O **<br>~~ee~~<br>~~ee~~|103<br>~~ee~~<br>~~ee~~|140<br>~~ee~~<br>~~ee~~|103<br>~~ee~~<br>~~ee~~|140<br>~~ee~~<br>~~ee~~|168<br>~~ee~~<br>~~ee~~|
|**Dual Function I/O**<br>~~ee~~<br>~~ee~~|37<br>~~ee~~<br>~~ee~~|37<br>~~ee~~<br>~~ee~~|37<br>~~ee~~<br>~~ee~~|37<br>~~ee~~<br>~~ee~~|37<br>~~ee~~<br>~~ee~~|
|**Number 7:1 or 8:1 Gearboxes**<br>~~ee~~<br>~~|~~||||||
|Number of 7:1 or 8:1 Output Gearbox Available(Bank 0)<br>~~|~~<br>~~a~~|20<br>~~|~~<br>~~a~~|21<br>~~|~~<br>~~a~~|20<br>~~|~~<br>~~a~~|21<br>~~|~~<br>~~a~~|21<br>~~|~~<br>~~a~~|
|Number of 7:1 or 8:1 Input Gearbox Available(Bank 2)<br>~~es~~|20<br>~~es~~|21<br>~~es~~|20<br>~~es~~|21<br>~~es~~|21<br>~~es~~|
|**High-speed Differential Outputs**<br>~~es~~<br>~~Rn~~||||||
|Bank 0<br>~~Rn~~<br>~~ee~~|20<br>~~Rn~~<br>~~ee~~|21<br>~~Rn~~<br>~~ee~~|20<br>~~Rn~~<br>~~ee~~|21<br>~~Rn~~<br>~~ee~~|21<br>~~Rn~~<br>~~ee~~|
|**VCCIO Pins**<br>~~ee~~<br>~~Rn~~||||||
|Bank 0<br>~~Rn~~<br>~~a~~|4<br>~~Rn~~<br>~~a~~|4<br>~~Rn~~<br>~~a~~|4<br>~~Rn~~<br>~~a~~|4<br>~~Rn~~<br>~~a~~|5<br>~~Rn~~<br>~~a~~|
|Bank 1<br>~~a~~<br>~~a~~|3<br>~~a~~<br>~~a~~|4<br>~~a~~<br>~~a~~|4<br>~~a~~<br>~~a~~|4<br>~~a~~<br>~~a~~|5<br>~~a~~<br>~~a~~|
|Bank 2<br>~~a~~|4<br>~~a~~|4<br>~~a~~|4<br>~~a~~|4<br>~~a~~|5<br>~~a~~|
|Bank 3<br>~~eG~~|2<br>~~eG~~|2<br>~~eG~~|1<br>~~eG~~|2<br>~~eG~~|2<br>~~eG~~|
|Bank 4<br>~~eG~~<br>~~es~~|2<br>~~eG~~<br>~~es~~|2<br>~~eG~~<br>~~es~~|2<br>~~eG~~<br>~~es~~|2<br>~~eG~~<br>~~es~~|2<br>~~eG~~<br>~~es~~|
|Bank 5<br>~~es~~<br>~~ee~~|2<br>~~es~~<br>~~ee~~|2<br>~~es~~<br>~~ee~~|1<br>~~es~~<br>~~ee~~|2<br>~~es~~<br>~~ee~~|2<br>~~es~~<br>~~ee~~|
|**VCC**<br>~~ee~~<br>~~ee~~|8<br>~~ee~~<br>~~ee~~|8<br>~~ee~~<br>~~ee~~|8<br>~~ee~~<br>~~ee~~|10<br>~~ee~~<br>~~ee~~|10<br>~~ee~~<br>~~ee~~|
|**GND**<br>~~ee~~<br>~~ee~~|24<br>~~ee~~<br>~~ee~~|16<br>~~ee~~<br>~~ee~~|24<br>~~ee~~<br>~~ee~~|16<br>~~ee~~<br>~~ee~~|33<br>~~ee~~<br>~~ee~~|
|**NC**<br>~~ee~~<br>~~a~~|0<br>~~ee~~<br>~~a~~|0<br>~~ee~~<br>~~a~~|1<br>~~ee~~<br>~~a~~|0<br>~~ee~~<br>~~a~~|0<br>~~ee~~<br>~~a~~|
|**Total Count of Bonded Pins**<br>~~DG~~|**256**<br>~~DG~~|**324**<br>~~DG~~|**256**<br>~~DG~~|**324**<br>~~DG~~|**400**<br>~~DG~~|



© 2014-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02032-2.8 

79 

**MachXO3 Family Data Sheet** 

**Table 4.6. MachXO3L/LF-9400C Pin Summary** 

|~~ee~~|**MachXO3L/LF-9400C**<br>~~PO~~<br>~~ee~~<br>~~eeeeeee~~|**MachXO3L/LF-9400C**<br>~~PO~~<br>~~ee~~<br>~~eeeeeee~~|**MachXO3L/LF-9400C**<br>~~PO~~<br>~~ee~~<br>~~eeeeeee~~|**MachXO3L/LF-9400C**<br>~~PO~~<br>~~ee~~<br>~~eeeeeee~~|
|---|---|---|---|---|
||**CSFBGA256**<br>~~PO~~<br>~~ee~~<br>~~ee~~|**CABGA256**<br>~~PO~~<br>~~ee~~<br>~~ee~~|**CABGA400**<br>~~PO~~<br>~~ee~~<br>~~eee~~|**CABGA484**<br>~~PO~~<br>~~ee~~<br>~~eee~~|
|**General Purpose I/Oper Bank**<br>~~ee~~<br>~~ee ee eee~~<br>~~Pe~~|||||
|Bank 0<br>~~OO~~|51<br>~~OO~~|51<br>~~OO~~|84<br>~~OO~~|96<br>~~OO~~|
|Bank 1<br>~~OO~~<br>~~a~~<br>~~a~~|52<br>~~OO~~<br>~~a~~|52<br>~~OO~~<br>~~a~~|84<br>~~OO~~<br>~~a~~|96<br>~~OO~~<br>~~a~~|
|Bank 2<br>~~a~~<br>~~a~~<br>~~**a**~~|52<br>~~a~~<br>|52<br>~~a~~<br>|84<br>~~a~~<br>|96<br>~~a~~<br>|
|Bank 3<br>~~a~~<br>~~**a**~~|16<br>|16<br>|28<br>|36<br>|
|Bank 4<br>~~**a**~~|16<br>|16<br>|24<br>|24<br>|
|Bank 5<br>~~GG~~|20<br>~~GG~~|20<br>~~GG~~|32<br>~~GG~~|36<br>~~GG~~|
|**Total General Purpose Single Ended I/O **<br>~~a~~|207<br>~~a~~|207<br>~~a~~|336<br>~~a~~|384<br>~~a~~|
|**Minimum Reserved for Configuration***<br>~~a~~|1<br>~~a~~|1<br>~~a~~|1<br>~~a~~|1<br>~~a~~|
|**Maximum Programmable Single Ended I/O **<br>~~a~~<br>~~DO~~|206<br>~~a~~<br>~~DO~~|206<br>~~a~~<br>~~DO~~|335<br>~~a~~<br>~~DO~~|383<br>~~a~~<br>~~DO~~|
|**Differential I/O per Bank**<br>~~DO~~<br>~~|~~|||||
|Bank 0<br>~~|~~<br>~~a~~|25<br>~~|~~<br>~~a~~|25<br>~~|~~<br>~~a~~|42<br>~~|~~<br>~~a~~|48<br>~~|~~<br>~~a~~|
|Bank 1<br>~~a~~<br>~~a~~|26<br>~~a~~<br>~~a~~|26<br>~~a~~<br>~~a~~|42<br>~~a~~<br>~~a~~|48<br>~~a~~<br>~~a~~|
|Bank 2<br>~~a~~<br>~~GG~~|26<br>~~a~~<br>~~GG~~|26<br>~~a~~<br>~~GG~~|42<br>~~a~~<br>~~GG~~|48<br>~~a~~<br>~~GG~~|
|Bank 3<br>~~a~~|8<br>~~a~~|8<br>~~a~~|14<br>~~a~~|18<br>~~a~~|
|Bank 4<br>~~a~~<br>~~a~~|8<br>~~a~~|8<br>~~a~~|12<br>~~a~~|12<br>~~a~~|
|Bank 5<br>~~a~~<br>~~a~~<br>~~a~~|10<br>~~a~~<br>|10<br>~~a~~<br>|16<br>~~a~~<br>|18<br>~~a~~<br>|
|**Total General Purpose Differential I/O **<br>~~a~~<br>~~a~~|103<br>|103<br>|168<br>|192<br>|
|**Dual Function I/O**<br>~~aDe~~|37<br>~~De~~|37<br>~~De~~|37<br>~~De~~|45<br>~~De~~|
|**Number 7:1 or 8:1 Gearboxes**<br>~~De~~<br>~~PR~~|||||
|Number of 7:1 or 8:1 Output Gearbox Available(Bank 0)<br>~~PR~~<br>~~GG~~|20<br>~~PR~~<br>~~GG~~|20<br>~~PR~~<br>~~GG~~|22<br>~~PR~~<br>~~GG~~|24<br>~~PR~~<br>~~GG~~|
|Number of 7:1 or 8:1 Input Gearbox Available(Bank 2)<br>~~Pp~~|20<br>~~Pp~~|20<br>~~Pp~~|22<br>~~Pp~~|24<br>~~Pp~~|
|**High-speed Differential Outputs**<br>~~Pp~~<br>~~PR~~|||||
|Bank 0<br>~~PR~~<br>~~a~~|20<br>~~PR~~<br>~~a~~|20<br>~~PR~~<br>~~a~~|21<br>~~PR~~<br>~~a~~|24<br>~~PR~~<br>~~a~~|
|**VCCIO Pins**<br>~~a~~<br>~~Rn~~|||||
|Bank 0<br>~~Rn~~<br>~~Ge~~|4<br>~~Rn~~<br>~~Ge~~|4<br>~~Rn~~<br>~~Ge~~|5<br>~~Rn~~<br>~~Ge~~|9<br>~~Rn~~<br>~~Ge~~|
|Bank 1<br>~~Ge~~<br>~~GC~~|3<br>~~Ge~~<br>~~GC~~|4<br>~~Ge~~<br>~~GC~~|5<br>~~Ge~~<br>~~GC~~|9<br>~~Ge~~<br>~~GC~~|
|Bank 2<br>~~GG~~|4<br>~~GG~~|4<br>~~GG~~|5<br>~~GG~~|9<br>~~GG~~|
|Bank 3<br>~~a~~|2<br>~~a~~|1<br>~~a~~|2<br>~~a~~|3<br>~~a~~|
|Bank 4<br>~~a~~<br>~~eG~~|2<br>~~a~~<br>~~eG~~|2<br>~~a~~<br>~~eG~~|2<br>~~a~~<br>~~eG~~|3<br>~~a~~<br>~~eG~~|
|Bank 5<br>~~eG~~<br>~~a~~|2<br>~~eG~~<br>~~a~~|1<br>~~eG~~<br>~~a~~|2<br>~~eG~~<br>~~a~~|3<br>~~eG~~<br>~~a~~|
|**VCC**<br>~~a~~<br>~~a~~|8<br>~~a~~<br>~~a~~|8<br>~~a~~<br>~~a~~|10<br>~~a~~<br>~~a~~|12<br>~~a~~<br>~~a~~|
|**GND**<br>~~a~~<br>~~a~~|24<br>~~a~~<br>~~a~~|24<br>~~a~~<br>~~a~~|33<br>~~a~~<br>~~a~~|52<br>~~a~~<br>~~a~~|
|**NC**<br>~~a~~<br>~~GC~~|0<br>~~a~~<br>~~GC~~|1<br>~~a~~<br>~~GC~~|0<br>~~a~~<br>~~GC~~|0<br>~~a~~<br>~~GC~~|
|**Total Count of Bonded Pins**<br>~~I~~|**256**<br>~~I~~|**256**<br>~~I~~|**400**<br>~~I~~|**484**<br>~~I~~|



© 2014-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

80 

FPGA-DS-02032-2.8 

**MachXO3 Family Data Sheet** 

## **5. MachXO3 Part Number Description** 

© 2014-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02032-2.8 

81 

**MachXO3 Family Data Sheet** 

## **6. Ordering Information** 

LCMXO3L/LF devices have top-side markings as shown in the examples below for the 256-Ball caBGA package with MachXO3-6900 device in Commercial Temperature in Speed Grade 5. Notice that for the MachXO3LF device, _LMXO3LF_ is used instead of _LCMXO3LF_ as in the Part Number. 

**Note:** Markings are abbreviated for small packages. MachXO3L WLSC packages (UWG) are dual speed grade marked _5C-5I_ 

**==> picture [81 x 7] intentionally omitted <==**

**----- Start of picture text -----**<br>
Marked with LMXO3LF<br>**----- End of picture text -----**<br>


LAMXO3LF devices have top-side markings as shown in the examples below: 

Markings for the 324-ball caBGA package with LAMXO3LF-4300C device in Automotive Temperature in Speed Grade 5 

## **6.1. MachXO3L Ultra Low Power Commercial and Industrial Grade Devices, Halogen Free (RoHS) Packaging** 

|**Part Number**<br>~~I~~<br>~~ee~~|**LUTs**<br>~~I~~<br>~~ee~~|**Supply Voltage **<br>~~I~~<br>~~(~~<br>~~GOD~~|**Speed**<br>~~I~~<br>~~(~~<br>~~GOD~~|**Package **<br>~~I~~<br>~~(~~<br>~~GOD~~|**Leads**<br>~~I~~<br>~~I~~|**Temp. **<br>~~I~~|
|---|---|---|---|---|---|---|
|LCMXO3L-1300E-5UWG36CTR<br>~~ee~~|1300<br>~~ee~~|1.2 V<br>~~(~~<br>~~GOD~~|5<br>~~(~~<br>~~GOD~~|Halogen-Free WLCSP<br>~~(~~<br>~~GOD~~|36<br>~~I~~|COM|
|LCMXO3L-1300E-5UWG36CTR50<br>~~es~~|1300<br>~~es~~|1.2 V<br>~~GOD~~<br>~~es~~|5<br>~~GOD~~<br>~~es~~|Halogen-Free WLCSP<br>~~GOD ~~<br>~~es~~|36<br> ~~I~~<br>~~es~~|COM<br>~~es~~|
|LCMXO3L-1300E-5UWG36CTR1K<br>~~es~~<br>~~eG~~|1300<br>~~es~~<br>~~eG~~|1.2 V<br>~~es~~<br>~~eG~~|5<br>~~es~~<br>~~eG~~|Halogen-Free WLCSP<br>~~es~~<br>~~eG~~|36<br>~~es~~<br>~~eG~~|COM<br>~~es~~<br>~~eG~~|
|LCMXO3L-1300E-5UWG36ITR<br>~~eG~~<br>~~GG~~|1300<br>~~eG~~<br>~~GG~~|1.2 V<br>~~eG~~<br>~~GG~~|5<br>~~eG~~<br>~~GG~~|Halogen-Free WLCSP<br>~~eG~~<br>~~GG~~|36<br>~~eG~~<br>~~GG~~|IND<br>~~eG~~<br>~~GG~~|
|LCMXO3L-1300E-5UWG36ITR50<br>~~eG~~<br>~~eG~~|1300<br>~~eG~~<br>~~eG~~|1.2 V<br>~~eG~~<br>~~eG~~|5<br>~~eG~~<br>~~Gs~~|Halogen-Free WLCSP<br>~~eG~~<br>~~Gs~~|36<br>~~eG~~|IND<br>~~eG~~|
|LCMXO3L-1300E-5UWG36ITR1K<br>~~eG~~|1300<br>~~eG~~|1.2 V<br>~~eG~~|5<br>~~Gs~~|Halogen-Free WLCSP<br>~~Gs~~|36|IND|
|LCMXO3L-1300E-5MG121C<br>~~eG~~<br>~~es~~|1300<br>~~eG~~<br>~~es~~|1.2 V<br>~~eG~~<br>~~es~~|5<br>~~Gs~~<br>~~es~~|Halogen-Free csfBGA<br>~~Gs~~<br>~~es~~|121<br>~~es~~|COM<br>~~es~~|
|LCMXO3L-1300E-6MG121C<br>~~es~~<br>~~eG~~|1300<br>~~es~~<br>~~eG~~|1.2 V<br>~~es~~<br>~~eG~~|6<br>~~es~~<br>~~eG~~|Halogen-Free csfBGA<br>~~es~~<br>~~eG~~|121<br>~~es~~<br>~~eG~~|COM<br>~~es~~<br>~~eG~~|
|LCMXO3L-1300E-5MG121I<br>~~eG~~<br>~~ns~~|1300<br>~~eG~~<br>~~ns~~|1.2 V<br>~~eG~~<br>~~ns~~|5<br>~~eG~~<br>~~ns~~|Halogen-Free csfBGA<br>~~eG~~<br>~~ns~~|121<br>~~eG~~<br>~~ns~~|IND<br>~~eG~~<br>~~ns~~|
|LCMXO3L-1300E-6MG121I<br>~~ns~~<br>~~Gs~~|1300<br>~~ns~~<br>~~Gs~~|1.2 V<br>~~ns~~<br>~~Gs~~|6<br>~~ns~~<br>~~Gs~~<br>~~GO~~|Halogen-Free csfBGA<br>~~ns~~<br>~~Gs~~<br>~~GO~~|121<br>~~ns~~<br>~~Gs~~|IND<br>~~ns~~<br>~~Gs~~|
|LCMXO3L-1300E-5MG256C<br>~~eG~~|1300<br>~~eG~~|1.2 V<br>~~eG~~|5<br>~~eG~~<br>~~GO~~|Halogen-Free csfBGA<br>~~eG~~<br>~~GO~~|256<br>~~eG~~|COM<br>~~eG~~|
|LCMXO3L-1300E-6MG256C<br>~~I~~|1300<br>~~I~~|1.2 V<br>~~I~~|6<br>~~GO~~<br>~~I~~|Halogen-Free csfBGA<br>~~GO~~<br>~~I~~|256<br>~~I~~|COM<br>~~I~~|
|LCMXO3L-1300E-5MG256I<br>~~I~~<br>~~eG~~|1300<br>~~I~~<br>~~eG~~|1.2 V<br>~~I~~<br>~~eG~~|5<br>~~I~~<br>~~eG~~|Halogen-Free csfBGA<br>~~I~~<br>~~eG~~|256<br>~~I~~<br>~~eG~~|IND<br>~~I~~<br>~~eG~~|



© 2014-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

82 

FPGA-DS-02032-2.8 

**MachXO3 Family Data Sheet** 

|**Part Number**<br>**LUTs**<br>**Supply Voltage **<br>**Speed**<br>**Package **<br>**Leads**<br>**Temp. **|
|---|
|LCMXO3L-1300E-6MG256I<br>1300<br>1.2 V<br>6<br>Halogen-Free csfBGA<br>256<br>IND|
|LCMXO3L-1300C-5BG256C<br>1300<br>2.5 V/3.3 V<br>5<br>Halogen-Free caBGA<br>256<br>COM|
|LCMXO3L-1300C-6BG256C<br>1300<br>2.5 V/3.3 V<br>6<br>Halogen-Free caBGA<br>256<br>COM|
|LCMXO3L-1300C-5BG256I<br>1300<br>2.5 V/3.3 V<br>5<br>Halogen-Free caBGA<br>256<br>IND|
|LCMXO3L-1300C-6BG256I<br>1300<br>2.5 V/3.3 V<br>6<br>Halogen-Free caBGA<br>256<br>IND|
|**Part Number**<br>**LUTs**<br>**Supply Voltage **<br>**Speed**<br>**Package **<br>**Leads**<br>**Temp. **<br>LCMXO3L-2100E-5UWG49CTR<br>2100<br>1.2 V<br>5<br>Halogen-Free WLCSP<br>49<br>COM<br>LCMXO3L-2100E-5UWG49CTR50<br>2100<br>1.2 V<br>5<br>Halogen-Free WLCSP<br>49<br>COM<br>LCMXO3L-2100E-5UWG49CTR1K<br>2100<br>1.2 V<br>5<br>Halogen-Free WLCSP<br>49<br>COM<br>~~po~~<br>~~GO~~<br>~~eG~~<br>~~GO~~<br>~~eeGG~~|
|LCMXO3L-2100E-5UWG49ITR<br>2100<br>1.2 V<br>5<br>Halogen-Free WLCSP<br>49<br>IND<br>~~GG~~|
|LCMXO3L-2100E-5UWG49ITR50<br>2100<br>1.2 V<br>5<br>Halogen-Free WLCSP<br>49<br>IND<br>~~pO~~|
|LCMXO3L-2100E-5UWG49ITR1K<br>2100<br>1.2 V<br>5<br>Halogen-Free WLCSP<br>49<br>IND<br>LCMXO3L-2100E-5MG121C<br>2100<br>1.2 V<br>5<br>Halogen-Free csfBGA<br>121<br>COM<br>LCMXO3L-2100E-6MG121C<br>2100<br>1.2 V<br>6<br>Halogen-Free csfBGA<br>121<br>COM<br>~~GO~~<br>~~eG~~<br>~~GO~~<br>~~eeGG~~|
|LCMXO3L-2100E-5MG121I<br>2100<br>1.2 V<br>5<br>Halogen-Free csfBGA<br>121<br>IND<br>~~GG~~|
|LCMXO3L-2100E-6MG121I<br>2100<br>1.2 V<br>6<br>Halogen-Free csfBGA<br>121<br>IND<br>~~pO~~|
|LCMXO3L-2100E-5MG256C<br>2100<br>1.2 V<br>5<br>Halogen-Free csfBGA<br>256<br>COM<br>~~GO~~|
|LCMXO3L-2100E-6MG256C<br>2100<br>1.2 V<br>6<br>Halogen-Free csfBGA<br>256<br>COM<br>LCMXO3L-2100E-5MG256I<br>2100<br>1.2 V<br>5<br>Halogen-Free csfBGA<br>256<br>IND<br>LCMXO3L-2100E-6MG256I<br>2100<br>1.2 V<br>6<br>Halogen-Free csfBGA<br>256<br>IND<br>~~CO~~<br>~~eG~~<br>~~**G**O~~<br>~~G~~|
|LCMXO3L-2100E-5MG324C<br>2100<br>1.2 V<br>5<br>Halogen-Free csfBGA<br>324<br>COM<br>~~pO~~|
|LCMXO3L-2100E-6MG324C<br>2100<br>1.2 V<br>6<br>Halogen-Free csfBGA<br>324<br>COM<br>~~GO~~|
|LCMXO3L-2100E-5MG324I<br>2100<br>1.2 V<br>5<br>Halogen-Free csfBGA<br>324<br>IND<br>LCMXO3L-2100E-6MG324I<br>2100<br>1.2 V<br>6<br>Halogen-Free csfBGA<br>324<br>IND<br>LCMXO3L-2100C-5BG256C<br>2100<br>2.5 V/3.3 V<br>5<br>Halogen-Free caBGA<br>256<br>COM<br>LCMXO3L-2100C-6BG256C<br>2100<br>2.5 V/3.3 V<br>6<br>Halogen-Free caBGA<br>256<br>COM<br>LCMXO3L-2100C-5BG256I<br>2100<br>2.5 V/3.3 V<br>5<br>Halogen-Free caBGA<br>256<br>IND<br>LCMXO3L-2100C-6BG256I<br>2100<br>2.5 V/3.3 V<br>6<br>Halogen-Free caBGA<br>256<br>IND<br>~~OO~~<br>~~eG~~<br>~~GO~~<br>~~Se~~<br>~~GG~~<br>~~eG~~<br>~~deGOO~~<br>~~I~~<br>~~ee~~<br>~~GO~~|
|LCMXO3L-2100C-5BG324C<br>2100<br>2.5 V/3.3 V<br>5<br>Halogen-Free caBGA<br>324<br>COM<br>LCMXO3L-2100C-6BG324C<br>2100<br>2.5 V/3.3 V<br>6<br>Halogen-Free caBGA<br>324<br>COM<br>LCMXO3L-2100C-5BG324I<br>2100<br>2.5 V/3.3 V<br>5<br>Halogen-Free caBGA<br>324<br>IND<br>LCMXO3L-2100C-6BG324I<br>2100<br>2.5 V/3.3 V<br>6<br>Halogen-Free caBGA<br>324<br>IND<br>~~GG~~<br>~~Se~~<br>~~GG~~<br>~~ee~~<br>~~GG~~<br>~~eG~~|
|**Part Number**<br>**LUTs**<br>**Supply Voltage **<br>**Speed**<br>**Package **<br>**Leads**<br>**Temp. **<br>~~pO~~|
|LCMXO3L-4300E-5UWG81CTR<br>4300<br>1.2 V<br>5<br>Halogen-Free WLCSP<br>81<br>COM<br>LCMXO3L-4300E-5UWG81CTR50<br>4300<br>1.2 V<br>5<br>Halogen-Free WLCSP<br>81<br>COM<br>LCMXO3L-4300E-5UWG81CTR1K<br>4300<br>1.2 V<br>5<br>Halogen-Free WLCSP<br>81<br>COM<br>~~GG~~<br>~~ee~~<br>~~GG~~<br>~~eG~~|
|LCMXO3L-4300E-5UWG81ITR<br>4300<br>1.2 V<br>5<br>Halogen-Free WLCSP<br>81<br>IND<br>~~ee~~<br>~~OO~~|
|LCMXO3L-4300E-5UWG81ITR50<br>4300<br>1.2 V<br>5<br>Halogen-Free WLCSP<br>81<br>IND<br>~~GG~~|
|LCMXO3L-4300E-5UWG81ITR1K<br>4300<br>1.2 V<br>5<br>Halogen-Free WLCSP<br>81<br>IND<br>LCMXO3L-4300E-5MG121C<br>4300<br>1.2 V<br>5<br>Halogen-Free csfBGA<br>121<br>COM<br>LCMXO3L-4300E-6MG121C<br>4300<br>1.2 V<br>6<br>Halogen-Free csfBGA<br>121<br>COM<br>~~eeGG~~<br>~~Se~~<br>~~GG~~<br>~~eG~~|
|LCMXO3L-4300E-5MG121I<br>4300<br>1.2 V<br>5<br>Halogen-Free csfBGA<br>121<br>IND<br>LCMXO3L-4300E-6MG121I<br>4300<br>1.2 V<br>6<br>Halogen-Free csfBGA<br>121<br>IND<br>LCMXO3L-4300E-5MG256C<br>4300<br>1.2 V<br>5<br>Halogen-Free csfBGA<br>256<br>COM<br>LCMXO3L-4300E-6MG256C<br>4300<br>1.2 V<br>6<br>Halogen-Free csfBGA<br>256<br>COM<br>LCMXO3L-4300E-5MG256I<br>4300<br>1.2 V<br>5<br>Halogen-Free csfBGA<br>256<br>IND<br>~~ee~~<br>~~OO~~<br>~~ee~~<br>~~GC~~<br>~~po~~<br>~~ne~~<br>~~GG~~<br>~~GD~~|



© 2014-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02032-2.8 

83 

**MachXO3 Family Data Sheet** 

|**Part Number**<br>**LUTs**<br>**Supply Voltage **<br>**Speed**<br>**Package **<br>**Leads**<br>**Temp. **<br>~~pO~~|
|---|
|LCMXO3L-4300E-6MG256I<br>4300<br>1.2 V<br>6<br>Halogen-Free csfBGA<br>256<br>IND<br>~~eeGG~~|
|LCMXO3L-4300E-5MG324C<br>4300<br>1.2 V<br>5<br>Halogen-Free csfBGA<br>324<br>COM<br>~~GG~~|
|LCMXO3L-4300E-6MG324C<br>4300<br>1.2 V<br>6<br>Halogen-Free csfBGA<br>324<br>COM<br>LCMXO3L-4300E-5MG324I<br>4300<br>1.2 V<br>5<br>Halogen-Free csfBGA<br>324<br>IND<br>LCMXO3L-4300E-6MG324I<br>4300<br>1.2 V<br>6<br>Halogen-Free csfBGA<br>324<br>IND<br>LCMXO3L-4300C-5BG256C<br>4300<br>2.5 V/3.3 V<br>5<br>Halogen-Free caBGA<br>256<br>COM<br>LCMXO3L-4300C-6BG256C<br>4300<br>2.5 V/3.3 V<br>6<br>Halogen-Free caBGA<br>256<br>COM<br>~~GO~~<br>~~po~~<br>~~Ce~~<br>~~GG~~<br>~~ee~~<br>~~GG~~<br>~~GG~~|
|LCMXO3L-4300C-5BG256I<br>4300<br>2.5 V/3.3 V<br>5<br>Halogen-Free caBGA<br>256<br>IND<br>~~ee~~<br>~~GO~~|
|LCMXO3L-4300C-6BG256I<br>4300<br>2.5 V/3.3 V<br>6<br>Halogen-Free caBGA<br>256<br>IND<br>~~GG~~|
|LCMXO3L-4300C-5BG324C<br>4300<br>2.5 V/3.3 V<br>5<br>Halogen-Free caBGA<br>324<br>COM<br>LCMXO3L-4300C-6BG324C<br>4300<br>2.5 V/3.3 V<br>6<br>Halogen-Free caBGA<br>324<br>COM<br>LCMXO3L-4300C-5BG324I<br>4300<br>2.5 V/3.3 V<br>5<br>Halogen-Free caBGA<br>324<br>IND<br>~~eeGG~~<br>~~Ce~~<br>~~GG~~<br>~~GG~~|
|LCMXO3L-4300C-6BG324I<br>4300<br>2.5 V/3.3 V<br>6<br>Halogen-Free caBGA<br>324<br>IND<br>~~ee~~<br>~~GO~~|
|LCMXO3L-4300C-5BG400C<br>4300<br>2.5 V/3.3 V<br>5<br>Halogen-Free caBGA<br>400<br>COM<br>~~GG~~|
|LCMXO3L-4300C-6BG400C<br>4300<br>2.5 V/3.3 V<br>6<br>Halogen-Free caBGA<br>400<br>COM<br>LCMXO3L-4300C-5BG400I<br>4300<br>2.5 V/3.3 V<br>5<br>Halogen-Free caBGA<br>400<br>IND<br>LCMXO3L-4300C-6BG400I<br>4300<br>2.5 V/3.3 V<br>6<br>Halogen-Free caBGA<br>400<br>IND<br>~~eeGG~~<br>~~Ce~~<br>~~GG~~<br>~~pO~~|
|**Part Number**<br>**LUTs**<br>**Supply Voltage **<br>**Speed**<br>**Package **<br>**Leads**<br>**Temp. **<br>~~GO~~|
|LCMXO3L-6900E-5MG256C<br>6900<br>1.2 V<br>5<br>Halogen-Free csfBGA<br>256<br>COM<br>LCMXO3L-6900E-6MG256C<br>6900<br>1.2 V<br>6<br>Halogen-Free csfBGA<br>256<br>COM<br>LCMXO3L-6900E-5MG256I<br>6900<br>1.2 V<br>5<br>Halogen-Free csfBGA<br>256<br>IND<br>~~GG~~<br>~~Ce~~<br>~~GG~~<br>~~GG~~|
|LCMXO3L-6900E-6MG256I<br>6900<br>1.2 V<br>6<br>Halogen-Free csfBGA<br>256<br>IND<br>~~ee~~<br>~~GO~~|
|LCMXO3L-6900E-5MG324C<br>6900<br>1.2 V<br>5<br>Halogen-Free csfBGA<br>324<br>COM<br>LCMXO3L-6900E-6MG324C<br>6900<br>1.2 V<br>6<br>Halogen-Free csfBGA<br>324<br>COM<br>LCMXO3L-6900E-5MG324I<br>6900<br>1.2 V<br>5<br>Halogen-Free csfBGA<br>324<br>IND<br>LCMXO3L-6900E-6MG324I<br>6900<br>1.2 V<br>6<br>Halogen-Free csfBGA<br>324<br>IND<br>LCMXO3L-6900C-5BG256C<br>6900<br>2.5 V/3.3 V<br>5<br>Halogen-Free caBGA<br>256<br>COM<br>LCMXO3L-6900C-6BG256C<br>6900<br>2.5 V/3.3 V<br>6<br>Halogen-Free caBGA<br>256<br>COM<br>LCMXO3L-6900C-5BG256I<br>6900<br>2.5 V/3.3 V<br>5<br>Halogen-Free caBGA<br>256<br>IND<br>LCMXO3L-6900C-6BG256I<br>6900<br>2.5 V/3.3 V<br>6<br>Halogen-Free caBGA<br>256<br>IND<br>LCMXO3L-6900C-5BG324C<br>6900<br>2.5 V/3.3 V<br>5<br>Halogen-Free caBGA<br>324<br>COM<br>~~OO~~<br>~~ee~~<br>~~CO~~<br>~~eG~~<br>~~GO~~<br>~~ef~~<br>~~deGOO~~<br>~~I~~<br>~~SCO~~<br>~~ee~~<br>~~OG~~<br>~~eG~~<br>~~**G**O~~<br>~~e~~|
|LCMXO3L-6900C-6BG324C<br>6900<br>2.5 V/3.3 V<br>6<br>Halogen-Free caBGA<br>324<br>COM<br>LCMXO3L-6900C-5BG324I<br>6900<br>2.5 V/3.3 V<br>5<br>Halogen-Free caBGA<br>324<br>IND<br>LCMXO3L-6900C-6BG324I<br>6900<br>2.5 V/3.3 V<br>6<br>Halogen-Free caBGA<br>324<br>IND<br>LCMXO3L-6900C-5BG400C<br>6900<br>2.5 V/3.3 V<br>5<br>Halogen-Free caBGA<br>400<br>COM<br>LCMXO3L-6900C-6BG400C<br>6900<br>2.5 V/3.3 V<br>6<br>Halogen-Free caBGA<br>400<br>COM<br>~~ef~~<br>~~eG~~<br>~~GO~~<br>~~ee~~<br>~~OG~~<br>~~eG~~<br>~~**G**O~~<br>~~e~~|
|LCMXO3L-6900C-5BG400I<br>6900<br>2.5 V/3.3 V<br>5<br>Halogen-Free caBGA<br>400<br>IND<br>LCMXO3L-6900C-6BG400I<br>6900<br>2.5 V/3.3 V<br>6<br>Halogen-Free caBGA<br>400<br>IND<br>~~ef~~<br>~~ee~~<br>~~FO~~|
|**Part Number**<br>**LUTs**<br>**Supply Voltage **<br>**Speed**<br>**Package **<br>**Leads**<br>**Temp. **<br>LCMXO3L-9400E-5MG256C<br>9400<br>1.2 V<br>5<br>Halogen-Free csfBGA<br>256<br>COM<br>LCMXO3L-9400E-6MG256C<br>9400<br>1.2 V<br>6<br>Halogen-Free csfBGA<br>256<br>COM<br>LCMXO3L-9400E-5MG256I<br>9400<br>1.2 V<br>5<br>Halogen-Free csfBGA<br>256<br>IND<br>LCMXO3L-9400E-6MG256I<br>9400<br>1.2 V<br>6<br>Halogen-Free csfBGA<br>256<br>IND<br>LCMXO3L-9400E-5BG256C<br>9400<br>1.2 V<br>5<br>Halogen-Free caBGA<br>256<br>COM<br>LCMXO3L-9400E-6BG256C<br>9400<br>1.2 V<br>6<br>Halogen-Free caBGA<br>256<br>COM<br>~~pO~~<br>~~ee~~<br>~~GO~~<br>~~ef~~<br>~~eG~~<br>~~GO~~<br>~~ee~~<br>~~GC~~<br>~~Ce~~<br>~~GG~~<br>~~GG~~|
|LCMXO3L-9400E-5BG256I<br>9400<br>1.2 V<br>5<br>Halogen-Free caBGA<br>256<br>IND<br>~~eeGD~~|



© 2014-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

84 

FPGA-DS-02032-2.8 

**MachXO3 Family** 

**Data Sheet** 

|**Part Number**<br>~~pO~~<br>~~po~~|**LUTs**<br>~~pO~~|**Supply Voltage **<br>~~pO~~|**Speed**<br>~~pO~~|**Package **<br>~~pO~~|**Leads**<br>~~pO~~|**Temp. **<br>~~pO~~|
|---|---|---|---|---|---|---|
|LCMXO3L-9400E-6BG256I<br>~~po~~|9400|1.2 V|6|Halogen-Free caBGA|256|IND|
|LCMXO3L-9400E-5BG400C<br>~~po~~<br>~~Ce~~|9400<br>~~Ce~~|1.2 V<br>~~GG~~|5<br>~~GG~~|Halogen-Free caBGA<br>~~GG~~|400|COM|
|LCMXO3L-9400E-6BG400C<br>~~GO~~|9400<br>~~GO~~|1.2 V<br>~~GO~~|6<br>~~GO~~|Halogen-Free caBGA<br>~~GO~~|400<br>~~GO~~|COM<br>~~GO~~|
|LCMXO3L-9400E-5BG400I<br>~~GO~~<br>~~ee~~|9400<br>~~GO~~<br>~~ee~~|1.2 V<br>~~GO~~<br>~~GG~~|5<br>~~GO~~<br>~~GG~~|Halogen-Free caBGA<br>~~GO~~<br>~~GG~~|400<br>~~GO~~|IND<br>~~GO~~|
|LCMXO3L-9400E-6BG400I<br>~~GG~~|9400<br>~~GG~~|1.2 V<br>~~GG~~<br>~~GG~~|6<br>~~GG~~<br>~~GG~~|Halogen-Free caBGA<br>~~GG~~|400<br>~~GG~~|IND<br>~~GG~~|
|LCMXO3L-9400E-5BG484C<br>~~ee~~|9400<br>~~ee~~|1.2 V<br>~~ee~~<br>~~GG~~|5<br>~~ee~~<br>~~GG~~|Halogen-Free caBGA<br>~~ee~~|484<br>~~ee~~|COM<br>~~ee~~|
|LCMXO3L-9400E-6BG484C<br>~~pO~~|9400<br>~~pO~~|1.2 V<br>~~GG~~<br>~~pO~~|6<br>~~GG~~<br>~~pO~~|Halogen-Free caBGA<br>~~pO~~|484<br>~~pO~~|COM<br>~~pO~~|
|LCMXO3L-9400E-5BG484I<br>~~GO~~<br>~~ee~~|9400<br>~~GO~~<br>~~ee~~|1.2 V<br>~~GO~~<br>|5<br>~~GO~~<br>~~GO~~<br>|Halogen-Free caBGA<br>~~GO~~<br>|484<br>~~GO~~|IND<br>~~GO~~|
|LCMXO3L-9400E-6BG484I<br>~~GO~~<br>~~eG~~<br>~~ee~~|9400<br>~~GO~~<br>~~eG~~<br>~~ee~~|1.2 V<br>~~GO~~<br>~~eG~~<br>|6<br>~~GO~~<br>~~eG~~<br>~~GO~~<br>|Halogen-Free caBGA<br>~~GO~~<br>~~eG~~<br>|484<br>~~GO~~<br>~~eG~~|IND<br>~~GO~~<br>~~eG~~|
|LCMXO3L-9400C-5BG256C<br>~~ee~~|9400<br>~~ee~~|2.5 V/3.3 V<br>~~GG~~|5<br>~~GO~~<br>~~GG~~|Halogen-Free caBGA<br>~~GG~~|256|COM|
|LCMXO3L-9400C-6BG256C<br>~~GG~~|9400<br>~~GG~~|2.5 V/3.3 V<br>~~GG~~|6<br>~~GG~~|Halogen-Free caBGA<br>~~GG~~|256<br>~~GG~~|COM<br>~~GG~~|
|LCMXO3L-9400C-5BG256I<br>~~pO~~|9400<br>~~pO~~|2.5 V/3.3 V<br>~~pO~~|5<br>~~pO~~|Halogen-Free caBGA<br>~~pO~~|256<br>~~pO~~|IND<br>~~pO~~|
|LCMXO3L-9400C-6BG256I<br>~~GO~~<br>~~ee~~|9400<br>~~GO~~<br>~~ee~~|2.5 V/3.3 V<br>~~GO~~<br>|6<br>~~GO~~<br>~~GO~~<br>|Halogen-Free caBGA<br>~~GO~~<br>|256<br>~~GO~~|IND<br>~~GO~~|
|LCMXO3L-9400C-5BG400C<br>~~GO~~<br>~~eG~~<br>~~ee~~|9400<br>~~GO~~<br>~~eG~~<br>~~ee~~|2.5 V/3.3 V<br>~~GO~~<br>~~eG~~<br>|5<br>~~GO~~<br>~~eG~~<br>~~GO~~<br>|Halogen-Free caBGA<br>~~GO~~<br>~~eG~~<br>|400<br>~~GO~~<br>~~eG~~|COM<br>~~GO~~<br>~~eG~~|
|LCMXO3L-9400C-6BG400C<br>~~ee~~|9400<br>~~ee~~|2.5 V/3.3 V<br>~~GG~~|6<br>~~GO~~<br>~~GG~~|Halogen-Free caBGA<br>~~GG~~|400|COM|
|LCMXO3L-9400C-5BG400I<br>~~GG~~|9400<br>~~GG~~|2.5 V/3.3 V<br>~~GG~~|5<br>~~GG~~|Halogen-Free caBGA<br>~~GG~~|400<br>~~GG~~|IND<br>~~GG~~|
|LCMXO3L-9400C-6BG400I<br>~~pO~~|9400<br>~~pO~~|2.5 V/3.3 V<br>~~pO~~|6<br>~~pO~~|Halogen-Free caBGA<br>~~pO~~|400<br>~~pO~~|IND<br>~~pO~~|
|LCMXO3L-9400C-5BG484C<br>~~GO~~|9400<br>~~GO~~|2.5 V/3.3 V<br>~~GO~~|5<br>~~GO~~|Halogen-Free caBGA<br>~~GO~~|484<br>~~GO~~|COM<br>~~GO~~|
|LCMXO3L-9400C-6BG484C<br>~~GO~~<br>~~CO~~<br>~~po~~|9400<br>~~GO~~<br>~~CO~~|2.5 V/3.3 V<br>~~GO~~<br>~~CO~~|6<br>~~GO~~<br>~~CO~~<br>~~GO~~|Halogen-Free caBGA<br>~~GO~~<br>~~CO~~|484<br>~~GO~~<br>~~CO~~|COM<br>~~GO~~<br>~~CO~~|
|LCMXO3L-9400C-5BG484I<br>~~CO~~<br>~~eG~~<br>~~po~~|9400<br>~~CO~~<br>~~eG~~|2.5 V/3.3 V<br>~~CO~~<br>~~eG~~|5<br>~~CO~~<br>~~eG~~<br>~~GO~~|Halogen-Free caBGA<br>~~CO~~<br>~~eG~~|484<br>~~CO~~<br>~~eG~~|IND<br>~~CO~~<br>~~eG~~|
|LCMXO3L-9400C-6BG484I<br>~~po~~|9400|2.5 V/3.3 V|6<br>~~GO~~|Halogen-Free caBGA|484|IND|



## **6.2. MachXO3LF Ultra Low Power Commercial and Industrial Grade Devices, Halogen Free (RoHS) Packaging** 

|**Part Number**<br>~~pO~~|**LUTs**<br>~~pO~~|**Supply Voltage **<br>~~pO~~|**Speed**<br>~~pO~~|**Package **<br>~~pO~~|**Leads**<br>~~pO~~|**Temp. **<br>~~pO~~|
|---|---|---|---|---|---|---|
|LCMXO3LF-1300E-5UWG36CTR<br>~~GG~~|1300<br>~~GG~~|1.2 V<br>~~GG~~|5<br>~~GG~~|Halogen-Free WLCSP<br>~~GG~~|36<br>~~GG~~|COM<br>~~GG~~|
|LCMXO3LF-1300E-5UWG36CTR50<br>~~eG~~<br>~~ed~~|1300<br>~~eG~~<br>~~GOO~~|1.2 V<br>~~eG~~<br>~~GOO~~|5<br>~~eG~~<br>~~GOO~~|Halogen-Free WLCSP<br>~~eG~~<br>~~GOO~~|36<br>~~eG~~|COM<br>~~eG~~|
|LCMXO3LF-1300E-5UWG36CTR1K<br>~~eG~~<br>~~ed~~|1300<br>~~eG~~<br>~~GOO~~|1.2 V<br>~~eG~~<br>~~GOO~~|5<br>~~eG~~<br>~~GOO~~|Halogen-Free WLCSP<br>~~eG~~<br>~~GOO~~|36<br>~~eG~~|COM<br>~~eG~~|
|LCMXO3LF-1300E-5UWG36ITR<br>~~ed ~~<br>~~ee~~|1300<br> ~~GOO~~<br>~~ee~~|1.2 V<br>~~GOO~~<br>~~OO~~|5<br>~~GOO~~<br>~~OO~~|Halogen-Free WLCSP<br>~~GOO~~<br>~~OO~~|36|IND|
|LCMXO3LF-1300E-5UWG36ITR50<br>~~ee~~<br>~~GG~~|1300<br>~~ee~~<br>~~GG~~|1.2 V<br>~~OO~~<br>~~GG~~<br>~~GG~~|5<br>~~OO~~<br>~~GG~~<br>~~GG~~|Halogen-Free WLCSP<br>~~OO~~<br>~~GG~~|36<br>~~GG~~|IND<br>~~GG~~|
|LCMXO3LF-1300E-5UWG36ITR1K<br>~~Se~~|1300<br>~~Se~~|1.2 V<br>~~Se~~<br>~~GG~~|5<br>~~Se~~<br>~~GG~~|Halogen-Free WLCSP<br>~~Se~~|36<br>~~Se~~|IND<br>~~Se~~|
|LCMXO3LF-1300E-5MG121C<br>~~eG~~<br>~~ed~~|1300<br>~~eG~~<br>~~GOO~~|1.2 V<br>~~GG~~<br>~~eG~~<br>~~GOO~~|5<br>~~GG~~<br>~~eG~~<br>~~GOO~~|Halogen-Free csfBGA<br>~~eG~~<br>~~GOO~~|121<br>~~eG~~|COM<br>~~eG~~|
|LCMXO3LF-1300E-6MG121C<br>~~eG~~<br>~~ed~~|1300<br>~~eG~~<br>~~GOO~~|1.2 V<br>~~eG~~<br>~~GOO~~|6<br>~~eG~~<br>~~GOO~~|Halogen-Free csfBGA<br>~~eG~~<br>~~GOO~~|121<br>~~eG~~|COM<br>~~eG~~|
|LCMXO3LF-1300E-5MG121I<br>~~ed ~~<br>~~ee~~|1300<br> ~~GOO~~<br>~~ee~~|1.2 V<br>~~GOO~~<br>~~OO~~|5<br>~~GOO~~<br>~~OO~~|Halogen-Free csfBGA<br>~~GOO~~<br>~~OO~~|121|IND|
|LCMXO3LF-1300E-6MG121I<br>~~ee~~<br>~~GG~~|1300<br>~~ee~~<br>~~GG~~|1.2 V<br>~~OO~~<br>~~GG~~<br>~~GG~~|6<br>~~OO~~<br>~~GG~~<br>~~GG~~|Halogen-Free csfBGA<br>~~OO~~<br>~~GG~~|121<br>~~GG~~|IND<br>~~GG~~|
|LCMXO3LF-1300E-5MG256C<br>~~Se~~|1300<br>~~Se~~|1.2 V<br>~~Se~~<br>~~GG~~<br>~~GG~~|5<br>~~Se~~<br>~~GG~~<br>~~GG~~|Halogen-Free csfBGA<br>~~Se~~|256<br>~~Se~~|COM<br>~~Se~~|
|LCMXO3LF-1300E-6MG256C<br>~~Ce~~|1300<br>~~Ce~~|1.2 V<br>~~GG~~<br>~~Ce~~<br>~~GG~~|6<br>~~GG~~<br>~~Ce~~<br>~~GG~~|Halogen-Free csfBGA<br>~~Ce~~|256<br>~~Ce~~|COM<br>~~Ce~~|
|LCMXO3LF-1300E-5MG256I<br>~~GO~~|1300<br>~~GO~~|1.2 V<br>~~GG~~<br>~~GO~~|5<br>~~GG~~<br>~~GO~~|Halogen-Free csfBGA<br>~~GO~~|256<br>~~GO~~|IND<br>~~GO~~|
|LCMXO3LF-1300E-6MG256I<br>~~GO~~<br>~~GG~~|1300<br>~~GO~~<br>~~GG~~|1.2 V<br>~~GO~~<br>~~GG~~|6<br>~~GO~~<br>~~GG~~|Halogen-Free csfBGA<br>~~GO~~<br>~~GG~~|256<br>~~GO~~<br>~~GG~~|IND<br>~~GO~~<br>~~GG~~|
|LCMXO3LF-1300C-5BG256C<br>~~GG~~<br>~~po~~|1300<br>~~GG~~<br>~~po~~|2.5 V/3.3 V<br>~~GG~~<br>~~po~~|5<br>~~GG~~<br>~~po~~|Halogen-Free caBGA<br>~~GG~~<br>~~po~~|256<br>~~GG~~<br>~~po~~|COM<br>~~GG~~<br>~~po~~|



© 2014-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02032-2.8 

85 

**MachXO3 Family Data Sheet** 

|**Part Number**<br>**LUTs**<br>**Supply Voltage **<br>**Speed**<br>**Package **<br>**Leads**<br>**Temp. **|
|---|
|LCMXO3LF-1300C-6BG256C<br>1300<br>2.5 V/3.3 V<br>6<br>Halogen-Free caBGA<br>256<br>COM|
|LCMXO3LF-1300C-5BG256I<br>1300<br>2.5 V/3.3 V<br>5<br>Halogen-Free caBGA<br>256<br>IND|
|LCMXO3LF-1300C-6BG256I<br>1300<br>2.5 V/3.3 V<br>6<br>Halogen-Free caBGA<br>256<br>IND|
|**Part Number**<br>**LUTs**<br>**Supply Voltage **<br>**Speed**<br>**Package **<br>**Leads**<br>**Temp. **<br>LCMXO3LF-2100E-5UWG49CTR<br>2100<br>1.2 V<br>5<br>Halogen-Free WLCSP<br>49<br>COM<br>LCMXO3LF-2100E-5UWG49CTR50<br>2100<br>1.2 V<br>5<br>Halogen-Free WLCSP<br>49<br>COM<br>~~pO~~<br>~~Ge~~<br>~~GG~~<br>~~GG~~|
|LCMXO3LF-2100E-5UWG49CTR1K<br>2100<br>1.2 V<br>5<br>Halogen-Free WLCSP<br>49<br>COM<br>~~ee~~<br>~~GO~~|
|LCMXO3LF-2100E-5UWG49ITR<br>2100<br>1.2 V<br>5<br>Halogen-Free WLCSP<br>49<br>IND<br>~~GG~~|
|LCMXO3LF-2100E-5UWG49ITR50<br>2100<br>1.2 V<br>5<br>Halogen-Free WLCSP<br>49<br>IND<br>LCMXO3LF-2100E-5UWG49ITR1K<br>2100<br>1.2 V<br>5<br>Halogen-Free WLCSP<br>49<br>IND<br>LCMXO3LF-2100E-5MG121C<br>2100<br>1.2 V<br>5<br>Halogen-Free csfBGA<br>121<br>COM<br>~~eeGG~~<br>~~Ce~~<br>~~GG~~<br>~~GG~~|
|LCMXO3LF-2100E-6MG121C<br>2100<br>1.2 V<br>6<br>Halogen-Free csfBGA<br>121<br>COM<br>~~ee~~<br>~~GO~~|
|LCMXO3LF-2100E-5MG121I<br>2100<br>1.2 V<br>5<br>Halogen-Free csfBGA<br>121<br>IND<br>~~GG~~|
|LCMXO3LF-2100E-6MG121I<br>2100<br>1.2 V<br>6<br>Halogen-Free csfBGA<br>121<br>IND<br>LCMXO3LF-2100E-5MG256C<br>2100<br>1.2 V<br>5<br>Halogen-Free csfBGA<br>256<br>COM<br>LCMXO3LF-2100E-6MG256C<br>2100<br>1.2 V<br>6<br>Halogen-Free csfBGA<br>256<br>COM<br>~~eeGG~~<br>~~Ce~~<br>~~GG~~<br>~~GG~~|
|LCMXO3LF-2100E-5MG256I<br>2100<br>1.2 V<br>5<br>Halogen-Free csfBGA<br>256<br>IND<br>LCMXO3LF-2100E-6MG256I<br>2100<br>1.2 V<br>6<br>Halogen-Free csfBGA<br>256<br>IND<br>LCMXO3LF-2100E-5MG324C<br>2100<br>1.2 V<br>5<br>Halogen-Free csfBGA<br>324<br>COM<br>LCMXO3LF-2100E-6MG324C<br>2100<br>1.2 V<br>6<br>Halogen-Free csfBGA<br>324<br>COM<br>LCMXO3LF-2100E-5MG324I<br>2100<br>1.2 V<br>5<br>Halogen-Free csfBGA<br>324<br>IND<br>~~ee~~<br>~~GO~~<br>~~ee~~<br>~~CO~~<br>~~GG~~<br>~~Ce~~<br>~~GG~~<br>~~GG~~|
|LCMXO3LF-2100E-6MG324I<br>2100<br>1.2 V<br>6<br>Halogen-Free csfBGA<br>324<br>IND<br>~~ee~~<br>~~GO~~|
|LCMXO3LF-2100C-5BG256C<br>2100<br>2.5 V/3.3 V<br>5<br>Halogen-Free caBGA<br>256<br>COM<br>LCMXO3LF-2100C-6BG256C<br>2100<br>2.5 V/3.3 V<br>6<br>Halogen-Free caBGA<br>256<br>COM<br>LCMXO3LF-2100C-5BG256I<br>2100<br>2.5 V/3.3 V<br>5<br>Halogen-Free caBGA<br>256<br>IND<br>LCMXO3LF-2100C-6BG256I<br>2100<br>2.5 V/3.3 V<br>6<br>Halogen-Free caBGA<br>256<br>IND<br>LCMXO3LF-2100C-5BG324C<br>2100<br>2.5 V/3.3 V<br>5<br>Halogen-Free caBGA<br>324<br>COM<br>LCMXO3LF-2100C-6BG324C<br>2100<br>2.5 V/3.3 V<br>6<br>Halogen-Free caBGA<br>324<br>COM<br>LCMXO3LF-2100C-5BG324I<br>2100<br>2.5 V/3.3 V<br>5<br>Halogen-Free caBGA<br>324<br>IND<br>LCMXO3LF-2100C-6BG324I<br>2100<br>2.5 V/3.3 V<br>6<br>Halogen-Free caBGA<br>324<br>IND<br>~~OO~~<br>~~ee~~<br>~~CO~~<br>~~eG~~<br>~~GO~~<br>~~ef~~<br>~~deGOO~~<br>~~I~~<br>~~SCO~~<br>~~ee~~<br>~~OG~~<br>~~po~~|
|**Part Number**<br>**LUTs**<br>**Supply Voltage **<br>**Speed**<br>**Package **<br>**Leads**<br>**Temp. **<br>LCMXO3LF-4300E-5UWG81CTR<br>4300<br>1.2 V<br>5<br>Halogen-Free WLCSP<br>81<br>COM<br>LCMXO3LF-4300E-5UWG81CTR50<br>4300<br>1.2 V<br>5<br>Halogen-Free WLCSP<br>81<br>COM<br>LCMXO3LF-4300E-5UWG81CTR1K<br>4300<br>1.2 V<br>5<br>Halogen-Free WLCSP<br>81<br>COM<br>LCMXO3LF-4300E-5UWG81ITR<br>4300<br>1.2 V<br>5<br>Halogen-Free WLCSP<br>81<br>IND<br>~~GG~~<br>~~GO~~<br>~~GO~~<br>~~GG~~<br>~~ee~~<br>~~OG~~<br>~~eG~~<br>~~**G**O~~<br>~~e~~|
|LCMXO3LF-4300E-5UWG81ITR50<br>4300<br>1.2 V<br>5<br>Halogen-Free WLCSP<br>81<br>IND<br>LCMXO3LF-4300E-5UWG81ITR1K<br>4300<br>1.2 V<br>5<br>Halogen-Free WLCSP<br>81<br>IND<br>LCMXO3LF-4300E-5MG121C<br>4300<br>1.2 V<br>5<br>Halogen-Free csfBGA<br>121<br>COM<br>LCMXO3LF-4300E-6MG121C<br>4300<br>1.2 V<br>6<br>Halogen-Free csfBGA<br>121<br>COM<br>LCMXO3LF-4300E-5MG121I<br>4300<br>1.2 V<br>5<br>Halogen-Free csfBGA<br>121<br>IND<br>LCMXO3LF-4300E-6MG121I<br>4300<br>1.2 V<br>6<br>Halogen-Free csfBGA<br>121<br>IND<br>LCMXO3LF-4300E-5MG256C<br>4300<br>1.2 V<br>5<br>Halogen-Free csfBGA<br>256<br>COM<br>LCMXO3LF-4300E-6MG256C<br>4300<br>1.2 V<br>6<br>Halogen-Free csfBGA<br>256<br>COM<br>LCMXO3LF-4300E-5MG256I<br>4300<br>1.2 V<br>5<br>Halogen-Free csfBGA<br>256<br>IND<br>LCMXO3LF-4300E-6MG256I<br>4300<br>1.2 V<br>6<br>Halogen-Free csfBGA<br>256<br>IND<br>~~ef~~<br>~~eG~~<br>~~GO~~<br>~~ee~~<br>~~OG~~<br>~~eeGG~~<br>~~eG~~<br>~~GO~~<br>~~ef~~<br>~~eG~~<br>~~GO~~<br>~~ee~~<br>~~GC~~<br>~~Ce~~<br>~~GG~~<br>~~GG~~|
|LCMXO3LF-4300E-5MG324C<br>4300<br>1.2 V<br>5<br>Halogen-Free csfBGA<br>324<br>COM<br>~~eeGD~~|



© 2014-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

86 

FPGA-DS-02032-2.8 

**MachXO3 Family** 

**Data Sheet** 

|**Part Number**<br>**LUTs**<br>**Supply Voltage **<br>**Speed**<br>**Package **<br>**Leads**<br>**Temp. **<br>LCMXO3LF-4300E-6MG324C<br>4300<br>1.2 V<br>6<br>Halogen-Free csfBGA<br>324<br>COM<br>LCMXO3LF-4300E-5MG324I<br>4300<br>1.2 V<br>5<br>Halogen-Free csfBGA<br>324<br>IND<br>~~pO~~<br>~~po~~<br>~~CeGG~~|
|---|
|LCMXO3LF-4300E-6MG324I<br>4300<br>1.2 V<br>6<br>Halogen-Free csfBGA<br>324<br>IND<br>~~GO~~|
|LCMXO3LF-4300C-5BG256C<br>4300<br>2.5 V/3.3 V<br>5<br>Halogen-Free caBGA<br>256<br>COM<br>~~eeGG~~|
|LCMXO3LF-4300C-6BG256C<br>4300<br>2.5 V/3.3 V<br>6<br>Halogen-Free caBGA<br>256<br>COM<br>LCMXO3LF-4300C-5BG256I<br>4300<br>2.5 V/3.3 V<br>5<br>Halogen-Free caBGA<br>256<br>IND<br>LCMXO3LF-4300C-6BG256I<br>4300<br>2.5 V/3.3 V<br>6<br>Halogen-Free caBGA<br>256<br>IND<br>~~GG~~<br>~~ee~~<br>~~GG~~<br>~~pO~~|
|LCMXO3LF-4300C-5BG324C<br>4300<br>2.5 V/3.3 V<br>5<br>Halogen-Free caBGA<br>324<br>COM<br>LCMXO3LF-4300C-6BG324C<br>4300<br>2.5 V/3.3 V<br>6<br>Halogen-Free caBGA<br>324<br>COM<br>LCMXO3LF-4300C-5BG324I<br>4300<br>2.5 V/3.3 V<br>5<br>Halogen-Free caBGA<br>324<br>IND<br>~~GO~~<br>~~eG~~<br>~~GO~~<br>~~eeGG~~|
|LCMXO3LF-4300C-6BG324I<br>4300<br>2.5 V/3.3 V<br>6<br>Halogen-Free caBGA<br>324<br>IND<br>~~GG~~|
|LCMXO3LF-4300C-5BG400C<br>4300<br>2.5 V/3.3 V<br>5<br>Halogen-Free caBGA<br>400<br>COM<br>~~pO~~|
|LCMXO3LF-4300C-6BG400C<br>4300<br>2.5 V/3.3 V<br>6<br>Halogen-Free caBGA<br>400<br>COM<br>LCMXO3LF-4300C-5BG400I<br>4300<br>2.5 V/3.3 V<br>5<br>Halogen-Free caBGA<br>400<br>IND<br>LCMXO3LF-4300C-6BG400I<br>4300<br>2.5 V/3.3 V<br>6<br>Halogen-Free caBGA<br>400<br>IND<br>~~GO~~<br>~~eG~~<br>~~GO~~<br>~~po~~|
|**Part Number**<br>**LUTs**<br>**Supply Voltage **<br>**Speed**<br>**Package **<br>**Leads**<br>**Temp. **<br>LCMXO3LF-6900E-5MG256C<br>6900<br>1.2 V<br>5<br>Halogen-Free csfBGA<br>256<br>COM<br>~~Ce~~<br>~~S(O~~<br>~~GO~~<br>~~GO~~|
|LCMXO3LF-6900E-6MG256C<br>6900<br>1.2 V<br>6<br>Halogen-Free csfBGA<br>256<br>COM<br>LCMXO3LF-6900E-5MG256I<br>6900<br>1.2 V<br>5<br>Halogen-Free csfBGA<br>256<br>IND<br>LCMXO3LF-6900E-6MG256I<br>6900<br>1.2 V<br>6<br>Halogen-Free csfBGA<br>256<br>IND<br>~~CO~~<br>~~eG~~<br>~~**G**O~~<br>~~G~~|
|LCMXO3LF-6900E-5MG324C<br>6900<br>1.2 V<br>5<br>Halogen-Free csfBGA<br>324<br>COM<br>~~pO~~|
|LCMXO3LF-6900E-6MG324C<br>6900<br>1.2 V<br>6<br>Halogen-Free csfBGA<br>324<br>COM<br>~~GO~~|
|LCMXO3LF-6900E-5MG324I<br>6900<br>1.2 V<br>5<br>Halogen-Free csfBGA<br>324<br>IND<br>LCMXO3LF-6900E-6MG324I<br>6900<br>1.2 V<br>6<br>Halogen-Free csfBGA<br>324<br>IND<br>LCMXO3LF-6900C-5BG256C<br>6900<br>2.5 V/3.3 V<br>5<br>Halogen-Free caBGA<br>256<br>COM<br>LCMXO3LF-6900C-6BG256C<br>6900<br>2.5 V/3.3 V<br>6<br>Halogen-Free caBGA<br>256<br>COM<br>LCMXO3LF-6900C-5BG256I<br>6900<br>2.5 V/3.3 V<br>5<br>Halogen-Free caBGA<br>256<br>IND<br>LCMXO3LF-6900C-6BG256I<br>6900<br>2.5 V/3.3 V<br>6<br>Halogen-Free caBGA<br>256<br>IND<br>~~OO~~<br>~~eG~~<br>~~GO~~<br>~~Se~~<br>~~GG~~<br>~~eG~~<br>~~deGOO~~<br>~~I~~<br>~~ee~~<br>~~GO~~|
|LCMXO3LF-6900C-5BG324C<br>6900<br>2.5 V/3.3 V<br>5<br>Halogen-Free caBGA<br>324<br>COM<br>LCMXO3LF-6900C-6BG324C<br>6900<br>2.5 V/3.3 V<br>6<br>Halogen-Free caBGA<br>324<br>COM<br>LCMXO3LF-6900C-5BG324I<br>6900<br>2.5 V/3.3 V<br>5<br>Halogen-Free caBGA<br>324<br>IND<br>LCMXO3LF-6900C-6BG324I<br>6900<br>2.5 V/3.3 V<br>6<br>Halogen-Free caBGA<br>324<br>IND<br>~~GG~~<br>~~Se~~<br>~~GG~~<br>~~ee~~<br>~~GG~~<br>~~eG~~|
|LCMXO3LF-6900C-5BG400C<br>6900<br>2.5 V/3.3 V<br>5<br>Halogen-Free caBGA<br>400<br>COM<br>~~ee~~<br>~~OO~~|
|LCMXO3LF-6900C-6BG400C<br>6900<br>2.5 V/3.3 V<br>6<br>Halogen-Free caBGA<br>400<br>COM<br>LCMXO3LF-6900C-5BG400I<br>6900<br>2.5 V/3.3 V<br>5<br>Halogen-Free caBGA<br>400<br>IND<br>LCMXO3LF-6900C-6BG400I<br>6900<br>2.5 V/3.3 V<br>6<br>Halogen-Free caBGA<br>400<br>IND<br>~~GG~~<br>~~Se~~<br>~~GG~~<br>~~DO~~|



© 2014-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02032-2.8 

87 

**MachXO3 Family Data Sheet** 

|**Part Number**<br>~~pO~~|**LUTs**<br>~~pO~~|**Supply Voltage **<br>~~pO~~|**Speed**<br>~~pO~~|**Package **<br>~~pO~~|**Leads**<br>~~pO~~|**Temp. **<br>~~pO~~|
|---|---|---|---|---|---|---|
|LCMXO3LF-9400E-5MG256C<br>~~ee~~|9400<br>~~ee~~|1.2 V<br>~~GG~~|5<br>~~GG~~|Halogen-Free csfBGA<br>~~GG~~|256|COM|
|LCMXO3LF-9400E-6MG256C<br>~~GG~~|9400<br>~~GG~~|1.2 V<br>~~GG~~|6<br>~~GG~~|Halogen-Free csfBGA<br>~~GG~~|256<br>~~GG~~|COM<br>~~GG~~|
|LCMXO3LF-9400E-5MG256I<br>~~GO~~<br>~~po~~|9400<br>~~GO~~|1.2 V<br>~~GO~~|5<br>~~GO~~|Halogen-Free csfBGA<br>~~GO~~|256<br>~~GO~~|IND<br>~~GO~~|
|LCMXO3LF-9400E-6MG256I<br>~~GO~~<br>~~po~~|9400<br>~~GO~~|1.2 V<br>~~GO~~<br>~~GG~~|6<br>~~GO~~<br>~~GG~~|Halogen-Free csfBGA<br>~~GO~~|256<br>~~GO~~|IND<br>~~GO~~|
|LCMXO3LF-9400E-5BG256C<br>~~po~~<br>~~Ce~~|9400<br>~~Ce~~|1.2 V<br>~~Ce~~<br>~~GG~~<br>~~GG~~|5<br>~~Ce~~<br>~~GG~~<br>~~GG~~|Halogen-Free caBGA<br>~~Ce~~|256<br>~~Ce~~|COM<br>~~Ce~~|
|LCMXO3LF-9400E-6BG256C<br>~~ee~~|9400<br>~~ee~~|1.2 V<br>~~GG~~<br>~~ee~~<br>~~GG~~|6<br>~~GG~~<br>~~ee~~<br>~~GG~~|Halogen-Free caBGA<br>~~ee~~|256<br>~~ee~~|COM<br>~~ee~~|
|LCMXO3LF-9400E-5BG256I<br>~~GG~~|9400<br>~~GG~~|1.2 V<br>~~GG~~<br>~~GG~~|5<br>~~GG~~<br>~~GG~~|Halogen-Free caBGA<br>~~GG~~|256<br>~~GG~~|IND<br>~~GG~~|
|LCMXO3LF-9400E-6BG256I<br>~~ee~~|9400<br>~~ee~~|1.2 V<br>~~GO~~|6<br>~~GO~~|Halogen-Free caBGA<br>~~GO~~|256|IND|
|LCMXO3LF-9400E-5BG400C<br>~~ee~~<br>~~GG~~|9400<br>~~ee~~<br>~~GG~~|1.2 V<br>~~GO~~<br>~~GG~~|5<br>~~GO~~<br>~~GG~~|Halogen-Free caBGA<br>~~GO~~<br>~~GG~~|400<br>~~GG~~|COM<br>~~GG~~|
|LCMXO3LF-9400E-6BG400C<br>~~ee~~|9400<br>~~ee~~|1.2 V<br>~~GG~~<br>~~GG~~|6<br>~~GG~~<br>~~GG~~|Halogen-Free caBGA<br>~~GG~~|400|COM|
|LCMXO3LF-9400E-5BG400I<br>~~Ce~~|9400<br>~~Ce~~|1.2 V<br>~~Ce~~<br>~~GG~~|5<br>~~Ce~~<br>~~GG~~|Halogen-Free caBGA<br>~~Ce~~|400<br>~~Ce~~|IND<br>~~Ce~~|
|LCMXO3LF-9400E-6BG400I<br>~~GG~~|9400<br>~~GG~~|1.2 V<br>~~GG~~<br>~~GG~~|6<br>~~GG~~<br>~~GG~~|Halogen-Free caBGA<br>~~GG~~|400<br>~~GG~~|IND<br>~~GG~~|
|LCMXO3LF-9400E-5BG484C<br>~~ee~~|9400<br>~~ee~~|1.2 V<br>~~GO~~|5<br>~~GO~~|Halogen-Free caBGA<br>~~GO~~|484|COM|
|LCMXO3LF-9400E-6BG484C<br>~~ee~~<br>~~GG~~|9400<br>~~ee~~<br>~~GG~~|1.2 V<br>~~GO~~<br>~~GG~~|6<br>~~GO~~<br>~~GG~~|Halogen-Free caBGA<br>~~GO~~<br>~~GG~~|484<br>~~GG~~|COM<br>~~GG~~|
|LCMXO3LF-9400E-5BG484I<br>~~ee~~|9400<br>~~ee~~|1.2 V<br>~~GG~~<br>~~GG~~|5<br>~~GG~~<br>~~GG~~|Halogen-Free caBGA<br>~~GG~~|484|IND|
|LCMXO3LF-9400E-6BG484I<br>~~Ce~~|9400<br>~~Ce~~|1.2 V<br>~~Ce~~<br>~~GG~~|6<br>~~Ce~~<br>~~GG~~|Halogen-Free caBGA<br>~~Ce~~|484<br>~~Ce~~|IND<br>~~Ce~~|
|LCMXO3LF-9400C-5BG256C<br>~~GG~~|9400<br>~~GG~~|2.5 V/3.3 V<br>~~GG~~<br>~~GG~~|5<br>~~GG~~<br>~~GG~~|Halogen-Free caBGA<br>~~GG~~|256<br>~~GG~~|COM<br>~~GG~~|
|LCMXO3LF-9400C-6BG256C<br>~~ee~~<br>~~ee~~|9400<br>~~ee~~|2.5 V/3.3 V<br>~~GO~~<br>~~CO~~|6<br>~~GO~~<br>~~CO~~|Halogen-Free caBGA<br>~~GO~~<br>~~CO~~|256|COM|
|LCMXO3LF-9400C-5BG256I<br>~~ee~~<br>~~ee~~|9400<br>~~ee~~|2.5 V/3.3 V<br>~~GO~~<br>~~CO~~|5<br>~~GO~~<br>~~CO~~|Halogen-Free caBGA<br>~~GO~~<br>~~CO~~|256|IND|
|LCMXO3LF-9400C-6BG256I<br>~~ee~~<br>~~GG~~|9400<br>~~GG~~|2.5 V/3.3 V<br>~~CO~~<br>~~GG~~<br>~~GG~~|6<br>~~CO~~<br>~~GG~~<br>~~GG~~|Halogen-Free caBGA<br>~~CO~~<br>~~GG~~|256<br>~~GG~~|IND<br>~~GG~~|
|LCMXO3LF-9400C-5BG400C<br>~~Ce~~|9400<br>~~Ce~~|2.5 V/3.3 V<br>~~Ce~~<br>~~GG~~|5<br>~~Ce~~<br>~~GG~~|Halogen-Free caBGA<br>~~Ce~~|400<br>~~Ce~~|COM<br>~~Ce~~|
|LCMXO3LF-9400C-6BG400C<br>~~GG~~|9400<br>~~GG~~|2.5 V/3.3 V<br>~~GG~~<br>~~GG~~|6<br>~~GG~~<br>~~GG~~|Halogen-Free caBGA<br>~~GG~~|400<br>~~GG~~|COM<br>~~GG~~|
|LCMXO3LF-9400C-5BG400I<br>~~ee~~|9400<br>~~ee~~|2.5 V/3.3 V<br>~~GO~~|5<br>~~GO~~|Halogen-Free caBGA<br>~~GO~~|400|IND|
|LCMXO3LF-9400C-6BG400I<br>~~ee~~<br>~~OO~~|9400<br>~~ee~~<br>~~OO~~|2.5 V/3.3 V<br>~~GO~~<br>~~OO~~<br>~~CO~~|6<br>~~GO~~<br>~~OO~~<br>~~CO~~|Halogen-Free caBGA<br>~~GO~~<br>~~OO~~|400<br>~~OO~~|IND<br>~~OO~~|
|LCMXO3LF-9400C-5BG484C<br>~~OO~~<br>~~ee~~|9400<br>~~OO~~<br>~~ee~~|2.5 V/3.3 V<br>~~OO~~<br>~~ee~~<br>~~CO~~|5<br>~~OO~~<br>~~ee~~<br>~~CO~~<br>~~GO~~|Halogen-Free caBGA<br>~~OO~~<br>~~ee~~|484<br>~~OO~~<br>~~ee~~|COM<br>~~OO~~<br>~~ee~~|
|LCMXO3LF-9400C-6BG484C<br>~~eG~~|9400<br>~~eG~~|2.5 V/3.3 V<br>~~CO~~<br>~~eG~~|6<br>~~CO~~<br>~~eG~~<br>~~GO~~|Halogen-Free caBGA<br>~~eG~~|484<br>~~eG~~|COM<br>~~eG~~|
|LCMXO3LF-9400C-5BG484I<br>~~ef~~<br>~~ee~~|9400<br>~~ef~~|2.5 V/3.3 V<br>~~ef~~<br>~~FO~~|5<br>~~GO~~<br>~~ef~~<br>~~FO~~|Halogen-Free caBGA<br>~~ef~~<br>~~FO~~|484<br>~~ef~~|IND<br>~~ef~~|
|LCMXO3LF-9400C-6BG484I<br>~~ef~~<br>~~ee~~|9400<br>~~ef~~|2.5 V/3.3 V<br>~~ef~~<br>~~FO~~|6<br>~~ef~~<br>~~FO~~|Halogen-Free caBGA<br>~~ef~~<br>~~FO~~|484<br>~~ef~~|IND<br>~~ef~~|



|**Part Number**<br>~~pO~~|**LUTs**|**Supply Voltage **|**Speed**|**Package **|**Leads**|**Temp. **|
|---|---|---|---|---|---|---|
|LAMXO3LF-1300E-5BG256E<br>~~pO~~<br>~~Ge~~|1300<br>~~Ge~~|1.2<br>~~Ge~~|5<br>~~Ge~~|Halogen-Free caBGA<br>~~Ge~~|256<br>~~Ge~~|AUTO<br>~~Ge~~|
|LAMXO3LF-1300C-5BG256E<br>~~Ge~~<br>~~ee~~|1300<br>~~Ge~~<br>~~ee~~|3.3<br>~~Ge~~<br>~~GO~~|5<br>~~Ge~~<br>~~GO~~<br>~~GO~~|Halogen-Free caBGA<br>~~Ge~~<br>~~GO~~<br>~~GO~~|256<br>~~Ge~~|AUTO<br>~~Ge~~|
|LAMXO3LF-2100E-5BG256E<br>~~ee~~<br>~~eG~~|2100<br>~~ee~~<br>~~eG~~|1.2<br>~~GO~~<br>~~eG~~<br>~~OG~~|5<br>~~GO~~<br>~~eG~~<br>~~GO~~<br>~~OG~~|Halogen-Free caBGA<br>~~GO~~<br>~~eG~~<br>~~GO~~|256<br>~~eG~~|AUTO<br>~~eG~~|
|LAMXO3LF-2100C-5BG256E<br>~~eG~~<br>~~ee~~|2100<br>~~eG~~<br>~~ee~~|3.3<br>~~eG~~<br>~~ee~~<br>~~OG~~|5<br>~~eG~~<br>~~GO~~<br>~~ee~~<br>~~OG~~<br>~~GO~~|Halogen-Free caBGA<br>~~eG~~<br>~~GO~~<br>~~ee~~|256<br>~~eG~~<br>~~ee~~|AUTO<br>~~eG~~<br>~~ee~~|
|LAMXO3LF-2100E-5BG324E<br>~~eG~~|2100<br>~~eG~~|1.2<br>~~OG~~<br>~~eG~~|5<br>~~OG~~<br>~~eG~~<br>~~GO~~|Halogen-Free caBGA<br>~~eG~~|324<br>~~eG~~|AUTO<br>~~eG~~|
|LAMXO3LF-2100C-5BG324E<br>~~ef~~|2100<br>~~ef~~|3.3<br>~~ef~~|5<br>~~GO~~<br>~~ef~~|Halogen-Free caBGA<br>~~ef~~|324<br>~~ef~~|AUTO<br>~~ef~~|
|LAMXO3LF-4300E-5BG256E<br>~~ef~~<br>~~ee~~|4300<br>~~ef~~<br>~~ee~~|1.2<br>~~ef~~<br>~~GO~~|5<br>~~ef~~<br>~~GO~~<br>~~GO~~|Halogen-Free caBGA<br>~~ef~~<br>~~GO~~<br>~~GO~~|256<br>~~ef~~|AUTO<br>~~ef~~|
|LAMXO3LF-4300C-5BG256E<br>~~ee~~<br>~~eG~~<br>~~po~~|4300<br>~~ee~~<br>~~eG~~|3.3<br>~~GO~~<br>~~eG~~<br>~~OG~~|5<br>~~GO~~<br>~~eG~~<br>~~GO~~<br>~~OG~~|Halogen-Free caBGA<br>~~GO~~<br>~~eG~~<br>~~GO~~|256<br>~~eG~~|AUTO<br>~~eG~~|
|LAMXO3LF-4300E-5BG324E<br>~~eG~~<br>~~ee~~<br>~~po~~|4300<br>~~eG~~<br>~~ee~~|1.2<br>~~eG~~<br>~~ee~~<br>~~OG~~|5<br>~~eG~~<br>~~GO~~<br>~~ee~~<br>~~OG~~|Halogen-Free caBGA<br>~~eG~~<br>~~GO~~<br>~~ee~~|324<br>~~eG~~<br>~~ee~~|AUTO<br>~~eG~~<br>~~ee~~|
|LAMXO3LF-4300C-5BG324E<br>~~po~~|4300|3.3<br>~~OG~~|5<br>~~OG~~|Halogen-Free caBGA|324|AUTO|



© 2014-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

88 

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## **References** 

A variety of technical notes for the MachXO3 family are available on the Lattice web site. 

- MachXO3 sysCLOCK PLL Design and Usage Guide (FPGA-TN-02058) 

- Implementing High-Speed Interfaces with MachXO3 Devices (FPGA-TN-02057) 

- MachXO3 sysI/O Usage Guide (FPGA-TN-02047) 

- MachXO3 Programming and Configuration Usage Guide (FPGA-TN-02055) 

- PCB Layout Recommendations for BGA Packages (FPGA-TN-02024) 

- Minimizing System Interruption During Configuration Using TransFR Technology (FPGA-TN-02025) 

- Boundary Scan Testability with Lattice sysI/O Capability (AN8066) 

- MachXO3 Device Pinout File 

- Thermal Management (FPGA-TN-02044) 

- Lattice Design Tools 

© 2014-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02032-2.8 

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## **Revision History** 

## **Revision 2.8, January 2021** 

|**Section**|**Change Summary**|
|---|---|
|Acronyms in This Document|Added items.|
|Introduction|<br>InFeaturessection:<br><br>Indicated 10,000 write/erase cycle for automotive.<br><br>Indicated on-chip oscillator with 5.5% accuracy is for commercial/industrial<br>devices.<br><br>UpdatedTable 1.1. MachXO3L/LF FamilySelection Guide.|
|Architecture|Indicated 10,000 write/erase cycle for automotive in theUser Flash Memory (UFM)section.|
|DC and Switching Characteristics|<br>Added automotive data inTable 3.4. Power-On Reset Voltage Levels.<br><br>Updated tRETENTIONvalues inTable 3.6. Programming/Erase Specifications.<br><br>Added automotive data and updated IPUvalues inTable 3.7. DC Electrical<br>Characteristics.<br><br>Added VINP, VINM, and VOSrows for automotive inTable 3.12. LVDS.<br><br>Added automotive data inTable 3.21. MachXO3L/LF External Switching Characteristics<br>– C/E Devices1,2, 3, 4, 5, 6, 10.<br><br>Indicated commercial/industrial and automotive data inTable 3.22. sysCLOCK PLL<br>Timing.<br><br>AddedOscillator Output Frequencysection.<br><br>Added automotive data inTable 3.25. JTAG Port Timing Specifications.<br><br>Added automotive data inTable 3.26. sysCONFIG Port TimingSpecifications.|
|MachXO3 Part Number<br>Description|Fixed error in device family names. Changed LCMXO3X and LAMXO3X to LCMXO3 and<br>LAMXO3 under Device Family.|
|Ordering Information|<br>Removed marking for LAMX3LF-13.<br><br>Updated theMachXO3LF Ultra Low Power Automotive Grade Devices, Halogen Free<br>(RoHS)Packagingsection.|



## **Revision 2.7, October 2020** 

|**Section**|**Change Summary**|
|---|---|
|Ordering Information|Updated the MachXO3LF Ultra Low Power Automotive Grade Devices, Halogen Free (RoHS)<br>Packagingsection.|



© 2014-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

90 

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## **Revision 2.6, September 2020** 

|**Section**|**Change Summary**|
|---|---|
|All|<br>Added automotive data.<br><br>Minor formattingchanges.|
|DC and Switching Characteristics|<br>Corrected footnotes in Table 3.6. Programming/Erase Specifications.<br><br>Added Automotive values to the following tables:<br><br>Table 3.3. Power Supply Ramp Rates<br><br>Table 3.4. Power-On Reset Voltage Levels<br><br>Table 3.6. Programming/Erase Specifications<br><br>Table 3.7. DC Electrical Characteristics<br><br>Table 3.21. MachXO3L/LF External Switching Characteristics – C/E Devices<br><br>Table 3.24. JTAG Port Timing Specifications<br><br>Table 3.25. sysCONFIG Port Timing Specifications<br><br>Updated TSUMin value for -5 Commercial/Industrial in Table 3.21. MachXO3L/LF<br>External Switching Characteristics – C/E Devices. Changes were applied under_Generic_<br>_DDRX1 Inputs with Clock and Data Centered at Pin Using PCLK Pin for Clock Input –_<br>_GDDRX1_RX.SCLK.Centered_and_Generic DDRX2 Inputs with Clock and Data Centered at_<br>_Pin Using PCLK Pinfor Clock Input – GDDRX2_RX.ECLK.Centered_.|



## **Revision 2.5, March 2020** 

|**Section**|**Change Summary**|
|---|---|
|Disclaimers|Added this section.|
|Architecture|<br>Added the MachXO3LF to MachXO3L Low Cost Migration Path section.<br><br>Removed lastparagraph from the Typical I/O Behavior duringPower-upsection.|
|DC and Switching Characteristics|<br>Added NVCM Programming cycles and Flash Feature Row Programming Cycles to Table<br>3.6.<br><br>Added clarification to "Blank Pattern" in footnote to Table 3.9.<br><br>Added footnote to clarifyVCCIO in Table 3.12.|
|Signal Descriptions|<br>Added rows and footnote to clarify configuration usage in Table 4.1 thru Table 4.6.<br><br>Added "Pin Summary" to table captions for clarity.|



## **Revision 2.4, February 2019** 

|**Section**|**Change Summary**|
|---|---|
|Architecture|Updated Figure 2.12. Output Register Block Diagram (PIO on the Left, Top and Bottom<br>Edges)caption.|



## **Revision 2.3, November 2018** 

|**Section**|**Change Summary**|
|---|---|
|Architecture|Clarified PCI support in the following sections and tables:<br><br>Programmable I/O Cells (PIC)Programmable I/O Cells (PIC)<br><br>sysI/O Buffer<br><br>Table 2.11. Supported Input Standards<br><br>Table 2.12. Supported Output Standards|
|References|Updated PCB Layout Recommendations for BGA Packages document number to FPGA-TN-<br>02024.|



© 2014-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02032-2.8 

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## **Revision 2.2, October 2018** 

|**Section**|**Change Summary**|
|---|---|
|Introduction|<br>Added Device Options to Table 1.1. MachXO3L/LF Family Selection Guide.<br><br>Updated footnotes.|
|Architecture|General update to Table 2.11. Supported Input Standards|
|Ordering Information|<br>Corrected BG256 packages for 1300 LUT parts.<br><br>Added information on dual markingfor MachXO3L WLCSpackages.|
|All|Minor formattingchanges.|



|**Revision 2.1, March 2018**|**Revision 2.1, March 2018**||
|---|---|---|
|**Section**<br>**Change Summary**<br>DC and Switching Characteristics<br>Removed extraneous TJAUTOspecification from Table 3.2 Recommended Operating<br>Conditions.<br>Ordering Information<br>Restored MachXO3LF Ultra Low Power Commercial and Industrial Grade Devices, Halogen<br>Free(RoHS)Packagingsection back to the OrderingInformation section.<br>Revision History<br>Restored Revision History contents for Revision 1.6 and prior back to this Revision History<br>section.<br>~~==~~|||
|**Revision 2.0, January 2018**|||
|**Section**<br>**Change Summary**<br>All<br><br>Applied new company template.<br><br>Changed document number fron DS1047 to FPGA-DS-02032.<br><br>Fixed various reference links.<br>DC and Switching Characteristics<br><br>Added Programming/Erase Specifications section. Clarified Write/Erase cycle.<br><br>Removed unnecessary C2 Dedicated Input Capacitance specification from the DC<br>Electrical Characteristics section.<br><br>Added note to the NVCM/Flash Download Time section to clarify maximum tREFRESH<br>time.<br>~~—~~|||
|**Revision 1.9, October 2017**|||
||**Section**|**Change Summary**|
||Introduction|<br>Updated Features section. Changed Advanced Packaging feature to “0.5 mm pitch: 640|
|||to 9.4K LUT densities....”|
|||<br>Updated Table 1.1, MachXO3L Family Selection Guide.|
|||<br>Added footnotes to MachXO3L-6900/MachXO3LF-6900 and MachXO3L-|
|||9400/MachXO3LF-9400 LUTs.|
|||<br>Added UFM (kbits, MachXO3LF only) feature.|
|||<br>Moved footnotes from packages to corresponding I/O values in 256- ball caBGA, 400-|
|||ball caBGA and 484-ball caBGA.|
|||<br>Updated footnote 2.|
|||<br>Added footnotes 3 and 4.|
||Architecture|<br>Updated User Flash Memory (UFM) section. Changed feature to “Non-volatile storage|
|||up to 448 kbits”.|
|||<br>Updated Standby Mode and Power Saving Options section. Updated the title of TN1289|
|||reference.|
||DC and Switching Characteristics|<br>Updated Absolute Maximum Ratings section. Added footnote 6.|
|||<br>Updated Static Supply Current – C/E Devices section.|
|||<br>Updated the title of TN1289 reference in footnote 1.|
|||<br>Removed footnote 7. Updated Programming and Erase Supply Current – C/E Devices|
|||section. Updated the title of TN1289 reference in footnote 1|



All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

© 2014-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. 

92 

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|**Section**|**Change Summary**|
|---|---|
|Ordering Information|<br>Updated the MachXO3L Ultra Low Power Commercial and Industrial Grade Devices,<br>Halogen Free (RoHS) Packaging section. Added MachXO3L-9600E part numbers.<br><br>Updated the MachXO3LF Ultra Low Power Commercial and Industrial Grade Devices,<br>Halogen Free(RoHS)Packagingsection. Added MachXO3LF-9600Epart numbers.|



## **Revision 1.8, February 2017** 

|**Section**|**Change Summary**|
|---|---|
|Architecture|<br>Updated Supported Standards section.<br><br>Corrected “MDVS” to “MLDVS” in Table 2.11, Supported Input Standards.|
|DC and Switching Characteristics|<br>Updated ESD Performance section. Added reference to the MachXO2 Product Family<br>Qualification Summary document.<br><br>Updated Static Supply Current – C/E Devices section. Added footnote 7.<br><br>Updated MachXO3L/LF External Switching Characteristics – C/E Devices section.<br><br>Populated values for MachXO3L/LF-9400.<br><br>Under 7:1 LVDS Outputs – GDDR71_TX.ECLK.7:1, corrected “tDVB” to “tDIB” and<br>“tDVA” to “tDIA” and revised their descriptions.<br><br>Added Figure 3-6, Receiver GDDR71_RX Waveforms and Figure 3-7, Transmitter<br>GDDR71_TX Waveforms.|
|Pinout Information|<br>Updated the Pin Information Summarysection. Added MachXO3L/LF- 9600Cpackages.|



## **Revision 1.7, May 2016** 

|**Section**|**Change Summary**|
|---|---|
|DC and Switching Characteristics|<br>Updated Absolute Maximum Ratings section. Modified I/O Tri-state Voltage Applied<br>and Dedicated Input Voltage Applied footnotes.<br><br>Updated sysI/O Recommended Operating Conditions section.<br><br>Added standards.<br><br>Added VREF (V)<br><br>Added footnote 4.<br><br>Updated sysI/O Single-Ended DC Electrical Characteristics section.<br><br>Added I/O standards.|
|Ordering Information|<br>Updated MachXO3L Ultra Low Power Commercial and Industrial Grade Devices,<br>Halogen Free (RoHS) Packaging section. Added LCMXO3L- 9400C part numbers.<br><br>Updated MachXO3LF Ultra Low Power Commercial and Industrial Grade Devices,<br>Halogen Free(RoHS)Packagingsection. Added LCMXO3L- 9400Cpart numbers.|



## **Revision 1.6, April 2016** 

|**Section**|**Change Summary**|
|---|---|
|Introduction|<br>Updated Features section.<br><br>Revised logic density range and I/O to LUT ratio under Flexible Architecture.<br><br>Revised 0.8 mm pitch information under Advanced Packaging.<br><br>Added MachXO3L-9400/MachXO3LF-9400 information to Table 1-1, MachXO3L/LF<br>Family Selection Guide.<br><br>Updated Introduction section.<br><br>Changed density from 6900 to 9400 LUTs.<br><br>Changed caBGA packaging to 19 x 19 mm.|



© 2014-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02032-2.8 

93 

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|**Section**|**Change Summary**|
|---|---|
|Architecture|<br>Updated Architecture Overview section.<br><br>Changed statement to “All logic density devices in this family...”<br><br>Updated Figure 2-2 heading and notes.<br><br>Updated sysCLOCK Phase Locked Loops (PLLs) section.<br><br>Changed statement to “All MachXO3L/LF devices have one or more sysCLOCK PLL.”<br><br>Updated Programmable I/O Cells (PIC) section.<br><br>Changed statement to “All PIO pairs can implement differential receivers.”<br><br>Updated sysI/O Buffer Banks section. Updated Figure 2-5 heading.<br><br>Updated Device Configuration section. Added Password and Soft Error Correction.|
|DC and Switching Characteristics|<br>Updated Static Supply Current – C/E Devices section. Added LCMXO3L/LF-9400C and<br>LCMXO3L/LF-9400E devices.<br><br>Updated Programming and Erase Supply Current – C/E Devices section.<br><br>Added LCMXO3L/LF-9400C and LCMXO3L/LF-9400E devices.<br><br>Changed LCMXO3L/LF-640E and LCMXO3L/LF-1300E Typ. values.<br><br>Updated MachXO3L/LF External Switching Characteristics – C/E Devices section. Added<br>MachXO3L/LF-9400 devices.<br><br>Updated NVCM/Flash Download Time section. Added LCMXO3L/LF-9400C device.<br><br>Updated sysCONFIG Port Timing Specifications section.<br><br>Added LCMXO3L/LF-9400C device.<br><br>Changed tINITL units to from ns to us.<br><br>Changed tDPPINIT and tDPPDONE Max. values areper PCN#03A-16.|
|Pinout Information|Updated Pin Information Summarysection. Added LCMXO3L/LF-9400C device.|
|Ordering Information|<br>Updated MachXO3 Part Number Description section.<br><br>Added 9400 = 9400 LUTs.<br><br>Added BG484 package.<br><br>Updated MachXO3L Ultra Low Power Commercial and Industrial Grade Devices,<br>Halogen Free (RoHS) Packaging section. Added LCMXO3L-9400C part numbers.<br><br>Updated MachXO3LF Ultra Low Power Commercial and Industrial Grade Devices,<br>Halogen Free(RoHS)Packagingsection. Added LCMXO3L-9400Cpart numbers.|



## **Revision 1.5, September 2015** 

|**Section**|**Change Summary**|
|---|---|
|DC and Switching Characteristics|<br>Updated the MIPI D-PHY Emulation section. Revised Table 3-5, MIPI DPHY Output DC<br>Conditions.<br><br>Revised RL Typ. value.<br><br>Revised RH description and values.<br><br>Updated the Maximum sysI/O Buffer Performance section. Revised MIPI Max. Speed<br>value.<br><br>Updated the MachXO3L/LF External Switching Characteristics – C/E Devices section.<br>Added footnotes 14 and 15.|



## **Revision 1.4, August 2015** 

|**Section**|**Change Summary**|
|---|---|
|Architecture|Updated the Device Configuration section. Added JTAGENB to TAP dual purpose pins.|
|Ordering Information|Updated the top side markings section to indicate the use of LMXO3LF for the LCMXO3LF<br>device.|



© 2014-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

94 

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## **Revision 1.3, March 2015** 

|**Section**|**Change Summary**|
|---|---|
|All|General update. Added MachXO3LF devices.|



## **Revision 1.2, August 2015** 

|**Section**|**Change Summary**|
|---|---|
|Introduction|Updated Table 1-1, MachXO3L Family Selection Guide. Revised XO3L-2100 and XO3L-4300<br>I/O for 324-ball csfBGApackage.|
|Architecture|Updated the Dual Boot section. Corrected information on where the primary bitstream and<br>thegolden image must reside.|
|DC and Switching Characteristics|<br>Updated the BLVDS section. Changed output impedance nominal values in Table 3-2,<br>BLVDS DC Condition.<br><br>Updated the LVPECL section. Changed output impedance nominal value in Table 3-3,<br>LVPECL DC Condition.<br><br>Updated the sysCONFIG Port Timing Specifications section. Updated INITN low time<br>values.|
|Pinout Information|<br>Changed General Purpose I/O Bank 5 values for MachXO3L-2100 and MachXO3L-4300<br>CSFBGA 324 package.<br><br>Changed Number 7:1 or 8:1 Gearboxes for MachXO3L-640 and MachXO3L-1300.<br><br>Removed DQS Groups (Bank 1) section.<br><br>Changed VCCIO Pins Bank 1 values for MachXO3L-1300, MachXO3L-2100, MachXO3L-<br>4300 and MachXO3L-6900 CSFBGA 256 package.<br><br>Changed GND values for MachXO3L-1300, MachXO3L-2100, MachXO3L-4300 and<br>MachXO3L-6900 CSFBGA 256 package.<br><br>Changed NC values for MachXO3L-2100 and MachXO3L-4300 CSFBGA 324package.|



## **Revision 1.1, July 2014** 

|**Section**|**Change Summary**|
|---|---|
|DC and Switching Characteristics|<br>Updated the Static Supply Current – C/E Devices section. Added devices.<br><br>Updated the Programming and Erase Supply Current – C/E Device section. Added<br>devices.<br><br>Updated the sysI/O Single-Ended DC Electrical Characteristics section. Revised footnote<br>4.<br><br>Added the NVCM Download Time section.<br><br>Updated the Typical Building Block Function Performance – C/E Devices section. Added<br>information to footnote.|
|Pinout Information|Updated the Pin Information Summary section.|
|Ordering Information|<br>Updated the MachXO3L Part Number Description section. Added packages.<br><br>Updated the Ordering Information section. General update.|



© 2014-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02032-2.8 

95 

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## **Revision 1.0, June 2014** 

|**Section**|**Change Summary**|
|---|---|
|Introduction|<br>Updated Features section.<br><br>Updated Table 1-1, MachXO3L Family Selection Guide. Changed fcCSP packages to<br>csfBGA. Adjusted 121-ball csfBGA arrow.<br><br>Introduction sectiongeneral update.|
|Architecture|General update.|
|DC and Switching Characteristics|<br>Updated sysI/O Recommended Operating Conditions section. Removed VREF (V)<br>column. Added standards.<br><br>Updated Maximum sysI/O Buffer Performance section. Added MIPI I/O standard.<br><br>Updated MIPI D-PHY Emulation section. Changed Low Speed to Low Power. Updated<br>Table 3-4, MIPI DC Conditions.<br><br>Updated Table 3-5, MIPI D-PHY Output DC Conditions.<br><br>Updated Maximum sysI/O Buffer Performance section.<br><br>Updated MachXO3L External SwitchingCharacteristics – C/E Device section.|



## **Revision 00.3, May 2014** 

|**Section**|**Change Summary**|
|---|---|
|Introduction|<br>Updated Features section.<br><br>Updated Table 1-1, MachXO3L Family Selection Guide. Moved 121-ball fcCSP arrow.<br><br>General update of Introduction section.|
|Architecture|General update.|
|Pinout Information|Updated Pin Information Summary section. Updated or added data on WLCSP49, WLCSP81,<br>CABGA324, and CABGA400 for specific devices.|
|Ordering Information|<br>Updated MachXO3L Part Number Description section. Updated or added data on<br>WLCSP49, WLCSP81, CABGA324, and CABGA400 for specific devices.<br><br>Updated Ultra Low Power Commercial and Industrial Grade Devices, Halogen Free<br>(RoHS) Packaging section. Added part numbers.<br><br>Revision 00.2, February 2014<br><br>DC and Switching Characteristics section:<br><br>Updated MachXO3L External Switching Characteristics – C/E Devices table. Removed<br>LPDDR and DDR2parameters.|



## **Revision 00.2, February 2014** 

|**Section**|**Change Summary**|
|---|---|
|DC and Switching Characteristics|Updated MachXO3L External Switching Characteristics – C/E Devices table. Removed LPDDR|
||and DDR2parameters.|
|**Revision 00.1, February 2014**||
|**Section**|**Change Summary**|
|All|Initial release.|



## **Revision 00.1, February 2014** 

© 2014-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

96 

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