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LCMXO2-4000HC-6FTG256I
FPGA, Flash, 65nm, 206 I/O's, 4320 Logic Cells, FTBGA-256
⚠️ Reference pricing provided. In case of supply shortages, we will connect you with our trusted procurement partners to ensure your project's continuity.
- Manufacturer: LATTICE SEMICONDUCTOR
- Product type: FPGAs
- SVHC: No SVHC (25-Jun-2025)
- FPGA Type: Flash based FPGA
- IC Mounting: Surface Mount
- No. of Pins: 256Pins
- Speed Grade: 6
- Product Range: -
- Qualification: -
- No.of User I/Os: 206I/O's
- IC Case / Package: FTBGA
- No. of Logic Cells: 4320Logic Cells
- Process Technology: 65nm
- Operating Temperature Max: 100°C
- Operating Temperature Min: -40°C
| Delivery and price | |
|---|---|
| Units per pack | 50 |
| Price | 24.99 € |
| Current stock | 50+ |
| Lead time | 30 days |
Datasheet
ili 7s
## **MachXO2 Family Data Sheet**
## **Data Sheet**
FPGA-DS-02056-4.3
November 2023
**MachXO2 Family Data Sheet Data Sheet**
## **Disclaimers**
Lattice makes no warranty, representation, or guarantee regarding the accuracy of information contained in this document or the suitability of its products for any particular purpose. All information herein is provided AS IS, with all faults, and all associated risk is the responsibility entirely of the Buyer. The information provided herein is for informational purposes only and may contain technical inaccuracies or omissions, and may be otherwise rendered inaccurate for many reasons, and Lattice assumes no obligation to update or otherwise correct or revise this information. Products sold by Lattice have been subject to limited testing and it is the Buyer's responsibility to independently determine the suitability of any products and to test and verify the same. LATTICE PRODUCTS AND SERVICES ARE NOT DESIGNED, MANUFACTURED, OR TESTED FOR USE IN LIFE OR SAFETY CRITICAL SYSTEMS, HAZARDOUS ENVIRONMENTS, OR ANY OTHER ENVIRONMENTS REQUIRING FAIL-SAFE PERFORMANCE, INCLUDING ANY APPLICATION IN WHICH THE FAILURE OF THE PRODUCT OR SERVICE COULD LEAD TO DEATH, PERSONAL INJURY, SEVERE PROPERTY DAMAGE OR ENVIRONMENTAL HARM (COLLECTIVELY, "HIGH-RISK USES"). FURTHER, BUYER MUST TAKE PRUDENT STEPS TO PROTECT AGAINST PRODUCT AND SERVICE FAILURES, INCLUDING PROVIDING APPROPRIATE REDUDANCIES, FAIL-SAFE FEATURES, AND/OR SHUT-DOWN MECHANISMS. LATTICE EXPRESSLY DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY OF FITNESS OF THE PRODUCTS OR SERVICES FOR HIGH-RISK USES. The information provided in this document is proprietary to Lattice Semiconductor, and Lattice reserves the right to make any changes to the information in this document or to any products at any time without notice.
© 2010-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
2
FPGA-DS-02056-4.3
**MachXO2 Family Data Sheet Data Sheet**
## **Contents**
|**Contents**|**Contents**|**Contents**|
|---|---|---|
|Contents ............................................................................................................................................................................... 2|||
|Acronyms in This Document ................................................................................................................................................. 9|||
|1.|Introduction ................................................................................................................................................................ 10||
||1.1.|Features ............................................................................................................................................................ 11|
|||1.1.1. Flexible Logic Architecture ....................................................................................................................... 11|
|||1.1.2. Ultra Low Power Devices .......................................................................................................................... 11|
|||1.1.3. Embedded and Distributed Memory ........................................................................................................ 11|
|||1.1.4. On-Chip User Flash Memory .................................................................................................................... 11|
|||1.1.5. Pre-Engineered Source Synchronous I/O ................................................................................................. 11|
|||1.1.6. High Performance, Flexible I/O Buffer ..................................................................................................... 11|
|||1.1.7. Flexible On-Chip Clocking ......................................................................................................................... 11|
|||1.1.8. Non-volatile, Infinitely Reconfigurable ..................................................................................................... 11|
|||1.1.9. TransFR™ Reconfiguration ....................................................................................................................... 11|
|||1.1.10. Enhanced System Level Support .............................................................................................................. 11|
|||1.1.11. Broad Range of Package Options ............................................................................................................. 11|
|||1.1.12. Application ............................................................................................................................................... 11|
|2.|Architecture ................................................................................................................................................................ 14||
||2.1.|Architecture Overview ...................................................................................................................................... 14|
||2.2.|PFU Blocks ......................................................................................................................................................... 15|
|||2.2.1. Slices ......................................................................................................................................................... 16|
|||2.2.2. Modes of Operation ................................................................................................................................. 17|
|||2.2.3. RAM Mode ............................................................................................................................................... 18|
|||2.2.4. ROM Mode ............................................................................................................................................... 18|
||2.3.|Routing .............................................................................................................................................................. 18|
||2.4.|Clock/Control Distribution Network ................................................................................................................. 18|
|||2.4.1. sysCLOCK Phase Locked Loops (PLLs) ....................................................................................................... 20|
||2.5.|sysMEM Embedded Block RAM Memory ......................................................................................................... 23|
||2.6.|Programmable I/O Cells (PIC) ........................................................................................................................... 26|
||2.7.|PIO .................................................................................................................................................................... 28|
|||2.7.1. Input Register Block .................................................................................................................................. 28|
|||2.7.2. Output Register Block ............................................................................................................................... 30|
|||2.7.3. Tri-state Register Block ............................................................................................................................. 31|
||2.8.|Input Gearbox ................................................................................................................................................... 31|
||2.9.|Output Gearbox ................................................................................................................................................ 33|
||2.10. DDR Memory Support ....................................................................................................................................... 35||
||2.11. DQS Read Write Block ....................................................................................................................................... 35||
||2.12. sysI/O Buffer ..................................................................................................................................................... 35||
|||2.12.1. Typical I/O Behavior During Power-up ..................................................................................................... 36|
|||2.12.2. Supported Standards ................................................................................................................................ 36|
|||2.12.3. sysI/O Buffer Banks .................................................................................................................................. 39|
||2.13. Hot Socketing .................................................................................................................................................... 40||
||2.14. On-chip Oscillator ............................................................................................................................................. 40||
||2.15. Embedded Hardened IP Functions and User Flash Memory ............................................................................ 41||
|||2.15.1. Hardened I2C IP Core ................................................................................................................................ 41|
|||2.15.2. Hardened SPI IP Core ................................................................................................................................ 42|
|||2.15.3. Hardened Timer/Counter ......................................................................................................................... 43|
||2.16. User Flash Memory (UFM) ................................................................................................................................ 44||
||2.17. Standby Mode and Power Saving Options........................................................................................................ 45||
||2.18. Power-On-Reset ................................................................................................................................................ 46||
||2.19. Configuration and Testing................................................................................................................................. 46||
|||2.19.1. IEEE 1149.1-Compliant Boundary Scan Testability ................................................................................... 46|
|||2.19.2. Device Configuration ................................................................................................................................ 47|
© 2010-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02056-4.3
3
**MachXO2 Family Data Sheet Data Sheet**
||2.20. TraceID .............................................................................................................................................................. 48|
|---|---|
||2.21. Density Shifting ................................................................................................................................................. 48|
|3.|DC and Switching Characteristics ................................................................................................................................ 49|
||3.1.<br>Absolute Maximum Ratings .............................................................................................................................. 49|
||3.2.<br>Recommended Operating Conditions ............................................................................................................... 49|
||3.3.<br>Power Supply Ramp Rates ................................................................................................................................ 49|
||3.4.<br>Power-On-Reset Voltage Levels ........................................................................................................................ 50|
||3.5.<br>Programming/Erase Specifications ................................................................................................................... 50|
||3.6.<br>Hot Socketing Specifications ............................................................................................................................. 50|
||3.7.<br>ESD Performance .............................................................................................................................................. 51|
||3.8.<br>DC Electrical Characteristics .............................................................................................................................. 51|
||3.9.<br>Static Supply Current – ZE Devices .................................................................................................................... 52|
||3.10. Static Power Consumption Contribution of Different Components – ZE Devices ............................................ 52|
||3.11. Static Supply Current – HC/HE Devices ............................................................................................................. 52|
||3.12. Programming and Erase Flash Supply Current – HC/HE Devices ...................................................................... 53|
||3.13. Programming and Erase Flash Supply Current – ZE Devices ............................................................................. 53|
||3.14. sysI/O Recommended Operating Conditions .................................................................................................... 54|
||3.15. sysI/O Single-Ended DC Electrical Characteristics ............................................................................................. 55|
||3.16. sysI/O Differential Electrical Characteristics ..................................................................................................... 56|
||3.16.1. LVDS .......................................................................................................................................................... 56|
||3.16.2. LVDS Emulation ........................................................................................................................................ 57|
||3.16.3. BLVDS ........................................................................................................................................................ 58|
||3.16.4. LVPECL ...................................................................................................................................................... 59|
||3.16.5. RSDS .......................................................................................................................................................... 60|
||3.17. Typical Building Block Function Performance – HC/HE Devices ....................................................................... 61|
||3.17.1. Pin-to-Pin Performance (LVCMOS25 12 mA Drive) .................................................................................. 61|
||3.17.2. Register-to-Register Performance ............................................................................................................ 61|
||3.18. Typical Building Block Function Performance – ZE Devices .............................................................................. 62|
||3.18.1. Pin-to-Pin Performance (LVCMOS25 12 mA Drive) .................................................................................. 62|
||3.18.2. Register-to-Register Performance ............................................................................................................ 62|
||3.19. Derating Logic Timing ....................................................................................................................................... 62|
||3.20. Maximum sysI/O Buffer Performance .............................................................................................................. 63|
||3.21. MachXO2 External Switching Characteristics – HC/HE Devices ........................................................................ 64|
||3.22. MachXO2 External Switching Characteristics – ZE Devices............................................................................... 69|
||3.23. sysCLOCK PLL Timing ......................................................................................................................................... 78|
||3.24. MachXO2 Oscillator Output Frequency ............................................................................................................ 79|
||3.25. MachXO2 Standby Mode Timing – HC/HE Devices ........................................................................................... 79|
||3.26. MachXO2 Standby Mode Timing – ZE Devices ................................................................................................. 80|
||3.27. Flash Download Time ........................................................................................................................................ 80|
||3.28. JTAG Port Timing Specifications ........................................................................................................................ 81|
||3.29. sysCONFIG Port Timing Specifications .............................................................................................................. 82|
||3.30. I2C Port Timing Specifications ........................................................................................................................... 83|
||3.31. SPI Port Timing Specifications ........................................................................................................................... 83|
||3.32. Switching Test Conditions ................................................................................................................................. 83|
|4.|Pinout Information ..................................................................................................................................................... 85|
||4.1.<br>Signal Descriptions ............................................................................................................................................ 85|
||4.2.<br>Pinout Information Summary ........................................................................................................................... 87|
||4.3.<br>For Further Information .................................................................................................................................... 92|
||4.4.<br>Thermal Management ...................................................................................................................................... 92|
||4.4.1. For Further Information ........................................................................................................................... 92|
|5.|Ordering Information .................................................................................................................................................. 93|
||5.1.<br>MachXO2 Part Number Description ................................................................................................................. 93|
||5.2.<br>Ordering Information ........................................................................................................................................ 94|
||5.2.1. Ultra Low Power Commercial Grade Devices, Halogen Free (RoHS) Packaging ....................................... 94|
© 2010-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02056-4.3
4
**MachXO2 Family Data Sheet Data Sheet**
|||5.2.2. High-Performance Commercial Grade Devices with Voltage Regulator, Halogen Free (RoHS) Packaging|
|---|---|---|
|||............................................................................................................................................................... 96|
|||5.2.3. High-Performance Commercial Grade Devices without Voltage Regulator, Halogen Free (RoHS)|
|||Packaging ............................................................................................................................................. 100|
|||5.2.4. Ultra Low Power Industrial Grade Devices, Halogen Free (RoHS) Packaging ......................................... 101|
|||5.2.5. High-Performance Industrial Grade Devices with Voltage Regulator, Halogen Free (RoHS) Packaging 104|
|||5.2.6. High Performance Industrial Grade Devices Without Voltage Regulator, Halogen Free (RoHS) Packaging|
|||............................................................................................................................................................. 107|
|||5.2.7. High Performance Automotive Grade Devices Halogen Free (RoHS) Packaging .................................... 109|
||5.3.|R1 Device Specifications ................................................................................................................................. 110|
|6.|Supplemental Information ....................................................................................................................................... 111||
|Technical Support Assistance ........................................................................................................................................... 112|||
|Revision History ................................................................................................................................................................ 113||Revision History ................................................................................................................................................................ 113|
© 2010-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02056-4.3
5
**MachXO2 Family Data Sheet Data Sheet**
## **Figures**
|Figure 2.1. Top View of the MachXO2-1200 Device ........................................................................................................... 14|Figure 2.1. Top View of the MachXO2-1200 Device ........................................................................................................... 14|
|---|---|
|Figure 2.2. Top View of the MachXO2-4000 Device ........................................................................................................... 14|Figure 2.2. Top View of the MachXO2-4000 Device ........................................................................................................... 14|
|Figure 2.3. PFU Block Diagram ............................................................................................................................................ 15|Figure 2.3. PFU Block Diagram ............................................................................................................................................ 15|
|Figure 2.4. Slice Diagram .................................................................................................................................................... 16|Figure 2.4. Slice Diagram .................................................................................................................................................... 16|
|Figure 2.5. Primary Clocks for MachXO2 Devices ............................................................................................................... 19|Figure 2.5. Primary Clocks for MachXO2 Devices ............................................................................................................... 19|
|Figure 2.6. Secondary High Fanout Nets for MachXO2 Devices ......................................................................................... 20|Figure 2.6. Secondary High Fanout Nets for MachXO2 Devices ......................................................................................... 20|
|Figure 2.7. PLL Diagram ...................................................................................................................................................... 21|Figure 2.7. PLL Diagram ...................................................................................................................................................... 21|
|Figure 2.8. sysMEM Memory Primitives ............................................................................................................................. 24|Figure 2.8. sysMEM Memory Primitives ............................................................................................................................. 24|
|Figure 2.9. Memory Core Reset .......................................................................................................................................... 25|Figure 2.9. Memory Core Reset .......................................................................................................................................... 25|
|Figure 2.10. EBR Asynchronous Reset (Including GSR) Timing Diagram ............................................................................. 26|Figure 2.10. EBR Asynchronous Reset (Including GSR) Timing Diagram ............................................................................. 26|
|Figure 2.11. Group of Four Programmable I/O Cells .......................................................................................................... 27|Figure 2.11. Group of Four Programmable I/O Cells .......................................................................................................... 27|
|Figure 2.12. MachXO2 Input Register Block Diagram (PIO on Left, Top and Bottom Edges) ............................................. 29|Figure 2.12. MachXO2 Input Register Block Diagram (PIO on Left, Top and Bottom Edges) ............................................. 29|
|Figure 2.13. MachXO2 Input Register Block Diagram (PIO on Right Edge) ......................................................................... 29|Figure 2.13. MachXO2 Input Register Block Diagram (PIO on Right Edge) ......................................................................... 29|
|Figure 2.14. MachXO2 Output Register Block Diagram (PIO on the Left, Top and Bottom Edges) .................................... 30|Figure 2.14. MachXO2 Output Register Block Diagram (PIO on the Left, Top and Bottom Edges) .................................... 30|
|Figure 2.15. MachXO2 Output Register Block Diagram (PIO on the Right Edges) .............................................................. 31|Figure 2.15. MachXO2 Output Register Block Diagram (PIO on the Right Edges) .............................................................. 31|
|Figure 2.16. Input Gearbox ................................................................................................................................................. 32|Figure 2.16. Input Gearbox ................................................................................................................................................. 32|
|Figure 2.17. Output Gearbox .............................................................................................................................................. 34|Figure 2.17. Output Gearbox .............................................................................................................................................. 34|
|Figure 2.18. MachXO2-1200U, MachXO2-2000/U, MachXO2-4000 and MachXO2-7000 Banks........................................ 39|Figure 2.18. MachXO2-1200U, MachXO2-2000/U, MachXO2-4000 and MachXO2-7000 Banks........................................ 39|
|Figure 2.19. MachXO2-256, MachXO2-640/U and MachXO2-1200 Banks ......................................................................... 39|Figure 2.19. MachXO2-256, MachXO2-640/U and MachXO2-1200 Banks ......................................................................... 39|
|Figure 2.20. MachXO2-256, MachXO2-640/U and MachXO2-1200 Banks ......................................................................... 41|Figure 2.20. MachXO2-256, MachXO2-640/U and MachXO2-1200 Banks ......................................................................... 41|
|Figure 2.21. I|Figure 2.21. I2C Core Block Diagram ................................................................................................................................... 42|
|Figure 2.22. SPI Core Block Diagram ................................................................................................................................... 43|Figure 2.22. SPI Core Block Diagram ................................................................................................................................... 43|
|Figure 2.23. Timer/Counter Block Diagram ........................................................................................................................ 44|Figure 2.23. Timer/Counter Block Diagram ........................................................................................................................ 44|
|Figure 3.1. LVDS Using External Resistors (LVDS25E) ......................................................................................................... 57|Figure 3.1. LVDS Using External Resistors (LVDS25E) ......................................................................................................... 57|
|Figure 3.2. BLVDS Multi-point Output Example .................................................................................................................. 58|Figure 3.2. BLVDS Multi-point Output Example .................................................................................................................. 58|
|Figure 3.3. Differential LVPECL ........................................................................................................................................... 59|Figure 3.3. Differential LVPECL ........................................................................................................................................... 59|
|Figure 3.4. RSDS (Reduced Swing Differential Standard) .................................................................................................... 60|Figure 3.4. RSDS (Reduced Swing Differential Standard) .................................................................................................... 60|
|Figure 3.5. Receiver RX.CLK.Aligned and MEM DDR Input Waveforms .............................................................................. 75|Figure 3.5. Receiver RX.CLK.Aligned and MEM DDR Input Waveforms .............................................................................. 75|
|Figure 3.6. Receiver RX.CLK.Centered Waveforms ............................................................................................................. 76|Figure 3.6. Receiver RX.CLK.Centered Waveforms ............................................................................................................. 76|
|Figure 3.7. Transmitter TX.CLK.Aligned Waveforms ........................................................................................................... 76|Figure 3.7. Transmitter TX.CLK.Aligned Waveforms ........................................................................................................... 76|
|Figure 3.8. Transmitter TX.CLK.Centered and MEM DDR Output Waveforms ................................................................... 76|Figure 3.8. Transmitter TX.CLK.Centered and MEM DDR Output Waveforms ................................................................... 76|
|Figure 3.9. GDDR71 Video Timing Waveforms ................................................................................................................... 77|Figure 3.9. GDDR71 Video Timing Waveforms ................................................................................................................... 77|
|Figure 3.10. Receiver GDDR71_RX. Waveforms ................................................................................................................. 77|Figure 3.10. Receiver GDDR71_RX. Waveforms ................................................................................................................. 77|
|Figure 3.11. Transmitter GDDR71_TX. Waveforms ............................................................................................................ 77|Figure 3.11. Transmitter GDDR71_TX. Waveforms ............................................................................................................ 77|
|Figure 3.12. JTAG Port Timing Waveforms ......................................................................................................................... 81|Figure 3.12. JTAG Port Timing Waveforms ......................................................................................................................... 81|
|Figure 3.13. Output Test Load, LVTTL and LVCMOS Standards .......................................................................................... 83|Figure 3.13. Output Test Load, LVTTL and LVCMOS Standards .......................................................................................... 83|
|Figure 5.1. MachXO2 Part Number Description ................................................................................................................. 93|Figure 5.1. MachXO2 Part Number Description ................................................................................................................. 93|
© 2010-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02056-4.3
6
**MachXO2 Family Data Sheet Data Sheet**
## **Tables**
|Table 1.1. MachXO2 Family Selection Guide ...................................................................................................................... 12|Table 1.1. MachXO2 Family Selection Guide ...................................................................................................................... 12|
|---|---|
|Table 2.1. Resources and Modes Available per Slice .......................................................................................................... 16|Table 2.1. Resources and Modes Available per Slice .......................................................................................................... 16|
|Table 2.2. Slice Signal Descriptions ..................................................................................................................................... 17|Table 2.2. Slice Signal Descriptions ..................................................................................................................................... 17|
|Table 2.3. Number of Slices Required For Implementing Distributed RAM|Table 2.3. Number of Slices Required For Implementing Distributed RAM1...................................................................... 18|
|Table 2.4. PLL Signal Descriptions ....................................................................................................................................... 22|Table 2.4. PLL Signal Descriptions ....................................................................................................................................... 22|
|Table 2.5. sysMEM Block Configurations ............................................................................................................................ 23|Table 2.5. sysMEM Block Configurations ............................................................................................................................ 23|
|Table 2.6. EBR Signal Descriptions ...................................................................................................................................... 24|Table 2.6. EBR Signal Descriptions ...................................................................................................................................... 24|
|Table 2.7. Programmable FIFO Flag Ranges|Table 2.7. Programmable FIFO Flag Ranges1...................................................................................................................... 25|
|Table 2.8. PIO Signal List|Table 2.8. PIO Signal List1.................................................................................................................................................... 28|
|Table 2.9. Input Gearbox Signal List ................................................................................................................................... 31|Table 2.9. Input Gearbox Signal List ................................................................................................................................... 31|
|Table 2.10. Output Gearbox Signal List .............................................................................................................................. 33|Table 2.10. Output Gearbox Signal List .............................................................................................................................. 33|
|Table 2.11. I/O Support Device by Device .......................................................................................................................... 37|Table 2.11. I/O Support Device by Device .......................................................................................................................... 37|
|Table 2.12. Supported Input Standards .............................................................................................................................. 37|Table 2.12. Supported Input Standards .............................................................................................................................. 37|
|Table 2.13. Supported Output Standards ........................................................................................................................... 38|Table 2.13. Supported Output Standards ........................................................................................................................... 38|
|Table 2.14. Available MCLK Frequencies ............................................................................................................................ 40|Table 2.14. Available MCLK Frequencies ............................................................................................................................ 40|
|Table 2.15. Supported Input Standards .............................................................................................................................. 42|Table 2.15. Supported Input Standards .............................................................................................................................. 42|
|Table 2.16. SPI Core Signal Description .............................................................................................................................. 43|Table 2.16. SPI Core Signal Description .............................................................................................................................. 43|
|Table 2.17. Timer/Counter Signal Description .................................................................................................................... 44|Table 2.17. Timer/Counter Signal Description .................................................................................................................... 44|
|Table 2.18. MachXO2 Power Saving Features Description ................................................................................................. 45|Table 2.18. MachXO2 Power Saving Features Description ................................................................................................. 45|
|Table 3.1. Absolute Maximum Ratings|Table 3.1. Absolute Maximum Ratings1, 2, 3......................................................................................................................... 49|
|Table 3.2. Recommended Operating Conditions|Table 3.2. Recommended Operating Conditions1.............................................................................................................. 49|
|Table 3.3. Power Supply Ramp Rates|Table 3.3. Power Supply Ramp Rates1................................................................................................................................ 49|
|Table 3.4. Power Supply Ramp Rates|Table 3.4. Power Supply Ramp Rates1, 2, 3, 4, 5, 6................................................................................................................... 50|
|Table 3.5. Programming/Erase Specifications .................................................................................................................... 50|Table 3.5. Programming/Erase Specifications .................................................................................................................... 50|
|Table 3.6. Hot Socketing Specifications|Table 3.6. Hot Socketing Specifications1, 2, 3........................................................................................................................ 50|
|Table 3.7. DC Electrical Characteristics ............................................................................................................................... 51|Table 3.7. DC Electrical Characteristics ............................................................................................................................... 51|
|Table 3.8. Static Supply Current – ZE Devices|Table 3.8. Static Supply Current – ZE Devices1, 2, 3, 6............................................................................................................ 52|
|Table 3.9. Static Power Consumption Contribution of Different Components – ZE Devices ............................................. 52|Table 3.9. Static Power Consumption Contribution of Different Components – ZE Devices ............................................. 52|
|Table 3.10. Static Supply Current – HC/HE Devices|Table 3.10. Static Supply Current – HC/HE Devices1, 2, 3, 6................................................................................................... 52|
|Table 3.11. Programming and Erase Flash Supply Current – HC/HE Devices|Table 3.11. Programming and Erase Flash Supply Current – HC/HE Devices1, 2, 3, 4............................................................ 53|
|Table 3.12. Programming and Erase Flash Supply Current – ZE Devices|Table 3.12. Programming and Erase Flash Supply Current – ZE Devices1, 2, 3, 4................................................................... 53|
|Table 3.13. sysI/O Recommended Operating Conditions ................................................................................................... 54|Table 3.13. sysI/O Recommended Operating Conditions ................................................................................................... 54|
|Table 3.14. sysI/O Single-Ended DC Electrical Characteristics|Table 3.14. sysI/O Single-Ended DC Electrical Characteristics1, 2........................................................................................ 55|
|Table 3.15. LVDS ................................................................................................................................................................. 56|Table 3.15. LVDS ................................................................................................................................................................. 56|
|Table 3.16. LVDS25E DC Conditions .................................................................................................................................... 57|Table 3.16. LVDS25E DC Conditions .................................................................................................................................... 57|
|Table 3.17. LVDS25E DC Conditions .................................................................................................................................... 57|Table 3.17. LVDS25E DC Conditions .................................................................................................................................... 57|
|Table 3.18. BLVDS DC Conditions|Table 3.18. BLVDS DC Conditions1...................................................................................................................................... 58|
|Table 3.19. LVPECL DC Conditions|Table 3.19. LVPECL DC Conditions1..................................................................................................................................... 59|
|Table 3.20. RSDS DC Conditions ......................................................................................................................................... 60|Table 3.20. RSDS DC Conditions ......................................................................................................................................... 60|
|Table 3.21. Pin-to-Pin Performance (LVCMOS25 12 mA Drive) .......................................................................................... 61|Table 3.21. Pin-to-Pin Performance (LVCMOS25 12 mA Drive) .......................................................................................... 61|
|Table 3.22. Register-to-Register Performance|Table 3.22. Register-to-Register Performance1.................................................................................................................. 61|
|Table 3.23. Pin-to-Pin Performance (LVCMOS25 12 mA Drive) .......................................................................................... 62|Table 3.23. Pin-to-Pin Performance (LVCMOS25 12 mA Drive) .......................................................................................... 62|
|Table 3.24. Register-to-Register Performance|Table 3.24. Register-to-Register Performance1.................................................................................................................. 62|
|Table 3.25. Maximum sysI/O Buffer Performance ............................................................................................................. 63|Table 3.25. Maximum sysI/O Buffer Performance ............................................................................................................. 63|
|Table 3.26. MachXO2 External Switching Characteristics – HC/HE Devices|Table 3.26. MachXO2 External Switching Characteristics – HC/HE Devices1, 2, 3, 4, 5, 6, 7...................................................... 64|
|Table 3.27. MachXO2 External Switching Characteristics – ZE Devices|Table 3.27. MachXO2 External Switching Characteristics – ZE Devices1, 2, 3, 4, 5, 6, 7............................................................. 70|
|Table 3.28. sysCLOCK PLL Timing ........................................................................................................................................ 78|Table 3.28. sysCLOCK PLL Timing ........................................................................................................................................ 78|
|Table 3.29. MachXO2 Oscillator Output Frequency|Table 3.29. MachXO2 Oscillator Output Frequency1.......................................................................................................... 79|
|Table 3.30. MachXO2 Standby Mode Timing – HC/HE Devices .......................................................................................... 79|Table 3.30. MachXO2 Standby Mode Timing – HC/HE Devices .......................................................................................... 79|
|Table 3.31. MachXO2 Standby Mode Timing – ZE Devices ................................................................................................. 80|Table 3.31. MachXO2 Standby Mode Timing – ZE Devices ................................................................................................. 80|
|Table 3.32. Flash Download Time ....................................................................................................................................... 80|Table 3.32. Flash Download Time ....................................................................................................................................... 80|
|Table 3.33. JTAG Port Timing Specifications ....................................................................................................................... 81|Table 3.33. JTAG Port Timing Specifications ....................................................................................................................... 81|
© 2010-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02056-4.3
7
**MachXO2 Family Data Sheet Data Sheet**
|Table 3.34. sysCONFIG Port Timing Specifications ............................................................................................................. 82|Table 3.34. sysCONFIG Port Timing Specifications ............................................................................................................. 82|
|---|---|
|Table 3.35. I|Table 3.35. I2C Port Timing Specifications .......................................................................................................................... 83|
|Table 3.36. SPI Port Timing Specifications|Table 3.36. SPI Port Timing Specifications1......................................................................................................................... 83|
|Table 3.37. Test Fixture Required Components, Non-Terminated Interfaces|Table 3.37. Test Fixture Required Components, Non-Terminated Interfaces1................................................................... 84|
|Table 4.1. Signal Descriptions ............................................................................................................................................. 85|Table 4.1. Signal Descriptions ............................................................................................................................................. 85|
|Table 4.2. MachXO2-256/MachXO2-640/MachXO2-640U Pin Summary ........................................................................... 87|Table 4.2. MachXO2-256/MachXO2-640/MachXO2-640U Pin Summary ........................................................................... 87|
|Table 4.3. MachXO2-1200/MachXO2-1200U Pin Summary ............................................................................................... 88|Table 4.3. MachXO2-1200/MachXO2-1200U Pin Summary ............................................................................................... 88|
|Table 4.4. MachXO2-2000/MachXO2-2000U Pin Summary ............................................................................................... 89|Table 4.4. MachXO2-2000/MachXO2-2000U Pin Summary ............................................................................................... 89|
|Table 4.5. MachXO2-4000 Pin Summary ............................................................................................................................ 90|Table 4.5. MachXO2-4000 Pin Summary ............................................................................................................................ 90|
|Table 4.6. MachXO2-7000 Pin Summary ............................................................................................................................ 91|Table 4.6. MachXO2-7000 Pin Summary ............................................................................................................................ 91|
|Table 5.1. Ultra Low Power Commercial Grade Devices, Halogen Free (RoHS) Packaging ................................................ 94|Table 5.1. Ultra Low Power Commercial Grade Devices, Halogen Free (RoHS) Packaging ................................................ 94|
|Table 5.2. High-Performance Commercial Grade Devices with Voltage Regulator, Halogen Free (RoHS) Packaging ........ 96|Table 5.2. High-Performance Commercial Grade Devices with Voltage Regulator, Halogen Free (RoHS) Packaging ........ 96|
|Table 5.3. High-Performance Commercial Grade Devices without Voltage Regulator, Halogen Free (RoHS) Packaging 100|Table 5.3. High-Performance Commercial Grade Devices without Voltage Regulator, Halogen Free (RoHS) Packaging 100|
|Table 5.4. Ultra Low Power Industrial Grade Devices, Halogen Free (RoHS) Packaging................................................... 101|Table 5.4. Ultra Low Power Industrial Grade Devices, Halogen Free (RoHS) Packaging................................................... 101|
|Table 5.5. High-Performance Industrial Grade Devices with Voltage Regulator, Halogen Free (RoHS) Packaging .......... 104|Table 5.5. High-Performance Industrial Grade Devices with Voltage Regulator, Halogen Free (RoHS) Packaging .......... 104|
|Table 5.6. High Performance Industrial Grade Devices Without Voltage Regulator, Halogen Free (RoHS) Packaging .... 107|Table 5.6. High Performance Industrial Grade Devices Without Voltage Regulator, Halogen Free (RoHS) Packaging .... 107|
|Table 5.7. High Performance Automotive Grade Devices Halogen Free (RoHS) Packaging ............................................. 109|Table 5.7. High Performance Automotive Grade Devices Halogen Free (RoHS) Packaging ............................................. 109|
|Table 5.8. R1 Device Specifications ................................................................................................................................... 110|Table 5.8. R1 Device Specifications ................................................................................................................................... 110|
© 2010-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
8
FPGA-DS-02056-4.3
**MachXO2 Family Data Sheet Data Sheet**
## **Acronyms in This Document**
A list of acronyms used in this document. **Acronym Definition** ~~CR~~ BGA Ball Grid Array ~~Re a~~ caBGA ChipArray Ball Grid Array CE Clock Enable ~~a a~~ CLK System clock CMOS Complementary Metal Oxide Semiconductor ~~Re~~ DDR Double Data Rate EBR Embedded Block RAM ~~a~~ ECLK Edge Clock ~~Ce~~ FCIN Fast Carry In ~~a~~ FCO Fast Carry Out ~~a~~ I[2] C Inter-Integrated Circuit IP Intellectual Property I/O Input/Output ~~pe~~ JTAG Joint Test Action Group ~~pe~~ LED Light-emitting Diode ~~a~~ LSR Local Set/Reset ~~a~~ LUT Look-Up Table LVCMOS Low-Voltage CMOS LVDS Low-Voltage Differential Signaling ~~pe~~ LVPECL Low-Voltage Positive/Pseudo Emitter-Coupled Logic ~~pe~~ LVTTL Low Voltage Transistor to Transistor Logic ~~pe Ge~~ MIPI Mobile Industry Processor Interface ~~I~~ MLVDS Multipoint Low-Voltage Differential Signaling ~~I~~ PCI Peripheral Component Interconnect PCLK Primary Clock PDPR Pseudo Dual Port RAM PFU Programmable Functional Unit ~~Ge~~ PIC Programmable Interface Controllers ~~I~~ PIO Programmed Input/Output ~~I~~ PLD Programmable Logic Device PLL Phase Locked Loop RAM Random Access Memory ROM Read-only Memory SDR Single Data Rate ~~Ge~~ SHA Secure Hash Algorithm SPI Serial Peripheral Interface ~~Re~~ SPR Single Port Random Access Memory ~~Re pf~~ SRAM Static Random Access Memory ~~a~~ TransFR™ Transparent Field Reconfiguration ~~a~~ UFM User Flash Memory WLCSP Wafer Level Chip Scale Package ~~ER~~
© 2010-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02056-4.3
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**MachXO2 Family Data Sheet Data Sheet**
## **1. Introduction**
The MachXO2™ family of ultra low power, instant-on, non-volatile PLDs has six devices with densities ranging from 256 to 6864 Look-Up Tables (LUTs). In addition to LUT-based, low-cost programmable logic, these devices feature Embedded Block RAM (EBR), Distributed RAM, User Flash Memory (UFM), Phase Locked Loops (PLLs), preengineered source synchronous I/O support, advanced configuration support including dual-boot capability and hardened versions of commonly used functions such as SPI controller, I[2] C controller and timer/counter. These features allow these devices to be used in low cost, high volume consumer and system applications.
The MachXO2 devices are designed on a 65 nm non-volatile low power process. The device architecture has several features such as programmable low swing differential I/O and the ability to turn off I/O banks, on-chip PLLs and oscillators dynamically. These features help manage static and dynamic power consumption resulting in low static power for all members of the family.
The MachXO2 devices are available in two versions – ultra low power (ZE) and high performance (HC and HE) devices. The ultra low power devices are offered in three speed grades –1, –2 and –3, with –3 being the fastest. Similarly, the high-performance devices are offered in three speed grades: –4, –5 and –6, with –6 being the fastest. HC devices have an internal linear voltage regulator which supports external VCC supply voltages of 3.3 V or 2.5 V. ZE and HE devices only accept 1.2 V as the external VCC supply voltage. With the exception of power supply voltage all three types of devices (ZE, HC and HE) are functionally compatible and pin compatible with each other.
The MachXO2 PLDs are available in a broad range of advanced halogen-free packages ranging from the space saving 2.5 mm x 2.5 mm WLCSP to the 23 mm x 23 mm fpBGA. MachXO2 devices support density migration within the same package. Table 1.1 shows the LUT densities, package and I/O options, along with other key parameters.
The pre-engineered source synchronous logic implemented in the MachXO2 device family supports a broad range of interface standards, including LPDDR, DDR, DDR2 and 7:1 gearing for display I/O.
The MachXO2 devices offer enhanced I/O features such as drive strength control, slew rate control, PCI compatibility, bus-keeper latches, pull-up resistors, pull-down resistors, open drain outputs and hot socketing. Pull-up, pulldown and bus-keeper features are controllable on a “per-pin” basis.
A user-programmable internal oscillator is included in MachXO2 devices. The clock output from this oscillator may be divided by the timer/counter for use as clock input in functions such as LED control, keyboard scanner and similar state machines.
The MachXO2 devices also provide flexible, reliable and secure configuration from on-chip Flash memory. These devices can also configure themselves from external SPI Flash or be configured by an external master through the JTAG test access port or through the I[2] C port. Additionally, MachXO2 devices support dual-boot capability (using external Flash memory) and remote field upgrade (TransFR) capability.
Lattice provides a variety of design tools that allow complex designs to be efficiently implemented using the MachXO2 family of devices. Popular logic synthesis tools provide synthesis library support for MachXO2. Lattice design tools use the synthesis tool output along with the user-specified preferences and constraints to place and route the design in the MachXO2 device. These tools extract the timing from the routing and back-annotate it into the design for timing verification.
Lattice provides many pre-engineered IP (Intellectual Property) LatticeCORE™ modules, including a number of reference designs licensed free of charge, optimized for the MachXO2 PLD family. By using these configurable soft core IP cores as standardized blocks, users are free to concentrate on the unique aspects of their design, increasing their productivity.
© 2010-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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**MachXO2 Family Data Sheet Data Sheet**
## **1.1. Features**
## **1.1.7. Flexible On-Chip Clocking**
- Eight primary clocks
## **1.1.1. Flexible Logic Architecture**
- Six devices with 256 to 6864 LUT4s and 18 to 334 I/O
## **1.1.2. Ultra Low Power Devices**
- Advanced 65 nm low power process
- As low as 22 μW standby power
- Programmable low swing differential I/O
- Stand-by mode and other power saving options
## **1.1.3. Embedded and Distributed Memory**
- Up to 240 kbits sysMEM™ Embedded Block RAM
- Up to 54 kbits Distributed RAM
- Dedicated FIFO control logic
## **1.1.4. On-Chip User Flash Memory**
- Up to 256 kbits of User Flash Memory
- 100,000 write cycles
- Accessible through WISHBONE, SPI, I[2] C and JTAG interfaces
- Can be used as soft processor PROM or as Flash memory
## **1.1.5. Pre-Engineered Source Synchronous I/O**
- DDR registers in I/O cells
- Dedicated gearing logic
- 7:1 Gearing for Display I/O
- Generic DDR, DDRX2, DDRX4
- Dedicated DDR/DDR2/LPDDR memory with DQS support
## **1.1.6. High Performance, Flexible I/O Buffer**
- Programmable sysI/O™ buffer supports wide range of interfaces:
- LVCMOS 3.3/2.5/1.8/1.5/1.2
- LVTTL
- PCI
- LVDS, Bus-LVDS, MLVDS, RSDS, LVPECL
- SSTL 25/18
- HSTL 18
- MIPI D-PHY Emulated
- Schmitt trigger inputs, up to 0.5 V hysteresis
- Up to two edge clocks for high-speed I/O interfaces (top and bottom sides only)
- Up to two analog PLLs per device with fractional-n frequency synthesis
- Wide input frequency range (7 MHz to 400 MHz)
## **1.1.8. Non-volatile, Infinitely Reconfigurable**
- Instant-on – powers up in microseconds
- Single-chip, secure solution
- Programmable through JTAG, SPI or I[2] C
- Supports background programming of non-volatile memory
- Optional dual boot with external SPI memory
## **1.1.9. TransFR™ Reconfiguration**
- In-field logic update while system operates
## **1.1.10. Enhanced System Level Support**
- On-chip hardened functions: SPI, I[2] C, timer/counter
- On-chip oscillator with 5.5% accuracy
- Unique TraceID for system tracking
- One Time Programmable (OTP) mode
- Single power supply with extended operating range
- IEEE Standard 1149.1 boundary scan
- • IEEE 1532 compliant in-system programming
## **1.1.11. Broad Range of Package Options**
- TQFP, WLCSP, ucBGA, csBGA, caBGA, ftBGA, fpBGA, QFN package options
- Small footprint package options
- As small as 2.5 mm x 2.5 mm
- Density migration supported
- Advanced halogen-free packaging
## **1.1.12. Application**
- Consumer electronics
- Compute and storage
- Wireless communications
- Industrial control systems
- Automotive system
- I/O support hot socketing
- On-chip differential termination
- Programmable pull-up or pull-down mode
© 2010-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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**MachXO2 Family Data Sheet Data Sheet**
**Table 1.1. MachXO2 Family Selection Guide**
|||**XO2-**<br>**256**<br>~~|~~|**XO2-**<br>**640**<br>||**XO2-**<br>**640U1**<br>||**XO2-**<br>**1200**<br>~~|~~|**XO2-**<br>**1200U1**<br>~~|~~|**XO2-**<br>**2000**<br>~~|~~|**XO2-**<br>**2000U1**<br>~~ft~~|**XO2-**<br>**4000**<br>~~ft~~|**XO2-**<br>**7000**|
|---|---|---|---|---|---|---|---|---|---|---|
|LUTs<br>~~OG~~||256<br>~~|~~<br>~~OG~~|640<br>|<br>~~OG~~|640<br>|<br>~~OG~~<br>~~eG~~|1280<br>~~|~~<br>~~OG~~<br>~~eG~~|1280<br>~~|~~<br>~~OG~~<br>~~eG~~|2112<br>~~|~~<br>~~OG~~<br>~~GO~~|2112<br>~~ft~~<br>~~OG~~<br>~~GO~~|4320<br>~~ft~~<br>~~OG~~|6864<br>~~OG~~|
|Distributed RAM(kbits)<br>~~eG~~||2<br>~~eG~~|5<br>~~eG~~|5<br>~~eG~~<br>~~eG~~|10<br>~~eG~~<br>~~eG~~|10<br>~~eG~~<br>~~eG~~|16<br>~~eG~~<br>~~GO~~|16<br>~~eG~~<br>~~GO~~|34<br>~~eG~~|34<br>~~eG~~|
|EBR SRAM(Kbits)<br>~~po~~||0<br>~~po~~|18<br>~~po~~|64<br>~~eG~~<br>~~po~~|64<br>~~eG~~<br>~~po~~|74<br>~~eG~~<br>~~po~~|74<br>~~GO~~<br>~~po~~<br>~~GO~~|92<br>~~GO~~<br>~~po~~<br>~~GO~~|92<br>~~po~~<br>~~GO~~|240<br>~~po~~|
|Number of EBR SRAM Blocks(9 Kbits)<br>~~a~~||0<br>~~GG~~|2<br>~~GG~~|7<br>~~GG~~|7<br>~~GG~~|8<br>~~GG~~|8<br>~~GG~~<br>~~GO~~|10<br>~~GG~~<br>~~GO~~|10<br>~~GG~~<br>~~GO~~|26<br>~~GG~~|
|UFM(kbits)<br>~~po~~<br>~~NE~~||0<br>~~po~~|24<br>~~po~~|64<br>~~po~~<br>~~ee~~|64<br>~~po~~<br>~~ee~~|80<br>~~po~~<br>~~ee~~|80<br>~~GO~~<br>~~po~~<br>~~ee~~|96<br>~~GO~~<br>~~po~~<br>~~ee~~|96<br>~~GO~~<br>~~po~~<br>~~ee~~|256<br>~~po~~<br>~~ee~~|
|Device Options:<br>~~NE~~<br>~~po~~<br>~~po~~<br>~~po~~|HC2<br>~~po~~|Yes|Yes|Yes<br>~~ee~~|Yes<br>~~ee~~|Yes<br>~~ee~~|Yes<br>~~ee~~|Yes<br>~~ee~~|Yes<br>~~ee~~|Yes<br>~~ee~~|
||HE3<br>~~po~~<br>~~po~~|—|—|—<br>~~ee~~|—<br>~~ee~~|—<br>~~ee~~|Yes<br>~~ee~~|Yes<br>~~ee~~|Yes<br>~~ee~~|Yes<br>~~ee~~|
||ZE4<br>~~po~~<br>~~po~~<br>~~po~~|Yes<br>|Yes<br>|—<br>~~ee~~<br>|Yes<br>~~ee~~<br>|—<br>~~ee~~<br>|Yes<br>~~ee~~<br>|—<br>~~ee~~<br>|Yes<br>~~ee~~<br>|Yes<br>~~ee~~|
|Number of PLLs<br>~~NE~~<br>~~po~~<br>~~po~~||0<br>|0<br>|1<br>~~ee~~<br>|1<br>~~ee~~<br>|1<br>~~ee~~<br>|1<br>~~ee~~<br>|2<br>~~ee~~<br>|2<br>~~ee~~<br>|2<br>~~ee~~|
|Hardened Functions<br>~~poet~~<br>~~po~~<br>~~po~~|I2C<br>~~poet~~<br>~~po~~|2<br>~~et~~|2<br>~~et~~|2<br>~~et~~|2<br>~~et~~|2<br>~~et~~|2<br>~~et~~|2<br>~~et~~|2<br>~~et~~|2|
||SPI<br>~~et~~<br>~~po~~<br>~~po~~|1<br>~~et~~|1<br>~~et~~|1<br>~~et~~|1<br>~~et~~|1<br>~~et~~|1<br>~~et~~|1<br>~~et~~|1<br>~~et~~|1|
||Timer/Counter<br>~~et~~<br>~~po~~<br>~~po~~<br>~~ET~~|1<br>~~et~~<br>~~ET~~|1<br>~~et~~<br>~~ET|~~|1<br>~~et~~<br>~~|~~<br>~~TE~~|1<br>~~et~~<br>~~TETT~~|1<br>~~et~~<br>~~TT~~|1<br>~~et~~<br>~~TT Tt~~|1<br>~~et~~<br>~~Tt~~|1<br>~~et~~<br>~~Tt~~|1<br>~~Tt~~|
|Automotive Qualified<br>~~po~~<br>~~PoC~~<br>~~ET~~||XO2-<br>256<br>~~PoC~~<br>~~ET~~|XO2-<br>640<br>~~PoC~~<br>~~ET|~~|—<br>~~PoC~~<br>~~|~~<br>~~TE~~|—<br>~~PoC~~<br>~~TETT~~|—<br>~~PoC~~<br>~~TT~~|—<br>~~PoC~~<br>~~TT Tt~~|—<br>~~PoC~~<br>~~Tt~~|—<br>~~PoC~~<br>~~Tt~~|—<br>~~PoC~~<br>~~Tt~~|
|**Packages**<br>**I/O**<br>~~ET |~~<br>~~TE TT Tt~~<br>~~eee~~<br>~~ee~~|||||||||||
|25-ball WLCSP5<br>(2.5 mm x 2.5 mm, 0.4 mm)<br>~~eee~~<br>~~a~~||~~eee~~<br>~~a~~<br>~~ee~~|~~eee~~<br>~~a~~<br>~~ee~~|~~eee~~<br>~~a~~<br>~~ee~~|18<br>~~eee~~<br>~~a~~<br>~~ee~~|~~eee~~<br>~~a~~|~~eee~~<br>~~a~~|~~eee~~<br>~~a~~|~~eee~~<br>~~a~~|~~eee~~<br>~~a~~|
|32 QFN6<br>(5 mm x 5 mm, 0.5 mm)<br>~~a~~<br>~~ee~~||21<br>~~a~~<br>~~ee~~<br>~~ee~~|~~a~~<br>~~ee~~<br>~~ee~~|~~a~~<br>~~ee~~<br>~~ee~~|21<br>~~a~~<br>~~ee~~<br>~~ee~~|~~a~~<br>~~ee~~|~~a~~<br>~~ee~~|~~a~~<br>~~ee~~|~~a~~<br>~~ee~~|~~a~~<br>~~ee~~|
|36-ball WLCSP5<br>(2.5 mm x 2.5 mm,0.4 mm)<br>~~ee~~<br>~~ee~~||~~ee~~<br>~~ee~~|~~ee~~<br>~~ee~~|~~ee~~<br>~~ee~~|28<br>~~ee~~<br>~~ee~~|~~ee~~<br>~~ee~~|~~ee~~<br>~~ee~~|~~ee~~<br>~~ee~~|~~ee~~<br>~~ee~~|~~ee~~<br>~~ee~~|
|48 QFN8, 9<br>(7 mm x 7 mm, 0.5 mm)<br>~~ee~~<br>~~ee~~||40<br>~~ee~~<br>~~ee~~|40<br>~~ee~~<br>~~ee~~|~~ee~~<br>~~ee~~|~~ee~~<br>~~ee~~|~~ee~~<br>~~ee~~|~~ee~~<br>~~ee~~|~~ee~~<br>~~ee~~|~~ee~~<br>~~ee~~|~~ee~~<br>~~ee~~|
|49-ball WLCSP5<br>(3.2 mm x 3.2 mm, 0.4 mm)<br>~~a~~|||||||38||||
|64-ball ucBGA<br>(4 mm x 4 mm, 0.4 mm)<br>~~a~~||44|||||||||
|81-ball WLCSP5<br>(3.8 mm x 3.8 mm, 0.4 mm)<br>~~a~~|||||||||63||
|84 QFN7<br>(7 mm x 7 mm, 0.5 mm)<br>~~a~~<br>~~a~~<br>~~ee~~|||||~~eee~~|~~eee~~|~~eee~~|~~eee~~|68<br>~~eee~~|~~eee~~|
|100-pin TQFP<br>(14 mm x 14 mm)<br>~~a~~<br>~~ee~~<br>~~Pe~~||5510|7810||79<br>~~eee~~|~~eee~~<br>~~ee~~|79<br>~~eee~~<br>~~ee~~|~~eee~~<br>~~ee~~|~~eee~~<br>~~ee~~|~~eee~~<br>~~ee~~|
|132-ball csBGA<br>(8 mm x 8 mm,0.5 mm)<br>~~ee~~<br>~~Pe~~<br>~~|~~<br>~~a~~||5510<br>|7910<br>||104<br>~~eee~~<br>|~~eee~~<br>~~ee~~<br>|104<br>~~eee~~<br>~~ee~~<br><br>~~>~~|~~eee~~<br>~~ee~~<br><br>~~>~~|104<br>~~eee~~<br>~~ee~~<br><br>~~>~~|~~eee~~<br>~~ee~~<br><br>~~>~~|
|144-pin TQFP<br>(20 mm x 20 mm)<br>~~Pe~~<br>~~||_|~~<br>~~a~~||~~|_|~~|~~|_|~~|107<br>~~|_|~~|107<br>~~|_|~~|~~ee~~<br>~~|_|~~|111<br>~~ee~~<br>~~|_|~~<br>~~>~~|~~ee~~<br>~~|_|~~<br>~~>~~|115<br>~~ee~~<br>~~|_|~~<br>~~>~~|115<br>~~ee~~<br>~~|_|~~<br>~~>~~|
|184-ball csBGA7<br>(8 mm x 8 mm, 0.5 mm)<br>~~|~~<br>~~a~~|||~~ee~~||~~ee~~|~~ee~~|~~>~~|~~>~~|150<br><br>~~>~~|~~>~~|
|256-ball caBGA<br>(14 mm x 14 mm, 0.8 mm)<br>~~ee~~||~~ee~~<br>~~ee~~|~~ee~~<br>~~ee~~<br>~~ee~~|~~ee~~<br>~~ee~~|~~ee~~<br>~~ee~~<br>~~ee~~|~~ee~~<br>~~ee~~|206<br>~~ee~~|~~ee~~|206<br>~~ee~~|206<br>~~ee~~|
|256-ball ftBGA<br>(17 mm x 17 mm,1.0 mm)<br>~~ee~~<br>~~a~~||~~ee~~<br>~~ee~~<br>~~ee~~|~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|~~ee~~<br>~~ee~~<br>~~ee~~|~~ee~~<br>~~ee~~<br>~~ee~~|206<br>~~ee~~<br>~~ee~~|206<br>~~ee~~|~~ee~~|206<br>~~ee~~|206<br>~~ee~~|
|332-ball caBGA<br>(17 mm x 17 mm, 0.8 mm)<br>~~ee~~<br>~~a~~||~~ee ~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|~~ee~~<br>~~ee~~<br>~~ee~~|~~ee~~|~~ee~~|~~ee~~|274<br>~~ee~~|278<br>~~ee~~|
|484-ball ftBGA<br>(23 mm x 23 mm, 1.0 mm)<br>~~ee~~<br>~~a~~||~~ee~~<br>~~ee~~<br>~~ee~~|~~ee~~<br>~~ee~~<br>~~ee~~|~~ee~~<br>~~ee~~<br>~~ee~~|~~ee~~<br>~~ee~~|~~ee~~|~~ee~~|278<br>~~ee~~|278<br>~~ee~~|334<br>~~ee~~|
© 2010-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02056-4.3
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**MachXO2 Family Data Sheet Data Sheet**
## **Notes:**
1. Ultra high I/O device.
2. High performance with regulator – VCC = 2.5 V, 3.3 V
3. High performance without regulator – VCC = 1.2 V
4. Low power without regulator – VCC = 1.2 V
5. WLCSP package only available for ZE devices.
6. 32 QFN package only available for HC and ZE devices.
7. 184 csBGA package only available for HE devices.
8. 48-pin QFN information is ‘Advanced’.
9. 48 QFN package only available for HC devices.
10. Package is available for automotive devices.
© 2010-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02056-4.3
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**MachXO2 Family Data Sheet Data Sheet**
## **2. Architecture**
## **2.1. Architecture Overview**
The MachXO2 family architecture contains an array of logic blocks surrounded by Programmable I/O (PIO). The larger logic density devices in this family have sysCLOCK™ PLLs and blocks of sysMEM Embedded Block RAM (EBRs). Figure 2.1 and Figure 2.2 show the block diagrams of the various family members.
**==> picture [439 x 372] intentionally omitted <==**
**----- Start of picture text -----**<br>
Embedded Function Block (EFB)<br>User Flash Memory (UFM)<br>7 Podee Sneenenen<br>sysCLOCK PLL<br>sysMEM Embedded Block RAM (EBR)<br>On-chip Configuration Flash<br>Memory<br>Programmable Function Units with<br>Distributed RAM (PFUs)<br>PIOs Arranged into<br>sysI/O Banks<br>=<br>|<br>Note: MachXO2-256, and MachXO2-640/U are similar to MachXO2-1200. MachXO2-256 has a lower LUT count and no PLL or EBR blocks.<br>MachXO2-640 has no PLL, a lower LUT count and two EBR blocks. MachXO2-640U has a lower LUT count, one PLL and seven EBR blocks.<br>Figure 2.1. Top View of the MachXO2-1200 Device<br>Embedded Function<br>Block(EFB)<br>User Flash<br>Memory (UFM)<br>sysCLOCK PLL<br>On-chip Configuration<br>Flash Memory<br>sysMEM Embedded Block RAM (EBR)<br>PIOs Arranged into<br>sysI/O Banks<br>**----- End of picture text -----**<br>
**==> picture [95 x 159] intentionally omitted <==**
**----- Start of picture text -----**<br>
Embedded Function<br>Block(EFB)<br>User Flash<br>Memory (UFM)<br>sysMEM Embedded Block RAM (EBR)<br>Programmable Function Units<br>with Distributed RAM (PFUs)<br>**----- End of picture text -----**<br>
Note: MachXO2-1200U, MachXO2-2000/U and MachXO2-7000 are similar to MachXO2-4000. MachXO2-1200U and MachXO2-2000 have a lower LUT count, one PLL, and eight EBR blocks. MachXO2-2000U has a lower LUT count, two PLLs, and 10 EBR blocks. MachXO2-7000 has a higher LUT count, two PLLs, and 26 EBR blocks.
**Figure 2.2. Top View of the MachXO2-4000 Device**
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**MachXO2 Family Data Sheet Data Sheet**
The logic blocks, Programmable Functional Unit (PFU) and sysMEM EBR blocks, are arranged in a two-dimensional grid with rows and columns. Each row has either the logic blocks or the EBR blocks. The PIO cells are located at the periphery of the device, arranged in banks. The PFU contains the building blocks for logic, arithmetic, RAM, ROM, and register functions. The PIOs utilize a flexible I/O buffer referred to as a sysI/O buffer that supports operation with a variety of interface standards. The blocks are connected with many vertical and horizontal routing channel resources. The place and route software tool automatically allocates these routing resources.
In the MachXO2 family, the number of sysI/O banks varies by device. There are different types of I/O buffers on the different banks. Refer to the details in later sections of this document. The sysMEM EBRs are large, dedicated fast memory blocks; these blocks are found in MachXO2-640/U and larger devices. These blocks can be configured as RAM, ROM or FIFO. FIFO support includes dedicated FIFO pointer and flag “hard” control logic to minimize LUT usage.
The MachXO2 registers in PFU and sysI/O can be configured to be SET or RESET. After power-up and device is configured, the device enters into user mode with these registers SET/RESET according to the configuration setting, allowing device entering to a known state for predictable system function.
The MachXO2 architecture also provides up to two sysCLOCK Phase Locked Loop (PLL) blocks on MachXO2- 640U, MachXO2-1200/U and larger devices. These blocks are located at the ends of the on-chip Flash block. The PLLs have multiply, divide, and phase shifting capabilities that are used to manage the frequency and phase relationships of the clocks.
MachXO2 devices provide commonly used hardened functions such as SPI controller, I[2] C controller and timer/ counter. MachXO2-640/U and higher density devices also provide User Flash Memory (UFM). These hardened functions and the UFM interface to the core logic and routing through a WISHBONE interface. The UFM can also be accessed through the SPI, I[2] C and JTAG ports.
Every device in the family has a JTAG port that supports programming and configuration of the device as well as access to the user logic. The MachXO2 devices are available for operation from 3.3 V, 2.5 V and 1.2 V power supplies, providing easy integration into the overall system.
## **2.2. PFU Blocks**
The core of the MachXO2 device consists of PFU blocks, which can be programmed to perform logic, arithmetic, distributed RAM and distributed ROM functions. Each PFU block consists of four interconnected slices numbered 0 to 3 as shown in Figure 2.3. Each slice contains two LUTs and two registers. There are 53 inputs and 25 outputs associated with each PFU block.
**==> picture [360 x 176] intentionally omitted <==**
**----- Start of picture text -----**<br>
From<br>Routing<br>FCIN LUT4 anCARRYd LUT4 andCARRY LUT4 CARRYand LUT4 andCARRY LUT4 andCARRY LUT4 andCARRY LUT4 andCARRY LUTCARRY4 and FCO<br>Slice 0 Slice 1 Slice 2 Slice 3<br>D D D D D D D D<br>FF/ FF/ FF/ FF/ FF/ FF/ FF/ FF/<br>Latch Latch Latch Latch Latch Latch Latch Latch<br>AICUCICIoCe|<br>To<br>Routing<br><=<br>**----- End of picture text -----**<br>
**Figure 2.3. PFU Block Diagram**
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**MachXO2 Family Data Sheet Data Sheet**
## **2.2.1. Slices**
Slices 0-3 contain two LUT4s feeding two registers. Slices 0-2 can be configured as distributed memory. Table 2.1 shows the capability of the slices in PFU blocks along with the operation modes they enable. In addition, each PFU contains logic that allows the LUTs to be combined to perform functions such as LUT5, LUT6, LUT7 and LUT8. The control logic performs set/reset functions (programmable as synchronous/ asynchronous), clock select, chipselect and wider RAM/ROM functions.
**Table 2.1. Resources and Modes Available per Slice**
|**Slice**|**PFU Block**|**PFU Block**|
|---|---|---|
||**Resources**|**Modes**|
|Slice 0|2 LUT4s and 2 Registers|Logic, Ripple, RAM, ROM|
|Slice 1|2 LUT4s and 2 Registers|Logic, Ripple, RAM, ROM|
|Slice 2|2 LUT4s and 2 Registers|Logic, Ripple, RAM, ROM|
|Slice 3|2 LUT4s and 2 Registers|Logic, Ripple, ROM|
Figure 2.4 shows an overview of the internal logic of the slice. The registers in the slice can be configured for positive/ negative and edge triggered or level sensitive clocks. All slices have 15 inputs from routing and one from the carry-chain (from the adjacent slice or PFU). There are seven outputs: six for routing and one to carry-chain (to the adjacent PFU). Table 2.2 lists the signals associated with Slices 0-3.
**==> picture [382 x 317] intentionally omitted <==**
**----- Start of picture text -----**<br>
FCO to Different Slice/PFU<br>Slice<br>FXB<br>OFX1<br>FXA<br>a ee<br>F/SUM F1<br>AI<br>CO<br>B1<br>D1C1 |__|[sd LUT4 and 7 D Q1<br>Carry<br>Flip-flop/<br>Latch<br>CI To<br>Routing<br>M1<br>From M0 LUT5<br>Routing Mux<br>CO i OFX0<br>A1 CO<br>B0<br>C0 F0<br>D0 ee < i LUT4 and | |<br>Carry<br>D Q0<br>- CI F/SUM maynd Flip-flop/<br>Latch<br>CE<br>CLK<br>LSR ——_I])<br>Memory and FCI from<br>Control Different<br>Signals Slice/PFU<br>For Slice 0 and 1, memory control signals are generated from Slice 2 as follows:<br>**----- End of picture text -----**<br>
**Figure 2.4. Slice Diagram**
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**MachXO2 Family Data Sheet Data Sheet**
**Table 2.2. Slice Signal Descriptions**
|**Function**<br>~~**e**s~~|**Type **<br>|**Signal Names**<br>~~G~~|**Description**<br>~~G~~|
|---|---|---|---|
|Input<br>~~**e**s ~~<br>~~es~~|Data signal<br>|A0, B0, C0, D0<br> ~~G~~|Inputs to LUT4<br>~~G~~<br>~~G~~|
|Input<br>~~es~~<br>~~es~~|Data signal<br>|A1, B1, C1, D1<br>|Inputs to LUT4<br>|
|Input<br>~~es~~<br>~~es~~|Multi-purpose<br>|M0/M1<br>|Multipurpose Input<br>|
|Input<br>~~esse~~|Control signal<br>~~se~~|CE<br>~~se~~|Clock Enable<br>~~se~~|
|Input<br>~~se~~|Control signal<br>~~se~~|LSR<br>~~se~~|Local Set/Reset<br>~~se~~|
|Input<br>~~sO~~<br>~~es~~|Control signal<br>~~sO~~|CLK<br>~~sO~~|System Clock<br>~~sO~~|
|Input<br>~~es~~<br>~~es~~|Inter-PFU signal<br>|FCIN<br>|Fast CarryIn1<br>|
|Output<br>~~es~~<br>~~es~~|Data signals<br>|F0, F1<br>|LUT4 output register bypass signals<br>|
|Output<br>~~esse~~|Data signals<br>~~se~~|Q0, Q1<br>~~se~~|Register Outputs<br>~~se~~|
|Output<br>~~se~~<br>~~**e**e~~|Data signals<br>~~se~~<br>~~a~~|OFX0<br>~~se~~<br>~~G~~|Output of a LUT5 MUX<br>~~se~~<br>~~G~~|
|Output<br>~~**e**e~~|Data signals<br>~~a~~|OFX1<br>~~G~~|Output of a LUT6, LUT7, LUT82MUX dependingon the Slice<br>~~G~~|
|Output<br>~~**e**e~~|Inter-PFU signal<br>~~a ~~|FCO<br> ~~G~~|Fast CarryOut1<br>~~G~~<br>~~e~~|
**Notes:**
1. See Figure 2.3 for connection details.
2. Requires two PFUs.
## **2.2.2. Modes of Operation**
Each slice has up to four potential modes of operation: Logic, Ripple, RAM and ROM.
## **Logic Mode**
In this mode, the LUTs in each slice are configured as 4-input combinatorial lookup tables. A LUT4 can have 16 possible input combinations. Any four input logic functions can be generated by programming this lookup table. Since there are two LUT4s per slice, a LUT5 can be constructed within one slice. Larger look-up tables such as LUT6, LUT7 and LUT8 can be constructed by concatenating other slices. Note LUT8 requires more than four slices.
## **Ripple Mode**
Ripple mode supports the efficient implementation of small arithmetic functions. In Ripple mode, the following functions can be implemented by each slice:
- Addition 2-bit
- Subtraction 2-bit
- Add/subtract 2-bit using dynamic control
- Up counter 2-bit
- Down counter 2-bit
- Up/down counter with asynchronous clear
- Up/down counter with preload (sync)
- Ripple mode multiplier building block
- Multiplier support
- Comparator functions of A and B inputs
- A greater-than-or-equal-to B
- A not-equal-to B
- A less-than-or-equal-to B
Ripple mode includes an optional configuration that performs arithmetic using fast carry chain methods. In this configuration (also referred to as CCU2 mode) two additional signals, Carry Generate and Carry Propagate, are generated on a per-slice basis to allow fast arithmetic functions to be constructed by concatenating slices.
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**MachXO2 Family Data Sheet Data Sheet**
## **2.2.3. RAM Mode**
In this mode, a 16x4-bit distributed single port RAM (SPR) can be constructed by using each LUT block in Slice 0 and Slice 1 as a 16x1-bit memory. Slice 2 is used to provide memory address and control signals. MachXO2 devices support distributed memory initialization.
The Lattice design tools support the creation of a variety of different size memories. Where appropriate, the software constructs these using distributed memory primitives that represent the capabilities of the PFU. Table 2.3 shows the number of slices required to implement different distributed RAM primitives. For more information about using RAM in MachXO2 devices, see Memory Usage Guide for MachXO2 Devices (FPGA-TN-02159).
## **Table 2.3. Number of Slices Required For Implementing Distributed RAM[1]**
||**SPR 16x4**|**PDPR 16x4**|
|---|---|---|
|Number of Slices|3|3|
**Note:**
1. SPR = Single Port RAM, PDPR = Pseudo Dual Port RAM
## **2.2.4. ROM Mode**
ROM mode uses the LUT logic; hence, slices 0-3 can be used in ROM mode. Preloading is accomplished through the programming interface during PFU configuration.
For more information on the RAM and ROM modes, refer to Memory Usage Guide for MachXO2 Devices (FPGA-TN-02159).
## **2.3. Routing**
There are many resources provided in the MachXO2 devices to route signals individually or as buses with related control signals. The routing resources consist of switching circuitry, buffers and metal interconnect (routing) segments.
The inter-PFU connections are made with three different types of routing resources: x1 (spans two PFUs), x2 (spans three PFUs) and x6 (spans seven PFUs). The x1, x2, and x6 connections provide fast and efficient connections in the horizontal and vertical directions.
The design tools take the output of the synthesis tool and places and routes the design. Generally, the place and route tool is completely automatic, although an interactive routing editor is available to optimize the design.
## **2.4. Clock/Control Distribution Network**
Each MachXO2 device has eight clock inputs (PCLK [T, C] [Banknum]_[2..0]) – three pins on the left side, two pins each on the bottom and top sides and one pin on the right side. These clock inputs drive the clock nets. These eight inputs can be differential or single-ended and may be used as general purpose I/O if they are not used to drive the clock nets. When using a single ended clock input, only the PCLKT input can drive the clock tree directly.
The MachXO2 architecture has three types of clocking resources: edge clocks, primary clocks and secondary high fanout nets. MachXO2-640U, MachXO2-1200/U and higher density devices have two edge clocks each on the top and bottom edges. Lower density devices have no edge clocks. Edge clocks are used to clock I/O registers and have low injection time and skew. Edge clock inputs are from PLL outputs, primary clock pads, edge clock bridge outputs and CIB sources.
The eight primary clock lines in the primary clock network drive throughout the entire device and can provide clocks for all resources within the device including PFUs, EBRs and PICs. In addition to the primary clock signals, MachXO2 devices also have eight secondary high fanout signals which can be used for global control signals, such as clock enables, synchronous or asynchronous clears, presets, output enables, etc. Internal logic can drive the global clock network for internally-generated global clocks and control signals.
The maximum frequency for the primary clock network is shown in the MachXO2 External Switching Characteristics table.
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**MachXO2 Family Data Sheet Data Sheet**
The primary clock signals for the MachXO2-256 and MachXO2-640 are generated from eight 17:1 muxes The available clock sources include eight I/O sources and 9 routing inputs. Primary clock signals for the MachXO2-640U, MachXO2-1200/U and larger devices are generated from eight 27:1 muxes. The available clock sources include eight I/O sources, 11 routing inputs, eight clock divider inputs and up to eight sysCLOCK PLL outputs.
**==> picture [313 x 461] intentionally omitted <==**
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Up to 8 8 11 8<br>esee ee Dynamic<br>a 27:1 Clock Primary Clock 0<br>Enable<br>a Dynamic<br>re 27:1 Clock Primary Clock 1<br>Enable<br>ee is Dynamic<br>a 27:1 Clock Primary Clock 2<br>Enable<br>is<br>a<br>re 27:1 DynamicClock Primary Clock 3<br>Enable<br>a| o-<br>re 27:1 DynamicClock Primary Clock 4<br>Enable<br>i s<br>a<br>ee 27:1 DynamicClock Primary Clock 5<br>Enable<br>i n<br>esee ee<br>re 27:1<br>Dynamic<br>Clock<br>ins Enable Primary Clock 6<br>a 27:1 Clock<br>Switch<br>is<br>a 27:1<br>Dynamic<br>Clock<br>Enable<br>eS eeis , So Primary Clock<br>reae 27:1 Clock 7<br>=<br>Switch<br>2 un x<br>icy 3 oo 3<br>a= S8 =Q »>23vo =<br>a oO (“4 wu A<br>Primary clocks for MachXO2-640U, MachXO2-1200/U and larger devices.<br>Note: MachXO2-640 and smaller devices do not have inputs from the Edge Clock Divider or PLL<br>and fewer routing inputs. These devices have 17:1 muxes instead of 27:1 muxes.<br>**----- End of picture text -----**<br>
**Figure 2.5. Primary Clocks for MachXO2 Devices**
Eight secondary high fanout nets are generated from eight 8:1 muxes, as shown in Figure 2.6. One of the eight inputs to the secondary high fanout net input mux comes from dual function clock pins and the remaining seven come from internal routing. The maximum frequency for the secondary clock network is shown in Table 3.26.
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**MachXO2 Family Data Sheet Data Sheet**
**==> picture [212 x 351] intentionally omitted <==**
**----- Start of picture text -----**<br>
1 7<br>Secondary High<br>8:1<br>Fanout Net 0<br>Secondary High<br>8:1<br>Fanout Net 1<br>Secondary High<br>8:1<br>Fanout Net 2<br>Secondary High<br>8:1<br>Fanout Net 3<br>Secondary High<br>8:1<br>Fanout Net 4<br>Secondary High<br>8:1<br>Fanout Net 5<br>Secondary High<br>8:1<br>Fanout Net 6<br>Secondary High<br>8:1<br>Fanout Net 7<br>Clock Pads Routing<br>**----- End of picture text -----**<br>
**Figure 2.6. Secondary High Fanout Nets for MachXO2 Devices**
## **2.4.1. sysCLOCK Phase Locked Loops (PLLs)**
The sysCLOCK PLLs provide the ability to synthesize clock frequencies. The MachXO2-640U, MachXO2-1200/U and larger devices have one or more sysCLOCK PLL. CLKI is the reference frequency input to the PLL and its source can come from an external I/O pin or from internal routing. CLKFB is the feedback signal to the PLL which can come from internal routing or an external I/O pin. The feedback divider is used to multiply the reference frequency and thus synthesize a higher frequency clock output.
The MachXO2 sysCLOCK PLLs support high resolution (16-bit) fractional-N synthesis. Fractional-N frequency synthesis allows the user to generate an output clock which is a non-integer multiple of the input frequency. For more information about using the PLL with Fractional-N synthesis, see MachXO2 sysCLOCK PLL Design and Usage Guide (FPGA-TN-02157).
Each output has its own output divider, thus allowing the PLL to generate different frequencies for each output. The output dividers can have a value from 1 to 128. The output dividers may also be cascaded together to generate low frequency clocks. The CLKOP, CLKOS, CLKOS2, and CLKOS3 outputs can all be used to drive the MachXO2 clock distribution network directly or general purpose routing resources can be used.
The LOCK signal is asserted when the PLL determines it has achieved lock and de-asserted if a loss of lock is detected. A block diagram of the PLL is shown in Figure 2.7.
The setup and hold times of the device can be improved by programming a phase shift into the CLKOS, CLKOS2, and CLKOS3 output clocks which advance or delay the output clock with reference to the CLKOP output clock.
This phase shift can be either programmed during configuration or can be adjusted dynamically. In dynamic mode, the PLL may lose lock after a phase adjustment on the output used as the feedback source and not relock until the tLOCK parameter has been satisfied.
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**MachXO2 Family Data Sheet Data Sheet**
The MachXO2 also has a feature that allows the user to select between two different reference clock sources dynamically. This feature is implemented using the PLLREFCS primitive. The timing parameters for the PLL are shown in the sysCLOCK PLL Timing table.
The MachXO2 PLL contains a WISHBONE port feature that allows the PLL settings, including divider values, to be dynamically changed from the user logic. When using this feature the EFB block must also be instantiated in the design to allow access to the WISHBONE ports. Similar to the dynamic phase adjustment, when PLL settings are updated through the WISHBONE port the PLL may lose lock and not relock until the tLOCK parameter has been satisfied. The timing parameters for the PLL are shown in the sysCLOCK PLL Timing table.
For more details on the PLL and the WISHBONE interface, see MachXO2 sysCLOCK PLL Design and Usage Guide (FPGA-TN-02157).
**==> picture [476 x 299] intentionally omitted <==**
**----- Start of picture text -----**<br>
DPHSRC<br>PHASESEL[1:0]<br>PHASEDIR Dynamic<br>Phase<br>PHASESTEP Adjust<br>CLKOP Phase CLKOP<br>A2 ClkEn<br>STDBY A0 Divider Adjust/ Mux Synch<br>(1 - 12 8) Edge Trim<br>REFCLK<br>CLKOS<br>CLKI REFCLK Divider Phase detector, B0 MuxB1 (1 - 12CLKOS Divider8) Edge TrimAdjust/ Phase MuxB2 SynchClkEn<br>7 M (1 - 40) VCO, and DH}. o O Dp.<br> loop filter.<br>CLKFB FBKSEL CLKOS2<br>CLKOS2<br>FBKCLK Fractional- N C0 MuxC1 Divider Phase Adjust MuxC2 SynchClkEn<br>Divider Synthesizer (1 - 12 8)<br>N (1 - 40)<br>CLKOS3<br>CLKOS3<br>D1 Phase D2 ClkEn<br>D0 Divider<br>Mux Adjust Mux Synch<br>Internal Feed back (1 - 12 8)<br>eee<br>CLKOP, CLKOS, CLKOS2, CLKOS3<br>LOCK<br>4 Lock<br>RST, RESETM, RESETC, RESETD Detect<br>ENCLKOP, ENCLKOS, ENCLKOS2, ENCLKOS3<br>PLLDATO[7:0] , PLLACK<br>PLLCLK, PLLRST, PLLSTB, PLLWE, PLLDATI[7:0], PLLADDR[4:0]<br>**----- End of picture text -----**<br>
**Figure 2.7. PLL Diagram**
Table 2.4 provides signal descriptions of the PLL block.
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**MachXO2 Family Data Sheet Data Sheet**
**Table 2.4. PLL Signal Descriptions**
|**Port Name**<br>~~a~~|**I/O**|**Description**|
|---|---|---|
|CLKI<br>~~a~~|I|Input clock to PLL|
|CLKFB<br>~~a~~|I|Feedback clock|
|PHASESEL[1:0]<br>~~a~~|I|Select which output is affected byDynamic Phase adjustmentports|
|PHASEDIR<br>~~a~~|I<br>~~eG~~|Dynamic Phase adjustment direction<br>~~eG~~|
|PHASESTEP<br>~~a~~|I<br>~~eG~~|Dynamic Phase step– toggle shifts VCOphase adjust byone step.<br>~~eG~~|
|CLKOP<br>~~a~~|O<br>~~G~~|PrimaryPLL output clock(withphase shift adjustment)<br>~~G~~|
|CLKOS<br>~~a~~|O|SecondaryPLL output clock(withphase shift adjust)|
|CLKOS2<br>~~a~~|O|SecondaryPLL output clock2(withphase shift adjust)|
|CLKOS3|O|SecondaryPLL output clock3(withphase shift adjust)|
|LOCK<br>~~a~~|O|PLL LOCK, asynchronous signal. Active high indicates PLL is locked to input<br>and feedback signals.|
|DPHSRC<br>~~a~~|O|Dynamic Phase source –ports or WISHBONE is active|
|STDBY<br>~~a~~|I|Standbysignal topower down the PLL|
|RST<br>~~a~~<br>~~eG~~|I<br>~~eG~~|PLL reset without resettingthe M-divider. Active high reset.<br>~~eG~~|
|RESETM<br>~~eG~~<br>~~eG~~|I<br>~~eG~~<br>~~eG~~|PLL reset - includes resettingthe M-divider. Active high reset.<br>~~eG~~<br>~~eG~~|
|RESETC<br>~~eG~~<br>~~a~~|I<br>~~eG~~|Reset for CLKOS2 output divider only. Active high reset.<br>~~eG~~|
|RESETD<br>~~a~~|I|Reset for CLKOS3 output divider only. Active high reset.|
|ENCLKOP<br>~~a~~|I|Enable PLL output CLKOP|
|ENCLKOS<br>~~a~~<br>~~eG~~|I<br>~~eG~~|Enable PLL output CLKOS whenport is active<br>~~eG~~|
|ENCLKOS2<br>~~eG~~<br>~~eG~~|I<br>~~eG~~<br>~~eG~~|Enable PLL output CLKOS2 whenport is active<br>~~eG~~<br>~~eG~~|
|ENCLKOS3<br>~~eG~~<br>~~a~~|I<br>~~eG~~|Enable PLL output CLKOS3 whenport is active<br>~~eG~~|
|PLLCLK<br>~~a~~|I|PLL data bus clock input signal|
|PLLRST<br>~~a~~|I|PLL data bus reset. This resets onlythe data bus not anyregister values.|
|PLLSTB<br>~~a~~|I<br>~~D~~|PLL data bus strobe signal|
|PLLWE<br>~~a~~<br>~~a~~|I<br>~~D~~|PLL data bus write enable signal|
|PLLADDR [4:0]<br>~~a~~<br>~~a~~|I|PLL data bus address|
|PLLDATI[7:0]<br>~~a~~|I<br>~~G~~|PLL data bus data input<br>~~G~~|
|PLLDATO[7:0]<br>~~a~~|O<br>~~G~~|PLL data bus data output<br>~~G~~|
|PLLACK<br>~~a~~|O<br>~~D~~|PLL data bus acknowledge signal|
© 2010-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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**MachXO2 Family Data Sheet Data Sheet**
## **2.5. sysMEM Embedded Block RAM Memory**
The MachXO2-640/U and larger devices contain sysMEM Embedded Block RAMs (EBRs). The EBR consists of a 9-kbit RAM, with dedicated input and output registers. This memory can be used for a wide variety of purposes including data buffering, PROM for the soft processor and FIFO.
## **sysMEM Memory Block**
The sysMEM block can implement single port, dual port, pseudo dual port, or FIFO memories. Each block can be used in a variety of depths and widths as shown in Table 2.5.
**Table 2.5. sysMEM Block Configurations**
|**Memory Mode**|**Configurations**|
|---|---|
|Single Port|8,192 x 1<br>4,096 x 2<br>2,048 x 4<br>1,024 x 9|
|True Dual Port|8,192 x 1<br>4,096 x 2<br>2,048 x 4<br>1,024 x 9|
|Pseudo Dual Port|8,192 x 1<br>4,096 x 2<br>2,048 x 4<br>1,024 x 9<br>512 x 18|
|FIFO|8,192 x 1<br>4,096 x 2<br>2,048 x 4<br>1,024 x 9<br>512 x 18|
## **Bus Size Matching**
All of the multi-port memory modes support different widths on each of the ports. The RAM bits are mapped LSB word 0 to MSB word 0, LSB word 1 to MSB word 1, and so on. Although the word size and number of words for each port varies, this mapping scheme applies to each port.
## **RAM Initialization and ROM Operation**
If desired, the contents of the RAM can be pre-loaded during device configuration. EBR initialization data can be loaded from the UFM. To maximize the number of UFM bits, initialize the EBRs used in your design to an all-zero pattern. Initializing to an all-zero pattern does not use up UFM bits. MachXO2 devices have been designed such that multiple EBRs share the same initialization memory space if they are initialized to the same pattern.
By preloading the RAM block during the chip configuration cycle and disabling the write controls, the sysMEM block can also be utilized as a ROM.
## **Memory Cascading**
Larger and deeper blocks of RAM can be created using EBR sysMEM Blocks. Typically, the Lattice design tools cascade memory transparently, based on specific design inputs.
## **Single, Dual, Pseudo-Dual Port and FIFO Modes**
Figure 2.8 shows the five basic memory configurations and their input/output names. In all the sysMEM RAM modes, the input data and addresses for the ports are registered at the input of the memory array. The output data of the memory is optionally registered at the memory array output.
© 2010-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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**MachXO2 Family Data Sheet Data Sheet**
**==> picture [486 x 346] intentionally omitted <==**
**----- Start of picture text -----**<br>
MachXO2 Family Data Sheet<br>Data Sheet<br>AD[12:0] DIA[8:0] DI[8:0]<br>DI[8:0] ADW[8:0]<br>ADA[12:0] ADB[12:0] DI[17:0] ADR[12:0]<br>CLK CLKA CLKB BE[1:0] CLKR<br>CE CEA CEB CLKW<br>OCE CER<br>EBR DO[8:0] RSTA EBR RSTB CEW EBR<br>RST WEA WEB RST DO[17:0]<br>WE CSA[2:0] CSB[2:0] OCER<br>CS[2:0] OCEA OCEB CSW[2:0] CSR[2:0]<br>DOA[8:0] DOB[8:0]<br>Ag<br>Single-Port RAM True Dual Port RAM Pseudo Dual Port RAM<br>AFF AD[12:0]<br>DI[17:0] FF<br>AEF<br>CLKW EF CLK<br>WE DO[17:0] CE<br>RST EBR ORE OCE EBR DO[17:0]<br>CLKR<br>FULLI RE RST<br>CSW[1:0] EMPTYI<br>CSR[1:0] CS[2:0]<br>RPRST<br>I<br>FIFO RAM ROM<br>**----- End of picture text -----**<br>
**Figure 2.8. sysMEM Memory Primitives**
**Table 2.6. EBR Signal Descriptions**
|**Port Name**|**Description**|**Active State**|
|---|---|---|
|CLK|Clock|Rising Clock Edge|
|CE|Clock Enable|Active High|
|OCE1|Output Clock Enable|Active High|
|RST|Reset|Active High|
|BE1|Byte Enable|Active High|
|WE|Write Enable|Active High|
|AD|Address Bus|—|
|DI|Data In|—|
|DO|Data Out|—|
|CS|Chip Select|Active High|
|AFF|FIFO RAM Almost Full Flag|—|
|FF|FIFO RAM Full Flag|—|
|AEF|FIFO RAM Almost Empty Flag|—|
|EF|FIFO RAM Empty Flag|—|
|RPRST|FIFO RAM Read Pointer Reset|—|
## **Notes:**
1. Optional signals.
2. For dual port EBR primitives a trailing ‘A’ or ‘B’ in the signal name specifies the EBR port A or port B respectively.
3. For FIFO RAM mode primitive, a trailing ‘R’ or ‘W’ in the signal name specifies the FIFO read port or write port respectively.
4. For FIFO RAM mode primitive FULLI has the same function as CSW(2) and EMPTYI has the same function as CSR(2).
5. In FIFO mode, CLKW is the write port clock, CSW is the write port chip select, CLKR is the read port clock, CSR is the read port chip select, ORE is the output read enable.
© 2010-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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The EBR memory supports three forms of write behavior for single or dual port operation:
1. **Normal** – Data on the output appears only during the read cycle. During a write cycle, the data (at the current address) does not appear on the output. This mode is supported for all data widths.
2. **Write Through** – A copy of the input data appears at the output of the same port. This mode is supported for all data widths.
3. **Read-Before-Write** – When new data is being written, the old contents of the address appears at the output.
## **FIFO Configuration**
The FIFO has a write port with data-in, CEW, WE and CLKW signals. There is a separate read port with data-out, RCE, RE and CLKR signals. The FIFO internally generates Almost Full, Full, Almost Empty and Empty Flags. The Full and Almost Full flags are registered with CLKW. The Empty and Almost Empty flags are registered with CLKR. Table 2.7 shows the range of programming values for these flags.
**Table 2.7. Programmable FIFO Flag Ranges[1]**
|**Flag Name**|**Programming Range **|
|---|---|
|Full(FF)|1 to max(upto 2N-1)|
|Almost Full(AF)|1 to Full-1|
|Almost Empty (AE)|1 to Full-1|
|Empty (EF)|0|
**Note:**
1. N = Address bit width
The FIFO state machine supports two types of reset signals: RST and RPRST. The RST signal is a global reset that clears the contents of the FIFO by resetting the read/write pointer and puts the FIFO flags in their initial reset state. The RPRST signal is used to reset the read pointer. The purpose of this reset is to retransmit the data that is in the FIFO. In these applications it is important to keep careful track of when a packet is written into or read from the FIFO.
## **Memory Core Reset**
The memory core contains data output latches for ports A and B. These are simple latches that can be reset synchronously or asynchronously. RSTA and RSTB are local signals, which reset the output latches associated with port A and port B respectively. The Global Reset (GSRN) signal resets both ports. The output data latches and associated resets for both ports are as shown in Figure 2.9.
**==> picture [290 x 191] intentionally omitted <==**
**----- Start of picture text -----**<br>
Memory Core<br>| Port A[18:0]<br>Output Data<br>Latches<br>| Port B[18:0]<br>RSTA<br>— ) ><br>RSTB<br>GSRN<br>Programmable Disable<br>**----- End of picture text -----**<br>
**Figure 2.9. Memory Core Reset**
For further information on the sysMEM EBR block, refer to Memory Usage Guide for MachXO2 Devices (FPGA-TN-02159).
© 2010-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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**MachXO2 Family Data Sheet Data Sheet**
## **EBR Asynchronous Reset**
EBR asynchronous reset or GSR (if used) can only be applied if all clock enables are low for a clock cycle before the reset is applied and released a clock cycle after the reset is released, as shown in Figure 2.10. The GSR input to the EBR is always asynchronous.
**==> picture [25 x 98] intentionally omitted <==**
**----- Start of picture text -----**<br>
Reset<br>Clock<br>Clock<br>Enable<br>**----- End of picture text -----**<br>
**Figure 2.10. EBR Asynchronous Reset (Including GSR) Timing Diagram**
If all clock enables remain enabled, the EBR asynchronous reset or GSR may only be applied and released after the EBR read and write clock inputs are in a steady state condition for a minimum of 1/fMAX (EBR clock). The reset release must adhere to the EBR synchronous reset setup time before the next active read or write clock edge.
If an EBR is pre-loaded during configuration, the GSR input must be disabled or the release of the GSR during device wake up must occur before the release of the device I/O becoming active.
These instructions apply to all EBR RAM, ROM and FIFO implementations. For the EBR FIFO mode, the GSR signal is always enabled and the WE and RE signals act like the clock enable signals in Figure 2.10. The reset timing rules apply to the RPReset input versus the RE input and the RST input versus the WE and RE inputs. Both RST and RPReset are always asynchronous EBR inputs. For more details refer to Memory Usage Guide for MachXO2 Devices (FPGA-TN-02159).
Note that there are no reset restrictions if the EBR synchronous reset is used and the EBR GSR input is disabled.
## **2.6. Programmable I/O Cells (PIC)**
The programmable logic associated with an I/O is called a PIO. The individual PIO are connected to their respective sysI/O buffers and pads. On the MachXO2 devices, the PIO cells are assembled into groups of four PIO cells called a Programmable I/O Cell or PIC. The PICs are placed on all four sides of the device.
On all the MachXO2 devices, two adjacent PIOs can be combined to provide a complementary output driver pair.
The MachXO2-640U, MachXO2-1200/U and higher density devices contain enhanced I/O capability. All PIO pairs on these larger devices can implement differential receivers. Half of the PIO pairs on the top edge of these devices can be configured as true LVDS transmit pairs. The PIO pairs on the bottom edge of these higher density devices have on-chip differential termination and also provide PCI support.
© 2010-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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**==> picture [336 x 518] intentionally omitted <==**
**----- Start of picture text -----**<br>
1 PIC<br>PIO A<br>Input Register<br>Block<br>a 4<br>Output<br>Register Block Pin<br>and Tri-state A<br>Register Block<br>PIO B<br>ie Input Register<br>Block<br>- 4<br>Output<br>Register Block Pin<br>and Tri-state B<br>Core Logic/ Register Block<br>Input Output<br>Routing Gearbox Gearbox<br>PIO C<br>Input Register<br>Block<br>= _ 2<br>Output<br>Register Block Pin<br>and Tri-state C<br>Register Block<br>i LH<br>PIO D<br>7 ee<br>Input Register<br>Block 4<br>Output<br>Register Block Pin<br>and Tri-state D<br>Register Block<br>es.<br>Notes:<br>1. Input gearbox is available only in PIC on the bottom edge of MachXO2-640U, MachXO2-1200/U and larger devices.<br>**----- End of picture text -----**<br>
2. Output gearbox is available only in PIC on the top edge of MachXO2-640U, MachXO2-1200/U and larger devices.
**Figure 2.11. Group of Four Programmable I/O Cells**
© 2010-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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**MachXO2 Family Data Sheet Data Sheet**
## **2.7. PIO**
The PIO contains three blocks: an input register block, output register block and tri-state register block. These blocks contain registers for operating in a variety of modes along with the necessary clock and selection logic.
## **Table 2.8. PIO Signal List[1]**
|**Pin Name**<br>~~Ge~~|**I/O Type **<br>~~Ge~~|**Description**<br>~~Ge~~|
|---|---|---|
|CE<br>~~Ge~~|Input<br>~~Ge~~|Clock Enable<br>~~Ge~~|
|D<br>~~Ge~~|Input<br>~~Ge~~|Pin input from sysI/O buffer<br>~~Ge~~|
|INDD<br>~~Ge~~|Output<br>~~Ge~~|Register bypassed input<br>~~Ge~~|
|INCK<br>~~Ge~~|Output<br>~~Ge~~|Clock input<br>~~Ge~~|
|Q0<br>~~GG~~|Output<br>~~GG~~|DDRpositive edge input<br>~~GG~~|
|Q1<br>~~Ge~~|Output<br>~~Ge~~|Registered input/DDR negative edge input<br>~~Ge~~|
|D0<br>~~Ge~~|Input<br>~~Ge~~|Output signal from the core(SDR and DDR)<br>~~Ge~~|
|D1<br>~~GG~~|Input<br>~~GG~~|Output signal from the core(DDR)<br>~~GG~~|
|TD|Input|Tri-state signal from the core|
|Q<br>~~GG~~|Output<br>~~GG~~|Data output signals to sysI/O Buffer<br>~~GG~~|
|TQ<br>~~GG~~<br>~~Ge~~|Output<br>~~GG~~<br>~~Ge~~|Tri-state output signals to sysI/O Buffer<br>~~GG~~<br>~~Ge~~|
|DQSR90<br>~~Ge~~|Input<br>~~Ge~~|DQS shift 90-degree read clock<br>~~Ge~~|
|DQSW90<br>~~Ge~~|Input<br>~~Ge~~|DQS shift 90-degree write clock<br>~~Ge~~|
|DDRCLKPOL<br>~~Ge~~|Input<br>~~Ge~~|DDR input registerpolaritycontrol signal from DQS<br>~~Ge~~|
|SCLK<br>~~Ge~~<br>~~GG~~|Input<br>~~Ge~~<br>~~GG~~|System clock for input and output/tri-state blocks<br>~~Ge~~<br>~~GG~~|
|RST<br>~~GG~~<br>~~Ge~~|Input<br>~~GG~~<br>~~Ge~~|Local set reset signal<br>~~GG~~<br>~~Ge~~|
**Note:**
1. Available in PIO on right edge only.
## **2.7.1. Input Register Block**
The input register blocks for the PIOs on all edges contain delay elements and registers that can be used to condition high-speed interface signals before they are passed to the device core. In addition to this functionality, the input register blocks for the PIOs on the right edge include built-in logic to interface to DDR memory.
Figure 2.12 shows the input register block for the PIOs located on the left, top and bottom edges. Figure 2.13 shows the input register block for the PIOs on the right edge.
## **Left, Top, Bottom Edges**
Input signals are fed from the sysI/O buffer to the input register block (as signal D). If desired, the input signal can bypass the register and delay elements and be used directly as a combinatorial signal (INDD), and a clock (INCK). If an input delay is desired, users can select a fixed delay. I/O on the bottom edge also have a dynamic delay, DEL[4:0]. The delay, if selected, reduces input register hold time requirements when using a global clock. The input block allows two modes of operation. In single data rate (SDR) the data is registered with the system clock (SCLK) by one of the registers in the single data rate sync register block. In Generic DDR mode, two registers are used to sample the data on the positive and negative edges of the system clock (SCLK) signal, creating two data streams.
© 2010-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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**==> picture [374 x 161] intentionally omitted <==**
**----- Start of picture text -----**<br>
INCK<br>INDD<br>D ProgrammableDelay Cell D Q Q1 D/L Q Q1<br>Q0<br>D Q D Q Q0<br>SCLK<br>**----- End of picture text -----**<br>
**Figure 2.12. MachXO2 Input Register Block Diagram (PIO on Left, Top and Bottom Edges)**
## **Right Edge**
The input register block on the right edge is a superset of the same block on the top, bottom, and left edges. In addition to the modes described above, the input register block on the right edge also supports DDR memory mode.
In DDR memory mode, two registers are used to sample the data on the positive and negative edges of the modified DQS (DQSR90) in the DDR Memory mode creating two data streams. Before entering the core, these two data streams are synchronized to the system clock to generate two data streams.
The signal DDRCLKPOL controls the polarity of the clock used in the synchronization registers. It ensures adequate timing when data is transferred to the system clock domain from the DQS domain. The DQSR90 and DDRCLKPOL signals are generated in the DQS read-write block.
**==> picture [422 x 195] intentionally omitted <==**
**----- Start of picture text -----**<br>
INCK<br>INDD<br>D ProgrammableDelay Cell D Q Q1 D Q S1 D Q D/L Q Q1<br>i H ) HADI<br>D Q Q0 D Q S0 D Q D Q Q0<br>|<br>DQSR90<br>DDRCLKPOL :<br>SCLK L ae<br>**----- End of picture text -----**<br>
**Figure 2.13. MachXO2 Input Register Block Diagram (PIO on Right Edge)**
© 2010-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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**MachXO2 Family Data Sheet Data Sheet**
## **2.7.2. Output Register Block**
The output register block registers signals from the core of the device before they are passed to the sysI/O buffers.
## **Left, Top, Bottom Edges**
In SDR mode, D0 feeds one of the flip-flops that then feeds the output. The flip-flop can be configured as a D-type register or latch.
In DDR generic mode, D0 and D1 inputs are fed into registers on the positive edge of the clock. At the next falling edge the registered D1 input is registered into the register Q1. A multiplexer running off the same clock is used to switch the mux between the outputs of registers Q0 and Q1 that feed the output.
Figure 2.14 shows the output register block on the left, top and bottom edges.
**==> picture [388 x 202] intentionally omitted <==**
**----- Start of picture text -----**<br>
|<br>Q0 Q<br>| D0 D/L Q |<br>|<br>|<br>|<br>|<br>|<br>I<br>|<br>| D1 D Q D Q Q1 |<br>|<br>| |<br>I<br>|<br>|<br>| SCLK<br>|aC c Output path<br>|<br>TD<br>| D/L Q TQ [|]<br>|<br>| [|]<br>|<br>| [|]<br>Tri-state path<br>**----- End of picture text -----**<br>
**Figure 2.14. MachXO2 Output Register Block Diagram (PIO on the Left, Top and Bottom Edges)**
## **Right Edge**
The output register block on the right edge is a superset of the output register on left, top and bottom edges of the device. In addition to supporting SDR and Generic DDR modes, the output register blocks for PIOs on the right edge include additional logic to support DDR-memory interfaces. Operation of this block is similar to that of the output register block on other edges.
In DDR memory mode, D0 and D1 inputs are fed into registers on the positive edge of the clock. At the next falling edge the registered D1 input is registered into the register Q1. A multiplexer running off the DQSW90 signal is used to switch the mux between the outputs of registers Q0 and Q1 that feed the output.
Figure 2.15 shows the output register block on the right edge.
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**==> picture [417 x 219] intentionally omitted <==**
**----- Start of picture text -----**<br>
Q0 Q<br>D0 D/L Q<br>D1 D Q D Q Q1<br>!<br>!<br>! SCLK<br>1 IN| ||<br>DQS W90 - Output Register Block |<br>_________<____-_ TTFT TTTSDD ffffcf 255252222;<br>|<br>TD T0<br>D/L Q D Q TQ |<br>po! Dp _a ima =) l |<br>Tri-state Register Block<br>**----- End of picture text -----**<br>
**Figure 2.15. MachXO2 Output Register Block Diagram (PIO on the Right Edges)**
## **2.7.3. Tri-state Register Block**
The tri-state register block registers tri-state control signals from the core of the device before they are passed to the sysI/O buffers. The block contains a register for SDR operation. In SDR, TD input feeds one of the flip-flops that then feeds the output.
The tri-state register blocks on the right edge contain an additional register for DDR memory operation. In DDR memory mode, the register TS input is fed into another register that is clocked using the DQSW90 signal. The output of this register is used as a tri-state control.
## **2.8. Input Gearbox**
Each PIC on the bottom edge has a built-in 1:8 input gearbox. Each of these input gearboxes may be programmed as a 1:7 de-serializer or as one IDDRX4 (1:8) gearbox or as two IDDRX2 (1:4) gearboxes. Table 2.9 shows the gearbox signals.
**Table 2.9. Input Gearbox Signal List**
|**Name**|**I/O Type **|**Description**|
|---|---|---|
|D|Input|High-speed data input afterprogrammable delayin PIO A input register block|
|ALIGNWD|Input|Data alignment signal from device core|
|SCLK|Input|Slow-speed system clock|
|ECLK[1:0]|Input|High-speed edge clock|
|RST|Input|Reset|
|Q[7:0]|Output|Low-speed data to device core:<br>Video RX(1:7): Q[6:0]<br>GDDRX4(1:8): Q[7:0]<br>GDDRX2(1:4)(IOL-A): Q4, Q5, Q6, Q7<br>GDDRX2(1:4)(IOL-C): Q0, Q1, Q2, Q3|
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**MachXO2 Family Data Sheet Data Sheet**
These gearboxes have three stage pipeline registers. The first stage registers sample the high-speed input data by the high-speed edge clock on its rising and falling edges. The second stage registers perform data alignment based on the control signals UPDATE and SEL0 from the control block. The third stage pipeline registers pass the data to the device core synchronized to the low-speed system clock. Figure 2.16 shows a block diagram of the input gearbox.
**==> picture [393 x 531] intentionally omitted <==**
**----- Start of picture text -----**<br>
Q0<br>Q21 D Q Q0_ D Q S0 D Q T0<br>Q10 CE<br>Q43 Lf) D Q Q21 re D Q S2 a D Q T T2 Q2<br>Q32 CE<br>Q65 Q43 S4 T4 Q4<br>D Q D Q D Q<br>Q54 CE<br>Q65 S6 T6 Q6<br>D Q D Q D Q<br>Q_6 CE<br>D<br>Q_6 S7 T7 Q7<br>D Q D Q D Q<br>Q0_(x4) CE<br>Q43_(x2)<br>Q_6 Q54<br>S5 T5 Q5<br>D Q D Q D<br>Q65 CE<br>Q54<br>Q32 S3 T3 Q3<br>D Q D Q D<br>Q43 CE<br>Q32 Q10 S1 T1 Q1<br>D Q D Q D<br>Q21 CE<br>ECLK0/1 SCLK<br>SEL0<br>UPDATE<br>**----- End of picture text -----**<br>
**Figure 2.16. Input Gearbox**
More information on the input gearbox is available in Implementing High-Speed Interfaces with MachXO2 Devices (FPGA-TN-02153).
© 2010-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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## **2.9. Output Gearbox**
Each PIC on the top edge has a built-in 8:1 output gearbox. Each of these output gearboxes may be programmed as a 7:1 serializer or as one ODDRX4 (8:1) gearbox or as two ODDRX2 (4:1) gearboxes. Table 2.10 shows the gearbox signals.
**Table 2.10. Output Gearbox Signal List**
|**Name**|**I/O Type **|**Description**|
|---|---|---|
|Q|Output|High-speed data output|
|D[7:0]|Input|Low-speed data from device core|
|Video TX(7:1): D[6:0]|—|—|
|GDDRX4(8:1): D[7:0]|—|—|
|GDDRX2(4:1)(IOL-A): D[3:0]|—|—|
|GDDRX2(4:1)(IOL-C): D[7:4]|—|—|
|SCLK|Input|Slow-speed system clock|
|ECLK[1:0]|Input|High-speed edge clock|
|RST|Input|Reset|
The gearboxes have three stage pipeline registers. The first stage registers sample the low-speed input data on the low-speed system clock. The second stage registers transfer data from the low-speed clock registers to the highspeed clock registers. The third stage pipeline registers controlled by high-speed edge clock shift and mux the high-speed data out to the sysI/O buffer. Figure 2.17 shows the output gearbox block diagram.
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**MachXO2 Family Data Sheet Data Sheet**
**==> picture [407 x 495] intentionally omitted <==**
**----- Start of picture text -----**<br>
D6 D Q T6 D Q S6 0 GND 01 D Q Q67<br>CE S7 1<br>bP 7<br>D4 D Q T4 D Q S4 0 Q67 0 D Q Q45<br>1<br>CE S5 1<br>ODDRx2_C<br>D2 D Q T2 D Q S2 0 Q45 0 D Q Q23<br>CE S3 1 1<br>QC<br>D0 D Q T0 D Q S0 0 Q23 0 D Q Q01<br>CE S1 1 1<br>Q/QA<br>D1 D Q T1 D QCE S1 S0 01 Q12 01 D Q Q10<br>D3 D Q T3 D QCE S3 S2 01 01 D Q Q32<br>ODDRx2_A<br>D5 Q D T5 D Q S5 0 0 D Q Q54<br>CE S4 1 1<br>D7 Tt Q D T7 D Q S7 0 01 D Q Q76<br>CE S6 1<br>ODDRx2_C<br>SCLK<br>SEL/0<br>UPDATE<br>ECLK0/1<br>**----- End of picture text -----**<br>
**Figure 2.17. Output Gearbox**
More information on the output gearbox is available in Implementing High-Speed Interfaces with MachXO2 Devices (FPGA-TN-02153).
© 2010-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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**MachXO2 Family Data Sheet Data Sheet**
## **2.10. DDR Memory Support**
Certain PICs on the right edge of MachXO2-640U, MachXO2-1200/U and larger devices, have additional circuitry to allow the implementation of DDR memory interfaces. There are two groups of 14 or 12 PIOs each on the right edge with additional circuitry to implement DDR memory interfaces. This capability allows the implementation of up to 16-bit wide memory interfaces. One PIO from each group contains a control element, the DQS Read/Write Block, to facilitate the generation of clock and control signals (DQSR90, DQSW90, DDRCLKPOL and DATAVALID). These clock and control signals are distributed to the other PIO in the group through dedicated low skew routing.
## **2.11. DQS Read Write Block**
Source synchronous interfaces generally require the input clock to be adjusted in order to correctly capture data at the input register. For most interfaces a PLL is used for this adjustment. However, in DDR memories the clock (referred to as DQS) is not free-running so this approach cannot be used. The DQS Read Write block provides the required clock alignment for DDR memory interfaces. DQSR90 and DQSW90 signals are generated by the DQS Read Write block from the DQS input.
In a typical DDR memory interface design, the phase relationship between the incoming delayed DQS strobe and the internal system clock (during the read cycle) is unknown. The MachXO2 family contains dedicated circuits to transfer data between these domains. To prevent set-up and hold violations, at the domain transfer between DQS (delayed) and the system clock, a clock polarity selector is used. This circuit changes the edge on which the data is registered in the synchronizing registers in the input register block. This requires evaluation at the start of each read cycle for the correct clock polarity. Prior to the read operation in DDR memories, DQS is in tri-state (pulled by termination). The DDR memory device drives DQS low at the start of the preamble state. A dedicated circuit in the DQS Read Write block detects the first DQS rising edge after the preamble state and generates the DDRCLKPOL signal. This signal is used to control the polarity of the clock to the synchronizing registers.
The temperature, voltage and process variations of the DQS delay block are compensated by a set of calibration signals (6-bit bus) from a DLL on the right edge of the device. The DLL loop is compensated for temperature, voltage and process variations by the system clock and feedback loop.
## **2.12. sysI/O Buffer**
Each I/O is associated with a flexible buffer referred to as a sysI/O buffer. These buffers are arranged around the periphery of the device in groups referred to as banks. The sysI/O buffers allow users to implement a wide variety of standards that are found in today’s systems including LVCMOS, TTL, PCI, SSTL, HSTL, LVDS, BLVDS, MLVDS and LVPECL.
Each bank is capable of supporting multiple I/O standards. In the MachXO2 devices, single-ended output buffers, ratioed input buffers (LVTTL, LVCMOS and PCI), differential (LVDS) and referenced input buffers (SSTL and HSTL) are powered using I/O supply voltage (VCCIO). Each sysI/O bank has its own VCCIO. In addition, each bank has a voltage reference, VREF, which allows the use of referenced input buffers independent of the bank VCCIO.
MachXO2-256 and MachXO2-640 devices contain single-ended ratioed input buffers and single-ended output buffers with complementary outputs on all the I/O banks. Note that the single-ended input buffers on these devices do not contain PCI clamps. In addition to the single-ended I/O buffers these two devices also have differential and referenced input buffers on all I/O. The I/O are arranged in pairs, the two pads in the pair are described as “T” and “C”, where the true pad is associated with the positive side of the differential input buffer and the comp (complementary) pad is associated with the negative side of the differential input buffer.
© 2010-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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**MachXO2 Family Data Sheet Data Sheet**
MachXO2-640U, MachXO2-1200/U, MachXO2-2000/U, MachXO2-4000 and MachXO2-7000 devices contain three types of sysI/O buffer pairs.
1. Left and Right sysI/O Buffer Pairs
The sysI/O buffer pairs in the left and right banks of the device consist of two single-ended output drivers and two single-ended input buffers (for ratioed inputs such as LVCMOS and LVTTL). The I/O pairs on the left and right of the devices also have differential and referenced input buffers.
2. Bottom sysI/O Buffer Pairs
The sysI/O buffer pairs in the bottom bank of the device consist of two single-ended output drivers and two single-ended input buffers (for ratioed inputs such as LVCMOS and LVTTL). The I/O pairs on the bottom also have differential and referenced input buffers. Only the I/O on the bottom banks have programmable PCI clamps and differential input termination. The PCI clamp is enabled after VCC and VCCIO are at valid operating levels and the device has been configured.
3. Top sysI/O Buffer Pairs
The sysI/O buffer pairs in the top bank of the device consist of two single-ended output drivers and two single-ended input buffers (for ratioed inputs such as LVCMOS and LVTTL). The I/O pairs on the top also have differential and referenced I/O buffers. Half of the sysI/O buffer pairs on the top edge have true differential outputs. The sysI/O buffer pair comprising of the A and B PIOs in every PIC on the top edge have a differential output driver. The referenced input buffer can also be configured as a differential input buffer.
## **2.12.1. Typical I/O Behavior During Power-up**
The internal power-on-reset (POR) signal is deactivated when VCC and VCCIO0 have reached VPORUP level defined in the Power-On-Reset Voltage table in the DC and Switching Characteristics section of this data sheet. After the POR signal is deactivated, the FPGA core logic becomes active. It is the user’s responsibility to ensure that all VCCIO banks are active with valid input logic levels to properly control the output logic states of all the I/O banks that are critical to the application. The default configuration of the I/O pins in a blank device is tri-state with a weak pulldown to GND (some pins such as PROGRAMN and the JTAG pins have weak pull-up to VCCIO as the default functionality). The I/O pins maintain the blank configuration until VCC and VCCIO (for I/O banks containing configuration I/O) have reached VPORUP levels at which time the I/O takes on the user-configured settings only after a proper download/configuration.
## **2.12.2. Supported Standards**
The MachXO2 sysI/O buffer supports both single-ended and differential standards. Single-ended standards can be further subdivided into LVCMOS, LVTTL, and PCI. The buffer supports the LVTTL, PCI, LVCMOS 1.2, 1.5, 1.8, 2.5, and 3.3 V standards. In the LVCMOS and LVTTL modes, the buffer has individually configurable options for drive strength, bus maintenance (weak pull-up, weak pull-down, bus-keeper latch or none) and open drain. BLVDS, MLVDS and LVPECL output emulation is supported on all devices. The MachXO2-640U, MachXO2-1200/U and higher devices support on-chip LVDS output buffers on approximately 50% of the I/O on the top bank. Differential receivers for LVDS, BLVDS, MLVDS and LVPECL are supported on all banks of MachXO2 devices. PCI support is provided in the bottom bank of theMachXO2-640U, MachXO2-1200/U and higher density devices. Table 2.11 summarizes the I/O characteristics of the MachXO2 PLDs.
Table 2.11 and Table 2.12 show the I/O standards (together with their supply and reference voltages) supported by the MachXO2 devices. For further information on utilizing the sysI/O buffer to support a variety of standards see MachXO2 sysIO Usage Guide (FPGA-TN-02158).
© 2010-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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**MachXO2 Family Data Sheet Data Sheet**
**Table 2.11. I/O Support Device by Device**
||**MachXO2-256,**<br>**MachXO2-640**|**MachXO2-640U,**<br>**MachXO2-1200**|**MachXO2-1200U,**<br>**MachXO2-2000/U,**<br>**MachXO2-4000,**<br>**MachXO2-7000**|
|---|---|---|---|
|Number of I/O Banks|4|4|6|
|Type of Input Buffers|Single-ended (all I/O banks)<br>Differential Receivers (all I/O<br>banks)|Single-ended (all I/O banks)<br>Differential Receivers (all I/O<br>banks)<br>Differential input termination<br>(bottom side)|Single-ended (all I/O banks)<br>Differential Receivers (all I/O<br>banks)<br>Differential input termination<br>(bottom side)|
|Types of Output Buffers|Single-ended buffers with<br>complementary outputs (all<br>I/O Banks)|Single-ended buffers with<br>complementary outputs (all<br>I/O banks)<br>Differential buffers with true<br>LVDS outputs (50% on top<br>side)|Single-ended buffers with<br>complementary outputs (all<br>I/O banks)<br>Differential buffers with true<br>LVDS outputs (50% on top<br>side)|
|Differential Output Emulation<br>Capability|All I/O Banks|All I/O Banks|All I/O Banks|
|PCI ClampSupport|No|Clampon bottom side only|Clampon bottom side only|
## **Table 2.12. Supported Input Standards**
|**Table 2.12. Supported Input Standards**||||||
|---|---|---|---|---|---|
||**VCCIO(Typ.)**<br>~~PT~~|||||
|**Input Standard**<br>~~CO~~|**3.3 V**<br>~~PT~~<br>~~CO~~|**2.5 V**<br>~~PT~~<br>~~CO~~|**1.8 V**<br>~~PT~~<br>~~CO~~|**1.5 V**<br>~~PT~~<br>~~CO~~|**1.2 V**<br>~~PT~~<br>~~CO~~|
|**Single Ended Interfaces**<br>~~CO~~<br>~~pT~~<br>~~GO~~||||||
|LVTTL<br>~~a~~<br>~~a~~|✔<br>~~a~~|✔2<br>~~a~~<br>~~GO~~<br>~~CO~~|✔2<br>~~a~~<br>~~GO~~<br>~~CO~~|✔2<br>~~a~~<br>~~GO~~<br>~~CO~~|—<br>~~a~~|
|LVCMOS33<br>~~a~~<br>~~a~~|✔<br>~~a~~|✔2<br>~~GO~~<br>~~a~~<br>~~CO~~|✔2<br>~~GO~~<br>~~a~~<br>~~CO~~|✔2<br>~~GO~~<br>~~a~~<br>~~CO~~|—<br>~~a~~|
|LVCMOS25<br>~~a~~|✔2|✔<br>~~CO~~<br>~~GO~~|✔2<br>~~CO~~<br>~~GO~~|✔2<br>~~CO~~|—|
|LVCMOS18<br>~~a~~|✔2|✔2<br>~~GO~~|✔<br>~~GO~~|✔2|—|
|LVCMOS15<br>~~a~~<br>~~a~~|✔2|✔2<br>~~GO~~<br>~~CO~~|✔2<br>~~GO~~<br>~~CO~~|✔|✔2|
|LVCMOS12<br>~~a~~<br>~~a~~|✔2|✔2<br>~~CO~~<br>~~CO~~|✔2<br>~~CO~~<br>~~CO~~|✔2|✔|
|PCI1<br>~~a~~<br>~~Ce~~|✔<br>~~Ce~~|—<br>~~CO~~<br>~~Ce~~|—<br>~~CO~~<br>~~Ce~~|—<br>~~Ce~~|—<br>~~Ce~~|
|SSTL18 (Class I, Class II)<br>~~a~~|✔<br>~~a~~|✔<br>~~a~~|✔<br>~~a~~|✔<br>~~a~~|—<br>~~a~~|
|SSTL25 (Class I, Class II)<br>~~a~~|✔<br>~~a~~|✔<br>~~a~~<br>~~GO~~|~~a~~<br>~~GO~~|~~a~~|—<br>~~a~~|
|HSTL18 (Class I, Class II)<br>~~a~~<br>~~Ge~~|✔<br>~~a~~<br>~~Ge~~|✔<br>~~a~~<br>~~GO~~<br>~~Ge~~|✔<br>~~a~~<br>~~GO~~<br>~~Ge~~|✔<br>~~a~~<br>~~Ge~~|—<br>~~a~~<br>~~Ge~~|
|**Differential Interfaces**<br>~~pT~~||||||
|LVDS<br>~~a~~|✔|✔<br>~~GO~~|—<br>~~GO~~|—|—|
|MIPI3<br>~~a~~<br>~~a~~|✔<br>~~a~~|✔<br>~~GO~~<br>~~a~~|—<br>~~GO~~<br>~~a~~|—<br>~~a~~|—<br>~~a~~|
|Differential SSTL18 Class I, II<br>~~a~~<br>~~Ge~~|✔<br>~~a~~<br>~~Ge~~|✔<br>~~a~~<br>~~Ge~~|✔<br>~~a~~<br>~~Ge~~|✔<br>~~a~~<br>~~Ge~~|—<br>~~a~~<br>~~Ge~~|
|Differential SSTL25 Class I, II<br>~~CO~~|✔<br>~~CO~~|✔<br>~~CO~~<br>~~CO~~|—<br>~~CO~~<br>~~CO~~|—<br>~~CO~~<br>~~CO~~|—<br>~~CO~~|
|Differential HSTL18 Class I, II<br>~~a~~|✔<br>~~a~~|✔<br>~~a~~<br>~~CO~~|✔<br>~~a~~<br>~~CO~~|✔<br>~~a~~<br>~~CO~~|—<br>~~a~~|
1. Bottom banks of MachXO2-640U, MachXO2-1200/U and higher density devices only.
2. Reduced functionality. Refer to MachXO sysIO Usage Guide (FPGA-TN-02169) for more details.
3. These interfaces can be emulated with external resistors in all devices. Refer to MIPI D-PHY Bandwidth Matrix and Implementation (FPGA-TN-02090) for more details.
© 2010-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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**MachXO2 Family Data Sheet Data Sheet**
**Table 2.13. Supported Output Standards**
|**Output Standard**<br>~~a~~|**VCCIO (Typ.)**<br>~~a~~|
|---|---|
|**Single-Ended Interfaces**||
|LVTTL<br>~~a~~<br>~~i~~|3.3<br>~~a~~<br>|
|LVCMOS33<br>~~i~~|3.3<br>|
|LVCMOS25<br>~~iGO~~|2.5<br>~~GO~~|
|LVCMOS18<br>~~GO~~<br>~~GO~~|1.8<br>~~GO~~<br>~~GO~~|
|LVCMOS15<br>~~GO~~<br>~~a~~<br>~~a~~|1.5<br>~~GO~~<br>~~G~~|
|LVCMOS12<br>~~a~~<br>~~i~~|1.2<br>|
|LVCMOS33, Open Drain<br>~~a~~<br>~~i~~|—<br>|
|LVCMOS25, Open Drain<br>~~iGO~~|—<br>~~GO~~|
|LVCMOS18, Open Drain<br>~~GO~~<br>~~a~~|—<br>~~GO~~<br>~~a~~|
|LVCMOS15, Open Drain<br>~~a~~<br>~~i~~|—<br>~~a~~|
|LVCMOS12, Open Drain<br>~~a~~<br>~~i~~<br>~~i~~|—<br>~~a~~|
|PCI333<br>~~i~~<br>~~i~~<br>~~i~~|3.3|
|SSTL25 (Class I)<br>~~i~~<br>~~i~~<br>~~i~~|2.5<br>|
|SSTL18 (Class I)<br>~~i~~<br>~~i~~|1.8<br>|
|HSTL18(Class I)<br>~~ia~~|1.8<br>~~a~~|
|**Differential Interfaces**<br>~~a~~<br>~~Re~~||
|LVDS1, 2<br>~~Re~~<br>~~a~~<br>~~Re~~|2.5, 3.3<br>~~Re~~<br>~~a~~|
|BLVDS, MLVDS, RSDS2<br>~~a~~<br>~~Re~~<br>~~Re~~|2.5<br>~~a~~|
|LVPECL2<br>~~Re~~<br>~~Re~~<br>~~Re~~|3.3|
|MIPI2<br>~~Re~~<br>~~Re~~|2.5|
|Differential SSTL18<br>~~Re~~<br>~~a~~<br>~~i~~|1.8<br>~~a~~<br>|
|Differential SSTL25<br>~~a~~<br>~~i~~|2.5<br>~~a~~<br>|
|Differential SSTL25<br>~~ia~~|1.8<br>~~a~~|
## **Notes:**
1. MachXO2-640U, MachXO2-1200/U and larger devices have dedicated LVDS buffers.
2. These interfaces can be emulated with external resistors in all devices.
© 2010-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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FPGA-DS-02056-4.3
**MachXO2 Family Data Sheet Data Sheet**
## **2.12.3. sysI/O Buffer Banks**
The numbers of banks vary between the devices of this family. MachXO2-1200U, MachXO2-2000/U and higher density devices have six I/O banks (one bank on the top, right and bottom side and three banks on the left side). The MachXO2-1200 and lower density devices have four banks (one bank per side). Figure 2.18 and Figure 2.19 show the sysI/O banks and their associated supplies for all devices.
**==> picture [271 x 201] intentionally omitted <==**
**----- Start of picture text -----**<br>
GND VCCIO0<br>Bank 0<br>VCCIO5<br>—<br>GND rit jis<br>8 | VCCIO1<br>1 a!<br>VCCIO4<br>GND 1s |<br>| GND<br>VCCIO3 1<br>GND<br>I<br>SE Bank 2<br>**----- End of picture text -----**<br>
GND VCCIO2
**Figure 2.18. MachXO2-1200U, MachXO2-2000/U, MachXO2-4000 and MachXO2-7000 Banks**
**==> picture [271 x 232] intentionally omitted <==**
**----- Start of picture text -----**<br>
GND VCCIO0<br>Bank 0<br>| TE |<br>|<br>|<br>VCCIO3 VCCIO1<br>12 2 |<br>GND \™ || GND<br>|<br>|<br>|<br>re Bank 2<br>[---=7<br>GND VCCIO2<br>**----- End of picture text -----**<br>
**Figure 2.19. MachXO2-256, MachXO2-640/U and MachXO2-1200 Banks**
© 2010-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02056-4.3
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**MachXO2 Family Data Sheet Data Sheet**
## **2.13. Hot Socketing**
The MachXO2 devices have been carefully designed to ensure predictable behavior during power-up and powerdown. Leakage into I/O pins is controlled to within specified limits. This allows for easy integration with the rest of the system. These capabilities make the MachXO2 ideal for many multiple power supply and hot-swap applications.
## **2.14. On-chip Oscillator**
Every MachXO2 device has an internal CMOS oscillator. The oscillator output can be routed as a clock to the clock tree or as a reference clock to the sysCLOCK PLL using general routing resources. The oscillator frequency can be divided by internal logic. There is a dedicated programming bit and a user input to enable/disable the oscillator. The oscillator frequency ranges from 2.08 MHz to 133 MHz. The software default value of the Master Clock (MCLK) is nominally 2.08 MHz. When a different MCLK is selected during the design process, the following sequence takes place:
1. Device powers up with a nominal MCLK frequency of 2.08 MHz.
2. During configuration, users select a different master clock frequency.
3. The MCLK frequency changes to the selected frequency once the clock configuration bits are received.
4. If the user does not select a master clock frequency, then the configuration bitstream defaults to the MCLK frequency of 2.08 MHz.
Table 2.14 lists all the available MCLK frequencies.
**Table 2.14. Available MCLK Frequencies**
|**MCLK(MHz, Nominal)**|**MCLK(MHz, Nominal)**|**MCLK(MHz, Nominal)**|
|---|---|---|
|2.08(default)|9.17|33.25|
|2.46|10.23|38|
|3.17|13.3|44.33|
|4.29|14.78|53.2|
|5.54|20.46|66.5|
|7|26.6|88.67|
|8.31|29.56|133|
© 2010-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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FPGA-DS-02056-4.3
**MachXO2 Family Data Sheet Data Sheet**
## **2.15. Embedded Hardened IP Functions and User Flash Memory**
All MachXO2 devices provide embedded hardened functions such as SPI, I[2] C and Timer/Counter. MachXO2-640/U and higher density devices also provide User Flash Memory (UFM). These embedded blocks interface through the WISHBONE interface with routing as shown in Figure 2.20.
**==> picture [363 x 218] intentionally omitted <==**
**----- Start of picture text -----**<br>
Configuration Power<br>Logic Control<br>pi J<br>Embedded Function Block (EFB)<br>2 I/O for I2C<br>I C (Primary)<br>(Primary)<br>Core EFB a I2C (Secondary) I/O for I2C<br>Logic/ WISHBONE (Secondary)<br>Routing Interface<br>SPI I/O for SPI<br>Timer/Counter<br>|<br>- a ——<br>to Ud<br>Indicates connection<br>PLL0 PLL1 UFM<br>through core logic/routing<br>**----- End of picture text -----**<br>
**Figure 2.20. MachXO2-256, MachXO2-640/U and MachXO2-1200 Banks**
## **2.15.1. Hardened I[2] C IP Core**
Every MachXO2 device contains two I[2] C IP cores. These are the primary and secondary I[2] C IP cores. Either of the two cores can be configured either as an I[2] C master or as an I[2] C slave. The only difference between the two IP cores is that the primary core has pre-assigned I/O pins whereas users can assign I/O pins for the secondary core.
When the IP core is configured as a master it is able to control other devices on the I[2] C bus through the interface. When the core is configured as the slave, the device is able to provide I/O expansion to an I[2] C Master. The I[2] C cores support the following functionality:
- Master and Slave operation
- 7-bit and 10-bit addressing
- Multi-master arbitration support
- Up to 400 kHz data transfer speed
- General call support
- Interface to custom logic through 8-bit WISHBONE interface
© 2010-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02056-4.3
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**MachXO2 Family Data Sheet Data Sheet**
**==> picture [272 x 112] intentionally omitted <==**
**----- Start of picture text -----**<br>
Configuration Power<br>Logic Control<br>EFB<br>Core I2C Function<br>Logic/<br>Routing SCL<br>WISHBONEEFB I2C Control<br>Interface Registers Logic<br>SDA<br>**----- End of picture text -----**<br>
**Figure 2.21. I[2] C Core Block Diagram**
Table 2.15 describes the signals interfacing with the I[2] C cores.
**Table 2.15. Supported Input Standards**
|**Signal Name**|**I/O**|**Description**|
|---|---|---|
|i2c_scl|Bi-directional|Bi-directional clock line of the I2C core. The signal is an output if the I2C core is in<br>master mode. The signal is an input if the I2C core is in slave mode. MUST be routed<br>directly to the pre-assigned I/O of the chip. Refer to thePinout Informationsection<br>of this document for detailed pad and pin locations of I2C ports in each MachXO2<br>device.|
|i2c_sda|Bi-directional|Bi-directional data line of the I2C core. The signal is an output when data is<br>transmitted from the I2C core. The signal is an input when data is received into the<br>I2C core. MUST be routed directly to the pre-assigned I/O of the chip. Refer to the<br>Pinout Informationsection of this document for detailed pad and pin locations of<br>I2Cports in each MachXO2 device.|
|i2c_irqo|Output|Interrupt request output signal of the I2C core. The intended usage of this signal is<br>for it to be connected to the WISHBONE master controller (i.e. a microcontroller or<br>state machine) and request an interrupt when a specific condition is met. These<br>conditions are described with the I2C register definitions.|
|cfg_wake|Output|Wake-up signal – To be connected only to the power module of the MachXO2<br>device. The signal is enabled only if the “Wakeup Enable” feature has been set<br>within the EFB GUI, I2C Tab.|
|cfg_stdby|Output|Stand-by signal – To be connected only to the power module of the MachXO2<br>device. The signal is enabled only if the “Wakeup Enable” feature has been set<br>within the EFB GUI, I2C Tab.|
## **2.15.2. Hardened SPI IP Core**
Every MachXO2 device has a hard SPI IP core that can be configured as a SPI master or slave. When the IP core is configured as a master it is able to control other SPI enabled chips connected to the SPI bus. When the core is configured as the slave, the device is able to interface to an external SPI master. The SPI IP core on MachXO2 devices supports the following functions:
- Configurable Master and Slave modes
- Full-Duplex data transfer
- Mode fault error flag with CPU interrupt capability
- Double-buffered data register
- Serial clock with programmable polarity and phase
- LSB First or MSB First Data Transfer
- Interface to custom logic through 8-bit WISHBONE interface
There are some limitations on the use of the hardened user SPI. These are defined in the following technical notes:
© 2010-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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FPGA-DS-02056-4.3
**MachXO2 Family Data Sheet Data Sheet**
- Minimizing System Interruption During Configuration Using TransFR Technology (FPGA-TN-02025) (Appendix B)
- Using User Flash Memory and Hardened Control Functions in MachXO2 Devices (FPGA-TN-02162)
**==> picture [274 x 183] intentionally omitted <==**
**----- Start of picture text -----**<br>
Configuration<br>Logic<br>EFB<br>SPI Function<br>MISO<br>Core<br>Logic/ MOSI<br>Routing<br>EFB<br>WISHBONE SPI Control SCK<br>Interface Registers Logic<br>MCSN<br>SCSN<br>**----- End of picture text -----**<br>
**Figure 2.22. SPI Core Block Diagram**
Table 2.16 describes the signals interfacing with the SPI cores.
**Table 2.16. SPI Core Signal Description**
|**Signal Name**|**I/O**|**Master/Slave**|**Description**|
|---|---|---|---|
|spi_csn[0]|O|Master|SPI master chip-select output|
|spi_csn[1..7]|O|Master|Additional SPI chip-select outputs(total upto eight slaves)|
|spi_scsn|I|Slave|SPI slave chip-select input|
|spi_irq|O|Master/Slave|Interrupt request|
|spi_clk|I/O|Master/Slave|SPI clock. Output in master mode. Input in slave mode.|
|spi_miso|I/O|Master/Slave|SPI data. Input in master mode. Output in slave mode.|
|spi_mosi|I/O|Master/Slave|SPI data. Output in master mode. Input in slave mode.|
|ufm_sn|I|Slave|Configuration Slave Chip Select (active low), dedicated for selecting the User<br>Flash Memory (UFM).|
|cfg_stdby|O|Master/Slave|Stand-by signal – To be connected only to the power module of the MachXO2<br>device. The signal is enabled only if the “Wakeup Enable” feature has been set<br>within the EFB GUI, SPI Tab.|
|cfg_wake|O|Master/Slave|Wake-up signal – To be connected only to the power module of the MachXO2<br>device. The signal is enabled only if the “Wakeup Enable” feature has been set<br>within the EFB GUI, SPI Tab.|
## **2.15.3. Hardened Timer/Counter**
MachXO2 devices provide a hard Timer/Counter IP core. This Timer/Counter is a general purpose, bi-directional, 16-bit timer/counter module with independent output compare units and PWM support. The Timer/Counter supports the following functions:
- Supports the following modes of operation:
- Watchdog timer
- Clear timer on compare match
© 2010-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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- Fast PWM
- Phase and Frequency Correct PWM
- Programmable clock input source
- Programmable input clock prescaler
- One static interrupt output to routing
- One wake-up interrupt to on-chip standby mode controller.
- Three independent interrupt sources: overflow, output compare match, and input capture
- Auto reload
- Time-stamping support on the input capture unit
- Waveform generation on the output
- Glitch-free PWM waveform generation with variable PWM period
- Internal WISHBONE bus access to the control and status registers
- Stand-alone mode with preloaded control registers and direct reset input
**==> picture [319 x 139] intentionally omitted <==**
**----- Start of picture text -----**<br>
EFB Timer/Counter<br>Core ; EFB Timer/ Control<br>RoutingLogic WISHBONE Interface RegistersCounter Logic PWM<br>4| :<br>**----- End of picture text -----**<br>
**Figure 2.23. Timer/Counter Block Diagram**
**Table 2.17. Timer/Counter Signal Description**
|**Port**|**I/O**|**Description**|
|---|---|---|
|tc_clki|I|Timer/Counter input clock signal|
|tc_rstn|I|Register tc_rstn_ena is preloaded by configuration to always keep this pin enabled|
|tc_ic|I|Input capture trigger event, applicable for non-pwm modes with WISHBONE interface. If enabled,<br>a rising edge of this signal is detected and synchronized to capture tc_cnt value into tc_icr for<br>time-stamping.|
|tc_int|O|Without WISHBONE – Can be used as overflow flag With WISHBONE – Controlled by three IRQ<br>registers|
|tc_oc|O|Timer counter output signal|
For more details on these embedded functions, refer to Using User Flash Memory and Hardened Control Functions in MachXO2 Devices (FPGA-TN-02162).
## **2.16. User Flash Memory (UFM)**
MachXO2-640/U and higher density devices provide a User Flash Memory block, which can be used for a variety of applications including storing a portion of the configuration image, initializing EBRs, to store PROM data or, as a general purpose user Flash memory. The UFM block connects to the device core through the embedded function block WISHBONE interface. Users can also access the UFM block through the JTAG, I[2] C and SPI interfaces of the device. The UFM block offers the following features:
- Non-volatile storage up to 256 kbits
© 2010-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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- 100K write cycles
- Write access is performed page-wise; each page has 128 bits (16 bytes)
- Auto-increment addressing
- WISHBONE interface
For more information on the UFM, refer to Using User Flash Memory and Hardened Control Functions in MachXO2 Devices (FPGA-TN-02162).
## **2.17. Standby Mode and Power Saving Options**
MachXO2 devices are available in three options for maximum flexibility: ZE, HC and HE devices. The ZE devices have ultra low static and dynamic power consumption. These devices use a 1.2 V core voltage that further reduces power consumption. The HC and HE devices are designed to provide high performance. The HC devices have a built-in voltage regulator to allow for 2.5 V VCC and 3.3 V VCC while the HE devices operate at 1.2 V VCC.
MachXO2 devices have been designed with features that allow users to meet the static and dynamic power requirements of their applications by controlling various device subsystems such as the bandgap, power-on-reset circuitry, I/O bank controllers, power guard, on-chip oscillator, PLLs, etc. In order to maximize power savings, MachXO2 devices support an ultra low power Stand-by mode. While most of these features are available in all three device types, these features are mainly intended for use with MachXO2 ZE devices to manage power consumption.
In the stand-by mode the MachXO2 devices are powered on and configured. Internal logic, I/O and memories are switched on and remain operational, as the user logic waits for an external input. The device enters this mode when the standby input of the standby controller is toggled or when an appropriate I[2] C or JTAG instruction is issued by an external master. Various subsystems in the device such as the band gap, power-on-reset circuitry etc can be configured such that they are automatically turned “off” or go into a low power consumption state to save power when the device enters this state. Note that the MachXO2 devices are powered on when in standby mode and all power supplies should remain in the Recommended Operating Conditions.
**Table 2.18. MachXO2 Power Saving Features Description**
|**Device Subsystem**|**Feature Description**|
|---|---|
|Bandgap|The bandgap can be turned off in standby mode. When the Bandgap is turned off,<br>analog circuitry such as the POR, PLLs, on-chip oscillator, and referenced and differential<br>I/O buffers are also turned off. Bandgapcan onlybe turned off for 1.2 V devices.|
|Power-On-Reset (POR)|The POR can be turned off in standby mode. This monitors VCC levels. In the event of<br>unsafe VCC drops, this circuit reconfigures the device. When the POR circuitry is turned<br>off, limited power detector circuitry is still active. This option is only recommended for<br>applications in which thepower supplyrails are reliable.|
|On-Chip Oscillator|The on-chip oscillator has two power saving features. It may be switched off if it is not<br>needed inyour design. It can also be turned off in Standbymode.|
|PLL|Similar to the on-chip oscillator, the PLL also has two power saving features. It can be<br>statically switched off if it is not needed in a design. It can also be turned off in Standby<br>mode. The PLL waits until all output clocks from the PLL are driven low before powering<br>off.|
|I/O Bank Controller|Referenced and differential I/O buffers (used to implement standards such as HSTL, SSTL<br>and LVDS) consume more than ratioed single-ended I/O such as LVCMOS and LVTTL. The<br>I/O bank controller allows the user to turn these I/O off dynamically on a per bank<br>selection.|
|Dynamic Clock Enable for Primary<br>Clock Nets|Each primary clock net can be dynamically disabled to save power.|
|Power Guard|Power Guard is a feature implemented in input buffers. This feature allows users to<br>switch off the input buffer when it is not needed. This feature can be used in both clock<br>and data paths. Its biggest impact is that in the standby mode it can be used to switch off<br>clock inputs that are distributed using general routingresources.|
For more details on the standby mode refer to Power Estimation and Management for MachXO2 Devices (FPGA-TN-02161).
© 2010-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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## **2.18. Power-On-Reset**
MachXO2 devices have power-on-reset circuitry to monitor VCCINT and VCCIO voltage levels during power-up and operation. At power-up, the POR circuitry monitors VCCINT and VCCIO0 (controls configuration) voltage levels. It then triggers download from the on-chip configuration Flash memory after reaching the VPORUP level specified in the Power-On-Reset Voltage table in the DC and Switching Characteristics section of this data sheet. For devices without voltage regulators (ZE and HE devices), VCCINT is the same as the VCC supply voltage. For devices with voltage regulators (HC devices), VCCINT is regulated from the VCC supply voltage. From this voltage reference, the time taken for configuration and entry into user mode is specified as Flash Download Time (tREFRESH) in the DC and Switching Characteristics section of this data sheet. Before and during configuration, the I/O are held in tristate. I/O are released to user functionality once the device has finished configuration. Note that for HC devices, a separate POR circuit monitors external VCC voltage in addition to the POR circuit that monitors the internal postregulated power supply voltage level.
Once the device enters into user mode, the POR circuitry can optionally continue to monitor VCCINT levels. If VCCINT drops below VPORDNBG level (with the bandgap circuitry switched on) or below VPORDNSRAM level (with the bandgap circuitry switched off to conserve power) device functionality cannot be guaranteed. In such a situation the POR issues a reset and begins monitoring the VCCINT and VCCIO voltage levels. VPORDNBG and VPORDNSRAM are both specified in the Power-On-Reset Voltage table in the DC and Switching Characteristics section of this data sheet.
Note that once a ZE or HE device enters user mode, users can switch off the bandgap to conserve power. When the bandgap circuitry is switched off, the POR circuitry also shuts down. The device is designed such that a minimal, low power POR circuit is still operational (this corresponds to the VPORDNSRAM reset point described in the paragraph above). However this circuit is not as accurate as the one that operates when the bandgap is switched on. The low power POR circuit emulates an SRAM cell and is biased to trip before the vast majority of SRAM cells flip. If users are concerned about the VCC supply dropping below VCC (min) they should not shut down the bandgap or POR circuit.
The power-up sequence is described below.
1. I/O tri-state with a weak pull down.
2. VCC/VCCAUX/VCCIO reaches minimal voltage level as recommended in the POR voltage table in the DC and Switching Characteristics section.
3. POR (Power-On-Reset) for internal circuitry de-asserted.
4. Device performs PPT test to ensure Flash to SRAM transfer is reliable.
5. Flash to SRAM transfer.
6. SRAM Done bit set.
7. Device wake up sequence including GSR.
8. Device is active.
## **2.19. Configuration and Testing**
This section describes the configuration and testing features of the MachXO2 family.
## **2.19.1. IEEE 1149.1-Compliant Boundary Scan Testability**
All MachXO2 devices have boundary scan cells that are accessed through an IEEE 1149.1 compliant test access port (TAP). This allows functional testing of the circuit board, on which the device is mounted, through a serial scan path that can access all critical logic nodes. Internal registers are linked internally, allowing test data to be shifted in and loaded directly onto test nodes, or test data to be captured and shifted out for verification. The test access port consists of dedicated I/O: TDI, TDO, TCK and TMS. The test access port shares its power supply with VCCIO Bank 0 and can operate with LVCMOS3.3, 2.5, 1.8, 1.5, and 1.2 standards.
For more details on boundary scan test, see Boundary Scan Testability with Lattice sysIO Capability (AN8066) and Minimizing System Interruption During Configuration Using TransFR Technology (FPGA-TN-02198).
© 2010-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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## **2.19.2. Device Configuration**
All MachXO2 devices contain two ports that can be used for device configuration. The Test Access Port (TAP), which supports bit-wide configuration and the sysCONFIG port which supports serial configuration through I[2] C or SPI. The TAP supports both the IEEE Standard 1149.1 Boundary Scan specification and the IEEE Standard 1532 In-System Configuration specification. There are various ways to configure a MachXO2 device:
1. Internal Flash Download
2. JTAG
3. Standard Serial Peripheral Interface (Master SPI mode) – interface to boot PROM memory
4. System microprocessor to drive a serial slave SPI port (SSPI mode)
5. Standard I[2] C Interface to system microprocessor
Upon power-up, the configuration SRAM is ready to be configured using the selected sysCONFIG port. Once a configuration port is selected, it remains active throughout that configuration cycle. The IEEE 1149.1 port can be activated any time after power-up by sending the appropriate command through the TAP port. Optionally the device can run a CRC check upon entering the user mode. This ensures that the device is configured correctly.
The sysCONFIG port has 10 dual-function pins which can be used as general purpose I/O if they are not required for configuration. See MachXO2 Programming and Configuration Usage Guide (FPGA-TN-02155) for more information about using the dual-use pins as general purpose I/O.
Lattice design software uses proprietary compression technology to compress bit-streams for use in MachXO2 devices. Use of this technology allows Lattice to provide a lower cost solution. In the unlikely event that this technology is unable to compress bitstreams to fit into the amount of on-chip Flash memory, there are a variety of techniques that can be utilized to allow the bitstream to fit in the on-chip Flash memory. For more details, refer to MachXO2 Programming and Configuration Usage Guide (FPGA-TN-02155).
The Test Access Port (TAP) has five dual purpose pins (TDI, TDO, TMS, TCK and JTAGENB). These pins are dual function pins - TDI, TDO, TMS and TCK can be used as general purpose I/O if desired. For more details, refer to MachXO2 Programming and Configuration Usage Guide (FPGA-TN-02155).
## **TransFR (Transparent Field Reconfiguration)**
TransFR is a unique Lattice technology that allows users to update their logic in the field without interrupting system operation using a simple push-button solution. For more details refer to Minimizing System Interruption During Configuration Using TransFR Technology (FPGA-TN-02198) for details.
When implementing background programming of the on-chip Flash, care must be taken for the operation of the PLL. For devices that have two PLLs (XO2-2000U, -4000 and -7000), the system must put the RPLL (Right-side PLL) in reset state during the background Flash programming. More detailed description can be found in MachXO2 Programming and Configuration Usage Guide (FPGA-TN-02155).
## **Security and One-Time Programmable Mode (OTP)**
For applications where security is important, the lack of an external bitstream provides a solution that is inherently more secure than SRAM-based FPGAs. This is further enhanced by device locking. MachXO2 devices contain security bits that, when set, prevent the readback of the SRAM configuration and non-volatile Flash memory spaces. The device can be in one of two modes:
1. Unlocked – Readback of the SRAM configuration and non-volatile Flash memory spaces is allowed.
2. Permanently Locked – The device is permanently locked.
Once set, the only way to clear the security bits is to erase the device. To further complement the security of the device, a One Time Programmable (OTP) mode is available. Once the device is set in this mode it is not possible to erase or re-program the Flash and SRAM OTP portions of the device. For more details, refer to MachXO2 Programming and Configuration Usage Guide (FPGA-TN-02155).
## **Dual Boot**
MachXO2 devices can optionally boot from two patterns, a primary bitstream and a golden bitstream. If the primary bitstream is found to be corrupt while being downloaded into the SRAM, the device shall then automatically re-boot
© 2010-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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from the golden bitstream. Note that the primary bitstream must reside in the on-chip Flash. The golden image MUST reside in an external SPI Flash. For more details, refer to MachXO2 Programming and Configuration Usage Guide (FPGA-TN-02155).
## **Soft Error Detection**
The SED feature is a CRC check of the SRAM cells after the device is configured. This check ensures that the SRAM cells were configured successfully. This feature is enabled by a configuration bit option. The Soft Error Detection can also be initiated in user mode via an input to the fabric. The clock for the Soft Error Detection circuit is generated using a dedicated divider. The undivided clock from the on-chip oscillator is the input to this divider. For low power applications users can switch off the Soft Error Detection circuit. For more details, refer to MachXO2 Soft Error Detection Usage Guide (FPGA-TN-02156).
## **2.20. TraceID**
Each MachXO2 device contains a unique (per device), TraceID that can be used for tracking purposes or for IP security applications. The TraceID is 64 bits long. Eight out of 64 bits are user-programmable, the remaining 56 bits are factory-programmed. The TraceID is accessible through the EFB WISHBONE interface and can also be accessed through the SPI, I[2] C, or JTAG interfaces.
## **2.21. Density Shifting**
The MachXO2 family has been designed to enable density migration within the same package. Furthermore, the architecture ensures a high success rate when performing design migration from lower density devices to higher density devices. In many cases, it is also possible to shift a lower utilization design targeted for a high-density device to a lower density device. However, the exact details of the final resource utilization can impact the likely success in each case. When migrating from lower to higher density or higher to lower density, ensure that all the power supplies and NC pins of the chosen devices are reviewed. For more details, refer to the MachXO2 migration files.
© 2010-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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**MachXO2 Family Data Sheet Data Sheet**
## **3. DC and Switching Characteristics**
## **3.1. Absolute Maximum Ratings**
**Table 3.1. Absolute Maximum Ratings[1, 2, 3]**
||**MachXO2 ZE/HE (1.2 V)**|**MachXO2 HC (2.5 V / 3.3 V)**|
|---|---|---|
|SupplyVoltage VCC|–0.5 V to 1.32 V|–0.5 V to 3.75 V|
|Output SupplyVoltage VCCIO|–0.5 V to 3.75 V|–0.5 V to 3.75 V|
|I/O Tristate Voltage Applied4, 5|–0.5 V to 3.75 V|–0.5 V to 3.75 V|
|Dedicated Input Voltage Applied4|–0.5 V to 3.75 V|–0.5 V to 3.75 V|
|Storage Temperature(Ambient)|–55 °C to 125 °C|–55 °C to 125 °C|
|Junction Temperature(TJ)|–40 °C to 125 °C|–40 °C to 125 °C|
## **Notes:**
1. Stress above those listed under the Absolute Maximum Ratings may cause permanent damage to the device. Functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
2. Compliance with the Lattice Thermal Management document is required.
3. All voltages referenced to GND.
4. Overshoot and undershoot of –2 V to (VIHMAX + 2) volts is permitted for a duration of <20 ns.
5. The dual function I[2] C pins SCL and SDA are limited to –0.25 V to 3.75 V or to –0.3 V with a duration of <20 ns.
## **3.2. Recommended Operating Conditions**
**Table 3.2. Recommended Operating Conditions[1]**
|**Symbol**|**Parameter**|**Min.**|**Max.**|**Units**|
|---|---|---|---|---|
|VCC1|Core Supply Voltage for 1.2 V Devices|1.14|1.26|V|
||Core Supply Voltage for 2.5 V / 3.3 V Devices|2.375|3.6|V|
|VCCIO1,2,3|I/O Driver Supply Voltage|1.14|3.6|V|
|tJCOM|Junction Temperature Commercial Operation|0|85|°C|
|tJIND|Junction Temperature Industrial Operation|–40|100|°C|
|tJAUTO|Junction Temperature Automotive Operation|–40|125|°C|
## **Notes:**
1. Like power supplies must be tied together. For example, if VCCIO and VCC are both the same voltage, they must also be the same supply.
2. See recommended voltages by I/O standard in subsequent table.
3. VCCIO pins of unused I/O banks should be connected to the VCC power supply on boards.
## **3.3. Power Supply Ramp Rates**
**Table 3.3. Power Supply Ramp Rates[1]**
|**Symbol**|**Parameter**|**Min.**|**Typ. **|**Max.**|**Units**|
|---|---|---|---|---|---|
|tRAMP IND/COM|Power supply ramp rates for all power supplies.|0.01|—|100|V/ms|
|tRAMP AUTO|Power supply ramp rates for all power supplies.|0.01|—|40|V/ms|
**Note:**
1. Assumes monotonic ramp rates.
© 2010-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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## **3.4. Power-On-Reset Voltage Levels**
**Table 3.4. Power Supply Ramp Rates[1, 2, 3, 4, 5, 6 ]**
|**Symbol**|**Parameter**|**Min.**|**Typ. **|**Max.**|**Units**|
|---|---|---|---|---|---|
|VPORUP|Power-On-Reset ramp up trip point (band gap based circuit<br>monitoringVCCINTand VCCIO0)|0.9|—|1.06|V|
|VPORUPEXT|Power-On-Reset ramp up trip point (band gap based circuit<br>monitoringexternal VCC power supply)|1.5|—|2.1|V|
|VPORDNBG|Power-On-Reset ramp down trip point (band gap based circuit<br>monitoringVCCINT)|0.75|—|0.93|V|
|VPORDNBGEXT|Power-On-Reset ramp down trip point (band gap based circuit<br>monitoringVCC)|0.98|—|1.33|V|
|VPORDNSRAM|Power-On-Reset ramp down trip point (SRAM based circuit<br>monitoringVCCINT)|—|0.6|—|V|
|VPORDNSRAMEXT|Power-On-Reset ramp down trip point (SRAM based circuit<br>monitoringVCC)|—|0.96|—|V|
## **Notes:**
1. These POR trip points are only provided for guidance. Device operation is only characterized for power supply voltages specified under recommended operating conditions.
2. For devices without voltage regulators VCCINT is the same as the VCC supply voltage. For devices with voltage regulators, VCCINT is regulated from the VCC supply voltage.
3. Note that VPORUP (min.) and VPORDNBG (max.) are in different process corners. For any given process corner VPORDNBG (max.) is always 12.0 mV below VPORUP (min.).
4. VPORUPEXT is for HC devices only. In these devices a separate POR circuit monitors the external VCC power supply.
5. VCCIO0 does not have a Power-On-Reset ramp down trip point. VCCIO0 must remain within the Recommended Operating Conditions to ensure proper operation.
6. If VCCINT or Vcc fall below VPORDNBG or VPORDNBGEXT (brown-out condition), power supplies should be held at GND for at least 200 µs before powering up.
## **3.5. Programming/Erase Specifications**
**Table 3.5. Programming/Erase Specifications**
|**Symbol**|**Parameter**|**Min.**|**Max.1**|**Units**|
|---|---|---|---|---|
|NPROGCYC|Flash Programmingcyclesper tRETENTION|—|10,000|Cycles|
||Flash functionalprogrammingcycles|—|100,000||
|tRETENTION|Data retention at 100 °C junction temperature|10|—|Years|
||Data retention at 85 °Cjunction temperature|20|—||
**Note:**
1. Maximum Flash memory reads are limited to 7.5E13 cycles over the lifetime of the product.
## **3.6. Hot Socketing Specifications**
**Table 3.6. Hot Socketing Specifications[1, 2, 3]**
|**Symbol**|**Parameter**|**Condition**|**Max.**|**Units**|
|---|---|---|---|---|
|IDK|Input or I/O leakage Current|0 < VIN < VIH (MAX)|+/–1000|µA|
## **Notes:**
1. Insensitive to sequence of VCC and VCCIO. However, assumes monotonic rise/fall rates for VCC and VCCIO.
2. 0 < VCC < VCC (MAX), 0 < VCCIO < VCCIO (MAX).
3. IDK is additive to IPU, IPD or IBH.
© 2010-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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**MachXO2 Family Data Sheet Data Sheet**
## **3.7. ESD Performance**
Refer to the MachXO2 Product Family Qualification Summary for complete qualification data, including ESD performance.
## **3.8. DC Electrical Characteristics**
Over Recommended Operating Conditions
**Table 3.7. DC Electrical Characteristics**
|**Symbol**<br>~~a~~|**Parameter**<br>~~a ~~|**Condition**<br>|**Min.**<br>|**Typ.**<br>|**Max.**<br>|**Units**<br>|
|---|---|---|---|---|---|---|
|IIL, IIH1, 4<br>~~P|~~|Input or I/O Leakage<br> <br>~~P|~~|Clamp OFF and VCCIO< VIN< VIH(MAX)<br> ~~a~~<br>~~**a**~~|—<br>~~a~~<br>~~**a**~~|—<br>~~a~~<br>~~**a**~~|+175<br>~~a~~<br>~~**a**~~|µA<br>~~a~~<br>~~**a**~~|
|||Clamp OFF and VIN= VCCIO<br>~~a~~<br>~~**a**~~|–10<br>~~a~~<br>~~**a**~~|—<br>~~a~~<br>~~**a**~~|10<br>~~a~~<br>~~**a**~~|µA<br>~~a~~<br>~~**a**~~|
|||Clamp OFF and VCCIO –0.97 V < VIN<<br>VCCIO<br>~~**a**~~|–175<br>~~**a**~~|—<br>~~**a**~~|—<br>~~**a**~~|µA<br>~~**a**~~|
|||Clamp OFF and 0 V < VIN< VCCIO–0.97 V<br>~~**a**~~|—<br>~~**a**~~|—<br>~~**a**~~|10<br>~~**a**~~|µA<br>~~**a**~~|
|||Clamp OFF and VIN= GND<br>~~**a**~~<br>~~a~~|—<br>~~**a**~~<br>~~a~~|—<br>~~**a**~~<br>~~a~~|10<br>~~**a**~~<br>~~a~~|µA<br>~~**a**~~<br>~~a~~|
|||Clamp ON and 0 V < VIN< VCCIO<br>~~**a**~~|—<br>~~**a**~~|—<br>~~**a**~~|10<br>~~**a**~~|µA<br>~~**a**~~|
|IPU<br>~~a~~|I/O Active Pull-up Current<br>~~a~~<br>~~a~~|0 < VIN< 0.7 VCCIO<br>~~a~~|–30|—|-309|µA|
|IPD<br>~~a~~<br>~~a~~|I/O Active Pull-down<br>Current<br>~~a~~<br>~~a~~<br>~~aee~~|VIL(MAX) < VIN< VCCIO<br>~~a~~<br>~~ee~~|30<br>~~ee~~|—<br>~~ee~~|305<br>~~ee~~|µA<br>~~ee~~|
|IBHLS<br>~~a~~<br>~~ee~~|Bus Hold Low sustaining<br>current<br>~~aee~~<br>~~ee~~|VIN= VIL(MAX)<br>~~ee~~<br>~~ee~~|30<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~|µA<br>~~ee~~<br>~~ee~~|
|IBHHS<br>~~a~~|Bus Hold High sustaining<br>current<br>~~ee~~|VIN= 0.7 VCCIO<br>~~ee~~|–30<br>~~ee~~|—<br>~~ee~~|—<br>~~ee~~|µA<br>~~ee~~|
|IBHLO<br>~~a~~|Bus Hold Low Overdrive<br>current<br>~~ee~~|0<VIN <VCCIO<br>~~ee~~|—<br>~~ee~~|—<br>~~ee~~|305<br>~~ee~~|µA<br>~~ee~~|
|IBHHO<br>~~a~~<br>~~a~~|Bus Hold High Overdrive<br>current<br>~~ee~~|0<VIN <VCCIO<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~|–309<br>~~ee~~<br>~~ee~~|µA<br>~~ee~~<br>~~ee~~|
|VBHT3<br>~~a~~<br>~~a~~|Bus Hold Trip Points<br>~~ee~~|—<br>~~ee~~<br>~~ee~~|VIL<br>(MAX)<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~|VIH<br>(MIN)<br>~~ee~~|V<br>~~ee~~|
|C1<br>~~a~~<br>~~a~~|I/O Capacitance2<br>~~ee~~|VCCIO= 3.3 V, 2.5 V, 1.8 V, 1.5 V, 1.2 V,<br>VCC= Typ.,VIO= 0 to VIH (MAX)<br>~~ee ~~<br>~~ee~~|3<br> ~~ee~~<br>~~ee~~|5<br>~~ee~~<br>~~ee~~|9<br>~~ee~~|pF<br>~~ee~~|
|VHYST<br>~~a~~<br>~~|~~|Hysteresis for Schmitt<br>Trigger Inputs5<br>~~ee~~|VCCIO= 3.3 V, Hysteresis = Large<br>~~ee~~<br>~~Seer~~|—<br>~~ee ~~<br>~~Seer~~|450<br> ~~ee~~<br>~~Seer~~|—<br>~~Seer~~|mV<br>~~Seer~~|
|||VCCIO= 2.5 V, Hysteresis = Large<br>~~Seer~~<br>~~a~~|—<br>~~Seer~~<br>~~a~~|250<br>~~Seer~~<br>~~a~~|—<br>~~Seer~~<br>~~a~~|mV<br>~~Seer~~<br>~~a~~|
|||VCCIO= 1.8 V, Hysteresis = Large<br>~~Seer~~<br>~~a~~<br>~~a~~|—<br>~~Seer~~<br>~~a~~<br>~~a~~|125<br>~~Seer~~<br>~~a~~<br>~~a~~|—<br>~~Seer~~<br>~~a~~<br>~~a~~|mV<br>~~Seer~~<br>~~a~~<br>~~a~~|
|||VCCIO= 1.5 V, Hysteresis = Large<br>~~Seer~~<br>~~7~~|—<br>~~Seer~~<br>~~7~~|100<br>~~Seer~~<br>~~7~~|—<br>~~Seer~~<br>~~7~~|mV<br>~~Seer~~<br>~~7~~|
|||VCCIO= 3.3 V, Hysteresis = Small<br>~~Seer~~<br>~~a~~|—<br>~~Seer~~<br>~~a~~|250<br>~~Seer~~<br>~~a~~|—<br>~~Seer~~<br>~~a~~|mV<br>~~Seer~~<br>~~a~~|
|||VCCIO= 2.5 V, Hysteresis = Small<br>~~Seer~~<br>~~a~~<br>~~a~~|—<br>~~Seer~~<br>~~a~~<br>~~a~~|150<br>~~Seer~~<br>~~a~~<br>~~a~~|—<br>~~Seer~~<br>~~a~~<br>~~a~~|mV<br>~~Seer~~<br>~~a~~<br>~~a~~|
|||VCCIO= 1.8 V, Hysteresis = Small<br>~~Seer~~<br>~~a~~<br>~~a~~|—<br>~~Seer~~<br>~~a~~<br>~~a~~|60<br>~~Seer~~<br>~~a~~<br>~~a~~|—<br>~~Seer~~<br>~~a~~<br>~~a~~|mV<br>~~Seer~~<br>~~a~~<br>~~a~~|
|||VCCIO= 1.5 V, Hysteresis = Small<br>~~Seer~~<br>~~a~~<br>~~a~~|—<br>~~Seer~~<br>~~a~~<br>~~a~~|40<br>~~Seer~~<br>~~a~~<br>~~a~~|—<br>~~Seer~~<br>~~a~~<br>~~a~~|mV<br>~~Seer~~<br>~~a~~<br>~~a~~|
2. TA 25 °C, f = 1.0 MHz.
3. Refer to VIL and VIH in the sysI/O Single-Ended DC Electrical Characteristics table of this document.
4. When VIH is higher than VCCIO, a transient current typically of 30 ns in duration or less with a peak current of 6 mA can occur on the high-tolow transition. For true LVDS output pins in MachXO2-640U, MachXO2-1200/U and larger devices, VIH must be less than or equal to VCCIO.
5. With bus keeper circuit turned on. For more details, refer to MachXO2 sysIO Usage Guide (FPGA-TN-02158).
© 2010-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02056-4.3
51
**MachXO2 Family Data Sheet Data Sheet**
## **3.9. Static Supply Current – ZE Devices**
**Table 3.8. Static Supply Current – ZE Devices[1, 2, 3, 6]**
|**Symbol**|**Parameter**|**Device**|**Typ.4**|**Units**|
|---|---|---|---|---|
|ICC|Core Power Supply|LCMXO2-256ZE|18|µA|
|||LCMXO2-640ZE|28|µA|
|||LCMXO2-1200ZE|56|µA|
|||LCMXO2-2000ZE|80|µA|
|||LCMXO2-4000ZE|124|µA|
|||LCMXO2-7000ZE|189|µA|
|ICCIO|Bank Power Supply5VCCIO= 2.5 V|All devices|1|µA|
## **Notes:**
1. For further information on supply current, refer to Power Estimation and Management for MachXO2 Devices (TN1198).
2. Assumes programmed blank pattern with the following characteristics: all outputs are tri-stated, all inputs configured as LVCMOS and held at VCCIO or GND, on-chip oscillator is off, and on-chip PLL is off. To estimate power for your specific case, refer to the Power Calculator tool.
3. Frequency = 0 MHz.
4. TJ = 25°C, power supplies at nominal voltage.
5. Does not include pull-up/pull-down.
6. To determine the MachXO2 peak start-up current data, use the Power Calculator tool.
## **3.10. Static Power Consumption Contribution of Different Components – ZE Devices**
The table below can be used for approximating static power consumption. For a more accurate power analysis for your design, use the Power Calculator tool.
**Table 3.9. Static Power Consumption Contribution of Different Components – ZE Devices**
|**Symbol**|**Parameter**|**Typ.**|**Units**|
|---|---|---|---|
|IDCBG|Bandgap DC power contribution|101|µA|
|IDCPOR|POR DC power contribution|38|µA|
|IDCIOBANKCONTROLLER|DC power contribution per I/O bank controller|143|µA|
## **3.11. Static Supply Current – HC/HE Devices**
|**Symbol**<br>~~eG~~|**Parameter**<br>~~eG~~|**Device**<br>~~eG~~|**Typ.4**<br>~~C(O~~|**Units**<br>~~C(O~~|
|---|---|---|---|---|
|ICC<br>~~eG~~<br>~~| ~~|Core Power Supply<br>~~eG~~<br>|LCMXO2-256HC<br>~~eG~~<br>~~a~~<br>~~Ss~~|1.15<br>~~C(O~~<br>~~Ss~~|mA<br>~~C(O~~<br>~~Ss~~|
|||LCMXO2-640HC<br>~~a~~<br>~~Ss~~|1.84<br>~~Ss~~|mA<br>~~Ss~~|
|||LCMXO2-640UHC<br>~~Ss~~|3.48<br>~~Ss~~|mA<br>~~Ss~~|
|||LCMXO2-1200HC<br>~~Ss~~<br>~~ee~~|3.49<br>~~Ss~~<br>~~ee~~|mA<br>~~Ss~~<br>~~ee~~|
|||LCMXO2-1200UHC<br>~~Ss~~<br>~~ee~~<br>~~ee~~|4.80<br>~~Ss~~<br>~~ee~~<br>~~ee~~|mA<br>~~Ss~~<br>~~ee~~<br>~~ee~~|
|||LCMXO2-2000HC<br>~~Ss~~<br>~~ee~~<br>~~ee~~|4.80<br>~~Ss~~<br>~~ee~~<br>~~ee~~|mA<br>~~Ss~~<br>~~ee~~<br>~~ee~~|
|||LCMXO2-2000UHC<br>~~Ss~~<br>~~a~~|8.44<br>~~Ss~~|mA<br>~~Ss~~|
|||LCMXO2-4000HC<br>~~Ss~~<br>~~a~~|8.45<br>~~Ss~~|mA<br>~~Ss~~|
|||LCMXO2-7000HC<br>~~Ss~~<br>~~a~~<br>~~ee~~|12.87<br>~~Ss~~<br>~~ee~~|mA<br>~~Ss~~<br>~~ee~~|
|||LCMXO2-2000HE<br>~~Ss~~<br>~~ee~~<br>~~ee~~|1.39<br>~~Ss~~<br>~~ee~~<br>~~ee~~|mA<br>~~Ss~~<br>~~ee~~<br>~~ee~~|
|||LCMXO2-4000HE<br>~~Ss~~<br>~~ee~~<br>~~ee~~|2.55<br>~~Ss~~<br>~~ee~~<br>~~ee~~|mA<br>~~Ss~~<br>~~ee~~<br>~~ee~~|
|||LCMXO2-7000HE<br> ~~Ss~~<br>~~a~~|4.06<br>~~Ss~~|mA<br>~~Ss~~|
|ICCIO<br>~~a~~|Bank Power Supply5VCCIO= 2.5 V|All devices|0|mA|
© 2010-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
52
FPGA-DS-02056-4.3
**MachXO2 Family Data Sheet Data Sheet**
## **Notes:**
1. For further information on supply current, refer to Power Estimation and Management for MachXO2 Devices (TN1198).
2. Assumes programmed blank pattern with the following characteristics: all outputs are tri-stated, all inputs configured as LVCMOS and held at VCCIO or GND, on-chip oscillator is off, and on-chip PLL is off. To estimate power for your specific case, refer to the Power Calculator tool.
3. Frequency = 0 MHz.
4. TJ = 25 °C, power supplies at nominal voltage.
5. Does not include pull-up/pull-down.
6. To determine the MachXO2 peak start-up current data, use the Power Calculator tool.
## **3.12. Programming and Erase Flash Supply Current – HC/HE Devices**
**Table 3.11. Programming and Erase Flash Supply Current – HC/HE Devices[1, 2, 3, 4]**
|**Symbol**<br>~~Ge~~|**Parameter**<br>~~Ge~~|**Device**<br>~~Ge~~|**Typ.5**<br>~~Ge~~|**Units**<br>~~Ge~~|
|---|---|---|---|---|
|ICC|Core Power Supply|LCMXO2-256HC<br>~~a~~|14.6|mA|
|||LCMXO2-640HC<br>~~a~~<br>~~a~~|16.1|mA|
|||LCMXO2-640UHC<br>~~es~~|18.8<br>~~es~~|mA<br>~~es~~|
|||LCMXO2-1200HC<br>~~es~~|18.8<br>~~es~~|mA<br>~~es~~|
|||LCMXO2-1200UHC<br>~~a~~|22.1|mA|
|||LCMXO2-2000HC<br>~~a~~<br>~~a~~|22.1|mA|
|||LCMXO2-2000UHC<br>~~a~~<br>~~a~~|26.8|mA|
|||LCMXO2-4000HC<br>~~a~~<br>~~a~~|26.8|mA|
|||LCMXO2-7000HC<br>~~es~~|33.2<br>~~es~~|mA<br>~~es~~|
|||LCMXO2-2000HE<br>~~es~~|18.3<br>~~es~~|mA<br>~~es~~|
|||LCMXO2-2000UHE<br>~~a~~|20.4|mA|
|||LCMXO2-4000HE<br>~~a~~<br>~~a~~|20.4|mA|
|||LCMXO2-7000HE<br>~~a~~<br>~~es~~|23.9<br>~~es~~|mA<br>~~es~~|
|ICCIO<br>~~a~~|Bank Power Supply6|All devices|0|mA|
## **Notes:**
1. For further information on supply current, refer to Power Estimation and Management for MachXO2 Devices (TN1198).
2. Assumes all inputs are held at VCCIO or GND and all outputs are tri-stated.
3. Typical user pattern.
4. JTAG programming is at 25 MHz.
5. TJ = 25 °C, power supplies at nominal voltage.
6. Per bank. VCCIO = 2.5 V. Does not include pull-up/pull-down.
## **3.13. Programming and Erase Flash Supply Current – ZE Devices**
**Table 3.12. Programming and Erase Flash Supply Current – ZE Devices[1, 2, 3, 4]**
|**Symbol**|**Parameter**|**Device**|**Typ.5**|**Units**|
|---|---|---|---|---|
|ICC|Core Power Supply|LCMXO2-256ZE|13|mA|
|||LCMXO2-640ZE|14|mA|
|||LCMXO2-1200ZE|15|mA|
|||LCMXO2-2000ZE|17|mA|
|||LCMXO2-4000ZE|18|mA|
|||LCMXO2-7000ZE|20|mA|
|ICCIO|Bank Power Supply6|All devices|0|mA|
## **Notes:**
1. For further information on supply current, refer to Power Estimation and Management for MachXO2 Devices (TN1198).
2. Assumes all inputs are held at VCCIO or GND and all outputs are tri-stated.
© 2010-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02056-4.3
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**MachXO2 Family Data Sheet Data Sheet**
3. Typical user pattern.
4. JTAG programming is at 25 MHz.
5. TJ = 25 °C, power supplies at nominal voltage.
6. Per bank. VCCIO = 2.5 V. Does not include pull-up/pull-down.
## **3.14. sysI/O Recommended Operating Conditions**
**Table 3.13. sysI/O Recommended Operating Conditions**
|**Standard**<br>~~ee~~|**VCCIO (V)**<br>~~a~~<br>~~ee~~|**VCCIO (V)**<br>~~a~~<br>~~ee~~|**VCCIO (V)**<br>~~a~~<br>~~ee~~|**VREF (V)**<br>~~a~~|**VREF (V)**<br>~~a~~|**VREF (V)**<br>~~a~~|
|---|---|---|---|---|---|---|
||**Min.**<br>~~ee~~|**Typ.**<br>~~ee~~|**Max.**<br>~~ee~~|**Min.**|**Typ.**|**Max.**|
|LVCMOS 3.3<br>~~GO~~|3.135<br>~~GO~~|3.3<br>~~GO~~|3.6<br>~~GO~~|—<br>~~GO~~|—<br>~~GO~~|—<br>~~GO~~|
|LVCMOS 2.5<br>~~eG~~|2.375<br>~~eG~~|2.5<br>~~eG~~|2.625<br>~~eG~~|—<br>~~eG~~|—<br>~~eG~~|—<br>~~eG~~|
|LVCMOS 1.8<br>~~GO~~|1.71<br>~~GO~~|1.8<br>~~GO~~|1.89<br>~~GO~~|—<br>~~GO~~|—<br>~~GO~~|—<br>~~GO~~|
|LVCMOS 1.5<br>~~GG~~|1.425<br>~~GG~~|1.5<br>~~GG~~|1.575<br>~~GG~~|—<br>~~GG~~|—<br>~~GG~~|—<br>~~GG~~|
|LVCMOS 1.2<br>~~OG~~|1.14<br>~~OG~~|1.2<br>~~OG~~|1.26<br>~~OG~~|—<br>~~OG~~|—<br>~~OG~~|—<br>~~OG~~|
|LVTTL<br>~~OG~~<br>~~GG~~|3.135<br>~~OG~~<br>~~GG~~|3.3<br>~~OG~~<br>~~GG~~|3.6<br>~~OG~~<br>~~GG~~|—<br>~~OG~~<br>~~GG~~|—<br>~~OG~~<br>~~GG~~|—<br>~~OG~~<br>~~GG~~|
|PCI3<br>~~GG~~<br>~~GG~~|3.135<br>~~GG~~<br>~~GG~~|3.3<br>~~GG~~<br>~~GG~~|3.6<br>~~GG~~<br>~~GG~~|—<br>~~GG~~<br>~~GG~~|—<br>~~GG~~<br>~~GG~~|—<br>~~GG~~<br>~~GG~~|
|SSTL25<br>~~GG~~<br>~~se~~|2.375<br>~~GG~~<br>~~se~~|2.5<br>~~GG~~<br>~~se~~|2.625<br>~~GG~~<br>~~se~~|1.15<br>~~GG~~<br>~~se~~|1.25<br>~~GG~~<br>~~se~~|1.35<br>~~GG~~<br>~~se~~|
|SSTL18<br>~~GG~~|1.71<br>~~GG~~|1.8<br>~~GG~~|1.89<br>~~GG~~|0.833<br>~~GG~~|0.9<br>~~GG~~|0.969<br>~~GG~~|
|HSTL18<br>~~GG~~|1.71<br>~~GG~~|1.8<br>~~GG~~|1.89<br>~~GG~~|0.816<br>~~GG~~|0.9<br>~~GG~~|1.08<br>~~GG~~|
|LVCMOS25R33<br>~~OG~~|3.135<br>~~OG~~|3.3<br>~~OG~~|3.6<br>~~OG~~|1.1<br>~~OG~~|1.25<br>~~OG~~|1.4<br>~~OG~~|
|LVCMOS18R33<br>~~OG~~<br>~~GG~~|3.135<br>~~OG~~<br>~~GG~~|3.3<br>~~OG~~<br>~~GG~~|3.6<br>~~OG~~<br>~~GG~~|0.75<br>~~OG~~<br>~~GG~~|0.9<br>~~OG~~<br>~~GG~~|1.05<br>~~OG~~<br>~~GG~~|
|LVCMOS18R25<br>~~GG~~<br>~~se~~|2.375<br>~~GG~~<br>~~se~~|2.5<br>~~GG~~<br>~~se~~|2.625<br>~~GG~~<br>~~se~~|0.75<br>~~GG~~<br>~~se~~|0.9<br>~~GG~~<br>~~se~~|1.05<br>~~GG~~<br>~~se~~|
|LVCMOS15R33<br>~~GG~~|3.135<br>~~GG~~|3.3<br>~~GG~~|3.6<br>~~GG~~|0.6<br>~~GG~~|0.75<br>~~GG~~|0.9<br>~~GG~~|
|LVCMOS15R25<br>~~GO~~<br>~~ee~~|2.375<br>~~GO~~<br>~~OG~~|2.5<br>~~GO~~<br>~~OG~~|2.625<br>~~GO~~<br>~~OG~~|0.6<br>~~GO~~<br>~~OG~~|0.75<br>~~GO~~<br>~~OG~~|0.9<br>~~GO~~<br>~~OG~~|
|LVCMOS12R334<br>~~ee~~<br>~~pO~~|3.135<br>~~OG~~|3.3<br>~~OG~~<br>~~GO~~|3.6<br>~~OG~~<br>~~GO~~|0.45<br>~~OG~~|0.6<br>~~OG~~|0.75<br>~~OG~~|
|LVCMOS12R254<br>~~ee~~<br>~~se~~<br>~~pO~~|2.375<br>~~OG~~<br>~~se~~|2.5<br>~~OG~~<br>~~se~~<br>~~GO~~|2.625<br>~~OG~~<br>~~se~~<br>~~GO~~|0.45<br>~~OG~~<br>~~se~~|0.6<br>~~OG~~<br>~~se~~|0.75<br>~~OG~~<br>~~se~~|
|LVCMOS10R334<br>~~se~~<br>~~pO~~<br>~~po~~|3.135<br>~~se~~|3.3<br>~~se~~<br>~~GO~~|3.6<br>~~se~~<br>~~GO~~|0.35<br>~~se~~|0.5<br>~~se~~|0.65<br>~~se~~|
|LVCMOS10R254<br>~~pO~~<br>~~po~~<br>~~pO~~|2.375<br>~~pO~~|2.5<br>~~GO~~|2.625<br>~~GO~~|0.35|0.5|0.65|
|LVDS251, 2<br>~~po~~<br>~~pO~~|2.375<br>~~pO~~|2.5<br>~~GO~~|2.625<br>~~GO~~|—|—|—|
|LVDS331, 2<br>~~pO~~<br>~~se~~<br>~~pO~~|3.135<br>~~pO~~<br>~~se~~|3.3<br>~~se~~<br>~~GO~~<br>~~GO~~|3.6<br>~~se~~<br>~~GO~~<br>~~GO~~|—<br>~~se~~|—<br>~~se~~|—<br>~~se~~|
|LVPECL1<br>~~se~~<br>~~se~~<br>~~pO~~|3.135<br>~~se~~<br>~~se~~|3.3<br>~~se~~<br>~~GO~~<br>~~se~~<br>~~GO~~|3.6<br>~~se~~<br>~~GO~~<br>~~se~~<br>~~GO~~|—<br>~~se~~<br>~~se~~|—<br>~~se~~<br>~~se~~|—<br>~~se~~<br>~~se~~|
|BLVDS1<br>~~se~~<br>~~pO~~<br>~~po~~|2.375<br>~~se~~|2.5<br>~~se~~<br>~~GO~~|2.625<br>~~se~~<br>~~GO~~|—<br>~~se~~|—<br>~~se~~|—<br>~~se~~|
|RSDS1<br>~~pO~~<br>~~po~~<br>~~po~~|2.375|2.5<br>~~GO~~|2.625<br>~~GO~~||||
|SSTL18D<br>~~po~~<br>~~po~~<br>~~pO~~|1.71<br>~~pO~~|1.8|1.89|0.833|0.9|0.969|
|SSTL25D<br>~~po~~<br>~~pO~~|2.375<br>~~pO~~|2.5|2.625|1.15|1.25|1.35|
|HSTL18D<br>~~pO~~<br>~~GG~~|1.71<br>~~pO~~<br>~~GG~~|1.8<br>~~GG~~|1.89<br>~~GG~~|0.816<br>~~GG~~|0.9<br>~~GG~~|1.08<br>~~GG~~|
## **Notes:**
1. Inputs on-chip. Outputs are implemented with the addition of external resistors.
2. MachXO2-640U, MachXO2-1200/U and larger devices have dedicated LVDS buffers.
3. Input on the bottom bank of the MachXO2-640U, MachXO2-1200/U and larger devices only.
4. Supported only for inputs and BIDIs for all ZE devices, and –6 speed grade for HE and HC devices.
© 2010-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02056-4.3
54
**MachXO2 Family Data Sheet Data Sheet**
## **3.15. sysI/O Single-Ended DC Electrical Characteristics**
**Table 3.14. sysI/O Single-Ended DC Electrical Characteristics[1, 2]**
|**Input/Output**<br>**Standard**<br>~~a~~|**VIL**<br>~~——~~<br>~~ee~~|**VIL**<br>~~——~~<br>~~ee~~|**VIH**<br>~~——~~<br>~~ee~~|**VIH**<br>~~——~~<br>~~ee~~|**VOL Max.**<br>**(V)**|**VOH Min.**<br>**(V)**|**IOL Max.4**<br>**(mA)**<br>~~a~~|**IOH Max.4**<br>**(mA)**<br>~~a~~|
|---|---|---|---|---|---|---|---|---|
||**Min. (V)3**<br>~~——~~|**Max. (V)**<br>~~——~~<br>~~ee~~|**Min. (V)**<br>~~——~~<br>~~ee~~|**Max. (V)**<br>~~——~~<br>~~ee~~|||||
|LVCMOS 3.3<br>LVTTL|-0.3|0.8<br>~~ee~~|2.0<br>~~ee~~|3.6<br>~~ee~~|0.4|VCCIO– 0.4|4<br>~~a~~|–4<br>~~a~~|
||||||||8<br>~~ee~~|–8<br>~~ee~~|
||||||||12<br>~~a~~|–12<br>~~a~~|
||||||||16<br>~~a~~|–16<br>~~a~~|
||||||||24<br>~~ee~~|–24<br>~~ee~~|
||||||0.2<br>~~a~~|VCCIO– 0.2|0.1|–0.1|
|LVCMOS 2.5|–0.3|0.7|1.7|3.6|0.4|VCCIO– 0.4|4<br>~~a~~|–4<br>~~a~~|
||||||||8<br>~~ee~~|–8<br>~~ee~~|
||||||||12<br>~~ee~~<br>~~ee~~|–12<br>~~ee~~<br>~~ee~~|
||||||||16<br>~~ee~~<br>~~a~~|–16<br>~~ee~~<br>~~a~~|
||||||0.2<br>~~J~~|VCCIO– 0.2<br>~~J~~|0.1<br>~~J~~|–0.1<br>~~J~~|
|LVCMOS 1.8|–0.3|0.35 VCCIO|0.65 VCCIO|3.6|0.4|VCCIO– 0.4|4<br>~~ee~~|–4<br>~~ee~~|
||||||||8<br>~~ee~~|–8<br>~~ee~~|
||||||||12<br>~~ee~~<br>~~ee~~|–12<br>~~ee~~<br>~~ee~~|
||||||0.2<br>~~a~~|VCCIO– 0.2<br>|0.1<br>~~ee~~<br>|–0.1<br>~~ee~~<br>~~—~~|
|LVCMOS 1.5|–0.3|0.35 VCCIO|0.65 VCCIO|3.6|0.4<br>~~aP|~~|VCCIO– 0.4<br>~~P|~~|4<br>~~P|~~|–4<br>~~P|—~~|
||||||||8<br>~~P|~~<br>~~ee~~|–8<br>~~P|—~~<br>~~ee~~|
||||||0.2<br><br>~~J~~<br>~~P|~~|VCCIO– 0.2<br><br>~~J~~<br>~~P|py~~|0.1<br><br>~~J~~<br>~~py~~|–0.1<br>~~—~~<br>~~J~~<br>~~py—~~|
|LVCMOS 1.2|–0.3|0.35 VCCIO|0.65 VCCIO|3.6|0.4<br>~~P|~~|VCCIO– 0.4<br>~~P|py~~|4<br>~~py~~|–2<br>~~py—~~|
||||||||8<br>~~py~~<br>~~ee~~|–6<br>~~py—~~<br>~~ee~~|
||||||0.2<br>~~P|~~<br>~~—~~|VCCIO– 0.2<br>~~P| py~~|0.1<br>~~py~~<br>~~ee~~|–0.1<br>~~py —~~<br>~~ee~~|
|PCI<br>~~a~~|–0.3<br>~~a~~<br>~~a~~|0.3 VCCIO<br>~~a~~<br>~~a~~|0.5 VCCIO<br>~~a~~|3.6<br>~~a~~|0.1 VCCIO|0.9 VCCIO|1.5|–0.5|
|SSTL25 Class I<br>~~a~~|–0.3<br>~~a~~<br>~~a~~|VREF– 0.18<br>~~a~~<br>~~a~~|VREF+ 0.18<br>~~a~~|3.6<br>~~a~~|0.54|VCCIO- 0.62|8|8|
|SSTL25 Class II<br>~~a~~<br><br>~~a~~|–0.3<br>~~a~~<br>|VREF– 0.18<br>~~a~~<br>~~ee~~|VREF+ 0.18<br>~~ee~~|3.6<br>~~ee~~|NA<br>~~**ee**~~|NA<br>~~**ee**~~|NA<br>~~**ee**~~|NA<br>~~**ee**~~|
|SSTL18 Class I<br>~~a~~<br>~~a~~<br>~~a~~|–0.3<br>~~a~~<br>~~a~~|VREF– 0.125<br>~~a~~<br>~~aee~~<br>~~ee~~|VREF+<br>0.125<br>~~ee~~<br>~~ee~~|3.6<br>~~ee~~<br>~~ee~~|0.40<br>~~**ee**~~|VCCIO- 0.40<br>~~**ee**~~|8<br>~~**ee**~~|8<br>~~**ee**~~|
|SSTL18 Class II<br>~~a~~<br>~~a~~|–0.3<br>~~a~~|VREF– 0.125<br>~~aee~~<br>~~ee~~|VREF+<br>0.125<br>~~ee~~<br>~~ee~~|3.6<br>~~ee~~<br>~~ee~~|NA<br>~~**ee**~~|NA<br>~~**ee**~~|NA<br>~~**ee**~~|NA<br>~~**ee**~~|
|HSTL18 Class I<br><br>~~a~~<br>~~a~~|–0.3<br><br>~~a~~|VREF– 0.1<br>~~ee~~<br>~~ee~~<br>~~a~~|VREF+ 0.1<br>~~ee~~<br>~~ee~~<br>~~a~~|3.6<br>~~ee~~<br>~~ee~~<br>~~a~~|0.40<br>~~**ee**~~<br>~~a~~|VCCIO- 0.40<br>~~**ee**~~<br>~~a~~|8<br>~~**ee**~~<br>~~a~~|8<br>~~**ee**~~<br>~~a~~|
|HSTL18 Class II<br>~~a~~<br>~~a~~|–0.3<br>~~a~~<br>~~a~~|VREF– 0.1<br>~~a~~<br>~~a~~|VREF+ 0.1<br>~~a~~<br>~~a~~|3.6<br>~~a~~<br>~~a~~|NA<br>~~a~~<br>~~a~~|NA<br>~~a~~<br>~~a~~|NA<br>~~a~~<br>~~a~~|NA<br>~~a~~<br>~~a~~|
|LVCMOS25R33<br>~~a~~|–0.3<br>~~a~~<br>~~a~~|VREF– 0.1<br>~~a~~<br>~~a~~|VREF+ 0.1<br>~~a~~|3.6<br>~~a~~|NA<br>~~a~~|NA<br>~~a~~|NA<br>~~a~~|NA<br>~~a~~|
|LVCMOS18R33<br>~~a~~|–0.3<br>~~a~~<br>~~a~~|VREF– 0.1<br>~~a~~<br>~~a~~|VREF+ 0.1<br>~~a~~<br>~~a~~|3.6<br>~~a~~<br>~~a~~|NA<br>~~a~~<br>~~a~~|NA<br>~~a~~<br>~~a~~|NA<br>~~a~~<br>~~a~~|NA<br>~~a~~<br>~~a~~|
|LVCMOS18R25<br>~~a~~|–0.3<br>~~a~~|VREF– 0.1<br>~~a~~|VREF+ 0.1<br>~~a~~|3.6<br>~~a~~|NA<br>~~a~~|NA<br>~~a~~|NA<br>~~a~~|NA<br>~~a~~|
|LVCMOS15R33<br>~~a~~<br>~~a~~|–0.3<br>~~a~~<br>~~a~~|VREF– 0.1<br>~~a~~<br>~~a~~|VREF+ 0.1<br>~~a~~<br>~~a~~|3.6<br>~~a~~<br>~~a~~|NA<br>~~a~~<br>~~a~~|NA<br>~~a~~<br>~~a~~|NA<br>~~a~~<br>~~a~~|NA<br>~~a~~<br>~~a~~|
|LVCMOS15R25<br>~~a~~<br>~~a~~<br>~~a~~|–0.3<br>~~a~~<br>~~a~~|VREF– 0.1<br>~~a~~<br>~~a~~<br>~~ee~~|VREF+ 0.1<br>~~a~~<br>~~a~~<br>~~ee~~|3.6<br>~~a~~<br>~~a~~<br>~~ee~~|NA<br>~~a~~<br>~~a~~<br>~~ee~~|NA<br>~~a~~<br>~~a~~<br>~~ee~~|NA<br>~~a~~<br>~~a~~<br>~~ee~~|NA<br>~~a~~<br>~~a~~<br>~~ee~~|
|LVCMOS12R33<br>~~a~~<br>~~a~~<br>~~a~~<br>~~a~~|–0.3<br>~~a~~<br>~~a~~|VREF– 0.1<br>~~a~~<br>~~a~~<br>~~ee~~<br>~~ee~~|VREF+ 0.1<br>~~a~~<br>~~a~~<br>~~ee~~<br>~~ee~~|3.6<br>~~a~~<br>~~a~~<br>~~ee~~<br>~~ee~~|0.40<br>~~a~~<br>~~a~~<br>~~ee~~<br>~~ee~~|NA Open<br>Drain<br>~~a~~<br>~~a~~<br>~~ee~~<br>~~ee~~|24, 16, 12,<br>8, 4<br>~~a~~<br>~~a~~<br>~~ee~~<br>~~ee~~|NA Open<br>Drain<br>~~a~~<br>~~a~~<br>~~ee~~<br>~~ee~~|
|LVCMOS12R25<br>~~a~~<br>~~a~~<br>~~a~~<br>~~a~~|–0.3<br>~~a~~<br>|VREF– 0.1<br>~~a~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>|VREF+ 0.1<br>~~a~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>|3.6<br>~~a~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>|0.40<br>~~a~~<br>~~ee~~<br>~~ee~~<br>~~**e**~~<br>|NA Open<br>Drain<br>~~a~~<br>~~ee~~<br>~~ee~~<br>~~**e**e~~|16, 12, 8, 4<br>~~a~~<br>~~ee~~<br>~~ee~~<br>~~e~~|NA Open<br>Drain<br>~~a~~<br>~~ee~~<br>~~ee~~<br>~~e~~|
|LVCMOS10R33<br>~~a~~<br>~~a~~<br>~~a~~|–0.3<br>|VREF– 0.1<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>|VREF+ 0.1<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>|3.6<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>|0.40<br>~~ee~~<br>~~ee~~<br>~~**e**~~<br>|NA Open<br>Drain<br>~~ee~~<br>~~ee~~<br>~~**e**e~~|24, 16, 12,<br>8, 4<br>~~ee~~<br>~~ee~~<br>~~e~~|NA Open<br>Drain<br>~~ee~~<br>~~ee~~<br>~~e~~|
|LVCMOS10R25<br>~~a~~<br>~~a e~~|–0.3<br>~~e~~|VREF– 0.1<br>~~ee~~<br>~~ee~~<br>~~e~~|VREF+ 0.1<br>~~ee~~<br>~~ee~~<br>~~e~~|3.6<br>~~ee~~<br>~~ee~~<br>~~e~~|0.40<br>~~ee~~<br>~~**e**~~<br>~~e~~|NA Open<br>Drain<br>~~ee~~<br>~~**e**e~~|16, 12, 8, 4<br>~~ee~~<br>~~e~~|NA Open<br>Drain<br>~~ee~~<br>~~e~~|
© 2010-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02056-4.3
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**MachXO2 Family Data Sheet Data Sheet**
## **Notes:**
1. MachXO2 devices allow LVCMOS inputs to be placed in I/O banks where VCCIO is different from what is specified in the applicable JEDEC specification. This is referred to as a ratioed input buffer. In a majority of cases this operation follows or exceeds the applicable JEDEC specification. The cases where MachXO2 devices do not meet the relevant JEDEC specification are documented in the table below.
2. MachXO2 devices allow for LVCMOS referenced I/O which follow applicable JEDEC specifications. For more details about mixed mode operation, refer to MachXO2 sysIO Usage Guide (FPGA-TN-02158).
3. The dual function I[2] C pins SCL and SDA are limited to a VIL min of –0.25 V or to –0.3 V with a duration of <10 ns.
4. For electromigration, the average DC current sourced or sinked by I/O pads between two consecutive VCCIO or GND pad connections, or between the last VCCIO or GND in an I/O bank and the end of an I/O bank, as shown in the Logic Signal Connections table (also shown as I/O grouping) shall not exceed a maximum of n * 8 mA. “n” is the number of I/O pads between the two consecutive bank VCCIO or GND connections or between the last VCCIO and GND in a bank and the end of a bank. I/O Grouping can be found in the Data Sheet Pin Tables, which can also be generated from the Lattice Diamond software.
|**Input Standard**|**VCCIO (V)**|**VIL Max.(V)**|
|---|---|---|
|LVCMOS 33|1.5|0.685|
|LVCMOS 25|1.5|0.687|
|LVCMOS 18|1.5|0.655|
## **3.16. sysI/O Differential Electrical Characteristics**
The LVDS differential output buffers are available on the top side of MachXO2-640U, MachXO2-1200/U and higher density devices in the MachXO2 PLD family.
## **3.16.1. LVDS**
Over Recommended Operating Conditions
**Table 3.15. LVDS**
|**Parameter**<br>**Symbol**<br>~~a~~|**Parameter Description**<br>~~ee~~|**Test Conditions**<br>~~ee~~<br>~~ee~~|**Min.**<br>~~ee~~<br>~~eee~~|**Typ.**<br>~~ee~~<br>~~ee~~<br>~~eee~~|**Max.**<br>~~ee~~<br>~~ee~~<br>~~eee~~|**Units**<br>~~ee~~<br>~~ee~~<br>~~eee~~|
|---|---|---|---|---|---|---|
|VINP, VINM<br>~~Ne~~|Input Voltage<br>~~Ne~~|VCCIO= 3.3 V<br>~~Ne~~<br>~~ee~~|0<br>~~Ne~~<br>~~eee~~|—<br>~~ee~~<br>~~Ne~~<br>~~eee~~|2.605<br>~~ee~~<br>~~Ne~~<br>~~eee~~|V<br>~~ee~~<br>~~Ne~~<br>~~eee~~|
|||VCCIO= 2.5 V<br>~~Ne~~<br>~~ee~~<br>~~oo~~|0<br>~~Ne~~<br>~~eee~~<br>~~oo~~|—<br>~~Ne~~<br>~~eee~~<br>~~oo~~|2.05<br>~~Ne~~<br>~~eee~~<br>~~oo~~|V<br>~~Ne~~<br>~~eee~~<br>~~oo~~|
|VTHD<br>~~a~~<br>~~ee~~|Differential Input Threshold<br>~~a~~|—<br>~~ee ~~<br>~~a~~<br>~~a~~|±100<br> ~~eee~~<br>~~a~~<br>~~a~~|—<br>~~eee~~<br>~~a~~<br>~~a~~|~~eee~~<br>~~a~~<br>~~a~~|mV<br>~~eee~~<br>~~a~~<br>~~a~~|
|VCM<br>~~a~~<br>~~ee~~|Input Common Mode Voltage<br>~~a~~|VCCIO= 3.3 V<br>~~a~~<br>~~a~~|0.05<br>~~a~~<br>~~a~~|—<br>~~a~~<br>~~a~~|2.6<br>~~a~~<br>~~a~~|V<br>~~a~~<br>~~a~~|
|||VCCIO= 2.5 V<br>~~a~~|0.05<br>~~a~~|—<br>~~a~~|2.0<br>~~a~~|V<br>~~a~~|
|IIN<br>~~ee~~<br>~~a~~|Input current<br>~~a~~|Power on<br>~~a~~<br>~~a~~|—<br>~~a~~<br>~~a~~|—<br>~~a~~<br>~~a~~|±10<br>~~a~~<br>~~a~~|µA<br>~~a~~<br>~~a~~|
|VOH<br>~~a~~|Output high voltage for VOPor VOM<br>~~a~~|RT= 100 Ω<br>~~a~~|—<br>~~a~~|1.375<br>~~a~~|—<br>~~a~~|V<br>~~a~~|
|VOL<br>~~a~~|Output low voltage for VOPor VOM<br>~~a~~|RT= 100 Ω<br>~~a~~|0.90<br>~~a~~|1.025<br>~~a~~|—<br>~~a~~|V<br>~~a~~|
|VOD<br>~~a~~|Output voltage differential<br>~~a~~|(VOP- VOM), RT= 100 Ω<br>~~a~~|250<br>~~a~~<br>~~ee~~|350<br>~~a~~<br>~~ee~~|450<br>~~a~~<br>~~ee~~|mV<br>~~a~~<br>~~ee~~|
|VOD<br>~~a~~<br>~~a~~|Change in VODbetween high and<br>low<br>~~a~~<br>~~a~~<br>~~ee~~|—<br>~~a~~<br>~~a~~<br>~~ee~~|—<br>~~a~~<br>~~a~~<br>~~ee~~<br>~~ee~~|—<br>~~a~~<br>~~a~~<br>~~ee~~<br>~~ee~~|50<br>~~a~~<br>~~a~~<br>~~ee~~<br>~~ee~~|mV<br>~~a~~<br>~~a~~<br>~~ee~~<br>~~ee~~|
|VOS<br>~~a~~<br>~~a~~|Output voltage offset<br>~~a~~<br>~~ee~~<br>~~a~~|(VOP+ VOM)/2, RT= 100 Ω<br>~~a~~<br>~~ee~~<br>~~a~~|1.125<br>~~a~~<br>~~ee~~<br>~~ee ~~<br>~~a~~|1.20<br>~~a~~<br>~~ee~~<br> ~~ee~~<br>~~a~~|1.395<br>~~a~~<br>~~ee~~<br>~~ee~~<br>~~a~~|V<br>~~a~~<br>~~ee~~<br>~~ee~~<br>~~a~~|
|VOS<br>~~a~~<br>~~a~~|Change in VOSbetween H and L<br>~~a~~<br>~~a~~|—<br>~~a~~<br>~~a~~|—<br>~~a~~<br>~~a~~|—<br>~~a~~<br>~~a~~|50<br>~~a~~<br>~~a~~|mV<br>~~a~~<br>~~a~~|
|IOSD<br>~~a~~|Output short circuit current<br>~~a~~|VOD= 0 V driver outputs shorted<br>~~a~~|—<br>~~a~~|—<br>~~a~~|24<br>~~a~~|mA<br>~~a~~|
© 2010-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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**MachXO2 Family Data Sheet Data Sheet**
## **3.16.2. LVDS Emulation**
MachXO2 devices can support LVDS outputs via emulation (LVDS25E). The output is emulated using complementary LVCMOS outputs in conjunction with resistors across the driver outputs on all devices. The scheme shown in Figure 3.1 is one possible solution for LVDS standard implementation. Resistor values in Figure 3.1 are industry standard values for 1% resistors.
**==> picture [324 x 119] intentionally omitted <==**
**----- Start of picture text -----**<br>
VCCIO = 2.5<br>158<br>8 mA<br>Zo = 100<br>+<br>VCCIO = 2.5 140 100 –<br>158<br>8 mA<br>Onc- pih Oc-ff pih Oc-ff pih Onc- pih<br>Emulated<br>LVDS Buffer<br>**----- End of picture text -----**<br>
**==> picture [79 x 5] intentionally omitted <==**
**----- Start of picture text -----**<br>
Note: All resistors are ±1%.<br>**----- End of picture text -----**<br>
**Figure 3.1. LVDS Using External Resistors (LVDS25E)**
## **Table 3.16. LVDS25E DC Conditions**
Over Recommended Operating Conditions
**Table 3.17. LVDS25E DC Conditions**
|**Parameter**|**Description**|**Typ. **|**Units**|
|---|---|---|---|
|ZOUT|Output impedance|20|Ω|
|RS|Driver series resistor|158|Ω|
|RP|Driverparallel resistor|140|Ω|
|RT|Receiver termination|100|Ω|
|VOH|Output high voltage|1.43|V|
|VOL|Output low voltage|1.07|V|
|VOD|Output differential voltage|0.35|V|
|VCM|Output common mode voltage|1.25|V|
|ZBACK|Back impedance|100.5|Ω|
|IDC|DC output current|6.03|mA|
© 2010-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02056-4.3
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**MachXO2 Family Data Sheet Data Sheet**
## **3.16.3. BLVDS**
The MachXO2 family supports the BLVDS standard through emulation. The output is emulated using complementary LVCMOS outputs in conjunction with resistors across the driver outputs. The input standard is supported by the LVDS differential input buffer. BLVDS is intended for use when multi-drop and bi-directional multi-point differential signaling is required. The scheme shown in Figure 3.2 is one possible solution for bi-directional multi-point differential signals.
**==> picture [374 x 199] intentionally omitted <==**
**----- Start of picture text -----**<br>
Heavily loaded backplane, effective Zo ~ 45 to 90 Ω differential<br>2.5 V 2.5 V<br>80 45-90 Ohms 45-90 Ohms<br>1 6 mA 16 mA<br>80<br>2.5 V 2.5 V<br>80<br>16 mA 16 mA<br>80 80 80 80<br>. . .<br>+ +<br>– –<br>2.5 V 2.5V – 2.5 V 2.5 V –<br>16 mA 16 mA 16 mA 16 mA<br>KA Y KA Y<br>+ +<br>**----- End of picture text -----**<br>
**Figure 3.2. BLVDS Multi-point Output Example**
Over Recommended Operating Conditions
**Table 3.18. BLVDS DC Conditions[1]**
|**Symbol**<br>~~ee~~|**Description**<br>~~ee~~|**Nominal**<br>~~ee~~|**Nominal**<br>~~ee~~|**Units**<br>~~ee~~|
|---|---|---|---|---|
|||**Zo = 45**<br>~~ee~~|**Zo = 90**<br>~~ee~~||
|ZOUT<br>~~ee~~|Output impedance<br>~~ee~~|20<br>~~ee~~|20<br>~~ee~~|Ω<br>~~ee~~|
|RS|Driver series resistance|80|80|Ω|
|RTLEFT|Left end termination|45|90|Ω|
|RTRIGHT<br>~~————~~|Right end termination<br>~~————~~|45<br>~~————~~|90<br>~~————~~|Ω<br>~~————~~|
|VOH<br>~~————~~|Output high voltage<br>~~————~~|1.376<br>~~————~~|1.480<br>~~————~~|V<br>~~————~~|
|VOL<br>~~————~~<br>~~————~~|Output low voltage<br>~~————~~<br>~~————~~|1.124<br>~~————~~<br>~~————~~|1.020<br>~~————~~<br>~~————~~|V<br>~~————~~<br>~~————~~|
|VOD<br>~~————~~|Output differential voltage<br>~~————~~|0.253<br>~~————~~|0.459<br>~~————~~|V<br>~~————~~|
|VCM<br>~~—————————~~|Output common mode voltage<br>~~—————————~~|1.250<br>~~—————————~~|1.250<br>~~—————————~~|V<br>~~—————————~~|
|IDC<br>~~—————————~~|DC output current<br>~~—————————~~|11.236<br>~~—————————~~|10.204<br>~~—————————~~|mA<br>~~—————————~~|
**Note:**
1. For input buffer, see Table 3.15.
© 2010-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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FPGA-DS-02056-4.3
**MachXO2 Family Data Sheet Data Sheet**
## **3.16.4. LVPECL**
The MachXO2 family supports the differential LVPECL standard through emulation. This output standard is emulated using complementary LVCMOS outputs in conjunction with resistors across the driver outputs on all the devices. The LVPECL input standard is supported by the LVDS differential input buffer. The scheme shown in Differential LVPECL is one possible solution for point-to-point signals.
**==> picture [353 x 132] intentionally omitted <==**
**----- Start of picture text -----**<br>
V CCIO = 3.3 V<br>|<br>93 Ohms<br>, |<br>16 mA |_|<br>|<br>V CCIO = 3.3 V +<br>196 Ohms 100 ohms –<br>||<br>93 Ohms<br>3<br>16 mA<br>Transmission line, Zo = 100 Ohm differential<br>> [|<br>On-chip Off-chip Off-chip On-chip<br>**----- End of picture text -----**<br>
**Figure 3.3. Differential LVPECL**
Over Recommended Operating Conditions
**Table 3.19. LVPECL DC Conditions[1]**
|**Symbol**|**Description**|**Nominal**|**Units**|
|---|---|---|---|
|ZOUT|Output impedance|20|Ω|
|RS|Driver series resistor|93|Ω|
|RP|Driver parallel resistor|196|Ω|
|RT|Receiver termination|100|Ω|
|VOH|Output high voltage|2.05|V|
|VOL|Output low voltage|1.25|V|
|VOD|Output differential voltage|0.80|V|
|VCM|Output common mode voltage|1.65|V|
|ZBACK|Back impedance|100.5|Ω|
|IDC|DC output current|12.11|mA|
## **Note:**
1. For input buffer, see Table 3.15.
For further information on LVPECL, BLVDS and other differential interfaces, see details of additional technical documentation at the end of the data sheet.
© 2010-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02056-4.3
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**MachXO2 Family Data Sheet Data Sheet**
## **3.16.5. RSDS**
The MachXO2 family supports the differential RSDS standard. The output standard is emulated using complementary LVCMOS outputs in conjunction with resistors across the driver outputs on all the devices. The RSDS input standard is supported by the LVDS differential input buffer. The scheme shown in Figure 3.4 is one possible solution for RSDS standard implementation. Use LVDS25E mode with suggested resistors for RSDS operation. Resistor values in Figure 3.4 are industry standard values for 1% resistors.
**==> picture [359 x 160] intentionally omitted <==**
**----- Start of picture text -----**<br>
VCCIO = 2.5 V<br>|<br>294<br>, |<br>8 mA |_|<br>Zo = 100<br>|<br>VCCIO = 2.5 V +<br>121 100 –<br>||<br>294<br>,<br>8 mA<br>> |<br>On-chip Off-chip Off-chip On-chip<br>Emulated<br>RSDS Buffer<br>**----- End of picture text -----**<br>
**Figure 3.4. RSDS (Reduced Swing Differential Standard)**
**Table 3.20. RSDS DC Conditions**
|**Parameter**|**Description**|**Typical**|**Units**|
|---|---|---|---|
|ZOUT|Output impedance|20|Ω|
|RS|Driver series resistor|294|Ω|
|RP|Driverparallel resistor|121|Ω|
|RT|Receiver termination|100|Ω|
|VOH|Output high voltage|1.35|V|
|VOL|Output low voltage|1.15|V|
|VOD|Output differential voltage|0.20|V|
|VCM|Output common mode voltage|1.25|V|
|ZBACK|Back impedance|101.5|Ω|
|IDC|DC output current|3.66|mA|
© 2010-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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## **3.17. Typical Building Block Function Performance – HC/HE Devices**
## **3.17.1. Pin-to-Pin Performance (LVCMOS25 12 mA Drive)**
**Table 3.21. Pin-to-Pin Performance (LVCMOS25 12 mA Drive)**
|**Function**|**–6 Timing**|**Units**|
|---|---|---|
|**Basic Functions**|||
|16-bit decoder|8.9|ns|
|4:1 MUX|7.5|ns|
|16:1 MUX|8.3|ns|
## **3.17.2. Register-to-Register Performance**
**Table 3.22. Register-to-Register Performance[1]**
|**Function**|**–6 Timing**|**Units**|
|---|---|---|
|**Basic Functions**|||
|16:1 MUX|412|MHz|
|16-bit adder|297|MHz|
|16-bit counter|324|MHz|
|64-bit counter|161|MHz|
|**Embedded Memory Functions**|||
|1024 × 9 True-Dual Port RAM<br>(Write Through or Normal, EBR output<br>registers)|183|MHz|
|**Distributed Memory Functions**|||
|16 × 4 Pseudo-Dual Port RAM (one PFU)|500|MHz|
**Note:**
1. The above timing numbers are generated using the Diamond design tool. Exact performance may vary with device and tool version. The tool uses internal parameters that have been characterized but are not tested on every device. Commercial timing numbers are shown at 85 °C and 1.14 V. Other operating conditions, including industrial and automotive, can be extracted from the Diamond software.
© 2010-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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## **3.18. Typical Building Block Function Performance – ZE Devices**
## **3.18.1. Pin-to-Pin Performance (LVCMOS25 12 mA Drive)**
## **Table 3.23. Pin-to-Pin Performance (LVCMOS25 12 mA Drive)**
|**Function**|**-6 Timing**|**Units**|
|---|---|---|
|**Basic Functions**|||
|16-bit decoder|8.9|ns|
|4:1 MUX|7.5|ns|
|16:1 MUX|8.3|ns|
## **3.18.2. Register-to-Register Performance**
## **Table 3.24. Register-to-Register Performance[1]**
|**Function**|**-6 Timing**|**Units**|
|---|---|---|
|**Basic Functions**|||
|16:1 MUX|412|MHz|
|16-bit adder|297|MHz|
|16-bit counter|324|MHz|
|64-bit counter|161|MHz|
|**Embedded Memory Functions**|||
|1024x9 True-Dual Port RAM<br>(Write Through or Normal, EBR output registers)|183|MHz|
|**Distributed Memory Functions**|||
|16x4 Pseudo-Dual Port RAM (one PFU)|500|MHz|
**Note:**
1. The above timing numbers are generated using the Diamond design tool. Exact performance may vary with device and tool version. The tool uses internal parameters that have been characterized but are not tested on every device.
## **3.19. Derating Logic Timing**
Logic timing provided in the following sections of the data sheet and the Lattice design tools are worst case numbers in the operating range. Actual delays may be much faster. Lattice design tools can provide logic timing numbers at a particular temperature and voltage.
© 2010-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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## **3.20. Maximum sysI/O Buffer Performance**
**Table 3.25. Maximum sysI/O Buffer Performance**
|**I/O Standard**<br>~~eC~~|**Max. Speed**<br>~~eC~~|**Units**<br>~~eC~~|
|---|---|---|
|LVDS25<br>~~a~~|400<br>~~a~~|MHz<br>~~a~~|
|LVDS25E<br>~~a~~|150<br>~~a~~|MHz<br>~~a~~|
|RSDS25<br>~~a~~|150<br>~~a~~|MHz<br>~~a~~|
|RSDS25E<br>~~a~~|150<br>~~a~~|MHz<br>~~a~~|
|BLVDS25<br>~~a~~|150<br>~~a~~|MHz<br>~~a~~|
|BLVDS25E<br>~~a~~|150<br>~~a~~|MHz<br>~~a~~|
|MLVDS25<br>~~a~~|150<br>~~a~~|MHz<br>~~a~~|
|MLVDS25E<br>~~a~~|150<br>~~a~~|MHz<br>~~a~~|
|LVPECL33<br>~~a~~|150<br>~~a~~|MHz<br>~~a~~|
|LVPECL33E<br>~~a~~<br>~~a~~|150<br>~~a~~<br>~~a~~|MHz<br>~~a~~<br>~~a~~|
|SSTL25_I<br>~~a~~<br>~~a~~|150<br>~~a~~<br>~~a~~|MHz<br>~~a~~<br>~~a~~|
|SSTL25_II<br>~~a~~<br>~~a~~|150<br>~~a~~<br>~~a~~|MHz<br>~~a~~<br>~~a~~|
|SSTL25D_I<br>~~a~~|150<br>~~a~~|MHz<br>~~a~~|
|SSTL25D_II<br>~~a~~|150<br>~~a~~|MHz<br>~~a~~|
|SSTL18_I<br>~~a~~|150<br>~~a~~|MHz<br>~~a~~|
|SSTL18_II<br>~~a~~<br>~~a~~|150<br>~~a~~<br>~~a~~|MHz<br>~~a~~<br>~~a~~|
|SSTL18D_I<br>~~a~~<br>~~a~~|150<br>~~a~~<br>~~a~~|MHz<br>~~a~~<br>~~a~~|
|SSTL18D_II<br>~~a~~<br>~~a~~|150<br>~~a~~<br>~~a~~|MHz<br>~~a~~<br>~~a~~|
|HSTL18_I<br>~~a~~|150<br>~~a~~|MHz<br>~~a~~|
|HSTL18_II<br>~~a~~|150<br>~~a~~|MHz<br>~~a~~|
|HSTL18D_I<br>~~a~~<br>~~a~~|150<br>~~a~~<br>~~a~~|MHz<br>~~a~~<br>~~a~~|
|HSTL18D_II<br>~~a~~<br>~~a~~|150<br>~~a~~<br>~~a~~|MHz<br>~~a~~<br>~~a~~|
|PCI33<br>~~a~~|134<br>~~a~~|MHz<br>~~a~~|
|LVTTL33<br>~~a~~|150<br>~~a~~|MHz<br>~~a~~|
|LVTTL33D<br>~~a~~|150<br>~~a~~|MHz<br>~~a~~|
|LVCMOS33<br>~~a~~<br>~~a~~|150<br>~~a~~<br>~~a~~|MHz<br>~~a~~<br>~~a~~|
|LVCMOS33D<br>~~a~~<br>~~a~~|150<br>~~a~~<br>~~a~~|MHz<br>~~a~~<br>~~a~~|
|LVCMOS25<br>~~a~~|150<br>~~a~~|MHz<br>~~a~~|
|LVCMOS25D<br>~~a~~|150<br>~~a~~|MHz<br>~~a~~|
|LVCMOS25R33<br>~~a~~|150<br>~~a~~|MHz<br>~~a~~|
|LVCMOS18<br>~~a~~<br>~~a~~|150<br>~~a~~<br>~~a~~|MHz<br>~~a~~<br>~~a~~|
|LVCMOS18D<br>~~a~~<br>~~a~~|150<br>~~a~~<br>~~a~~|MHz<br>~~a~~<br>~~a~~|
|LVCMOS18R33<br>~~a~~<br>~~a~~|150<br>~~a~~<br>~~a~~|MHz<br>~~a~~<br>~~a~~|
|LVCMOS18R25<br>~~a~~|150<br>~~a~~|MHz<br>~~a~~|
|LVCMOS15<br>~~a~~|150<br>~~a~~|MHz<br>~~a~~|
|LVCMOS15D<br>~~a~~|150<br>~~a~~|MHz<br>~~a~~|
|LVCMOS15R33<br>~~a~~<br>~~a~~|150<br>~~a~~<br>~~a~~|MHz<br>~~a~~<br>~~a~~|
|LVCMOS15R25<br>~~a~~<br>~~a~~|150<br>~~a~~<br>~~a~~|MHz<br>~~a~~<br>~~a~~|
|LVCMOS12<br>~~a~~|91<br>~~a~~|MHz<br>~~a~~|
|LVCMOS12D<br>~~a~~|91<br>~~a~~|MHz<br>~~a~~|
© 2010-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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## **3.21. MachXO2 External Switching Characteristics – HC/HE Devices**
Over Recommended Operating Conditions
**Table 3.26. MachXO2 External Switching Characteristics – HC/HE Devices[1, 2, 3, 4, 5, 6, 7]**
|**Parameter**<br>~~**a**~~|**Description**|**Device**<br>~~ee~~|**–6**<br>~~a~~|**–6**<br>~~a~~|**–5**|**–5**|**–4**|**–4**|**Units**|
|---|---|---|---|---|---|---|---|---|---|
||||**Min.**<br>~~a~~|**Max.**|**Min.**|**Max.**|**Min.**|**Max.**||
|**Clocks**<br>~~**a**~~<br>~~ee a~~||||||||||
|**Primary Clocks**<br>~~eS~~||||||||||
|fMAX_PRI8<br>~~eS~~<br>~~ee~~<br>~~SR~~|Frequency for Primary<br>Clock Tree<br>~~eS~~<br>~~ee~~|All MachXO2 devices<br>~~eS~~<br>~~ee~~<br>~~oo~~|—<br>~~eS~~<br>~~ee~~<br>~~oo~~|388<br>~~eS~~<br>~~ee~~<br>~~oo~~|—<br>~~eS~~<br>~~ee~~<br>~~oo~~|323<br>~~eS~~<br>~~ee~~<br>~~oo~~|—<br>~~eS~~<br>~~ee~~<br>~~oo~~|269<br>~~eS~~<br>~~ee~~<br>~~oo~~|MHz<br>~~eS~~<br>~~ee~~<br>~~oo~~|
|tW_PRI<br>~~SR~~|Clock Pulse Width for<br>PrimaryClock|All MachXO2 devices<br>~~oo~~|0.5<br>~~oo~~|—<br>~~oo~~|0.6<br>~~oo~~|—<br>~~oo~~|0.7<br>~~oo~~|—<br>~~oo~~|ns<br>~~oo~~|
|tSKEW_PRI<br>~~SR~~|Primary Clock Skew Within<br>a Device|MachXO2-256HC-HE<br>~~oo~~|—<br>~~oo~~|912<br>~~oo~~|—<br>~~oo~~|939<br>~~oo~~|—<br>~~oo~~|975<br>~~oo~~|ps<br>~~oo~~|
|||MachXO2-640HC-HE<br>~~a~~|—<br>~~a~~|844<br>~~a~~|—<br>~~a~~|871<br>~~a~~|—<br>~~a~~|908<br>~~a~~|ps<br>~~a~~|
|||MachXO2-1200HC-HE<br>~~a~~<br>~~a~~|—<br>~~a~~<br>~~a~~|868<br>~~a~~<br>~~a~~|—<br>~~a~~<br>~~a~~|902<br>~~a~~<br>~~a~~|—<br>~~a~~<br>~~a~~|951<br>~~a~~<br>~~a~~|ps<br>~~a~~<br>~~a~~|
|||MachXO2-2000HC-HE<br>~~a~~|—<br>~~a~~|867<br>~~a~~|—<br>~~a~~|897<br>~~a~~|—<br>~~a~~|941<br>~~a~~|ps<br>~~a~~|
|||MachXO2-4000HC-HE<br>~~a~~|—<br>~~a~~|865<br>~~a~~|—<br>~~a~~|892<br>~~a~~|—<br>~~a~~|931<br>~~a~~|ps<br>~~a~~|
|||MachXO2-7000HC-HE<br>~~a~~<br>~~a~~|—<br>~~a~~<br>~~a~~|902<br>~~a~~<br>~~a~~|—<br>~~a~~<br>~~a~~|942<br>~~a~~<br>~~a~~|—<br>~~a~~<br>~~a~~|989<br>~~a~~<br>~~a~~|ps<br>~~a~~<br>~~a~~|
|**Edge Clock**<br>~~a~~<br>~~a~~<br>~~eeeeee~~||||||||||
|fMAX_EDGE8<br>~~a~~<br>~~ee~~|Frequency for Edge Clock<br>~~a~~<br>~~ee~~|MachXO2-1200 and<br>larger devices<br>~~a~~<br>~~ee~~<br>~~eee~~|—<br>~~a~~<br>~~ee~~<br>~~eee~~|400<br>~~a~~<br>~~ee~~<br>~~eee~~|—<br>~~a~~<br>~~ee~~<br>~~eee~~|333<br>~~a~~<br>~~ee~~<br>~~eee~~|—<br>~~a~~<br>~~ee~~<br>~~eee~~|278<br>~~a~~<br>~~ee~~<br>~~eee~~|MHz<br>~~a~~<br>~~ee~~<br>~~eee~~|
|**Pin-LUT-Pin Propagation Delay**<br>~~ee~~<br>~~eee eee~~<br>~~a~~||||||||||
|tPD<br>~~eee~~|Best case propagation<br>delaythrough one LUT-4<br>~~eee~~|All MachXO2 devices<br>~~eee~~|—<br>~~eee~~|6.72<br>~~eee~~|—<br>~~eee~~|6.96<br>~~eee~~|—<br>~~eee~~|7.24<br>~~eee~~|ns<br>~~eee~~|
|**General I/O Pin Parameters (Using Primary Clock without PLL)**<br>~~a~~||||||||||
|tCO|Clock to Output – PIO<br>Output Register|MachXO2-256HC-HE<br>~~a~~|—<br>~~a~~|7.13<br>~~a~~|—<br>~~a~~|7.30<br>~~a~~|—<br>~~a~~|7.57<br>~~a~~|ns<br>~~a~~|
|||MachXO2-640HC-HE<br>~~a~~<br>~~a~~|—<br>~~a~~<br>~~a~~|7.15<br>~~a~~<br>~~a~~|—<br>~~a~~<br>~~a~~|7.30<br>~~a~~<br>~~a~~|—<br>~~a~~<br>~~a~~|7.57<br>~~a~~<br>~~a~~|ns<br>~~a~~<br>~~a~~|
|||MachXO2-1200HC-HE<br>~~a~~<br>~~a~~|—<br>~~a~~<br>~~a~~|7.44<br>~~a~~<br>~~a~~|—<br>~~a~~<br>~~a~~|7.64<br>~~a~~<br>~~a~~|—<br>~~a~~<br>~~a~~|7.94<br>~~a~~<br>~~a~~|ns<br>~~a~~<br>~~a~~|
|||MachXO2-2000HC-HE<br>~~a~~<br>~~a~~|—<br>~~a~~<br>~~a~~|7.46<br>~~a~~<br>~~a~~|—<br>~~a~~<br>~~a~~|7.66<br>~~a~~<br>~~a~~|—<br>~~a~~<br>~~a~~|7.96<br>~~a~~<br>~~a~~|ns<br>~~a~~<br>~~a~~|
|||MachXO2-4000HC-HE<br>~~a~~|—<br>~~a~~|7.51<br>~~a~~|—<br>~~a~~|7.71<br>~~a~~|—<br>~~a~~|8.01<br>~~a~~|ns<br>~~a~~|
|||MachXO2-7000HC-HE<br>~~a~~|—<br>~~a~~|7.54<br>~~a~~|—<br>~~a~~|7.75<br>~~a~~|—<br>~~a~~|8.06<br>~~a~~|ns<br>~~a~~|
|tSU|Clock to Data Setup – PIO<br>Input Register|MachXO2-256HC-HE<br>~~a~~|–0.06<br>~~a~~|—<br>~~a~~|–0.06<br>~~a~~|—<br>~~a~~|–0.06<br>~~a~~|—<br>~~a~~|ns<br>~~a~~|
|||MachXO2-640HC-HE<br>~~a~~<br>~~a~~|–0.06<br>~~a~~<br>~~a~~|—<br>~~a~~<br>~~a~~|–0.06<br>~~a~~<br>~~a~~|—<br>~~a~~<br>~~a~~|–0.06<br>~~a~~<br>~~a~~|—<br>~~a~~<br>~~a~~|ns<br>~~a~~<br>~~a~~|
|||MachXO2-1200HC-HE<br>~~a~~<br>~~a~~|–0.17<br>~~a~~<br>~~a~~|—<br>~~a~~<br>~~a~~|–0.17<br>~~a~~<br>~~a~~|—<br>~~a~~<br>~~a~~|–0.17<br>~~a~~<br>~~a~~|—<br>~~a~~<br>~~a~~|ns<br>~~a~~<br>~~a~~|
|||MachXO2-2000HC-HE<br>~~a~~<br>~~a~~|–0.20<br>~~a~~<br>~~a~~|—<br>~~a~~<br>~~a~~|–0.20<br>~~a~~<br>~~a~~|—<br>~~a~~<br>~~a~~|–0.20<br>~~a~~<br>~~a~~|—<br>~~a~~<br>~~a~~|ns<br>~~a~~<br>~~a~~|
|||MachXO2-4000HC-HE<br>~~a~~|–0.23<br>~~a~~|—<br>~~a~~|–0.23<br>~~a~~|—<br>~~a~~|–0.23<br>~~a~~|—<br>~~a~~|ns<br>~~a~~|
|||MachXO2-7000HC-HE<br>~~a~~|–0.23<br>~~a~~|—<br>~~a~~|–0.23<br>~~a~~|—<br>~~a~~|–0.23<br>~~a~~|—<br>~~a~~|ns<br>~~a~~|
|tH|Clock to Data Hold – PIO<br>Input Register|MachXO2-256HC-HE<br>~~a~~<br>~~a~~|1.75<br>~~a~~<br>~~a~~|—<br>~~a~~<br>~~a~~|1.95<br>~~a~~<br>~~a~~|—<br>~~a~~<br>~~a~~|2.16<br>~~a~~<br>~~a~~|—<br>~~a~~<br>~~a~~|ns<br>~~a~~<br>~~a~~|
|||MachXO2-640HC-HE<br>~~a~~<br>~~a~~|1.75<br>~~a~~<br>~~a~~|—<br>~~a~~<br>~~a~~|1.95<br>~~a~~<br>~~a~~|—<br>~~a~~<br>~~a~~|2.16<br>~~a~~<br>~~a~~|—<br>~~a~~<br>~~a~~|ns<br>~~a~~<br>~~a~~|
|||MachXO2-1200HC-HE<br>~~a~~<br>~~a~~|1.88<br>~~a~~<br>~~a~~|—<br>~~a~~<br>~~a~~|2.12<br>~~a~~<br>~~a~~|—<br>~~a~~<br>~~a~~|2.36<br>~~a~~<br>~~a~~|—<br>~~a~~<br>~~a~~|ns<br>~~a~~<br>~~a~~|
|||MachXO2-2000HC-HE<br>~~a~~|1.89<br>~~a~~|—<br>~~a~~|2.13<br>~~a~~|—<br>~~a~~|2.37<br>~~a~~|—<br>~~a~~|ns<br>~~a~~|
|||MachXO2-4000HC-HE<br>~~a~~|1.94<br>~~a~~|—<br>~~a~~|2.18<br>~~a~~|—<br>~~a~~|2.43<br>~~a~~|—<br>~~a~~|ns<br>~~a~~|
|||MachXO2-7000HC-HE<br>~~a~~<br>~~a~~|1.98<br>~~a~~<br>~~a~~|—<br>~~a~~<br>~~a~~|2.23<br>~~a~~<br>~~a~~|—<br>~~a~~<br>~~a~~|2.49<br>~~a~~<br>~~a~~|—<br>~~a~~<br>~~a~~|ns<br>~~a~~<br>~~a~~|
© 2010-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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|**Parameter**<br>~~ee~~|**Description**<br>~~ee~~<br>~~po~~|**Device**<br>~~ee~~<br>~~po~~|**–6**<br>~~ee~~<br>~~eeeee~~|**–6**<br>~~ee~~<br>~~eeeee~~|**–5**<br>~~ee~~<br>~~eee~~|**–5**<br>~~ee~~<br>~~eee~~|**–4**<br>~~ee~~<br>~~eee~~|**–4**<br>~~ee~~<br>~~eee~~|**Units**<br>~~ee~~|
|---|---|---|---|---|---|---|---|---|---|
||||**Min.**<br>~~ee~~<br>~~ee~~|**Max.**<br>~~ee~~<br>~~eee~~|**Min.**<br>~~ee~~<br>~~eee~~|**Max.**<br>~~ee~~<br>~~eee~~|**Min.**<br>~~ee~~<br>~~eee~~|**Max.**<br>~~ee~~<br>~~eee~~||
|tSU_DEL|Clock to Data Setup – PIO<br>Input Register with Data<br>Input Delay<br>~~po~~<br>~~po~~<br>~~po~~<br>~~po~~|MachXO2-256HC-HE<br>~~po~~<br>~~po~~|1.42<br>~~ee~~|—<br>~~eee~~|1.59<br>~~eee~~|—<br>~~eee~~|1.96<br>~~eee~~|—<br>~~eee~~|ns|
|||MachXO2-640HC-HE<br>~~po~~<br>~~po~~|1.41<br>~~ee~~|—<br>~~eee~~|1.58<br>~~eee~~|—<br>~~eee~~|1.96<br>~~eee~~|—<br>~~eee~~|ns|
|||MachXO2-1200HC-HE<br>~~po~~<br>~~eG~~|1.63<br>~~eG~~|—<br>~~eG~~|1.79<br>~~eG~~|—<br>~~eG~~|2.17<br>~~eG~~|—<br>~~eG~~|ns<br>~~eG~~|
|||MachXO2-2000HC-HE<br>~~se~~|1.61<br>~~se~~|—<br>~~se~~|1.76<br>~~se~~|—<br>~~se~~|2.13<br>~~se~~|—<br>~~se~~|ns<br>~~se~~|
|||MachXO2-4000HC-HE<br>~~se~~<br>~~po~~|1.66<br>~~se ~~|—<br> ~~ee~~|1.81<br>~~ee~~|—<br>~~ee~~|2.19|—|ns|
|||MachXO2-7000HC-HE<br>~~po~~<br>~~po~~|1.53|—|1.67|—|2.03|—|ns|
|tH_DEL|Clock to Data Hold – PIO<br>Input Register with Input<br>Data Delay<br>~~po~~<br>~~po~~<br>~~po~~<br>~~po~~|MachXO2-256HC-HE<br>~~po~~<br>~~po~~|–0.24|—|–0.24|—|–0.24|—|ns|
|||MachXO2-640HC-HE<br>~~po~~<br>~~eG~~|–0.23<br>~~eG~~|—<br>~~eG~~|–0.23<br>~~eG~~|—<br>~~eG~~|–0.23<br>~~eG~~|—<br>~~eG~~|ns<br>~~eG~~|
|||MachXO2-1200HC-HE<br>~~se~~<br>~~po~~|–0.24<br>~~se~~|—<br>~~se~~|–0.24<br>~~se~~|—<br>~~se~~|–0.24<br>~~se~~|—<br>~~se~~|ns<br>~~se~~|
|||MachXO2-2000HC-HE<br>~~po~~<br>~~po~~|–0.23|—|–0.23|—|–0.23|—|ns|
|||MachXO2-4000HC-HE<br>~~po~~<br>~~po~~|–0.25|—|–0.25|—|–0.25|—|ns|
|||MachXO2-7000HC-HE<br>~~po~~<br>~~po~~|–0.21<br>~~po~~|—<br>~~po~~|–0.21<br>~~po~~|—<br>~~po~~|–0.21<br>~~po~~|—<br>~~po~~|ns<br>~~po~~|
|fMAX_IO|Clock Frequency of I/O and<br>PFU Register|All MachXO2 devices|—|388|—|323|—|269|MHz|
|**General I/O Pin Parameters (Using Edge Clock without PLL)**<br>~~|~~<br>~~po~~||||||||||
|tCOE|Clock to Output – PIO<br>Output Register<br>~~po~~<br>~~po~~<br>~~po~~|MachXO2-1200HC-HE<br>~~po~~<br>~~po~~|—<br>~~ee~~|7.53<br>~~ee~~|—<br>~~ee~~|7.76<br>~~ee~~|—<br>~~ee~~|8.10|ns|
|||MachXO2-2000HC-HE<br>~~po~~<br>~~ee~~<br>~~po~~|—<br>~~ee~~<br>~~ee~~|7.53<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~|7.76<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~|8.10<br>~~ee~~|ns<br>~~ee~~|
|||MachXO2-4000HC-HE<br>~~ee~~<br>~~po~~<br>~~po~~|—<br>~~ee~~<br>~~ee~~|7.45<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~|7.68<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~|8.00<br>~~ee~~|ns<br>~~ee~~|
|||MachXO2-7000HC-HE<br>~~po~~<br>~~po~~|—<br>~~ee~~|7.53<br>~~ee ~~|—<br> ~~ee~~|7.76<br>~~ee~~|—<br>~~ee~~|8.10|ns|
|tSUE|Clock to Data Setup – PIO<br>Input Register<br>~~po~~<br>~~po~~<br>~~po~~|MachXO2-1200HC-HE<br>~~po~~<br>~~po~~|–0.19<br>~~po~~|—<br>~~po~~|–0.19<br>~~po~~|—<br>~~po~~|–0.19<br>~~po~~|—<br>~~po~~|ns<br>~~po~~|
|||MachXO2-2000HC-HE<br>~~po~~<br>~~po~~|–0.19<br>~~po~~|—<br>~~po~~|–0.19<br>~~po~~|—<br>~~po~~|–0.19<br>~~po~~|—<br>~~po~~|ns<br>~~po~~|
|||MachXO2-4000HC-HE<br>~~po~~<br>~~po~~|–0.16<br>~~ee~~|—<br>~~ee~~|–0.16<br>~~Ge~~|—|–0.16|—|ns|
|||MachXO2-7000HC-HE<br>~~po~~<br>~~ee~~<br>~~po~~|–0.19<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~|–0.19<br>~~ee~~<br>~~Ge~~|—<br>~~ee~~|–0.19<br>~~ee~~|—<br>~~ee~~|ns<br>~~ee~~|
|tHE|Clock to Data Hold – PIO<br>Input Register<br>~~po~~<br>~~po~~<br>~~po~~|MachXO2-1200HC-HE<br>~~ee~~<br>~~po~~|1.97<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~|2.24<br>~~ee~~<br>~~Ge~~|—<br>~~ee~~|2.52<br>~~ee~~|—<br>~~ee~~|ns<br>~~ee~~|
|||MachXO2-2000HC-HE<br>~~po~~<br>~~po~~<br>~~po~~|1.97<br>~~ee~~<br>~~po~~|—<br>~~ee~~<br>~~po~~|2.24<br>~~Ge~~<br>~~po~~|—<br>~~po~~|2.52<br>~~po~~|—<br>~~po~~|ns<br>~~po~~|
|||MachXO2-4000HC-HE<br>~~po~~<br>~~po~~|1.89|—|2.16|—|2.43|—|ns|
|||MachXO2-7000HC-HE<br>~~po~~<br>~~po~~|1.97<br>~~ee~~|—<br>~~ee~~|2.24<br>~~se~~|—<br>~~se~~|2.52|—|ns|
|tSU_DELE|Clock to Data Setup – PIO<br>Input Register with Data<br>Input Delay<br>~~po~~<br>~~po~~|MachXO2-1200HC-HE<br>~~po~~<br>~~ee~~|1.56<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~|1.69<br>~~ee~~<br>~~se~~|—<br>~~ee~~<br>~~se~~|2.05<br>~~ee~~|—<br>~~ee~~|ns<br>~~ee~~|
|||MachXO2-2000HC-HE<br>~~ee~~<br>~~se~~|1.56<br>~~ee~~<br>~~ee~~<br>~~se~~|—<br>~~ee~~<br>~~ee ~~<br>~~eG~~|1.69<br>~~ee~~<br> ~~se~~<br>~~eG~~|—<br>~~ee~~<br>~~se~~<br>~~eG~~|2.05<br>~~ee~~|—<br>~~ee~~|ns<br>~~ee~~|
|||MachXO2-4000HC-HE<br>~~se~~<br>~~po~~<br>~~po~~|1.74<br>~~se ~~<br>~~po~~|—<br> ~~eG~~<br>~~po~~|1.88<br>~~eG~~<br>~~po~~|—<br>~~eG~~<br>~~po~~|2.25<br>~~po~~|—<br>~~po~~|ns<br>~~po~~|
|||MachXO2-7000HC-HE<br>~~po~~|1.66<br>~~ee~~|—<br>~~ee~~|1.81<br>~~se~~|—<br>~~se~~|2.17|—|ns|
|tH_DELE|Clock to Data Hold – PIO<br>Input Register with Input<br>Data Delay<br>~~po~~<br>~~po~~<br>~~po~~|MachXO2-1200HC-HE<br>~~po~~<br>~~ee~~|–0.23<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~|–0.23<br>~~ee~~<br>~~se~~|—<br>~~ee~~<br>~~se~~|–0.23<br>~~ee~~|—<br>~~ee~~|ns<br>~~ee~~|
|||MachXO2-2000HC-HE<br>~~ee~~<br>~~se~~<br>~~po~~|–0.23<br>~~ee~~<br>~~ee~~<br>~~se~~|—<br>~~ee~~<br>~~ee ~~<br>~~eG~~|–0.23<br>~~ee~~<br> ~~se~~<br>~~eG~~|—<br>~~ee~~<br>~~se~~<br>~~eG~~|–0.23<br>~~ee~~|—<br>~~ee~~|ns<br>~~ee~~|
|||MachXO2-4000HC-HE<br>~~se~~<br>~~po~~<br>~~po~~|–0.34<br>~~se ~~|—<br> ~~eG~~|–0.34<br>~~eG~~|—<br>~~eG~~|–0.34|—|ns|
|||MachXO2-7000HC-HE<br>~~po~~<br>~~po~~|–0.29|—|–0.29|—|–0.29|—|ns|
|**General I/O Pin Parameters (Using Primary Clock with PLL)**<br>~~po~~<br>~~Pe~~||||||||||
|tCOPLL|Clock to Output – PIO<br>Output Register|MachXO2-1200HC-HE<br>~~eG~~|—<br>~~eG~~<br>~~ee~~|5.97<br>~~eG~~<br>~~ee~~|—<br>~~eG~~|6.00<br>~~eG~~|—<br>~~eG~~|6.13<br>~~eG~~|ns<br>~~eG~~|
|||MachXO2-2000HC-HE<br>~~ee~~|—<br>~~ee~~<br>~~ee~~|5.98<br>~~ee~~<br>~~ee~~|—<br>~~ee~~|6.01<br>~~ee~~|—<br>~~ee~~|6.14<br>~~ee~~|ns<br>~~ee~~|
|||MachXO2-4000HC-HE<br>~~ee~~<br>~~se~~|—<br>~~ee~~<br>~~ee~~<br>~~se~~|5.99<br>~~ee~~<br>~~ee~~<br>~~eG~~|—<br>~~ee~~<br>~~eG~~|6.02<br>~~ee~~<br>~~eG~~|—<br>~~ee~~|6.16<br>~~ee~~|ns<br>~~ee~~|
|||MachXO2-7000HC-HE<br>~~se~~<br>~~se~~|—<br>~~se ~~<br>~~se ~~|6.02<br> ~~eG~~<br> ~~eG~~|—<br>~~eG~~<br>~~eG~~|6.06<br>~~eG~~<br>~~eG~~|—|6.20|ns|
|tSUPLL|Clock to Data Setup – PIO<br>Input Register<br>~~po~~|MachXO2-1200HC-HE<br>~~po~~|0.36<br>~~po~~|—<br>~~po~~<br>~~eG~~|0.36<br>~~po~~<br>~~eG~~|—<br>~~po~~<br>~~eG~~|0.65<br>~~po~~|—<br>~~po~~|ns<br>~~po~~|
|||MachXO2-2000HC-HE<br>~~ee~~<br>~~po~~|0.36<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~eG~~<br>~~ee~~|0.36<br>~~ee~~<br>~~eG~~|—<br>~~ee~~<br>~~eG~~|0.63<br>~~ee~~|—<br>~~ee~~|ns<br>~~ee~~|
|||MachXO2-4000HC-HE<br>~~ee~~<br>~~po~~|0.35<br>~~ee~~<br>~~ee~~|—<br>~~eG~~<br>~~ee~~<br>~~ee~~|0.35<br>~~eG~~<br>~~ee~~|—<br>~~eG~~<br>~~ee~~|0.62<br>~~ee~~|—<br>~~ee~~|ns<br>~~ee~~|
|||MachXO2-7000HC-HE<br>~~ee~~<br>~~po~~|0.34<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~|0.34<br>~~ee~~|—<br>~~ee~~|0.59<br>~~ee~~|—<br>~~ee~~|ns<br>~~ee~~|
© 2010-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02056-4.3
65
**MachXO2 Family Data Sheet Data Sheet**
|**Parameter**<br>~~a~~|**Description**<br>~~a~~|**Device**<br>~~ee~~|**–6**<br>~~aee~~|**–6**<br>~~aee~~|**–5**<br>~~eeee~~|**–5**<br>~~eeee~~|**–4**<br>~~eee~~|**–4**<br>~~eee~~|**Units**|
|---|---|---|---|---|---|---|---|---|---|
||||**Min.**<br>~~a~~<br>~~ee~~|**Max.**<br>~~ee~~<br>~~ee~~|**Min.**<br>~~ee~~|**Max.**<br>~~ee~~|**Min.**<br>~~eee~~|**Max.**<br>~~eee~~||
|tHPLL<br>~~a~~|Clock to Data Hold – PIO<br>Input Register<br>~~a~~|MachXO2-1200HC-HE<br>~~ee~~<br>~~ee~~|0.41<br>~~a~~<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~Ge~~|0.48<br>~~ee~~<br>~~ee~~<br>~~Ge~~|—<br>~~ee~~<br>~~ee~~|0.55<br>~~eee~~<br>~~ee~~|—<br>~~eee~~<br>~~ee~~|ns<br>~~ee~~|
|||MachXO2-2000HC-HE<br>~~ee ~~<br>~~ee~~|0.42<br> ~~a ~~<br>~~ee~~<br>~~ee~~|—<br> ~~ee~~<br>~~ee~~<br>~~ee~~<br>~~Ge~~|0.49<br>~~ee ~~<br>~~ee~~<br>~~Ge~~|—<br> ~~ee~~<br>~~ee~~|0.56<br>~~eee~~<br>~~ee~~|—<br>~~eee~~<br>~~ee~~|ns<br>~~ee~~|
|||MachXO2-4000HC-HE<br>~~ee~~|0.43<br>~~ee~~|—<br>~~Ge~~<br>~~ee~~|0.50<br>~~Ge~~<br>~~ee~~|—<br>~~ee~~|0.58<br>~~ee~~|—<br>~~ee~~|ns<br>~~ee~~|
|||MachXO2-7000HC-HE<br>~~ee~~<br>~~ee~~|0.46<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~|0.54<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~|0.62<br>~~ee~~|—<br>~~ee~~|ns<br>~~ee~~|
|tSU_DELPLL|Clock to Data Setup – PIO<br>Input Register with Data<br>Input Delay|MachXO2-1200HC-HE<br>~~ee~~|2.88<br>~~ee~~|—<br>~~ee~~<br>~~Ge~~|3.19<br>~~ee~~<br>~~Ge~~|—<br>~~ee~~|3.72|—|ns|
|||MachXO2-2000HC-HE<br>~~ee ~~<br>~~ee~~|2.87<br> ~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~<br>~~Ge~~<br>~~Ge~~|3.18<br>~~ee~~<br>~~ee~~<br>~~Ge~~<br>~~Ge~~|—<br>~~ee~~<br>~~ee~~|3.70<br>~~ee~~|—<br>~~ee~~|ns<br>~~ee~~|
|||MachXO2-4000HC-HE<br>~~ee~~|2.96<br>~~ee~~|—<br>~~Ge~~<br>~~ee~~<br>~~Ge~~<br>~~ee~~|3.28<br>~~Ge~~<br>~~ee~~<br>~~Ge~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~|3.81<br>~~ee~~|—<br>~~ee~~|ns<br>~~ee~~|
|||MachXO2-7000HC-HE<br>~~ee~~|3.05<br>~~ee~~<br>~~es~~|—<br>~~Ge~~<br>~~ee~~<br>~~ee~~<br>~~es~~|3.35<br>~~Ge~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~<br>~~ee~~|3.87<br>~~ee~~|—<br>~~ee~~|ns<br>~~ee~~|
|tH_DELPLL|Clock to Data Hold – PIO<br>Input Register with Input<br>Data Delay<br>~~po~~|MachXO2-1200HC-HE<br>~~ee~~|–0.83<br>~~ee~~<br>~~es~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~<br>~~es~~<br>~~ee~~|–0.83<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|–0.83<br>~~ee~~|—<br>~~ee~~|ns<br>~~ee~~|
|||MachXO2-2000HC-HE<br>~~ee~~<br>~~po~~|–0.83<br>~~es~~<br>~~ee~~<br>~~ee~~|—<br>~~es ~~<br>~~ee~~<br>~~ee~~|–0.83<br> ~~ee~~<br>~~ee~~<br>~~ee~~<br>~~es~~|—<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~es~~|–0.83<br>~~ee~~|—<br>~~ee~~|ns<br>~~ee~~|
|||MachXO2-4000HC-HE<br>~~ss~~<br>~~po~~|–0.87<br>~~ee~~<br>~~ss~~|—<br>~~ee ~~<br>~~ss~~|–0.87<br> ~~ee~~<br>~~ss~~<br>~~es~~|—<br>~~ee~~<br>~~ss~~<br>~~es~~|–0.87<br>~~ss~~|—<br>~~ss~~|ns<br>~~ss~~|
|||MachXO2-7000HC-HE<br>~~ss~~<br>~~po~~|–0.91<br>~~ss~~|—<br>~~ss~~|–0.91<br>~~ss~~<br>~~es~~|—<br>~~ss~~<br>~~es~~|–0.91<br>~~ss~~|—<br>~~ss~~|ns<br>~~ss~~|
|**Generic DDRX1 Inputs with Clock and Data Aligned at Pin Using PCLK Pin for Clock Input – GDDRX1_RX.SCLK.Aligned9, 11**<br>~~es es~~<br>~~po~~<br>~~pe~~<br>~~ee~~<br>~~ee~~<br>~~aee~~<br>~~ee~~<br>~~pO~~||||||||||
|tDVA<br>~~ee~~<br>~~pO~~<br>~~ee~~|Input Data Valid After CLK<br>~~ee~~<br>~~pO~~<br>|All MachXO2 devices,<br>all sides<br>~~ee~~<br>~~ee~~<br>~~ee~~|—<br>~~a~~<br>~~**ee**~~|0.317<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~|0.344<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~|0.368<br>~~ee~~<br>~~ee~~<br>~~ee~~|UI<br>~~ee~~<br>~~ee~~|
|tDVE<br>~~ee~~<br>~~pO~~<br>~~ee ee~~<br>~~ee~~|Input Data Hold After CLK<br>~~ee~~<br>~~pO~~<br>~~ee~~||0.742<br>~~a~~<br>~~**ee**~~|—<br>~~ee~~<br>~~ee~~<br>~~ee~~|0.702<br>~~ee~~<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~<br>~~ee~~|0.668<br>~~ee~~<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|UI<br>~~ee~~<br>~~ee~~<br>~~ee~~|
|fDATA<br>~~pO~~<br>~~ee ee~~<br>~~ee~~|DDRX1 Input Data Speed<br>~~pO~~<br>~~ee~~<br>~~ee~~||—<br>~~**ee**~~<br>~~a~~|300<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~|250<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~|208<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|Mbps<br>~~ee~~<br>~~ee~~|
|fDDRX1<br>~~ee ee~~<br>~~ee~~|DDRX1 SCLK Frequency<br>~~ee~~<br>~~ee~~||—<br>~~**ee** ~~<br>~~a~~|150<br> ~~ee~~<br>~~ee~~|—<br>~~ee ~~<br>~~ee~~|125<br> ~~ee ~~<br>~~ee~~|—<br> ~~ee ~~<br>~~ee~~|104<br> ~~ee~~<br>~~ee~~<br>~~ee~~|MHz<br>~~ee~~<br>~~ee~~|
|**Generic DDRX1 Inputs with Clock and Data Centered at Pin Using PCLK Pin for Clock Input – GDDRX1_RX.SCLK.Centered9, 11**<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~a~~<br>~~ee~~<br>~~|~~<br>|<br>~~|Pt~~||||||||||
|tSU<br>~~ee~~<br>~~ee~~|Input Data Setup Before<br>CLK<br>~~ee~~<br>~~eee~~|All MachXO2 devices,<br>all sides<br>~~ee~~<br>~~eee~~<br>~~eee~~|0.566<br>~~|~~<br>~~a~~|—<br>|<br>~~ee~~|0.560<br>~~|~~<br>~~ee~~|—<br>~~Pt~~|0.538<br>~~Pt~~|—<br>~~Pt~~|ns|
|tHO<br>~~ee~~<br>~~ee~~<br>~~pO~~|Input Data Hold After CLK<br>~~ee~~<br>~~eee~~<br>~~pO~~||0.778<br>~~|~~<br>~~a~~<br>~~ee~~|—<br>|<br>~~ee~~<br>~~ee~~|0.879<br>~~| ~~<br>~~ee~~<br>~~ee~~|—<br> ~~Pt~~<br>~~ee~~|1.090<br>~~Pt~~<br>~~ee~~|—<br>~~Pt~~<br>~~ee~~|ns<br>~~ee~~|
|fDATA<br>~~ee ~~<br>~~pO~~<br>~~ee~~|DDRX1 Input Data Speed<br> ~~eee~~<br>~~pO~~<br>~~eee~~||—<br>~~a ~~<br>~~ee~~<br>~~a~~|300<br> ~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~|250<br>~~ee~~|—<br>~~ee~~|208<br>~~ee~~|Mbps<br>~~ee~~|
|fDDRX1<br>~~pO~~<br>~~ee~~|DDRX1 SCLK Frequency<br>~~pO~~<br>~~eee~~||—<br>~~ee ~~<br>~~a~~|150<br> ~~ee~~|—<br>~~ee ~~|125<br> ~~ee ~~|—<br> ~~ee ~~|104<br> ~~ee~~|MHz<br>~~ee~~|
|**Generic DDRX2 Inputs with Clock and Data Aligned at Pin Using PCLK Pin for Clock Input – GDDRX2_RX.ECLK.Aligned9, 11**<br>~~ee~~<br>~~eee~~<br>~~a~~<br>~~PR~~<br>~~eeeee~~<br>~~aee~~<br>~~ee~~<br>~~ee~~||||||||||
|tDVA<br>~~PR~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|Input Data Valid After CLK<br>~~PR~~<br>~~eee~~<br>~~eee~~<br>~~ee~~|MachXO2-640U,<br>MachXO2-1200/U and<br>larger devices, bottom<br>side only<br>~~PR~~<br>~~eee~~<br>~~eee~~<br>~~ee~~<br>~~eee~~|—<br>~~PR~~<br>~~a~~<br>~~a~~|0.316<br>~~PR~~<br>~~ee~~<br>~~ee~~|—<br>~~PR~~<br>~~ee~~<br>~~ee~~|0.342<br>~~PR~~<br>~~ee~~<br>~~ee~~|—<br>~~PR~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|0.364<br>~~PR~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|UI<br>~~PR~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|
|tDVE<br>~~ee ~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|Input Data Hold After CLK<br> ~~eee~~<br>~~eee~~<br>~~ee~~<br>||0.710<br>~~a~~<br>~~a~~<br>~~|~~|—<br>~~ee~~<br>~~ee~~<br>~~|~~|0.675<br>~~ee~~<br>~~ee~~<br>~~|~~|—<br>~~ee~~<br>~~ee~~<br>~~Pt~~|0.679<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~Pt~~|—<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~Pt~~|UI<br>~~ee~~<br>~~ee~~<br>~~ee~~|
|fDATA<br>~~ee ~~<br>~~ee~~<br>~~ee~~<br>~~a~~|DDRX2 Serial Input Data<br>Speed<br> ~~eee~~<br>~~ee~~<br>~~eee~~||—<br>~~a~~<br>~~|~~<br>~~a~~|664<br>~~ee~~<br>~~|~~<br>~~ee~~|—<br>~~ee~~<br>~~|~~<br>~~ee~~|554<br>~~ee~~<br>~~Pt~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~<br>~~Pt~~<br>~~ee~~<br>~~**e**~~|462<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~Pt~~<br>~~ee~~<br>~~**e**e~~|Mbps<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|
|fDDRX2<br>~~ee~~<br>~~ee~~<br>~~a~~|DDRX2 ECLK Frequency<br>~~ee~~<br>~~eee~~||—<br>~~|~~<br>~~a~~|332<br>~~|~~<br>~~ee~~|—<br>~~|~~<br>~~ee~~|277<br>~~Pt~~<br>~~ee~~|—<br>~~ee~~<br>~~Pt~~<br>~~ee~~<br>~~**e**~~|231<br>~~ee ~~<br>~~Pt~~<br>~~ee~~<br>~~**e**e~~|MHz<br> ~~ee~~<br>~~ee~~<br>~~ee~~|
|fSCLK<br>~~ee ~~<br>~~a~~|SCLK Frequency<br> ~~eee~~||—<br>~~|~~<br>~~a~~<br>~~a~~|166<br>~~|~~<br>~~ee~~<br>~~ee~~|—<br>~~| ~~<br>~~ee~~<br>~~ee~~|139<br> ~~Pt~~<br>~~ee~~<br>~~ee~~|—<br>~~Pt~~<br>~~ee~~<br>~~**e**~~|116<br>~~Pt~~<br>~~ee~~<br>~~**e**e~~<br>~~e~~|MHz<br>~~ee~~<br>~~ee~~<br>~~e~~|
|**Generic DDRX2 Inputs with Clock and Data Centered at Pin Using PCLK Pin for Clock Input – GDDRX2_RX.ECLK.Centered9, 11**<br>~~**e**e ee~~<br>~~a~~<br>~~a~~<br>~~ee~~<br>~~e~~<br>~~PR~~<br>~~ee~~<br>~~|~~<br>|<br>~~|tt|~~||||||||||
|tSU<br>~~PR~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|Input Data Setup Before<br>CLK<br>~~PR~~<br>~~ee~~<br>~~eee~~<br>~~ee~~|MachXO2-640U,<br>MachXO2-1200/U and<br>larger devices, bottom<br>side only<br>~~PR~~<br>~~ee~~<br>~~eee~~<br>~~ee~~<br>~~**ee**~~|0.233<br>~~PR~~<br>~~|~~<br>~~a~~|—<br>~~PR~~<br>|<br>~~ee~~|0.219<br>~~PR~~<br>~~|~~<br>~~ee~~|—<br>~~PR~~<br>~~tt~~<br>~~ee~~|0.198<br>~~PR~~<br>~~tt~~<br>~~ee~~|—<br>~~PR~~<br>~~tt|~~<br>~~ee~~<br>~~ee~~|ns<br>~~PR~~<br>~~ee~~|
|tHO<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|Input Data Hold After CLK<br>~~ee~~<br>~~eee~~<br>~~ee~~||0.287<br>~~|~~<br>~~a~~<br>~~|~~|—<br>|<br>~~ee~~<br>~~|~~|0.287<br>~~| ~~<br>~~ee~~<br>~~|~~|—<br> ~~tt~~<br>~~ee~~<br>~~Pt~~|0.344<br>~~tt~~<br>~~ee~~<br>~~Pt~~|—<br>~~tt |~~<br>~~ee~~<br>~~ee~~<br>~~Pt~~|ns<br>~~ee~~|
|fDATA<br>~~ee ~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|DDRX2 Serial Input Data<br>Speed<br> ~~eee~~<br>~~ee~~<br>~~**ee**~~||—<br>~~a~~<br>~~|~~<br>~~**a**~~|664<br>~~ee~~<br>~~|~~<br>~~**ee**~~|—<br>~~ee~~<br>~~|~~<br>~~**ee**~~|554<br>~~ee~~<br>~~Pt~~<br>~~**ee**~~|—<br>~~ee~~<br>~~Pt~~<br>~~**ee**~~|462<br>~~ee~~<br>~~ee~~<br>~~Pt~~<br>~~**ee**~~|Mbps<br>~~ee~~<br>~~**ee**~~|
|fDDRX2<br>~~ee~~<br>~~ee~~<br>~~ee~~|DDRX2 ECLK Frequency<br>~~ee~~<br>~~**ee**~~||—<br>~~|~~<br>~~**a**~~|332<br>~~|~~<br>~~**ee**~~|—<br>~~|~~<br>~~**ee**~~|277<br>~~Pt~~<br>~~**ee**~~|—<br>~~Pt~~<br>~~**ee**~~|231<br>~~ee~~<br>~~Pt~~<br>~~**ee**~~<br>~~ee~~|MHz<br>~~**ee**~~<br>~~ee~~|
|fSCLK<br>~~ee~~<br>~~ee~~|SCLK Frequency<br>~~**ee**~~||—<br>~~|~~<br>~~**a**~~|166<br>~~|~~<br>~~**ee**~~|—<br>~~| ~~<br>~~**ee**~~|139<br> ~~Pt~~<br>~~**ee**~~|—<br>~~Pt~~<br>~~**ee**~~|116<br>~~Pt~~<br>~~**ee**~~<br>~~ee~~|MHz<br>~~**ee**~~<br>~~ee~~|
|**Generic DDR4 Inputs with Clock and Data Aligned at Pin Using PCLK Pin for Clock Input – GDDRX4_RX.ECLK.Aligned9, 11**<br>~~**ee**~~<br>~~**aee**~~<br>~~ee~~<br>~~ee~~<br>~~pe~~<br>~~a~~<br>~~|~~<br>|<br>~~|~~<br>~~fttt~~||||||||||
|tDVA<br>~~pe~~<br>~~a~~<br>~~ee~~|Input Data Valid After<br>ECLK<br>~~pe~~<br>~~ee~~|MachXO2-640U,<br>MachXO2-1200/U and<br>larger devices, bottom<br>side only<br>~~pe~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|—<br>~~pe~~<br>~~|~~<br>~~a~~|0.290<br>~~pe~~<br>|<br>~~ee~~|—<br>~~pe~~<br>~~|~~<br>~~ee~~|0.320<br>~~pe~~<br>~~ft~~<br>~~ee~~|—<br>~~pe~~<br>~~fttt~~<br>~~ee~~|0.345<br>~~pe~~<br>~~tt~~<br>~~ee~~|UI<br>~~pe~~|
|tDVE<br>~~a~~<br>~~ee~~<br>~~ee~~|Input Data Hold After ECLK<br>~~ee~~<br>~~ee~~||0.739<br>~~|~~<br>~~a~~<br>~~ft~~|—<br>|<br>~~ee~~<br>~~ft~~<br>||0.699<br>~~|~~<br>~~ee~~<br>~~|~~|—<br>~~ft~~<br>~~ee~~<br>~~Pt~~|0.703<br>~~ft tt~~<br>~~ee~~<br>~~Pt~~|—<br>~~tt~~<br>~~ee~~<br>~~Pt~~|UI|
|fDATA<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|DDRX4 Serial Input Data<br>Speed<br>~~ee~~<br>~~ee~~<br>~~ee~~||—<br>~~a ~~<br>~~ft~~<br>~~a~~|756<br> ~~ee~~<br>~~ft~~<br>|<br>~~ee~~|—<br>~~ee ~~<br>~~|~~<br>~~ee~~|630<br> ~~ee~~<br>~~Pt~~<br>~~ee~~|—<br>~~ee ~~<br>~~Pt~~<br>~~ee~~<br>~~ee~~|524<br> ~~ee~~<br>~~Pt~~<br>~~ee~~<br>~~ee~~|Mbps<br>~~ee~~|
|fDDRX4<br>~~ee~~<br>~~ee~~<br>~~ee~~|DDRX4 ECLK Frequency<br>~~ee~~<br>~~ee~~<br>~~ee~~||—<br>~~ft~~<br>~~a~~<br>~~a~~|378<br>~~ft~~<br>|<br>~~ee~~<br>~~ee~~|—<br>~~| ~~<br>~~ee~~<br>~~ee~~|315<br> ~~Pt~~<br>~~ee~~<br>~~ee~~|—<br>~~Pt~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|262<br>~~Pt~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|MHz<br>~~ee~~<br>~~ee~~|
|fSCLK<br>~~ee~~<br>~~ee~~|SCLK Frequency<br>~~ee~~<br>~~ee~~||—<br>~~a~~<br>~~a~~|95<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~|79<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~<br>~~ee~~|66<br>~~ee~~<br>~~ee~~<br>~~ee~~|MHz<br>~~ee~~<br>~~ee~~|
|**Generic DDR4 Inputs with Clock and Data Centered at Pin Using PCLK Pin for Clock Input – GDDRX4_RX.ECLK.Centered9, 11**<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~a eeee~~||||||||||
© 2010-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02056-4.3
66
**MachXO2 Family Data Sheet**
**Data Sheet**
|**Parameter**<br>~~Pe~~<br>~~|~~|**Description**<br>~~Pe~~<br>~~|~~|**Device**<br>~~Pe~~|**–6**<br>~~Pe~~<br>~~aa~~|**–6**<br>~~Pe~~<br>~~aa~~|**–5**<br>~~Pe~~<br>eeee|**–5**<br>~~Pe~~<br>eeee|**–4**<br>~~Pe~~<br>eeee|**–4**<br>~~Pe~~<br>eeee|**Units**<br>~~Pe~~<br>|
|---|---|---|---|---|---|---|---|---|---|
||||**Min.**<br>~~Pe~~<br>~~a~~<br>~~ft~~|**Max.**<br>~~Pe~~<br>~~a~~<br>~~fttf~~|**Min.**<br>~~Pe~~<br>ee<br>~~tffF~~|**Max.**<br>~~Pe~~<br>ee<br>~~fF~~|**Min.**<br>~~Pe~~<br>ee<br>|**Max.**<br>~~Pe~~<br>ee<br>||
|tSU<br>~~|~~<br>~~a~~<br>~~Pf~~|Input Data Setup Before<br>ECLK<br>~~|~~<br>~~ee~~<br>~~Pf~~|MachXO2-640U,<br>MachXO2-1200/U and<br>larger devices, bottom<br>side only|0.233<br>~~a ~~<br>~~ft~~<br>~~a ee~~|—<br> ~~a~~<br>~~fttf~~<br>~~ee~~|0.219<br>ee <br>~~tffF~~<br>~~ee~~|—<br> ee <br>~~fFfff~~<br>~~ee~~|0.198<br> ee <br>~~fff~~<br>~~ee~~|—<br> ee<br>~~fff~~<br>~~ee~~<br>ee|ns<br>~~fff~~<br>~~ee~~|
|tHO<br>~~a~~<br>~~Pf~~<br>~~ee~~|Input Data Hold After ECLK<br>~~ee~~<br>~~Pf~~||0.287<br>~~ft~~<br>~~a ee~~|—<br>~~ft tf~~<br>~~ee~~|0.287<br>~~tf fF~~<br>~~ee~~<br>~~ft~~|—<br>~~fF~~<br>~~ee~~<br>~~ft EE~~|0.344<br><br>~~ee~~<br>~~EE~~|—<br><br>~~ee~~<br>ee<br>~~EE~~|ns<br><br>~~ee~~<br>~~EE~~|
|fDATA<br>~~a~~<br>~~Pf~~<br>~~ee~~<br>~~ee~~|DDRX4 Serial Input Data<br>Speed<br>~~ee~~<br>~~Pf~~<br>~~**ee**~~||—<br>~~a ee~~<br>~~ff~~<br>~~ee~~|756<br>~~ee~~<br>~~ff~~<br>~~**e**e~~|—<br>~~ee~~<br>~~ff~~<br>~~ft~~<br>~~ee~~|630<br>~~ee~~<br>~~ff~~<br>~~ft EE~~<br>~~**e**e~~|—<br>~~ee~~<br>~~ff~~<br>~~EE~~<br>~~**e**e~~|524<br>~~ee~~<br>ee<br>~~ff~~<br>~~EE~~<br>~~ee~~|Mbps<br>~~ee~~<br>~~ff~~<br>~~EE~~<br>~~ee~~|
|fDDRX4<br>~~ee~~<br>~~ee~~|DDRX4 ECLK Frequency<br>~~**ee**~~||—<br>~~ee~~<br>~~a~~|378<br>~~**e**e~~|—<br>~~ft~~<br>~~ee~~<br>~~e~~|315<br>~~ft EE~~<br>~~**e**e~~<br>~~s~~|—<br>~~EE~~<br>~~**e**e~~<br>~~s~~|262<br>~~EE~~<br>~~ee~~<br>~~ee~~|MHz<br>~~EE~~<br>~~ee~~|
|fSCLK<br>~~ee~~<br>~~ee~~|SCLK Frequency<br>~~**ee**~~||—<br>~~ee~~<br>~~a~~|95<br>~~**e**e~~|—<br>~~ft~~<br>~~ee~~<br>~~e~~|79<br>~~ft EE~~<br>~~**e**e~~<br>~~s~~|—<br>~~EE~~<br>~~**e**e~~<br>~~s~~|66<br>~~EE~~<br>~~ee~~<br>~~ee~~|MHz<br>~~EE~~<br>~~ee~~|
|**7:1 LVDS Inputs (GDDR71_RX.ECLK.7:1)9, 11**<br>~~**ee**~~<br>~~ee ~~~~**e**e ee ~~~~**e**e ~~~~**e**e ee ee~~<br>~~ee~~<br>~~a~~<br>~~e~~<br>~~s~~<br>~~s ee~~<br>~~Ree~~<br>~~fo~~<br>~~|~~<br>~~tffFft~~<br>~~ft~~||||||||||
|tDVA<br>~~fo~~<br>~~ee ee~~|Input Data Valid After<br>ECLK<br>~~fo~~<br>~~ee~~|MachXO2-640U,<br>MachXO2-1200/U and<br>larger devices, bottom<br>side only<br>~~ee~~|—<br>~~|~~<br>~~a~~|0.290<br>~~tf~~|—<br>~~tffF~~<br>~~es~~|0.320<br>~~fFft~~<br>~~es~~|—<br>~~ft~~<br>~~ee~~|0.345<br>~~ft~~<br>~~ft~~|UI<br>~~ft~~|
|tDVE<br>~~fo~~<br>~~ee ee~~<br>~~fo~~|Input Data Hold After ECLK<br>~~fo~~<br>~~ee~~<br>~~fo~~||0.739<br>~~|~~<br>~~a~~<br>~~ft~~|—<br>~~tf~~<br>~~ftft~~|0.699<br>~~tf fF~~<br>~~es~~<br>~~ftfF~~|—<br>~~fF ft~~<br>~~es~~<br>~~fF~~|0.703<br>~~ft~~<br>~~ee~~<br>|—<br>~~ft~~<br>~~ft~~<br>|UI<br>~~ft~~<br>|
|fDATA<br>~~ee ee~~<br>~~fo~~<br>~~ee~~|DDR71 Serial Input Data<br>Speed<br>~~ee~~<br>~~fo~~<br>~~ee~~||—<br>~~a~~<br>~~ft~~|756<br>~~ftft~~|—<br>~~es~~<br>~~ftfF~~|630<br>~~es ~~<br>~~fFttf~~|—<br> ~~ee~~<br>~~ttf~~|524<br>~~ttf~~|Mbps<br>~~ttf~~|
|fDDR71<br>~~fo~~<br>~~ee~~|DDR71 ECLK Frequency<br>~~fo~~<br>~~ee~~||—<br>~~ft~~|378<br>~~ft ft~~|—<br>~~ft fF~~|315<br>~~fF~~|—<br>|262<br>|MHz<br>|
|fCLKIN<br>~~ee~~|7:1 Input Clock Frequency<br>(SCLK) (minimum limited<br>byPLL)<br>~~ee~~||—|108|—|90|—|75|MHz|
|**Generic DDR Outputs with Clock and Data Aligned at Pin Using PCLK Pin for Clock Input – GDDRX1_TX.SCLK.Aligned9, 11**<br>~~ee ee~~<br>~~Pee~~<br>~~|~~<br>~~fttffF~~||||||||||
|tDIA<br>~~|~~<br>~~|~~|Output Data Invalid After<br>CLK Output<br>~~|~~<br>~~|~~|All MachXO2 devices,<br>all sides|—<br>~~ft~~<br>~~ft~~|0.520<br>~~fttf~~<br>~~ft~~<br>~~tf~~|—<br>~~tffF~~<br>~~tffF~~|0.550<br>~~fFfff~~<br>~~fF~~|—<br>~~fff~~<br>|0.580<br>~~fff~~<br>|ns<br>~~fff~~<br>|
|tDIB<br>~~|~~<br>~~|~~<br>~~ee~~<br>~~ee~~|Output Data Invalid Before<br>CLK Output<br>~~|~~<br>~~|~~<br>~~**ee**~~||—<br>~~ft~~<br>~~ft~~<br>~~**a**~~|0.520<br>~~ft tf~~<br>~~ft~~<br>~~tf~~|—<br>~~tf fF~~<br>~~tffF~~|0.550<br>~~fF~~<br>~~fFfff~~|—<br><br>~~fff~~|0.580<br><br>~~fff~~|ns<br><br>~~fff~~|
|fDATA<br>~~|~~<br>~~ee~~<br>~~ee~~|DDRX1 Output Data Speed<br>~~|~~<br>~~**ee**~~||—<br>~~ft~~<br>~~**a**~~|300<br>~~ft~~<br>~~tf~~<br>~~ee~~|—<br>~~tf fF~~<br>~~ee~~|250<br>~~fFfff~~<br>~~ee~~|—<br>~~fff~~<br>~~es~~|208<br>~~fff~~|Mbps<br>~~fff~~|
|fDDRX1<br>~~ee~~<br>~~ee~~|DDRX1 SCLK frequency<br>~~**ee**~~||—<br>~~**a**~~|150<br><br>~~ee~~|—<br><br>~~ee~~|125<br>~~fff~~<br>~~ee~~|—<br>~~fff~~<br>~~es~~|104<br>~~fff~~|MHz<br>~~fff~~|
|**Generic DDR Outputs with Clock and Data Centered at Pin Using PCLK Pin for Clock Input – GDDRX1_TX.SCLK.Centered9, 11**<br>~~**ee**~~<br>~~**a**~~<br>~~ee~~<br>~~ee ee~~<br>~~es~~<br>~~eee~~<br>~~|~~<br>~~fttffttt~~||||||||||
|tDVB<br>~~eee~~<br>~~|~~<br>~~fo~~|Output Data Valid Before<br>CLK Output<br>~~eee~~<br>~~|~~<br>~~fo~~|All MachXO2 devices,<br>all sides<br>~~eee~~|1.210<br>~~eee~~<br>~~ft~~<br>~~ft~~|—<br>~~eee~~<br>~~fttf~~<br>~~fttf~~|1.510<br>~~eee~~<br>~~tfft~~<br>~~tf~~|—<br>~~eee~~<br>~~ft~~<br>|1.870<br>~~eee~~<br>~~fttt~~<br>|—<br>~~eee~~<br>~~tt~~<br>|ns<br>~~eee~~<br>~~tt~~<br>|
|tDVA<br>~~|~~<br>~~fo~~<br>~~ee~~|Output Data Valid After<br>CLK Output<br>~~|~~<br>~~fo~~<br>~~ee~~||1.210<br>~~ft~~<br>~~ft~~<br>~~a~~|—<br>~~ft tf~~<br>~~fttf~~<br>~~es~~|1.510<br>~~tf ft~~<br>~~tffff~~<br>~~es~~|—<br>~~ft~~<br>~~fff~~<br>~~ee~~|1.870<br>~~ft tt~~<br>~~fff~~<br>~~es~~|—<br>~~tt~~<br>~~fff~~<br>~~es~~|ns<br>~~tt~~<br>~~fff~~|
|fDATA<br>~~fo~~<br>~~ee~~|DDRX1 Output Data Speed<br>~~fo~~<br>~~ee~~||—<br>~~ft~~<br>~~a~~|300<br>~~ft tf~~<br>~~es~~|—<br>~~tffff~~<br>~~es~~<br>~~fF~~|250<br>~~fff~~<br>~~ee~~<br>~~fFttt~~|—<br>~~fff~~<br>~~es~~<br>~~ttt~~|208<br>~~fff~~<br>~~es~~<br>~~ttt~~|Mbps<br>~~fff~~<br>~~ttt~~|
|fDDRX1<br>~~ee~~<br>~~fo~~|DDRX1 SCLK Frequency<br>(minimum limited byPLL)<br>~~ee~~<br>~~fo~~||—<br><br>~~a~~<br>~~tf~~|150<br><br>~~es~~<br>~~tf~~|—<br>~~fff~~<br>~~es ~~<br>~~tf~~<br>~~fF~~|125<br>~~fff~~<br> ~~ee~~<br>~~tf~~<br>~~fFttt~~|—<br>~~fff~~<br>~~es ~~<br>~~tf~~<br>~~ttt~~|104<br>~~fff~~<br> ~~es~~<br>~~tf~~<br>~~ttt~~|MHz<br>~~fff~~<br>~~tf~~<br>~~ttt~~|
|**Generic DDRX2 Outputs with Clock and Data Aligned at Pin Using PCLK Pin for Clock Input – GDDRX2_TX.ECLK.Aligned9, 11**<br>~~fo~~<br>~~tf~~<br>~~fF ttt~~<br>~~Pee~~<br>~~fo~~<br>~~ftftfFff~~<br>~~ft~~||||||||||
|tDIA<br>~~fo~~<br>~~|~~|Output Data Invalid After<br>CLK Output<br>~~fo~~<br>~~|~~|MachXO2-640U,<br>MachXO2-1200/U and<br>larger devices, top side<br>only|—<br>~~ft~~<br>~~ft~~|0.200<br>~~ftft~~<br>~~ftft~~|—<br>~~ftfF~~<br>~~ftfF~~|0.215<br>~~fFff~~<br>~~fFtf~~|—<br>~~ff~~<br>~~tfff~~|0.230<br>~~ff~~<br>~~ft~~<br>~~ff~~|ns<br>~~ft~~|
|tDIB<br>~~fo~~<br>~~|~~<br>~~|~~|Output Data Invalid Before<br>CLK Output<br>~~fo~~<br>~~|~~<br>~~|~~||—<br>~~ft~~<br>~~ft~~<br>~~ft~~|0.200<br>~~ft ft~~<br>~~ftft~~<br>~~ftft~~|—<br>~~ft fF~~<br>~~ftfF~~<br>~~ftfF~~|0.215<br>~~fF ff~~<br>~~fFtf~~<br>~~fFtf~~|—<br>~~ff~~<br>~~tfff~~<br>~~tfff~~|0.230<br>~~ff~~<br>~~ft~~<br>~~ff~~<br>~~ff~~|ns<br>~~ft~~|
|fDATA<br>~~|~~<br>~~|~~<br>~~ee~~|DDRX2 Serial Output Data<br>Speed<br>~~|~~<br>~~|~~<br>~~ee~~||—<br>~~ft~~<br>~~ft~~<br>~~a~~|664<br>~~ft ft~~<br>~~ftft~~<br>~~ee~~|—<br>~~ft fF~~<br>~~ftfF~~<br>~~es~~|554<br>~~fF tf~~<br>~~fFtf~~<br>~~es~~|—<br>~~tf ff~~<br>~~tfff~~<br>~~ee~~|462<br>~~ff~~<br>~~ff~~|Mbps|
|fDDRX2<br>~~|~~<br>~~ee~~<br>~~ee~~|DDRX2 ECLK frequency<br>~~|~~<br>~~ee~~<br>~~ee~~||—<br>~~ft~~<br>~~a~~<br>~~es~~|332<br>~~ft ft~~<br>~~ee~~<br>~~es~~|—<br>~~ft fF~~<br>~~es~~<br>~~es~~|277<br>~~fF tf~~<br>~~es~~<br>~~es~~|—<br>~~tf ff~~<br>~~ee~~<br>~~ee~~|231<br>~~ff~~|MHz|
|fSCLK<br>~~ee~~<br>~~ee~~|SCLK Frequency<br>~~ee~~<br>~~ee~~||—<br>~~a~~<br>~~es~~|166<br>~~ee ~~<br>~~es~~|—<br> ~~es~~<br>~~es~~|139<br>~~es ~~<br>~~es~~|—<br> ~~ee~~<br>~~ee~~|116|MHz|
|**Generic DDRX2 Outputs with Clock and Data Centered at Pin Using PCLK Pin for Clock Input – GDDRX2_TX.ECLK.Centered9, 11**<br>~~ee~~<br>~~ee~~<br>~~es~~<br>~~es~~<br>~~es ee~~<br>~~eee~~<br>~~fo~~<br>~~fttffFff~~<br>~~ft~~||||||||||
|tDVB<br>~~eee~~<br>~~fo~~<br>~~|~~|Output Data Valid Before<br>CLK Output<br>~~eee~~<br>~~fo~~<br>~~|~~|MachXO2-640U,<br>MachXO2-1200/U and<br>larger devices, top side<br>only<br>~~eee~~|0.535<br>~~eee~~<br>~~ft~~<br>~~fF~~|—<br>~~eee~~<br>~~fttf~~<br>~~fFff~~|0.670<br>~~eee~~<br>~~tffF~~<br>~~ff~~|—<br>~~eee~~<br>~~fFff~~<br>~~ffff~~|0.830<br>~~eee~~<br>~~ff~~<br>~~ff~~|—<br>~~eee~~<br>~~ff~~<br>~~ft~~<br>~~ff~~|ns<br>~~eee~~<br>~~ft~~|
|tDVA<br>~~fo~~<br>~~|~~<br>~~|~~|Output Data Valid After<br>CLK Output<br>~~fo~~<br>~~|~~<br>~~|~~||0.535<br>~~ft~~<br>~~fF~~<br>~~fF~~|—<br>~~ft tf~~<br>~~fFff~~<br>~~fFff~~|0.670<br>~~tf fF~~<br>~~ff~~<br>~~ff~~|—<br>~~fF ff~~<br>~~ffff~~<br>~~ffff~~|0.830<br>~~ff~~<br>~~ff~~<br>~~ff~~|—<br>~~ff~~<br>~~ft~~<br>~~ff~~<br>~~ff~~|ns<br>~~ft~~|
|fDATA<br>~~|~~<br>~~|~~<br>~~fo~~|DDRX2 Serial Output Data<br>Speed<br>~~|~~<br>~~|~~<br>~~fo~~||—<br>~~fF~~<br>~~fF~~<br>~~ft~~|664<br>~~fF ff~~<br>~~fFff~~<br>~~ftft~~|—<br>~~ff~~<br>~~ff~~<br>~~ftft~~|554<br>~~ff ff~~<br>~~ffff~~<br>~~fttt~~|—<br>~~ff~~<br>~~ff~~<br>~~tt~~|462<br>~~ff~~<br>~~ff~~<br>~~tt~~|Mbps|
|fDDRX2<br>~~|~~<br>~~fo~~|DDRX2 ECLK Frequency<br>(minimum limited byPLL)<br>~~|~~<br>~~fo~~||—<br>~~fF~~<br>~~ft~~|332<br>~~fF ff~~<br>~~ftft~~|—<br>~~ff~~<br>~~ftft~~|277<br>~~ff ff~~<br>~~fttt~~|—<br>~~ff~~<br>~~tt~~|231<br>~~ff~~<br>~~tt~~|MHz|
© 2010-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02056-4.3
67
**MachXO2 Family Data Sheet Data Sheet**
|**Parameter**<br>~~i~~<br>~~ee~~|**Description**<br>~~i~~<br>~~ee~~|**Device**<br>~~ee~~|**–6**<br>~~**a**a ee~~|**–6**<br>~~**a**a ee~~|**–5**<br>~~ee~~|**–5**<br>~~ee~~|**–4**<br>~~ee~~|**–4**<br>~~ee~~|**Units**<br>~~ee~~|
|---|---|---|---|---|---|---|---|---|---|
||||**Min.**<br>~~**a**~~|**Max.**<br>~~a ee~~|**Min.**<br>~~ee~~<br>~~ee~~|**Max.**<br>~~ee~~<br>~~ee~~|**Min.**<br>~~ee~~<br>~~ee~~|**Max.**<br>~~ee~~<br>~~ee~~||
|fSCLK<br>~~i~~<br>~~ee~~|SCLK Frequency<br>~~i~~<br>~~ee~~||—<br>~~**a**~~|166<br>~~a ee~~|—<br>~~ee~~<br>~~ee~~|139<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~|116<br>~~ee~~<br>~~ee~~|MHz<br>~~ee~~|
|**Generic DDRX4 Outputs with Clock and Data Aligned at Pin Using PCLK Pin for Clock Input – GDDRX4_TX.ECLK.Aligned9, 11**<br>~~i~~<br>~~ee ~~~~**a** a ee~~<br>~~ee~~<br>~~ee~~<br>~~ee ee~~<br>~~ee ee~~<br>~~Re~~<br>~~ft EE~~<br>~~PF~~||||||||||
|tDIA<br>~~Re~~<br>~~Pf~~<br>~~PF~~<br>~~PF~~|Output Data Invalid After<br>CLK Output<br>~~Re~~<br>~~Pf~~<br><br>|MachXO2-640U,<br>MachXO2-1200/U and<br>larger devices, top side<br>only<br>~~Re~~|—<br>~~Re~~<br>~~fof~~|0.200<br>~~Re~~<br>~~fof~~|—<br>~~Re~~<br>~~fof~~<br>~~ft~~<br>~~ft~~|0.215<br>~~Re~~<br>~~fof~~<br>~~ft EE~~<br>~~ft~~|—<br>~~Re~~<br>~~fof~~<br>~~EE~~<br>~~ft~~|0.230<br>~~Re~~<br>~~fof~~<br>~~EE~~|ns<br>~~Re~~<br>~~fof~~<br>~~EE~~|
|tDIB<br>~~PF of~~<br>~~PF~~<br>~~ee~~|Output Data Invalid Before<br>CLK Output<br>~~of~~<br>||—<br>~~fof~~|0.200<br>~~fof~~|—<br>~~ft~~<br>~~fof~~<br>~~ft~~<br>~~ft~~|0.215<br>~~ft EE~~<br>~~fof~~<br>~~ft~~<br>~~ft~~|—<br>~~EE~~<br>~~fof~~<br>~~ft~~<br>~~ft~~|0.230<br>~~EE~~<br>~~fof~~|ns<br>~~EE~~<br>~~fof~~|
|fDATA<br>~~PF ~~<br>~~PF of~~<br>~~ee~~<br>~~ee~~|DDRX4 Serial Output Data<br>Speed<br><br>~~of~~<br>~~**e**ee~~||—<br>~~fof~~<br>~~**a**~~|756<br>~~fof~~<br>~~**e**e~~|—<br>~~ft~~<br>~~ft~~<br>~~fof~~<br>~~ft~~<br>~~ee~~|630<br>~~ft EE~~<br>~~ft~~<br>~~fof~~<br>~~ft~~<br>~~**e**e~~|—<br>~~EE~~<br>~~ft~~<br>~~fof~~<br>~~ft~~<br>~~**e**e~~|524<br>~~EE~~<br>~~fof~~<br>~~ee~~|Mbps<br>~~EE~~<br>~~fof~~<br>~~ee~~|
|fDDRX4<br>~~PF of~~<br>~~ee~~<br>~~ee~~|DDRX4 ECLK Frequency<br>~~of~~<br>~~**e**ee~~<br>~~e~~||—<br>~~**a**~~|378<br>~~**e**e~~|—<br>~~ft~~<br>~~ft~~<br>~~ee~~<br>~~s~~|315<br>~~ft~~<br>~~ft~~<br>~~**e**e~~<br>~~s~~|—<br>~~ft~~<br>~~ft~~<br>~~**e**e~~<br>~~s~~|262<br>~~ee~~<br>~~ee~~|MHz<br>~~ee~~|
|fSCLK<br>~~ee~~<br>~~ee~~|SCLK Frequency<br>~~**e**ee~~<br>~~e~~||—<br>~~**a**~~|95<br>~~**e**e~~|—<br>~~ft~~<br>~~ee~~<br>~~s~~|79<br>~~ft~~<br>~~**e**e~~<br>~~s~~|—<br>~~ft~~<br>~~**e**e~~<br>~~s~~|66<br>~~ee~~<br>~~ee~~|MHz<br>~~ee~~|
|**Generic DDRX4 Outputs with Clock and Data Centered at Pin Using PCLK Pin for Clock Input – GDDRX4_TX.ECLK.Centered9, 11**<br>~~**e**ee~~<br>~~**a**~~<br>~~**e**e ee ~~~~**e**e ~~~~**e**e ee ee~~<br>~~ee~~<br>~~e~~<br>~~s~~<br>~~s~~<br>~~s ee~~<br>~~eee~~<br>~~|~~<br>~~ftftfFff~~||||||||||
|tDVB<br>~~|~~<br>~~fo~~|Output Data Valid Before<br>CLK Output<br>~~|~~<br>~~fo~~|MachXO2-640U,<br>MachXO2-1200/U and<br>larger devices, top side<br>only|0.455<br>~~ft~~<br>~~ft~~|—<br>~~ftft~~<br>~~ft~~<br>~~tf~~|0.570<br>~~ftfF~~<br>~~tffF~~|—<br>~~fFff~~<br>~~fF~~|0.710<br>~~ff~~<br>|—<br>~~ff~~<br>|ns<br>|
|tDVA<br>~~|~~<br>~~fo~~<br>~~fo~~|Output Data Valid After<br>CLK Output<br>~~|~~<br>~~fo~~<br>~~fo~~||0.455<br>~~ft~~<br>~~ft~~<br>~~ft~~|—<br>~~ft ft~~<br>~~ft~~<br>~~tf~~<br>~~ft~~<br>~~tf~~|0.570<br>~~ft fF~~<br>~~tffF~~<br>~~tffF~~|—<br>~~fF ff~~<br>~~fFfff~~<br>~~fF~~|0.710<br>~~ff~~<br>~~fff~~<br>|—<br>~~ff~~<br>~~fff~~<br>|ns<br>~~fff~~<br>|
|fDATA<br>~~fo~~<br>~~fo~~<br>~~fo~~|DDRX4 Serial Output Data<br>Speed<br>~~fo~~<br>~~fo~~<br>~~fo~~||—<br>~~ft~~<br>~~ft~~<br>~~ft~~|756<br>~~ft~~<br>~~tf~~<br>~~ft~~<br>~~tf~~<br>~~ft~~<br>~~tf~~|—<br>~~tf fF~~<br>~~tffF~~<br>~~tffF~~|630<br>~~fF~~<br>~~fFfff~~<br>~~fF~~|—<br><br>~~fff~~<br>|524<br><br>~~fff~~<br>|Mbps<br><br>~~fff~~<br>|
|fDDRX4<br>~~fo~~<br>~~fo~~<br>~~ee~~|DDRX4 ECLK Frequency<br>(minimum limited byPLL)<br>~~fo~~<br>~~fo~~<br>~~eee~~||—<br>~~ft~~<br>~~ft~~<br>~~a~~|378<br>~~ft~~<br>~~tf~~<br>~~ft~~<br>~~tf~~|—<br>~~tf fF~~<br>~~tffF~~|315<br>~~fF~~<br>~~fFfff~~|—<br><br>~~fff~~|262<br><br>~~fff~~|MHz<br><br>~~fff~~|
|fSCLK<br>~~fo~~<br>~~ee~~|SCLK Frequency<br>~~fo~~<br>~~eee~~||—<br>~~ft~~<br>~~a~~|95<br>~~ft~~<br>~~tf~~|—<br>~~tf fF~~|79<br>~~fFfff~~|—<br>~~fff~~|66<br>~~fff~~|MHz<br>~~fff~~|
|**7:1 LVDS Outputs – GDDR71_TX.ECLK.7:19, 11**<br>~~fff~~<br>~~ee eee~~<br>~~a~~<br>~~Bee~~<br>~~f~~~~**f**ft~~<br>~~fo~~||||||||||
|tDIB<br>~~Bee~~<br>~~|~~<br>~~fo~~<br>~~Ff~~|Output Data Invalid Before<br>CLK Output<br>~~Bee~~<br>~~|~~<br>~~fo~~<br>~~Ff~~|MachXO2-640U,<br>MachXO2-1200/U and<br>larger devices, top side<br>only<br>~~Bee~~|—<br>~~Bee~~<br>~~ff~~<br>|0.160<br>~~Bee~~<br>~~ff~~<br>|—<br>~~Bee~~<br>~~ff~~<br>~~f~~<br>~~ff~~|0.180<br>~~Bee~~<br>~~ff~~<br>~~f~~~~**f**~~<br>~~ff~~|—<br>~~Bee~~<br>~~ff~~<br>~~**f**ft~~<br>~~ff~~|0.200<br>~~Bee~~<br>~~ff~~<br>~~ft~~|ns<br>~~Bee~~<br>~~ff~~<br>~~ft~~|
|tDIA<br>~~|~~<br>~~fo~~<br>~~Ff~~<br>~~rr~~|Output Data Invalid After<br>CLK Output<br>~~|~~<br>~~fo~~<br>~~Ff~~<br>~~rr~~||—<br>~~ff~~<br>~~F~~|0.160<br>~~ff~~<br>~~F~~|—<br>~~ff~~<br>~~f~~<br>~~Fff~~<br>~~ft~~|0.180<br>~~ff~~<br>~~f~~~~**f**~~<br>~~Fff~~<br>~~ft~~|—<br>~~ff~~<br>~~**f**ft~~<br>~~ff~~<br>~~ft tt~~|0.200<br>~~ff~~<br>~~ft~~<br>~~tt~~|ns<br>~~ff~~<br>~~ft~~<br>~~tt~~|
|fDATA<br>~~fo~~<br>~~Ff~~<br>~~rr~~|DDR71 Serial Output Data<br>Speed<br>~~fo~~<br>~~Ff~~<br>~~rr~~||—<br>~~F~~<br>~~fof~~|756<br>~~F~~<br>~~fof~~|—<br>~~f~~<br>~~Fff~~<br>~~fof~~<br>~~ft~~|630<br>~~f~~~~**f**~~<br>~~Fff~~<br>~~fof~~<br>~~ft~~|—<br>~~**f** ft~~<br>~~ff~~<br>~~fof~~<br>~~ft tt~~|524<br>~~ft~~<br>~~fof~~<br>~~tt~~|Mbps<br>~~ft~~<br>~~fof~~<br>~~tt~~|
|fDDR71<br>~~rr~~|DDR71 ECLK Frequency<br>~~rr~~||—|378|—<br>~~ft~~|315<br>~~ft~~|—<br>~~ft tt~~|262<br>~~tt~~|MHz<br>~~tt~~|
|fCLKOUT<br>~~rr~~|7:1 Output Clock<br>Frequency (SCLK)<br>(minimum limited byPLL)<br>~~rr~~||—|108|—<br>~~ft~~|90<br>~~ft~~|—<br>~~ft tt~~|75<br>~~tt~~|MHz<br>~~tt~~|
|**LPDDR9, 11**<br>~~ft tt~~<br>~~rr~~<br>~~eee~~<br>~~f~~~~**f**ft~~<br>~~fo~~||||||||||
|tDVADQ<br>~~eee~~<br>~~fo~~<br>~~fo~~<br>~~fo~~|Input Data Valid After DQS<br>Input<br>~~eee~~<br>~~fo~~<br>~~fo~~<br>~~fo~~|MachXO2-1200/U and<br>larger devices, right<br>side only12<br>~~eee~~|—<br>~~eee~~<br>~~Ff~~<br>|0.369<br>~~eee~~<br>~~Ff~~<br>|—<br>~~eee~~<br>~~Ff~~<br>~~f~~<br>~~f~~|0.395<br>~~eee~~<br>~~Ff~~<br>~~f~~~~**f**~~<br>~~f~~~~**f**~~|—<br>~~eee~~<br>~~Ff~~<br>~~**f**ft~~<br>~~**f**tt~~|0.421<br>~~eee~~<br>~~Ff~~<br>~~ft~~<br>~~tt~~|UI<br>~~eee~~<br>~~Ff~~<br>~~ft~~<br>~~tt~~|
|tDVEDQ<br>~~fo~~<br>~~fo~~<br>~~fo~~<br>~~fo~~|Input Data Hold After DQS<br>Input<br>~~fo~~<br>~~fo~~<br>~~fo~~<br>~~fo~~||0.529<br>~~Ff~~<br>~~F~~<br>|—<br>~~Ff~~<br>~~F~~<br>|0.530<br>~~Ff~~<br>~~f~~<br>~~Ff~~<br>~~ft~~|—<br>~~Ff~~<br>~~f~~~~**f**~~<br>~~Ff~~~~**f**~~<br>~~ft~~|0.527<br>~~Ff~~<br>~~**f**ft~~<br>~~**f**tt~~<br>~~ft~~|—<br>~~Ff~~<br>~~ft~~<br>~~tt~~|UI<br>~~Ff~~<br>~~ft~~<br>~~tt~~|
|tDQVBS<br>~~fo~~<br>~~fo~~<br>~~fo~~<br>~~fo~~|Output Data Invalid Before<br>DQS Output<br>~~fo~~<br>~~fo~~<br>~~fo~~<br>~~fo~~||0.25<br>~~F~~<br>~~F~~<br>~~fF~~|—<br>~~F~~<br>~~F~~<br>~~fFtf~~|0.25<br>~~f~~<br>~~Ff~~<br>~~Fft~~<br>~~tftf~~|—<br>~~f~~~~**f**~~<br>~~Ff~~~~**f**~~<br>~~Fft~~<br>~~tfft~~|0.25<br>~~**f** ft~~<br>~~**f**tt~~<br>~~ft~~<br>~~ft~~|—<br>~~ft~~<br>~~tt~~<br>~~ft~~|UI<br>~~ft~~<br>~~tt~~|
|tDQVAS<br>~~fo~~<br>~~fo~~<br>~~fo~~<br>~~ee~~|Output Data Invalid After<br>DQS Output<br>~~fo~~<br>~~fo~~<br>~~fo~~||0.25<br><br>~~F~~<br>~~fF~~<br>~~ft~~|—<br><br>~~F~~<br>~~fFtf~~<br>~~ftff~~|0.25<br>~~f~~<br>~~Fft~~<br>~~tftf~~<br>~~ff~~|—<br>~~f~~~~**f**~~<br>~~Fft~~<br>~~tfft~~<br>~~ffff~~|0.25<br>~~**f** tt~~<br>~~ft~~<br>~~ft~~<br>~~ff~~|—<br>~~tt~~<br>~~ft~~<br>~~ff~~|UI<br>~~tt~~|
|fDATA<br>~~fo~~<br>~~fo~~<br>~~ee~~<br>~~ee~~|MEM LPDDR Serial Data<br>Speed<br>~~fo~~<br>~~fo~~<br>~~**ee**~~||—<br><br>~~fF~~<br>~~ft~~<br>~~**a**~~|280<br><br>~~fFtf~~<br>~~ftff~~<br>~~**ee**~~|—<br>~~ft~~<br>~~tftf~~<br>~~ff~~<br>~~**ee**~~|250<br>~~ft~~<br>~~tfft~~<br>~~ffff~~<br>~~**e**s~~|—<br>~~ft~~<br>~~ft~~<br>~~ff~~<br>~~es~~|208<br>~~ft~~<br>~~ff~~<br>~~ee~~|Mbps|
|fSCLK<br>~~fo~~<br>~~ee~~<br>~~ee~~|SCLK Frequency<br>~~fo~~<br>~~**ee**~~||—<br>~~fF~~<br>~~ft~~<br>~~**a**~~|140<br>~~fF tf~~<br>~~ftff~~<br>~~**ee**~~|—<br>~~tf tf~~<br>~~ff~~<br>~~**ee**~~|125<br>~~tf ft~~<br>~~ffff~~<br>~~**e**s~~<br>~~e~~|—<br>~~ft~~<br>~~ff~~<br>~~es~~<br>~~ee~~|104<br>~~ft~~<br>~~ff~~<br>~~ee~~<br>~~ee~~|MHz|
|fLPDDR<br>~~ee~~<br>~~ee~~|LPDDR Data Transfer Rate<br>~~**ee**~~||0<br>~~ft~~<br>~~**a**~~|280<br>~~ft ff~~<br>~~**ee**~~|0<br>~~ff~~<br>~~**ee**~~|250<br>~~ff ff~~<br>~~**e**s~~<br>~~e~~|0<br>~~ff~~<br>~~es~~<br>~~ee~~|208<br>~~ff~~<br>~~ee~~<br>~~ee~~|Mbps|
© 2010-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
68
FPGA-DS-02056-4.3
**MachXO2 Family Data Sheet**
**Data Sheet**
|**Parameter**<br>~~ee~~|**Description**<br>~~ee~~|**Device**<br>~~ee~~<br>~~ee Se~~|**–6**<br>~~ee~~<br>~~Se~~|**–6**<br>~~ee~~<br>~~Se~~|**–5**<br>~~ee~~<br>~~Se~~|**–5**<br>~~ee~~<br>~~Se~~|**–4**<br>~~ee~~<br>~~Se~~|**–4**<br>~~ee~~<br>~~Se~~|**Units**<br>~~ee~~<br>~~Se~~|
|---|---|---|---|---|---|---|---|---|---|
||||**Min.**<br>~~ee~~<br>~~Se~~|**Max.**<br>~~ee~~<br>~~Se~~|**Min.**<br>~~ee~~<br>~~Se~~|**Max.**<br>~~ee~~<br>~~Se~~|**Min.**<br>~~ee~~<br>~~Se~~|**Max.**<br>~~ee~~<br>~~Se~~||
|**DDR9, 11**<br>~~ee Se~~<br>~~a~~||||||||||
|tDVADQ<br>~~pf~~<br>~~ee~~|Input Data Valid After DQS<br>Input<br>~~pf~~<br>~~ee~~|MachXO2-1200/U and<br>larger devices, right<br>side only12<br>~~ee~~<br>~~ee~~<br>~~ee~~|—<br>~~|~~<br>~~|~~|0.350<br>|<br>~~|~~|—<br>|<br>~~|~~|0.387<br>|<br>~~|~~|—|0.414|UI|
|tDVEDQ<br>~~ee~~<br>~~ee~~|Input Data Hold After DQS<br>Input<br>~~ee~~<br>~~ee~~||0.545<br>~~|~~<br>~~|~~|—<br>~~|~~<br>~~|~~|0.538<br>~~|~~<br>~~|~~|—<br>~~|~~<br>~~|~~|0.532|—|UI|
|tDQVBS<br>~~ee~~<br>~~ee~~<br>~~ee~~|Output Data Invalid Before<br>DQS Output<br>~~ee~~<br>~~ee~~<br>~~ee~~||0.25<br>~~|~~<br>~~|~~<br>~~|~~|—<br>~~|~~<br>~~|~~<br>~~|~~|0.25<br>~~|~~<br>~~|~~<br>~~|~~|—<br>~~|~~<br>~~|~~<br>~~|~~|0.25|—|UI|
|tDQVAS<br>~~ee~~<br>~~ee~~|Output Data Invalid After<br>DQS Output<br>~~ee~~<br>~~ee~~||0.25<br>~~|~~<br>~~|~~|—<br>~~|~~<br>~~|~~|0.25<br>~~|~~<br>~~|~~|—<br>~~|~~<br>~~|~~|0.25|—|UI|
|fDATA<br>~~ee~~<br>~~pf~~|MEM DDR Serial Data<br>Speed<br>~~ee~~<br>~~pf~~||—<br>~~|~~<br>~~i~~|300<br>~~|~~<br>||—<br>~~|~~<br>||250<br>~~|~~<br>||—|208|Mbps|
|fSCLK<br>~~a~~<br>~~pf~~|SCLK Frequency<br>~~pf~~||—<br>~~a~~<br>~~pt~~|150<br>~~a~~<br>~~pt~~<br>~~|~~|—<br>~~|~~|125<br>~~tlt~~|—<br>~~tlt~~|104<br>~~tlt~~|MHz<br>~~tlt~~|
|fMEM_DDR<br>~~a~~<br>~~pf~~|MEM DDR Data Transfer<br>Rate<br>~~pf~~||N/A<br>~~a~~<br>~~pt~~|300<br>~~a~~<br>~~pt~~<br>~~|~~|N/A<br>~~|~~|250<br>~~tlt~~|N/A<br>~~tlt~~|208<br>~~tlt~~|Mbps<br>~~tlt~~|
|**DDR9, 11**<br>~~pf~~<br>~~pt~~<br>~~|~~<br>~~|tlt~~<br>~~pf~~<br>~~ei~~<br>~~|~~<br>|<br>~~tt~~||||||||||
|tDVADQ<br>~~pf~~<br>~~Pf~~|Input Data Valid After DQS<br>Input<br>~~pf~~<br>~~Pf~~|MachXO2-1200/U and<br>larger devices, right<br>side only12|—<br>~~ei~~<br>~~ei~~|0.360<br>~~ei~~<br>~~|~~<br>~~ei~~<br>~~|~~|—<br>|<br>||0.378<br>~~tt~~<br>~~tt~~|—<br>~~tt~~<br>~~tt~~|0.406<br>~~tt~~|UI<br>~~tt~~|
|tDVEDQ<br>~~pf~~<br>~~Pf~~<br>~~Pf~~|Input Data Hold After DQS<br>Input<br>~~pf~~<br>~~Pf~~<br>~~Pf~~||0.555<br>~~ei~~<br>~~ei~~<br>~~ei~~|—<br>~~ei~~<br>~~|~~<br>~~ei~~<br>~~|~~<br>~~ei~~<br>~~|~~|0.549<br>|<br>|<br>||—<br>~~tt~~<br>~~tt~~<br>~~tt~~|0.542<br>~~tt~~<br>~~tt~~<br>~~tt~~|—<br>~~tt~~<br>~~tt~~|UI<br>~~tt~~<br>~~tt~~|
|tDQVBS<br>~~Pf~~<br>~~Pf~~<br>~~Pf~~|Output Data Invalid Before<br>DQS Output<br>~~Pf~~<br>~~Pf~~<br>~~Pf~~||0.25<br>~~ei~~<br>~~ei~~<br>~~ei~~|—<br>~~ei~~<br>~~|~~<br>~~ei~~<br>~~|~~<br>~~ei~~<br>~~|~~|0.25<br>|<br>|<br>||—<br>~~tt~~<br>~~tt~~<br>~~tt~~|0.25<br>~~tt~~<br>~~tt~~<br>~~tt~~|—<br>~~tt~~<br>~~tt~~<br>~~tt~~|UI<br>~~tt~~<br>~~tt~~<br>~~tt~~|
|tDQVAS<br>~~Pf~~<br>~~Pf~~<br>~~Pf~~|Output Data Invalid After<br>DQS Output<br>~~Pf~~<br>~~Pf~~<br>~~Pf~~||0.25<br>~~ei~~<br>~~ei~~<br>~~ei~~|—<br>~~ei~~<br>~~|~~<br>~~ei~~<br>~~|~~<br>~~ei~~<br>~~|~~|0.25<br>|<br>|<br>||—<br>~~tt~~<br>~~tt~~<br>~~tt~~|0.25<br>~~tt~~<br>~~tt~~<br>~~tt~~|—<br>~~tt~~<br>~~tt~~<br>~~tt~~|UI<br>~~tt~~<br>~~tt~~<br>~~tt~~|
|fDATA<br>~~Pf~~<br>~~Pf~~|MEM DDR Serial Data<br>Speed<br>~~Pf~~<br>~~Pf~~||—<br>~~ei~~<br>~~ei~~|300<br>~~ei~~<br>~~|~~<br>~~ei~~<br>~~|~~|—<br>|<br>||250<br>~~tt~~<br>~~tt~~|—<br>~~tt~~<br>~~tt~~|208<br>~~tt~~<br>~~tt~~|Mbps<br>~~tt~~<br>~~tt~~|
|fSCLK<br>~~Pf~~<br>~~a~~|SCLK Frequency<br>~~Pf~~||—<br>~~ei~~<br>~~a~~|150<br>~~ei~~<br>~~|~~<br>~~a~~|—<br>|<br>~~a~~<br>~~|~~|125<br>~~tt~~<br>~~a~~<br>~~|tt~~|—<br>~~tt~~<br>~~a~~<br>~~tt~~|104<br>~~tt~~<br>~~a~~<br>~~tt~~|MHz<br>~~tt~~<br>~~a~~|
|fMEM_DDR2<br>~~a~~<br>~~pt~~|MEM DDR2 Data Transfer<br>Rate<br>~~pt~~||N/A<br>~~a~~<br>~~et}~~|300<br>~~a~~<br>~~et}~~|N/A<br>~~a~~<br>~~et}~~<br>~~|~~|250<br>~~a~~<br>~~et}~~<br>~~|tt~~|N/A<br>~~a~~<br>~~et}~~<br>~~tt~~|208<br>~~a~~<br>~~et}~~<br>~~tt~~|Mbps<br>~~a~~<br>~~et}~~|
**Notes:**
1. Exact performance may vary with the device and design implementation. Commercial timing numbers are shown at 85 °C and
- 1.14 V. Other operating conditions, including industrial and automotive, can be extracted from the Diamond software.
2. General I/O timing numbers based on LVCMOS 2.5, 8 mA, 0pf load, fast slew rate.
3. Generic DDR timing numbers based on LVDS I/O (for input, output, and clock ports).
4. DDR timing numbers based on SSTL25. DDR2 timing numbers based on SSTL18. LPDDR timing numbers based in LVCMOS18.
5. 7:1 LVDS (GDDR71) uses the LVDS I/O standard (for input, output, and clock ports).
6. For Generic DDRX1 mode tSU = tHO = (tDVE - tDVA - 0.03 ns)/2.
7. The tSU_DEL and tH_DEL values use the SCLK_ZERHOLD default step size. Each step is 105 ps (–6), 113 ps (–5), 120 ps (–4).
8. This number is for general purpose usage. Duty cycle tolerance is +/– 10%.
9. Duty cycle is +/–5% for system usage.
10. The above timing numbers are generated using the Diamond design tool. Exact performance may vary with the device selected.
11. Advance information for MachXO2 devices in 48 QFN packages.
12. DDR memory interface not supported in QN84 (84 QFN) and SG32 (32 QFN) packages.
## **3.22. MachXO2 External Switching Characteristics – ZE Devices**
Over Recommended Operating Conditions
© 2010-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02056-4.3
69
**MachXO2 Family Data Sheet Data Sheet**
|**Parameter**<br>~~ee~~|**Description**<br>~~ee~~|**Device**<br>~~ee~~<br>~~ee a~~|**–3**<br>~~ee~~<br>~~aee~~|**–3**<br>~~ee~~<br>~~aee~~|**–2**<br>~~ee~~<br>~~ee~~|**–2**<br>~~ee~~<br>~~ee~~|**–1**<br>~~ee~~<br>~~ee~~|**–1**<br>~~ee~~<br>~~ee~~|**Units**<br>~~ee~~|
|---|---|---|---|---|---|---|---|---|---|
||||**Min.**<br>~~ee~~<br>~~a~~|**Max.**<br>~~ee~~<br>~~ee~~|**Min.**<br>~~ee~~<br>~~ee~~|**Max.**<br>~~ee~~<br>~~ee~~|**Min.**<br>~~ee~~<br>~~ee~~|**Max.**<br>~~ee~~<br>~~ee~~||
|**Clocks**<br>~~ee aeeee~~<br>~~Re~~||||||||||
|**Primary Clocks**<br>~~ee a ee ee~~<br>~~pn~~||||||||||
|fMAX_PRI8<br>~~a~~|Frequency for Primary Clock<br>Tree<br>~~ee~~|All MachXO2<br>devices<br>~~ee~~|—<br>~~ee~~|150<br>~~ee~~|—<br>~~ee~~|125<br>~~ee~~|—<br>~~ee~~|104<br>~~ee~~|MHz<br>~~ee~~|
|tW_PRI<br>~~a~~|Clock Pulse Width for Primary<br>Clock<br>~~ee~~|All MachXO2<br>devices<br>~~ee~~|1.00<br>~~ee~~<br>~~es~~|—<br>~~ee~~<br>~~ed~~|1.20<br>~~ee~~|—<br>~~ee~~|1.40<br>~~ee~~|—<br>~~ee~~|ns<br>~~ee~~|
|tSKEW_PRI|Primary Clock Skew Within a<br>Device<br>~~po~~<br>~~po~~|MachXO2-256ZE<br>~~es~~<br>~~po~~|—<br>~~es~~<br>~~es~~<br>~~es~~|1250<br>~~es~~<br>~~ed~~<br>~~es~~|—<br>~~es~~|1272<br>~~es~~|—<br>~~es~~|1296<br>~~es~~|ps<br>~~es~~|
|||MachXO2-640ZE<br>~~es~~<br>~~po~~|—<br>~~es ~~<br>~~es~~<br>~~es~~|1161<br> ~~ed~~<br>~~es~~<br>~~es~~|—<br>~~es~~|1183<br>~~es~~|—<br>~~es~~|1206<br>~~es~~|ps<br>~~es~~|
|||MachXO2-1200ZE<br>~~po~~<br>~~po~~|—<br>~~es~~|1213<br>~~es~~|—|1267|—|1322|ps|
|||MachXO2-2000ZE<br>~~po~~<br>~~po~~|—<br>~~es ~~|1204<br> ~~es~~|—|1250|—|1296|ps|
|||MachXO2-4000ZE<br>~~po~~<br>~~po~~|—<br>~~po~~|1195<br>~~po~~|—<br>~~po~~|1233<br>~~po~~|—<br>~~po~~|1269<br>~~po~~|ps<br>~~po~~|
|||MachXO2-7000ZE<br>~~po~~<br>~~pO~~|—<br>~~po~~<br>~~pO~~|1243<br>~~po~~<br>~~pO~~|—<br>~~po~~<br>~~pO~~|1268<br>~~po~~<br>~~pO~~|—<br>~~po~~<br>~~pO~~|1296<br>~~po~~<br>~~pO~~|ps<br>~~po~~<br>~~pO~~|
|**Edge Clock**<br>~~pT~~||||||||||
|fMAX_EDGE8<br>~~a ee~~|Frequency for Edge Clock<br>~~ee~~|MachXO2-1200 and<br>larger devices<br>~~ee~~|—<br>~~ee~~|210<br>~~ee~~|—<br>~~ee~~|175<br>~~ee~~|—<br>~~ee~~|146<br>~~ee~~|MHz<br>~~ee~~|
|**Pin-LUT-Pin Propagation Delay**||||||||||
|tPD<br>~~a~~|Best case propagation delay<br>through one LUT-4<br>~~ee~~|All MachXO2<br>devices<br>~~ee~~|—<br>~~ee~~|9.35<br>~~ee~~|—<br>~~ee~~|9.78<br>~~ee~~|—<br>~~ee~~|10.21<br>~~ee~~|ns<br>~~ee~~|
|**General I/O Pin Parameters (Using Primary Clock without PLL)**<br>~~Pe~~<br>~~es~~<br>~~po~~||||||||||
|tCO<br>~~Pe~~|Clock to Output – PIO Output<br>Register<br>~~Pe~~<br>~~po~~<br>~~po~~|MachXO2-256ZE<br>~~Pe~~<br>~~es~~<br>~~po~~|—<br>~~Pe~~<br>~~es~~<br>~~es~~|10.46<br>~~Pe~~<br>~~es~~|—<br>~~Pe~~<br>~~es~~|10.86<br>~~Pe~~<br>~~es~~|—<br>~~Pe~~<br>~~es~~|11.25<br>~~Pe~~<br>~~es~~|ns<br>~~Pe~~<br>~~es~~|
|||MachXO2-640ZE<br>~~es~~<br>~~po~~|—<br>~~es~~<br>~~es~~<br>~~ed~~|10.52<br>~~es~~|—<br>~~es~~|10.92<br>~~es~~|—<br>~~es~~|11.32<br>~~es~~|ns<br>~~es~~|
|||MachXO2-1200ZE<br>~~po~~<br>~~es~~|—<br>~~es~~<br>~~es~~<br>~~ed~~|11.24<br>~~es~~<br>~~de~~|—<br>~~es~~<br>~~de~~|11.68<br>~~es~~|—<br>~~es~~|12.12<br>~~es~~|ns<br>~~es~~|
|||MachXO2-2000ZE<br>~~ee~~|—<br>~~ed~~<br>~~ee~~<br>~~es~~|11.27<br>~~ee~~<br>~~de~~<br>~~es~~|—<br>~~ee~~<br>~~de~~|11.71<br>~~ee~~|—<br>~~ee~~|12.16<br>~~ee~~|ns<br>~~ee~~|
|||MachXO2-4000ZE<br>~~ee~~<br>~~es~~|—<br>~~ee~~<br>~~es~~<br>~~es~~<br>~~es~~|11.28<br>~~ee~~<br>~~de~~<br>~~es~~<br>~~es~~<br>~~es~~|—<br>~~ee~~<br>~~de~~<br>~~es~~|11.78<br>~~ee~~<br>~~es~~|—<br>~~ee~~<br>~~es~~|12.28<br>~~ee~~<br>~~es~~|ns<br>~~ee~~<br>~~es~~|
|||MachXO2-7000ZE<br>~~es~~<br>~~es~~<br>~~po~~|—<br>~~es~~<br>~~es ~~<br>~~es~~<br>~~es~~<br>~~es~~|11.22<br>~~es~~<br> ~~es~~<br>~~es~~<br>~~es~~<br>~~es~~|—<br>~~es~~<br>~~es~~<br>~~es~~|11.76<br>~~es~~<br>~~es~~<br>~~es~~|—<br>~~es~~<br>~~es~~|12.30<br>~~es~~<br>~~es~~|ns<br>~~es~~<br>~~es~~|
|tSU|Clock to Data Setup – PIO<br>Input Register<br>~~po~~<br>~~po~~<br>~~po~~|MachXO2-256ZE<br>~~es~~<br>~~es~~<br>~~po~~|–0.21<br>~~es~~<br>~~es ~~<br>~~es~~<br>~~es~~|—<br>~~es~~<br> ~~es~~<br>~~es~~<br>~~es~~|–0.21<br>~~es~~<br>~~es~~<br>~~es~~|—<br>~~es~~<br>~~es~~<br>~~es~~|–0.21<br>~~es~~<br>~~es~~|—<br>~~es~~<br>~~es~~|ns<br>~~es~~<br>~~es~~|
|||MachXO2-640ZE<br>~~po~~|–0.22<br>~~es~~|—<br>~~es~~|–0.22<br>~~es~~<br>~~ee~~|—<br>~~es~~<br>~~ee~~|–0.22|—|ns|
|||MachXO2-1200ZE<br>~~po~~<br>~~ed~~|–0.25<br>~~es ~~<br>~~ed~~<br>~~es~~|—<br> ~~es~~<br>~~ed~~<br>~~es~~|–0.25<br>~~es~~<br>~~ed~~<br>~~ee~~|—<br>~~es~~<br>~~ed~~<br>~~ee~~|–0.25<br>~~ed~~|—<br>~~ed~~|ns<br>~~ed~~|
|||MachXO2-2000ZE<br>~~ed~~<br>~~es~~<br>~~po~~|–0.27<br>~~ed~~<br>~~es~~<br>~~es~~<br>~~es~~|—<br>~~ed~~<br>~~es~~<br>~~es~~<br>~~es~~|–0.27<br>~~ed~~<br>~~ee~~<br>~~es~~|—<br>~~ed~~<br>~~ee~~<br>~~es~~|–0.27<br>~~ed~~<br>~~es~~|—<br>~~ed~~<br>~~es~~|ns<br>~~ed~~<br>~~es~~|
|||MachXO2-4000ZE<br>~~es~~<br>~~es~~<br>~~po~~|–0.31<br>~~es~~<br>~~es ~~<br>~~es~~<br>~~es~~|—<br>~~es~~<br> ~~es~~<br>~~es~~<br>~~es~~|–0.31<br>~~es~~<br>~~es~~|—<br>~~es~~<br>~~es~~|–0.31<br>~~es~~<br>~~es~~|—<br>~~es~~<br>~~es~~|ns<br>~~es~~<br>~~es~~|
|||MachXO2-7000ZE<br>~~es~~<br>~~po~~<br>~~po~~|–0.33<br>~~es~~<br>~~es~~|—<br>~~es~~<br>~~es~~|–0.33<br>~~es~~|—<br>~~es~~|–0.33<br>~~es~~|—<br>~~es~~|ns<br>~~es~~|
|tH|Clock to Data Hold – PIO<br>Input Register<br>~~po~~<br>~~po~~<br>~~po~~<br>~~po~~|MachXO2-256ZE<br>~~po~~<br>~~po~~<br>~~po~~|3.96<br>~~es ~~|—<br> ~~es~~|4.25|—|4.65|—|ns|
|||MachXO2-640ZE<br>~~po~~<br>~~po~~|4.01|—|4.31<br>~~se~~|—<br>~~se~~|4.71|—|ns|
|||MachXO2-1200ZE<br>~~po~~<br>~~ed~~|3.95<br>~~ed~~<br>~~es~~|—<br>~~ed~~<br>~~es~~|4.29<br>~~ed~~<br>~~se~~|—<br>~~ed~~<br>~~se~~|4.73<br>~~ed~~|—<br>~~ed~~|ns<br>~~ed~~|
|||MachXO2-2000ZE<br>~~ed~~<br>~~es~~<br>~~po~~|3.94<br>~~ed~~<br>~~es~~<br>~~es~~<br>~~es~~|—<br>~~ed~~<br>~~es~~<br>~~es~~<br>~~es~~|4.29<br>~~ed~~<br>~~se~~<br>~~es~~|—<br>~~ed~~<br>~~se~~<br>~~es~~|4.74<br>~~ed~~<br>~~es~~|—<br>~~ed~~<br>~~es~~|ns<br>~~ed~~<br>~~es~~|
|||MachXO2-4000ZE<br>~~es~~<br>~~es~~<br>~~po~~|3.96<br>~~es~~<br>~~es ~~<br>~~es~~<br>~~es~~|—<br>~~es~~<br> ~~es~~<br>~~es~~<br>~~es~~|4.36<br>~~es~~<br>~~es~~|—<br>~~es~~<br>~~es~~|4.87<br>~~es~~<br>~~es~~|—<br>~~es~~<br>~~es~~|ns<br>~~es~~<br>~~es~~|
|||MachXO2-7000ZE<br>~~es~~<br>~~po~~<br>~~Re~~|3.93<br>~~es~~<br>~~es~~<br>~~ee~~|—<br>~~es~~<br>~~es~~<br>~~ee~~|4.37<br>~~es~~<br>~~ee~~|—<br>~~es~~|4.91<br>~~es~~|—<br>~~es~~|ns<br>~~es~~|
|tSU_DEL|Clock to Data Setup – PIO<br>Input Register with Data<br>Input Delay<br>~~po~~<br>~~pO~~<br>~~po~~<br>~~po~~|MachXO2-256ZE<br>~~po~~<br>~~Re~~<br>~~pO~~|2.62<br>~~es ~~<br>~~ee~~<br>~~es~~|—<br> ~~es~~<br>~~ee~~<br>~~es~~|2.91<br>~~ee~~|—|3.14|—|ns|
|||MachXO2-640ZE<br>~~Re ~~<br>~~es~~<br>~~pO~~|2.56<br> ~~ee~~<br>~~es~~<br>~~es~~|—<br>~~ee~~<br>~~es~~<br>~~es~~|2.85<br>~~ee~~<br>~~es~~|—<br>~~es~~|3.08<br>~~es~~|—<br>~~es~~|ns<br>~~es~~|
|||MachXO2-1200ZE<br>~~es~~<br>~~pO~~<br>~~po~~|2.30<br>~~es~~<br>~~es~~|—<br>~~es~~<br>~~es~~|2.57<br>~~es~~|—<br>~~es~~|2.79<br>~~es~~|—<br>~~es~~|ns<br>~~es~~|
|||MachXO2-2000ZE<br>~~pO~~<br>~~po~~<br>~~po~~|2.25<br>~~es ~~|—<br> ~~es~~|2.50|—|2.70|—|ns|
|||MachXO2-4000ZE<br>~~po~~<br>~~po~~|2.39|—|2.60|—|2.76|—|ns|
|||MachXO2-7000ZE<br>~~po~~<br>~~po~~|2.17<br>~~po~~|—<br>~~po~~|2.33<br>~~po~~|—<br>~~po~~|2.43<br>~~po~~|—<br>~~po~~|ns<br>~~po~~|
**Table 3.27. MachXO2 External Switching Characteristics – ZE Devices[1, 2, 3, 4, 5, 6, 7]**
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70
FPGA-DS-02056-4.3
**MachXO2 Family Data Sheet Data Sheet**
|**Parameter**<br>~~a~~|**Description**<br>~~a~~|**Device**<br>~~a~~<br>~~ee eee~~|**–3**<br>~~a~~<br>~~eee~~|**–3**<br>~~a~~<br>~~eee~~|**–2**<br>~~a~~<br>~~eee~~|**–2**<br>~~a~~<br>~~eee~~|**–1**<br>~~a~~<br>~~eee~~|**–1**<br>~~a~~<br>~~eee~~|**Units**<br>~~a~~|
|---|---|---|---|---|---|---|---|---|---|
||||**Min.**<br>~~a~~<br>~~eee~~|**Max.**<br>~~a~~<br>~~eee~~|**Min.**<br>~~a~~<br>~~eee~~|**Max.**<br>~~a~~<br>~~eee~~|**Min.**<br>~~a~~<br>~~eee~~|**Max.**<br>~~a~~<br>~~eee~~||
|tH_DEL|Clock to Data Hold – PIO<br>Input Register with Input<br>Data Delay<br>~~po~~<br>~~po~~|MachXO2-256ZE<br>~~ee eee~~<br>~~eG~~<br>~~po~~|–0.44<br>~~eee~~<br>~~eG~~<br>~~ee~~|—<br>~~eee~~<br>~~eG~~<br>~~ee~~|–0.44<br>~~eee~~<br>~~eG~~|—<br>~~eee~~<br>~~eG~~|–0.44<br>~~eee~~<br>~~eG~~|—<br>~~eee~~<br>~~eG~~|ns<br>~~eG~~|
|||MachXO2-640ZE<br>~~ee eee~~<br>~~Re~~<br>~~po~~|–0.43<br>~~eee~~<br>~~Re~~<br>~~ee~~|—<br>~~eee~~<br>~~Re~~<br>~~ee~~|–0.43<br>~~eee~~<br>~~Re~~|—<br>~~eee~~<br>~~Re~~|–0.43<br>~~eee~~<br>~~Re~~|—<br>~~eee~~<br>~~Re~~|ns<br>~~Re~~|
|||MachXO2-1200ZE<br>~~po~~<br>~~po~~|–0.28<br>~~ee~~<br>~~es~~|—<br>~~ee~~|–0.28|—|–0.28|—|ns|
|||MachXO2-2000ZE<br>~~po~~<br>~~es~~<br>~~po~~|–0.31<br>~~ee~~<br>~~es~~<br>~~es~~|—<br>~~ee~~<br>~~es~~|–0.31<br>~~es~~|—<br>~~es~~|–0.31<br>~~es~~|—<br>~~es~~|ns<br>~~es~~|
|||MachXO2-4000ZE<br>~~po~~|–0.34<br>~~es~~|—|–0.34|—|–0.34|—|ns|
|||MachXO2-7000ZE<br>~~po~~|–0.21<br>~~es~~|—|–0.21|—|–0.21|—|ns|
|fMAX_IO<br>~~a~~|Clock Frequency of I/O and<br>PFU Register<br>~~ee~~|All MachXO2<br>devices<br>~~ee~~|—<br>~~ee~~|150<br>~~ee~~|—<br>~~ee~~|125<br>~~ee~~|—<br>~~ee~~|104<br>~~ee~~|MHz<br>~~ee~~|
|**General I/O Pin Parameters (Using Edge Clock without PLL)**<br>~~Rn~~<br>~~eses~~<br>~~pO~~||||||||||
|tCOE|Clock to Output – PIO Output<br>Register<br>~~pO~~<br>~~po~~<br>~~pO~~|MachXO2-1200ZE<br>~~es~~<br>~~pO~~|—<br>~~es~~<br>~~es~~|11.10<br>~~es~~<br>~~es~~|—<br>~~es~~|11.51<br>~~es~~|—<br>~~es~~|11.91<br>~~es~~|ns<br>~~es~~|
|||MachXO2-2000ZE<br>~~pO~~|—<br>~~es~~|11.10<br>~~es~~|—|11.51|—|11.91|ns|
|||MachXO2-4000ZE<br>~~pO~~<br>~~es~~<br>~~po~~|—<br>~~es ~~<br>~~es~~|10.89<br> ~~es~~<br>~~es~~|—<br>~~es~~|11.28<br>~~es~~|—<br>~~es~~|11.67<br>~~es~~|ns<br>~~es~~|
|||MachXO2-7000ZE<br>~~es~~<br>~~po~~<br>~~pO~~|—<br>~~es~~|11.10<br>~~es~~|—<br>~~es~~|11.51<br>~~es~~|—<br>~~es~~|11.91<br>~~es~~|ns<br>~~es~~|
|tSUE|Clock to Data Setup – PIO<br>Input Register<br>~~po~~<br>~~pO~~<br>~~po~~<br>~~po~~|MachXO2-1200ZE<br>~~po~~<br>~~pO~~<br>~~po~~|–0.23|—|–0.23|—|–0.23|—|ns|
|||MachXO2-2000ZE<br>~~pO~~<br>~~po~~<br>~~po~~|–0.23|—|–0.23|—|–0.23|—|ns|
|||MachXO2-4000ZE<br>~~po~~<br>~~po~~|–0.15|—<br>~~ee~~|–0.15<br>~~ee~~|—<br>~~ee~~|–0.15<br>~~ee~~|—|ns|
|||MachXO2-7000ZE<br>~~po~~<br>~~es~~|–0.23<br>~~es~~<br>~~es~~|—<br>~~es~~<br>~~ee~~<br>~~es~~|–0.23<br>~~es~~<br>~~ee~~|—<br>~~es~~<br>~~ee~~|–0.23<br>~~es~~<br>~~ee~~|—<br>~~es~~|ns<br>~~es~~|
|tHE|Clock to Data Hold – PIO<br>Input Register<br>~~po~~<br>~~po~~<br>~~po~~|MachXO2-1200ZE<br>~~es~~<br>~~es~~<br>~~po~~|3.81<br>~~es~~<br>~~es~~<br>~~es~~<br>~~es~~|—<br>~~es~~<br>~~ee~~<br>~~es~~<br>~~es~~<br>~~es~~|4.11<br>~~es~~<br>~~ee ~~<br>~~es~~|—<br>~~es~~<br> ~~ee~~<br>~~es~~|4.52<br>~~es~~<br>~~ee~~<br>~~es~~|—<br>~~es~~<br>~~es~~|ns<br>~~es~~<br>~~es~~|
|||MachXO2-2000ZE<br>~~es~~<br>~~es~~<br>~~po~~|3.81<br>~~es~~<br>~~es ~~<br>~~es~~<br>~~es~~|—<br>~~es~~<br> ~~es~~<br>~~es~~<br>~~es~~|4.11<br>~~es~~<br>~~es~~|—<br>~~es~~<br>~~es~~|4.52<br>~~es~~<br>~~es~~|—<br>~~es~~<br>~~es~~|ns<br>~~es~~<br>~~es~~|
|||MachXO2-4000ZE<br>~~es~~<br>~~po~~<br>~~po~~|3.60<br>~~es~~<br>~~es~~|—<br>~~es~~<br>~~es~~|3.89<br>~~es~~|—<br>~~es~~|4.28<br>~~es~~|—<br>~~es~~|ns<br>~~es~~|
|||MachXO2-7000ZE<br>~~po~~<br>~~po~~<br>~~po~~|3.81<br>~~es ~~|—<br> ~~es~~|4.11|—|4.52|—|ns|
|tSU_DELE|Clock to Data Setup – PIO<br>Input Register with Data<br>Input Delay<br>~~po~~<br>~~po~~<br>~~po~~|MachXO2-1200ZE<br>~~po~~<br>~~po~~|2.78|—|3.11|—|3.40|—|ns|
|||MachXO2-2000ZE<br>~~po~~<br>~~ee~~|2.78<br>~~ee~~<br>~~ed~~|—<br>~~ee~~<br>~~es~~|3.11<br>~~ee~~|—<br>~~ee~~|3.40<br>~~ee~~|—<br>~~ee~~|ns<br>~~ee~~|
|||MachXO2-4000ZE<br>~~ee~~<br>~~es~~|3.11<br>~~ee~~<br>~~es~~<br>~~ed~~|—<br>~~ee~~<br>~~es~~<br>~~es~~|3.48<br>~~ee~~<br>~~es~~|—<br>~~ee~~<br>~~es~~|3.79<br>~~ee~~<br>~~es~~|—<br>~~ee~~<br>~~es~~|ns<br>~~ee~~<br>~~es~~|
|||MachXO2-7000ZE<br>~~es~~<br>~~po~~<br>~~po~~|2.94<br>~~es~~<br>~~ed ~~<br>~~po~~|—<br>~~es~~<br> ~~es~~<br>~~po~~|3.30<br>~~es~~<br>~~po~~|—<br>~~es~~<br>~~po~~|3.60<br>~~es~~<br>~~po~~|—<br>~~es~~<br>~~po~~|ns<br>~~es~~<br>~~po~~|
|tH_DELE|Clock to Data Hold – PIO<br>Input Register with Input<br>Data Delay<br>~~po~~<br>~~po~~|MachXO2-1200ZE<br>~~po~~<br>~~po~~|–0.29|—|-0.29|—|–0.29|—|ns|
|||MachXO2-2000ZE<br>~~po~~<br>~~po~~|–0.29|—|-0.29|—|–0.29|—|ns|
|||MachXO2-4000ZE<br>~~po~~<br>~~ds~~|–0.46<br>~~ds~~<br>~~es~~|—<br>~~ds~~<br>~~es~~|-0.46<br>~~ds~~|—<br>~~ds~~|–0.46<br>~~ds~~|—<br>~~ds~~|ns<br>~~ds~~|
|||MachXO2-7000ZE<br>~~ds~~<br>~~es~~|–0.37<br>~~ds~~<br>~~es~~<br>~~es~~|—<br>~~ds~~<br>~~es~~<br>~~es~~|-0.37<br>~~ds~~<br>~~es~~|—<br>~~ds~~<br>~~es~~|–0.37<br>~~ds~~<br>~~es~~|—<br>~~ds~~<br>~~es~~|ns<br>~~ds~~<br>~~es~~|
|**General I/O Pin Parameters (Using Primary Clock with PLL)**<br>~~es~~<br>~~es es~~<br>~~pT~~||||||||||
|tCOPLL|Clock to Output – PIO Output<br>Register<br>~~po~~|MachXO2-1200ZE<br>~~ss~~|—<br>~~ss~~|7.95<br>~~ss~~|—<br>~~ss~~|8.07<br>~~ss~~|—<br>~~ss~~|8.19<br>~~ss~~|ns<br>~~ss~~|
|||MachXO2-2000ZE<br>~~ds~~|—<br>~~ds~~<br>~~ed~~|7.97<br>~~ds~~<br>~~es~~|—<br>~~ds~~|8.10<br>~~ds~~|—<br>~~ds~~|8.22<br>~~ds~~|ns<br>~~ds~~|
|||MachXO2-4000ZE<br>~~ds~~<br>~~es~~<br>~~po~~|—<br>~~ds~~<br>~~es~~<br>~~ed~~<br>~~es~~|7.98<br>~~ds~~<br>~~es~~<br>~~es~~<br>~~es~~|—<br>~~ds~~<br>~~es~~|8.10<br>~~ds~~<br>~~es~~|—<br>~~ds~~<br>~~es~~|8.23<br>~~ds~~<br>~~es~~|ns<br>~~ds~~<br>~~es~~|
|||MachXO2-7000ZE<br>~~es~~<br>~~es~~<br>~~po~~|—<br>~~es~~<br>~~ed ~~<br>~~es~~<br>~~es~~|8.02<br>~~es~~<br> ~~es~~<br>~~es~~<br>~~es~~|—<br>~~es~~<br>~~es~~|8.14<br>~~es~~<br>~~es~~|—<br>~~es~~<br>~~es~~|8.26<br>~~es~~<br>~~es~~|ns<br>~~es~~<br>~~es~~|
|tSUPLL|Clock to Data Setup – PIO<br>Input Register<br>~~po~~<br>~~po~~<br>~~po~~<br>~~po~~|MachXO2-1200ZE<br>~~es~~<br>~~po~~<br>~~po~~|0.85<br>~~es~~<br>~~es~~|—<br>~~es~~<br>~~es~~|0.85<br>~~es~~|—<br>~~es~~|0.89<br>~~es~~|—<br>~~es~~|ns<br>~~es~~|
|||MachXO2-2000ZE<br>~~po~~<br>~~po~~<br>~~po~~|0.84<br>~~es ~~|—<br> ~~es~~<br>~~se~~|0.84<br>~~se~~|—<br>~~ee~~|0.86<br>~~ee~~|—|ns|
|||MachXO2-4000ZE<br>~~po~~<br>~~ee~~<br>~~po~~|0.84<br>~~ee~~|—<br>~~ee~~<br>~~se~~|0.84<br>~~ee~~<br>~~se~~|—<br>~~ee~~<br>~~ee~~|0.85<br>~~ee~~<br>~~ee~~|—<br>~~ee~~|ns<br>~~ee~~|
|||MachXO2-7000ZE<br>~~ee~~<br>~~po~~<br>~~po~~|0.83<br>~~ee~~|—<br>~~ee~~<br>~~se~~|0.83<br>~~ee~~<br>~~se~~|—<br>~~ee~~<br>~~ee~~|0.81<br>~~ee~~<br>~~ee~~|—<br>~~ee~~|ns<br>~~ee~~|
|tHPLL|Clock to Data Hold – PIO<br>Input Register<br>~~po~~<br>~~po~~<br>~~po~~<br>~~po~~<br>~~po~~|MachXO2-1200ZE<br>~~po~~<br>~~po~~<br>~~po~~|0.66|—<br>~~se~~|0.68<br>~~se ~~|—<br> ~~ee~~|0.80<br>~~ee~~|—|ns|
|||MachXO2-2000ZE<br>~~po~~<br>~~po~~<br>~~po~~|0.68|—|0.70|—|0.83|—|ns|
|||MachXO2-4000ZE<br>~~po~~<br>~~po~~<br>~~po~~|0.68|—|0.71|—|0.84|—|ns|
|||MachXO2-7000ZE<br>~~po~~<br>~~po~~|0.73|—|0.74|—|0.87|—|ns|
© 2010-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02056-4.3
71
**MachXO2 Family Data Sheet Data Sheet**
|**Parameter**<br>~~a~~|**Description**<br>~~a~~|**Device**<br>~~a~~<br>~~ee a~~|**–3**<br>~~a~~<br>~~aee~~|**–3**<br>~~a~~<br>~~aee~~|**–2**<br>~~a~~<br>~~eeee~~|**–2**<br>~~a~~<br>~~eeee~~|**–1**<br>~~a~~<br>~~eee~~|**–1**<br>~~a~~<br>~~eee~~|**Units**<br>~~a~~|
|---|---|---|---|---|---|---|---|---|---|
||||**Min.**<br>~~a~~<br>~~a~~|**Max.**<br>~~a~~<br>~~ee~~|**Min.**<br>~~a~~<br>~~ee~~|**Max.**<br>~~a~~<br>~~ee~~|**Min.**<br>~~a~~<br>~~eee~~|**Max.**<br>~~a~~<br>~~eee~~||
|tSU_DELPLL<br>~~i~~<br>~~Sf~~|Clock to Data Setup – PIO<br>Input Register with Data<br>Input Delay<br>~~i~~<br>~~**p**~~<br>~~Sf~~|MachXO2-1200ZE<br>~~ee a~~<br>~~Re~~|5.14<br>~~a~~<br>~~Re~~|—<br>~~ee~~<br>~~Re~~|5.69<br>~~ee~~<br>~~Re~~|—<br>~~ee~~<br>~~Re~~|6.20<br>~~eee~~<br>~~Re~~|—<br>~~eee~~<br>~~Re~~|ns<br>~~Re~~|
|||MachXO2-2000ZE<br>~~ee a~~<br>~~Re~~<br>~~=-===--—~~<br>~~**p**o~~|5.11<br>~~a ~~<br>~~Re~~<br>~~=-===--—~~<br>~~es es~~|—<br> ~~ee~~<br>~~Re~~<br>~~=-===--—~~<br>~~es~~|5.67<br>~~ee ~~<br>~~Re~~<br>~~=-===--—~~|—<br> ~~ee~~<br>~~Re~~<br>~~=-===--—~~|6.17<br>~~eee~~<br>~~Re~~<br>~~=-===--—~~|—<br>~~eee~~<br>~~Re~~<br>~~=-===--—~~|ns<br>~~Re~~<br>~~=-===--—~~|
|||MachXO2-4000ZE<br>~~Re~~<br>~~es~~<br>~~**p**o~~|5.27<br>~~Re~~<br>~~es~~<br>~~es es~~|—<br>~~Re~~<br>~~es~~<br>~~es~~|5.84<br>~~Re~~<br>~~es~~|—<br>~~Re~~<br>~~es~~|6.35<br>~~Re~~<br>~~es~~|—<br>~~Re~~<br>~~es~~|ns<br>~~Re~~<br>~~es~~|
|||MachXO2-7000ZE<br>~~Re~~<br>~~**p**o~~|5.15<br>~~Re~~<br>~~es es~~|—<br>~~Re~~<br>~~es~~|5.71<br>~~Re~~|—<br>~~Re~~|6.23<br>~~Re~~|—<br>~~Re~~|ns<br>~~Re~~|
|tH_DELPLL<br>~~Sf~~|Clock to Data Hold – PIO<br>Input Register with Input<br>Data Delay<br>~~**p**~~<br>~~Sf~~<br>~~po~~<br>~~po~~|MachXO2-1200ZE<br>~~**p**o~~<br>~~EE~~<br>~~po~~|–1.36<br>~~es es~~<br>~~EE~~|—<br>~~es~~<br>~~EE~~|–1.36<br>~~EE~~|—<br>~~EE~~|–1.36<br>~~EE~~|—<br>~~EE~~|ns<br>~~EE~~|
|||MachXO2-2000ZE<br>~~**p**o~~<br>~~po~~<br>~~po~~|–1.35<br>~~es es~~|—<br>~~es~~|–1.35|—|–1.35|—|ns|
|||MachXO2-4000ZE<br>~~**p**o~~<br>~~po~~<br>~~po~~|–1.43<br>~~es es~~|—<br>~~es~~|–1.43|—|–1.43|—|ns|
|||MachXO2-7000ZE<br>~~**p**o~~<br>~~po~~|–1.41<br>~~es es~~|—<br>~~es~~|–1.41<br>~~o~~|—<br>~~o~~|–1.41<br>~~o~~|—<br>~~o~~|ns<br>~~o~~|
|**Generic DDRX1 Inputs with Clock and Data Aligned at Pin Using PCLK Pin for Clock Input – GDDRX1_RX.SCLK.Aligned9, 11**<br>~~pe~~||||||||||
|tDVA<br>~~ee~~<br>~~ee~~|Input Data Valid After CLK<br>~~ee~~|All MachXO2<br>devices, all sides<br>~~ee~~|—<br>~~ee~~<br>~~ee~~|0.382<br>~~ee~~<br>~~ee~~|—|0.401<br>~~ee~~|—<br>~~ee~~|0.417<br>~~ee~~|UI|
|tDVE<br>~~ee~~<br>~~ee~~<br>~~pO~~<br>~~ee~~|Input Data Hold After CLK<br>~~ee~~<br>~~pO~~||0.670<br>~~ee~~<br>~~ee~~<br>~~a~~|—<br>~~ee~~<br>~~ee~~<br>~~ee~~|0.684<br>~~ee~~|—<br>~~ee~~<br>~~ee~~|0.693<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~<br>~~ee~~|UI<br>~~ee~~|
|fDATA<br>~~ee~~<br>~~ee~~<br>~~pO~~<br>~~ee~~|DDRX1 Input Data Speed<br>~~ee~~<br>~~pO~~<br>~~ee~~||—<br>~~ee~~<br>~~ee~~<br>~~a~~<br>~~a ee~~|140<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~|116<br>~~ee~~<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~<br>~~ee~~|98<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|Mbps<br>~~ee~~<br>~~ee~~<br>~~ee~~|
|fDDRX1<br>~~ee~~<br>~~pO~~<br>~~ee~~|DDRX1 SCLK Frequency<br>~~ee~~<br>~~pO~~<br>~~ee~~||—<br>~~ee~~<br>~~a~~<br>~~a ee~~|70<br>~~ee~~<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~|58<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~|49<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|MHz<br>~~ee~~<br>~~ee~~<br>~~ee~~|
|**Generic DDRX1 Inputs with Clock and Data Centered at Pin Using PCLK Pin for Clock Input – GDDRX1_RX.SCLK.Centered9, 11**<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~a ee~~<br>~~ee~~<br>~~pT~~||||||||||
|tSU<br>~~ee~~<br>~~pO~~|Input Data SetupBefore CLK<br>~~pO~~|All MachXO2<br>devices, all sides<br>~~_~~|1.319<br>~~ee~~|—<br>~~ee~~|1.412<br>~~ee~~|—<br>~~ee~~|1.462<br>~~ee~~|—<br>~~ee~~<br>~~ee~~|ns<br>~~ee~~|
|tHO<br>~~ee~~<br>~~pO~~<br>~~ee~~|Input Data Hold After CLK<br>~~pO~~||0.717<br>~~ee~~|—<br>~~ee~~|1.010<br>~~ee~~|—<br>~~ee~~|1.340<br>~~ee~~|—<br>~~ee~~<br>~~ee~~<br>~~ee~~|ns<br>~~ee~~|
|fDATA<br>~~ee~~<br>~~pO~~<br>~~ee~~|DDRX1 Input Data Speed<br>~~pO~~<br>~~ee~~||—<br>~~ee~~<br>~~a~~<br>~~a ee~~|140<br>~~ee~~<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~<br>~~ee~~|116<br>~~ee~~<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~<br>~~ee~~|98<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|Mbps<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|
|fDDRX1<br>~~ee~~<br>~~pO~~<br>~~ee~~|DDRX1 SCLK Frequency<br>~~pO~~<br>~~ee~~||—<br>~~ee~~<br>~~a ee~~|70<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~|58<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~|49<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|MHz<br>~~ee~~<br>~~ee~~<br>~~ee~~|
|**Generic DDRX2 Inputs with Clock and Data Aligned at Pin Using PCLK Pin for Clock Input – GDDRX2_RX.ECLK.Aligned9, 11**<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~a ee~~<br>~~ee~~<br>~~pT~~<br>~~ee~~<br>~~ee~~<br>~~a~~<br>~~eeeeeeee~~||||||||||
|tDVA<br>~~ee~~<br>~~ee~~<br>~~Se~~<br>~~ee~~|Input Data Valid After CLK<br>~~ee~~<br>~~Se~~|MachXO2-640U,<br>MachXO2-1200/U<br>and larger devices,<br>bottom side only<br>~~ee~~|—<br>~~a~~<br>~~ee~~|0.361<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~<br>~~E~~|0.346<br>~~ee~~<br>~~ee~~<br>~~E~~|—<br>~~ee~~<br>~~ee~~<br>~~E~~|0.334<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~E~~|UI<br>~~ee~~<br>~~ee~~<br>~~E~~|
|tDVE<br>~~ee~~<br>~~ee~~<br>~~Se~~<br>~~ee~~|Input Data Hold After CLK<br>~~ee~~<br>~~Se~~||0.602<br>~~a~~<br>~~ee~~|—<br>~~ee ~~<br>~~ee~~|0.625<br> ~~ee~~<br>~~ee~~<br>~~E~~|—<br>~~ee ~~<br>~~ee~~<br>~~E~~|0.648<br> ~~ee ~~<br>~~ee~~<br>~~E~~|—<br> ~~ee~~<br>~~ee~~<br>~~ee~~<br>~~E~~|UI<br>~~ee~~<br>~~ee~~<br>~~E~~|
|fDATA<br>~~ee~~<br>~~Se~~<br>~~ee~~<br>~~ee~~|DDRX2 Serial Input Data<br>Speed<br>~~Se~~||—<br>~~ee~~<br>~~ee~~|280<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~E~~<br>~~ee~~|234<br>~~ee~~<br>~~E~~<br>~~ee~~|—<br>~~ee~~<br>~~E~~<br>~~ee~~|194<br>~~ee~~<br>~~ee~~<br>~~E~~<br>~~ee~~|Mbps<br>~~ee~~<br>~~E~~<br>~~ee~~|
|fDDRX2<br>~~Se~~<br>~~ee~~<br>~~ee~~|DDRX2 ECLK Frequency<br>~~Se~~<br>~~ee~~||—<br>~~ee~~<br>~~a~~|140<br>~~ee~~<br>~~ee~~|—<br>~~E~~<br>~~ee~~<br>~~ee~~|117<br>~~E~~<br>~~ee~~<br>~~ee~~|—<br>~~E~~<br>~~ee~~<br>~~ee~~|97<br>~~ee~~<br>~~E~~<br>~~ee~~<br>~~ee~~|MHz<br>~~E~~<br>~~ee~~<br>~~ee~~|
|fSCLK<br>~~ee~~<br>~~ee~~|SCLK Frequency<br>~~ee~~||—<br>~~ee~~<br>~~a~~|70<br>~~ee~~<br>~~ee~~|—<br>~~E~~<br>~~ee~~<br>~~ee~~|59<br>~~E~~<br>~~ee~~<br>~~ee~~|—<br>~~E~~<br>~~ee~~<br>~~ee~~|49<br>~~E~~<br>~~ee~~<br>~~ee~~|MHz<br>~~E~~<br>~~ee~~<br>~~ee~~|
|**Generic DDRX2 Inputs with Clock and Data Centered at Pin Using PCLK Pin for Clock Input – GDDRX2_RX.ECLK.Centered9, 11**<br>~~eeee~~<br>~~ee~~<br>~~ee~~<br>~~a~~<br>~~ee ee~~<br>~~pT~~<br>~~ee~~<br>~~ee~~<br>~~aee~~<br>~~ee~~<br>~~po~~||||||||||
|tSU<br>~~ee~~<br>~~po~~<br>~~Se~~<br>~~ee~~|Input Data SetupBefore CLK<br>~~ee~~<br>~~po~~<br>~~Se~~|MachXO2-640U,<br>MachXO2-1200/U<br>and larger devices,<br>bottom side only|0.472<br>~~a~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~|0.672<br>~~ee~~<br>~~ee~~<br>~~E~~|—<br>~~ee~~<br>~~ee~~<br>~~E~~|0.865<br>~~ee~~<br>~~eee~~<br>~~E~~|—<br>~~ee~~<br>~~ee~~<br>~~eee~~<br>~~E~~|ns<br>~~ee~~<br>~~ee~~<br>~~eee~~<br>~~E~~|
|tHO<br>~~ee~~<br>~~po~~<br>~~Se~~<br>~~ee~~|Input Data Hold After CLK<br>~~ee~~<br>~~po~~<br>~~Se~~||0.363<br>~~a~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~|0.501<br>~~ee~~<br>~~ee~~<br>~~E~~|—<br>~~ee~~<br>~~ee~~<br>~~E~~|0.743<br>~~ee~~<br>~~eee~~<br>~~E~~|—<br>~~ee~~<br>~~ee~~<br>~~eee~~<br>~~E~~|ns<br>~~ee~~<br>~~ee~~<br>~~eee~~<br>~~E~~|
|fDATA<br>~~po~~<br>~~Se~~<br>~~ee~~<br>~~ee~~|DDRX2 Serial Input Data<br>Speed<br>~~po~~<br>~~Se~~||—<br>~~ee~~<br>~~ee~~|280<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~E~~<br>~~ee~~|234<br>~~ee~~<br>~~E~~<br>~~ee~~|—<br>~~eee~~<br>~~E~~<br>~~ee~~|194<br>~~ee~~<br>~~eee~~<br>~~E~~<br>~~ee~~|Mbps<br>~~ee~~<br>~~eee~~<br>~~E~~<br>~~ee~~|
|fDDRX2<br>~~Se~~<br>~~ee~~<br>~~ee~~|DDRX2 ECLK Frequency<br>~~Se~~<br>~~ee~~||—<br>~~ee ~~<br>~~ee~~<br>~~a~~|140<br> ~~ee ~~<br>~~ee~~<br>~~ee~~|—<br> ~~ee~~<br>~~E~~<br>~~ee~~<br>~~ee~~|117<br>~~ee~~<br>~~E~~<br>~~ee~~<br>~~ee~~|—<br>~~eee~~<br>~~E~~<br>~~ee~~<br>~~ee~~|97<br>~~eee~~<br>~~E~~<br>~~ee~~<br>~~ee~~|MHz<br>~~eee~~<br>~~E~~<br>~~ee~~<br>~~ee~~|
|fSCLK<br>~~ee~~<br>~~ee~~|SCLK Frequency<br>~~ee~~||—<br>~~ee~~<br>~~a~~|70<br>~~ee~~<br>~~ee~~|—<br>~~E~~<br>~~ee~~<br>~~ee~~|59<br>~~E~~<br>~~ee~~<br>~~ee~~|—<br>~~E~~<br>~~ee~~<br>~~ee~~|49<br>~~E~~<br>~~ee~~<br>~~ee~~|MHz<br>~~E~~<br>~~ee~~<br>~~ee~~|
|**Generic DDR4 Inputs with Clock and Data Aligned at Pin Using PCLK Pin for Clock Input - GDDRX4_RX.ECLK.Aligned9, 11**<br>~~eeee~~<br>~~ee~~<br>~~ee~~<br>~~a~~<br>~~ee ee~~<br>~~pT~~<br>~~ee~~<br>~~ee~~<br>~~aee~~<br>~~ee~~<br>~~es~~||||||||||
|tDVA<br>~~ee~~<br>~~es~~<br>~~Se~~|Input Data Valid After ECLK<br>~~ee~~<br>~~ee~~<br>~~Se~~|MachXO2-640U,<br>MachXO2-1200/U<br>and larger devices,<br>bottom side only<br>~~ee~~|—<br>~~a~~<br>~~ee~~|0.307<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~<br>~~E~~|0.316<br>~~ee~~<br>~~ee~~<br>~~E~~|—<br>~~ee~~<br>~~ee~~<br>~~E~~|0.326<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~E~~|UI<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~E~~|
|tDVE<br>~~ee~~<br>~~es~~<br>~~Se~~|Input Data Hold After ECLK<br>~~ee~~<br>~~ee~~<br>~~Se~~||0.662<br>~~a~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~|0.650<br>~~ee~~<br>~~ee~~<br>~~E~~|—<br>~~ee~~<br>~~ee~~<br>~~E~~|0.649<br>~~ee~~<br>~~ee~~<br>~~E~~|—<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~E~~|UI<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~E~~|
|fDATA<br>~~es~~<br>~~Se~~<br>~~ee~~<br>~~ee~~|DDRX4 Serial Input Data<br>Speed<br>~~ee~~<br>~~Se~~||—<br>~~ee~~<br>~~a~~|420<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~E~~<br>~~ee~~|352<br>~~ee ~~<br>~~E~~<br>~~ee~~|—<br> ~~ee~~<br>~~E~~<br>~~ee~~|292<br>~~ee~~<br>~~ee~~<br>~~E~~<br>~~ee~~<br>~~ee~~|Mbps<br>~~ee~~<br>~~ee~~<br>~~E~~<br>~~ee~~|
|fDDRX4<br>~~Se~~<br>~~ee~~<br>~~ee~~|DDRX4 ECLK Frequency<br>~~Se~~<br>~~ee~~||—<br>~~a~~<br>~~a ee~~|210<br>~~ee~~<br>~~ee~~|—<br>~~E~~<br>~~ee~~<br>~~ee~~|176<br>~~E~~<br>~~ee~~<br>~~ee~~|—<br>~~E~~<br>~~ee~~<br>~~ee~~|146<br>~~E~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|MHz<br>~~E~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|
|fSCLK<br>~~Se~~<br>~~ee~~<br>~~ee~~|SCLK Frequency<br>~~Se~~<br>~~ee~~||—<br>~~a~~<br>~~a ee~~|53<br>~~ee~~<br>~~ee~~|—<br>~~E~~<br>~~ee~~<br>~~ee~~|44<br>~~E~~<br>~~ee~~<br>~~ee~~|—<br>~~E~~<br>~~ee~~<br>~~ee~~|37<br>~~E~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|MHz<br>~~E~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|
|**Generic DDR4 Inputs with Clock and Data Centered at Pin Using PCLK Pin for Clock Input – GDDRX4_RX.ECLK.Centered9, 11**<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~a ee~~<br>~~ee~~<br>~~Pe~~<br>~~ee~~<br>~~ee~~<br>~~a ee~~||||||||||
|tSU<br>~~ee~~<br>~~po~~<br>~~Se~~|Input Data SetupBefore ECLK<br>~~ee~~<br>~~po~~<br>~~Se~~|MachXO2-640U,<br>MachXO2-1200/U<br>and larger devices,<br>bottom side only|0.434<br>~~a ee~~<br>~~a~~|—<br>~~ee~~<br>~~ee~~|0.535<br>~~ee~~<br>~~ee~~<br>~~E~~|—<br>~~ee~~<br>~~ee~~<br>~~E~~|0.630<br>~~ee~~<br>~~ee~~<br>~~E~~|—<br>~~ee~~<br>~~ee~~<br>~~E~~|ns<br>~~ee~~<br>~~ee~~<br>~~E~~|
|tHO<br>~~ee~~<br>~~po~~<br>~~Se~~|Input Data Hold After ECLK<br>~~ee~~<br>~~po~~<br>~~Se~~||0.385<br>~~a ee~~<br>~~a~~|—<br>~~ee~~<br>~~ee~~|0.395<br>~~ee~~<br>~~ee~~<br>~~E~~|—<br>~~ee~~<br>~~ee~~<br>~~E~~|0.463<br>~~ee~~<br>~~ee~~<br>~~E~~|—<br>~~ee~~<br>~~ee~~<br>~~E~~|ns<br>~~ee~~<br>~~ee~~<br>~~E~~|
|fDATA<br>~~po~~<br>~~Se~~<br>~~ee~~<br>~~ee~~|DDRX4 Serial Input Data<br>Speed<br>~~po~~<br>~~Se~~||—<br>~~a~~<br>~~a~~|420<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~E~~<br>~~ee~~|352<br>~~ee ~~<br>~~E~~<br>~~ee~~|—<br> ~~ee~~<br>~~E~~<br>~~ee~~|292<br>~~ee~~<br>~~E~~<br>~~ee~~<br>~~ee~~|Mbps<br>~~ee~~<br>~~E~~<br>~~ee~~|
|fDDRX4<br>~~Se~~<br>~~ee~~<br>~~ee~~|DDRX4 ECLK Frequency<br>~~Se~~<br>~~ee~~||—<br>~~a~~<br>~~po~~|210<br>~~ee~~<br>~~po~~|—<br>~~E~~<br>~~ee~~<br>~~po~~|176<br>~~E~~<br>~~ee~~<br>~~po~~|—<br>~~E~~<br>~~ee~~<br>~~po~~|146<br>~~E~~<br>~~ee~~<br>~~ee~~<br>~~po~~|MHz<br>~~E~~<br>~~ee~~<br>~~po~~|
|fSCLK<br>~~Se~~<br>~~ee~~<br>~~ee~~|SCLK Frequency<br>~~Se~~<br>~~ee~~||—<br>~~a~~<br>~~po~~|53<br>~~ee~~<br>~~po~~|—<br>~~E~~<br>~~ee~~<br>~~po~~|44<br>~~E~~<br>~~ee~~<br>~~po~~|—<br>~~E~~<br>~~ee~~<br>~~po~~|37<br>~~E~~<br>~~ee~~<br>~~ee~~<br>~~po~~|MHz<br>~~E~~<br>~~ee~~<br>~~po~~|
72
FPGA-DS-02056-4.3
**MachXO2 Family Data Sheet Data Sheet**
|**Parameter**<br>~~a~~|**Description**<br>~~a~~|**Device**<br>~~e~~|**–3**<br>~~e~~~~**e**~~<br>~~a~~<br>~~e ee~~|**–3**<br>~~e~~~~**e**~~<br>~~a~~<br>~~e ee~~|**–2**<br>~~**e**~~<br>~~ee~~|**–2**<br>~~**e**~~<br>~~ee~~|**–1**<br>~~**e**e~~<br>~~ee~~<br>~~eeee~~|**–1**<br>~~**e**e~~<br>~~ee~~<br>~~eeee~~|**Units**<br>~~e~~|
|---|---|---|---|---|---|---|---|---|---|
||||**Min.**<br>~~e~~<br>~~a~~|**Max.**<br>~~e~~~~**e**~~<br>~~e ee~~|**Min.**<br>~~**e**~~<br>~~ee~~|**Max.**<br>~~**e**~~<br>~~ee~~|**Min.**<br>~~**e**e~~<br>~~ee~~<br>~~ee~~|**Max.**<br>~~e~~<br>~~ee~~<br>~~ee~~||
|**7:1 LVDS Inputs – GDDR71_RX.ECLK.7.19, 11**<br>~~a~~<br>~~e ee~~<br>~~ee ee~~<br>~~eee~~<br>~~ee~~<br>~~ee~~<br>~~aa~~<br>~~ee~~<br>~~ee~~<br>~~ee~~||||||||||
|tDVA<br>~~ee~~<br>~~ee~~<br>~~err~~|Input Data Valid After ECLK<br>~~ee~~<br>~~ee~~<br>~~err~~|MachXO2-640U,<br>MachXO2-1200/U<br>and larger devices,<br>bottom side only<br>~~ee~~<br>~~ee~~<br>~~err~~e~~eeee~~<br>~~PET~~|—<br>~~a~~<br>~~a~~<br>~~eeee~~|0.307<br>~~a~~<br>~~eeee~~|—<br>~~ee~~<br>~~eeee~~|0.316<br>~~ee~~<br>~~eeee~~|—<br>~~ee~~<br>~~eeee~~|0.326<br>~~ee~~<br>~~eeee~~|UI<br>~~eeee~~|
|tDVE<br>~~ee~~<br>~~ee~~<br>~~err~~|Input Data Hold After ECLK<br>~~ee~~<br>~~ee~~<br>~~err~~||0.662<br>~~a ~~<br>~~a~~<br>~~eeee~~|—<br> ~~a~~<br>~~eeee~~|0.650<br>~~ee~~<br>~~eeee~~|—<br>~~ee~~<br>~~eeee~~|0.649<br>~~ee~~<br>~~eeee~~|—<br>~~ee~~<br>~~eeee~~|UI<br>~~eeee~~|
|fDATA<br>~~ee~~<br>~~err~~|DDR71 Serial Input Data<br>Speed<br>~~ee~~<br>~~err~~||—<br>~~a~~<br>~~eeee~~|420<br>~~eeee~~|—<br>~~eeee~~|352<br>~~eeee~~|—<br>~~eeee~~|292<br>~~eeee~~|Mbps<br>~~eeee~~|
|fDDR71<br>~~err~~<br>~~PET~~|DDR71 ECLK Frequency<br>~~err~~<br>~~PET~~||—<br>~~eeee~~<br>~~PET~~|210<br>~~eeee~~<br>~~PET~~|—<br>~~eeee~~<br>~~PET~~|176<br>~~eeee~~<br>~~PET~~|—<br>~~eeee~~<br>~~PET~~|146<br>~~eeee~~<br>~~PET~~|MHz<br>~~eeee~~<br>~~PET~~|
|fCLKIN<br>~~err~~<br>~~PET~~|7:1 Input Clock Frequency<br>(SCLK) (minimum limited by<br>PLL)<br>~~err~~<br>~~PET~~||—<br>~~eeee~~<br>~~PET~~|60<br>~~eeee~~<br>~~PET~~|—<br>~~eeee~~<br>~~PET~~|50<br>~~eeee~~<br>~~PET~~|—<br>~~eeee~~<br>~~PET~~|42<br>~~eeee~~<br>~~PET~~|MHz<br>~~eeee~~<br>~~PET~~|
|**Generic DDR Outputs with Clock and Data Aligned at Pin Using PCLK Pin for Clock Input – GDDRX1_TX.SCLK.Aligned9, 11**<br>~~Pe~~<br>~~—~~<br>~~fttffFff~~||||||||||
|tDIA<br>~~Pe~~<br>~~—~~<br>~~ee~~|Output Data Invalid After CLK<br>Output<br>~~Pe~~|All MachXO2<br>devices, all sides<br>~~Pe~~<br>~~**ee**~~<br>|—<br>~~Pe~~<br>~~ft~~|0.850<br>~~Pe~~<br>~~fttf~~|—<br>~~Pe~~<br>~~tffF~~<br>~~fF~~|0.910<br>~~Pe~~<br>~~fFff~~<br>~~fFff~~|—<br>~~Pe~~<br>~~ff~~<br>~~ff~~|0.970<br>~~Pe~~<br>~~ff~~<br>~~ff~~|ns<br>~~Pe~~|
|tDIB<br>~~—~~<br>~~i~~<br>~~ee~~<br>~~ee~~|Output Data Invalid Before<br>CLK Output<br>~~i~~<br>~~**ee**~~<br>||—<br>~~ft~~<br>~~ff~~<br>~~**a**~~<br>|0.850<br>~~ft tf~~<br>~~ff~~<br>~~ee~~<br>|—<br>~~tf fF~~<br>~~ff~~<br>~~fF~~<br>|0.910<br>~~fF ff~~<br>~~ff~~<br>~~fFff~~<br>|—<br>~~ff~~<br>~~ff~~<br>~~ff~~<br>|0.970<br>~~ff~~<br>~~ff~~<br>~~ff~~<br>|ns<br>~~ff~~<br>|
|fDATA<br>~~i~~<br>~~ee~~<br>~~ee~~|DDRX1 Output Data Speed<br>~~i~~<br>~~**ee**~~<br>||—<br>~~ff~~<br>~~**a**~~<br>|140<br>~~ff~~<br>~~ee~~<br>|—<br>~~ff~~<br>~~fF~~<br>|116<br>~~ff~~<br>~~fFff~~<br>|—<br>~~ff~~<br>~~ff~~<br>|98<br>~~ff~~<br>~~ff~~<br>|Mbps<br>~~ff~~<br>|
|fDDRX1<br>~~ee~~<br>~~ee~~|DDRX1 SCLK frequency<br>~~**ee**~~<br>||—<br>~~**a**~~<br>|70<br>~~ee~~<br>|—<br>~~fF~~<br>|58<br>~~fF ff~~<br>|—<br>~~ff~~<br>|49<br>~~ff~~<br>|MHz<br>|
|**Generic DDR Outputs with Clock and Data Centered at Pin Using PCLK Pin for Clock Input – GDDRX1_TX.SCLK.Centered9, 11**<br>~~**ee**~~<br>~~**a**~~<br>~~ee~~<br>~~eeRee~~<br>~~op~~<br>~~ftftfF~~||||||||||
|tDVB<br>~~op~~<br>~~—~~|Output Data Valid Before CLK<br>Output<br>~~op~~|All MachXO2<br>devices, all sides<br>~~ee~~|2.720<br>~~ft~~<br>~~ft~~|—<br>~~ftft~~<br>~~fttf~~|3.380<br>~~ftfF~~<br>~~tffF~~|—<br>~~fFfff~~<br>~~fF~~|4.140<br>~~fff~~<br>|—<br>~~fff~~<br>|ns<br>~~fff~~<br>|
|tDVA<br>~~op~~<br>~~—~~<br>~~ee~~<br>~~ot~~|Output Data Valid After CLK<br>Output<br>~~op~~<br>~~ee~~<br>~~ot~~||2.720<br>~~ft~~<br>~~ft~~<br>~~a~~|—<br>~~ft ft~~<br>~~fttf~~|3.380<br>~~ft fF~~<br>~~tffF~~|—<br>~~fFfff~~<br>~~fFfff~~|4.140<br>~~fff~~<br>~~fff~~|—<br>~~fff~~<br>~~fff~~|ns<br>~~fff~~<br>~~fff~~|
|fDATA<br>~~—~~<br>~~ee~~<br>~~ot~~|DDRX1 Output Data Speed<br>~~ee~~<br>~~ot~~||—<br><br>~~ft~~<br>~~a~~<br>~~ft~~|140<br><br>~~ft tf~~<br>~~ftft~~|—<br><br>~~tf fF~~<br>~~ftf~~|116<br>~~fff~~<br>~~fFfff~~<br>~~f~~~~**t**~~|—<br>~~fff~~<br>~~fff~~<br>|98<br>~~fff~~<br>~~fff~~<br>|Mbps<br>~~fff~~<br>~~fff~~<br>|
|fDDRX1<br>~~ee~~<br>~~ot~~|DDRX1 SCLK Frequency<br>(minimum limited byPLL)<br>~~ee~~<br>~~ot~~||—<br><br>~~a~~<br>~~ft~~|70<br><br>~~ftft~~|—<br><br>~~ftf~~|58<br>~~fff~~<br>~~f~~~~**t** ~~|—<br>~~fff~~<br> ~~tf~~|49<br>~~fff~~<br>~~tf~~|MHz<br>~~fff~~<br>~~tf~~|
|**Generic DDRX2 Outputs with Clock and Data Aligned at Pin Using PCLK Pin for Clock Input – GDDRX2_TX.ECLK.Aligned9, 11**<br>~~ee~~<br>~~a~~<br>~~ot~~<br>~~ft ft f~~~~**t** ~~<br>~~Pee~~<br>~~op~~<br>~~otftfF~~||||||||||
|tDIA<br>~~op~~<br>~~op~~|Output Data Invalid After CLK<br>Output<br>~~op~~<br>~~op~~|MachXO2-640U,<br>MachXO2-1200/U<br>and larger devices,<br>top side only<br>~~**ee**~~|—<br>~~ot~~<br>~~tf~~|0.270<br>~~otft~~<br>~~tf~~<br>~~tf~~|—<br>~~ftfF~~<br>~~tffF~~|0.300<br>~~fFfff~~<br>~~fF~~|—<br>~~fff~~<br>|0.330<br>~~fff~~<br>|ns<br>~~fff~~<br>|
|tDIB<br>~~op~~<br>~~op~~<br>~~op~~|Output Data Invalid Before<br>CLK Output<br>~~op~~<br>~~op~~<br>~~op~~||—<br>~~ot~~<br>~~tf~~<br>~~tf~~|0.270<br>~~ot ft~~<br>~~tf~~<br>~~tf~~<br>~~tf~~<br>~~tf~~|—<br>~~ft fF~~<br>~~tffF~~<br>~~tffF~~|0.300<br>~~fF~~<br>~~fFfff~~<br>~~fF~~|—<br><br>~~fff~~<br>|0.330<br><br>~~fff~~<br>|ns<br><br>~~fff~~<br>|
|fDATA<br>~~op~~<br>~~op~~<br>~~ee~~<br>~~ee~~|DDRX2 Serial Output Data<br>Speed<br>~~op~~<br>~~op~~<br>~~**ee**~~||—<br>~~tf~~<br>~~tf~~<br>~~**a**~~|280<br>~~tf~~<br>~~tf~~<br>~~tf~~<br>~~tf~~<br>~~ee~~|—<br>~~tf fF~~<br>~~tffF~~<br>~~ee~~|234<br>~~fF~~<br>~~fFfff~~<br>~~ee~~|—<br><br>~~fff~~<br>~~**e**e~~|194<br><br>~~fff~~|Mbps<br><br>~~fff~~|
|fDDRX2<br>~~op~~<br>~~ee~~<br>~~ee~~|DDRX2 ECLK frequency<br>~~op~~<br>~~**ee**~~||—<br>~~tf~~<br>~~**a**~~|140<br>~~tf~~<br>~~tf~~<br>~~ee~~<br>~~e~~|—<br>~~tf fF~~<br>~~ee~~<br>~~e~~|117<br>~~fFfff~~<br>~~ee~~<br>~~e~~|—<br>~~fff~~<br>~~**e**e~~<br>~~e~~|97<br>~~fff~~<br>~~es~~|MHz<br>~~fff~~|
|fSCLK<br>~~ee~~<br>~~ee~~|SCLK Frequency<br>~~**ee**~~||—<br>~~**a**~~|70<br><br>~~ee~~<br>~~e~~|—<br><br>~~ee~~<br>~~e~~|59<br>~~fff~~<br>~~ee~~<br>~~e~~|—<br>~~fff~~<br>~~**e**e~~<br>~~e~~|49<br>~~fff~~<br>~~es~~|MHz<br>~~fff~~|
|**Generic DDRX2 Outputs with Clock and Data Centered at Pin Using PCLK Pin for Clock Input – GDDRX2_TX.ECLK.Centered9, 11**<br>~~**ee**~~<br>~~**a**~~<br>~~ee ee ee ~~~~**e**e~~<br>~~ee~~<br>~~e~~<br>~~es~~<br>~~Ree~~<br>~~op~~<br>~~otftfF~~||||||||||
|tDVB<br>~~op~~<br>~~op~~|Output Data Valid Before CLK<br>Output<br>~~op~~<br>~~op~~|MachXO2-640U,<br>MachXO2-1200/U<br>and larger devices,<br>top side only<br>~~ee~~|1.445<br>~~ot~~<br>~~ft~~|—<br>~~otft~~<br>~~fttf~~|1.760<br>~~ftfF~~<br>~~tffF~~|—<br>~~fF~~~~**fff**~~<br>~~fF~~|2.140<br>~~**fff**~~|—<br>~~**fff**~~|ns<br>~~**fff**~~|
|tDVA<br>~~op~~<br>~~op~~<br>~~op~~|Output Data Valid After CLK<br>Output<br>~~op~~<br>~~op~~<br>~~op~~||1.445<br>~~ot~~<br>~~ft~~<br>~~ft~~|—<br>~~ot ft~~<br>~~fttf~~<br>~~fttf~~|1.760<br>~~ft fF~~<br>~~tffF~~<br>~~tffF~~|—<br>~~fF~~~~**fff**~~<br>~~fF~~<br>~~fF~~|2.140<br>~~**fff**~~<br>|—<br>~~**fff**~~<br>|ns<br>~~**fff**~~<br>|
|fDATA<br>~~op~~<br>~~op~~<br>~~op~~|DDRX2 Serial Output Data<br>Speed<br>~~op~~<br>~~op~~<br>~~op~~||—<br><br>~~ft~~<br>~~ft~~<br>~~ft~~|280<br><br>~~ft tf~~<br>~~fttf~~<br>~~fttf~~|—<br><br>~~tf fF~~<br>~~tffF~~<br>~~tffF~~|234<br>~~**fff**~~<br>~~fF~~<br>~~fFfff~~<br>~~fF~~|—<br>~~**fff**~~<br>~~fff~~<br>|194<br>~~**fff**~~<br>~~fff~~<br>|Mbps<br>~~**fff**~~<br>~~fff~~<br>|
|fDDRX2<br>~~op~~<br>~~op~~<br>~~a~~|DDRX2 ECLK Frequency<br>(minimum limited byPLL)<br>~~op~~<br>~~op~~<br>~~ee~~||—<br>~~ft~~<br>~~ft~~<br>~~a ee~~|140<br>~~ft tf~~<br>~~fttf~~<br>~~ee~~|—<br>~~tf fF~~<br>~~tffF~~<br>~~ee~~|117<br>~~fFfff~~<br>~~fFfff~~<br>~~ee~~|—<br>~~fff~~<br>~~fff~~<br>~~ee~~<br>~~ee~~|97<br>~~fff~~<br>~~fff~~<br>~~ee~~<br>~~ee~~|MHz<br>~~fff~~<br>~~fff~~<br>~~ee~~<br>~~ee~~|
|fSCLK<br>~~op~~<br>~~a~~|SCLK Frequency<br>~~op~~<br>~~ee~~||—<br>~~ft~~<br>~~a ee~~|70<br>~~ft tf~~<br>~~ee~~|—<br>~~tf fF~~<br>~~ee~~|59<br>~~fFfff~~<br>~~ee~~|—<br>~~fff~~<br>~~ee~~<br>~~ee~~|49<br>~~fff~~<br>~~ee~~<br>~~ee~~|MHz<br>~~fff~~<br>~~ee~~<br>~~ee~~|
© 2010-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02056-4.3
73
**MachXO2 Family Data Sheet Data Sheet**
|**Parameter**<br>~~a~~|**Description**<br>~~a~~|**Device**<br>~~e~~|**–3**<br>~~e~~~~**e**~~<br>~~a~~<br>~~e~~|**–3**<br>~~e~~~~**e**~~<br>~~a~~<br>~~e~~|**–2**<br>~~**e**~~<br>~~ee~~<br>~~ee~~|**–2**<br>~~**e**~~<br>~~ee~~<br>~~ee~~|**–1**<br>~~**e**e~~<br>~~ee~~<br>~~ee~~|**–1**<br>~~**e**e~~<br>~~ee~~<br>~~ee~~|**Units**<br>~~e~~|
|---|---|---|---|---|---|---|---|---|---|
||||**Min.**<br>~~e~~<br>~~a~~|**Max.**<br>~~e~~~~**e**~~<br>~~e~~|**Min.**<br>~~**e**~~<br>~~ee~~|**Max.**<br>~~**e**~~<br>~~ee~~|**Min.**<br>~~**e**e~~<br>~~ee~~|**Max.**<br>~~e~~<br>~~ee~~||
|**Generic DDRX4 Outputs with Clock and Data Aligned at Pin Using PCLK Pin for Clock Input – GDDRX4_TX.ECLK.Aligned9, 11**<br>~~a~~<br>~~e~~<br>~~ee~~<br>~~ee ee~~<br>~~ee~~<br>~~Bee~~<br>~~op~~<br>~~fttffF~~||||||||||
|tDIA<br>~~op~~<br>~~PF~~<br>~~Po~~|Output Data Invalid After CLK<br>Output<br>~~op~~<br>~~Po~~|MachXO2-640U,<br>MachXO2-1200/U<br>and larger devices,<br>top side only<br>~~ee~~<br>~~ee~~|—<br>~~ft~~|0.270<br>~~fttf~~|—<br>~~tffF~~<br>~~ft~~|0.300<br>~~fFfff~~<br>~~ftttt~~|—<br>~~fff~~<br>~~ttt~~|0.330<br>~~fff~~<br>~~ttt~~|ns<br>~~fff~~<br>~~ttt~~|
|tDIB<br>~~op~~<br>~~PF~~<br>~~Po~~<br>~~ee~~|Output Data Invalid Before<br>CLK Output<br>~~op~~<br>~~Po~~||—<br>~~ft~~<br>~~ff~~|0.270<br>~~ft tf~~<br>~~ff~~|—<br>~~tf fF~~<br>~~ff~~<br>~~ft~~<br>~~ft~~|0.300<br>~~fFfff~~<br>~~ff~~<br>~~ftttt~~<br>~~ft tt~~|—<br>~~fff~~<br>~~ff~~<br>~~ttt~~<br>~~tt~~|0.330<br>~~fff~~<br>~~ff~~<br>~~ttt~~<br>~~tt~~|ns<br>~~fff~~<br>~~ff~~<br>~~ttt~~<br>~~tt~~|
|fDATA<br>~~PF~~<br>~~Po~~<br>~~ee~~<br>~~ee~~|DDRX4 Serial Output Data<br>Speed<br>~~Po~~<br>~~ee~~<br>||—<br><br>~~ft}~~<br>~~**a**~~|420<br><br>~~ft}~~<br>~~ee~~|—<br><br>~~ft~~<br>~~ft}~~<br>~~ft~~<br>~~es~~|352<br>~~fff~~<br>~~ftttt~~<br>~~ft}~~<br>~~ft tt~~<br>~~es~~|—<br>~~fff~~<br>~~ttt~~<br>~~ft}~~<br>~~tt~~<br>~~es~~|292<br>~~fff~~<br>~~ttt~~<br>~~ft}~~<br>~~tt~~<br>~~ee~~|Mbps<br>~~fff~~<br>~~ttt~~<br>~~ft}~~<br>~~tt~~|
|fDDRX4<br>~~Po~~<br>~~ee~~<br>~~ee ee~~|DDRX4 ECLK Frequency<br>~~Po~~<br>~~ee~~<br>~~ee~~||—<br>~~**a**~~|210<br>~~ee~~|—<br>~~ft~~<br>~~ft~~<br>~~es~~|176<br>~~ft ttt~~<br>~~ft tt~~<br>~~es~~|—<br>~~ttt~~<br>~~tt~~<br>~~es~~|146<br>~~ttt~~<br>~~tt~~<br>~~ee~~|MHz<br>~~ttt~~<br>~~tt~~|
|fSCLK<br>~~ee~~<br>~~ee ee~~|SCLK Frequency<br>~~ee~~<br>~~ee~~||—<br>~~**a**~~|53<br>~~ee~~|—<br>~~ft~~<br>~~es~~|44<br>~~ft tt~~<br>~~es~~|—<br>~~tt~~<br>~~es~~|37<br>~~tt~~<br>~~ee~~|MHz<br>~~tt~~|
|**Generic DDRX4 Outputs with Clock and Data Centered at Pin Using PCLK Pin for Clock Input – GDDRX4_TX.ECLK.Centered9, 11**<br>~~ee~~<br>~~**a**~~<br>~~ee~~<br>~~es es ee~~<br>~~ee ee~~<br>~~en~~<br>~~op~~<br>~~ef~~<br>~~tffFft~~||||||||||
|tDVB<br>~~op~~<br>~~FP~~|Output Data Valid Before CLK<br>Output<br>~~op~~|MachXO2-640U,<br>MachXO2-1200/U<br>and larger devices,<br>top side only<br>~~ee~~|0.873<br>~~ef~~<br>~~ff~~|—<br>~~ef~~<br>~~tf~~<br>~~ff~~|1.067<br>~~tffF~~<br>~~ffft~~|—<br>~~fFft~~<br>~~ft~~|1.319<br>~~ft~~<br>~~ft~~|—<br>~~ft~~<br>~~ft~~|ns|
|tDVA<br>~~op~~<br>~~FP~~<br>~~—~~|Output Data Valid After CLK<br>Output<br>~~op~~||0.873<br>~~ef~~<br>~~ff~~<br>~~ft~~|—<br>~~ef~~<br>~~tf~~<br>~~ff~~<br>~~ftft~~|1.067<br>~~tf fF~~<br>~~ffft~~<br>~~ftfF~~|—<br>~~fF ft~~<br>~~ft~~<br>~~fF~~|1.319<br>~~ft~~<br>~~ft~~<br>|—<br>~~ft~~<br>~~ft~~<br>|ns<br>|
|fDATA<br>~~FP~~<br>~~—~~<br>~~—~~|DDRX4 Serial Output Data<br>Speed||—<br>~~ff~~<br>~~ft~~<br>~~ft~~|420<br>~~ff~~<br>~~ftft~~<br>~~ftft~~|—<br>~~ff ft~~<br>~~ftfF~~<br>~~ftfF~~|352<br>~~ft~~<br>~~fFfff~~<br>~~fF~~|—<br>~~ft~~<br>~~fff~~<br>|292<br>~~ft~~<br>~~fff~~<br>|Mbps<br>~~fff~~<br>|
|fDDRX4<br>~~—~~<br>~~—~~<br>~~ee~~|DDRX4 ECLK Frequency<br>(minimum limited byPLL)<br>~~ee~~||—<br>~~ft~~<br>~~ft~~<br>~~a~~|210<br>~~ft ft~~<br>~~ftft~~<br>~~ee~~|—<br>~~ft fF~~<br>~~ftfF~~<br>~~es~~|176<br>~~fFfff~~<br>~~fFfff~~<br>~~ee~~|—<br>~~fff~~<br>~~fff~~|146<br>~~fff~~<br>~~fff~~|MHz<br>~~fff~~<br>~~fff~~|
|fSCLK<br>~~—~~<br>~~ee~~|SCLK Frequency<br>~~ee~~||—<br><br>~~ft~~<br>~~a~~|53<br><br>~~ft ft~~<br>~~ee~~|—<br><br>~~ft fF~~<br>~~es~~|44<br>~~fff~~<br>~~fFfff~~<br>~~ee~~|—<br>~~fff~~<br>~~fff~~|37<br>~~fff~~<br>~~fff~~|MHz<br>~~fff~~<br>~~fff~~|
|**7:1 LVDS Outputs – GDDR71_TX.ECLK.7:19, 11**<br>~~fff~~<br>~~ee~~<br>~~ee~~<br>~~a~~<br>~~ee es ee~~<br>~~eee~~<br>~~op~~<br>~~offfff~~||||||||||
|tDIB<br>~~eee~~<br>~~op~~<br>~~i~~|Output Data Invalid Before<br>CLK Output<br>~~eee~~<br>~~op~~<br>~~i~~|MachXO2-640U,<br>MachXO2-1200/U<br>and larger devices,<br>top side only<br>~~eee~~<br>~~ee~~|—<br>~~eee~~<br>~~of~~<br>~~fF~~|0.240<br>~~eee~~<br>~~offf~~<br>~~fFfF~~|—<br>~~eee~~<br>~~ff~~<br>~~fF~~<br>~~fF~~|0.270<br>~~eee~~<br>~~ffff~~<br>~~fFff~~|—<br>~~eee~~<br>~~ff~~<br>~~ff~~|0.300<br>~~eee~~<br>~~ff~~<br>~~ff~~|ns<br>~~eee~~|
|tDIA<br>~~op~~<br>~~i~~<br>~~i~~|Output Data Invalid After CLK<br>Output<br>~~op~~<br>~~i~~<br>~~i~~||—<br>~~of~~<br>~~fF~~<br>~~of~~|0.240<br>~~of ff~~<br>~~fFfF~~<br>~~of~~<br>~~tf~~|—<br>~~ff~~<br>~~fF~~<br>~~fF~~<br>~~tf~~<br>~~fF~~|0.270<br>~~ff ff~~<br>~~fFff~~<br>~~fFtt~~|—<br>~~ff~~<br>~~ff~~<br>~~tt~~|0.300<br>~~ff~~<br>~~ff~~<br>~~tt~~|ns|
|fDATA<br>~~i~~<br>~~i~~<br>~~ee~~|DDR71 Serial Output Data<br>Speed<br>~~i~~<br>~~i~~<br>~~ee~~||—<br>~~fF~~<br>~~of~~|420<br>~~fF fF~~<br>~~of~~<br>~~tf~~|—<br>~~fF~~<br>~~fF~~<br>~~tf~~<br>~~fF~~|352<br>~~fF ff~~<br>~~fFtt~~|—<br>~~ff~~<br>~~tt~~|292<br>~~ff~~<br>~~tt~~|Mbps|
|fDDR71<br>~~i~~<br>~~ee~~|DDR71 ECLK Frequency<br>~~i~~<br>~~ee~~||—<br>~~of~~|210<br>~~of~~<br>~~tf~~|—<br>~~tf~~<br>~~fF~~|176<br>~~fF tt~~|—<br>~~tt~~|146<br>~~tt~~|MHz|
|fCLKOUT<br>~~ee~~|7:1 Output Clock Frequency<br>(SCLK) (minimum limited by<br>PLL)<br>~~ee~~||—|60|—|50|—|42|MHz|
|**LPDDR9, 11**<br>~~ee ee~~<br>~~eee~~<br>~~fFft~~<br>~~op~~||||||||||
|tDVADQ<br>~~eee~~<br>~~op~~<br>~~op~~<br>~~op~~|Input Data Valid After DQS<br>Input<br>~~eee~~<br>~~op~~<br>~~op~~<br>~~op~~|MachXO2-1200/U<br>and larger devices,<br>right side only12<br>~~eee~~<br>~~ee~~<br>~~ee~~|—<br>~~eee~~<br>~~ff~~<br>~~of~~|0.349<br>~~eee~~<br>~~ff~~<br>~~offf~~|—<br>~~eee~~<br>~~ff~~<br>~~fF~~<br>~~ff~~|0.381<br>~~eee~~<br>~~ff~~<br>~~fFft~~<br>~~ffff~~|—<br>~~eee~~<br>~~ff~~<br>~~ft~~<br>~~ff~~|0.396<br>~~eee~~<br>~~ff~~<br>~~ft~~<br>~~ff~~|UI<br>~~eee~~<br>~~ff~~|
|tDVEDQ<br>~~op~~<br>~~op~~<br>~~op~~<br>~~i~~|Input Data Hold After DQS<br>Input<br>~~op~~<br>~~op~~<br>~~op~~<br>~~i~~||0.665<br>~~ff~~<br>~~of~~<br>~~ef~~|—<br>~~ff~~<br>~~offf~~<br>~~eftf~~|0.630<br>~~ff~~<br>~~fF~~<br>~~ff~~<br>~~tffF~~|—<br>~~ff~~<br>~~fFft~~<br>~~ffff~~<br>~~fFff~~|0.613<br>~~ff~~<br>~~ft~~<br>~~ff~~<br>~~ff~~|—<br>~~ff~~<br>~~ft~~<br>~~ff~~<br>~~ff~~|UI<br>~~ff~~|
|tDQVBS<br>~~op~~<br>~~op~~<br>~~i~~<br>~~op~~|Output Data Invalid Before<br>DQS Output<br>~~op~~<br>~~op~~<br>~~i~~<br>~~op~~||0.25<br>~~of~~<br>~~ef~~<br>~~fF~~|—<br>~~offf~~<br>~~eftf~~<br>~~fFtf~~|0.25<br>~~fF~~<br>~~ff~~<br>~~tffF~~<br>~~tfft~~|—<br>~~fF ft~~<br>~~ffff~~<br>~~fFff~~<br>~~ft~~|0.25<br>~~ft~~<br>~~ff~~<br>~~ff~~<br>~~ftff~~|—<br>~~ft~~<br>~~ff~~<br>~~ff~~<br>~~ff~~|UI|
|tDQVAS<br>~~op~~<br>~~i~~<br>~~op~~<br>~~ee~~|Output Data Invalid After<br>DQS Output<br>~~op~~<br>~~i~~<br>~~op~~||0.25<br>~~of~~<br>~~ef~~<br>~~fF~~<br>~~ot~~|—<br>~~of ff~~<br>~~eftf~~<br>~~fFtf~~<br>~~otfF~~|0.25<br>~~ff~~<br>~~tffF~~<br>~~tfft~~<br>~~fFfF~~|—<br>~~ff ff~~<br>~~fFff~~<br>~~ft~~<br>~~fFff~~|0.25<br>~~ff~~<br>~~ff~~<br>~~ftff~~<br>~~ff~~|—<br>~~ff~~<br>~~ff~~<br>~~ff~~<br>~~ff~~|UI|
|fDATA<br>~~i~~<br>~~op~~<br>~~ee~~<br>~~ee~~|MEM LPDDR Serial Data<br>Speed<br>~~i~~<br>~~op~~<br>~~ee~~<br>||—<br>~~ef~~<br>~~fF~~<br>~~ot~~<br>~~**a**~~|120<br>~~ef tf~~<br>~~fFtf~~<br>~~otfF~~<br>~~ee~~|—<br>~~tf fF~~<br>~~tfft~~<br>~~fFfF~~<br>~~ee~~|110<br>~~fF ff~~<br>~~ft~~<br>~~fFff~~<br>~~es~~|—<br>~~ff~~<br>~~ftff~~<br>~~ff~~<br>~~e~~~~**e**~~|96<br>~~ff~~<br>~~ff~~<br>~~ff~~|Mbps|
|fSCLK<br>~~op~~<br>~~ee~~<br>~~ee ee~~|SCLK Frequency<br>~~op~~<br>~~ee~~<br>~~ee~~||—<br>~~fF~~<br>~~ot~~<br>~~**a**~~|60<br>~~fF tf~~<br>~~otfF~~<br>~~ee~~<br>~~a e~~|—<br>~~tf ft~~<br>~~fFfF~~<br>~~ee~~<br>~~e~~|55<br>~~ft~~<br>~~fFff~~<br>~~es~~<br>~~e~~|—<br>~~ft ff~~<br>~~ff~~<br>~~e~~~~**e**~~<br>~~e~~|48<br>~~ff~~<br>~~ff~~<br>~~ee~~|MHz<br>~~ee~~|
|fLPDDR<br>~~ee~~<br>~~ee ee~~|LPDDR Data Transfer Rate<br>~~ee~~<br>~~ee~~||0<br>~~ot~~<br>~~**a**~~|120<br>~~ot fF~~<br>~~ee~~<br>~~a e~~|0<br>~~fF fF~~<br>~~ee~~<br>~~e~~|110<br>~~fF ff~~<br>~~es~~<br>~~e~~|0<br>~~ff~~<br>~~e~~~~**e**~~<br>~~e~~|96<br>~~ff~~<br>~~ee~~|Mbps<br>~~ee~~|
|**DDR9, 11**<br>~~ee~~<br>~~**a** ee ee es e~~~~**e**~~<br>~~ee ee~~<br>~~a e~~<br>~~ee ee~~<br>~~Re~~<br>~~op~~<br>~~tfftftff~~||||||||||
|tDVADQ<br>~~op~~<br>~~—~~|Input Data Valid After DQS<br>Input<br>~~op~~|MachXO2-1200/U<br>and larger devices,<br>right side only12|—<br>~~tf~~<br>~~|~~|0.347<br>~~tfft~~<br>~~ft~~|—<br>~~ftft~~<br>~~ftft~~|0.374<br>~~ft~~<br>~~ft~~|—<br>~~ftff~~<br>~~fttf~~|0.393<br>~~ff~~<br>~~tf~~|UI<br>~~tf~~|
|tDVEDQ<br>~~op~~<br>~~—~~<br>~~op~~|Input Data Hold After DQS<br>Input<br>~~op~~<br>~~op~~||0.665<br>~~tf~~<br>~~|~~<br>~~et~~|—<br>~~tf ft~~<br>~~ft~~<br>~~etft~~|0.637<br>~~ft ft~~<br>~~ftft~~<br>~~ftft~~|—<br>~~ft~~<br>~~ft~~<br>~~ftft~~|0.616<br>~~ft ff~~<br>~~fttf~~<br>~~fttf~~|—<br>~~ff~~<br>~~tf~~<br>~~tf~~|UI<br>~~tf~~|
|tDQVBS<br>~~—~~<br>~~op~~|Output Data Invalid Before<br>DQS Output<br>~~op~~||0.25<br>~~|~~<br>~~et~~|—<br>~~ft~~<br>~~etft~~|0.25<br>~~ft ft~~<br>~~ftft~~|—<br>~~ft~~<br>~~ftft~~|0.25<br>~~ft tf~~<br>~~fttf~~|—<br>~~tf~~<br>~~tf~~|UI<br>~~tf~~|
© 2010-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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**MachXO2 Family Data Sheet Data Sheet**
|**Parameter**<br>~~—{f~~<br>~~|~~|**Description**<br>~~{f~~<br>~~|~~|**Device**<br>~~ee~~|**–3**<br>~~ee~~|**–3**<br>~~ee~~|**–2**<br>~~ee~~|**–2**<br>~~ee~~|**–1**<br>~~ee~~|**–1**<br>~~ee~~|**Units**<br>~~ee~~|
|---|---|---|---|---|---|---|---|---|---|
||||**Min.**<br>~~ee~~<br>~~|~~|**Max.**<br>~~ee~~<br>~~|~~|**Min.**<br>~~ee~~<br>~~|~~|**Max.**<br>~~ee~~<br>~~yt~~|**Min.**<br>~~ee~~<br>~~yt~~|**Max.**<br>~~ee~~||
|tDQVAS<br>~~— {f~~<br>~~|~~<br>~~ee~~|Output Data Invalid After<br>DQS Output<br>~~{f~~<br>~~|~~<br>~~ee~~||0.25<br>~~ee~~<br>~~|~~<br>~~ee~~|—<br>~~ee~~<br>~~|~~<br>~~ee ee~~|0.25<br>~~ee~~<br>~~|~~<br>~~ee~~|—<br>~~ee~~<br>~~yt~~<br>~~ee~~|0.25<br>~~ee~~<br>~~yt~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~|UI<br>~~ee~~<br>~~ee~~|
|fDATA<br>~~|~~<br>~~ee~~<br>~~ee~~|MEM DDR Serial Data Speed<br>~~|~~<br>~~ee~~||—<br>~~|~~<br>~~ee~~<br>~~ee~~|140<br>~~|~~<br>~~ee ee~~<br>~~ee~~|—<br>~~|~~<br>~~ee~~<br>~~ee~~|116<br>~~yt~~<br>~~ee~~<br>~~ee~~|—<br>~~yt~~<br>~~ee~~<br>~~es~~|98<br>~~ee~~|Mbps<br>~~ee~~|
|fSCLK<br>~~ee~~<br>~~ee~~<br>~~es~~|SCLK Frequency<br>~~ee~~||—<br>~~ee ~~<br>~~ee~~<br>~~ee~~|70<br> ~~ee ee~~<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|58<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|—<br>~~ee ~~<br>~~es~~<br>~~ee~~<br>~~ee~~|49<br> ~~ee~~<br>~~ee~~|MHz<br>~~ee~~<br>~~ee~~|
|fMEM_DDR<br>~~ee~~<br>~~es~~|MEM DDR Data Transfer Rate||N/A<br>~~ee~~<br>~~ee~~|140<br>~~ee~~<br>~~ee~~|N/A<br>~~ee~~<br>~~ee~~<br>~~ee~~|116<br>~~ee~~<br>~~ee~~<br>~~ee~~|N/A<br>~~es~~<br>~~ee~~<br>~~ee~~|98<br>~~ee~~|Mbps<br>~~ee~~|
|**DDR29, 11**<br>~~es~~<br>~~ee~~<br>~~ee ee ee~~<br>~~|~~||||||||||
|tDVADQ|Input Data Valid After DQS<br>Input|MachXO2-1200/U<br>and larger devices,<br>right side only12<br>~~ee~~|—|0.372|—|0.394|—|0.410|UI|
|tDVEDQ|Input Data Hold After DQS<br>Input||0.690|—|0.658|—|0.618|—|UI|
|tDQVBS|Output Data Invalid Before<br>DQS Output||0.25|—|0.25|—|0.25|—|UI|
|tDQVAS<br>~~ee ee~~|Output Data Invalid After<br>DQS Output<br>~~ee~~||0.25<br>~~ee~~|—|0.25|—|0.25|—|UI|
|fDATA<br>~~ee ee~~<br>~~ee~~|MEM DDR Serial Data Speed<br>~~ee~~||—<br>~~ee~~<br>~~ee~~|140<br>~~ee~~|—<br>~~ee~~|116<br>~~ee~~|—<br>~~ee~~|98|Mbps|
|fSCLK<br>~~ee ee~~<br>~~ee~~|SCLK Frequency<br>~~ee~~||—<br>~~ee~~<br>~~ee~~|70<br>~~ee~~|—<br>~~ee~~|58<br>~~ee~~|—<br>~~ee~~|49|MHz|
|fMEM_DDR2<br>~~ee~~|MEM DDR2 Data Transfer<br>Rate||N/A<br>~~ee~~|140<br>~~ee~~|N/A<br>~~ee~~|116<br>~~ee~~|N/A<br>~~ee~~|98|Mbps|
## **Notes:**
1. Exact performance may vary with device and design implementation. Commercial timing numbers are shown at 85 °C and 1.14 V. Other operating conditions, including industrial and automotive, can be extracted from the Diamond software.
2. General I/O timing numbers based on LVCMOS 2.5, 8 mA, 0 pf load, fast slew rate.
3. Generic DDR timing numbers based on LVDS I/O (for input, output, and clock ports).
4. DDR timing numbers based on SSTL25. DDR2 timing numbers based on SSTL18. LPDDR timing numbers based in LVCMOS18.
5. 7:1 LVDS (GDDR71) uses the LVDS I/O standard (for input, output, and clock ports).
6. For Generic DDRX1 mode tSU = tHO = (tDVE - tDVA - 0.03 ns)/2.
7. The tSU_DEL and tH_DEL values use the SCLK_ZERHOLD default step size. Each step is 167 ps (–3), 182 ps (–2), 195 ps (–1).
8. This number is for general purpose usage. Duty cycle tolerance is +/–10%.
9. Duty cycle is +/– 5% for system usage.
10. The above timing numbers are generated using the Diamond design tool. Exact performance may vary with the device selected.
11. Advance information for MachXO2 devices in 48 QFN packages.
12. DDR memory interface is not supported in QN84 (84 QFN) and SG32 (32 QFN) packages.
**==> picture [113 x 96] intentionally omitted <==**
**----- Start of picture text -----**<br>
RX CLK Input<br>or DQS Input<br>RX Data Input<br>or DQ Input<br>RX.Aligned tDVA or tDVADQ<br>tDVE or tDVEDQ<br>**----- End of picture text -----**<br>
**Figure 3.5. Receiver RX.CLK.Aligned and MEM DDR Input Waveforms**
© 2010-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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**MachXO2 Family Data Sheet Data Sheet**
**==> picture [344 x 349] intentionally omitted <==**
**----- Start of picture text -----**<br>
RX CLK Input<br>|I<br>I|<br>RX Data Input XXXXYY) NYXXY) XXXXYY)<br>Ss a tt GA<br>RX.Centered +i, (+e)<br>||<br>tSU | tHO tSU | tHO<br>Figure 3.6. Receiver RX.CLK.Centered Waveforms<br>TX CLK Output<br>I |<br>a Irn | oe an<br>and Oh) ONY)<br>TX Data Output<br>RRR NKR<br>TX.Aligned i panna<br>||<br>tDIB | tDIA tDIB | tDIA<br>Figure 3.7. Transmitter TX.CLK.Aligned Waveforms<br>TX CLK Output<br>or DQS Output<br>I|<br>yn I Ce|<br>TX Data Outputor DQ Output iXXYY) OXY) XXXY)<br>TX.Centered <I<br>|I<br>tDVB or l tDVA or tDVB or I tDVA or<br>tDQ VBS | tDQ VAS tDQ VBS I tDQ VAS<br>**----- End of picture text -----**<br>
**Figure 3.8. Transmitter TX.CLK.Centered and MEM DDR Output Waveforms**
© 2010-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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**MachXO2 Family Data Sheet Data Sheet**
## **Receiver – Shown for one LVDS Channel**
**==> picture [439 x 470] intentionally omitted <==**
**----- Start of picture text -----**<br>
# of Bits 12 3<br>Data In<br>756 Mbps FOX 7X 2K SX 4X SX EF ON 1X 2X SX AK SX OX OX 1K 2K 3X 4 SH SH OX 1X 24 SK 4X SX Cf 0}<br>ol 11 21 3l 4l<br>Clock In<br>125 MHz<br>||<br>| | Bit # | Bit # | Bit # | Bit #<br>lox 40 -4 120 - 8 130 - 15 | 40 - 22<br>lox I41 - 2 121 - 9 131 - 16 141 - 23<br>For each Channel: lox 142 - 3 122 - 10 132 - 47 142 - 24<br>7-bit Output Words lox 143 - 4 123 - 41 133 - 18 | 43 - 25<br>to FPGA Fabric lox 114 - 5 124 - 12 134 - 19 144 - 26<br>lox 115 - 6 125 - 13 135 - 20 | 45 - 27<br>lox 116 - 7 126 - 14 136 - 21 | 46 - 28<br>Transmitter – Shown for one LVDS Channel<br># of Bits 12 34 56 7 8 9 10 11 121314 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29<br>Data Out756 Mbps LOX AK 2K SK 4X SX EX OK AN 2K SK 4K SX SX OK 1K 2K 3K 4K SX SX OX 1K 2K 3X 4X 5X 6X 0)<br>ol 11 2! 3l 4l<br>Clock Out<br>125 MHz<br>||<br>Bit # | Bit # | Bit # | Bit # | |<br>For each Channel: 00 - 1! 10 - 8 ! 20 -1 5 | 30 - 22! I<br>7-bit Words from 01 - 2! 11 - 9 ! 21 -1 6 | 31 - 23! I<br>FPGA Fabric 020304 --- 5!3)4 121314 --- 1110112! 222324-1 -1- 1879 || 32 33 34 --- 24126! 25 ||<br>05 - 6 | 15 - 13! 25 - 20 | 35 - 27! |<br>06 - 7! 16 - 14! 26 -2 1 | 36 - 28! |<br>Figure 3.9. GDDR71 Video Timing Waveforms<br>CLK Yoef<br>|<br>|<br>Data<br>0 1 2 3 4 5 6 0<br>(4-6 bits) X X [__KXXXX__XXAAX__AKXXXX_—_XXAAX] VV VVVVV VYWVY VYVWVYV VAVAVAVAY/ XXXVYWY —_XHAAX__XXXXXVYVVV VVVVV _XXVV<br>> |<br>I4 tDVA > !I<br>tDVE<br>Figure 3.10. Receiver GDDR71_RX. Waveforms<br>CLK YoNf<br>|<br>| |<br>Data<br>0 1 2 3 4 5 6 0<br>(4-6 bits) X X WYWWVY_VYW¥_AXMAX MAXX VWWWY_XXXXX AXAVYWW¥W___ XXXVYWWY_ VWXXX HXYYW VY<br>> Ae tDIB<br>tDIA<br>**----- End of picture text -----**<br>
**Transmitter – Shown for one LVDS Channel**
## **Figure 3.11. Transmitter GDDR71_TX. Waveforms**
© 2010-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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**MachXO2 Family Data Sheet Data Sheet**
## **3.23. sysCLOCK PLL Timing**
Over Recommended Operating Conditions
## **Table 3.28. sysCLOCK PLL Timing**
|**Parameter**<br>~~CO~~|**Descriptions**<br>~~CO~~|**Conditions**<br>~~CO~~|**Min.**<br>~~CO~~|**Max.**<br>~~CO~~|**Units**<br>~~CO~~|
|---|---|---|---|---|---|
|fIN|Input Clock Frequency (CLKI, CLKFB)|—|7|400|MHz|
|fOUT<br>~~a~~|Output Clock Frequency (CLKOP, CLKOS,<br>CLKOS2)<br>~~ee~~|—<br>~~ee~~|1.5625<br>~~ee~~|400<br>~~ee~~|MHz<br>~~ee~~|
|fOUT2|Output Frequency (CLKOS3 cascaded from<br>CLKOS2)|—|0.0122|400|MHz|
|fVCO<br>~~OO~~<br>~~es~~|PLL VCO Frequency<br>~~OO~~<br>|—<br>~~OO~~<br>|200<br>~~OO~~<br>|800<br>~~OO~~<br>|MHz<br>~~OO~~<br>|
|fPFD<br>~~es~~|Phase Detector Input Frequency<br>|—<br>|7<br>|400<br>|MHz<br>|
|**AC Characteristics**<br>~~esPe~~||||||
|tDT<br>~~Pe~~<br>~~CO~~|Output Clock Duty Cycle<br>~~Pe~~<br>~~CO~~|Without duty trim selected3<br>~~Pe~~<br>~~CO~~|45<br>~~Pe~~<br>~~CO~~|55<br>~~Pe~~<br>~~CO~~|%<br>~~Pe~~<br>~~CO~~|
|tDT_TRIM7<br>~~CO~~<br>~~a~~|Edge Duty Trim Accuracy<br>~~CO~~<br>|—<br>~~CO~~<br>|–75<br>~~CO~~<br>|75<br>~~CO~~<br>|%<br>~~CO~~<br>|
|tPH4<br>~~aeC~~<br>~~a~~|Output Phase Accuracy<br>~~eC~~<br>~~a~~|—<br>~~eC~~<br>~~po~~|–6<br>~~eC~~<br>~~po~~|6<br>~~eC~~<br>~~po~~|%<br>~~eC~~<br>~~po~~|
|tOPJIT1, 8<br>~~a~~|Output Clock Period Jitter<br>~~a~~<br>~~ee~~|fOUT> 100 MHz<br>~~po~~|—<br>~~po~~|150<br>~~po~~|ps p-p<br>~~po~~|
|||fOUT< 100 MHz<br>~~po~~<br>~~po~~|—<br>~~po~~<br>~~po~~|0.007<br>~~po~~<br>~~po~~|UIPP<br>~~po~~<br>~~po~~|
||Output Clock Cycle-to-cycle Jitter<br>~~a~~<br>~~ee~~<br>~~a~~|fOUT> 100 MHz<br>~~po~~<br>~~po~~|—<br>~~po~~<br>~~po~~|180<br>~~po~~<br>~~po~~|ps p-p<br>~~po~~<br>~~po~~|
|||fOUT< 100 MHz<br>~~po~~<br>~~ee~~|—<br>~~po~~<br>~~ee eee~~|0.009<br>~~po~~<br>~~eee~~|UIPP<br>~~po~~<br>~~eee~~|
||Output Clock Phase Jitter<br>~~ee~~<br>~~a~~|fPFD> 100 MHz<br>~~po~~<br>~~ee~~|—<br>~~po~~<br>~~ee eee~~|160<br>~~po~~<br>~~eee~~|ps p-p<br>~~po~~<br>~~eee~~|
|||fPFD< 100 MHz<br>~~ee~~<br>~~po~~|—<br>~~ee eee~~<br>~~po~~|0.011<br>~~eee~~<br>~~po~~<br>~~eee~~|UIPP<br>~~eee~~<br>~~po~~<br>~~eee~~|
||Output Clock Period Jitter (Fractional-N)<br>~~a~~<br>~~a~~|fOUT> 100 MHz<br>~~ee ~~<br>~~e~~|—<br> ~~ee eee~~<br>~~e~~~~**e**~~|230<br>~~eee~~<br>~~**e**~~<br>~~eee~~|ps p-p<br>~~eee~~<br>~~**e**~~<br>~~eee~~|
|||fOUT< 100 MHz<br>~~e~~<br>~~R~~|—<br>~~e~~~~**e**~~<br>~~R~~|0.12<br>~~**e**~~<br>~~eee~~|UIPP<br>~~**e**~~<br>~~eee~~|
||Output Clock Cycle-to-cycle Jitter<br>(Fractional-N)<br>~~a~~<br>~~yy~~|fOUT> 100 MHz<br>~~e~~<br>~~R~~<br>~~yy~~|—<br>~~e~~~~**e**~~<br>~~R~~<br>~~yy~~|230<br>~~**e**~~<br>~~eee~~<br>~~yy~~|ps p-p<br>~~**e**~~<br>~~eee~~<br>~~yy~~|
|||fOUT< 100 MHz<br>~~yy~~<br>~~es~~|—<br>~~yy~~<br>~~es~~|0.12<br>~~yy~~<br>~~es~~|UIPP<br>~~yy~~<br>~~es~~|
|tSPO<br>~~eC~~|Static Phase Offset<br>~~eC~~|Divider ratio = integer<br>~~eC~~|–120<br>~~eC~~|120<br>~~eC~~|ps<br>~~eC~~|
|tW<br>~~a~~|Output Clock Pulse Width<br>~~a~~|At 90% or 10%3<br>~~GG~~|0.9<br>~~GG~~|—<br>~~GG~~|ns<br>~~GG~~|
|tLOCK2, 5<br>~~a ~~<br>~~CO~~|PLL Lock-in Time<br> ~~a~~<br>~~CO~~|—<br>~~GG~~<br>~~CO~~|—<br>~~GG~~<br>~~CO~~|15<br>~~GG~~<br>~~CO~~|ms<br>~~GG~~<br>~~CO~~|
|tUNLOCK<br>~~CO~~<br>~~CO~~<br>~~—~~|PLL Unlock Time<br>~~CO~~<br>~~CO~~<br>~~————EEEEEE~~|—<br>~~CO~~<br>~~CO~~<br>~~————EEEEEE~~|—<br>~~CO~~<br>~~CO~~<br>~~————EEEEEE~~|50<br>~~CO~~<br>~~CO~~<br>~~————EEEEEE~~|ns<br>~~CO~~<br>~~CO~~<br>~~————EEEEEE~~|
|tIPJIT6<br>~~CO~~<br>~~—~~|Input Clock Period Jitter<br>~~CO~~<br>~~————EEEEEE~~|fPFD> 20 MHz<br>~~CO~~<br>~~————EEEEEE~~|—<br>~~CO~~<br>~~————EEEEEE~~|1,000<br>~~CO~~<br>~~————EEEEEE~~|ps p-p<br>~~CO~~<br>~~————EEEEEE~~|
|||fPFD< 20 MHz<br>~~————EEEEEE~~<br>~~es~~|—<br>~~————EEEEEE~~<br>~~es~~|0.02<br>~~————EEEEEE~~<br>~~es~~|UIPP<br>~~————EEEEEE~~<br>~~es~~|
|tHI<br>~~—~~<br>~~eC~~|Input Clock High Time<br>~~————EEEEEE~~<br>~~eC~~|90% to 90%<br>~~————EEEEEE~~<br>~~eC~~|0.5<br>~~————EEEEEE~~<br>~~eC~~|—<br>~~————EEEEEE~~<br>~~eC~~|ns<br>~~————EEEEEE~~<br>~~eC~~|
|tLO<br>~~a~~|Input Clock Low Time<br>~~a~~|10% to 10%<br>~~GG~~|0.5<br>~~GG~~|—<br>~~GG~~|ns<br>~~GG~~|
|tSTABLE5<br>~~a ~~<br>~~CO~~|STANDBY High to PLL Stable<br> ~~a~~<br>~~CO~~|—<br>~~GG~~<br>~~CO~~|—<br>~~GG~~<br>~~CO~~|15<br>~~GG~~<br>~~CO~~|ms<br>~~GG~~<br>~~CO~~|
|tRST<br>~~CO~~<br>~~CO~~|RST/RESETM Pulse Width<br>~~CO~~<br>~~CO~~|—<br>~~CO~~<br>~~CO~~|1<br>~~CO~~<br>~~CO~~|—<br>~~CO~~<br>~~CO~~|ns<br>~~CO~~<br>~~CO~~|
|tRSTREC<br>~~CO~~<br>~~GO~~<br>~~es~~|RST Recovery Time<br>~~CO~~<br>~~GO~~|—<br>~~CO~~<br>~~GO~~|1<br>~~CO~~<br>~~GO~~|—<br>~~CO~~<br>~~GO~~|ns<br>~~CO~~<br>~~GO~~|
|tRST_DIV<br>~~es~~|RESETC/D Pulse Width|—|10|—|ns|
|tRSTREC_DIV<br>~~es~~<br>~~a~~|RESETC/D Recovery Time<br>~~GG~~|—<br>~~GG~~|1<br>~~GG~~|—<br>~~GG~~|ns<br>~~GG~~|
|tROTATE-SETUP<br>~~a~~<br>~~a~~<br>~~es~~|PHASESTEP Setup Time<br>~~GG~~|—<br>~~GG~~|10<br>~~GG~~|—<br>~~GG~~|ns<br>~~GG~~|
|tROTATE_WD<br>~~a~~<br>~~es~~|PHASESTEP Pulse Width|—|4|—|VCO Cycles|
**Notes:**
1. Period jitter sample is taken over 10,000 samples of the primary PLL output with a clean reference clock. Cycle-to-cycle jitter is taken over 1000 cycles. Phase jitter is taken over 2000 cycles. All values per JESD65B.
2. Output clock is valid after tLOCK for PLL reset and dynamic delay adjustment.
3. Using LVDS output buffers.
4. CLKOS as compared to CLKOP output for one phase step at the maximum VCO frequency. See MachXO2 sysCLOCK PLL Design and Usage Guide (FPGA-TN-02157) for more details.
5. At minimum fPFD. As the fPFD increases, the time decreases to approximately 60% of the value listed.
© 2010-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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6. Maximum allowed jitter on an input clock. PLL unlock may occur if the input jitter exceeds this specification. Jitter on the input clock may be transferred to the output clocks, resulting in jitter measurements outside the output specifications listed in this table.
7. Edge Duty Trim Accuracy is a percentage of the setting value. Settings available are 70 ps, 140 ps, and 280 ps in addition to the default value of none.
8. Jitter values measured with the internal oscillator operating. The jitter values increase with the loading of the PLD fabric and in the presence of SSO noise.
## **3.24. MachXO2 Oscillator Output Frequency**
**Table 3.29. MachXO2 Oscillator Output Frequency[1]**
|**Symbol**|**Parameter**|**Min.**|**Typ.**|**Max**|**Units**|
|---|---|---|---|---|---|
|fMAX|Oscillator Output Frequency (Commercial Grade Devices, 0<br>to 85°C)|125.685|133|140.315|MHz|
||Oscillator Output Frequency (Industrial Grade Devices, –40<br>°C to 100 °C)|124.355|133|141.645|MHz|
|tDT|Output Clock Duty Cycle|43|50|57|%|
|tOPJIT|Output Clock Period Jitter|0.01|0.012|0.02|UIPP|
|tSTABLEOSC|STDBY Low to Oscillator Stable|0.01|0.05|0.1|µs|
**Note:**
1. Output Clock Period Jitter specified at 133 MHz. The values for lower frequencies are smaller UIPP. The typical value for 133 MHz is 95 ps and for 2.08 MHz the typical value is 1.54 ns.
## **3.25. MachXO2 Standby Mode Timing – HC/HE Devices**
**Table 3.30. MachXO2 Standby Mode Timing – HC/HE Devices**
**==> picture [486 x 174] intentionally omitted <==**
**----- Start of picture text -----**<br>
pf Symbol Parameter Device Min. Typ. Max Units<br>a tPWRDN GG USERSTDBY High to Stop All — — 9 ns<br>ee LCMXO2-256 — — — µs<br>es LCMXO2-640 — — — µs<br>es LCMXO2-640U — — — µs<br>es LCMXO2-1200 20 — 50 µs<br>tPWRUP USERSTDBY Low to Power-Up es LCMXO2-1200U — — — µs<br>ee LCMXO2-2000 — — — µs<br>es LCMXO2-2000U — — — µs<br>es LCMXO2-4000 — — — µs<br>LCMXO2-7000 — — — µs<br>tWSTDBY USERSTDBY Pulse Width All 18 — — ns<br>Re po<br>**----- End of picture text -----**<br>
**==> picture [321 x 81] intentionally omitted <==**
**----- Start of picture text -----**<br>
USERSTDBY Mode<br>BG, POR<br>tPWRUP<br>tPWRDN<br>USERSTDBY<br>tWSTDBY<br>**----- End of picture text -----**<br>
© 2010-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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## **3.26. MachXO2 Standby Mode Timing – ZE Devices**
**Table 3.31. MachXO2 Standby Mode Timing – ZE Devices**
|**Symbol**<br>~~a ~~<br>~~ee~~|**Parameter**<br> ~~GO~~<br>|**Device**<br>~~GO~~<br>|**Min.**<br>~~GO~~<br>|**Typ.**<br>~~GO~~<br>~~CO~~<br>|**Max**<br>~~GO~~<br>~~CO~~<br>|**Units**<br>~~GO~~<br>|
|---|---|---|---|---|---|---|
|tPWRDN<br>~~ee~~|USERSTDBY High to Stop<br>~~eG~~|All<br>~~eG~~|—<br>~~eG~~|—<br>~~CO~~<br>~~eG~~|13<br>~~CO~~<br>~~eG~~|ns<br>~~eG~~|
|tPWRUP<br>~~ee~~|USERSTDBY Low to Power-Up<br>|LCMXO2-256<br><br>~~es~~|—<br><br>~~es~~|—<br>~~CO~~<br><br>~~es~~|—<br>~~CO~~<br><br>~~es~~|µs<br><br>~~es~~|
|||LCMXO2-640<br>~~ee~~|—<br>~~ee~~|—<br>~~ee~~|—<br>~~ee~~|µs<br>~~ee~~|
|||LCMXO2-1200<br>~~es~~|20<br>~~es~~|—<br>~~es~~|50<br>~~es~~|µs<br>~~es~~|
|||LCMXO2-2000<br>~~es~~|—<br>~~es~~|—<br>~~es~~|—<br>~~es~~|µs<br>~~es~~|
|||LCMXO2-4000<br>~~es~~|—<br>~~es~~|—<br>~~es~~|—<br>~~es~~|µs<br>~~es~~|
|||LCMXO2-7000<br>~~ee~~|—<br>~~ee~~|—<br>~~ee~~|—<br>~~ee~~|µs<br>~~ee~~|
|tWSTDBY<br>~~a ~~|USERSTDBY Pulse Width<br> ~~a~~|All<br>~~GO~~|19<br>~~GO~~|—<br>~~GO~~|—<br>~~GO~~|ns<br>~~GO~~|
|tBNDGAPSTBL<br>~~a~~|USERSTDBY High to Bandgap Stable<br>~~a~~|All<br>~~DC~~|—<br>~~DC~~|—<br>~~DC~~|15|ns|
## **3.27. Flash Download Time**
**Table 3.32. Flash Download Time**
|**Symbol**|**Parameter**|**Device**|**Typ.**|**Units**|
|---|---|---|---|---|
|tREFRESH|POR to Device I/O Active|LCMXO2-256|0.6|ms|
|||LCMXO2-640|1.0|ms|
|||LCMXO2-640U|1.9|ms|
|||LCMXO2-1200|1.9|ms|
|||LCMXO2-1200U|1.4|ms|
|||LCMXO2-2000|1.4|ms|
|||LCMXO2-2000U|2.4|ms|
|||LCMXO2-4000|2.4|ms|
|||LCMXO2-7000|3.8|ms|
## **Notes:**
1. Assumes sysMEM EBR initialized to an all zero pattern if they are used.
2. The Flash download time is measured starting from the maximum voltage of POR trip point.
© 2010-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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## **3.28. JTAG Port Timing Specifications**
**Table 3.33. JTAG Port Timing Specifications**
|**Symbol**|**Parameter**|**Min.**|**Max.**|**Units**|
|---|---|---|---|---|
|fMAX|TCK clock frequency|—|25|MHz|
|tBTCPH|TCK [BSCAN] clock pulse width high|20|—|ns|
|tBTCPL|TCK [BSCAN] clock pulse width low|20|—|ns|
|tBTS|TCK [BSCAN] setup time|10|—|ns|
|tBTH|TCK [BSCAN] hold time|8|—|ns|
|tBTCO|TAP controller falling edge of clock to valid output|—|10|ns|
|tBTCODIS|TAP controller falling edge of clock to valid disable|—|10|ns|
|tBTCOEN|TAP controller falling edge of clock to valid enable|—|10|ns|
|tBTCRS|BSCAN test capture register setup time|8|—|ns|
|tBTCRH|BSCAN test capture register hold time|20|—|ns|
|tBUTCO|BSCAN test update register, falling edge of clock to valid output|—|25|ns|
|tBTUODIS|BSCAN test update register, falling edge of clock to valid disable|—|25|ns|
|tBTUPOEN|BSCAN test update register, falling edge of clock to valid enable|—|25|ns|
**==> picture [419 x 308] intentionally omitted <==**
**----- Start of picture text -----**<br>
TMS<br>TDI<br>tBTS tBTH<br>tBTCPH tBTCPL tBTCP<br>TCK<br>tBTCOEN tBTCO tBTCODIS<br>TDO Valid Data Valid Data<br>tBTCRH<br>tBTCRS<br>Data to be<br>captured Data Captured<br>from I/O<br>tBTUPOEN tBUTCO tBTUODIS<br>Data to be<br>driven out<br>to I/O Valid Data Valid Data<br>**----- End of picture text -----**<br>
**Figure 3.12. JTAG Port Timing Waveforms**
© 2010-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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## **3.29. sysCONFIG Port Timing Specifications**
**Table 3.34. sysCONFIG Port Timing Specifications**
|**Symbol**<br>~~GG~~|**Parameter**<br>~~GG~~|**Parameter**<br>~~GG~~|**Min.**<br>~~GG~~|**Max.**<br>~~GG~~|**Units**<br>~~GG~~|
|---|---|---|---|---|---|
|**All Configuration Modes**<br>~~PR~~||||||
|tPRGM<br>~~Ce~~|PROGRAMN low pulse accept<br>~~Ce~~||55<br>~~Ce~~|—<br>~~Ce~~|ns<br>~~Ce~~|
|tPRGMJ<br>~~Ce~~|PROGRAMN low pulse rejection<br>~~Ce~~||—<br>~~Ce~~|25<br>~~Ce~~|ns<br>~~Ce~~|
|tINITL|INITN low time<br>~~po~~|LCMXO2-256<br>~~es~~|—<br>~~es~~|30<br>~~es~~|µs<br>~~es~~|
|||LCMXO2-640|—<br>~~ee~~|35<br>~~eee~~|µs<br>~~ee~~|
|||LCMXO2-640U/<br>LCMXO2-1200<br>~~re~~|—<br>~~re~~<br>~~ee~~|55<br>~~re~~<br>~~eee~~|µs<br>~~re~~<br>~~ee~~|
|||LCMXO2-1200U/<br>LCMXO2-2000|—<br>~~ee ~~|70<br> ~~eee ~~|µs<br> ~~ee~~|
|||LCMXO2-2000U/<br>LCMXO2-4000<br>~~po~~|—|105|µs|
|||LCMXO2-7000<br>~~po~~|—|130|µs|
|tDPPINIT<br>~~eG~~|PROGRAMN low to INITN low<br>~~po~~<br>~~eG~~||—<br>~~eG~~|150<br>~~eG~~|ns<br>~~eG~~|
|tDPPDONE<br>~~Ce~~|PROGRAMN low to DONE low<br>~~Ce~~||—<br>~~Ce~~|150<br>~~Ce~~|ns<br>~~Ce~~|
|tIODISS<br>~~CD~~|PROGRAMN low to I/O disable<br>~~CD~~||—<br>~~CD~~|120<br>~~CD~~|ns<br>~~CD~~|
|**Slave SPI**<br>~~pn~~||||||
|fMAX<br>~~pn~~<br>~~CG~~|CCLK clock frequency<br>~~pn~~<br>~~CG~~||—<br>~~pn~~<br>~~CG~~|66<br>~~pn~~<br>~~CG~~|MHz<br>~~pn~~<br>~~CG~~|
|tCCLKH<br>~~CG~~<br>~~a~~|CCLK clock pulse width high<br>~~CG~~||7.5<br>~~CG~~|—<br>~~CG~~|ns<br>~~CG~~|
|tCCLKL<br>~~Ce~~|CCLK clock pulse width low<br>~~Ce~~||7.5<br>~~Ce~~|—<br>~~Ce~~|ns<br>~~Ce~~|
|tSTSU<br>~~GG~~|CCLK setup time<br>~~GG~~||2<br>~~GG~~|—<br>~~GG~~|ns<br>~~GG~~|
|tSTH<br>~~GG~~<br>~~CG~~|CCLK hold time<br>~~GG~~<br>~~CG~~||0<br>~~GG~~<br>~~CG~~|—<br>~~GG~~<br>~~CG~~|ns<br>~~GG~~<br>~~CG~~|
|tSTCO<br>~~CG~~<br>~~GG~~|CCLK falling edge to valid output<br>~~CG~~<br>~~GG~~||—<br>~~CG~~<br>~~GG~~|10<br>~~CG~~<br>~~GG~~|ns<br>~~CG~~<br>~~GG~~|
|tSTOZ<br>~~GG~~<br>~~CG~~|CCLK falling edge to valid disable<br>~~GG~~<br>~~CG~~||—<br>~~GG~~<br>~~CG~~|10<br>~~GG~~<br>~~CG~~|ns<br>~~GG~~<br>~~CG~~|
|tSTOV<br>~~fe~~|CCLK falling edge to valid enable<br>~~fe~~||—<br>~~fe~~|10<br>~~fe~~|ns<br>~~fe~~|
|tSCS<br>~~fe~~|Chip select high time<br>~~fe~~||25<br>~~fe~~|—<br>~~fe~~|ns<br>~~fe~~|
|tSCSS<br>~~GG~~|Chip select setup time<br>~~GG~~||3<br>~~GG~~|—<br>~~GG~~|ns<br>~~GG~~|
|tSCSH<br>~~GG~~<br>~~CG~~|Chip select hold time<br>~~GG~~<br>~~CG~~||3<br>~~GG~~<br>~~CG~~|—<br>~~GG~~<br>~~CG~~|ns<br>~~GG~~<br>~~CG~~|
|**Master SPI**<br>~~CG~~<br>~~pe~~||||||
|fMAX<br>~~pe~~<br>~~CG~~|MCLK clock frequency<br>~~pe~~<br>~~CG~~||—<br>~~pe~~<br>~~CG~~|133<br>~~pe~~<br>~~CG~~|MHz<br>~~pe~~<br>~~CG~~|
|tMCLKH<br>~~fe~~|MCLK clock pulse width high<br>~~fe~~||3.75<br>~~fe~~|—<br>~~fe~~|ns<br>~~fe~~|
|tMCLKL<br>~~GG~~|MCLK clock pulse width low<br>~~GG~~||3.75<br>~~GG~~|—<br>~~GG~~|ns<br>~~GG~~|
|tSTSU<br>~~GG~~<br>~~Ge~~|MCLK setup time<br>~~GG~~<br>~~Ge~~||5<br>~~GG~~<br>~~Ge~~|—<br>~~GG~~<br>~~Ge~~|ns<br>~~GG~~<br>~~Ge~~|
|tSTH<br>~~Ge~~<br>~~Ge~~|MCLK hold time<br>~~Ge~~<br>~~Ge~~||1<br>~~Ge~~<br>~~Ge~~|—<br>~~Ge~~<br>~~Ge~~|ns<br>~~Ge~~<br>~~Ge~~|
|tCSSPI<br>~~Ge~~<br>~~CG~~|INITN high to chip select low<br>~~Ge~~<br>~~CG~~||100<br>~~Ge~~<br>~~CG~~|200<br>~~Ge~~<br>~~CG~~|ns<br>~~Ge~~<br>~~CG~~|
|tMCLK<br>~~GO~~|INITN high to first MCLK edge<br>~~GO~~||0.75<br>~~GO~~|1<br>~~GO~~|µs<br>~~GO~~|
© 2010-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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## **3.30. I[2] C Port Timing Specifications**
**Table 3.35. I[2] C Port Timing Specifications Symbol Parameter Min. Max. Units** fMAX Maximum SCL clock frequency — 400 kHz ~~es~~ **Notes:**
1. MachXO2 supports the following modes:
- Standard-mode (Sm), with a bit rate up to 100 kbit/s (user and configuration mode)
- Fast-mode (Fm), with a bit rate up to 400 kbit/s (user and configuration mode)
2. Refer to the I[2] C specification for timing requirements.
## **3.31. SPI Port Timing Specifications**
**Table 3.36. SPI Port Timing Specifications[1 ] Symbol Parameter Min. Max. Units** fMAX Maximum SCK clock frequency — 45 MHz ~~ee~~ **Note:**
1. Applies to user mode only. For configuration mode timing specifications, refer to Table 3.34 in this data sheet.
## **3.32. Switching Test Conditions**
Figure 3.13 shows the output test load used for AC testing. The specific values for resistance, capacitance, voltage, and other test conditions are shown in Table 3.37.
**==> picture [190 x 86] intentionally omitted <==**
**----- Start of picture text -----**<br>
V T<br>R1<br>DUT TesP t t n io<br>CL<br>**----- End of picture text -----**<br>
**Figure 3.13. Output Test Load, LVTTL and LVCMOS Standards**
© 2010-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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**Table 3.37. Test Fixture Required Components, Non-Terminated Interfaces[1]**
|**Test Condition**|**R1**|**CL**|**Timing Ref.**|**VT**|
|---|---|---|---|---|
|LVTTL and LVCMOS settings (L -> H, H -> L)|∞|0pF|LVTTL, LVCMOS 3.3 = 1.5 V|—|
||||LVCMOS 2.5 = VCCIO/2|—|
||||LVCMOS 1.8 = VCCIO/2|—|
||||LVCMOS 1.5 = VCCIO/2|—|
||||LVCMOS 1.2 = VCCIO/2|—|
|LVTTL and LVCMOS 3.3 (Z -> H)|188|0pF|1.5 V|VOL|
|LVTTL and LVCMOS 3.3 (Z -> L)|||1.5 V|VOH|
|Other LVCMOS (Z -> H)|||VCCIO/2|VOL|
|Other LVCMOS (Z -> L)|||VCCIO/2|VOH|
|LVTTL + LVCMOS (H -> Z)|||VOH– 0.15 V|VOL|
|LVTTL + LVCMOS (L -> Z)|||VOL– 0.15 V|VOH|
## **Note:**
1. Output test conditions for all other interfaces are determined by the respective standards.
© 2010-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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## **4. Pinout Information**
## **4.1. Signal Descriptions**
|**Signal Name**<br>~~SS~~|**I/O**<br>~~SS~~|**Descriptions**<br>~~SS~~|
|---|---|---|
|**General Purpose**<br>~~a~~|||
|P[Edge]<br>[Row/Column<br>Number]_[A/B/C/D]<br>~~la~~|I/O<br>~~la~~|[Edge] indicates the edge of the device on which the pad is located. Valid edge designations are<br>L (Left), B (Bottom), R (Right), T (Top).<br>[Row/Column Number] indicates the PFU row or the column of the device on which the PIO<br>Group exists. When Edge is T (Top) or B(Bottom), only the Row Number needs to be specified.<br>When Edge is L (Left) or R (Right), only the Column Number needs to be specified.<br>[A/B/C/D] indicates the PIO within the group to which the pad is connected.<br>Some of these user-programmable pins are shared with special function pins. When not used<br>as special function pins, these pins can be programmed as I/O for user logic.<br>During configuration of the user-programmable I/O, the user has an option to tri-state the I/O<br>and enable an internal pull-up, pull-down or buskeeper resistor. This option also applies to<br>unused pins (or those not bonded to a package pin). The default during configuration is for<br>user-programmable I/O to be tri-stated with an internal pull-down resistor enabled. When the<br>device is erased, I/O is tri-stated with an internal pull-down resistor enabled. Some pins, such<br>as PROGRAMN and JTAG pins, default to tri-stated I/O with pull-up resistors enabled when the<br>device is erased.<br>~~la~~|
|NC<br>~~la~~<br>~~a~~|—<br>~~la~~<br>~~ee~~|No connect.<br>~~la~~<br>~~ee~~|
|GND<br>~~a~~<br>~~a~~|—<br>~~ee~~<br>~~ee~~|GND – Ground. Dedicated pins. It is recommended that all GNDs are tied together. For QFN 48<br>package, the exposed diepad is the deviceground.<br>~~ee~~<br>~~ee~~|
|VCC<br>~~a~~<br>~~a~~<br>~~rr~~|—<br>~~ee~~<br>~~ee~~<br>~~ee~~|VCC – The power supply pins for core logic. Dedicated pins. It is recommended that all VCCs are<br>tied to the same supply.<br>~~ee~~<br>~~ee~~<br>~~ee~~|
|VCCIOx<br>~~a~~<br>~~rr~~|—<br>~~ee~~<br>~~ee~~|VCCIO – The power supply pins for I/O Bank x. Dedicated pins. It is recommended that all<br>VCCIOs located in the same bank are tied to the same supply.<br>~~ee~~<br>~~ee~~|
|**PLL and Clock Functions**(Used as user-programmable I/O pins when not used for PLL or clock pins)<br>~~rree~~<br>~~a~~<br>ee~~ee~~<br>~~a~~|||
|[LOC]_GPLL[T, C]_IN<br>~~a~~<br>~~a~~|—<br>~~a~~<br>ee<br>~~ee~~|Reference Clock (PLL) input pads: [LOC] indicates location. Valid designations are L (Left PLL)<br>and R(Right PLL). T = true and C = complement.<br>~~a~~<br>~~ee~~|
|[LOC]_GPLL[T, C]_FB<br>~~a~~|—<br>ee<br>~~ee~~|Optional Feedback (PLL) input pads: [LOC] indicates location. Valid designations are L (Left PLL)<br>and R(Right PLL). T = true and C = complement.<br>~~ee~~|
|PCLK [n]_[2:0]<br>~~a~~|—<br>~~ee~~<br>~~a~~|Primary Clock pads. One to three clock pads per side.<br>~~a~~|
|**Test and Programming**(Dual function pins used for test access port and during sysCONFIG™)<br>~~a~~<br>~~a~~|||
|TMS<br>~~a~~<br>~~a~~|I<br>~~a~~<br>~~a~~|Test Mode Select input pin, used to control the 1149.1 state machine.<br>~~a~~<br>~~a~~|
|TCK<br>~~a~~<br>~~a~~|I<br>~~a~~<br>~~a~~|Test Clock input pin, used to clock the 1149.1 state machine.<br>~~a~~<br>~~a~~|
|TDI<br>~~a~~|I<br>~~a~~|Test Data input pin, used to load data into the device using an 1149.1 state machine.<br>~~a~~|
|TDO|O|Output pin – Test Data output pin used to shift data out of the device using 1149.1.|
|JTAGENB|I|Optionally controls behavior of TDI, TDO, TMS, TCK. If the device is configured to use the JTAG<br>pins (TDI, TDO, TMS, TCK) as general purpose I/O, then:<br>If JTAGENB is low: TDI, TDO, TMS and TCK can function a general purpose I/O. If JTAGENB is<br>high: TDI, TDO, TMS and TCK function as JTAG pins.<br>For more details, refer toMachXO2 Programming and Configuration Usage Guide<br>(FPGA-TN-02155).|
|**Configuration**(Dual function pins used during sysCONFIG)<br>~~a~~<br>**e**e~~ee~~<br>~~a~~|||
|PROGRAMN<br>~~a~~<br>~~a~~|I<br>~~a~~<br>**e**e|Initiates configuration sequence when asserted low. During configuration, or when reserved as<br>PROGRAMN in user mode, thispin always has an activepull-up.<br>~~a~~<br>~~ee~~|
|INITN<br>~~a~~|I/O<br>**e**e|Open Drain pin. Indicates the FPGA is ready to be configured. During configuration, or when<br>reserved as INITn in user mode, thispin has an activepull-up.<br>~~ee~~<br>~~e~~|
FPGA-DS-02056-4.3
85
**MachXO2 Family Data Sheet Data Sheet**
|**Signal Name**|**I/O**|**Descriptions**|
|---|---|---|
|DONE|I/O|Open Drain pin. Indicates that the configuration sequence is complete, and the start-up<br>sequence is in progress. During configuration, or when reserved as DONE in user mode, this pin<br>has an activepull-up.|
|MCLK/CCLK|I/O|Input Configuration Clock for configuring an FPGA in Slave SPI mode. Output Configuration<br>Clock for configuringan FPGA in SPI and SPIm configuration modes.|
|SN|I|Slave SPI active low chip select input.|
|CSSPIN|I/O|Master SPI active low chip select output.|
|SI/SPISI|I/O|Slave SPI serial data input and master SPI serial data output.|
|SO/SPISO|I/O|Slave SPI serial data output and master SPI serial data input.|
|SCL|I/O|Slave I2C clock input and master I2C clock output.|
|SDA|I/O|Slave I2C data input and master I2C data output.|
© 2010-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
86
FPGA-DS-02056-4.3
**MachXO2 Family Data Sheet Data Sheet**
## **4.2. Pinout Information Summary**
## **Table 4.2. MachXO2-256/MachXO2-640/MachXO2-640U Pin Summary**
||**MachXO2-256**<br>~~a~~<br>~~pit~~<br>|<br>|<br>~~Pry~~|**MachXO2-256**<br>~~a~~<br>~~pit~~<br>|<br>|<br>~~Pry~~|**MachXO2-256**<br>~~a~~<br>~~pit~~<br>|<br>|<br>~~Pry~~|**MachXO2-256**<br>~~a~~<br>~~pit~~<br>|<br>|<br>~~Pry~~|**MachXO2-256**<br>~~a~~<br>~~pit~~<br>|<br>|<br>~~Pry~~|**MachXO2-640**<br>~~a~~<br>~~G~~<br>~~Pry||~~|**MachXO2-640**<br>~~a~~<br>~~G~~<br>~~Pry||~~|**MachXO2-640**<br>~~a~~<br>~~G~~<br>~~Pry||~~|**MachXO2-640U**<br>~~a~~<br>~~|~~|
|---|---|---|---|---|---|---|---|---|---|
||**32**<br>**QFN1**<br>~~pit~~|**48**<br>**QFN3**<br>~~pit~~|**64**<br>**ucBGA**<br>~~pit~~<br>||**100**<br>**TQFP**<br>||**132**<br>**csBGA**<br>~~Pry~~|**48**<br>**QFN3**<br>~~G~~<br>~~Pry~~|**100**<br>**TQFP**<br>~~G~~<br>~~Pry|~~|**132**<br>**csBGA**<br>~~|~~|**144 TQFP**<br>~~|~~|
|**General Purpose I/Oper Bank**<br>~~G~~<br>~~pit~~<br>|<br>|<br>~~Pry | |~~<br>~~pC~~<br>~~po~~||||||||||
|Bank 0<br>~~po~~<br>~~po~~|8|10|9|13|13|10|18|19|27|
|Bank 1<br>~~po~~<br>~~po~~<br>~~po~~|2|10|12|14|14|10|20|20|26|
|Bank 2<br>~~po~~<br>~~po~~<br>~~po~~|9|10|11|14|14|10|20|20|28|
|Bank 3<br>~~po~~<br>~~po~~<br>~~po~~|2|10|12|14|14|10|20|20|26|
|Bank 4<br>~~po~~<br>~~po~~<br>~~po~~|0|0|0|0|0|0|0|0|0|
|Bank 5<br>~~po~~<br>~~po~~|0|0|0|0|0|0|0|0|0|
|**Total General Purpose Single Ended**<br>**I/O**<br>~~po~~<br>~~a~~|21|40|44<br>~~ee~~|55<br>~~ee~~|55<br>~~ee~~|40<br>~~ee~~|78<br>~~ee~~|79<br>~~ee~~|107<br>~~ee~~|
|**Differential I/Oper Bank**||||||||||
|Bank 0<br>~~po~~|4<br>~~po~~|5<br>~~po~~|5<br>~~po~~|7<br>~~po~~|7<br>~~po~~|5<br>~~po~~|9<br>~~po~~|10<br>~~po~~|14<br>~~po~~|
|Bank 1<br>~~po~~<br>~~po~~|1<br>~~po~~|5<br>~~po~~|6<br>~~po~~|7<br>~~po~~|7<br>~~po~~|5<br>~~po~~|10<br>~~po~~|10<br>~~po~~|13<br>~~po~~|
|Bank 2<br>~~po~~<br>~~po~~<br>~~po~~|4<br>~~po~~|5<br>~~po~~|5<br>~~po~~|7<br>~~po~~|7<br>~~po~~|5<br>~~po~~|10<br>~~po~~|10<br>~~po~~|14<br>~~po~~|
|Bank 3<br>~~po~~<br>~~po~~<br>~~po~~|1|5|6|7|7|5|10|10|13|
|Bank 4<br>~~po~~<br>~~po~~<br>~~po~~|0|0|0|0|0|0|0|0|0|
|Bank 5<br>~~po~~<br>~~po~~|0|0|0|0|0|0|0|0|0|
|**Total General Purpose Differential**<br>**I/O**<br>~~po~~<br>~~a~~<br>~~pO~~|10|20|22<br>~~ee~~|28<br>~~ee~~|28<br>~~ee~~|20<br>~~ee~~|39<br>~~ee~~|40<br>~~ee~~|54<br>~~ee~~|
|**Dual Function I/O**<br>~~pO~~|22|25|27|29|29|25|29|29|33|
|**High-speed Differential I/O**<br>~~pO~~<br>~~po~~||||||||||
|Bank 0<br>~~po~~|0|0|0|0|0|0|0|0|7|
|**Gearboxes**<br>~~po~~<br>~~a~~<br>~~eeee~~||||||||||
|Number of 7:1 or 8:1 Output<br>Gearbox Available(Bank 0)<br>~~a~~|0<br>~~ee~~|0<br>~~ee~~|0<br>~~ee~~|0<br>~~ee~~|0<br>~~ee~~|0<br>~~ee~~|0<br>~~ee~~|0<br>~~ee~~|7<br>~~ee~~|
|Number of 7:1 or 8:1 Input Gearbox<br>Available(Bank 2)<br>~~a~~<br>~~a~~|0<br>~~ee~~<br>~~ee~~|0<br>~~ee~~<br>~~ee~~|0<br>~~ee~~<br>~~ee~~|0<br>~~ee~~<br>~~ee~~|0<br>~~ee~~<br>~~ee~~|0<br>~~ee~~<br>~~ee~~|0<br>~~ee~~<br>~~ee~~|0<br>~~ee~~<br>~~ee~~|7<br>~~ee~~<br>~~ee~~|
|**DQS Groups **<br>~~po~~||||||||||
|Bank 1<br>~~po~~|0|0|0|0|0|0|0|0|2|
|**VCCIO Pins**<br>~~po~~<br>~~pe~~||||||||||
|Bank 0<br>~~pe~~<br>~~po~~<br>~~po~~|2<br>~~pe~~<br>~~po~~|2<br>~~pe~~<br>~~po~~|2<br>~~pe~~<br>~~po~~|2<br>~~pe~~<br>~~po~~|2<br>~~pe~~<br>~~po~~|2<br>~~pe~~<br>~~po~~|2<br>~~pe~~<br>~~po~~|2<br>~~pe~~<br>~~po~~|3<br>~~pe~~<br>~~po~~|
|Bank 1<br>~~po~~<br>~~po~~<br>~~po~~|1<br>~~po~~|1<br>~~po~~|2<br>~~po~~|2<br>~~po~~|2<br>~~po~~|1<br>~~po~~|2<br>~~po~~|2<br>~~po~~|3<br>~~po~~|
|Bank 2<br>~~po~~<br>~~po~~<br>~~po~~|2|2|2|2|2|2|2|2|3|
|Bank 3<br>~~po~~<br>~~po~~<br>~~pO~~|1|1|2|2|2|1|2|2|3|
|Bank 4<br>~~po~~<br>~~pO~~<br>~~po~~|0|0|0|0|0|0|0|0|0|
|Bank 5<br>~~pO~~<br>~~po~~<br>~~po~~|0|0|0|0|0|0|0|0|0|
|**VCC**<br>~~po~~<br>~~po~~<br>~~po~~|2|2|2|2|2|2|2|2|4|
|**GND2**<br>~~po~~<br>~~po~~<br>~~po~~|2|1|8|8|8|1|8|10|12|
|**NC**<br>~~po~~<br>~~po~~<br>~~pO~~|0|0|1|26|58|0|3|32|8|
|**Reserved for Configuration**<br>~~po~~<br>~~pO~~<br>~~po~~|1|1|1|1|1|1|1|1|1|
|**Total Count of Bonded Pins**<br>~~pO~~<br>~~po~~|32|49|64|100|132|49|100|132|144|
1. Lattice recommends soldering the central thermal pad onto the top PCB ground for improved thermal resistance.
2. For 48 QFN package, exposed die pad is the device ground.
3. 48-pin QFN information is 'Advanced'.
© 2010-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02056-4.3
87
**MachXO2 Family Data Sheet Data Sheet**
## **Table 4.3. MachXO2-1200/MachXO2-1200U Pin Summary**
||**MachXO2-1200**<br>~~pot~~<br>~~t~~<br>~~|~~<br>~~|~~<br>~~**|**~~|**MachXO2-1200**<br>~~pot~~<br>~~t~~<br>~~|~~<br>~~|~~<br>~~**|**~~|**MachXO2-1200**<br>~~pot~~<br>~~t~~<br>~~|~~<br>~~|~~<br>~~**|**~~|**MachXO2-1200**<br>~~pot~~<br>~~t~~<br>~~|~~<br>~~|~~<br>~~**|**~~|**MachXO2-1200**<br>~~pot~~<br>~~t~~<br>~~|~~<br>~~|~~<br>~~**|**~~|**MachXO2-1200**<br>~~pot~~<br>~~t~~<br>~~|~~<br>~~|~~<br>~~**|**~~|**MachXO2-1200U**|
|---|---|---|---|---|---|---|---|
||**100**<br>**TQFP**<br>~~pot~~|**132**<br>**csBGA**<br>~~pot~~<br>~~t~~|**144**<br>**TQFP**<br>~~|~~|**25**<br>**WLCSP**<br>~~|~~|**32**<br>**QFN1**<br>~~**|**~~|**36**<br>**WLCSP**|**256 ftBGA**|
|**General Purpose I/O per Bank**<br>~~pot~~<br>~~t~~<br>~~|~~<br>~~|~~<br>~~**|**~~<br>~~Pe~~<br>~~po~~||||||||
|Bank 0<br>~~po~~|18|25|27|11|9|15|50|
|Bank 1<br>~~po~~<br>~~po~~|21<br>~~po~~|26<br>~~po~~|26<br>~~po~~|0<br>~~po~~|2<br>~~po~~|0<br>~~po~~|52<br>~~po~~|
|Bank 2<br>~~po~~|20<br>~~po~~|28<br>~~po~~|28<br>~~po~~|7<br>~~po~~|9<br>~~po~~|9<br>~~po~~|52<br>~~po~~|
|Bank 3<br>~~po~~<br>~~pO~~|20<br>~~po~~|25<br>~~po~~|26<br>~~po~~|0<br>~~po~~|2<br>~~po~~|4<br>~~po~~|16<br>~~po~~|
|Bank 4<br>~~pO~~|0|0|0|0|0|0|16|
|Bank 5<br>~~pO~~<br>~~pO~~<br>~~po~~|0<br>~~pO~~|0<br>~~pO~~|0<br>~~pO~~|0<br>~~pO~~|0<br>~~pO~~|0<br>~~pO~~|20<br>~~pO~~|
|**Total General Purpose Single Ended I/O**<br>~~po~~|79|104|107|18|22|28|206|
|**Differential I/O per Bank**<br>~~po~~<br>~~pT~~||||||||
|Bank 0<br>~~po~~<br>~~po~~|9<br>~~po~~|13<br>~~po~~|14<br>~~po~~|5<br>~~po~~|4<br>~~po~~|7<br>~~po~~|25<br>~~po~~|
|Bank 1<br>~~po~~|10|13|13|0|1|0|26|
|Bank 2<br>~~po~~<br>~~po~~|10<br>~~po~~|14<br>~~po~~|14<br>~~po~~|2<br>~~po~~|4<br>~~po~~|4<br>~~po~~|26<br>~~po~~|
|Bank 3<br>~~po~~<br>~~po~~|10<br>~~po~~<br>~~po~~|12<br>~~po~~<br>~~po~~|13<br>~~po~~<br>~~po~~|0<br>~~po~~<br>~~po~~|1<br>~~po~~<br>~~po~~|2<br>~~po~~<br>~~po~~|8<br>~~po~~<br>~~po~~|
|Bank 4<br>~~po~~<br>~~po~~|0<br>~~po~~<br>~~po~~|0<br>~~po~~<br>~~po~~|0<br>~~po~~<br>~~po~~|0<br>~~po~~<br>~~po~~|0<br>~~po~~<br>~~po~~|0<br>~~po~~<br>~~po~~|8<br>~~po~~<br>~~po~~|
|Bank 5<br>~~po~~|0<br>~~po~~|0<br>~~po~~|0<br>~~po~~|0<br>~~po~~|0<br>~~po~~|0<br>~~po~~|10<br>~~po~~|
|**Total General Purpose Differential I/O**<br>~~po~~<br>~~pO~~|39<br>~~po~~|52<br>~~po~~|54<br>~~po~~|7<br>~~po~~|10<br>~~po~~|14<br>~~po~~|103<br>~~po~~|
|**Dual Function I/O**<br>~~pO~~|31|33|33|18|22|25|33|
|**High-speed Differential I/O**<br>~~pO~~<br>~~pn~~||||||||
|Bank 0<br>~~pn~~<br>~~pO~~|4<br>~~pn~~<br>~~pO~~|7<br>~~pn~~<br>~~pO~~|7<br>~~pn~~<br>~~pO~~|0<br>~~pn~~<br>~~pO~~|0<br>~~pn~~<br>~~pO~~|3<br>~~pn~~<br>~~pO~~|14<br>~~pn~~<br>~~pO~~|
|**Gearboxes**<br>~~pO~~<br>~~Ee~~||||||||
|Number of 7:1 or 8:1 Output Gearbox<br>Available(Bank 0)|4|7|7|0|0|3|14|
|Number of 7:1 or 8:1 Input Gearbox Avail-<br>able(Bank 2)|5|7|7|0|2|2|14|
|**DQS Groups**<br>~~|~~<br>~~pO~~||||||||
|Bank 1<br>~~pO~~|1|2|2|0|0|0|2|
|**VCCIO Pins**<br>~~pO~~<br>~~CO~~||||||||
|Bank 0<br>~~GG~~|2<br>~~GG~~|3<br>~~GG~~|3<br>~~GG~~|1<br>~~GG~~|2<br>~~GG~~<br>~~CO~~|1<br>~~GG~~|4<br>~~GG~~|
|Bank 1<br>~~GG~~<br>~~po~~|2<br>~~GG~~<br>~~po~~|3<br>~~GG~~<br>~~po~~|3<br>~~GG~~<br>~~po~~|0<br>~~GG~~<br>~~po~~|1<br>~~GG~~<br>~~CO~~<br>~~po~~|0<br>~~GG~~<br>~~po~~|4<br>~~GG~~<br>~~po~~|
|Bank 2<br>~~po~~<br>~~po~~|2<br>~~po~~|3<br>~~po~~|3<br>~~po~~|1<br>~~po~~|2<br>~~po~~|1<br>~~po~~|4<br>~~po~~|
|Bank 3<br>~~po~~|3|3|3|0|1|1|1|
|Bank 4<br>~~po~~<br>~~po~~|0<br>~~po~~|0<br>~~po~~|0<br>~~po~~|0<br>~~po~~|0<br>~~po~~|0<br>~~po~~|2<br>~~po~~|
|Bank 5<br>~~po~~<br>~~po~~|0<br>~~po~~<br>~~po~~|0<br>~~po~~<br>~~po~~|0<br>~~po~~<br>~~po~~|0<br>~~po~~<br>~~po~~|0<br>~~po~~<br>~~po~~|0<br>~~po~~<br>~~po~~|1<br>~~po~~<br>~~po~~|
|**VCC**<br>~~po~~<br>~~po~~|2<br>~~po~~<br>~~po~~|4<br>~~po~~<br>~~po~~|4<br>~~po~~<br>~~po~~|2<br>~~po~~<br>~~po~~|2<br>~~po~~<br>~~po~~|2<br>~~po~~<br>~~po~~|8<br>~~po~~<br>~~po~~|
|**GND**<br>~~po~~<br>~~pO~~<br>~~po~~|8<br>~~po~~<br>~~pO~~|10<br>~~po~~<br>~~pO~~|12<br>~~po~~<br>~~pO~~|2<br>~~po~~<br>~~pO~~|2<br>~~po~~<br>~~pO~~|2<br>~~po~~<br>~~pO~~|24<br>~~po~~<br>~~pO~~|
|**NC**<br>~~po~~<br>~~pO~~|1|1|8|0|0|0|1|
|**Reserved for Configuration**<br>~~po~~<br>~~pO~~|1|1|1|1|1|1|1|
|**Total Count of Bonded Pins**<br>~~pO~~<br>~~po~~|100<br>~~po~~|132<br>~~po~~|144<br>~~po~~|25<br>~~po~~|32<br>~~po~~|36<br>~~po~~|256<br>~~po~~|
**Note:**
1. Lattice recommends soldering the central thermal pad onto the top PCB ground for improved thermal resistance.
© 2010-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
88
FPGA-DS-02056-4.3
**MachXO2 Family Data Sheet Data Sheet**
**Table 4.4. MachXO2-2000/MachXO2-2000U Pin Summary**
||**MachXO2-2000**<br>~~pi~~<br>~~|~~<br>~~|~~<br>~~|~~<br>~~**|**~~|**MachXO2-2000**<br>~~pi~~<br>~~|~~<br>~~|~~<br>~~|~~<br>~~**|**~~|**MachXO2-2000**<br>~~pi~~<br>~~|~~<br>~~|~~<br>~~|~~<br>~~**|**~~|**MachXO2-2000**<br>~~pi~~<br>~~|~~<br>~~|~~<br>~~|~~<br>~~**|**~~|**MachXO2-2000**<br>~~pi~~<br>~~|~~<br>~~|~~<br>~~|~~<br>~~**|**~~|**MachXO2-2000**<br>~~pi~~<br>~~|~~<br>~~|~~<br>~~|~~<br>~~**|**~~|**MachXO2-2000U**|
|---|---|---|---|---|---|---|---|
||**49**<br>**WLCSP**<br>~~pi~~|**100**<br>**TQFP**<br>~~pi~~<br>~~|~~|**132**<br>**csBGA**<br>~~|~~|**144**<br>**TQFP**<br>~~|~~|**256**<br>**caBGA**<br>~~**|**~~|**256**<br>**ftBGA**|**484 ftBGA**|
|**General Purpose I/O per Bank**<br>~~pi~~<br>~~|~~<br>~~|~~<br>~~|~~<br>~~**|**~~<br>~~Pe~~||||||||
|Bank 0<br>~~Pe~~<br>~~po~~<br>~~po~~|19<br>~~Pe~~<br>~~po~~|18<br>~~Pe~~<br>~~po~~|25<br>~~Pe~~<br>~~po~~|27<br>~~Pe~~<br>~~po~~|50<br>~~Pe~~<br>~~po~~|50<br>~~Pe~~<br>~~po~~|70<br>~~Pe~~<br>~~po~~|
|Bank 1<br>~~po~~|0|21|26|28|52|52|68|
|Bank 2<br>~~po~~<br>~~po~~|13<br>~~po~~|20<br>~~po~~|28<br>~~po~~|28<br>~~po~~|52<br>~~po~~|52<br>~~po~~|72<br>~~po~~|
|Bank 3<br>~~a~~<br>~~po~~|0<br>~~GG~~|6<br>~~GG~~|7<br>~~GG~~|8<br>~~GO~~|16<br>~~GO~~|16|24|
|Bank 4<br>~~po~~<br>~~po~~|0|6|8|10|16|16|16|
|Bank 5<br>~~po~~<br>~~po~~|6|8|10|10<br>~~DO~~|20<br>~~DO~~|20|28|
|**Total General Purpose Single-Ended I/O**<br>~~po~~<br>~~GF~~|38<br>~~GF~~|79<br>~~GF~~|104<br>~~GF~~|111<br>~~GF~~<br>~~DO~~|206<br>~~GF~~<br>~~DO~~|206<br>~~GF~~|278<br>~~GF~~|
|**Differential I/O per Bank**<br>~~DO~~<br>~~Ee~~<br>~~po~~||||||||
|Bank 0<br>~~po~~<br>~~a~~|7|9|13|14<br>~~GO~~|25<br>~~GO~~|25|35|
|Bank 1<br>~~po~~<br>~~GG~~<br>~~a~~|0<br>~~GG~~|10<br>~~GG~~|13<br>~~GG~~|14<br>~~GG~~<br>~~GO~~|26<br>~~GG~~<br>~~GO~~|26<br>~~GG~~|34<br>~~GG~~|
|Bank 2<br>~~GG~~<br>~~a~~<br>~~po~~|6<br>~~GG~~<br>~~GG~~|10<br>~~GG~~<br>~~GG~~|14<br>~~GG~~<br>~~GG~~|14<br>~~GG~~<br>~~GO~~<br>~~GO~~|26<br>~~GG~~<br>~~GO~~<br>~~GO~~|26<br>~~GG~~|36<br>~~GG~~|
|Bank 3<br>~~po~~<br>~~po~~|0<br>~~GG~~|3<br>~~GG~~|3<br>~~GG~~|4<br>~~GO~~|8<br>~~GO~~|8|12|
|Bank 4<br>~~po~~<br>~~po~~|0<br>~~GG~~|3<br>~~GG~~|4<br>~~GG~~|5<br>~~GO~~|8<br>~~GO~~|8|8|
|Bank 5<br>~~po~~<br>~~po~~<br>~~pO~~|3<br>~~po~~|4<br>~~po~~|5<br>~~po~~|5<br>~~po~~<br>~~GO~~|10<br>~~po~~<br>~~GO~~|10<br>~~po~~|14<br>~~po~~|
|**Total General Purpose Differential I/O**<br>~~po~~<br>~~GG~~<br>~~pO~~|16<br>~~po~~<br>~~GG~~|39<br>~~po~~<br>~~GG~~|52<br>~~po~~<br>~~GG~~|56<br>~~po~~<br>~~GG~~<br>~~GO~~|103<br>~~po~~<br>~~GG~~<br>~~GO~~|103<br>~~po~~<br>~~GG~~|139<br>~~po~~<br>~~GG~~|
|**Dual Function I/O**<br>~~GG~~<br>~~pO~~|24<br>~~GG~~|31<br>~~GG~~|33<br>~~GG~~|33<br>~~GG~~<br>~~GO~~|33<br>~~GG~~<br>~~GO~~|33<br>~~GG~~|37<br>~~GG~~|
|**High-speed Differential I/O**<br>~~GO~~<br>~~pO~~<br>~~PC~~<br>~~GG~~||||||||
|Bank 0<br>~~GG~~|5<br>~~GG~~|4<br>~~GG~~|8<br>~~GG~~|9<br>~~GG~~<br>~~GG~~|14<br>~~GG~~<br>~~GG~~|14<br>~~GG~~<br>~~GG~~|18<br>~~GG~~|
|**Gearboxes**<br>~~GG~~<br>~~Pe~~||||||||
|Number of 7:1 or 8:1 Output Gearbox<br>Available(Bank 0)<br>~~Pe~~|5<br>~~Pe~~|4<br>~~Pe~~|8<br>~~Pe~~|9<br>~~Pe~~|14<br>~~Pe~~|14<br>~~Pe~~|18<br>~~Pe~~|
|Number of 7:1 or 8:1 Input Gearbox<br>Available(Bank 2)|6|10|14|14|14|14|18|
|**DQS Groups**<br>~~pO~~||||||||
|Bank 1<br>~~pO~~|0|1|2|2|2|2|2|
|**VCCIO Pins**<br>~~pO~~<br>~~po~~||||||||
|Bank 0<br>~~po~~<br>~~po~~|2|2|3|3|4|4|10|
|Bank 1<br>~~po~~<br>~~po~~|0|2|3|3|4|4|10|
|Bank 2<br>~~po~~<br>~~po~~|1<br>~~po~~|2<br>~~po~~|3<br>~~po~~|3<br>~~po~~<br>~~OO~~|4<br>~~po~~<br>~~OO~~|4<br>~~po~~|10<br>~~po~~|
|Bank 3<br>~~po~~<br>~~GG~~<br>~~po~~|0<br>~~po~~<br>~~GG~~|1<br>~~po~~<br>~~GG~~|1<br>~~po~~<br>~~GG~~|1<br>~~po~~<br>~~GG~~<br>~~OO~~<br>~~GO~~|1<br>~~po~~<br>~~GG~~<br>~~OO~~<br>~~GO~~|1<br>~~po~~<br>~~GG~~|3<br>~~po~~<br>~~GG~~|
|Bank 4<br>~~GG~~<br>~~GG~~<br>~~po~~|0<br>~~GG~~<br>~~GG~~|1<br>~~GG~~<br>~~GG~~|1<br>~~GG~~<br>~~GG~~|1<br>~~GG~~<br>~~OO~~<br>~~GG~~<br>~~GO~~|2<br>~~GG~~<br>~~OO~~<br>~~GG~~<br>~~GO~~|2<br>~~GG~~<br>~~GG~~|4<br>~~GG~~<br>~~GG~~|
|Bank 5<br>~~po~~<br>~~po~~|1|1|1|1<br>~~GO~~|1<br>~~GO~~|1|3|
|**VCC**<br>~~po~~<br>~~po~~|2|2|4|4<br>~~GO~~|8<br>~~GO~~|8|12|
|**GND**<br>~~po~~<br>~~po~~|4<br>~~po~~|8<br>~~po~~|10<br>~~po~~|12<br>~~po~~|24<br>~~po~~|24<br>~~po~~|48<br>~~po~~|
|**NC**<br>~~po~~<br>~~po~~<br>~~po~~|0<br>~~po~~<br>~~po~~|1<br>~~po~~<br>~~po~~|1<br>~~po~~<br>~~po~~|4<br>~~po~~<br>~~po~~|1<br>~~po~~<br>~~po~~|1<br>~~po~~<br>~~po~~|105<br>~~po~~<br>~~po~~|
|**Reserved for Configuration**<br>~~po~~<br>~~po~~<br>~~po~~|1<br>~~po~~|1<br>~~po~~|1<br>~~po~~|1<br>~~po~~|v<br>~~po~~|1<br>~~po~~|1<br>~~po~~|
|**Total Count of Bonded Pins**<br>~~po~~<br>~~po~~|39|100|132|144|256|256|484|
© 2010-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02056-4.3
89
**MachXO2 Family Data Sheet Data Sheet**
**Table 4.5. MachXO2-4000 Pin Summary**
||**MachXO2-4000**<br>~~(a~~<br>~~Pt~~<br>~~|~~<br>|<br>~~|~~<br>~~ft~~<br>~~ft~~<br>~~ftft~~|**MachXO2-4000**<br>~~(a~~<br>~~Pt~~<br>~~|~~<br>|<br>~~|~~<br>~~ft~~<br>~~ft~~<br>~~ftft~~|**MachXO2-4000**<br>~~(a~~<br>~~Pt~~<br>~~|~~<br>|<br>~~|~~<br>~~ft~~<br>~~ft~~<br>~~ftft~~|**MachXO2-4000**<br>~~(a~~<br>~~Pt~~<br>~~|~~<br>|<br>~~|~~<br>~~ft~~<br>~~ft~~<br>~~ftft~~|**MachXO2-4000**<br>~~(a~~<br>~~Pt~~<br>~~|~~<br>|<br>~~|~~<br>~~ft~~<br>~~ft~~<br>~~ftft~~|**MachXO2-4000**<br>~~(a~~<br>~~Pt~~<br>~~|~~<br>|<br>~~|~~<br>~~ft~~<br>~~ft~~<br>~~ftft~~|**MachXO2-4000**<br>~~(a~~<br>~~Pt~~<br>~~|~~<br>|<br>~~|~~<br>~~ft~~<br>~~ft~~<br>~~ftft~~|**MachXO2-4000**<br>~~(a~~<br>~~Pt~~<br>~~|~~<br>|<br>~~|~~<br>~~ft~~<br>~~ft~~<br>~~ftft~~|**MachXO2-4000**<br>~~(a~~<br>~~Pt~~<br>~~|~~<br>|<br>~~|~~<br>~~ft~~<br>~~ft~~<br>~~ftft~~|
|---|---|---|---|---|---|---|---|---|---|
||**81**<br>**WLCSP**<br>~~Pt~~|**84**<br>**QFN**<br>~~Pt~~<br>~~|~~|**132**<br>**csBGA**<br>||**144**<br>**TQFP**<br>~~|~~|**184**<br>**csBGA**<br>~~ft~~|**256**<br>**caBGA**<br>~~ft~~<br>~~ft~~|**256**<br>**ftBGA**<br>~~ft~~<br>~~ft~~|**332**<br>**caBGA**<br>~~ftft~~|**484**<br>**fpBGA**<br>~~ft~~|
|**General Purpose I/O per Bank**<br>~~Pt~~<br>~~|~~<br>|<br>~~|~~<br>~~ft~~<br>~~ft~~<br>~~ft ft~~<br>~~a~~||||||||||
|Bank 0<br>~~a~~|30<br>~~a~~|26<br>~~a~~|25<br>~~a~~|28<br>~~a~~|37<br>~~a~~|50<br>~~a~~|50<br>~~a~~|68<br>~~a~~|70<br>~~a~~|
|Bank 1<br>~~a~~|0<br>~~a~~<br>~~a~~|10<br>~~a~~<br>~~a~~|26<br>~~a~~|29<br>~~a~~|37<br>~~a~~|52<br>~~a~~|52<br>~~a~~|68<br>~~a~~|68<br>~~a~~|
|Bank 2<br>~~a~~|20|22|28|29|39|52|52|70|72|
|Bank 3<br>~~eS~~|7<br>~~eS~~|0<br>~~eS~~|7<br>~~eS~~|9<br>~~eS~~|10<br>~~eS~~|16<br>~~eS~~|16<br>~~eS~~|24<br>~~eS~~|24<br>~~eS~~|
|Bank 4<br>~~eS~~|0<br>~~eS~~|9<br>~~eS~~|8<br>~~eS~~|10<br>~~eS~~|12<br>~~eS~~|16<br>~~eS~~|16<br>~~eS~~|16<br>~~eS~~|16<br>~~eS~~|
|Bank 5<br>~~a~~<br>~~re~~|7<br>~~a~~<br>~~eee~~|0<br>~~a~~<br>~~eee~~|10<br>~~eee~~|10<br>~~eee~~|15<br>~~eee~~|20<br>~~eee~~|20<br>~~eee~~|28<br>~~eee~~|28<br>~~eee~~|
|**Total General Purpose Single Ended**<br>**I/O**<br>~~re~~|64<br>~~eee~~|67<br>~~eee~~|104<br>~~eee~~|115<br>~~eee~~|150<br>~~eee~~|206<br>~~eee~~|206<br>~~eee~~|274<br>~~eee~~|278<br>~~eee~~|
|**Differential I/O per Bank**<br>~~re eee eee~~<br>~~a~~||||||||||
|Bank 0<br>~~a~~|15<br>~~a~~|12<br>~~a~~|13<br>~~a~~|14<br>~~a~~|18<br>~~a~~|25<br>~~a~~|25<br>~~a~~|34<br>~~a~~|35<br>~~a~~|
|Bank 1<br>~~a~~|0<br>~~a~~|4<br>~~a~~|13<br>~~a~~|14<br>~~a~~|18<br>~~a~~|26<br>~~a~~|26<br>~~a~~|34<br>~~a~~|34<br>~~a~~|
|Bank 2<br>~~a~~<br>~~a~~|10<br>~~a~~<br>~~a~~|11<br>~~a~~<br>~~a~~|14<br>~~a~~<br>~~a~~|14<br>~~a~~<br>~~a~~|19<br>~~a~~<br>~~a~~|26<br>~~a~~<br>~~a~~|26<br>~~a~~<br>~~a~~|35<br>~~a~~<br>~~a~~|36<br>~~a~~<br>~~a~~|
|Bank 3<br>~~a~~<br>~~a~~|3<br>~~a~~<br>~~a~~|0<br>~~a~~<br>~~a~~|3<br>~~a~~<br>~~a~~|4<br>~~a~~<br>~~a~~|4<br>~~a~~<br>~~a~~|8<br>~~a~~<br>~~a~~|8<br>~~a~~<br>~~a~~|12<br>~~a~~<br>~~a~~|12<br>~~a~~<br>~~a~~|
|Bank 4<br>~~a~~|0<br>~~a~~<br>~~a~~|4<br>~~a~~<br>~~a~~|4<br>~~a~~<br>~~a~~|5<br>~~a~~<br>~~a~~|6<br>~~a~~<br>~~a~~|8<br>~~a~~<br>~~a~~|8<br>~~a~~<br>~~a~~|8<br>~~a~~<br>~~a~~|8<br>~~a~~<br>~~a~~|
|Bank 5<br>~~a~~|3<br>~~a~~|0<br>~~a~~|5<br>~~a~~|5<br>~~a~~|7<br>~~a~~|10<br>~~a~~|10<br>~~a~~|14<br>~~a~~|14<br>~~a~~|
|**Total General Purpose Differential**<br>**I/O **<br>~~a~~<br>~~Ds~~|31<br>~~a~~<br>~~Ds~~|31<br>~~a~~<br>~~Ds~~|52<br>~~a~~<br>~~Ds~~|56<br>~~a~~<br>~~Ds~~|72<br>~~a~~<br>~~Ds~~|103<br>~~a~~<br>~~Ds~~|103<br>~~a~~<br>~~Ds~~|137<br>~~a~~<br>~~Ds~~|139<br>~~a~~<br>~~Ds~~|
|**Dual Function I/O**<br>~~a~~|25<br>~~a~~|28<br>~~a~~|37<br>~~a~~|37<br>~~a~~|37<br>~~a~~|37<br>~~a~~|37<br>~~a~~|37<br>~~a~~|37<br>~~a~~|
|**High-speed Differential I/O**<br>~~a~~<br>~~a~~||||||||||
|Bank 0<br>~~a~~<br>~~a~~|10<br>~~a~~<br>~~a~~|8<br>~~a~~<br>~~a~~|8<br>~~a~~<br>~~a~~|9<br>~~a~~<br>~~a~~|8<br>~~a~~<br>~~a~~|18<br>~~a~~<br>~~a~~|18<br>~~a~~<br>~~a~~|18<br>~~a~~<br>~~a~~|18<br>~~a~~<br>~~a~~|
|**Gearboxes**<br>~~a~~<br>~~eeee ee~~||||||||||
|Number of 7:1 or 8:1 Output<br>Gearbox Available(Bank 0)<br>~~ee~~|10<br>~~ee~~<br>~~ee~~|8<br>~~ee~~<br>~~ee~~|8<br>~~ee~~<br>~~ee~~|9<br>~~ee ee~~<br>~~ee ee~~|9<br>~~ee~~<br>~~ee~~|18<br>~~ee~~<br>~~ee~~|18<br>~~ee~~<br>~~ee~~|18<br>~~ee~~<br>~~ee~~|18<br>~~ee~~<br>~~ee~~|
|Number of 7:1 or 8:1 Input Gearbox<br>Available(Bank 2)<br>~~ee ~~<br>~~ee~~|10<br> ~~ee~~<br>~~ee~~<br>~~ee~~|11<br>~~ee~~<br>~~ee~~<br>~~ee~~|14<br>~~ee~~<br>~~ee~~<br>~~ee~~|14<br>~~ee ee~~<br>~~ee~~<br>~~ee ee~~|12<br>~~ee~~<br>~~ee~~<br>~~ee~~|18<br>~~ee~~<br>~~ee~~<br>~~ee~~|18<br>~~ee~~<br>~~ee~~<br>~~ee~~|18<br>~~ee~~<br>~~ee~~<br>~~ee~~|18<br>~~ee~~<br>~~ee~~<br>~~ee~~|
|**DQS Groups**<br>~~ee ee ee~~<br>~~a~~<br>~~OO~~||||||||||
|Bank 1<br>~~OO~~|0|1|2|2|2|2|2|2|2|
|**VCCIO Pins**<br>~~OO~~<br>~~a~~||||||||||
|Bank 0<br>~~a~~<br>~~a~~|3<br>~~a~~<br>~~a~~|3<br>~~a~~<br>~~a~~|3<br>~~a~~<br>~~a~~|3<br>~~a~~<br>~~a~~|3<br>~~a~~<br>~~a~~|4<br>~~a~~<br>~~a~~|4<br>~~a~~<br>~~a~~|4<br>~~a~~<br>~~a~~|10<br>~~a~~<br>~~a~~|
|Bank 1<br>~~a~~<br>~~a~~|0<br>~~a~~<br>~~a~~<br>~~a~~|1<br>~~a~~<br>~~a~~<br>~~a~~|3<br>~~a~~<br>~~a~~|3<br>~~a~~<br>~~a~~|3<br>~~a~~<br>~~a~~|4<br>~~a~~<br>~~a~~|4<br>~~a~~<br>~~a~~|4<br>~~a~~<br>~~a~~|10<br>~~a~~<br>~~a~~|
|Bank 2<br>~~a~~|2|2|3|3|3|4|4|4|10|
|Bank 3<br>~~a~~|1|0|1|1|1|1|1|2|3|
|Bank 4<br>~~a~~|0<br>~~a~~|1<br>~~a~~|1|1|1|2|2|1|4|
|Bank 5<br>~~a~~<br>~~a~~|1<br>~~a~~<br>~~a~~|0<br>~~a~~<br>~~a~~|1<br>~~a~~|1<br>~~a~~|1<br>~~a~~|1<br>~~a~~|1<br>~~a~~|2<br>~~a~~|3<br>~~a~~|
|**VCC**<br>~~a~~<br>~~a~~|4<br>~~a~~<br>~~a~~<br>~~a~~|4<br>~~a~~<br>~~a~~<br>~~a~~|4<br>~~a~~<br>~~a~~<br>~~a~~|4<br>~~a~~<br>~~a~~<br>~~a~~|4<br>~~a~~<br>~~a~~<br>~~a~~|8<br>~~a~~<br>~~a~~<br>~~a~~|8<br>~~a~~<br>~~a~~|8<br>~~a~~<br>~~a~~|12<br>~~a~~<br>~~a~~|
|**GND**<br>~~a~~|6<br>~~a~~<br>~~a~~|4<br>~~a~~<br>~~a~~|10<br>~~a~~<br>~~a~~|12<br>~~a~~<br>~~a~~|16<br>~~a~~<br>~~a~~|24<br>~~a~~<br>~~a~~|24<br>~~a~~|27<br>~~a~~|48<br>~~a~~|
|**NC**<br>~~a~~|0<br>~~a~~<br>~~a~~|1<br>~~a~~<br>~~a~~|1<br>~~a~~|1<br>~~a~~|1<br>~~a~~|1<br>~~a~~|1|5|105|
|**Reserved for configuration**<br>~~a~~<br>~~a~~|1<br>~~a~~<br>~~a~~|1<br>~~a~~<br>~~a~~|1|1|1|1|1|1|1|
|**Total Count of Bonded Pins**<br>~~a~~<br>~~a~~|81<br>~~a~~<br>~~a~~<br>~~a~~|84<br>~~a~~<br>~~a~~<br>~~a~~|132|144|184|256|256|332|484|
© 2010-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
90
FPGA-DS-02056-4.3
**MachXO2 Family Data Sheet Data Sheet**
## **Table 4.6. MachXO2-7000 Pin Summary**
||**MachXO2-7000**<br>~~pT~~|**MachXO2-7000**<br>~~pT~~|**MachXO2-7000**<br>~~pT~~|**MachXO2-7000**<br>~~pT~~|**MachXO2-7000**<br>~~pT~~|**MachXO2-7000**<br>~~pT~~|
|---|---|---|---|---|---|---|
||**144 TQFP**<br>~~es~~|**256 caBGA**<br>~~es~~|**256 ftBGA**<br>~~es~~|**332 caBGA**<br>~~es~~|**400 caBGA**<br>~~es~~|**484 fpBGA**<br>~~es~~|
|**General Purpose I/O per Bank**<br>~~PC~~<br>~~po~~|||||||
|Bank 0<br>~~po~~|28|50|50|68|83|82|
|Bank 1<br>~~po~~<br>~~GG~~|29<br>~~GG~~|52<br>~~GG~~|52<br>~~GG~~|70<br>~~GG~~|84<br>~~GG~~|84<br>~~GG~~|
|Bank 2<br>~~GG~~|29<br>~~GG~~|52<br>~~GG~~|52<br>~~GG~~|70<br>~~GG~~|84<br>~~GG~~|84<br>~~GG~~|
|Bank 3<br>~~GG~~<br>~~po~~|9<br>~~GG~~|16<br>~~GG~~|16<br>~~GG~~|24<br>~~GG~~|28<br>~~GG~~|28<br>~~GG~~|
|Bank 4<br>~~po~~|10|16|16|16|24|24|
|Bank 5<br>~~po~~<br>~~GG~~<br>~~pO~~|10<br>~~GG~~|20<br>~~GG~~|20<br>~~GG~~|30<br>~~GG~~|32<br>~~GG~~|32<br>~~GG~~|
|**Total General Purpose Single Ended I/O**<br>~~pO~~|115|206|206|278|335|334|
|**Differential I/O per Bank**<br>~~pO~~<br>~~Pe~~|||||||
|Bank 0<br>~~po~~|14<br>~~po~~|25<br>~~po~~|25<br>~~po~~|34<br>~~po~~|42<br>~~po~~|41<br>~~po~~|
|Bank 1<br>~~po~~|14<br>~~po~~|26<br>~~po~~|26<br>~~po~~|35<br>~~po~~|42<br>~~po~~|42<br>~~po~~|
|Bank 2<br>~~po~~<br>~~GG~~|14<br>~~po~~<br>~~GG~~|26<br>~~po~~<br>~~GG~~|26<br>~~po~~<br>~~GG~~|35<br>~~po~~<br>~~GG~~|42<br>~~po~~<br>~~GG~~|42<br>~~po~~<br>~~GG~~|
|Bank 3<br>~~GG~~<br>~~GG~~|4<br>~~GG~~<br>~~GG~~|8<br>~~GG~~<br>~~GG~~|8<br>~~GG~~<br>~~GG~~|12<br>~~GG~~<br>~~GG~~|14<br>~~GG~~<br>~~GG~~|14<br>~~GG~~<br>~~GG~~|
|Bank 4<br>~~GG~~<br>~~GG~~<br>~~po~~|5<br>~~GG~~<br>~~GG~~|8<br>~~GG~~<br>~~GG~~|8<br>~~GG~~<br>~~GG~~|8<br>~~GG~~<br>~~GG~~|12<br>~~GG~~<br>~~GG~~|12<br>~~GG~~<br>~~GG~~|
|Bank 5<br>~~po~~|5|10|10|15|16|16|
|**Total General Purpose Differential I/O**<br>~~po~~<br>~~po~~|56<br>~~po~~|103<br>~~po~~|103<br>~~po~~|139<br>~~po~~|168<br>~~po~~|167<br>~~po~~|
|**Dual Function I/O**<br>~~po~~<br>~~GG~~|37<br>~~po~~<br>~~GG~~|37<br>~~po~~<br>~~GG~~|37<br>~~po~~<br>~~GG~~|37<br>~~po~~<br>~~GG~~|37<br>~~po~~<br>~~GG~~|37<br>~~po~~<br>~~GG~~|
|**High-speed Differential I/O**<br>~~GG~~<br>~~po~~|||||||
|Bank 0<br>~~po~~|9|20|20|21|21|21|
|**Gearboxes**<br>~~po~~<br>~~Pe~~|||||||
|Number of 7:1 or 8:1 Output Gearbox<br>Available(Bank 0)|9|20|20|21|21|21|
|Number of 7:1 or 8:1 Input Gearbox<br>Available(Bank 2)|14|20|20|21|21|21|
|**DQS Groups**<br>~~Pe~~|||||||
|Bank 1<br>~~po~~|2<br>~~po~~|2<br>~~po~~|2<br>~~po~~|2<br>~~po~~|2<br>~~po~~|2<br>~~po~~|
|**VCCIO Pins**<br>~~po~~|||||||
|Bank 0<br>~~pO~~|3<br>~~pO~~|4<br>~~pO~~|4<br>~~pO~~|4<br>~~pO~~|5<br>~~pO~~|10<br>~~pO~~|
|Bank 1<br>~~po~~|3<br>~~po~~|4<br>~~po~~|4<br>~~po~~|4<br>~~po~~|5<br>~~po~~|10<br>~~po~~|
|Bank 2<br>~~po~~|3<br>~~po~~|4<br>~~po~~|4<br>~~po~~|4<br>~~po~~|5<br>~~po~~|10<br>~~po~~|
|Bank 3<br>~~po~~|1<br>~~po~~|1<br>~~po~~|1<br>~~po~~|2<br>~~po~~|2<br>~~po~~|3<br>~~po~~|
|Bank 4<br>~~po~~<br>~~GG~~|1<br>~~po~~<br>~~GG~~|2<br>~~po~~<br>~~GG~~|2<br>~~po~~<br>~~GG~~|1<br>~~po~~<br>~~GG~~|2<br>~~po~~<br>~~GG~~|4<br>~~po~~<br>~~GG~~|
|Bank 5<br>~~GG~~<br>~~GG~~<br>~~po~~|1<br>~~GG~~<br>~~GG~~|1<br>~~GG~~<br>~~GG~~|1<br>~~GG~~<br>~~GG~~|2<br>~~GG~~<br>~~GG~~|2<br>~~GG~~<br>~~GG~~|3<br>~~GG~~<br>~~GG~~|
|**VCC**<br>~~GG~~<br>~~po~~<br>~~pO~~|4<br>~~GG~~|8<br>~~GG~~|8<br>~~GG~~|8<br>~~GG~~|10<br>~~GG~~|12<br>~~GG~~|
|**GND**<br>~~po~~<br>~~pO~~|12|24|24|27|33|48|
|**NC**<br>~~pO~~<br>~~po~~|1<br>~~po~~|1<br>~~po~~|1<br>~~po~~|1<br>~~po~~|0<br>~~po~~|49<br>~~po~~|
|**Reserved for Configuration**<br>~~po~~<br>~~GG~~<br>~~po~~|1<br>~~po~~<br>~~GG~~|1<br>~~po~~<br>~~GG~~|1<br>~~po~~<br>~~GG~~|1<br>~~po~~<br>~~GG~~|1<br>~~po~~<br>~~GG~~|1<br>~~po~~<br>~~GG~~|
|**Total Count of Bonded Pins**<br>~~GG~~<br>~~po~~|144<br>~~GG~~|256<br>~~GG~~|256<br>~~GG~~|332<br>~~GG~~|400<br>~~GG~~|484<br>~~GG~~|
© 2010-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02056-4.3
91
**MachXO2 Family Data Sheet Data Sheet**
## **4.3. For Further Information**
For further information regarding logic signal connections for various packages, refer to the MachXO2 Device Pinout Files.
## **4.4. Thermal Management**
Thermal management is recommended as part of any sound FPGA design methodology. To assess the thermal characteristics of a system, Lattice specifies a maximum allowable junction temperature in all device data sheets. Users must complete a thermal analysis of their specific design to ensure that the device and package do not exceed the junction temperature limits. Refer to the Thermal Management document to find the device/package specific thermal values.
## **4.4.1. For Further Information**
For further information regarding Thermal Management, refer to the following:
- Thermal Management (FPGA-TN-02044)
- Power Estimation and Management for MachXO2 Devices (TN1198)
- The Power Calculator tool is included within the Lattice design tools
© 2010-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
92
FPGA-DS-02056-4.3
**MachXO2 Family Data Sheet Data Sheet**
## **5. Ordering Information**
## **5.1. MachXO2 Part Number Description**
LXMXO2 – XXXX X X X – X XXXXXX X XX XX
**Device Family** LCMXO2 = MachXO2 FPGA COM/IND LAMXO2 = MachXO2 FPGA AUTO
**Logic Capacity** 256 = 256 LUTs 640 = 640 LUTs 1200 = 1280 LUTs 2000 = 2112 LUTs 4000 = 4320 LUTs 7000 = 6864 LUTs **I/O Count** Blank = Standard Device U = Ultra High I/O Device
## **Power/Performance**
Z = Low Power H = High Performance
## **Supply Voltage**
C = 2.5 V / 3.3 V E = 1.2 V
## **Speed**
1 = Slowest 2 Low Power 3 = Fastest 4 = Slowest 5 High Performance 6 = Fastest
* 48-pin QFN information is 'Advanced'.
## **Device Status**
Blank = Production Device ES = Engineering Sample R1 = Production Release 1 Device 1K = WLCSP Package, 1,000 parts per reel **Shipping Method** Blank = Trays TR = Tape and Reel **Grade** C = Commercial E = Automotive I = Industrial
**Package** UWG25 = 25-Ball Halogen-Free WLCSP (0.4 mm Pitch) SG32 = 32-Pin Halogen-Free QFN (0.5 mm Pitch) UWG36 = 36-Ball Halogen-Free WLSCP (0.4 mm Pitch) SG48 = 48-Pin Halogen-Free QFN (0.5 mm Pitch) UWG49 = 49-ball Halogen-Free WLCSP (0.4 mm Pitch) UMG64 = 64-Ball Halogen-Free ucBGA (0.4 mm Pitch) UWG81 = 81-Ball Halogen-Free WLCSP (0.4 mm Pitch) QN84 = 84-Pin Halogen-Free QFN (0.5 mm Pitch) TG100 = 100-Pin Halogen-Free TQFP TG144 = 144-Pin Halogen-Free TQFP MG132 = 132-Ball Halogen-Free csBGA (0.5 mm Pitch) MG184 = 184-Ball Halogen-Free csBGA (0.5 mm Pitch) BG256 = 256-Ball Halogen-Free caBGA (0.8 mm Pitch) FTG256 = 256-Ball Halogen-Free ftBGA (1.0 mm Pitch) BG332 = 332-Ball Halogen-Free caBGA (0.8 mm Pitch) FG484 = 484-Ball Halogen-Free fpBGA (1.0 mm Pitch)
**Figure 5.1. MachXO2 Part Number Description**
© 2010-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02056-4.3
93
**MachXO2 Family Data Sheet Data Sheet**
## **5.2. Ordering Information**
- For the following new devices,
- LAMXO2-256HC-5TG100E, LAMXO2-256HC-5MG132E, LAMXO2-640HC-5TG100E, and LAMXO2-640HC-5MG132E, the top-side marking below is used:
**==> picture [100 x 68] intentionally omitted <==**
**----- Start of picture text -----**<br>
MachXO2TM<br>Lot ID<br>Barcode COO<br>**----- End of picture text -----**<br>
- For other MachXO2 devices, the top-side markings below are used:
**==> picture [238 x 107] intentionally omitted <==**
**----- Start of picture text -----**<br>
LCMXO2<br>256ZE<br>LCMXO2-1200ZE<br>1UG64C<br>1TG100C<br>Datacode<br>Datacode<br>— _<br>**----- End of picture text -----**<br>
**Notes:**
1. Markings are abbreviated for small packages.
2. See PCN 05B-12 for information regarding a change to the top-side mark logo.
## **5.2.1. Ultra Low Power Commercial Grade Devices, Halogen Free (RoHS) Packaging**
**Table 5.1. Ultra Low Power Commercial Grade Devices, Halogen Free (RoHS) Packaging**
|**Part Number**<br>~~pO~~<br>~~po~~|**LUTs**|**Supply Voltage**|**Speed**|**Package**|**Leads**|**Temp.**|
|---|---|---|---|---|---|---|
|LCMXO2-256ZE-1SG32C<br>~~pO~~<br>~~po~~<br>~~po~~|256|1.2 V|–1|Halogen-Free QFN|32|COM|
|LCMXO2-256ZE-2SG32C<br>~~po~~<br>~~po~~<br>~~po~~|256|1.2 V|–2|Halogen-Free QFN|32|COM|
|LCMXO2-256ZE-3SG32C<br>~~po~~<br>~~po~~<br>~~po~~|256|1.2 V|–3|Halogen-Free QFN|32|COM|
|LCMXO2-256ZE-1UMG64C<br>~~po~~<br>~~po~~<br>~~po~~|256|1.2 V|–1|Halogen-Free ucBGA|64|COM|
|LCMXO2-256ZE-2UMG64C<br>~~po~~<br>~~po~~|256|1.2 V|–2|Halogen-Free ucBGA|64|COM|
|LCMXO2-256ZE-3UMG64C<br>~~po~~<br>~~pO~~<br>~~pO~~|256<br>~~pO~~|1.2 V<br>~~pO~~|–3<br>~~pO~~|Halogen-Free ucBGA<br>~~pO~~|64<br>~~pO~~|COM<br>~~pO~~|
|LCMXO2-256ZE-1TG100C<br>~~pO~~|256|1.2 V|–1|Halogen-Free TQFP|100|COM|
|LCMXO2-256ZE-2TG100C<br>~~pO~~<br>~~pf~~<br>~~po~~|256<br>~~pf~~|1.2 V<br>~~pf~~|–2<br>~~pf~~|Halogen-Free TQFP<br>~~pf~~|100<br>~~pf~~|COM<br>~~pf~~|
|LCMXO2-256ZE-3TG100C<br>~~pf~~<br>~~po~~<br>~~po~~|256<br>~~pf~~|1.2 V<br>~~pf~~|–3<br>~~pf~~|Halogen-Free TQFP<br>~~pf~~|100<br>~~pf~~|COM<br>~~pf~~|
|LCMXO2-256ZE-1MG132C<br>~~po~~<br>~~po~~<br>~~eG~~|256<br>~~eG~~|1.2 V<br>~~GG~~|–1<br>~~GG~~|Halogen-Free csBGA<br>~~GG~~|132|COM|
|LCMXO2-256ZE-2MG132C<br>~~po~~<br>~~eG~~<br>~~pO~~|256<br>~~eG~~|1.2 V<br>~~GG~~|–2<br>~~GG~~|Halogen-Free csBGA<br>~~GG~~|132|COM|
|LCMXO2-256ZE-3MG132C<br>~~eG~~<br>~~pO~~<br>~~pO~~|256<br>~~eG~~|1.2 V<br>~~GG~~|–3<br>~~GG~~|Halogen-Free csBGA<br>~~GG~~|132|COM|
|LCMXO2-640ZE-1TG100C<br>~~pO~~<br>~~pO~~|640|1.2 V|–1|Halogen-Free TQFP|100|COM|
|LCMXO2-640ZE-2TG100C<br>~~pO~~<br>~~pf~~<br>~~po~~|640<br>~~pf~~|1.2 V<br>~~pf~~|–2<br>~~pf~~|Halogen-Free TQFP<br>~~pf~~|100<br>~~pf~~|COM<br>~~pf~~|
|LCMXO2-640ZE-3TG100C<br>~~pf~~<br>~~po~~|640<br>~~pf~~|1.2 V<br>~~pf~~|–3<br>~~pf~~|Halogen-Free TQFP<br>~~pf~~|100<br>~~pf~~|COM<br>~~pf~~|
|LCMXO2-640ZE-1MG132C<br>~~po~~<br>~~po~~|640<br>~~po~~|1.2 V<br>~~po~~|–1<br>~~po~~|Halogen-Free csBGA<br>~~po~~|132<br>~~po~~|COM<br>~~po~~|
© 2010-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
94
FPGA-DS-02056-4.3
**MachXO2 Family Data Sheet Data Sheet**
|**Part Number**<br>~~pO~~<br>~~eG~~|**LUTs**<br>~~eG~~|**Supply Voltage**<br>~~GG~~|**Speed**<br>~~GG~~|**Package**<br>~~GG~~|**Leads**|**Temp.**|
|---|---|---|---|---|---|---|
|LCMXO2-640ZE-2MG132C<br>~~pO~~<br>~~eG~~<br>~~pO~~|640<br>~~eG~~|1.2 V<br>~~GG~~|–2<br>~~GG~~|Halogen-Free csBGA<br>~~GG~~|132|COM|
|LCMXO2-640ZE-3MG132C<br>~~eG~~<br>~~pO~~<br>~~pO~~|640<br>~~eG~~|1.2 V<br>~~GG~~|–3<br>~~GG~~|Halogen-Free csBGA<br>~~GG~~|132|COM|
|LCMXO2-1200ZE-1SG32C<br>~~pO~~<br>~~pO~~<br>~~po~~|1280|1.2 V|–1|Halogen-Free QFN|32|COM|
|LCMXO2-1200ZE-2SG32C<br>~~pO~~<br>~~po~~<br>~~po~~|1280|1.2 V|–2|Halogen-Free QFN|32|COM|
|LCMXO2-1200ZE-3SG32C<br>~~po~~<br>~~po~~<br>~~eG~~|1280<br>~~eG~~|1.2 V<br>~~GG~~|–3<br>~~GG~~|Halogen-Free QFN<br>~~GG~~|32|COM|
|LCMXO2-1200ZE-1TG100C<br>~~po~~<br>~~eG~~<br>~~pO~~|1280<br>~~eG~~|1.2 V<br>~~GG~~|–1<br>~~GG~~|Halogen-Free TQFP<br>~~GG~~|100|COM|
|LCMXO2-1200ZE-2TG100C<br>~~eG~~<br>~~pO~~<br>~~pO~~|1280<br>~~eG~~|1.2 V<br>~~GG~~|–2<br>~~GG~~|Halogen-Free TQFP<br>~~GG~~|100|COM|
|LCMXO2-1200ZE-3TG100C<br>~~pO~~<br>~~pO~~<br>~~po~~|1280|1.2 V|–3|Halogen-Free TQFP|100|COM|
|LCMXO2-1200ZE-1MG132C<br>~~pO~~<br>~~po~~<br>~~po~~|1280|1.2 V|–1|Halogen-Free csBGA|132|COM|
|LCMXO2-1200ZE-2MG132C<br>~~po~~<br>~~po~~<br>~~eG~~|1280<br>~~eG~~|1.2 V<br>~~GG~~|–2<br>~~GG~~|Halogen-Free csBGA<br>~~GG~~|132|COM|
|LCMXO2-1200ZE-3MG132C<br>~~po~~<br>~~eG~~<br>~~eG~~|1280<br>~~eG~~<br>~~eG~~|1.2 V<br>~~GG~~<br>~~GG~~|–3<br>~~GG~~<br>~~GG~~|Halogen-Free csBGA<br>~~GG~~<br>~~GG~~|132|COM|
|LCMXO2-1200ZE-1TG144C<br>~~eG~~<br>~~eG~~<br>~~po~~|1280<br>~~eG~~<br>~~eG~~|1.2 V<br>~~GG~~<br>~~GG~~|–1<br>~~GG~~<br>~~GG~~|Halogen-Free TQFP<br>~~GG~~<br>~~GG~~|144|COM|
|LCMXO2-1200ZE-2TG144C<br>~~eG~~<br>~~po~~<br>~~eG~~|1280<br>~~eG~~<br>~~eG~~|1.2 V<br>~~GG~~<br>~~GG~~|–2<br>~~GG~~<br>~~GG~~|Halogen-Free TQFP<br>~~GG~~<br>~~GG~~|144|COM|
|LCMXO2-1200ZE-3TG144C<br>~~po~~<br>~~eG~~<br>~~po~~|1280<br>~~eG~~|1.2 V<br>~~GG~~|–3<br>~~GG~~|Halogen-Free TQFP<br>~~GG~~|144|COM|
|LCMXO2-2000ZE-1TG100C<br>~~eG~~<br>~~po~~<br>~~po~~|2112<br>~~eG~~|1.2 V<br>~~GG~~|–1<br>~~GG~~|Halogen-Free TQFP<br>~~GG~~|100|COM|
|LCMXO2-2000ZE-2TG100C<br>~~po~~<br>~~po~~<br>~~po~~|2112|1.2 V|–2|Halogen-Free TQFP|100|COM|
|LCMXO2-2000ZE-3TG100C<br>~~po~~<br>~~po~~<br>~~eG~~|2112<br>~~eG~~|1.2 V<br>~~GG~~|–3<br>~~GG~~|Halogen-Free TQFP<br>~~GG~~|100|COM|
|LCMXO2-2000ZE-1MG132C<br>~~po~~<br>~~eG~~<br>~~po~~|2112<br>~~eG~~|1.2 V<br>~~GG~~|–1<br>~~GG~~|Halogen-Free csBGA<br>~~GG~~|132|COM|
|LCMXO2-2000ZE-2MG132C<br>~~eG~~<br>~~po~~<br>~~po~~|2112<br>~~eG~~|1.2 V<br>~~GG~~|–2<br>~~GG~~|Halogen-Free csBGA<br>~~GG~~|132|COM|
|LCMXO2-2000ZE-3MG132C<br>~~po~~<br>~~po~~<br>~~po~~|2112|1.2 V|–3|Halogen-Free csBGA|132|COM|
|LCMXO2-2000ZE-1TG144C<br>~~po~~<br>~~po~~<br>~~po~~|2112|1.2 V|–1|Halogen-Free TQFP|144|COM|
|LCMXO2-2000ZE-2TG144C<br>~~po~~<br>~~po~~<br>~~po~~|2112|1.2 V|–2|Halogen-Free TQFP|144|COM|
|LCMXO2-2000ZE-3TG144C<br>~~po~~<br>~~po~~<br>~~po~~|2112|1.2 V|–3|Halogen-Free TQFP|144|COM|
|LCMXO2-2000ZE-1BG256C<br>~~po~~<br>~~po~~|2112|1.2 V|–1|Halogen-Free caBGA|256|COM|
|LCMXO2-2000ZE-2BG256C<br>~~po~~<br>~~pO~~|2112<br>~~pO~~|1.2 V<br>~~pO~~|–2<br>~~pO~~|Halogen-Free caBGA<br>~~pO~~|256<br>~~pO~~|COM<br>~~pO~~|
|LCMXO2-2000ZE-3BG256C<br>~~pO~~|2112<br>~~pO~~|1.2 V<br>~~pO~~|–3<br>~~pO~~|Halogen-Free caBGA<br>~~pO~~|256<br>~~pO~~|COM<br>~~pO~~|
|LCMXO2-2000ZE-1FTG256C<br>~~pf~~|2112<br>~~pf~~|1.2 V<br>~~pf~~|–1<br>~~pf~~|Halogen-Free ftBGA<br>~~pf~~|256<br>~~pf~~|COM<br>~~pf~~|
|LCMXO2-2000ZE-2FTG256C<br>~~pf~~<br>~~Ge~~|2112<br>~~pf~~<br>~~Ge~~|1.2 V<br>~~pf~~<br>~~GG~~|–2<br>~~pf~~<br>~~GG~~|Halogen-Free ftBGA<br>~~pf~~<br>~~GG~~|256<br>~~pf~~|COM<br>~~pf~~|
|LCMXO2-2000ZE-3FTG256C<br>~~Ge~~<br>~~Ge~~|2112<br>~~Ge~~<br>~~Ge~~|1.2 V<br>~~GG~~<br>~~GG~~|–3<br>~~GG~~<br>~~GG~~|Halogen-Free ftBGA<br>~~GG~~<br>~~GG~~|256|COM|
|LCMXO2-4000ZE-1QN84C<br>~~pO~~|4320<br>~~pO~~|1.2 V<br>~~pO~~|–1<br>~~pO~~|Halogen-Free QFN<br>~~pO~~|84<br>~~pO~~|COM<br>~~pO~~|
|LCMXO2-4000ZE-2QN84C<br>~~pf~~|4320<br>~~pf~~|1.2 V<br>~~pf~~|–2<br>~~pf~~|Halogen-Free QFN<br>~~pf~~|84<br>~~pf~~|COM<br>~~pf~~|
|LCMXO2-4000ZE-3QN84C<br>~~pf~~<br>~~Ge~~|4320<br>~~pf~~<br>~~Ge~~|1.2 V<br>~~pf~~<br>~~GG~~|–3<br>~~pf~~<br>~~GG~~|Halogen-Free QFN<br>~~pf~~<br>~~GG~~|84<br>~~pf~~|COM<br>~~pf~~|
|LCMXO2-4000ZE-1MG132C<br>~~Ge~~<br>~~Ge~~|4320<br>~~Ge~~<br>~~Ge~~|1.2 V<br>~~GG~~<br>~~GG~~|–1<br>~~GG~~<br>~~GG~~|Halogen-Free csBGA<br>~~GG~~<br>~~GG~~|132|COM|
|LCMXO2-4000ZE-2MG132C<br>~~Ge~~<br>~~Ge~~|4320<br>~~Ge~~<br>~~Ge~~|1.2 V<br>~~GG~~<br>~~GG~~|–2<br>~~GG~~<br>~~GG~~|Halogen-Free csBGA<br>~~GG~~<br>~~GG~~|132|COM|
|LCMXO2-4000ZE-3MG132C<br>~~pO~~|4320<br>~~pO~~|1.2 V<br>~~pO~~|–3<br>~~pO~~|Halogen-Free csBGA<br>~~pO~~|132<br>~~pO~~|COM<br>~~pO~~|
|LCMXO2-4000ZE-1TG144C<br>~~pf~~<br>~~po~~|4320<br>~~pf~~|1.2 V<br>~~pf~~|–1<br>~~pf~~|Halogen-Free TQFP<br>~~pf~~|144<br>~~pf~~|COM<br>~~pf~~|
|LCMXO2-4000ZE-2TG144C<br>~~pf~~<br>~~po~~<br>~~po~~|4320<br>~~pf~~|1.2 V<br>~~pf~~|–2<br>~~pf~~|Halogen-Free TQFP<br>~~pf~~|144<br>~~pf~~|COM<br>~~pf~~|
|LCMXO2-4000ZE-3TG144C<br>~~po~~<br>~~po~~|4320|1.2 V|–3|Halogen-Free TQFP|144|COM|
|LCMXO2-4000ZE-1BG256C<br>~~po~~<br>~~pO~~<br>~~po~~|4320<br>~~pO~~|1.2 V<br>~~pO~~|–1<br>~~pO~~|Halogen-Free caBGA<br>~~pO~~|256<br>~~pO~~|COM<br>~~pO~~|
|LCMXO2-4000ZE-2BG256C<br>~~po~~<br>~~po~~|4320|1.2 V|–2|Halogen-Free caBGA|256|COM|
|LCMXO2-4000ZE-3BG256C<br>~~po~~<br>~~po~~<br>~~pO~~|4320|1.2 V|–3|Halogen-Free caBGA|256|COM|
|LCMXO2-4000ZE-1FTG256C<br>~~po~~<br>~~pO~~<br>~~po~~|4320|1.2 V|–1|Halogen-Free ftBGA|256|COM|
|LCMXO2-4000ZE-2FTG256C<br>~~pO~~<br>~~po~~<br>~~po~~|4320|1.2 V|–2|Halogen-Free ftBGA|256|COM|
|LCMXO2-4000ZE-3FTG256C<br>~~po~~<br>~~po~~<br>~~pO~~|4320|1.2 V|–3|Halogen-Free ftBGA|256|COM|
|LCMXO2-4000ZE-1BG332C<br>~~po~~<br>~~pO~~|4320|1.2 V|–1|Halogen-Free caBGA|332|COM|
|LCMXO2-4000ZE-2BG332C<br>~~pO~~<br>~~pe~~|4320<br>~~pe~~|1.2 V<br>~~pe~~|–2<br>~~pe~~|Halogen-Free caBGA<br>~~pe~~|332<br>~~pe~~|COM<br>~~pe~~|
© 2010-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02056-4.3
95
**MachXO2 Family Data Sheet Data Sheet**
|**Part Number**<br>~~pO~~<br>~~po~~|**LUTs**|**Supply Voltage**|**Speed**|**Package**|**Leads**|**Temp.**|
|---|---|---|---|---|---|---|
|LCMXO2-4000ZE-3BG332C<br>~~pO~~<br>~~po~~<br>~~eG~~|4320<br>~~eG~~|1.2 V<br>~~GG~~|–3<br>~~GG~~|Halogen-Free caBGA<br>~~GG~~|332|COM|
|LCMXO2-4000ZE-1FG484C<br>~~po~~<br>~~eG~~<br>~~eG~~|4320<br>~~eG~~<br>~~eG~~|1.2 V<br>~~GG~~<br>~~GG~~|–1<br>~~GG~~<br>~~GG~~|Halogen-Free fpBGA<br>~~GG~~<br>~~GG~~|484|COM|
|LCMXO2-4000ZE-2FG484C<br>~~eG~~<br>~~eG~~<br>~~po~~|4320<br>~~eG~~<br>~~eG~~|1.2 V<br>~~GG~~<br>~~GG~~|–2<br>~~GG~~<br>~~GG~~|Halogen-Free fpBGA<br>~~GG~~<br>~~GG~~|484|COM|
|LCMXO2-4000ZE-3FG484C<br>~~eG~~<br>~~po~~<br>~~po~~|4320<br>~~eG~~|1.2 V<br>~~GG~~|–3<br>~~GG~~|Halogen-Free fpBGA<br>~~GG~~|484|COM|
|LCMXO2-7000ZE-1TG144C<br>~~po~~<br>~~po~~<br>~~eG~~|6864<br>~~eG~~|1.2 V<br>~~GG~~|–1<br>~~GG~~|Halogen-Free TQFP<br>~~GG~~|144|COM|
|LCMXO2-7000ZE-2TG144C<br>~~po~~<br>~~eG~~<br>~~eG~~|6864<br>~~eG~~<br>~~eG~~|1.2 V<br>~~GG~~<br>~~GG~~|–2<br>~~GG~~<br>~~GG~~|Halogen-Free TQFP<br>~~GG~~<br>~~GG~~|144|COM|
|LCMXO2-7000ZE-3TG144C<br>~~eG~~<br>~~eG~~<br>~~po~~|6864<br>~~eG~~<br>~~eG~~|1.2 V<br>~~GG~~<br>~~GG~~|–3<br>~~GG~~<br>~~GG~~|Halogen-Free TQFP<br>~~GG~~<br>~~GG~~|144|COM|
|LCMXO2-7000ZE-1BG256C<br>~~eG~~<br>~~po~~<br>~~po~~|6864<br>~~eG~~|1.2 V<br>~~GG~~|–1<br>~~GG~~|Halogen-Free caBGA<br>~~GG~~|256|COM|
|LCMXO2-7000ZE-2BG256C<br>~~po~~<br>~~po~~<br>~~po~~|6864|1.2 V|–2|Halogen-Free caBGA|256|COM|
|LCMXO2-7000ZE-3BG256C<br>~~po~~<br>~~po~~|6864|1.2 V|–3|Halogen-Free caBGA|256|COM|
|LCMXO2-7000ZE-1FTG256C<br>~~po~~<br>~~Ge~~<br>~~po~~|6864<br>~~Ge~~|1.2 V<br>~~GG~~|–1<br>~~GG~~|Halogen-Free ftBGA<br>~~GG~~|256|COM|
|LCMXO2-7000ZE-2FTG256C<br>~~po~~<br>~~po~~|6864|1.2 V|–2|Halogen-Free ftBGA|256|COM|
|LCMXO2-7000ZE-3FTG256C<br>~~po~~<br>~~po~~<br>~~po~~|6864|1.2 V|–3|Halogen-Free ftBGA|256|COM|
|LCMXO2-7000ZE-1BG332C<br>~~po~~<br>~~po~~<br>~~po~~|6864|1.2 V|–1|Halogen-Free caBGA|332|COM|
|LCMXO2-7000ZE-2BG332C<br>~~po~~<br>~~po~~<br>~~po~~|6864|1.2 V|–2|Halogen-Free caBGA|332|COM|
|LCMXO2-7000ZE-3BG332C<br>~~po~~<br>~~po~~<br>~~eG~~|6864<br>~~eG~~|1.2 V<br>~~GG~~|–3<br>~~GG~~|Halogen-Free caBGA<br>~~GG~~|332|COM|
|LCMXO2-7000ZE-1FG484C<br>~~po~~<br>~~eG~~<br>~~po~~|6864<br>~~eG~~|1.2 V<br>~~GG~~|–1<br>~~GG~~|Halogen-Free fpBGA<br>~~GG~~|484|COM|
|LCMXO2-7000ZE-2FG484C<br>~~eG~~<br>~~po~~<br>~~po~~|6864<br>~~eG~~|1.2 V<br>~~GG~~|–2<br>~~GG~~|Halogen-Free fpBGA<br>~~GG~~|484|COM|
|LCMXO2-7000ZE-3FG484C<br>~~po~~<br>~~po~~<br>~~po~~|6864|1.2 V|–3|Halogen-Free fpBGA|484|COM|
|LCMXO2-1200ZE-1TG100CR11<br>~~po~~<br>~~po~~<br>~~eG~~|1280<br>~~eG~~|1.2 V<br>~~GG~~|–1<br>~~GG~~|Halogen-Free TQFP<br>~~GG~~|100|COM|
|LCMXO2-1200ZE-2TG100CR11<br>~~po~~<br>~~eG~~<br>~~eG~~|1280<br>~~eG~~<br>~~eG~~|1.2 V<br>~~GG~~<br>~~GG~~|–2<br>~~GG~~<br>~~GG~~|Halogen-Free TQFP<br>~~GG~~<br>~~GG~~|100|COM|
|LCMXO2-1200ZE-3TG100CR11<br>~~eG~~<br>~~eG~~<br>~~po~~|1280<br>~~eG~~<br>~~eG~~|1.2 V<br>~~GG~~<br>~~GG~~|–3<br>~~GG~~<br>~~GG~~|Halogen-Free TQFP<br>~~GG~~<br>~~GG~~|100|COM|
|LCMXO2-1200ZE-1MG132CR11<br>~~eG~~<br>~~po~~<br>~~po~~|1280<br>~~eG~~|1.2 V<br>~~GG~~|–1<br>~~GG~~|Halogen-Free csBGA<br>~~GG~~|132|COM|
|LCMXO2-1200ZE-2MG132CR11<br>~~po~~<br>~~po~~<br>~~po~~|1280|1.2 V|–2|Halogen-Free csBGA|132|COM|
|LCMXO2-1200ZE-3MG132CR11<br>~~po~~<br>~~po~~<br>~~po~~|1280|1.2 V|–3|Halogen-Free csBGA|132|COM|
|LCMXO2-1200ZE-1TG144CR11<br>~~po~~<br>~~po~~<br>~~pO~~|1280|1.2 V|–1|Halogen-Free TQFP|144|COM|
|LCMXO2-1200ZE-2TG144CR11<br>~~po~~<br>~~pO~~<br>~~pO~~|1280|1.2 V|–2|Halogen-Free TQFP|144|COM|
|LCMXO2-1200ZE-3TG144CR11<br>~~pO~~<br>~~pO~~|1280|1.2 V|–3|Halogen-Free TQFP|144|COM|
**Note:**
1. Specifications for the “LCMXO2-1200ZE-speed package CR1” are the same as the “LCMXO2-1200ZE-speed package C” devices respectively, except as specified in the R1 Device Specifications section of this data sheet.
## **5.2.2. High-Performance Commercial Grade Devices with Voltage Regulator, Halogen Free (RoHS) Packaging**
**Table 5.2. High-Performance Commercial Grade Devices with Voltage Regulator, Halogen Free (RoHS) Packaging**
|**Part Number**<br>~~po~~<br>~~pO~~|**LUTs**|**Supply Voltage**|**Speed**|**Package**|**Leads**|**Temp.**|
|---|---|---|---|---|---|---|
|LCMXO2-256HC-4SG32C<br>~~po~~<br>~~pO~~<br>~~pO~~|256|2.5 V / 3.3 V|–4|Halogen-Free QFN|32|COM|
|LCMXO2-256HC-5SG32C<br>~~pO~~<br>~~pO~~|256|2.5 V / 3.3 V|–5|Halogen-Free QFN|32|COM|
|LCMXO2-256HC-6SG32C<br>~~pO~~<br>~~pf~~<br>~~po~~|256<br>~~pf~~|2.5 V / 3.3 V<br>~~pf~~|–6<br>~~pf~~|Halogen-Free QFN<br>~~pf~~|32<br>~~pf~~|COM<br>~~pf~~|
|LCMXO2-256HC-4SG48C<br>~~pf~~<br>~~po~~<br>~~po~~|256<br>~~pf~~|2.5 V / 3.3 V<br>~~pf~~|–4<br>~~pf~~|Halogen-Free QFN<br>~~pf~~|48<br>~~pf~~|COM<br>~~pf~~|
|LCMXO2-256HC-5SG48C<br>~~po~~<br>~~po~~<br>~~eG~~|256<br>~~eG~~|2.5 V / 3.3 V<br>~~GG~~|–5<br>~~GG~~|Halogen-Free QFN<br>~~GG~~|48|COM|
|LCMXO2-256HC-6SG48C<br>~~po~~<br>~~eG~~<br>~~pO~~|256<br>~~eG~~|2.5 V / 3.3 V<br>~~GG~~|–6<br>~~GG~~|Halogen-Free QFN<br>~~GG~~|48|COM|
|LCMXO2-256HC-4UMG64C<br>~~eG~~<br>~~pO~~|256<br>~~eG~~|2.5 V / 3.3 V<br>~~GG~~|–4<br>~~GG~~|Halogen-Free ucBGA<br>~~GG~~|64|COM|
|LCMXO2-256HC-5UMG64C<br>~~pO~~<br>~~pf~~<br>~~po~~|256<br>~~pf~~|2.5 V / 3.3 V<br>~~pf~~|–5<br>~~pf~~|Halogen-Free ucBGA<br>~~pf~~|64<br>~~pf~~|COM<br>~~pf~~|
|LCMXO2-256HC-6UMG64C<br>~~pf~~<br>~~po~~<br>~~po~~|256<br>~~pf~~|2.5 V / 3.3 V<br>~~pf~~|–6<br>~~pf~~|Halogen-Free ucBGA<br>~~pf~~|64<br>~~pf~~|COM<br>~~pf~~|
|LCMXO2-256HC-4TG100C<br>~~po~~<br>~~po~~|256|2.5 V / 3.3 V|–4|Halogen-Free TQFP|100|COM|
© 2010-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
96
FPGA-DS-02056-4.3
**MachXO2 Family Data Sheet Data Sheet**
|**Part Number**<br>~~pO~~<br>~~po~~|**LUTs**|**Supply Voltage**|**Speed**|**Package**|**Leads**|**Temp.**|
|---|---|---|---|---|---|---|
|LCMXO2-256HC-5TG100C<br>~~pO~~<br>~~po~~<br>~~eG~~|256<br>~~eG~~|2.5 V / 3.3 V<br>~~GG~~|–5<br>~~GG~~|Halogen-Free TQFP<br>~~GG~~|100|COM|
|LCMXO2-256HC-6TG100C<br>~~po~~<br>~~eG~~<br>~~pO~~|256<br>~~eG~~|2.5 V / 3.3 V<br>~~GG~~|–6<br>~~GG~~|Halogen-Free TQFP<br>~~GG~~|100|COM|
|LCMXO2-256HC-4MG132C<br>~~eG~~<br>~~pO~~<br>~~po~~|256<br>~~eG~~|2.5 V / 3.3 V<br>~~GG~~|–4<br>~~GG~~|Halogen-Free csBGA<br>~~GG~~|132|COM|
|LCMXO2-256HC-5MG132C<br>~~pO~~<br>~~po~~<br>~~po~~|256|2.5 V / 3.3 V|–5|Halogen-Free csBGA|132|COM|
|LCMXO2-256HC-6MG132C<br>~~po~~<br>~~po~~<br>~~po~~|256|2.5 V / 3.3 V|–6|Halogen-Free csBGA|132|COM|
|LCMXO2-640HC-4SG48C<br>~~po~~<br>~~po~~<br>~~eG~~|640<br>~~eG~~|2.5 V / 3.3 V<br>~~GG~~|–4<br>~~GG~~|Halogen-Free QFN<br>~~GG~~|48|COM|
|LCMXO2-640HC-5SG48C<br>~~po~~<br>~~eG~~<br>~~pO~~|640<br>~~eG~~|2.5 V / 3.3 V<br>~~GG~~|–5<br>~~GG~~|Halogen-Free QFN<br>~~GG~~|48|COM|
|LCMXO2-640HC-6SG48C<br>~~eG~~<br>~~pO~~<br>~~pO~~|640<br>~~eG~~|2.5 V / 3.3 V<br>~~GG~~|–6<br>~~GG~~|Halogen-Free QFN<br>~~GG~~|48|COM|
|LCMXO2-640HC-4TG100C<br>~~pO~~<br>~~pO~~<br>~~po~~|640|2.5 V / 3.3 V|–4|Halogen-Free TQFP|100|COM|
|LCMXO2-640HC-5TG100C<br>~~pO~~<br>~~po~~<br>~~po~~|640|2.5 V / 3.3 V|–5|Halogen-Free TQFP|100|COM|
|LCMXO2-640HC-6TG100C<br>~~po~~<br>~~po~~|640|2.5 V / 3.3 V|–6|Halogen-Free TQFP|100|COM|
|LCMXO2-640HC-4MG132C<br>~~po~~<br>~~Ge~~<br>~~po~~|640<br>~~Ge~~|2.5 V / 3.3 V<br>~~GG~~|–4<br>~~GG~~|Halogen-Free csBGA<br>~~GG~~|132|COM|
|LCMXO2-640HC-5MG132C<br>~~po~~<br>~~po~~|640|2.5 V / 3.3 V|–5|Halogen-Free csBGA|132|COM|
|LCMXO2-640HC-6MG132C<br>~~po~~<br>~~po~~<br>~~eG~~|640<br>~~eG~~|2.5 V / 3.3 V<br>~~GG~~|–6<br>~~GG~~|Halogen-Free csBGA<br>~~GG~~|132|COM|
|LCMXO2-640UHC-4TG144C<br>~~po~~<br>~~eG~~<br>~~po~~|640<br>~~eG~~|2.5 V / 3.3 V<br>~~GG~~|–4<br>~~GG~~|Halogen-Free TQFP<br>~~GG~~|144|COM|
|LCMXO2-640UHC-5TG144C<br>~~eG~~<br>~~po~~<br>~~po~~|640<br>~~eG~~|2.5 V / 3.3 V<br>~~GG~~|–5<br>~~GG~~|Halogen-Free TQFP<br>~~GG~~|144|COM|
|LCMXO2-640UHC-6TG144C<br>~~po~~<br>~~po~~<br>~~po~~|640|2.5 V / 3.3 V|–6|Halogen-Free TQFP|144|COM|
|LCMXO2-1200HC-4SG32C<br>~~po~~<br>~~po~~<br>~~po~~|1280|2.5 V / 3.3 V|–4|Halogen-Free QFN|32|COM|
|LCMXO2-1200HC-5SG32C<br>~~po~~<br>~~po~~<br>~~eG~~|1280<br>~~eG~~|2.5 V / 3.3 V<br>~~GG~~|–5<br>~~GG~~|Halogen-Free QFN<br>~~GG~~|32|COM|
|LCMXO2-1200HC-6SG32C<br>~~po~~<br>~~eG~~<br>~~po~~|1280<br>~~eG~~|2.5 V / 3.3 V<br>~~GG~~|–6<br>~~GG~~|Halogen-Free QFN<br>~~GG~~|32|COM|
|LCMXO2-1200HC-4TG100C<br>~~eG~~<br>~~po~~<br>~~po~~|1280<br>~~eG~~|2.5 V / 3.3 V<br>~~GG~~|–4<br>~~GG~~|Halogen-Free TQFP<br>~~GG~~|100|COM|
|LCMXO2-1200HC-5TG100C<br>~~po~~<br>~~po~~<br>~~po~~|1280|2.5 V / 3.3 V|–5|Halogen-Free TQFP|100|COM|
|LCMXO2-1200HC-6TG100C<br>~~po~~<br>~~po~~<br>~~po~~|1280|2.5 V / 3.3 V|–6|Halogen-Free TQFP|100|COM|
|LCMXO2-1200HC-4MG132C<br>~~po~~<br>~~po~~|1280|2.5 V / 3.3 V|–4|Halogen-Free csBGA|132|COM|
|LCMXO2-1200HC-5MG132C<br>~~po~~<br>~~pO~~|1280<br>~~pO~~|2.5 V / 3.3 V<br>~~pO~~|–5<br>~~pO~~|Halogen-Free csBGA<br>~~pO~~|132<br>~~pO~~|COM<br>~~pO~~|
|LCMXO2-1200HC-6MG132C<br>~~pO~~|1280<br>~~pO~~|2.5 V / 3.3 V<br>~~pO~~|–6<br>~~pO~~|Halogen-Free csBGA<br>~~pO~~|132<br>~~pO~~|COM<br>~~pO~~|
|LCMXO2-1200HC-4TG144C<br>~~pf~~|1280<br>~~pf~~|2.5 V / 3.3 V<br>~~pf~~|–4<br>~~pf~~|Halogen-Free TQFP<br>~~pf~~|144<br>~~pf~~|COM<br>~~pf~~|
|LCMXO2-1200HC-5TG144C<br>~~pf~~<br>~~Ge~~|1280<br>~~pf~~<br>~~Ge~~|2.5 V / 3.3 V<br>~~pf~~<br>~~GG~~|–5<br>~~pf~~<br>~~GG~~|Halogen-Free TQFP<br>~~pf~~<br>~~GG~~|144<br>~~pf~~|COM<br>~~pf~~|
|LCMXO2-1200HC-6TG144C<br>~~Ge~~<br>~~Ge~~|1280<br>~~Ge~~<br>~~Ge~~|2.5 V / 3.3 V<br>~~GG~~<br>~~GG~~|–6<br>~~GG~~<br>~~GG~~|Halogen-Free TQFP<br>~~GG~~<br>~~GG~~|144|COM|
|LCMXO2-1200UHC-4FTG256C<br>~~Ge~~<br>~~Ge~~|1280<br>~~Ge~~<br>~~Ge~~|2.5 V / 3.3 V<br>~~GG~~<br>~~GG~~|–4<br>~~GG~~<br>~~GG~~|Halogen-Free ftBGA<br>~~GG~~<br>~~GG~~|256|COM|
|LCMXO2-1200UHC-5FTG256C<br>~~Ge~~<br>~~Ge~~|1280<br>~~Ge~~<br>~~Ge~~|2.5 V / 3.3 V<br>~~GG~~<br>~~GG~~|–5<br>~~GG~~<br>~~GG~~|Halogen-Free ftBGA<br>~~GG~~<br>~~GG~~|256|COM|
|LCMXO2-1200UHC-6FTG256C<br>~~pO~~|1280<br>~~pO~~|2.5 V / 3.3 V<br>~~pO~~|–6<br>~~pO~~|Halogen-Free ftBGA<br>~~pO~~|256<br>~~pO~~|COM<br>~~pO~~|
|LCMXO2-2000HC-4TG100C<br>~~pf~~|2112<br>~~pf~~|2.5 V / 3.3 V<br>~~pf~~|–4<br>~~pf~~|Halogen-Free TQFP<br>~~pf~~|100<br>~~pf~~|COM<br>~~pf~~|
|LCMXO2-2000HC-5TG100C<br>~~pf~~<br>~~Ge~~|2112<br>~~pf~~<br>~~Ge~~|2.5 V / 3.3 V<br>~~pf~~<br>~~GG~~|–5<br>~~pf~~<br>~~GG~~|Halogen-Free TQFP<br>~~pf~~<br>~~GG~~|100<br>~~pf~~|COM<br>~~pf~~|
|LCMXO2-2000HC-6TG100C<br>~~Ge~~<br>~~Ge~~|2112<br>~~Ge~~<br>~~Ge~~|2.5 V / 3.3 V<br>~~GG~~<br>~~GG~~|–6<br>~~GG~~<br>~~GG~~|Halogen-Free TQFP<br>~~GG~~<br>~~GG~~|100|COM|
|LCMXO2-2000HC-4MG132C<br>~~pO~~<br>~~po~~|2112<br>~~pO~~|2.5 V / 3.3 V<br>~~pO~~|–4<br>~~pO~~|Halogen-Free csBGA<br>~~pO~~|132<br>~~pO~~|COM<br>~~pO~~|
|LCMXO2-2000HC-5MG132C<br>~~po~~<br>~~pO~~|2112|2.5 V / 3.3 V|–5|Halogen-Free csBGA|132|COM|
|LCMXO2-2000HC-6MG132C<br>~~po~~<br>~~pO~~<br>~~po~~|2112|2.5 V / 3.3 V|–6|Halogen-Free csBGA|132|COM|
|LCMXO2-2000HC-4TG144C<br>~~pO~~<br>~~po~~<br>~~po~~|2112|2.5 V / 3.3 V|–4|Halogen-Free TQFP|144|COM|
|LCMXO2-2000HC-5TG144C<br>~~po~~<br>~~po~~|2112|2.5 V / 3.3 V|–5|Halogen-Free TQFP|144|COM|
|LCMXO2-2000HC-6TG144C<br>~~po~~<br>~~pO~~<br>~~po~~|2112<br>~~pO~~|2.5 V / 3.3 V<br>~~pO~~|–6<br>~~pO~~|Halogen-Free TQFP<br>~~pO~~|144<br>~~pO~~|COM<br>~~pO~~|
|LCMXO2-2000HC-4BG256C<br>~~po~~<br>~~po~~|2112|2.5 V / 3.3 V|–4|Halogen-Free caBGA|256|COM|
|LCMXO2-2000HC-5BG256C<br>~~po~~<br>~~po~~<br>~~pO~~|2112|2.5 V / 3.3 V|–5|Halogen-Free caBGA|256|COM|
|LCMXO2-2000HC-6BG256C<br>~~po~~<br>~~pO~~<br>~~po~~|2112|2.5 V / 3.3 V|–6|Halogen-Free caBGA|256|COM|
|LCMXO2-2000HC-4FTG256C<br>~~pO~~<br>~~po~~<br>~~po~~|2112|2.5 V / 3.3 V|–4|Halogen-Free ftBGA|256|COM|
|LCMXO2-2000HC-5FTG256C<br>~~po~~<br>~~po~~|2112|2.5 V / 3.3 V|–5|Halogen-Free ftBGA|256|COM|
© 2010-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02056-4.3
97
**MachXO2 Family Data Sheet Data Sheet**
|**Part Number**<br>~~pO~~<br>~~eG~~|**LUTs**<br>~~eG~~|**Supply Voltage**<br>~~GG~~|**Speed**<br>~~GG~~|**Package**<br>~~GG~~|**Leads**|**Temp.**|
|---|---|---|---|---|---|---|
|LCMXO2-2000HC-6FTG256C<br>~~pO~~<br>~~eG~~<br>~~eG~~|2112<br>~~eG~~<br>~~eG~~|2.5 V / 3.3 V<br>~~GG~~<br>~~GG~~|–6<br>~~GG~~<br>~~GG~~|Halogen-Free ftBGA<br>~~GG~~<br>~~GG~~|256|COM|
|LCMXO2-2000UHC-4FG484C<br>~~eG~~<br>~~eG~~<br>~~eG~~|2112<br>~~eG~~<br>~~eG~~<br>~~eG~~|2.5 V / 3.3 V<br>~~GG~~<br>~~GG~~<br>~~GG~~|–4<br>~~GG~~<br>~~GG~~<br>~~GG~~|Halogen-Free fpBGA<br>~~GG~~<br>~~GG~~<br>~~GG~~|484|COM|
|LCMXO2-2000UHC-5FG484C<br>~~eG~~<br>~~eG~~<br>~~po~~|2112<br>~~eG~~<br>~~eG~~|2.5 V / 3.3 V<br>~~GG~~<br>~~GG~~|–5<br>~~GG~~<br>~~GG~~|Halogen-Free fpBGA<br>~~GG~~<br>~~GG~~|484|COM|
|LCMXO2-2000UHC-6FG484C<br>~~eG~~<br>~~po~~<br>~~po~~|2112<br>~~eG~~|2.5 V / 3.3 V<br>~~GG~~|–6<br>~~GG~~|Halogen-Free fpBGA<br>~~GG~~|484|COM|
|LCMXO2-4000HC-4QN84C<br>~~po~~<br>~~po~~<br>~~eG~~|4320<br>~~eG~~|2.5 V / 3.3 V<br>~~GG~~|–4<br>~~GG~~|Halogen-Free QFN<br>~~GG~~|84|COM|
|LCMXO2-4000HC-5QN84C<br>~~po~~<br>~~eG~~<br>~~eG~~|4320<br>~~eG~~<br>~~eG~~|2.5 V / 3.3 V<br>~~GG~~<br>~~GG~~|–5<br>~~GG~~<br>~~GG~~|Halogen-Free QFN<br>~~GG~~<br>~~GG~~|84|COM|
|LCMXO2-4000HC-6QN84C<br>~~eG~~<br>~~eG~~<br>~~eG~~|4320<br>~~eG~~<br>~~eG~~<br>~~eG~~|2.5 V / 3.3 V<br>~~GG~~<br>~~GG~~<br>~~GG~~|–6<br>~~GG~~<br>~~GG~~<br>~~GG~~|Halogen-Free QFN<br>~~GG~~<br>~~GG~~<br>~~GG~~|84|COM|
|LCMXO2-4000HC-4MG132C<br>~~eG~~<br>~~eG~~<br>~~po~~|4320<br>~~eG~~<br>~~eG~~|2.5 V / 3.3 V<br>~~GG~~<br>~~GG~~|–4<br>~~GG~~<br>~~GG~~|Halogen-Free csBGA<br>~~GG~~<br>~~GG~~|132|COM|
|LCMXO2-4000HC-5MG132C<br>~~eG~~<br>~~po~~<br>~~po~~|4320<br>~~eG~~|2.5 V / 3.3 V<br>~~GG~~|–5<br>~~GG~~|Halogen-Free csBGA<br>~~GG~~|132|COM|
|LCMXO2-4000HC-6MG132C<br>~~po~~<br>~~po~~|4320|2.5 V / 3.3 V|–6|Halogen-Free csBGA|132|COM|
|LCMXO2-4000HC-4TG144C<br>~~po~~<br>~~Ge~~<br>~~po~~|4320<br>~~Ge~~|2.5 V / 3.3 V<br>~~GG~~|–4<br>~~GG~~|Halogen-Free TQFP<br>~~GG~~|144|COM|
|LCMXO2-4000HC-5TG144C<br>~~po~~<br>~~po~~|4320|2.5 V / 3.3 V|–5|Halogen-Free TQFP|144|COM|
|LCMXO2-4000HC-6TG144C<br>~~po~~<br>~~po~~<br>~~po~~|4320|2.5 V / 3.3 V|–6|Halogen-Free TQFP|144|COM|
|LCMXO2-4000HC-4BG256C<br>~~po~~<br>~~po~~<br>~~po~~|4320|2.5 V / 3.3 V|–4|Halogen-Free caBGA|256|COM|
|LCMXO2-4000HC-5BG256C<br>~~po~~<br>~~po~~<br>~~po~~|4320|2.5 V / 3.3 V|–5|Halogen-Free caBGA|256|COM|
|LCMXO2-4000HC-6BG256C<br>~~po~~<br>~~po~~<br>~~eG~~|4320<br>~~eG~~|2.5 V / 3.3 V<br>~~GG~~|–6<br>~~GG~~|Halogen-Free caBGA<br>~~GG~~|256|COM|
|LCMXO2-4000HC-4FTG256C<br>~~po~~<br>~~eG~~<br>~~eG~~|4320<br>~~eG~~<br>~~eG~~|2.5 V / 3.3 V<br>~~GG~~<br>~~GG~~|–4<br>~~GG~~<br>~~GG~~|Halogen-Free ftBGA<br>~~GG~~<br>~~GG~~|256|COM|
|LCMXO2-4000HC-5FTG256C<br>~~eG~~<br>~~eG~~<br>~~po~~|4320<br>~~eG~~<br>~~eG~~|2.5 V / 3.3 V<br>~~GG~~<br>~~GG~~|–5<br>~~GG~~<br>~~GG~~|Halogen-Free ftBGA<br>~~GG~~<br>~~GG~~|256|COM|
|LCMXO2-4000HC-6FTG256C<br>~~eG~~<br>~~po~~<br>~~po~~|4320<br>~~eG~~|2.5 V / 3.3 V<br>~~GG~~|–6<br>~~GG~~|Halogen-Free ftBGA<br>~~GG~~|256|COM|
|LCMXO2-4000HC-4BG332C<br>~~po~~<br>~~po~~<br>~~po~~|4320|2.5 V / 3.3 V|–4|Halogen-Free caBGA|332|COM|
|LCMXO2-4000HC-5BG332C<br>~~po~~<br>~~po~~<br>~~po~~|4320|2.5 V / 3.3 V|–5|Halogen-Free caBGA|332|COM|
|LCMXO2-4000HC-6BG332C<br>~~po~~<br>~~po~~<br>~~eG~~|4320<br>~~eG~~|2.5 V / 3.3 V<br>~~GG~~|–6<br>~~GG~~|Halogen-Free caBGA<br>~~GG~~|332|COM|
|LCMXO2-4000HC-4FG484C<br>~~po~~<br>~~eG~~<br>~~po~~|4320<br>~~eG~~|2.5 V / 3.3 V<br>~~GG~~|–4<br>~~GG~~|Halogen-Free fpBGA<br>~~GG~~|484|COM|
|LCMXO2-4000HC-5FG484C<br>~~eG~~<br>~~po~~<br>~~po~~|4320<br>~~eG~~|2.5 V / 3.3 V<br>~~GG~~|–5<br>~~GG~~|Halogen-Free fpBGA<br>~~GG~~|484|COM|
|LCMXO2-4000HC-6FG484C<br>~~po~~<br>~~po~~<br>~~po~~|4320|2.5 V / 3.3 V|–6|Halogen-Free fpBGA|484|COM|
|LCMXO2-7000HC-4TG144C<br>~~po~~<br>~~po~~<br>~~pO~~|6864|2.5 V / 3.3 V|–4|Halogen-Free TQFP|144|COM|
|LCMXO2-7000HC-5TG144C<br>~~po~~<br>~~pO~~<br>~~po~~|6864|2.5 V / 3.3 V|–5|Halogen-Free TQFP|144|COM|
|LCMXO2-7000HC-6TG144C<br>~~pO~~<br>~~po~~<br>~~po~~|6864|2.5 V / 3.3 V|–6|Halogen-Free TQFP|144|COM|
|LCMXO2-7000HC-4BG256C<br>~~po~~<br>~~po~~<br>~~po~~|6864|2.5 V / 3.3 V|–4|Halogen-Free caBGA|256|COM|
|LCMXO2-7000HC-5BG256C<br>~~po~~<br>~~po~~<br>~~po~~|6864|2.5 V / 3.3 V|–5|Halogen-Free caBGA|256|COM|
|LCMXO2-7000HC-6BG256C<br>~~po~~<br>~~po~~<br>~~pO~~|6864|2.5 V / 3.3 V|–6|Halogen-Free caBGA|256|COM|
|LCMXO2-7000HC-4FTG256C<br>~~po~~<br>~~pO~~<br>~~pO~~|6864|2.5 V / 3.3 V|–4|Halogen-Free ftBGA|256|COM|
|LCMXO2-7000HC-5FTG256C<br>~~pO~~<br>~~pO~~<br>~~po~~|6864|2.5 V / 3.3 V|–5|Halogen-Free ftBGA|256|COM|
|LCMXO2-7000HC-6FTG256C<br>~~pO~~<br>~~po~~<br>~~po~~|6864|2.5 V / 3.3 V|–6|Halogen-Free ftBGA|256|COM|
|LCMXO2-7000HC-4BG332C<br>~~po~~<br>~~po~~<br>~~po~~|6864|2.5 V / 3.3 V|–4|Halogen-Free caBGA|332|COM|
|LCMXO2-7000HC-5BG332C<br>~~po~~<br>~~po~~<br>~~po~~|6864|2.5 V / 3.3 V|–5|Halogen-Free caBGA|332|COM|
|LCMXO2-7000HC-6BG332C<br>~~po~~<br>~~po~~<br>~~eG~~|6864<br>~~eG~~|2.5 V / 3.3 V<br>~~GG~~|–6<br>~~GG~~|Halogen-Free caBGA<br>~~GG~~|332|COM|
|LCMXO2-7000HC-4FG400C<br>~~po~~<br>~~eG~~<br>~~pO~~|6864<br>~~eG~~|2.5 V / 3.3 V<br>~~GG~~|–4<br>~~GG~~|Halogen-Free fpBGA<br>~~GG~~|400|COM|
|LCMXO2-7000HC-5FG400C<br>~~eG~~<br>~~pO~~<br>~~pO~~|6864<br>~~eG~~|2.5 V / 3.3 V<br>~~GG~~|–5<br>~~GG~~|Halogen-Free fpBGA<br>~~GG~~|400|COM|
|LCMXO2-7000HC-6FG400C<br>~~pO~~<br>~~pO~~|6864|2.5 V / 3.3 V|–6|Halogen-Free fpBGA|400|COM|
|LCMXO2-7000HC-4FG484C<br>~~pO~~<br>~~pf~~<br>~~po~~|6864<br>~~pf~~|2.5 V / 3.3 V<br>~~pf~~|–4<br>~~pf~~|Halogen-Free fpBGA<br>~~pf~~|484<br>~~pf~~|COM<br>~~pf~~|
|LCMXO2-7000HC-5FG484C<br>~~pf~~<br>~~po~~<br>~~po~~|6864<br>~~pf~~|2.5 V / 3.3 V<br>~~pf~~|–5<br>~~pf~~|Halogen-Free fpBGA<br>~~pf~~|484<br>~~pf~~|COM<br>~~pf~~|
|LCMXO2-7000HC-6FG484C<br>~~po~~<br>~~po~~<br>~~pO~~|6864|2.5 V / 3.3 V|–6|Halogen-Free fpBGA|484|COM|
|LCMXO2-1200HC-4TG100CR1<br>~~po~~<br>~~pO~~<br>~~pO~~|1280|2.5 V / 3.3 V|–4|Halogen-Free TQFP|100|COM|
|LCMXO2-1200HC-5TG100CR1<br>~~pO~~<br>~~pO~~<br>~~po~~|1280|2.5 V / 3.3 V|–5|Halogen-Free TQFP|100|COM|
|LCMXO2-1200HC-6TG100CR1<br>~~pO~~<br>~~po~~|1280|2.5 V / 3.3 V|–6|Halogen-Free TQFP|100|COM|
© 2010-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
98
FPGA-DS-02056-4.3
**MachXO2 Family Data Sheet Data Sheet**
|**Part Number**<br>~~pO~~<br>~~po~~|**LUTs**|**Supply Voltage**|**Speed**|**Package**|**Leads**|**Temp.**|
|---|---|---|---|---|---|---|
|LCMXO2-1200HC-4MG132CR1<br>~~pO~~<br>~~po~~<br>~~eG~~|1280<br>~~eG~~|2.5 V / 3.3 V<br>~~GG~~|–4<br>~~GG~~|Halogen-Free csBGA<br>~~GG~~|132|COM|
|LCMXO2-1200HC-5MG132CR1<br>~~po~~<br>~~eG~~<br>~~pO~~|1280<br>~~eG~~|2.5 V / 3.3 V<br>~~GG~~|–5<br>~~GG~~|Halogen-Free csBGA<br>~~GG~~|132|COM|
|LCMXO2-1200HC-6MG132CR1<br>~~eG~~<br>~~pO~~<br>~~po~~|1280<br>~~eG~~|2.5 V / 3.3 V<br>~~GG~~|–6<br>~~GG~~|Halogen-Free csBGA<br>~~GG~~|132|COM|
|LCMXO2-1200HC-4TG144CR1<br>~~pO~~<br>~~po~~<br>~~po~~|1280|2.5 V / 3.3 V|–4|Halogen-Free TQFP|144|COM|
|LCMXO2-1200HC-5TG144CR1<br>~~po~~<br>~~po~~|1280|2.5 V / 3.3 V|–5|Halogen-Free TQFP|144|COM|
|LCMXO2-1200HC-6TG144CR1<br>~~po~~<br>~~po~~|1280<br>~~po~~|2.5 V / 3.3 V<br>~~po~~|–6<br>~~po~~|Halogen-Free TQFP<br>~~po~~|144<br>~~po~~|COM<br>~~po~~|
1. Specifications for the “LCMXO2-1200HC-speed package CR1” are the same as the “LCMXO2-1200HC-speed package C” devices respectively, except as specified in the R1 Device Specifications of this data sheet.
© 2010-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02056-4.3
99
**MachXO2 Family Data Sheet Data Sheet**
## **5.2.3. High-Performance Commercial Grade Devices without Voltage Regulator, Halogen Free (RoHS) Packaging**
**Table 5.3. High-Performance Commercial Grade Devices without Voltage Regulator, Halogen Free (RoHS) Packaging**
|**Part Number**<br>~~pO~~<br>~~eG~~|**LUTs**<br>~~eG~~|**Supply Voltage**<br>~~GG~~|**Speed**<br>~~GG~~|**Package**<br>~~GG~~|**Leads**|**Temp.**|
|---|---|---|---|---|---|---|
|LCMXO2-2000HE-4TG100C<br>~~pO~~<br>~~eG~~<br>~~eG~~|2112<br>~~eG~~<br>~~eG~~|1.2 V<br>~~GG~~<br>~~GG~~|–4<br>~~GG~~<br>~~GG~~|Halogen-Free TQFP<br>~~GG~~<br>~~GG~~|100|COM|
|LCMXO2-2000HE-5TG100C<br>~~eG~~<br>~~eG~~<br>~~po~~|2112<br>~~eG~~<br>~~eG~~|1.2 V<br>~~GG~~<br>~~GG~~|–5<br>~~GG~~<br>~~GG~~|Halogen-Free TQFP<br>~~GG~~<br>~~GG~~|100|COM|
|LCMXO2-2000HE-6TG100C<br>~~eG~~<br>~~po~~<br>~~po~~|2112<br>~~eG~~|1.2 V<br>~~GG~~|–6<br>~~GG~~|Halogen-Free TQFP<br>~~GG~~|100|COM|
|LCMXO2-2000HE-4TG144C<br>~~po~~<br>~~po~~<br>~~eG~~|2112<br>~~eG~~|1.2 V<br>~~GG~~|–4<br>~~GG~~|Halogen-Free TQFP<br>~~GG~~|144|COM|
|LCMXO2-2000HE-5TG144C<br>~~po~~<br>~~eG~~<br>~~eG~~|2112<br>~~eG~~<br>~~eG~~|1.2 V<br>~~GG~~<br>~~GG~~|–5<br>~~GG~~<br>~~GG~~|Halogen-Free TQFP<br>~~GG~~<br>~~GG~~|144|COM|
|LCMXO2-2000HE-6TG144C<br>~~eG~~<br>~~eG~~<br>~~po~~|2112<br>~~eG~~<br>~~eG~~|1.2 V<br>~~GG~~<br>~~GG~~|–6<br>~~GG~~<br>~~GG~~|Halogen-Free TQFP<br>~~GG~~<br>~~GG~~|144|COM|
|LCMXO2-2000HE-4MG132C<br>~~eG~~<br>~~po~~<br>~~po~~|2112<br>~~eG~~|1.2 V<br>~~GG~~|–4<br>~~GG~~|Halogen-Free csBGA<br>~~GG~~|132|COM|
|LCMXO2-2000HE-5MG132C<br>~~po~~<br>~~po~~<br>~~po~~|2112|1.2 V|–5|Halogen-Free csBGA|132|COM|
|LCMXO2-2000HE-6MG132C<br>~~po~~<br>~~po~~<br>~~po~~|2112|1.2 V|–6|Halogen-Free csBGA|132|COM|
|LCMXO2-2000HE-4BG256C<br>~~po~~<br>~~po~~<br>~~eG~~|2112<br>~~eG~~|1.2 V<br>~~GG~~|–4<br>~~GG~~|Halogen-Free caBGA<br>~~GG~~|256|COM|
|LCMXO2-2000HE-5BG256C<br>~~po~~<br>~~eG~~<br>~~eG~~|2112<br>~~eG~~<br>~~eG~~|1.2 V<br>~~GG~~<br>~~GG~~|–5<br>~~GG~~<br>~~GG~~|Halogen-Free caBGA<br>~~GG~~<br>~~GG~~|256|COM|
|LCMXO2-2000HE-6BG256C<br>~~eG~~<br>~~eG~~<br>~~po~~|2112<br>~~eG~~<br>~~eG~~|1.2 V<br>~~GG~~<br>~~GG~~|–6<br>~~GG~~<br>~~GG~~|Halogen-Free caBGA<br>~~GG~~<br>~~GG~~|256|COM|
|LCMXO2-2000HE-4FTG256C<br>~~eG~~<br>~~po~~<br>~~po~~|2112<br>~~eG~~|1.2 V<br>~~GG~~|–4<br>~~GG~~|Halogen-Free ftBGA<br>~~GG~~|256|COM|
|LCMXO2-2000HE-5FTG256C<br>~~po~~<br>~~po~~<br>~~po~~|2112|1.2 V|–5|Halogen-Free ftBGA|256|COM|
|LCMXO2-2000HE-6FTG256C<br>~~po~~<br>~~po~~<br>~~po~~|2112|1.2 V|–6|Halogen-Free ftBGA|256|COM|
|LCMXO2-2000UHE-4FG484C<br>~~po~~<br>~~po~~<br>~~eG~~|2112<br>~~eG~~|1.2 V<br>~~GG~~|–4<br>~~GG~~|Halogen-Free fpBGA<br>~~GG~~|484|COM|
|LCMXO2-2000UHE-5FG484C<br>~~po~~<br>~~eG~~<br>~~eG~~|2112<br>~~eG~~<br>~~eG~~|1.2 V<br>~~GG~~<br>~~GG~~|–5<br>~~GG~~<br>~~GG~~|Halogen-Free fpBGA<br>~~GG~~<br>~~GG~~|484|COM|
|LCMXO2-2000UHE-6FG484C<br>~~eG~~<br>~~eG~~<br>~~po~~|2112<br>~~eG~~<br>~~eG~~|1.2 V<br>~~GG~~<br>~~GG~~|–6<br>~~GG~~<br>~~GG~~|Halogen-Free fpBGA<br>~~GG~~<br>~~GG~~|484|COM|
|LCMXO2-4000HE-4TG144C<br>~~eG~~<br>~~po~~<br>~~po~~|4320<br>~~eG~~|1.2 V<br>~~GG~~|–4<br>~~GG~~|Halogen-Free TQFP<br>~~GG~~|144|COM|
|LCMXO2-4000HE-5TG144C<br>~~po~~<br>~~po~~<br>~~po~~|4320|1.2 V|–5|Halogen-Free TQFP|144|COM|
|LCMXO2-4000HE-6TG144C<br>~~po~~<br>~~po~~<br>~~pO~~|4320|1.2 V|–6|Halogen-Free TQFP|144|COM|
|LCMXO2-4000HE-4MG132C<br>~~po~~<br>~~pO~~<br>~~pO~~|4320|1.2 V|–4|Halogen-Free csBGA|132|COM|
|LCMXO2-4000HE-5MG132C<br>~~pO~~<br>~~pO~~<br>~~po~~|4320|1.2 V|–5|Halogen-Free csBGA|132|COM|
|LCMXO2-4000HE-6MG132C<br>~~pO~~<br>~~po~~<br>~~po~~|4320|1.2 V|–6|Halogen-Free csBGA|132|COM|
|LCMXO2-4000HE-4BG256C<br>~~po~~<br>~~po~~<br>~~po~~|4320|1.2 V|–4|Halogen-Free caBGA|256|COM|
|LCMXO2-4000HE-4MG184C<br>~~po~~<br>~~po~~<br>~~po~~|4320|1.2 V|–4|Halogen-Free csBGA|184|COM|
|LCMXO2-4000HE-5MG184C<br>~~po~~<br>~~po~~<br>~~pO~~|4320|1.2 V|–5|Halogen-Free csBGA|184|COM|
|LCMXO2-4000HE-6MG184C<br>~~po~~<br>~~pO~~<br>~~pO~~|4320|1.2 V|–6|Halogen-Free csBGA|184|COM|
|LCMXO2-4000HE-5BG256C<br>~~pO~~<br>~~pO~~<br>~~po~~|4320|1.2 V|–5|Halogen-Free caBGA|256|COM|
|LCMXO2-4000HE-6BG256C<br>~~pO~~<br>~~po~~<br>~~po~~|4320|1.2 V|–6|Halogen-Free caBGA|256|COM|
|LCMXO2-4000HE-4FTG256C<br>~~po~~<br>~~po~~<br>~~po~~|4320|1.2 V|–4|Halogen-Free ftBGA|256|COM|
|LCMXO2-4000HE-5FTG256C<br>~~po~~<br>~~po~~<br>~~po~~|4320|1.2 V|–5|Halogen-Free ftBGA|256|COM|
|LCMXO2-4000HE-6FTG256C<br>~~po~~<br>~~po~~<br>~~eG~~|4320<br>~~eG~~|1.2 V<br>~~GG~~|–6<br>~~GG~~|Halogen-Free ftBGA<br>~~GG~~|256|COM|
|LCMXO2-4000HE-4BG332C<br>~~po~~<br>~~eG~~<br>~~pO~~|4320<br>~~eG~~|1.2 V<br>~~GG~~|–4<br>~~GG~~|Halogen-Free caBGA<br>~~GG~~|332|COM|
|LCMXO2-4000HE-5BG332C<br>~~eG~~<br>~~pO~~<br>~~pO~~|4320<br>~~eG~~|1.2 V<br>~~GG~~|–5<br>~~GG~~|Halogen-Free caBGA<br>~~GG~~|332|COM|
|LCMXO2-4000HE-6BG332C<br>~~pO~~<br>~~pO~~|4320|1.2 V|–6|Halogen-Free caBGA|332|COM|
|LCMXO2-4000HE-4FG484C<br>~~pO~~<br>~~pf~~<br>~~po~~|4320<br>~~pf~~|1.2 V<br>~~pf~~|–4<br>~~pf~~|Halogen-Free fpBGA<br>~~pf~~|484<br>~~pf~~|COM<br>~~pf~~|
|LCMXO2-4000HE-5FG484C<br>~~pf~~<br>~~po~~<br>~~eG~~|4320<br>~~pf~~<br>~~eG~~|1.2 V<br>~~pf~~<br>~~GG~~|–5<br>~~pf~~<br>~~GG~~|Halogen-Free fpBGA<br>~~pf~~<br>~~GG~~|484<br>~~pf~~|COM<br>~~pf~~|
|LCMXO2-4000HE-6FG484C<br>~~po~~<br>~~eG~~<br>~~pO~~|4320<br>~~eG~~|1.2 V<br>~~GG~~|–6<br>~~GG~~|Halogen-Free fpBGA<br>~~GG~~|484|COM|
|LCMXO2-7000HE-4TG144C<br>~~eG~~<br>~~pO~~|6864<br>~~eG~~|1.2 V<br>~~GG~~|–4<br>~~GG~~|Halogen-Free TQFP<br>~~GG~~|144|COM|
|LCMXO2-7000HE-5TG144C<br>~~pO~~<br>~~pf~~<br>~~po~~|6864<br>~~pf~~|1.2 V<br>~~pf~~|–5<br>~~pf~~|Halogen-Free TQFP<br>~~pf~~|144<br>~~pf~~|COM<br>~~pf~~|
|LCMXO2-7000HE-6TG144C<br>~~pf~~<br>~~po~~<br>~~po~~|6864<br>~~pf~~|1.2 V<br>~~pf~~|–6<br>~~pf~~|Halogen-Free TQFP<br>~~pf~~|144<br>~~pf~~|COM<br>~~pf~~|
|LCMXO2-7000HE-4BG256C<br>~~po~~<br>~~po~~|6864|1.2 V|–4|Halogen-Free caBGA|256|COM|
© 2010-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
100
FPGA-DS-02056-4.3
**MachXO2 Family Data Sheet Data Sheet**
|**Part Number**<br>~~pO~~<br>~~eG~~|**LUTs**<br>~~eG~~|**Supply Voltage**<br>~~GG~~|**Speed**<br>~~GG~~|**Package**<br>~~GG~~|**Leads**|**Temp.**|
|---|---|---|---|---|---|---|
|LCMXO2-7000HE-5BG256C<br>~~pO~~<br>~~eG~~<br>~~pO~~|6864<br>~~eG~~|1.2 V<br>~~GG~~|–5<br>~~GG~~|Halogen-Free caBGA<br>~~GG~~|256|COM|
|LCMXO2-7000HE-6BG256C<br>~~eG~~<br>~~pO~~<br>~~pO~~|6864<br>~~eG~~|1.2 V<br>~~GG~~|–6<br>~~GG~~|Halogen-Free caBGA<br>~~GG~~|256|COM|
|LCMXO2-7000HE-4FTG256C<br>~~pO~~<br>~~pO~~<br>~~po~~|6864|1.2 V|–4|Halogen-Free ftBGA|256|COM|
|LCMXO2-7000HE-5FTG256C<br>~~pO~~<br>~~po~~<br>~~po~~|6864|1.2 V|–5|Halogen-Free ftBGA|256|COM|
|LCMXO2-7000HE-6FTG256C<br>~~po~~<br>~~po~~<br>~~eG~~|6864<br>~~eG~~|1.2 V<br>~~GG~~|–6<br>~~GG~~|Halogen-Free ftBGA<br>~~GG~~|256|COM|
|LCMXO2-7000HE-4BG332C<br>~~po~~<br>~~eG~~<br>~~pO~~|6864<br>~~eG~~|1.2 V<br>~~GG~~|–4<br>~~GG~~|Halogen-Free caBGA<br>~~GG~~|332|COM|
|LCMXO2-7000HE-5BG332C<br>~~eG~~<br>~~pO~~<br>~~pO~~|6864<br>~~eG~~|1.2 V<br>~~GG~~|–5<br>~~GG~~|Halogen-Free caBGA<br>~~GG~~|332|COM|
|LCMXO2-7000HE-6BG332C<br>~~pO~~<br>~~pO~~<br>~~po~~|6864|1.2 V|–6|Halogen-Free caBGA|332|COM|
|LCMXO2-7000HE-4FG484C<br>~~pO~~<br>~~po~~<br>~~po~~|6864|1.2 V|–4|Halogen-Free fpBGA|484|COM|
|LCMXO2-7000HE-5FG484C<br>~~po~~<br>~~po~~|6864|1.2 V|–5|Halogen-Free fpBGA|484|COM|
|LCMXO2-7000HE-6FG484C<br>~~po~~<br>~~po~~|6864<br>~~po~~|1.2 V<br>~~po~~|–6<br>~~po~~|Halogen-Free fpBGA<br>~~po~~|484<br>~~po~~|COM<br>~~po~~|
## **5.2.4. Ultra Low Power Industrial Grade Devices, Halogen Free (RoHS) Packaging**
**Table 5.4. Ultra Low Power Industrial Grade Devices, Halogen Free (RoHS) Packaging**
|**Part Number**<br>~~po~~<br>~~po~~|**LUTs**|**Supply Voltage**<br>~~GO~~|**Speed**<br>~~GO~~|**Package**<br>~~GO~~|**Leads**|**Temp.**|
|---|---|---|---|---|---|---|
|LCMXO2-256ZE-1SG32I<br>~~po~~<br>~~Ge~~<br>~~po~~|256<br>~~Ge~~|1.2 V<br>~~Ge~~<br>~~GO~~|–1<br>~~Ge~~<br>~~GO~~|Halogen-Free QFN<br>~~Ge~~<br>~~GO~~|32<br>~~Ge~~|IND<br>~~Ge~~|
|LCMXO2-256ZE-2SG32I<br>~~Ge~~<br>~~po~~|256<br>~~Ge~~|1.2 V<br>~~Ge~~<br>~~GO~~|–2<br>~~Ge~~<br>~~GO~~|Halogen-Free QFN<br>~~Ge~~<br>~~GO~~|32<br>~~Ge~~|IND<br>~~Ge~~|
|LCMXO2-256ZE-3SG32I<br>~~po~~<br>~~po~~<br>~~po~~|256<br>~~po~~|1.2 V<br>~~GO~~<br>~~po~~|–3<br>~~GO ~~<br>~~po~~|Halogen-Free QFN<br> ~~GO~~<br>~~po~~|32<br>~~po~~|IND<br>~~po~~|
|LCMXO2-256ZE-1UMG64I<br>~~po~~|256<br>~~Ge~~|1.2 V<br>~~Ge~~|–1<br>~~Ge~~|Halogen-Free ucBGA<br>~~GO~~|64<br>~~GO~~|IND|
|LCMXO2-256ZE-2UMG64I<br>~~po~~<br>~~ee~~<br>~~po~~|256<br>~~ee~~<br>~~Ge~~<br>~~Ge~~|1.2 V<br>~~ee~~<br>~~Ge~~<br>~~Ge~~|–2<br>~~ee~~<br>~~Ge~~<br>~~Ge~~|Halogen-Free ucBGA<br>~~ee~~<br>~~GO~~<br>~~GO~~|64<br>~~ee~~<br>~~GO~~<br>~~GO~~|IND<br>~~ee~~|
|LCMXO2-256ZE-3UMG64I<br>~~ee~~<br>~~ee~~<br>~~po~~|256<br>~~ee~~<br>~~Ge~~<br>~~ee~~<br>~~Ge~~|1.2 V<br>~~ee~~<br>~~Ge~~<br>~~ee~~<br>~~Ge~~|–3<br>~~ee~~<br>~~Ge ~~<br>~~ee~~<br>~~Ge~~|Halogen-Free ucBGA<br>~~ee~~<br> ~~GO~~<br>~~ee~~<br>~~GO~~|64<br>~~ee~~<br>~~GO~~<br>~~ee~~<br>~~GO~~|IND<br>~~ee~~<br>~~ee~~|
|LCMXO2-256ZE-1TG100I<br>~~ee~~<br>~~po~~|256<br>~~ee~~<br>~~Ge~~|1.2 V<br>~~ee~~<br>~~Ge~~|–1<br>~~ee~~<br>~~Ge~~|Halogen-Free TQFP<br>~~ee~~<br>~~GO~~|100<br>~~ee~~<br>~~GO~~|IND<br>~~ee~~|
|LCMXO2-256ZE-2TG100I<br>~~po~~<br>~~po~~<br>~~po~~|256<br>~~Ge~~<br>~~po~~|1.2 V<br>~~Ge~~<br>~~po~~|–2<br>~~Ge ~~<br>~~po~~|Halogen-Free TQFP<br> ~~GO~~<br>~~po~~|100<br>~~GO~~<br>~~po~~|IND<br>~~po~~|
|LCMXO2-256ZE-3TG100I<br>~~po~~<br>~~pO~~|256|1.2 V|–3|Halogen-Free TQFP<br>~~GO~~|100<br>~~GO~~|IND|
|LCMXO2-256ZE-1MG132I<br>~~po~~<br>~~GG~~<br>~~pO~~|256<br>~~GG~~|1.2 V<br>~~GG~~|–1<br>~~GG~~|Halogen-Free csBGA<br>~~GG~~<br>~~GO~~|132<br>~~GG~~<br>~~GO~~|IND<br>~~GG~~|
|LCMXO2-256ZE-2MG132I<br>~~GG~~<br>~~pO~~|256<br>~~GG~~|1.2 V<br>~~GG~~|–2<br>~~GG~~|Halogen-Free csBGA<br>~~GG~~<br>~~GO~~|132<br>~~GG~~<br>~~GO~~|IND<br>~~GG~~|
|LCMXO2-256ZE-3MG132I<br>~~pO~~<br>~~po~~|256<br>~~po~~|1.2 V<br>~~po~~|–3<br>~~po~~|Halogen-Free csBGA<br>~~GO~~<br>~~po~~|132<br>~~GO~~<br>~~po~~|IND<br>~~po~~|
|LCMXO2-640ZE-1TG100I<br>~~po~~|640<br>~~po~~|1.2 V<br>~~po~~|–1<br>~~po~~|Halogen-Free TQFP<br>~~po~~|100<br>~~po~~|IND<br>~~po~~|
|LCMXO2-640ZE-2TG100I<br>~~po~~<br>~~po~~|640<br>~~po~~|1.2 V<br>~~po~~|–2<br>~~po~~|Halogen-Free TQFP<br>~~po~~|100<br>~~po~~|IND<br>~~po~~|
|LCMXO2-640ZE-3TG100I<br>~~po~~|640|1.2 V|–3|Halogen-Free TQFP<br>~~GO~~|100<br>~~GO~~|IND|
|LCMXO2-640ZE-1MG132I<br>~~po~~<br>~~GG~~<br>~~pO~~|640<br>~~GG~~|1.2 V<br>~~GG~~|–1<br>~~GG~~|Halogen-Free csBGA<br>~~GG~~<br>~~GO~~<br>~~GO~~|132<br>~~GG~~<br>~~GO~~<br>~~GO~~|IND<br>~~GG~~|
|LCMXO2-640ZE-2MG132I<br>~~GG~~<br>~~GG~~<br>~~pO~~|640<br>~~GG~~<br>~~GG~~|1.2 V<br>~~GG~~<br>~~GG~~|–2<br>~~GG~~<br>~~GG~~|Halogen-Free csBGA<br>~~GG~~<br>~~GO~~<br>~~GG~~<br>~~GO~~|132<br>~~GG~~<br>~~GO~~<br>~~GG~~<br>~~GO~~|IND<br>~~GG~~<br>~~GG~~|
|LCMXO2-640ZE-3MG132I<br>~~GG~~<br>~~pO~~|640<br>~~GG~~|1.2 V<br>~~GG~~|–3<br>~~GG~~|Halogen-Free csBGA<br>~~GG~~<br>~~GO~~|132<br>~~GG~~<br>~~GO~~|IND<br>~~GG~~|
|LCMXO2-1200ZE-1UWG25ITR1<br>~~pO~~<br>~~po~~|1280<br>~~po~~|1.2 V<br>~~po~~|–1<br>~~po~~|Halogen-Free WLCSP<br>~~GO~~<br>~~po~~|25<br>~~GO~~<br>~~po~~|IND<br>~~po~~|
|LCMXO2-1200ZE-1UWG25ITR503<br>~~pf~~<br>~~po~~|1280<br>~~pf~~|1.2 V<br>~~pf~~|–1<br>~~pf~~|Halogen-Free WLCSP<br>~~pf~~|25<br>~~pf~~|IND<br>~~pf~~|
|LCMXO2-1200ZE-1UWG25ITR1K2<br>~~pf~~<br>~~po~~<br>~~pO~~|1280<br>~~pf~~|1.2 V<br>~~pf~~|–1<br>~~pf~~|Halogen-Free WLCSP<br>~~pf~~|25<br>~~pf~~|IND<br>~~pf~~|
|LCMXO2-1200ZE-1UWG36ITR1<br>~~po~~<br>~~pO~~<br>~~pO~~|1280|1.2 V|–1|Halogen-Free WLCSP|36|IND|
|LCMXO2-1200ZE-1UWG36ITR1K2<br>~~pO~~<br>~~pO~~<br>~~pO~~|1280|1.2 V|–1|Halogen-Free WLCSP|36|IND|
|LCMXO2-1200ZE-1SG32I<br>~~pO~~<br>~~pO~~<br>~~po~~|1280|1.2 V|–1|Halogen-Free QFN|32|IND|
|LCMXO2-1200ZE-2SG32I<br>~~pO~~<br>~~po~~<br>~~po~~|1280|1.2 V|–2|Halogen-Free QFN|32|IND|
|LCMXO2-1200ZE-3SG32I<br>~~po~~<br>~~po~~<br>~~po~~|1280|1.2 V|–3|Halogen-Free QFN|32|IND|
|LCMXO2-1200ZE-1TG100I<br>~~po~~<br>~~po~~|1280|1.2 V|–1|Halogen-Free TQFP|100|IND|
|LCMXO2-1200ZE-2TG100I<br>~~po~~<br>~~pO~~<br>~~pO~~|1280<br>~~pO~~|1.2 V<br>~~pO~~|–2<br>~~pO~~|Halogen-Free TQFP<br>~~pO~~|100<br>~~pO~~|IND<br>~~pO~~|
|LCMXO2-1200ZE-3TG100I<br>~~pO~~<br>~~po~~|1280|1.2 V|–3|Halogen-Free TQFP|100|IND|
|LCMXO2-1200ZE-1MG132I<br>~~pO~~<br>~~po~~|1280|1.2 V|–1|Halogen-Free csBGA|132|IND|
© 2010-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02056-4.3
101
**MachXO2 Family Data Sheet Data Sheet**
|**Part Number**<br>~~po~~<br>~~pO~~|**LUTs**<br>~~po~~|**Supply Voltage**<br>~~po~~|**Speed**<br>~~po~~|**Package**<br>~~po~~|**Leads**<br>~~po~~|**Temp.**<br>~~po~~|
|---|---|---|---|---|---|---|
|LCMXO2-1200ZE-2MG132I<br>~~pO~~<br>~~pO~~|1280|1.2 V|–2|Halogen-Free csBGA|132|IND|
|LCMXO2-1200ZE-3MG132I<br>~~pO~~<br>~~pO~~<br>~~pO~~|1280|1.2 V|–3|Halogen-Free csBGA|132|IND|
|LCMXO2-1200ZE-1TG144I<br>~~pO~~<br>~~pO~~<br>~~po~~|1280|1.2 V|–1|Halogen-Free TQFP|144|IND|
|LCMXO2-1200ZE-2TG144I<br>~~pO~~<br>~~po~~|1280|1.2 V|–2|Halogen-Free TQFP|144|IND|
|LCMXO2-1200ZE-3TG144I<br>~~po~~<br>~~pf~~|1280<br>~~pf~~|1.2 V<br>~~pf~~|–3<br>~~pf~~|Halogen-Free TQFP<br>~~pf~~|144<br>~~pf~~|IND<br>~~pf~~|
|LCMXO2-2000ZE-1UWG49ITR1<br>~~pO~~<br>~~pO~~|2112<br>~~pO~~|1.2 V<br>~~pO~~|–1<br>~~pO~~|Halogen-Free WLCSP<br>~~pO~~|49<br>~~pO~~|IND<br>~~pO~~|
|LCMXO2-2000ZE-1UWG49ITR503<br>~~pO~~<br>~~pO~~|2112|1.2 V|–1|Halogen-Free WLCSP|49|IND|
|LCMXO2-2000ZE-1UWG49ITR1K2<br>~~pO~~<br>~~pO~~<br>~~pO~~|2112|1.2 V|–1|Halogen-Free WLCSP|49|IND|
|LCMXO2-2000ZE-1TG100I<br>~~pO~~<br>~~pO~~<br>~~po~~|2112|1.2 V|–1|Halogen-Free TQFP|100|IND|
|LCMXO2-2000ZE-2TG100I<br>~~pO~~<br>~~po~~|2112|1.2 V|–2|Halogen-Free TQFP|100|IND|
|LCMXO2-2000ZE-3TG100I<br>~~po~~<br>~~pf~~|2112<br>~~pf~~|1.2 V<br>~~pf~~|–3<br>~~pf~~|Halogen-Free TQFP<br>~~pf~~|100<br>~~pf~~|IND<br>~~pf~~|
|LCMXO2-2000ZE-1MG132I<br>~~po~~<br>~~po~~|2112<br>~~po~~|1.2 V<br>~~po~~|–1<br>~~po~~|Halogen-Free csBGA<br>~~po~~|132<br>~~po~~|IND<br>~~po~~|
|LCMXO2-2000ZE-2MG132I<br>~~po~~<br>~~pO~~|2112|1.2 V|–2|Halogen-Free csBGA|132|IND|
|LCMXO2-2000ZE-3MG132I<br>~~po~~<br>~~pO~~|2112|1.2 V|–3|Halogen-Free csBGA<br>~~GO~~|132<br>~~GO~~|IND|
|LCMXO2-2000ZE-1TG144I<br>~~pO~~<br>~~GG~~|2112<br>~~GG~~|1.2 V<br>~~GG~~|–1<br>~~GG~~|Halogen-Free TQFP<br>~~GG~~<br>~~GO~~<br>~~GO~~|144<br>~~GG~~<br>~~GO~~<br>~~GO~~|IND<br>~~GG~~|
|LCMXO2-2000ZE-2TG144I<br>~~GG~~<br>~~GG~~<br>~~po~~|2112<br>~~GG~~<br>~~GG~~|1.2 V<br>~~GG~~<br>~~GG~~|–2<br>~~GG~~<br>~~GG~~|Halogen-Free TQFP<br>~~GG~~<br>~~GO~~<br>~~GG~~<br>~~GO~~<br>~~GO~~|144<br>~~GG~~<br>~~GO~~<br>~~GG~~<br>~~GO~~<br>~~GO~~|IND<br>~~GG~~<br>~~GG~~|
|LCMXO2-2000ZE-3TG144I<br>~~GG~~<br>~~GG~~<br>~~po~~|2112<br>~~GG~~<br>~~GG~~|1.2 V<br>~~GG~~<br>~~GG~~|–3<br>~~GG~~<br>~~GG~~|Halogen-Free TQFP<br>~~GG~~<br>~~GO~~<br>~~GG~~<br>~~GO~~|144<br>~~GG~~<br>~~GO~~<br>~~GG~~<br>~~GO~~|IND<br>~~GG~~<br>~~GG~~|
|LCMXO2-2000ZE-1BG256I<br>~~GG~~<br>~~po~~<br>~~po~~|2112<br>~~GG~~|1.2 V<br>~~GG~~|–1<br>~~GG~~|Halogen-Free caBGA<br>~~GG~~<br>~~GO~~|256<br>~~GG~~<br>~~GO~~|IND<br>~~GG~~|
|LCMXO2-2000ZE-2BG256I<br>~~po~~<br>~~po~~<br>~~po~~|2112|1.2 V|–2|Halogen-Free caBGA<br>~~GO~~|256<br>~~GO~~|IND|
|LCMXO2-2000ZE-3BG256I<br>~~po~~<br>~~po~~<br>~~po~~|2112|1.2 V|–3|Halogen-Free caBGA|256|IND|
|LCMXO2-2000ZE-1FTG256I<br>~~po~~<br>~~po~~<br>~~pO~~|2112|1.2 V|–1|Halogen-Free ftBGA|256|IND|
|LCMXO2-2000ZE-2FTG256I<br>~~po~~<br>~~pO~~|2112|1.2 V|–2|Halogen-Free ftBGA<br>~~GO~~|256<br>~~GO~~|IND|
|LCMXO2-2000ZE-3FTG256I<br>~~pO~~<br>~~GG~~|2112<br>~~GG~~|1.2 V<br>~~GG~~|–3<br>~~GG~~|Halogen-Free ftBGA<br>~~GG~~<br>~~GO~~|256<br>~~GG~~<br>~~GO~~|IND<br>~~GG~~|
|LCMXO2-4000ZE-1UWG81ITR1<br>~~GG~~<br>~~po~~<br>~~po~~|4320<br>~~GG~~<br>~~po~~|1.2 V<br>~~GG~~<br>~~po~~|–1<br>~~GG~~<br>~~po~~|Halogen-Free WLCSP<br>~~GG~~<br>~~GO~~<br>~~po~~|81<br>~~GG~~<br>~~GO~~<br>~~po~~|IND<br>~~GG~~<br>~~po~~|
|LCMXO2-4000ZE-1UWG81ITR1K2<br>~~po~~<br>~~po~~|4320<br>~~po~~|1.2 V<br>~~po~~|–1<br>~~po~~|Halogen-Free WLCSP<br>~~po~~|81<br>~~po~~|IND<br>~~po~~|
|LCMXO2-4000ZE-1QN84I<br>~~po~~<br>~~po~~|4320<br>~~po~~|1.2 V<br>~~po~~|–1<br>~~po~~|Halogen-Free QFN<br>~~po~~|84<br>~~po~~|IND<br>~~po~~|
|LCMXO2-4000ZE-2QN84I<br>~~po~~|4320<br>~~po~~|1.2 V<br>~~po~~|–2<br>~~po~~|Halogen-Free QFN<br>~~po~~|84<br>~~po~~|IND<br>~~po~~|
|LCMXO2-4000ZE-3QN84I<br>~~po~~|4320<br>~~po~~|1.2 V<br>~~po~~|–3<br>~~po~~|Halogen-Free QFN<br>~~po~~|84<br>~~po~~|IND<br>~~po~~|
|LCMXO2-4000ZE-1MG132I<br>~~po~~<br>~~po~~|4320<br>~~po~~|1.2 V<br>~~po~~|–1<br>~~po~~|Halogen-Free csBGA<br>~~po~~|132<br>~~po~~|IND<br>~~po~~|
|LCMXO2-4000ZE-2MG132I<br>~~po~~<br>~~po~~|4320|1.2 V|–2|Halogen-Free csBGA|132|IND|
|LCMXO2-4000ZE-3MG132I<br>~~po~~<br>~~po~~<br>~~po~~|4320|1.2 V|–3|Halogen-Free csBGA|132|IND|
|LCMXO2-4000ZE-1TG144I<br>~~po~~<br>~~po~~<br>~~po~~|4320|1.2 V|–1|Halogen-Free TQFP|144|IND|
|LCMXO2-4000ZE-2TG144I<br>~~po~~<br>~~po~~|4320|1.2 V|–2|Halogen-Free TQFP|144|IND|
|LCMXO2-4000ZE-3TG144I<br>~~po~~<br>~~po~~|4320<br>~~po~~|1.2 V<br>~~po~~|–3<br>~~po~~|Halogen-Free TQFP<br>~~po~~|144<br>~~po~~|IND<br>~~po~~|
|LCMXO2-4000ZE-1BG256I<br>~~po~~<br>~~pO~~|4320<br>~~po~~|1.2 V<br>~~po~~|–1<br>~~po~~|Halogen-Free caBGA<br>~~po~~|256<br>~~po~~|IND<br>~~po~~|
|LCMXO2-4000ZE-2BG256I<br>~~pO~~<br>~~pO~~|4320|1.2 V|–2|Halogen-Free caBGA|256|IND|
|LCMXO2-4000ZE-3BG256I<br>~~pO~~<br>~~pO~~<br>~~pO~~|4320|1.2 V|–3|Halogen-Free caBGA|256|IND|
|LCMXO2-4000ZE-1FTG256I<br>~~pO~~<br>~~pO~~<br>~~po~~|4320|1.2 V|–1|Halogen-Free ftBGA|256|IND|
|LCMXO2-4000ZE-2FTG256I<br>~~pO~~<br>~~po~~<br>~~po~~|4320|1.2 V|–2|Halogen-Free ftBGA|256|IND|
|LCMXO2-4000ZE-3FTG256I<br>~~po~~<br>~~po~~<br>~~po~~|4320|1.2 V|–3|Halogen-Free ftBGA|256|IND|
|LCMXO2-4000ZE-1BG332I<br>~~po~~<br>~~po~~<br>~~pO~~|4320|1.2 V|–1|Halogen-Free caBGA|332|IND|
|LCMXO2-4000ZE-2BG332I<br>~~po~~<br>~~pO~~<br>~~pO~~|4320|1.2 V|–2|Halogen-Free caBGA|332|IND|
|LCMXO2-4000ZE-3BG332I<br>~~pO~~<br>~~pO~~<br>~~pO~~|4320|1.2 V|–3|Halogen-Free caBGA|332|IND|
|LCMXO2-4000ZE-1FG484I<br>~~pO~~<br>~~pO~~|4320|1.2 V|–1|Halogen-Free fpBGA|484|IND|
|LCMXO2-4000ZE-2FG484I<br>~~pO~~<br>~~po~~|4320<br>~~po~~|1.2 V<br>~~po~~|–2<br>~~po~~|Halogen-Free fpBGA<br>~~po~~|484<br>~~po~~|IND<br>~~po~~|
|LCMXO2-4000ZE-3FG484I<br>~~pO~~|4320<br>~~pO~~|1.2 V<br>~~pO~~|–3<br>~~pO~~|Halogen-Free fpBGA<br>~~pO~~|484<br>~~pO~~|IND<br>~~pO~~|
© 2010-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
102
FPGA-DS-02056-4.3
**MachXO2 Family Data Sheet Data Sheet**
|**Part Number**<br>~~po~~|**LUTs**|**Supply Voltage**|**Speed**|**Package**|**Leads**|**Temp.**|
|---|---|---|---|---|---|---|
|LCMXO2-7000ZE-1TG144I<br>~~po~~<br>~~po~~<br>~~pO~~|6864<br>~~po~~|1.2 V<br>~~po~~|–1<br>~~po~~|Halogen-Free TQFP<br>~~po~~|144<br>~~po~~|IND<br>~~po~~|
|LCMXO2-7000ZE-2TG144I<br>~~pO~~<br>~~pO~~|6864|1.2 V|–2|Halogen-Free TQFP|144|IND|
|LCMXO2-7000ZE-3TG144I<br>~~pO~~<br>~~pO~~<br>~~pO~~|6864|1.2 V|–3|Halogen-Free TQFP|144|IND|
|LCMXO2-7000ZE-1BG256I<br>~~pO~~<br>~~pO~~<br>~~pO~~|6864|1.2 V|–1|Halogen-Free caBGA|256|IND|
|LCMXO2-7000ZE-2BG256I<br>~~pO~~<br>~~pO~~|6864|1.2 V|–2|Halogen-Free caBGA|256|IND|
|LCMXO2-7000ZE-3BG256I<br>~~pO~~<br>~~po~~|6864<br>~~po~~|1.2 V<br>~~po~~|–3<br>~~po~~|Halogen-Free caBGA<br>~~po~~|256<br>~~po~~|IND<br>~~po~~|
|LCMXO2-7000ZE-1FTG256I<br>~~po~~|6864<br>~~po~~|1.2 V<br>~~po~~|–1<br>~~po~~|Halogen-Free ftBGA<br>~~po~~|256<br>~~po~~|IND<br>~~po~~|
|LCMXO2-7000ZE-2FTG256I<br>~~po~~|6864<br>~~po~~|1.2 V<br>~~po~~|–2<br>~~po~~|Halogen-Free ftBGA<br>~~po~~|256<br>~~po~~|IND<br>~~po~~|
|LCMXO2-7000ZE-3FTG256I<br>~~po~~<br>~~pO~~|6864<br>~~po~~|1.2 V<br>~~po~~|–3<br>~~po~~|Halogen-Free ftBGA<br>~~po~~|256<br>~~po~~|IND<br>~~po~~|
|LCMXO2-7000ZE-1BG332I<br>~~pO~~<br>~~po~~|6864|1.2 V|–1|Halogen-Free caBGA|332|IND|
|LCMXO2-7000ZE-2BG332I<br>~~pO~~<br>~~po~~|6864|1.2 V|–2|Halogen-Free caBGA<br>~~GG~~|332<br>~~GG~~|IND|
|LCMXO2-7000ZE-3BG332I<br>~~po~~<br>~~GG~~<br>~~po~~|6864<br>~~GG~~<br>~~Ge~~|1.2 V<br>~~GG~~<br>~~Ge~~|–3<br>~~GG~~<br>~~Ge~~|Halogen-Free caBGA<br>~~GG~~<br>~~GG~~<br>~~GO~~|332<br>~~GG~~<br>~~GG~~<br>~~GO~~|IND<br>~~GG~~|
|LCMXO2-7000ZE-1FG484I<br>~~GG~~<br>~~ee~~<br>~~po~~|6864<br>~~GG~~<br>~~ee~~<br>~~Ge~~|1.2 V<br>~~GG~~<br>~~ee~~<br>~~Ge~~|–1<br>~~GG~~<br>~~ee~~<br>~~Ge~~|Halogen-Free fpBGA<br>~~GG~~<br>~~GG~~<br>~~ee~~<br>~~GO~~|484<br>~~GG~~<br>~~GG~~<br>~~ee~~<br>~~GO~~|IND<br>~~GG~~<br>~~ee~~|
|LCMXO2-7000ZE-2FG484I<br>~~ee~~<br>~~po~~|6864<br>~~ee~~<br>~~Ge~~|1.2 V<br>~~ee~~<br>~~Ge~~|–2<br>~~ee~~<br>~~Ge~~|Halogen-Free fpBGA<br>~~ee~~<br>~~GO~~|484<br>~~ee~~<br>~~GO~~|IND<br>~~ee~~|
|LCMXO2-7000ZE-3FG484I<br>~~po~~<br>~~po~~|6864<br>~~Ge~~<br>~~po~~|1.2 V<br>~~Ge~~<br>~~po~~|–3<br>~~Ge ~~<br>~~po~~|Halogen-Free fpBGA<br> ~~GO~~<br>~~po~~|484<br>~~GO~~<br>~~po~~|IND<br>~~po~~|
|LCMXO2-1200ZE-1TG100IR14<br>~~po~~|1280<br>~~po~~|1.2 V<br>~~po~~|–1<br>~~po~~|Halogen-Free TQFP<br>~~po~~|100<br>~~po~~|IND<br>~~po~~|
|LCMXO2-1200ZE-2TG100IR14<br>~~po~~<br>~~po~~|1280<br>~~po~~|1.2 V<br>~~po~~|–2<br>~~po~~|Halogen-Free TQFP<br>~~po~~|100<br>~~po~~|IND<br>~~po~~|
|LCMXO2-1200ZE-3TG100IR14<br>~~po~~|1280<br>~~Ge~~|1.2 V<br>~~Ge~~|–3<br>~~Ge~~|Halogen-Free TQFP<br>~~GO~~|100<br>~~GO~~|IND|
|LCMXO2-1200ZE-1MG132IR14<br>~~po~~<br>~~ee~~|1280<br>~~ee~~<br>~~Ge~~<br>~~Ge~~|1.2 V<br>~~ee~~<br>~~Ge~~<br>~~Ge~~|–1<br>~~ee~~<br>~~Ge~~<br>~~Ge~~|Halogen-Free csBGA<br>~~ee~~<br>~~GO~~<br>~~GO~~|132<br>~~ee~~<br>~~GO~~<br>~~GO~~|IND<br>~~ee~~|
|LCMXO2-1200ZE-2MG132IR14<br>~~ee~~<br>~~ee~~<br>~~po~~|1280<br>~~ee~~<br>~~Ge~~<br>~~ee~~<br>~~Ge~~<br>~~Ge~~|1.2 V<br>~~ee~~<br>~~Ge~~<br>~~ee~~<br>~~Ge~~<br>~~Ge~~|–2<br>~~ee~~<br>~~Ge ~~<br>~~ee~~<br>~~Ge~~<br>~~Ge~~|Halogen-Free csBGA<br>~~ee~~<br> ~~GO~~<br>~~ee~~<br>~~GO~~<br>~~GO~~|132<br>~~ee~~<br>~~GO~~<br>~~ee~~<br>~~GO~~<br>~~GO~~|IND<br>~~ee~~<br>~~ee~~|
|LCMXO2-1200ZE-3MG132IR14<br>~~ee~~<br>~~ee~~<br>~~po~~|1280<br>~~ee~~<br>~~Ge~~<br>~~ee~~<br>~~Ge~~|1.2 V<br>~~ee~~<br>~~Ge~~<br>~~ee~~<br>~~Ge~~|–3<br>~~ee~~<br>~~Ge ~~<br>~~ee~~<br>~~Ge~~|Halogen-Free csBGA<br>~~ee~~<br> ~~GO~~<br>~~ee~~<br>~~GO~~|132<br>~~ee~~<br>~~GO~~<br>~~ee~~<br>~~GO~~|IND<br>~~ee~~<br>~~ee~~|
|LCMXO2-1200ZE-1TG144IR14<br>~~ee~~<br>~~po~~|1280<br>~~ee~~<br>~~Ge~~|1.2 V<br>~~ee~~<br>~~Ge~~|–1<br>~~ee~~<br>~~Ge~~|Halogen-Free TQFP<br>~~ee~~<br>~~GO~~|144<br>~~ee~~<br>~~GO~~|IND<br>~~ee~~|
|LCMXO2-1200ZE-2TG144IR14<br>~~po~~<br>~~po~~<br>~~po~~|1280<br>~~Ge~~<br>~~po~~|1.2 V<br>~~Ge~~<br>~~po~~|–2<br>~~Ge ~~<br>~~po~~|Halogen-Free TQFP<br> ~~GO~~<br>~~po~~|144<br>~~GO~~<br>~~po~~|IND<br>~~po~~|
|LCMXO2-1200ZE-3TG144IR14<br>~~po~~|1280|1.2 V|–3|Halogen-Free TQFP|144|IND|
1. This part number has a tape and reel quantity of 5,000 units with a minimum order quantity of 10,000 units. Order quantities must be in increments of 5,000 units. For example, a 10,000 unit order is shipped in two reels with one reel containing 5,000 units and the other reel with less than 5,000 units (depending on test yields). Unserviced backlog is canceled.
2. This part number has a tape and reel quantity of 1,000 units with a minimum order quantity of 1,000. Order quantities must be in increments of 1,000 units. For example, a 5,000 unit order is shipped as 5 reels of 1000 units each.
3. This part number has a tape and reel quantity of 50 units with a minimum order quantity of 50. Order quantities must be in increments of 50 units. For example, a 1,000 unit order is shipped as 20 reels of 50 units each.
4. Specifications for the “LCMXO2-1200ZE-speed package IR1” are the same as the “LCMXO2-1200ZE-speed package I” devices respectively, except as specified in the R1 Device Specifications section of this data sheet.
© 2010-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02056-4.3
103
**MachXO2 Family Data Sheet Data Sheet**
## **5.2.5. High-Performance Industrial Grade Devices with Voltage Regulator, Halogen Free (RoHS) Packaging**
**Table 5.5. High-Performance Industrial Grade Devices with Voltage Regulator, Halogen Free (RoHS) Packaging**
|**Part Number**<br>~~pO~~<br>~~eG~~|**LUTs**<br>~~eG~~|**Supply Voltage**<br>~~GG~~|**Speed**<br>~~GG~~|**Package**<br>~~GG~~|**Leads**|**Temp.**|
|---|---|---|---|---|---|---|
|LCMXO2-256HC-4SG32I<br>~~pO~~<br>~~eG~~<br>~~eG~~|256<br>~~eG~~<br>~~eG~~|2.5 V / 3.3 V<br>~~GG~~<br>~~GG~~|–4<br>~~GG~~<br>~~GG~~|Halogen-Free QFN<br>~~GG~~<br>~~GG~~|32|IND|
|LCMXO2-256HC-5SG32I<br>~~eG~~<br>~~eG~~<br>~~po~~|256<br>~~eG~~<br>~~eG~~|2.5 V / 3.3 V<br>~~GG~~<br>~~GG~~|–5<br>~~GG~~<br>~~GG~~|Halogen-Free QFN<br>~~GG~~<br>~~GG~~|32|IND|
|LCMXO2-256HC-6SG32I<br>~~eG~~<br>~~po~~<br>~~po~~|256<br>~~eG~~|2.5 V / 3.3 V<br>~~GG~~|–6<br>~~GG~~|Halogen-Free QFN<br>~~GG~~|32|IND|
|LCMXO2-256HC-4SG48I<br>~~po~~<br>~~po~~<br>~~eG~~|256<br>~~eG~~|2.5 V / 3.3 V<br>~~GG~~|–4<br>~~GG~~|Halogen-Free QFN<br>~~GG~~|48|IND|
|LCMXO2-256HC-5SG48I<br>~~po~~<br>~~eG~~<br>~~eG~~|256<br>~~eG~~<br>~~eG~~|2.5 V / 3.3 V<br>~~GG~~<br>~~GG~~|–5<br>~~GG~~<br>~~GG~~|Halogen-Free QFN<br>~~GG~~<br>~~GG~~|48|IND|
|LCMXO2-256HC-6SG48I<br>~~eG~~<br>~~eG~~<br>~~po~~|256<br>~~eG~~<br>~~eG~~|2.5 V / 3.3 V<br>~~GG~~<br>~~GG~~|–6<br>~~GG~~<br>~~GG~~|Halogen-Free QFN<br>~~GG~~<br>~~GG~~|48|IND|
|LCMXO2-256HC-4UMG64I<br>~~eG~~<br>~~po~~<br>~~po~~|256<br>~~eG~~|2.5 V / 3.3 V<br>~~GG~~|–4<br>~~GG~~|Halogen-Free ucBGA<br>~~GG~~|64|IND|
|LCMXO2-256HC-5UMG64I<br>~~po~~<br>~~po~~<br>~~po~~|256|2.5 V / 3.3 V|–5|Halogen-Free ucBGA|64|IND|
|LCMXO2-256HC-6UMG64I<br>~~po~~<br>~~po~~<br>~~po~~|256|2.5 V / 3.3 V|–6|Halogen-Free ucBGA|64|IND|
|LCMXO2-256HC-4TG100I<br>~~po~~<br>~~po~~<br>~~eG~~|256<br>~~eG~~|2.5 V / 3.3 V<br>~~GG~~|–4<br>~~GG~~|Halogen-Free TQFP<br>~~GG~~|100|IND|
|LCMXO2-256HC-5TG100I<br>~~po~~<br>~~eG~~<br>~~po~~|256<br>~~eG~~|2.5 V / 3.3 V<br>~~GG~~|–5<br>~~GG~~|Halogen-Free TQFP<br>~~GG~~|100|IND|
|LCMXO2-256HC-6TG100I<br>~~eG~~<br>~~po~~<br>~~po~~|256<br>~~eG~~|2.5 V / 3.3 V<br>~~GG~~|–6<br>~~GG~~|Halogen-Free TQFP<br>~~GG~~|100|IND|
|LCMXO2-256HC-4MG132I<br>~~po~~<br>~~po~~<br>~~po~~|256|2.5 V / 3.3 V|–4|Halogen-Free csBGA|132|IND|
|LCMXO2-256HC-5MG132I<br>~~po~~<br>~~po~~<br>~~po~~|256|2.5 V / 3.3 V|–5|Halogen-Free csBGA|132|IND|
|LCMXO2-256HC-6MG132I<br>~~po~~<br>~~po~~<br>~~eG~~|256<br>~~eG~~|2.5 V / 3.3 V<br>~~GG~~|–6<br>~~GG~~|Halogen-Free csBGA<br>~~GG~~|132|IND|
|LCMXO2-640HC-4SG48I<br>~~po~~<br>~~eG~~<br>~~po~~|640<br>~~eG~~|2.5 V / 3.3 V<br>~~GG~~|–4<br>~~GG~~|Halogen-Free QFN<br>~~GG~~|48|IND|
|LCMXO2-640HC-5SG48I<br>~~eG~~<br>~~po~~<br>~~po~~|640<br>~~eG~~|2.5 V / 3.3 V<br>~~GG~~|–5<br>~~GG~~|Halogen-Free QFN<br>~~GG~~|48|IND|
|LCMXO2-640HC-6SG48I<br>~~po~~<br>~~po~~<br>~~po~~|640|2.5 V / 3.3 V|–6|Halogen-Free QFN|48|IND|
|LCMXO2-640HC-4TG100I<br>~~po~~<br>~~po~~<br>~~po~~|640|2.5 V / 3.3 V|–4|Halogen-Free TQFP|100|IND|
|LCMXO2-640HC-5TG100I<br>~~po~~<br>~~po~~<br>~~pO~~|640|2.5 V / 3.3 V|–5|Halogen-Free TQFP|100|IND|
|LCMXO2-640HC-6TG100I<br>~~po~~<br>~~pO~~<br>~~pO~~|640|2.5 V / 3.3 V|–6|Halogen-Free TQFP|100|IND|
|LCMXO2-640HC-4MG132I<br>~~pO~~<br>~~pO~~<br>~~po~~|640|2.5 V / 3.3 V|–4|Halogen-Free csBGA|132|IND|
|LCMXO2-640HC-5MG132I<br>~~pO~~<br>~~po~~<br>~~po~~|640|2.5 V / 3.3 V|–5|Halogen-Free csBGA|132|IND|
|LCMXO2-640HC-6MG132I<br>~~po~~<br>~~po~~<br>~~po~~|640|2.5 V / 3.3 V|–6|Halogen-Free csBGA|132|IND|
|LCMXO2-640UHC-4TG144I<br>~~po~~<br>~~po~~<br>~~pO~~|640|2.5 V / 3.3 V|–4|Halogen-Free TQFP|144|IND|
|LCMXO2-640UHC-5TG144I<br>~~po~~<br>~~pO~~<br>~~pO~~|640|2.5 V / 3.3 V|–5|Halogen-Free TQFP|144|IND|
|LCMXO2-640UHC-6TG144I<br>~~pO~~<br>~~pO~~<br>~~po~~|640|2.5 V / 3.3 V|–6|Halogen-Free TQFP|144|IND|
|LCMXO2-1200HC-4SG32I<br>~~pO~~<br>~~po~~<br>~~po~~|1280|2.5 V / 3.3 V|–4|Halogen-Free QFN|32|IND|
|LCMXO2-1200HC-5SG32I<br>~~po~~<br>~~po~~<br>~~po~~|1280|2.5 V / 3.3 V|–5|Halogen-Free QFN|32|IND|
|LCMXO2-1200HC-6SG32I<br>~~po~~<br>~~po~~<br>~~po~~|1280|2.5 V / 3.3 V|–6|Halogen-Free QFN|32|IND|
|LCMXO2-1200HC-4TG100I<br>~~po~~<br>~~po~~<br>~~po~~|1280|2.5 V / 3.3 V|–4|Halogen-Free TQFP|100|IND|
|LCMXO2-1200HC-5TG100I<br>~~po~~<br>~~po~~<br>~~eG~~|1280<br>~~eG~~|2.5 V / 3.3 V<br>~~GG~~|–5<br>~~GG~~|Halogen-Free TQFP<br>~~GG~~|100|IND|
|LCMXO2-1200HC-6TG100I<br>~~po~~<br>~~eG~~<br>~~pO~~|1280<br>~~eG~~|2.5 V / 3.3 V<br>~~GG~~|–6<br>~~GG~~|Halogen-Free TQFP<br>~~GG~~|100|IND|
|LCMXO2-1200HC-4MG132I<br>~~eG~~<br>~~pO~~|1280<br>~~eG~~|2.5 V / 3.3 V<br>~~GG~~|–4<br>~~GG~~|Halogen-Free csBGA<br>~~GG~~|132|IND|
|LCMXO2-1200HC-5MG132I<br>~~pO~~<br>~~pf~~<br>~~po~~|1280<br>~~pf~~|2.5 V / 3.3 V<br>~~pf~~|–5<br>~~pf~~|Halogen-Free csBGA<br>~~pf~~|132<br>~~pf~~|IND<br>~~pf~~|
|LCMXO2-1200HC-6MG132I<br>~~pf~~<br>~~po~~<br>~~eG~~|1280<br>~~pf~~<br>~~eG~~|2.5 V / 3.3 V<br>~~pf~~<br>~~GG~~|–6<br>~~pf~~<br>~~GG~~|Halogen-Free csBGA<br>~~pf~~<br>~~GG~~|132<br>~~pf~~|IND<br>~~pf~~|
|LCMXO2-1200HC-4TG144I<br>~~po~~<br>~~eG~~<br>~~pO~~|1280<br>~~eG~~|2.5 V / 3.3 V<br>~~GG~~|–4<br>~~GG~~|Halogen-Free TQFP<br>~~GG~~|144|IND|
|LCMXO2-1200HC-5TG144I<br>~~eG~~<br>~~pO~~<br>~~pO~~|1280<br>~~eG~~|2.5 V / 3.3 V<br>~~GG~~|–5<br>~~GG~~|Halogen-Free TQFP<br>~~GG~~|144|IND|
|LCMXO2-1200HC-6TG144I<br>~~pO~~<br>~~pO~~<br>~~pO~~|1280|2.5 V/ 3.3 V|–6|Halogen-Free TQFP|144|IND|
|LCMXO2-1200UHC-4FTG256I<br>~~pO~~<br>~~pO~~|1280|2.5 V / 3.3 V|–4|Halogen-Free ftBGA|256|IND|
|LCMXO2-1200UHC-5FTG256I<br>~~pO~~<br>~~pf~~<br>~~po~~|1280<br>~~pf~~|2.5 V / 3.3 V<br>~~pf~~|–5<br>~~pf~~|Halogen-Free ftBGA<br>~~pf~~|256<br>~~pf~~|IND<br>~~pf~~|
|LCMXO2-1200UHC-6FTG256I<br>~~pf~~<br>~~po~~<br>~~po~~|1280<br>~~pf~~|2.5 V / 3.3 V<br>~~pf~~|–6<br>~~pf~~|Halogen-Free ftBGA<br>~~pf~~|256<br>~~pf~~|IND<br>~~pf~~|
|LCMXO2-2000HC-4TG100I<br>~~po~~<br>~~po~~|2112|2.5 V / 3.3 V|–4|Halogen-Free TQFP|100|IND|
© 2010-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
104
FPGA-DS-02056-4.3
**MachXO2 Family Data Sheet Data Sheet**
|**Part Number**<br>~~pO~~<br>~~po~~|**LUTs**|**Supply Voltage**|**Speed**|**Package**|**Leads**|**Temp.**|
|---|---|---|---|---|---|---|
|LCMXO2-2000HC-5TG100I<br>~~pO~~<br>~~po~~<br>~~eG~~|2112<br>~~eG~~|2.5 V / 3.3 V<br>~~GG~~|–5<br>~~GG~~|Halogen-Free TQFP<br>~~GG~~|100|IND|
|LCMXO2-2000HC-6TG100I<br>~~po~~<br>~~eG~~<br>~~pO~~|2112<br>~~eG~~|2.5 V / 3.3 V<br>~~GG~~|–6<br>~~GG~~|Halogen-Free TQFP<br>~~GG~~|100|IND|
|LCMXO2-2000HC-4MG132I<br>~~eG~~<br>~~pO~~<br>~~po~~|2112<br>~~eG~~|2.5 V / 3.3 V<br>~~GG~~|–4<br>~~GG~~|Halogen-Free csBGA<br>~~GG~~|132|IND|
|LCMXO2-2000HC-5MG132I<br>~~pO~~<br>~~po~~<br>~~po~~|2112|2.5 V / 3.3 V|–5|Halogen-Free csBGA|132|IND|
|LCMXO2-2000HC-6MG132I<br>~~po~~<br>~~po~~<br>~~eG~~|2112<br>~~eG~~|2.5 V / 3.3 V<br>~~GG~~|–6<br>~~GG~~|Halogen-Free csBGA<br>~~GG~~|132|IND|
|LCMXO2-2000HC-4TG144I<br>~~po~~<br>~~eG~~<br>~~pO~~|2112<br>~~eG~~|2.5 V / 3.3 V<br>~~GG~~|–4<br>~~GG~~|Halogen-Free TQFP<br>~~GG~~|144|IND|
|LCMXO2-2000HC-5TG144I<br>~~eG~~<br>~~pO~~<br>~~pO~~|2112<br>~~eG~~|2.5 V / 3.3 V<br>~~GG~~|–5<br>~~GG~~|Halogen-Free TQFP<br>~~GG~~|144|IND|
|LCMXO2-2000HC-6TG144I<br>~~pO~~<br>~~pO~~<br>~~po~~|2112|2.5 V / 3.3 V|–6|Halogen-Free TQFP|144|IND|
|LCMXO2-2000HC-4BG256I<br>~~pO~~<br>~~po~~<br>~~po~~|2112|2.5 V / 3.3 V|–4|Halogen-Free caBGA|256|IND|
|LCMXO2-2000HC-5BG256I<br>~~po~~<br>~~po~~<br>~~po~~|2112|2.5 V / 3.3 V|–5|Halogen-Free caBGA|256|IND|
|LCMXO2-2000HC-6BG256I<br>~~po~~<br>~~po~~<br>~~po~~|2112|2.5 V / 3.3 V|–6|Halogen-Free caBGA|256|IND|
|LCMXO2-2000HC-4FTG256I<br>~~po~~<br>~~po~~<br>~~po~~|2112|2.5 V / 3.3 V|–4|Halogen-Free ftBGA|256|IND|
|LCMXO2-2000HC-5FTG256I<br>~~po~~<br>~~po~~<br>~~po~~|2112|2.5 V / 3.3 V|–5|Halogen-Free ftBGA|256|IND|
|LCMXO2-2000HC-6FTG256I<br>~~po~~<br>~~po~~<br>~~eG~~|2112<br>~~eG~~|2.5 V / 3.3 V<br>~~GG~~|–6<br>~~GG~~|Halogen-Free ftBGA<br>~~GG~~|256|IND|
|LCMXO2-2000UHC-4FG484I<br>~~po~~<br>~~eG~~<br>~~po~~|2112<br>~~eG~~|2.5 V / 3.3 V<br>~~GG~~|–4<br>~~GG~~|Halogen-Free fpBGA<br>~~GG~~|484|IND|
|LCMXO2-2000UHC-5FG484I<br>~~eG~~<br>~~po~~<br>~~po~~|2112<br>~~eG~~|2.5 V / 3.3 V<br>~~GG~~|–5<br>~~GG~~|Halogen-Free fpBGA<br>~~GG~~|484|IND|
|LCMXO2-2000UHC-6FG484I<br>~~po~~<br>~~po~~<br>~~po~~|2112|2.5 V / 3.3 V|–6|Halogen-Free fpBGA|484|IND|
|LCMXO2-4000HC-4QN84I<br>~~po~~<br>~~po~~<br>~~po~~|4320|2.5 V / 3.3 V|–4|Halogen-Free QFN|84|IND|
|LCMXO2-4000HC-5QN84I<br>~~po~~<br>~~po~~<br>~~eG~~|4320<br>~~eG~~|2.5 V / 3.3 V<br>~~GG~~|–5<br>~~GG~~|Halogen-Free QFN<br>~~GG~~|84|IND|
|LCMXO2-4000HC-6QN84I<br>~~po~~<br>~~eG~~<br>~~po~~|4320<br>~~eG~~|2.5 V / 3.3 V<br>~~GG~~|–6<br>~~GG~~|Halogen-Free QFN<br>~~GG~~|84|IND|
|LCMXO2-4000HC-4TG144I<br>~~eG~~<br>~~po~~<br>~~po~~|4320<br>~~eG~~|2.5 V / 3.3 V<br>~~GG~~|–4<br>~~GG~~|Halogen-Free TQFP<br>~~GG~~|144|IND|
|LCMXO2-4000HC-5TG144I<br>~~po~~<br>~~po~~<br>~~po~~|4320|2.5 V / 3.3 V|–5|Halogen-Free TQFP|144|IND|
|LCMXO2-4000HC-6TG144I<br>~~po~~<br>~~po~~<br>~~po~~|4320|2.5 V / 3.3 V|–6|Halogen-Free TQFP|144|IND|
|LCMXO2-4000HC-4MG132I<br>~~po~~<br>~~po~~|4320|2.5 V / 3.3 V|–4|Halogen-Free csBGA|132|IND|
|LCMXO2-4000HC-5MG132I<br>~~po~~<br>~~pO~~|4320<br>~~pO~~|2.5 V / 3.3 V<br>~~pO~~|–5<br>~~pO~~|Halogen-Free csBGA<br>~~pO~~|132<br>~~pO~~|IND<br>~~pO~~|
|LCMXO2-4000HC-6MG132I<br>~~pO~~|4320<br>~~pO~~|2.5 V / 3.3 V<br>~~pO~~|–6<br>~~pO~~|Halogen-Free csBGA<br>~~pO~~|132<br>~~pO~~|IND<br>~~pO~~|
|LCMXO2-4000HC-4BG256I<br>~~pf~~|4320<br>~~pf~~|2.5 V / 3.3 V<br>~~pf~~|–4<br>~~pf~~|Halogen-Free caBGA<br>~~pf~~|256<br>~~pf~~|IND<br>~~pf~~|
|LCMXO2-4000HC-5BG256I<br>~~pf~~<br>~~Ge~~|4320<br>~~pf~~<br>~~Ge~~|2.5 V / 3.3 V<br>~~pf~~<br>~~GG~~|–5<br>~~pf~~<br>~~GG~~|Halogen-Free caBGA<br>~~pf~~<br>~~GG~~|256<br>~~pf~~|IND<br>~~pf~~|
|LCMXO2-4000HC-6BG256I<br>~~Ge~~<br>~~Ge~~|4320<br>~~Ge~~<br>~~Ge~~|2.5 V / 3.3 V<br>~~GG~~<br>~~GG~~|–6<br>~~GG~~<br>~~GG~~|Halogen-Free caBGA<br>~~GG~~<br>~~GG~~|256|IND|
|LCMXO2-4000HC-4FTG256I<br>~~Ge~~<br>~~Ge~~|4320<br>~~Ge~~<br>~~Ge~~|2.5 V / 3.3 V<br>~~GG~~<br>~~GG~~|–4<br>~~GG~~<br>~~GG~~|Halogen-Free ftBGA<br>~~GG~~<br>~~GG~~|256|IND|
|LCMXO2-4000HC-5FTG256I<br>~~pO~~|4320<br>~~pO~~|2.5 V / 3.3 V<br>~~pO~~|–5<br>~~pO~~|Halogen-Free ftBGA<br>~~pO~~|256<br>~~pO~~|IND<br>~~pO~~|
|LCMXO2-4000HC-6FTG256I<br>~~pO~~|4320<br>~~pO~~|2.5 V / 3.3 V<br>~~pO~~|–6<br>~~pO~~|Halogen-Free ftBGA<br>~~pO~~|256<br>~~pO~~|IND<br>~~pO~~|
|LCMXO2-4000HC-4BG332I<br>~~pf~~|4320<br>~~pf~~|2.5 V / 3.3 V<br>~~pf~~|–4<br>~~pf~~|Halogen-Free caBGA<br>~~pf~~|332<br>~~pf~~|IND<br>~~pf~~|
|LCMXO2-4000HC-5BG332I<br>~~pf~~<br>~~Ge~~|4320<br>~~pf~~<br>~~Ge~~|2.5 V / 3.3 V<br>~~pf~~<br>~~GG~~|–5<br>~~pf~~<br>~~GG~~|Halogen-Free caBGA<br>~~pf~~<br>~~GG~~|332<br>~~pf~~|IND<br>~~pf~~|
|LCMXO2-4000HC-6BG332I<br>~~Ge~~<br>~~Ge~~|4320<br>~~Ge~~<br>~~Ge~~|2.5 V / 3.3 V<br>~~GG~~<br>~~GG~~|–6<br>~~GG~~<br>~~GG~~|Halogen-Free caBGA<br>~~GG~~<br>~~GG~~|332|IND|
|LCMXO2-4000HC-4FG484I<br>~~pO~~<br>~~po~~|4320<br>~~pO~~|2.5 V / 3.3 V<br>~~pO~~|–4<br>~~pO~~|Halogen-Free fpBGA<br>~~pO~~|484<br>~~pO~~|IND<br>~~pO~~|
|LCMXO2-4000HC-5FG484I<br>~~po~~<br>~~pO~~|4320|2.5 V / 3.3 V|–5|Halogen-Free fpBGA|484|IND|
|LCMXO2-4000HC-6FG484I<br>~~po~~<br>~~pO~~<br>~~po~~|4320|2.5 V / 3.3 V|–6|Halogen-Free fpBGA|484|IND|
|LCMXO2-7000HC-4TG144I<br>~~pO~~<br>~~po~~<br>~~po~~|6864|2.5 V / 3.3 V|–4|Halogen-Free TQFP|144|IND|
|LCMXO2-7000HC-5TG144I<br>~~po~~<br>~~po~~|6864|2.5 V / 3.3 V|–5|Halogen-Free TQFP|144|IND|
|LCMXO2-7000HC-6TG144I<br>~~po~~<br>~~pO~~<br>~~po~~|6864<br>~~pO~~|2.5 V / 3.3 V<br>~~pO~~|–6<br>~~pO~~|Halogen-Free TQFP<br>~~pO~~|144<br>~~pO~~|IND<br>~~pO~~|
|LCMXO2-7000HC-4BG256I<br>~~po~~<br>~~po~~|6864|2.5 V / 3.3 V|–4|Halogen-Free caBGA|256|IND|
|LCMXO2-7000HC-5BG256I<br>~~po~~<br>~~po~~<br>~~pO~~|6864|2.5 V / 3.3 V|–5|Halogen-Free caBGA|256|IND|
|LCMXO2-7000HC-6BG256I<br>~~po~~<br>~~pO~~<br>~~po~~|6864|2.5 V / 3.3 V|–6|Halogen-Free caBGA|256|IND|
|LCMXO2-7000HC-4FTG256I<br>~~pO~~<br>~~po~~<br>~~po~~|6864|2.5 V / 3.3 V|–4|Halogen-Free ftBGA|256|IND|
|LCMXO2-7000HC-5FTG256I<br>~~po~~<br>~~po~~|6864|2.5 V / 3.3 V|–5|Halogen-Free ftBGA|256|IND|
© 2010-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02056-4.3
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**MachXO2 Family Data Sheet Data Sheet**
|**Part Number**<br>~~pO~~<br>~~eG~~|**LUTs**<br>~~eG~~|**Supply Voltage**<br>~~GG~~|**Speed**<br>~~GG~~|**Package**<br>~~GG~~|**Leads**|**Temp.**|
|---|---|---|---|---|---|---|
|LCMXO2-7000HC-6FTG256I<br>~~pO~~<br>~~eG~~<br>~~eG~~|6864<br>~~eG~~<br>~~eG~~|2.5 V / 3.3 V<br>~~GG~~<br>~~GG~~|–6<br>~~GG~~<br>~~GG~~|Halogen-Free ftBGA<br>~~GG~~<br>~~GG~~|256|IND|
|LCMXO2-7000HC-4BG332I<br>~~eG~~<br>~~eG~~<br>~~eG~~|6864<br>~~eG~~<br>~~eG~~<br>~~eG~~|2.5 V / 3.3 V<br>~~GG~~<br>~~GG~~<br>~~GG~~|–4<br>~~GG~~<br>~~GG~~<br>~~GG~~|Halogen-Free caBGA<br>~~GG~~<br>~~GG~~<br>~~GG~~|332|IND|
|LCMXO2-7000HC-5BG332I<br>~~eG~~<br>~~eG~~<br>~~po~~|6864<br>~~eG~~<br>~~eG~~|2.5 V / 3.3 V<br>~~GG~~<br>~~GG~~|–5<br>~~GG~~<br>~~GG~~|Halogen-Free caBGA<br>~~GG~~<br>~~GG~~|332|IND|
|LCMXO2-7000HC-6BG332I<br>~~eG~~<br>~~po~~<br>~~po~~|6864<br>~~eG~~|2.5 V / 3.3 V<br>~~GG~~|–6<br>~~GG~~|Halogen-Free caBGA<br>~~GG~~|332|IND|
|LCMXO2-7000HC-4FG400I<br>~~po~~<br>~~po~~<br>~~eG~~|6864<br>~~eG~~|2.5 V / 3.3 V<br>~~GG~~|–4<br>~~GG~~|Halogen-Free fpBGA<br>~~GG~~|400|IND|
|LCMXO2-7000HC-5FG400I<br>~~po~~<br>~~eG~~<br>~~eG~~|6864<br>~~eG~~<br>~~eG~~|2.5 V / 3.3 V<br>~~GG~~<br>~~GG~~|–5<br>~~GG~~<br>~~GG~~|Halogen-Free fpBGA<br>~~GG~~<br>~~GG~~|400|IND|
|LCMXO2-7000HC-6FG400I<br>~~eG~~<br>~~eG~~<br>~~eG~~|6864<br>~~eG~~<br>~~eG~~<br>~~eG~~|2.5 V / 3.3 V<br>~~GG~~<br>~~GG~~<br>~~GG~~|–6<br>~~GG~~<br>~~GG~~<br>~~GG~~|Halogen-Free fpBGA<br>~~GG~~<br>~~GG~~<br>~~GG~~|400|IND|
|LCMXO2-7000HC-4FG484I<br>~~eG~~<br>~~eG~~<br>~~po~~|6864<br>~~eG~~<br>~~eG~~|2.5 V / 3.3 V<br>~~GG~~<br>~~GG~~|–4<br>~~GG~~<br>~~GG~~|Halogen-Free fpBGA<br>~~GG~~<br>~~GG~~|484|IND|
|LCMXO2-7000HC-5FG484I<br>~~eG~~<br>~~po~~<br>~~po~~|6864<br>~~eG~~|2.5 V / 3.3 V<br>~~GG~~|–5<br>~~GG~~|Halogen-Free fpBGA<br>~~GG~~|484|IND|
|LCMXO2-7000HC-6FG484I<br>~~po~~<br>~~po~~|6864|2.5 V / 3.3 V|–6|Halogen-Free fpBGA|484|IND|
|LCMXO2-1200HC-4TG100IR1<br>~~po~~<br>~~Ge~~<br>~~po~~|1280<br>~~Ge~~|2.5 V / 3.3 V<br>~~GG~~|–4<br>~~GG~~|Halogen-Free TQFP<br>~~GG~~|100|IND|
|LCMXO2-1200HC-5TG100IR1<br>~~po~~<br>~~po~~|1280|2.5 V / 3.3 V|–5|Halogen-Free TQFP|100|IND|
|LCMXO2-1200HC-6TG100IR1<br>~~po~~<br>~~po~~<br>~~po~~|1280|2.5 V / 3.3 V|–6|Halogen-Free TQFP|100|IND|
|LCMXO2-1200HC-4MG132IR1<br>~~po~~<br>~~po~~<br>~~po~~|1280|2.5 V / 3.3 V|–4|Halogen-Free csBGA|132|IND|
|LCMXO2-1200HC-5MG132IR1<br>~~po~~<br>~~po~~<br>~~po~~|1280|2.5 V / 3.3 V|–5|Halogen-Free csBGA|132|IND|
|LCMXO2-1200HC-6MG132IR1<br>~~po~~<br>~~po~~<br>~~eG~~|1280<br>~~eG~~|2.5 V / 3.3 V<br>~~GG~~|–6<br>~~GG~~|Halogen-Free csBGA<br>~~GG~~|132|IND|
|LCMXO2-1200HC-4TG144IR1<br>~~po~~<br>~~eG~~<br>~~po~~|1280<br>~~eG~~|2.5 V / 3.3 V<br>~~GG~~|–4<br>~~GG~~|Halogen-Free TQFP<br>~~GG~~|144|IND|
|LCMXO2-1200HC-5TG144IR1<br>~~eG~~<br>~~po~~<br>~~po~~|1280<br>~~eG~~|2.5 V / 3.3 V<br>~~GG~~|–5<br>~~GG~~|Halogen-Free TQFP<br>~~GG~~|144|IND|
|LCMXO2-1200HC-6TG144IR1<br>~~po~~<br>~~po~~|1280|2.5 V / 3.3 V|–6|Halogen-Free TQFP|144|IND|
1. Specifications for the “LCMXO2-1200HC-speed package IR1” are the same as the “LCMXO2-1200ZE-speed package I” devices respectively, except as specified in the R1 Device Specifications section of this data sheet.
© 2010-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
106
FPGA-DS-02056-4.3
**MachXO2 Family Data Sheet Data Sheet**
## **5.2.6. High Performance Industrial Grade Devices Without Voltage Regulator, Halogen Free (RoHS) Packaging**
**Table 5.6. High Performance Industrial Grade Devices Without Voltage Regulator, Halogen Free (RoHS) Packaging**
|**Part Number**<br>~~pO~~<br>~~eG~~|**LUTs**<br>~~eG~~|**Supply Voltage**<br>~~GG~~|**Speed**<br>~~GG~~|**Package**<br>~~GG~~|**Leads**|**Temp.**|
|---|---|---|---|---|---|---|
|LCMXO2-2000HE-4TG100I<br>~~pO~~<br>~~eG~~<br>~~pO~~|2112<br>~~eG~~|1.2 V<br>~~GG~~|–4<br>~~GG~~|Halogen-Free TQFP<br>~~GG~~|100|IND|
|LCMXO2-2000HE-5TG100I<br>~~eG~~<br>~~pO~~<br>~~po~~|2112<br>~~eG~~|1.2 V<br>~~GG~~|–5<br>~~GG~~|Halogen-Free TQFP<br>~~GG~~|100|IND|
|LCMXO2-2000HE-6TG100I<br>~~pO~~<br>~~po~~<br>~~po~~|2112|1.2 V|–6|Halogen-Free TQFP|100|IND|
|LCMXO2-2000HE-4MG132I<br>~~po~~<br>~~po~~<br>~~eG~~|2112<br>~~eG~~|1.2 V<br>~~GG~~|–4<br>~~GG~~|Halogen-Free csBGA<br>~~GG~~|132|IND|
|LCMXO2-2000HE-5MG132I<br>~~po~~<br>~~eG~~<br>~~pO~~|2112<br>~~eG~~|1.2 V<br>~~GG~~|–5<br>~~GG~~|Halogen-Free csBGA<br>~~GG~~|132|IND|
|LCMXO2-2000HE-6MG132I<br>~~eG~~<br>~~pO~~<br>~~pO~~|2112<br>~~eG~~|1.2 V<br>~~GG~~|–6<br>~~GG~~|Halogen-Free csBGA<br>~~GG~~|132|IND|
|LCMXO2-2000HE-4TG144I<br>~~pO~~<br>~~pO~~|2112|1.2 V|–4|Halogen-Free TQFP|144|IND|
|LCMXO2-2000HE-5TG144I<br>~~pO~~<br>~~po~~<br>~~po~~|2112<br>~~po~~|1.2 V<br>~~po~~|–5<br>~~po~~|Halogen-Free TQFP<br>~~po~~|144<br>~~po~~|IND<br>~~po~~|
|LCMXO2-2000HE-6TG144I<br>~~po~~<br>~~po~~|2112|1.2 V|–6|Halogen-Free TQFP|144|IND|
|LCMXO2-2000HE-4BG256I<br>~~po~~<br>~~po~~<br>~~po~~|2112|1.2 V|–4|Halogen-Free caBGA|256|IND|
|LCMXO2-2000HE-5BG256I<br>~~po~~<br>~~po~~<br>~~po~~|2112|1.2 V|–5|Halogen-Free caBGA|256|IND|
|LCMXO2-2000HE-6BG256I<br>~~po~~<br>~~po~~<br>~~eG~~|2112<br>~~eG~~|1.2 V<br>~~GG~~|–6<br>~~GG~~|Halogen-Free caBGA<br>~~GG~~|256|IND|
|LCMXO2-2000HE-4FTG256I<br>~~po~~<br>~~eG~~<br>~~po~~|2112<br>~~eG~~|1.2 V<br>~~GG~~|–4<br>~~GG~~|Halogen-Free ftBGA<br>~~GG~~|256|IND|
|LCMXO2-2000HE-5FTG256I<br>~~eG~~<br>~~po~~<br>~~po~~|2112<br>~~eG~~|1.2 V<br>~~GG~~|–5<br>~~GG~~|Halogen-Free ftBGA<br>~~GG~~|256|IND|
|LCMXO2-2000HE-6FTG256I<br>~~po~~<br>~~po~~<br>~~po~~|2112|1.2 V|–6|Halogen-Free ftBGA|256|IND|
|LCMXO2-2000UHE-4FG484I<br>~~po~~<br>~~po~~<br>~~po~~|2112|1.2 V|–4|Halogen-Free fpBGA|484|IND|
|LCMXO2-2000UHE-5FG484I<br>~~po~~<br>~~po~~<br>~~po~~|2112|1.2 V|–5|Halogen-Free fpBGA|484|IND|
|LCMXO2-2000UHE-6FG484I<br>~~po~~<br>~~po~~|2112|1.2 V|–6|Halogen-Free fpBGA|484|IND|
|LCMXO2-4000HE-4MG132I<br>~~po~~<br>~~Se~~<br>~~po~~|4320<br>~~Se~~|1.2 V<br>~~GG~~|–4<br>~~GG~~|Halogen-Free csBGA<br>~~GG~~|132|IND|
|LCMXO2-4000HE-5MG132I<br>~~po~~|4320|1.2 V|–5|Halogen-Free csBGA|132|IND|
|LCMXO2-4000HE-6MG132I<br>~~po~~<br>~~pf~~|4320<br>~~pf~~|1.2 V<br>~~pf~~|–6<br>~~pf~~|Halogen-Free csBGA<br>~~pf~~|132<br>~~pf~~|IND<br>~~pf~~|
|LCMXO2-4000HE-4TG144I<br>~~pf~~<br>~~Ge~~|4320<br>~~pf~~<br>~~Ge~~|1.2 V<br>~~pf~~<br>~~GG~~|–4<br>~~pf~~<br>~~GG~~|Halogen-Free TQFP<br>~~pf~~<br>~~GG~~|144<br>~~pf~~|IND<br>~~pf~~|
|LCMXO2-4000HE-5TG144I<br>~~Ge~~<br>~~Ge~~|4320<br>~~Ge~~<br>~~Ge~~|1.2 V<br>~~GG~~<br>~~GG~~|–5<br>~~GG~~<br>~~GG~~|Halogen-Free TQFP<br>~~GG~~<br>~~GG~~|144|IND|
|LCMXO2-4000HE-6TG144I<br>~~pO~~|4320<br>~~pO~~|1.2 V<br>~~pO~~|–6<br>~~pO~~|Halogen-Free TQFP<br>~~pO~~|144<br>~~pO~~|IND<br>~~pO~~|
|LCMXO2-4000HE-4MG184I<br>~~pO~~|4320<br>~~pO~~|1.2 V<br>~~pO~~|–4<br>~~pO~~|Halogen-Free csBGA<br>~~pO~~|184<br>~~pO~~|IND<br>~~pO~~|
|LCMXO2-4000HE-5MG184I<br>~~pf~~|4320<br>~~pf~~|1.2 V<br>~~pf~~|–5<br>~~pf~~|Halogen-Free csBGA<br>~~pf~~|184<br>~~pf~~|IND<br>~~pf~~|
|LCMXO2-4000HE-6MG184I<br>~~pf~~<br>~~Ge~~|4320<br>~~pf~~<br>~~Ge~~|1.2 V<br>~~pf~~<br>~~GG~~|–6<br>~~pf~~<br>~~GG~~|Halogen-Free csBGA<br>~~pf~~<br>~~GG~~|184<br>~~pf~~|IND<br>~~pf~~|
|LCMXO2-4000HE-4BG256I<br>~~Ge~~<br>~~Ge~~|4320<br>~~Ge~~<br>~~Ge~~|1.2 V<br>~~GG~~<br>~~GG~~|–4<br>~~GG~~<br>~~GG~~|Halogen-Free caBGA<br>~~GG~~<br>~~GG~~|256|IND|
|LCMXO2-4000HE-5BG256I<br>~~pO~~|4320<br>~~pO~~|1.2 V<br>~~pO~~|–5<br>~~pO~~|Halogen-Free caBGA<br>~~pO~~|256<br>~~pO~~|IND<br>~~pO~~|
|LCMXO2-4000HE-6BG256I<br>~~pO~~<br>~~pO~~|4320<br>~~pO~~|1.2 V<br>~~pO~~|–6<br>~~pO~~|Halogen-Free caBGA<br>~~pO~~|256<br>~~pO~~|IND<br>~~pO~~|
|LCMXO2-4000HE-4FTG256I<br>~~pO~~|4320|1.2 V|–4|Halogen-Free ftBGA|256|IND|
|LCMXO2-4000HE-5FTG256I<br>~~pO~~<br>~~GG~~<br>~~po~~|4320<br>~~GG~~|1.2 V<br>~~GG~~|–5<br>~~GG~~|Halogen-Free ftBGA<br>~~GG~~|256<br>~~GG~~|IND<br>~~GG~~|
|LCMXO2-4000HE-6FTG256I<br>~~GG~~<br>~~po~~|4320<br>~~GG~~|1.2 V<br>~~GG~~|–6<br>~~GG~~|Halogen-Free ftBGA<br>~~GG~~|256<br>~~GG~~|IND<br>~~GG~~|
|LCMXO2-4000HE-4BG332I<br>~~po~~<br>~~pO~~<br>~~po~~|4320<br>~~pO~~|1.2 V<br>~~pO~~|–4<br>~~pO~~|Halogen-Free caBGA<br>~~pO~~|332<br>~~pO~~|IND<br>~~pO~~|
|LCMXO2-4000HE-5BG332I<br>~~po~~<br>~~po~~|4320|1.2 V|–5|Halogen-Free caBGA|332|IND|
|LCMXO2-4000HE-6BG332I<br>~~po~~<br>~~po~~<br>~~pO~~|4320|1.2 V|–6|Halogen-Free caBGA|332|IND|
|LCMXO2-4000HE-4FG484I<br>~~po~~<br>~~pO~~<br>~~po~~|4320|1.2 V|–4|Halogen-Free fpBGA|484|IND|
|LCMXO2-4000HE-5FG484I<br>~~pO~~<br>~~po~~|4320|1.2 V|–5|Halogen-Free fpBGA|484|IND|
|LCMXO2-4000HE-6FG484I<br>~~po~~<br>~~pO~~<br>~~po~~|4320<br>~~pO~~|1.2 V<br>~~pO~~|–6<br>~~pO~~|Halogen-Free fpBGA<br>~~pO~~|484<br>~~pO~~|IND<br>~~pO~~|
|LCMXO2-7000HE-4TG144I<br>~~po~~<br>~~pO~~|6864|1.2 V|–4|Halogen-Free TQFP|144|IND|
|LCMXO2-7000HE-5TG144I<br>~~po~~<br>~~pO~~<br>~~po~~|6864|1.2 V|–5|Halogen-Free TQFP|144|IND|
|LCMXO2-7000HE-6TG144I<br>~~pO~~<br>~~po~~|6864|1.2 V|–6|Halogen-Free TQFP|144|IND|
|LCMXO2-7000HE-4BG256I<br>~~po~~<br>~~po~~|6864<br>~~po~~|1.2 V<br>~~po~~|–4<br>~~po~~|Halogen-Free caBGA<br>~~po~~|256<br>~~po~~|IND<br>~~po~~|
© 2010-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02056-4.3
107
**MachXO2 Family Data Sheet Data Sheet**
|**Part Number**<br>~~pO~~<br>~~eG~~|**LUTs**<br>~~eG~~|**Supply Voltage**<br>~~GG~~|**Speed**<br>~~GG~~|**Package**<br>~~GG~~|**Leads**|**Temp.**|
|---|---|---|---|---|---|---|
|LCMXO2-7000HE-5BG256I<br>~~pO~~<br>~~eG~~<br>~~eG~~|6864<br>~~eG~~<br>~~eG~~|1.2 V<br>~~GG~~<br>~~GG~~|–5<br>~~GG~~<br>~~GG~~|Halogen-Free caBGA<br>~~GG~~<br>~~GG~~|256|IND|
|LCMXO2-7000HE-6BG256I<br>~~eG~~<br>~~eG~~<br>~~eG~~|6864<br>~~eG~~<br>~~eG~~<br>~~eG~~|1.2 V<br>~~GG~~<br>~~GG~~<br>~~GG~~|–6<br>~~GG~~<br>~~GG~~<br>~~GG~~|Halogen-Free caBGA<br>~~GG~~<br>~~GG~~<br>~~GG~~|256|IND|
|LCMXO2-7000HE-4FTG256I<br>~~eG~~<br>~~eG~~<br>~~po~~|6864<br>~~eG~~<br>~~eG~~|1.2 V<br>~~GG~~<br>~~GG~~|–4<br>~~GG~~<br>~~GG~~|Halogen-Free ftBGA<br>~~GG~~<br>~~GG~~|256|IND|
|LCMXO2-7000HE-5FTG256I<br>~~eG~~<br>~~po~~<br>~~po~~|6864<br>~~eG~~|1.2 V<br>~~GG~~|–5<br>~~GG~~|Halogen-Free ftBGA<br>~~GG~~|256|IND|
|LCMXO2-7000HE-6FTG256I<br>~~po~~<br>~~po~~<br>~~eG~~|6864<br>~~eG~~|1.2 V<br>~~GG~~|–6<br>~~GG~~|Halogen-Free ftBGA<br>~~GG~~|256|IND|
|LCMXO2-7000HE-4BG332I<br>~~po~~<br>~~eG~~<br>~~eG~~|6864<br>~~eG~~<br>~~eG~~|1.2 V<br>~~GG~~<br>~~GG~~|–4<br>~~GG~~<br>~~GG~~|Halogen-Free caBGA<br>~~GG~~<br>~~GG~~|332|IND|
|LCMXO2-7000HE-5BG332I<br>~~eG~~<br>~~eG~~<br>~~eG~~|6864<br>~~eG~~<br>~~eG~~<br>~~eG~~|1.2 V<br>~~GG~~<br>~~GG~~<br>~~GG~~|–5<br>~~GG~~<br>~~GG~~<br>~~GG~~|Halogen-Free caBGA<br>~~GG~~<br>~~GG~~<br>~~GG~~|332|IND|
|LCMXO2-7000HE-6BG332I<br>~~eG~~<br>~~eG~~<br>~~po~~|6864<br>~~eG~~<br>~~eG~~|1.2 V<br>~~GG~~<br>~~GG~~|–6<br>~~GG~~<br>~~GG~~|Halogen-Free caBGA<br>~~GG~~<br>~~GG~~|332|IND|
|LCMXO2-7000HE-4FG484I<br>~~eG~~<br>~~po~~<br>~~po~~|6864<br>~~eG~~|1.2 V<br>~~GG~~|–4<br>~~GG~~|Halogen-Free fpBGA<br>~~GG~~|484|IND|
|LCMXO2-7000HE-5FG484I<br>~~po~~<br>~~po~~<br>~~po~~|6864|1.2 V|–5|Halogen-Free fpBGA|484|IND|
|LCMXO2-7000HE-6FG484I<br>~~po~~<br>~~po~~|6864|1.2 V|–6|Halogen-Free fpBGA|484|IND|
© 2010-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
108
FPGA-DS-02056-4.3
**MachXO2 Family Data Sheet Data Sheet**
## **5.2.7. High Performance Automotive Grade Devices Halogen Free (RoHS) Packaging**
**Table 5.7. High Performance Automotive Grade Devices Halogen Free (RoHS) Packaging**
|**Part Number**|**LUTs**|**Supply Voltage**|**Speed**|**Package**|**Leads**|**Temp.**|
|---|---|---|---|---|---|---|
|LAMXO2-256HC-5TG100E|256|2.5 V/3.3 V|–5|Halogen Free TQFP|100|AUTO|
|LAMXO2-256HC-5MG132E|256|2.5 V/3.3 V|–5|Halogen Free csBGA|132|AUTO|
|LAMXO2-640HC-5TG100E|640|2.5 V/3.3 V|–5|Halogen Free TQFP|100|AUTO|
|LAMXO2-640HC-5MG132E|640|2.5 V/3.3 V|–5|Halogen Free csBGA|132|AUTO|
© 2010-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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## **5.3. R1 Device Specifications**
The LCMXO2-1200ZE/HC “R1” devices have the same specifications as their Standard (non-R1) counterparts except as listed below. For more details on the R1 to Standard migration refer to Designing for Migration from MachXO2-1200-R1 to Standard Non-R1) Devices (FPGA-AN-02012).
- The User Flash Memory (UFM) cannot be programmed through the internal WISHBONE interface. It can still be programmed through the JTAG/SPI/I[2] C ports.
- The on-chip differential input termination resistor value is higher than intended. It is approximately 200 Ω as opposed to the intended 100 Ω. It is recommended to use external termination resistors for differential inputs. The on-chip termination resistors can be disabled through Lattice design software.
- Soft Error Detection logic may not produce the correct result when it is run for the first time after configuration. To use this feature, discard the result from the first operation. Subsequent operations produce the correct result.
- Under certain conditions, IIH exceeds data sheet specifications. The following table provides more details:
**Table 5.8. R1 Device Specifications**
|**Condition**|**Clamp**|**Pad Rising IIH**<br>**Max.**|**Pad Falling IIH**<br>**Min.**|**Steady State Pad**<br>**High IIH**|**Steady State Pad**<br>**Low IIL**|
|---|---|---|---|---|---|
|VPAD > VCCIO|OFF|1 mA|–1 mA|1 mA|10 µA|
|VPAD = VCCIO|ON|10 µA|–10 µA|10 µA|10 µA|
|VPAD = VCCIO|OFF|1 mA|–1 mA|1 mA|10 µA|
|VPAD < VCCIO|OFF|10 µA|–10 µA|10 µA|10 µA|
- The user SPI interface does not operate correctly in some situations. During master read access and slave write access, the last byte received does not generate the RRDY interrupt.
- In GDDRX2, GDDRX4 and GDDR71 modes, ECLKSYNC may have a glitch in the output under certain conditions, leading to possible loss of synchronization.
- When using the hard I[2] C IP core, the I[2] C status registers I2C_1_SR and I2C_2_SR may not update correctly.
- PLL Lock signal glitches high when coming out of standby. This glitch lasts for about 10 μsec before returning low.
- • Dual boot only available on HC devices, requires tying VCC and VCCIO2 to the same 3.3 V or 2.5 V supply.
© 2010-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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## **6. Supplemental Information**
A variety of technical notes for the MachXO2 family are available on the Lattice website.
- Power Estimation and Management for MachXO2 Devices (TN1198)
- MachXO2 sysCLOCK PLL Design and Usage Guide (FPGA-TN-02157)
- Memory Usage Guide for MachXO2 Devices (FPGA-TN-02159)
- MachXO2 sysI/O Usage Guide (FPGA-TN-02158)
- Implementing High-Speed Interfaces with MachXO2 Devices (FPGA-TN-02153)
- MachXO2 Programming and Configuration Usage Guide (FPGA-TN-02155)
- Using User Flash Memory and Hardened Control Functions in MachXO2 Devices (FPGA-TN-02162)
- MachXO2 SED Usage Guide (FPGA-TN-02156)
- Using TraceID in MachXO2 Devices (FPGA-TN-02084)
- PCB Layout Recommendations for BGA Packages (FPGA-TN-02024)
- Minimizing System Interruption During Configuration Using TransFR Technology (FPGA-TN-02198)
- MIPI D-PHY Bandwidth Matrix and Implementation (FPGA-TN-02090)
- Designing for Migration from MachXO2-1200-R1 to Standard (non-R1) Devices (FPGA-AN-02012)
- Boundary Scan Testability with Lattice sysIO Capability (AN8066)
- MachXO2 Device Pinout Files
- Thermal Management document (FPGA-TN-02044)
- Lattice design tools
Below are some useful links related to the MachXO2 family devices.
- MachXO2 Family Web Page
- Boards, Demos, IP Cores and Reference Designs for MachXO2 Family Devices
- Lattice Insights for Training Series and Learning Plans
For further information on interface standards, refer to the following web sites.
- JEDEC Standards (LVTTL, LVCMOS, LVDS, DDR, DDR2, LPDDR): www.jedec.org
- PCI: www.pcisig.com
© 2010-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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## **Technical Support Assistance**
Submit a technical support case through www.latticesemi.com/techsupport. For frequently asked questions, please refer to the Lattice Answer Database at www.latticesemi.com/Support/AnswerDatabase.
© 2010-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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## **Revision History**
## **Revision 4.3, November 2023**
|**Section**|**Change Summary**|
|---|---|
|Pinout Information|UpdatedTable 4.5. MachXO2-4000 Pin Summary. Updated the values of the 81 WLCSP for<br>the following:<br>•<br>General Purpose I/O per Bank:<br>•<br>Bank 0 – changed to 30<br>•<br>Total General Purpose Single Ended I/O – changed to 64<br>•<br>Differential I/O Bank<br>•<br>Bank 0 – changed to 15<br>•<br>Total General Purpose Differential I/O – changed to 31|
## **Revision 4.2, October 2023**
|**Section**|**Change Summary**|
|---|---|
|Disclaimers|Updated this section.|
|Introduction|•<br>Newly added theApplicationsection.<br>•<br>Table 1.1. MachXO2 Family Selection Guide:<br>•<br>newly added the_Automotive Qualified_feature row and pointed out MachXO2-256<br>and MachXO2-640 devices are automotive qualified;<br>•<br>added Note 10,_Package is available for automotive devices_;<br>•<br>attached Note 10 to the_100-pin TQFP_and_132-ball csBGA_packages of<br>MachXO2-256 and MachXO2-640 devices.|
|DC and Switching Characteristics|•<br>InTable 3.2. Recommended Operating Conditions1, newly added the symbol_tJAUTO_for<br>Junction Temperature Automotive Operation and provided its corresponding values.<br>•<br>UpdatedTable 3.3. Power Supply Ramp Rates1to include the_tRAMP IND/COM_and_tRAMP AUTO_<br>symbols and their corresponding Parameter and values.<br>•<br>In Note 1 ofTable 3.22. Register-to-Register Performance1,Table 3.26. MachXO2<br>External Switching Characteristics – HC/HE Devices1,2, 3, 4, 5, 6, 7, andTable 3.27.<br>MachXO2 External Switching Characteristics – ZE Devices1,2, 3, 4, 5, 6, 7, updated that<br>other operating conditions, including industrial and_automotive_, can be extracted from<br>the Diamond software.|
|Ordering Information|•<br>Figure 5.1. MachXO2 Part Number Description: <br>•<br>added_LAMXO2_in Device Family for automotive devices;<br>•<br>added_E = Automotive_in Grade.<br>•<br>Added new top-side marking figure for MachXO2 devices of Automotive grade.<br>•<br>Reorganized this section and changed the numbering of the following sub-sections:<br>•<br>changed previous_5.3. Ultra Low Power Industrial Grade Devices, Halogen Free_<br>_(RoHS) Packaging_to5.2.4 Ultra Low Power Industrial Grade Devices, Halogen Free<br>(RoHS) Packaging;<br>•<br>changed previous_5.3.1. High-Performance Industrial Grade Devices with Voltage_<br>_Regulator, Halogen Free (RoHS) Packaging_to5.2.5 High-Performance Industrial<br>Grade Devices with Voltage Regulator, Halogen Free (RoHS) Packaging;<br>•<br>changed previous_5.4. High Performance Industrial Grade Devices Without Voltage_<br>_Regulator, Halogen Free (RoHS) Packaging_to5.2.6 High Performance Industrial<br>Grade Devices Without Voltage Regulator, Halogen Free (RoHS) Packaging.<br>•<br>Newly added theHigh Performance Automotive Grade Devices Halogen Free (RoHS)<br>Packagingsection to include LAMXO2-256HC-5TG100E, LAMXO2-256HC-5MG132E,<br>LAMXO2-640HC-5TG100E, and LAMXO2-640HC-5MG132E OPNs.<br>•<br>Changed the header_Grade_to_Speed_in the following tables:<br>•<br>Table 5.1. Ultra Low Power Commercial Grade Devices, Halogen Free (RoHS)<br>Packaging;<br>•<br>Table 5.2. High-Performance Commercial Grade Devices with Voltage Regulator,|
© 2010-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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|**Section**|**Change Summary**|
|---|---|
||Halogen Free (RoHS) Packaging;<br>•<br>Table 5.3. High-Performance Commercial Grade Devices without Voltage<br>Regulator, Halogen Free (RoHS) Packaging;<br>•<br>Table 5.4. Ultra Low Power Industrial Grade Devices, Halogen Free (RoHS)<br>Packaging;<br>•<br>Table 5.5. High-Performance Industrial Grade Devices with Voltage Regulator,<br>Halogen Free (RoHS) Packaging;<br>•<br>Table 5.6. High Performance Industrial Grade Devices Without Voltage Regulator,<br>Halogen Free (RoHS) Packaging;<br>•<br>Table 5.7. High Performance Automotive Grade Devices Halogen Free(RoHS)Packaging.|
|Supplemental Information|Newly added the links toMachXO2 FamilyWeb Page,Boards, Demos, IP Cores and<br>Reference Designs for MachXO2 Family Devices, andLattice Insights for Training Series and<br>LearningPlans.|
## **Revision 4.1, March 2023**
|**Section**|**Change Summary**|
|---|---|
|Introduction|In Table 1.1. MachXO2 Family Selection Guide, changed the I/O number of the 144-pin TQFP<br>to_115_for both MachXO2-4000 and MachXO2-7000 devices.|
|Pinout Information|•<br>In Table 4.5. MachXO2-4000 Pin Summary:<br>•<br>changed the General Purpose I/O number in Bank 0 to_28_for the 144-pin TQFP;<br>•<br>changed the total number of General Purpose Single Ended I/O to_115_for the<br>144-pin TQFP.<br>•<br>In Table 4.6. MachXO2-7000 Pin Summary:<br>•<br>changed the General Purpose I/O number in Bank 0 to_28_for the 144-pin TQFP;<br>•<br>changed the total number of General Purpose Single Ended I/O to_115_for the<br>144-pin TQFP.<br>•<br>In the For Further Information section, removed the standalone download path of the<br>Power Calculator.|
## **Revision 4.0, February 2023**
|**Section**|**Change Summary**|
|---|---|
|DC and Switching Characteristics|Corrected typo in Table 3.1. Absolute Maximum Ratings. Changed_Dedicated Input Voltage_<br>_Applied_to_–0.5 V to 3.75 V_.|
|Technical Support Assistance|Added reference to the Lattice Answer Database on the Lattice website.|
|All|Updated single table footnote style.|
|**Revision 3.9, February 2022**<br>**Section**<br>DC and Switching Characteristics<br>Supplemental Information<br>~~—~~|**Revision 3.9, February 2022**<br>**Section**<br>DC and Switching Characteristics<br>Supplemental Information<br>~~—~~|**Change Summary**<br>Corrected typo in Table 3.1. Absolute Maximum Ratings. Changed Storage Temperature<br>(Ambient)to_–55 °C to 125 °C_.<br>Updated linked documents in this section(and across the document if theyare referenced.)|
|---|---|---|
|**Revision 3.8, October 2021**|||
||**Section**|**Change Summary**|
||DC and SwitchingCharacteristics|Added footnote 6 to Table 3.4. Power SupplyRampRates.|
**Revision 3.7, June 2021 Section Change Summary** Acronyms in This Document Added items. ~~——————~~ Architecture • Added a graphical MUX symbol in Figure 2.16. Input Gearbox.
© 2010-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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||**Section**|**Change Summary**|
|---|---|---|
|||•<br>Changed_pull-up_to_pull-down_in the power-up sequence described in the Power-On-|
|||Reset section.|
||DC and Switching Characteristics|•<br>Removed footnote indicators from Absolute Maximum Ratings heading.|
|||•<br>Added VREF(V) values for SSTL18D, SSTL25D, and HSTL18D in Table 3.13. sysI/O|
|||Recommended OperatingConditions.|
||—|Corrected superscript formatting in Table 1.1, Table 2.13, Table 3.10, Table 3.14, and Table|
|||3.26.|
|**Revision 3.6, December 2020**<br>**Section**<br>**Change Summary**<br>All<br>Updated document template.<br>Introduction<br>Added 36-ball WLCSP and 81-ball WLCSP to Table 1.1. MachXO2 FamilySelection Guide.<br>Pinout Information<br>•<br>Added 36-WLCSP to Table 4.3. MachXO2-1200/MachXO2-1200U Pin Summary.<br>•<br>Updated Table 4.5. MachXO2-4000 Pin Summary. Added 81-WLCSP and adjusted values<br>of 84 QFNpackages.<br>Ordering Information<br>•<br>Added 36-ball WLCSP and 81-ball WLCSP to Figure 5.1. MachXO2 Part Number<br>Description.<br>•<br>Added part numbers: LCMXO2-1200ZE-1UWG36ITR , LCMXO2-1200ZE-1UWG36ITR1K,<br>LCMXO2-4000ZE-1UWG81ITR, and LCMXO2-4000ZE-1UWG81ITR1K.<br>All<br>Updated document numbers of referenced technical notes.<br>~~==~~|||
|**Revision 3.5, October 2020**|||
||**Section**|**Change Summary**|
||DC and Switching Characteristics|Revised footnote 2 in the Static Supply Current – ZE Devices and Static Supply Current –|
|||HC/HE Devices tables.|
## **Revision 3.4, June 2019**
|**Section**|**Change Summary**|
|---|---|
|All|•<br>Changed document number from DS1035 to FPGA-DS-02056.<br>•<br>Added Disclaimers section.<br>•<br>Minor editorial and style changes.|
|Introduction|Added MIPI D-PHY Emulated to Features section.|
|Architecture|•<br>Added MIPI D-PHY Bandwidth Matrix and Implementation reference to Table 2.12<br>footnote 3.<br>•<br>Addedpower-upsequence to the Power-On-Reset section.|
|DC and Switching Characteristics|•<br>Removed C2 row from the DC Electrical Characteristics table.<br>•<br>Removed footnote 11 from MachXO2 External Switching Characteristics – HC/HE<br>Devices and the MachXO2 External SwitchingCharacteristics – ZE Devices tables.|
|Supplemental Information|Added MIPI D-PHY Bandwidth Matrix and Implementation reference.|
|**Section**<br>~~TT~~|**Change Summary**<br>~~TT~~|
|---|---|
|DC and Switching Characteristics<br>~~TT~~|•<br>Updated the Absolute Maximum Ratings section. Added standards.<br>•<br>Updated the sysI/O Recommended Operating Conditions section. Added standards.<br>•<br>Updated the sysI/O Single-Ended DC Electrical Characteristics section. Added standards.<br>•<br>Updated the MachXO2 External Switching Characteristics – HC/HE Devices section.<br>•<br>Under 7:1 LVDS Outputs – GDDR71_TX.ECLK.7:1, the DVBand the DVAparameters were<br>changed to DIBand DIA. The parameter descriptions were also modified.<br>•<br>Updated the MachXO2 External SwitchingCharacteristics – ZE Devices section.<br>~~TT~~|
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|**Section**|**Change Summary**|
|---|---|
||•<br>Under 7:1 LVDS Outputs – GDDR71_TX.ECLK.7:1, the DVBand the DVAparameters were<br>changed to DIBand DIA. The parameter descriptions were also modified.<br>•<br>Updated the sysCONFIG Port Timing Specifications section.<br>•<br>Corrected the tINITLunits from ns toμs.|
|Pinout Information|•<br>Updated the Signal Descriptions section. Revised the descriptions of the PROGRAMN,<br>INITN, and DONE signals.<br>•<br>Updated the Pinout Information Summary section. Added footnote to MachXO2-1200<br>32 QFN.|
|Ordering Information|•<br>Updated the MachXO2 Part Number Description section. Corrected the MG184, BG256,<br>FTG256 package information. Added “(0.8 mm Pitch)” to BG332.<br>•<br>Updated the Ultra Low Power Industrial Grade Devices, Halogen Free (RoHS) Packaging<br>section.<br>•<br>Updated LCMXO2-1200ZE-1UWG25ITR50 footnote.<br>•<br>Corrected footnote numbering typo.<br>•<br>Added the LCMXO2-2000ZE-1UWG49ITR50 and LCMXO2-2000ZE-1UWG49ITR1K<br>part numbers. Updated/added footnote/s.|
## **Revision 3.2, May 2016**
|**Section**|**Change Summary**|
|---|---|
|All|•<br>Updated the MachXO2 External Switching Characteristics – HC/HE Devices section.<br>Added footnote 12.<br>•<br>Updated the MachXO2 External Switching Characteristics – ZE Devices section. Added<br>footnote 12.|
|Introduction|•<br>Updated the Features section. Revised Table 1.1. MachXO2 Family Selection Guide.<br>•<br>Added ‘Advanced’ 48 QFN package.<br>•<br>Revised footnote 6.<br>•<br>Added footnote 9.|
|DC and Switching Characteristics|•<br>Updated the MachXO2 External Switching Characteristics – HC/HE Devices section.<br>Added footnote 12.<br>•<br>Updated the MachXO2 External Switching Characteristics – ZE Devices section. Added<br>footnote 12.|
|Pinout Information|•<br>Updated the Signal Descriptions section. Added information on GND signal.<br>•<br>Updated the Pinout Information Summary section.<br>•<br>Added ‘Advanced’ MachXO2-256 48 QFN values.<br>•<br>Added ‘Advanced’ MachXO2-640 48 QFN values.<br>•<br>Added footnote to GND.<br>•<br>Added footnotes 2 and 3.|
|Ordering Information|•<br>Updated the MachXO2 Part Number Description section. Added ‘Advanced’ SG48<br>package and revised footnote.<br>•<br>Updated the Ordering Information section. Added part numbers for ‘Advanced’ QFN 48<br>package.|
FPGA-DS-02056-4.3
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|**Section**|**Change Summary**|
|---|---|
|DC and Switching Characteristics|Updated the sysCONFIG Port Timing Specifications section. Revised tDPPDONEand tDPPINITMax.<br>valuesper PCN 03A-16, released March 2016.|
|Pinout Information|•<br>Updated the Pinout Information Summary section.<br>•<br>Added MachXO2-1200 32 QFN values.<br>•<br>Added ‘Advanced’ MachXO2-4000 84 QFN values.|
|Ordering Information|•<br>Updated the MachXO2 Part Number Description section. Added ‘Advanced’ QN84<br>package and footnote.<br>•<br>Updated the Ordering Information section.<br>•<br>Added part numbers for 1280 LUTs QFN 32 package.<br>•<br>Addedpart numbers for 4320 LUTs QFN 84package.|
## **Revision 3.0, March 2015**
|**Section**|**Change Summary**||
|---|---|---|
|Introduction|•<br>Updated the Features section. Revised Table 1.1. MachXO2 Family Selection Guide.||
||Changed 64-ball ucBGA dimension.||
|Architecture|Updated the Device Configuration section. Added JTAGENB to TAP dualpurposepins.||
|**Revision 2.9, December 2014**|||
|**Section**<br>**Change Summary**<br>Introduction<br>•<br>Updated the Features section. Revised Table 1.1, MachXO2 Family Selection Guide.<br>•<br>Removed XO2-4000U data.<br>•<br>Removed 400-ball ftBGA.<br>•<br>Removed 25-ball WLCSP value for XO2-2000U.<br>DC and Switching Characteristics<br>•<br>Updated the Recommended Operating Conditions section. Adjusted Max. values for VCC<br>and VCCIO.<br>•<br>Updated the sysI/O Recommended Operating Conditions section. Adjusted Max. values<br>for LVCMOS 3.3, LVTTL, PCI, LVDS33 and LVPECL.<br>Pinout Information<br>Updated the Pinout Information Summarysection. Removed MachXO2-4000U.<br>Ordering Information<br>•<br>Updated the MachXO2 Part Number Description section. Removed BG400 package.<br>•<br>Updated the High-Performance Commercial Grade Devices with Voltage Regulator,<br>Halogen Free (RoHS) Packaging section. Removed LCMXO2-4000UHC part numbers.<br>•<br>Updated the High-Performance Industrial Grade Devices with Voltage Regulator,<br>Halogen Free(RoHS)Packagingsection. Removed LCMXO2-4000UHCpart numbers.<br>**Revision 2.8, November 2014**<br>**Section**<br>**Change Summary**<br>Introduction<br>•<br>Updated the Features section.<br>•<br>Revised I/O under Flexible Logic Architecture.<br>•<br>Revised standby power under Ultra Low Power Devices.<br>•<br>Revise input frequency range under Flexible On-Chip Clocking.<br>•<br>Updated Table 1.1, MachXO2 Family Selection Guide.<br>•<br>Added XO2-4000U data.<br>•<br>Removed HE and ZE device options for XO2-4000.<br>•<br>Added 400-ball ftBGA.<br>Pinout Information<br>Updated the Pinout Information Summary section. Added MachXO2-4000U caBGA400 and<br>MachXO2-7000 caBGA400.<br>Ordering Information<br>•<br>Updated the MachXO2 Part Number Description section. Added BG400 package.<br>•<br>Updated the Ordering Information section. Added MachXO2-4000U caBGA400 and<br>MachXO2-7000 caBGA400part numbers.<br>~~a—}—~~|||
|© 2010-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed atwww.latticesemi.com/legal.|||
|All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.|||
|FPGA-DS-02056-4.3|117||
**MachXO2 Family Data Sheet Data Sheet**
**Revision 2.7, October 2014 Section Change Summary** Ordering Information Updated the Ultra Low Power Industrial Grade Devices, Halogen Free (RoHS) Packaging section. Fixed typo in LCMXO2-2000ZE-1UWG49ITR part number package. Architecture Updated the Supported Standards section. Added MIPI information to Table 2.12. Supported Input Standards and Table 2.13. Supported Output Standards. DC and Switching Characteristics • Updated the BLVDS section. Changed output impedance nominal values in Table 3.3, BLVDS DC Condition. • Updated the LVPECL section. Changed output impedance nominal value in Table 3.4, LVPECL DC Condition. • Updated the sysCONFIG Port Timing Specifications section. Updated INITN low time values. ~~—__~~ **Revision 2.6, July 2014 Section Change Summary** DC and Switching Characteristics • Updated sysI/O Single-Ended DC Electrical Characteristics section. Updated footnote 4. • Updated Register-to-Register Performance section. Updated footnote. Ordering Information • Updated UW49 package to UWG49 in MachXO2 Part Number Description. • Updated LCMXO2-2000ZE-1UWG49CTR package in Ultra Low Power Commercial Grade ~~fp~~ Devices, Halogen Free (RoHS) Packaging. **Revision 2.5, May 2014 Section Change Summary** Architecture Updated TransFR (Transparent Field Reconfiguration) section. Updated TransFR description for PLL use during background Flash programming. **Revision 2.4, February 2014 Section Change Summary** Introduction Included the 49 WLCSP package in the MachXO2 Family Selection Guide table. Architecture Added information to Standby Mode and Power Saving Options section. Pinout Information Added the XO2-2000 49 WLCSP in the Pinout Information Summary table. Ordering Information • Added UW49 package in MachXO2 Part Number Description. • Added and LCMXO2-2000ZE-1UWG49CTR in Ultra Low Power Commercial Grade Devices, Halogen Free (RoHS) Packaging section. • Added and LCMXO2-2000ZE-1UWG49ITR in Ultra Low Power Industrial Grade Devices, ~~——~~ Halogen Free (RoHS) Packaging section. **Revision 2.3, December 2013 Section Change Summary** Architecture Updated information on CLKOS output divider in sysCLOCK Phase Locked Loops (PLLs) section. DC and Switching Characteristics • Updated Static Supply Current – ZE Devices table. • Updated footnote 4 in sysI/O Single-Ended DC Electrical Characteristics table; Updated VIL Max. (V) data for LVCMOS 25 and LVCMOS 28. ~~-—_f~~ • Updated VOS test condition in sysI/O Differential Electrical Characteristics - LVDS table. **Revision 2.2, September 2013 Section Change Summary** Architecture • Removed I2C Clock-Stretching feature per PCN #10A-13. • Removed information on PDPR memory in RAM Mode section. ~~——~~ • Updated Supported Input Standards table. © 2010-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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|**Section**|**Change Summary**|
|---|---|
|DC and SwitchingCharacteristics|Updated Power-On-Reset Volta|
Updated Power-On-Reset Voltage Levels table.
**Revision 2.1, June 2013**
|**Section**<br>**Change Summary**<br>Architecture<br>•<br>Architecture Overview – Added information on the state of the register on power-up<br>and after configuration.<br>•<br>sysCLOCK Phase Locked Loops (PLLs) section – Added missing cross reference to<br>sysCLOCK PLL Timingtable.<br>DC and Switching Characteristics<br>•<br>Added slew rate information to footnote 2 of the MachXO2 External Switching<br>Characteristics – HC/HE Devices and the MachXO2 External Switching Characteristics –<br>ZE Devices tables.<br>•<br>Power-On-Reset Voltage Levels table – Added symbols.<br>~~—_——~~|**Section**<br>**Change Summary**<br>Architecture<br>•<br>Architecture Overview – Added information on the state of the register on power-up<br>and after configuration.<br>•<br>sysCLOCK Phase Locked Loops (PLLs) section – Added missing cross reference to<br>sysCLOCK PLL Timingtable.<br>DC and Switching Characteristics<br>•<br>Added slew rate information to footnote 2 of the MachXO2 External Switching<br>Characteristics – HC/HE Devices and the MachXO2 External Switching Characteristics –<br>ZE Devices tables.<br>•<br>Power-On-Reset Voltage Levels table – Added symbols.<br>~~—_——~~|**Section**<br>**Change Summary**<br>Architecture<br>•<br>Architecture Overview – Added information on the state of the register on power-up<br>and after configuration.<br>•<br>sysCLOCK Phase Locked Loops (PLLs) section – Added missing cross reference to<br>sysCLOCK PLL Timingtable.<br>DC and Switching Characteristics<br>•<br>Added slew rate information to footnote 2 of the MachXO2 External Switching<br>Characteristics – HC/HE Devices and the MachXO2 External Switching Characteristics –<br>ZE Devices tables.<br>•<br>Power-On-Reset Voltage Levels table – Added symbols.<br>~~—_——~~|
|---|---|---|
|**Revision 2.0, January 2013**|||
||**Section**|**Change Summary**|
||Introduction|Updated the total number I/O to include JTAGENB.|
||Architecture|•<br>Supported Output Standards table – Added 3.3 VCCIO (Typ.) to LVDS row.|
|||•<br>Changed SRAM CRC Error Detection to Soft Error Detection.|
||DC and Switching Characteristics|•<br>Power Supply Ramp Rates table – Updated Units column for tRAMP symbol.|
|||•<br>Added new Maximum sysI/O Buffer Performance table.|
|||•<br>sysCLOCK PLL Timing table – Updated Min. column values for fIN, fOUT, fOUT2 and fPFD|
|||parameters. Added tSPO parameter. Updated footnote 6.|
|||•<br>MachXO2 Oscillator Output Frequency table – Updated symbol name for tSTABLEOSC.|
|||•<br>DC Electrical Characteristics table – Updated conditions for IIL, IIH symbols.|
|||•<br>Corrected parameters tDQVBS and tDQVAS|
|||•<br>Corrected MachXO2 ZEparameters tDVADQ and tDVEDQ|
||Pinout Information|Included the MachXO2-4000HE 184 csBGApackage.|
||OrderingInformation|Updatedpart number.|
|**Revision 1.9, April 2012**<br>**Section**<br>**Change Summary**<br>Architecture<br>Removed references to TN1200.<br>Ordering Information<br>•<br>Updated the Device Status portion of the MachXO2 Part Number Description to include<br>the 50 parts per reel for the WLCSP package.<br>•<br>Added new part number and footnote 2 for LCMXO2-1200ZE-1UWG25ITR50.<br>•<br>Updated footnote 1 for LCMXO2-1200ZE-1UWG25ITR.<br>Supplemental Information<br>Removed references to TN1200.<br>~~ff~~|
|---|
|**Revision 1.8, March 2012**|
|**Section**<br>**Change Summary**<br>Introduction<br>Added 32 QFN packaging information to Features bullets and MachXO2 Family Selection<br>Guide table.<br>DC and SwitchingCharacteristics<br>Changed ‘STANDBY’ to ‘USERSTDBY’ in StandbyMode timingdiagram.<br>Pinout Information<br>•<br>Removed footnote from Pin Information Summary tables.<br>•<br>Added 32 QFNpackage to Pin Information Summarytable.<br>Ordering Information<br>•<br>Updated Part Number Description and Ordering Information tables for 32 QFN package.<br>•<br>Updated topside mark diagram in the OrderingInformation section.<br>~~————~~|
|© 2010-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed atwww.latticesemi.com/legal.|
|All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.|
|FPGA-DS-02056-4.3<br>119|
119
**MachXO2 Family Data Sheet Data Sheet**
## **Revision 1.7, February 2012**
|**Section**|**Change Summary**|
|---|---|
|All|Updated document with new corporate logo.|
## **Revision 1.6, February 2012**
|**Section**|**Change Summary**|
|---|---|
|All|Data sheet status changed frompreliminaryto final.|
|Introduction|MachXO2 FamilySelection Guide table – Removed references to 49-ball WLCSP.|
|DC and Switching Characteristics|•<br>Updated Flash Download Time table.<br>•<br>Modified Storage Temperature in the Absolute Maximum Ratings section.<br>•<br>Updated IDKmax in Hot Socket Specifications table.<br>•<br>Modified Static Supply Current tables for ZE and HC/HE devices.<br>•<br>Updated Power Supply Ramp Rates table.<br>•<br>Updated Programming and Erase Supply Current tables.<br>•<br>Updated data in the External Switching Characteristics table.<br>•<br>Corrected Absolute Maximum Ratings for Dedicated Input Voltage Applied for LCMXO2<br>HC.<br>•<br>DC Electrical Characteristics table – Minor corrections to conditions for IIL,IIH.|
|Pinout Information|•<br>Removed references to 49-ball WLCSP.<br>•<br>Signal Descriptions table – Updated description for GND, VCC, and VCCIOx.<br>•<br>Updated Pin Information Summary table – Number of VCCIOs, GNDs, VCCs, and Total<br>Count of Bonded Pins for MachXO2-256, 640, and 640U and Dual Function I/O for<br>MachXO2-4000 332caBGA.|
|OrderingInformation|Removed references to 49-ball WLCSP|
## **Revision 1.4, August 2011**
|**Section**|**Change Summary**|
|---|---|
|Architecture|Updated information in Clock/Control Distribution Network and sysCLOCK Phase Locked<br>Loops(PLLs).|
|DC and SwitchingCharacteristics|Updated IILand IIHconditions in the DC Electrical Characteristics table.|
|Pinout Information|•<br>Included number of 7:1 and 8:1 gearboxes (input and output) in the pin information<br>summary tables.<br>•<br>Updated Pin Information Summary table: Dual Function I/O, DQS Groups Bank 1, Total<br>General Purpose Single-Ended I/O, Differential I/O Per Bank, Total Count of Bonded<br>Pins, Gearboxes.<br>•<br>Added column of data for MachXO2-2000 49 WLCSP.|
|Ordering Information|•<br>Updated R1 Device Specifications text section with information on migration from<br>MachXO2-1200-R1 to Standard (non-R1) devices.<br>•<br>Corrected Supply Voltage typo for part numbers: LCMX02-2000UHE-4FG484I, LCMX02-<br>2000UHE-5FG484I, LCMX02-2000UHE-6FG484I.<br>•<br>Added footnote for WLCSPpackageparts.|
|Supplemental Information|Removed reference to Stand-alone Power Calculator for MachXO2 Devices. Added reference<br>to AN8086, Designingfor Migration from MachXO2-1200-R1 to Standard(non-R1)Devices.|
## **Revision 1.3, May 2011**
|**Section**|**Change Summary**|
|---|---|
|Multiple|Replaced “SED” with “SRAM CRC Error Detection” throughout the document.|
|DC and SwitchingCharacteristics|Added footnote 1 to Program Erase Specifications table.|
|Pinout Information|•<br>Updated Pin Information Summary tables.<br>•<br>Signal name SO/SISPISO changed to SO/SPISO in the Signal Descriptions table.|
© 2010-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
120
FPGA-DS-02056-4.3
**MachXO2 Family Data Sheet Data Sheet**
## **Revision 1.2, April 2011**
|**Section**|**Change Summary**|
|---|---|
|All|Data sheet status changed from Advance to Preliminary.|
|Introduction|Updated MachXO2 FamilySelection Guide table.|
|Architecture|•<br>Updated Supported Input Standards table.<br>•<br>Updated sysMEM Memory Primitives diagram.<br>•<br>Added differential SSTL and HSTL I/O standards.|
|DC and Switching Characteristics|•<br>Updates following parameters: POR voltage levels, DC electrical characteristics, static<br>supply current for ZE/HE/HC devices, static power consumption contribution of<br>different components – ZE devices, programming and erase Flash supply current.<br>•<br>Added VREF specifications to sysI/O recommended operating conditions.<br>•<br>Updating timing information based on characterization.<br>•<br>Added differential SSTL and HSTL I/O standards.|
|Ordering Information|•<br>Added Ordering Part Numbers for R1 devices, and devices in WLCSP packages.<br>•<br>Added R1 device specifications.|
## **Revision 1.1, January 2011**
|**Section**|**Change Summary**|
|---|---|
|All|Included ultra-high I/O devices.|
|DC and Switching Characteristics|•<br>Recommended Operating Conditions table – Added footnote 3.<br>•<br>DC Electrical Characteristics table – Updated data for IIL, IIH. VHYST typical values<br>updated.<br>•<br>Generic DDRX2 Outputs with Clock and Data Aligned at Pin (GDDRX2_TX.ECLK.Aligned)<br>Using PCLK Pin for Clock Input tables – Updated data for TDIA and TDIB.<br>•<br>Generic DDRX4 Outputs with Clock and Data Aligned at Pin (GDDRX4_TX.ECLK.Aligned)<br>Using PCLK Pin for Clock Input tables – Updated data for TDIA and TDIB.<br>•<br>Power-On-Reset Voltage Levels table - clarified note 3.<br>•<br>Clarified VCCIO related recommended operating conditions specifications.<br>•<br>Added power supply ramp rate requirements.<br>•<br>Added Power Supply Ramp Rates table.<br>•<br>Updated Programming/Erase Specifications table.<br>•<br>Removed references to VCCP.|
|Pinout Information|•<br>Included number of 7:1 and 8:1 gearboxes (input and output) in the pin information<br>summary tables.<br>•<br>Removed references to VCCP.|
## **Revision 1.0, November 2010**
|**Section**|**Change Summary**|
|---|---|
|All|Initial release.|
© 2010-2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02056-4.3
121
www.latticesemi.com
Updated at April 17, 2026
Lattice Semiconductor is a premier developer of low-power, programmable design solutions, specializing in Field-Programmable Gate Arrays (FPGAs) and Programmable Logic Devices (PLDs). Recognized for driving innovation in cost-effective and power-efficient architectures, the company provides essential semiconductor components for consumer, mobile, and industrial design applications. Our selection of Lattice Semiconductor products is focused on their highly regarded FPGA integrated circuits. Devices from industry-leading families like the iCE40, MachXO, and LatticeECP series offer designers an exceptional combination of high system integration and industry-low power consumption. These FPGAs are engineered to handle complex tasks such as sensor management, custom connectivity, and advanced video processing while minimizing overall board footprint. To ensure seamless integration from concept to production, Lattice backs its hardware with a comprehensive support ecosystem. Engineers can accelerate their development cycles utilizing intuitive tools like the Lattice Diamond design software, paired with flexible IP cores and reference designs that reduce design risk and increase system reliability.
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