Image not available
Illustrative purposes only
KX124-1051
MEMS Accelerometer, Digital, X, Y, Z, ± 2g, ± 4g, ± 8g, 1.71 V, 3.6 V, LGA
⚠️ Reference pricing provided. In case of supply shortages, we will connect you with our trusted procurement partners to ensure your project's continuity.
- Manufacturer: KIONIX
- Product type: MEMS Accelerometers
- No. of Pins: 16Pins
- Sensitivity Max: 16384counts/g
- Sensitivity Min: 4096counts/g
- Measurement Axis: X, Y, Z
- Sensor Case Style: LGA
- Acceleration Range: ± 2g, ± 4g, ± 8g
- MEMS Sensor Output: Digital
- Supply Voltage Max: 3.6V
- Supply Voltage Min: 1.71V
| Delivery and price | |
|---|---|
| Units per pack | 1000 |
| Price | 0.511 € |
| Current stock | 10+ |
| Lead time | 30 days |
Datasheet
**PART NUMBER: ± 2g / 4g / 8g Tri-axis Digital KX124-1051 Accelerometer Specifications Rev. 1.0 20-Jan-16**
## **Product Description**
The KX124-1051 is a tri-axis ±2g, ±4g or ±8g silicon micromachined accelerometer with integrated 2048 byte buffer, orientation, tap/double tap, activity detecting, and Free fall algorithms. The sense element is fabricated using Kionix’s proprietary plasma micromachining process technology. Acceleration sensing is based on the principle of a differential capacitance arising from acceleration-induced motion of the sense element, which further utilizes common mode cancellation to decrease errors from process variation, temperature, and environmental stress. The sense element is hermetically sealed at the wafer level by bonding a second silicon lid wafer to the device using a glass frit. A separate ASIC device packaged with the sense element provides signal conditioning, and intelligent user-programmable application algorithms. The accelerometer is delivered in a 3 x 3 x 0.9mm LGA plastic package operating from a 1.71V – 3.6V DC supply. Voltage regulators are used to maintain constant
internal operating voltages over the range of input supply voltages. This results in stable operating characteristics over the range of input supply voltages. I[2] C or SPI digital protocol is used to communicate with the chip to configure and check for updates to the orientation, Directional Tap[TM] detection, Free fall detection and activity monitoring algorithms.
## **Features**
- 3 x 3 x 0.9 mm LGA
- User-selectable g Range up to ± 8g
- User-selectable Output Data Rate up to 25600Hz
- User-selectable low power or high resolution mode
- Digital High-Pass Filter Outputs
- Extra large embedded 2048 byte FIFO/FILO buffer
- Low Power Consumption with FlexSet™ Performance Optimization
- Internal voltage regulator
- Enhanced integrated Free fall, Directional Tap/Double-Tap[TM] , and Device-orientation Algorithms
- User-configurable wake-up function
- Digital I[2] C up to 3.4MHz
- Digital SPI up to 10MHz
- Lead-free Solderability
- Excellent Temperature Performance
- High Shock Survivability
- Factory Programmed Offset and Sensitivity
- Self-test Function
36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - info@kionix.com
© 2016 Kionix – All Rights Reserved
Page 1 of 81
**PART NUMBER: ± 2g / 4g / 8g Tri-axis Digital KX124-1051 Accelerometer Specifications Rev. 1.0** 6Kionix’
**20-Jan-16**
## **Table of Contents**
**==> picture [539 x 503] intentionally omitted <==**
**----- Start of picture text -----**<br>
|||||
|---|---|---|---|
|PRODUCT DESCRIPTION .................................................................................................................................................................... 1|
|FEATURES ......................................................................................................................................................................................... 1|
|TABLE OF CONTENTS ......................................................................................................................................................................... 2|
|FUNCTIONAL DIAGRAM .................................................................................................................................................................... 6|
|PRODUCT SPECIFICATIONS ................................................................................................................................................................ 7|
|MECHANICAL ............................................................................................................................................................................................ 7|
|ELECTRICAL ............................................................................................................................................................................................... 8|
|Start Up Time Profile ........................................................................................................................................................................ 9|
|Current Profile .................................................................................................................................................................................. 9|
|Power-On Procedure ....................................................................................................................................................................... 10|
|ENVIRONMENTAL ..................................................................................................................................................................................... 11|
|TERMINOLOGY ........................................................................................................................................................................................ 12|
|g ...................................................................................................................................................................................................... 12|
|Sensitivity ........................................................................................................................................................................................ 12|
|Zero-g offset ................................................................................................................................................................................... 12|
|Self-test ........................................................................................................................................................................................... 12|
|FUNCTIONALITY ....................................................................................................................................................................................... 13|
|Sense element ................................................................................................................................................................................. 13|
|ASIC interface ................................................................................................................................................................................. 13|
|Factory calibration .......................................................................................................................................................................... 13|
|APPLICATION SCHEMATIC AND PIN DESCRIPTION ........................................................................................................................................... 14|
|Application Schematic .................................................................................................................................................................... 14|
|Pin Descriptions .............................................................................................................................................................................. 14|
|TEST SPECIFICATIONS ................................................................................................................................................................................ 15|
|PACKAGE DIMENSIONS AND ORIENTATION ................................................................................................................................................... 16|
|Dimensions ..................................................................................................................................................................................... 16|
|Orientation ..................................................................................................................................................................................... 17|
|DIGITAL INTERFACE ......................................................................................................................................................................... 19|
|I|[2]|C|SERIAL INTERFACE ............................................................................................................................................................................... 19|
|I|[2]|C Operation .................................................................................................................................................................................. 20|
|Writing to accelerometer’s 8-bit Register....................................................................................................................................... 22|
|Reading from accelerometer’s 8-bit Register ................................................................................................................................. 22|
|Data Transfer Sequences ................................................................................................................................................................ 23|
|HS-mode ......................................................................................................................................................................................... 24|
|I|[2]|C Timing Diagram ......................................................................................................................................................................... 25|
|SPI|COMMUNICATIONS............................................................................................................................................................................. 26|
|4-Wire SPI Interface ........................................................................................................................................................................ 26|
|4-Wire SPI Timing Diagram ............................................................................................................................................................ 27|
**----- End of picture text -----**<br>
36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - info@kionix.com
© 2016 Kionix – All Rights Reserved
Page 2 of 81
**==> picture [499 x 66] intentionally omitted <==**
**----- Start of picture text -----**<br>
|||
|---|---|
|PART NUMBER:|
|± 2g / 4g / 8g Tri-axis Digital|KX124-1051|
|Accelerometer Specifications|Rev. 1.0|
|6Kionix’|
|20-Jan-16|
**----- End of picture text -----**<br>
_4-Wire Read and Write Registers ................................................................................................................................................... 28 3-Wire SPI Interface ........................................................................................................................................................................ 29 3-Wire SPI Timing Diagram ............................................................................................................................................................ 30 3-Wire Read and Write Registers ................................................................................................................................................... 31_ **EMBEDDED REGISTERS.................................................................................................................................................................... 32** ACCELEROMETER OUTPUTS........................................................................................................................................................................ 33 XHP_L .................................................................................................................................................................................................. 34 XHP_H ................................................................................................................................................................................................. 34 YHP_L .................................................................................................................................................................................................. 34 YHP_H ................................................................................................................................................................................................. 34 ZHP_L .................................................................................................................................................................................................. 35 ZHP_H ................................................................................................................................................................................................. 35 XOUT_L ............................................................................................................................................................................................... 35 XOUT_H............................................................................................................................................................................................... 35 YOUT_L ............................................................................................................................................................................................... 36 YOUT_H ............................................................................................................................................................................................... 36 ZOUT_L................................................................................................................................................................................................ 36 ZOUT_H ............................................................................................................................................................................................... 36 COTR ................................................................................................................................................................................................... 37 WHO_AM_I ......................................................................................................................................................................................... 37 TSCP .................................................................................................................................................................................................... 37 TSPP .................................................................................................................................................................................................... 38 INS1 ..................................................................................................................................................................................................... 38 INS2 ..................................................................................................................................................................................................... 39 INS3 ..................................................................................................................................................................................................... 40 STATUS_REG ....................................................................................................................................................................................... 41 INT_REL ............................................................................................................................................................................................... 41 CNTL1 .................................................................................................................................................................................................. 41 CNTL2 .................................................................................................................................................................................................. 42 CNTL3 .................................................................................................................................................................................................. 43 ODCNTL ............................................................................................................................................................................................... 45 INC1 .................................................................................................................................................................................................... 46 INC2 .................................................................................................................................................................................................... 47 INC3 .................................................................................................................................................................................................... 47 INC4 .................................................................................................................................................................................................... 48 INC5 .................................................................................................................................................................................................... 48 INC6 .................................................................................................................................................................................................... 49 TILT_TIMER ......................................................................................................................................................................................... 50 WUFC .................................................................................................................................................................................................. 50 TDTRC .................................................................................................................................................................................................. 50 TDTC .................................................................................................................................................................................................... 51 TTH ...................................................................................................................................................................................................... 51 TTL ....................................................................................................................................................................................................... 52
36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - info@kionix.com
© 2016 Kionix – All Rights Reserved
Page 3 of 81
**==> picture [499 x 66] intentionally omitted <==**
**----- Start of picture text -----**<br>
|||
|---|---|
|PART NUMBER:|
|± 2g / 4g / 8g Tri-axis Digital|KX124-1051|
|Accelerometer Specifications|Rev. 1.0|
|6Kionix’|
|20-Jan-16|
**----- End of picture text -----**<br>
**==> picture [539 x 533] intentionally omitted <==**
**----- Start of picture text -----**<br>
|||
|---|---|
|FTD ...................................................................................................................................................................................................... 52|
|STD ...................................................................................................................................................................................................... 52|
|TLT ....................................................................................................................................................................................................... 53|
|TWS ..................................................................................................................................................................................................... 53|
|FFTH .................................................................................................................................................................................................... 54|
|FFC ...................................................................................................................................................................................................... 54|
|FFCNTL ................................................................................................................................................................................................ 54|
|ATH ..................................................................................................................................................................................................... 55|
|TILT_ANGLE_LL ................................................................................................................................................................................... 55|
|TILT_ANGLE_HL................................................................................................................................................................................... 56|
|HYST_SET ............................................................................................................................................................................................ 56|
|LP_CNTL .............................................................................................................................................................................................. 56|
|BUF_CNTL1 ......................................................................................................................................................................................... 57|
|BUF_CNTL2 ......................................................................................................................................................................................... 58|
|BUF_STATUS_1 ................................................................................................................................................................................... 59|
|BUF_STATUS_2 ................................................................................................................................................................................... 59|
|BUF_CLEAR ......................................................................................................................................................................................... 59|
|BUF_READ ........................................................................................................................................................................................... 59|
|SELF_TEST ........................................................................................................................................................................................... 60|
|EMBEDDED APPLICATIONS ............................................................................................................................................................. 61|
|ORIENTATION DETECTION FEATURE ............................................................................................................................................................. 61|
|Hysteresis........................................................................................................................................................................................ 61|
|Device Orientation Angle (aka Tilt Angle)....................................................................................................................................... 62|
|Tilt Timer ......................................................................................................................................................................................... 63|
|MOTION INTERRUPT FEATURE DESCRIPTION ................................................................................................................................................. 64|
|DIRECTIONAL TAP DETECTION FEATURE DESCRIPTION ..................................................................................................................................... 66|
|Performance Index.......................................................................................................................................................................... 66|
|Single Tap Detection ....................................................................................................................................................................... 67|
|Double Tap Detection ..................................................................................................................................................................... 68|
|FREE FALL DETECT .................................................................................................................................................................................... 69|
|SAMPLE BUFFER FEATURE DESCRIPTION ....................................................................................................................................................... 71|
|FIFO Mode ...................................................................................................................................................................................... 71|
|Stream Mode .................................................................................................................................................................................. 71|
|Trigger Mode .................................................................................................................................................................................. 72|
|FILO Mode ...................................................................................................................................................................................... 72|
|Buffer Operation ............................................................................................................................................................................. 72|
|NOTICE............................................................................................................................................................................................ 78|
|PRECAUTION ON USING KIONIX|PRODUCTS ................................................................................................................................................. 78|
|PRECAUTION FOR MOUNTING /|CIRCUIT BOARD DESIGN .................................................................................................................................. 79|
|PRECAUTIONS REGARDING APPLICATION EXAMPLES AND EXTERNAL CIRCUITS ..................................................................................................... 79|
|PRECAUTION FOR ELECTROSTATIC ............................................................................................................................................................... 79|
|PRECAUTION FOR STORAGE /|TRANSPORTATION ............................................................................................................................................ 79|
**----- End of picture text -----**<br>
36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - info@kionix.com
© 2016 Kionix – All Rights Reserved
Page 4 of 81
**==> picture [499 x 66] intentionally omitted <==**
**----- Start of picture text -----**<br>
|||
|---|---|
|PART NUMBER:|
|± 2g / 4g / 8g Tri-axis Digital|KX124-1051|
|Accelerometer Specifications|Rev. 1.0|
|6Kionix’|
|20-Jan-16|
**----- End of picture text -----**<br>
PRECAUTION FOR PRODUCT LABEL .............................................................................................................................................................. 80 PRECAUTION FOR DISPOSITION ................................................................................................................................................................... 80 PRECAUTION FOR FOREIGN EXCHANGE AND FOREIGN TRADE ACT ...................................................................................................................... 80 PRECAUTION REGARDING INTELLECTUAL PROPERTY RIGHTS ............................................................................................................................. 80 OTHER PRECAUTION ................................................................................................................................................................................. 80 GENERAL PRECAUTION ............................................................................................................................................................................. 80 **REVISION HISTORY .......................................................................................................................................................................... 81**
36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - info@kionix.com
© 2016 Kionix – All Rights Reserved
Page 5 of 81
## ~~Then]~~
## **± 2g / 4g / 8g Tri-axis Digital Accelerometer Specifications**
**PART NUMBER: KX124-1051 Rev. 1.0 20-Jan-16**
## **Functional Diagram**
**==> picture [357 x 294] intentionally omitted <==**
**----- Start of picture text -----**<br>
X<br>Accel<br>Y<br>Amplifier ADC<br>Accel<br>oR | |<br>Z<br>Accel<br>Digital<br>Power<br>14Na,SYNa,aNanevo™~ no_ 7 no( > C)aN }—_ yo™~C) aC<br>VDD GND IO_VDD nCS SDO SDA SCL ADDR TRIG INT1 INT2<br>**----- End of picture text -----**<br>
36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - info@kionix.com
© 2016 Kionix – All Rights Reserved
Page 6 of 81
## **± 2g / 4g / 8g Tri-axis Digital Accelerometer Specifications** Ktonix: ~~Tene}~~
**PART NUMBER: KX124-1051**
**Rev. 1.0**
**20-Jan-16**
## **Product Specifications**
## **Mechanical**
° (specifications are for operation at VDD = 2.5V and T = 25 C unless stated otherwise) ~~I~~ **Parameters Uni** ~~nD~~ **ts** ~~I~~ **Min Typ** ~~I~~ **ical Max** Operating Temperature Range °C -40 - 85 ~~————~~ Zero-g Offset mg ±25 Zero-g Offset Variation from RT over Temp. mg/°C 0.2 ~~ee ee~~ GSEL1=0, GSEL0=0 (± 2g) 16384 Sensitivity[1] GSEL1=0, GSEL0=1 (± 4g) counts/g 8192 ~~a~~ GSEL1=1, GSEL0=0 (± 8g) 4096 GSEL1=0, GSEL0=0 (± 2g) 64 Sensitivity GSEL1=0, GSEL0=1 (± 4g) counts/g 32 (Buffer 8-bit mode)[1,2] ~~a~~ GSEL1=1, GSEL0=0 (± 8g) 16 Sensitivity Variation from RT over Temp. %/°C 0.01 ~~eeee ee~~ 0.25(xy) Positive Self Test Output change on Activation g 0.5 0.75 ~~a~~ 0.20(z) 3500 (xy) Mechanical Resonance (-3dB)[3] Hz ~~LO~~ 1800 (z) ~~ns~~ Non-Linearity ~~UD~~ % of FS ~~I~~ 0.6 ~~I~~ Cross Axis Sensitivity % 2 ~~rr~~ Noise (RMS at 50Hz with low-pass filter = ODR/9)[4] mg 0.75 **Table 1:** Mechanical Specifications
Notes:
1. Resolution and acceleration ranges are user selectable via I[2] C or SPI.
2. Sensitivity is proportional to BRES in BUF_CNTL2.
3. Resonance as defined by the dampened mechanical sensor.
4. Noise varies with Output Data Rate (ODR) and Current Consumption settings. Contact Kionix Engineering for additional details on FlexSet™ Performance Optimization.
36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - info@kionix.com
© 2016 Kionix – All Rights Reserved
Page 7 of 81
**PART NUMBER:**
**==> picture [119 x 52] intentionally omitted <==**
**----- Start of picture text -----**<br>
6Kionix’<br>**----- End of picture text -----**<br>
**± 2g / 4g / 8g Tri-axis Digital Accelerometer Specifications**
**KX124-1051**
**Rev. 1.0**
**20-Jan-16**
## **Electrical**
(specifications are for operation at VDD = 2.5V and T = 25°C unless stated otherwise)
|**Parameters**<br>~~a~~|**Parameters**<br>~~a~~|**Parameters**<br>~~a~~|**Units**<br>~~a~~|**Min**<br>~~a~~|**Typical **<br>~~a~~|**Max **<br>~~a~~|
|---|---|---|---|---|---|---|
|Supply Voltage (VDD) Operating<br>~~a~~||Supply Voltage (VDD) Operating<br>~~a~~|V<br>~~a~~|1.71<br>~~a~~|2.5<br>~~a~~|3.6<br>~~a~~|
|I/O Pads Supply Voltage (IO_VDD)<br>~~a~~|||V<br>~~a~~|1.7<br>~~a~~|~~a~~|VDD<br>~~a~~|
|Current Consumption||High Resolution Mode (RES=1)<br>~~es~~|1)<br>A<br>~~a~~||145||
|||Low Power Mode1(RES=0)<br>~~Te~~|||10||
|||Standby<br>~~Te~~<br>~~a~~||~~a~~|0.9<br>~~a~~|~~a~~|
|Output Low Voltage (IO_VDD < 2V)2<br>~~a~~<br>~~a~~|||V<br>~~a~~<br>~~a~~|-<br>~~a~~<br>~~a~~|-<br>~~a~~<br>~~a~~|0.2*IO_VDD<br>~~a~~<br>~~a~~|
|Output Low Voltage (IO_VDD≥2V)2<br>~~a~~|||V<br>~~a~~|-<br>~~a~~|-<br>~~a~~|0.4<br>~~a~~|
|Output High Voltage<br>~~a~~<br>~~a~~|||V<br>~~a~~<br>~~a~~|0.8*IO_VDD<br>~~a~~<br>~~a~~|-<br>~~a~~<br>~~a~~|-<br>~~a~~<br>~~a~~|
|Input Low Voltage<br>~~a~~<br>~~a~~|||V<br>~~a~~<br>~~a~~|-<br>~~a~~<br>~~a~~|-<br>~~a~~<br>~~a~~|0.2*IO_VDD<br>~~a~~<br>~~a~~|
|InputHigh Voltage<br>~~a~~|||V<br>~~a~~|0.8* IO_VDD<br>~~a~~|-<br>~~a~~|-<br>~~a~~|
|Input Pull-down Current<br>~~a~~|||A<br>~~a~~|~~a~~|0<br>~~a~~|~~a~~|
|Start Up Time3<br>~~a~~<br>~~a~~|||ms<br>~~a~~<br>~~a~~|2.0<br>~~a~~<br>~~a~~|~~a~~<br>~~a~~|1300<br>~~a~~<br>~~a~~|
|PowerUpTime4<br>~~a~~|||ms<br>~~a~~|~~a~~|20<br>~~a~~|50<br>~~a~~|
|I2C Communication Rate<br>~~a~~|||MHz<br>~~a~~|~~a~~|~~a~~|3.4<br>~~a~~|
|SPI Communication Rate<br>~~a~~<br>~~a~~|||MHz<br>~~a~~<br>~~a~~|~~a~~<br>~~a~~|~~a~~<br>~~a~~|10<br>~~a~~<br>~~a~~|
|OutputDataRate (ODR)5<br>~~a~~<br>~~cerry~~|||Hz<br>~~a~~<br>~~eres~~|0.781<br>~~a~~<br>~~cere~~|50<br>~~a~~<br>~~eee~~|25600<br>~~a~~<br>~~eee~~|
|Bandwidth (-3dB)6<br>~~a~~<br>~~cerry~~|RES=0<br>~~a~~<br>~~OST~~<br>~~cerry~~||Hz<br>~~a~~<br>~~eres~~|~~a~~<br>~~cere~~|800<br>~~a~~<br>~~eee~~|~~a~~<br>~~eee~~|
||RES= 1<br>~~a~~<br>~~OST~~<br>~~cerry~~||Hz<br>~~a~~<br>~~eres~~|~~a~~<br>~~cere~~|ODR/2<br>~~a~~<br>~~eee~~|~~a~~<br>~~eee~~|
2. For I[2] C communication, this assumes a minimum 1.5K pull-up resistor on SCL and SDA pins.
3. Start up time is from PC1 set to valid outputs. Time varies with Output Data Rate (ODR); see chart below
4. Power up time is from VDD valid to device boot completion.
5. User selectable through I[2] C or SPI.
6. User selectable and dependent on ODR and RES.
36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - info@kionix.com
© 2016 Kionix – All Rights Reserved
Page 8 of 81
**± 2g / 4g / 8g Tri-axis Digital Accelerometer Specifications** 6Kionix’
**PART NUMBER: KX124-1051 Rev. 1.0 20-Jan-16**
## **Start Up Time Profile**
**==> picture [367 x 208] intentionally omitted <==**
**----- Start of picture text -----**<br>
Startup Time over ODR setting<br>1400.0<br>Power mode depends on RES setting Full power mode<br>a||<br>1200.0<br>1000.0 | |<br>800.0 | |<br>600.0<br>~\ 3<br>400.0<br>—\<br>200.0<br>0.0<br>ee 0.781 1.563 3.125 6.25 12.5 25 50 100 200 400 800 1600 3200 6400 12800 25600<br>VDD=2.5,RES=0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0<br>VDD=2.5,RES=1 1287.0 644.5 323.2 162.7 82.3 42.1 22.1 12.0 7.0 4.5 3.3 2.6 2.3 2.2 2.1 2.0<br>RE Ee<br>Startup Time(ms)<br>**----- End of picture text -----**<br>
**Current Profile**
**==> picture [487 x 276] intentionally omitted <==**
**----- Start of picture text -----**<br>
Representative Current Profile<br>ee ODR (Hz) RES ee Current ee (µA) Representative Current (µA)<br>ee 0 Standb ee y 0.9 ee 16x Averaging Filter (default )<br>ee 0.781 ee 0 1.8 ee 1000.0<br>ee 1.563 ee 0 2.0 ee<br>ee 3.125 ee 0 2.2 ee<br>146 146 146 146 146 146 146<br>6.25 0 3.0<br>12.5 0 5 100.0<br>a ee<br>ee 25 0 7 43<br>50 0 13 21<br>ee a<br>100 0 21 13<br>ee ee eee °<br>ee 200 ee 0 ee 43 10.0 5 7 e<br>400 1 146<br>eeee 800 eeeeee 1 146 ee ee 1.8 [2.0] [2.2] 3.0 ° °° ° ° RES = 0RES = 1 when ODR ≥ 400Hz<br>1600 1 146<br>ee 3200 ee 1 146 ee 1.0<br>ee 6400 ee 1 146<br>ee 12800 1 146<br>Accelerometer ODR (Hz)<br>|a 25600 eeee 1 146 ee<br>36 Thornwood Dr. – Ithaca, NY 14850<br>tel: 607-257-1080 – fax:607-257-1146<br>www.kionix.com - info@kionix.com<br>0.1 1 10 100 1000 10000 100000<br>Current (µA)<br>**----- End of picture text -----**<br>
© 2016 Kionix – All Rights Reserved
Page 9 of 81
**==> picture [508 x 114] intentionally omitted <==**
**----- Start of picture text -----**<br>
PART NUMBER:<br>± 2g / 4g / 8g Tri-axis Digital KX124-1051<br>Accelerometer Specifications Rev. 1.0<br>20-Jan-16<br>Khe Power-On Procedure f<br>**----- End of picture text -----**<br>
## **Power-On Procedure**
Proper functioning of power-on reset (POR) is dependent on the specific **VDD, VDDLow** , **TVDD** (rise time) **,** and **TVDD_Off** profile of individual applications. It is recommended to minimize **VDDLow,** and **TVDD** , and maximize **TVdd_Off** . It is also advised that the **VDD** ramp up time **TVDD** be monotonic. Note that the outputs will not be stable until **VDD** has reached its final value.
_To assure proper POR, the application should be evaluated over the customer specified range of VDD, VDDLow, TVDD, TVDD_Off and temperature as POR performance can vary depending on these parameters._
Please refer to Technical Note _**TN004 KX112, KX122, KX123, KX124 Accelerometer Power-On Procedure**_ for more information.
36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - info@kionix.com
© 2016 Kionix – All Rights Reserved Page 10 of 81
## **± 2g / 4g / 8g Tri-axis Digital Accelerometer Specifications**
**PART NUMBER: KX124-1051**
**Rev. 1.0 20-Jan-16**
## **Environmental**
|**Environmental**|**Environmental**|||||
|---|---|---|---|---|---|
|**Parameters**||**Units**|**Min**|**Typical**|**Max**|
|SupplyVoltage (VDD)A|AbsoluteLimits|V|-0.5|-|3.60|
|OperatingTemperatureRange||°C|-40|-|85|
|StorageTemperatureRange||°C|-55|-|150|
|Mech. Shock (powered and unpowered)||g|-|-|5000 for 0.5ms<br>10000for0.2ms|
|ESD|HBM|V|-|-|2000|
**Table 3:** Environmental Specifications
Caution: ESD Sensitive and Mechanical Shock Sensitive Component, improper handling can cause permanent damage to the device.
These products conform to RoHS Directive 2011/65/EU of the European Parliament and of Y the Council of the European Union that was issued June 8, 2011. Specifically, these products RoHS do not contain any non-exempted amounts of lead, mercury, cadmium, hexavalent chromium, 2011/65/EU polybrominated biphenyls (PBB) or polybrominated diphenyl ethers (PBDE) above the maximum concentration values (MCV) by weight in any of its homogenous materials. Homogenous materials are “of uniform composition throughout”. The MCV for lead, mercury, hexavalent chromium, PBB, and PBDE is 0.10%. The MCV for cadmium is 0.010%.
Applicable Exemption: _7C-I - Electrical and electronic components containing lead in a glass or ceramic other than dielectric ceramic in capacitors (piezoelectronic devices) or in a glass or ceramic matrix compound._
These products are also in conformance with REACH Regulation No 1907/2006 of the European Parliament and of the Council that was issued Dec. 30, 2011. They do not contain any Substances of Very High Concern (SVHC-161) as identified by the European Chemicals Agency as of 17 December 2014.
This product is halogen-free per IEC 61249-2-21. Specifically, the materials used in this product HF contain a maximum total halogen content of 1500 ppm with less than 900-ppm bromine and less than 900-ppm chlorine.
## **Soldering**
Soldering recommendations are available upon request or from www.kionix.com.
36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - info@kionix.com
© 2016 Kionix – All Rights Reserved
Page 11 of 81
**==> picture [119 x 52] intentionally omitted <==**
**----- Start of picture text -----**<br>
6Kionix’<br>**----- End of picture text -----**<br>
**PART NUMBER: ± 2g / 4g / 8g Tri-axis Digital KX124-1051 Accelerometer Specifications Rev. 1.0 20-Jan-16**
## **Terminology**
## **g**
A unit of acceleration equal to the acceleration of gravity at the earth’s surface.
**==> picture [53 x 26] intentionally omitted <==**
One thousandth of a g (0.0098 m/ s[2] ) is referred to as 1 milli-g (1 mg).
## **Sensitivity**
The sensitivity of an accelerometer is the change in output per unit of input acceleration at nominal VDD and temperature. The term is essentially the gain of the sensor expressed in counts per g (counts/g) or LSB’s per g (LSB/g). Occasionally, sensitivity is expressed as a resolution, i.e. milli-g per LSB (mg/LSB) or milli-g per count (mg/count). Sensitivity for a given axis is determined by measurements of the formula: _Sensitivity_ _Output_ @ 1 _g_ _Output_ @ 1 _g_ 2 _g_
The sensitivity tolerance describes the range of sensitivities that can be expected from a large population of sensors at room temperature and over life. When the temperature deviates from room temperature (25°C), the sensitivity will vary by the amount shown in Table 1.
## **Zero-g offset**
Zero-g offset or 0-g offset describes the actual output of the accelerometer when no acceleration is applied. Ideally, the output would always be in the middle of the dynamic range of the sensor (content of the OUTX, OUTY, OUTZ registers = 00h, expressed as a 2’s complement number). However, because of mismatches in the sensor, calibration errors, and mechanical stress, the output can deviate from 00h. This deviation from the ideal value is called 0-g offset. The zero-g offset tolerance describes the range of 0-g offsets of a population of sensors over the operating temperature range.
## **Self-test**
Self-test allows a functional test of the sensor without applying a physical acceleration to it. When activated, an electrostatic force is applied to the sensor, simulating an input acceleration. The sensor outputs respond accordingly. If the output signals change within the amplitude specified in Table 1, then the sensor is working properly and the parameters of the interface chip are within the defined specifications.
36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - info@kionix.com
© 2016 Kionix – All Rights Reserved
Page 12 of 81
**PART NUMBER: ± 2g / 4g / 8g Tri-axis Digital KX124-1051 Accelerometer Specifications Rev. 1.0** 6Kionix’ **20-Jan-16**
## **Functionality**
## **Sense element**
The sense element is fabricated using Kionix’s proprietary plasma micromachining process technology. This process technology allows Kionix to create mechanical silicon structures which are essentially massspring systems that move in the direction of the applied acceleration. Acceleration sensing is based on the principle of a differential capacitance arising from the acceleration-induced motion. Capacitive plates on the moving mass move relative to fixed capacitive plates anchored to the substrate. The sense element is hermetically sealed at the wafer level by bonding a second silicon lid wafer to the device using a glass frit.
## **ASIC interface**
A separate ASIC device packaged with the sense element provides all of the signal conditioning and communication with the sensor. The complete measurement chain is composed by a low-noise capacitance to voltage amplifier which converts the differential capacitance of the MEMS sensor into an analog voltage that is sent through an analog-to-digital converter. The acceleration data may be accessed through the I[2] C digital communications provided by the ASIC. In addition, the ASIC contains all of the logic to allow the user to choose data rates, g-ranges, filter settings, and interrupt logic. Plus, there are two programmable state machines which allow the user to create unique embedded functions based on changes in acceleration.
## **Factory calibration**
Kionix trims the offset and sensitivity of each accelerometer by adjusting gain (sensitivity) and 0-g offset trim codes stored in non-volatile memory (OTP). Additionally, all functional register default values are also programmed into the non-volatile memory. Every time the device is turned on or a software reset command is issued, the trimming parameters and default register values are downloaded into the volatile registers to be used during active operation. This allows the device to function without further calibration.
36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - info@kionix.com
© 2016 Kionix – All Rights Reserved
Page 13 of 81
**PART NUMBER: ± 2g / 4g / 8g Tri-axis Digital KX124-1051 Accelerometer Specifications Rev. 1.0 20-Jan-16** ~~Cs Soni —~~ **Application Schematic and Pin Description**
## **Application Schematic**
## **Pin Descriptions**
|**Pin**|**Name**|**Description**|
|---|---|---|
|1|IO_VDD|The power supply input for the digital communication bus. Optionally decouple this pin to ground with a 0.1uF ceramic<br>capacitor.|
|2<br>~~a~~|NC|Not InternallyConnected – Can be connected to VDD, IO_VDD, GND or leave floating|
|3<br>~~a~~|NC|Not InternallyConnected – Can be connected to VDD, IO_VDD, GND or leave floating|
|4<br>~~a~~|SCLK/SCL|SPI and I2C Serial Clock|
|5<br>~~a~~|GND|Ground|
|6<br>~~a~~|SDI/SDA|SPI Data input / I2C Serial Data|
|7<br>~~a~~|SDO/ADDR<br>|Serial Data Outpin during4 wire SPI communication andpart of the device address duringI2C communication.<br>|
|8<br>|nCS<br>|SPI enable / I2C mode select. Connect to GND for SPI enabled, I2C communication disabled. Connect to IO_VDD for SPI<br>disabled,I2C communicationenabled. Donotleavefloating.<br>|
|9<br>~~sO~~|INT2<br>~~sO~~|Physical Interrupt 2. Leave floatingif not used.<br>~~sO~~|
|10<br>~~a~~|NC|Not InternallyConnected – Can be connected to VDD, IO_VDD, GND or leave floating|
|11<br>~~a~~|INT1|Physical Interrupt 1. Leave floatingif not used.|
|12<br>~~a~~|GND|Ground|
|13<br>~~a~~|TRIG|Triggerpin for FIFO buffer control – Connect to GND when not usingexternal trigger option.|
|14<br>~~a~~|VDD|Thepower supplyinput. Decouple thispin toground with a 0.1uF ceramic capacitor.|
|15<br>~~a~~|NC|Not InternallyConnected – Can be connected to VDD, IO_VDD, GND or leave floating|
|16<br>~~a~~|NC|Not InternallyConnected – Can be connected to VDD, IO_VDD, GND or leave floating|
**Table 4:** Pin Description
36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - info@kionix.com
© 2016 Kionix – All Rights Reserved
Page 14 of 81
## **PART NUMBER: ± 2g / 4g / 8g Tri-axis Digital KX124-1051 Accelerometer Specifications Rev. 1.0 20-Jan-16** ~~KS)~~ **Test Specifications** ! _**Special Characteristics** :_ ~~I~~
These characteristics have been identified as being critical to the customer. Every part is tested to verify its conformance to specification prior to shipment.
Parameter Specification Test Conditions Zero-g Offset @ RT (2g range) 0 ± 1475 counts 25°C, VDD = 2.5 V Sensitivity @ RT (2g range) 16384 ± 819 counts/g 25°C, VDD = 2.5 V ~~———~~
## **Table 5:** Test Specifications
36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - info@kionix.com
© 2016 Kionix – All Rights Reserved
Page 15 of 81
## **± 2g / 4g / 8g Tri-axis Digital Accelerometer Specifications**
**==> picture [88 x 66] intentionally omitted <==**
**----- Start of picture text -----**<br>
PART NUMBER:<br>KX124-1051<br>Rev. 1.0<br>20-Jan-16<br>**----- End of picture text -----**<br>
## **Package Dimensions and Orientation**
## **Dimensions**
## 3 x 3 x 0.9 mm LGA
All dimensions and tolerances conform to ASME Y14.5M-1994
36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - info@kionix.com
© 2016 Kionix – All Rights Reserved
Page 16 of 81
||**PART NUMBER:**|
|---|---|
|**± 2g / 4g / 8g Tri-axis Digital**|**KX124-1051**|
|**Accelerometer Specifications**|**Rev. 1.0**|
||**20-Jan-16**|
## **Orientation**
**==> picture [58 x 61] intentionally omitted <==**
**----- Start of picture text -----**<br>
Pin 1<br>+X<br>+Z<br>+Y<br>**----- End of picture text -----**<br>
When device is accelerated in +X, +Y or +Z direction, the corresponding output will increase.
|**Position **|**1**|**1**|**2**|**2**|**3**|**3**|**4**|**4**|**5**|**5**|**6**|**6**|
|---|---|---|---|---|---|---|---|---|---|---|---|---|
|Diagram<br>~~Re~~<br>~~a~~|~~eG~~<br>||~~eG~~<br>||~~eG~~<br>||~~eG~~<br>~~GG~~<br>||Top<br>Bottom<br>~~eG~~<br>~~GG~~<br>||Bottom<br>Top<br>~~eG~~<br>||
|Resolution(bits)<br>~~Re~~<br>~~a~~<br>~~a~~|16<br>~~eG~~<br><br>|8<br>~~eG~~<br><br>|16<br>~~eG~~<br><br>|8<br>~~eG~~<br><br>|16<br>~~eG~~<br><br>|8<br>~~eG~~<br><br>|16<br>~~eG~~<br>~~GG~~<br><br>~~Gs~~<br>|8<br>~~eG~~<br>~~GG~~<br><br>~~Gs~~<br>|16<br>~~eG~~<br>~~GG~~<br><br>~~Gs~~<br>|8<br>~~eG~~<br>~~GG~~<br><br>~~Gs~~<br>|16<br>~~eG~~<br><br>|8<br>~~eG~~<br><br>|
|X(counts)<br>~~Re~~<br>~~a~~<br>~~a~~<br>~~ee~~|0<br>~~eG~~<br>~~eG~~<br><br>|0<br>~~eG~~<br>~~eG~~<br><br>|-16384 -64<br>~~eG~~<br>~~eG~~<br><br>|-16384 -64<br>~~eG~~<br>~~eG~~<br><br>|0<br>~~eG~~<br>~~eG~~<br><br>|0<br>~~eG~~<br>~~eG~~<br><br>|16384 64<br>~~eG~~<br>~~GG~~<br>~~eG~~<br>~~Gs~~<br><br>~~Gs~~<br>|16384 64<br>~~eG~~<br>~~GG~~<br>~~eG~~<br>~~Gs~~<br><br>~~Gs~~<br>|0<br>~~eG~~<br>~~GG~~<br>~~eG~~<br>~~Gs~~<br><br>~~Gs~~<br>|0<br>~~eG~~<br>~~GG~~<br>~~eG~~<br>~~Gs~~<br><br>~~Gs~~|0<br>~~eG~~<br>~~eG~~<br>|0<br>~~eG~~<br>~~eG~~<br>|
|Y(counts)<br>~~a ~~<br>~~a~~<br>~~ee~~<br>~~a~~|-16384 -64<br> ~~eG~~<br>~~eG~~<br>~~ee~~|-16384 -64<br>~~eG~~<br>~~eG~~<br>~~ee~~|0<br>~~eG~~<br>~~eG~~<br>~~ee~~|0<br>~~eG~~<br>~~eG~~<br>~~ee~~|16384 64<br>~~eG~~<br>~~eG~~<br>~~DGG~~|16384 64<br>~~eG~~<br>~~eG~~<br>~~DGG~~|0<br>~~GG~~<br>~~eG~~<br>~~Gs~~<br>~~eG~~<br>~~Gs~~<br>~~DGG~~|0<br>~~GG~~<br>~~eG~~<br>~~Gs~~<br>~~eG~~<br>~~Gs~~<br>~~DGG~~|0<br>~~GG~~<br>~~eG~~<br>~~Gs~~<br>~~eG~~<br>~~Gs~~<br>~~DGG~~|0<br>~~GG~~<br>~~eG~~<br>~~Gs~~<br>~~eG~~<br>~~Gs~~|0<br>~~eG~~<br>~~eG~~|0<br>~~eG~~<br>~~eG~~|
|Z(counts)<br>~~a ~~<br>~~ee~~<br>~~a~~|0<br> ~~eG~~<br>~~ee~~|0<br>~~eG~~<br>~~ee~~|0<br>~~eG~~<br>~~ee~~|0<br>~~eG~~<br>~~ee~~|0<br>~~eG~~<br>~~DGG~~|0<br>~~eG~~<br>~~DGG~~|0<br>~~Gs~~<br>~~eG~~<br>~~Gs~~<br>~~DGG~~|0<br>~~Gs~~<br>~~eG~~<br>~~Gs~~<br>~~DGG~~|16384 64 -16384 -64<br>~~Gs~~<br>~~eG~~<br>~~Gs~~<br>~~DGG~~|16384 64 -16384 -64<br>~~Gs~~<br>~~eG~~<br>~~Gs~~|16384 64 -16384 -64<br>~~eG~~|16384 64 -16384 -64<br>~~eG~~|
|~~ee ~~<br>~~a~~|~~ee~~||~~ee~~||~~DGG~~||~~Gs~~<br>~~DGG~~||~~Gs~~<br>~~DGG~~||||
|X-Polarity<br> <br>~~a~~<br>~~a~~|**0**<br> ~~ee~~||**-**<br>~~ee ~~||**0**<br> ~~DGG~~||**+**<br>~~DGG~~||**0**<br>~~DGG~~||**0**||
|Y-Polarity<br>~~a~~<br>~~a~~|**-**<br>||**0**<br>||**+**<br>||**0**<br>||**0**<br>||**0**<br>||
|Z-Polarity<br>~~aee~~|**0**<br>~~ee~~||**0**<br>~~ee~~||**0**<br>~~ee~~||**0**<br>~~ee~~||**+**<br>~~ee~~||**-**<br>~~ee~~||
Earth’s Surface
36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - info@kionix.com
© 2016 Kionix – All Rights Reserved
Page 17 of 81
**PART NUMBER: ± 2g / 4g / 8g Tri-axis Digital KX124-1051 Accelerometer Specifications Rev. 1.0 20-Jan-16**
**Static X/Y/Z Output Response versus Orientation to Earth’s surface (1g):**
## GSEL1=0, GSEL0=1 (± 4g)
|**Position **|**1**|**1**|**2**|**2**|**3**|**3**|**4**|**4**|**5**|**5**|**6**|**6**|
|---|---|---|---|---|---|---|---|---|---|---|---|---|
|Diagram<br>~~ee~~|~~ee~~||~~ee~~||~~eeGG~~||~~GG~~||Top<br>Bottom<br>~~GO~~||Bottom<br>Top||
|Resolution(bits)<br>~~ee~~<br>~~oo~~|16<br>~~ee~~|8<br>~~ee~~|16|8<br>~~ee~~|16<br>~~ee~~|8<br>~~GG~~|16<br>~~GG~~|8<br>~~GG~~|16<br>~~GO~~|8<br>~~GO~~|16|8|
|X(counts)<br>~~ee ~~<br>~~oo~~<br>~~oo~~|0<br> ~~ee~~|0<br>~~ee~~|-8192|-32<br>~~ee~~|0<br>~~ee ~~|0<br> ~~GG~~|8192<br>~~GG~~|32<br>~~GG~~|0<br>~~GO~~|0<br>~~GO~~|0|0|
|Y(counts)<br>~~oo~~<br>~~oo~~<br>~~oo~~|-8192<br>|-32<br>|0<br>|0<br>|8192<br>|32<br>|0<br>|0<br>|0<br>|0<br>|0<br>|0<br>|
|Z(counts)<br>~~oo~~<br>~~oo~~|0<br>|0<br>|0<br>|0<br>|0<br>|0<br>|0<br>|0<br>|8192 32<br>|8192 32<br>|-8192<br>|-32<br>|
|~~oose~~<br>~~se~~|~~se~~<br>~~se~~||~~se~~||~~se~~<br>~~(~~||~~se~~<br>~~(~~||~~se~~||~~se~~||
|X-Polarity<br>~~se~~<br>~~se~~<br>~~se~~|**0**<br>~~se~~<br>~~se~~<br>~~se~~||**-**<br>~~se~~<br>~~se~~||**0**<br>~~se~~<br>~~se~~<br>~~(~~||**+**<br>~~se~~<br>~~se~~<br>~~(~~||**0**<br>~~se~~<br>~~se~~||**0**<br>~~se~~<br>~~se~~||
|Y-Polarity<br>~~se~~<br>~~se~~|**-**<br>~~se~~<br>~~se~~||**0**<br>~~se~~<br>~~GG~~||**+**<br>~~se~~<br>~~(~~<br>~~GG~~||**0**<br>~~se~~<br>~~(~~<br>~~GG~~||**0**<br>~~se~~||**0**<br>~~se~~||
|Z-Polarity<br>~~Ce~~|**0**<br>~~Ce~~||**0**<br>~~GF~~||**0**<br>~~GF~~||**0**<br>~~GF~~||**+**||**-**||
~~i~~
**==> picture [48 x 11] intentionally omitted <==**
**----- Start of picture text -----**<br>
(1g)<br>**----- End of picture text -----**<br>
Earth’s Surface
**Static X/Y/Z Output Response versus Orientation to Earth’s surface (1g):**
|**Position**|**1**|**1**|**2**|**2**|**3**|**3**|**4**|**4**|**5**|**5**|**6**|**6**|
|---|---|---|---|---|---|---|---|---|---|---|---|---|
|Diagram<br>~~oo~~|||||||||Top<br>Bottom||Bottom<br>Top||
|Resolution(bits)<br>~~oo~~<br>~~po~~|16<br>|8<br>|16<br>|8<br>|16<br>|8<br>|16<br>|8<br>|16<br>|8<br>|16<br>|8<br>|
|X(counts)<br>~~oo~~<br>~~po~~|0<br>|0<br><br>~~Gn~~|-4096<br><br>~~eG~~|-16<br><br>~~eG~~|0<br><br>~~eG~~|0<br><br>~~GO~~|4096<br><br>~~GO~~|16<br><br>~~GOO~~|0<br><br>~~GOO~~|0<br><br>~~GO~~|0<br>|0<br>|
|Y(counts)<br>~~poee~~|-4096<br>~~ee~~|-16<br>~~ee~~<br>~~Gn~~|0<br>~~ee~~<br>~~eG~~|0<br>~~ee~~<br>~~eG~~|4096<br>~~ee~~<br>~~eG~~|16<br>~~ee~~<br>~~GO~~|0<br>~~ee~~<br>~~GO~~|0<br>~~ee~~<br>~~GOO~~|0<br>~~ee~~<br>~~GOO~~|0<br>~~ee~~<br>~~GO~~|0<br>~~ee~~|0<br>~~ee~~|
|Z(counts)<br>~~ee~~<br>~~po~~|0<br>~~ee~~<br>~~po~~|0<br>~~ee~~<br>~~Gn~~<br>~~po~~|0<br>~~ee~~<br>~~eG~~<br>~~po~~|0<br>~~ee~~<br>~~eG~~<br>~~po~~|0<br>~~ee~~<br>~~eG~~<br>~~po~~|0<br>~~ee~~<br>~~GO~~<br>~~po~~|0<br>~~ee~~<br>~~GO ~~<br>~~po~~|0<br>~~ee~~<br> ~~GOO~~<br>~~po~~|4096 16<br>~~ee~~<br>~~GOO~~<br>~~po~~|4096 16<br>~~ee~~<br>~~GO~~<br>~~po~~|-4096<br>~~ee~~<br>~~po~~|-16<br>~~ee~~<br>~~po~~|
|~~po~~<br>~~SG~~|~~po~~<br>~~SG~~||~~po~~<br>~~SG~~||~~po~~<br>~~SG~~||~~po~~<br>~~SG~~||~~po~~<br>~~SG~~||~~po~~<br>~~SG~~||
|X-Polarity<br>~~Ge~~|**0**<br>~~Ge~~||**-**<br>~~GG~~||**0**<br>~~GG~~<br>~~GG~~||**+**<br>~~GG~~<br>~~GG~~||**0**<br>~~OO~~||**0**||
|Y-Polarity<br>~~Ge~~<br>~~eG~~|**-**<br>~~Ge~~<br>~~eG~~||**0**<br>~~GG~~<br>~~eG~~||**+**<br>~~GG~~<br>~~eG~~<br>~~GG~~||**0**<br>~~GG~~<br>~~eG~~<br>~~GG~~<br>~~DO~~||**0**<br>~~eG~~<br>~~OO~~||**0**<br>~~eG~~||
|Z-Polarity<br>~~eG~~|**0**<br>~~eG~~||**0**<br>~~eG~~||**0**<br>~~GG~~<br>~~eG~~||**0**<br>~~GG~~<br>~~eG~~<br>~~DO~~||**+**<br>~~OO~~<br>~~eG~~||**-**<br>~~eG~~||
(1g)
Earth’s Surface
36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - info@kionix.com
© 2016 Kionix – All Rights Reserved
Page 18 of 81
||**PART NUMBER:**|
|---|---|
|**± 2g / 4g / 8g Tri-axis Digital**|**KX124-1051**|
|**Accelerometer Specifications**|**Rev. 1.0**|
||**20-Jan-16**|
## **Digital Interface**
The Kionix KX124 digital accelerometer has the ability to communicate via the I[2] C and SPI digital serial interface protocols. This allows for easy system integration by eliminating analog-to-digital converter requirements and by providing direct communication with system micro-controllers.
The serial interface terms and descriptions as indicated in Table 6 below will be observed throughout this document.
|**Term**<br>**Description **<br>Transmitter<br>The device that transmits data to the bus.<br>Receiver<br>The device that receives data from the bus.<br>Master<br>The device that initiates a transfer, generates clock signals, and terminates a transfer.<br>Slave<br>The device addressed by the Master.<br>~~—————~~|**Term**<br>**Description **<br>Transmitter<br>The device that transmits data to the bus.<br>Receiver<br>The device that receives data from the bus.<br>Master<br>The device that initiates a transfer, generates clock signals, and terminates a transfer.<br>Slave<br>The device addressed by the Master.<br>~~—————~~||
|---|---|---|
||**Table 6:**Serial Interface Terminologies||
|**I2C Serial Interface**|||
|As previously mentioned, the KX124 accelerometer has the ability to communicate on an I2C bus. I2C is primarily|||
|used for synchronous serial communication between a Master device and one or more Slave devices. The|||
|Master, typically a micro controller, provides the serial clock signal and addresses Slave devices on the bus.|||
|The KX124 always operates as a Slave device during standard Master-Slave I2C operation.|||
I[2] C is a two-wire serial interface that contains a Serial Clock (SCL) line and a Serial Data (SDA) line. SCL is a serial clock that is provided by the Master, but can be held low by any Slave device, putting the Master into a wait condition. SDA is a bi-directional line used to transmit and receive data to and from the interface. Data is transmitted MSB (Most Significant Bit) first in 8-bit per byte format, and the number of bytes transmitted per transfer is unlimited. The I[2] C bus is considered free when both lines are high.
The I2C interface is compliant with high-speed mode, fast mode and standard mode I2C protocols.
36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - info@kionix.com
© 2016 Kionix – All Rights Reserved
Page 19 of 81
**==> picture [499 x 66] intentionally omitted <==**
**----- Start of picture text -----**<br>
PART NUMBER:<br>± 2g / 4g / 8g Tri-axis Digital KX124-1051<br>Accelerometer Specifications Rev. 1.0<br>6Ktonix:<br>20-Jan-16<br>**----- End of picture text -----**<br>
## **I[2] C Operation**
Transactions on the I2C bus begin after the Master transmits a start condition (S), which is defined as a high-tolow transition on the data line while the SCL line is held high. The bus is considered busy after this condition. The next byte of data transmitted after the start condition contains the Slave Address (SAD) in the seven MSBs (Most Significant Bits), and the LSB (Least Significant Bit) tells whether the Master will be receiving data ‘1’ from the Slave or transmitting data ‘0’ to the Slave. When a Slave Address is sent, each device on the bus compares the seven MSBs with its internally stored address. If they match, the device considers itself addressed by the Master. The KX124 Slave Address is comprised of a user programmable part, a factory programmable part, and a fixed part, which allows for connection of multiple accelerometers to the same I[2] C bus. The Slave Address associated with the KX124 is 00111YX, where the user programmable bit X, is determined by the assignment of ADDR (pin 1) to GND or IO_VDD. Also, the factory programmable bit Y is set at the factory. **For KX124-1051, the factory programmable bit Y is fixed to 1** (contact your Kionix sales representative for list of available devices). Table 7 lists possible I[2] C addresses for KX124-1051. As a result, up to four accelerometers can be implemented on a shared I[2] C bus as shown in Figure 1 on the next page (e.g. two KX124-1051 accelerometers and two other accelerometers with factory programmable bit Y set to 0).
~~rd~~ **Y X 7 bit Description[Address ] Pad Address[Address <7> <6> <5> <4> <3> <2> <1> <0> ]** ~~eee~~ I2C Wr IO_VDD 0x1F 0x3E 0 0 1 1 1 **1** 1 0 ~~a~~ I2C Rd IO_VDD ~~Oa~~ 0x1F 0x3F ~~OO~~ 0 0 1 1 1 **1** 1 1 ~~a~~ I2C Wr GND 0x1E 0x3C ~~OO~~ 0 0 1 1 1 **1** 0 0 ~~FOSS~~ I2C Rd GND 0x1E 0x3D 0 0 1 1 1 **1** 0 1
**Table 7:** I[2] C Slave Addresses for KX124-1051
It is mandatory that receiving devices acknowledge (ACK) each transaction. Therefore, the transmitter must release the SDA line during this ACK pulse. The receiver then pulls the data line low so that it remains stable low during the high period of the ACK clock pulse. A receiver that has been addressed, whether it is Master or Slave, is obliged to generate an ACK after each byte of data has been received. To conclude a transaction, the Master must transmit a stop condition (P) by transitioning the SDA line from low to high while SCL is high. The I[2] C bus is now free. Note that if the accelerometer is accessed through I[2] C protocol before the startup is finished a NACK signal is sent.
36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - info@kionix.com
© 2016 Kionix – All Rights Reserved
Page 20 of 81
6Kionix’
**± 2g / 4g / 8g Tri-axis Digital**
**Accelerometer Specifications**
**PART NUMBER: KX124-1051**
**Rev. 1.0**
**20-Jan-16**
**==> picture [319 x 403] intentionally omitted <==**
**----- Start of picture text -----**<br>
IO_VDD<br>MCU KX124-1051<br>SDA<br>Bit Y (Bit 1 in 7-bit address)<br>SCL Factory Set to 1<br>ADDR<br>KX124-1051<br>SDA<br>Bit Y (Bit 1 in 7-bit address)<br>SCL Factory Set to 1<br>ADDR<br>GND<br>IO_VDD<br>* KXMMM<br>SDA<br>Bit Y (Bit 1 in 7-bit address)<br>SCL Factory Set to 0<br>ADDR<br>* KXMMM<br>SDA<br>Bit Y (Bit 1 in 7-bit address)<br>SCL Factory Set to 0<br>ADDR<br>GND<br>**----- End of picture text -----**<br>
## **Figure 1:** Multiple KX124 Accelerometers on a Shared I[2] C Bus
* KXMMM – contact Kionix sales representative for list of compatible devices
36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - info@kionix.com
© 2016 Kionix – All Rights Reserved
Page 21 of 81
**==> picture [499 x 66] intentionally omitted <==**
**----- Start of picture text -----**<br>
PART NUMBER:<br>± 2g / 4g / 8g Tri-axis Digital KX124-1051<br>Accelerometer Specifications Rev. 1.0<br>6Kionix’<br>20-Jan-16<br>**----- End of picture text -----**<br>
## **Writing to accelerometer’s 8-bit Register**
Upon power up, the Master must write to the KX124 accelerometer’s control registers to set its operational mode. Therefore, when writing to a control register on the I[2] C bus, as shown Sequence 1 on the following page, the following protocol must be observed: After a start condition, SAD+W transmission, and the accelerometer’s ACK has been returned, an 8-bit Register Address (RA) command is transmitted by the Master. This command is telling the accelerometer to which 8-bit register the Master will be writing the data. Since this is I[2] C mode, the MSB of the RA command should always be zero (0). The accelerometer acknowledges the RA and the Master transmits the data to be stored in the 8-bit register. The accelerometer acknowledges that it has received the data and the Master transmits a stop condition (P) to end the data transfer. The data sent to the accelerometer is now stored in the appropriate register. The accelerometer automatically increments the received RA commands and, therefore, multiple bytes of data can be written to sequential registers after each Slave ACK as shown in Sequence 2 on the following page.
Note** If a STOP condition is sent on the least significant bit of write data or the following master acknowledge cycle, the last write operation is not guaranteed and it may alter the content of the affected registers
## **Reading from accelerometer’s 8-bit Register**
When reading data from a KX124 accelerometer’s 8-bit register on the I[2] C bus, as shown in Sequence 3 on the next page, the following protocol must be observed: The Master first transmits a start condition (S) and the appropriate Slave Address (SAD) with the LSB set at ‘0’ to write. The accelerometer acknowledges and the Master transmits the 8-bit RA of the register it wants to read. The accelerometer again acknowledges, and the Master transmits a repeated start condition (Sr). After the repeated start condition, the Master addresses the accelerometer with a ‘1’ in the LSB (SAD+R) to read from the previously selected register. The Slave then acknowledges and transmits the data from the requested register. The Master does not acknowledge (NACK) it received the transmitted data, but transmits a stop condition to end the data transfer. The accelerometer automatically increments through its sequential registers, allowing data to be read from multiple registers following a single SAD+R command as shown below in Sequence 4 on the following page. Reading data from a buffer read register is a special case because if register address (RA) is set to buffer read register (BUF_READ) in Sequence 4, the register auto-increment feature is automatically disabled. Instead, the Read Pointer will increment to the next data in the buffer, thus allowing reading multiple bytes of data from the buffer using a single SAD+R command.
Note** Accelerometer’s output data should be read in a single transaction using the auto-increment feature to prevent output data from being updated prior to intended completion of the read transaction.
36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - info@kionix.com
© 2016 Kionix – All Rights Reserved
Page 22 of 81
**PART NUMBER: ± 2g / 4g / 8g Tri-axis Digital KX124-1051 Accelerometer Specifications Rev. 1.0 20-Jan-16** ~~Chow} |~~ **Data Transfer Sequences** The following information clearly illustrates the variety of data transfers that can occur on the I[2] C bus and how the Master and Slave interact during these transfers. Table 8 defines the I[2] C terms used during the data transfers.
|**Term**|**Definition **|
|---|---|
|S|Start Condition|
|Sr|Repeated Start Condition|
|SAD|Slave Address|
|W|WriteBit|
|R|Read Bit|
|ACK|Acknowledge|
|NACK|NotAcknowledge|
|RA|Register Address|
|Data|Transmitted/Received Data|
|P|Stop Condition|
**Table 8:** I[2] C Terms
**Sequence 1:** The Master is writing one byte to the Slave.
|Master<br>S<br>SAD + W<br>RA<br>Slave<br>ACK<br>ACK<br>~~—~~|DATA<br>ACK<br>ACK|P<br>ACK|||||||||
|---|---|---|---|---|---|---|---|---|---|---|
|**Sequence 2**: The Master is writing multiple bytes to the Slave.|||||||||||
|Master<br>S<br>SAD + W<br>RA<br>Slave<br>ACK<br>ACK<br>~~— a~~|DATA<br>K<br>ACK|DATA<br>K||ACK|K|P|||||
|**Sequence 3:**The Master is receiving one byte of data from the Slave.|||||||||||
|Master<br>S<br>SAD + W<br>RA<br>Slave<br>ACK<br>ACK<br>~~—~~|Sr<br>SAD + R<br>K<br>ACK|K<br>DATA||NACK||NACK<br>P|||||
|**Sequence 4:**The Master is receiving multiple bytes of data from the Slave.|||The Master is receiving multiple bytes of data from the Slave.||||||||
|Master<br>S<br>SAD + W<br>RA<br>Sr<br>SAD + R<br>ACK<br>NACK<br>P<br>Slave<br>ACK<br>ACK<br>ACK<br>DATA<br>DATA<br>~~—— ee~~<br>~~ee~~<br>~~ee~~|||||||||||
|36 Thornwood Dr. – Ithaca, NY 14850||||© 2016 Kionix – All Rights Reserved||© 2016 Kionix – All Rights Reserved||||© 2016 Kionix – All Rights Reserved|
36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - info@kionix.com
Page 23 of 81
||**PART NUMBER:**|
|---|---|
|**± 2g / 4g / 8g Tri-axis Digital**|**KX124-1051**|
|**Accelerometer Specifications**|**Rev. 1.0**|
||**20-Jan-16**|
## **HS-mode**
To enter the 3.4MHz high speed mode of communication, the device must receive the following sequence of conditions from the master: a Start condition followed by a Master code (00001XXX) and a Master Nonacknowledge. Once recognized, the device switches to HS-mode communication. Read/write data transfers then proceed as described in the sequences above. Devices return to the FS-mode after a STOP occurrence on the bus.
## **Sequence 5:** HS-mode data transfer of the Master writing multiple bytes to the Slave.
|Speed<br>~~————~~|FS-mode<br>~~————~~|FS-mode<br>~~————~~|FS-mode<br>~~————~~|HS-mode|HS-mode|HS-mode|HS-mode|HS-mode|HS-mode|HS-mode|HS-mode|FS-mode|
|---|---|---|---|---|---|---|---|---|---|---|---|---|
|Master<br>~~————~~|S<br>~~————~~|M-code NACK Sr<br>~~————~~|code NACK Sr|code NACK Sr|SAD + W||RA||DATA||P||
|Slave<br>~~————~~|~~————~~|~~————~~||||ACK|ACK|ACK|ACK|ACK|||
**Sequence 6:** HS-mode data transfer of the Master receiving multiple bytes of data from the Slave.
|Speed<br>FS-mode<br>HS-mode<br>Master<br>S<br>M-code NACK Sr<br>SAD + W<br>RA<br>Slave<br>ACK<br>ACK<br>~~———~~|Speed<br>FS-mode<br>HS-mode<br>Master<br>S<br>M-code NACK Sr<br>SAD + W<br>RA<br>Slave<br>ACK<br>ACK<br>~~———~~|ACK||
|---|---|---|---|
|Speed<br>HS-mode<br>FS-mode<br>Master<br>Sr<br>SAD+R<br>NACK<br>P<br>Slave<br>ACK<br>DATA<br>ACK<br>DATA<br>~~————~~||||
|(n-1) bytes + ack.||||
36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - info@kionix.com
© 2016 Kionix – All Rights Reserved
Page 24 of 81
**PART NUMBER: ± 2g / 4g / 8g Tri-axis Digital KX124-1051 Accelerometer Specifications Rev. 1.0 20-Jan-16** ~~CsStoneFf~~ **I[2] C Timing Diagram**
**Table 9:** I[2] C Timing (Fast Mode)
**==> picture [436 x 186] intentionally omitted <==**
**----- Start of picture text -----**<br>
sn Number Description MIN MAX Units<br>se t0 SDA low to SCL low transition (Start event) 50 - ns<br>se t1 SDA low to first SCL rising edge 100 - ns<br>se t2 SCL pulse width: high 100 - ns<br>se t3 SCL pulse width: low 100 - ns<br>t4 SCL high before SDA falling edge (Start Repeated) 50 - ns<br>es<br>Rs t5 SCL pulse width: high during a S/Sr/P event 100 - ns<br>t6 SCL high before SDA rising edge (Stop) 50 - ns<br>es<br>t7 SDA pulse width: high 25 - ns<br>es<br>t8 SDA valid to SCL rising edge 50 - ns<br>es<br>t9 SCL rising edge to SDA invalid 50 - ns<br>es<br>t10 SCL falling edge to SDA valid (when slave is transmitting) - 100 ns<br>es<br>t11 SCL falling edge to SDA invalid (when slave is transmitting) 0 - ns<br>es<br>Note Recommended I [2] C CLK 2.5 - us<br>Rs<br>**----- End of picture text -----**<br>
36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - info@kionix.com
© 2016 Kionix – All Rights Reserved
Page 25 of 81
**==> picture [347 x 66] intentionally omitted <==**
**----- Start of picture text -----**<br>
PART NUMBER:<br>± 2g / 4g / 8g Tri-axis Digital KX124-1051<br>Accelerometer Specifications Rev. 1.0<br>20-Jan-16<br>**----- End of picture text -----**<br>
## **SPI Communications**
## **4-Wire SPI Interface**
The KX124 also utilize an integrated 4-Wire Serial Peripheral Interface (SPI) for digital communication. The SPI interface is primarily used for synchronous serial communication between one Master device and one or more Slave devices. The Master, typically a micro controller, provides the SPI clock signal (SCLK) and determines the state of Chip Select (nCS). The accelerometer always operates as a Slave device during standard MasterSlave SPI operation.
4-wire SPI is a synchronous serial interface that uses two control and two data lines. With respect to the Master, the Serial Clock output (SCLK), the Data Output (SDI or MOSI) and the Data Input (SDO or MISO) are shared among the Slave devices. The Master generates an independent Chip Select (nCS) for each Slave device that goes low at the start of transmission and goes back high at the end. The Slave Data Output (SDO) line, remains in a high-impedance (hi-z) state when the device is not selected, so it does not interfere with any active devices. This allows multiple Slave devices to share a master SPI port as shown in Figure 2 below.
**Figure 2:** 4-wire SPI Connections
36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - info@kionix.com
© 2016 Kionix – All Rights Reserved
Page 26 of 81
**==> picture [508 x 251] intentionally omitted <==**
**----- Start of picture text -----**<br>
PART NUMBER:<br>± 2g / 4g / 8g Tri-axis Digital KX124-1051<br>Accelerometer Specifications Rev. 1.0<br>« Kionix’<br>20-Jan-16<br>The<br>4-Wire SPI Timing Diagram<br>t3 t1 t2 t4<br>nCS<br>HAT<br>CLK<br>PLL LLL<br>SDI bit 7 bit 6 bit 1 bit 0 bit 7 bit 6 bit 1 bit 0<br>SDO bit 7 bit 6 bit 1 bit 0<br>t5<br>EI t6 t7 IE<br>**----- End of picture text -----**<br>
**Table 10:** 4-Wire SPI Timing
|**Number**|**Description**|**MIN MAX**|**MIN MAX**|**Units**|
|---|---|---|---|---|
|t1|CLKpulsewidth: high|40||ns|
|t2|CLK pulse width: low|40||ns|
|t3|nCS low to first CLK rising edge|20||ns|
|t4|nCS low after the final CLK rising edge|30||ns|
|t5|SDI valid to CLK rising edge|10||ns|
|t6|CLK rising edge to SDI invalid|10||ns|
|t7|CLK falling edge to SDO valid||35|ns|
Notes
1. t7 is only present during reads.
2. Timings are for VDD of 1.8V to 3.6V with 1K pull-up resistor and maximum 20pF load capacitor on SDO.
36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - info@kionix.com
© 2016 Kionix – All Rights Reserved
Page 27 of 81
**==> picture [347 x 66] intentionally omitted <==**
**----- Start of picture text -----**<br>
PART NUMBER:<br>± 2g / 4g / 8g Tri-axis Digital KX124-1051<br>Accelerometer Specifications Rev. 1.0<br>20-Jan-16<br>**----- End of picture text -----**<br>
## **4-Wire Read and Write Registers**
The registers embedded in the KX124 accelerometer have 8-bit addresses. Upon power up, the Master must write to the accelerometer’s control registers to set its operational mode. On the falling edge of nCS, a 2-byte command is written to the appropriate control register. The first byte initiates the write to the appropriate register, and is followed by the user-defined, data byte. The MSB (Most Significant Bit) of the register address byte will indicate “0” when writing to the register and “1” when reading from the register. This operation occurs over 16 clock cycles. All commands are sent MSB first. The host must return nCS high for at least one clock cycle before the next data request. However, when data is being read from a buffer read register (BUF_READ), the nCS signal can remain low until the buffer is read. Figure 3 below shows the timing diagram for carrying out an 8-bit register write operation.
**==> picture [330 x 66] intentionally omitted <==**
**----- Start of picture text -----**<br>
Write Address First 8 bits Second 8 bits Last 8 bits<br>CLK<br>SDI A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D2 D1 D0<br>SDO HI-Z HI-Z<br>A EE Mie<br>CS<br>**----- End of picture text -----**<br>
**Figure 3:** Timing Diagram for 8-Bit Register Write Operation
In order to read an 8-bit register, an 8-bit register address must be written to the accelerometer to initiate the read. The MSB of this register address byte will indicate “0” when writing to the register and “1” when reading from the register. Upon receiving the address, the accelerometer returns the 8-bit data stored in the addressed register. This operation also occurs over 16 clock cycles. All returned data is sent MSB first, and the host must return nCS high for at least one clock cycle before the next data request. Figure 4 shows the timing diagram for an 8-bit register read operation.
**==> picture [334 x 66] intentionally omitted <==**
**----- Start of picture text -----**<br>
Read Address First 8 bits Second 8 bits Last 8 bits<br>CLK<br>SDI A7 A6 A5 A4 A3 A2 A1 A0<br>SDO HI-Z D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D3 D2 D1 D0 HI-Z<br>CS<br>**----- End of picture text -----**<br>
**Figure 4:** Timing Diagram for 8-Bit Register Read Operation
36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - info@kionix.com
© 2016 Kionix – All Rights Reserved
Page 28 of 81
**PART NUMBER: ± 2g / 4g / 8g Tri-axis Digital KX124-1051 Accelerometer Specifications Rev. 1.0 20-Jan-16** KI0" IX . ~~fe~~ **3-Wire SPI Interface** The KX124 also utilize an integrated 3-Wire Serial Peripheral Interface (SPI) for digital communication. 3-wire SPI is a synchronous serial interface that uses two control lines and one data line. With respect to the Master, the Serial Clock output (SCLK), the Data Output/Input (SDI) are shared among the Slave devices. The Master generates an independent Chip Select (nCS) for each Slave device that goes low at the start of transmission and goes back high at the end. This allows multiple Slave devices to share a master SPI port as shown in Figure 5 below.
**Figure 5:** 3-wire SPI Connections
36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - info@kionix.com
© 2016 Kionix – All Rights Reserved
Page 29 of 81
**PART NUMBER: ± 2g / 4g / 8g Tri-axis Digital KX124-1051 Accelerometer Specifications Rev. 1.0** 6Kionix’ **20-Jan-16**
## **3-Wire SPI Timing Diagram**
**==> picture [474 x 122] intentionally omitted <==**
**----- Start of picture text -----**<br>
t3 t1 t2 t4<br>nCS<br>—<br> CLK<br>Ne ee eee ee<br>SDI bit 7 bit 6 bit 1 bit 0 bit 7 bit 1 bit 0<br>YI t5 t6 IO t7 t8<br>Table 11: 3-Wire SPI Timing<br>**----- End of picture text -----**<br>
|**Number**|**Description**|**MIN**|**MAX Units**|**MAX Units**|
|---|---|---|---|---|
|t1|**Description**<br>CLK pulse width: high|40|-|ns|
|t2|CLK pulse width: high<br>CLK pulse width: low|40|-|ns|
|t3|CLK pulse width: low<br>nCS low to first CLK rising edge|20|-|ns|
|t4|nCS low to first CLK rising edge<br>nCS low after the final CLK falling edge|20|-|ns|
|t5|nCS low after the final CLK falling edge<br>SDI valid to CLK rising edge|10|-|ns|
|t6|SDI valid to CLK rising edge<br>CLK rising edge to SDI input invalid|10|-|ns|
|t7|CLK rising edge to SDI input invalid<br>CLK extra clock cycle rising edge to SDI output|-|-|ns|
|t8|CLK extra clock cycle rising edge to SDI output<br>CLK falling edge to SDI output becomes valid|-|35|ns|
## Notes
1. t7 and t8 are only present during reads.
2. Timings are for VDD of 1.8V to 3.6V with 1K pull-up resistor and maximum 20pF load capacitor on SDI.
36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - info@kionix.com
© 2016 Kionix – All Rights Reserved
Page 30 of 81
**PART NUMBER: ± 2g / 4g / 8g Tri-axis Digital KX124-1051 Accelerometer Specifications Rev. 1.0** [<Kionix’ **20-Jan-16**
## **3-Wire Read and Write Registers**
The registers embedded in the KX124 accelerometer have 8-bit addresses. Upon power up, the Master must write to the accelerometer’s control registers to set its operational mode. On the falling edge of nCS, a 2-byte command is written to the appropriate control register. The first byte initiates the write to the appropriate register, and is followed by the user-defined, data byte. The MSB (Most Significant Bit) of the register address byte will indicate “0” when writing to the register and “1” when reading from the register. A read operation occurs over 17 clock cycles and a write operation occurs over 16 clock cycles. All commands are sent MSB first. The host must return nCS high for at least one clock cycle before the next data request. However, when data is being read from a buffer read register (BUF_READ), the nCS signal can remain low until the buffer is read. Figure 6 below shows the timing diagram for carrying out an 8-bit register write operation.
**==> picture [305 x 60] intentionally omitted <==**
**----- Start of picture text -----**<br>
SCLK LU UU<br>SDI 00000000000000000! A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0<br>mn (MSB) (MSB)<br>CS ea e<br>**----- End of picture text -----**<br>
**Figure 6:** Timing Diagram for 8-Bit Register Write Operation
In order to read an 8-bit register, an 8-bit register address must be written to the accelerometer to initiate the read. The MSB of this register address byte will indicate “0” when writing to the register and “1” when reading from the register. Upon receiving the address, the accelerometer returns the 8-bit data stored in the addressed register. For 3-wire read operations, one extra clock cycle between the address byte and the data output byte is required. Therefore, this operation occurs over 17 clock cycles. All returned data is sent MSB first, and the host must return nCS high for at least one clock cycle before the next data request. Figure 7 shows the timing diagram for an 8-bit register read operation.
**==> picture [303 x 48] intentionally omitted <==**
**----- Start of picture text -----**<br>
SCLK<br>SDI 0000000000000000 A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 -— HI-Z<br>[mn (MSB) 0 (MSB)<br>Oe<br>CS<br>**----- End of picture text -----**<br>
**Figure 7:** Timing Diagram for 8-Bit Register Read Operation
36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - info@kionix.com
© 2016 Kionix – All Rights Reserved
Page 31 of 81
||**PART NUMBER:**|
|---|---|
|**± 2g / 4g / 8g Tri-axis Digital**|**KX124-1051**|
|**Accelerometer Specifications**|**Rev. 1.0**<br>**20-Jan-16**|
## **Embedded Registers**
The KX124 accelerometer has 57 embedded 8-bit registers that are accessible by the user. This section contains the addresses for all embedded registers and also describes bit functions of each register. Table 12 below provides a listing of the accessible 8-bit registers and their addresses.
**==> picture [389 x 418] intentionally omitted <==**
**----- Start of picture text -----**<br>
| Address Register Name R/W Address Register Name R/W<br>ee 00h XHPL ee ee R a 21h ee INC6* R/W<br>es 01h XHPH ee R ee 22h ee TILT_TIMER* R/W<br>es 02h YHPL ee ee R a 23h ee WUFC* R/W<br>03h YHPH R 24h TDTRC* R/W<br>es ee ee a eeee<br>04h ZHPL R 25h TDTC* R/W<br>es ee ee a eeee<br>05h ZHPH R 26h TTH* R/W<br>es ee ee a eeee<br>06h XOUTL R 27h TTL* R/W<br>es ee ee a eeee<br>07h XOUTH R 28h FTD* R/W<br>es ee ee a eeee<br>08h YOUTL R 29h STD* R/W<br>es ee ee a eeee<br>09h YOUTH R 2Ah TLT* R/W<br>es ee ee a eeee<br>0Ah ZOUTL R 2Bh TWS* R/W<br>es ee ee a eeee<br>0Bh ZOUTH R 2Ch FFTH* R/W<br>es ee ee a eeee<br>0Ch COTR R 2Dh FFC* R/W<br>es ee ee a eeee<br>0Dh Kionix Reserved 2Eh FFCNTL* R/W<br>es ee ee a eeee<br>0Eh Kionix Reserved 2Fh Kionix Reserved<br>ee ee<br>ee 0Fh Who_ ee AM_I R/W a 30h ee ATH* R/W<br>10h TSCP R 31h Kionix Reserved<br>ee ee ee ee<br>ee 11h TS ee PP R ee 32h TILT_AN ee GLE_LL* R/W<br>ee 12h IN ee S1 R ee 33h TILT_AN ee GLE_HL* R/W<br>ee 13h IN ee S2 R ee 34h HYST ee _SET* R/W<br>ee 14h IN ee S3 R ee 35h LP_C ee NTL* R/W<br>15h STAT R 36h Kionix Reserved<br>ee ee ee ee<br>16h Kionix Reserved 37h Kionix Reserved<br>ee ee ee ee<br>ee 17h INT_REL ee R ee 38h Kionix Reserved ee<br>18h CNTL1* R/W 39h Kionix Reserved<br>ee ee ee ee<br>ee 19h CNTL2* ee R/W ee 3Ah BUF_C ee NTL1* R/W<br>a 1Ah CNTL ee 3* R ee /W aee 3Bh ee BUF_CNTL2* R/W<br>a 1Bh ODC ee NTL* R ee /W ee 3Ch ee BUF_STATUS_1 R ee<br>a 1Ch INC1* R/W 3Dh BUF_STATUS_2 R ee<br>a 1Dh IN ee C2* R eeee /W esa 3Eh e BUF_C e LEAR e ee W<br>es 1Eh IN ee C3* R ee /W a 3Fh ee BUF_READ R ee<br>es 1Fh IN ee C4* R ee /W a 60h ee SELF_TEST R ee /W<br>20h INC5* R/W<br>es ee ee a ee ee<br>**----- End of picture text -----**<br>
- Note: - When changing the contents of these registers, the PC1 bit in CNTL1 must first be set to “0”. - Reserved registers should not be written.
**Table 12:** Register Map
36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - info@kionix.com
© 2016 Kionix – All Rights Reserved
Page 32 of 81
## 6KTonix:
**PART NUMBER: ± 2g / 4g / 8g Tri-axis Digital KX124-1051 Accelerometer Specifications Rev. 1.0 20-Jan-16**
## **Register Descriptions**
## **Accelerometer Outputs**
These registers contain up to 16-bits of valid acceleration data for each axis. Depending on the setting of the RES bit in CNTL1, the user may choose to read only the 8 MSB thus reading an effective 8-bit resolution. When BRES = 0 in BUF_CNTL2 the 8 MSB is the only data recorded in the buffer. The data is updated every user-defined ODR period, is protected from overwrite during each read, and can be converted from digital counts to acceleration (g) per Table 13 below. The register acceleration output binary data is represented in 2’s complement format. For example, if N = 16 bits, then the Counts range is from -32768 to 32767, and if N = 8 bits, then the Counts range is from -128 to 127.
||**16-bit**|**Equivalent**|||
|---|---|---|---|---|
||**Register Data**|**Counts in**|||
|**(2’s complement)**<br>0111 1111 1111 1111<br>0111 1111 1111 1110<br>…<br>0000 0000 0000 0001<br>0000 0000 0000 0000<br>1111 1111 1111 1111<br>…<br>1000 0000 0000 0001<br>1000 0000 0000 0000<br>~~ee ~~<br>~~ee ~~<br>~~ee ~~<br>~~ee ~~<br>~~ee ~~<br>~~ee es~~<br>~~ee ~~<br>~~ee ~~<br>~~ee Ps~~||**decimal**<br>32767<br>32766<br>…<br>1<br>0<br>-1<br>…<br>-32767<br>-32768<br> ~~es~~<br> ~~es~~<br> ~~es~~<br> ~~es~~<br> ~~es~~<br>~~es~~<br> ~~es~~<br> ~~es~~<br>~~Ps es~~|**Range =±2g**<br>**Range =±4g**<br>+1.99994g<br>+3.99988g<br>+1.99988g<br>+3.99976g<br>…<br>…<br>+0.00006g<br>+0.00012g<br>0.000g<br>0.0000g<br>-0.00006g<br>-0.00012g<br>…<br>…<br>-1.99994g<br>-3.99988g<br>-2.00000g<br>-4.00000g<br>~~rrr es~~<br>~~rrr es~~<br>~~rrr es~~<br>~~rrr es~~<br>~~rrr es~~<br>~~errs~~<br>~~rn es~~<br>~~rn es~~<br>~~es es~~|**Range =±8g**<br>+7.99976g<br>+7.99951g<br>…<br>+0.00024g<br>0.0000g<br>-0.00024g<br>…<br>-7.99976g<br>-8.00000g|
||**8-bit**|**Equivalent**|||
||**Register Data**|**Counts in**|||
||**(2’s complement)**|**decimal **|**Range =±2g**<br>**Range =±4g**|**Range =±8g**|
|0111 1111<br>0111 1110<br>…<br>0000 0001<br>0000 0000<br>1111 1111<br>…<br>1000 0001<br>1000 0000<br>~~ee ees~~<br>~~ee ees~~<br>~~ee ees~~<br>~~ee ees~~<br>~~ee es~~<br>~~ee ~~<br>~~ee ~~<br>~~ee ~~<br>~~ee~~||127<br>+1.9844g<br>+3.9688g<br>126<br>+1.9688g<br>+3.9375g<br>…<br>…<br>…<br>1<br>+0.0156g<br>+0.0313g<br>0<br>0.0000g<br>0.0000g<br>-1<br>-0.0156g<br>-0.0313g<br>…<br>…<br>…<br>-127<br>-1.9844g<br>-3.9688g<br>-128<br>-2.000g<br>-4.000g<br>~~ees ere~~<br>~~es~~<br>~~ees ere~~<br>~~es~~<br>~~ees ere~~<br>~~es~~<br>~~ees er es~~<br>~~es errs~~<br> ~~es eeses~~<br> ~~es eeses~~<br> ~~es eeses~~<br>~~esees~~<br>~~es~~||+7.9375g<br>+7.8750g<br>…<br>+0.0625g<br>0.0000g<br>-0.0625g<br>…<br>-7.9375g<br>-8.000g|
**Table 13:** Acceleration (g) Calculation
36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - info@kionix.com
© 2016 Kionix – All Rights Reserved
Page 33 of 81
**± 2g / 4g / 8g Tri-axis Digital Accelerometer Specifications**
**PART NUMBER: KX124-1051 Rev. 1.0 20-Jan-16**
## **XHP_L**
X-axis high pass filter accelerometer output least significant byte. Data is updated at the ODR frequency determined by OWUF in CNTL3.
R R R R R R R R XHPD7 XHPD6 XHPD5 XHPD4 XHPD3 XHPD2 XHPD1 XHPD0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 ~~a~~ I[2] C Address: 0x00h **XHP_H** X-axis high pass filter accelerometer output most significant byte. Data is updated at the ODR frequency determined by OWUF in CNTL3.
|R<br>R<br>R<br>R<br>R<br>R<br>R<br>R||
|---|---|
|XHPD15<br>XHPD14<br>XHPD13<br>XHPD12<br>XHPD11<br>XHPD10<br>XHPD9<br>XHPD8<br>Bit7<br>Bit6<br>Bit5<br>Bit4<br>Bit3<br>Bit2<br>Bit1<br>Bit0<br>I2CAddress:0x01h<br>~~——ee~~<br>~~oe~~||
|**YHP_L**||
|Y-axis high pass filter accelerometer output least significant byte. Data is updated at the ODR||
|frequency determined by OWUF in CNTL3.||
|YHPD7<br>~~—~~|YHPD6<br>~~ee~~|YHPD5<br>~~ee~~|YHPD4|YHPD3|YHPD2|YHPD1|YHPD0|
|---|---|---|---|---|---|---|---|
|Bit7<br>~~—~~|Bit6<br>~~ee~~|Bit5<br>~~ee~~|Bit4|Bit3|Bit2|Bit1|Bit0|
|~~—ee~~|||||I2CAddress:0x02h|||
## **YHP_H**
Y-axis high pass filter accelerometer output most significant byte. Data is updated at the ODR frequency determined by OWUF in CNTL3.
|YHPD15<br>~~—~~|YHPD14|YHPD13|YHPD12|YHPD11|YHPD10|YHPD9|YHPD8|
|---|---|---|---|---|---|---|---|
|Bit7<br>~~—~~|Bit6|Bit5|Bit4|Bit3|Bit2|Bit1|Bit0|
|~~—~~|||||I2CAddress:0x03h|||
36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - info@kionix.com
© 2016 Kionix – All Rights Reserved
Page 34 of 81
**PART NUMBER:**
# **± 2g / 4g / 8g Tri-axis Digital Accelerometer Specifications**
**KX124-1051 Rev. 1.0 20-Jan-16**
## **ZHP_L**
Z-axis high pass filter accelerometer output least significant byte. Data is updated at the ODR frequency determined by OWUF in CNTL3
R R R R R R R R ZHPD7 ZHPD6 ZHPD5 ZHPD4 ZHPD3 ZHPD2 ZHPD1 ZHPD0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 ~~a~~ I[2] C Address: 0x04h
## **ZHP_H**
Z-axis high pass filter accelerometer output most significant byte. Data is updated at the ODR frequency determined by OWUF in CNTL3.
|R<br>R<br>R<br>R|R<br>R|R|R||
|---|---|---|---|---|
|ZHPD15<br>ZHPD14<br>ZHPD13<br>ZHPD12<br>ZHPD11<br>ZHPD10<br>ZHPD9<br>ZHPD8<br>Bit7<br>Bit6<br>Bit5<br>Bit4<br>Bit3<br>Bit2<br>Bit1<br>Bit0<br>I2CAddress:0x05h<br>~~——ee~~<br>~~oe~~|||||
|**XOUT_L**|||||
|X-axis accelerometer output least significant byte. Data is updated at the ODR frequency determined||X-axis accelerometer output least significant byte. Data is updated at the ODR frequency determined|||
|by OSA in ODCNTL.|||||
|R<br>R<br>R<br>R|R|R<br>R<br>R||
|---|---|---|---|
|XOUTD7 XOUTD6XOUTD5XOUTD4 XOUTD3XOUTD2 XOUTD1 XOUTD0<br>Bit7<br>Bit6<br>Bit5<br>Bit4<br>Bit3<br>Bit2<br>Bit1<br>Bit0<br>I2CAddress:0x06h<br>~~ee~~||||
|**XOUT_H**||||
|X-axis accelerometer output most significant byte. Data is updated at the ODR frequency determined||X-axis accelerometer output most significant byte. Data is updated at the ODR frequency determined||
|by OSA in ODCNTL.||||
|R<br>~~—~~|R|R|R|R|R|R|R|
|---|---|---|---|---|---|---|---|
|XOUTD15X<br>~~—~~|XOUTD14 X|TD14 XOUTD13X|XOUTD12 X|TD12 XOUTD11 X|TD11 XOUTD10X|XOUTD9X|XOUTD8|
|Bit7<br>~~—~~|Bit6|Bit5|Bit4|Bit3|Bit2|Bit1|Bit0|
||||||I2CAddress:0x07h|||
36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - info@kionix.com
© 2016 Kionix – All Rights Reserved
Page 35 of 81
**PART NUMBER:**
# **± 2g / 4g / 8g Tri-axis Digital Accelerometer Specifications**
**KX124-1051 Rev. 1.0 20-Jan-16**
## **YOUT_L**
Y-axis accelerometer output least significant byte. Data is updated at the ODR frequency determined by OSA in ODCNTL.
R R R R R R R R YOUTD7 YOUTD6 YOUTD5 YOUTD4 YOUTD3 YOUTD2 YOUTD1 YOUTD0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 ~~a~~ I[2] C Address: 0x08h
## **YOUT_H**
Y-axis accelerometer output most significant byte. Data is updated at the ODR frequency determined by OSA in ODCNTL.
**==> picture [530 x 103] intentionally omitted <==**
|ZOUTD7<br>~~—~~|ZOUTD6<br>~~ee~~|ZOUTD5<br>~~ee~~|ZOUTD4|ZOUTD3|ZOUTD2|ZOUTD1|ZOUTD0|
|---|---|---|---|---|---|---|---|
|Bit7<br>~~—~~|Bit6<br>~~ee~~|Bit5<br>~~ee~~|Bit4|Bit3|Bit2|Bit1|Bit0|
|~~—ee~~|||||I2CAddress:0x0Ah|||
## **ZOUT_H**
Z-axis accelerometer output most significant byte. Data is updated at the ODR frequency determined by OSA in ODCNTL.
|YOUTD15Y<br>~~—~~|YOUTD14 Y|TD14 YOUTD13Y|YOUTD12 Y|TD12 YOUTD11 Y|TD11 YOUTD10Y|YOUTD9Y|YOUTD8|
|---|---|---|---|---|---|---|---|
|Bit7<br>~~—~~|Bit6|Bit5|Bit4|Bit3|Bit2|Bit1|Bit0|
|~~—~~|||||I2CAddress:0x0Bh|||
36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - info@kionix.com
© 2016 Kionix – All Rights Reserved
Page 36 of 81
**PART NUMBER: ± 2g / 4g / 8g Tri-axis Digital KX124-1051 Accelerometer Specifications Rev. 1.0 20-Jan-16**
## **COTR**
This register can be used to verify proper integrated circuit functionality. It always has a byte value of 0x55h unless the COTC bit in CNTL2 is set. At that point this value is set to 0xAAh. The byte value is returned to 0x55h after reading this register and the COTC bit in CNTL2 is cleared.
|DCSTR7<br>~~ee~~|DCSTR6<br>~~ee~~|DCSTR5D|DCSTR4 D|TR4 DCSTR3|DCSTR2|DCSTR1|DCSTR0|ResetValue|
|---|---|---|---|---|---|---|---|---|
|Bit7<br>~~ee~~|Bit6<br>~~ee~~|Bit5|Bit4|Bit3|Bit2|Bit1|Bit0|01010101|
|~~ee~~|||||I2CAddress:0x0Ch||||
## **WHO_AM_I**
|**WHO_AM_I**|**WHO_AM_I**|**WHO_AM_I**|**WHO_AM_I**|**WHO_AM_I**|**WHO_AM_I**|**WHO_AM_I**|**WHO_AM_I**|**WHO_AM_I**|**WHO_AM_I**|
|---|---|---|---|---|---|---|---|---|---|
|This register can be used for supplier recognition, as it can be factory written to a known byte value.||||||||||
|The default value is 0x28h.||||||||||
|R<br>WIA7<br>Bit7<br>~~So~~|R<br>WIA6<br>Bit6|R<br>WIA5<br>Bit5|R<br>WIA4<br>Bit4|R<br>WIA3<br>Bit3|R<br>R<br>WIA2<br>WIA1<br>Bit2<br>Bit1<br>I2CAddress:||R<br>WIA0<br>Bit0<br>:0x0Fh|ResetValue<br>00101000||
## **Tilt Position Registers**
These two registers report previous and current position data that is updated at the user-defined ODR frequency and is protected during register read. Table 14 describes the reported position for each bit value.
## **TSCP**
Current Tilt Position Register.
**==> picture [500 x 98] intentionally omitted <==**
© 2016 Kionix – All Rights Reserved
Page 37 of 81
**± 2g / 4g / 8g Tri-axis Digital Accelerometer Specifications**
**PART NUMBER: KX124-1051 Rev. 1.0 20-Jan-16**
## **TSPP**
Previous Tilt Positon Register.
R R R R R R R R 0 0 LE RI DO UP FD FU Reset Value Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 00100000 ~~a~~ I[2] C Address: 0x11h
**==> picture [187 x 96] intentionally omitted <==**
**----- Start of picture text -----**<br>
Bit Description<br>LE Left State (X-)<br>RI Right State (X+)<br>DO Down State (Y-)<br>UP Up State (Y+)<br>FD Face-Down State (Z-)<br>=— FU Face-Up State (Z+)<br>**----- End of picture text -----**<br>
**Table 14:** Tilt Position
## **Interrupt Source Registers**
These three registers report interrupt state changes. This data is updated when a new interrupt event occurs and each application’s result is latched until the interrupt release register is read.
## **INS1**
This register indicates the triggering axis when a tap/double tap interrupt occurs. Data is updated at the ODR settings determined by OTDT<2:0> in CNTL3.
R R R R R R R R 0 0 TLE TRI TDO TUP TFD TFU Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 ~~re~~ I[2] C Address: 0x12h
36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - info@kionix.com
© 2016 Kionix – All Rights Reserved
Page 38 of 81
## **± 2g / 4g / 8g Tri-axis Digital Accelerometer Specifications**
**PART NUMBER: KX124-1051**
**Rev. 1.0**
**20-Jan-16**
**Bit Description** TLE X Negative (X-) Reported TRI X Positive (X+) Reported TDO Y Negative (Y-) Reported TUP Y Positive (Y+) Reported TFD Z Negative (Z-) Reported ~~=—~~ TFU Z Positive (Z+) Reported
**Table 15:** Directional Tap[TM] Reporting
## **INS2**
This Register tells witch function caused an interrupt.
R R R R R R R R FFS BFI WMI DRDY TDTS1 TDTS0 WUFS TPS Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 ~~a~~ I[2] C Address: 0x13h
_**FFS** – Free fall. This bit is cleared when the interrupt latch release register (INL) is read. FFS = 0 – No Free fall_
_FFS = 1 – Free fall has activated the interrupt_
- _**BFI** – indicates buffer full interrupt. Automatically cleared when buffer is read. BFI = 0 – Buffer is not full_
_BFI = 1 – Buffer is full_
- _**WMI** – Watermark interrupt, bit is set to one when FIFO has filled up to the value stored in the sample bits. This bit is automatically cleared when FIFO/FILO is read and the content returns to a value below the value stored in the sample bits._
- _WMI = 0 – Buffer watermark has not been exceeded WMI = 1 – Buffer watermark has been exceeded_
- _**DRDY** – indicates that new acceleration data (0x06h to 0x0Bh) is available. This bit is cleared when acceleration data is read or the interrupt release register INT_REL is read._
- _DRDY = 0 – new acceleration data not available DRDY = 1 - new acceleration data available_
36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - info@kionix.com
© 2016 Kionix – All Rights Reserved
Page 39 of 81
**± 2g / 4g / 8g Tri-axis Digital Accelerometer Specifications**
**PART NUMBER: KX124-1051 Rev. 1.0 20-Jan-16**
_**TDTS(1,0)** – status of tap/double tap, bit is released when interrupt release register INT_REL is read._
**TDTS1 TDTS0 Event** 0 0 No Tap 0 1 Single Tap 1 0 Double Tap 1 1 Do not exist ~~===~~ _**WUFS** – Status of Wake up. This bit is cleared when the interrupt release register INT_REL is read._
_WUFS = 1 – Motion has activated the interrupt_
_WUFS = 0 – No motion_
- _**TPS** – Tilt Position status. This bit is cleared when the interrupt release register INT_REL is read._
_TPS = 0 – Position not changed_
_TPS = 1 – Position changed_
## **INS3**
This register reports the axis and direction of detected motion.
|R<br>~~—~~|R|R|R|R|R|R|R|
|---|---|---|---|---|---|---|---|
|0<br>~~—~~|0|XNWU|XPWU|YNWU|YPWU|ZNWU|ZPWU|
|Bit7<br>~~—~~|Bit6|Bit5|Bit4|Bit3|Bit2|Bit1|Bit0|
|~~—~~|||||I2CAddress:0x14h|||
**Bit Description** XNWU X Negative (X-) Reported XPWU X Positive (X+) Reported YNWU Y Negative (Y-) Reported YPWU Y Positive (Y+) Reported ZNWU Z Negative (Z-) Reported ~~=—~~ ZPWU Z Positive (Z+) Reported **Table 16:** Motion Detection[TM] Reporting
36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - info@kionix.com
© 2016 Kionix – All Rights Reserved
Page 40 of 81
## **± 2g / 4g / 8g Tri-axis Digital Accelerometer Specifications**
**PART NUMBER: KX124-1051**
**Rev. 1.0 20-Jan-16**
## **STATUS_REG**
This register reports the status of the interrupt.
R R R R R R R R 0 0 0 INT 0 0 0 0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 ~~re~~ I[2] C Address: 0x15h _**INT** reports the combined (OR) interrupt information of all features. When BFI and WMI in INS2 are 0, the INT bit is released to 0 when INT_REL is read. If WMI or BFI is 1, INT bit remains at 1 until they are cleared by FIFO/FILO buffer read._
_0 = no interrupt event_
_1 = interrupt event has occurred_
## **INT_REL**
Latched interrupt source information (INS1, INS2, INS3 except WMI/BFI and INT when WMI/BFI is zero) is cleared and physical interrupt latched pin is changed to its inactive state when this register is read. Read value is dummy.
R R R R R R R R X X X X X X X X Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 ~~re~~ I[2] C Address: 0x17h **CNTL1** Read/write control register that controls the main feature set.
|R/W<br>PC1<br>Bit7<br>~~So~~|R/W<br>PC1<br>Bit7<br>~~So~~|R/W<br>RES<br>Bit6||R/W<br>DRDYE<br>Bit5|R/W<br>GSEL1<br>Bit4|R/W<br>R/W<br>R/W<br>GSEL0<br>TDTE<br>WUFE<br>Bit3<br>Bit2<br>Bit1<br>I2CAddress:|R/W<br>TPE<br>Bit0<br>:0x18h|ResetValue<br>00000000|
|---|---|---|---|---|---|---|---|---|
|||**_PC1_**_controls the operating mode of the KX124._||_controls the operating mode of the KX124._|||||
_0 = stand-by mode 1 = operating mode_
_**RES** determines the performance mode of the KX124. The noise varies with ODR, RES and different LP_CNTL settings possibly reducing the effective resolution. Note that to change the value of this bit, the PC1 bit must first be set to “0”. 0 = low current._
_1 = high resolution._
36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - info@kionix.com
© 2016 Kionix – All Rights Reserved
Page 41 of 81
**± 2g / 4g / 8g Tri-axis Digital Accelerometer Specifications**
**PART NUMBER: KX124-1051 Rev. 1.0 20-Jan-16**
_**DRDYE** enables the reporting of the availability of new acceleration data as an interrupt. Note that to change the value of this bit, the PC1 bit must first be set to “0”._
_0 = availability of new acceleration data is not reflected as an interrupt_
_1 = availability of new acceleration data is reflected as an interrupt_
_**GSEL1, GSEL0** selects the acceleration range of the accelerometer outputs per Table 17. Note that to change the value of this bit, the PC1 bit must first be set to “0”._
|**GSEL1**<br>~~===~~|**GSEL0**<br>~~===~~|**Range**<br>~~===~~|
|---|---|---|
|0<br>~~===~~|0<br>~~===~~|±2g<br>~~===~~|
|0<br>~~===~~|1<br>~~===~~|±4g<br>~~===~~|
|1<br>~~===~~|0<br>~~===~~|±8g<br>~~===~~|
**Table 17:** Selected Acceleration Range
_**TDTE** enables the Directional Tap[TM] function that will detect single and double tap events. Note that to change the value of this bit, the PC1 bit must first be set to “0”. TDTE = 0 – disable TDTE = 1 – enable_
_**WUFE** enables the Wake Up (motion detect) function. 0= disabled, 1= enabled. Note that to change the value of this bit, the PC1 bit must first be set to “0”._
_0 = Wake Up function disabled_
_1 = Wake Up function enabled_
_**TPE** enables the Tilt Position function that will detect changes in device orientation. Note that to change the value of this bit, the PC1 bit must first be set to “0”._
_TPE = 0 – disable TPE = 1 – enable_
## **CNTL2**
Read/write control register that provides more feature set control. Note that to properly change the value of this register, the PC1 bit in CNTL1 must first be set to “0”.
R/W R/W R/W R/W R/W R/W R/W R/W SRST COTC LEM RIM DOM UPM FDM FUM Reset Value Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 00111111 ~~a~~ I[2] C Address: 0x19h
36 Thornwood Dr. – Ithaca, NY 14850 © 2016 Kionix – All Rights Reserved tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - info@kionix.com Page 42 of 81
Page 42 of 81
**PART NUMBER: ± 2g / 4g / 8g Tri-axis Digital KX124-1051 Accelerometer Specifications Rev. 1.0 20-Jan-16**
_**SRST** initiates software reset, which performs the RAM reboot routine. This bit will remain 1 until the RAM reboot routine is finished._
_SRST = 0 – no action_
_SRST = 1 – start RAM reboot routine_
_**COTC** Command test control._
- _COTC = 0 – no action_
- _COTC = 1 – sets COTR register to 0xAAh and when COTR is read, sets this bit to 0 and sets COTR to 0x55h_
- _**LEM, RIM, DOM, UPM, FDM, FUM** these bits control the tilt axis mask._ Per Table 18, if a direction’s bit is set to one (1), tilt in that direction will generate an interrupt. If it is set to zero (0), tilt in that direction will not generate an interrupt. Note that to properly change the value of this register, the PC1 bit in CNTL1 must first be set to “0”.
|**Bit**<br>~~=—~~|**Description**<br>~~=—~~|
|---|---|
|LEM<br>~~=—~~|X Negative(X-)<br>~~=—~~|
|RIM<br>~~=—~~|X Positive(X+)<br>~~=—~~|
|DOM<br>~~=—~~|Y Negative(Y-)<br>~~=—~~|
|UPM<br>~~=—~~|Y Positive(Y+)<br>~~=—~~|
|FDM<br>~~=—~~|Z Negative(Z-)<br>~~=—~~|
|FUM<br>~~=—~~|Z Positive(Z+)<br>~~=—~~|
## **Table 18:** Tilt Direction[TM] Axis Mask
## **CNTL3**
Read/write control register that provides more feature set control. Note that to properly change the value of this register, the PC1 bit in CNTL1 must first be set to “0”.
R/W R/W R/W R/W R/W R/W R/W R/W OTP1 OTP0 OTDT2 OTDT1 OTDT0 OWUF2 OWUF1 OWUF0 Reset Value Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 10011000 ~~re~~ I[2] C Address: 0x1Ah _**OTP1, OTP0** sets the output data rate for the Tilt Position function per_ Table 19 _. The default Tilt Position ODR is 12.5Hz._ **OTP1 OTP0 Output Data Rate** 0 0 1.563Hz 0 1 6.25Hz 1 0 12.5Hz 1 1 50Hz ~~=~~ **Table 19:** Tilt Position Function Output Data Rate
36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - info@kionix.com
© 2016 Kionix – All Rights Reserved
Page 43 of 81
**PART NUMBER: ± 2g / 4g / 8g Tri-axis Digital KX124-1051 Accelerometer Specifications Rev. 1.0 20-Jan-16**
_**OTDT2, OTDT1, OTDT0** sets the output data rate for the Directional Tap[TM] function per Table 20. The default Directional Tap[TM] ODR is 400Hz._
|**OTDT2**|**OTDT1**|**OTDT0 **|**Output Data Rate**|
|---|---|---|---|
|0|0|0|50Hz|
|0|0|1|100Hz|
|0|1|0|200Hz|
|0|1|1|400Hz|
|1|0|0|12.5Hz|
|1|0|1|25Hz|
|1|1|0|800Hz|
|1|1|1|1600Hz|
**Table 20:** Directional Tap[TM] Function Output Data Rate
_**OWUF2, OWUF1, OWUF0** sets the output data rate for the general motion detection function and the high-pass filtered outputs per Table 21. The default Motion Wake Up ODR is 0.781Hz._
|**OWUF2**|**OWUF1**|**OWUF0 **|**Output Data Rate**|
|---|---|---|---|
|0|0|0|0.781Hz|
|0|0|1|1.563Hz|
|0|1|0|3.125Hz|
|0|1|1|6.250Hz|
|1|0|0|12.5Hz|
|1|0|1|25Hz|
|1|1|0|50Hz|
|1|1|1|100Hz|
**Table 21:** Motion Wake Up Function Output Data Rate
36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - info@kionix.com
© 2016 Kionix – All Rights Reserved
Page 44 of 81
## **± 2g / 4g / 8g Tri-axis Digital Accelerometer Specifications**
**PART NUMBER: KX124-1051 Rev. 1.0 20-Jan-16**
## **ODCNTL**
This register is responsible for configuring ODR (output data rate) and filter settings. Note that to properly change the value of this register, the PC1 bit in CNTL1 must first be set to “0”.
|R/W<br>~~Ce~~|R/W<br>~~Ce~~|R/W|R/W|R/W|R/W|R/W|R/W||
|---|---|---|---|---|---|---|---|---|
|IIR_BYPASS<br>~~Ce~~|LPRO<br>~~Ce~~|RESERVED RE|ERVED RESERVED|ERVED<br>OSA3|OSA2|OSA1|OSA0|ResetValue|
|Bit7<br>~~Ce~~|Bit6<br>~~Ce~~|Bit5|Bit4|Bit3|Bit2|Bit1|Bit0|00000010|
|~~Ce~~|||||I2CAddress:0x1Bh||||
## _**IIR_BYPASS** filter bypass mode_
_IIR_BYPASS = 0 – filtering applied IIR_BYPASS = 1 – filter bypassed_
## _**LPRO** low-pass filter roll off control_
_LPRO = 0 – filter corner frequency set to ODR/9 LPRO = 1 – filter corner frequency set to ODR/2_
## _**OSA3, OSA2, OSA1, OSA0** acceleration output data rate. The default ODR is 50Hz._
|**OSA3 OSA2**|**OSA3 OSA2**|**OSA1**|**OSA0**|**Output Data Rate**|
|---|---|---|---|---|
|0|0|0|0|12.5Hz*|
|0|0|0|1|25Hz*|
|0|0|1|0|50Hz*|
|0|0|1|1|100Hz*|
|0|1|0|0|200Hz*|
|0|1|0|1|400Hz***|
|0|1|1|0|800Hz|
|0|1|1|1|1600Hz|
|1|0|0|0|0.781Hz*|
|1|0|0|1|1.563Hz*|
|1|0|1|0|3.125Hz*|
|1|0|1|1|6.25Hz*|
|1|1|0|0|3200Hz**|
|1|1|0|1|6400Hz**|
|1|1|1|0|12800Hz**|
|1|1|1|1|25600Hz**|
**Table 22:** Accelerometer Output Data Rates (ODR)
- Low power mode available, all other data rates will default to high resolution mode
- ** If the interrupt pin is enabled and set to pulse mode, the pulse width is about 10us over 1600Hz ODR. And when ODR is up to 1600Hz, the pulse width is about 50us.
*** 400Hz high resolution mode only (will not output in low power mode)
36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - info@kionix.com
© 2016 Kionix – All Rights Reserved
Page 45 of 81
**± 2g / 4g / 8g Tri-axis Digital Accelerometer Specifications**
**PART NUMBER: KX124-1051 Rev. 1.0 20-Jan-16**
## **INC1**
This register controls the settings for the physical interrupt pin INT1. Note that to properly change the value of this register, the PC1 bit in CNTL1 must first be set to “0”.
R/W R/W R/W R/W R/W R/W R/W R/W PWSEL11 PWSEL10 IEN1 IEA1 IEL1 Reserved STPOL SPI3E Reset Value Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 00010000 ~~re~~ I[2] C Address: 0x1Ch _**PWSEL1<1:0>** – Pulse interrupt 1 width configuration 00 = 50us (10us if OSA > 1600Hz)_
- _01 = 1 * OSA period_
- _10 = 2 * OSA periods_
- _11 = 4 * OSA periods_
_When PWSEL1 > 0, Interrupt source auto-clearing (ACLR1=1) should be set to keep consistency between the internal status and the physical interrupt._
- _**IEN1** enables/disables the physical interrupt pin IEN = 0 – physical interrupt pin is disabled_
- _IEN = 1 – physical interrupt pin is enabled_
- _**IEA1** sets the polarity of the physical interrupt pin_
- _IEA = 0 – polarity of the physical interrupt pin is active low_
- _IEA = 1 – polarity of the physical interrupt pin is active high_
- _**IEL1** sets the response of the physical interrupt pin_
- _IEL = 0 – the physical interrupt pin latches until it is cleared by reading INT_REL_
- _IEL = 1 – the physical interrupt pin will transmit one pulse configurable by PWSEL1_
- _**STPOL** sets the polarity of Self Test_
- _STPOL = 0 – Negative_
- _STPOL = 1 – Positive_
_**SPI3E** sets the 3-wire SPI interface_
_SPI3E = 0 – disabled_
_SPI3E = 1 – enabled_
36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - info@kionix.com
© 2016 Kionix – All Rights Reserved
Page 46 of 81
**± 2g / 4g / 8g Tri-axis Digital Accelerometer Specifications**
**PART NUMBER: KX124-1051**
**Rev. 1.0 20-Jan-16**
## **INC2**
This register controls which axis and direction of detected motion can cause an interrupt. Note that to properly change the value of this register, the PC1 bit in CNTL1 must first be set to “0”.
R/W R/W R/W R/W R/W R/W R/W R/W 0 AOI XNWUE XPWUE YNWUE YPWUE ZNWUE ZPWUE Reset Value Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 00111111 ~~re~~ I[2] C Address: 0x1Dh _**AOI** – AND-OR configuration on motion detection 0 – OR combination between selected directions_
_1 – AND combination between selected axes Ex. If all directions are enabled, Active state in OR configuration = (XN || XP || YN || TP || ZN || ZP) Active state in AND configuration = (XN || XP) && (YN || YP) && (ZN || ZP)_
_**XNWU** – x negative (x-): 0 = disabled, 1 = enabled_ _**XPWU** – x positive (x+): 0 = disabled, 1 = enabled_ _**YNWU** – y negative (y-): 0 = disabled, 1 = enabled_ _**YPWU** – y positive (y+): 0 = disabled, 1 = enabled_ _**ZNWU** – z negative (z-): 0 = disabled, 1 = enabled_ _**ZPWU** – z positive (z+): 0 = disabled, 1 = enabled_
## **INC3**
This register controls which axis and direction of tap/double tap can cause an interrupt. Note that to properly change the value of this register, the PC1 bit in CNTL1 must first be set to “0”.
R/W R/W R/W R/W R/W R/W R/W R/W 0 0 TLEM TRIM TDOM TUPM TFDM TFUM Reset Value Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 00111111 ~~re~~ I[2] C Address: 0x1Eh _**TLEM** – x negative (x-): 0 = disabled, 1 = enabled_ _**TRIM** – x positive (x+): 0 = disabled, 1 = enabled_ _**TDOM** – y negative (y-): 0 = disabled, 1 = enabled_ _**TUPM** – y positive (y+): 0 = disabled, 1 = enabled_ _**TFDM** – z negative (z-): 0 = disabled, 1 = enabled_ _**TFUM** – z positive (z+): 0 = disabled, 1 = enabled_
36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - info@kionix.com
© 2016 Kionix – All Rights Reserved
Page 47 of 81
**± 2g / 4g / 8g Tri-axis Digital Accelerometer Specifications**
**PART NUMBER: KX124-1051 Rev. 1.0 20-Jan-16**
## **INC4**
This register controls routing of an interrupt reporting to physical interrupt pin INT1. Note that to properly change the value of this register, the PC1 bit in CNTL1 must first be set to “0”.
R/W R/W R/W R/W R/W R/W R/W R/W FFI1 BFI1 WMI1 DRDYI1 Reserved TDTI1 WUFI1 TPI1 Reset Value Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 00000000 ~~re~~ I[2] C Address: 0x1Fh _**FFI1** – Free fall interrupt reported on physical interrupt INT1_ _**BFI1** – Buffer full interrupt reported on physical interrupt pin INT1_ _**WMI1** – Watermark interrupt reported on physical interrupt pin INT1_ _**DRDYI1** – Data ready interrupt reported on physical interrupt pin INT1_ _**TDTI1** – Tap/Double Tap interrupt reported on physical interrupt pin INT1_ _**WUFI1** – Wake-Up (motion detect) interrupt reported on physical interrupt pin INT1_ _**TPI1** – Tilt position interrupt reported on physical interrupt pin INT1_
## **INC5**
This register controls the settings for the physical interrupt pin INT2. Note that to properly change the value of this register, the PC1 bit in CNTL1 must first be set to “0”.
||R/W|R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W|R/W||
|---|---|---|---|---|
|PWSEL21 PWSEL20<br>IEN2<br>IEA2<br>IEL2<br>Reserved<br>ACLR2<br>ACLR1<br>ResetValue<br>Bit7<br>Bit6<br>Bit5<br>Bit4<br>Bit3<br>Bit2<br>Bit1<br>Bit0<br>00010000<br>I2CAddress:0x20h<br>~~re~~|||||
|||**_PWSEL2<1:0>_**_– Pulse interrupt 2 width configuration_|||
|||_00 = 50us (10us if OSA > 1600Hz)_|||
|||_01 = 1 * OSA period_|||
_10 = 2 * OSA periods 11 = 4 * OSA periods_
_When PWSEL2 > 0, Interrupt source auto-clearing (ACLR2=1) is strongly recommended to keep consistency between the internal status and the physical interrupt._
_**IEN2** enables/disables the physical interrupt pin_
_IEN2 = 0 – physical interrupt pin is disabled_
_IEN2 = 1 – physical interrupt pin is enabled_
36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - info@kionix.com
© 2016 Kionix – All Rights Reserved
Page 48 of 81
**PART NUMBER: ± 2g / 4g / 8g Tri-axis Digital KX124-1051 Accelerometer Specifications Rev. 1.0 20-Jan-16**
_**IEA2** sets the polarity of the physical interrupt pin_
_IEA2 = 0 – polarity of the physical interrupt pin is active low IEA2 = 1 – polarity of the physical interrupt pin is active high_
_**IEL2** sets the response of the physical interrupt pin_
_IEL2 = 0 – the physical interrupt pin latches until it is cleared by reading INT_REL_
_IEL2 = 1 – the physical interrupt pin will transmit one pulse configurable by PWSEL2_
_**ACLR2** – Interrupt source automatic clear at pulse interrupt 2 trailing edge ACLR2 = 0 – disable_
_ACLR2 = 1 – enable_
_**ACLR1** – Interrupt source automatic clear at pulse interrupt 1 trailing edge ACLR1 = 0 – disable_
_ACLR1 = 1 – enable_
## **INC6**
This register controls routing of interrupt reporting to physical interrupt pin INT2. Note that to properly change the value of this register, the PC1 bit in CNTL1 must first be set to “0”.
R/W R/W R/W R/W R/W R/W R/W R/W FFI2 BFI2 WMI2 DRDYI2 Reserved TDTI2 WUFI2 TPI2 Reset Value Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 00000000 ~~re~~ I[2] C Address: 0x21h _**FFI2** – Free fall interrupt reported on physical interrupt INT2_ _**BFI2** – Buffer full interrupt reported on physical interrupt pin INT2_ _**WMI2** – Watermark interrupt reported on physical interrupt pin INT2_ _**DRDYI2** – Data ready interrupt reported on physical interrupt pin INT2_ _**TDTI2** - Tap/Double Tap interrupt reported on physical interrupt pin INT2_ _**WUFI2** – Wake-Up (motion detect) interrupt reported on physical interrupt pin INT2_ _**TPI2** – Tilt position interrupt reported on physical interrupt pin INT2_
36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - info@kionix.com
© 2016 Kionix – All Rights Reserved
Page 49 of 81
**± 2g / 4g / 8g Tri-axis Digital Accelerometer Specifications**
**PART NUMBER: KX124-1051 Rev. 1.0 20-Jan-16**
## **TILT_TIMER**
This register is the initial count register for the tilt position state timer (0 to 255 counts). Every count is calculated as 1/ODR delay period, where the ODR is user-defined per Table 19. A new state must be valid as many measurement periods before the change is accepted. Note that to properly change the value of this register, the PC1 bit in CNTL1 must first be set to “0”.
|TSC7<br>~~a~~|TSC6<br>~~a~~|TSC5<br>~~a~~|TSC4<br>~~a~~|TSC3<br>~~a~~|TSC2<br>~~a~~|TSC1<br>~~a~~|TSC0<br>~~a~~|ResetValue<br>~~a~~|
|---|---|---|---|---|---|---|---|---|
|Bit7<br>~~a~~|Bit6<br>~~a~~|Bit5<br>~~a~~|Bit4<br>~~a~~|Bit3<br>~~a~~|Bit2<br>~~a~~|Bit1<br>~~a~~|Bit0<br>~~a~~|00000000<br>~~a~~|
|~~a~~|||||I2CAddress:0x22h<br>~~a~~|||~~a~~|
## **WUFC**
This register is the initial count register for the motion detection timer (0 to 255 counts). Every count is calculated as 1/ODR delay period, where the ODR is user-defined per Table 21. A new state must be valid as many measurement periods before the change is accepted. Note that to properly change the value of this register, the PC1 bit in CNTL1 must first be set to “0”.
|R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W||
|---|---|
|WUFC7<br>WUFC6<br>WUFC5<br>WUFC4<br>WUFC3<br>WUFC2<br>WUFC1<br>WUFC0<br>Reset Value<br>Bit7<br>Bit6<br>Bit5<br>Bit4<br>Bit3<br>Bit2<br>Bit1<br>Bit0<br>00000000<br>I2CAddress:0x23h<br>~~re~~||
|**TDTRC**||
|This register is responsible for enabling/disabling reporting of Tap/Double Tap. Note that to properly||
|change the value of this register, the PC1 bit in CNTL1 must first be set to “0”.||
R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 DTRE STRE Reset Value Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 00000011 ~~re~~ I[2] C Address: 0x24h _**DTRE** enables/disables the double tap interrupt DTRE = 0 – do not update/trigger interrupts on double tap events DTRE = 1 –update interrupts on double tap events_ _**STRE** enables/disables single tap interrupt_
_STRE = 0 – do not update/trigger interrupts on single tap events STRE = 1 –update interrupts on single tap events_
36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - info@kionix.com
© 2016 Kionix – All Rights Reserved
Page 50 of 81
**PART NUMBER: ± 2g / 4g / 8g Tri-axis Digital KX124-1051 Accelerometer Specifications Rev. 1.0 20-Jan-16**
## **TDTC**
This register contains counter information for the detection of a double tap event. When the Directional TapTM ODR is 400Hz or less, every count is calculated as 1/ODR delay period. When the Directional TapTM ODR is 800Hz, every count is calculated as 2/ODR delay period. When the Directional TapTM ODR is 1600Hz, every count is calculated as 4/ODR delay period. The Directional TapTM ODR is userdefined per Table 20. The TDTC counts starts at the beginning of the first tap and it represents the minimum time separation between the first tap and the second tap in a double tap event. More specifically, the second tap event must end outside of the TDTC. The Kionix recommended default value is 0.3 seconds (0x78h). Note that to properly change the value of this register, the PC1 bit in CNTL1 must first be set to “0”.
R/W R/W R/W R/W R/W R/W R/W R/W TDTC7 TDTC6 TDTC5 TDTC4 TDTC3 TDTC2 TDTC1 TDTC0 Reset Value Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 01111000 ~~re~~ I[2] C Address: 0x25h **TTH** This register represents the 8-bit jerk high threshold to determine if a tap is detected. Though this is an 8-bit register, the register value is internally multiplied by two in order to set the high threshold. This multiplication results in a range of 0d to 510d with a resolution of two counts. The Performance Index (PI) is the jerk signal that is expected to be less than this threshold, but greater than the TTL threshold during single and double tap events. Note that to properly change the value of this register, the PC1 bit in CNTL1 must first be set to “0”. The Kionix recommended default value is 203 (0xCBh) and the Performance Index is calculated as:
**==> picture [150 x 37] intentionally omitted <==**
**==> picture [98 x 11] intentionally omitted <==**
## **Equation 1:** Performance Index
R/W R/W R/W R/W R/W R/W R/W R/W TTH7 TTH6 TTH5 TTH4 TTH3 TTH2 TTH1 TTH0 Reset Value Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 11001011 ~~re~~ I[2] C Address: 0x26h 36 Thornwood Dr. – Ithaca, NY 14850 © 2016 Kionix – All Rights Reserved tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - info@kionix.com
© 2016 Kionix – All Rights Reserved
Page 51 of 81
**PART NUMBER: ± 2g / 4g / 8g Tri-axis Digital KX124-1051 Accelerometer Specifications Rev. 1.0 20-Jan-16**
## **TTL**
This register represents the 8-bit (0d– 255d) jerk low threshold to determine if a tap is detected. The Performance Index (PI) is the jerk signal that is expected to be greater than this threshold and less than the TTH threshold during single and double tap events. The Kionix recommended default value is 26 (0x1Ah). Note that to properly change the value of this register, the PC1 bit in CNTL1 must first be set to “0”.
R/W R/W R/W R/W R/W R/W R/W R/W TTL7 TTL6 TTL5 TTL4 TTL3 TTL2 TTL1 TTL0 Reset Value Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 00011010 ~~re~~ I[2] C Address: 0x27h **FTD** This register contains counter information for the detection of any tap event. When the Directional TapTM ODR is 400Hz or less, every count is calculated as 1/ODR delay period. When the Directional TapTM ODR is 800Hz, every count is calculated as 2/ODR delay period. When the Directional TapTM ODR is 1600Hz, every count is calculated as 4/ODR delay period. The Directional TapTM ODR is user-defined per Table 20. In order to ensure that only tap events are detected, these time limits are used. A tap event must be above the performance index threshold for at least the low limit (FTDL0 – FTDL2) and no more than the high limit (FTDH0 – FTDH4). The Kionix recommended default value for the high limit is 0.05 seconds and for the low limit is 0.005 seconds (0xA2h). Note that to properly change the value of this register, the PC1 bit in CNTL1 must first be set to “0”.
|FTDH4<br>~~a~~|FTDH3<br>~~a~~|FTDH2<br>~~a~~|FTDH1<br>~~a~~|FTDH0<br>~~a~~|FTDL2<br>~~a~~|FTDL1<br>~~a~~|FTDL0<br>~~a~~|ResetValue<br>~~a~~|
|---|---|---|---|---|---|---|---|---|
|Bit7<br>~~a~~|Bit6<br>~~a~~|Bit5<br>~~a~~|Bit4<br>~~a~~|Bit3<br>~~a~~|Bit2<br>~~a~~|Bit1<br>~~a~~|Bit0<br>~~a~~|10100010<br>~~a~~|
|~~a~~|||||I2CAddress:0x28h<br>~~a~~|||~~a~~|
**STD** This register contains counter information for the detection of a double tap event. When the Directional Tap[TM] ODR is 400Hz or less, every count is calculated as 1/ODR delay period. When the Directional Tap[TM] ODR is 800Hz, every count is calculated as 2/ODR delay period. When the Directional Tap[TM] ODR is 1600Hz, every count is calculated as 4/ODR delay period. The Directional Tap[TM] ODR is user-defined per Table 20. In order to ensure that only tap events are detected, this time limit is used. This register sets the total amount of time that the two taps in a double tap event can be above the PI threshold (TTL). The Kionix recommended default value for STD is 0.09 seconds (0x24h). Note that to properly change the value of this register, the PC1 bit in CNTL1 must first be set to “0”.
|R/W<br>R/W<br>R/W|R/W|R/W|R/W|R/W|R/W||
|---|---|---|---|---|---|---|
|STD7<br>STD6<br>STD5<br>STD4<br>STD3<br>STD2<br>STD1<br>STD0<br>ResetValue<br>Bit7<br>Bit6<br>Bit5<br>Bit4<br>Bit3<br>Bit2<br>Bit1<br>Bit0<br>00100100<br>I2CAddress:0x29h<br>~~a~~|||||||
|36 Thornwood Dr. – Ithaca, NY 14850|||||© 2016 Kionix – All Rights Reserved||
|tel: 607-257-1080 – fax:607-257-1146|||||||
|www.kionix.com - info@kionix.com||||||Page 52 of 81|
© 2016 Kionix – All Rights Reserved Page 52 of 81
**PART NUMBER: ± 2g / 4g / 8g Tri-axis Digital KX124-1051 Accelerometer Specifications Rev. 1.0 20-Jan-16**
## **TLT**
This register contains counter information for the detection of a tap event. When the Directional Tap[TM] ODR is 400Hz or less, every count is calculated as 1/ODR delay period. When the Directional Tap[TM] ODR is 800Hz, every count is calculated as 2/ODR delay period. When the Directional Tap[TM] ODR is 1600Hz, every count is calculated as 4/ODR delay period. The Directional Tap[TM] ODR is user-defined per Table 20. In order to ensure that only tap events are detected, this time limit is used. This register sets the total amount of time that the tap algorithm will count samples that are above the PI threshold (TTL) during a potential tap event. It is used during both single and double tap events. However, reporting of single taps on the physical interrupt pin INT1 or INT2 will occur at the end of the TWS. The Kionix recommended default value for TLT is 0.1 seconds (0x28h). Note that to properly change the value of this register, the PC1 bit in CNTL1 must first be set to “0”.
||R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W||
|---|---|---|
|TLT7<br>TLT6<br>TLT5<br>TLT4<br>TLT3<br>TLT2<br>TLT1<br>TLT0<br>ResetValue<br>Bit7<br>Bit6<br>Bit5<br>Bit4<br>Bit3<br>Bit2<br>Bit1<br>Bit0<br>00101000<br>I2CAddress:0x2Ah<br>~~re~~|||
||**TWS**||
||This register contains counter information for the detection of single and double taps. When the||
||Directional TapTMODR is 400Hz or less, every count is calculated as 1/ODR delay period. When the||
||Directional TapTMODR is 800Hz, every count is calculated as 2/ODR delay period. When the Directional||
||TapTMODR is 1600Hz, every count is calculated as 4/ODR delay period. The Directional TapTMODR is||
||user-defined per Table 20. It defines the time window for the entire tap event, single or double, to occur.||
||Reporting of single taps on the physical interrupt pin INT1 or INT2 will occur at the end of this tap window.||
||The Kionix recommended default value for TWS is 0.4 seconds (0xA0h). Note that to properly change|The Kionix recommended default value for TWS is 0.4 seconds (0xA0h). Note that to properly change|
||the value of this register, the PC1 bit in CNTL1 must first be set to “0”.||
|R/W<br>R/W<br>R/W|R/W|R/W|R/W|R/W|R/W||
|---|---|---|---|---|---|---|
|TWS7<br>TWS6<br>TWS5<br>TWS4<br>TWS3<br>TWS2<br>TWS1<br>TWS0<br>Reset Value<br>Bit7<br>Bit6<br>Bit5<br>Bit4<br>Bit3<br>Bit2<br>Bit1<br>Bit0<br>10100000<br>I2CAddress:0x2Bh<br>~~re~~|||||||
|36 Thornwood Dr. – Ithaca, NY 14850|||||© 2016 Kionix – All Rights Reserved||
|tel: 607-257-1080 – fax:607-257-1146|||||||
|www.kionix.com - info@kionix.com||||||Page 53 of 81|
© 2016 Kionix – All Rights Reserved
Page 53 of 81
**± 2g / 4g / 8g Tri-axis Digital Accelerometer Specifications**
**PART NUMBER: KX124-1051 Rev. 1.0 20-Jan-16**
## **FFTH**
Free Fall Threshold: This register contains the threshold of the Free fall detection. This value is compared to the top 8 bits of the accelerometer 8g output. Note that to properly change the value of this register, the PC1 bit in CNTL1 must first be set to “0”.
|R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W|R/W<br>R/W||
|---|---|---|
|FFTH7<br>FFTH6<br>FFTH5<br>FFTH4<br>FFTH3<br>FFTH2<br>FFTH1<br>FFTH0<br>Reset Value<br>Bit7<br>Bit6<br>Bit5<br>Bit4<br>Bit3<br>Bit2<br>Bit1<br>Bit0<br>00000000<br>I2CAddress:0x2Ch<br>~~re~~|||
|**FFC**|||
|Free Fall Counter: This register contains the counter setting of the Free fall detection. Every count is|Free Fall Counter: This register contains the counter setting of the Free fall detection. Every count is||
|calculated as 1/ODR delay period. Note that to properly change the value of this register, the PC1 bit in|||
|CNTL1 must first be set to “0”.|||
|CNTL1 must first be set to “0”.||
|---|---|
|R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W||
|FFC7<br>FFC6<br>FFC5<br>FFC4<br>FFC3<br>FFC2<br>FFC1<br>FFC0<br>ResetValue<br>Bit7<br>Bit6<br>Bit5<br>Bit4<br>Bit3<br>Bit2<br>Bit1<br>Bit0<br>00000000<br>I2CAddress:0x2Dh<br>~~re~~||
|**FFCNTL**||
|Free Fall Control: This register contains the counter setting of the Free fall detection. Every count is||
|calculated as 1/ODR delay period. Note that to properly change the value of this register, the PC1 bit in||
|CNTL1 must first be set to “0”.||
R/W R/W R/W R/W R/W R/W R/W R/W FFIE ULMODE 0 0 DCRM OFFI2 OFFI1 OFFI0 Reset Value Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 00000000 ~~re~~ I[2] C Address: 0x2Eh _**FFIE –** Free fall engine enable FFIE = 0 – disable FFIE = 1 – enable_ _**ULMODE** – Free fall interrupt latch/un-latch control ULMODE = 0 – latched ULMODE = 1 – unlatched_ _**DCRM** – Debounce methodology control DCRM = 0 – count up/down DCRM = 1 – count up/reset_
36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - info@kionix.com
© 2016 Kionix – All Rights Reserved
Page 54 of 81
## **± 2g / 4g / 8g Tri-axis Digital Accelerometer Specifications**
**PART NUMBER: KX124-1051 Rev. 1.0 20-Jan-16**
**OFFI<2:0>:** _–_ Output Data Rate at which the Free fall engine performs its function. The default Free fall ODR is 12.5Hz.
|**OFFI**|**Output Data Rate (Hz)**|
|---|---|
|000|12.5|
|001|25|
|010|50|
|011|100|
|100|200|
|101|400|
|110|800|
|111|1600|
## **ATH**
This register sets the threshold for wake-up (motion detect) interrupt is set. The KX124 will ship from the factory with this value set to correspond to a change in acceleration of 0.5g. Note that to properly change the value of this register, the PC1 bit in CNTL1 must first be set to “0”.
R/W R/W R/W R/W R/W R/W R/W R/W ATH7 ATH6 ATH5 ATH4 ATH3 ATH2 ATH1 ATH0 Reset Value Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 00001000 ~~re~~ I[2] C Address: 0x30h **TILT_ANGLE_LL** This register sets the low level threshold for tilt angle detection. The KX124 ships from the factory with tilt angle set to a low threshold of 22° from horizontal. A different default tilt angle can be requested from the factory. Note that the minimum suggested tilt angle is 10°. Note that to properly change the value of this register, the PC1 bit in CNTL1 must first be set to “0”.
|TA7|TA6|TA5|TA4|TA3|TA2|TA1|TA0|Reset Value|
|---|---|---|---|---|---|---|---|---|
|Bit7|Bit6|Bit5|Bit4|Bit3|Bit2|Bit1|Bit0|00001100|
||||||I2CAddress:0x32h||||
36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - info@kionix.com
© 2016 Kionix – All Rights Reserved
Page 55 of 81
**± 2g / 4g / 8g Tri-axis Digital Accelerometer Specifications**
**PART NUMBER: KX124-1051 Rev. 1.0 20-Jan-16**
## **TILT_ANGLE_HL**
This register sets the high level threshold for tilt angle detection. Note that to properly change the value of this register, the PC1 bit in CNTL1 must first be set to “0”.
||R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W||
|---|---|---|
|HL7<br>HL6<br>HL5<br>HL4<br>HL3<br>HL2<br>HL1<br>HL0<br>Reset Value<br>Bit7<br>Bit6<br>Bit5<br>Bit4<br>Bit3<br>Bit2<br>Bit1<br>Bit0<br>00101010<br>I2CAddress:0x33h<br>~~a~~|||
||**HYST_SET**||
||This register sets the Hysteresis that is placed in between the Screen Rotation states. The KX124 ships||
||from the factory with HYST_SET set to ±15° of hysteresis. A different default hysteresis can be requested||
||from the factory. Note that when writing a new value to this register the current values of RES0 and RES1||
||must be preserved. These values are set at the factory and must not change. Note that to properly||
||change the value of this register, the PC1 bit in CNTL1 must first be set to “0”.||
|RES1<br>~~i~~|RES0<br>~~i~~|HYST5<br>~~i~~|HYST4<br>~~i~~|HYST3<br>~~i~~|HYST2<br>~~i~~|HYST1<br>~~i~~|HYST0<br>~~i~~|ResetValue<br>~~i~~|
|---|---|---|---|---|---|---|---|---|
|Bit7<br>~~i~~|Bit6<br>~~i~~|Bit5<br>~~i~~|Bit4<br>~~i~~|Bit3<br>~~i~~|Bit2<br>~~i~~|Bit1<br>~~i~~|Bit0<br>~~i~~|00010100<br>~~i~~|
|~~i~~|||||I2CAddress:0x34h<br>~~i~~|||~~i~~|
## **LP_CNTL**
Low Power Control sets the number of samples of accelerometer output to be averaged. Note that to properly change the value of this register, the PC1 bit in CNTL1 must first be set to “0”.
||R/W|R/W<br>R/W|R/W|R/W<br>R/W<br>R/W<br>R/W|
|---|---|---|---|---|
|Reserved<br>AVC2<br>AVC1<br>AVC0<br>Reserved Reserved Reserved<br>Reserved<br>Reset Value<br>Bit7<br>Bit6<br>Bit5<br>Bit4<br>Bit3<br>Bit2<br>Bit1<br>Bit0<br>01001011<br>I2CAddress:0x35h<br>~~ee~~|||||
|||**_AVC<2:0>_**_– Averaging Filter Control, the default setting is 16 samples averaged_|_– Averaging Filter Control, the default setting is 16 samples averaged_||
|||_000 = No Averaging_|||
_001 = 2 Samples Averaged 010 = 4 Samples Averaged 011 = 8 Samples Averaged 100 = 16 Samples Averaged (default) 101 = 32 Samples Averaged 110 = 64 Samples Averaged 111 = 128 Samples Averaged_
36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - info@kionix.com
© 2016 Kionix – All Rights Reserved
Page 56 of 81
**PART NUMBER: ± 2g / 4g / 8g Tri-axis Digital KX124-1051 Accelerometer Specifications Rev. 1.0 20-Jan-16**
## **BUF_CNTL1**
Read/write control register that controls the buffer sample threshold. Note that to properly change the value of this register, the PC1 bit in CNTL1 must first be set to “0”.
R/W R/W R/W R/W R/W R/W R/W R/W SMP_TH7 SMP_TH6 SMP_TH5 SMP_TH4 SMP_TH3 SMP_TH2 SMP_TH1 SMP_TH0 Reset Value Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 00000000 ~~a~~ I[2] C Address: 0x3Ah _**SMP_TH[9:0] Sample Threshold** ; determines the number of samples that will trigger a watermark interrupt or will be saved prior to a trigger event. When BUF_RES=1, the maximum number of samples is 339; when BUF_RES=0, the maximum number of samples is 681._
|_samples is 681._|_samples is 681._|
|---|---|
|**Buffer Model**|**Sample Function**|
|Bypass|None|
|FIFO|Specifies how many buffer samples are needed<br>to trigger a watermark interrupt.|
|Stream|Specifies how many buffer samples are needed<br>to trigger a watermark interrupt.|
|Trigger|Specifies how many buffer samples before the<br>triggerevent areretainedinthe buffer.|
|FILO|Specifies how many buffer samples are needed<br>to triggerawatermark interrupt.|
**Table 23:** Sample Threshold Operation by Buffer Mode
36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - info@kionix.com
© 2016 Kionix – All Rights Reserved
Page 57 of 81
**± 2g / 4g / 8g Tri-axis Digital Accelerometer Specifications**
**PART NUMBER: KX124-1051**
**Rev. 1.0 20-Jan-16**
## **BUF_CNTL2**
Read/write control register that controls sample buffer operation. Note that to properly change the value of this register, the PC1 bit in CNTL1 must first be set to “0”.
R/W R/W R/W R/W R/W R/W R/W R/W BUFE BRES BFIE 0 SMP_TH9 SMP_TH8 BUF_M1 BUF_M0 Reset Value Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 00000000 ~~a~~ I[2] C Address: 0x3Bh _**BUFE** controls activation of the sample buffer. BUFE = 0 – sample buffer inactive BUFE = 1 – sample buffer active_ _**BRES** determines the resolution of the acceleration data samples collected by the sample buffer._
_BUF_RES = 0 – 8-bit samples are accumulated in the buffer BUF_RES = 1 – 16-bit samples are accumulated in the buffer_
_**BFIE** buffer full interrupt enable bit BFIE = 0 – buffer full interrupt disabled BFIE = 1 – buffer full interrupt updated in INS2_
_**BUF_M1, BUF_M0** selects the operating mode of the sample buffer per_ Table 24 _._
|**BUF_M1**|**BUF_M0**|**Mode**|**Description**|
|---|---|---|---|
|0|0|FIFO|The buffer collects 681 sets of 8-bit low resolution values or 339<br>sets of 16-bit high resolution values and then stops collecting<br>data, collecting new data only when the buffer is not full.|
|0|1|Stream|The buffer holds the last 681 sets of 8-bit low resolution values<br>or 339 sets of 16-bit high resolution values. Once the buffer is full,<br>the oldest datais discarded tomakeroom for newerdata.|
|1|0|Trigger|When a trigger event occurs, the buffer holds the last data set of<br>SMP_TH[9:0] samples before the trigger event and then<br>continues to collect data until full. New data is collected only when<br>the buffer is not full.|
|1|1|FILO|The buffer holds the last 681 sets of 8-bit low resolution values<br>or 339 sets of 16-bit high resolution values. Once the buffer is full,<br>the oldest data is discarded to make room for newer data.<br>Reading from the buffer in this mode will return the most recent<br>datafirst.|
**Table 24:** Selected Buffer Mode
36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - info@kionix.com
© 2016 Kionix – All Rights Reserved
Page 58 of 81
**PART NUMBER:**
**± 2g / 4g / 8g Tri-axis Digital Accelerometer Specifications**
**KX124-1051**
**Rev. 1.0**
**20-Jan-16**
## **BUF_STATUS_1**
This register reports the status of the sample buffer.
R/W R/W R/W R/W R/W R/W R/W R/W SMP_LEV7 SMP_LEV6 SMP_LEV5 SMP_LEV4 SMP_LEV3 SMP_LEV2 SMP_LEV1 SMP_LEV0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 I[2] C Address: 0x3Ch ~~SSS~~ _**SMP_LEV[10:0] Sample Level** ; reports the number of_ ~~SS~~ _data bytes that have been stored in the sample buffer. When BUF_RES=1, this count will increase by 6 for each 3-axis sample in the buffer; when BUF_RES=0, the count will increase by 3 for each 3-axis sample. If this register reads 0, no data has been stored in the buffer._
## **BUF_STATUS_2**
This register reports the status of the sample buffer trigger function.
|R/W<br>~~—~~|R/W|R/W|R/W|R/W|R/W|R/W|R/W|
|---|---|---|---|---|---|---|---|
|BUF_TRIG<br>~~—~~|0|0|0|0|SMP_LEV10|SMP_LEV9|SMP_LEV8|
|Bit7<br>~~—~~|Bit6|Bit5|Bit4|Bit3|Bit2|Bit1|Bit0|
|~~—~~|||||I2CAddress:0x3Dh|||
_**BUF_TRIG** reports the status of the buffer’s trigger function if this mode has been selected. When using trigger mode, a buffer read should only be performed after a trigger event._
## **BUF_CLEAR**
Latched buffer status information and the entire sample buffer are cleared when any data is written to this register.
|X<br>~~——~~|X<br>~~——~~|X|X|X|X|X|X|
|---|---|---|---|---|---|---|---|
|Bit7<br>~~——~~|Bit6<br>~~——~~|Bit5|Bit4|Bit3|Bit2|Bit1|Bit0|
|~~——~~|||||I2CAddress:0x3Eh|||
## **BUF_READ**
Buffer output register
|R/W<br>R/W|R/W|R/W|R/W|R/W||R/W|R/W|
|---|---|---|---|---|---|---|---|
|X<br>X<br>Bit7<br>Bit6<br>~~—~~|X<br>Bit5|X<br>Bit4|X<br>Bit3|X<br>Bit2|X<br>Bit1<br>I2CAddress:||X<br>Bit0<br>:0x3Fh|
|36 Thornwood Dr. – Ithaca, NY 14850||||||||
|tel: 607-257-1080 – fax:607-257-1146||||||||
|www.kionix.com - info@kionix.com||||||||
© 2016 Kionix – All Rights Reserved
Page 59 of 81
**PART NUMBER: ± 2g / 4g / 8g Tri-axis Digital KX124-1051 Accelerometer Specifications Rev. 1.0 20-Jan-16**
## **SELF_TEST**
When 0xCA is written to this register, the MEMS self-test function is enabled. Electrostatic-actuation of the accelerometer, results in a DC shift of the X, Y and Z axis outputs. Writing 0x00 to this register will return the accelerometer to normal operation.
**Note, this is a write-only register. Read back value from this register will always be 0x00.
W W W W W W W W W 1 1 0 0 1 0 1 0 Reset Value Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 00000000 ~~re~~ I[2] C Address: 0x60h
36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - info@kionix.com
© 2016 Kionix – All Rights Reserved
Page 60 of 81
||**PART NUMBER:**|
|---|---|
|**± 2g / 4g / 8g Tri-axis Digital**|**KX124-1051**|
|**Accelerometer Specifications**|**Rev. 1.0**|
||**20-Jan-16**|
## **Embedded Applications**
## **Orientation Detection Feature**
The orientation detection feature of the KX124 will report changes in face up, face down, ± vertical and ± horizontal orientation. This intelligent embedded algorithm considers very important factors that provide accurate orientation detection from low cost tri-axis accelerometers. Factors such as: hysteresis, device orientation angle and delay time are described below as these techniques are utilized inside the KX124.
## **Hysteresis**
A 45° tilt angle threshold seems like a good choice because it is halfway between 0° and 90°. However, a problem arises when the user holds the device near 45°. Slight vibrations, noise and inherent sensor error will cause the acceleration to go above and below the threshold rapidly and randomly, so the screen will quickly flip back and forth between the 0° and the 90° orientations. This problem is avoided in the KX124 by choosing a 30° threshold angle. With a 30° threshold, the screen will not rotate from 0° to 90° until the device is tilted to 60° (30° from 90°). To rotate back to 0°, the user must tilt back to 30°, thus avoiding the screen flipping problem. This example essentially applies ± 15° of hysteresis in between the four screen rotation states. Table 25 shows the acceleration limits implemented for T =30°.
|**Orientation X A**<br>~~=——~~|**n X Acceleration (g) Y A**<br>~~=——~~|**Y Acceleration (g)**<br>~~=——~~|
|---|---|---|
|0°/360°<br>~~=——~~|-0.5 <_ax_< 0.5<br>~~=——~~|_ay_> 0.866<br>~~=——~~|
|90°<br>~~=——~~|_ax_ > 0.866<br>~~=——~~|-0.5 < _ay_ < 0.5<br>~~=——~~|
|180°<br>~~=——~~|-0.5 <_ax_< 0.5<br>~~=——~~|_ay_<-0.866<br>~~=——~~|
|270°<br>~~=——~~|_ax_<-0.866<br>~~=——~~|-0.5 <_ay_< 0.5<br>~~=——~~|
**Table 25:** Acceleration at the four orientations with ± 15° of hysteresis
The KX124 allows the user to change the amount of hysteresis in between the four screen rotation states. By simply writing to the HYST_SET register, the user can adjust the amount of hysteresis up to ± 45°. The plot in Figure 8 shows the typical amount of hysteresis applied for a given digital count value of HYST_SET.
36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - info@kionix.com
© 2016 Kionix – All Rights Reserved
Page 61 of 81
**==> picture [499 x 329] intentionally omitted <==**
**----- Start of picture text -----**<br>
PART NUMBER:<br>± 2g / 4g / 8g Tri-axis Digital KX124-1051<br>Accelerometer Specifications Rev. 1.0<br>«6Kionix’<br>20-Jan-16<br>HYST_SET vs Hysteresis<br>50<br>45<br>40<br>35<br>30<br>25 Hysteresis<br>20<br>15<br>10<br>5<br>0<br>0 5 10 15 20 25 30<br>HYST_SET Value (Counts)<br>Hysteresis (+/- degrees)<br>**----- End of picture text -----**<br>
**Figure 8:** HYST_SET vs Hysteresis
## **Device Orientation Angle (aka Tilt Angle)**
To ensure that horizontal and vertical device orientation changes are detected, even when it isn’t in the ideal vertical orientation – where the angle θ in Figure 9 is 90°, the KX124 considers device orientation angle in its algorithm.
**Figure 9:** Device Orientation Angle
As the angle in Figure 9 is decreased, the maximum gravitational acceleration on the X-axis or Y-axis will also decrease. Therefore, when the angle becomes small enough, the user will not be able to make the screen orientation change. When the device orientation angle approaches 0° (device is flat on a desk
36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - info@kionix.com
© 2016 Kionix – All Rights Reserved
Page 62 of 81
6Kionix’
**PART NUMBER: ± 2g / 4g / 8g Tri-axis Digital KX124-1051 Accelerometer Specifications Rev. 1.0 20-Jan-16**
or table), _ax_ = _ay_ = 0g, _az_ = +1g, and there is no way to determine which way the screen should be oriented, the internal algorithm determines that the device is in either the face-up or face-down orientation, depending on the sign of the z-axis. The KX124 will only change the screen orientation when the orientation angle is above the factory-defaulted/user-defined threshold set in the TILT_ANGLE_LL register. Equation 2 can be used to determine what value to write to the TILT_ANGLE_LL register to set the device orientation angle. The value for TILT_ANGLE_HL is preset at the factory but can be adjusted in special cases (e.g. to reduce the effect of transient g-variation such as when device is being moved rather than just being rotated).
TILT_ANGLE_LL (counts) = sin θ * (32 (counts/g))
## **Equation 2:** Tilt Angle Threshold
## **Tilt Timer**
The 8-bit register, TILT_TIMER can be used to qualify changes in orientation. The KX124 does this by incrementing a counter with a size that is specified by the value in TILT_TIMER for each set of acceleration samples to verify that a change to a new orientation state is maintained. A user defined output data rate (ODR) determines the time period for each sample. Equation 3 shows how to calculate the TILT_TIMER register value for a desired delay time.
TILT_TIMER (counts) = Delay Time (sec) x ODR (Hz)
## **Equation 3:** Tilt Position Delay Time
36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - info@kionix.com
© 2016 Kionix – All Rights Reserved
Page 63 of 81
**PART NUMBER: ± 2g / 4g / 8g Tri-axis Digital KX124-1051 Accelerometer Specifications Rev. 1.0** 6Kionix’ **20-Jan-16**
## **Motion Interrupt Feature Description**
The Motion interrupt feature of the KX124 reports qualified changes in the high-pass filtered acceleration based on the Wake Up (ATH) threshold. If the high-pass filtered acceleration on any axis is greater than the userdefined wake up threshold (ATH), the device has transitioned from an inactive state to an active state. Equation 4 shows how to calculate the ATH register value for a desired wake up threshold.
ATH (counts) = Wake Up Threshold (g) x 16 (counts/g)
## **Equation 4:** Wake Up Threshold
An 8-bit raw unsigned value represents a counter that permits the user to qualify each active/inactive state change. Note that each WUFC Timer count qualifies 1 (one) user-defined ODR period (OWUF). Equation 5 shows how to calculate the WUFC register value for a desired wake up delay time.
WUFC (counts) = Wake Up Delay Time (sec) x OWUF (Hz)
## **Equation 5:** Wake Up Delay Time
The latched motion interrupt response algorithm works as following: while the part is in inactive state, the algorithm evaluates differential measurement between each new acceleration data point with the preceding one and evaluates it against the ATH threshold. When the differential measurement is greater than ATH threshold, the wakeup counter starts the count. Differential measurements are now calculated based on the difference between the current acceleration and the acceleration when the counter started. The part will report that motion has occurred at the end of the count assuming each differential measurement has remained above the threshold. If at any moment during the count the differential measurement falls below the threshold, the counter will stop the count and the part will remain in inactive state.
To illustrate how the algorithm works, consider the Figure 10 below that shows the latched response of the motion detection algorithm with WUF Timer (WUFC) set to 10 counts. Note how the difference between the acceleration sample marked in red and the one marked in green resulted in a differential measurements represented with orange bar being above the WUF threshold. At this point, the counter begins to count number of counts stored in WUFC register and the wakeup algorithm will evaluate the difference between each new acceleration measurement and the measurement marked in green that will remain a reference measurement for the duration of the counter count. At the end of the count, assuming all differential measurements were larger than WUF threshold, as is the case in the example showed in Figure 10, a motion event will be reported.
36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - info@kionix.com
© 2016 Kionix – All Rights Reserved
Page 64 of 81
**==> picture [347 x 66] intentionally omitted <==**
**----- Start of picture text -----**<br>
PART NUMBER:<br>± 2g / 4g / 8g Tri-axis Digital KX124-1051<br>Accelerometer Specifications Rev. 1.0<br>20-Jan-16<br>**----- End of picture text -----**<br>
**Figure 10:** Latched Motion Interrupt Response
36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - info@kionix.com
© 2016 Kionix – All Rights Reserved
Page 65 of 81
**==> picture [509 x 92] intentionally omitted <==**
**----- Start of picture text -----**<br>
PART NUMBER:<br>± 2g / 4g / 8g Tri-axis Digital KX124-1051<br>Accelerometer Specifications Rev. 1.0<br>20-Jan-16<br>Thon |<br>**----- End of picture text -----**<br>
## **Directional Tap Detection Feature Description**
The Directional Tap Detection feature of the KX124 recognizes single and double tap inputs and reports the acceleration axis and direction that each tap occurred. Eight performance parameters, as well as a userselectable ODR are used to configure the KX124 for a desired tap detection response.
## **Performance Index**
The Directional Tap[TM] detection algorithm uses low and high thresholds to help determine when a tap event has occurred. A tap event is detected when the previously described jerk summation exceeds the low threshold (TTL) for more than the tap detection low limit, but less than the tap detection high limit as contained in FTD. Samples that exceed the high limit (TTH) will be ignored. Figure 11 shows an example of a single tap event meeting the performance index criteria.
Calculated Performance Index
**==> picture [413 x 312] intentionally omitted <==**
**----- Start of picture text -----**<br>
PI<br>180 —<br>°© : Sampled Data<br>160<br>140<br>120<br>100<br>80<br>o<br>60<br>40<br> TTL<br>20<br>0<br>3.14 3.15 3.16 3.17 3.18 3.19 3.2 3.21<br>time(sec)<br>jerk (counts)<br>**----- End of picture text -----**<br>
**Figure 11:** Jerk Summation vs Threshold
36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - info@kionix.com
© 2016 Kionix – All Rights Reserved
Page 66 of 81
**==> picture [347 x 66] intentionally omitted <==**
**----- Start of picture text -----**<br>
PART NUMBER:<br>± 2g / 4g / 8g Tri-axis Digital KX124-1051<br>Accelerometer Specifications Rev. 1.0<br>20-Jan-16<br>**----- End of picture text -----**<br>
## **Single Tap Detection**
The latency timer (TLT) sets the time period that a tap event will only be characterized as a single tap. A second tap has to occur outside of the latency timer. If a second tap occurs inside the latency time, it will be ignored as it occurred too quickly. The single tap will be reported at the end of the TWS. Figure 12 shows a single tap event meeting the PI, latency and window requirements.
**==> picture [422 x 353] intentionally omitted <==**
**----- Start of picture text -----**<br>
Calculated Performance Index<br>160<br>PI<br>140<br> TWS<br><<<br>120<br>|<br>|<br>100<br>|<br>|<br> TLT<br>80<br>|<br>|<br>60<br>|<br>40<br>|<br> TTL |<br>a ee Seee na nen a an<br>20 in<br>i<br>0 v_wvnlla (VW\/ WARN AN Vw \ val! hall LAA AS LL. Mens WA! al A MVE AA pana NY Vaan aulaa My SY Lad<br>2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3 3.1<br>time(sec)<br>jerk (counts)<br>**----- End of picture text -----**<br>
**Figure 12:** Single Directional TapTM Timing
36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - info@kionix.com
© 2016 Kionix – All Rights Reserved
Page 67 of 81
**==> picture [347 x 66] intentionally omitted <==**
**----- Start of picture text -----**<br>
PART NUMBER:<br>± 2g / 4g / 8g Tri-axis Digital KX124-1051<br>Accelerometer Specifications Rev. 1.0<br>20-Jan-16<br>**----- End of picture text -----**<br>
## **Double Tap Detection**
An event can be characterized as a double tap if the second tap crosses the performance index (TTL) inside the TWS period and ends outside the TDTC. This means that the TDTC determines the minimum time separation that must exist between the two taps of a double tap event. Similar to the single tap, the first tap event must exceed the performance index for the time limit contained in FTD. Also, the duration when the first and second events combined exceed the performance index should not exceed STD. The double tap will be reported at the end of the second TLT. Figure 13 shows a double tap event meeting the PI, latency and window requirements.
**Figure 13:** Double Directional TapTM Timing
36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - info@kionix.com
© 2016 Kionix – All Rights Reserved
Page 68 of 81
**PART NUMBER: ± 2g / 4g / 8g Tri-axis Digital KX124-1051 Accelerometer Specifications Rev. 1.0** 6Kionix’ **20-Jan-16**
## **Free fall Detect**
The KX124 features a Free fall interrupt that sends a flag through INT1 or INT2 when the accelerometer senses a Free fall event. A Free fall event is evident when all three accelerometer axes simultaneously fall below a certain acceleration threshold for a set amount of time. The KX124 gives the user the option to define the acceleration threshold value through the FFTH 8-bit register where 256 counts cover the g range of the accelerometer. This value is compared to the top 8 bits of the accelerometer 8g output.
Through the Free Fall Counter (FFC), the user can set the amount of time all three accelerometer axes must simultaneously remain below the FFTH acceleration threshold before the Free fall interrupt flag is sent through INT1 or INT2. This delay/debounce time is defined by the available 0 to 255 counts, which represent accelerometer samples taken at the rate defined by OFFI<2:0>. Every count is calculated as 1/ODR delay period.
When the Free fall interrupt is enabled the part must not be in a physical state that would trigger the Free fall interrupt or the delay will not be correct for the present Free fall.
36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - info@kionix.com
© 2016 Kionix – All Rights Reserved
Page 69 of 81
**==> picture [119 x 52] intentionally omitted <==**
**----- Start of picture text -----**<br>
46Kionix’<br>**----- End of picture text -----**<br>
**PART NUMBER: ± 2g / 4g / 8g Tri-axis Digital KX124-1051 Accelerometer Specifications Rev. 1.0**
**20-Jan-16**
## Typical Freefall Interrupt Example (nonLatching)
**==> picture [109 x 204] intentionally omitted <==**
**----- Start of picture text -----**<br>
255<br>Pos. Motion limit 216<br>Pos. Freefall limit 148<br>0g 128<br>Neg. Freefall limit 108<br>Neg. Motion limit 40<br>0<br>Freefall debounce timer 10<br>Set to 10 counts.<br>FF/MOT Interrupt<br>**----- End of picture text -----**<br>
**Figure 14:** Typical Free fall Interrupt Example (FFC ULMODE = 1)
## Typical Freefall Interrupt Example (Latching)
**==> picture [108 x 203] intentionally omitted <==**
**----- Start of picture text -----**<br>
255<br>Pos. Motion limit 216<br>Pos. Freefall limit 148<br>0g 128<br>Neg. Freefall limit 108<br>Neg. Motion limit 40<br>0<br>Freefall debounce timer 10<br>Set to 10 counts.<br>FF/MOT Interrupt<br>**----- End of picture text -----**<br>
**Figure 15:** Typical Free fall Interrupt Example (FFC ULMODE = 0)
36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - info@kionix.com
© 2016 Kionix – All Rights Reserved
Page 70 of 81
**PART NUMBER: ± 2g / 4g / 8g Tri-axis Digital KX124-1051 Accelerometer Specifications Rev. 1.0** 6Kionix’ **20-Jan-16**
## **Sample Buffer Feature Description**
The sample buffer feature of the KX124 accumulates and outputs acceleration data based on how it is configured. There are 4 buffer modes available, and samples can be accumulated at either low (8-bit) or high (16-bit) resolution. Acceleration data is collected at the ODR specified by OSA in the ODCNTL register. Each buffer mode accumulates data, reports data, and interacts with status indicators in a slightly different way.
## **FIFO Mode**
Data Accumulation Data Reporting
Sample collection stops when the buffer is full.
Data is reported with the oldest byte of the oldest sample first (X_L or X based on resolution).
## Status Indicators
A watermark interrupt occurs when the number of samples in the buffer reaches the Sample Threshold. The watermark interrupt stays active until the buffer contains less than this number of samples. This can be accomplished through clearing the buffer or explicitly reading greater than SMPX samples (calculated with Equation 6).
BUF_RES=0: SMPX = SMP_LEV[10:0] /3 – SMP_TH[9:0]
BUF_RES=1: SMPX = SMP_LEV[10:0] /6 – SMP_TH[9:0]
## **Equation 6:** Samples Above Sample Threshold
## **Stream Mode**
## Data Accumulation
Sample collection continues when the buffer is full; older data is discarded to make room for newer data.
Data Reporting
Data is reported with the oldest sample first (uses FIFO read pointer).
## Status Indicators
A watermark interrupt occurs when the number of samples in the buffer reaches the Sample Threshold. The watermark interrupt stays active until the buffer contains less than this number of samples. This can be accomplished through clearing the buffer or explicitly reading greater than SMPX samples (calculated with Equation 6).
36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - info@kionix.com
© 2016 Kionix – All Rights Reserved
Page 71 of 81
**PART NUMBER: ± 2g / 4g / 8g Tri-axis Digital KX124-1051 Accelerometer Specifications Rev. 1.0** 6Kionix’
**20-Jan-16**
## **Trigger Mode**
## Data Accumulation
When a physical interrupt is caused by one of the digital engines or when a logic high signal occurs on the TRIG pin, the trigger event is asserted and SMP_TH[9:0] samples prior to the event are retained. Sample collection continues until the buffer is full. Data Reporting Data is reported with the oldest sample first (uses FIFO read pointer). Status Indicators When a physical interrupt occurs and there are at least SMP_TH[9:0] samples in the buffer, BUF_TRIG in BUF_STATUS_REG2 is asserted.
## **FILO Mode**
## Data Accumulation
Sample collection continues when the buffer is full; older data is discarded to make room for newer data.
Data Reporting
Data is reported with the newest byte of the newest sample first (Z_H or Z based on resolution).
Status Indicators
A watermark interrupt occurs when the number of samples in the buffer reaches the Sample Threshold. The watermark interrupt stays active until the buffer contains less than this number of samples. This can be accomplished through clearing the buffer or explicitly reading greater than SMPX samples (calculated with Equation 6).
## **Buffer Operation**
The following diagrams illustrate the operation of the buffer conceptually. Actual physical implementation has been abstracted to offer a simplified explanation of how the different buffer modes operate. Figure 16 represents a high-resolution 3-axis sample within the buffer. Figure 17 – Figure 25 represent a 10-sample version of the buffer (for simplicity), with Sample Threshold set to 8.
Regardless of the selected mode, the buffer fills sequentially, one byte at a time. Figure 16 shows one 6-byte data sample. Note the location of the FILO read pointer versus that of the FIFO read pointer.
36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - info@kionix.com
© 2016 Kionix – All Rights Reserved
Page 72 of 81
**PART NUMBER: ± 2g / 4g / 8g Tri-axis Digital KX124-1051 Accelerometer Specifications Rev. 1.0 20-Jan-16**
|buffer write pointer --|**Index**<br>**Byte**<br>0<br>X_L<br>1<br>X_H<br>2<br>Y_L<br>3<br>Y_H<br>4<br>Z_L<br>5<br>Z_H<br>6<br>~~=~~|-- FIFO read pointer<br>-- FILO read pointer|
|---|---|---|
## **Figure 16:** One Buffer Sample
Regardless of the selected mode, the buffer fills sequentially, one sample at a time. Note in Figure 17 the location of the FILO read pointer versus that of the FIFO read pointer. The buffer write pointer shows where the next sample will be written to the buffer.
||**Index**|**Sample**||
|---|---|---|---|
||0|Data0|←FIFO read pointer|
||1|Data1||
||2|Data2|←FILO read pointer|
|buffer write pointer→|3|||
||4|||
||5|||
||6|||
||7||←Sample Threshold|
||8|||
||9|||
**Figure 17:** Buffer Filling
36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - info@kionix.com
© 2016 Kionix – All Rights Reserved
Page 73 of 81
||**PART NUMBER:**|
|---|---|
|**± 2g / 4g / 8g Tri-axis Digital**|**KX124-1051**|
|**Accelerometer Specifications**|**Rev. 1.0**|
||**20-Jan-16**|
The buffer continues to fill sequentially until the Sample Threshold is reached. Note in Figure 18 the location of the FILO read pointer versus that of the FIFO read pointer.
||**Index**|**Sample**||
|---|---|---|---|
||0|Data0|←FIFO read pointer|
||1|Data1||
||2|Data2||
||3|Data3||
||4|Data4||
||5|Data5||
||6|Data6|←FILO read pointer|
|buffer write pointer→|7||←Sample Threshold|
||8|||
||9|||
**Figure 18:** Buffer Approaching Sample Threshold
In FIFO, Stream, and FILO modes, a watermark interrupt is issued when the number of samples in the buffer reaches the Sample Threshold. In trigger mode, this is the point where the oldest data in the buffer is discarded to make room for newer data.
||**Index**|**Sample**||
|---|---|---|---|
||0|Data0|←FIFO read pointer|
||1|Data1||
||2|Data2||
||3|Data3||
||4|Data4||
||5|Data5||
||6|Data6||
||7|Data7|←Sample Threshold/FILO read pointer|
|buffer write pointer→|8|||
||9|||
**Figure 19:** Buffer at Sample Threshold
36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - info@kionix.com
© 2016 Kionix – All Rights Reserved
Page 74 of 81
**PART NUMBER: ± 2g / 4g / 8g Tri-axis Digital KX124-1051 Accelerometer Specifications Rev. 1.0 20-Jan-16**
In trigger mode, data is accumulated in the buffer sequentially until the Sample Threshold is reached. Once the Sample Threshold is reached, the oldest samples are discarded when new samples are collected. Note in Figure 20 how Data0 was thrown out to make room for Data8.
||**Index**|**Sample**||
|---|---|---|---|
||0|Data1|←Trigger read pointer|
||1|Data2||
||2|Data3||
||3|Data4||
||4|Data5||
||5|Data6||
||6|Data7||
|Trigger write pointer→|7|Data8|←Sample Threshold|
||8|||
||9|||
**Figure 20:** Additional Data Prior to Trigger Event
After a trigger event occurs, the buffer no longer discards the oldest samples, and instead begins accumulating samples sequentially until full. The buffer then stops collecting samples, as seen in Figure 21. This results in the buffer holding SMP_TH[9:0] samples prior to the trigger event, and SMPX samples after the trigger event.
|**Index**|**Sample**||
|---|---|---|
|0|Data1|←Trigger read pointer|
|1|Data2||
|2|Data3||
|3|Data4||
|4|Data5||
|5|Data6||
|6|Data7||
|7|Data8|←Sample Threshold|
|8|Data9||
|9|Data10||
**Figure 21:** Additional Data after Trigger Event
36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - info@kionix.com
© 2016 Kionix – All Rights Reserved
Page 75 of 81
**PART NUMBER: ± 2g / 4g / 8g Tri-axis Digital KX124-1051 Accelerometer Specifications Rev. 1.0 20-Jan-16**
In FIFO, Stream, FILO, and Trigger (after a trigger event has occurred) modes, the buffer continues filling sequentially after the Sample Threshold is reached. Sample accumulation after the buffer is full depends on the selected operation mode. FIFO and Trigger modes stop accumulating samples when the buffer is full, and Stream and FILO modes begin discarding the oldest data when new samples are accumulated.
|**Index**|**Sample**||
|---|---|---|
|0|Data0|←FIFO read pointer|
|1|Data1||
|2|Data2||
|3|Data3||
|4|Data4||
|5|Data5||
|6|Data6||
|7|Data7|←Sample Threshold|
|8|Data8||
|9|Data9|←FILO read pointer|
**Figure 22:** Buffer Full
After the buffer has been filled in FILO or Stream mode, the oldest samples are discarded when new samples are collected. Note in Figure 21 how Data0 was thrown out to make room for Data10.
|**Index**|**Sample**||
|---|---|---|
|0|Data1|←FIFO read pointer|
|1|Data2||
|2|Data3||
|3|Data4||
|4|Data5||
|5|Data6||
|6|Data7||
|7|Data8|←Sample Threshold|
|8|Data9||
|9|Data10|←FILO read pointer|
**Figure 23:** Buffer Full – Additional Sample Accumulation in Stream or FILO Mode
36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - info@kionix.com
© 2016 Kionix – All Rights Reserved
Page 76 of 81
**PART NUMBER: ± 2g / 4g / 8g Tri-axis Digital KX124-1051 Accelerometer Specifications Rev. 1.0 20-Jan-16**
In FIFO, Stream, or Trigger mode, reading one sample from the buffer will remove the oldest sample and effectively shift the entire buffer contents up, as seen in Figure 24.
||**Index**|**Sample**||
|---|---|---|---|
||0|Data1|←FIFO read pointer|
||1|Data2||
||2|Data3||
||3|Data4||
||4|Data5||
||5|Data6||
||6|Data7||
||7|Data8|←Sample Threshold|
||8|Data9|←FILO read pointer|
|buffer write pointer→|9|||
**Figure 24:** FIFO Read from Full Buffer
In FILO mode, reading one sample from the buffer will remove the newest sample and leave the older samples untouched, as seen in Figure **25** .
||**Index**|**Sample**||
|---|---|---|---|
||0|Data0|←FIFO read pointer|
||1|Data1||
||2|Data2||
||3|Data3||
||4|Data4||
||5|Data5||
||6|Data6||
||7|Data7|←Sample Threshold|
||8|Data8|←FILO read pointer|
|buffer write pointer→|9|||
**Figure 25:** FILO Read from Full Buffer
36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - info@kionix.com
© 2016 Kionix – All Rights Reserved
Page 77 of 81
**PART NUMBER: ± 2g / 4g / 8g Tri-axis Digital KX124-1051 Accelerometer Specifications Rev. 1.0 20-Jan-16**
## **Notice**
## **Precaution on using KIONIX Products**
1. Our Products are designed and manufactured for application in ordinary electronic equipment (such as AV equipment, OA equipment, telecommunication equipment, home electronic appliances, amusement equipment, etc.). If you intend to use our Products in devices requiring extremely high reliability (such as medical equipment (Note 1), transport equipment, traffic equipment, aircraft/spacecraft, nuclear power controllers, fuel controllers, car equipment including car accessories, safety devices, etc.) and whose malfunction or failure may cause loss of human life, bodily injury or serious damage to property (“Specific Applications”), please consult with the KIONIX sales representative in advance. Unless otherwise agreed in writing by KIONIX in advance, KIONIX shall not be in any way responsible or liable for any damages, expenses or losses incurred by you or third parties arising from the use of any KIONIX’s Products for Specific Applications.
|2. KIONIX designs and manufactures its Products subject to strict quality control system. However, semiconductor|(Note1)Medical Equipment Classificationofthe SpecificApplications<br>JAPAN<br>USA<br>EU<br>CHINA<br>CLASSⅢ<br>CLASSⅢ<br>CLASSⅡb<br>CLASSⅢ<br>CLASSⅣ<br>CLASSⅢ<br>2. KIONIX designs and manufactures its Products subject to strict quality control system. However, semiconductor<br>~~——~~|(Note1)Medical Equipment Classificationofthe SpecificApplications<br>JAPAN<br>USA<br>EU<br>CHINA<br>CLASSⅢ<br>CLASSⅢ<br>CLASSⅡb<br>CLASSⅢ<br>CLASSⅣ<br>CLASSⅢ<br>2. KIONIX designs and manufactures its Products subject to strict quality control system. However, semiconductor<br>~~——~~|
|---|---|---|
||products can fail or malfunction at a certain rate. Please be sure to implement, at your own responsibilities,||
||adequate safety measures including but not limited to fail-safe design against the physical injury, damage to any||
||property, which a failure or malfunction of our Products may cause. The following are examples of safety measures:||
||a) Installation of protection circuits or other protective devices to improve system safety||
||b) Installation of redundant circuits to reduce the impact of single or multiple circuit failure||
|3. Our Products are designed and manufactured for use under standard conditions and not under any special or|3. Our Products are designed and manufactured for use under standard conditions and not under any special or|3. Our Products are designed and manufactured for use under standard conditions and not under any special or|
||extraordinary environments or conditions, as exemplified below. Accordingly, KIONIX shall not be in any way||
||responsible or liable for any damages, expenses or losses arising from the use of any KIONIX’s Products under||
||any special or extraordinary environments or conditions. If you intend to use our Products under any special or|any special or extraordinary environments or conditions. If you intend to use our Products under any special or|
||extraordinary environments or conditions (as exemplified below), your independent verification and confirmation of||
||product performance, reliability, etc., prior to use, must be necessary:||
||a) Use of our Products in any types of liquid, including water, oils, chemicals, and organic solvents||
||b) Use of our Products outdoors or in places where the Products are exposed to direct sunlight or dust||
||c) Use of our Products in places where the Products are exposed to sea wind or corrosive gases, including Cl2,||
||H2S, NH3, SO2, and NO2||
- d) Use of our Products in places where the Products are exposed to static electricity or electromagnetic waves
- e) Use of our Products in proximity to heat-producing components, plastic cords, or other flammable items f) Sealing or coating our Products with resin or other coating materials
- g) Use of our Products without cleaning residue of flux (even if you use no-clean type fluxes, cleaning residue of flux is recommended); or Washing our Products by using water or water-soluble cleaning agents for cleaning residue after soldering
- h) Use of the Products in places subject to dew condensation
4. The Products are not subject to radiation-proof design.
5. Please verify and confirm characteristics of the final or mounted products in using the Products.
6. In particular, if a transient load (a large amount of load applied in a short period of time, such as pulse. is applied, confirmation of performance characteristics after on-board mounting is strongly recommended. Avoid applying
36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - info@kionix.com
© 2016 Kionix – All Rights Reserved
Page 78 of 81
**PART NUMBER: ± 2g / 4g / 8g Tri-axis Digital KX124-1051 Accelerometer Specifications Rev. 1.0** 6Kionix’ **20-Jan-16**
power exceeding normal rated power; exceeding the power rating under steady-state loading condition may negatively affect product performance and reliability.
7. De-rate Power Dissipation (Pd) depending on ambient temperature (Ta). When used in sealed area, confirm the actual ambient temperature.
8. Confirm that operation temperature is within the specified range described in the product specification.
9. KIONIX shall not be in any way responsible or liable for failure induced under deviant condition from what is defined in this document.
## **Precaution for Mounting / Circuit board design**
1. When a highly active halogenous (chlorine, bromine, etc.) flux is used, the residue of flux may negatively affect product performance and reliability.
2. In principle, the reflow soldering method must be used; if flow soldering method is preferred, please consult with the KIONIX representative in advance.
For details, please refer to KIONIX Mounting specification.
## **Precautions Regarding Application Examples and External Circuits**
1. If change is made to the constant of an external circuit, please allow a sufficient margin considering variations of the characteristics of the Products and external components, including transient characteristics, as well as static characteristics.
2. You agree that application notes, reference designs, and associated data and information contained in this document are presented only as guidance for Products use. Therefore, in case you use such information, you are solely responsible for it and you must exercise your own independent verification and judgment in the use of such information contained in this document. KIONIX shall not be in any way responsible or liable for any damages, expenses or losses incurred by you or third parties arising from the use of such information.
## **Precaution for Electrostatic**
This Product is electrostatic sensitive product, which may be damaged due to electrostatic discharge. Please take proper caution in your manufacturing process and storage so that voltage exceeding the Products maximum rating will not be applied to Products. Please take special care under dry condition (e.g. Grounding of human body / equipment / solder iron, isolation from charged objects, setting of Ionizer, friction prevention and temperature / humidity control).
## **Precaution for Storage / Transportation**
1. Product performance and soldered connections may deteriorate if the Products are stored in the places where: a) the Products are exposed to sea winds or corrosive gases, including Cl2, H2S, NH3, SO2, and NO2 b) the temperature or humidity exceeds those recommended by KIONIX
- c) the Products are exposed to direct sunshine or condensation
- d) the Products are exposed to high Electrostatic
2. Even under KIONIX recommended storage condition, solderability of products out of recommended storage time period may be degraded. It is strongly recommended to confirm solderability before using Products of which storage time is exceeding the recommended storage time period.
3. Store / transport cartons in the correct direction, which is indicated on a carton with a symbol. Otherwise bent leads may occur due to excessive stress applied when dropping of a carton.
4. Use Products within the specified time after opening a humidity barrier bag. Baking is required before using Products of which storage time is exceeding the recommended storage time period.
36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - info@kionix.com
© 2016 Kionix – All Rights Reserved
Page 79 of 81
**PART NUMBER: ± 2g / 4g / 8g Tri-axis Digital KX124-1051 Accelerometer Specifications Rev. 1.0** 6Kionix’ **20-Jan-16**
## **Precaution for Product Label**
QR code printed on KIONIX Products label is for KIONIX’s internal use only.
## **Precaution for Disposition**
When disposing Products please dispose them properly using an authorized industry waste company.
## **Precaution for Foreign Exchange and Foreign Trade act**
Since our Products might fall under controlled goods prescribed by the applicable foreign exchange and foreign trade act, please consult with KIONIX representative in case of export.
## **Precaution Regarding Intellectual Property Rights**
1. All information and data including but not limited to application example contained in this document is for reference only. KIONIX does not warrant that foregoing information or data will not infringe any intellectual property rights or any other rights of any third party regarding such information or data. KIONIX shall not be in any way responsible or liable for infringement of any intellectual property rights or other damages arising from use of such information or data.
2. No license, expressly or implied, is granted hereby under any intellectual property rights or other rights of KIONIX or any third parties with respect to the information contained in this document.
## **Other Precaution**
1. This document may not be reprinted or reproduced, in whole or in part, without prior written consent of KIONIX.
2. The Products may not be disassembled, converted, modified, reproduced or otherwise changed without prior written consent of KIONIX.
3. In no event shall you use in any way whatsoever the Products and the related technical information contained in the Products or this document for any military purposes, including but not limited to, the development of massdestruction weapons.
4. The proper names of companies or products described in this document are trademarks or registered trademarks of KIONIX, its affiliated companies or third parties.
## **General Precaution**
1. Before you use our Products, you are requested to carefully read this document and fully understand its contents. KIONIX shall not be in any way responsible or liable for failure, malfunction or accident arising from the use of any KIONIX’s Products against warning, caution or note contained in this document.
2. All information contained in this document is current as of the issuing date and subject to change without any prior notice. Before purchasing or using KIONIX’s Products, please confirm the latest information with a KIONIX sales representative.
3. The information contained in this document is provided on an “as is” basis and KIONIX does not warrant that all information contained in this document is accurate and/or error-free. KIONIX shall not be in any way responsible or liable for any damages, expenses or losses incurred by you or third parties resulting from inaccuracy or errors of or concerning such information.
36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - info@kionix.com
© 2016 Kionix – All Rights Reserved
Page 80 of 81
**PART NUMBER: ± 2g / 4g / 8g Tri-axis Digital KX124-1051 Accelerometer Specifications Rev. 1.0 20-Jan-16**
**Revision History** REVISION DESCRIPTION DATE ~~ee~~ 1.0 Release 20-Jan-2016
"Kionix" is a registered trademark of Kionix, Inc. Products described herein are protected by patents issued or pending. No license is granted by implication or otherwise under any patent or other rights of Kionix. The information contained herein is believed to be accurate and reliable but is not guaranteed. Kionix does not assume responsibility for its use or distribution. Kionix also reserves the right to change product specifications or discontinue this product at any time without prior notice. This publication supersedes and replaces all information previously supplied.
36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - info@kionix.com
© 2016 Kionix – All Rights Reserved
Page 81 of 81
Updated at February 9, 2023
About Novapart
Novapart is a B2B electronic component broker specialising in stock shortages and cost reduction. We source hard-to-find parts and identify compliant alternatives across a catalogue of 410,000+ components from 500+ manufacturers.
Learn more →Stock Shortage Specialist
When a component is unavailable, discontinued or has an unacceptable lead time, we tap into our network of vetted European and Asian distributors to source what you need — without compromising on quality or traceability.
Request a quote →Compliant Alternatives
We identify pin-to-pin, electrically equivalent substitutes that meet the same certifications (RoHS, AEC-Q100, REACH) as your original specification — validated against datasheets, not just part numbers. Often at a lower cost.
BOM Analysis service →