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ISA170230C04LMDSXTMA1
Dual MOSFET, Complementary N and P Channel, 40 V, 40 V, 9.6 A, 9.6 A, 0.017 ohm
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- Manufacturer: INFINEON
- Product type: Dual MOSFETs
- SVHC: No SVHC (25-Jun-2025)
- No. of Pins: 8Pins
- Operating Temperature Max: 150°C
- Power Dissipation N Channel: 2.5W
- Power Dissipation P Channel: 2.5W
- Drain Source Voltage Vds N Channel: 40V
- Drain Source Voltage Vds P Channel: 40V
- Continuous Drain Current Id N Channel: 9.6A
- Continuous Drain Current Id P Channel: 9.6A
- Drain Source On State Resistance N Channel: 0.017ohm
- Drain Source On State Resistance P Channel: 0.023ohm
| Delivery and price | |
|---|---|
| Units per pack | 5000 |
| Price | 0.338 € |
| Current stock | 1000+ |
| Lead time | 30 days |
Datasheet
**Public ISA170230C04LMDS Final datasheet** ## **MOSFET** PG‑DSO‑8 ## OptiMOS™ 3 Power‑Transistors, 40 V ## **Features** - Complementary N‑ and P‑channel - Very low on‑resistance R - - DS(on) - Superior thermal resistance - - 100% avalanche tested - - Pb‑free lead plating; RoHS compliant - 8 7 6 5 1 2 oy 3 4 - Halogen‑free according to IEC61249‑2‑21 **==> picture [84 x 74] intentionally omitted <==** **----- Start of picture text -----**<br> Source 1 Drain 1<br>Pin 1 Pin 8<br>Gate 1 *1 Drain 1<br>Pin 2 Pin 7<br>Source 2 Drain 2<br>Pin 3 Pin 6<br>Gate 2 *1 Drain 2<br>Pin 4 Pin 5<br>**----- End of picture text -----**<br> ## **Product validation** Qualified according to JEDEC Standard **Table 1 Key Performance Parameters** |Parameter|Value|Unit| |---|---|---| |V<br>DS (n‑channel)|40|V| |R<br>DS(on),max (n‑channel)|17|mΩ| |I<br>D (n‑channel)|9.6|A| |V<br>DS (p‑channel)|‑40|V| |R<br>DS(on),max (p‑channel)|23|mΩ| |I<br>D (p‑channel)|‑8.8|A| _*1: Internal body diode_ I ‑8.8 A D (p‑channel) Js Type/Ordering Code Package Marking Related Links ISA170230C04LMDS PG‑DSO‑8 1723C04L ‑ oF Datasheet https://www.infineon.com Revision 2.0 2024‑10‑02 1 **Public** OptiMOS™ 3 Power‑Transistors, 40 V **ISA170230C04LMDS** **==> picture [108 x 48] intentionally omitted <==** ## **Table of Contents** **Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Electrical characteristics diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Disclaimer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18** Datasheet https://www.infineon.com Revision 2.0 2024‑10‑02 2 **Public** OptiMOS™ 3 Power‑Transistors, 40 V **ISA170230C04LMDS** **==> picture [108 x 48] intentionally omitted <==** ## **1 Maximum ratings** at TA=25 °C, unless otherwise specified **Table 2 Maximum ratings (n‑channel)** **==> picture [526 x 228] intentionally omitted <==** **----- Start of picture text -----**<br> Values<br>Parameter Symbol Unit Note/ Test Condition<br>Min. Typ. Max.<br>9.6 VGS=10 V, TC=25 °C<br>6.1 VGS=10 V, TC=100 °C<br>Continuous drain current [1)] ID ‑ ‑ 5.2 A VGS=4.5 V, TC=100 °C<br>7.2 VGS=10 V,TA=25 °C,RthJA=90 °C/W 2)<br>Pulsed drain current [3)] ID,pulse ‑ ‑ 38 A TA=25 °C<br>Avalanche energy, single pulse [4)] EAS ‑ ‑ 36 mJ ID=9.6 A, RGS=25 Ω<br>Gate source voltage VGS ‑20 ‑ 20 V ‑<br>2.5 TC=25 °C<br>Power dissipation Ptot ‑ ‑ 1.4 W TA=25 °C, RthJA=90 °C/W 2)<br>Operating and storage temperature T , Tj stg ‑55 ‑ 150 °C ‑<br>**----- End of picture text -----**<br> 1) Rating refers to the product only with datasheet specified absolute maximum values, maintaining case temperature as specified. For other case temperatures please refer to Diagram 2 for n‑channel and the Diagram 17 for p‑channel. De‑rating will be required based on the actual environmental conditions. 2) Device on 40 mm x 40 mm x 1.5 mm epoxy PCB FR4 with 6 cm2 (one layer, 70 μm thick) copper area for drain connection. PCB is vertical in still air. One transistor active. - 3) See Diagrams 3 and 18 for more detailed information - 4) See Diagrams 13 and 28 for more detailed information **Table 3 Maximum ratings (p‑channel)** **==> picture [526 x 228] intentionally omitted <==** **----- Start of picture text -----**<br> Values<br>Parameter Symbol Unit Note/ Test Condition<br>Min. Typ. Max.<br>‑8.8 VGS=‑10 V, TC=25 °C<br>‑5.6 VGS=‑10 V, TC=100 °C<br>Continuous drain current [5)] ID ‑ ‑ ‑4.9 A VGS=‑4.5 V, TC=100 °C<br>‑6.6 VGS=‑10 V,TA=25 °C,RthJA=90 °C/W 6)<br>Pulsed drain current [7)] ID,pulse ‑ ‑ ‑35 A TA=25 °C<br>Avalanche energy, single pulse [8)] EAS ‑ ‑ 36 mJ ID=‑8.8 A, RGS=25 Ω<br>Gate source voltage VGS ‑20 ‑ 20 V ‑<br>2.5 TC=25 °C<br>Power dissipation Ptot ‑ ‑ 1.4 W TA=25 °C, RthJA=90 °C/W 6)<br>Operating and storage temperature T , Tj stg ‑55 ‑ 150 °C ‑<br>**----- End of picture text -----**<br> 5) Rating refers to the product only with datasheet specified absolute maximum values, maintaining case temperature as specified. For other case temperatures please refer to Diagram 2 for n‑channel and the Diagram 17 for p‑channel. De‑rating will be required based on the actual environmental conditions. 6) Device on 40 mm x 40 mm x 1.5 mm epoxy PCB FR4 with 6 cm2 (one layer, 70 μm thick) copper area for drain connection. PCB is vertical in still air. One transistor active. Datasheet https://www.infineon.com Revision 2.0 2024‑10‑02 3 **Public** OptiMOS™ 3 Power‑Transistors, 40 V **ISA170230C04LMDS** **==> picture [108 x 48] intentionally omitted <==** - 7) See Diagrams 3 and 18 for more detailed information - 8) See Diagrams 13 and 28 for more detailed information Datasheet https://www.infineon.com Revision 2.0 2024‑10‑02 4 **Public** OptiMOS™ 3 Power‑Transistors, 40 V **ISA170230C04LMDS** **==> picture [108 x 48] intentionally omitted <==** ## **2 Thermal characteristics** **Table 4 Thermal characteristics** **==> picture [526 x 177] intentionally omitted <==** **----- Start of picture text -----**<br> Values<br>Parameter Symbol Unit Note/ Test Condition<br>Min. Typ. Max.<br>Thermal resistance, junction ‑ solder point RthJC ‑ ‑ 50 °C/W ‑<br>Thermal resistance, junction ‑<br>ambient, RthJA ‑ ‑ 150 °C/W ‑<br>minimal footprint, steady state<br>Thermal resistance, junction ‑<br>ambient, RthJA ‑ ‑ 90 °C/W ‑<br>6 cm² cooling area, steady state [9)]<br>**----- End of picture text -----**<br> 9) Device on 40 mm x 40 mm x 1.5 mm epoxy PCB FR4 with 6 cm2 (one layer, 70 μm thick) copper area for drain connection. PCB is vertical in still air. One transistor active. Datasheet https://www.infineon.com Revision 2.0 2024‑10‑02 5 **Public** OptiMOS™ 3 Power‑Transistors, 40 V **ISA170230C04LMDS** **==> picture [108 x 48] intentionally omitted <==** ## **3 Electrical characteristics** at =25 °C, unless otherwise specifiedTj **Table 5 Static characteristics (n‑channel)** **==> picture [526 x 208] intentionally omitted <==** **----- Start of picture text -----**<br> Values<br>Parameter Symbol Unit Note/ Test Condition<br>Min. Typ. Max.<br>Drain‑source breakdown voltage V(BR)DSS 40 ‑ ‑ V VGS=0 V, =1 mAID<br>Gate threshold voltage VGS(th) 1.1 ‑ 2.7 V VDS=VGS, =1000 μAID<br>Zero gate voltage drain current IDSS ‑ 0.1 10 1 100 μA VVDSDS=40 V, =40 V, VVGSGS=0 V, =25 °C =0 V, =125 °CTTjj<br>Gate‑source leakage current IGSS ‑ 10 100 nA VGS=20 V, VDS=0 V<br>Drain‑source on‑state resistance R ‑ 13 17 VGS=10 V, =9.6 A ID<br>DS(on)<br>18 23.6 [mΩ] VGS=4.5 V, =8.5 AID<br>Gate resistance RG ‑ 1.1 ‑ Ω ‑<br>Transconductance [10)] gfs 12 25 ‑ S |VDS|≥2|ID|RDS(on)max, =9.6 AID<br>**----- End of picture text -----**<br> - 10) Defined by design. Not subject to production test. **Table 6 Static characteristics (p‑channel)** **==> picture [526 x 207] intentionally omitted <==** **----- Start of picture text -----**<br> Values<br>Parameter Symbol Unit Note/ Test Condition<br>Min. Typ. Max.<br>Drain‑source breakdown voltage V(BR)DSS ‑40 ‑ ‑ V VGS=0 V, =‑1 mAID<br>Gate threshold voltage VGS(th) ‑1.1 ‑ ‑2.7 V VDS=VGS, =‑1000 μAID<br>Zero gate voltage drain current IDSS ‑ ‑0.1 ‑1 VDS=‑40 V, VGS=0 V, =25 °C Tj<br>‑10 ‑100 [μA] VDS=‑40 V, VGS=0 V, =125 °CTj<br>Gate‑source leakage current IGSS ‑ ‑10 ‑100 nA VGS=‑20 V, VDS=0 V<br>Drain‑source on‑state resistance R ‑ 18 23 VGS=‑10 V, =‑8.8 A ID<br>DS(on)<br>23 29.5 [mΩ] VGS=‑4.5 V, =‑6.9 AID<br>Gate resistance RG ‑ 3 ‑ Ω ‑<br>Transconductance [11)] gfs 12 24 ‑ S |VDS|≥2|ID|RDS(on)max, =‑8.8 AID<br>**----- End of picture text -----**<br> - 11) Defined by design. Not subject to production test. **Table 7 Dynamic characteristics (n‑channel)** **==> picture [526 x 140] intentionally omitted <==** **----- Start of picture text -----**<br> Values<br>Parameter Symbol Unit Note/ Test Condition<br>Min. Typ. Max.<br>Input capacitance [12)] Ciss ‑ 880 1100 pF VGS=0 V, VDS=20 V, =1 MHzf<br>Output capacitance [12)] Coss ‑ 220 290 pF VGS=0 V, VDS=20 V, =1 MHzf<br>Reverse transfer capacitance [12)] Crss ‑ 15 26 pF VGS=0 V, VDS=20 V, =1 MHzf<br>Turn‑on delay time td(on) ‑ 6.7 ‑ ns VRDD=20 V, =1.6 ΩVGS=4.5 V, =9.6 A, ID<br>G,ext<br>**----- End of picture text -----**<br> Datasheet https://www.infineon.com Revision 2.0 2024‑10‑02 6 **Public** OptiMOS™ 3 Power‑Transistors, 40 V **ISA170230C04LMDS** **==> picture [108 x 48] intentionally omitted <==** **Table 7 Dynamic characteristics (n‑channel)** **==> picture [526 x 300] intentionally omitted <==** **----- Start of picture text -----**<br> Values<br>Parameter Symbol Unit Note/ Test Condition<br>Min. Typ. Max.<br>Rise time tr ‑ 5.0 ‑ ns VRDD=20 V, =1.6 ΩVGS=4.5 V, =9.6 A, ID<br>G,ext<br>Turn‑off delay time td(off) ‑ 4.6 ‑ ns VRDD=20 V, =1.6 ΩVGS=4.5 V, =9.6 A, ID<br>G,ext<br>Fall time tf ‑ 4.0 ‑ ns VRDD=20 V, =1.6 ΩVGS=4.5 V, =9.6 A, ID<br>G,ext<br>Gate to source charge Qgs ‑ 2.7 ‑ nC VDD=20 V, =9.6 A, ID VGS=0 to 4.5 V<br>Gate charge at threshold Qg(th) ‑ 1.5 ‑ nC VDD=20 V, =9.6 A, ID VGS=0 to 4.5 V<br>Gate to drain charge Qgd ‑ 1.6 ‑ nC VDD=20 V, =9.6 A, ID VGS=0 to 4.5 V<br>Switching charge Qsw ‑ 2.8 ‑ nC VDD=20 V, =9.6 A, ID VGS=0 to 4.5 V<br>Gate charge total [12)] Qg ‑ 6.0 9.0 nC VDD=20 V, =9.6 A, ID VGS=0 to 4.5 V<br>Gate plateau voltage Vplateau ‑ 3.1 ‑ V VDD=20 V, =9.6 A, ID VGS=0 to 4.5 V<br>Gate charge total Qg ‑ 13 19.5 nC VDD=20 V, =9.6 A, ID VGS=0 to 10 V<br>Output charge Qoss ‑ 7.8 ‑ nC VDS=20 V, VGS=0 V<br>**----- End of picture text -----**<br> - 12) Defined by design. Not subject to production test. **Table 8 Dynamic characteristics (p‑channel)** **==> picture [526 x 343] intentionally omitted <==** **----- Start of picture text -----**<br> Values<br>Parameter Symbol Unit Note/ Test Condition<br>Min. Typ. Max.<br>Input capacitance [13)] Ciss ‑ 1900 2500 pF VGS=0 V, VDS=‑20 V, =1 MHzf<br>Output capacitance [13)] Coss ‑ 750 980 pF VGS=0 V, VDS=‑20 V, =1 MHzf<br>Reverse transfer capacitance [13)] Crss ‑ 38 67 pF VGS=0 V, VDS=‑20 V, =1 MHzf<br>Turn‑on delay time td(on) ‑ 15 ‑ ns VRDD=‑20 V, =1.6 ΩVGS=‑4.5 V, =‑8.8 A, ID<br>G,ext<br>Rise time tr ‑ 8.9 ‑ ns VRDD=‑20 V, =1.6 ΩVGS=‑4.5 V, =‑8.8 A, ID<br>G,ext<br>Turn‑off delay time td(off) ‑ 15 ‑ ns VRDD=‑20 V, =1.6 ΩVGS=‑4.5 V, =‑8.8 A, ID<br>G,ext<br>Fall time tf ‑ 7.4 ‑ ns VRDD=‑20 V, =1.6 ΩVGS=‑4.5 V, =‑8.8 A, ID<br>G,ext<br>Gate to source charge Qgs ‑ ‑5.9 ‑ nC VDD=‑20 V, =‑8.8 A, ID VGS=0 to ‑4.5 V<br>Gate charge at threshold Qg(th) ‑ ‑3.3 ‑ nC VDD=‑20 V, =‑8.8 A, ID VGS=0 to ‑4.5 V<br>Gate to drain charge Qgd ‑ ‑3.5 ‑ nC VDD=‑20 V, =‑8.8 A, ID VGS=0 to ‑4.5 V<br>Switching charge Qsw ‑ ‑6.1 ‑ nC VDD=‑20 V, =‑8.8 A, ID VGS=0 to ‑4.5 V<br>Gate charge total [13)] Qg ‑ ‑12.6 ‑19 nC VDD=‑20 V, =‑8.8 A, ID VGS=0 to ‑4.5 V<br>**----- End of picture text -----**<br> Datasheet https://www.infineon.com Revision 2.0 2024‑10‑02 7 **Public** OptiMOS™ 3 Power‑Transistors, 40 V **ISA170230C04LMDS** **==> picture [108 x 48] intentionally omitted <==** **Table 8 Dynamic characteristics (p‑channel)** **==> picture [526 x 100] intentionally omitted <==** **----- Start of picture text -----**<br> Values<br>Parameter Symbol Unit Note/ Test Condition<br>Min. Typ. Max.<br>Gate plateau voltage Vplateau ‑ ‑3.1 ‑ V VDD=‑20 V, =‑8.8 A, ID VGS=0 to ‑4.5 V<br>Gate charge total [13)] Qg ‑ ‑25 ‑38 nC VDD=‑20 V, =‑8.8 A, ID VGS=0 to ‑10 V<br>Output charge Qoss ‑ ‑22 ‑ nC VDS=‑20 V, VGS=0 V<br>**----- End of picture text -----**<br> - 13) Defined by design. Not subject to production test. **Table 9 Reverse diode (n‑channel)** **==> picture [526 x 136] intentionally omitted <==** **----- Start of picture text -----**<br> Values<br>Parameter Symbol Unit Note/ Test Condition<br>Min. Typ. Max.<br>Diode continuous forward current IS ‑ ‑ 3.1 A TC=25 °C<br>Diode pulse current IS,pulse ‑ ‑ 38 A TA=25 °C<br>Diode forward voltage VSD ‑ 0.86 1 V VGS=0 V, =9.6 A, =25 °CIF Tj<br>Reverse recovery time trr ‑ 13 ‑ ns VR=20 V, =9.6 A, dIF iF/dt=100 A/μs<br>Reverse recovery charge Qrr ‑ 4.3 ‑ nC VR=20 V, =9.6 A, dIF iF/dt=100 A/μs<br>**----- End of picture text -----**<br> **Table 10 Reverse diode (p‑channel)** **==> picture [526 x 136] intentionally omitted <==** **----- Start of picture text -----**<br> Values<br>Parameter Symbol Unit Note/ Test Condition<br>Min. Typ. Max.<br>Diode continuous forward current IS ‑ ‑ ‑3.4 A TC=25 °C<br>Diode pulse current IS,pulse ‑ ‑ ‑35 A TA=25 °C<br>Diode forward voltage VSD ‑ ‑0.86 ‑1 V VGS=0 V, =‑8.8 A, =25 °CIF Tj<br>Reverse recovery time trr ‑ 22 ‑ ns VR=‑20 V, =‑8.8 A, dIF iF/dt=‑100 A/μs<br>Reverse recovery charge Qrr ‑ 11 ‑ nC VR=‑20 V, =‑8.8 A, dIF iF/dt=‑100 A/μs<br>**----- End of picture text -----**<br> Datasheet https://www.infineon.com Revision 2.0 2024‑10‑02 8 **Public** OptiMOS™ 3 Power‑Transistors, 40 V **ISA170230C04LMDS** **==> picture [108 x 48] intentionally omitted <==** ## **4 Electrical characteristics diagrams** **==> picture [529 x 299] intentionally omitted <==** **----- Start of picture text -----**<br> Diagram 1: Power dissipation (n‑channel) Diagram 2: Drain current (n‑channel)<br>3.00 10<br>2.75<br>9<br>2.50<br>8<br>2.25<br>7<br>2.00<br>6<br>1.75<br>1.50 5<br>1.25<br>4<br>1.00<br>3<br>0.75<br>2<br>0.50<br>1<br>0.25<br>0.00 0<br>0 25 50 75 100 125 150 175 0 25 50 75 100 125 150 175<br>TC [°C] TC [°C]<br>Ptot=f(TC) ID=f(TC); VGS≥10 V<br>[W] [A]<br>Ptot ID<br>**----- End of picture text -----**<br> Diagram 3: Safe operating area (n‑channel) Diagram 4: Max. transient thermal impedance (n‑ channel) **==> picture [529 x 280] intentionally omitted <==** **----- Start of picture text -----**<br> 10 [2] 10 [3]<br>single pulse<br>0.01<br>1 µs<br>0.02<br>10 [1] 0.05<br>10 µs 0.1<br>0.2<br>10 [2]<br>0.5<br>10 [0] 100 µs<br>10 1 1 ms 10 [1]<br>10 2 10 ms<br>10 [0]<br>10 3<br>DC<br>10 4 10 1<br>10 1 10 [0] 10 [1] 10 [2] 10 5 10 4 10 3 10 2 10 1 10 [0] 10 [1]<br>VDS [V] tp [s]<br>ID=f(VDS); TC=25 °C; =0; parameter: D tp ZthJC=f(tp); parameter: =D tp/T<br>[A] [K/W]<br>D<br>I<br>thJC<br>Z<br>**----- End of picture text -----**<br> Datasheet https://www.infineon.com Revision 2.0 2024‑10‑02 9 **Public** OptiMOS™ 3 Power‑Transistors, 40 V **ISA170230C04LMDS** **==> picture [108 x 48] intentionally omitted <==** Diagram 5: Typ. output characteristics (n‑channel) Diagram 6: Typ. drain‑source on resistance (n‑channel) **==> picture [529 x 599] intentionally omitted <==** **----- Start of picture text -----**<br> 40 40<br>10 V 4.5 V 3.5 V<br>5 V<br>35 4 V<br>35<br>30<br>30<br>25<br>25<br>20<br>3.5 V 4 V<br>20<br>4.5 V<br>15<br>5 V<br>15<br>10<br>10 V<br>3 V 10<br>5<br>0 5<br>0.0 0.5 1.0 1.5 2.0 2.5 3.0 0 2 4 6 8 10 12 14 16 18 20<br>VDS [V] ID [A]<br>ID=f(VDS), =25 °C; parameter: Tj VGS RDS(on)=f(ID), =25 °C; parameter: Tj VGS<br>Diagram 7: Typ. transfer characteristics (n‑channel) Diagram 8: Typ. drain‑source on resistance (n‑channel)<br>40 40<br>35<br>30<br>30<br>25<br>20<br>15<br>150 °C<br>20<br>10<br>150 °C<br>5 25 °C<br>25 °C<br>0 10<br>0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 0 2 4 6 8 10 12 14 16<br>VGS [V] VGS [V]<br>ID=f(VGS), |VDS|>2|ID|RDS(on)max; parameter: Tj RDS(on)=f(VGS), =9.6 A; parameter: ID Tj<br>]<br>[m<br>[A]<br>D<br>I<br>DS(on)<br>R<br>]<br>[m<br>[A]<br>D<br>I<br>DS(on)<br>R<br>**----- End of picture text -----**<br> Datasheet https://www.infineon.com Revision 2.0 2024‑10‑02 10 **Public** OptiMOS™ 3 Power‑Transistors, 40 V **ISA170230C04LMDS** **==> picture [108 x 48] intentionally omitted <==** Diagram 9: Normalized drain‑source on resistance (n‑ channel) Diagram 10: Typ. gate threshold voltage (n‑channel) **==> picture [529 x 280] intentionally omitted <==** **----- Start of picture text -----**<br> 1.8 2.4<br>1.6<br>1.4 2.0<br>1.2<br>1.0 1.6<br>0.8<br>0.6 1.2<br>75 50 25 0 25 50 75 100 125 150 175 75 50 25 0 25 50 75 100 125 150 175<br>Tj [°C] Tj [°C]<br>RDS(on)=f(Tj), =9.6 A, ID VGS=10 V VGS(th=f(Tj), VGS=VDS; parameter: =1000μAID<br>°C)<br>25<br>to<br>[V]<br>GS(th)<br>V<br>(normalized<br>DS(on)<br>R<br>**----- End of picture text -----**<br> Diagram 11: Typ. capacitances (n‑channel) Diagram 12: Forward characteristics of reverse diode (n‑ ch.) **==> picture [529 x 280] intentionally omitted <==** **----- Start of picture text -----**<br> 10 [4] 10 [2]<br>25 °C<br>150 °C<br>10 [3]<br>Ciss<br>10 [1]<br>10 [2]<br>Coss<br>10 [0]<br>10 [1]<br>Crss<br>10 [0] 10 1<br>0 5 10 15 20 25 30 35 40 0.0 0.2 0.4 0.6 0.8 1.0 1.2<br>VDS [V] VSD [V]<br>C=f(VDS); VGS=0 V; =1 MHzf IF=f(VSD); parameter: Tj<br>[pF] [A]<br>F<br>C I<br>**----- End of picture text -----**<br> Datasheet https://www.infineon.com Revision 2.0 2024‑10‑02 11 **Public** OptiMOS™ 3 Power‑Transistors, 40 V **ISA170230C04LMDS** **==> picture [108 x 48] intentionally omitted <==** **==> picture [529 x 634] intentionally omitted <==** **----- Start of picture text -----**<br> Diagram 13: Avalanche characteristics (n‑channel) Diagram 14: Typ. gate charge (n‑channel)<br>10 [2] 10<br>8 V<br>20 V<br>9 32 V<br>8<br>7<br>10 [1]<br>6<br>25 °C<br>5<br>100 °C 4<br>10 [0]<br>3<br>125 °C 2<br>1<br>10 1 0<br>10 [0] 10 [1] 10 [2] 10 [3] 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14<br>tAV [µs] Qgate [nC]<br>IAS=f(tAV); RGS=25 Ω; parameter: Tj,start VGS=f(Qgate), =9.6 A pulsed, =25 °C; parameter: ID Tj VDD<br>Diagram 15: Drain‑source breakdown voltage (n‑<br>Diagram 16: Power dissipation (p‑channel)<br>channel)<br>43 3.00<br>2.75<br>2.50<br>42<br>2.25<br>2.00<br>41<br>1.75<br>1.50<br>1.25<br>40<br>1.00<br>0.75<br>39<br>0.50<br>0.25<br>38 0.00<br>75 50 25 0 25 50 75 100 125 150 175 0 25 50 75 100 125 150 175<br>Tj [°C] TC [°C]<br>VBR(DSS)=f(Tj); =1 mAID Ptot=f(TC)<br>[A] [V]<br>AV GS<br>I V<br>[V]<br>[W]<br>tot<br>BR(DSS) P<br>V<br>**----- End of picture text -----**<br> Datasheet https://www.infineon.com Revision 2.0 2024‑10‑02 12 **Public** OptiMOS™ 3 Power‑Transistors, 40 V **ISA170230C04LMDS** **==> picture [108 x 48] intentionally omitted <==** **==> picture [529 x 299] intentionally omitted <==** **----- Start of picture text -----**<br> Diagram 17: Drain current (p‑channel) Diagram 18: Safe operating area (p‑channel)<br>10 10 [2]<br>1 µs<br>9<br>10 µs<br>10 [1]<br>8<br>7 100 µs<br>10 [0]<br>6<br>5 10 1 1 ms<br>4<br>10 2 10 ms<br>3<br>2<br>10 3<br>1<br>DC<br>0 10 4<br>0 25 50 75 100 125 150 175 10 1 10 [0] 10 [1] 10 [2]<br>TC [°C] VDS [V]<br>ID=f(TC); |VGS|≥10 V ID=f(VDS); TC=25 °C; =0; parameter: D tp<br>[A] [A]<br>ID ID<br>**----- End of picture text -----**<br> Diagram 19: Max. transient thermal impedance (p‑ channel) Diagram 20: Typ. output characteristics (p‑channel) **==> picture [529 x 280] intentionally omitted <==** **----- Start of picture text -----**<br> 10 [3] 40<br>single pulse 10 V 5 V<br>0.01 4.5 V<br>0.02 35<br>0.05<br>0.1<br>0.2 4 V<br>10 [2] 30<br>0.5<br>25<br>10 [1] 20<br>3.5 V<br>15<br>10 [0] 10<br>3 V<br>5<br>10 1 0<br>10 5 10 4 10 3 10 2 10 1 10 [0] 10 [1] 0.0 0.5 1.0 1.5 2.0 2.5 3.0<br>tp [s] VDS [V]<br>ZthJC=f(tp); parameter: =D tp/T ID=f(VDS), =25 °C; parameter: Tj VGS<br>[A]<br>[K/W]<br>D<br>thJC I<br>Z<br>**----- End of picture text -----**<br> Datasheet https://www.infineon.com Revision 2.0 2024‑10‑02 13 **Public** OptiMOS™ 3 Power‑Transistors, 40 V **ISA170230C04LMDS** **==> picture [108 x 48] intentionally omitted <==** Diagram 21: Typ. drain‑source on resistance (p‑channel) Diagram 22: Typ. transfer characteristics (p‑channel) **==> picture [529 x 615] intentionally omitted <==** **----- Start of picture text -----**<br> 60 40<br>35<br>50<br>30<br>3.5 V<br>25<br>40<br>20<br>4 V<br>30<br>15<br>4.5 V<br>10<br>5 V<br>20<br>5<br>10 V<br>150 °C<br>25 °C<br>10 0<br>0 2 4 6 8 10 12 14 16 18 20 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0<br>ID [A] VGS [V]<br>RDS(on)=f(ID), =25 °C; parameter: Tj VGS ID=f(VGS), |VDS|>2|ID|RDS(on)max; parameter: Tj<br>Diagram 23: Typ. drain‑source on resistance (p‑channel) [Diagram 24: Normalized drain‑source on resistance (p‑]<br>ch.)<br>60 1.6<br>50 1.4<br>40 1.2<br>30 1.0<br>150 °C<br>20 0.8<br>25 °C<br>10 0.6<br>0 2 4 6 8 10 12 14 16 75 50 25 0 25 50 75 100 125 150 175<br>VGS [V] Tj [°C]<br>RDS(on)=f(VGS), =‑8.8 A; parameter: ID Tj RDS(on)=f(Tj), =‑8.8 A, ID VGS=‑10 V<br>]<br>[m [A]<br>D<br>I<br>DS(on)<br>R<br>°C)<br>25<br>] to<br>[m<br>DS(on)<br>R<br>(normalized<br>DS(on)<br>R<br>**----- End of picture text -----**<br> Datasheet https://www.infineon.com Revision 2.0 2024‑10‑02 14 **Public** OptiMOS™ 3 Power‑Transistors, 40 V **ISA170230C04LMDS** **==> picture [108 x 48] intentionally omitted <==** Diagram 25: Typ. gate threshold voltage (p‑channel) Diagram 26: Typ. capacitances (p‑channel) **==> picture [529 x 280] intentionally omitted <==** **----- Start of picture text -----**<br> 2.2 10 [4]<br>Ciss<br>2.0<br>10 [3]<br>Coss<br>1.8<br>1.6 10 [2]<br>1.4 Crss<br>10 [1]<br>1.2<br>1.0 10 [0]<br>75 50 25 0 25 50 75 100 125 150 175 0 5 10 15 20 25 30 35 40<br>Tj [°C] VDS [V]<br>VGS(th=f(Tj), VGS=VDS; parameter: =1000μAID C=f(VDS); VGS=0 V; =1 MHzf<br>[V]<br>[pF]<br>GS(th) C<br>V<br>**----- End of picture text -----**<br> Diagram 27: Forward characteristics of reverse diode (p‑ ch.) Diagram 28: Avalanche characteristics (p‑channel) **==> picture [529 x 280] intentionally omitted <==** **----- Start of picture text -----**<br> 10 [2] 10 [2]<br>25 °C<br>150 °C<br>10 [1] 10 [1]<br>25 °C<br>100 °C<br>10 [0] 10 [0]<br>125 °C<br>10 1 10 1<br>0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 10 [0] 10 [1] 10 [2] 10 [3]<br>VSD [V] tAV [µs]<br>IF=f(VSD); parameter: Tj IAS=f(tAV); RGS=25 Ω; parameter: Tj,start<br>[A]<br>[A]<br>IF IAV<br>**----- End of picture text -----**<br> Datasheet https://www.infineon.com Revision 2.0 2024‑10‑02 15 **Public** OptiMOS™ 3 Power‑Transistors, 40 V **ISA170230C04LMDS** Diagram 29: Typ. gate charge (p‑channel) Diagram 30: Drain‑source breakdown voltage (p‑ channel) **==> picture [528 x 271] intentionally omitted <==** **----- Start of picture text -----**<br> 10 42<br>8 V<br>er ba<br>20 V<br>9 32 V<br>8 Mr<br>Vj<br>7<br>Mf<br>V4 41<br>6 bie<br>5 Vi<br>Ve<br>4<br>40<br>3<br>2<br>1<br>0 od 39<br>0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 75 50 25 0 25 50 75 100 125 150 175<br>Qgate [nC] Tj [°C]<br>rs VGS=f(Qgate), =‑8.8 A pulsed, =25 °C; parameter: ID Tj VDD VBR(DSS)=f(Tj); =‑1 mAID<br>[V]<br>[V]<br>GS<br>V BR(DSS)<br>V<br>**----- End of picture text -----**<br> ## Gate charge waveforms ee ‑ ee Datasheet https://www.infineon.com Revision 2.0 2024‑10‑02 16 **Public** OptiMOS™ 3 Power‑Transistors, 40 V **ISA170230C04LMDS** **==> picture [108 x 48] intentionally omitted <==** ## **5 Package Outlines** |PACKAGE - GROUP<br>NUMBER:|PACKAGE - GROUP<br>NUMBER:|**PG-DSO-8-U02**|**PG-DSO-8-U02**| |---|---|---|---| |**DIMENSIONS**||MIN.<br>MAX.<br>**MILLIMETERS**|| |**A**||0.18|0.25| |**A1**||1.35|1.75| |**b**||0.38|0.51| |**c**||0.254|| |**D**||4.80|5.00| |**E**||5.80|6.20| |**E1**||3.80|4.00| |**e**||1.27|| |**L**||0.48|0.91| |**O**||4°|| |**N**||8|| **Figure 1** Outline PG‑DSO‑8, dimensions in mm Datasheet https://www.infineon.com Revision 2.0 2024‑10‑02 17 **Public** OptiMOS™ 3 Power‑Transistors, 40 V **ISA170230C04LMDS** **==> picture [108 x 48] intentionally omitted <==** ## **Revision History** ISA170230C04LMDS ## **Revision 2024‑10‑02, Rev. 2.0** Previous Revision Revision Date Subjects (major changes since last revision) 2.0 2024‑10‑02 Release of final datasheet ## Trademarks All referenced product or service names and trademarks are the property of their respective owners. We Listen to Your Comments Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us to continuously improve the quality of this document. Please send your proposal (including a reference to this document) to: erratum@infineon.com Published by Infineon Technologies AG 81726 München, Germany © 2024 Infineon Technologies AG All Rights Reserved. ## Legal Disclaimer The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics (“Beschaffenheitsgarantie”) . With respect to any examples, hints or any typical values stated herein and/or any information regarding the application of the product, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation warranties of non‑infringement of intellectual property rights of any third party. In addition, any information given in this document is subject to customer’s compliance with its obligations stated in this document and any applicable legal requirements, norms and standards concerning customer’s products and any use of the product of Infineon Technologies in customer’s applications. The data contained in this document is exclusively intended for technically trained staff. It is the responsibility of customer’s technical departments to evaluate the suitability of the product for the intended application and the completeness of the product information given in this document with respect to such application. ## Information For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office (www. infineon.com). ## Warnings Due to technical requirements, components may contain dangerous substances. For information on the types in question, please contact the nearest Infineon Technologies Office. The Infineon Technologies component described in this Data Sheet may be used in life‑support devices or systems and/or automotive, aviation and aerospace applications or systems only with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life‑support, automotive, aviation and aerospace device or system or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. Datasheet https://www.infineon.com Revision 2.0 2024‑10‑02 18
Updated at June 9, 2026
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