IRLD014PBF

**IRLD014** 

Vishay Siliconix 

www.vishay.com 

## **Power MOSFET** 

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D<br>HVMDIP<br>G<br>S<br>G<br>D S<br>N-Channel MOSFET<br>**----- End of picture text -----**<br>


|**PRODUCT SUMMARY**|**PRODUCT SUMMARY**|**PRODUCT SUMMARY**|
|---|---|---|
|VDS(V)|60||
|RDS(on)(Ω)|VGS= 5 V|0.20|
|Qg(Max.) (nC)|8.4||
|Qgs(nC)|2.6||
|Qgd(nC)|6.4||
|Configuration|Single||



## **FEATURES** 

- Dynamic dV/dt rating 

- For automatic insertion 

- End stackable 

- Logic-level gate drive 

- RDS(on) specified at VGS = 4 V and 5 V 

- 175 °C operating temperature 

- Fast switching 

- Material categorization: for definitions of compliance please see www.vishay.com/doc?99912 

## **DESCRIPTION** 

Third generation power MOSFETs from Vishay provide the designer with the best combination of fast switching, ruggedized device design, low on-resistance and cost-effectiveness. 

The 4 pin DIP package is a low cost machine-insertiable case style which can be stacked in multiple combinations on standard 0.1" pin centers. The dual drain servers as a thermal link to the mounting surface for power dissipation levels up to 1 W. 

|**ORDERING INFORMATION**|**ORDERING INFORMATION**|
|---|---|
|Package|HVMDIP|
|Lead (Pb)-free|IRLD014PbF|



## **ABSOLUTE MAXIMUM RATINGS** (T **A** = 25 °C, unless otherwise noted) 

|**ABSOLUTE MAXIMUM RATINGS**(T**A**= 25 °C,unless otherwise noted)|**ABSOLUTE MAXIMUM RATINGS**(T**A**= 25 °C,unless otherwise noted)|**ABSOLUTE MAXIMUM RATINGS**(T**A**= 25 °C,unless otherwise noted)|**ABSOLUTE MAXIMUM RATINGS**(T**A**= 25 °C,unless otherwise noted)|**ABSOLUTE MAXIMUM RATINGS**(T**A**= 25 °C,unless otherwise noted)|**ABSOLUTE MAXIMUM RATINGS**(T**A**= 25 °C,unless otherwise noted)|
|---|---|---|---|---|---|
|**PARAMETER**|||**SYMBOL**|**LIMIT**|**UNIT**|
|Drain-source voltage|||VDS|60|V|
|Gate-source voltage|||VGS|± 10||
|Continuous drain current|VGSat 5.0 V|TA= 25 °C|ID|1.7|A|
|||TA= 100 °C||1.2||
|Pulsed drain currenta|||IDM|14||
|Linear derating factor||||0.0083|W/°C|
|Single pulse avalanche energyb|||EAS|490|mJ|
|Maximum power dissipation|TA=|25 °C|PD|1.3|W|
|Peak diode recovery dV/dtc|||dV/dt|4.5|V/ns|
|Operating junction and storage temperature range|||TJ, Tstg|- 55 to + 175|°C|
|Soldering recommendations (peak temperature)|For|10 s||300d||



## **Notes** 

a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11) 

- b. VDD = 25 V, starting TJ = 25 °C, L = 197 mH, Rg = 25 Ω, IAS = 1.7 A (see fig. 12) 

- c. ISD ≤ 10 A, dI/dt ≤ 90 A/μs, VDD ≤ VDS, TJ ≤ 175 °C 

d. 1.6 mm from case 

S21-0886-Rev. E, 30-Aug-2021 

Document Number: 91307 

**1** 

For technical questions, contact: hvmos.techsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 

**IRLD014** 

www.vishay.com 

Vishay Siliconix 

## **THERMAL RESISTANCE RATINGS** 

|**THERMAL RESISTANCE RATINGS**|**THERMAL RESISTANCE RATINGS**|**THERMAL RESISTANCE RATINGS**|**THERMAL RESISTANCE RATINGS**|**THERMAL RESISTANCE RATINGS**|
|---|---|---|---|---|
|**PARAMETER**|**SYMBOL**|**TYP.**|**MAX.**|**UNIT**|
|Maximum Junction-to-Ambient|RthJA|-|120|°C/W|



|**SPECIFICATIONS**(T**J**= 25 °C,unless otherwise noted)|**SPECIFICATIONS**(T**J**= 25 °C,unless otherwise noted)|**SPECIFICATIONS**(T**J**= 25 °C,unless otherwise noted)|**SPECIFICATIONS**(T**J**= 25 °C,unless otherwise noted)|||||
|---|---|---|---|---|---|---|---|
|**PARAMETER**|**SYMBOL**|**TEST CONDITIONS**||**MIN.**|**TYP.**|**MAX.**|**UNIT**|
|**Static**||||||||
|Drain-Source Breakdown Voltage|VDS|VGS= 0 V, ID= 250 μA||60|-|-|V|
|VDSTemperature Coefficient|ΔVDS/TJ|Reference to 25 °C, ID= 1 mA||-|0.070|-|V/°C|
|Gate-Source Threshold Voltage|VGS(th)|VDS= VGS, ID= 250 μA||1.0|-|2.0|V|
|Gate-Source Leakage|IGSS|VGS= ± 10 V||-|-|± 100|nA|
|Zero Gate Voltage Drain Current|IDSS|VDS= 60 V, VGS= 0 V||-|-|25|μA|
|||VDS= 48 V, VGS= 0 V, TJ= 150 °C||-|-|250||
|Drain-Source On-State Resistance|RDS(on)|VGS= 5.0 V|ID= 1.0 Ab|-|-|0.20|Ω|
|||VGS= 4.0 V|ID= 0.85 Ab|-|-|0.28||
|Forward Transconductance|gfs|VDS= 25 V, ID= 1.0 Ab||1.9|-|-|S|
|**Dynamic**||||||||
|Input Capacitance|Ciss|VGS= 0 V<br>VDS= 25 V<br>f = 1.0 MHz, see fig. 5||-|400|-|pF|
|Output Capacitance|Coss|||-|170|-||
|Reverse Transfer Capacitance|Crss|||-|42|-||
|Total Gate Charge|Qg|VGS= 5.0 V|ID= 10 A, VDS= 48 V<br>see fig. 6 and 13b|-|-|8.4|nC|
|Gate-Source Charge|Qgs|||-|-|2.6||
|Gate-Drain Charge|Qgd|||-|-|6.4||
|Turn-On Delay Time|td(on)|VDD= 30 V, ID= 10 A<br>Rg= 12Ω, RD= 2.8Ω, see fig. 10b||-|9.3|-|ns|
|Rise Time|tr|||-|110|-||
|Turn-Off Delay Time|td(off)|||-|17|-||
|Fall Time|tf|||-|26|-||
|Internal Drain Inductance|LD|Between lead,<br>6 mm (0.25") from<br>package and center of<br>die contact<br>D<br>S<br>G||-|4.0|-|nH|
|Internal Source Inductance|LS|||-|6.0|-||
|**Drain-Source Body Diode Characteristics**||||||||
|Continuous Source-Drain Diode Current|IS|MOSFET symbol<br>showing the<br>integral reverse<br>p - n junction diode<br>S<br>D<br>G||-|-|1.7|A|
|Pulsed Diode Forward Currenta|ISM|||-|-|14||
|Body Diode Voltage|VSD|TJ= 25 °C, IS= 1.7 A, VGS= 0 Vb||-|-|1.6|V|
|Body Diode Reverse Recovery Time|trr|TJ= 25 °C, IF= 10 A, dI/dt = 100 A/μsb||-|93|130|ns|
|Body Diode Reverse Recovery Charge|Qrr|||-|0.34|0.65|μC|
|Forward Turn-On Time|ton|Intrinsic turn-on time is negligible (turn-on is dominated by LSand LD)||||||



## **Notes** 

a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11) 

b. Pulse width ≤ 300 μs; duty cycle ≤ 2 % 

S21-0886-Rev. E, 30-Aug-2021 

Document Number: 91307 

**2** 

For technical questions, contact: hvmos.techsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 

**IRLD014** Vishay Siliconix 

## www.vishay.com 

## **TYPICAL CHARACTERISTICS** (25 °C, unless otherwise noted) 

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20 μs PULSE WIDTH<br>TA = 25 °C<br>**----- End of picture text -----**<br>


**Fig. 1 - Typical Output Characteristics, TA = 25 °C** 

**Fig. 3 - Typical Transfer Characteristics** 

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20 μs PULSE WIDTH<br>TA = 175 °C<br>i eee<br>**----- End of picture text -----**<br>


**Fig. 2 - Typical Output Characteristics, TA = 175 °C** 

**Fig. 4 - Normalized On-Resistance vs. Temperature** 

S21-0886-Rev. E, 30-Aug-2021 

Document Number: 91307 

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For technical questions, contact: hvmos.techsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 

**IRLD014** Vishay Siliconix 

## www.vishay.com 

**Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage** 

**Fig. 7 - Typical Source-Drain Diode Forward Voltage** 

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| TA = 25 °C |<br>TJ = 175 °C 1ll<br>SINGLE PULSE<br>**----- End of picture text -----**<br>


**Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage** 

**Fig. 8 - Maximum Safe Operating Area** 

S21-0886-Rev. E, 30-Aug-2021 

Document Number: 91307 

**4** For technical questions, contact: hvmos.techsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 

**IRLD014** Vishay Siliconix 

www.vishay.com 

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RSS<br>CARAS<br>“CEETTTTT<br>Pett N<br>Pi ti tt tt yi<br>aePo tit50 5 tt tt25<br>TA, Ambient Temperature (°C) 100 125 150<br>, Drain Current (A)<br>ID<br>**----- End of picture text -----**<br>


**Fig. 9 - Maximum Drain Current vs. Ambient Temperature** 

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RD<br>VDS<br>VGS<br>D.U.T.<br>R<br>g +- VDD<br>10 V<br>Pulse width ≤ 1 µs<br>Duty factor ≤ 0.1 %<br>Fig. 10a - Switching Time Test Circuit<br>VDS<br>90 %<br>| |<br>Y<br>| |<br>10 % [\_|<br>VGS 14 a \<br>td(on) tr td(off) tf<br>**----- End of picture text -----**<br>


**Fig. 10b - Switching Time Waveforms** 

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th)Beeee eel ae aiia imeme a —_a@ea<br>Ss Sibecsssthlememe eames,een emeeee!git Stalll SES:RE<br>: sppSTreen etemauiEeesami Ee<br>roeee  iSEa2 ASeatreea SSMSSSS aeDSSHt THE<br>||<br>wo LUEV 2: "Fou *<br>10-5 1074 10-8 102 = 0.4 4<br>tt11, Rectangular Pulse Duration (s), Rectangular Pulse Duration (s)<br>)thJA<br>Thermal Response (Z<br>**----- End of picture text -----**<br>


**Fig. 11 - Maximum Effective Transient Thermal Impedance, Junction-to-Ambient** 

S21-0886-Rev. E, 30-Aug-2021 

Document Number: 91307 

**5** For technical questions, contact: hvmos.techsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 

**IRLD014** 

## www.vishay.com a ~~[OO]~~ 

## Vishay Siliconix 

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L<br>VDS<br>Vary tp to obtain<br>required IAS<br>Rg D.U.T. +<br>- [V][ DD]<br>VW IAS<br>10 V<br>+<br>t p 0.01 W<br>**----- End of picture text -----**<br>


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VDS<br>t<br>/* — p —S| VDD<br>VDS /N\\/ Z<br>/ |i<br>IAS an LHe<br>**----- End of picture text -----**<br>


**Fig. 12a - Unclamped Inductive Test Circuit** 

**Fig. 12b - Unclamped Inductive Waveforms** 

**Fig. 12c - Maximum Avalanche Energy vs. Drain Current** 

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Current regulator<br>Same type as D.U.T.<br>QG 50 kΩ<br>VGS 12 V 0.2 µF<br>0.3 µF<br>QGS QGD +<br>D.U.T. - VDS<br>VG VGS<br>| 74 a<br>3 mA<br>Charge o rs<br>IG ID<br>Current sampling resistors<br>Fig. 13a - Basic Gate Charge Waveform Fig. 13b - Gate Charge Test Circuit<br>**----- End of picture text -----**<br>


Document Number: 91307 

S21-0886-Rev. E, 30-Aug-2021 

**6** 

For technical questions, contact: hvmos.techsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 

**IRLD014** 

Vishay Siliconix 

**==> picture [77 x 10] intentionally omitted <==**

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www.vishay.com<br>**----- End of picture text -----**<br>


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Peak Diode Recovery dV/dt Test Circuit<br>+ Circuit layout considerations<br>D.U.T.<br>•  Low stray inductance<br>•  Ground plane<br>•  Low leakage inductance<br>current transformer<br>-<br>+<br>- - +<br>Rg •  dV/dt controlled by Rg +<br>••   Driver same type as D.U.T.ISD controlled by duty factor “D” - VDD<br>•  D.U.T. - device under test<br>Driver gate drive<br>Period D = P.W.<br>P.W. Period<br>VGS = 10 V [a]<br>D.U.T. lSD waveform<br>Reverse<br>recovery Body diode forward<br>current current dI/dt<br>D.U.T. VDS waveform Diode recovery<br>dV/dt<br>VDD<br>Re-applied<br>voltage<br>Body diode forward drop<br>Inductor current<br>Ripple ≤ 5 % ISD<br>Note<br>a. VGS = 5 V for logic level devices<br>**----- End of picture text -----**<br>


**Fig. 14 - For N-Channel** 

_Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?91307._ 

Document Number: 91307 

S21-0886-Rev. E, 30-Aug-2021 

**7** 

For technical questions, contact: hvmos.techsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 

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Revision: 09-Jul-2021 

Document Number: 91000 

**1**