IRFU120PBF

**IRFR120, IRFU120, SiHFR120, SiHFU120** 

www.vishay.com 

## Vishay Siliconix 

## **Power MOSFET** 

**==> picture [195 x 96] intentionally omitted <==**

**----- Start of picture text -----**<br>
D<br>DPAK IPAK<br>(TO-252) (TO-251)<br>D<br>D<br>G<br>S<br>G [S]<br>G [D] S<br>**----- End of picture text -----**<br>


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N-Channel MOSFET<br>**----- End of picture text -----**<br>


## **FEATURES** 

- Dynamic dV/dt rating 

- Repetitive avalanche rated 

- Surface-mount (IRFR120, SiHFR120) 

- Straight lead (IRFU120, SiHFU120) 

- Available in tape and reel 

Available 

- Fast switching 

- Ease of paralleling 

- Material categorization: for definitions of compliance please see www.vishay.com/doc?99912 

## **DESCRIPTION** 

## **PRODUCT SUMMARY** 

|**PRODUCT SUMMARY**|**PRODUCT SUMMARY**|**PRODUCT SUMMARY**|
|---|---|---|
|VDS(V)|100||
|RDS(on)(Ω)|VGS= 10 V|0.27|
|Qgmax. (nC)|16||
|Qgs(nC)|4.4||
|Qgd(nC)|7.7||
|Configuration|Single||



Third generation power MOSFETs from Vishay provide the designer with the best combination of fast switching, ruggedized device design, low on-resistance and cost-effectiveness. 

The DPAK is designed for surface mounting using vapor phase, infrared, or wave soldering techniques. The straight lead version (IRFU, SiHFU series) is for through-hole mounting applications. Power dissipation levels up to 1.5 W are possible in typical surface mount applications. 

## **ORDERING INFORMATION** 

|**ORDERING INFORMATION**|**ORDERING INFORMATION**|**ORDERING INFORMATION**|**ORDERING INFORMATION**|**ORDERING INFORMATION**|**ORDERING INFORMATION**|
|---|---|---|---|---|---|
|**PACKAGE**|**DPAK (TO-252)**|**DPAK (TO-252)**|**DPAK (TO-252)**|**DPAK (TO-252)**|**IPAK (TO-251)**|
|Lead (Pb)-free<br>and halogen-free<br>|SiHFR120-GE3|SiHFR120TR-GE3a|SiHFR120TRR-GE3a|SiHFR120TRL-GE3a|SiHFU120-GE3|
||IRFR120PbF-BE3<br>b|IRFR120TRPbF-BE3<br>ab|IRFR120TRRPbF-BE3<br>ab|IRFR120TRLPbF-BE3<br>ab|-|
|Lead (Pb)-free<br>|IRFR120PbF|IRFR120TRPbFa|IRFR120TRRPbFa|IRFR120TRLPbFa|IRFU120PbF|



## **Notes** 

a. See device orientation 

b. “-BE3” denotes alternate manufacturing location 

|**ABSOLUTE MAXIMUM RATINGS**(TC= 25 °C, unless otherwise noted)|**ABSOLUTE MAXIMUM RATINGS**(TC= 25 °C, unless otherwise noted)|**ABSOLUTE MAXIMUM RATINGS**(TC= 25 °C, unless otherwise noted)|**ABSOLUTE MAXIMUM RATINGS**(TC= 25 °C, unless otherwise noted)|||
|---|---|---|---|---|---|
|**PARAMETER**|||**SYMBOL**|**LIMIT**|**UNIT**|
|Drain-source voltage|||VDS|100|V|
|Gate-source voltage|||VGS|± 20||
|Continuous drain current|VGSat 10 V|TC= 25 °C|ID|7.7|A|
|||TC= 100 °C||4.9||
|Pulsed drain currenta|||IDM|31||
|Linear deratingfactor||||0.33|W/°C|
|Linear deratingfactor(PCB mount)e||||0.020||
|Singlepulse avalanche energyb|||EAS|210|mJ|
|Repetitive avalanche Currenta|||IAR|7.7|A|
|Repetitive avalanche Energya|||EAR|4.2|mJ|
|Maximumpower dissipation|TC=|25 °C|PD|42|W|
|Maximumpower dissipation(PCB mount)e|TA=|25 °C||2.5||
|Peak diode recoverydV/dtc|||dV/dt|5.5|V/ns|
|Operating junction and storage temperature range|||TJ,Tstg|-55 to +150|°C|
|Solderingrecommendations(peak temperature) d|for|10 s||260||



## **Notes** 

a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11). 

b. VDD = 25 V, starting TJ = 25 °C, L = 5.3 mH, Rg = 25 Ω, IAS = 7.7 A (see fig. 12). 

c. ISD ≤ 9.2 A, dI/dt ≤ 110 A/μs, VDD ≤ VDS, TJ ≤ 150 °C. 

d. 1.6 mm from case. 

e. When mounted on 1" square PCB (FR-4 or G-10 material). 

S21-0466-Rev. D, 17-May-2021 

Document Number: 91266 

**1** 

For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 

**IRFR120, IRFU120, SiHFR120, SiHFU120** 

Vishay Siliconix 

www.vishay.com 

|**THERMAL RESISTANCE RATINGS**|**THERMAL RESISTANCE RATINGS**|**THERMAL RESISTANCE RATINGS**|**THERMAL RESISTANCE RATINGS**|**THERMAL RESISTANCE RATINGS**|**THERMAL RESISTANCE RATINGS**|
|---|---|---|---|---|---|
|**PARAMETER**|**SYMBOL**|**MIN.**|**TYP.**|**MAX.**|**UNIT**|
|Maximum junction-to-ambient|RthJA|-|-|110|°C/W|
|Maximum junction-to-ambient (PCB mount)a|RthJA|-|-|50||
|Maximum junction-to-case (drain)|RthJC|-|-|3.0||



## **Note** 

a. When mounted on 1" square PCB (FR-4 or G-10 material). 

|**SPECIFICATIONS**(TJ= 25 °C, unless otherwise noted)|**SPECIFICATIONS**(TJ= 25 °C, unless otherwise noted)|**SPECIFICATIONS**(TJ= 25 °C, unless otherwise noted)|**SPECIFICATIONS**(TJ= 25 °C, unless otherwise noted)|||||
|---|---|---|---|---|---|---|---|
|**PARAMETER**|**SYMBOL**|**TEST CONDITIONS**||**MIN.**|**TYP.**|**MAX.**|**UNIT**|
|**Static**||||||||
|Drain-source breakdown voltage|VDS|VGS= 0 V, ID= 250 μA||100|-|-|V|
|VDStemperature coefficient|ΔVDS/TJ|Reference to 25 °C, ID= 1 mA||-|0.13|-|V/°C|
|Gate-source threshold voltage|VGS(th)|VDS= VGS, ID= 250 μA||2.0|-|4.0|V|
|Gate-source leakage|IGSS|VGS= ± 20 V||-|-|± 100|nA|
|Zero gate voltage drain current|IDSS|VDS= 100 V, VGS= 0 V||-|-|25|μA|
|||VDS= 80 V, VGS= 0 V, TJ= 125 °C||-|-|250||
|Drain-source on-state resistance|RDS(on)|VGS= 10 V|ID= 4.6 Ab|-|-|0.27|Ω|
|Forward transconductance|gfs|VDS= 50 V, ID= 4.6 A||1.6|-|-|S|
|**Dynamic**||||||||
|Input capacitance|Ciss|VGS= 0 V,<br>VDS= 25 V,<br>f = 1.0 MHz, see fig. 5||-|360|-|pF|
|Output capacitance|Coss|||-|150|-||
|Reverse transfer capacitance|Crss|||-|34|-||
|Totalgate charge|Qg|VGS= 10 V|ID= 9.2 A, VDS= 80 V,<br>see fig. 6 and 13b|-|-|16|nC|
|Gate-source charge|Qgs|||-|-|4.4||
|Gate-drain charge|Qgd|||-|-|7.7||
|Turn-on delay time|td(on)|VDD= 50 V, ID= 9.2 A,<br>Rg= 18Ω, RD= 5.2Ω, see fig. 10b||-|6.8|-|ns|
|Rise time|tr|||-|27|-||
|Turn-off delay time|td(off)|||-|18|-||
|Fall time|tf|||-|17|-||
|Internal drain inductance|Rg|f = 1 MHz, open drain||1.0|-|5.0|Ω|
|Internal source inductance|LD|Between lead,<br>6 mm (0.25") from<br>package and center of<br>die contact<br>D<br>S<br>G||-|4.5|-|nH|
|Input capacitance|LS|||-|7.5|-||
|**Drain-source body diode characteristics**||||||||
|Continuous source-drain diode current|IS|MOSFET symbol<br>showing the<br>integral reverse<br>p - n junction diode<br>S<br>D<br>G||-|-|7.7|A|
|Pulsed diode forward currenta|ISM|||-|-|31||
|Body diode voltage|VSD|TJ= 25 °C, IS= 7.7 A, VGS= 0 Vb||-|-|2.5|V|
|Body diode reverse recovery time|trr|TJ= 25 °C, IF= 9.2 A, dI/dt = 100 A/μsb||-|130|260|ns|
|Body diode reverse recovery charge|Qrr|||-|0.65|1.3|μC|
|Forward turn-on time|ton|Intrinsic turn-on time is negligible (turn-on is dominated by LSand LD)||||||



## **Notes** 

a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11). 

b. Pulse width ≤ 300 μs; duty cycle ≤ 2 %. 

S21-0466-Rev. D, 17-May-2021 

Document Number: 91266 

**2** 

For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 

**IRFR120, IRFU120, SiHFR120, SiHFU120** Vishay Siliconix 

## www.vishay.com 

## **TYPICAL CHARACTERISTICS** (25 °C, unless otherwise noted) 

**Fig. 1 -  Typical Output Characteristics, TC = 25 °C** 

**Fig. 2 - Typical Output Characteristics, TC = 150 °C** 

**Fig. 3 - Typical Transfer Characteristics** 

**Fig. 4 - Normalized On-Resistance vs. Temperature** 

S21-0466-Rev. D, 17-May-2021 

Document Number: 91266 

**3** For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 

**IRFR120, IRFU120, SiHFR120, SiHFU120** Vishay Siliconix 

**==> picture [77 x 10] intentionally omitted <==**

**----- Start of picture text -----**<br>
www.vishay.com<br>**----- End of picture text -----**<br>


**Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage** 

**Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage** 

**Fig. 7 - Typical Source-Drain Diode Forward Voltage** 

**Fig. 8 - Maximum Safe Operating Area** 

S21-0466-Rev. D, 17-May-2021 

Document Number: 91266 

**4** For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 

**IRFR120, IRFU120, SiHFR120, SiHFU120** 

## www.vishay.com 

## Vishay Siliconix 

**==> picture [148 x 223] intentionally omitted <==**

**----- Start of picture text -----**<br>
RD<br>VDS<br>VGS<br>D.U.T.<br>R<br>g +- VDD<br>10 V<br>Pulse width ≤ 1 µs<br>Duty factor ≤ 0.1 %<br>tr<br>Fig. 10a - Switching Time Test Circuit<br>VDS<br>90 %<br>‘<br>1<br>| \/ 1|<br>10 %VGS aa) \ if T e/\ o rH \i<br>td(on) tr td(off) tf<br>**----- End of picture text -----**<br>


**Fig. 9 - Maximum Drain Current vs. Case Temperature** 

**Fig. 10b - Switching Time Waveforms** 

**Fig. 11 - Maximum Effective Transient Thermal Impedance, Junction-to-Case** 

S21-0466-Rev. D, 17-May-2021 

Document Number: 91266 

**5** For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 

**==> picture [506 x 165] intentionally omitted <==**

**----- Start of picture text -----**<br>
IRFR120, IRFU120, SiHFR120, SiHFU120<br>www.vishay.com Vishay Siliconix<br>a a<br>L<br>VDS VDS<br>required IVary tp to obtainAS /— tp —— VDD<br>Rg D.U.T +<br>- [V][ DD] VDS<br>IAS /A\<br>2 10 V \ le<br>ft<br>t p 0.01 Ω IAS —~_e Le<br>**----- End of picture text -----**<br>


**Fig. 12a - Unclamped Inductive Test Circuit** 

**Fig. 12b - Unclamped Inductive Waveforms** 

**Fig. 12c - Maximum Avalanche Energy vs. Drain Current** 

**==> picture [415 x 163] intentionally omitted <==**

**----- Start of picture text -----**<br>
Current regulator<br>Same type as D.U.T.<br>QG 50 kΩ<br>VGS 12 V 0.2 µF<br>0.3 µF<br>QGS QGD +<br>D.U.T. - VDS<br>VG VGS<br>rs Sint 3 mA he|<br>Charge — D m<br>IG ID<br>Current sampling resistors<br>Fig. 13a - Basic Gate Charge Waveform Fig. 13b - Gate Charge Test Circuit<br>**----- End of picture text -----**<br>


S21-0466-Rev. D, 17-May-2021 

Document Number: 91266 

**6** For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 

**IRFR120, IRFU120, SiHFR120, SiHFU120** 

Vishay Siliconix 

**==> picture [77 x 10] intentionally omitted <==**

**----- Start of picture text -----**<br>
www.vishay.com<br>**----- End of picture text -----**<br>


## **Peak Diode Recovery dV/dt Test Circuit** 

**==> picture [284 x 462] intentionally omitted <==**

**----- Start of picture text -----**<br>
+ Circuit layout considerations<br>D.U.T.<br>•  Low stray inductance<br>•  Ground plane<br>•  Low leakage inductance<br>current transformer<br>-<br>+<br>- - +<br>Rg •  dV/dt controlled by Rg +<br>••   Driver same type as D.U.T.ISD controlled by duty factor “D” - VDD<br>•  D.U.T. - device under test<br>Driver gate drive<br>Period D = P.W.<br>P.W. Period<br>VGS = 10 V [a]<br>D.U.T. lSD waveform<br>Reverse<br>recovery Body diode forward<br>current current dI/dt<br>D.U.T. VDS waveform Diode recovery<br>dV/dt<br>VDD<br>Re-applied<br>voltage<br>Body diode forward drop<br>Inductor current<br>Ripple ≤ 5 % ISD<br>Note<br>a. VGS = 5 V for logic level devices<br>**----- End of picture text -----**<br>


**Fig. 14 - For N-Channel** 

_Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?91266._ 

Document Number: 91266 

S21-0466-Rev. D, 17-May-2021 

**7** 

For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 

**Package Information** 

Vishay Siliconix 

**==> picture [59 x 48] intentionally omitted <==**

www.vishay.com 

## **TO-252AA Case Outline** 

## **VERSION 1: FACILITY CODE = Y** 

**==> picture [364 x 211] intentionally omitted <==**

**----- Start of picture text -----**<br>
E A<br>C2<br>b3<br>E1<br>b b2 C<br>e<br>A1<br>e1<br>L3<br>D1<br>D<br>H<br>L4<br>L5 L<br>gage plane height (0.5 mm)<br>**----- End of picture text -----**<br>


|b|b2<br>e1<br>gage plane height (0.5 mm)<br>e|b2<br>e1<br>gage plane height (0.5 mm)<br>e|
|---|---|---|
||**MILLIMETERS**||
|**DIM.**|**MIN.**|**MAX.**|
|A|2.18|2.38|
|A1|-|0.127|
|b|0.64|0.88|
|b2|0.76|1.14|
|b3|4.95|5.46|
|C|0.46|0.61|
|C2|0.46|0.89|
|D|5.97|6.22|
|D1|4.10|-|
|E|6.35|6.73|
|E1|4.32|-|
|H|9.40|10.41|
|e|2.28 BSC||
|e1|4.56 BSC||
|L|1.40|1.78|
|L3|0.89|1.27|
|L4|-|1.02|
|L5|1.01|1.52|



## **Note** 

- Dimension L3 is for reference only 

Revision: 16-Dec-2019 

Document Number: 71197 

**1** For technical questions, contact: pmostechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 

**Package Information** 

Vishay Siliconix 

**==> picture [59 x 48] intentionally omitted <==**

www.vishay.com 

## **VERSION 2: FACILITY CODE = N** 

**==> picture [338 x 254] intentionally omitted <==**

**----- Start of picture text -----**<br>
e<br>E A<br>b3<br>E1<br>e c2 E1/2<br>2x b2<br>2x e 3x b 0.25 C A B DETAIL "B" (b)<br>H<br>C<br>b1<br>GAUGE<br>PLANE SEATING DETAIL "B"<br>C C<br>L PLANE<br>(L1)<br>(3°) (3°)<br>θ<br>θ<br>L3 D1<br>D<br>H<br>L6<br>L5<br>L4<br>c<br>c1<br>L2 A1<br>θ<br>**----- End of picture text -----**<br>


||**MILLIMETERS**|**MILLIMETERS**|
|---|---|---|
|**DIM.**|**MIN.**|**MAX.**|
|A|2.18|2.39|
|A1|-|0.13|
|b|0.65|0.89|
|b1|0.64|0.79|
|b2|0.76|1.13|
|b3|4.95|5.46|
|c|0.46|0.61|
|c1|0.41|0.56|
|c2|0.46|0.60|
|D|5.97|6.22|
|D1|5.21|-|
|E|6.35|6.73|
|E1|4.32|-|
|e|2.29 BSC||
|H|9.94|10.34|



||**MILLIMETERS**|**MILLIMETERS**|
|---|---|---|
|**DIM.**|**MIN.**|**MAX.**|
|L|1.50|1.78|
|L1|2.74 ref.||
|L2|0.51 BSC||
|L3|0.89|1.27|
|L4|-|1.02|
|L5|1.14|1.49|
|L6|0.65|0.85|
||0°|10°|
|1|0°|15°|
|2|25°|35°|



## **Notes** 

- Dimensioning and tolerance confirm to ASME Y14.5M-1994 

- All dimensions are in millimeters. Angles are in degrees 

- Heat sink side flash is max. 0.8 mm 

- Radius on terminal is optional 

ECN: E19-0649-Rev. Q, 16-Dec-2019 DWG: 5347 

Revision: 16-Dec-2019 

Document Number: 71197 

**2** 

For technical questions, contact: pmostechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 

**Package Information** Vishay Siliconix 

www.vishay.com 

## **Case Outline for TO-251AA (High Voltage)** 

## **OPTION 1:** 

**==> picture [378 x 278] intentionally omitted <==**

**----- Start of picture text -----**<br>
4 3 A<br>E1 Thermal PAD E A<br>4<br>b4 0.010 0.25 M C A B c2<br>L2 4 A<br>θ2 θ1<br>D1 4<br>B<br>C<br>3<br>Seating<br>5 plane<br>L1 L3 C C<br>(Datum A)<br>L<br>B B<br>A<br>A1<br>3  x b2<br>c<br>3 x b<br>View A - A 2 x e 0.010 0.25 M C A B<br>Base<br>5 metal<br>Plating<br>b1, b3<br>Lead tip<br>(c) c1 5<br>( b, b2)<br>Section B - B and C - C<br>D<br>**----- End of picture text -----**<br>


||**MILLIMETERS**|**MILLIMETERS**|**INCHES**|**INCHES**||**MILLIMETERS**<br>**INCHES**<br>**DIM.**<br>**MIN.**<br>**MAX.**<br>**MIN.**<br>**MAX.**<br>D1<br>5.21<br>-<br>0.205<br>-<br>E<br>6.35<br>6.73<br>0.250<br>0.265<br>E1<br>4.32<br>-<br>0.170<br>-<br>e<br>2.29 BSC<br>2.29 BSC<br>L<br>8.89<br>9.65<br>0.350<br>0.380<br>L1<br>1.91<br>2.29<br>0.075<br>0.090<br>L2<br>0.89<br>1.27<br>0.035<br>0.050<br>L3<br>1.14<br>1.52<br>0.045<br>0.060<br>θ1<br>0'<br>15'<br>0'<br>15'<br>θ2<br>25'<br>35'<br>25'<br>35'|**MILLIMETERS**|**MILLIMETERS**|**INCHES**|**INCHES**|
|---|---|---|---|---|---|---|---|---|---|---|
|**DIM.**|**MIN.**|**MAX.**|**MIN.**|**MAX.**|||**MIN.**|**MAX.**|**MIN.**|**MAX.**|
|A|2.18|2.39|0.086|0.094|||5.21|-|0.205|-|
|A1|0.89|1.14|0.035|0.045|||6.35|6.73|0.250|0.265|
|b|0.64|0.89|0.025|0.035|||4.32|-|0.170|-|
|b1|0.65|0.79|0.026|0.031|||2.29 BSC||2.29 BSC||
|b2|0.76|1.14|0.030|0.045|||8.89|9.65|0.350|0.380|
|b3|0.76|1.04|0.030|0.041|||1.91|2.29|0.075|0.090|
|b4|4.95|5.46|0.195|0.215|||0.89|1.27|0.035|0.050|
|c|0.46|0.61|0.018|0.024|||1.14|1.52|0.045|0.060|
|c1|0.41|0.56|0.016|0.022|||0'|15'|0'|15'|
|c2|0.46|0.86|0.018|0.034|||25'|35'|25'|35'|
|D|5.97|6.22|0.235|0.245|||||||
|ECN: E21-0605-Rev. B, 25-Oct-2021<br>DWG: 5968|||||||||||
||||||||||||



## **Notes** 

- Dimensioning and tolerancing per ASME Y14.5M-1994 

- Dimension are shown in inches and millimeters 

- Dimension D and E do not include mold flash. Mold flash shall not exceed 0.13 mm (0.005") per side. These dimensions are measured at the outermost extremes of the plastic body 

- Thermal pad contour optional with dimensions b4, L2, E1 and D1 

- Lead dimension uncontrolled in L3 

- Dimension b1, b3 and c1 apply to base metal only 

- Outline conforms to JEDEC[®] outline TO-251AA 

Revision: 25-Oct-2021 

Document Number: 91362 

**1** 

For technical questions, contact: hvmos.techsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 

**Package Information** 

Vishay Siliconix 

**==> picture [77 x 10] intentionally omitted <==**

**----- Start of picture text -----**<br>
www.vishay.com<br>**----- End of picture text -----**<br>


## **OPTION 2: FACILITY CODE = N** 

|Ø 1.00<br>x 0.10 deep<br>L2<br>L4<br>L3|Ø 1.00<br>x 0.10 deep<br>L2<br>L4<br>L3|L2||E<br>b4<br>CL|E<br>b4<br>CL|E<br>b4<br>CL||D<br>L1<br>C<br>B<br>L|θ1<br><br>θ1|θ1<br><br>θ1|θ1<br><br>θ1|||A1<br>D1<br>Third angle<br>projection|||||||c1<br>D2|c1<br>D2|c1<br>D2|
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|||||||||||||||||||||||||
|||||||||||θ1||c|A<br>2|A1||||||||||
||||||||||||||||D1||E1|||||||
|||||||||||||||||||||||||
|||||||||||||||||||||||D2||
|||||||||||θ1||||||||||||||
|||||||||||||||||||||||||
|||||||||||||||||||||||||
|||L4||||||||||||||||||||||
|||||b2<br>b<br>e<br>C<br>B||||||||||||||||||||
|||L3||||||||||||||||||||||
|||||||||||||||||||||||||
|||||||||||||||||||||||||
||||||||||||||c|||c|b1, b3<br>b, b2<br><br>Section “B-B” a|||nd “C-C”||||
||||||e|||||||||||||||||||
|||||||||θ2||||||||||||||||
|||||||||||||||||||||||||
|||||||||||||||||||||||||
|||||||||||||||||||||||||
|**DIM.**|||**MIN.**|||**MAX.**||**MAX.**||||||**DIM.**|||**MIN.**|||**MAX.**|||**MAX.**|
|A|||2.180|||2.285||2.390||||||D2|||5.380|||-|||-|
|A1|||0.890|||1.015||1.140||||||E|||6.350|||6.540|||6.730|
|b|||0.640|||0.765||0.890||||||E1|||4.32|||-|||-|
|b1|||0.640|||0.715||0.790||||||e|||2.29 BSC|||||||
|b2|||0.760|||0.950||1.140||||||L|||8.890||9.270||||9.650|
|b3|||0.760|||0.900||1.040||||||L1|||1.910||2.100||||2.290|
|b4|||4.950|||5.205||5.460||||||L2|||0.890||1.080||||1.270|
|c|||0.460|||-||0.610||||||L3|||1.140||1.330||||1.520|
|c1|||0.410|||-||0.560||||||L4|||1.300||1.400||||1.500|
|c2|||0.460|||-||0.610||||||θ1|||0°||7.5°||||15°|
|D|||5.970|||6.095||6.220||||||θ2|||4°||-||||-|
|D1|||4.300|||-||-||||||||||||||||
|ECN: E21-0605-Rev. B, 25-Oct-2021<br>DWG: 5968||||||||||||||||||||||||
|||||||||||||||||||||||||



## **Notes** 

- Dimensioning and tolerancing per ASME Y14.5M-1994 

- All dimension are in millimeters, angles are in degrees 

- Heat sink side flash is max. 0.8 mm 

Revision: 25-Oct-2021 

Document Number: 91362 

**2** 

For technical questions, contact: hvmos.techsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 

**Application Note 826** 

**==> picture [60 x 50] intentionally omitted <==**

## Vishay Siliconix 

## **RECOMMENDED MINIMUM PADS FOR DPAK (TO-252)** 

**==> picture [203 x 287] intentionally omitted <==**

**----- Start of picture text -----**<br>
0.224<br>(5.690)<br>0.180 0.055<br>(4.572) (1.397)<br>0.243 (6.180)<br>0.420<br>(10.668)<br>0.087 (2.202)<br>0.090 (2.286)<br>**----- End of picture text -----**<br>


Recommended Minimum Pads Dimensions in Inches/(mm) 

> Return to Index Return to Index 

Document Number: 72594 Revision: 21-Jan-08 

www.vishay.com 

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