IRFS11N50APBF

**IRFS11N50A, SiHFS11N50A** 

www.vishay.com 

## Vishay Siliconix 

## **Power MOSFET** 

|**PRODUCT SUMMARY**|**PRODUCT SUMMARY**|**PRODUCT SUMMARY**|
|---|---|---|
|VDS(V)|500||
|RDS(on)()|VGS= 10 V|0.52|
|Qg(Max.) (nC)|52||
|g<br>Qgs(nC)|13||
|Qgd(nC)|18||
|Configuration|Single||



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D<br>D [2] PAK (TO-263)<br>G<br>G D<br>S<br>S<br>N-Channel MOSFET<br>**----- End of picture text -----**<br>


## **FEATURES** 

- Low Gate Charge Qg results in Simple Drive Requirement 

- Improved Gate, Avalanche and Dynamic dV/dt Available Ruggedness 

- • Fully Characterized Capacitance and Available Avalanche Voltage and Current 

- Effective Coss Specified 

- Material categorization: For definitions of compliance please see www.vishay.com/doc?99912 

**Note** 

- This    datasheet    provides    information    about    parts    that    are RoHS-compliant  and/or  parts  that  are  non-RoHS-compliant.  For example, parts with lead (Pb) terminations are not RoHS-compliant. Please see the information/tables in this datasheet for details. 

## **APPLICATIONS** 

- Switch Mode Power Supply (SMPS) 

- Uninterruptible Power Supply 

- High Speed Power Switching 

## **TYPICAL SMPS TOPOLOGIES** 

- Two Transistor Forward 

- Half and Full Bridge 

- Power Factor Correction Boost 

|**ORDERING INFORMATION**|**ORDERING INFORMATION**|**ORDERING INFORMATION**|**ORDERING INFORMATION**|
|---|---|---|---|
|Package|D2PAK (TO-263)|D2PAK (TO-263)|D2PAK (TO-263)|
|Lead (Pb)-free and Halogen-free|SiHFS11N50A-GE3|SiHFS11N50ATRR-GE3a|SiHFS11N50ATRL-GE3a|
|Lead (Pb)-free|IRFS11N50APbF|IRFS11N50ATRRPa|IRFS11N50ATRLPa|



## **Note** 

a. See device orientation. 

~~Ce~~ **ABSOLUTE MAXIMUM RATINGS** (TC = 25 °C, unless otherwise noted) ~~GG~~ **PARAMETER SYMBOL LIMIT UNIT** ~~SH~~ Drain-Source Voltage VDS 500 V Gate-Source Voltage VGS ± 30 TC = 25 °C 11 Continuous Drain Current VGS at 10 V ID TC = 100 °C 7.0 A ~~a~~ Pulsed Drain Current[a] IDM 44 ~~a~~ Linear Derating Factor 1.3 W/°C ~~**a**~~ Single Pulse Avalanche Energy[b] EAS 275 mJ ~~a~~ Repetitive Avalanche Current[a] IAR 11 A ~~GO~~ Repetitive Avalanche Energy[a] EAR 17 mJ ~~eG~~ Maximum Power Dissipation TC = 25 °C PD 170 W ~~GG~~ Peak Diode Recovery dV/dt[c] dV/dt 6.9 V/ns Operating Junction and Storage Temperature Range TJ, Tstg - 55 to + 150 °C ~~a~~ Soldering Recommendations (Peak Temperature)[d] for 10 s ~~oe~~ 300 **Notes** 

a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11). b. Starting TJ = 25 °C, L = 4.5 mH, Rg = 25  , IAS = 11 A (see fig. 12). 

c. ISD  11 A, dI/dt  140 A/μs, VDD  VDS, TJ  150 °C. 

d. 1.6 mm from case. 

S13-1927-Rev. E, 09-Sep-13 

Document Number: 91286 

**1** 

For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 

**IRFS11N50A, SiHFS11N50A** 

Vishay Siliconix 

**==> picture [59 x 48] intentionally omitted <==**

www.vishay.com 

## **THERMAL RESISTANCE RATINGS** 

|**THERMAL RESISTANCE RATINGS**|**THERMAL RESISTANCE RATINGS**|**THERMAL RESISTANCE RATINGS**|**THERMAL RESISTANCE RATINGS**|**THERMAL RESISTANCE RATINGS**|
|---|---|---|---|---|
|**PARAMETER**|**SYMBOL**|**TYP.**|**MAX.**|**UNIT**|
|Maximum Junction-to-Case (Drain)|RthJC|-|0.75|°C/W|
|Case-to-Sink, Flat, Greased Surface|RthCS|0.50|-||
|Maximum Junction-to-Ambient|RthJA|-|62||



|**SPECIFICATIONS**(TJ= 25 °C, unless otherwise noted)|**SPECIFICATIONS**(TJ= 25 °C, unless otherwise noted)|**SPECIFICATIONS**(TJ= 25 °C, unless otherwise noted)|**SPECIFICATIONS**(TJ= 25 °C, unless otherwise noted)|||||
|---|---|---|---|---|---|---|---|
|**PARAMETER**|**SYMBOL**|**TEST CONDITIONS**||**MIN.**|**TYP.**|**MAX.**|**UNIT**|
|**Static**||||||||
|Drain-Source Breakdown Voltage|VDS|VGS= 0, ID= 250 μA||500|-|-|V|
|VDSTemperature Coefficient|VDS/TJ|Reference to 25 °C, ID= 1 mA||-|0.060|-|V/°C|
|Gate-Source Threshold Voltage|VGS(th)|VDS= VGS, ID= 250 μA||2.0|-|4.0|V|
|Gate-Source Leakage|IGSS|VGS= ± 30 V||-|-|± 100|nA|
|Zero Gate Voltage Drain Current|IDSS|VDS= 500 V, VGS= 0 V||-|-|25|μA|
|||VDS= 400 V, VGS= 0 V, TJ= 125 °C||-|-|250||
|Drain-Source On-State Resistance|RDS(on)|VGS= 10 V|ID= 6.6 Ab|-|-|0.52||
|Forward Transconductance|gfs|VDS= 50 V, ID= 6.6 A||6.1|-|-|S|
|**Dynamic**||||||||
|Input Capacitance|Ciss|VGS= 0 V,<br>VDS= 25 V,<br>f = 1.0 MHz, see fig. 5||-|1423|-|pF|
|Output Capacitance|Coss|||-|208|-||
|Reverse Transfer Capacitance|Crss|||-|8.1|-||
|Output Capacitance|Coss|VGS= 0 V|VDS= 1.0 V, f = 1.0 MHz|-|2000|-||
||||VDS= 400 V, f = 1.0 MHz|-|55|-||
|Effective Output Capacitance|Cosseff.||VDS= 0 V to 400 Vc|-|97|-||
|Total Gate Charge|Qg|VGS= 10 V|ID= 11 A, VDS= 400 V<br>see fig. 6 and 13b|-|-|52|nC|
|Gate-Source Charge|Qgs|||-|-|13||
|Gate-Drain Charge|Qgd|||-|-|18||
|Turn-On Delay Time|td(on)|VDD <br>Rg=|= 250 V, ID= 11 A<br>9.1, RD= 22<br>see fig. 10b|-|14|-|ns|
|Rise Time|tr|||-|35|-||
|Turn-Off Delay Time|td(off)|||-|32|-||
|Fall Time|tf|||-|28|-||
|**Drain-Source Body Diode Characteristics**||||||||
|Continuous Source-Drain Diode Current|IS|MOSFET symbol<br>showing the<br>integral reverse<br>p - n junction diode<br>S<br>D<br>G||-|-|11|A|
|Pulsed Diode Forward Currenta|ISM|||-|-|44||
|Body Diode Voltage|VSD|TJ= 25 °C, IS= 11 A, VGS= 0 Vb||-|-|1.5|V|
|Body Diode Reverse Recovery Time|trr|TJ= 25 °C, IF= 11 A, dI/dt = 100 A/μsb||-|510|770|ns|
|Body Diode Reverse Recovery Charge|Qrr|||-|3.4|5.1|μC|
|Forward Turn-On Time|ton|Intrinsic turn-on time is negligible (turn-on is dominated by LSand LD)||||||



## **Notes** 

a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11). 

b. Pulse width  300 μs; duty cycle  2 %. 

c. Coss eff. is a fixed capacitance that gives the same charging time as Coss while VDS is rising fom 0 % VDS to 80 % VDS. 

S13-1927-Rev. E, 09-Sep-13 

Document Number: 91286 

**2** 

For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 

**IRFS11N50A, SiHFS11N50A** Vishay Siliconix 

## www.vishay.com 

## **TYPICAL CHARACTERISTICS** (25 °C, unless otherwise noted) 

**Fig. 1 - Typical Output Characteristics** 

**Fig. 2 - Typical Output Characteristics** 

**Fig. 3 - Typical Transfer Characteristics** 

**Fig. 4 - Normalized On-Resistance vs. Temperature** 

S13-1927-Rev. E, 09-Sep-13 

Document Number: 91286 

**3** 

For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 

**IRFS11N50A, SiHFS11N50A** Vishay Siliconix 

www.vishay.com 

**Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage** 

**Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage** 

**Fig. 7 - Typical Source-Drain Diode Forward Voltage** 

**Fig. 8 - Maximum Safe Operating Area** 

S13-1927-Rev. E, 09-Sep-13 

Document Number: 91286 

**4** For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 

**IRFS11N50A, SiHFS11N50A** 

## www.vishay.com 

## Vishay Siliconix 

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RD<br>VDS<br>VGS<br>D.U.T.<br>R<br>g<br>+ - VDD<br>10 V<br>Pulse width ≤ 1 µs<br>Duty factor ≤ 0.1 %<br>°<br>Fig. 10a - Switching Time Test Circuit<br>VDS<br>90 % N/....\ |<br>!<br>|<br>10 % /\_|<br>VGS ol i! a r e e r |<br>td(on) tr td(off) tf<br>**----- End of picture text -----**<br>


**Fig. 9 - Maximum Drain Current vs. Case Temperature** 

**Fig. 10b - Switching Time Waveforms** 

**Fig. 11 - Maximum Effective Transient Thermal Impedance, Junction-to-Case** 

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15 V<br>VDS L Driver<br>Rg D.U.T. +<br>- [V][DD] A<br>IAS<br>gp 20 V at<br>tp 0.01 Ω<br>**----- End of picture text -----**<br>


**Fig. 12a - Unclamped Inductive Test Circuit** 

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VDS<br>t<br>/*— p —S|<br>/ \\<br>y \\<br>// \<br>IAS a<br>Fig. 12b - Unclamped Inductive Waveforms<br>**----- End of picture text -----**<br>


S13-1927-Rev. E, 09-Sep-13 

Document Number: 91286 

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For technical questions, contact: hvm@vishay.com 

THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 

**IRFS11N50A, SiHFS11N50A** 

www.vishay.com 

Vishay Siliconix 

**Fig. 12c - Maximum Avalanche Energy vs. Drain Current** 

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QG<br>VGS<br>QGS QGD<br>VG<br>Charge<br>**----- End of picture text -----**<br>


**Fig. 13a - Basic Gate Charge Waveform** 

**Fig. 12d - Typical Drain-to-Source Voltage vs. Avalanche Current** 

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Current regulator<br>Same type as D.U.T.<br>50 kΩ<br>12 V 0.2 µF<br>0.3 µF<br>pals<br>+<br>D.U.T. - VDS<br>VGS<br>3 mA<br>IG ID<br>Current sampling resistors<br>**----- End of picture text -----**<br>


**Fig. 13b - Gate Charge Test Circuit** 

S13-1927-Rev. E, 09-Sep-13 

Document Number: 91286 

**6** For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 

**IRFS11N50A, SiHFS11N50A** 

Vishay Siliconix 

**==> picture [59 x 48] intentionally omitted <==**

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www.vishay.com<br>**----- End of picture text -----**<br>


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Peak Diode Recovery dV/dt Test Circuit<br>+ Circuit layout considerations<br>D.U.T.<br>•  Low stray inductance<br>•  Ground plane<br>•  Low leakage inductance<br>current transformer<br>-<br>+<br>- - +<br>Rg •  dV/dt controlled by Rg +<br>••   Driver same type as D.U.T.ISD controlled by duty factor “D” - VDD<br>•  D.U.T. - device under test<br>Driver gate drive<br>Period D = P.W.<br>P.W. Period<br>VGS = 10 V [a]<br>D.U.T. lSD waveform<br>Reverse<br>recovery Body diode forward<br>current current dI/dt<br>D.U.T. VDS waveform Diode recovery<br>dV/dt<br>VDD<br>Re-applied<br>voltage<br>Body diode forward drop<br>Inductor current<br>Ripple ≤ 5 % ISD<br>Note<br>a. VGS = 5 V for logic level devices<br>**----- End of picture text -----**<br>


**Fig. 14 - For N-Channel** 

_Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?91286._ 

S13-1927-Rev. E, 09-Sep-13 

Document Number: 91286 

**7** 

For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 

**Package Information** 

**==> picture [60 x 50] intentionally omitted <==**

## Vishay Siliconix 

## **TO-263AB (HIGH VOLTAGE)** 

|L1<br>L2<br>D<br>4<br>(Datum A|L1<br>L2<br>D<br>4<br>(Datum A|L1<br>L2<br>D<br><br>(Datum A|L1<br>L2<br>D<br><br>(Datum A|)|3<br>|4|4|4|4|4|4|4|4|4|
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
||||||E<br><br>||||||||||
||||1||4||||||||||
||||D||1<br>2<br>C|3<br><br>C|||||||||
||||2||**B**<br>e||||||||||
|||||**B**|||||||||||
|||||2 x|||||||||||
||||||||||||||||
||||||||||||||||
||||||||||||||||
|||||Lead tip||||Section B - B and C - C<br>Scale: none|||||||
||||||||||||||||
||||**MILLIMETERS**||||**INCHES**<br>**MIN.**<br>**MAX.**<br>0.160<br>0.190<br>0.000<br>0.010<br>0.020<br>0.039<br>0.020<br>0.035<br>0.045<br>0.070<br>0.045<br>0.068<br>0.015<br>0.029<br>0.015<br>0.023<br>0.045<br>0.065<br>0.330<br>0.380||||**MILLIMETERS**||**INCHES**||
|**DIM.**|**MIN.**||||**MA**|**X.**|**MIN.**|||**DIM.**|**MIN.**|**MAX.**|**MIN.**|**MAX.**|
|A|4.06||||4.8|3|0.160|||D1|6.86|-|0.270|-|
|A1|0.00||||0.2|5|0.000|||E|9.65|10.67|0.380|0.420|
|b|0.51||||0.9|9|0.020|||E1|6.22|-|0.245|-|
|b1|0.51||||0.8|9|0.020|||e|2.54 BSC||0.100 BSC||
|b2|1.14||||1.7|8|0.045|||H|14.61|15.88|0.575|0.625|
|b3|1.14||||1.7|3|0.045|||L|1.78|2.79|0.070|0.110|
|c|0.38||||0.7|4|0.015|||L1|-|1.65|-|0.066|
|c1|0.38||||0.5|8|0.015|||L2|-|1.78|-|0.070|
|c2|1.14||||1.6|5|0.045|||L3|0.25 BSC||0.010 BSC||
|D|8.38||||9.6|5|0.330|||L4|4.78|5.28|0.188|0.208|
|ECN: S-82110-Rev. A, 15-Sep-08<br>DWG: 5970|||||||||||||||



ECN: S-82110-Rev. A, 15-Sep-08 DWG: 5970 

## **Notes** 

1. Dimensioning and tolerancing per ASME Y14.5M-1994. 

2. Dimensions are shown in millimeters (inches). 

3. Dimension D and E do not include mold flash. Mold flash shall not exceed 0.127 mm (0.005") per side. These dimensions are measured at the outmost extremes of the plastic body at datum A. 

4. Thermal PAD contour optional within dimension E, L1, D1 and E1. 

5. Dimension b1 and c1 apply to base metal only. 

6. Datum A and B to be determined at datum plane H. 

7. Outline conforms to JEDEC outline to TO-263AB. 

Document Number: 91364 Revision: 15-Sep-08 

www.vishay.com 

1 

**AN826** 

## **Vishay Siliconix** 

## RECOMMENDED MINIMUM PADS FOR D[2] PAK:  3-Lead 

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0.420<br>(10.668)<br>mil<br>0.145<br>(3.683)<br>0.135<br>(3.429)<br>0.200 0.050<br>| rt<br>— (5.080) (1.257)<br>Recommended Minimum Pads<br>Dimensions in Inches/(mm)<br>0.355 (9.017)<br>0.635<br>(16.129)<br>**----- End of picture text -----**<br>


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Document Number:   73397 11-Apr-05 

www.vishay.com 

**1** 

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**==> picture [59 x 48] intentionally omitted <==**

## **Disclaimer** 

ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE. 

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## **Material Category Policy** 

**Vishay Intertechnology, Inc. hereby certifies that all its products that are identified as RoHS-Compliant fulfill the definitions and restrictions defined under Directive 2011/65/EU of The European Parliament and of the Council of June 8, 2011 on the restriction of the use of certain hazardous substances in electrical and electronic equipment (EEE) - recast, unless otherwise specified as non-compliant.** 

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Revision: 02-Oct-12 

Document Number: 91000 

**1**