IRFP450APBF.

**IRFP450A, SiHFP450A** 

## Vishay Siliconix 

## **Power MOSFET** 

**PRODUCT SUMMARY** VDS (V) 500 RDS(on) ( Ω ) VGS = 10 V 0.40 Qg (Max.) (nC) 64 Qgs (nC) 16 Qgd (nC) 26 Configuration Single ~~==~~ D **TO-247** G @e S ~~4~~ D S G 

N-Channel MOSFET 

## **FEATURES** 

- Low Gate Charge Qg Results in Simple Driveg Results in Simple Drive Results in Simple Drive Requirement Available 

- • Improved Gate, Avalanche and Dynamic dV/dt **RoHS*** Ruggedness **COMPLIANT** 

- • Fully Characterized Capacitance and Avalanche Voltage and Current 

- • Effective Coss Specified ; 

- Low Gate Charge Qg Results in Simple Driveg Results in Simple Drive Results in Simple Drive Requirement 

- Lead (Pb)-free Available 

## **APPLICATIONS** 

- Switch Mode Power Supply (SMPS) 

- Uninterruptable Power Supply 

- High Speed Power Switching 

## **TYPICAL SMPS TOPOLOGIES** 

- Two Transistor Forward 

- Half Bridge, Full Bridge 

• PFC Boost 

|**ABSOLUTE MAXIMUM RATINGS**TC= 25 °C,unless otherwise noted|**ABSOLUTE MAXIMUM RATINGS**TC= 25 °C,unless otherwise noted|**ABSOLUTE MAXIMUM RATINGS**TC= 25 °C,unless otherwise noted|**ABSOLUTE MAXIMUM RATINGS**TC= 25 °C,unless otherwise noted|**ABSOLUTE MAXIMUM RATINGS**TC= 25 °C,unless otherwise noted|**ABSOLUTE MAXIMUM RATINGS**TC= 25 °C,unless otherwise noted|
|---|---|---|---|---|---|
|**PARAMETER**|||**SYMBOL**|**LIMIT**|**UNIT**|
|Drain-Source Voltage|||VDS|500|V|
|Gate-Source Voltage|||VGS|± 30||
|Continuous Drain Current|VGSat 10 V|TC= 25 °C|ID|14|A|
|||TC= 100 °C||8.7||
|Pulsed Drain Currenta|||IDM|56||
|Linear Derating Factor||||1.5|W/°C|
|Single Pulse Avalanche Energyb|||EAS|760|mJ|
|Repetitive Avalanche Currenta|||IAR|14|A|
|Repetitive Avalanche Energya<br>~~Be~~|||EAR<br>~~Be~~|19<br>~~Be~~|mJ<br>~~Be~~|
|Maximum Power Dissipation<br>~~Be~~|TC= 25 °C<br>~~Be~~||PD<br>~~Be~~|190<br>~~Be~~|W<br>~~Be~~|
|Peak Diode Recovery dV/dtc<br>~~Be~~|||dV/dt<br>~~Be~~|4.1<br>~~Be~~|V/ns<br>~~Be~~|
|Operating Junction and Storage Temperature Range<br>~~Be~~|||TJ, Tstg<br>~~Be~~|- 55 to + 150<br>~~Be~~|°C<br>~~Be~~|
|Soldering Recommendations (Peak Temperature)<br>~~Be~~|for 10 s<br>~~Be~~||~~Be~~|300d<br>~~Be~~||
|Mounting Torque<br>~~Be~~|6-32 or M3 screw<br>~~Be~~||~~Be~~|10<br>~~Be~~|lbf · in<br>~~Be~~|
|||||1.1<br>~~Be~~|N · m<br>~~Be~~|



**Notes** a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11). 

- b. Starting TJ = 25 °C, L = 7.8 mH, RG = 25 Ω , IAS = 14 A (see fig. 12). 

- c. ISD ≤ 14 A, dI/dt ≤ 130 A/µs, VDD ≤ VDS, TJ ≤ 150 °C. 

- d. 1.6 mm from case. 

- Pb containing terminations are not RoHS compliant, exemptions may apply 

Document Number: 91230 S-81271-Rev. A, 16-Jun-08 

www.vishay.com 

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**IRFP450A, SiHFP450A** 

## Vishay Siliconix 

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|**THERMAL RESISTANCE RATINGS**|**THERMAL RESISTANCE RATINGS**|**THERMAL RESISTANCE RATINGS**|**THERMAL RESISTANCE RATINGS**|**THERMAL RESISTANCE RATINGS**|
|---|---|---|---|---|
|**PARAMETER**|**SYMBOL**|**TYP.**|**MAX.**|**UNIT**|
|Maximum Junction-to-Ambient|RthJA|-|40|°C/W|
|Case-to-Sink, Flat, Greased Surface|RthCS|0.24|-||
|Maximum Junction-to-Case (Drain)|RthJC|-|0.65||



|**SPECIFICATIONS** TJ= 25 °C,unless otherwise noted|**SPECIFICATIONS** TJ= 25 °C,unless otherwise noted|**SPECIFICATIONS** TJ= 25 °C,unless otherwise noted|**SPECIFICATIONS** TJ= 25 °C,unless otherwise noted|||||
|---|---|---|---|---|---|---|---|
|**PARAMETER**|**SYMBOL**|**TEST CONDITIONS**||**MIN.**|**TYP.**|**MAX.**|**UNIT**|
|**Static**||||||||
|Drain-Source Breakdown Voltage|VDS|VGS= 0 V, ID= 250 µA||500|-|-|V|
|VDSTemperature Coefficient|ΔVDS/TJ|Reference to 25 °C, ID= 1 mA||-|0.58|-|V/°C|
|Gate-Source Threshold Voltage|VGS(th)|VDS= VGS, ID= 250 µA||2.0|-|4.0|V|
|Gate-Source Leakage|IGSS|VGS= ± 30 V||-|-|± 100|nA|
|Zero Gate Voltage Drain Current|IDSS|VDS= 500 V, VGS= 0 V||-|-|25|µA|
|||VDS= 400 V, VGS= 0 V, TJ= 125 °C||-|-|250||
|Drain-Source On-State Resistance|RDS(on)|VGS= 10 V|ID= 8.4 Ab|-|-|0.40|Ω|
|Forward Transconductance|gfs|VDS= 50 V, ID= 8.4 Ab||7.8|-|-|S|
|**Dynamic**||||||||
|Input Capacitance|Ciss|VGS= 0 V,<br>VDS= 25 V,<br>f = 1.0 MHz, see fig. 5||-|2038|-|pF|
|Output Capacitance|Coss|||-|307|-||
|Reverse Transfer Capacitance|Crss|||-|10|-||
|Output Capacitance|Coss|VGS= 0 V; VDS= 1.0 V, f = 1.0 MHz|||2859|||
|Output Capacitance|Coss|VGS= 0 V; VDS= 400 V, f = 1.0 MHz|||81|||
|Effective Output Capacitance|Cosseff.|VGS= 0 V; VDS= 0 V to 400 Vc|||96|||
|Total Gate Charge|Qg|VGS= 10 V|ID= 14 A, VDS= 400 V,<br>see fig. 6 and 13b|-|-|64|nC|
|Gate-Source Charge|Qgs|||-|-|16||
|Gate-Drain Charge|Qgd|||-|-|26||
|Turn-On Delay Time|td(on)|VDD= 250 V, ID= 14 A,<br>RG= 6.2Ω, RD= 17Ω, see fig. 10b||-|15|-|ns|
|Rise Time|tr|||-|36|-||
|Turn-Off Delay Time|td(off)|||-|35|-||
|Fall Time|tf|||-|29|-||
|**Drain-Source Body Diode Characteristics**||||||||
|Continuous Source-Drain Diode Current|IS|MOSFET symbol<br>showing the<br>integral reverse<br>p - n junction diode<br>S<br>D<br>G||-|-|14|A|
|Pulsed Diode Forward Currenta|ISM|||-|-|56||
|Body Diode Voltage|VSD|TJ= 25 °C, IS= 14 A, VGS= 0 Vb||-|-|1.4|V|
|Body Diode Reverse Recovery Time|trr|TJ= 25 °C, IF= 14 A, dI/dt = 100 A/µsb||-|487|731|ns|
|Body Diode Reverse Recovery Charge|Qrr|||-|3.9|5.8|µC|
|Forward Turn-On Time|ton|Intrinsic turn-on time is negligible (turn-on is dominated by LSand LD)||||||



## **Notes** 

a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11). 

b. Pulse width ≤ 300 µs; duty cycle ≤ 2 %. 

c. Coss eff. is a fixed capacitance that gives the same charging time as Coss while VDS is rising from 0 to 80 % VDS. 

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Document Number: 91230 S-81271-Rev. A, 16-Jun-08 

**IRFP450A, SiHFP450A** Vishay Siliconix 

## **TYPICAL CHARACTERISTICS** 25 °C, unless otherwise noted 

**Fig. 1 - Typical Output Characteristics** 

**Fig. 2 - Typical Output Characteristics** 

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Fig. 3 - Typical Transfer Characteristics<br>**----- End of picture text -----**<br>


**Fig. 4 - Normalized On-Resistance vs. Temperature** 

Document Number: 91230 S-81271-Rev. A, 16-Jun-08 

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## **IRFP450A** ~~tC“~~ **, SiHFP450A** VGH, Vishay Siliconix 

**Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage** 

**Fig. 7 - Typical Source-Drain Diode Forward Voltage** 

**Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage** 

**Fig. 8 - Maximum Safe Operating Area** 

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Document Number: 91230 S-81271-Rev. A, 16-Jun-08 

## VISHAY, ~~sss~~ **IRFP450A, SiHFP450A** Vishay Siliconix 

**Fig. 9 - Maximum Drain Current vs. Case Temperature** 

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RD<br>VDS<br>VGS<br>D.U.T.<br>RG +- VDD<br>10 V<br>Pulse width ≤ 1 µs<br>Duty factor ≤ 0.1 %<br>t<br>Fig. 10a - Switching Time Test Circuit<br>VDS<br>90 % —,<br>i<br>\/1<br>1<br>10 % /\_\ I|<br>VGS 1 Nt<br>td(on) tr td(off) tf<br>Fig. 10b - Switching Time Waveforms<br>**----- End of picture text -----**<br>


**Fig. 11 - Maximum Effective Transient Thermal Impedance, Junction-to-Case** 

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**----- Start of picture text -----**<br>
15 V<br>L Driver<br>VDS<br>RG D.U.T. +<br>- [V][DD] A<br>IAS<br>y 20 V Jt<br>tp 0.01 Ω<br>Fig. 12a - Unclamped Inductive Test Circuit<br>**----- End of picture text -----**<br>


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VDS<br>t<br>ke p —<br>/<br>// \<br>/ \<br>/ \<br>IAS<br>**----- End of picture text -----**<br>


**Fig. 12b - Unclamped Inductive Waveforms** 

Document Number: 91230 S-81271-Rev. A, 16-Jun-08 

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**IRFP450A, SiHFP450A** Vishay Siliconix ~~a~~ wv 

**Fig. 12c - Maximum Avalanche Energy vs. Drain Current** 

## **Fig. 12d - Typical Drain-to-Source Voltage vs. Avalanche Current** 

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Current regulator<br>Same type as D.U.T.<br>QG 50 kΩ<br>10 V 12 V 0.2 µF<br>0.3 µF<br>QGS QGD +<br>D.U.T. - VDS<br>VG VGS<br>| “Tt Gg<br>3 mA<br>Charge<br>ail os IG ID<br>Current sampling resistors<br>Fig. 13a - Basic Gate Charge Waveform Fig. 13b - Gate Charge Test Circuit<br>**----- End of picture text -----**<br>


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Document Number: 91230 S-81271-Rev. A, 16-Jun-08 

**IRFP450A, SiHFP450A** Vishay Siliconix 

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## **Peak Diode Recovery dV/dt Test Circuit** 

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**----- Start of picture text -----**<br>
+ Circuit layout considerations<br>D.U.T.<br>   •  Low stray inductance<br> •  Ground plane<br> •  Low leakage inductance<br>      current transformer<br>-<br>+<br>- - +<br>RG •  dV/dt controlled by RG +<br>•  Driver same type as D.U.T. - VDD<br>•  ISD controlled by duty factor "D"<br>•  D.U.T. - device under test<br>Driver gate drive<br>P.W.<br>Period D =<br>P.W. Period<br>VGS = 10 V*<br>D.U.T. ISD waveform<br>Reverse<br>recovery Body diode forward<br>current current<br>dI/dt<br>D.U.T. VDS waveform<br>Diode recovery<br>dV/dt<br>VDD<br>Re-applied<br>voltage Body diode forward drop<br>Inductor current<br>Ripple ≤ 5 % ISD<br>**----- End of picture text -----**<br>


* VGS = 5 V for logic level devices 

**Fig. 14 - For N-Channel** 

_Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see http://www.vishay.com/ppg?91230._ 

Document Number: 91230 S-81271-Rev. A, 16-Jun-08 

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**Package Information** 

Vishay Siliconix 

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, §#£f<br>“wv BS<br>**----- End of picture text -----**<br>


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## **TO-247AC (High Voltage)** 

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4 4 A L A |<br>B E         ØP7 (Datum B)<br>E/2 S A2 Ø k M D B M<br>3  R/2 ØP1<br>A<br>D2<br>Q<br>r i A E 7 =e<br>2 x R 4 4<br>(2) D D1<br>ak | ain<br>1 2 3 D 4<br>Thermal pad<br>5  L1<br>C L 4<br>E1<br>MA See view B i A o| TUt 0.01 A M D B M<br>2 x b2 C View A - A<br>2 x  e<br>3 x b<br>b4 A1<br>0.10 M C A M<br>s —o 57 7 _<br>Planting (b1, b3, b5) Base metal<br>Lead Assignments<br>1. Gate D D E E<br>2. Drain<br>3. Source C C (c) c1<br>4. Drain<br>| (b, b2, b4) ss<br>(4)<br>Section C - C, D - D, E - E<br>View B<br>MILLIMETERS INCHES MILLIMETERS INCHES<br>ee ee<br>DIM. MIN. MAX. MIN. MAX. DIM. — MIN. MAX. MIN. MAX.<br>A 4.58 5.31 0.180 0.209 D2 0.51 1.30 0.020 0.051<br>a | +} ——<br>A1 2.21 2.59 0.087 0.102 E 15.29 15.87 0.602 a 0.625<br>sses A2 1.17 ee 2.49 es 0.046 0.098 nn E1 13.72 - 0.540 -<br>— b 0.99 1.40 0.039 0.055 — e 5.46 BSC 0.215 BSC<br>b1 0.99 1.35 0.039 0.053 Ø k 0.254 0.010<br>ee b2  a 1.53 2.39 0.060 0.094 L a 14.20 16.25 0.559 0.640<br>b3 1.65 2.37 0.065 0.093 L1 3.71 4.29 0.146 0.169<br>——— b4 2.42 3.43 0.095 0.135 N es 7.62 BSC 0.300 BSC<br>—_}| b5 2.59 3.38 ae 0.102 0.133 a Ø P a 3.51 3.66 0.138 0.144<br>c 0.38 0.86 —— 0.015 0.034 ee Ø P1 - 7.39 - 0.291<br>I c1 0.38 0.76 0.015 0.030 > Q 5.31 5.69 0.209 0.224<br>— D ft 19.71 20.82 0.776 0.820 R 4.52 5.49 0.178 0.216<br>D1 13.08 - 0.515 - S 5.51 BSC 0.217 BSC<br>ee es —<br>ECN: X13-0103-Rev. D, 01-Jul-13<br>DWG: 5971<br>PC —<br>**----- End of picture text -----**<br>


## **Notes** 

1. Dimensioning and tolerancing per ASME Y14.5M-1994. 

2. Contour of slot optional. 

3. Dimension D and E do not include mold flash. Mold flash shall not exceed 0.127 mm (0.005") per side. These dimensions are measured at the outermost extremes of the plastic body. 

4. Thermal pad contour optional with dimensions D1 and E1. 

5. Lead finish uncontrolled in L1. 

6. Ø P to have a maximum draft angle of 1.5 to the top of the part with a maximum hole diameter of 3.91 mm (0.154"). 

7. Outline conforms to JEDEC outline TO-247 with exception of dimension c. 

8. Xian and Mingxin actually photo. 

Revision: 01-Jul-13 

Document Number: 91360 

For technical questions, contact: hvm@vishay.com 

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## **Disclaimer** 

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Revision: 02-Oct-12 

Document Number: 91000 

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