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IIS3DHHCTR
MEMS Accelerometer, ± 2.5g, X, Y, Z, LGA, 16 Pins, 0.076mg/digit
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- Manufacturer: STMICROELECTRONICS
- Product type: MEMS Accelerometers
- MEMS Sensor Output:Digital; Measurement Axis:X, Y, Z; Acceleration Range:± 2.5g; Supply Voltage Min:1.71V; Supply Voltage Max:3.6V; Sensor Case Style:LGA; No. of Pins:16Pins; Sensitivity
- MSL: MSL 3 - 168 hours
- SVHC: No SVHC (25-Jun-2025)
- No. of Pins: 16Pins
- Sensing Axis: X, Y, Z
- Product Range: -
- Qualification: -
- Sensitivity Max: 7mg/digit
- Sensitivity Min: -7mg/digit
- Sensitivity Typ: 0.076mg/digit
- Sensor Case Style: LGA
- MEMS Sensor Output: Digital
- Supply Voltage Max: 3.6V
- Supply Voltage Min: 1.71V
- Sensor Case / Package: LGA
- Sensing Range - Accelerometer: ± 2.5g
| Delivery and price | |
|---|---|
| Units per pack | 3000 |
| Price | 7.05 € |
| Current stock | 10+ |
| Lead time | 30 days |
Datasheet
**IIS3DHHC** Datasheet ## High-resolution, high-stability 3-axis digital accelerometer ## **Features** - Included in the 10-year longevity program - 3-axis, ±2.5 _g_ full-scale - Ultra-low noise performance: 45 µ _g_ /√Hz - Excellent stability over temperature (<0.4 m _g_ /°C) and time - 16-bit data output ## **Ceramic cavity LGA-16 (5x5x1.7 mm)** - SPI 4-wire digital output interface - Embedded FIFO (depth 32 levels) - Embedded temperature sensor - 12-bit temperature data output - High shock survivability - Extended operating temperature range (-40 °C to +85 °C) - ECOPACK[®] , RoHS and “Green” compliant ## **Applications** - Precision inclinometer - Antenna and platform pointing and leveling - Leveling instruments ## **Description** ## **Maturity status link** ~~ea~~ IIS3DHHC |**Maturity status link**<br>~~ea~~|**Maturity status link**<br>~~ea~~| |---|---| |IIS3DHHC|| |**Device summary**<br>~~Sea~~|| |**Order code**|IIS3DHHCTR| |**Temperature**<br>**range [°C]**|-40 to +85| |**Package**|CC LGA-16<br>(5x5x1.7 mm)| |**Packing**|Tape and reel| The IIS3DHHC is an ultra-low noise, high-stability three-axis linear accelerometer. The IIS3DHHC has a full scale of ±2.5 _g_ and is capable of providing the measured accelerations to the application through an SPI 4-wire digital interface. The sensing element is manufactured using a dedicated micromachining process developed by STMicroelectronics to produce inertial sensors and actuators on silicon wafers. The IC interface is manufactured using a CMOS process that allows a high level of integration to design a dedicated circuit which is trimmed to better match the characteristics of the sensing element. The IIS3DHHC is available in a high-performance (low-stress) ceramic cavity land grid array (CC LGA) package and can operate within a temperature range of -40 °C to +85 °C. **DS12292** - **Rev 2** - **January 2018** For further information contact your local STMicroelectronics sales office. www.st.com/ **IIS3DHHC Pin description** **1** ## **Pin description** **Figure 1. Pin connections** **==> picture [421 x 226] intentionally omitted <==** **----- Start of picture text -----**<br> Z<br>Y<br>14 13 12 11<br>X Connect to GND<br>or leave unconnected 15 10 Connect to GND<br>Connect to GND 16 9 GND<br>or leave unconnected TOP<br>VIEW<br>SPC 1 8 VDD<br>1<br>(TOP VIEW) SDI 2 7 VDDIO<br>DIRECTION OF THE 3 4 5 6<br>DETECTABLE<br>ACCELERATIONS<br>Connect to GND or leave unconnected Connect to GND Connect to GND Connect to GND<br>SDO CS INT2 INT1<br>**----- End of picture text -----**<br> **Table 1. Pin description** |**Pin#**|**Name**|**Function**| |---|---|---| |1|SPC|Clock line for SPI 4-wire interface (SPC)| |2|SDI|Serial data input (SDI) line for SPI 4-wire interface| |3|SDO|Serial data output (SDO) line for SPI 4-wire interface| |4|CS|SPI chip-select line (CS)| |5|INT2|Programmable interrupt 2 generated according to a configurable FIFO threshold in a dedicated register| |6|INT1|Programmable interrupt 1 generated according to a configurable FIFO threshold in a dedicated register| |7|Vdd_IO|Power supply for I/O pins<br>Recommended power supply decoupling capacitor (100 nF)| |8|Vdd|Power supply<br>Recommended power supply decoupling capacitors (100 nF ceramic in parallel with 10 µF aluminum)| |9|GND|0 V power supply| |10|Reserved|Connect to GND| |11|Reserved|Connect to GND| |12|Reserved|Connect to GND| |13|Reserved|Connect to GND| |14|Reserved|Connect to GND or leave unconnected| |15|Reserved|Connect to GND or leave unconnected| |16|Reserved|Connect to GND or leave unconnected| **DS12292** - **Rev 2** **page 2/31** **IIS3DHHC Mechanical and electrical specifications** ## **2 Mechanical and electrical specifications** ## **2.1 Mechanical characteristics** @ Vdd = 2.8 V, T = 25 °C unless otherwise noted. ## **Table 2. Mechanical characteristics** |**Symbol**|**Parameter**|**Test condition**|**Min.(1)**|**Typ.(2)**|**Max.(1)**|**Unit**| |---|---|---|---|---|---|---| |FS|Measurement range(3)|||±2.5||_g_| |So|Sensitivity(4)||-7%|0.076|+7%|mg/digit| |TCSo|Sensitivity change vs. temperature|From -40 °C to +85 °C, delta from 25°C|-1.35|0.7|+1.35|%| |Off|Zero-g level offset accuracy(5)||-35|±20|+35|m_g_| |TCOff|Zero-g level change vs. temperature(6)|From -40 °C to +85 °C, delta from 25 °C|-0.4||0.4|m_g_/°C| |NL|Non linearity|Best-fit straight line|||2|% FS| |Zgn|Zero-g noise density|FS = ±2.5_g_||45|65|µ_g_/√(Hz)| |ODR|Digital output data rate|||1.1||kHz| |Bw|Bandwidth|For both FIR and IIR filters||235 or 440||Hz| |StartT|Startup time|For cold start condition|||150|ms| |ST|Self-test positive difference(7)|X, Y-axis<br>Z-axis|75<br>75||650<br>1400|m_g_| |Top|Operating temperature range||-40||+85|°C| _1. Min/Max values are based on characterization results, not tested in production and not guaranteed._ _2. Typical specifications are not guaranteed._ _3. Sensor is designed with larger dynamic to avoid variation of FS limits in the operative bandwidth. Consequently to trim operations at factory final test._ _4. Sensitivity range after MSL3 preconditioning._ _5. Typical zero-g level offset value after MSL3 preconditioning._ _6. Valid if OFF_TCOMP_EN in Section 7.4 CTRL_REG4 (23h) is set to '1'. Min/max at 3 sigma. Based on characterization data for a limited number of samples, not measured during final test for production._ _7. Self-test positive difference is defined as: OUTPUT[mg](Section 7.4 CTRL_REG4 (23h) ST2, ST1 bits = 01 ) - OUTPUT[mg](Section 7.4 CTRL_REG4 (23h) ST2, ST1 bits = 00 ) in steady state._ **DS12292** - **Rev 2** **page 3/31** **IIS3DHHC Electrical characteristics** ## **2.2 Electrical characteristics** @ Vdd = 2.8 V, T = 25 °C unless otherwise noted. ## **Table 3. Electrical characteristics** |**Symbol**|**Parameter**|**Test condition**|**Min.**|**Typ.(1)**|**Max.**|**Unit**| |---|---|---|---|---|---|---| |Vdd|Supply voltage||1.71|2.8|3.6|V| |Vdd_IO|I/O pins supply voltage||1.71||Vdd+0.1|V| |Idd|Supply current|||2.5|5|mA| |VIH|Digital high-level input voltage||0.7*Vdd_IO|||V| |VIL|Digital low-level input voltage||||0.3*Vdd_IO|V| |VOH|High-level output voltage|IOH= 4 mA(2)|Vdd_IO - 0.2|||V| |VOL|Low-level output voltage|IOL= 4 mA(2)|||0.2|V| |Top|Operating temperature range||-40||+85|°C| |SPI_Fr|SPI frequency|4-wire interface||5|10|MHz| |Trise|Time for power supply rising(3)||0.01||100|ms| |Twait|Time delay between Vdd_IO and Vdd(3)||0||10|ms| _1. Typical specifications are not guaranteed._ _2. 4 mA is the maximum driving capability, i.e. the maximum DC current that can be sourced/sunk by the digital pad in order to guarantee the correct digital output voltage levels VOH and VOL._ _3. Please refer to Figure 2. Recommended power-up sequence for more details._ ## **2.2.1 Recommended power-up sequence** For the power-up sequence please refer to the following figure, where: - Trise is the time for the power supply to rise from 10% to 90% of its final value - Twait is the time delay between the end of the Vdd_IO ramp (90% of its final value) and the start of the Vdd ramp In the power-down sequence Vdd and Vdd_IO can come down in any order. ## **Figure 2. Recommended power-up sequence** **==> picture [358 x 156] intentionally omitted <==** **----- Start of picture text -----**<br> Trise<br>Vdd_IO 0V<br>Twait<br>0V<br>Vdd<br>Trise<br>**----- End of picture text -----**<br> **DS12292** - **Rev 2** **page 4/31** **IIS3DHHC Temperature sensor characteristics** ## **2.3 Temperature sensor characteristics** @ Vdd = 2.8 V, T = 25 °C unless otherwise noted. **Table 4. Temperature sensor characteristics** |**Symbol**|**Parameter**|**Test condition**|**Min.(1)**|**Typ.(2)**|**Max.(1)**|**Unit**| |---|---|---|---|---|---|---| |TSDr|Temperature sensor output change vs. temperature|||16||digit/°C| |Tn|Temperature sensor noise (_RMS_)||||0.1|°C| |Ta|Temperature accuracy||-15||+15|°C| |TODR|Temperature refresh rate|Equal to ODR/16|62.5|||Hz| |TNL|Temperature nonlinearity|Best-fit straight line||5||% Top| |Top|Operating temperature range||-40||+85|°C| _1. Min/Max values are based on characterization results, not tested in production and not guaranteed_ _2. Typical specifications are not guaranteed._ **DS12292** - **Rev 2** **page 5/31** **IIS3DHHC Absolute maximum ratings** **3 Absolute maximum ratings** Stresses above those listed as “Absolute maximum ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device under these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. **Table 5. Absolute maximum ratings** |**Symbol**|**Ratings**|**Maximum value**|**Unit**| |---|---|---|---| |Vdd and Vdd_IO|Supply voltage|-0.3 to 4.8|V| |TSTG|Storage temperature range|-40 to +85|°C| |Sg|Acceleration g for 0.2 ms|10,000|_g_| |ESD|Electrostatic discharge protection (HBM)|2|kV| |Vin|Input voltage on any control pin<br>(including CS, SPC, SDI, SDO)|-0.3 to Vdd_IO +0.3|V| _Note:_ _Supply voltage on any pin should never exceed 4.8 V._ **DS12292** - **Rev 2** **page 6/31** **IIS3DHHC Communication interface characteristics** ## **4 Communication interface characteristics** ## **4.1 SPI - serial peripheral interface** Subject to general operating conditions for Vdd and Top. **Table 6. SPI slave timing values** ||**Table 6. SPI slave timing valuesSPI slave timing values**|||| |---|---|---|---|---| |Symbol|Parameter|Value||Unit| |||Min|Max|| |tc(SPC)|SPI clock cycle|100||ns| |fc(SPC)|SPI clock frequency||10|MHz| |tsu(CS)|CS setup time|5||ns| |th(CS)|CS hold time|20||| |tsu(SI)|SDI input setup time|5||| |th(SI)|SDI input hold time|15||| |tv(SO)|SDO valid output time||35|| |th(SO)|SDO output hold time|5||| |tdis(SO)|SDO output disable time||50|| _1. Values are guaranteed at 10 MHz clock frequency for SPI 4 wires, based on characterization results, not tested in production_ **Figure 4. SPI slave timing diagram** _Note: Measurement points are done at 0.2·Vdd_IO and 0.8·Vdd_IO, for both input and output ports. The SPI state machine is reset each time the CS signal is de-asserted._ **DS12292** - **Rev 2** **page 7/31** **IIS3DHHC SPI bus interface** ## **4.2 SPI bus interface** The ISS3DHHC SPI is a bus slave. The SPI allows writing to and reading from the registers of the device. The serial interface interacts with the application using 4 wires: **CS** , **SPC** , **SDI** and **SDO** . **Figure 5. Read and write protocol** **==> picture [331 x 109] intentionally omitted <==** **----- Start of picture text -----**<br> CS<br>SPC<br>SDI<br>RW DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0<br>AD6 AD5 AD4 AD3 AD2 AD1 AD0<br>SDO<br>DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0<br>**----- End of picture text -----**<br> **CS** is the serial port enable and it is controlled by the SPI master. It goes low at the start of the transmission and goes back high at the end. **SPC** is the serial port clock and it is controlled by the SPI master. It is stopped high when **CS** is high (no transmission). **SDI** and **SDO** are respectively the serial port data input and output. These lines are driven at the falling edge of **SPC** and should be captured at the rising edge of **SPC** . Both the read register and write register commands are completed in 16 clock pulses or in multiples of 8 in case of multiple read/write bytes. Bit duration is the time between two falling edges of **SPC** . The first bit (bit 0) starts at the first falling edge of **SPC** after the falling edge of **CS** while the last bit (bit 15, bit 23, ...) starts at the last falling edge of SPC just before the rising edge of **CS** . **bit 0** : RW bit. When 0, the data DI(7:0) is written into the device. When 1, the data DO(7:0) from the device is read. In latter case, the chip will drive **SDO** at the start of bit 8. **bit 1-7** : address AD(6:0). This is the address field of the indexed register. **bit 8-15** : data DI(7:0) (write mode). This is the data that is written into the device (MSb first). **bit 8-15** : data DO(7:0) (read mode). This is the data that is read from the device (MSb first). In multiple read/write commands further blocks of 8 clock periods will be added. When the Section 7.1 CTRL_REG1 (20h) (IF_ADD_INC) bit is ‘0’ the address used to read/write data remains the same for every block. When Section 7.1 CTRL_REG1 (20h)(IF_ADD_INC) bit is ‘1’ the address used to read/write data is increased at every block. The function and the behavior of **SDI** and **SDO** remain unchanged. **DS12292** - **Rev 2** **page 8/31** **IIS3DHHC SPI bus interface** ## **4.2.1 SPI read** ## **Figure 6. SPI read protocol** **==> picture [281 x 75] intentionally omitted <==** **----- Start of picture text -----**<br> CS<br>SPC<br>SDI<br>RW<br>AD6 AD5 AD4 AD3 AD2 AD1 AD0<br>SDO<br>DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0<br>**----- End of picture text -----**<br> The SPI read command is performed with 16 clock pulses. The multiple byte read command is performed by adding blocks of 8 clock pulses to the previous one. **bit 0** : READ bit. The value is 1. **bit 1-7** : address AD(6:0). This is the address field of the indexed register. **bit 8-15** : data DO(7:0) (read mode). This is the data that will be read from the device (MSb first). **bit 16-...** : data DO(...-8). Further data in multiple byte reads. **Figure 7. Multiple byte SPI read protocol (2-byte example)** **==> picture [379 x 99] intentionally omitted <==** **----- Start of picture text -----**<br> CS<br>SPC<br>SDI<br>RW<br>AD6 AD5 AD4 AD3 AD2 AD1 AD0<br>SDO<br>DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0DO15 DO14 DO13 DO12 DO11 DO10 DO9 DO8<br>**----- End of picture text -----**<br> **DS12292** - **Rev 2** **page 9/31** **IIS3DHHC SPI bus interface** ## **4.2.2 SPI write** **Figure 8. SPI write protocol** **==> picture [306 x 77] intentionally omitted <==** **----- Start of picture text -----**<br> CS<br>SPC<br>SDI<br>RW DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0<br>AD6 AD5 AD4 AD3 AD2 AD1 AD0<br>**----- End of picture text -----**<br> The SPI write command is performed with 16 clock pulses. The multiple byte write command is performed by adding blocks of 8 clock pulses to the previous one. **bit 0** : WRITE bit. The value is 0. **bit 1 -7** : address AD(6:0). This is the address field of the indexed register. **bit 8-15** : data DI(7:0) (write mode). This is the data that is written inside the device (MSb first). **bit 16-...** : data DI(...-8). Further data in multiple byte writes. **Figure 9. Multiple byte SPI write protocol (2-byte example)** **==> picture [394 x 95] intentionally omitted <==** **----- Start of picture text -----**<br> CS<br>SPC<br>SDI<br>DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 DI15 DI14 DI13 DI12 DI11 DI10 DI9 DI8<br>RW<br>AD6 AD5 AD4 AD3 AD2 AD1 AD0<br>**----- End of picture text -----**<br> **DS12292** - **Rev 2** **page 10/31** **IIS3DHHC FIFO** ## **5 FIFO** The IIS3DHHC embeds 32 slots of 16-bit data FIFO for each of the accelerometer’s three output channels, X, Y and Z. This allows consistent power saving for the system since the host processor does not need to continuously poll data from the sensor, but it can wake up only when needed and burst the significant data out from the FIFO. This buffer can work accordingly to five different modes: Bypass mode, FIFO mode, Continuous mode, Continuous-to-FIFO mode and Bypass-to-Continuous mode. Each mode is selected by the FMODE [2:0] bits in the Section 7.11 FIFO_CTRL (2Eh) register. Programmable FIFO threshold status, FIFO overrun events and the number of unread samples stored are available in the Section 7.12 FIFO_SRC (2Fh) register and can be set to generate dedicated interrupts on the INT1 and INT2 pins using the Section 7.2 INT1_CTRL (21h) and Section 7.3 INT2_CTRL (22h) registers. Section 7.12 FIFO_SRC (2Fh)(FTH) goes to '1' when the number of unread samples (Section 7.12 FIFO_SRC (2Fh) (FSS5:0)) is greater than or equal to FTH [4:0] in Section 7.11 FIFO_CTRL (2Eh). If Section 7.11 FIFO_CTRL (2Eh) (FTH[4:0]) is equal to 0, Section 7.12 FIFO_SRC (2Fh)(FTH) goes to ‘0’. Section 7.12 FIFO_SRC (2Fh)(OVRN) is equal to '1' if a FIFO slot is overwritten. Section 7.12 FIFO_SRC (2Fh)(FSS [5:0]) contains stored data levels of unread samples. When FSS [5:0] is equal to ‘000000’, FIFO is empty. When FSS [5:0] is equal to ‘100000’, FIFO is full and the unread samples are 32. The FIFO feature is enabled by writing '1' in Section 7.4 CTRL_REG4 (23h) (FIFO_EN). To guarantee the correct acquisition of data during the switching into and out of FIFO mode, the first sample acquired must be discarded. ## **5.1** ## **Bypass mode** In Bypass mode (Section 7.11 FIFO_CTRL (2Eh)(FMODE [2:0]= 000), the FIFO is not operational, no data is collected in FIFO memory, and it remains empty with the only actual sample available in the output registers. Bypass mode is also used to reset the FIFO when in FIFO mode. As described in Figure 10. Bypass mode, for each channel only the first address is used. When new data is available the old data is overwritten. **Figure 10. Bypass mode** **==> picture [238 x 174] intentionally omitted <==** **----- Start of picture text -----**<br> xi,yi,zi<br>x0 y0 z0<br>x1 y1 z1<br>empty x2 y2 z2<br>x31 y31 z31<br>**----- End of picture text -----**<br> **==> picture [62 x 147] intentionally omitted <==** **DS12292** - **Rev 2** **page 11/31** **IIS3DHHC FIFO mode** ## **5.2 FIFO mode** In FIFO mode (Section 7.11 FIFO_CTRL (2Eh) (FMODE [2:0] = 001) data from the output channels are stored in the FIFO memory until it is full, when 32 unread samples are stored in memory, data collecting is stopped. To reset FIFO content, Bypass mode should be selected by writing Section 7.11 FIFO_CTRL (2Eh) (FMODE [2:0]) to '000'. After this reset command, it is possible to restart FIFO mode, writing Section 7.11 FIFO_CTRL (2Eh) (FMODE [2:0]) to '001'. A FIFO threshold interrupt can be enabled (INT1_OVR bit in Section 7.2 INT1_CTRL (21h) or INT2_OVR bit in Section 7.3 INT2_CTRL (22h)) in order to be raised when the FIFO is filled to the level specified by the FTH[4:0] bits of Section 7.11 FIFO_CTRL (2Eh). ## **Figure 11. FIFO mode** |xi,yi,zi|**x0**<br>**y**<br>**z0**<br>**0**<br>**x1**<br>**y1**<br>**z1**<br>**x2**<br>**y2**<br>**z2**<br>**x31**<br>**y31**<br>**z31**| |---|---| **==> picture [62 x 146] intentionally omitted <==** **DS12292** - **Rev 2** **page 12/31** **IIS3DHHC Continuous mode** ## **5.3 Continuous mode** Continuous mode (Section 7.11 FIFO_CTRL (2Eh) (FMODE[2:0] = 110) provides a continuous FIFO update: when 32 unread samples are stored in memory, as new data arrives the oldest data is discarded and overwritten by the newer. A FIFO threshold flag Section 7.12 FIFO_SRC (2Fh)(FTH) is asserted when the number of unread samples in FIFO is greater than or equal to Section 7.11 FIFO_CTRL (2Eh)(FTH4:0). It is possible to route Section 7.12 FIFO_SRC (2Fh)(FTH) to the INT1 pin by writing the INT1_FTH bit to ‘1’ in register Section 7.2 INT1_CTRL (21h) or to the INT2 pin by writing the INT2_FTH bit to ‘1’ in register Section 7.3 INT2_CTRL (22h). A full-flag interrupt can be enabled (Section 7.2 INT1_CTRL (21h) (INT_ FSS5)= '1' or Section 7.3 INT2_CTRL (22h) (INT_ FSS5)= '1') when the FIFO becomes saturated and in order to read the contents all at once. If an overrun occurs, the oldest sample in FIFO is overwritten and the OVRN flag in Section 7.12 FIFO_SRC (2Fh) is asserted. In order to empty the FIFO before it is full, it is also possible to pull from FIFO the number of unread samples available in Section 7.12 FIFO_SRC (2Fh) (FSS[5:0]). **Figure 12. Continuous mode** **==> picture [212 x 124] intentionally omitted <==** **----- Start of picture text -----**<br> xi,yi,zi<br>x0 y0 z0<br>( ee<br>x1 y1 z1<br>F [[1]<br>x2 y2 z2<br>x30 y30 z30<br>x31 y31 z31<br>**----- End of picture text -----**<br> **DS12292** - **Rev 2** **page 13/31** **IIS3DHHC Continuous-to-FIFO mode** ## **5.4 Continuous-to-FIFO mode** In Continuous-to-FIFO mode (Section 7.11 FIFO_CTRL (2Eh)(FMODE [2:0] = 011), FIFO operates in Continuous mode and FIFO mode starts on the INT1 edge trigger event. When the FIFO is full, data collecting is stopped. **Figure 13. Continuous-to-FIFO mode** **==> picture [298 x 176] intentionally omitted <==** **----- Start of picture text -----**<br> xi,yi,zi x0 y0 z0 xi,yi,zi x0 y0 z0<br>—e | L__[ ft) — - (_T [|<br>x1 y1 z1<br>x1 y1 z1<br>[ | [| rf.<br>x2 y2 z2<br>x2 y2 z2<br>x30 y30 z30<br>x31 y31 z31<br>x31 y31 z31<br>Continuous Mode FIFO Mode<br>a<br>Trigger event<br>**----- End of picture text -----**<br> **Figure 14. External asynchronous trigger to FIFO for Continuous-to-FIFO mode** **DS12292** - **Rev 2** **page 14/31** **IIS3DHHC Bypass-to-Continuous mode** ## **5.5 Bypass-to-Continuous mode** In Bypass-to-Continuous mode (Section 7.11 FIFO_CTRL (2Eh)(FMODE[2:0] = '100'), data measurement storage inside FIFO starts in Continuous mode on the INT1 edge trigger event, then the sample that follows the trigger is available in FIFO. **Figure 15. Bypass-to-Continuous mode** **==> picture [346 x 163] intentionally omitted <==** **----- Start of picture text -----**<br> — xi,yi,zi x0 y0 z0 xi,yi,zi x0 y0 z0<br>>i | | | — > /(__|| |<br>x1 y1 z1<br>x1 y1 z1<br>x2 y2 z2<br>empty x2 y2 z2 [Tt<br>x30 y30 z30<br>x31 y31 z31<br>x31 y31 z31 =<br>Bypass Mode Continuous Mode<br>ee od<br>Trigger event<br>**----- End of picture text -----**<br> **Figure 16. External asynchronous trigger to FIFO for Bypass-to-Continuous mode** **DS12292** - **Rev 2** **page 15/31** **IIS3DHHC Register mapping** **6 Register mapping** The table given below provides a list of the 8/16-bit registers embedded in the device and the corresponding addresses. **Table 7. Register mapping** |**Name**|**Type**|**Register address**|**Register address**|**Default**|**Note**| |---|---|---|---|---|---| |||**Hex**|**Binary**||| |Reserved|--|00-0E|--|--|Reserved| |WHO_AM_I|r|0F|00001111|00010001|| |Reserved|--|10-1F|--|--|Reserved| |CTRL_REG1|r/w|20|00100000|00000000|| |INT1_CTRL|r/w|21|00100001|00000000|| |INT2_CTRL|r/w|22|00100010|00000000|| |CTRL_REG4|r/w|23|00100011|00000000|| |CTRL_REG5|r/w|24|00100100|00000000|| |OUT_TEMP_L|r|25|00100101|output|| |OUT_TEMP_H|r|26|00100110|output|| |STATUS|r|27|00100111|output|| |OUT_X_L_XL|r|28|00101000|output|| |OUT_X_H_XL|r|29|00101001|output|| |OUT_Y_L_XL|r|2A|00101010|output|| |OUT_Y_H_XL|r|2B|00101011|output|| |OUT_Z_L_XL|r|2C|00101100|output|| |OUT_Z_H_XL|r|2D|00101101|output|| |FIFO_CTRL|r/w|2E|00101110|00000000|| |FIFO_SRC|r|2F|00101111|output|| |Reserved|--|30-32|--|--|Reserved| Registers marked as Reserved must not be changed. Writing to those registers may affect the correct behavior of the device. Their content is automatically restored when the device is powered up. **DS12292** - **Rev 2** **page 16/31** **IIS3DHHC Register description** ## **7** ## **Register description** The device contains a set of registers which are used to control its behavior and to retrieve linear acceleration and temperature data. The register addresses, consisting of 7 bits, are used to identify them and to write the data through the serial interface. ## **7.1 CTRL_REG1 (20h)** Control register 1 ## **Table 8. CTRL_REG1 register** |NORM_<br>MOD_EN|IF_ADD_INC|0(1)|0(1)|BOOT|SW_RESET|DRDY_<br>PULSE|BDU| |---|---|---|---|---|---|---|---| _1. These bits must be set to ‘0’ for the correct operation of the device._ ## **Table 9. CTRL_REG1 register description** ||**Table 9.CTRL_REG1 register description**| |---|---| |NORM_MOD_EN|Normal mode enable. Default value: 0<br>(0: power down; 1: enabled)| |IF_ADD_INC|Register address automatically incremented during a multiple byte access with SPI serial interface. Default<br>value: 1<br>(0: disabled; 1: enabled)| |BOOT|Reboot memory content. Default value: 0<br>(0: normal mode; 1: reboot memory content(1))| |SW_RESET|Software reset. Default value: 0<br>With SW_RESET the values in the writable CTRL registers are changed to the default values.<br>(0: normal mode; 1: reset device)<br>This bit is cleared by hardware at the end of the operation.| |DRDY_PULSE|Data-ready on INT1 pin. Default value: 0<br>(0: DRDY latched; 1: DRDY pulsed, pulse duration is 1/4 ODR)| |BDU|Block Data Update. Default value: 0<br>(0: continuous update; 1: output registers not updated until MSB and LSB read)| _1. Boot request is executed as soon as the internal oscillator is turned on. It is possible to set the bit while in power-down mode, in this case it will be served at the next normal mode._ **DS12292** - **Rev 2** **page 17/31** **IIS3DHHC INT1_CTRL (21h)** ## **7.2 INT1_CTRL (21h)** INT1 pin control register ## **Table 10. INT1_CTRL register** |INT1_<br>DRDY|INT1_<br>BOOT|INT1_<br>OVR|INT1_ FSS5|INT1_FTH|INT1_ EXT|0(1)|0(1)| |---|---|---|---|---|---|---|---| |_1._<br>_These bits must be set to ‘0’ for the correct operation of the device._|||||||| |INT1_DRDY|Accelerometer data ready on INT1 pin. Default value: 0<br>(0: disabled; 1: enabled)||||||| |INT1_ BOOT|Boot status available on INT1 pin. Default value: 0<br>(0: disabled; 1: enabled)||||||| |INT1_OVR|Overrun flag on INT1 pin. Default value: 0<br>(0: disabled; 1: enabled)||||||| |INT1_ FSS5|FSS5 full FIFO flag on INT1 pin. Default value: 0<br>(0: disabled; 1: enabled)||||||| |INT1_FTH|FIFO threshold flag on INT1 pin. Default value: 0<br>(0: disabled; 1: enabled)||||||| |INT1_ EXT|INT1 pin configuration. Default value: 0<br>It configures the INT1 pad as output for FIFO flags or as external asynchronous input trigger to FIFO.<br>INT2 pad is always available as output for FIFO flags.<br>(0: INT1 as output interrupt; 1: INT1 as input channel)||||||| **DS12292** - **Rev 2** **page 18/31** **IIS3DHHC INT2_CTRL (22h)** ## **7.3 INT2_CTRL (22h)** INT2 pin control register ## **Table 11. INT2_CTRL register** INT2_DRDY INT2_BOOT INT2_OVR INT2_ FSS5 INT2_FTH 0[(1)] 0[(1)] 0[(1)] _1. These bits must be set to ‘0’ for the correct operation of the device._ |INT2_DRDY|Accelerometer data ready on INT2 pin. Default value: 0<br>(0: disabled; 1: enabled)| |---|---| |INT2_ BOOT|Boot status available on INT2 pin. Default value: 0<br>(0: disabled; 1: enabled)| |INT2_OVR|Overrun flag on INT2 pin. Default value: 0<br>(0: disabled; 1: enabled)| |INT2_ FSS5|FSS5 full FIFO flag on INT2 pin. Default value: 0<br>(0: disabled; 1: enabled)| |INT2_FTH|FIFO threshold flag on INT2 pin. Default value: 0<br>(0: disabled; 1: enabled)| ## **7.4 CTRL_REG4 (23h)** Control register 4 ## **Table 12. CTRL_REG4 register** |DSP_LP_<br>TYPE|DSP_BW_<br>SEL|ST2|ST1|PP_OD_<br>INT2|PP_OD_<br>INT1|FIFO_EN|OFF_TCOMP<br>_EN| |---|---|---|---|---|---|---|---| **Table 13. CTRL_REG4 register description** ||**Table 13.CTRL_REG4 register description**| |---|---| |DSP_LP_TYPE|Digital filtering selection. Default value: 0<br>(0: FIR Linear Phase; 1: IIR Nonlinear Phase)| |DSP_BW_SEL|User-selectable bandwidth. Default value: 0<br>(0: 440 Hz typ.; 1: 235 Hz typ.)| |ST [2:1]|Self-test enable. Default value: 00<br>(00: Self-test disabled; Other: SeeTable 14. Self-test mode selection)| |PP_OD_INT2|Push-pull/open drain selection on INT2 pin. Default value: 0<br>(0: push-pull mode; 1: open drain mode)| |PP_OD_INT1|Push-pull/open drain selection on INT1 pin. Default value: 0<br>(0: push-pull mode; 1: open drain mode)| |FIFO_EN|FIFO memory enable. Default value: 0<br>(0: disabled; 1: enabled)| |OFF_TCOMP_EN|Offset temperature compensation enable. Default value: 0<br>(0: disabled; 1: enabled)| **DS12292** - **Rev 2** **page 19/31** **IIS3DHHC CTRL_REG5 (24h)** ## **Table 14. Self-test mode selection** |||**Table 14.Self-test mode selection**| |---|---|---| |ST2|ST1|Self-test mode| |0|0|Normal mode| |0|1|Positive sign self-test| |1|0|Negative sign self-test| |1|1|Not allowed| ## **7.5** ## **CTRL_REG5 (24h)** Control register 5 ## **Table 15. CTRL_REG5 register** |0(1)|0(1)|0(1)|0(1)|0(1)|0(1)|0(1)|FIFO_SPI_<br>HS_ON| |---|---|---|---|---|---|---|---| _1. These bits must be set to ‘0’ for correct operation of the device._ ## **Table 16. CTRL_REG5 register description** FIFO_SPI_HS_ON Enables the SPI high speed configuration for the FIFO block that is used to guarantee a minimum duration of the window in which writing operation of RAM output is blocked. This bit is recommended for SPI clock frequencies higher than 6 MHz. Default value: 0 (0: not enabled; 1: enabled) ## **7.6 OUT_TEMP_L (25h), OUT_TEMP_H (26h)** Temperature data output register. L and H registers together express a 16-bit word in two’s complement leftjustified. ## **Table 17. OUT_TEMP_L register** Temp3 Temp2 Temp1 Temp0 0 0 0 0 ## **Table 18. OUT_TEMP_H register** Temp11 Temp10 Temp9 Temp8 Temp7 Temp6 Temp5 Temp4 ## **Table 19. OUT_TEMP register description** |Temp [11:0]|Temperature sensor output data.<br>The value is expressed as two’s complement sign.<br>0 LSB represents T=25 °C ambient.| |---|---| **DS12292** - **Rev 2** **page 20/31** **IIS3DHHC STATUS (27h)** ## **7.7 STATUS (27h)** Status register (r) ## **Table 20. Status register** ZYXOR ZOR YOR XOR ZYXDA ZDA YDA XDA ## **Table 21. Status register description** ||**Table 21.Status register description**| |---|---| |ZYXOR|Logic OR of the single X-, Y- and Z-axis data overrun. Default value: 0<br>(0: no overrun has occurred; 1: a new set of data has overwritten the previous set)| |ZOR|Z-axis data overrun. Default value: 0<br>(0: no overrun has occurred; 1: new data for the Z-axis has overwritten the previous data)| |YOR|Y-axis data overrun. Default value: 0<br>(0: no overrun has occurred; 1: new data for the Y-axis has overwritten the previous data)| |XOR|X-axis data overrun. Default value: 0<br>(0: no overrun has occurred; 1: new data for the X-axis has overwritten the previous data)| |ZYXDA|Logic AND of the single X-, Y- and Z-axis new data available. Default value: 0<br>(0: a new set of data is not yet available; 1: a new set of data is available)| |ZDA|Z-axis new data available. Default value: 0<br>(0: new data for the Z-axis is not yet available; 1: new data for the Z-axis is available)| |YDA|Y-axis new data available. Default value: 0<br>(0: new data for the Y-axis is not yet available; 1: new data for the Y-axis is available)| |XDA|X-axis new data available. Default value: 0<br>(0: new data for the X-axis is not yet available; 1: new data for the X-axis is available)| ## **7.8 OUT_X (28h - 29h)** Linear acceleration sensor X-axis output register. The value is expressed as a 16-bit word in two’s complement. ## **7.9 OUT_Y (2Ah - 2Bh)** Linear acceleration sensor Y-axis output register. The value is expressed as a 16-bit word in two’s complement. ## **7.10 OUT_Z (2Ch - 2Dh)** Linear acceleration sensor Z-axis output register. The value is expressed as a 16-bit word in two’s complement. **DS12292** - **Rev 2** **page 21/31** **IIS3DHHC FIFO_CTRL (2Eh)** ## **7.11 FIFO_CTRL (2Eh)** FIFO control register ## **Table 22. FIFO_CTRL register** FMODE2 FMODE1 FMODE0 FTH4 FTH3 FTH2 FTH1 FTH0 ## **Table 23. FIFO_CTRL register description** ||**Table 23.FIFO_CTRL register description**| |---|---| |FMODE [2:0]|FIFO mode selection bits. Default value: 000<br>For further details refer toTable 24. FIFO mode selection.| |FTH [4:0]|FIFO threshold level setting. Default value: 0 0000| ## **Table 24. FIFO mode selection** |**FMODE2**|**FMODE1**|**FMODE0**|**Mode**| |---|---|---|---| |0|0|0|Bypass mode. FIFO turned off| |0|0|1|FIFO mode. Stops collecting data when FIFO is full.| |0|1|0|Reserved| |0|1|1|Continuous mode until trigger is asserted, then FIFO mode.| |1|0|0|Bypass mode until trigger is asserted, then Continuous mode.| |1|0|1|Reserved| |1|1|0|Continuous mode. If the FIFO is full, the new sample overwrites the older sample.| |1|1|1|Reserved| **DS12292** - **Rev 2** **page 22/31** **IIS3DHHC FIFO_SRC (2Fh)** ## **7.12 FIFO_SRC (2Fh)** FIFO status register ## **Table 25. FIFO_SRC register** |FTH|FTH|OVRN|FSS5|FSS4|FSS3|FSS2|FSS1|FSS0| |---|---|---|---|---|---|---|---|---| |||||||||| |FTH|FIFO threshold status.<br>(0: FIFO filling is lower than threshold level; 1: FIFO filling is equal to or higher than the threshold level|||||||| |OVRN|FIFO overrun status.<br>(0: FIFO is not completely filled; 1: FIFO is completely filled and at least one sample has been overwritten) For<br>further details refer toTable 26. FIFO_SRC example: OVR/FSS details.|||||||| |FSS [5:0]|Number of unread samples stored in FIFO.<br>(000000: FIFO empty; 100000: FIFO full, 32 unread samples)<br>For further details refer toTable 26. FIFO_SRC example: OVR/FSS details.|||||||| **Table 26. FIFO_SRC example: OVR/FSS details** |**FTH**|**OVRN**|**FSS5**|**FSS4**|**FSS3**|**FSS2**|**FSS1**|**FSS0**|**Description**| |---|---|---|---|---|---|---|---|---| |0|0|0|0|0|0|0|0|FIFO empty| |--(1)|0|0|0|0|0|0|1|1 unread sample| |...||||||||| |--(1)|0|1|0|0|0|0|0|32 unread samples| |0(1)|1|1|0|0|0|0|0|At least one sample has been overwritten| _1. When the number of unread samples in FIFO is equal to or greater than the threshold level set in register Section 7.11 FIFO_CTRL (2Eh), the FTH value is ‘1’._ The FSS is the FIFO stored data level of the unread samples. When it is equal to FTH, all data available in FIFO are read without additional read operations. The INT output is high when the number of samples to read is equal to or greater than FTH. **DS12292** - **Rev 2** **page 23/31** **IIS3DHHC FIFO_SRC (2Fh)** ## **Figure 17. Continuous mode: FTH/FSS details** **DS12292** - **Rev 2** **page 24/31** **IIS3DHHC Package information** ## **8 Package information** In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK[®] packages, depending on their level of environmental compliance. ECOPACK[®] specifications, grade definitions and product status are available at: www.st.com. ECOPACK[®] is an ST trademark. ## **8.1 LGA-16 package information** **Figure 18. Ceramic cavity LGA-16: package outline and mechanical data** **==> picture [434 x 253] intentionally omitted <==** **----- Start of picture text -----**<br> H<br>L<br>8535893_A<br>Pin 1<br>indicator<br>W<br>**----- End of picture text -----**<br> _Note: Top and bottom view: dimensions are expressed in mm_ ## **Table 27. Outer dimensions** |**ITEM**|**Dimension [mm]**|**Tolerance [mm]**| |---|---|---| |Length [L]|5|±0.15| |Width [W]|5|±0.15| |Height [H]|1.7 typ|±0.15| |Pad size|0.7 x 0.5|±0.15| _Note: General tolerance is ±0.1 mm unless otherwise specified_ **DS12292** - **Rev 2** **page 25/31** **IIS3DHHC** ## **Revision history** **Table 28. Document revision history** |**Date**|**Revision**|**Changes**| |---|---|---| |02-Oct-2017|1|Initial release| |19-Jan-2018|2|Added information concerning 10-year longevity commitment<br>UpdatedFigure 2. Recommended power-up sequence| **DS12292** - **Rev 2** **page 26/31** **IIS3DHHC Contents** |**Contents**|**Contents**|| |---|---|---| |**1**|**Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2**|| |**2**|**Mechanical and electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3**|| ||**2.1**|Mechanical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3| ||**2.2**|Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4| |||**2.2.1**<br>Recommended power-up sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4| ||**2.3**|Temperature sensor characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5| |**3**|**Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6**|| |**4**|**Communication interface characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7**|| ||**4.1**|SPI - serial peripheral interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7| ||**4.2**|SPI bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8| |||**4.2.1**<br>SPI read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9| |||**4.2.2**<br>SPI write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10| |**5**|**FIFO.**|**. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11**| ||**5.1**|Bypass mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11| ||**5.2**|FIFO mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11| ||**5.3**|Continuous mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13| ||**5.4**|Continuous-to-FIFO mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14| ||**5.5**|Bypass-to-Continuous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15| |**6**|**Register mapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16**|| |**7**|**Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17**|| ||**7.1**|CTRL_REG1 (20h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17| ||**7.2**|INT1_CTRL (21h). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18| ||**7.3**|INT2_CTRL (22h). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19| ||**7.4**|CTRL_REG4 (23h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19| ||**7.5**|CTRL_REG5 (24h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20| ||**7.6**|OUT_TEMP_L (25h), OUT_TEMP_H (26h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20| ||**7.7**|STATUS (27h). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21| ||**7.8**|OUT_X (28h - 29h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21| ||**7.9**|OUT_Y (2Ah - 2Bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21| **DS12292** - **Rev 2** **page 27/31** **IIS3DHHC Contents** ||**7.10**|OUT_Z (2Ch - 2Dh). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21| |---|---|---| ||**7.11**|FIFO_CTRL (2Eh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22| ||**7.12**|FIFO_SRC (2Fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23| |**8**|**Package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25**|| ||**8.1**|LGA-16 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25| |**Revision**||**history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26**| **DS12292** - **Rev 2** **page 28/31** **IIS3DHHC List of tables** ## **List of tables** |**Table**|**1.**|Pin description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2| |---|---|---| |**Table**|**2.**|Mechanical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3| |**Table**|**3.**|Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4| |**Table**|**4.**|Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5| |**Table**|**5.**|Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6| |**Table**|**6.**|SPI slave timing values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7| |**Table**|**7.**|Register mapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16| |**Table**|**8.**|CTRL_REG1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17| |**Table**|**9.**|CTRL_REG1 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17| |**Table**|**10.**|INT1_CTRL register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18| |**Table**|**11.**|INT2_CTRL register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19| |**Table**|**12.**|CTRL_REG4 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19| |**Table**|**13.**|CTRL_REG4 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19| |**Table**|**14.**|Self-test mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20| |**Table**|**15.**|CTRL_REG5 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20| |**Table**|**16.**|CTRL_REG5 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20| |**Table**|**17.**|OUT_TEMP_L register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20| |**Table**|**18.**|OUT_TEMP_H register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20| |**Table**|**19.**|OUT_TEMP register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20| |**Table**|**20.**|Status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21| |**Table**|**21.**|Status register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21| |**Table**|**22.**|FIFO_CTRL register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22| |**Table**|**23.**|FIFO_CTRL register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22| |**Table**|**24.**|FIFO mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22| |**Table**|**25.**|FIFO_SRC register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23| |**Table**|**26.**|FIFO_SRC example: OVR/FSS details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23| |**Table**|**27.**|Outer dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25| |**Table**|**28.**|Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26| **DS12292** - **Rev 2** **page 29/31** **IIS3DHHC List of figures** ## **List of figures** |**Figure**|**1.**|Pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2| |---|---|---| |**Figure**|**2.**|Recommended power-up sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4| |**Figure**|**4.**|SPI slave timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7| |**Figure**|**5.**|Read and write protocol. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8| |**Figure**|**6.**|SPI read protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9| |**Figure**|**7.**|Multiple byte SPI read protocol (2-byte example). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9| |**Figure**|**8.**|SPI write protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10| |**Figure**|**9.**|Multiple byte SPI write protocol (2-byte example) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10| |**Figure**|**10.**|Bypass mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11| |**Figure**|**11.**|FIFO mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12| |**Figure**|**12.**|Continuous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13| |**Figure**|**13.**|Continuous-to-FIFO mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14| |**Figure**|**14.**|External asynchronous trigger to FIFO for Continuous-to-FIFO mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14| |**Figure**|**15.**|Bypass-to-Continuous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15| |**Figure**|**16.**|External asynchronous trigger to FIFO for Bypass-to-Continuous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15| |**Figure**|**17.**|Continuous mode: FTH/FSS details. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24| |**Figure**|**18.**|Ceramic cavity LGA-16: package outline and mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25| **DS12292** - **Rev 2** **page 30/31** **IIS3DHHC** ## **IMPORTANT NOTICE – PLEASE READ CAREFULLY** STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. - © 2018 STMicroelectronics – All rights reserved **DS12292** - **Rev 2** **page 31/31**
Updated at April 22, 2026
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