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IIM-42652
MEMS Module, SmartIndustrial, Accelerometer, Gyroscope, X, Y, Z, 1.71 V, 3.6 V, LGA, 14 Pins
⚠️ Reference pricing provided. In case of supply shortages, we will connect you with our trusted procurement partners to ensure your project's continuity.
- Manufacturer: TDK INVENSENSE
- Product type: MEMS Modules
- MSL: MSL 1 - Unlimited
- SVHC: No SVHC (25-Jun-2025)
- No. of Pins: 14Pins
- Sensor Type: Accelerometer, Gyroscope
- Sensing Axis: X, Y, Z
- Product Range: -
- Output Interface: I2C, I3C, SPI
- Sensor Case Style: LGA
- Supply Voltage Max: 3.6V
- Supply Voltage Min: 1.71V
- MEMS Module Function: Tri-Axis Gyroscope, Tri-Axis Accelerometer
- Sensor Case / Package: LGA
- Operating Temperature Max: 105°C
- Operating Temperature Min: -40°C
- Sensing Range - Gyroscope: ± 15.625°/s, ± 31.25°/s, ± 62.5°/s, ± 125°/s, ± 250°/s, ± 500°/s, ± 1000°/s, ± 2000°/s
- Temperature Sensing Range: -
- Sensing Range - Accelerometer: ± 2g, ± 4g, ± 8g, ± 16g
| Delivery and price | |
|---|---|
| Units per pack | 500 |
| Price | 7.05 € |
| Current stock | 10+ |
| Lead time | 30 days |
Datasheet
_**IIM-42652 Datasheet**_
_**High-performance 6-Axis SmartIndustrial™ MotionTracking MEMS Device for Industrial Applications**_
## **GENERAL DESCRIPTION**
The IIM-42652 is a 6-axis SmartIndustrial™ MotionTracking device that supports an extended operating temperature range.
The IIM-42652 combines a 3-axis gyroscope, and a 3-axis accelerometer in a small 2.5 mm x 3 mm x 0.91 mm (14-pin LGA) package. It also features a 2 KB FIFO that can lower the traffic
on the serial bus interface and reduce power consumption by allowing the system processor to burst read sensor data and then go into a low-power mode.
## **FEATURES**
- Digital-output X-, Y-, and Z-axis angular rate sensors (gyroscopes) with programmable full-scale range of ±15.625, ±31.25, ±62.5, ±125, ±250, ±500, ±1000, and ±2000 degrees/sec
- Digital-output X-, Y-, and Z-axis accelerometer with programmable fullscale range of ±2 _g_ , ±4 _g_ , ±8 _g_ and ±16 _g_
- User-programmable interrupts
- I3C[SM] / I[2] C / SPI slave host interface
- Digital-output temperature sensor
- Small and thin package:
IIM-42652 supports highly accurate external clock input to reduce system level sensitivity error, improve orientation measurement from gyroscope data and to reduce ODR sensitivity to temperature and device to device variation.
- 2.5 mm x 3 mm x 0.91 mm (14-pin LGA)
- 20,000 _g_ shock tolerant
- MEMS structure hermetically sealed and bonded at wafer level
- MEMS structure hermetically sealed and bonded at wafer level
The host interface can be configured to support I3C[SM] slave, I[2] C slave, or SPI slave modes. The I3C[SM] interface supports speeds up to 12.5 MHz (data rates up to 12.5 Mbps in SDR mode, 25 Mbps in DDR mode), the I[2] C interface supports speeds up to 1 MHz, and the SPI interface supports speeds up to 24 MHz.
- RoHS and Green compliant
**TYPICAL OPERATING CIRCUIT**
**==> picture [512 x 172] intentionally omitted <==**
**----- Start of picture text -----**<br>
and the SPI interface supports speeds up to 24 MHz. AP_CS<br>The device features an operating voltage range from<br>3.6V down to 1.71V.<br>14 13 12<br>ORDERING INFORMATION AP_SDO 1 11 RESV<br>RESV 2 10 RESV<br>PART NUMBER TEMPERATURE PACKAGE ICM-42605 INT2 / FSYNC / CLKIN<br>RESV 3 IIM-42652 9<br>IIM-42652† −40°C to +105°C 14-pin LGA 1.71 – 3.6VDC<br>INT1 / INT 4 8 VDD<br>†Denotes RoHS and Green-compliant package 5 6 7<br>C1, 0.1 µF C2, 2.2 µF<br>APPLICATIONS<br>1.71 – 3.6VDC<br>• Navigation Tab C3, 10 nF :<br>AP<br>AP_SDI AP_SDIO / _ SCLK<br>VDDIO GND RESV<br>**----- End of picture text -----**<br>
The device features an operating voltage range from 3.6V down to 1.71V.
- Orientation measurement
- Tilt sensing
- Platform stabilization
- Robotics
## **Application Schematic (SPI Interface to Host)**
## **LONGEVITY COMMITMENT**
To provide the best service for customers developing products with a long-life cycle we have designed and engineered products with longevity in mind. These products are designed for harsher environments and are tested and manufactured to higher accuracy and stability. https://invensense.tdk.com/longevity/ ~~a~~
InvenSense, Inc. reserves the right to change specifications and information herein without notice unless the product is in mass production and the datasheet has been designated by InvenSense in writing as subject to a specified Product / Process Change Notification Method regulation.
Document Number: DS-000401 Revision: 1.3
**InvenSense, a TDK Group Company** 1745 Technology Drive, San Jose, CA 95110 U.S.A +1(408) 988–7339 invensense.tdk.com
Release Date: 02/14/2022
_**IIM-42652**_
## **TABLE OF CONTENTS**
||Longevity Commitment .........................................................................................**Error! Bookmark not defined.**|Longevity Commitment .........................................................................................**Error! Bookmark not defined.**|
|---|---|---|
||General Description ............................................................................................................................................. 1||
||Ordering Information .......................................................................................................................................... 1||
||Applications ......................................................................................................................................................... 1||
||Features ............................................................................................................................................................... 1||
||Typical Operating Circuit ..................................................................................................................................... 1||
|1|Introduction .......................................................................................................................................................... 9||
||1.1|Purpose and Scope ................................................................................................................................... 9|
||1.2|Product Overview ..................................................................................................................................... 9|
||1.3|Applications .............................................................................................................................................. 9|
|2|Features .............................................................................................................................................................. 10||
||2.1|Gyroscope Features ................................................................................................................................ 10|
||2.2|Accelerometer Features ......................................................................................................................... 10|
||2.3|Motion Features ..................................................................................................................................... 10|
||2.4|Additional Features ................................................................................................................................. 10|
|3|Electrical Characteristics ..................................................................................................................................... 11||
||3.1|Gyroscope Specifications ........................................................................................................................ 11|
||3.2|Accelerometer Specifications ................................................................................................................. 12|
||3.3|Electrical Specifications .......................................................................................................................... 13|
||3.4|I2C Timing Characterization .................................................................................................................... 15|
||3.5|SPI Timing Characterization – 4-Wire SPI Mode ..................................................................................... 16|
||3.6|SPI Timing Characterization – 3-Wire SPI Mode ..................................................................................... 17|
||3.7|RTC (CLKIN) Timing Characterization ...................................................................................................... 18|
||3.8|Absolute Maximum Ratings .................................................................................................................... 19|
|4|Applications Information .................................................................................................................................... 20||
||4.1|Pin Out Diagram and Signal Description ................................................................................................. 20|
||4.2|Typical Operating Circuit......................................................................................................................... 21|
||4.3|Bill of Materials for External Components .............................................................................................. 22|
||4.4|System Block Diagram ............................................................................................................................ 22|
||4.5|Overview ................................................................................................................................................. 23|
||4.6|Three-Axis MEMS Gyroscope with 16-bit ADCs and Signal Conditioning ............................................... 23|
||4.7|Three-Axis MEMS Accelerometer with 16-bit ADCs and Signal Conditioning ........................................ 23|
||4.8|I3CSM, I2C, and SPI Host Interface ............................................................................................................ 23|
||4.9|Self-Test .................................................................................................................................................. 23|
||4.10|Clocking .............................................................................................................................................. 24|
||4.11|Sensor Data Registers ......................................................................................................................... 24|
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||4.12|Interrupts ............................................................................................................................................ 24|
|---|---|---|
||4.13|Digital-Output Temperature Sensor ................................................................................................... 24|
||4.14|Bias and LDOs ..................................................................................................................................... 25|
||4.15|Charge Pump ...................................................................................................................................... 25|
||4.16|Standard Power Modes ...................................................................................................................... 25|
|5|Signal Path .......................................................................................................................................................... 26||
||5.1|Summary of Parameters Used to Configure the Signal Path .................................................................. 26|
||5.2|Notch Filter ............................................................................................................................................. 26|
||5.3|Anti-Alias Filter ....................................................................................................................................... 28|
||5.4|User Programmable Offset ..................................................................................................................... 30|
||5.5|UI Filter Block .......................................................................................................................................... 30|
||5.6|ODR And FSR Selection ........................................................................................................................... 36|
|6|FIFO ..................................................................................................................................................................... 38||
||6.1|Packet Structure ..................................................................................................................................... 38|
||6.2|FIFO Header ............................................................................................................................................ 40|
||6.3|Maximum FIFO Storage .......................................................................................................................... 41|
||6.4|FIFO Configuration Registers .................................................................................................................. 41|
|7|Programmable Interrupts ................................................................................................................................... 43||
|8|APEX Motion Functions ...................................................................................................................................... 44|APEX Motion Functions ...................................................................................................................................... 44|
||8.1|APEX ODR Support .................................................................................................................................. 44|
||8.2|DMP Power Save Mode .......................................................................................................................... 45|
||8.3|Pedometer Programming ....................................................................................................................... 45|
||8.4|Tilt Detection Programming .................................................................................................................... 46|
||8.5|Freefall Detection Programming ............................................................................................................. 47|
||8.6|Tap Detection Programming ................................................................................................................... 48|
||8.7|Wake on Motion Programming .............................................................................................................. 48|
||8.8|Significant Motion Detection Programming ........................................................................................... 49|
|9|Digital Interface .................................................................................................................................................. 51||
||9.1|I3CSM, I2C, and SPI Serial Interfaces ......................................................................................................... 51|
||9.2|I3CSMInterface ........................................................................................................................................ 51|
||9.3|I2C Interface ............................................................................................................................................ 51|
||9.4|I2C Communications Protocol ................................................................................................................. 51|
||9.5|I2C Terms ................................................................................................................................................. 54|
||9.6|SPI Interface ............................................................................................................................................ 54|
|10|Assembly ............................................................................................................................................................ 56||
||10.1|Orientation of Axes ............................................................................................................................ 56|
||10.2|Package Dimensions ........................................................................................................................... 57|
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_**IIM-42652**_
|11|Part Number Package Marking ........................................................................................................................... 59|Part Number Package Marking ........................................................................................................................... 59|
|---|---|---|
|12|Use Notes ........................................................................................................................................................... 60||
||12.1|Accelerometer Mode Transitions ....................................................................................................... 60|
||12.2|Accelerometer Low Power (LP) Mode Averaging Filter Setting ......................................................... 60|
||12.3|Settings for I2C, I3CSM, and SPI Operation ........................................................................................... 60|
||12.4|Notch Filter and Anti-Alias Filter Operation ....................................................................................... 60|
||12.5|external clock input effect on odr ...................................................................................................... 60|
||12.6|INT_ASYNC_RESET Configuration ....................................................................................................... 61|
||12.7|FIFO Timestamp Interval Scaling ........................................................................................................ 61|
||12.8|Supplementary Information for FIFO_HOLD_LAST_DATA_EN ........................................................... 61|
||12.9|Register Values Modification .............................................................................................................. 63|
|13|Register Map ...................................................................................................................................................... 64|Register Map ...................................................................................................................................................... 64|
||13.1|User Bank 0 Register Map .................................................................................................................. 64|
||13.2|User Bank 1 Register Map .................................................................................................................. 65|
||13.3|User Bank 2 Register Map .................................................................................................................. 66|
||13.4|User Bank 3 Register Map .................................................................................................................. 66|
||13.5|User Bank 4 Register Map .................................................................................................................. 66|
||13.6|Register Values Modification .............................................................................................................. 67|
|14|User Bank 0 Register Map – Descriptions ........................................................................................................... 68||
||14.1|DEVICE_CONFIG ................................................................................................................................. 68|
||14.2|DRIVE_CONFIG ................................................................................................................................... 68|
||14.3|INT_CONFIG ........................................................................................................................................ 69|
||14.4|FIFO_CONFIG ...................................................................................................................................... 69|
||14.5|TEMP_DATA1 ..................................................................................................................................... 69|
||14.6|TEMP_DATA0 ..................................................................................................................................... 70|
||14.7|ACCEL_DATA_X1 ................................................................................................................................. 70|
||14.8|ACCEL_DATA_X0 ................................................................................................................................. 70|
||14.9|ACCEL_DATA_Y1 ................................................................................................................................. 70|
||14.10|ACCEL_DATA_Y0 ................................................................................................................................. 71|
||14.11|ACCEL_DATA_Z1 ................................................................................................................................. 71|
||14.12|ACCEL_DATA_Z0 ................................................................................................................................. 71|
||14.13|GYRO_DATA_X1 .................................................................................................................................. 71|
||14.14|GYRO_DATA_X0 .................................................................................................................................. 71|
||14.15|GYRO_DATA_Y1 .................................................................................................................................. 72|
||14.16|GYRO_DATA_Y0 .................................................................................................................................. 72|
||14.17|GYRO_DATA_Z1 .................................................................................................................................. 72|
||14.18|GYRO_DATA_Z0 .................................................................................................................................. 72|
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Document Number: DS-000401 Revision: 1.3
_**IIM-42652**_
TMST_FSYNCH .................................................................................................................................... 72 TMST_FSYNCL ..................................................................................................................................... 73 INT_STATUS ........................................................................................................................................ 73 FIFO_COUNTH .................................................................................................................................... 73 FIFO_COUNTL ..................................................................................................................................... 74 FIFO_DATA .......................................................................................................................................... 74 APEX_DATA0 ...................................................................................................................................... 74 APEX_DATA1 ...................................................................................................................................... 74 APEX_DATA2 ...................................................................................................................................... 75 APEX_DATA3 ...................................................................................................................................... 75 APEX_DATA4 ...................................................................................................................................... 76 APEX_DATA5 ...................................................................................................................................... 76 INT_STATUS2 ...................................................................................................................................... 77 INT_STATUS3 ...................................................................................................................................... 77 SIGNAL_PATH_RESET ......................................................................................................................... 77 INTF_CONFIG0 .................................................................................................................................... 78 INTF_CONFIG1 .................................................................................................................................... 79 PWR_MGMT0 ..................................................................................................................................... 80 GYRO_CONFIG0 .................................................................................................................................. 81 ACCEL_CONFIG0 ................................................................................................................................. 82 GYRO_CONFIG1 .................................................................................................................................. 83 GYRO_ACCEL_CONFIG0 ...................................................................................................................... 84 ACCEL_CONFIG1 ................................................................................................................................. 85 TMST_CONFIG .................................................................................................................................... 85 APEX_CONFIG0 ................................................................................................................................... 86 SMD_CONFIG ..................................................................................................................................... 86 FIFO_CONFIG1 .................................................................................................................................... 87 FIFO_CONFIG2 .................................................................................................................................... 87 FIFO_CONFIG3 .................................................................................................................................... 87 FSYNC_CONFIG ................................................................................................................................... 88 INT_CONFIG0 ...................................................................................................................................... 88 INT_CONFIG1 ...................................................................................................................................... 89 INT_SOURCE0 ..................................................................................................................................... 89 INT_SOURCE1 ..................................................................................................................................... 90 INT_SOURCE3 ..................................................................................................................................... 90 INT_SOURCE4 ..................................................................................................................................... 91 FIFO_LOST_PKT0 ................................................................................................................................ 91
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_**IIM-42652**_
||14.56|FIFO_LOST_PKT1 ................................................................................................................................ 91|
|---|---|---|
||14.57|SELF_TEST_CONFIG ............................................................................................................................ 92|
||14.58|WHO_AM_I ........................................................................................................................................ 92|
||14.59|REG_BANK_SEL ................................................................................................................................... 92|
|15|User Bank 1 Register Map – Descriptions ........................................................................................................... 93||
||15.1|SENSOR_CONFIG0 .............................................................................................................................. 93|
||15.2|GYRO_CONFIG_STATIC2 ..................................................................................................................... 93|
||15.3|GYRO_CONFIG_STATIC3 ..................................................................................................................... 93|
||15.4|GYRO_CONFIG_STATIC4 ..................................................................................................................... 94|
||15.5|GYRO_CONFIG_STATIC5 ..................................................................................................................... 94|
||15.6|GYRO_CONFIG_STATIC6 ..................................................................................................................... 94|
||15.7|GYRO_CONFIG_STATIC7 ..................................................................................................................... 94|
||15.8|GYRO_CONFIG_STATIC8 ..................................................................................................................... 95|
||15.9|GYRO_CONFIG_STATIC9 ..................................................................................................................... 95|
||15.10|GYRO_CONFIG_STATIC10 ................................................................................................................... 95|
||15.11|XG_ST_DATA....................................................................................................................................... 96|
||15.12|YG_ST_DATA ....................................................................................................................................... 96|
||15.13|ZG_ST_DATA ....................................................................................................................................... 96|
||15.14|TMSTVAL0 .......................................................................................................................................... 96|
||15.15|TMSTVAL1 .......................................................................................................................................... 97|
||15.16|TMSTVAL2 .......................................................................................................................................... 97|
||15.17|INTF_CONFIG4 .................................................................................................................................... 97|
||15.18|INTF_CONFIG5 .................................................................................................................................... 98|
||15.19|INTF_CONFIG6 .................................................................................................................................... 98|
|16|User Bank 2 Register Map – Descriptions ........................................................................................................... 99||
||16.1|ACCEL_CONFIG_STATIC2 .................................................................................................................... 99|
||16.2|ACCEL_CONFIG_STATIC3 .................................................................................................................... 99|
||16.3|ACCEL_CONFIG_STATIC4 .................................................................................................................... 99|
||16.4|XA_ST_DATA ....................................................................................................................................... 99|
||16.5|YA_ST_DATA ..................................................................................................................................... 100|
||16.6|ZA_ST_DATA ..................................................................................................................................... 100|
|17|User Bank 3 Register Map – Descriptions ......................................................................................................... 101||
||17.1|PU_PD_CONFIG1 .............................................................................................................................. 101|
||17.2|PU_PD_CONFIG2 .............................................................................................................................. 102|
|18|User Bank 4 Register Map – Descriptions ......................................................................................................... 103||
||18.1|FDR_CONFIG ..................................................................................................................................... 103|
||18.2|APEX_CONFIG1 ................................................................................................................................. 103|
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||18.3|APEX_CONFIG2 ................................................................................................................................. 104|
|---|---|---|
||18.4|APEX_CONFIG3 ................................................................................................................................. 105|
||18.5|APEX_CONFIG4 ................................................................................................................................. 106|
||18.6|APEX_CONFIG5 ................................................................................................................................. 107|
||18.7|APEX_CONFIG6 ................................................................................................................................. 108|
||18.8|APEX_CONFIG7 ................................................................................................................................. 109|
||18.9|APEX_CONFIG8 ................................................................................................................................. 109|
||18.10|APEX_CONFIG9 ................................................................................................................................. 109|
||18.11|APEX_CONFIG10 ............................................................................................................................... 110|
||18.12|ACCEL_WOM_X_THR........................................................................................................................ 110|
||18.13|ACCEL_WOM_Y_THR ........................................................................................................................ 111|
||18.14|ACCEL_WOM_Z_THR ........................................................................................................................ 111|
||18.15|INT_SOURCE6 ................................................................................................................................... 111|
||18.16|INT_SOURCE7 ................................................................................................................................... 112|
||18.17|INT_SOURCE8 ................................................................................................................................... 112|
||18.18|INT_SOURCE9 ................................................................................................................................... 113|
||18.19|INT_SOURCE10 ................................................................................................................................. 113|
||18.20|OFFSET_USER0 ................................................................................................................................. 114|
||18.21|OFFSET_USER1 ................................................................................................................................. 114|
||18.22|OFFSET_USER2 ................................................................................................................................. 114|
||18.23|OFFSET_USER3 ................................................................................................................................. 114|
||18.24|OFFSET_USER4 ................................................................................................................................. 115|
||18.25|OFFSET_USER5 ................................................................................................................................. 115|
||18.26|OFFSET_USER6 ................................................................................................................................. 115|
||18.27|OFFSET_USER7 ................................................................................................................................. 115|
||18.28|OFFSET_USER8 ................................................................................................................................. 116|
|19|Reference ......................................................................................................................................................... 117||
|20|SmartIndustrial Family ...................................................................................................................................... 118||
|21|Revision History ................................................................................................................................................ 119|Revision History ................................................................................................................................................ 119|
Page 7 of 120
Document Number: DS-000401 Revision: 1.3
_**IIM-42652**_
## **TABLE OF FIGURES**
|Figure 1. I|Figure 1. I2C Bus Timing Diagram ...................................................................................................................................... 15|
|---|---|
|Figure 2. 4-Wire SPI Bus Timing Diagram ......................................................................................................................... 16|Figure 2. 4-Wire SPI Bus Timing Diagram ......................................................................................................................... 16|
|Figure 3. 3-Wire SPI Bus Timing Diagram ......................................................................................................................... 17|Figure 3. 3-Wire SPI Bus Timing Diagram ......................................................................................................................... 17|
|Figure 4. RTC Timing Diagram ........................................................................................................................................... 18|Figure 4. RTC Timing Diagram ........................................................................................................................................... 18|
|Figure 5. Pin Out Diagram for IIM-42652 2.5 mm x 3.0 mm x 0.91 mm LGA ................................................................... 21|Figure 5. Pin Out Diagram for IIM-42652 2.5 mm x 3.0 mm x 0.91 mm LGA ................................................................... 21|
|Figure 6. IIM-42652 Application Schematic (I3C|Figure 6. IIM-42652 Application Schematic (I3CSM/ I2C Interface to Host) ...................................................................... 21|
|Figure 7. IIM-42652 Application Schematic (SPI Interface to Host) .................................................................................. 22|Figure 7. IIM-42652 Application Schematic (SPI Interface to Host) .................................................................................. 22|
|Figure 8. IIM-42652 System Block Diagram ...................................................................................................................... 22|Figure 8. IIM-42652 System Block Diagram ...................................................................................................................... 22|
|Figure 9. IIM-42652 Signal Path ........................................................................................................................................ 26|Figure 9. IIM-42652 Signal Path ........................................................................................................................................ 26|
|Figure 10. FIFO Packet Structure ...................................................................................................................................... 38|Figure 10. FIFO Packet Structure ...................................................................................................................................... 38|
|Figure 11. Maximum FIFO Storage ................................................................................................................................... 41|Figure 11. Maximum FIFO Storage ................................................................................................................................... 41|
|Figure 12. START and STOP Conditions ............................................................................................................................ 52|Figure 12. START and STOP Conditions ............................................................................................................................ 52|
|Figure 13. Complete I|Figure 13. Complete I2C Data Transfer ............................................................................................................................. 52|
|Figure 14. Typical SPI Master/Slave Configuration ........................................................................................................... 55|Figure 14. Typical SPI Master/Slave Configuration ........................................................................................................... 55|
|Figure 15. Orientation of Axes of Sensitivity and Polarity of Rotation ............................................................................. 56|Figure 15. Orientation of Axes of Sensitivity and Polarity of Rotation ............................................................................. 56|
|Figure 16. Package Dimensions ........................................................................................................................................ 57|Figure 16. Package Dimensions ........................................................................................................................................ 57|
|Figure 17. Part Number Package Marking ........................................................................................................................ 59|Figure 17. Part Number Package Marking ........................................................................................................................ 59|
## **TABLE OF TABLES**
|Table 1. Gyroscope Specifications .................................................................................................................................... 11|Table 1. Gyroscope Specifications .................................................................................................................................... 11|
|---|---|
|Table 2. Accelerometer Specifications ............................................................................................................................. 12|Table 2. Accelerometer Specifications ............................................................................................................................. 12|
|Table 3. D.C. Electrical Characteristics .............................................................................................................................. 13|Table 3. D.C. Electrical Characteristics .............................................................................................................................. 13|
|Table 4. A.C. Electrical Characteristics .............................................................................................................................. 14|Table 4. A.C. Electrical Characteristics .............................................................................................................................. 14|
|Table 5. I|Table 5. I2C Timing Characteristics .................................................................................................................................... 15|
|Table 6. 4-Wire SPI Timing Characteristics (24-MHz Operation) ...................................................................................... 16|Table 6. 4-Wire SPI Timing Characteristics (24-MHz Operation) ...................................................................................... 16|
|Table 7. 3-Wire SPI Timing Characteristics (24-MHz Operation) ...................................................................................... 17|Table 7. 3-Wire SPI Timing Characteristics (24-MHz Operation) ...................................................................................... 17|
|Table 8. RTC Timing Characteristics .................................................................................................................................. 18|Table 8. RTC Timing Characteristics .................................................................................................................................. 18|
|Table 9. Absolute Maximum Ratings ................................................................................................................................ 19|Table 9. Absolute Maximum Ratings ................................................................................................................................ 19|
|Table 10. Signal Descriptions ............................................................................................................................................ 20|Table 10. Signal Descriptions ............................................................................................................................................ 20|
|Table 11. Bill of Materials ................................................................................................................................................. 22|Table 11. Bill of Materials ................................................................................................................................................. 22|
|Table 12. Standard Power Modes for IIM-42652 ............................................................................................................. 25|Table 12. Standard Power Modes for IIM-42652 ............................................................................................................. 25|
|Table 13. Signal path parameters ..................................................................................................................................... 26|Table 13. Signal path parameters ..................................................................................................................................... 26|
|Table 14. I|Table 14. I2C Terms ........................................................................................................................................................... 54|
Page 8 of 120
Document Number: DS-000401 Revision: 1.3
_**IIM-42652**_
## _**1 INTRODUCTION**_
## **PURPOSE AND SCOPE**
This document is a product specification, providing a description, specifications, and design related information on the IIM-42652 SmartIndustrial™ device. The device is housed in a small 2.5 mm x 3 mm x 0.91 mm 14-pin LGA package.
## **PRODUCT OVERVIEW**
The IIM-42652 is a 6-axis MotionTracking device that combines a 3-axis gyroscope, and a 3-axis accelerometer in a small 2.5 mm x 3 mm x 0.91 mm (14-pin LGA) package. It also features a 2 KB FIFO that can lower the traffic on the serial bus interface and reduce power consumption by allowing the system processor to burst read sensor data and then go into a low-power mode. IIM-42652, with its 6-axis integration, enables manufacturers to eliminate the costly and complex selection, qualification, and system level integration of discrete devices, guaranteeing optimal motion performance for customers.
The gyroscope supports eight programmable full-scale range settings from ±15.625 dps to ±2000 dps, and the accelerometer supports four programmable full-scale range settings from ±2g to ±16g. IIM-42652 also supports external clock input for highly accurate 31 kHz to 50 kHz clocks to reduce system level sensitivity error and reduce ODR sensitivity to temperature and device to device variation.
Other industry-leading features include on-chip 16-bit ADCs, programmable digital filters, an embedded temperature sensor, and programmable interrupts. The device features I3C[SM] , I[2] C, and SPI serial interfaces; a VDD operating range of 1.71V to 3.6V; and a separate VDDIO operating range of 1.71V to 3.6V.
The host interface can be configured to support I3C[SM] slave, I[2] C slave, or SPI slave modes. The I3C[SM] interface supports speeds up to 12.5 MHz (data rates up to 12.5 Mbps in SDR mode, 25 Mbps in DDR mode), the I[2] C interface supports speeds up to 1 MHz, and the SPI interface supports speeds up to 24 MHz.
IIM-42652 also supports external clock input for highly accurate 31 kHz to 50 kHz clocks to reduce system level sensitivity error, improve orientation measurement from gyroscope data, and reduce ODR sensitivity to temperature and device to device variation.
By leveraging its patented and volume-proven CMOS-MEMS fabrication platform, which integrates MEMS wafers with companion CMOS electronics through wafer-level bonding, InvenSense has driven the package size down to a footprint and thickness of 2.5 mm x 3 mm x 0.91 mm (14-pin LGA), to provide a very small yet high performance low cost package. The device provides high robustness by supporting 20,000 _g_ shock reliability.
## **APPLICATIONS**
- Navigation
- Orientation measurement
- Tilt sensing
- Platform stabilization
- Robotics
Page 9 of 120
Document Number: DS-000401 Revision: 1.3
_**IIM-42652**_
## _**2 FEATURES**_
## **GYROSCOPE FEATURES**
The triple-axis MEMS gyroscope in the IIM-42652 includes a wide range of features:
- Digital-output X-, Y-, and Z-axis angular rate sensors (gyroscopes) with programmable full-scale range of ±15.625, ±31.25, ±62.5, ±125, ±250, ±500, ±1000, and ±2000 degrees/sec
- Low Noise (LN) power mode support
- Digitally-programmable low-pass filters
- Factory calibrated sensitivity scale factor
- Self-test
## **ACCELEROMETER FEATURES**
The triple-axis MEMS accelerometer in IIM-42652 includes a wide range of features:
- Digital-output X-, Y-, and Z-axis accelerometer with programmable full-scale range of ±2 _g_ , ±4 _g_ , ±8 _g_ and ±16 _g_
- Low Noise (LN) and Low Power (LP) power modes support
- User-programmable interrupts
- Wake-on-motion interrupt for low power operation of applications processor
- Self-test
## **MOTION FEATURES**
IIM-42652 includes the following motion features, also known as APEX ( **A** dvanced **P** edometer and **E** vent Detection – ne **X** t gen)
- Pedometer: tracks step count, also issues step detect interrupt
- Tilt Detection: issues an interrupt when the tilt angle exceeds 35° for more than a programmable time
- Tap Detection: issues an interrupt when a tap is detected, along with the tap count
- Freefall Detection: triggers an interrupt when device freefall is detected and outputs freefall duration
- Wake on Motion: detects motion when accelerometer data exceeds a programmable threshold
- Significant Motion Detection: detects significant motion if wake on motion events are detected during a programmable time window
## **ADDITIONAL FEATURES**
IIM-42652 includes the following additional features:
- External clock input supports highly accurate clock input from 31 kHz to 50 kHz, helps to reduce system level sensitivity error
- 2 KB FIFO buffer enables the applications processor to read the data in bursts
- User-programmable digital filters for gyroscope, accelerometer, and temperature sensor
- User configurable internal pull-up/pull-downs included on I/O interfaces to reduce system costs associated with external pull-ups/pull-downs
- 12.5 MHz I3C[SM] (data rates up to 12.5 Mbps in SDR mode, 25Mbps in DDR mode) / 1 MHz I[2] C / 24 MHz SPI slave host interface
- Digital-output temperature sensor
- Smallest and thinnest LGA package for Industrial IoT applications: 2.5 mm x 3 mm x 0.91 mm (14-pin LGA)
- • 20,000 _g_ shock tolerant
- MEMS structure hermetically sealed and bonded at wafer level
- RoHS and Green compliant
Page 10 of 120
Document Number: DS-000401 Revision: 1.3
_**IIM-42652**_
## _**3 ELECTRICAL CHARACTERISTICS**_
## **GYROSCOPE SPECIFICATIONS**
Typical Operating Circuit of section 4.2, VDD = 1.8V, VDDIO = 1.8V, TA=25°C, unless otherwise noted.
|**PARAMETER**<br>~~Cn~~|**CONDITIONS**<br>~~es~~|**MIN**<br>~~es~~|**TYP**<br>~~es~~|**MAX**<br>~~es~~|**UNITS**<br>~~es~~|**NOTES**<br>~~es~~|
|---|---|---|---|---|---|---|
|**GYROSCOPE SENSITIVITY**<br>~~Cn~~<br>~~es~~|||||||
|Full-Scale Range<br>~~Cn~~|GYRO_FS_SEL=0<br>~~es~~|~~es~~|±2000<br>~~es~~|~~es~~|º/s<br>~~es~~|2<br>~~es~~|
||GYRO_FS_SEL =1<br>~~es~~<br>~~ss~~|~~es~~<br>~~ss~~|±1000<br>~~es~~<br>~~ss~~|~~es~~<br>~~ss~~|º/s<br>~~es~~<br>~~ss~~|2<br>~~es~~<br>~~ss~~|
||GYRO_FS_SEL =2<br>~~ss~~<br>~~ss~~|~~ss~~<br>~~ss~~<br>~~rs~~|±500<br>~~ss~~<br>~~ss~~<br>~~es~~|~~ss~~<br>~~ss~~<br>~~es~~|º/s<br>~~ss~~<br>~~ss~~|2<br>~~ss~~<br>~~ss~~|
||GYRO_FS_SEL =3<br>~~ss~~<br>~~es~~|~~ss~~<br>~~es~~<br>~~rs~~<br>~~es~~|±250<br>~~ss~~<br>~~es~~<br>~~es~~<br>~~es~~|~~ss~~<br>~~es~~<br>~~es~~<br>~~es~~|º/s<br>~~ss~~<br>~~es~~|2<br>~~ss~~<br>~~es~~|
||GYRO_FS_SEL =4<br>~~er~~|~~rs ~~<br>~~er~~<br>~~es~~<br>~~rs~~|±125<br> ~~es~~<br>~~er~~<br>~~es~~|~~es~~<br>~~er~~<br>~~es~~|º/s<br>~~er~~|2<br>~~er~~|
||GYRO_FS_SEL =5<br>~~rs~~|~~es~~<br>~~rs~~<br>~~rs~~<br>~~rs~~|±62.5<br>~~es~~<br>~~rs~~|~~es~~<br>~~rs~~|º/s<br>~~rs~~|2<br>~~rs~~|
||GYRO_FS_SEL =6<br>~~rs~~|~~rs~~<br>~~rs~~<br>~~rs~~<br>~~rs~~|±31.25<br>~~rs~~|~~rs~~|º/s<br>~~rs~~|2<br>~~rs~~|
||GYRO_FS_SEL =7<br>~~rs~~|~~rs~~<br>~~rs~~<br>~~rs~~<br>~~GQ~~|±15.625<br>~~rs~~<br>~~GQ~~|~~rs~~<br>~~QO~~|º/s<br>~~rs~~|2<br>~~rs~~|
|Gyroscope ADC Word Length<br>~~eG~~|~~eG~~|~~rs~~<br>~~eG~~<br>~~GQ~~|16<br>~~eG~~<br>~~GQ~~|~~eG~~<br>~~QO~~|bits<br>~~eG~~|2,6<br>~~eG~~|
|Sensitivity Scale Factor<br>~~eG~~|GYRO_FS_SEL=0<br>~~eG~~<br>~~es~~|~~eG~~<br>~~GQ~~<br>~~es~~<br>~~rs~~|16.4<br>~~eG~~<br>~~GQ~~<br>~~es~~|~~eG~~<br>~~QO~~<br>~~es~~|LSB/(º/s)<br>~~eG~~<br>~~es~~|2<br>~~eG~~<br>~~es~~|
||GYRO_FS_SEL =1<br>~~es~~<br>~~ee~~|~~es~~<br>~~ee~~<br>~~rs~~|32.8<br>~~es~~<br>~~ee~~|~~es~~<br>~~ee~~|LSB/(º/s)<br>~~es~~<br>~~ee~~|2<br>~~es~~<br>~~ee~~|
||GYRO_FS_SEL =2<br>~~ee~~<br>~~es~~|~~ee~~<br>~~rs~~<br>~~es~~<br>~~es~~|65.5<br>~~ee~~<br>~~es~~<br>~~es~~|~~ee~~<br>~~es~~<br>~~es~~|LSB/(º/s)<br>~~ee~~<br>~~es~~|2<br>~~ee~~<br>~~es~~|
||GYRO_FS_SEL =3<br>~~es~~<br>~~rs~~|~~es~~<br>~~rs~~<br>~~es~~<br>~~es~~|131<br>~~es~~<br>~~rs~~<br>~~es~~<br>~~es~~|~~es~~<br>~~rs~~<br>~~es~~<br>~~es~~|LSB/(º/s)<br>~~es~~<br>~~rs~~|2<br>~~es~~<br>~~rs~~|
||GYRO_FS_SEL =4<br>~~er~~|~~es ~~<br>~~er~~<br>~~es~~<br>~~es~~|262<br> ~~es~~<br>~~er~~<br>~~es~~<br>~~es~~|~~es~~<br>~~er~~<br>~~es~~<br>~~es~~|LSB/(º/s)<br>~~er~~|2<br>~~er~~|
||GYRO_FS_SEL =5<br>~~er~~|~~es~~<br>~~er~~<br>~~es~~<br>~~rs~~|524.3<br>~~es~~<br>~~er~~<br>~~es~~|~~es~~<br>~~er~~<br>~~es~~|LSB/(º/s)<br>~~er~~|2<br>~~er~~|
||GYRO_FS_SEL =6<br>~~rs~~|~~es~~<br>~~rs~~<br>~~rs~~<br>~~rs~~|1048.6<br>~~es~~<br>~~rs~~|~~es~~<br>~~rs~~|LSB/(º/s)<br>~~rs~~|2<br>~~rs~~|
||GYRO_FS_SEL =7<br>~~rs~~|~~rs~~<br>~~rs~~<br>~~rs~~<br>~~GQ~~|2097.2<br>~~rs~~<br>~~GQ~~|~~rs~~<br>~~QO~~|LSB/(º/s)<br>~~rs~~|2<br>~~rs~~|
|SensitivityScale Factor Initial Tolerance<br>~~eG~~|25°C<br>~~eG~~<br>~~ee~~|-1<br>~~rs~~<br>~~eG~~<br>~~GQ~~<br>~~es~~|±0.5<br>~~eG~~<br>~~GQ~~|+1<br>~~eG~~<br>~~QO~~|%<br>~~eG~~|1, 5<br>~~eG~~|
|Sensitivity Scale Factor Variation Over<br>Temperature<br>~~eG~~<br>~~es~~<br>~~pe~~|-40°C to +105°C<br>~~eG~~<br>~~es~~<br>~~ee~~<br>|-0.02<br>~~eG~~<br>~~GQ~~<br>~~es~~<br>~~es~~<br>|±0.005<br>~~eG~~<br>~~GQ~~<br>~~es~~<br>|+0.02<br>~~eG~~<br>~~QO~~<br>~~es~~<br>~~GO~~<br>|%/ºC<br>~~eG~~<br>~~es~~<br>|3, 5<br>~~eG~~<br>~~es~~<br>|
|Nonlinearity<br>~~GGG~~<br>~~pe~~|Best fit straight line; 25°C<br>~~ee~~<br>~~GGG~~<br>|-0.2<br>~~es~~<br>~~GGG~~<br>|±0.1<br>~~GGG~~<br>|+0.2<br>~~GGG~~<br>~~GO~~<br>|%<br>~~GGG~~<br>|3, 5<br>~~GGG~~<br>|
|Cross-Axis Sensitivity<br>~~pe~~||-3.0<br>|±1.25<br>|+3.0<br>~~GO~~<br>|%<br>|3, 5<br>|
|**ZERO-RATE OUTPUT (ZRO)**<br>~~GO~~<br>~~pea~~|||||||
|Initial ZRO Tolerance<br>~~a~~<br>~~|~~<br>~~es~~|Board-level, 25°C<br>~~a~~<br>~~|~~<br>~~QQ~~|-3<br>~~a~~<br>~~|~~<br>~~QQ~~|±0.5<br>~~a~~<br>~~|~~<br>~~QQ~~|+3<br>~~a~~<br>~~|~~<br>~~GO~~|º/s<br>~~a~~<br>~~|~~|3, 5<br>~~a~~<br>~~|~~|
|ZRO Variation vs. Temperature<br>~~|~~<br>~~es~~<br>~~Cn~~|-40°C to +105°C<br>~~|~~<br>~~QQ~~|-0.025<br>~~|~~<br>~~QQ~~|±0.02<br>~~|~~<br>~~QQ~~|+0.025<br>~~|~~<br>~~GO~~|º/s/ºC<br>~~|~~|3, 5<br>~~|~~|
|**OTHER PARAMETERS**<br>~~es~~<br>~~QQ~~<br>~~GO~~<br>~~Cn~~<br>~~QO(OO~~|||||||
|Rate Noise Spectral Density<br>~~Cn~~<br>~~es~~|@ 10 Hz<br>~~es~~<br>~~QO~~<br>~~QO~~|~~es~~<br>~~QO~~<br>~~QO~~|0.0038<br>~~es~~<br>~~(OO~~<br>~~QQ~~|0.0052<br>~~es~~<br>~~(OO~~<br>~~QQ~~|º/s /√Hz<br>~~es~~<br>~~QQ~~|1, 5<br>~~es~~|
|Total RMS Noise<br>~~es~~<br>~~a~~|Bandwidth = 100 Hz<br>~~QO~~<br>~~es~~<br>~~QO~~<br>~~QO~~|~~QO ~~<br>~~es~~<br>~~QO~~<br>~~QO~~|0.038<br> ~~(OO~~<br>~~es~~<br>~~QQ~~<br>~~QQ~~|0.052<br>~~(OO~~<br>~~es~~<br>~~QQ~~<br>~~QQ~~|º/s-rms<br>~~es~~<br>~~QQ~~<br>~~QQ~~|4, 5<br>~~es~~|
|Gyroscope Mechanical Frequencies<br>~~es~~<br>~~a~~|~~QO~~<br>~~es~~<br>~~QO~~<br>~~nn~~|25<br>~~QO ~~<br>~~es~~<br>~~QO~~|27<br> ~~QQ~~<br>~~es~~<br>~~QQ~~|29<br>~~QQ~~<br>~~es~~<br>~~QQ~~|KHz<br>~~QQ~~<br>~~es~~<br>~~QQ~~|1<br>~~es~~|
|Low Pass Filter Response<br>~~a~~|ODR < 1 kHz<br>~~QO~~<br>~~nn~~|5<br>~~QO~~|~~QQ~~|500<br>~~QQ~~|Hz<br>~~QQ~~|2|
||ODR ≥ 1 kHz<br>~~QO~~<br>~~nn~~|42<br>~~QO ~~|~~QQ~~|3979<br>~~QQ~~|Hz<br>~~QQ~~|2|
|Gyroscope Start-UpTime|Time fromgyro enable togyro drive ready<br>~~nn~~||30|45|ms|3,5|
|Output Data Rate<br>~~QQ~~|~~QQ~~|12.5<br>~~QQ~~|~~QQ~~|32000<br>~~QQ~~|Hz<br>~~QQ~~|2<br>~~QQ~~|
## **Table 1. Gyroscope Specifications**
**Notes:**
1. Tested in production.
2. Guaranteed by design.
3. Derived from validation or characterization of parts, not tested in production.
4. Calculated from Rate Noise Spectral Density.
5. MIN/MAX or MAX specs are derived from characterization data based 3σ calculation.
6. 20-bits data format supported in FIFO, see section 6.1.
Page 11 of 120
Document Number: DS-000401 Revision: 1.3
_**IIM-42652**_
## **ACCELEROMETER SPECIFICATIONS**
Typical Operating Circuit of section 4.2, VDD = 1.8V, VDDIO = 1.8V, TA=25°C, unless otherwise noted.
|**PARAMETER**|**CONDITIONS**|**MIN**|**TYP**|**MAX**|**UNITS**|**NOTES**|
|---|---|---|---|---|---|---|
|**ACCELEROMETER SENSITIVITY**<br>~~|~~|||||||
|Full-Scale Range<br>~~—————-___-——~~|ACCEL_FS_SEL =0<br>~~—————-___-——~~|~~—————-___-——~~|±16<br>~~—————-___-——~~|~~—————-___-——~~|_g_<br>~~—————-___-——~~|2<br>~~—————-___-——~~|
||ACCEL_FS_SEL =1<br>~~—————-___-——~~|~~—————-___-——~~|±8<br>~~—————-___-——~~|~~—————-___-——~~|_g_<br>~~—————-___-——~~|2<br>~~—————-___-——~~|
||ACCEL_FS_SEL =2<br>~~—————-___-——~~<br>~~tt~~|~~—————-___-——~~<br>~~tt~~|±4<br>~~—————-___-——~~<br>~~tt~~|~~—————-___-——~~<br>~~tt~~|_g_<br>~~—————-___-——~~<br>~~tt~~|2<br>~~—————-___-——~~<br>~~tt~~|
||ACCEL_FS_SEL =3<br>~~—————-___-——~~<br>~~tt~~|~~—————-___-——~~<br>~~tt~~|±2<br>~~—————-___-——~~<br>~~tt~~|~~—————-___-——~~<br>~~tt~~|_g_<br>~~—————-___-——~~<br>~~tt~~|2<br>~~—————-___-——~~<br>~~tt~~|
|ADC Word Length<br>~~—————-___-——~~<br>~~ee ee~~|Output in two’s complement format<br>~~—————-___-——~~<br>~~tt~~<br>~~ee~~|~~—————-___-——~~<br>~~tt~~<br>~~ee~~|16<br>~~—————-___-——~~<br>~~tt~~<br>~~ee~~|~~—————-___-——~~<br>~~tt~~<br>|bits<br>~~—————-___-——~~<br>~~tt~~<br>~~ee~~|2, 6<br>~~—————-___-——~~<br>~~tt~~<br>~~ee~~|
|Sensitivity Scale Factor<br>~~ee ee~~<br>~~pt~~|ACCEL_FS_SEL =0<br>~~ee~~|~~ee~~|2,048<br>~~ee~~||LSB/_g_<br>~~ee~~|2<br>~~ee~~|
||ACCEL_FS_SEL =1<br>~~ee~~|~~ee~~|4,096<br>~~ee~~||LSB/_g_<br>~~ee~~|2<br>~~ee~~|
||ACCEL_FS_SEL =2<br>~~ee~~|~~ee~~|8,192<br>~~ee~~||LSB/_g_<br>~~ee~~|2<br>~~ee~~|
||ACCEL_FS_SEL =3<br>~~ee~~<br>~~pt~~|~~ee~~<br>~~pt~~|16,384<br>~~ee~~<br>~~pt~~|~~pt~~|LSB/_g_<br>~~ee~~<br>~~pt~~|2<br>~~ee~~<br>~~pt~~|
|Sensitivity Scale Factor Initial Tolerance<br>~~ee ee~~<br>~~pt~~|Component-level<br>~~ee ~~<br>~~pt~~|-1<br> ~~ee~~<br>~~pt~~|±0.5<br>~~ee ~~<br>~~pt~~|+1<br> <br>~~pt~~|%<br> ~~ee~~<br>~~pt~~|1, 5<br>~~ee~~<br>~~pt~~|
|Sensitivity Change vs. Temperature<br>~~Gs~~|-40°C to +105°C<br>~~Gs~~|-0.025<br>~~Gs~~|±0.005<br>~~Gs~~|+0.025<br>~~Gs~~|%/ºC<br>~~Gs~~|3, 5<br>~~Gs~~|
|Nonlinearity<br>~~Gs~~<br>~~ot~~|Best Fit Straight Line, ±2g<br>~~Gs~~<br>~~ot~~|-0.2<br>~~Gs~~<br>~~ot~~|±0.1<br>~~Gs~~<br>~~ot~~|+0.2<br>~~Gs~~<br>~~ot~~|%<br>~~Gs~~<br>~~ot~~|3, 5<br>~~Gs~~<br>~~ot~~|
|Cross-Axis Sensitivity<br>~~ot~~<br>~~———~~|~~ot~~|-2.0<br>~~ot~~|±1<br>~~ot~~|+2.0<br>~~ot~~|%<br>~~ot~~|3, 5<br>~~ot~~|
|**ZERO-G OUTPUT**<br>~~ot~~<br>~~———~~|||||||
|Initial Tolerance<br>~~———~~|Board-level, all axes|-30|±20|+30|m_g_|3, 5|
|Zero-G Level Change vs. Temperature<br>~~———~~|-40°C to +105°C|-0.40|±0.15|+0.40|m_g/_ºC|3, 5|
|**OTHER PARAMETERS**<br>~~———~~<br>~~—————————~~|||||||
|Power Spectral Density<br>~~—————————~~|@ 10 Hz<br>~~———————~~|~~———————~~|70<br>~~———————~~|100<br>~~———————~~|µ_g_/√Hz<br>~~———————~~|1, 5<br>~~———————~~|
|RMS Noise<br>~~—————————~~|Bandwidth = 100 Hz<br>~~———————~~|~~———————~~|0.70<br>~~———————~~|1.00<br>~~———————~~|mg-rms<br>~~———————~~|4, 5<br>~~———————~~|
|Low-Pass Filter Response<br>~~—————————~~<br>~~SS~~|ODR < 1 kHz<br>~~———————~~<br>~~SS~~|5<br>~~———————~~<br>~~SS~~|~~———————~~<br>~~SS~~|500<br>~~———————~~<br>~~SS~~|Hz<br>~~———————~~<br>~~SS~~|2<br>~~———————~~<br>~~SS~~|
||ODR ≥ 1 kHz<br>~~SS~~|42<br>~~SS~~|~~SS~~|3979<br>~~SS~~|Hz<br>~~SS~~|2<br>~~SS~~|
|Accelerometer StartupTime<br>~~SS~~|From sleepmode to valid data<br>~~SS~~|~~SS~~|10<br>~~SS~~|20<br>~~SS~~|ms<br>~~SS~~|3,5<br>~~SS~~|
|Output Data Rate<br>~~NO~~|~~NO~~|12.5<br>~~NO~~|~~NO~~|32000<br>~~NO~~|Hz<br>~~NO~~|2<br>~~NO~~|
**Table 2. Accelerometer Specifications**
## **Notes:**
1. Tested in production.
2. Guaranteed by design.
3. Derived from validation or characterization of parts, not tested in production.
4. Calculated from Power Spectral Density.
5. MIN/MAX or MAX specs are derived from characterization data based 3σ calculation.
6. 20-bits data format supported in FIFO, see section 6.1.
Page 12 of 120
Document Number: DS-000401 Revision: 1.3
_**IIM-42652**_
## **ELECTRICAL SPECIFICATIONS**
## **D.C. Electrical Characteristics**
|**PARAMETER**<br>|**CONDITIONS**<br>|**MIN**<br>|**TYP**<br>|**MAX**<br>|**UNITS**<br>|**NOTES**<br>|
|---|---|---|---|---|---|---|
|**SUPPLY VOLTAGES**<br>~~|~~|||||||
|VDD<br>~~sf~~|~~sf~~|1.71<br>~~sf~~|1.8<br>~~sf~~|3.6<br>~~sf~~|V<br>~~sf~~|1<br>~~sf~~|
|VDDIO<br>~~Fe~~|~~Fe~~|1.71<br>~~Fe~~|1.8<br>~~Fe~~|3.6<br>~~Fe~~|V<br>~~Fe~~|1<br>~~Fe~~|
|**SUPPLY CURRENTS**<br>~~|~~|||||||
|Low-Noise Mode<br>~~|~~|6-Axis Gyroscope + Accelerometer<br>~~|~~<br>~~es~~|~~|~~<br>~~es~~<br>~~Ge~~|0.88<br>~~|~~<br>~~es~~<br>~~ss~~|0.95<br>~~|~~<br>~~es~~<br>~~ss~~|mA<br>~~|~~<br>~~es~~|2, 3<br>~~|~~<br>~~es~~|
||3-Axis Accelerometer<br>~~es~~<br>~~es~~|~~es~~<br>~~es~~<br>~~Ge~~|0.28<br>~~es~~<br>~~es~~<br>~~ss~~|0.35<br>~~es~~<br>~~es~~<br>~~ss~~|mA<br>~~es~~<br>~~es~~|2, 3<br>~~es~~<br>~~es~~|
||3-Axis Gyroscope<br>~~es~~|~~Ge ~~<br>~~es~~|0.73<br> ~~ss~~<br>~~es~~|0.85<br>~~ss~~<br>~~es~~|mA<br>~~es~~|2, 3<br>~~es~~|
|Full-ChipSleepMode<br>~~Qe~~|At 25ºC<br>~~Qe~~|~~Qe~~|7.5<br>~~Qe~~|10<br>~~Qe~~|µA<br>~~Qe~~|2, 3<br>~~Qe~~|
|**TEMPERATURE RANGE**<br>~~|~~|||||||
|Specified Temperature Range<br>~~es~~|Performance parameters are not applicable<br>beyond Specified Temperature Range<br>~~es~~|-40<br>~~es~~|~~es~~|+105<br>~~es~~|°C<br>~~es~~|2<br>~~es~~|
**Table 3. D.C. Electrical Characteristics**
- **Notes:** 1. Guaranteed by design. 2. Derived from validation or characterization of parts, not tested in production.
3. MIN/MAX or MAX specs are derived from characterization data based 3σ calculation.
Page 13 of 120
Document Number: DS-000401 Revision: 1.3
_**IIM-42652**_
## **A.C. Electrical Characteristics**
Typical Operating Circuit of section 4.2, VDD = 1.8V, VDDIO = 1.8V, TA=25°C, unless otherwise noted.
|**PARAMETER**<br>~~Ce~~|**CONDITIONS**<br>|**MIN**<br>|**TYP**<br>|**MAX**<br>|**UNITS**<br>|**NOTES**<br>|
|---|---|---|---|---|---|---|
|**SUPPLIES**<br>~~Ceeserrs~~<br>~~**r**srsrs~~<br>~~ee~~|||||||
|Supply Ramp Time<br>~~Cees~~<br>~~ee~~|Monotonic ramp. Ramp rate is 10% to 90% of<br>the final value<br>~~errs~~<br>~~rs~~|0.01<br>~~errs~~<br>~~**r**s~~<br>~~err~~|~~errs~~<br>~~rs~~<br>~~rs es~~|3<br>~~errs~~<br>~~rs~~<br>~~es~~|ms<br>~~errs~~<br>~~es~~|1<br>~~errs~~|
|Power Supply Noise<br>~~es~~<br>~~ee~~|Up to 10 kHz<br>~~errs~~<br>~~rs~~|~~errs~~<br>~~**r**s~~<br>~~err~~|10<br>~~errs~~<br>~~rs~~<br>~~rs es~~|50<br>~~errs~~<br>~~rs~~<br>~~es~~|mV<br>peak-peak<br>~~errs~~<br>~~es~~|1<br>~~errs~~|
|**TEMPERATURE SENSOR**<br>~~**r**s rs rs~~<br>~~ee~~<br>~~rs er r~~<br>~~rs es~~<br>~~es~~<br>~~Ce~~<br>~~CG~~<br>~~a~~|||||||
|OperatingRange<br>~~GOO~~<br>~~a~~<br>~~a~~|Ambient<br>~~GOO~~|-40<br>~~GOO~~|~~GOO~~|105<br>~~GOO~~<br>~~CG~~<br>~~GO~~|°C<br>~~GOO~~<br>~~CG~~<br>~~GO~~|2<br>~~GOO~~<br>~~|~~|
|25°C Output<br>~~GOO~~<br>~~a~~<br>~~a~~|~~GOO~~<br>~~OO~~|~~GOO~~<br>~~OO~~|0<br>~~GOO~~<br>~~OO~~|~~GOO~~<br>~~CG~~<br>~~OO~~<br>~~GO~~|LSB<br>~~GOO~~<br>~~CG~~<br>~~OO~~<br>~~GO~~|3<br>~~GOO~~<br>~~OO~~<br>~~|~~|
|ADC Resolution<br>~~a~~<br>~~a~~|~~OO~~|~~OO~~|16<br>~~OO~~<br>~~GOOG~~|~~GO~~<br>~~OO~~<br>~~GOOG~~|bits<br>~~GO~~<br>~~OO~~<br>~~GOOG~~|2<br>~~|~~<br>~~OO~~|
|ODR<br>~~GC~~<br>~~a~~<br>~~RR~~|With Filter<br>~~GC~~|25<br>~~GC~~|~~GC~~<br>~~GOOG~~|8000<br>~~GC~~<br>~~GOOG~~<br>~~GO~~|Hz<br>~~GC~~<br>~~GOOG~~<br>~~GO~~|2<br>~~GC~~<br>~~**|**~~|
|Room Temperature Offset<br>~~GC~~<br>~~a~~<br>~~RR~~|25°C<br>~~GC~~<br>~~OO~~|-5<br>~~GC~~<br>~~OO~~|~~GC~~<br>~~GOOG~~<br>~~OO~~|5<br>~~GC~~<br>~~GOOG~~<br>~~OO~~<br>~~GO~~|°C<br>~~GC~~<br>~~GOOG~~<br>~~OO~~<br>~~GO~~|3<br>~~GC~~<br>~~OO~~<br>~~**|**~~|
|Stabilization Time<br>~~RR~~|~~OO~~|~~OO~~|~~OO~~<br>~~GO~~|14000<br>~~GO~~<br>~~OO~~<br>~~GO~~|µs<br>~~GO~~<br>~~OO~~|2<br>~~**|**~~<br>~~OO~~|
|Sensitivity<br>~~RR~~<br>~~GO~~|Untrimmed<br>~~GO~~|~~GO~~|132.48<br>~~GO~~<br>~~GO~~|~~GO~~<br>~~GO~~<br>~~GO~~|LSB/°C<br>~~GO~~<br>~~GO~~|1<br>~~**|**~~<br>~~GO~~<br>~~|~~|
|Sensitivityfor FIFO data<br>~~GO~~<br>~~CO~~|~~GO~~<br>~~CO~~|~~GO~~<br>~~CO~~|2.07<br>~~GO~~<br>~~GO~~<br>~~CO~~|~~GO~~<br>~~GO~~<br>~~CO~~|LSB/°C<br>~~GO~~<br>~~CO~~|1<br>~~GO~~<br>~~CO~~<br>~~|~~|
|**POWER-ON RESET**<br>~~|~~<br>~~TTT~~|||||||
|Start-uptime for register read/write<br>~~RG~~|Frompower-up<br>~~RG~~|~~GG~~|~~GG~~|1|ms|1|
|**I2C ADDRESS**<br>~~RG~~<br>~~GG~~<br>~~eeers~~<br>~~rsrsrs~~<br>~~Ce~~|||||||
|**I2C ADDRESS**<br>~~ee~~<br>~~Ce~~|AP_AD0 = 0<br>AP_AD0 = 1<br>~~ers~~<br>|~~ers~~<br>~~rs~~<br>|1101000<br>1101001<br>~~ers~~<br>~~rs~~<br>|~~ers~~<br>~~rs~~<br>|~~ers~~<br>|~~ers~~|
|**DIGITAL INPUTS(FSYNC, SCLK, SDI, CS)**<br>~~eeers~~<br>~~rsrsrs~~<br>~~Ce~~<br>~~—~~<br>~~ee~~|||||||
|VIH, High Level Input Voltage<br>~~CesO~~<br>~~—~~|~~sO~~|0.7*VDDIO<br>~~rs ~~<br>~~sO~~<br>~~ee~~|~~rs ~~<br>~~sO~~<br>~~ee~~|~~rs~~<br>~~sO~~<br>~~ee~~|V<br>~~sO~~<br>~~ee~~|1<br>~~ee~~|
|VIL, Low Level Input Voltage<br>~~sO~~<br>~~—~~<br>~~Rs~~|~~sO~~<br>~~nC~~|~~sO~~<br>~~ee~~<br>~~nC~~|~~sO~~<br>~~ee~~|0.3*VDDIO<br>~~sO~~<br>~~ee~~|V<br>~~sO~~<br>~~ee~~||
|CI, Input Capacitance<br>~~—~~<br>~~Rs~~|~~nC~~|~~ee~~<br>~~nC~~|< 10<br>~~ee~~|~~ee~~|pF<br>~~ee~~||
|Input Leakage Current<br>~~—~~<br>~~Rs~~<br>~~es~~<br>~~Cn~~|~~nC~~<br>~~es~~<br>|~~ee~~<br>~~nC~~<br>~~es~~<br>|100<br>~~ee~~<br>~~es~~<br>|~~ee~~<br>~~es~~<br>|nA<br>~~ee~~<br>~~es~~<br>||
|**DIGITAL OUTPUT(SDO, INT1, INT2)**<br>~~—~~<br>~~ee~~<br>~~Cn~~<br>~~——~~|||||||
|VOH, High Level Output Voltage<br>~~CneG~~<br>~~——~~|RLOAD=1 MΩ;<br>~~eG~~|0.9*VDDIO<br>~~eG~~|~~eG~~|~~eG~~|V<br>~~eG~~|1|
|VOL1, LOW-Level Output Voltage<br>~~eG~~<br>~~dG~~<br>~~——~~|RLOAD=1 MΩ;<br>~~eG~~<br>~~dG~~|~~eG~~<br>~~dG~~|~~eG~~<br>~~dG~~|0.1*VDDIO<br>~~eG~~<br>~~dG~~|V<br>~~eG~~<br>~~dG~~||
|VOL.INT, INT Low-Level Output Voltage<br>~~dG~~<br>~~——~~|OPEN=1, 0.3 mA sink<br>Current<br>~~dG~~<br>~~Q~~|~~dG~~<br>~~Q~~|~~dG~~|0.1<br>~~dG~~|V<br>~~dG~~||
|Output Leakage Current<br>~~——~~<br>~~Rn~~|OPEN=1<br>~~Rn~~<br>~~Q~~|~~Rn~~<br>~~Q~~|100<br>~~Rn~~|~~Rn~~|nA<br>~~Rn~~||
|tINT, INT Pulse Width<br>~~——~~<br>~~dG~~|int_tpulse_duration= 0, 1 (100us, 8us ) ;<br>~~Q~~<br>~~dG~~|8<br>~~Q~~<br>~~dG~~|~~dG~~|100<br>~~dG~~|µs<br>~~dG~~||
|**I2C I/O (SCL, SDA)**<br>~~——~~|||||||
|VIL, LOW-Level Input Voltage<br>~~sO~~|~~sO~~<br>~~en es~~|-0.5 V<br>~~sO~~<br>~~es es~~|~~sO~~<br>~~es~~|0.3*VDDIO<br>~~sO~~|V<br>~~sO~~|1|
|VIH, HIGH-Level Input Voltage<br>~~ee~~|~~ee~~<br>~~en es~~|0.7*VDDIO<br>~~ee~~<br>~~es es~~|~~ee~~<br>~~es~~|VDDIO +<br>0.5V<br>~~ee~~|V<br>~~ee~~||
|Vhys, Hysteresis<br>~~dG~~|~~en es~~<br>~~dG~~|~~es es~~<br>~~dG~~|0.1*VDDIO<br>~~es~~<br>~~dG~~|~~dG~~|V<br>~~dG~~||
|VOL, LOW-Level Output Voltage<br>~~dG~~<br>~~sO~~<br>~~es es~~|3 mA sink current<br>~~dG~~<br>~~sO~~<br>~~es Gs~~|0<br>~~dG~~<br>~~sO~~<br>~~Gs Gs~~|~~dG~~<br>~~sO~~<br>~~Gs~~|0.4<br>~~dG~~<br>~~sO~~|V<br>~~dG~~<br>~~sO~~||
|IOL, LOW-Level Output Current<br>~~sO~~<br>~~es es~~|VOL=0.4V<br>VOL=0.6V<br>~~sO~~<br>~~es Gs~~<br>~~Q~~|~~sO~~<br>~~Gs Gs~~<br>~~Q~~|3<br>6<br>~~sO~~<br>~~Gs~~|~~sO~~|mA<br>mA<br>~~sO~~||
|Output Leakage Current<br>~~es es~~<br>~~Rn~~|~~es Gs~~<br>~~Rn~~<br>~~Q~~|~~Gs Gs~~<br>~~Rn~~<br>~~Q~~|100<br>~~Gs~~<br>~~Rn~~|~~Rn~~|nA<br>~~Rn~~||
|tof, Output Fall Time from VIHmaxto VILmax<br>~~dG~~|Cbbus capacitance in pf<br>~~Q~~<br>~~dG~~|20+0.1Cb<br>~~Q~~<br>~~dG~~|~~dG~~|300<br>~~dG~~|ns<br>~~dG~~||
|**INTERNAL CLOCK SOURCE**<br>~~|~~<br>~~——————~~|||||||
|Clock Frequency Initial Tolerance<br>~~—~~|CLKSEL=2b00 or gyro inactive; 25°C<br>~~—~~|-3<br>~~—~~<br>~~—~~|~~—~~<br>~~——~~|+3<br>~~—~~<br>~~——~~|%<br>~~—~~<br>~~——~~|1<br>~~—~~<br>~~—~~|
||CLK_SEL=2b01 and gyro active; 25°C<br>~~—~~<br>~~Rn~~|-1.5<br>~~—~~<br>~~—~~<br>~~Rn~~<br>~~—~~|~~—~~<br>~~——~~<br>~~Rn~~<br>~~———~~|+1.5<br>~~—~~<br>~~——~~<br>~~Rn~~|%<br>~~—~~<br>~~——~~<br>~~Rn~~|1<br>~~—~~<br>~~—~~<br>~~Rn~~|
|Frequency Variation over Temperature|CLK_SEL=2b00 or gyro inactive; -40°C to +85°C|~~— ~~<br>~~—~~|~~—— ~~<br>~~———~~|±3<br> ~~——~~|%<br>~~—— ~~|1<br> ~~—~~|
||CLK_SEL=2b01 and gyro active; -40oC to +85oC<br>~~De~~|~~—~~<br>~~De~~|~~———~~<br>~~De~~|±2<br>~~De~~|%<br>~~De~~|1<br>~~De~~|
## **Table 4. A.C. Electrical Characteristics**
## **Notes:**
1. Expected results based on design, will be updated after characterization. Not tested in production. 2. Guaranteed by design.
3. Production tested.
Page 14 of 120
Document Number: DS-000401 Revision: 1.3
_**IIM-42652**_
## **I[2] C TIMING CHARACTERIZATION**
|**Parameters**<br>|**Conditions**<br>|**Min**<br>|**Typical**<br>|**Max**<br>|**Units**<br>|**Notes**<br>|
|---|---|---|---|---|---|---|
|**I2C TIMING**<br>~~GO~~|**I2C FAST-MODE PLUS**<br>~~GO~~|~~GO~~|~~GO~~|~~GO~~|~~GO~~|~~GO~~|
|fSCL, SCL Clock Frequency<br>~~GQ~~|~~GQ~~|~~GQ~~|~~GQ~~|1<br>~~GQ~~|MHz<br>~~GQ~~|1<br>~~GQ~~|
|tHD.STA, (Repeated) START Condition Hold Time<br>~~eG~~|~~eG~~|0.26<br>~~eG~~|~~eG~~|~~eG~~|µs<br>~~eG~~|1<br>~~eG~~|
|tLOW, SCL Low Period||0.5|||µs|1|
|tHIGH, SCL High Period<br>~~QQ~~|~~QQ~~|0.26<br>~~QQ~~|~~QQ~~|~~QQ~~|µs<br>~~QQ~~|1<br>~~QQ~~|
|tSU.STA, Repeated START Condition Setup Time<br>~~sO~~|~~sO~~|0.26<br>~~sO~~|~~sO~~|~~sO~~|µs<br>~~sO~~|1<br>~~sO~~|
|tHD.DAT, SDA Data Hold Time<br>~~ef~~|~~ef~~|0<br>~~ef~~|~~ef~~|~~ef~~|µs<br>~~ef~~|1<br>~~ef~~|
|tSU.DAT, SDA Data SetupTime<br>~~a~~|~~GQ~~|50<br>~~GQ~~|~~GQ~~|~~GQ~~|ns<br>~~GQ~~|1<br>~~GQ~~|
|tr, SDA and SCL Rise Time|Cbbus cap. from 10 to 400pF|||120|ns|1|
|tf, SDA and SCL Fall Time<br>~~QQ~~|Cbbus cap. from 10 to 400 pF<br>~~QQ~~<br>~~rs~~|~~QQ~~<br>~~(OR~~|~~QQ~~|120<br>~~QQ~~|ns<br>~~QQ~~|1<br>~~QQ~~|
|tSU.STO, STOP Condition Setup Time<br>~~rs~~|~~rs~~<br>~~rs~~|0.5<br>~~rs~~<br>~~(OR~~|~~rs~~|~~rs~~|µs<br>~~rs~~|1<br>~~rs~~|
|tBUF, Bus Free Time Between STOP and START<br>Condition|~~rs ~~|0.5<br> ~~(OR~~|||µs|1|
|Cb, Capacitive Load for each Bus Line<br>~~QQ~~|~~QQ~~<br>~~rs~~|~~QQ~~<br>~~QOD~~|< 400<br>~~QQ~~<br>~~QO~~|~~QQ~~<br>~~(~~|pF<br>~~QQ~~|1<br>~~QQ~~|
|tVD.DAT, Data Valid Time<br>~~rd~~|~~rd~~<br>~~rs~~|~~rd~~<br>~~QOD~~|~~rd~~<br>~~QO~~|0.45<br>~~rd~~<br>~~(~~|µs<br>~~rd~~|1<br>~~rd~~|
|tVD.ACK, Data Valid Acknowledge Time<br>~~GQ~~|~~rs~~<br>~~GQ~~|~~QOD~~<br>~~GQ~~|~~QO~~<br>~~GQ~~|0.45<br>~~(~~<br>~~GQ~~|µs<br>~~GQ~~|1<br>~~GQ~~|
## **Table 5. I[2] C Timing Characteristics**
## **Notes:**
1. Based on characterization of 5 parts over temperature and voltage as mounted on evaluation board or in sockets
**==> picture [473 x 143] intentionally omitted <==**
**----- Start of picture text -----**<br>
SDA 70% tf : tr 70% tSU.DAT oc opoccces P eet ort<br>30% 30% N = e “ wcccce<br>tf weeccoescces continued below at " O A<br>tr tVD.DAT<br>SCL 70% tHD.DAT 70%<br>30% 30%<br>tHD.STA 1/fSCL tLOW 9 [th] clock cycle<br>S 1 [st] clock cycle tHIGH<br>tBUF<br>SDA 70%<br>A 30%<br>tSU.STA tHD.STA tVD.ACK tSU.STO<br>SCL 70%<br>30%<br>Sr 9 [th] clock cycle P S<br>**----- End of picture text -----**<br>
**Figure 1. I[2] C Bus Timing Diagram**
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Document Number: DS-000401 Revision: 1.3
_**IIM-42652**_
## **SPI TIMING CHARACTERIZATION – 4-WIRE SPI MODE**
Typical Operating Circuit of section 4.2, VDD = 1.8V, VDDIO = 1.8V, TA=25°C, unless otherwise noted.
|**PARAMETERS**|**CONDITIONS**|**MIN**|**TYP**|**MAX**|**UNITS**|**NOTES**|
|---|---|---|---|---|---|---|
|**SPI TIMING**<br>~~CG~~|~~CG~~|~~CG~~|~~CG~~|~~CG~~|~~CG~~|~~CG~~|
|fSPC, SCLK Clock Frequency<br>~~ee~~|Default<br>~~ee~~|~~ee~~|~~ee~~|24<br>~~ee~~|MHz<br>~~ee~~|1<br>~~ee~~|
|tLOW, SCLK Low Period<br>~~ee~~<br>~~oe~~|~~ee~~|17<br>~~ee~~|~~ee~~|~~ee~~|ns<br>~~ee~~|1<br>~~ee~~|
|tHIGH, SCLK High Period<br>~~oe~~||17|||ns|1|
|tSU.CS, CS Setup Time<br>~~oe~~||39|||ns|1|
|tHD.CS, CS Hold Time<br>~~oe~~<br>~~ee~~|~~ee~~|18<br>~~ee~~|~~ee~~|~~ee~~|ns<br>~~ee~~|1<br>~~ee~~|
|tSU.SDI, SDI Setup Time<br>~~ee~~|~~ee~~|13<br>~~ee~~|~~ee~~|~~ee~~|ns<br>~~ee~~|1<br>~~ee~~|
|tHD.SDI, SDI Hold Time<br>~~ee~~<br>~~eo~~|~~ee~~<br>~~eo~~|8<br>~~ee~~<br>~~eo~~|~~ee~~<br>~~eo~~|~~ee~~<br>~~eo~~|ns<br>~~ee~~<br>~~eo~~|1<br>~~ee~~<br>~~eo~~|
|tVD.SDO, SDO Valid Time<br>~~eo~~|Cload= 20 pF<br>~~eo~~|~~eo~~|~~eo~~|21.5<br>~~eo~~|ns<br>~~eo~~|1<br>~~eo~~|
|tHD.SDO, SDO Hold Time<br>~~eo~~<br>~~oo~~|Cload= 20 pF<br>~~eo~~<br>~~oo~~|3.5<br>~~eo~~<br>~~oo~~|~~eo~~<br>~~oo~~|~~eo~~<br>~~oo~~|ns<br>~~eo~~<br>~~oo~~|1<br>~~eo~~<br>~~oo~~|
|tDIS.SDO, SDO Output Disable Time<br>~~oo~~|~~oo~~|~~oo~~|~~oo~~|28<br>~~oo~~|ns<br>~~oo~~|1<br>~~oo~~|
**Table 6. 4-Wire SPI Timing Characteristics (24-MHz Operation)**
**Notes:**
**==> picture [474 x 178] intentionally omitted <==**
**----- Start of picture text -----**<br>
1. Based on characterization of 5 parts over temperature and voltage as mounted on evaluation board or in sockets<br>CS 70%<br>30%<br>tFall tRise tHD;CS<br>ia tSU;CS tHIGH 1/fCLK<br>SCLK 70%<br>30%<br>tSU;SDI tHD;SDI tLOW<br>SDI 70% MSB IN LSB IN<br>30%<br>tVD;SDO tHD;SDO tDIS;SDO<br>SDO 70%<br>MSB OUT LSB OUT<br>30%<br>aa. a a. Ga<br>**----- End of picture text -----**<br>
**Figure 2. 4-Wire SPI Bus Timing Diagram**
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_**IIM-42652**_
## **SPI TIMING CHARACTERIZATION – 3-WIRE SPI MODE**
Typical Operating Circuit of section 4.2, VDD = 1.8 V, VDDIO = 1.8V, TA=25°C, unless otherwise noted.
**==> picture [489 x 391] intentionally omitted <==**
**----- Start of picture text -----**<br>
PARAMETERS CONDITIONS MIN TYP MAX UNITS NOTES<br>SPI TIMING<br>fSPC, SCLK Clock Frequency Default 24 MHz 1<br>tLOW, SCLK Low Period 17 ns 1<br>———<br>tHIGH, SCLK High Period 17 ns 1<br>tSU.CS, CS Setup Time 39 ns 1<br>—— a<br>tHD.CS, CS Hold Time 5 ns 1<br>— tSU.SDIO, SDIO Input Setup Time 13 ns 1<br>a a<br>tHD.SDIO, SDIO Input Hold Time 8 ns 1<br>a tVD.SDIO, SDIO Output Valid Time Cload = 20 pF 18.5 ns 1<br>tHD.SDIO, SDIO Output Hold Time Cload = 20 pF 3.5 ns 1<br>a tDIS.SDIO, SDIO Output Disable Time 28 ns 1<br>a<br>Table 7. 3-Wire SPI Timing Characteristics (24-MHz Operation)<br>Notes:<br>1. Based on characterization of 5 parts over temperature and voltage as mounted on evaluation board or in sockets<br>CS 70%<br>30%<br>tFall tRise tHD;CS<br>ae tSU;CS tHIGH 1/fCLK<br>SCLK 70%<br>30%<br>tSU;SDIO tHD;SDIO tLOW<br>! 4 )<br>I 70% MSB IN LSB IN<br>30%<br>a tVD;SDIO tHD;SDIO tDIS;SDIO<br>O 70%<br>MSB OUT LSB OUT<br>30%<br>$F—E<br>Figure 3. 3-Wire SPI Bus Timing Diagram<br>SDIO<br>**----- End of picture text -----**<br>
Page 17 of 120
Document Number: DS-000401 Revision: 1.3
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## **RTC (CLKIN) TIMING CHARACTERIZATION**
Typical Operating Circuit of section 4.2, VDD = 1.8V, VDDIO = 1.8V, TA=25°C, unless otherwise noted.
|**PARAMETERS**|**CONDITIONS**|**MIN**|**TYP**|**MAX**|**UNITS**|**NOTES**|
|---|---|---|---|---|---|---|
|**RTC (CLKIN) TIMING**|||||||
|FRTC, RTC Clock Frequency|Default|31|32|50|kHz|1|
|tHIGHRTC, RTC Clock High Period||1|||µs|1|
|tRISERTC, RTC Clock Rise Time||5||500|ns|1|
|tFALLRTC, RTC Clock Fall Time||5||500|ns|1|
**Table 8. RTC Timing Characteristics**
## **Notes:**
1. Based on characterization. Not tested in production.
**Figure 4. RTC Timing Diagram**
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Document Number: DS-000401 Revision: 1.3
_**IIM-42652**_
## **ABSOLUTE MAXIMUM RATINGS**
Stress above those listed as “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to the absolute maximum ratings conditions for extended periods may affect device reliability. Prolonged exposure to acceleration ranges beyond ±60g may affect device reliability.
|**PARAMETER**|**RATING**|
|---|---|
|Supply Voltage, VDD|-0.5V to +4V|
|Supply Voltage, VDDIO|-0.5V to +4V|
|Input Voltage Level (FSYNC, SCL, SDA)|-0.5V to VDDIO + 0.5V|
|Acceleration (Any Axis, unpowered)|20,000g for 0.2 ms|
|Operating Temperature Range|-40°C to +105°C|
|Storage Temperature Range|-40°C to +125°C|
|Electrostatic Discharge (ESD) Protection|2 kV (HBM);<br>500V (CDM)|
|Latch-up|JEDEC Class II (2),125°C<br>±100 mA|
**Table 9. Absolute Maximum Ratings**
Page 19 of 120
Document Number: DS-000401 Revision: 1.3
_**IIM-42652**_
## _**4 APPLICATIONS INFORMATION**_
## **PIN OUT DIAGRAM AND SIGNAL DESCRIPTION**
|**PIN NUMBER**<br>~~pj~~|**PIN NAME**<br>~~pj~~|**PIN DESCRIPTION**<br>|**PIN STATUS**<br>|
|---|---|---|---|
|1<br>~~pj~~|AP_SDO / AP_AD0<br>~~pjjf~~|AP_SDO: AP SPI serial data output (4-wire mode);<br>AP_AD0: AP I3CSM/ I2C slave address LSB<br>~~jf~~|By default, pull-up/pull-down is disabled. Pull-up can be<br>enabled by setting PIN1_PU_EN = 1 (register 0x0Eh in<br>Bank 3). Pull-down can be enabled by setting<br>PIN1_PD_EN = 1 (register 0x0Eh in Bank 3). Note that<br>both pull-up and pull-down must not be simultaneously<br>enabled for the samepin.<br>~~jf~~|
|2<br>~~pj~~<br>~~a~~|RESV<br>~~pj~~<br>~~ee~~|No Connect or Connect to GND<br>|By default, pull-up is disabled. Pull-up can be enabled by<br>settingPIN2_PU_EN = 1(register 0x06h in Bank 3).<br>|
|3<br>~~pj~~<br>~~a~~|RESV<br>~~pj~~<br>~~ee~~|No Connect or Connect to GND<br>|By default, pull-up is disabled. Pull-up can be enabled by<br>settingPIN3_PU_EN = 1(register 0x06h in Bank 3).<br>|
|4<br>~~a~~<br>~~ff~~|INT1 / INT<br>~~ee~~<br>~~ff~~|INT1: Interrupt 1 (Note: INT1 can be push-pull or open drain)<br>INT: All interrupts mapped to pin 4<br>~~ff~~|By default, pull-down is disabled. Pull-down can be<br>enabled by setting PIN4_PD_EN = 1 (register 0x06h in<br>Bank 3).<br>~~ff~~|
|5<br>~~ff~~|VDDIO<br>~~ff~~|IO power supply voltage<br>~~ff~~|~~ff~~|
|6<br>~~sO~~|GND<br>~~sO~~|Power supply ground<br>~~sO~~|~~sO~~|
|7<br>~~oe~~|RESV<br>~~oe~~|Connect to GND|By default, pull-up is disabled. Pull-up can be enabled by<br>setting PIN7_PU_EN = 1 (register 0x06h in Bank 3) and it<br>can be disabled bysettingPIN7_PU_EN = 0.|
|8<br>~~oe~~|VDD<br>~~oe~~|Power supply voltage||
|9<br>~~a~~|INT2 / FSYNC / CLKIN<br>~~a~~|INT2: Interrupt 2 (Note: INT2 can be push-pull or open drain)<br>FSYNC: Frame sync input; Connect to GND if FSYNC not used<br>CLKIN: External Clock Input|By default, pull-down is disabled.<br>Pull-down can be enabled by setting PIN9_PD_EN = 1<br>(register 0x06h in Bank 3).|
|10<br>~~a~~|RESV<br>~~a~~|No Connect or Connect to GND<br>|By default, pull-up is enabled.<br>Pull-up can be disabled by setting PIN10_PU_EN = 0 and<br>it can be enabled by setting PIN10_PU_EN = 1 (register<br>0x06h in Bank 3).<br>|
|11<br>~~pp~~|RESV<br>~~pp~~|No Connect or Connect to GND<br>~~pp~~|By default, pull-up is enabled.<br>Pull-up can be disabled by setting PIN11_PU_EN = 0 and<br>it can be enabled by setting PIN11_PU_EN = 1 (register<br>0x06h in Bank 3).<br>~~pp~~|
|12<br>~~pp~~|AP_CS<br>~~pp~~|AP SPI Chip select (AP SPI interface); Connect to VDDIO if<br>using AP I3CSM/ I2C interface<br>~~pp~~|By default, pull-up is enabled. Pull-up can be disabled by<br>setting PIN12_PU_EN = 0 (register 0x0Eh in Bank 3).<br>Pull-down can be enabled by setting PIN12_PD_EN = 1<br>(register 0x0Eh in Bank 3). Note that both pull-up and<br>pull-down must not be simultaneously enabled for the<br>samepin.<br>~~pp~~|
|13|AP_SCL / AP_SCLK|AP_SCL: AP I3CSM/ I2C serial clock; AP_SCLK: AP SPI serial<br>clock|By default, pull-up/pull-down is disabled. Pull-up can be<br>enabled by setting PIN13_PU_EN = 1 (register 0x0Eh in<br>Bank 3). Pull-down can be enabled by setting<br>PIN13_PD_EN = 1 (register 0x0Eh in Bank 3). Note that<br>both pull-up and pull-down must not be simultaneously<br>enabled for the same pin.|
|14|AP_SDA / AP_SDIO /<br>AP_SDI|AP_SDA: AP I3CSM/ I2C serial data; AP_SDIO: AP SPI serial<br>data I/O (3-wire mode); AP_SDI: AP SPI serial data input (4-<br>wire mode)|By default, pull-up/pull-down is disabled. Pull-up can be<br>enabled by setting PIN14_PU_EN = 1 (register 0x0Eh in<br>Bank 3). Pull-down can be enabled by setting<br>PIN14_PD_EN = 1 (register 0x0Eh in Bank 3). Note that<br>both pull-up and pull-down must not be simultaneously<br>enabled for the same pin.|
**Table 10. Signal Descriptions**
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**==> picture [240 x 74] intentionally omitted <==**
**----- Start of picture text -----**<br>
+Z<br>IIM-42652<br>| 9) INT2 [/] [FSYNC]<br>/ CLKIN LAS<br>Es VDD SK<br>+Y +X<br>lle R&S<br>**----- End of picture text -----**<br>
**Figure 5. Pin Out Diagram for IIM-42652 2.5 mm x 3.0 mm x 0.91 mm LGA**
**TYPICAL OPERATING CIRCUIT**
**==> picture [267 x 183] intentionally omitted <==**
**----- Start of picture text -----**<br>
VDDIO<br>14 13 12<br>AP_AD0 1 11 | RESV rh<br>RESV 2 10 RESV<br>IIM-42ICM-42688-G52 INT2 / FSYNC / CLKIN<br>RESV 3 9<br>1.71 – 3.6VDC<br>, INT1 / INT EE 4 8 VDD<br>5 6 7<br>C1, 0.1 µF C2, 2.2 µF<br>1.71 – 3.6VDC<br>C3, 10 nF<br>AP<br>_<br>AP_SDA SCL<br>VDDIO GND RESV<br>**----- End of picture text -----**<br>
**Figure 6. IIM-42652 Application Schematic (I3C[SM] / I[2] C Interface to Host)**
**Note:** I[2] C lines are open drain and pull-up resistors (e.g. 10 kΩ) are required.
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_**IIM-42652**_
**==> picture [265 x 187] intentionally omitted <==**
**----- Start of picture text -----**<br>
AP_CS<br>14 13 12<br>AP_SDO 1 11 RESV<br>T h<br>RESV 2 10 RESV<br>IIM-42652ICM-42688-G INT2 / FSYNC / CLKIN<br>RESV 3 9<br>1.71 – 3.6VDC<br>INT1 / INT 4 8 VDD<br>5 6 7<br>C1, 0.1 µF C2, 2.2 µF<br>, dh<br>1.71 – 3.6VDC<br>C3, 10 nF<br>AP<br>_<br>AP_SDI AP_SDIO / SCLK<br>VDDIO GND RESV<br>**----- End of picture text -----**<br>
**Figure 7. IIM-42652 Application Schematic (SPI Interface to Host)**
**BILL OF MATERIALS FOR EXTERNAL COMPONENTS**
|**COMPONENT**|**LABEL**|**SPECIFICATION**|**QUANTITY**|
|---|---|---|---|
|VDD Bypass Capacitors|C1<br>C2|X7R, 0.1µF ±10%<br>X7R, 2.2µF ±10%|1<br>1|
|VDDIO Bypass Capacitor|C3|X7R, 10nF ±10%|1|
**Table 11. Bill of Materials**
**SYSTEM BLOCK DIAGRAM**
I3CS™/|2C/SPI **IIM-42652** ~~a~~ —— ae
**Figure 8. IIM-42652 System Block Diagram**
**Note:** The above block diagram is an example. Please refer to the pin-out (section 4.1) for other configuration options.
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_**IIM-42652**_
## **OVERVIEW**
The IIM-42652 is comprised of the following key blocks and functions:
- Three-axis MEMS rate gyroscope sensor with 16-bit ADCs and signal conditioning
- 20-bits data format support in FIFO for high-data resolution (see section 6 for details)
- Three-axis MEMS accelerometer sensor with 16-bit ADCs and signal conditioning
- 20-bits data format support in FIFO for high-data resolution (see section 6 for details)
- I3C[SM] , I[2] C, and SPI serial communications interfaces to Host
- Self-Test
- Clocking
- Sensor Data Registers
- FIFO
- Interrupts
- Digital-Output Temperature Sensor
- Bias and LDOs
- Charge Pump
- Standard Power Modes
## **THREE-AXIS MEMS GYROSCOPE WITH 16-BIT ADCS AND SIGNAL CONDITIONING**
The IIM-42652 includes a vibratory MEMS rate gyroscope, which detects rotation about the X-, Y-, and Z- Axes. When the gyroscope is rotated about any of the sense axes, the Coriolis Effect causes a vibration that is detected by a capacitive pickoff. The resulting signal is amplified, demodulated, and filtered to produce a voltage that is proportional to the angular rate. This voltage is digitized using on-chip Analog-to-Digital Converters (ADCs) to sample each axis. The full-scale range of the gyro sensors may be digitally programmed to ±15.625, ±31.25, ±62.5, ±125, ±250, ±500, ±1000, and ±2000 degrees per second (dps).
## **THREE-AXIS MEMS ACCELEROMETER WITH 16-BIT ADCS AND SIGNAL CONDITIONING**
The IIM-42652 includes a 3-Axis MEMS accelerometer. Acceleration along a particular axis induces displacement of a proof mass in the MEMS structure, and capacitive sensors detect the displacement. The IIM-42652 architecture reduces the accelerometers’ susceptibility to fabrication variations as well as to thermal drift. When the device is placed on a flat surface, it will measure 0 _g_ on the X- and Y-axes and +1 _g_ on the Z-axis. The accelerometers’ scale factor is calibrated at the factory and is nominally independent of supply voltage. The full-scale range of the digital output can be adjusted to ±2 _g_ , ±4 _g_ , ±8 _g_ and ±16 _g_ .
## **I3C[SM] , I[2] C, AND SPI HOST INTERFACE**
The IIM-42652 communicates to the application processor using an I3C[SM] , I[2] C, or SPI serial interface. The IIM-42652 always acts as a slave when communicating to the application processor.
## **SELF-TEST**
Self-test allows for the testing of the mechanical and electrical portions of the sensors. The self-test for each measurement axis can be activated by means of the gyroscope and accelerometer self-test registers.
When the self-test is activated, the electronics cause the sensors to be actuated and produce an output signal. The output signal is used to observe the self-test response.
The self-test response is defined as follows:
## SELF-TEST RESPONSE = SENSOR OUTPUT WITH SELF-TEST ENABLED – SENSOR OUTPUT WITH SELF-TEST DISABLED
When the value of the self-test response is within the specified min/max limits of the product specification, the part has passed self-test. When the self-test response exceeds the min/max values, the part is deemed to have failed selftest.
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_**IIM-42652**_
## **CLOCKING**
The IIM-42652 has a flexible clocking scheme, allowing the following internal clock sources to be used for the internal synchronous circuitry. This synchronous circuitry includes signal conditioning, ADCs, and various control circuits and registers.
The CLKIN pin on IIM-42652 provides the ability to input an external clock. A highly accurate external clock may be used rather than the internal clock sources if greater clock accuracy is desired. External clock input supports highly accurate clock input from 31 kHz to 50 kHz, resulting in improvement of the following:
- ODR uncertainty due to process, temperature, operating mode (PLL vs. RCOSC), and design limitations. This uncertainty can be as high as ±8% in RCOSC mode and ±1% in PLL mode. The CLKIN, assuming a 50 ppm or better 32.768 kHz source, will improve the ODR accuracy from ±80,000 ppm to ±50 ppm in RCOSC mode, or from ±10,000 ppm to ±50 ppm in PLL mode.
- System level sensitivity error. Any clock uncertainty directly impacts gyroscope sensitivity at the system level. Sophisticated systems can estimate ODR inaccuracy to some extent, but not to the extent improved by using CLKIN.
- System-level clock/sensor synchronization. When using CLKIN, the accelerometer and gyroscope are on the same clock as the host. There is no need to continually re-synchronize the sensor data as the sensor sample points and period are in exact alignment with the common system clock.
- Other applications that benefit from CLKIN include navigation, robotics.
Allowable internal sources for generating the internal clock are:
- a) An internal relaxation oscillator
- b) Auto-select between internal relaxation oscillator and gyroscope MEMS oscillator to use the best available source
The only setting supporting specified performance in all modes is option b). Option b) is recommended when using the internal clock source.
## **SENSOR DATA REGISTERS**
The sensor data registers contain the latest gyroscope, accelerometer, and temperature measurement data. They are read-only registers and are accessed via the serial interface. Data from these registers may be read anytime.
## **INTERRUPTS**
Interrupt functionality is configured via the Interrupt Configuration register. Items that are configurable include the interrupt pins configuration, the interrupt latching and clearing method, and triggers for the interrupt. Items that can trigger an interrupt are (1) clock generator locked to new reference oscillator (used when switching clock sources); (2) new data is available to be read (from the FIFO and Data registers); (3) accelerometer event interrupts; (4) FIFO watermark; (5) FIFO overflow. The interrupt status can be read from the Interrupt Status register.
## **DIGITAL-OUTPUT TEMPERATURE SENSOR**
An on-chip temperature sensor and ADC are used to measure the IIM-42652 die temperature. The readings from the ADC can be read from the FIFO or the Sensor Data registers.
Temperature data value from the sensor data registers can be converted to degrees centigrade by using the following formula:
Temperature in Degrees Centigrade = (TEMP_DATA / 132.48) + 25
FIFO_TEMP_DATA, temperature data stored in FIFO, can be 8-bit or 16-it quantity. The 8-bit of temperature data stored in FIFO is limited to -40°C to 85°C range, while the 16-bit representation can support the full operating temperature range. It can be converted to degrees centigrade by using the following formula:
Temperature in Degrees Centigrade = (FIFO_TEMP_DATA / 2.07) + 25
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_**IIM-42652**_
## **BIAS AND LDOS**
The bias and LDO section generate the internal supply and the reference voltages and currents required by the IIM42652.
## **CHARGE PUMP**
An on-chip charge pump generates the high voltage required for the MEMS oscillator.
## **STANDARD POWER MODES**
Table 12 lists the user-accessible power modes for IIM-42652.
|**MODE**|**NAME**|**GYRO**|**ACCEL**|
|---|---|---|---|
|1|SleepMode|Off|Off|
|2|StandbyMode|Drive On|Off|
|3|Accelerometer Low-Power Mode|Off|Duty-Cycled|
|4|Accelerometer Low-Noise Mode|Off|On|
|5|Gyroscope Low-Noise Mode|On|Off|
|6|6-Axis Low-Noise Mode|On|On|
**Table 12. Standard Power Modes for IIM-42652**
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_**IIM-42652**_
## _**5 SIGNAL PATH**_
The following figure shows a block diagram of the signal path for IIM-42652.
**==> picture [544 x 79] intentionally omitted <==**
**----- Start of picture text -----**<br>
Gyro Only<br>ADC Decimation (32kHz)Filter Notch Filter 0 Filter (AAF)Anti-Alias 0 Programmable OffsetUser (order, BW, ODR)UI Filter Block RegistersSensor UI Interface<br>1 1<br>FSR Selection<br>GYRO_NF_DIS AAF_DIS<br>**----- End of picture text -----**<br>
**Figure 9. IIM-42652 Signal Path**
The signal path starts with ADCs for the gyroscope and accelerometer. Other components of the signal path are described in section 5.1 in further detail.
## **SUMMARY OF PARAMETERS USED TO CONFIGURE THE SIGNAL PATH**
Table 13 shows the parameters that can control the signal path.
|**PARAMETER NAME**|**DESCRIPTION**|
|---|---|
|GYRO_AAF_DIS|Disables the Gyroscope Anti Alias Filter(AAF)|
|GYRO_AAF_DELT<br>GYRO_AAF_DELTSQR<br>GYRO_AAF_BITSHIFT|Three parameters required to program the gyroscope AAF. This is a 2ndorder filter with<br>programmable low pass filter. This is a user programmable filter which can be used to select<br>the desired BW. This filter allows tradingoff RMS noise vs. latencyfor agiven ODR.|
|ACCEL_AAF_DIS|Disables the Accelerometer Anti Alias Filter|
|ACCEL_AAF_DELT<br>ACCEL_AAF_DELTSQR<br>ACCEL_AAF_BITSHIFT|Three parameters required to program the accelerometer AAF. This is a 2ndorder filter with<br>programmable low pass filter. This is a user programmable filter which can be used to select<br>the desired BW. This filter allows tradingoff RMS noise vs. latencyfor agiven ODR.|
|GYRO_NF_DIS|Disables thegyro Notch Filter|
|GYRO_X/Y/Z_NF_COSWZ<br>GYRO_X/Y/Z_NF_COSWZ_SEL|Factory trimmed parameters, designed to position a Notch at or near the sense peak<br>frequency of Gyro. This allows the user to suppress only sense peak contribution to noise,<br>while still maintaining a low latency high BW/ODR interface from the Sensor. This filter is<br>available onlyingyro,and theparameters for X,Y,and Z are chosen independently.|
|GYRO_NF_BW_SEL|Factory trimmed parameter to cancel noise created by sense peak from gyro. This parameter<br>is common to all three axes|
**Table 13. Signal path parameters**
## **NOTCH FILTER**
The Notch Filter is only supported for the gyroscope signal path. The following steps can be used to program the notch filter. Note that the notch filter is specific to each axis in the gyroscope, so the X-, Y-, and Z-axis can be programmed independently.
## **Frequency of Notch Filter (each axis)**
To operate the Notch filter, two parameters NF_COSWZ, and NF_COSWZ_SEL must be programmed for each gyroscope axis.
Parameters NF_COSWZ are defined for each axis of the gyroscope as GYRO_X_NF_COSWZ (register bank 1, register 0x0Fh & register 0x12h), GYRO_Y_NF_COSWZ (register bank 1, register 0x10h & register 0x12h), GYRO_Z_NF_COSWZ (register bank 1, register 0x11h & register 0x12h). Note that the parameters have 9-bit values across two different registers.
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_**IIM-42652**_
Parameters NF_COSWZ_SEL are defined for each axis of the gyroscope as GYRO_X_NF_COSWZ_SEL (register bank 1, register 0x12h, bit 3), GYRO_Y_NF_COSWZ_SEL (register bank 1, register 0x12h, bit 4), GYRO_Z_NF_COSWZ_SEL (register bank 1, register 0x12h, bit 5).
Each value must be calculated using the steps described below and programmed into the corresponding register locations mentioned above.
fdesired is the desired frequency of the Notch Filter in kHz. The lower bound for fdesired is 1 kHz, and the upper bound is 3 kHz. Operating the notch filter outside this range is not supported.
Step1: COSWZ = cos(2*pi*fdesired/8) Step2: If abs(COSWZ)≤0.875 NF_COSWZ = round[COSWZ*256] NF_COSWZ_SEL = 0 else NF_COSWZ_SEL = 1 if COSWZ > 0.875 NF_COSWZ = round [8*(1-COSWZ)*256] else if COSWZ < -0.875 NF_COSWZ = round [-8*(1+COSWZ)*256] end End
## **Bandwidth of Notch Filter (common to all axes)**
The notch filter allows the user to control the width of the notch from eight possible values using a 3-bit parameter GYRO_NF_BW_SEL in register bank 1, register 0x13h, bits 6:4. This parameter is common to all three axes.
|**GYRO_NF_BW_SEL**|**NOTCH FILTER BANDWIDTH (HZ)**|
|---|---|
|0|1449|
|1|680|
|2|329|
|3|162|
|4|80|
|5|40|
|6|20|
|7|10|
The notch filter can be selected or bypassed by using the parameter GYRO_NF_DIS in register bank 1, register 0x0Bh, bit 0 as shown below.
|**GYRO_NF_DIS**|**FUNCTION**|
|---|---|
|0|Enable notch filter|
|1|Disable notch filter|
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_**IIM-42652**_
## **ANTI-ALIAS FILTER**
To program the anti-alias filter for a required bandwidth, use the table below to map the bandwidth to register values as shown:
- Register bank 2, register 0x03h, bits 6:1, ACCEL_AAF_DELT: Code from 1 to 63 that allows programming the bandwidth for accelerometer anti-alias filter
- Register bank 2, register 0x04h, bits 7:0 and Bank 2, register 0x05h, bits 3:0, ACCEL_AAF_DELTSQR: Square of the delt value for accelerometer
- Register bank 2, register 0x05h, bits 7:4, ACCEL_AAF_BITSHIFT: Bitshift value for accelerometer used in hardware implementation
- Register bank 1, register 0x0Ch, bits 5:0, GYRO_AAF_DELT: Code from 1 to 63 that allows programming the bandwidth for gyroscope anti-alias filter
- Register bank 1, register 0x0Dh, bits 7:0 and Bank 1, register 0x0Eh, bits 3:0, GYRO_AAF_DELTSQR: Square of the delt value for gyroscope
- Register bank 1, register 0x0Eh, bits 7:4, GYRO_AAF_BITSHIFT: Bitshift value for gyroscope used in hardware implementation
|**3DB BANDWIDTH (HZ)**|**ACCEL_AAF_DELT;**<br>**GYRO_AAF_DELT**|**ACCEL_AAF_DELTSQR;**<br>**GYRO_AAF_DELTSQR**|**ACCEL_AAF_BITSHIFT;**<br>**GYRO_AAF_BITSHIFT**|
|---|---|---|---|
|42<br>~~ee~~|1<br>~~ee~~|1<br>~~ee~~|15<br>~~ee~~|
|84<br>~~ss~~|2<br>~~ss~~<br>~~es~~|4<br>~~ss~~<br>~~es~~|13<br>~~ss~~|
|126<br>~~es~~|3<br>~~es~~<br>~~es~~|9<br>~~es~~<br>~~es~~|12<br>~~es~~|
|170<br>~~es~~<br>~~es~~|4<br>~~es~~<br>~~es~~<br>~~es~~<br>~~es~~|16<br>~~es~~<br>~~es~~<br>~~es~~|11<br>~~es~~<br>~~es~~|
|213<br>~~es~~|5<br>~~es~~<br>~~es~~|25<br>~~es~~|10<br>~~es~~|
|258<br>~~es~~<br>~~ee~~|6<br>~~es~~<br>~~es~~<br>~~ee~~|36<br>~~es~~<br>~~ee~~|10<br>~~es~~<br>~~ee~~|
|303<br>~~ss~~<br>~~es~~|7<br>~~ss~~<br>~~es~~|49<br>~~ss~~<br>~~es~~|9<br>~~ss~~|
|348<br>~~ss~~<br>~~es~~|8<br>~~ss~~<br>~~es~~|64<br>~~ss~~<br>~~es~~|9<br>~~ss~~|
|394<br>~~es~~<br>~~es~~|9<br>~~es~~<br>~~es~~<br>~~es~~|81<br>~~es~~<br>~~es~~<br>~~es~~|9<br>~~es~~|
|441<br>~~es~~|10<br>~~es~~<br>~~es~~|100<br>~~es~~<br>~~es~~|8<br>~~es~~|
|488<br>~~es~~<br>~~Ge~~|11<br>~~es~~<br>~~es~~<br>~~Ge~~|122<br>~~es~~<br>~~es~~<br>~~Ge~~|8<br>~~es~~<br>~~Ge~~|
|536<br>~~ss~~|12<br>~~ss~~|144<br>~~ss~~|8<br>~~ss~~|
|585<br>~~ee~~|13<br>~~ee~~|170<br>~~ee~~|8<br>~~ee~~|
|634<br>~~ss~~|14<br>~~ss~~<br>~~es~~|196<br>~~ss~~<br>~~es~~|7<br>~~ss~~|
|684<br>~~es~~|15<br>~~es~~<br>~~es~~|224<br>~~es~~<br>~~es~~|7<br>~~es~~|
|734<br>~~es~~<br>~~es~~|16<br>~~es~~<br>~~es~~<br>~~es~~<br>~~es~~|256<br>~~es~~<br>~~es~~<br>~~es~~|7<br>~~es~~<br>~~es~~|
|785<br>~~es~~|17<br>~~es~~<br>~~es~~|288<br>~~es~~|7<br>~~es~~|
|837<br>~~es~~<br>~~ee~~|18<br>~~es~~<br>~~es~~<br>~~ee~~|324<br>~~es~~<br>~~ee~~|7<br>~~es~~<br>~~ee~~|
|890<br>~~ss~~<br>~~es~~|19<br>~~ss~~<br>~~es~~|360<br>~~ss~~<br>~~es~~|6<br>~~ss~~|
|943<br>~~ss~~<br>~~es~~|20<br>~~ss~~<br>~~es~~|400<br>~~ss~~<br>~~es~~|6<br>~~ss~~|
|997<br>~~es~~<br>~~es~~|21<br>~~es~~<br>~~es~~<br>~~es~~|440<br>~~es~~<br>~~es~~<br>~~es~~|6<br>~~es~~|
|1051<br>~~es~~|22<br>~~es~~<br>~~es~~|488<br>~~es~~<br>~~es~~|6<br>~~es~~|
|1107<br>~~es~~<br>~~Ge~~|23<br>~~es~~<br>~~es~~<br>~~Ge~~|528<br>~~es~~<br>~~es~~<br>~~Ge~~|6<br>~~es~~<br>~~Ge~~|
|1163<br>~~ss~~|24<br>~~ss~~|576<br>~~ss~~|6<br>~~ss~~|
|1220<br>~~ee~~|25<br>~~ee~~|624<br>~~ee~~|6<br>~~ee~~|
|1277<br>~~ss~~|26<br>~~ss~~<br>~~es~~|680<br>~~ss~~|6<br>~~ss~~|
|1336<br>~~es~~|27<br>~~es~~<br>~~es~~|736<br>~~es~~|5<br>~~es~~|
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_**IIM-42652**_
|**3DB BANDWIDTH (HZ)**|**ACCEL_AAF_DELT;**<br>**GYRO_AAF_DELT**|**ACCEL_AAF_DELTSQR;**<br>**GYRO_AAF_DELTSQR**|**ACCEL_AAF_BITSHIFT;**<br>**GYRO_AAF_BITSHIFT**|
|---|---|---|---|
|1395<br>~~a~~|28<br><br>~~es~~|784<br><br>~~es~~|5<br>|
|1454<br>~~es~~|29<br>~~es~~<br>~~es~~|848<br>~~es~~<br>~~es~~|5<br>~~es~~|
|1515<br>~~es~~<br>~~Ge~~|30<br>~~es~~<br>~~es~~<br>~~Ge~~|896<br>~~es~~<br>~~es~~<br>~~Ge~~|5<br>~~es~~<br>~~Ge~~|
|1577<br>~~es~~|31<br>~~es~~|960<br>~~es~~|5<br>~~es~~|
|1639<br>~~es~~|32<br>~~es~~|1024<br>~~es~~|5<br>~~es~~|
|1702<br>~~ss~~|33<br>~~ss~~<br>~~es~~|1088<br>~~ss~~<br>~~es~~|5<br>~~ss~~|
|1766<br>~~es~~|34<br>~~es~~<br>~~es~~|1152<br>~~es~~<br>~~es~~|5<br>~~es~~|
|1830<br>~~es~~<br>~~es~~|35<br>~~es~~<br>~~es~~<br>~~es~~<br>~~es~~|1232<br>~~es~~<br>~~es~~<br>~~es~~|5<br>~~es~~<br>~~es~~|
|1896<br>~~es~~|36<br>~~es~~<br>~~es~~|1296<br>~~es~~|5<br>~~es~~|
|1962<br>~~ee~~|37<br>~~es~~<br>~~ee~~|1376<br>~~ee~~|4<br>~~ee~~|
|2029<br>~~es~~|38<br>~~es~~<br>~~es~~|1440<br>~~es~~|4<br>~~es~~|
|2097<br>~~es~~|39<br>~~es~~<br>~~es~~|1536<br>~~es~~|4<br>~~es~~|
|2166<br>~~es~~<br>~~es~~|40<br>~~es~~<br>~~es~~<br>~~es~~<br>~~es~~|1600<br>~~es~~<br>~~es~~<br>~~es~~|4<br>~~es~~<br>~~es~~|
|2235<br>~~es~~|41<br>~~es~~<br>~~es~~|1696<br>~~es~~<br>~~es~~|4<br>~~es~~|
|2306<br>~~es~~<br>~~Ge~~|42<br>~~es~~<br>~~es~~<br>~~Ge~~|1760<br>~~es~~<br>~~es~~<br>~~Ge~~|4<br>~~es~~<br>~~Ge~~|
|2377<br>~~es~~|43<br>~~es~~|1856<br>~~es~~|4<br>~~es~~|
|2449<br>~~es~~<br>~~ee~~|44<br>~~es~~<br>~~ee~~|1952<br>~~es~~<br>~~ee~~|4<br>~~es~~<br>~~ee~~|
|2522<br>~~ss~~|45<br>~~ss~~<br>~~es~~|2016<br>~~ss~~<br>~~es~~|4<br>~~ss~~|
|2596<br>~~es~~|46<br>~~es~~<br>~~es~~|2112<br>~~es~~<br>~~es~~|4<br>~~es~~|
|2671<br>~~es~~<br>~~es~~|47<br>~~es~~<br>~~es~~<br>~~es~~<br>~~es~~|2208<br>~~es~~<br>~~es~~<br>~~es~~|4<br>~~es~~<br>~~es~~|
|2746<br>~~es~~|48<br>~~es~~<br>~~es~~|2304<br>~~es~~|4<br>~~es~~|
|2823<br>~~ee~~|49<br>~~es~~<br>~~ee~~|2400<br>~~ee~~|4<br>~~ee~~|
|2900<br>~~ss~~<br>~~es~~|50<br>~~ss~~<br>~~es~~|2496<br>~~ss~~<br>~~es~~|4<br>~~ss~~|
|2978<br>~~ss~~<br>~~es~~|51<br>~~ss~~<br>~~es~~|2592<br>~~ss~~<br>~~es~~|4<br>~~ss~~|
|3057<br>~~es~~<br>~~es~~|52<br>~~es~~<br>~~es~~<br>~~es~~|2720<br>~~es~~<br>~~es~~<br>~~es~~|4<br>~~es~~|
|3137<br>~~es~~|53<br>~~es~~<br>~~es~~|2816<br>~~es~~<br>~~es~~|3<br>~~es~~|
|3217<br>~~es~~<br>~~Ge~~|54<br>~~es~~<br>~~es~~<br>~~Ge~~|2944<br>~~es~~<br>~~es~~<br>~~Ge~~|3<br>~~es~~<br>~~Ge~~|
|3299<br>~~es~~|55<br>~~es~~|3008<br>~~es~~|3<br>~~es~~|
|3381<br>~~ee~~|56<br>~~ee~~|3136<br>~~ee~~|3<br>~~ee~~|
|3464<br>~~ss~~|57<br>~~ss~~<br>~~es~~|3264<br>~~ss~~<br>~~es~~|3<br>~~ss~~|
|3548<br>~~es~~|58<br>~~es~~<br>~~es~~|3392<br>~~es~~<br>~~es~~|3<br>~~es~~|
|3633<br>~~es~~<br>~~es~~|59<br>~~es~~<br>~~es~~<br>~~es~~<br>~~es~~|3456<br>~~es~~<br>~~es~~<br>~~es~~|3<br>~~es~~<br>~~es~~|
|3718<br>~~es~~|60<br>~~es~~<br>~~es~~|3584<br>~~es~~|3<br>~~es~~|
|3805<br>~~es~~<br>~~ee~~|61<br>~~es~~<br>~~es~~<br>~~ee~~|3712<br>~~es~~<br>~~ee~~|3<br>~~es~~<br>~~ee~~|
|3892<br>~~ss~~|62<br>~~ss~~|3840<br>~~ss~~|3<br>~~ss~~|
|3979<br>~~ss~~<br>~~es~~|63<br>~~ss~~<br>~~es~~|3968<br>~~ss~~<br>~~es~~|3<br>~~ss~~<br>~~es~~|
The anti-alias filter can be selected or bypassed for the gyroscope by using the parameter GYRO_AAF_DIS in register bank 1, register 0x0Bh, bit 1 as shown below.
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|**GYRO_AAF_DIS**|**FUNCTION**|
|---|---|
|0|Enable gyroscope anti-aliasing filter|
|1|Disable gyroscope anti-aliasing filter|
The anti-alias filter can be selected or bypassed for the accelerometer by using the parameter ACCEL_AAF_DIS in register bank 2, register 0x03h, bit 0 as shown below.
|**ACCEL_AAF_DIS**|**FUNCTION**|
|---|---|
|0|Enable accelerometer anti-aliasing filter|
|1|Disable accelerometer anti-aliasing filter|
## **USER PROGRAMMABLE OFFSET**
Gyroscope and accelerometer offsets can be programmed by the user by using registers OFFSET_USER0, through OFFSET_USER8, in bank 0, registers 0x77h through 0x7Fh (bank 4) as shown below.
|**REGISTER ADDRESS**|**REGISTER NAME**|**BITS**|**FUNCTION**|
|---|---|---|---|
|0x77h|OFFSET_USER0|7:0|Lower bits of X-gyro offset programmed by user. Max<br>value is ±64 dps,resolution is 1/32 dps.|
|0x78h|OFFSET_USER1|3:0|Upper bits of X-gyro offset programmed by user. Max<br>value is ±64 dps,resolution is 1/32 dps.|
|||7:4|Upper bits of Y-gyro offset programmed by user. Max<br>value is ±64 dps,resolution is 1/32 dps.|
|0x79h|OFFSET_USER2|7:0|Lower bits of Y-gyro offset programmed by user. Max<br>value is ±64 dps,resolution is 1/32 dps.|
|0x7Ah|OFFSET_USER3|7:0|Lower bits of Z-gyro offset programmed by user. Max<br>value is ±64 dps,resolution is 1/32 dps.|
|0x7Bh|OFFSET_USER4|3:0|Upper bits of Z-gyro offset programmed by user. Max<br>value is ±64 dps,resolution is 1/32 dps.|
|||7:4|Upper bits of X-accel offset programmed by user. Max<br>value is ±1g,resolution is 0.5 mg.|
|0x7Ch|OFFSET_USER5|7:0|Lower bits of X-accel offset programmed by user. Max<br>value is ±1g,resolution is 0.5 mg.|
|0x7Dh|OFFSET_USER6|7:0|Lower bits of Y-accel offset programmed by user. Max<br>value is ±1g,resolution is 0.5 mg.|
|0x7Eh|OFFSET_USER7|3:0|Upper bits of Y-accel offset programmed by user. Max<br>value is ±1g,resolution is 0.5 mg.|
|||7:4|Upper bits of Z-accel offset programmed by user. Max<br>value is ±1g,resolution is 0.5 mg.|
|0x7Fh|OFFSET_USER8|7:0|Lower bits of Z-accel offset programmed by user. Max<br>value is ±1g,resolution is 0.5 mg.|
## **UI FILTER BLOCK**
The UI filter block can be programmed to select filter order and bandwidth independently for gyroscope and accelerometer.
Gyroscope filter order can be selected by programming the parameter GYRO_UI_FILT_ORD in register bank 0, register 0x51h, bits 3:2, as shown below.
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|**GYRO_UI_FILT_ORD**|**FILTER ORDER**|
|---|---|
|00|1storder|
|01|2ndorder|
|10|3rdorder|
|11|Reserved|
Accelerometer filter order can be selected by programming the parameter ACCEL_UI_FILT_ORD in register bank 0, register 0x53h, bits 4:3, as shown below.
|**ACCEL_UI_FILT_ORD**|**FILTER ORDER**|
|---|---|
|00|1storder|
|01|2ndorder|
|10|3rdorder|
|11|Reserved|
Gyroscope and accelerometer filter 3dB bandwidth can be selected by programming the parameter GYRO_UI_FILT_BW in register bank 0, register 0x52h, bits 3:0, and the parameter ACCEL_UI_FILT_BW in register bank 0, register 0x52h, bits 7:4, as shown below. The values shown in bold correspond to low noise and the values shown in italics correspond to low latency. User can select the appropriate setting based on the application requirements for power and latency. Corresponding Noise Bandwidth (NBW) and Group Delay values are also shown.
## **1[st] Order Filter 3dB Bandwidth, Noise Bandwidth (NBW), Group Delay**
||**3dB Bandwidth(Hz) for GYRO/ACCEL_UI_FILT_ORD=0(1st order filter)**|**3dB Bandwidth(Hz) for GYRO/ACCEL_UI_FILT_ORD=0(1st order filter)**|**3dB Bandwidth(Hz) for GYRO/ACCEL_UI_FILT_ORD=0(1st order filter)**|**3dB Bandwidth(Hz) for GYRO/ACCEL_UI_FILT_ORD=0(1st order filter)**|**3dB Bandwidth(Hz) for GYRO/ACCEL_UI_FILT_ORD=0(1st order filter)**|**3dB Bandwidth(Hz) for GYRO/ACCEL_UI_FILT_ORD=0(1st order filter)**|**3dB Bandwidth(Hz) for GYRO/ACCEL_UI_FILT_ORD=0(1st order filter)**|**3dB Bandwidth(Hz) for GYRO/ACCEL_UI_FILT_ORD=0(1st order filter)**|**3dB Bandwidth(Hz) for GYRO/ACCEL_UI_FILT_ORD=0(1st order filter)**|**3dB Bandwidth(Hz) for GYRO/ACCEL_UI_FILT_ORD=0(1st order filter)**|**3dB Bandwidth(Hz) for GYRO/ACCEL_UI_FILT_ORD=0(1st order filter)**|
|---|---|---|---|---|---|---|---|---|---|---|---|
|~~po~~<br>~~rrti(CT~~|~~CT~~|GYRO/ACCEL_UI_FILT_BW<br>~~CT~~||||||||||
|GYRO/ACCEL_ODR<br>~~po~~<br>~~rrti(CT~~|ODR(Hz)<br>~~CT~~|0<br>~~CT~~|1<br>~~CT~~|2|3|4|5|6|7|14|15|
|1<br>~~po~~<br>~~rrti(CT~~<br>~~ee~~<br>~~re~~|32000<br>~~CT~~<br>~~ee~~|_8400.0_<br>~~CT~~<br>~~ee~~||||||||||
|2<br>~~ee~~<br>~~re~~|16000<br>~~ee~~|_4194.1_<br>~~ee~~||||||||||
|3<br>~~re~~<br>~~ee~~|8000<br>~~ee~~|_2096.30_<br>~~ee~~||||||||||
|4<br>~~ee~~<br>~~ee~~<br>~~re~~|4000<br>~~ee~~<br>~~ee~~|_1048.10_<br>~~ee~~<br>~~ee~~||||||||||
|5<br>~~ee~~<br>~~re~~<br>~~po~~<br>~~rrrtc“(ite~~|2000<br>~~ee~~<br>~~rrrtc“(ite~~<br>~~Em~~|_524.00_<br>~~ee~~<br>~~Em~~<br>~~em~~||||||||||
|6<br>~~re~~<br>~~po~~<br>~~rrrtc“(ite~~<br>~~po~~<br>~~rrti“<i‘iTt~~|1000<br>~~rrrtc“(ite~~<br>~~Em~~<br>~~rrti“<i‘iTtTE~~|**498.30**<br>~~Em~~<br>~~TE~~|**227.20**<br>~~em~~|**188.90**<br>~~em~~|**111.00**|**92.40**|**59.60**|**48.80**|**23.90**|**262.00**|_2096.30_|
|15<br>~~po~~<br>~~rrrtc“(ite~~<br>~~po~~<br>~~rrti“<i‘iTt~~<br>~~po~~<br>~~rrti“<i‘iT~~|500<br>~~rrrtc“(ite~~<br>~~Em~~<br>~~rrti“<i‘iTtTE~~<br>~~rrti“<i‘iT~~|**249.10**<br>~~Em~~<br>~~TE~~|**113.60**<br>~~em~~|**94.40**<br>~~em~~|**55.50**|**46.20**|**29.80**|**24.40**|**11.90**|**131.00**|_1048.10_|
|7<br>~~po~~<br>~~rrti“<i‘iTt~~<br>~~po~~<br>~~rrti“<i‘iT~~<br>~~po~~<br>~~rrti“<i‘iTt~~|200<br>~~rrti“<i‘iTt TE~~<br>~~rrti“<i‘iT~~<br>~~rrti“<i‘iTtEr~~|**99.60**<br>~~TE~~<br>~~Er~~|**90.90**|**75.50**|**44.40**|**37.00**|**23.80**|**19.50**|**9.60**|_104.80_|_419.20_|
|8<br>~~po~~<br>~~rrti“<i‘iT~~<br>~~po~~<br>~~rrti“<i‘iTt~~<br>~~Po~~<br>~~rrt—C~~|100<br>~~rrti“<i‘iT~~<br>~~rrti“<i‘iTtEr~~<br>~~rrt—Cet~~|**49.80**<br>~~Er~~<br>~~et~~|_90.90_|_75.50_|**44.40**|**37.00**|**23.80**|**19.50**|**9.60**|_104.80_|_209.60_|
|9<br>~~po~~<br>~~rrti“<i‘iTt~~<br>~~Po~~<br>~~rrt—C~~<br>~~po~~|50<br>~~rrti“<i‘iTt Er~~<br>~~rrt—Cet~~|**24.90**<br>~~Er~~<br>~~et~~|_90.90_<br>~~Cr~~|_75.50_<br>~~CrCE~~|_44.40_<br>~~CE~~|_37.00_|**23.80**|**19.50**|**9.60**|_104.80_|_104.80_|
|10<br>~~Po~~<br>~~rrt—C~~<br>~~po~~<br>~~rrti“‘LSCTCUT~~|25<br>~~rrt—C et~~<br>~~rrti“‘LSCTCUT~~|**12.50**<br>~~et~~<br>~~rrti“‘LSCTCUT~~|_90.90_<br>~~rrti“‘LSCTCUT~~<br>~~Cr~~|_75.50_<br>~~rrti“‘LSCTCUT~~<br>~~CrCE~~<br>~~CUE~~|_44.40_<br>~~rrti“‘LSCTCUT~~<br>~~CE~~<br>~~CUECE~~|_37.00_<br>~~rrti“‘LSCTCUT~~<br>~~CE~~|_23.80_<br>~~rrti“‘LSCTCUT~~|_19.50_<br>~~rrti“‘LSCTCUT~~|**9.60**<br>~~rrti“‘LSCTCUT~~|_104.80_<br>~~rrti“‘LSCTCUT~~|_52.40_<br>~~rrti“‘LSCTCUT~~|
|11<br>~~po~~<br>~~prrti“‘“C‘é*dLSCCYTCDCUTCUCUdE~~|12.5<br>~~prrti“‘“C‘é*dLSCCYTCDCUTCUCUdE~~|_12.50_<br>~~prrti“‘“C‘é*dLSCCYTCDCUTCUCUdE~~|_90.90_<br>~~Cr~~<br>~~prrti“‘“C‘é*dLSCCYTCDCUTCUCUdE~~|_75.50_<br>~~Cr CE~~<br>~~prrti“‘“C‘é*dLSCCYTCDCUTCUCUdE~~<br>~~CUE~~|_44.40_<br>~~CE~~<br>~~prrti“‘“C‘é*dLSCCYTCDCUTCUCUdE~~<br>~~CUECE~~|_37.00_<br>~~prrti“‘“C‘é*dLSCCYTCDCUTCUCUdE~~<br>~~CE~~|_23.80_<br>~~prrti“‘“C‘é*dLSCCYTCDCUTCUCUdE~~|_19.50_<br>~~prrti“‘“C‘é*dLSCCYTCDCUTCUCUdE~~|_9.60_<br>~~prrti“‘“C‘é*dLSCCYTCDCUTCUCUdE~~|_104.80_<br>~~prrti“‘“C‘é*dLSCCYTCDCUTCUCUdE~~|_52.40_<br>~~prrti“‘“C‘é*dLSCCYTCDCUTCUCUdE~~|
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_**IIM-42652**_
||**NBW Bandwidth(Hz) for GYRO/ACCEL_UI_FILT_ORD=0(1st order filter)**|**NBW Bandwidth(Hz) for GYRO/ACCEL_UI_FILT_ORD=0(1st order filter)**|**NBW Bandwidth(Hz) for GYRO/ACCEL_UI_FILT_ORD=0(1st order filter)**|**NBW Bandwidth(Hz) for GYRO/ACCEL_UI_FILT_ORD=0(1st order filter)**|**NBW Bandwidth(Hz) for GYRO/ACCEL_UI_FILT_ORD=0(1st order filter)**|**NBW Bandwidth(Hz) for GYRO/ACCEL_UI_FILT_ORD=0(1st order filter)**|**NBW Bandwidth(Hz) for GYRO/ACCEL_UI_FILT_ORD=0(1st order filter)**|**NBW Bandwidth(Hz) for GYRO/ACCEL_UI_FILT_ORD=0(1st order filter)**|**NBW Bandwidth(Hz) for GYRO/ACCEL_UI_FILT_ORD=0(1st order filter)**|**NBW Bandwidth(Hz) for GYRO/ACCEL_UI_FILT_ORD=0(1st order filter)**|**NBW Bandwidth(Hz) for GYRO/ACCEL_UI_FILT_ORD=0(1st order filter)**|
|---|---|---|---|---|---|---|---|---|---|---|---|
|~~po~~<br>~~rrti“‘<‘ TT~~|~~TT~~|GYRO/ACCEL_UI_FILT_BW||||||||||
|GYRO/ACCEL_ODR<br>~~po~~<br>~~rrti“‘<‘ TT~~|ODR(Hz)<br>~~TT~~|0|1|2|3|4|5|6|7|14|15|
|1<br>~~po~~<br>~~rrti“‘<‘ TT~~<br>~~en~~|32000<br>~~TT~~<br>~~en~~|_8831.7_||||||||||
|2<br>~~ee~~<br>~~es i~~|16000<br>~~ee~~<br>~~i~~|_4410.6_||||||||||
|3<br>~~es i~~<br>~~es ee~~|8000<br>~~i~~<br>~~ee~~|_2204.6_||||||||||
|4<br>~~es i~~<br>~~es ee~~|4000<br>~~i~~<br>~~ee~~|_1102.2_||||||||||
|5<br>~~es ee~~<br>~~ee~~<br>~~Prt~~|2000<br>~~ee~~<br>~~ee~~<br>~~er~~|_551.1_<br>~~er~~||||||||||
|6<br>~~ee~~<br>~~Prt~~<br>~~Prt~~|1000<br>~~ee~~<br>~~er~~<br>~~er~~|**551.1**<br>~~er~~<br>~~er~~|**230.8**|**196.3**|**126.5**|**108.9**|**75.8**|**64.1**|**34.1**|**275.6**|_2204.6_|
|15<br>~~Prt ~~<br>~~Prt~~<br>~~Prt(te~~|500<br> ~~er~~<br>~~er~~<br>~~(te~~|**280.5**<br>~~er~~<br>~~er~~|**115.4**|**98.2**|**63.3**|**54.5**|**37.9**|**32.1**|**17.1**|**137.8**|_1102.2_|
|7<br>~~Prt ~~<br>~~Prt(te~~<br>~~po~~<br>~~rrtc“(_e~~|200<br> ~~er~~<br>~~(te~~<br>~~rrtc“(_e~~|**112.2**<br>~~er~~|**92.4**|**78.5**|**50.6**|**43.6**|**30.3**|**25.7**|**13.7**|_110.3_|_440.9_|
|8<br>~~Prt(te~~<br>~~po~~<br>~~rrtc“(_e~~<br>~~po~~<br>~~rrrtc“(t~~|100<br>~~(te~~<br>~~rrtc“(_e~~<br>~~rrrtc“(t~~<br>~~TE~~|**56.1**<br>~~TE~~|_92.4_<br>~~mr~~|_78.5_<br>~~mr~~|**50.6**|**43.6**|**30.3**|**25.7**|**13.7**|_110.3_|_220.5_|
|9<br>~~po~~<br>~~rrtc“(_e~~<br>~~po~~<br>~~rrrtc“(t~~<br>~~po~~<br>~~rrti“‘T~~|50<br>~~rrtc“(_e~~<br>~~rrrtc“(t~~<br>~~TE~~<br>~~rrti“‘T~~|**28.1**<br>~~TE~~|_92.4_<br>~~mr~~|_78.5_<br>~~mr~~|_50.6_|_43.6_|**30.3**|**25.7**|**13.7**|_110.3_|_110.3_|
|10<br>~~po~~<br>~~rrrtc“(t~~<br>~~po~~<br>~~rrti“‘T~~<br>~~pF~~|25<br>~~rrrtc“(t~~<br>~~TE~~<br>~~rrti“‘T~~<br>|**14.1**<br>~~TE~~<br>|_92.4_<br>~~mr~~<br>|_78.5_<br>~~mr~~<br><br>~~CUE~~|_50.6_<br><br>~~CUErE~~|_43.6_<br><br>~~rECE~~|_30.3_<br><br>~~CE |~~|_25.7_<br><br>~~|~~|**13.7**<br><br>~~|~~|_110.3_<br><br>~~|~~|_55.2_<br><br>~~|~~|
|11<br>~~po~~<br>~~rrti“‘T~~<br>~~pFrrti“‘“aYSUCTTCUhUmEUhUhmdEL~~|12.5<br>~~rrti“‘T~~<br>~~rrti“‘“aYSUCTTCUhUmEUhUhmdEL~~|_14.1_<br>~~rrti“‘“aYSUCTTCUhUmEUhUhmdEL~~|_92.4_<br>~~rrti“‘“aYSUCTTCUhUmEUhUhmdEL~~|_78.5_<br>~~rrti“‘“aYSUCTTCUhUmEUhUhmdEL~~<br>~~CUE~~|_50.6_<br>~~rrti“‘“aYSUCTTCUhUmEUhUhmdEL~~<br>~~CUErE~~|_43.6_<br>~~rrti“‘“aYSUCTTCUhUmEUhUhmdEL~~<br>~~rECE~~|_30.3_<br>~~rrti“‘“aYSUCTTCUhUmEUhUhmdEL~~<br>~~CE |~~|_25.7_<br>~~rrti“‘“aYSUCTTCUhUmEUhUhmdEL~~<br>~~|~~|_13.7_<br>~~rrti“‘“aYSUCTTCUhUmEUhUhmdEL~~<br>~~|~~|_110.3_<br>~~rrti“‘“aYSUCTTCUhUmEUhUhmdEL~~<br>~~|~~|_55.2_<br>~~rrti“‘“aYSUCTTCUhUmEUhUhmdEL~~<br>~~|~~|
||**Group Delay @DC(ms) for GYRO/ACCEL_UI_FILT_ORD=0(1st order filter)**|**Group Delay @DC(ms) for GYRO/ACCEL_UI_FILT_ORD=0(1st order filter)**|**Group Delay @DC(ms) for GYRO/ACCEL_UI_FILT_ORD=0(1st order filter)**|**Group Delay @DC(ms) for GYRO/ACCEL_UI_FILT_ORD=0(1st order filter)**|**Group Delay @DC(ms) for GYRO/ACCEL_UI_FILT_ORD=0(1st order filter)**|**Group Delay @DC(ms) for GYRO/ACCEL_UI_FILT_ORD=0(1st order filter)**|**Group Delay @DC(ms) for GYRO/ACCEL_UI_FILT_ORD=0(1st order filter)**|**Group Delay @DC(ms) for GYRO/ACCEL_UI_FILT_ORD=0(1st order filter)**|**Group Delay @DC(ms) for GYRO/ACCEL_UI_FILT_ORD=0(1st order filter)**|**Group Delay @DC(ms) for GYRO/ACCEL_UI_FILT_ORD=0(1st order filter)**|**Group Delay @DC(ms) for GYRO/ACCEL_UI_FILT_ORD=0(1st order filter)**|
|---|---|---|---|---|---|---|---|---|---|---|---|
|~~es~~|~~es~~|GYRO/ACCEL_UI_FILT_BW<br>~~esssGeGO~~<br>~~Gs~~||||||||||
|GYRO/ACCEL_ODR<br>~~es~~<br>~~ee~~|ODR(Hz)<br>~~es~~|0<br>~~es~~|1<br>~~ss~~|2<br>~~ss~~|3<br>~~Ge~~|4<br>~~GO~~|5|6<br>~~Gs~~|7<br>~~Gs~~|14|15|
|1<br>~~es ~~<br>~~ee~~|32000<br> ~~es~~|_0.1_<br>~~es ss Ge GO~~<br>~~Gs~~||||||||||
|2<br>~~ee~~<br>~~ee~~|16000<br>~~ee~~|_0.1_<br>~~ee~~||||||||||
|3<br>~~ee~~<br>~~A~~|8000<br>~~ee~~<br>~~A~~|_0.2_<br>~~ee~~<br>~~A~~||||||||||
|4<br>~~A~~<br>~~ee~~|4000<br>~~A~~<br>~~ee~~|_0.4_<br>~~A~~<br>~~ee~~||||||||||
|5<br>~~ee~~<br>~~Po~~<br>~~rrrtc“(t~~|2000<br>~~ee~~<br>~~rrrtc“(t~~<br>~~Er~~|_0.8_<br>~~ee~~<br>~~Er~~||||||||||
|6<br>~~ee~~<br>~~Po~~<br>~~rrrtc“(t~~<br>~~po~~<br>~~rrti“‘T~~|1000<br>~~ee~~<br>~~rrrtc“(t~~<br>~~Er~~<br>~~rrti“‘T~~|**0.6**<br>~~ee~~<br>~~Er~~|**1.8**<br>~~ee~~|**2.0**<br>~~ee~~|**2.8**<br>~~ee~~|**3.1**<br>~~ee~~|**4.1**<br>~~ee~~|**4.7**<br>~~ee~~|**8.1**<br>~~ee~~|**1.5**<br>~~ee~~|_0.2_<br>~~ee~~|
|15<br>~~Po~~<br>~~rrrtc“(t~~<br>~~po~~<br>~~rrti“‘T~~<br>~~Po~~<br>~~rrrti“‘i‘iT~~|500<br>~~rrrtc“(t~~<br>~~Er~~<br>~~rrti“‘T~~<br>~~rrrti“‘i‘iT~~|**1.1**<br>~~Er~~|**3.6**|**4.0**|**5.5**|**6.1**|**8.1**|**9.3**|**16.2**|**3.0**|_0.4_|
|7<br>~~po~~<br>~~rrti“‘T~~<br>~~Po~~<br>~~rrrti“‘i‘iT~~<br>~~Po~~<br>~~rrti“‘iT~~|200<br>~~rrti“‘T~~<br>~~rrrti“‘i‘iT~~<br>~~rrti“‘iT~~|**2.7**|**4.4**|**5.0**|**6.8**|**7.6**|**10.2**|**11.7**|**20.3**|_3.8_|_1.0_|
|8<br>~~Po~~<br>~~rrrti“‘i‘iT~~<br>~~Po~~<br>~~rrti“‘iT~~<br>~~Po~~<br>~~rrt—“(CS~~|100<br>~~rrrti“‘i‘iT~~<br>~~rrti“‘iT~~<br>~~rrt—“(CSse~~|**5.3**<br>~~se~~|_4.4_|_5.0_|**6.8**|**7.6**|**10.2**|**11.7**|**20.3**|_3.8_|_1.9_|
|9<br>~~Po~~<br>~~rrti“‘iT~~<br>~~Po~~<br>~~rrt—“(CS~~<br>~~po~~<br>~~prt~~|50<br>~~rrti“‘iT~~<br>~~rrt—“(CSse~~<br>|**10.5**<br>~~se~~|_4.4_<br>~~CT~~|_5.0_<br>~~CT~~|_6.8_|_7.6_|**10.2**|**11.7**|**20.3**|_3.8_|_3.8_|
|10<br>~~Po~~<br>~~rrt—“(CS~~<br>~~po~~<br>~~rrti“‘LSUTCUT~~<br>~~prt te~~|25<br>~~rrt—“(CS se~~<br>~~rrti“‘LSUTCUT~~<br>~~te~~|**21.0**<br>~~se~~<br>~~rrti“‘LSUTCUT~~|_4.4_<br>~~rrti“‘LSUTCUT~~<br>~~CT~~|_5.0_<br>~~rrti“‘LSUTCUT~~<br>~~CT~~|_6.8_<br>~~rrti“‘LSUTCUT~~|_7.6_<br>~~rrti“‘LSUTCUT~~|_10.2_<br>~~rrti“‘LSUTCUT~~|_11.7_<br>~~rrti“‘LSUTCUT~~|**20.3**<br>~~rrti“‘LSUTCUT~~|_3.8_<br>~~rrti“‘LSUTCUT~~|_7.5_<br>~~rrti“‘LSUTCUT~~|
|11<br>~~po~~<br>~~prt te~~|12.5<br>~~te~~|_21.0_|_4.4_<br>~~CT~~|_5.0_<br>~~CT~~|_6.8_|_7.6_|_10.2_|_11.7_|_20.3_|_3.8_|_7.5_|
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Document Number: DS-000401 Revision: 1.3
_**IIM-42652**_
**2[nd ] Order Filter 3dB Bandwidth, Noise Bandwidth (NBW), Group Delay**
||**3dB Bandwidth(Hz) for GYRO/ACCEL_UI_FILT_ORD=1(2nd order filter)**|**3dB Bandwidth(Hz) for GYRO/ACCEL_UI_FILT_ORD=1(2nd order filter)**|**3dB Bandwidth(Hz) for GYRO/ACCEL_UI_FILT_ORD=1(2nd order filter)**|**3dB Bandwidth(Hz) for GYRO/ACCEL_UI_FILT_ORD=1(2nd order filter)**|**3dB Bandwidth(Hz) for GYRO/ACCEL_UI_FILT_ORD=1(2nd order filter)**|**3dB Bandwidth(Hz) for GYRO/ACCEL_UI_FILT_ORD=1(2nd order filter)**|**3dB Bandwidth(Hz) for GYRO/ACCEL_UI_FILT_ORD=1(2nd order filter)**|**3dB Bandwidth(Hz) for GYRO/ACCEL_UI_FILT_ORD=1(2nd order filter)**|**3dB Bandwidth(Hz) for GYRO/ACCEL_UI_FILT_ORD=1(2nd order filter)**|**3dB Bandwidth(Hz) for GYRO/ACCEL_UI_FILT_ORD=1(2nd order filter)**|**3dB Bandwidth(Hz) for GYRO/ACCEL_UI_FILT_ORD=1(2nd order filter)**|
|---|---|---|---|---|---|---|---|---|---|---|---|
|~~pri“tid~~|~~tid~~|GYRO/ACCEL_UI_FILT_BW<br>~~em~~||||||||||
|GYRO/ACCEL_ODR<br>~~pri“tid~~|ODR(Hz)<br>~~tid~~<br>~~ee~~|0<br>~~em~~|1|2|3|4|5|6|7|14|15|
|1<br>~~pri“tid~~<br>~~ee~~|32000<br>~~tid~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|_8400.0_<br>~~em~~||||||||||
|2<br>~~ee~~|16000<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|_4194.1_||||||||||
|3<br>~~ee~~|8000<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~eee~~|_2096.3_||||||||||
|4<br>~~ee~~|4000<br>~~ee~~<br>~~ee~~<br>~~eee~~<br>~~ee~~|_1048.1_<br>~~ee~~||||||||||
|5<br>~~ee~~<br>~~po~~|2000<br>~~eee~~<br>~~ee~~<br>~~ee~~|_524.0_<br>~~ee~~<br>~~CUTE~~<br>~~Cr~~||||||||||
|6<br>~~prrti“‘“‘iYS~~<br>~~po~~<br>~~rrrtc“(t~~<br>~~Po~~|1000<br>~~ee~~<br>~~prrti“‘“‘iYS~~<br>~~rrrtc“(t~~|**493.3**<br>~~ee~~<br>~~prrti“‘“‘iYS~~<br>~~CUTE~~|**230.7**<br>~~prrti“‘“‘iYS~~<br>~~CUTE~~|**191.6**<br>~~prrti“‘“‘iYS~~<br>~~CUTE~~|**117.5**<br>~~prrti“‘“‘iYS~~<br>~~Cr~~|**97.1**<br>~~prrti“‘“‘iYS~~<br>~~Cr~~|**59.6**<br>~~prrti“‘“‘iYS~~|**48.0**<br>~~prrti“‘“‘iYS~~|**21.3**<br>~~prrti“‘“‘iYS~~|**262.0**<br>~~prrti“‘“‘iYS~~|_2096.3_<br>~~prrti“‘“‘iYS~~|
|15<br>~~po~~<br>~~rrrtc“(t~~<br>~~Po~~<br>~~rrtc(dL~~|500<br>~~rrrtc“(t~~<br>~~dL~~|**246.7**<br>~~CUTE~~<br>~~em~~|**115.3**<br>~~CUTE~~<br>~~em~~|**95.8**<br>~~CUTE~~|**58.8**<br>~~Cr~~|**48.5**<br>~~Cr~~|**29.8**|**24.0**|**10.6**|**131.0**|_1048.1_|
|7<br>~~po~~<br>~~rrrtc“(t~~<br>~~Po~~<br>~~rrtc(dL~~<br>~~Porc“tL~~|200<br>~~rrrtc“(t~~<br>~~dL~~<br>~~tL~~|**98.7**<br>~~CUTE~~<br>~~em~~|**92.3**<br>~~CUTE~~<br>~~em~~|**76.6**<br>~~CUTE~~|**47.0**<br>~~Cr~~|**38.8**<br>~~Cr~~|**23.8**|**19.2**|**8.5**|_104.8_|_419.2_|
|8<br>~~rrrtc“(t~~<br>~~Po~~<br>~~rrtc( dL~~<br>~~Porc“tL~~<br>~~Pri“td~~|100<br>~~rrrtc“(t~~<br>~~dL~~<br>~~tL~~<br>~~td~~|**49.3**<br>~~em~~<br>~~mr~~|_92.3_<br>~~em~~<br>~~mr~~|_76.6_|**47.0**|**38.8**|**23.8**|**19.2**|**8.5**|_104.8_|_209.6_|
|9<br>~~Porc“tL~~<br>~~Pri“td~~<br>~~po~~<br>~~rrti“(‘iesd~~|50<br>~~tL~~<br>~~td~~<br>~~rrti“(‘iesd~~<br>~~mE~~|**24.7**<br>~~mr~~<br>~~mErE~~|_92.3_<br>~~mr~~<br>~~rE~~|_76.6_|_47.0_|_38.8_|**23.8**|**19.2**|**8.5**|_104.8_|_104.8_|
|10<br>~~Pri“td~~<br>~~po~~<br>~~rrti“(‘iesd~~<br>~~prc“tw™CUmdE~~|25<br>~~td~~<br>~~rrti“(‘iesd~~<br>~~mE~~<br>~~tw™CUmdELm~~|**12.3**<br>~~mr~~<br>~~mErE~~<br>~~mE~~|_92.3_<br>~~mr~~<br>~~rE~~<br>~~mE~~|_76.6_|_47.0_|_38.8_|_23.8_|_19.2_|**8.5**|_104.8_|_52.4_|
|11<br>~~po~~<br>~~rrti“(‘iesd~~<br>~~prc“tw™CUmdE~~|12.5<br>~~rrti“(‘iesd~~<br>~~mE~~<br>~~tw™CUmdELm~~|_12.3_<br>~~mE rE~~<br>~~mE~~|_92.3_<br>~~rE~~<br>~~mE~~|_76.6_|_47.0_|_38.8_|_23.8_|_19.2_|_8.5_|_104.8_|_52.4_|
||**NBW Bandwidth(Hz) for GYRO/ACCEL_UI_FILT_ORD=1(2nd order filter)**|**NBW Bandwidth(Hz) for GYRO/ACCEL_UI_FILT_ORD=1(2nd order filter)**|**NBW Bandwidth(Hz) for GYRO/ACCEL_UI_FILT_ORD=1(2nd order filter)**|**NBW Bandwidth(Hz) for GYRO/ACCEL_UI_FILT_ORD=1(2nd order filter)**|**NBW Bandwidth(Hz) for GYRO/ACCEL_UI_FILT_ORD=1(2nd order filter)**|**NBW Bandwidth(Hz) for GYRO/ACCEL_UI_FILT_ORD=1(2nd order filter)**|**NBW Bandwidth(Hz) for GYRO/ACCEL_UI_FILT_ORD=1(2nd order filter)**|**NBW Bandwidth(Hz) for GYRO/ACCEL_UI_FILT_ORD=1(2nd order filter)**|**NBW Bandwidth(Hz) for GYRO/ACCEL_UI_FILT_ORD=1(2nd order filter)**|**NBW Bandwidth(Hz) for GYRO/ACCEL_UI_FILT_ORD=1(2nd order filter)**|**NBW Bandwidth(Hz) for GYRO/ACCEL_UI_FILT_ORD=1(2nd order filter)**|
|---|---|---|---|---|---|---|---|---|---|---|---|
|||GYRO/ACCEL_UI_FILT_BW<br>~~lm~~||||||||||
|GYRO/ACCEL_ODR<br>~~prrti“‘“‘i;S~~|ODR(Hz)<br>~~prrti“‘“‘i;S~~|0<br>~~prrti“‘“‘i;S~~<br>~~lm~~|1<br>~~prrti“‘“‘i;S~~<br>~~lm~~|2<br>~~prrti“‘“‘i;S~~|3<br>~~prrti“‘“‘i;S~~|4<br>~~prrti“‘“‘i;S~~|5<br>~~prrti“‘“‘i;S~~|6<br>~~prrti“‘“‘i;S~~|7<br>~~prrti“‘“‘i;S~~|14<br>~~prrti“‘“‘i;S~~|15<br>~~prrti“‘“‘i;S~~|
|1<br>~~eG~~|32000<br>~~eG~~|_8831.7_<br>~~lm~~<br>~~eG~~||||||||||
|2<br>~~eG~~|16000<br>~~eG~~|_4410.6_<br>~~eG~~||||||||||
|3<br>~~ee~~<br>~~es~~|8000<br>~~ee~~|_2204.6_<br>~~ee~~||||||||||
|4<br>~~es~~<br>~~re~~|4000|_1102.2_||||||||||
|5<br>~~es~~<br>~~re~~<br>~~Pri(dL~~|2000<br>~~(dL~~|_551.1_<br>~~em~~||||||||||
|6<br>~~re~~<br>~~Pri(dL~~<br>~~Porc“tL~~|1000<br>~~(dL~~<br>~~tL~~|**551.1**<br>~~em~~|**223.7**<br>~~em~~|**189.9**|**122.7**|**102.8**|**64.7**|**52.5**|**23.7**|**275.6**|_2204.6_|
|15<br>~~Pri(dL~~<br>~~Porc“tL~~<br>~~Po~~<br>~~rrrti“(tL~~|500<br>~~(dL~~<br>~~tL~~<br>~~tL~~|**259.6**<br>~~em~~<br>~~mr~~|**111.9**<br>~~em~~<br>~~mr~~|**95.0**|**61.4**|**51.4**|**32.4**|**26.3**|**11.9**|**137.8**|_1102.2_|
|7<br>~~Porc“tL~~<br>~~Po~~<br>~~rrrti“(tL~~<br>~~po~~<br>~~rrti“(“‘“iES~~|200<br>~~tL~~<br>~~tL~~<br>~~rrti“(“‘“iESUT~~|**103.9**<br>~~mr~~<br>~~UThUmThmhUmTLUT~~|**89.5**<br>~~mr~~<br>~~hUmThmhUmTLUT~~|**76.0**<br>~~hUmThmhUmTLUT~~|**49.1**<br>~~hUmThmhUmTLUT~~|**41.2**|**25.9**|**21.0**|**9.5**|_110.3_|_440.9_|
|8<br>~~Po~~<br>~~rrrti“(tL~~<br>~~po~~<br>~~rrti“(“‘“iES~~<br>~~po~~<br>~~rrti“(“‘“i;S~~|100<br>~~tL~~<br>~~rrti“(“‘“iESUT~~<br>~~rrti“(“‘“i;S~~<br>~~TT~~|**52.0**<br>~~mr~~<br>~~UThUmThmhUmTLUT~~<br>~~TThUThUhUmT~~|_89.5_<br>~~mr~~<br>~~hUmThmhUmTLUT~~<br>~~hUThUhUmT~~|_76.0_<br>~~hUmThmhUmTLUT~~<br>~~hUThUhUmTUTE~~|**49.1**<br>~~hUmThmhUmTLUT~~<br>~~UTE~~|**41.2**<br>~~UTE~~|**25.9**|**21.0**|**9.5**|_110.3_|_220.5_|
|9<br>~~po~~<br>~~rrti“(“‘“iES~~<br>~~po~~<br>~~rrti“(“‘“i;S~~<br>~~po~~<br>~~rrti“‘“iLS~~|50<br>~~rrti“(“‘“iES UT~~<br>~~rrti“(“‘“i;S~~<br>~~TT~~<br>~~rrti“‘“iLSrh~~|**26.0**<br>~~UT hUmThmhUmTLUT~~<br>~~TThUThUhUmT~~<br>~~rhlm~~|_89.5_<br>~~hUmThmhUmTLUT~~<br>~~hUThUhUmT~~<br>~~lmCl~~|_76.0_<br>~~hUmThmhUmTLUT~~<br>~~hUThUhUmTUTE~~|_49.1_<br>~~hUmThmhUmTLUT~~<br>~~UTE~~|_41.2_<br>~~UTE~~|**25.9**|**21.0**|**9.5**|_110.3_|_110.3_|
|10<br>~~po~~<br>~~rrti“(“‘“i;S~~<br>~~po~~<br>~~rrti“‘“iLS~~<br>~~pF~~<br>~~rrti“‘“Cié‘LS~~|25<br>~~rrti“(“‘“i;S~~<br>~~TT~~<br>~~rrti“‘“iLSrh~~<br>~~rrti“‘“Cié‘LSOUT~~|**13.0**<br>~~TT hUThUhUmT~~<br>~~rhlm~~<br>~~OUTCUT~~|_89.5_<br>~~hUThUhUmT~~<br>~~lmCl~~<br>~~CUTCE~~|_76.0_<br>~~hUThUhUmT UTE~~<br>~~CEEE~~|_49.1_<br>~~UTE~~<br>~~EE~~|_41.2_<br>~~UTE~~<br>~~EE~~|_25.9_|_21.0_|**9.5**|_110.3_|_55.2_|
|11<br>~~po~~<br>~~rrti“‘“iLS~~<br>~~pF~~<br>~~rrti“‘“Cié‘LS~~|12.5<br>~~rrti“‘“iLS rh~~<br>~~rrti“‘“Cié‘LSOUT~~|_13.0_<br>~~rh lm~~<br>~~OUTCUT~~|_89.5_<br>~~lm Cl~~<br>~~CUTCE~~|_76.0_<br>~~CEEE~~|_49.1_<br>~~EE~~|_41.2_<br>~~EE~~|_25.9_|_21.0_|_9.5_|_110.3_|_55.2_|
Page 33 of 120
Document Number: DS-000401 Revision: 1.3
_**IIM-42652**_
||**Group Delay @DC(ms) for GYRO/ACCEL_UI_FILT_ORD=1(2nd order filter)**|**Group Delay @DC(ms) for GYRO/ACCEL_UI_FILT_ORD=1(2nd order filter)**|**Group Delay @DC(ms) for GYRO/ACCEL_UI_FILT_ORD=1(2nd order filter)**|**Group Delay @DC(ms) for GYRO/ACCEL_UI_FILT_ORD=1(2nd order filter)**|**Group Delay @DC(ms) for GYRO/ACCEL_UI_FILT_ORD=1(2nd order filter)**|**Group Delay @DC(ms) for GYRO/ACCEL_UI_FILT_ORD=1(2nd order filter)**|**Group Delay @DC(ms) for GYRO/ACCEL_UI_FILT_ORD=1(2nd order filter)**|**Group Delay @DC(ms) for GYRO/ACCEL_UI_FILT_ORD=1(2nd order filter)**|**Group Delay @DC(ms) for GYRO/ACCEL_UI_FILT_ORD=1(2nd order filter)**|**Group Delay @DC(ms) for GYRO/ACCEL_UI_FILT_ORD=1(2nd order filter)**|**Group Delay @DC(ms) for GYRO/ACCEL_UI_FILT_ORD=1(2nd order filter)**|
|---|---|---|---|---|---|---|---|---|---|---|---|
|||GYRO/ACCEL_UI_FILT_BW<br>~~lm~~||||||||||
|GYRO/ACCEL_ODR<br>~~prrti“‘“‘i;S~~|ODR(Hz)<br>~~prrti“‘“‘i;S~~|0<br>~~prrti“‘“‘i;S~~<br>~~lm~~|1<br>~~prrti“‘“‘i;S~~<br>~~lm~~|2<br>~~prrti“‘“‘i;S~~|3<br>~~prrti“‘“‘i;S~~|4<br>~~prrti“‘“‘i;S~~|5<br>~~prrti“‘“‘i;S~~|6<br>~~prrti“‘“‘i;S~~|7<br>~~prrti“‘“‘i;S~~|14<br>~~prrti“‘“‘i;S~~|15<br>~~prrti“‘“‘i;S~~|
|1<br>~~eG~~|32000<br>~~eG~~|_0.1_<br>~~lm~~<br>~~eG~~||||||||||
|2<br>~~eG~~|16000<br>~~eG~~|_0.1_<br>~~eG~~||||||||||
|3<br>~~ee~~<br>~~es~~|8000<br>~~ee~~|_0.2_<br>~~ee~~||||||||||
|4<br>~~es~~<br>~~re~~|4000|_0.4_||||||||||
|5<br>~~es~~<br>~~re~~<br>~~Pri(dL~~|2000<br>~~(dL~~|_0.8_<br>~~em~~||||||||||
|6<br>~~re~~<br>~~Pri(dL~~<br>~~Porc“tL~~|1000<br>~~(dL~~<br>~~tL~~|**0.7**<br>~~em~~|**2.1**<br>~~em~~|**2.4**|**3.2**|**3.7**|**5.2**|**6.1**|**12.0**|**1.5**|_0.2_|
|15<br>~~Pri(dL~~<br>~~Porc“tL~~<br>~~Pri“i‘~~|500<br>~~(dL~~<br>~~tL~~<br>~~i‘~~|**1.3**<br>~~em~~|**4.1**<br>~~em~~|**4.7**|**6.4**|**7.3**|**10.4**|**12.2**|**24.0**|**3.0**|_0.4_|
|7<br>~~Porc“tL~~<br>~~Pri“i‘~~<br>~~po~~<br>~~rrti“(‘(‘esdtU~~|200<br>~~tL~~<br>~~i‘~~<br>~~rrti“(‘(‘esdtU~~|**3.3**|**5.1**|**5.8**|**8.0**|**9.1**|**12.9**|**15.3**|**30.0**|_3.8_|_1.0_|
|8<br>~~Pri“i‘~~<br>~~po~~<br>~~rrti“(‘(‘esdtU~~<br>~~po~~<br>~~rrti“(“‘“i;S~~|100<br>~~i‘~~<br>~~rrti“(‘(‘esdtU~~<br>~~rrti“(“‘“i;SUT~~|**6.5**<br>~~UThUThUhUmT~~|_5.1_<br>~~hUThUhUmT~~|_5.8_<br>~~hUThUhUmTCUE~~|**8.0**<br>~~CUE~~|**9.1**|**12.9**|**15.3**|**30.0**|_3.8_|_1.9_|
|9<br>~~po~~<br>~~rrti“(‘(‘esdtU~~<br>~~po~~<br>~~rrti“(“‘“i;S~~<br>~~po~~<br>~~rrti“‘“iLS~~|50<br>~~rrti“(‘(‘esdtU~~<br>~~rrti“(“‘“i;SUT~~<br>~~rrti“‘“iLSrh~~|**12.9**<br>~~UThUThUhUmT~~<br>~~rhlm~~|_5.1_<br>~~hUThUhUmT~~<br>~~lmCl~~|_5.8_<br>~~hUThUhUmTCUE~~|_8.0_<br>~~CUE~~|_9.1_|**12.9**|**15.3**|**30.0**|_3.8_|_3.8_|
|10<br>~~po~~<br>~~rrti“(“‘“i;S~~<br>~~po~~<br>~~rrti“‘“iLS~~<br>~~pF~~<br>~~rrti“‘“Cié‘CLYS~~|25<br>~~rrti“(“‘“i;S UT~~<br>~~rrti“‘“iLSrh~~<br>~~rrti“‘“Cié‘CLYSUTD~~|**25.7**<br>~~UT hUThUhUmT~~<br>~~rhlm~~<br>~~UTDUT~~|_5.1_<br>~~hUThUhUmT~~<br>~~lmCl~~<br>~~UTCUE~~|_5.8_<br>~~hUThUhUmT CUE~~<br>~~CUEEE~~|_8.0_<br>~~CUE~~<br>~~EE~~|_9.1_<br>~~EE~~|_12.9_|_15.3_|**30.0**|_3.8_|_7.5_|
|11<br>~~po~~<br>~~rrti“‘“iLS~~<br>~~pF~~<br>~~rrti“‘“Cié‘CLYS~~|12.5<br>~~rrti“‘“iLS rh~~<br>~~rrti“‘“Cié‘CLYSUTD~~|_25.7_<br>~~rh lm~~<br>~~UTDUT~~|_5.1_<br>~~lm Cl~~<br>~~UTCUE~~|_5.8_<br>~~CUEEE~~|_8.0_<br>~~EE~~|_9.1_<br>~~EE~~|_12.9_|_15.3_|_30.0_|_3.8_|_7.5_|
**3[rd] Order Filter 3dB Bandwidth, Noise Bandwidth (NBW), Group Delay**
||**3dB Bandwidth(Hz) for GYRO/ACCEL_UI_FILT_ORD=2(3rd order filter)**|**3dB Bandwidth(Hz) for GYRO/ACCEL_UI_FILT_ORD=2(3rd order filter)**|**3dB Bandwidth(Hz) for GYRO/ACCEL_UI_FILT_ORD=2(3rd order filter)**|**3dB Bandwidth(Hz) for GYRO/ACCEL_UI_FILT_ORD=2(3rd order filter)**|**3dB Bandwidth(Hz) for GYRO/ACCEL_UI_FILT_ORD=2(3rd order filter)**|**3dB Bandwidth(Hz) for GYRO/ACCEL_UI_FILT_ORD=2(3rd order filter)**|**3dB Bandwidth(Hz) for GYRO/ACCEL_UI_FILT_ORD=2(3rd order filter)**|**3dB Bandwidth(Hz) for GYRO/ACCEL_UI_FILT_ORD=2(3rd order filter)**|**3dB Bandwidth(Hz) for GYRO/ACCEL_UI_FILT_ORD=2(3rd order filter)**|**3dB Bandwidth(Hz) for GYRO/ACCEL_UI_FILT_ORD=2(3rd order filter)**|**3dB Bandwidth(Hz) for GYRO/ACCEL_UI_FILT_ORD=2(3rd order filter)**|
|---|---|---|---|---|---|---|---|---|---|---|---|
|~~po~~<br>~~rrti“‘“C“i;S~~|~~rrti“‘“C“i;STT~~|GYRO/ACCEL_UI_FILT_BW<br>~~TThUmThUhlUmdEhUElrCE~~||||||||||
|GYRO/ACCEL_ODR<br>~~po~~<br>~~rrti“‘“C“i;S~~|ODR(Hz)<br>~~rrti“‘“C“i;STT~~<br>~~ee~~|0<br>~~TThUmThUhlUmdEh~~<br>~~ee~~|1<br>~~hUmThUhlUmdEh~~|2<br>~~hUmThUhlUmdEhUE~~|3<br>~~UElr~~|4<br>~~lrCE~~|5<br>~~CE~~|6|7|14|15|
|1<br>~~po~~<br>~~rrti“‘“C“i;S~~<br>~~ee~~|32000<br>~~rrti“‘“C“i;S TT~~<br>~~ee~~<br>~~ee~~|_8400.0_<br>~~TT hUmThUhlUmdEhUE lr CE~~<br>~~ee~~||||||||||
|2<br>~~eee~~|16000<br>~~ee~~<br>~~eee~~|_4194.1_<br>~~ee~~||||||||||
|3<br>~~PC~~|8000<br>~~PC~~<br>~~ee~~|_2096.3_<br>~~ee~~||||||||||
|4<br>~~ee~~<br>~~Prt~~|4000<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>|_1048.1_<br>~~ee~~<br>~~ee~~||||||||||
|5<br>~~ee~~<br>~~ee~~<br>~~Prted~~|2000<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ed~~|_524.0_<br>~~ee~~<br>~~ee~~||||||||||
|6<br>~~ee~~<br>~~Prted~~<br>~~po~~|1000<br>~~ee~~<br>~~ee~~<br>~~ed~~|**492.9**<br>~~ee~~<br>~~mr~~|**234.7**<br>~~mr~~|**195.8**|**118.9**|**97.9**|**60.8**|**46.8**|**25.2**|**262.0**|_2096.3_|
|15<br>~~Prt ed~~<br>~~prrti“(‘edT~~<br>~~po~~<br>~~rrti“(i‘~~<br>~~po~~|500<br>~~ee~~<br>~~ed~~<br>~~prrti“(‘edT~~<br>~~i‘~~|**246.4**<br>~~ee~~<br>~~prrti“(‘edT~~<br>~~mr~~|**117.4**<br>~~prrti“(‘edT~~<br>~~mr~~|**97.9**<br>~~prrti“(‘edT~~|**59.5**<br>~~prrti“(‘edT~~|**48.9**<br>~~prrti“(‘edT~~|**30.4**<br>~~prrti“(‘edT~~|**23.4**<br>~~prrti“(‘edT~~|**12.6**<br>~~prrti“(‘edT~~|**131.0**<br>~~prrti“(‘edT~~|_1048.1_<br>~~prrti“(‘edT~~|
|7<br>~~prrti“(‘edT~~<br>~~po~~<br>~~rrti“(i‘~~<br>~~po~~<br>~~po~~|200<br>~~prrti“(‘edT~~<br>~~i‘~~<br>|**98.6**<br>~~prrti“(‘edT~~<br>~~mr~~<br>|**93.9**<br>~~prrti“(‘edT~~<br>~~mr~~<br>~~rE~~<br>|**78.3**<br>~~prrti“(‘edT~~<br>~~rErE~~<br>|**47.6**<br>~~prrti“(‘edT~~<br>~~rE~~|**39.2**<br>~~prrti“(‘edT~~|**24.3**<br>~~prrti“(‘edT~~|**18.7**<br>~~prrti“(‘edT~~|**10.1**<br>~~prrti“(‘edT~~|_104.8_<br>~~prrti“(‘edT~~|_419.2_<br>~~prrti“(‘edT~~|
|8<br>~~po~~<br>~~rrti“(i‘~~<br>~~po~~<br>~~rrti“(‘iLSUTThCUmE~~<br>~~porrti“‘“‘imLSCCd~~<br>~~Po~~|100<br>~~i‘~~<br>~~rrti“(‘iLSUTThCUmE~~<br>~~rrti“‘“‘imLSCCd~~|**49.3**<br>~~mr~~<br>~~rrti“(‘iLSUTThCUmE~~<br>~~rrti“‘“‘imLSCCdUE~~|_93.9_<br>~~mr~~<br>~~rrti“(‘iLSUTThCUmE~~<br>~~rE~~<br>~~UECE~~|_78.3_<br>~~rrti“(‘iLSUTThCUmE~~<br>~~rErE~~<br>~~CE~~|**47.6**<br>~~rrti“(‘iLSUTThCUmE~~<br>~~rE~~|**39.2**<br>~~rrti“(‘iLSUTThCUmE~~|**24.3**<br>~~rrti“(‘iLSUTThCUmE~~|**18.7**<br>~~rrti“(‘iLSUTThCUmE~~|**10.1**<br>~~rrti“(‘iLSUTThCUmE~~|_104.8_<br>~~rrti“(‘iLSUTThCUmE~~|_209.6_<br>~~rrti“(‘iLSUTThCUmE~~|
|9<br>~~rrti“(i‘~~<br>~~po~~<br>~~rrti“(‘iLSUTThCUmE~~<br>~~porrti“‘“‘imLSCCd~~<br>~~Po~~<br>~~pti“~~|50<br>~~i‘~~<br>~~rrti“(‘iLSUTThCUmE~~<br>~~rrti“‘“‘imLSCCd~~<br>|**24.6**<br>~~rrti“(‘iLSUTThCUmE~~<br>~~rrti“‘“‘imLSCCdUE~~<br>|_93.9_<br>~~rrti“(‘iLSUTThCUmE~~<br>~~rE~~<br>~~UECE~~<br>|_78.3_<br>~~rrti“(‘iLSUTThCUmE~~<br>~~rErE~~<br>~~CE~~<br>~~CUE~~<br>|_47.6_<br>~~rrti“(‘iLSUTThCUmE~~<br>~~rE~~<br>~~CUE|~~<br>|_39.2_<br>~~rrti“(‘iLSUTThCUmE~~<br>~~|~~<br>|**24.3**<br>~~rrti“(‘iLSUTThCUmE~~|**18.7**<br>~~rrti“(‘iLSUTThCUmE~~|**10.1**<br>~~rrti“(‘iLSUTThCUmE~~|_104.8_<br>~~rrti“(‘iLSUTThCUmE~~|_104.8_<br>~~rrti“(‘iLSUTThCUmE~~|
|10<br>~~po rrti“‘“‘imLSCCd~~<br>~~Po~~<br>~~rrti“‘“‘i;SCdCUlmdEhmUlUmdE~~<br>~~pti“t‘;‘é‘smY,SSCi~~|25<br>~~rrti“‘“‘imLSCCd~~<br>~~rrti“‘“‘i;SCdCUlmdEhmUlUmdE~~<br>~~t‘;‘é‘smY,SSCi‘(ETE~~|**12.3**<br>~~rrti“‘“‘imLSCCdUE~~<br>~~rrti“‘“‘i;SCdCUlmdEhmUlUmdE~~<br>~~‘(ETE~~|_93.9_<br>~~rE~~<br>~~UECE~~<br>~~rrti“‘“‘i;SCdCUlmdEhmUlUmdE~~<br>~~‘(ETE~~|_78.3_<br>~~rE rE~~<br>~~CE~~<br>~~rrti“‘“‘i;SCdCUlmdEhmUlUmdE~~<br>~~CUE~~<br>~~‘(ETEEC~~|_47.6_<br>~~rE~~<br>~~rrti“‘“‘i;SCdCUlmdEhmUlUmdE~~<br>~~CUE|~~<br>~~EC~~|_39.2_<br>~~rrti“‘“‘i;SCdCUlmdEhmUlUmdE~~<br>~~|~~<br>~~EC~~|_24.3_<br>~~rrti“‘“‘i;SCdCUlmdEhmUlUmdE~~|_18.7_<br>~~rrti“‘“‘i;SCdCUlmdEhmUlUmdE~~|**10.1**<br>~~rrti“‘“‘i;SCdCUlmdEhmUlUmdE~~|_104.8_<br>~~rrti“‘“‘i;SCdCUlmdEhmUlUmdE~~|_52.4_<br>~~rrti“‘“‘i;SCdCUlmdEhmUlUmdE~~|
|11<br> ~~rrti“‘“‘imLSCCd~~<br>~~Po~~<br>~~pti“t‘;‘é‘smY,SSCi~~|12.5<br>~~rrti“‘“‘imLSCCd~~<br>~~t‘;‘é‘smY,SSCi‘(ETE~~|_12.3_<br>~~rrti“‘“‘imLSCCd UE~~<br>~~‘(ETE~~|_93.9_<br>~~UE CE~~<br>~~‘(ETE~~|_78.3_<br>~~CE~~<br>~~CUE~~<br>~~‘(ETEEC~~|_47.6_<br>~~CUE|~~<br>~~EC~~|_39.2_<br>~~|~~<br>~~EC~~|_24.3_|_18.7_|_10.1_|_104.8_|_52.4_|
Page 34 of 120
Document Number: DS-000401 Revision: 1.3
_**IIM-42652**_
||**NBW Bandwidth(Hz) for GYRO/ACCEL_UI_FILT_ORD=2(3rd order filter)**|**NBW Bandwidth(Hz) for GYRO/ACCEL_UI_FILT_ORD=2(3rd order filter)**|**NBW Bandwidth(Hz) for GYRO/ACCEL_UI_FILT_ORD=2(3rd order filter)**|**NBW Bandwidth(Hz) for GYRO/ACCEL_UI_FILT_ORD=2(3rd order filter)**|**NBW Bandwidth(Hz) for GYRO/ACCEL_UI_FILT_ORD=2(3rd order filter)**|**NBW Bandwidth(Hz) for GYRO/ACCEL_UI_FILT_ORD=2(3rd order filter)**|**NBW Bandwidth(Hz) for GYRO/ACCEL_UI_FILT_ORD=2(3rd order filter)**|**NBW Bandwidth(Hz) for GYRO/ACCEL_UI_FILT_ORD=2(3rd order filter)**|**NBW Bandwidth(Hz) for GYRO/ACCEL_UI_FILT_ORD=2(3rd order filter)**|**NBW Bandwidth(Hz) for GYRO/ACCEL_UI_FILT_ORD=2(3rd order filter)**|**NBW Bandwidth(Hz) for GYRO/ACCEL_UI_FILT_ORD=2(3rd order filter)**|
|---|---|---|---|---|---|---|---|---|---|---|---|
|~~po~~<br>~~rrti“‘c‘*LS~~|~~rrti“‘c‘*LS~~|GYRO/ACCEL_UI_FILT_BW<br>~~lmUErE~~||||||||||
|GYRO/ACCEL_ODR<br>~~po~~<br>~~rrti“‘c‘*LS~~|ODR(Hz)<br>~~rrti“‘c‘*LS~~|0<br>~~lm~~|1<br>~~lmUE~~|2<br>~~UErE~~|3<br>~~rE~~|4|5|6|7|14|15|
|1<br>~~po~~<br>~~rrti“‘c‘*LS~~<br>~~Ge~~|32000<br>~~rrti“‘c‘*LS~~<br>~~Ge~~|_8831.7_<br>~~lm UE rE~~<br>~~Ge~~||||||||||
|2<br>~~Ge~~|16000<br>~~Ge~~|_4410.6_<br>~~Ge~~||||||||||
|3<br>~~a ~~|8000<br> ~~eG~~|_2204.6_<br>~~eG~~||||||||||
|4<br>~~ee~~<br>~~a~~|4000<br>~~ee~~|_1102.2_<br>~~ee~~||||||||||
|5<br>~~a~~<br>~~Prtem~~|2000<br>~~em~~|_551.1_||||||||||
|6<br>~~a~~<br>~~Prtem~~<br>~~prt el~~|1000<br>~~em~~<br>~~el~~|**551.1**|**221.3**|**188.5**|**120.1**|**100.0**|**62.9**|**48.6**|**26.4**|**275.6**|_2204.6_|
|15<br>~~Prt em~~<br>~~prt el~~<br>~~po~~<br>~~rrti“(‘(esdT~~|500<br>~~em~~<br>~~el~~<br>~~rrti“(‘(esdT~~|**252.0**|**110.7**|**94.3**|**60.1**|**50.0**|**31.5**|**24.3**|**13.2**|**137.8**|_1102.2_|
|7<br>~~prt el~~<br>~~po~~<br>~~rrti“(‘(esdT~~<br>~~po~~<br>~~Po~~|200<br>~~el~~<br>~~rrti“(‘(esdT~~<br>|**100.8**|**88.6**|**75.4**<br>~~UE~~|**48.1**<br>~~UEEC~~|**40.0**<br>~~EC~~|**25.2**|**19.5**|**10.6**|_110.3_|_440.9_|
|8<br>~~po~~<br>~~rrti“(‘(esdT~~<br>~~po~~<br>~~rrti“‘“‘iYSCTThlUmTEhmlUmdE~~<br>~~Por~~~~**ti“**‘“‘iY~~<br>~~po~~|100<br>~~rrti“(‘(esdT~~<br>~~rrti“‘“‘iYSCTThlUmTEhmlUmdE~~<br>~~‘“‘iY~~|**50.4**<br>~~rrti“‘“‘iYSCTThlUmTEhmlUmdE~~<br>~~Ummm~~|_88.6_<br>~~rrti“‘“‘iYSCTThlUmTEhmlUmdE~~<br>~~Ummm~~|_75.4_<br>~~rrti“‘“‘iYSCTThlUmTEhmlUmdE~~<br>~~UE~~<br>~~Ummmhm~~|**48.1**<br>~~rrti“‘“‘iYSCTThlUmTEhmlUmdE~~<br>~~UEEC~~<br>~~hmrT~~|**40.0**<br>~~rrti“‘“‘iYSCTThlUmTEhmlUmdE~~<br>~~EC~~<br>~~rT~~|**25.2**<br>~~rrti“‘“‘iYSCTThlUmTEhmlUmdE~~|**19.5**<br>~~rrti“‘“‘iYSCTThlUmTEhmlUmdE~~|**10.6**<br>~~rrti“‘“‘iYSCTThlUmTEhmlUmdE~~|_110.3_<br>~~rrti“‘“‘iYSCTThlUmTEhmlUmdE~~|_220.5_<br>~~rrti“‘“‘iYSCTThlUmTEhmlUmdE~~|
|9<br>~~po~~<br>~~Por~~~~**ti“**‘“‘iY~~<br>~~po~~<br>~~rr~~<br>~~‘“‘imLS~~|50<br>~~‘“‘iY~~<br>~~‘“‘imLSCd~~|**25.2**<br>~~Ummm~~<br>~~CdUE~~|_88.6_<br>~~Ummm~~<br>~~UEEr~~|_75.4_<br>~~UE~~<br>~~Ummmhm~~<br>~~Er~~|_48.1_<br>~~UEEC~~<br>~~hmrT~~|_40.0_<br>~~EC~~<br>~~rT~~|**25.2**|**19.5**|**10.6**|_110.3_|_110.3_|
|10<br>~~Po r~~~~**ti“**‘“‘iY~~<br>~~po~~<br>~~rr~~<br>~~‘“‘imLS~~<br>~~pti“t‘;‘é‘smY,SSCi~~|25<br>~~‘“‘iY~~<br>~~‘“‘imLSCd~~<br>~~t‘;‘é‘smY,SSCi‘(ETE~~|**12.6**<br>~~Ummm~~<br>~~CdUE~~<br>~~‘(ETE~~|_88.6_<br>~~Ummm~~<br>~~UEEr~~<br>~~‘(ETE~~|_75.4_<br>~~UE~~<br>~~Ummmhm~~<br>~~Er~~<br>~~‘(ETEEC~~|_48.1_<br>~~UE EC~~<br>~~hmrT~~<br>~~EC~~|_40.0_<br>~~EC~~<br>~~rT~~<br>~~EC~~|_25.2_|_19.5_|**10.6**|_110.3_|_55.2_|
|11<br> ~~r~~~~**ti“**‘“‘iY~~<br>~~po~~<br>~~rr~~<br>~~‘“‘imLS~~<br>~~pti“t‘;‘é‘smY,SSCi~~|12.5<br>~~‘“‘iY~~<br>~~‘“‘imLS Cd~~<br>~~t‘;‘é‘smY,SSCi‘(ETE~~|_12.6_<br>~~Ummm~~<br>~~Cd UE~~<br>~~‘(ETE~~|_88.6_<br>~~Ummm~~<br>~~UE Er~~<br>~~‘(ETE~~|_75.4_<br>~~Ummm hm~~<br>~~Er~~<br>~~‘(ETEEC~~|_48.1_<br>~~hm rT~~<br>~~EC~~|_40.0_<br>~~rT~~<br>~~EC~~|_25.2_|_19.5_|_10.6_|_110.3_|_55.2_|
||**Group Delay @DC(ms) for GYRO/ACCEL_UI_FILT_ORD=2(3rd order filter)**|**Group Delay @DC(ms) for GYRO/ACCEL_UI_FILT_ORD=2(3rd order filter)**|**Group Delay @DC(ms) for GYRO/ACCEL_UI_FILT_ORD=2(3rd order filter)**|**Group Delay @DC(ms) for GYRO/ACCEL_UI_FILT_ORD=2(3rd order filter)**|**Group Delay @DC(ms) for GYRO/ACCEL_UI_FILT_ORD=2(3rd order filter)**|**Group Delay @DC(ms) for GYRO/ACCEL_UI_FILT_ORD=2(3rd order filter)**|**Group Delay @DC(ms) for GYRO/ACCEL_UI_FILT_ORD=2(3rd order filter)**|**Group Delay @DC(ms) for GYRO/ACCEL_UI_FILT_ORD=2(3rd order filter)**|**Group Delay @DC(ms) for GYRO/ACCEL_UI_FILT_ORD=2(3rd order filter)**|**Group Delay @DC(ms) for GYRO/ACCEL_UI_FILT_ORD=2(3rd order filter)**|**Group Delay @DC(ms) for GYRO/ACCEL_UI_FILT_ORD=2(3rd order filter)**|
|---|---|---|---|---|---|---|---|---|---|---|---|
|~~por tT~~|~~tT~~|GYRO/ACCEL_UI_FILT_BW<br>~~tT~~<br>~~ee~~||||||||||
|GYRO/ACCEL_ODR<br>~~por tT~~|ODR(Hz)<br>~~tT~~|0<br>~~tT~~|1<br>~~ee~~|2<br>~~ee~~|3|4|5|6|7|14|15|
|1<br>~~por tT~~<br>~~Ge~~|32000<br>~~tT~~<br>~~Ge~~|_0.1_<br>~~tT~~<br>~~ee~~<br>~~Ge~~||||||||||
|2<br>~~Ge~~<br>~~Gn~~|16000<br>~~Ge~~<br>~~Gn~~|_0.1_<br>~~Ge~~<br>~~Gn~~||||||||||
|3<br>~~Gn~~<br>~~Gn~~|8000<br>~~Gn~~<br>~~Gn~~|_0.2_<br>~~Gn~~<br>~~Gn~~||||||||||
|4<br>~~Gn~~<br>~~Ge~~|4000<br>~~Gn~~<br>~~Ge~~|_0.4_<br>~~Gn~~<br>~~Ge~~||||||||||
|5<br>~~Ge~~<br>~~po~~<br>~~rrti“(i(‘esdE~~|2000<br>~~Ge~~<br>~~rrti“(i(‘esdE~~|_0.8_<br>~~Ge~~||||||||||
|6<br>~~Ge~~<br>~~po~~<br>~~rrti“(i(‘esdE~~<br>~~po~~<br>~~rrti“‘“‘imLS~~|1000<br>~~Ge~~<br>~~rrti“(i(‘esdE~~<br>~~rrti“‘“‘imLSCd~~|**0.8**<br>~~Ge~~<br>~~CdUE~~|**2.3**<br>~~Ge~~<br>~~UEEr~~|**2.7**<br>~~Ge~~<br>~~Er~~|**4.0**<br>~~Ge~~|**4.6**<br>~~Ge~~|**6.6**<br>~~Ge~~|**8.2**<br>~~Ge~~|**14.1**<br>~~Ge~~|**1.5**<br>~~Ge~~|_0.2_<br>~~Ge~~|
|15<br>~~po~~<br>~~rrti“(i(‘esdE~~<br>~~po~~<br>~~rrti“‘“‘imLS~~<br>~~Po~~<br>~~Po~~|500<br>~~rrti“(i(‘esdE~~<br>~~rrti“‘“‘imLSCd~~|**1.6**<br>~~CdUE~~|**4.6**<br>~~UEEr~~|**5.4**<br>~~Er~~<br>~~CUE~~|**7.9**<br>~~CUE|~~|**9.2**<br>~~|~~|**13.2**|**16.3**|**28.1**|**3.0**|_0.4_|
|7<br>~~po~~<br>~~rrti“‘“‘imLS~~<br>~~Po~~<br>~~rrti“‘“‘i;SCdCUlmdEhmUlUmdE~~<br>~~Po~~<br>~~Pp~~|200<br>~~rrti“‘“‘imLS Cd~~<br>~~rrti“‘“‘i;SCdCUlmdEhmUlUmdE~~|**4.0**<br>~~Cd UE~~<br>~~rrti“‘“‘i;SCdCUlmdEhmUlUmdE~~|**5.8**<br>~~UE Er~~<br>~~rrti“‘“‘i;SCdCUlmdEhmUlUmdE~~|**6.8**<br>~~Er~~<br>~~rrti“‘“‘i;SCdCUlmdEhmUlUmdE~~<br>~~CUE~~<br>~~CUE~~|**9.8**<br>~~rrti“‘“‘i;SCdCUlmdEhmUlUmdE~~<br>~~CUE|~~<br>~~CUE|~~|**11.4**<br>~~rrti“‘“‘i;SCdCUlmdEhmUlUmdE~~<br>~~|~~<br>~~|Cr~~|**16.5**<br>~~rrti“‘“‘i;SCdCUlmdEhmUlUmdE~~<br>~~Cr~~|**20.4**<br>~~rrti“‘“‘i;SCdCUlmdEhmUlUmdE~~|**35.2**<br>~~rrti“‘“‘i;SCdCUlmdEhmUlUmdE~~|_3.8_<br>~~rrti“‘“‘i;SCdCUlmdEhmUlUmdE~~|_1.0_<br>~~rrti“‘“‘i;SCdCUlmdEhmUlUmdE~~|
|8<br>~~Po~~<br>~~Po~~<br>~~rrti“‘“‘i;SlUmdEhmUlmdE~~<br>~~Pp~~<br>~~r~~~~**rt**i“‘aL~~<br>~~po~~|100<br>~~rrti“‘“‘i;SlUmdEhmUlmdE~~<br>~~i“‘aL~~~~**S**~~|**8.0**<br>~~rrti“‘“‘i;SlUmdEhmUlmdE~~<br>~~ld~~|_5.8_<br>~~rrti“‘“‘i;SlUmdEhmUlmdE~~<br>~~ld~~|_6.8_<br>~~CUE~~<br>~~rrti“‘“‘i;SlUmdEhmUlmdE~~<br>~~CUE~~|**9.8**<br>~~CUE|~~<br>~~rrti“‘“‘i;SlUmdEhmUlmdE~~<br>~~CUE|~~|**11.4**<br>~~|~~<br>~~rrti“‘“‘i;SlUmdEhmUlmdE~~<br>~~|Cr~~|**16.5**<br>~~rrti“‘“‘i;SlUmdEhmUlmdE~~<br>~~Cr~~|**20.4**<br>~~rrti“‘“‘i;SlUmdEhmUlmdE~~|**35.2**<br>~~rrti“‘“‘i;SlUmdEhmUlmdE~~|_3.8_<br>~~rrti“‘“‘i;SlUmdEhmUlmdE~~|_1.9_<br>~~rrti“‘“‘i;SlUmdEhmUlmdE~~|
|9<br>~~Po~~<br>~~Pp~~<br>~~r~~~~**rt**i“‘aL~~<br>~~po~~<br>~~r~~<br>~~i“‘“‘i;~~|50<br>~~i“‘aL~~~~**S**~~<br>~~i“‘“‘i;~~<br>~~TLE~~|**15.9**<br>~~ld~~<br>~~TLE~~|_5.8_<br>~~ld~~<br>~~TLE~~|_6.8_<br>~~CUE~~<br>~~CUE~~|_9.8_<br>~~CUE |~~<br>~~CUE|~~|_11.4_<br>~~|~~<br>~~|Cr~~|**16.5**<br>~~Cr~~|**20.4**|**35.2**|_3.8_|_3.8_|
|10<br>~~Pp~~<br>~~r~~~~**rt**i“‘aL~~<br>~~po~~<br>~~r~~<br>~~i“‘“‘i;~~<br>~~prcCU~~|25<br>~~i“‘aL~~~~**S**~~<br>~~i“‘“‘i;~~<br>~~TLE~~<br>~~CU~~|**31.8**<br>~~ld~~<br>~~TLE~~|_5.8_<br>~~ld~~<br>~~TLE~~|_6.8_<br>~~CUE~~|_9.8_<br>~~CUE |~~|_11.4_<br>~~| Cr~~|_16.5_<br>~~Cr~~|_20.4_|**35.2**|_3.8_|_7.5_|
|11<br>~~r~~~~**rt**i“‘aL~~<br>~~po~~<br>~~r~~<br>~~i“‘“‘i;~~<br>~~prcCU~~|12.5<br>~~i“‘aL~~~~**S** ~~<br>~~i“‘“‘i;~~<br>~~TLE~~<br>~~CU~~|_31.8_<br> ~~ld~~<br>~~TLE~~|_5.8_<br>~~ld~~<br>~~TLE~~|_6.8_|_9.8_|_11.4_|_16.5_|_20.4_|_35.2_|_3.8_|_7.5_|
Page 35 of 120
Document Number: DS-000401 Revision: 1.3
_**IIM-42652**_
## **ODR AND FSR SELECTION**
Gyroscope ODR can be selected by programming the parameter GYRO_ODR in register bank 0, register 0x4Fh, bits 3:0 as shown below.
|**GYRO_ODR**|**GYROSCOPE ODR VALUE**|
|---|---|
|0000|Reserved|
|0001|32 kHz|
|0010|16 kHz|
|0011|8 kHz|
|0100|4 kHz|
|0101|2 kHz|
|0110|1 kHz (default)|
|0111|200 Hz|
|1000|100 Hz|
|1001|50 Hz|
|1010|25 Hz|
|1011|12.5 Hz|
|1100|Reserved|
|1101|Reserved|
|1110|Reserved|
|1111|500 Hz|
Gyroscope FSR can be selected by programming the parameter GYRO_FS_SEL in register bank 0, register 0x4Fh, bits 7:5 as shown below.
|**GYRO_FS_SEL**|**GYROSCOPE FSR VALUE**|
|---|---|
|000|2000 dps|
|001|1000 dps|
|010|500 dps|
|011|250 dps|
|100|125 dps|
|101|62.5 dps|
|110|31.25 dps|
|111|15.625 dps|
Accelerometer ODR can be selected by programming the parameter ACCEL_ODR in register bank 0, register 0x50h, bits 3:0 as shown below.
Page 36 of 120
Document Number: DS-000401 Revision: 1.3
_**IIM-42652**_
|**ACCEL_ODR**|**ACCELEROMETER ODR VALUE**|
|---|---|
|0000|Reserved|
|0001|32 kHz (LN mode)|
|0010|16 kHz (LN mode)|
|0011|8 kHz (LN mode)|
|0100|4 kHz (LN mode)|
|0101|2 kHz (LN mode)|
|0110|1 kHz (LN mode) (default)|
|0111|200 Hz (LP or LN mode)|
|1000|100 Hz (LP or LN mode)|
|1001|50 Hz (LP or LN mode)|
|1010|25 Hz (LP or LN mode)|
|1011|12.5 Hz (LP or LN mode)|
|1100|6.25 Hz (LP mode)|
|1101|3.125 Hz (LP mode)|
|1110|1.5625 Hz (LP mode)|
|1111|500 Hz (LP or LN mode)|
Accelerometer FSR can be selected by programming the parameter ACCEL_FS_SEL in register bank 0, register 0x50h, bits 7:5 as shown below.
|**ACCEL_FS_SEL**|**ACCELEROMETER FSR VALUE**|
|---|---|
|000|16g|
|001|8g|
|010|4g|
|011|2g|
|100|Reserved|
|101|Reserved|
|110|Reserved|
|111|Reserved|
Page 37 of 120
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## _**6 FIFO**_
The IIM-42652 contains a 2K-byte FIFO register that is accessible via the serial interface. The FIFO configuration register determines which data is written into the FIFO. Possible choices include gyroscope data, accelerometer data, temperature readings, and FSYNC input. A FIFO counter keeps track of how many bytes of valid data are contained in the FIFO.
## **PACKET STRUCTURE**
The following figure shows the FIFO packet structures supported in IIM-42652. Base data format for gyroscope and accelerometer is 16-bits per element. 20-bits data format support is included in one of the packet structures. When 20-bits data format is used, gyroscope data consists of 19-bits of actual data and the LSB is always set to 0, accelerometer data consists of 18-bits of actual data and the two lowest order bits are always set to 0. When 20-bits data format is used, the only FSR settings that are operational are ±2000 dps for gyroscope and ±16g for accelerometer, even if the FSR selection register settings are configured for other FSR values. The corresponding sensitivity scale factor values are 131 LSB/dps for gyroscope and 8192 LSB/g for accelerometer.
**==> picture [486 x 285] intentionally omitted <==**
**----- Start of picture text -----**<br>
Header Header Header Header<br>(1 byte) (1 byte) (1 byte) (1 byte)<br>Accelerometer Data Gyroscope Data Accelerometer Data Accelerometer Data<br> (6 bytes) (6 bytes) (6 bytes) (6 bytes)<br>Temperature Data Temperature Data<br>(1 byte) (1 byte)<br>Gyroscope Data Gyroscope Data<br>Packet 1 Packet 2<br>(6 bytes) (6 bytes)<br>Temperature Data Temperature Data<br>(1 byte) (2 bytes)<br>TimeStamp TimeStamp<br>(2 bytes) (2 bytes)<br>Packet 3<br>20-bit Extension<br>(3 bytes)<br>**----- End of picture text -----**<br>
## **Packet 4**
## **Figure 10. FIFO Packet Structure**
Due to limitations on the number of bits, 8-bit temperature data stored in FIFO is limited to a -40°C to 85°C range. Either 16-bit temperature data format (FIFO packet 4) or the value from the sensor data registers (TEMP_DATA) must be used to support a temperature measurements range of -40°C to 105°C.
The rest of this sub-section describes how individual data is packaged in the different FIFO packet structures.
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**Packet 1:** Individual data is packaged in Packet 1 as shown below.
|**BYTE**|**CONTENT**|
|---|---|
|0x00|FIFO Header|
|0x01|Accel X[15:8]|
|0x02|Accel X[7:0]|
|0x03|Accel Y[15:8]|
|0x04|Accel Y[7:0]|
|0x05|Accel Z[15:8]|
|0x06|Accel Z[7:0]|
|0x07|Temperature[7:0]|
**Packet 2:** Individual data is packaged in Packet 2 as shown below.
|**BYTE**|**CONTENT**|
|---|---|
|0x00|FIFO Header|
|0x01|Gyro X[15:8]|
|0x02|Gyro X[7:0]|
|0x03|Gyro Y[15:8]|
|0x04|Gyro Y[7:0]|
|0x05|Gyro Z[15:8]|
|0x06|Gyro Z[7:0]|
|0x07|Temperature[7:0]|
**Packet 3:** Individual data is packaged in Packet 3 as shown below.
|**BYTE**|**CONTENT**|
|---|---|
|0x00|FIFO Header|
|0x01|Accel X[15:8]|
|0x02|Accel X[7:0]|
|0x03|Accel Y[15:8]|
|0x04|Accel Y[7:0]|
|0x05|Accel Z[15:8]|
|0x06|Accel Z[7:0]|
|0x07|Gyro X[15:8]|
|0x08|Gyro X[7:0]|
|0x09|Gyro Y[15:8]|
|0x0A|Gyro Y[7:0]|
|0x0B|Gyro Z[15:8]|
|0x0C|Gyro Z[7:0]|
|0x0D|Temperature[7:0]|
|0x0E|TimeStamp[15:8]|
|0x0F|TimeStamp[7:0]|
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**Packet 4:** Individual data is packaged in Packet 4 as shown below.
|**BYTE**|**CONTENT**|**CONTENT**|
|---|---|---|
|0x00|FIFO Header||
|0x01|Accel X[19:12]||
|0x02|Accel X[11:4]||
|0x03|Accel Y[19:12]||
|0x04|Accel Y[11:4]||
|0x05|Accel Z[19:12]||
|0x06|Accel Z[11:4]||
|0x07|Gyro X[19:12]||
|0x08|Gyro X[11:4]||
|0x09|Gyro Y[19:12]||
|0x0A|Gyro Y[11:4]||
|0x0B|Gyro Z[19:12]||
|0x0C|Gyro Z[11:4]||
|0x0D|Temperature[15:8]||
|0x0E|Temperature[7:0]||
|0x0F|TimeStamp[15:8]||
|0x10|TimeStamp[7:0]||
|0x11|Accel X[3:0]|Gyro X[3:0]|
|0x12|Accel Y[3:0]|Gyro Y[3:0]|
|0x13|Accel Z[3:0]|Gyro Z[3:0]|
## **FIFO HEADER**
The following table shows the structure of the 1-byte FIFO header.
|**BIT FIELD**|**ITEM**|**DESCRIPTION**|
|---|---|---|
|7|HEADER_MSG|1: FIFO is empty<br>0: Packet contains sensor data|
|6|HEADER_ACCEL|1: Packet is sized so that accel data have location in the packet, FIFO_ACCEL_EN must be 1<br>0: Packet does not contain accel sample|
|5|HEADER_GYRO|1: Packet is sized so that gyro data have location in the packet, FIFO_GYRO_EN must be 1<br>0: Packet does not containgyro sample|
|4|HEADER_20|1: Packet has a new and valid sample of extended 20-bit data for gyro and/or accel<br>0: Packet does not contain a new and valid extended 20-bit data|
|3:2|HEADER_TIMESTAMP_FSYNC|00: Packet does not contain timestamp or FSYNC time data<br>01: Reserved<br>10: Packet contains ODR Timestamp<br>11: Packet contains FSYNC time, and this packet is flagged as first ODR after FSYNC (only if<br>FIFO_TMST_FSYNC_EN is 1)|
|1|HEADER_ODR_ACCEL|1: The ODR for accel is different for this accel data packet compared to the previous accel<br>packet<br>0: The ODR for accel is the same as thepreviouspacket with accel|
|0|HEADER_ODR_GYRO|1: The ODR for gyro is different for this gyro data packet compared to the previous gyro<br>packet<br>0: The ODR forgyro is the same as thepreviouspacket withgyro|
Note at least HEADER_ACCEL or HEADER_GYRO must be set for a sensor data packet to be set.
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## **MAXIMUM FIFO STORAGE**
The maximum number of packets that can be stored in FIFO is a variable quantity depending on the use case. As shown in Figure 11, the physical FIFO size is 2048 bytes. A number of bytes equal to the packet size selected (see section 6.1) is reserved to prevent reading a packet during write operation. Additionally, a read cache 2 packets wide is available.
When there is no serial interface operation, the read cache is not available for storing packets, being fed by the serial interface clock.
When serial interface operation happens, depending on the operation length and the packet size chosen, either 1 or 2 of the packet entries in read cache may become available for storing packets. In that case the total storage available is up to the maximum number of packets that can be accommodated in 2048 bytes + 1 packet size, depending on the packet size used.
Due to the non-deterministic nature of system operation, driver memory allocation should always be the largest size of 2080 bytes.
**==> picture [467 x 154] intentionally omitted <==**
**----- Start of picture text -----**<br>
< FIFO 2048 Bytes >< 2 Packet Size<br>Ba,<br>Ba,Ba, Read Cache<br>Ba,<br>Ba,<br>RX ov<br>< >< ><br>2048 Bytes – 1 packet size<br>1 Packet Size<br>Reserved to prevent reading a<br>packet during write operation<br>**----- End of picture text -----**<br>
**Figure 11. Maximum FIFO Storage**
## **FIFO CONFIGURATION REGISTERS**
The following control bits in bank 0, register 0x5Fh determine what data is placed into the FIFO. The values of these bits may change while the FIFO is being filled without corruption of the FIFO.
|**BIT**|**NAME**|**FUNCTION**|
|---|---|---|
|4|FIFO_HIRES_EN|0: Default setting; Sensor data have regular resolution<br>1: Sensor data in FIFO will have extended resolution enabling the 20 Bytes packet<br>withpriorityon other settingbelow|
|3|FIFO_TMST_FSYNC_EN|0: FIFO will only contain ODR timestamp information<br>1: FIFO can also contain FSYNC time and FSYNC tag for one ODR after an FSYNC<br>event|
|1|FIFO_GYRO_EN|0: Default setting; Gyroscope data not placed into FIFO<br>1: Enablesgyroscope datapackets of 6-bytes to beplaced in FIFO|
|0|FIFO_ACCEL_EN|0: Default setting; Accelerometer data not placed into FIFO<br>1: Enables accelerometer datapackets of 6-bytes to beplaced in FIFO|
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Configuration register settings above impact FIFO header and FIFO packet size as follows:
|**FIFO_HIRES_EN**|**FIFO_ACCEL_EN**|**FIFO_GYRO_EN**|**FIFO_TMST_**<br>**FSYNC_EN**|**HEADER**|**PACKET SIZE**|
|---|---|---|---|---|---|
|1|X|X|0|8’b_0111_10xx|20 Bytes|
|1|X|X|1|8’b_0111_11xx|20 Bytes|
|0|1|1|0|8’b_0110_10xx|16 Bytes|
|0|1|1|1|8’b_0110_11xx|16 Bytes|
|0|1|0|X|8’b_0100_00xx|8 Bytes|
|0|0|1|X|8’b_0010_00xx|8 Bytes|
|0|0|0|X|No FIFO writes|No FIFO writes|
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## _**7 PROGRAMMABLE INTERRUPTS**_
The IIM-42652 has a programmable interrupt system that can generate an interrupt signal on the INT pins. Status flags indicate the source of an interrupt. Interrupt sources may be enabled and disabled individually. There are two interrupt outputs. Any interrupt may be mapped to either interrupt pin as explained in the register section. The following configuration options are available for the interrupts:
- INT1 and INT2 can be push-pull or open drain
- Level or pulse mode
- Active high or active low
Additionally, IIM-42652 includes In-band Interrupt (IBI) support for the I3C[SM] interface.
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## _**8 APEX MOTION FUNCTIONS**_
The APEX ( **A** dvanced **P** edometer and **E** vent Detection – ne **X** t gen) features of IIM-42652 consist of:
- Pedometer: tracks step count and issues a step detect interrupt.
- Tilt Detection: issues an interrupt when the tilt angle exceeds 35 degrees for more than a programmable time.
- Freefall Detection: triggers an interrupt when device freefall is detected and outputs freefall duration.
- Tap Detection: issues an interrupt when tap is detected, along with a register containing the tap count.
- Wake on Motion (WoM): detects motion when accelerometer samples exceed a programmable threshold. This motion event can be used to enable chip operation from sleep mode.
- Significant Motion Detector (SMD): detects motion if WoM events are detected during a programmable time window (2s or 4s).
## **APEX ODR SUPPORT**
APEX algorithms are designed to work with the accelerometer for a variety of ODR settings. However, there is a minimum ODR required for each algorithm. The following table shows the relationship between the available accelerometer ODRs and the operation of the APEX algorithms. In order to allow more flexible operation where we can control the ODR of the APEX algorithms independent of the accelerometer ODR, we allow for an additional selection determined by the field DMP_ODR (DMP stands for Digital Motion Processor[TM] , an architectural component of APEX). The tables below show how DMP_ODR should be configured in relation to the accelerometer ODR and the expected performance.
|**ACCEL ODR**|**DMP_ODR**|**PEDOMETER**|**TILT DETECTION**|**FREEFALL DETECTION**|
|---|---|---|---|---|
|< 25 Hz|X|Disabled|Disabled|Disabled|
|≥ 25Hz|0 (25 Hz)|Low Power|Low Power|Low Power|
|≥ 50 Hz|2 (50 Hz)|Normal|Normal|Low Power|
|100 Hz|3 (100 Hz)|Normal (50 Hz)|High Performance (50 Hz)|Normal|
|500 Hz|1 (500 Hz)|Disabled|High Performance (50 Hz)|High Performance|
|**ACCEL ODR**|**TAP DETECTION**|
|---|---|
|200 Hz|Low Power|
|500 Hz|Normal|
|1 kHz|High Performance|
|> 1 kHz|Disabled|
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If the accelerometer ODR is set below the minimum DMP ODR (25 Hz), the APEX features cannot be enabled.
When the accelerometer ODR needs to be set differently from the DMP ODR, only the integer multiple of DMP ODR for accelerometer sensor ODR is suitable to use with DMP. For example, when the accelerometer ODR is set as 200 Hz, the APEX features can be enabled with choices of 25 Hz, or 50 Hz, depending on the DMP_ODR register setting.
DMP ODR should not be changed on the fly. The following sequence should be followed for changing the DMP ODR:
1. Disable Pedometer and Tilt Detection if they are enabled
2. Change DMP ODR
3. Set DMP_INIT_EN for one cycle (Register 0x4Bh in Bank 0)
4. Unset DMP_INIT_EN (Register 0x4Bh in Bank 0)
5. Enable APEX features of interest
## **DMP POWER SAVE MODE**
DMP Power Save Mode can be enabled or disabled by DMP_POWER_SAVE (Register 0x56h in Bank 0). When the DMP Power Save Mode is enabled, APEX features are enabled only when WOM is detected. WOM must be explicitly enabled for the DMP to work in this mode. When WOM is not detected the APEX features are on pause. If the user does not want to use DMP Power Save Mode they may set DMP_POWER_SAVE = 0, and use APEX functions without WOM detection.
## **PEDOMETER PROGRAMMING**
- Pedometer configuration parameters
1. LOW_ENERGY_AMP_TH_SEL (Register 0x40h in Bank 4)
2. PED_AMP_TH_SEL (Register 0x41h in Bank 4)
3. PED_STEP_CNT_TH_SEL (Register 0x41h in Bank 4)
4. PED_HI_EN_TH_SEL (Register 0x42h in Bank 4)
5. PED_SB_TIMER_TH_SEL (Register 0x42h in Bank 4)
6. PED_STEP_DET_TH_SEL (Register 0x42h in Bank 4)
7. SENSITIVITY_MODE (Register 0x48h in Bank 4)
8. There are 2 ODR and 2 sensitivity modes
|**ACCEL ODR(DMP_ODR)**|**NORMAL**|**SLOW WALK**|
|---|---|---|
|25 Hz(0)|lowpower|lowpower and slow walk|
|50 Hz(2)|highperformance|slow walk|
- Initialize Sensor in a typical configuration
1. Set accelerometer ODR to 50 Hz (Register 0x50h in Bank 0)
2. Set accelerometer to low power mode (Register 0x4Eh in Bank 0)
- ACCEL_MODE = 2 and (Register 0x4Eh in Bank 0), ACCEL_LP_CLK_SEL = 0, for low power mode
3. Set DMP ODR = 50 Hz and turn on Pedometer feature (Register 0x56h in Bank 0)
4. Wait 1 millisecond
- Initialize APEX hardware
1. Set DMP_MEM_RESET_EN to 1 (Register 0x4Bh in Bank 0)
2. Wait 1 millisecond
3. Set LOW_ENERGY_AMP_TH_SEL to 10 (Register 0x40h in Bank 4)
4. Set PED_AMP_TH_SEL to 8 (Register 0x41h in Bank 4)
5. Set PED_STEP_CNT_TH_SEL to 5 (Register 0x41h in Bank 4)
6. Set PED_HI_EN_TH_SEL to 1 (Register 0x42h in Bank 4)
7. Set PED_SB_TIMER_TH_SEL to 4 (Register 0x42h in Bank 4)
8. Set PED_STEP_DET_TH_SEL to 2 (Register 0x42h in Bank 4)
9. Set SENSITIVITY_MODE to 0 (Register 0x48h in Bank 4)
10. Set DMP_INIT_EN to 1 (Register 0x4Bh in Bank 0)
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11. Wait 50 milliseconds
12. Enable STEP detection, source for INT1 by setting bit 5 in register INT_SOURCE6 (Register 0x4Dh in Bank 4) to 1. Or if INT2 is selected for STEP detection, enable STEP detection source by setting bit 5 in register INT_SOURCE7 (Register 0x4Eh in Bank 4) to 1.
13. As freefall and pedometer share the same output register, they cannot run concurrently. Disable freefall by setting FF_ENABLE to 0 (Register 0x56h in Bank 0)
14. Turn on Pedometer feature by setting PED_ENABLE to 1 (Register 0x56h in Bank 0)
- Output registers
1. Read interrupt register (Register 0x38h in Bank 0) for STEP_DET_INT
2. If the step count is equal to or greater than 65535 (uint16), the STEP_CNT_OVF_INT (Register 0x38h in Bank 0) will be set to 1. Example:
- Take 1 step =>output step count = 65533 (real step count is 65533)
- Take 1 step => output step count = 65534 (real step count is 65534)
- Take 1 step => output step count = 0 and interrupt is fired (real step count is 65535+0= 65535)
- Take 1 step => output step count = 1 (real step count is 65535+1=65536)
3. Read the step count in STEP_CNT (Register 0x31h and 0x32h in Bank 0)
4. Read the step cadence in STEP_CADENCE (Register 0x33h in Bank 0)
5. Read the activity class in ACTIVITY_CLASS (Register 0x34h in Bank 0)
## **TILT DETECTION PROGRAMMING**
- Tilt Detection configuration parameters
1. TILT_WAIT_TIME (Register 0x43h in Bank 4)
This parameter configures how long of a delay after tilt is detected before interrupt is triggered Default is 2 (4s).
Range is 0 = 0s, 1 = 2s, 2 = 4s, 3 = 6s
For example, setting TILT_WAIT_TIME = 2 is equivalent to 4 seconds for all ODRs
- Initialize Sensor in a typical configuration
1. Set accelerometer ODR (Register 0x50h in Bank 0) ACCEL_ODR = 9 for 50 Hz or 10 for 25 Hz
2. Set Accel to Low Power mode (Register 0x4Eh in Bank 0) ACCEL_MODE = 2 and (Register 0x4Dh in Bank 0), ACCEL_LP_CLK_SEL = 0, for low power mode
3. Set DMP ODR (Register 0x56h in Bank 0) DMP_ODR = 0 for 25 Hz, 2 for 50 Hz
4. Wait 1 millisecond
- Initialize APEX hardware
1. Set DMP_MEM_RESET_EN to 1 (Register 0x4Bh in Bank 0)
2. Wait 1 millisecond
3. Set TILT_WAIT_TIME (Register 0x43h in Bank 4) if default value does not meet needs 4. Wait 1 millisecond
5. Set DMP_INIT_EN to 1 (Register 0x4Bh in Bank 0)
6. Enable Tilt Detection, source for INT1 by setting bit 3 in register INT_SOURCE6 (Register 0x4Dh in Bank 4) to 1. Or if INT2 is selected for Tilt Detection, enable Tilt Detection source by setting bit 3 in register INT_SOURCE7 (Register 0x4Eh in Bank 4) to 1.
7. Wait 50 milliseconds
8. Turn on Tilt Detection feature by setting TILT_ENABLE to 1 (Register 0x56h in Bank 0)
- Output registers
1. Read interrupt register (Register 0x38h in Bank 0) for TILT_DET_INT
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## **FREEFALL DETECTION PROGRAMMING**
Freefall Detection detects device freefall. It uses a low-g and a high-g detector to detect freefall start and freefall end. It provides a trigger indicating freefall event and the freefall duration. The duration is given in number of samples and can be converted to freefall distance in meters by applying the following formula:
FF_DISTANCE = 0.5 * 9.81 * (FF_DUR * DMP_ODR_S)^2
Note: DMP_ODR_S is the duration of DMP_ODR expressed in seconds.
- Freefall Detection configuration parameters
1. LOWG_PEAK_TH_SEL (Register 0x44h in Bank 4)
2. LOWG_TIME_TH_SEL (Register 0x44h in Bank 4)
3. LOWG_PEAK_TH_HYST_SEL (Register 0x43h in Bank 4)
4. HIGHG_PEAK_TH_SEL (Register 0x45h in Bank 4)
5. HIGHG_TIME_TH_SEL (Register 0x45h in Bank 4)
6. HIGHG_PEAK_TH_HYST_SEL (Register 0x43h in Bank 4)
7. FF_MIN_DURATION_CM (Register 0x49h in Bank 4)
8. FF_MAX_DURATION_CM (Register 0x49h in Bank 4)
9. FF_DEBOUNCE_DURATION (Register 0x49h in Bank 4)
- Initialize Sensor in a typical configuration
1. Set Accel ODR to 500 Hz (Register 0x50h in Bank 0)
2. Set AVG filtering to 1 sample to minimize power consumption (Register 0x52h in Bank 0) ACCEL_UI_FILT_BW = 1
3. Set Accel to Low Power mode (Register 0x4E in Bank 0) ACCEL_MODE[1:0] = 2
4. Set DMP ODR = 500 Hz (Register 0x56 in Bank 0) DMP_ODR[1:0] = 1
- Initialize APEX hardware
1. Set LOWG_PEAK_TH_SEL (Register 0x44h in Bank 4)
2. Set LOWG_TIME_TH_SEL (Register 0x44h in Bank 4)
3. Set LOWG_PEAK_TH_HYST_SEL (Register 0x43 in Bank4)
4. Set HIGHG_PEAK_TH_SEL (Register 0x45h in Bank 4)
5. Set HIGHG_TIME_TH_SEL (Register 0x45h in Bank 4)
6. Set HIGHG_PEAK_TH_HYST_SEL (Register 0x43h in Bank4)
7. Set FF_DEBOUNCE_DURATION (Register 0x49h in Bank 4)
8. Set FF_MIN_DURATION_CM (Register 0x49h in Bank 4) 9. Set FF_MAX_DURATION_CM (Register 0x49h in Bank 4)
10. Set DMP_MEM_RESET_EN to 1 if DMP is started for the first time after reset (Register 0x4Bh in Bank 0)
11. Wait 1 millisecond
12. Set DMP_INIT_EN to 1 (Register 0x4Bh in Bank 0)
13. Enable FREEFALL detection, source for INT1 by setting bit 1 in register INT_SOURCE6 (Register 0x4Dh in Bank 4) to 1. Or if INT2 is selected for FREEFALL detection, enable FREEFALL detection source by setting bit 1 in register INT_SOURCE7 (Register 0x4Eh in Bank 4) to 1.
14. Wait 50 milliseconds
15. As freefall and pedometer share the same output register, they cannot run concurrently. Disable pedometer by setting PED_ENABLE to 0 (Register 0x56h in Bank 0)
16. Set FF_ENABLE to 1 (Register 0x56h in Bank 0)
- Output registers
1. Read interrupt register (Register 0x38h in Bank 0) for FF_DET_INT
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## 2. Read the freefall duration (Registers 0x31h and 0x32h in Bank 0)
- **Note:** As freefall and pedometer share the same output register, they cannot be run concurrently.
- **TAP DETECTION PROGRAMMING**
- Tap Detection configuration parameters
1. TAP_TMAX (Register 0x47h in Bank 4)
2. TAP_TMIN (Register 0x47h in Bank 4)
3. TAP_TAVG (Register 0x47h in Bank 4)
4. TAP_MIN_JERK_THR (Register 0x46h in Bank 4)
5. TAP_MAX_PEAK_TOL (Register 0x46h in Bank 4)
6. TAP_ENABLE (Register 0x56h in Bank 0)
- Initialize Sensor in a typical configuration
1. Set accelerometer ODR (Register 0x50h in Bank 0)
ACCEL_ODR = 15 for 500 Hz (ODR of 200Hz or 1kHz may also be used)
2. Set power modes and filter configurations as shown below
- For ODR up to 500 Hz, set Accel to Low Power mode (Register 0x4Eh in Bank 0) ACCEL_MODE = 2 and ACCEL_LP_CLK_SEL = 0, (Register 0x4Dh in Bank 0) for low power
- mode
Set filter settings as follows: ACCEL_DEC2_M2_ORD = 2 (Register 0x53h in Bank 0); ACCEL_UI_FILT_BW = 4 (Register 0x52h in Bank 0)
- For ODR of 1 kHz, set Accel to Low Noise mode (Register 0x4Eh in Bank 0) ACCEL_MODE = 1
Set filter settings as follows: ACCEL_UI_FILT_ORD = 2 (Register 0x53h in Bank 0); ACCEL_UI_FILT_BW = 0 (Register 0x52h in Bank 0)
3. Wait 1 millisecond
## • Initialize APEX hardware
1. Set TAP_TMAX to 2 (Register 0x47h in Bank 4)
2. Set TAP_TMIN to 3 (Register 0x47h in Bank 4)
3. Set TAP_TAVG to 3 (Register 0x47h in Bank 4)
4. Set TAP_MIN_JERK_THR to 17 (Register 0x46h in Bank 4)
5. Set TAP_MAX_PEAK_TOL to 2 (Register 0x46h in Bank 4) 6. Wait 1 millisecond
7. Enable TAP source for INT1 by setting bit 0 in register INT_SOURCE6 (Register 0x4Dh in Bank 4) to 1. Or if INT2 is selected for TAP, enable TAP source by setting bit 0 in register INT_SOURCE7 (Register 0x4Eh in Bank 4) to 1.
8. Wait 50 milliseconds
9. Turn on TAP feature by setting TAP_ENABLE to 1 (Register 0x56h in Bank 0)
- Output registers
1. Read interrupt register (Register 0x38h in Bank 0) for TAP_DET_INT
2. Read the tap count in TAP_NUM (Register 0x7Bh in Bank 0)
3. Read the tap axis in TAP_AXIS (Register 0x7Bh in Bank 0)
4. Read the polarity of tap pulse in TAP_DIR (Register 0x7Bh in Bank 0)
## **WAKE ON MOTION PROGRAMMING**
- Wake on Motion configuration parameters
1. WOM_X_TH (Register 0x4Ah in Bank 4)
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2. WOM_Y_TH (Register 0x4Bh in Bank 4)
3. WOM_Z_TH (Register 0x4Ch in Bank 4)
4. WOM_INT_MODE (Register 0x57h in Bank 0)
5. WOM_MODE (Register 0x57h in Bank 0)
6. SMD_MODE (Register 0x57h in Bank 0)
- Initialize Sensor in a typical configuration
1. Set accelerometer ODR (Register 0x50h in Bank 0) ACCEL_ODR = 9 for 50 Hz
2. Set Accel to Low Power mode (Register 0x4Eh in Bank 0) ACCEL_MODE = 2 and (Register 0x4Dh in Bank 0), ACCEL_LP_CLK_SEL = 0, for low power mode
3. Wait 1 millisecond
- Initialize APEX hardware
1. Set WOM_X_TH to 98 (Register 0x4Ah in Bank 4)
2. Set WOM_Y_TH to 98 (Register 0x4Bh in Bank 4)
3. Set WOM_Z_TH to 98 (Register 0x4Ch in Bank 4)
4. Wait 1 millisecond
5. Enable all 3 axes as WOM sources for INT1 by setting bits 2:0 in register INT_SOURCE1 (Register 0x66h in Bank 0) to 1. Or if INT2 is selected for WOM, enable all 3 axes as WOM sources by setting bits 2:0 in register INT_SOURCE4 (Register 0x69h in Bank 0) to 1.
6. Wait 50 milliseconds
7. Turn on WOM feature by setting WOM_INT_MODE to 0, WOM_MODE to 1, SMD_MODE to 1 (Register 0x56h in Bank 0)
- Output registers
1. Read interrupt register (Register 0x37h in Bank 0) for WOM_X_INT
2. Read interrupt register (Register 0x37h in Bank 0) for WOM_Y_INT
3. Read interrupt register (Register 0x37h in Bank 0) for WOM_Z_INT
## **SIGNIFICANT MOTION DETECTION PROGRAMMING**
- Significant Motion Detection configuration parameters
1. WOM_X_TH (Register 0x4Ah in Bank 4)
2. WOM_Y_TH (Register 0x4Bh in Bank 4)
3. WOM_Z_TH (Register 0x4Ch in Bank 4)
4. WOM_INT_MODE (Register 0x57h in Bank 0)
5. WOM_MODE (Register 0x57h in Bank 0)
6. SMD_MODE (Register 0x57h in Bank 0)
- Initialize Sensor in a typical configuration
1. Set accelerometer ODR (Register 0x50h in Bank 0) ACCEL_ODR = 9 for 50 Hz
2. Set Accel to Low Power mode (Register 0x4Eh in Bank 0) ACCEL_MODE = 2 and (Register 0x4Dh in Bank 0), ACCEL_LP_CLK_SEL = 0, for low power mode
3. Wait 1 millisecond
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- Initialize APEX hardware
1. Set WOM_X_TH to 98 (Register 0x4Ah in Bank 4)
2. Set WOM_Y_TH to 98 (Register 0x4Bh in Bank 4)
3. Set WOM_Z_TH to 98 (Register 0x4Ch in Bank 4)
4. Wait 1 millisecond
5. Enable SMD source for INT1 by setting bit 3 in register INT_SOURCE1 (Register 0x66h in Bank 0) to 1. Or if INT2 is selected for SMD, enable SMD source by setting bit 3 in register INT_SOURCE4 (Register 0x69h in Bank 0) to 1.
6. Wait 50 milliseconds
7. Turn on SMD feature by setting WOM_INT_MODE to 0, WOM_MODE to 1, SMD_MODE to 3 (Register 0x56h in Bank 0)
- Output registers
1. Read interrupt register (Register 0x37h in Bank 0) for SMD_INT
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## _**9 DIGITAL INTERFACE**_
## **I3C[SM] , I[2] C, AND SPI SERIAL INTERFACES**
The internal registers and memory of the IIM-42652 can be accessed using I3C[SM] at 12.5 MHz (data rates up to 12.5 Mbps in SDR mode, 25 Mbps in DDR mode), I[2] C at 1 MHz or SPI at 24 MHz. SPI operates in 3-wire or 4-wire mode. Pin assignments for serial interfaces are described in Section 4.1.
## **I3C[SM] INTERFACE**
I3C[SM] is a new 2-wire digital interface comprised of the signals serial data (SDA) and serial clock (SCLK). I3C[SM] is intended to improve upon the I[2] C interface, while preserving backward compatibility.
I3C[SM] carries the advantages of I²C in simplicity, low pin count, easy board design, and multi-drop (vs. point to point), but provides the higher data rates, simpler pads, and lower power of SPI. I3C[SM] adds higher throughput for a given frequency, in-band interrupts (from slave to master), dynamic addressing.
IIM-42652 supports the following features of I3C[SM] :
- SDR data rate up to 12.5 Mbps
- DDR data rate up to 25 Mbps
- Dynamic address allocation
- In-band Interrupt (IBI) support
- Support for asynchronous timing control mode 0
- Error detection (CRC and/or Parity)
- Common Command Code (CCC)
The IIM-42652 always operates as an I3C[SM] slave device when communicating to the system processor, which thus acts as the I3C[SM] master. I3C[SM] master controls an active pullup resistance on SDA, which it can enable and disable. The pullup resistance may be a board level resistor controlled by a pin, or it may be internal to the I3C[SM] master.
## **I[2] C INTERFACE**
I[2] C is a two-wire interface comprised of the signals serial data (SDA) and serial clock (SCL). In general, the lines are open-drain and bi-directional. In a generalized I[2] C interface implementation, attached devices can be a master or a slave. The master device puts the slave address on the bus, and the slave device with the matching address acknowledges the master.
The IIM-42652 always operates as a slave device when communicating to the system processor, which thus acts as the master. SDA and SCL lines typically need pull-up resistors to VDDIO. The maximum bus speed is 1 MHz.
The slave address of the IIM-42652 is b110100X, which is 7 bits long. The LSB bit of the 7-bit address is determined by the logic level on pin AP_AD0. This allows two IIM-42652s to be connected to the same I[2] C bus. When used in this configuration, the address of one of the devices should be b1101000 (pin AP_AD0 is logic low) and the address of the other should be b1101001 (pin AP_AD0 is logic high).
## **I[2] C COMMUNICATIONS PROTOCOL**
## _START (S) and STOP (P) Conditions_
Communication on the I[2] C bus starts when the master puts the START condition (S) on the bus, which is defined as a HIGH-to-LOW transition of the SDA line while SCL line is HIGH (see figure below). The bus is considered to be busy until the master puts a STOP condition (P) on the bus, which is defined as a LOW to HIGH transition on the SDA line while SCL is HIGH (see figure below).
Additionally, the bus remains busy if a repeated START (Sr) is generated instead of a STOP condition.
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**==> picture [324 x 73] intentionally omitted <==**
**----- Start of picture text -----**<br>
SDA<br>SCL<br>S P<br>START condition STOP condition<br>**----- End of picture text -----**<br>
**Figure 12. START and STOP Conditions**
## _Data Format / Acknowledge_
I[2] C data bytes are defined to be 8-bits long. There is no restriction to the number of bytes transmitted per data transfer. Each byte transferred must be followed by an acknowledge (ACK) signal. The clock for the acknowledge signal is generated by the master, while the receiver generates the actual acknowledge signal by pulling down SDA and holding it low during the HIGH portion of the acknowledge clock pulse.
## _Communications_
After beginning communications with the START condition (S), the master sends a 7-bit slave address followed by an 8[th] bit, the read/write bit. The read/write bit indicates whether the master is receiving data from or is writing to the slave device. Then, the master releases the SDA line and waits for the acknowledge signal (ACK) from the slave device. Each byte transferred must be followed by an acknowledge bit. To acknowledge, the slave device pulls the SDA line LOW and keeps it LOW for the high period of the SCL line. Data transmission is always terminated by the master with a STOP condition (P), thus freeing the communications line. However, the master can generate a repeated START condition (Sr), and address another slave without first generating a STOP condition (P). A LOW to HIGH transition on the SDA line while SCL is HIGH defines the stop condition. All SDA changes should take place when SCL is low, with the exception of start and stop conditions.
**==> picture [394 x 109] intentionally omitted <==**
**----- Start of picture text -----**<br>
SDA<br>SCL 1 – 7 8 9 1 – 7 8 9 1 – 7 8 9<br>S P<br>START ADDRESS R/W ACK DATA ACK DATA ACK STOP<br>condition condition<br>**----- End of picture text -----**<br>
**Figure 13. Complete I[2] C Data Transfer**
To write the internal IIM-42652 registers, the master transmits the start condition (S), followed by the I[2] C address and the write bit (0). At the 9[th] clock cycle (when the clock is high), the IIM-42652 acknowledges the transfer. Then the master puts the register address (RA) on the bus. After the IIM-42652 acknowledges the reception of the register address, the master puts the register data onto the bus. This is followed by the ACK signal, and data transfer may be concluded by the stop condition (P). To write multiple bytes after the last ACK signal, the master can continue outputting data rather than transmitting a stop signal. In this case, the IIM-42652 automatically increments the register address and loads the data to the appropriate register. The following figures show single- and two-byte write sequences.
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## _Single-Byte Write Sequence_
|_Burst Write Sequence_<br>Master<br>S<br>AD+W<br>RA<br>DATA<br>P<br>Slave<br>ACK<br>ACK<br>ACK<br>Master<br>S<br>AD+W<br>RA<br>DATA<br>DATA<br>P<br>Slave<br>ACK<br>ACK<br>ACK<br>ACK<br>~~esee~~|
|---|
To read the internal IIM-42652 registers, the master sends a start condition, followed by the I[2] C address and a write bit, and then the register address that is going to be read. Upon receiving the ACK signal from the IIM-42652, the master transmits a start signal followed by the slave address and read bit. As a result, the IIM-42652 sends an ACK signal and the data. The communication ends with a not acknowledge (NACK) signal and a stop bit from master. The NACK condition is defined such that the SDA line remains high at the 9[th] clock cycle. The following figures show single and two-byte read sequences.
_Single-Byte Read Sequence_
|NACK condition is defined such that the SDA line remains high at the 9[th]clock cycle. The following figures show single<br>and two-byte read sequences.<br>_Single-Byte Read Sequence_|NACK condition is defined such that the SDA line remains high at the 9[th]clock cycle. The following figures show single<br>and two-byte read sequences.<br>_Single-Byte Read Sequence_|NACK condition is defined such that the SDA line remains high at the 9[th]clock cycle. The following figures show single<br>and two-byte read sequences.<br>_Single-Byte Read Sequence_|NACK condition is defined such that the SDA line remains high at the 9[th]clock cycle. The following figures show single<br>and two-byte read sequences.<br>_Single-Byte Read Sequence_|NACK condition is defined such that the SDA line remains high at the 9[th]clock cycle. The following figures show single<br>and two-byte read sequences.<br>_Single-Byte Read Sequence_|NACK condition is defined such that the SDA line remains high at the 9[th]clock cycle. The following figures show single<br>and two-byte read sequences.<br>_Single-Byte Read Sequence_|NACK condition is defined such that the SDA line remains high at the 9[th]clock cycle. The following figures show single<br>and two-byte read sequences.<br>_Single-Byte Read Sequence_|NACK condition is defined such that the SDA line remains high at the 9[th]clock cycle. The following figures show single<br>and two-byte read sequences.<br>_Single-Byte Read Sequence_|NACK condition is defined such that the SDA line remains high at the 9[th]clock cycle. The following figures show single<br>and two-byte read sequences.<br>_Single-Byte Read Sequence_|NACK condition is defined such that the SDA line remains high at the 9[th]clock cycle. The following figures show single<br>and two-byte read sequences.<br>_Single-Byte Read Sequence_|NACK condition is defined such that the SDA line remains high at the 9[th]clock cycle. The following figures show single<br>and two-byte read sequences.<br>_Single-Byte Read Sequence_|NACK condition is defined such that the SDA line remains high at the 9[th]clock cycle. The following figures show single<br>and two-byte read sequences.<br>_Single-Byte Read Sequence_|NACK condition is defined such that the SDA line remains high at the 9[th]clock cycle. The following figures show single<br>and two-byte read sequences.<br>_Single-Byte Read Sequence_|NACK condition is defined such that the SDA line remains high at the 9[th]clock cycle. The following figures show single<br>and two-byte read sequences.<br>_Single-Byte Read Sequence_|NACK condition is defined such that the SDA line remains high at the 9[th]clock cycle. The following figures show single<br>and two-byte read sequences.<br>_Single-Byte Read Sequence_|clock cycle. The following figures show single|clock cycle. The following figures show single|clock cycle. The following figures show single|
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|Master<br>S<br>AD+W<br>RA<br>S<br>AD+R<br>NACK<br>P<br>Slave<br>ACK<br>ACK<br>ACK<br>DATA<br>~~ee~~||||||||||||||||||
|_Burst Read Sequence_||||||||||||||||||
|Master<br>S<br>AD+W<br>Slave<br>~~—~~|ACK||RA||ACK||S||AD+R|ACK||DATA||ACK<br>DATA||NACK|P|
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## **I[2] C TERMS**
|**SIGNAL**|**DESCRIPTION**|
|---|---|
|S|Start Condition: SDAgoes from high to low while SCL is high|
|AD|Slave I2C address|
|W|Write bit(0)|
|R|Read bit(1)|
|ACK|Acknowledge: SDA line is low while the SCL line is high at the 9thclock cycle|
|NACK|Not-Acknowledge: SDA line stays high at the 9thclock cycle|
|RA|IIM-42652 internal register address|
|DATA|Transmit or received data|
|P|Stopcondition: SDAgoingfrom low to high while SCL is high|
**Table 14. I[2] C Terms**
## **SPI INTERFACE**
The IIM-42652 supports 3-wire or 4-wire SPI for the host interface. The IIM-42652 always operates as a Slave device during standard Master-Slave SPI operation.
With respect to the Master, the Serial Clock output (SCLK), the Serial Data Output (SDO), the Serial Data Input (SDI), and the Serial Data IO (SDIO) are shared among the Slave devices. Each SPI slave device requires its own Chip Select (CS) line from the master.
CS goes low (active) at the start of transmission and goes back high (inactive) at the end. Only one CS line is active at a time, ensuring that only one slave is selected at any given time. The CS lines of the non-selected slave devices are held high, causing their SDO lines to remain in a high-impedance (high-z) state so that they do not interfere with any active devices.
## _SPI Operational Features_
1. Data is delivered MSB first and LSB last
2. Data is latched on the rising edge of SCLK
3. Data should be transitioned on the falling edge of SCLK
4. The maximum frequency of SCLK is 24 MHz
5. SPI read operations are completed in 16 or more clock cycles (two or more bytes). The first byte contains the SPI Address, and the following byte(s) contain(s) the SPI data. The first bit of the first byte contains the Read/Write bit and indicates the Read (1) operation. The following 7 bits contain the Register Address. In cases of multiple-byte Reads, data is two or more bytes:
**==> picture [80 x 10] intentionally omitted <==**
**----- Start of picture text -----**<br>
SPI Address format<br>**----- End of picture text -----**<br>
**==> picture [196 x 85] intentionally omitted <==**
**----- Start of picture text -----**<br>
MSB LSB<br>a R/W A6 A5 A4 A3 A2 A1 A0<br>SPI Data format<br>MSB LSB<br>D7 D6 D5 D4 D3 D2 D1 D0<br>a<br>**----- End of picture text -----**<br>
_SPI Data format_
6. SPI write operations are completed in 16 clock cycles (two bytes). The first byte contains the SPI Address, and the second byte contains the SPI data. The first bit of the first byte contains the Read/Write bit and indicates the Write (0) operation. The following 7 bits contain the Register Address.
7. Supports Single or Burst Reads and Single Writes.
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**==> picture [189 x 117] intentionally omitted <==**
**----- Start of picture text -----**<br>
SCLK<br>SDIO<br>SPI Master SPI Slave 1<br>CS1 nCS<br>CS2<br>SCLK<br>SDIO<br>SPI Slave 2<br>nCS<br>**----- End of picture text -----**<br>
**Figure 14. Typical SPI Master/Slave Configuration**
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## _**10 ASSEMBLY**_
This section provides general guidelines for assembling InvenSense Micro Electro-Mechanical Systems (MEMS) devices packaged in LGA package.
## **ORIENTATION OF AXES**
Figure 15 shows the orientation of the axes of sensitivity and the polarity of rotation. Note the pin 1 identifier (•) in the figure.
**==> picture [76 x 110] intentionally omitted <==**
**----- Start of picture text -----**<br>
+Z<br>+Z +Y<br>RY +Y<br>+X +X<br>**----- End of picture text -----**<br>
**Figure 15. Orientation of Axes of Sensitivity and Polarity of Rotation**
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## **PACKAGE DIMENSIONS**
14 Lead LGA (2.5x3x0.91) mm NiAu pad finish
**Figure 16. Package Dimensions**
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|||**DIMENSIONS IN MILLIMETERS**|**DIMENSIONS IN MILLIMETERS**|**DIMENSIONS IN MILLIMETERS**|
|---|---|---|---|---|
||**SYMBOLS**|**MIN**|**NOM**|**MAX**|
|**Total Thickness**<br>~~es~~|**A**<br>~~es~~|0.85<br>~~es~~|0.91<br>~~es~~|0.97<br>~~es~~|
|**Substrate Thickness**|**A1**|0.105 REF|||
|**Mold Thickness**<br>~~———~~|**A2**<br>~~———~~|0.8 REF<br>~~———~~|||
|**Body Size**<br>~~———~~|**D**<br>~~———~~|~~———~~|2.5<br>~~———~~|BSC<br>~~———~~|
||**E**<br>~~———~~|~~———~~|3<br>~~———~~|BSC<br>~~———~~|
|**Lead Width**<br>~~op~~|**W**<br>~~op~~|0.2<br>~~op~~|0.25<br>~~op~~|0.3<br>~~op~~|
|**Lead Length**<br>~~op~~|**L**<br>~~op~~|0.425<br>~~op~~|0.475<br>~~op~~|0.525<br>~~op~~|
|**Lead Pitch**<br>~~op~~<br>~~a~~|**e**<br>~~op~~<br>~~a~~|0.5 BSC<br>~~op~~<br>~~a~~|||
|**Lead Count**<br>~~a~~|**n**<br>~~a~~|14<br>~~a~~|||
|**Edge Pin Center to Center**<br>~~ee~~|**D1**<br>~~ee~~|1.5 BSC<br>~~ee~~|||
||**E1**<br>~~ee~~|1 BSC<br>~~ee~~|||
|**Body Center to Contact Pin**<br>~~ee~~<br>~~[$$~~<br>~~J~~|**SD**<br>~~ee~~<br>~~_f—_§—__—~~|0.25 BSC<br>~~ee~~<br>~~_f—_§—__—~~|||
|**Package Edge Tolerance**<br>~~[$$~~<br>~~J~~|**aaa**<br>~~_f—_§—__—~~|0.1<br>~~_f—_§—__—~~|||
|**Mold Flatness**<br>~~[$$~~<br>~~J~~|**bbb**<br>~~_f—_§—__—~~|0.2<br>~~_f—_§—__—~~|||
|**Coplanarity**<br>~~[$$~~<br>~~J~~|**ddd**<br>~~_f—_§—__—~~|0.08<br>~~_f—_§—__—~~|||
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## _**11 PART NUMBER PACKAGE MARKING**_
The part number package marking for IIM-42652 devices is summarized below:
**==> picture [482 x 213] intentionally omitted <==**
**----- Start of picture text -----**<br>
PART NUMBER PART NUMBER PACKAGE MARKING<br>IIM-42652 I4652<br>eS<br>TOP VIEW<br>Part Number I4265I4652<br>Lot Traceability Code X X X X X X<br> YYWW<br>Y Y = Year Code<br>W W = Work Week<br>**----- End of picture text -----**<br>
**Figure 17. Part Number Package Marking**
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## _**12 USE NOTES**_
## **ACCELEROMETER MODE TRANSITIONS**
When transitioning from accelerometer Low Power (LP) mode to accelerometer Low Noise (LN) mode, if ODR is 6.25 Hz or lower, software should change ODR to a value of 12.5 Hz or higher, because accelerometer LN mode does not support ODR values below 12.5 Hz.
When transitioning from accelerometer LN mode to accelerometer LP mode, if ODR is greater than 500 Hz, software should change ODR to a value of 500 Hz or lower, because accelerometer LP mode does not support ODR values above 500 Hz.
## **ACCELEROMETER LOW POWER (LP) MODE AVERAGING FILTER SETTING**
Software drivers provided with the device use Averaging Filter setting of 16x. This setting is recommended for meeting Android noise requirements in LP mode, and to minimize accelerometer offset variation when transitioning from LP to Low Noise (LN) mode. 1x averaging filter can be used by following the setting configuration shown in section 14.38.
## **SETTINGS FOR I[2] C, I3C[SM] , AND SPI OPERATION**
Upon bootup the device comes up in SPI mode. The following settings should be used for I[2] C, I3C[SM] , and SPI operation.
**Scenario 1:** INT1/INT2 pins are used for interrupt assertion in I3C[SM] mode.
|**REGISTER FIELD**|**I2C Driver Setting**|**I3CSM Driver**<br>**Setting**|**SPI Driver Setting**|
|---|---|---|---|
|I3C_EN(bit 4,register INTF_CONFIG6,address 0x7C,bank 1)|1|1|1|
|I3C_SDR_EN(bit 0,register INTF_CONFIG6,address 0x7C,bank 1)|0|1|1|
|I3C_DDR_EN(bit 1,register INTF_CONFIG6,address 0x7C,bank 1)|0|0|1|
|I3C_BUS_MODE (bit 6, register INTF_CONFIG4, address 0x7A,<br>bank 1)|0|0|0|
|I2C_SLEW_RATE (bits 5:3, register DRIVE_CONFIG, address 0x13,<br>bank 0)|1|0|0|
|SPI_SLEW_RATE (bits 2:0, register DRIVE_CONFIG, address 0x13,<br>bank 0)|1|3|5|
**Scenario 2:** IBI is used for interrupt assertion in I3C[SM] mode.
|**REGISTER FIELD**|**I2C Driver Setting**|**I3CSM Driver**<br>**Setting**|**SPI Driver Setting**|
|---|---|---|---|
|I3C_EN(bit 4,register INTF_CONFIG6,address 0x7C,bank 1)|1|1|1|
|I3C_SDR_EN(bit 0,register INTF_CONFIG6,address 0x7C,bank 1)|0|1|1|
|I3C_DDR_EN(bit 1,register INTF_CONFIG6,address 0x7C,bank 1)|0|1|1|
|I3C_BUS_MODE (bit 6, register INTF_CONFIG4, address 0x7A,<br>bank 1)|0|0|0|
|I2C_SLEW_RATE (bits 5:3, register DRIVE_CONFIG, address 0x13,<br>bank 0)|1|0|0|
|SPI_SLEW_RATE (bits 2:0, register DRIVE_CONFIG, address 0x13,<br>bank 0)|1|5|5|
## **NOTCH FILTER AND ANTI-ALIAS FILTER OPERATION**
Use of Notch Filter and Anti-Alias Filter is supported only for Low Noise (LN) mode operation. The host is responsible for keeping the UI path in LN mode while Notch Filter and Anti-Alias Filter are turned on.
## **EXTERNAL CLOCK INPUT EFFECT ON ODR**
ODR values supported by the device scale with external clock frequency, if external clock input is used. The ODR values shown in the datasheet are supported with external clock input frequency of 32 kHz. For any other external clock input frequency, these ODR values will scale by a factor of (External clock value in kHz / 32). For example, if an external clock frequency of 32.768 kHz is used, instead of ODR value of 500 Hz, it will be 500 * (32.768 / 32) = 512 Hz.
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## **INT_ASYNC_RESET CONFIGURATION**
For register INT_CONFIG1 (bank 0 register 0x64) bit 4 INT_ASYNC_RESET, user should change setting to 0 from default setting of 1, for proper INT1 and INT2 pin operation.
## **FIFO TIMESTAMP INTERVAL SCALING**
When RTC_MODE =1 (bank 0 register 0x4D bit2) and register INTF_CONFIG5 (bank 1 register 0x7B) bit 2:1 (PIN9_FUNCTION) is set to 10 for CLKIN input;
THEN
If TMST_RES = 0 (corresponding to timestamp resolution of 1 µs), timestamp interval reported in FIFO requires scaling by a factor of 32.768/RTC Frequency.
For example, when ODR = 1 kHz, RTC Frequency 32 kHz, the true timestamp interval should be 1000 μs. But the value in FIFO toggles between 976 and 977. After scaling 976.5 * 32.768/32 = 1000 μs.
If TMST_RES = 1 (corresponding to timestamp resolution of 1 RTC clock period), timestamp interval reported in FIFO requires scaling by a factor of RTC clock period.
For example, when ODR = 1 kHz, RTC Frequency 32 kHz, the true timestamp interval should be 1000 μs. But the value in FIFO is 32. After scaling 1/32kHz*32 = 1000 μs.
## ELSE
If TMST_RES = 0 (corresponding to timestamp resolution of 1µs), timestamp interval reported in FIFO requires scaling by a factor of 32/30.
For example, when ODR = 1 kHz, the true timestamp interval should be 1000 μs. But the value in FIFO toggles between 937 and 938. After scaling 937.5 * 32/30 = 1000 μs.
If TMST_RES = 1 (corresponding to timestamp resolution of 16 µs), timestamp interval reported in FIFO requires scaling by a factor of 16*32/30.
For example, when ODR = 1 kHz, the true timestamp interval should be 1000 μs. But the value in FIFO toggles between 58 and 59. After scaling 58.5 * 16* 32/30 = 1000 μs.
## ELSE
Timestamp interval reported in FIFO requires scaling by a factor of 32/30. For example, when ODR = 1 kHz, the true timestamp interval should be 1000 µs. But the value in FIFO toggles between 937 and 938 µs. After scaling 937.5 * 32/30 = 1000 µs.
## **SUPPLEMENTARY INFORMATION FOR FIFO_HOLD_LAST_DATA_EN**
This section contains supplementary information for using register field FIFO_HOLD_LAST_DATA_EN (bit 7) of register INTF_CONFIG0 (address 0x4C, bank 0).
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The following table shows the values in FIFO:
|**FIFO_HOLD_LAST_DATA_EN**|**FIFO_HOLD_LAST_DATA_EN**|**16-BIT**<br>**FIFO**<br>**PACKET**|**20-BIT FIFO PACKET**|
|---|---|---|---|
|0 (Insert Invalid code)|Valid sample|All values<br>in:<br>{-32766 to<br>+32767}|Gyro: All Even numbers in {-524256 to +524286}<br>Example: {-524256, -524254, -524252, -524250 …..+524284,<br>+524286}|
||||Accel: Every Other Even number in {-524256 to +524284}<br>Example: {-524256, -524252, -524248, -524244 …..+524280,<br>+524284}|
||Invalid<br>sample|-32768|-524288|
|1 (“copy last valid” mode: No<br>invalid code insertion)|Valid sample|All values<br>in:<br>{-32768 to<br>+32767}|Gyro: All Even numbers in {-524288 to +524286}<br>Example: {-524288, -524286, -524284, -524282 …..+524284,<br>+524286}|
||||Accel: Every Other Even number in {-524288 to +524284}<br>Example: {-524288, -524284, -524280 …..+524280,<br>+524284}|
||Invalid<br>sample|Copy last valid sample||
The following table shows the values in sense registers on reset:
||FIFO_HOLD_LAST_DATA_EN = 0|FIFO_HOLD_LAST_DATA_EN = 1|
|---|---|---|
|Power On Reset till<br>First Sample|Accel/Gyro/Temperature Sensor = -32768|Accel/Gyro/Temperature Sensor = 0|
The following table shows the values in sense registers after first sample is received. As shown in the table, the combination of FIFO_HOLD_LAST_DATA_EN and FSYNC Tag determine the range of values read for valid samples and invalid samples.
|**FIFO_HOLD_LAST_DATA_EN**|**FIFO_HOLD_LAST_DATA_EN**|**FSYNC tag**<br>**disabled**|**FSYNC Enabled on one Sensor**|**FSYNC Enabled on one Sensor**|**FSYNC Enabled on one Sensor**|
|---|---|---|---|---|---|
||||Sensor selected for FSYNC Tag||Other Sensor Not<br>selected for FSYNC<br>tagging|
||||FSYNC tagged|FSYNC not tagged||
|0 (Insert Invalid<br>code)|Valid sample|All values in:<br>{-32766 to +32767}|All ODD values in:<br>{-32765 to +32767}|All EVEN values in:<br>{-32766 to<br>+32766}|All values in:<br>{-32766 to +32767}|
||Invalid<br>sample|Registers do not receive invalid samples. Registers hold last valid sample until new one<br>arrives||||
|1 (“copy last<br>valid” mode: No<br>invalid code<br>insertion)|Valid sample|All values in:<br>{-32768 to +32767}|All ODD values in:<br>{-32767 to +32767}|All EVEN values in:<br>{-32768 to<br>+32766}|All values in:<br>{-32768 to +32767}|
||Invalid<br>sample|Registers do not receive invalid samples. Registers hold last valid sample until new one<br>arrives||||
Page 62 of 120
Document Number: DS-000401 Revision: 1.3
_**IIM-42652**_
## **REGISTER VALUES MODIFICATION**
The only register settings that user can modify during sensor operation are for ODR selection, FSR selection, and sensor mode changes (register parameters GYRO_ODR, ACCEL_ODR, GYRO_FS_SEL, ACCEL_FS_SEL, GYRO_MODE, ACCEL_MODE). User must not modify any other register values during sensor operation. The following procedure must be used for other register values modification.
- Turn Accel and Gyro Off
- Modify register values
- Turn Accel and/or Gyro On
Page 63 of 120
Document Number: DS-000401 Revision: 1.3
_**IIM-42652**_
## _**13 REGISTER MAP**_
This section lists the register map for the IIM-42652, for user banks 0, 1, 2, 4.
## **USER BANK 0 REGISTER MAP**
|**Addr**<br>**(Hex)**|**Addr**<br>**(Dec.)**|**Register Name**|**Serial**<br>**I/F**|**Bit7**|**Bit6**|**Bit5**|**Bit4**|**Bit3**|**Bit2**|**Bit1**|**Bit0**|
|---|---|---|---|---|---|---|---|---|---|---|---|
|11<br>~~a~~ <br>~~a~~|17<br> a<br>~~a~~|DEVICE_CONFIG<br>~~es~~<br>~~ee~~|R/W<br>~~es~~<br>~~eG~~|-<br>~~ss~~<br>~~eGQO~~|||SPI_MODE<br>~~ss~~<br>~~QO~~|-<br>~~QO~~|||SOFT_RESET_<br>CONFIG<br>~~QO~~|
|13<br>~~a~~|19<br>~~a~~|DRIVE_CONFIG<br>~~ee~~|R/W<br>~~eG~~|-<br>~~eG~~||I2C_SLEW_RATE<br>~~QO~~|||SPI_SLEW_RATE<br>~~QO~~|||
|14<br>~~a ~~<br>~~a~~|20<br> ~~a ~~|INT_CONFIG<br> ~~ee ~~|~~eG~~|-<br>~~eG ~~||INT2_MODE<br> ~~QO~~|INT2_DRIVE_<br>CIRCUIT<br>~~QO~~|INT2_POLARI<br>TY<br>~~QO~~|INT1_MODE<br>~~QO~~|INT1_DRIVE_<br>CIRCUIT<br>~~QO~~|INT1_POLARI<br>TY<br>~~QO~~|
|16<br>~~a~~<br>~~a~~|22|FIFO_CONFIG<br>~~ss~~|R/W<br>~~ss~~|FIFO_MODE||-||||||
|1D<br>~~a~~<br>~~a~~|29<br>~~a~~|TEMP_DATA1_UI<br>~~ee~~<br>~~es~~|SYNCR<br>~~ee~~<br>~~ee~~|TEMP_DATA[15:8]||||||||
|1E<br>~~a ~~<br>~~a~~<br>~~a~~|30<br> ~~a~~<br>~~a~~|TEMP_DATA0_UI<br>~~ee~~<br>~~es~~<br>~~es~~|SYNCR<br>~~ee~~<br>~~ee~~|TEMP_DATA[7:0]||||||||
|1F<br>~~a~~<br>~~a~~<br>~~a~~|31<br>~~a~~|ACCEL_DATA_X1_UI<br>~~es ~~<br>~~es~~<br>~~es es~~|SYNCR<br> ~~ee~~<br>~~es~~|ACCEL_DATA_XI[15:8]||||||||
|20<br>~~a ~~<br>~~a~~<br>~~a~~|32<br> ~~a~~|ACCEL_DATA_X0_UI<br>~~es~~<br>~~es es~~<br>~~es es~~|SYNCR<br>~~es~~<br>~~es~~|ACCEL_DATA_X[7:0]||||||||
|21<br>~~a~~<br>~~a~~<br>~~a~~|33|ACCEL_DATA_Y1_UI<br>~~es es~~<br>~~es es~~|SYNCR<br>~~es~~<br>~~es~~<br>~~es~~|ACCEL_DATA_Y[15:8]||||||||
|22<br>~~a~~<br>~~ss~~<br>~~a~~|34<br>~~ss~~|ACCEL_DATA_Y0_UI<br>~~es es~~<br>~~ss~~|SYNCR<br>~~es~~<br>~~ss~~<br>~~es~~|ACCEL_DATA_YI[7:0]<br>~~ss~~||||||||
|23<br>~~a~~<br>~~a~~|35|ACCEL_DATA_Z1_UI<br>~~ss~~<br>~~es es~~|SYNCR<br>~~es~~<br>~~ss~~<br>~~es~~|ACCEL_DATA_Z[15:8]||||||||
|24<br>~~a~~<br>~~a~~|36|ACCEL_DATA_Z0_UI<br>~~ss~~<br>~~es es~~|SYNCR<br>~~es~~<br>~~ss~~<br>~~es~~|ACCEL_DATA_Z[7:0]||||||||
|25<br>~~a~~<br>~~a~~<br>~~a~~|37|GYRO_DATA_X1_UI<br>~~es es~~<br>~~ss~~<br>~~es es~~|SYNCR<br>~~es~~<br>~~ss~~<br>~~es~~|GYRO _DATA_XI[15:8]||||||||
|26<br>~~a~~<br>~~a~~|38|GYRO _DATA_X0_UI<br>~~ss~~<br>~~es es~~|SYNCR<br>~~ss~~<br>~~es~~|GYRO _DATA_X[7:0]||||||||
|27<br>~~a~~<br>~~a~~<br>~~a~~|39|GYRO _DATA_Y1_UI<br>~~es es~~<br>~~ss~~<br>~~es es~~|SYNCR<br>~~es~~<br>~~ss~~<br>~~es~~|GYRO _DATA_Y[15:8]||||||||
|28<br>~~a~~<br>~~a~~|40|GYRO _DATA_Y0_UI<br>~~ss~~<br>~~es es~~|SYNCR<br>~~ss~~<br>~~es~~|GYRO _DATA_YI[7:0]||||||||
|29<br>~~a~~<br>~~a~~<br>~~a~~|41|GYRO _DATA_Z1_UI<br>~~es es~~<br>~~ss~~<br>~~es es~~|SYNCR<br>~~es~~<br>~~ss~~<br>~~es~~|GYRO_DATA_ZI[15:8]||||||||
|2A<br>~~a~~<br>~~a~~|42|GYRO _DATA_Z0_UI<br>~~ss~~<br>~~es es~~|SYNCR<br>~~ss~~<br>~~es~~|GYRO_DATA_ZI[7:0]||||||||
|2B<br>~~a~~<br>~~a~~<br>~~a~~|43|TMST_FSYNCH<br>~~es es~~<br>~~ss~~<br>~~es es~~|SYNCR<br>~~es~~<br>~~ss~~<br>~~es~~|TMST_FSYNC_DATA[15:8]||||||||
|2C<br>~~a~~<br>~~a~~<br>~~a~~|44<br>~~a~~|TMST_FSYNCL<br>~~ss~~<br>~~es es~~<br>~~ee~~|SYNCR<br>~~ss~~<br>~~es~~<br>~~ee~~|TMST_FSYNC_DATA[7:0]<br>~~ee~~<br>~~ee eses~~||||||||
|2D<br>~~a~~<br>~~a~~<br>~~a~~|45<br>~~a~~|INT_STATUS<br>~~es es~~<br>~~ee~~<br>~~es re~~|R/C<br>~~es~~<br>~~ee~~<br>~~re~~|-<br>~~ee~~|FSYNC_INT<br>~~ee~~|PLL_RDY_INT<br>~~ee es~~|RESET_DONE<br>_INT<br>~~es~~|DATA_RDY_I<br>NT<br>~~es~~|FIFO_THS_IN<br>T|FIFO_FULL_I<br>NT|AGC_RDY_IN<br>T|
|2E<br>~~a ~~<br>~~a~~|46<br> ~~a~~|FIFO_COUNTH<br>~~ee~~<br>~~es re~~|R<br>~~ee ~~<br>~~re~~|FIFO_COUNT[15:8]<br> ~~ee~~<br>~~ee es es~~||||||||
|2F<br>~~a~~<br>~~a~~<br>~~a~~|47<br>~~a~~|FIFO_COUNTL<br>~~es re~~<br>~~ee~~<br>~~es~~|R<br>~~re~~<br>~~ee~~<br>~~ee~~|FIFO_COUNT[7:0]||||||||
|30<br>~~a ~~<br>~~a~~|48<br> ~~a~~|FIFO_DATA<br>~~ee~~<br>~~es~~|R<br>~~ee~~<br>~~ee~~|FIFO_DATA||||||||
|31<br>~~a~~<br>~~a~~<br>~~a~~|49<br>~~a~~|APEX_DATA0<br>~~es ~~<br>~~ee~~<br>~~es~~|SYNCR<br> ~~ee~~<br>~~ee~~<br>~~ee~~|STEP_CNT[7:0] / FF_DUR[7:0]||||||||
|32<br>~~a ~~<br>~~a~~<br>~~a~~|50<br> ~~a~~<br>~~a~~|APEX_DATA1<br>~~ee~~<br>~~es~~<br>~~ee~~|SYNCR<br>~~ee~~<br>~~ee~~|STEP_CNT[15:8] / FF_DUR[15:8]||||||||
|33<br>~~a~~<br>~~a~~<br>~~a~~|51<br>~~a~~<br>~~ss~~|APEX_DATA2<br>~~es ~~<br>~~ee~~<br>~~ss~~|R<br> ~~ee~~<br>~~es~~|STEP_CADENCE||||||||
|34<br>~~a ~~<br>~~a~~|52<br> ~~a~~<br>~~ss~~|APEX_DATA3<br>~~ee~~<br>~~ss~~|R<br>~~es~~|-|||||DMP_IDLE|ACTIVITY_CLASS||
|35<br>~~a ~~<br>~~a~~<br>~~a~~|53<br> ~~ss~~<br>~~a~~|APEX_DATA4<br>~~ss ~~<br>~~ee~~<br>~~es ee~~|R<br> ~~es~~<br>~~ee~~<br>~~ee~~|-<br>~~GG~~|||TAP_NUM<br>~~GG~~||TAP_AXIS<br>~~GG~~||TAP_DIR<br>~~GG~~|
|36<br>~~a~~<br>~~a~~<br>~~a~~|54<br>~~a~~<br>~~a~~|APEX_DATA5<br>~~ee~~<br>~~es ee~~<br>~~ee~~|R<br>~~ee~~<br>~~ee~~<br>~~GG~~|-<br>~~GG~~<br>~~GG~~||DOUBLE_TAP_TIMING<br>~~GG~~<br>~~GG~~||||||
|37<br>~~a~~<br>~~a~~|55<br>~~a~~|INT_STATUS2<br>~~es ee~~<br>~~ee~~|R/C<br>~~ee~~<br>~~GG~~|-<br>~~GG~~||||SMD_INT<br>~~GG~~|WOM_Z_INT<br>~~GG~~|WOM_Y_INT<br>~~GG~~|WOM_X_INT<br>~~GG~~|
|38<br>~~a ~~<br>~~aa~~|56<br> ~~a ~~|INT_STATUS3<br> ~~ee~~|R/C<br>~~GG~~|-<br>~~GG~~||STEP_DET_IN<br>T<br>~~GG~~|STEP_CNT_O<br>VF_INT<br>~~GG~~|TILT_DET_IN<br>T<br>~~GG~~|-<br>~~GG~~|FF_DET_INT<br>~~GG~~|TAP_DET_INT<br>~~GG~~|
|4B<br>~~aa~~|75|SIGNAL_PATH_RESET<br>~~ee~~|W/C<br>~~ee~~|-<br>~~ee~~|DMP_INIT_E<br>N|DMP_MEM_<br>RESET_EN|-|ABORT_AND<br>_RESET|TMST_STROB<br>E|FIFO_FLUSH|-|
|4C<br>~~aa~~<br>~~ee~~|76<br>~~ee~~|INTF_CONFIG0<br>~~ee~~<br>~~ee~~|R/W<br>~~ee~~<br>~~ee~~|FIFO_HOLD_L<br>AST_DATA_E<br>N<br>~~ee~~|FIFO_COUNT<br>_REC|FIFO_COUNT<br>_ENDIAN|SENSOR_DAT<br>A_ENDIAN|-||UI_SIFS_CFG||
|4D<br>~~ee~~<br>~~a~~|77<br>~~ee~~|INTF_CONFIG1<br>~~ee~~<br>~~es~~|R/W<br>~~ee~~<br>~~eG~~|-<br>~~eG~~||||ACCEL_LP_CL<br>K_SEL<br>~~eG~~|RTC_MODE<br>~~eG~~|CLKSEL<br>~~eG~~||
|4E<br>~~ee~~<br>~~a~~<br>~~a~~|78<br>~~ee ~~|PWR_MGMT0<br> ~~ee ~~<br>~~es~~<br>~~es es~~|R/W<br> ~~ee~~<br>~~eG~~<br>~~es~~|-<br>~~eG~~<br>~~DQ~~||TEMP_DIS<br>~~eG~~<br>~~DQ~~|IDLE<br>~~eG~~<br>~~DQ~~|GYRO_MODE<br>~~eG~~<br>~~DQ~~||ACCEL_MODE<br>~~eG~~<br>~~DQ~~||
|4F<br>~~a~~<br>~~a~~|79|GYRO_CONFIG0<br>~~es~~<br>~~es es~~|R/W<br>~~eG~~<br>~~es~~|GYRO_UI_FS_SEL<br>~~eG~~<br>~~DQ~~|||-<br>~~eG~~<br>~~DQ~~|GYRO_ODR<br>~~eG~~<br>~~DQ~~||||
|50<br>~~a~~<br>~~a~~|80|ACCEL_CONFIG0<br>~~es es~~<br>~~ss~~|R/W<br>~~es~~<br>~~ss~~|ACCEL_UI_FS_SEL<br>~~DQ~~|||-<br>~~DQ~~|ACCEL_ODR<br>~~DQ~~||||
|51<br>~~a~~<br>~~a~~<br>~~a~~|81|GYRO_CONFIG1<br>~~ss~~<br>~~ss~~<br>~~rs es~~|R/W<br>~~ss~~<br>~~ss~~<br>~~es~~|TEMP_FILT_BW|||-|GYRO_UI_FILT_ORD||GYRO_DEC2_M2_ORD||
|52<br>~~a~~|82|GYRO_ACCEL_CONFIG0<br>~~rs es~~|R/W<br>~~es~~|ACCEL_UI_FILT_BW||||GYRO_UI_FILT_BW||||
|53<br>~~a~~<br>~~a~~|83<br>~~a~~|ACCEL_CONFIG1<br>~~rs es~~<br>~~ee~~|R/W<br>~~es~~<br>~~ee~~|-<br>~~GQ~~|||ACCEL_UI_FILT_ORD<br>~~GQ~~||ACCEL_DEC2_M2_ORD<br>~~GQ~~||-<br>~~GQ~~|
Page 64 of 120
Document Number: DS-000401 Revision: 1.3
_**IIM-42652**_
|**Addr**<br>**(Hex)**|**Addr**<br>**(Dec.)**|**Register Name**|**Serial**<br>**I/F**|**Bit7**|**Bit6**|**Bit5**|**Bit4**|**Bit3**|**Bit2**|**Bit1**|**Bit0**|
|---|---|---|---|---|---|---|---|---|---|---|---|
|54<br>~~ee~~|84<br>~~ee~~|TMST_CONFIG<br>~~ee~~|R/W<br>~~ee~~|-<br>~~ee~~|||TMST_TO_RE<br>GS_EN<br>~~ee~~|TMST_RES<br>~~ee~~|TMST_DELTA<br>_EN<br>~~ee~~|TMST_FSYNC<br>_EN<br>~~ee~~|TMST_EN<br>~~ee~~|
|56<br>~~ee~~|86<br>~~ee~~|APEX_CONFIG0|R/W|DMP_POWE<br>R_SAVE|TAP_ENABLE|PED_ENABLE|TILT_ENABLE|-|FF_ENABLE|DMP_ODR||
|57<br>~~a~~|87<br>|SMD_CONFIG<br>|R/W<br>|-||||WOM_INT_<br>MODE|WOM_MODE|SMD_MODE||
|5F<br>~~ee~~<br>~~a~~|95<br>~~ee~~<br>~~es~~|FIFO_CONFIG1<br>~~ee~~|R/W<br>~~ee~~|-|FIFO_RESUM<br>E_PARTIAL_R<br>D<br>~~ee~~|FIFO_WM_G<br>T_TH<br>~~ee~~|FIFO_HIRES_<br>EN<br>~~ee~~|FIFO_TMST_F<br>SYNC_EN<br>~~ee~~|FIFO_TEMP_<br>EN|FIFO_GYRO_<br>EN|FIFO_ACCEL_<br>EN|
|60<br>~~ee~~<br>~~a~~|96<br>~~ee~~<br>~~es~~|FIFO_CONFIG2<br>~~ee~~|R/W<br>~~ee~~|FIFO_WM[7:0]<br>~~ee~~||||||||
|61<br>~~a~~<br>~~a~~~~**e**~~|97<br>~~es~~<br>~~**e**~~|FIFO_CONFIG3<br>~~**e**e ee~~|R/W<br>~~ee~~|-<br>~~ee~~||||FIFO_WM[11:8]<br>~~ee~~||||
|62<br>~~a~~~~**e**~~|98<br>~~**e**~~|FSYNC_CONFIG<br>~~**e**e ee~~|R/W<br>~~ee~~|-<br>~~ee~~|FSYNC_UI_SEL<br>~~ee~~<br>~~fe~~|||-<br>~~ee~~||FSYNC_UI_FL<br>AG_CLEAR_S<br>EL<br>~~ee~~|FSYNC_POLA<br>RITY|
|63<br>~~**e**~~|99<br>~~**e**~~|INT_CONFIG0<br>~~**e**e ee~~|R/W<br>~~ee~~|-<br>~~ee~~<br>~~fe~~||UI_DRDY_INT_CLEAR<br>~~ee~~<br>~~s~~<br>~~fe~~||FIFO_THS_INT_CLEAR<br>~~ee~~<br>~~s~~||FIFO_FULL_INT_CLEAR<br>~~ee~~<br>~~s~~||
|64<br>~~ee~~|100<br>~~ee~~|INT_CONFIG1<br>~~ee~~|R/W<br>~~ee~~|~~-~~<br>~~ee~~|INT_TPULSE_<br>DURATION<br>~~fe~~<br>~~ee~~|INT_TDEASSE<br>RT_DISABLE<br>~~s~~<br>~~fe~~<br>~~ee~~|INT_ASYNC_<br>RESET<br>~~s~~<br>~~fe~~<br>~~ee~~|-<br>~~s~~<br>~~ee~~||||
|65<br>~~ee~~<br>~~es~~<br>~~ee~~|101<br>~~ee~~<br>~~es~~<br>~~ee~~|INT_SOURCE0<br>~~ee~~<br>~~es~~<br>~~ee~~|R/W<br>~~ee~~<br>~~es~~<br>~~ee~~|-<br>~~ee~~<br>~~es~~<br>~~ee~~|UI_FSYNC_IN<br>T1_EN<br>~~ee~~<br>~~es~~<br>~~ee~~|PLL_RDY_INT<br>1_EN<br>~~ee~~<br>~~es~~|RESET_DONE<br>_INT1_EN<br>~~ee~~<br>~~es~~<br>~~ee~~|UI_DRDY_INT<br>1_EN<br>~~ee~~<br>~~es~~<br>~~ee~~|FIFO_THS_IN<br>T1_EN<br>~~ee~~<br>~~es~~<br>~~ee~~|FIFO_FULL_I<br>NT1_EN<br>~~ee~~<br>~~es~~<br>~~ee~~|UI_AGC_RDY<br>_INT1_EN<br>~~ee~~<br>~~es~~<br>~~ee~~|
|66<br>~~es~~<br>~~ee~~|102<br>~~es~~<br>~~ee~~|INT_SOURCE1<br>~~es~~<br>~~ee~~|R/W<br>~~es~~<br>~~ee~~|-<br>~~es~~<br>~~ee~~|I3C_PROTOC<br>OL_ERROR_I<br>NT1_EN<br>~~es~~<br>~~ee~~|-<br>~~es~~<br>~~ee~~<br>~~ee~~||SMD_INT1_E<br>N<br>~~es~~<br>~~ee~~|WOM_Z_INT<br>1_EN<br>~~es~~<br>~~ee~~|WOM_Y_INT<br>1_EN<br>~~es~~<br>~~ee~~|WOM_X_INT<br>1_EN<br>~~es~~<br>~~ee~~|
|68<br>~~ee~~<br>~~es~~|104<br>~~ee~~<br>~~es~~|INT_SOURCE3<br>~~ee ~~<br>~~es~~|R/W<br> ~~ee~~<br>~~es~~<br>~~ee~~|-<br>~~ee~~<br>~~es~~<br>~~ee~~|UI_FSYNC_IN<br>T2_EN<br>~~ee~~<br>~~es~~<br>~~ee~~|PLL_RDY_INT<br>2_EN<br>~~es~~<br>~~ee~~|RESET_DONE<br>_INT2_EN<br>~~ee~~<br>~~es~~<br>~~ee~~|UI_DRDY_INT<br>2_EN<br>~~ee ~~<br>~~es~~<br>~~ee~~|FIFO_THS_IN<br>T2_EN<br> ~~ee~~<br>~~es~~<br>~~ee~~|FIFO_FULL_I<br>NT2_EN<br>~~ee~~<br>~~es~~<br>~~ee~~|UI_AGC_RDY<br>_INT2_EN<br>~~ee~~<br>~~es~~<br>~~ee~~|
|69<br>~~ee~~|105<br>~~ee~~|INT_SOURCE4<br>~~ee~~|R/W<br>~~ee~~<br>~~ee~~|-<br>~~ee~~<br>~~ee~~|I3C_PROTOC<br>OL_ERROR_I<br>NT2_EN<br>~~ee~~<br>~~ee~~|-<br>~~ee~~<br>~~ee~~||SMD_INT2_E<br>N<br>~~ee~~<br>~~ee~~|WOM_Z_INT<br>2_EN<br>~~ee~~<br>~~ee~~|WOM_Y_INT<br>2_EN<br>~~ee~~<br>~~ee~~|WOM_X_INT<br>2_EN<br>~~ee~~<br>~~ee~~|
|6C<br>~~ee~~|108<br>~~ee~~|FIFO_LOST_PKT0<br>~~ee~~|R<br>~~ee~~<br>~~ee~~|FIFO_LOST_PKT_CNT[15:8]<br>~~ee~~<br>~~ee~~<br>~~ee~~||||||||
|6D|109|FIFO_LOST_PKT1|R|FIFO_LOST_PKT_CNT[7:0]||||||||
|70<br>~~ee~~<br>~~a~~|112<br>~~ee~~<br>~~es~~|SELF_TEST_CONFIG<br>~~ee~~<br>~~ee~~|R/W<br>~~ee~~<br>~~ee~~|~~ee~~|ACCEL_ST_P<br>OWER<br>~~ee~~|EN_AZ_ST<br>~~ee~~|EN_AY_ST<br>~~ee~~|EN_AX_ST<br>~~ee~~|EN_GZ_ST<br>~~ee~~|EN_GY_ST<br>~~ee~~|EN_GX_ST<br>~~ee~~|
|75<br>~~a~~<br>~~a~~|117<br>~~es~~<br>~~es~~|WHO_AM_I<br>~~ee~~|R<br>~~ee~~|WHOAMI||||||||
|76<br>~~a~~<br>~~a~~|118<br>~~es~~<br>~~es~~|REG_BANK_SEL<br>~~ee~~|R/W<br>~~ee~~|-|||||BANK_SEL|||
## **USER BANK 1 REGISTER MAP**
|**Addr**<br>**(Hex)**|**Addr**<br>**(Dec.)**|**Register Name**|**Serial**<br>**I/F**|**Bit7**|**Bit6**|**Bit5**|**Bit4**|**Bit3**|**Bit2**|**Bit1**|**Bit0**|
|---|---|---|---|---|---|---|---|---|---|---|---|
|03<br>~~a~~<br>~~a~~|03<br>~~es~~<br>|SENSOR_CONFIG0<br>~~GG~~|R/W<br>~~GG~~|-<br>~~GG~~||ZG_DISABLE<br>~~GG~~|YG_DISABLE<br>~~GG~~<br>~~DO~~|XG_DISABLE<br>~~GG~~<br>~~DO~~|ZA_DISABLE<br>~~GG~~|YA_DISABLE<br>~~GG~~|XA_DISABLE<br>~~GG~~|
|0B<br>~~a~~<br>~~a~~|11<br>~~es~~<br>|GYRO_CONFIG_STATIC2<br>~~GG~~|R/W<br>~~GG~~|-<br>~~GG~~<br>~~DO~~||||||GYRO_AAF_D<br>IS<br>~~GG~~|GYRO_NF_DI<br>S<br>~~GG~~|
|0C<br>~~a~~<br>~~a~~|12<br>~~a~~<br>~~es~~|GYRO_CONFIG_STATIC3<br>~~ee~~|R/W<br>~~ee~~|-||GYRO_AAF_DELT||||||
|0D<br>~~a ~~<br>~~a~~|13<br> ~~a~~<br>~~es~~|GYRO_CONFIG_STATIC4<br>~~ee~~|R/W<br>~~ee~~|GYRO_AAF_DELTSQR[7:0]||||||||
|0E<br>~~a~~<br>~~a~~|14<br>~~es~~<br>|GYRO_CONFIG_STATIC5<br>|R/W<br>|GYRO_AAF_BITSHIFT<br>||||GYRO_AAF_DELTSQR[11:8]<br>||||
|0F<br>~~es~~<br>~~a~~<br>|15<br>~~es~~<br>~~es~~|GYRO_CONFIG_STATIC6<br>~~es~~<br>|R/W<br>~~es~~<br>|GYRO_X_NF_COSWZ[7:0]<br>~~es~~<br>||||||||
|10<br>~~es~~<br>~~a~~<br>|16<br>~~es~~<br>~~es~~|GYRO_CONFIG_STATIC7<br>~~es~~<br>|R/W<br>~~es~~<br>|GYRO_Y_NF_COSWZ[7:0]<br>~~es~~<br>||||||||
|11<br>~~a~~<br>~~es~~<br>~~a~~|17<br>~~eses~~<br>|GYRO_CONFIG_STATIC8<br>~~es~~<br>|R/W<br>~~es~~<br>~~ee~~<br>|GYRO_Z_NF_COSWZ[7:0]<br>~~es~~<br>~~ee ee~~<br>||||||||
|12<br>~~es~~<br>~~ee~~<br>~~a~~|18<br>~~es~~<br>~~ee~~<br>|GYRO_CONFIG_STATIC9<br>~~es~~<br>~~ee~~<br>|R/W<br>~~es~~<br>~~ee~~<br>~~ee~~<br>|-<br>~~es~~<br>~~ee~~<br>~~ee ee~~<br>||GYRO_Z_NF_<br>COSWZ_SEL[<br>0]<br>~~es~~<br>~~ee~~<br>~~ee~~<br>|GYRO_Y_NF_<br>COSWZ_SEL[<br>0]<br>~~es~~<br>~~ee~~<br>~~ee~~<br>|GYRO_X_NF_<br>COSWZ_SEL[<br>0]<br>~~es~~<br>~~ee~~<br>~~ee~~<br>|GYRO_Z_NF_<br>COSWZ[8]<br>~~es~~<br>~~ee~~<br>~~ee~~<br>|GYRO_Y_NF_<br>COSWZ[8]<br>~~es~~<br>~~ee~~<br>~~ee~~<br>|GYRO_X_NF_<br>COSWZ[8]<br>~~es~~<br>~~ee~~<br>~~ee~~<br>|
|13<br>~~a~~|19<br>|GYRO_CONFIG_STATIC10<br>|R/W<br>~~ee~~<br>|-<br>~~ee~~<br>|GYRO_NF_BW_SEL<br>~~ee ee~~<br>|||GYRO_HPF_BW_IND<br>~~ee~~<br>|||GYRO_HPF_O<br>RD_IND<br>~~ee~~<br>|
|5F<br>~~es~~<br>~~a~~<br>|95<br>~~es~~<br>~~es~~|XG_ST_DATA<br>~~es~~<br>|R/W<br>~~es~~<br>|XG_ST_DATA<br>~~es~~<br>||||||||
|60<br>~~es~~<br>~~a~~<br>|96<br>~~es~~<br>~~es~~|YG_ST_DATA<br>~~es~~<br>|R/W<br>~~es~~<br>|YG_ST_DATA<br>~~es~~<br>||||||||
|61<br>~~a~~<br>~~es~~<br>~~a~~<br>|97<br>~~eses~~<br>~~es~~|ZG_ST_DATA<br>~~es~~<br>|R/W<br>~~es~~<br>|ZG_ST_DATA<br>~~es~~<br>||||||||
|62<br>~~es~~<br>~~a~~<br>|98<br>~~es~~<br>~~es~~|TMSTVAL0<br>~~es~~<br>|R<br>~~es~~<br>|TMST_VALUE[7:0]<br>~~es~~<br>||||||||
|63<br>~~a~~<br>~~es~~|99<br>~~eses~~|TMSTVAL1<br>~~es~~|R<br>~~es~~|TMST_VALUE[15:8]<br>~~es~~||||||||
|64<br>~~es~~<br>~~a ~~|100<br>~~es~~<br> ~~se~~|TMSTVAL2<br>~~es~~<br>~~se~~|R<br>~~es~~<br>~~se~~|-<br>~~es~~||||TMST_VALUE[19:16]<br>~~es~~||||
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|**Addr**<br>**(Hex)**|**Addr**<br>**(Dec.)**|**Register Name**|**Serial**<br>**I/F**|**Bit7**|**Bit6**|**Bit5**|**Bit4**|**Bit3**|**Bit2**|**Bit1**|**Bit0**|
|---|---|---|---|---|---|---|---|---|---|---|---|
|7A|122|INTF_CONFIG4|R/W|-|I3C_BUS_MO<br>DE|-||||SPI_AP_4WIR<br>E|-|
|7B|123|INTF_CONFIG5|R/W|-|||||PIN9_FUNCTION||-|
|7C|124|INTF_CONFIG6|R/W|ASYNCTIME0<br>_DIS|-||I3C_EN|I3C_IBI_BYTE<br>_EN|I3C_IBI_EN|I3C_DDR_EN|I3C_SDR_EN|
## **USER BANK 2 REGISTER MAP**
|**Addr**<br>**(Hex)**|**Addr**<br>**(Dec.)**|**Register Name**|**Serial**<br>**I/F**|**Bit7**|**Bit6**|**Bit5**|**Bit4**|**Bit3**|**Bit2**|**Bit1**|**Bit0**|
|---|---|---|---|---|---|---|---|---|---|---|---|
|03|03|ACCEL_CONFIG_STATIC2|R/W|-|ACCEL_AAF_DELT||||||ACCEL_AAF_<br>DIS|
|04|04|ACCEL_CONFIG_STATIC3|R/W|ACCEL_AAF_DELTSQR[7:0]||||||||
|05|05|ACCEL_CONFIG_STATIC4|R/W|ACCEL_AAF_BITSHIFT||||ACCEL_AAF_DELTSQR[11:8]||||
|3B|59|XA_ST_DATA|R/W|XA_ST_DATA||||||||
|3C|60|YA_ST_DATA|R/W|YA_ST_DATA||||||||
|3D|61|ZA_ST_DATA|R/W|ZA_ST_DATA||||||||
## **USER BANK 3 REGISTER MAP**
|**Addr**<br>**(Hex)**|**Addr**<br>**(Dec.)**|**Register Name**|**Serial**<br>**I/F**|**Bit7**|**Bit6**|**Bit5**|**Bit4**|**Bit3**|**Bit2**|**Bit1**|**Bit0**|
|---|---|---|---|---|---|---|---|---|---|---|---|
|06|06|PU_PD_CONFIG1|R/W|PIN11_PU_E<br>N|PIN7_PU_EN|-|PIN9_PD_EN|PIN10_PU_E<br>N|PIN3_PU_EN|PIN2_PU_EN|PIN4_PD_EN|
|0E|14|PU_PD_CONFIG2|R/W|PIN1_PU_EN|PIN1_PD_EN|PIN12_PU_E<br>N|PIN12_PD_E<br>N|PIN14_PU_E<br>N|PIN14_PD_E<br>N|PIN13_PU_E<br>N|PIN13_PD_E<br>N|
## **USER BANK 4 REGISTER MAP**
|**Addr**<br>**(Hex)**|**Addr**<br>**(Dec.)**|**Register Name**|**Serial**<br>**I/F**|**Bit7**|**Bit6**|**Bit5**|**Bit4**|**Bit3**|**Bit2**|**Bit1**|**Bit0**|
|---|---|---|---|---|---|---|---|---|---|---|---|
|09<br>~~a~~|09<br>~~a a~~|FDR_CONFIG<br>~~a~~|R/W<br>~~ee~~|-|FDR_SEL|||||||
|40<br>~~a ~~<br>~~a~~|64<br> ~~a a~~<br>~~a~~|APEX_CONFIG1<br>~~a~~<br>~~a~~|R/W<br>~~ee~~<br>~~a~~|LOW_ENERGY_AMP_TH_SEL<br>~~a~~||||DMP_POWER_SAVE_TIME_SEL<br>~~a~~||||
|41<br>~~a~~|65<br>~~a~~|APEX_CONFIG2<br>~~a~~|R/W<br>~~a~~|PED_AMP_TH_SEL<br>~~a~~||||PED_STEP_CNT_TH_SEL<br>~~a~~||||
|42<br>~~a~~|66<br>~~a~~|APEX_CONFIG3<br>~~a~~|R/W<br>~~a~~|PED_STEP_DET_TH_SEL<br>~~a~~|||PED_SB_TIMER_TH_SEL<br>~~a~~|||PED_HI_EN_TH_SEL<br>~~a~~||
|43<br>~~a~~|67<br>~~a~~|APEX_CONFIG4<br>~~a~~|R/W<br>~~a~~|TILT_WAIT_TIME_SEL<br>~~a~~||LOWG_PEAK_TH_HYST_SEL<br>~~a~~|||HIGHG_PEAK_TH_HYST_SEL<br>~~a~~|||
|44<br>~~a~~<br>~~a~~|68<br>~~a~~<br>~~a~~|APEX_CONFIG5<br>~~a~~<br>~~a~~|R/W<br>~~a~~<br>~~a~~|LOWG_PEAK_TH_SEL<br>~~a~~<br>~~a~~|||||LOWG_TIME_TH_SEL<br>~~a~~<br>~~a~~|||
|45<br>~~a~~|69<br>~~a~~|APEX_CONFIG6<br>~~a~~|R/W<br>~~a~~|HIGHG_PEAK_TH_SEL<br>~~a~~|||||HIGHG_TIME_TH_SEL<br>~~a~~|||
|46<br>~~a~~<br>~~ye~~|70<br>~~a~~<br>~~ye~~|APEX_CONFIG7<br>~~a~~<br>~~ye~~|R/W<br>~~a~~<br>~~ye~~|TAP_MIN_JERK_THR<br>~~a~~<br>~~ye~~||||||TAP_MAX_PEAK_TOL<br>~~a~~<br>~~ye~~||
|47<br>~~ye~~|71<br>~~ye~~|APEX_CONFIG8<br>~~ye~~|R/W<br>~~ye~~|-<br>~~ye~~|TAP_TMAX<br>~~ye~~||TAP_TAVG<br>~~ye~~||TAP_TMIN<br>~~ye~~|||
|48<br>~~ee~~|72<br>~~ee~~|APEX_CONFIG9<br>~~ee~~|R/W<br>~~ee~~|-<br>~~ee~~|||||||SENSITIVITY_<br>MODE<br>~~ee~~|
|49|73|APEX_CONFIG10|R/W|FF_MIN_DURATION_CM|||FF_MAX_DURATION_CM|||FF_DEBOUNCE_DURATION||
|4A|74|ACCEL_WOM_X_THR|R/W|WOM_X_TH||||||||
|4B<br>~~eT~~|75<br>~~eT~~|ACCEL_WOM_Y_THR<br>~~eT~~|R/W<br>~~eT~~|WOM_Y_TH<br>~~eT~~||||||||
|4C<br>~~eT~~|76<br>~~eT~~|ACCEL_WOM_Z_THR<br>~~eT~~|R/W<br>~~eT~~|WOM_Z_TH<br>~~eT~~||||||||
|4D<br>~~a~~|77<br>~~a~~|INT_SOURCE6|R/W|-||STEP_DET_IN<br>T1_EN|STEP_CNT_O<br>FL_INT1_EN|TILT_DET_IN<br>T1_EN|-|FREEFALL_DE<br>T_INT1_EN|TAP_DET_INT<br>1_EN|
|4E<br>~~a~~|78<br>~~a~~|INT_SOURCE7|R/W|-||STEP_DET_IN<br>T2_EN|STEP_CNT_O<br>FL_INT2_EN|TILT_DET_IN<br>T2_EN|-|FREEFALL_DE<br>T_INT2_EN|TAP_DET_INT<br>2_EN|
|4F<br>~~a~~<br>~~ee~~|79<br>~~a~~<br>~~ee~~|INT_SOURCE8<br>~~ee~~|R/W<br>~~ee~~<br>|-<br>~~ee~~<br>||FSYNC_IBI_E<br>N<br>~~ee~~<br>|PLL_RDY_IBI_<br>EN<br>~~ee~~<br>|UI_DRDY_IBI<br>_EN<br>~~ee~~<br>|FIFO_THS_IBI<br>_EN<br>~~ee~~<br>|FIFO_FULL_IB<br>I_EN<br>~~ee~~<br>|AGC_RDY_IBI<br>_EN<br>~~ee~~<br>|
|50<br>~~ee~~|80<br>~~ee~~|INT_SOURCE9<br>~~ee ee~~|R/W<br>~~ee~~<br>~~ee~~|I3C_PROTOC<br>OL_ERROR_I<br>BI_EN<br>~~ee~~<br>~~ee~~|-<br>~~eeee~~<br>~~ee~~||SMD_IBI_EN<br>~~ee~~<br>~~ee~~|WOM_Z_IBI_<br>EN<br>~~ee~~<br>~~ee~~|WOM_Y_IBI_<br>EN<br>~~ee~~<br>~~ee~~|WOM_X_IBI_<br>EN<br>~~ee~~<br>~~ee~~|-<br>~~ee~~<br>~~ee~~|
|51<br>~~ee~~|81<br>~~ee~~|INT_SOURCE10<br>~~ee ee~~|R/W<br>~~ee~~<br>~~ee~~|-<br>~~ee ~~<br>~~ee~~||STEP_DET_IB<br>I_EN<br> ~~ee~~<br>~~ee~~|STEP_CNT_O<br>FL_IBI_EN<br>~~ee~~<br>~~ee~~|TILT_DET_IBI<br>_EN<br>~~ee~~<br>~~ee~~|-<br>~~ee~~<br>~~ee~~|FREEFALL_DE<br>T_IBI_EN<br>~~ee~~<br>~~ee~~|TAP_DET_IBI<br>_EN<br>~~ee~~<br>~~ee~~|
|77|119|OFFSET_USER0|R/W|GYRO_X_OFFUSER[7:0]||||||||
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|**Addr**<br>**(Hex)**|**Addr**<br>**(Dec.)**|**Register Name**|**Serial**<br>**I/F**|**Bit7**|**Bit6**|**Bit5**|**Bit4**|**Bit3**|**Bit2**|**Bit1**|**Bit0**|
|---|---|---|---|---|---|---|---|---|---|---|---|
|78|120|OFFSET_USER1|R/W|GYRO_Y_OFFUSER[11:8]||||GYRO_X_OFFUSER[11:8]||||
|79|121|OFFSET_USER2|R/W|GYRO_Y_OFFUSER[7:0]||||||||
|7A|122|OFFSET_USER3|R/W|GYRO_Z_OFFUSER[7:0]||||||||
|7B|123|OFFSET_USER4|R/W|ACCEL_X_OFFUSER[11:8]||||GYRO_Z_OFFUSER[11:8]||||
|7C|124|OFFSET_USER5|R/W|ACCEL_X_OFFUSER[7:0]||||||||
|7D|125|OFFSET_USER6|R/W|ACCEL_Y_OFFUSER[7:0]||||||||
|7E|126|OFFSET_USER7|R/W|ACCEL_Z_OFFUSER[11:8]||||ACCEL_Y_OFFUSER[11:8]||||
|7F|127|OFFSET_USER8|R/W|ACCEL_Z_OFFUSER[7:0]||||||||
Detailed register descriptions are provided in the sections that follow. Please note the following regarding Clock Domain for each register:
- Clock Domain: SCLK_UI means that the register is controlled from the UI interface
Register fields marked as Reserved must not be modified by the user. The Reset Value of the register can be used to determine the default value of reserved register fields, and unless otherwise noted this default value must be maintained even if the values of other register fields are modified by the user.
## **REGISTER VALUES MODIFICATION**
The only register settings that user can modify during sensor operation are for ODR selection, FSR selection, and sensor mode changes (register parameters GYRO_ODR, ACCEL_ODR, GYRO_FS_SEL, ACCEL_FS_SEL, GYRO_MODE, ACCEL_MODE). User must not modify any other register values during sensor operation. The following procedure must be used for register values modification:
- Turn Accel and Gyro Off
- Modify register values
- Turn Accel and/or Gyro On
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## _**14 USER BANK 0 REGISTER MAP – DESCRIPTIONS**_
This section describes the function and contents of each register within USR Bank 0.
**Note:** The device powers up in sleep mode.
## **DEVICE_CONFIG**
|**Note:**The device powers up in sleep mode.<br> **DEVICE_CONFIG**|**Note:**The device powers up in sleep mode.<br> **DEVICE_CONFIG**|**Note:**The device powers up in sleep mode.<br> **DEVICE_CONFIG**|
|---|---|---|
|Name: DEVICE_CONFIG<br>Address: 17 (11h)<br>Serial IF: R/W<br>Reset value: 0x00<br>Clock Domain: SCLK_UI|||
|**BIT**|**NAME**|**FUNCTION**|
|7:5|-|Reserved|
|4|SPI_MODE|SPI mode selection<br>0: Mode 0 and Mode 3 (default)<br>1: Mode 1 and Mode 2|
|3:1|-|Reserved|
|0|SOFT_RESET_CONFIG|Software reset configuration<br>0: Normal (default)<br>1: Enable reset<br>After writing 1 to this bitfield, wait 1ms for soft reset to be effective, before<br>attemptinganyother register access|
## **DRIVE_CONFIG**
|Name: DRIVE_CONFIG<br>Address: 19 (13h)<br>Serial IF: R/W<br>Reset value: 0x05<br>Clock Domain: SCLK_UI|Name: DRIVE_CONFIG<br>Address: 19 (13h)<br>Serial IF: R/W<br>Reset value: 0x05<br>Clock Domain: SCLK_UI|Name: DRIVE_CONFIG<br>Address: 19 (13h)<br>Serial IF: R/W<br>Reset value: 0x05<br>Clock Domain: SCLK_UI|
|---|---|---|
|**BIT**|**NAME**|**FUNCTION**|
|7:6|-|Reserved|
|5:3|I2C_SLEW_RATE|Controls slew rate for output pin 14 in I2C mode only<br>000: 20ns-60ns<br>001: 12ns-36ns<br>010: 6ns-18ns<br>011: 4ns-12ns<br>100: 2ns-6ns<br>101: < 2ns<br>110: Reserved<br>111: Reserved|
|2:0|SPI_SLEW_RATE|Controls slew rate for output pin 14 in SPI or I3CSMmode, and for all other<br>output pins<br>000: 20ns-60ns<br>001: 12ns-36ns<br>010: 6ns-18ns<br>011: 4ns-12ns<br>100: 2ns-6ns<br>101: < 2ns<br>110: Reserved<br>111: Reserved|
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## **INT_CONFIG**
|Name: INT_CONFIG|Name: INT_CONFIG||
|---|---|---|
|Address: 20 (14h)|||
|Serial IF: R/W|Serial IF: R/W||
|Reset value: 0x00|Reset value: 0x00||
|Clock Domain: SCLK|Clock Domain: SCLK_UI||
|**BIT**|**NAME**|**FUNCTION**|
|7:6|-|Reserved|
|||INT2 interrupt mode|
|5|INT2_MODE|0: Pulsed mode|
|||1: Latched mode|
|||INT2 drive circuit|
|4|INT2_DRIVE_CIRCUIT|0: Open drain|
|||1: Pushpull|
|||INT2 interrupt polarity|
|3|INT2_POLARITY|0: Active low (default)|
|||1: Active high|
|||INT1 interrupt mode|
|2|INT1_MODE|0: Pulsed mode|
|||1: Latched mode|
|||INT1 drive circuit|
|1|INT1_DRIVE_CIRCUIT|0: Open drain|
|||1: Pushpull|
|||INT1 interrupt polarity|
|0|INT1_POLARITY|0: Active low (default)|
|||1: Active high|
|**FIFO_CONFIG**|||
|Name: FIFO_CONFIG|||
|Address: 22 (16h)|||
|Serial IF: R/W|Serial IF: R/W||
|Reset value: 0x00|Reset value: 0x00||
|Clock Domain: SCLK|Clock Domain: SCLK_UI||
|**BIT**|**NAME**|**FUNCTION**|
|7:6|FIFO_MODE|00: Bypass Mode (default)|
|||01: Stream-to-FIFO Mode|
|||10: STOP-on-FULL Mode|
|||11: STOP-on-FULL Mode|
|5:0|-|Reserved|
## **TEMP_DATA1**
|Name: TEMP_DATA1||
|---|---|
|Address: 29 (1Dh)||
|Serial IF: SYNCR||
|Reset value: 0x80||
|Clock Domain: SCLK_UI||
|**BIT**<br>**NAME**|**FUNCTION**|
|7:0<br>TEMP_DATA[15:8]|Upper byte of temperature data|
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## **TEMP_DATA0**
Name: TEMP_DATA0 Address: 30 (1Eh) Serial IF: SYNCR Reset value: 0x00 Clock Domain: SCLK_UI **BIT NAME FUNCTION** 7:0 TEMP_DATA[7:0] Lower byte of temperature data
Temperature data value from the sensor data registers can be converted to degrees centigrade by using the following formula:
Temperature in Degrees Centigrade = (TEMP_DATA / 132.48) + 25
FIFO_TEMP_DATA, temperature data stored in FIFO, can be 8-bit or 16-it quantity. The 8-bit of temperature data stored in FIFO is limited to -40°C to 85°C range, while the 16-bit representation can support the full operating temperature range. It can be converted to degrees centigrade by using the following formula:
Temperature in Degrees Centigrade = (FIFO_TEMP_DATA / 2.07) + 25
## **ACCEL_DATA_X1**
Name: ACCEL_DATA_X1 Address: 31 (1Fh) Serial IF: SYNCR Reset value: 0x80 Clock Domain: SCLK_UI **BIT NAME FUNCTION** 7:0 ACCEL_DATA_X[15:8] Upper byte of Accel X-axis data
## **ACCEL_DATA_X0**
Name: ACCEL_DATA_X0 Address: 32 (20h) Serial IF: SYNCR Reset value: 0x00 Clock Domain: SCLK_UI **BIT NAME FUNCTION** 7:0 ACCEL_DATA_X[7:0] Lower byte of Accel X-axis data
## **ACCEL_DATA_Y1**
Name: ACCEL_DATA_Y1 Address: 33 (21h) Serial IF: SYNCR Reset value: 0x80 Clock Domain: SCLK_UI **BIT NAME FUNCTION** 7:0 ACCEL_DATA_Y[15:8] Upper byte of Accel Y-axis data
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**ACCEL_DATA_Y0**
Name: ACCEL_DATA_Y0 Address: 34 (22h) Serial IF: SYNCR Reset value: 0x00 Clock Domain: SCLK_UI **BIT NAME FUNCTION** ~~————~~ 7:0 ACCEL_DATA_Y[7:0] Lower byte of Accel Y-axis data **ACCEL_DATA_Z1** Name: ACCEL_DATA_Z1 Address: 35 (23h) Serial IF: SYNCR Reset value: 0x80 Clock Domain: SCLK_UI **BIT NAME FUNCTION** ~~———~~ 7:0 ACCEL_DATA_Z[15:8] Upper byte of Accel Z-axis data
**ACCEL_DATA_Z0** Name: ACCEL_DATA_Z0 Address: 36 (24h) Serial IF: SYNCR Reset value: 0x00 Clock Domain: SCLK_UI **BIT NAME FUNCTION** ~~————~~ 7:0 ACCEL_DATA_Z[7:0] Lower byte of Accel Z-axis data **GYRO_DATA_X1** Name: GYRO_DATA_X1 Address: 37 (25h) Serial IF: SYNCR Reset value: 0x80 Clock Domain: SCLK_UI **BIT NAME FUNCTION** ~~————~~ 7:0 GYRO_DATA_X[15:8] Upper byte of Gyro X-axis data **GYRO_DATA_X0** Name: GYRO_DATA_X0 Address: 38 (26h) Serial IF: SYNCR Reset value: 0x00 Clock Domain: SCLK_UI **BIT NAME FUNCTION** ~~———~~ 7:0 GYRO_DATA_X[7:0] Lower byte of Gyro X-axis data Page 71 of 120 Document Number: DS-000401 Revision: 1.3
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**GYRO_DATA_Y1**
Name: GYRO_DATA_Y1 Address: 39 (27h) Serial IF: SYNCR Reset value: 0x80 Clock Domain: SCLK_UI **BIT NAME FUNCTION** ~~————~~ 7:0 GYRO_DATA_Y[15:8] Upper byte of Gyro Y-axis data **GYRO_DATA_Y0** Name: GYRO_DATA_Y0 Address: 40 (28h) Serial IF: SYNCR Reset value: 0x00 Clock Domain: SCLK_UI **BIT NAME FUNCTION** ~~———~~ 7:0 GYRO_DATA_Y[7:0] Lower byte of Gyro Y-axis data **GYRO_DATA_Z1** Name: GYRO_DATA_Z1 Address: 41 (29h) Serial IF: SYNCR Reset value: 0x80 Clock Domain: SCLK_UI **BIT NAME FUNCTION** ~~———~~ 7:0 GYRO_DATA_Z[15:8] Upper byte of Gyro Z-axis data **GYRO_DATA_Z0** Name: GYRO_DATA_Z0 Address: 42 (2Ah) Serial IF: SYNCR Reset value: 0x00 Clock Domain: SCLK_UI **BIT NAME FUNCTION** ~~————~~ 7:0 GYRO_DATA_Z[7:0] Lower byte of Gyro Z-axis data **TMST_FSYNCH** Name: TMST_FSYNCH Address: 43 (2Bh) Serial IF: SYNCR Reset value: 0x00 Clock Domain: SCLK_UI **BIT NAME FUNCTION** Stores the upper byte of the time delta from the rising edge of FSYNC to 7:0 TMST_FSYNC_DATA[15:8] the latest ODR until the UI Interface reads the FSYNC tag in the status ~~oe~~ register
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## **TMST_FSYNCL**
|**TMST_FSYNCL**<br>14.20|**TMST_FSYNCL**<br>14.20|**TMST_FSYNCL**<br>14.20|
|---|---|---|
|Name: TMST_FSYNCL<br>Address: 44 (2Ch)<br>Serial IF: SYNCR<br>Reset value: 0x00<br>Clock Domain: SCLK_UI|||
|**BIT**|**NAME**|**FUNCTION**|
|7:0|TMST_FSYNC_DATA[7:0]|Stores the lower byte of the time delta from the rising edge of FSYNC to<br>the latest ODR until the UI Interface reads the FSYNC tag in the status<br>register|
## **INT_STATUS**
Name: INT_STATUS Address: 45 (2Dh) Serial IF: R/C Reset value: 0x10 Clock Domain: SCLK_UI
|Name: INT_STATUS<br>Address: 45 (2Dh)<br>Serial IF: R/C<br>Reset value: 0x10<br>Clock Domain: SCLK_UI_UIUI|Name: INT_STATUS<br>Address: 45 (2Dh)<br>Serial IF: R/C<br>Reset value: 0x10<br>Clock Domain: SCLK_UI_UIUI|Name: INT_STATUS<br>Address: 45 (2Dh)<br>Serial IF: R/C<br>Reset value: 0x10<br>Clock Domain: SCLK_UI_UIUI|
|---|---|---|
|**BIT**|**NAME**|**FUNCTION**|
|7|-|Reserved|
|6|UI_FSYNC_INT|This bit automatically sets to 1 when a UI FSYNC interrupt is generated. The<br>bit clears to 0 after the register has been read.|
|5|PLL_RDY_INT|This bit automatically sets to 1 when a PLL Ready interrupt is generated. The<br>bit clears to 0 after the register has been read.|
|4|RESET_DONE_INT|This bit automatically sets to 1 when software reset is complete. The bit<br>clears to 0 after the register has been read.|
|3|DATA_RDY_INT|This bit automatically sets to 1 when a Data Ready interrupt is generated.<br>The bit clears to 0 after the register has been read.|
|2|FIFO_THS_INT|This bit automatically sets to 1 when the FIFO buffer reaches the threshold<br>value. The bit clears to 0 after the register has been read.|
|1|FIFO_FULL_INT|This bit automatically sets to 1 when the FIFO buffer is full. The bit clears to<br>0 after the register has been read.|
|0|AGC_RDY_INT|This bit automatically sets to 1 when an AGC Ready interrupt is generated.<br>The bit clears to 0 after the register has been read.|
## **FIFO_COUNTH**
|Name: FIFO_COUNTH<br>Address: 46 (2Eh)<br>Serial IF: R<br>Reset value: 0x00<br>Clock Domain: SCLK_UI|Name: FIFO_COUNTH<br>Address: 46 (2Eh)<br>Serial IF: R<br>Reset value: 0x00<br>Clock Domain: SCLK_UI|Name: FIFO_COUNTH<br>Address: 46 (2Eh)<br>Serial IF: R<br>Reset value: 0x00<br>Clock Domain: SCLK_UI|
|---|---|---|
|**BIT**|**NAME**|**FUNCTION**|
|7:0|FIFO_COUNT[15:8]|High Bits, count indicates the number of records or bytes available in FIFO<br>according to FIFO_COUNT_REC setting.<br>Note: Must read FIFO_COUNTL to latch new data for both FIFO_COUNTH<br>and FIFO_COUNTL.|
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## **FIFO_COUNTL**
|**FIFO_COUNTL**<br>14.23|**FIFO_COUNTL**<br>14.23|**FIFO_COUNTL**<br>14.23|
|---|---|---|
|Name: FIFO_COUNTL<br>Address: 47 (2Fh)<br>Serial IF: R<br>Reset value: 0x00<br>Clock Domain: SCLK_UI|||
|**BIT**|**NAME**|**FUNCTION**|
|7:0|FIFO_COUNT[7:0]|Low Bits, count indicates the number of records or bytes available in FIFO<br>according to FIFO_COUNT_REC setting.<br>Reading this byte latches the data for both FIFO_COUNTH, and<br>FIFO_COUNTL.|
## **FIFO_DATA**
|**FIFO_DATA**<br>14.24||
|---|---|
|Name: FIFO_DATA||
|Address: 48 (30h)||
|Serial IF: R||
|Reset value: 0xFF||
|Clock Domain: SCLK_UI||
|**BIT**<br>**NAME**|**FUNCTION**|
|7:0<br>FIFO_DATA|FIFO dataport|
## **APEX_DATA0**
|Name: APEX_DATA0<br>Address: 49 (31h)<br>Serial IF: SYNCR<br>Reset value: 0x00<br>Clock Domain: SCLK_UI|Name: APEX_DATA0<br>Address: 49 (31h)<br>Serial IF: SYNCR<br>Reset value: 0x00<br>Clock Domain: SCLK_UI|Name: APEX_DATA0<br>Address: 49 (31h)<br>Serial IF: SYNCR<br>Reset value: 0x00<br>Clock Domain: SCLK_UI|
|---|---|---|
|**BIT**|**NAME**|**FUNCTION**|
|7:0|STEP_CNT[7:0] (when<br>Pedometer is enabled)|Pedometer Output: Lower byte of Step Count measured by pedometer|
||FF_DUR[7:0] (when Freefall<br>Detection is enabled)|Lower byte of Freefall Duration|
## **APEX_DATA1**
|Name: APEX_DATA1<br>Address: 50 (32h)<br>Serial IF: SYNCR<br>Reset value: 0x00<br>Clock Domain: SCLK_UI|Name: APEX_DATA1<br>Address: 50 (32h)<br>Serial IF: SYNCR<br>Reset value: 0x00<br>Clock Domain: SCLK_UI|Name: APEX_DATA1<br>Address: 50 (32h)<br>Serial IF: SYNCR<br>Reset value: 0x00<br>Clock Domain: SCLK_UI|
|---|---|---|
|**BIT**|**NAME**|**FUNCTION**|
|7:0|STEP_CNT[15:8] (when<br>Pedometer is enabled)|Pedometer Output: Upper byte of Step Count measured by pedometer|
||FF_DUR[15:8] (when<br>Freefall Detection is<br>enabled)|Upper byte of Freefall Duration|
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## **APEX_DATA2**
|**APEX_DATA2**|**APEX_DATA2**|**APEX_DATA2**|
|---|---|---|
|Name: APEX_DATA2<br>Address: 51 (33h)<br>Serial IF: R<br>Reset value: 0x00<br>Clock Domain: SCLK_UI|||
|**BIT**|**NAME**|**FUNCTION**|
|7:0|STEP_CADENCE|Pedometer Output: Walk/run cadency in number of samples. Format is<br>u6.2. e.g. At 50Hz ODR and 2Hz walk frequency, the cadency is 25 samples.<br>The register will output 100.|
## **APEX_DATA3**
|**APEX_DATA3**|**APEX_DATA3**|**APEX_DATA3**|
|---|---|---|
|Name: APEX_DATA3<br>Address: 52 (34h)<br>Serial IF: R<br>Reset value: 0x04<br>Clock Domain: SCLK_UI|||
|**BIT**|**NAME**|**FUNCTION**|
|7:3|-|Reserved|
|2|DMP_IDLE|0: Indicates DMP is running<br>1: Indicates DMP is idle|
|1:0|ACTIVITY_CLASS|Pedometer Output: Detected activity<br>00: Unknown<br>01: Walk<br>10: Run<br>11: Reserved|
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## **APEX_DATA4**
Name: APEX_DATA4 Address: 53 (35h) Serial IF: R Reset value: 0x00 Clock Domain: SCLK_UI
|**APEX_DATA4**|**APEX_DATA4**|**APEX_DATA4**|
|---|---|---|
|Name: APEX_DATA4<br>Address: 53 (35h)<br>Serial IF: R<br>Reset value: 0x00<br>Clock Domain: SCLK_UI_UIUI|||
|**BIT**|**NAME**|**FUNCTION**|
|7:5|-|Reserved|
|4:3|TAP_NUM|Tap Detection Output: Number of taps in the current Tap event<br>00: No tap<br>01: Single tap<br>10: Double tap<br>11: Reserved|
|2:1|TAP_AXIS|Tap Detection Output: Represents the accelerometer axis on which tap<br>energy is concentrated<br>00: X-axis<br>01: Y-axis<br>10: Z-axis<br>11: Reserved|
|0|TAP_DIR|Tap Detection Output: Polarity of tap pulse<br>0: Current accelerometer value – Previous accelerometer value is a positive<br>value<br>1: Current accelerometer value – Previous accelerometer value is a negative<br>value or zero|
## **APEX_DATA5**
Name: APEX_DATA5 Address: 54 (36h) Serial IF: R Reset value: 0x00 Clock Domain: SCLK_UI
|**APEX_DATA5**|**APEX_DATA5**|**APEX_DATA5**|
|---|---|---|
|Name: APEX_DATA5<br>Address: 54 (36h)<br>Serial IF: R<br>Reset value: 0x00<br>Clock Domain: SCLK_UI_UIUI|||
|**BIT**|**NAME**|**FUNCTION**|
|7:6|-|Reserved|
|5:0|DOUBLE_TAP_TIMING|DOUBLE_TAP_TIMING measures the time interval between the two taps<br>when double tap is detected. It counts every 16 accelerometer samples as<br>one unit between the 2 tap pulses. Therefore, the value is related to the<br>accelerometer ODR.<br>Time in seconds = DOUBLE_TAP_TIMING * 16 / ODR<br>For example, if the accelerometer ODR is 500 Hz, and the<br>DOUBLE_TAP_TIMING register reading is 6, the time interval value is<br>6*16/500 = 0.192 seconds.|
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## **INT_STATUS2**
Name: INT_STATUS2 Address: 55 (37h) Serial IF: R/C Reset value: 0x00 Clock Domain: SCLK_UI
|**BIT**|**NAME**|**FUNCTION**|
|---|---|---|
|7:4|-|Reserved|
|3|SMD_INT|Significant Motion Detection Interrupt,clears on read|
|2|WOM_Z_INT|Wake on Motion Interrupt on Z-axis,clears on read|
|1|WOM_Y_INT|Wake on Motion Interrupt on Y-axis,clears on read|
|0|WOM_X_INT|Wake on Motion Interrupt on X-axis,clears on read|
## **INT_STATUS3**
Name: INT_STATUS3 Address: 56 (38h) Serial IF: R/C Reset value: 0x00 Clock Domain: SCLK_UI
|**BIT**|**NAME**|**FUNCTION**|
|---|---|---|
|7:6|-|Reserved|
|5|STEP_DET_INT|StepDetection Interrupt,clears on read|
|4|STEP_CNT_OVF_INT|StepCount Overflow Interrupt,clears on read|
|3|TILT_DET_INT|Tilt Detection Interrupt,clears on read|
|2|-|Reserved|
|1|FF_DET_INT|Freefall Interrupt,clears on read|
|0|TAP_DET_INT|TapDetection Interrupt,clears on read|
## **SIGNAL_PATH_RESET**
Name: SIGNAL_PATH_RESET Address: 75 (4Bh) Serial IF: W/C Reset value: 0x00 Clock Domain: SCLK_UI
|Name: SIGNAL_PATH_RESET<br>Address: 75 (4Bh)<br>Serial IF: W/C<br>Reset value: 0x00<br>Clock Domain: SCLK_UI_UIUI|Name: SIGNAL_PATH_RESET<br>Address: 75 (4Bh)<br>Serial IF: W/C<br>Reset value: 0x00<br>Clock Domain: SCLK_UI_UIUI|Name: SIGNAL_PATH_RESET<br>Address: 75 (4Bh)<br>Serial IF: W/C<br>Reset value: 0x00<br>Clock Domain: SCLK_UI_UIUI|
|---|---|---|
|**BIT**|**NAME**|**FUNCTION**|
|7|-|Reserved|
|6|DMP_INIT_EN|When this bit is set to 1,the DMP is enabled|
|5|DMP_MEM_RESET_EN|When this bit is set to 1,the DMP memoryis reset|
|4|-|Reserved|
|3|ABORT_AND_RESET|When this bit is set to 1, the signal path is reset by restarting the ODR<br>counter and signalpath controls|
|2|TMST_STROBE|When this bit is set to 1, the time stamp counter is latched into the time<br>stampregister. This is a write on clear bit.|
|1|FIFO_FLUSH|When set to 1,FIFO willget flushed.|
|0|-|Reserved|
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## **INTF_CONFIG0**
|**INTF_CONFIG0**|**INTF_CONFIG0**|**INTF_CONFIG0**|
|---|---|---|
|Name: INTF_CONFIG0<br>Address: 76 (4Ch)<br>Serial IF: R/W<br>Reset value: 0x30<br>Clock Domain: SCLK_UI|||
|**BIT**|**NAME**|**FUNCTION**|
|7|FIFO_HOLD_LAST_DATA_EN|**Setting this bit to 0:**<br>In order to signal an invalid sample, and to differentiate it from a valid<br>sample based on values only:<br>Sense Registers:<br>•<br>Do not receive invalid samples. They hold the last valid<br>sample. Repeated reading before new sample received will yield<br>copies of the last valid sample.<br>•<br>Valid samples of values -32768, -32767 are replaced with -32766<br>•<br>FSYNC Tagging can modify the least significant bit and further limit<br>values (see section 12.8).<br>FIFO:<br>•<br>16-bit FIFO packet: Same as Sense Registers, except:<br>o<br>FSYNC tagging is not applied to data in FIFO.<br>•<br>20-bit FIFO packet:<br>o<br>Invalid samples are indicated with the value -524288<br>o<br>Valid samples in {-524288 to -524258} are replaced by -<br>524256<br>o<br>Valid Gyro samples: All Even numbers in { -524256 to<br>+524286}<br>o<br>Valid Accel samples: All numbers divisible by 4 in {-524256 to<br>+524284}<br>o<br>FSYNC tagging is not applied to data in FIFO.<br>**Setting this bit to 1:**<br>Sense registers:<br>•<br>Do not receive invalid samples. They hold the last valid<br>sample. Repeated reading before new sample received will yield<br>copies of the last valid sample.<br>•<br>FSYNC Tagging can modify the least significant bit and further limit<br>values (see section 12.8).<br>FIFO:<br>•<br>Invalid sample will get copy of last valid sample<br>•<br>16-bit FIFO packet: Same as Sense Registers, except:<br>o<br>FSYNC tagging is not applied to data in FIFO.<br>•<br>20-bit FIFO packet:<br>o<br>Valid Gyro samples: All Even numbers in {-524288 to<br>+524286}<br>o<br>- Valid Accel samples: All numbers divisible by 4 in {-524288 to<br>+524284}|
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Name: INTF_CONFIG0 Address: 76 (4Ch) Serial IF: R/W Reset value: 0x30 Clock Domain: SCLK_UI
|Name: INTF_CONFIG0<br>Address: 76 (4Ch)<br>Serial IF: R/W<br>Reset value: 0x30<br>Clock Domain: SCLK_UI_UIUI|Name: INTF_CONFIG0<br>Address: 76 (4Ch)<br>Serial IF: R/W<br>Reset value: 0x30<br>Clock Domain: SCLK_UI_UIUI|Name: INTF_CONFIG0<br>Address: 76 (4Ch)<br>Serial IF: R/W<br>Reset value: 0x30<br>Clock Domain: SCLK_UI_UIUI|
|---|---|---|
|**BIT**|**NAME**|**FUNCTION**|
|6|FIFO_COUNT_REC|0: FIFO count is reported in bytes<br>1: FIFO count is reported in records (1 record = 16 bytes for header + gyro +<br>accel + temp sensor data + time stamp, or 8 bytes for header + gyro/accel +<br>tempsensor data)|
|5|FIFO_COUNT_ENDIAN|0: FIFO count is reported in Little Endian format<br>1: FIFO count is reported in BigEndian format(default)|
|4|SENSOR_DATA_ENDIAN|0: Sensor data is reported in Little Endian format<br>1: Sensor data is reported in BigEndian format(default)|
|3:2|-|Reserved|
|1:0|UI_SIFS_CFG|0x: Reserved<br>10: Disable SPI<br>11: Disable I2C|
**Invalid Data Generation:** FIFO/Sense Registers may contain invalid data under the following conditions:
- a) From power on reset to first ODR sample of any sensor (accel, gyro, temp sensor)
- b) When any sensor is disabled (accel, gyro, temp sensor)
- c) When accel and gyro are enabled with different ODRs. In this case, the sensor with lower ODR will generate invalid samples when it has no new data.
Invalid data can take special values or can hold last valid sample received. For -32768 to be used as a flag for invalid accel/gyro samples, the valid accel/gyro sample range is limited in such case as well. Bit 7 of INTF_CONFIG0 controls what values invalid (and valid) samples can take as shown above.
## **INTF_CONFIG1**
Name: INTF_CONFIG1 Address: 77 (4Dh) Serial IF: R/W Reset value: 0x91 Clock Domain: SCLK_UI
|**BIT**|**NAME**|**FUNCTION**|
|---|---|---|
|7:4|-|Reserved|
|3|ACCEL_LP_CLK_SEL|0: Accelerometer LP mode uses Wake Up oscillator clock<br>1: Accelerometer LP mode uses RC oscillator clock|
|2|RTC_MODE|0: No input RTC clock is required<br>1: RTC clock input is required|
|||00: Always select internal RC oscillator|
|1:0|CLKSEL|01: Select PLL when available, else select RC oscillator (default)<br>10: Reserved|
|||11: Disable all clocks|
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## **PWR_MGMT0**
Name: PWR_MGMT0 Address: 78 (4Eh) Serial IF: R/W Reset value: 0x00 Clock Domain: SCLK_UI
|**PWR_MGMT0**|**PWR_MGMT0**|**PWR_MGMT0**|
|---|---|---|
|Name: PWR_MGMT0<br>Address: 78 (4Eh)<br>Serial IF: R/W<br>Reset value: 0x00<br>Clock Domain: SCLK_UI_UIUI|||
|**BIT**|**NAME**|**FUNCTION**|
|7:6|-|Reserved|
|5|TEMP_DIS|0: Temperature sensor is enabled (default)<br>1: Temperature sensor is disabled|
|4|IDLE|If this bit is set to 1, the RC oscillator is powered on even if Accel and Gyro<br>are powered off.<br>Nominally this bit is set to 0, so when Accel and Gyro are powered off,<br>the chipwillgo to OFF state,since the RC oscillator will also bepowered off|
|3:2|GYRO_MODE|00: Turns gyroscope off (default)<br>01: Places gyroscope in Standby Mode<br>10: Reserved<br>11: Places gyroscope in Low Noise (LN) Mode<br>Gyroscope needs to be kept ON for a minimum of 45ms. When transitioning<br>from OFF to any of the other modes, do not issue any register writes for<br>200µs.|
|1:0|ACCEL_MODE|00: Turns accelerometer off (default)<br>01: Turns accelerometer off<br>10: Places accelerometer in Low Power (LP) Mode<br>11: Places accelerometer in Low Noise (LN) Mode<br>When transitioning from OFF to any of the other modes, do not issue any<br>register writes for 200µs.|
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## **GYRO_CONFIG0**
|**GYRO_CONFIG0**|**GYRO_CONFIG0**|**GYRO_CONFIG0**|
|---|---|---|
|Name: GYRO_CONFIG0<br>Address: 79 (4Fh)<br>Serial IF: R/W<br>Reset value: 0x06<br>Clock Domain: SCLK_UI|||
|**BIT**|**NAME**|**FUNCTION**|
|7:5|GYRO_FS_SEL|Full scale select for gyroscope UI interface output<br>000: ±2000dps (default)<br>001: ±1000dps<br>010: ±500dps<br>011: ±250dps<br>100: ±125dps<br>101: ±62.5dps<br>110: ±31.25dps<br>111: ±15.625dps|
|4|-|Reserved|
|3:0|GYRO_ODR|Gyroscope ODR selection for UI interface output<br>0000: Reserved<br>0001: 32kHz<br>0010: 16kHz<br>0011: 8kHz<br>0100: 4kHz<br>0101: 2kHz<br>0110: 1kHz (default)<br>0111: 200Hz<br>1000: 100Hz<br>1001: 50Hz<br>1010: 25Hz<br>1011: 12.5Hz<br>1100: Reserved<br>1101: Reserved<br>1110: Reserved<br>1111: 500Hz|
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## **ACCEL_CONFIG0**
|**ACCEL_CONFIG0**|**ACCEL_CONFIG0**|**ACCEL_CONFIG0**|
|---|---|---|
|Name: ACCEL_CONFIG0<br>Address: 80 (50h)<br>Serial IF: R/W<br>Reset value: 0x06<br>Clock Domain: SCLK_UI|||
|**BIT**|**NAME**|**FUNCTION**|
|7:5|ACCEL_FS_SEL|Full scale select for accelerometer UI interface output<br>000: ±16g (default)<br>001: ±8g<br>010: ±4g<br>011: ±2g<br>100: Reserved<br>101: Reserved<br>110: Reserved<br>111: Reserved|
|4|-|Reserved|
|3:0|ACCEL_ODR|Accelerometer ODR selection for UI interface output<br>0000: Reserved<br>0001: 32kHz<br>0010: 16kHz<br>0011: 8kHz (LN mode)<br>0100: 4kHz (LN mode)<br>0101: 2kHz (LN mode)<br>0110: 1kHz (LN mode) (default)<br>0111: 200Hz (LP or LN mode)<br>1000: 100Hz (LP or LN mode)<br>1001: 50Hz (LP or LN mode)<br>1010: 25Hz (LP or LN mode)<br>1011: 12.5Hz (LP or LN mode)<br>1100: 6.25Hz (LP mode)<br>1101: 3.125Hz (LP mode)<br>1110: 1.5625Hz (LP mode)<br>1111: 500Hz(LP or LN mode)|
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## **GYRO_CONFIG1**
|**GYRO_CONFIG1**|**GYRO_CONFIG1**|**GYRO_CONFIG1**|
|---|---|---|
|Name: GYRO_CONFIG1<br>Address: 81 (51h)<br>Serial IF: R/W<br>Reset value: 0x16<br>Clock Domain: SCLK_UI|||
|**BIT**|**NAME**|**FUNCTION**|
|7:5|TEMP_FILT_BW|Sets the bandwidth of the temperature signal DLPF<br>000: DLPF BW = 4000Hz; DLPF Latency = 0.125ms (default)<br>001: DLPF BW = 170Hz; DLPF Latency = 1ms<br>010: DLPF BW = 82Hz; DLPF Latency = 2ms<br>011: DLPF BW = 40Hz; DLPF Latency = 4ms<br>100: DLPF BW = 20Hz; DLPF Latency = 8ms<br>101: DLPF BW = 10Hz; DLPF Latency = 16ms<br>110: DLPF BW = 5Hz; DLPF Latency = 32ms<br>111: DLPF BW = 5Hz;DLPF Latency= 32ms|
|4|-|Reserved|
|3:2|GYRO_UI_FILT_ORD|Selects order of GYRO UI filter<br>00: 1stOrder<br>01: 2ndOrder<br>10: 3rdOrder<br>11: Reserved|
|1:0|GYRO_DEC2_M2_ORD|Selects order of GYRO DEC2_M2 Filter<br>00: Reserved<br>01: Reserved<br>10: 3rdOrder<br>11: Reserved|
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## **GYRO_ACCEL_CONFIG0**
|**GYRO_ACCEL_CONFIG0**|**GYRO_ACCEL_CONFIG0**|**GYRO_ACCEL_CONFIG0**|
|---|---|---|
|Name: GYRO_ACCEL_CONFIG0<br>Address: 82 (52h)<br>Serial IF: R/W<br>Reset value: 0x11<br>Clock Domain: SCLK_UI|||
|**BIT**|**NAME**|**FUNCTION**|
|7:4|ACCEL_UI_FILT_BW|**LN Mode:**<br>Bandwidth for Accel LPF<br>0 BW=ODR/2<br>1 BW=max(400Hz, ODR)/4 (default)<br>2 BW=max(400Hz, ODR)/5<br>3 BW=max(400Hz, ODR)/8<br>4 BW=max(400Hz, ODR)/10<br>5 BW=max(400Hz, ODR)/16<br>6 BW=max(400Hz, ODR)/20<br>7 BW=max(400Hz, ODR)/40<br>8 to 13: Reserved<br>14 Low Latency option: Trivial decimation @ ODR of Dec2 filter output. Dec2<br>runs at max(400Hz, ODR)<br>15 Low Latency option: Trivial decimation @ ODR of Dec2 filter output. Dec2<br>runs at max(200Hz, 8*ODR)<br>**LP Mode:**<br>0 Reserved<br>1 1x AVG filter (default)<br>2 to 5 Reserved<br>6 16x AVG filter<br>7 to 15 Reserved|
|3:0|GYRO_UI_FILT_BW|**LN Mode:**<br>Bandwidth for Gyro LPF<br>0 BW=ODR/2<br>1 BW=max(400Hz, ODR)/4 (default)<br>2 BW=max(400Hz, ODR)/5<br>3 BW=max(400Hz, ODR)/8<br>4 BW=max(400Hz, ODR)/10<br>5 BW=max(400Hz, ODR)/16<br>6 BW=max(400Hz, ODR)/20<br>7 BW=max(400Hz, ODR)/40<br>8 to 13: Reserved<br>14 Low Latency option: Trivial decimation @ ODR of Dec2 filter output. Dec2<br>runs at max(400Hz, ODR)<br>15 Low Latency option: Trivial decimation @ ODR of Dec2 filter output. Dec2<br>runs at max(200Hz,8*ODR)|
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## **ACCEL_CONFIG1**
**==> picture [315 x 218] intentionally omitted <==**
**----- Start of picture text -----**<br>
||||||
|---|---|---|---|---|
|Name: ACCEL_CONFIG1|
|Address: 83 (53h)|
|Serial IF: R/W|
|Reset value: 0x0D|
|Clock Domain: SCLK_UI|
|BIT|NAME|FUNCTION|
|7:5|-|Reserved|
|Selects order of ACCEL UI filter|
|00: 1|[st]|Order|
|4:3|ACCEL_UI_FILT_ORD|01: 2|[nd]|Order|
|10: 3|[rd]|Order|
|11: Reserved|
|Order of Accelerometer DEC2_M2 filter|
|00: Reserved|
|2:1|ACCEL_DEC2_M2_ORD|01: Reserved|
|10: 3|[rd]|order|
|11: Reserved|
|0|-|Reserved|
**----- End of picture text -----**<br>
## **TMST_CONFIG**
Name: TMST_CONFIG Address: 84 (54h) Serial IF: R/W Reset value: 0x23 Clock Domain: SCLK_UI
**==> picture [458 x 197] intentionally omitted <==**
**----- Start of picture text -----**<br>
||||
|---|---|---|
|BIT|NAME|FUNCTION|
|7:5|-|Reserved|
|0: TMST_VALUE[19:0] read always returns 0s|
|4|TMST_TO_REGS_EN|
|1: TMST_VALUE[19:0] read returns timestamp value|
|Time Stamp resolution:|
|When set to 0 (default), time stamp resolution is 1 µs.|
|3|TMST_RES|
|When set to 1: If RTC is disabled, resolution is 16 µs. If RTC is enabled,|
|resolution is 1 RTC clock period|
|Time Stamp delta enable: When set to 1, the time stamp field contains the|
|2|TMST_DELTA_EN|
|measurement of time since the last occurrence of ODR.|
|Time Stamp register FSYNC enable (default). When set to 1, the contents of|
|the Timestamp feature of FSYNC is enabled. The user also needs to select|
|1|TMST_FSYNC_EN|
|FIFO_TMST_FSYNC_EN in order to propagate the timestamp value to the|
|FIFO.|
|0: Time Stamp register disable|
|0|TMST_EN|
|1: Time Stamp register enable (default)|
**----- End of picture text -----**<br>
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## **APEX_CONFIG0**
|**APEX_CONFIG0**|**APEX_CONFIG0**|**APEX_CONFIG0**|
|---|---|---|
|Name: APEX_CONFIG0<br>Address: 86 (56h)<br>Serial IF: R/W<br>Reset value: 0x82<br>Clock Domain: SCLK_UI|||
|**BIT**|**NAME**|**FUNCTION**|
|7|DMP_POWER_SAVE|0: DMP power save mode not active<br>1: DMPpower save mode active(default)|
|6|TAP_ENABLE|0: Tap Detection not enabled<br>1: Tap Detection enabled when accelerometer ODR is set to one of the ODR<br>values supported byTapDetection(200Hz,500Hz,1kHz)|
|5|PED_ENABLE|0: Pedometer not enabled<br>1: Pedometer enabled|
|4|TILT_ENABLE|0: Tilt Detection not enabled<br>1: Tilt Detection enabled|
|3|-|Reserved|
|2|FF_ENABLE|0: Freefall Detection not enabled<br>1: Freefall Detection enabled|
|1:0|DMP_ODR|00: 25Hz<br>01: 500 Hz<br>10: 50Hz<br>11: 100 Hz|
## **SMD_CONFIG**
Name: SMD_CONFIG Address: 87 (57h) Serial IF: R/W Reset value: 0x00 Clock Domain: SCLK_UI
|**SMD_CONFIG**|**SMD_CONFIG**|**SMD_CONFIG**|
|---|---|---|
|Name: SMD_CONFIG<br>Address: 87 (57h)<br>Serial IF: R/W<br>Reset value: 0x00<br>Clock Domain: SCLK_UI_UIUI|||
|**BIT**|**NAME**|**FUNCTION**|
|7:4|-|Reserved|
|3|WOM_INT_MODE|0: Set WoM interrupt on the OR of all enabled accelerometer thresholds<br>1: Set WoM interrupt on the AND of all enabled accelerometer threshold|
|2|WOM_MODE|0: Initial sample is stored. Future samples are compared to initial sample<br>1: Compare current sample toprevious sample|
|1:0|SMD_MODE|00: SMD disabled<br>01: WOM mode<br>10: SMD short (1 sec wait) An SMD event is detected when two WOM are<br>detected 1 sec apart<br>11: SMD long (3 sec wait) An SMD event is detected when two WOM are<br>detected 3 sec apart|
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## **FIFO_CONFIG1**
|Name: FIFO_CONFIG1<br>Address: 95 (5Fh)<br>Serial IF: R/W<br>Reset value: 0x00<br>Clock Domain: SCLK_UI|Name: FIFO_CONFIG1<br>Address: 95 (5Fh)<br>Serial IF: R/W<br>Reset value: 0x00<br>Clock Domain: SCLK_UI|Name: FIFO_CONFIG1<br>Address: 95 (5Fh)<br>Serial IF: R/W<br>Reset value: 0x00<br>Clock Domain: SCLK_UI|
|---|---|---|
|**BIT**|**NAME**|**FUNCTION**|
|7|-|Reserved|
|6|FIFO_RESUME_PARTIAL_RD|0: Partial FIFO read disabled, requires re-reading of the entire FIFO<br>1: FIFO read can bepartial,and resume from last readpoint|
|5|FIFO_WM_GT_TH|Trigger FIFO watermark interrupt on every ODR (DMA write) if<br>FIFO_COUNT ≥ FIFO_WM_TH|
|4|FIFO_HIRES_EN|0: Default setting; Sensor data have regular resolution<br>1: Sensor data in FIFO will have extended resolution enabling the 20 Bytes<br>packet|
|3|FIFO_TMST_FSYNC_EN|Must be set to 1 for all FIFO use cases when FSYNC is used|
|2|FIFO_TEMP_EN|Enable temperature sensorpackets togo to FIFO|
|1|FIFO_GYRO_EN|Enablegyroscopepackets togo to FIFO|
|0|FIFO_ACCEL_EN|Enable accelerometerpackets togo to FIFO|
## **FIFO_CONFIG2**
|Name: FIFO_CONFIG2<br>Address: 96 (60h)<br>Serial IF: R/W<br>Reset value: 0x00<br>Clock Domain: SCLK_UI|Name: FIFO_CONFIG2<br>Address: 96 (60h)<br>Serial IF: R/W<br>Reset value: 0x00<br>Clock Domain: SCLK_UI|Name: FIFO_CONFIG2<br>Address: 96 (60h)<br>Serial IF: R/W<br>Reset value: 0x00<br>Clock Domain: SCLK_UI|
|---|---|---|
|**BIT**|**NAME**|**FUNCTION**|
|7:0|FIFO_WM[7:0]|Lower bits of FIFO watermark. Generate interrupt when the FIFO reaches<br>or exceeds FIFO_WM size in bytes or records according to<br>FIFO_COUNT_REC setting. Interrupt only fires once. This register should<br>be set to non-zero value,before choosingthis interrupt source.|
## **FIFO_CONFIG3**
Name: FIFO_CONFIG3 Address: 97 (61h) Serial IF: R/W Reset value: 0x00 Clock Domain: SCLK_UI
|**BIT**|**NAME**|**FUNCTION**|
|---|---|---|
|7:4|-|Reserved|
|||Upper bits of FIFO watermark. Generate interrupt when the FIFO reaches|
|3:0|FIFO_WM[11:8]|or exceeds FIFO_WM size in bytes or records according to<br>FIFO_COUNT_REC setting. Interrupt only fires once. This register should|
|||be set to non-zero value,before choosingthis interrupt source.|
**Note:** Do not set FIFO_WM to value 0.
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## **FSYNC_CONFIG**
|**FSYNC_CONFIG**|**FSYNC_CONFIG**|**FSYNC_CONFIG**|
|---|---|---|
|Name: FSYNC_CONFIG<br>Address: 98 (62h)<br>Serial IF: R/W<br>Reset value: 0x10<br>Clock Domain: SCLK_UI|||
|**BIT**|**NAME**|**FUNCTION**|
|7|-|Reserved|
|6:4|FSYNC_UI_SEL|000: Do not tag FSYNC flag<br>001: Tag FSYNC flag to TEMP_OUT LSB<br>010: Tag FSYNC flag to GYRO_XOUT LSB<br>011: Tag FSYNC flag to GYRO_YOUT LSB<br>100: Tag FSYNC flag to GYRO_ZOUT LSB<br>101: Tag FSYNC flag to ACCEL_XOUT LSB<br>110: Tag FSYNC flag to ACCEL_YOUT LSB<br>111: TagFSYNC flagto ACCEL_ZOUT LSB|
|3:2|-|Reserved|
|1|FSYNC_UI_FLAG_CLEAR_SE<br>L|0: FSYNC flag is cleared when UI sensor register is updated<br>1: FSYNC flag is cleared when UI interface reads the sensor register LSB of<br>FSYNC tagged axis|
|0|FSYNC_POLARITY|0: Start from Rising edge of FSYNC pulse to measure FSYNC interval<br>1: Start from Fallingedge of FSYNCpulse to measure FSYNC interval|
## **INT_CONFIG0**
|Name: INT_CONFIG0<br>Address: 99 (63h)<br>Serial IF: R/W<br>Reset value: 0x00<br>Clock Domain: SCLK_UI|Name: INT_CONFIG0<br>Address: 99 (63h)<br>Serial IF: R/W<br>Reset value: 0x00<br>Clock Domain: SCLK_UI|Name: INT_CONFIG0<br>Address: 99 (63h)<br>Serial IF: R/W<br>Reset value: 0x00<br>Clock Domain: SCLK_UI|
|---|---|---|
|**BIT**|**NAME**|**FUNCTION**|
|7:6|-|Reserved|
|5:4|UI_DRDY_INT_CLEAR|Data Ready Interrupt Clear Option (latched mode)<br>00: Clear on Status Bit Read (default)<br>01: Clear on Status Bit Read<br>10: Clear on Sensor Register Read<br>11: Clear on Status Bit Read AND on Sensor Register read|
|3:2|FIFO_THS_INT_CLEAR|FIFO Threshold Interrupt Clear Option (latched mode)<br>00: Clear on Status Bit Read (default)<br>01: Clear on Status Bit Read<br>10: Clear on FIFO data 1Byte Read<br>11: Clear on Status Bit Read AND on FIFO data 1 byte read|
|1:0|FIFO_FULL_INT_CLEAR|FIFO Full Interrupt Clear Option (latched mode)<br>00: Clear on Status Bit Read (default)<br>01: Clear on Status Bit Read<br>10: Clear on FIFO data 1Byte Read<br>11: Clear on Status Bit Read AND on FIFO data 1 byte read|
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## **INT_CONFIG1**
Name: INT_CONFIG1 Address: 100 (64h) Serial IF: R/W Reset value: 0x10 Clock Domain: SCLK_UI
|**INT_CONFIG1**|**INT_CONFIG1**|**INT_CONFIG1**|
|---|---|---|
|Name: INT_CONFIG1<br>Address: 100 (64h)<br>Serial IF: R/W<br>Reset value: 0x10<br>Clock Domain: SCLK_UI_UIUI|||
|**BIT**|**NAME**|**FUNCTION**|
|7|-|Reserved|
|6|INT_TPULSE_DURATION|Interrupt pulse duration<br>0: Interrupt pulse duration is 100µs. Use only if ODR < 4kHz. (Default)<br>1: Interrupt pulse duration is 8 µs. Required if ODR ≥ 4kHz, optional for ODR<br>< 4kHz.|
|5|INT_TDEASSERT_DISABLE|Interrupt de-assertion duration<br>0: The interrupt de-assertion duration is set to a minimum of 100µs. Use<br>only if ODR < 4kHz. (Default)<br>1: Disables de-assert duration. Required if ODR ≥ 4kHz, optional for ODR <<br>4kHz.|
|4|INT_ASYNC_RESET|User should change setting to 0 from default setting of 1, for proper INT1<br>and INT2pin operation|
|3:0|-|Reserved|
## **INT_SOURCE0**
Name: INT_SOURCE0 Address: 101 (65h) Serial IF: R/W Reset value: 0x10 Clock Domain: SCLK_UI
|**BIT**|**NAME**|**FUNCTION**|
|---|---|---|
|7|-|Reserved|
|6|UI_FSYNC_INT1_EN|0: UI FSYNC interrupt not routed to INT1<br>1: UI FSYNC interrupt routed to INT1|
|5|PLL_RDY_INT1_EN|0: PLL ready interrupt not routed to INT1<br>1: PLL readyinterrupt routed to INT1|
|4|RESET_DONE_INT1_EN|0: Reset done interrupt not routed to INT1<br>1: Reset done interrupt routed to INT1|
|3|UI_DRDY_INT1_EN|0: UI data ready interrupt not routed to INT1<br>1: UI data readyinterrupt routed to INT1|
|2|FIFO_THS_INT1_EN|0: FIFO threshold interrupt not routed to INT1<br>1: FIFO threshold interrupt routed to INT1|
|1|FIFO_FULL_INT1_EN|0: FIFO full interrupt not routed to INT1<br>1: FIFO full interrupt routed to INT1|
|0|UI_AGC_RDY_INT1_EN|0: UI AGC ready interrupt not routed to INT1<br>1: UI AGC readyinterrupt routed to INT1|
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## **INT_SOURCE1**
Name: INT_SOURCE1 Address: 102 (66h) Serial IF: R/W Reset value: 0x00 Clock Domain: SCLK_UI
|**BIT**|**NAME**|**FUNCTION**|
|---|---|---|
|7|-|Reserved|
|6|I3C_PROTOCOL_ERROR_IN<br>T1_EN|0: I3CSMprotocol error interrupt not routed to INT1<br>1: I3CSM protocol error interrupt routed to INT1|
|5:4|-|Reserved|
|3|SMD_INT1_EN|0: SMD interrupt not routed to INT1<br>1: SMD interrupt routed to INT1|
|2|WOM_Z_INT1_EN|0: Z-axis WOM interrupt not routed to INT1<br>1: Z-axis WOM interrupt routed to INT1|
|1|WOM_Y_INT1_EN|0: Y-axis WOM interrupt not routed to INT1<br>1: Y-axis WOM interrupt routed to INT1|
|0|WOM_X_INT1_EN|0: X-axis WOM interrupt not routed to INT1<br>1: X-axis WOM interrupt routed to INT1|
## **INT_SOURCE3**
Name: INT_SOURCE3 Address: 104 (68h) Serial IF: R/W Reset value: 0x00 Clock Domain: SCLK_UI
|**BIT**|**NAME**|**FUNCTION**|
|---|---|---|
|7|-|Reserved|
|6|UI_FSYNC_INT2_EN|0: UI FSYNC interrupt not routed to INT2<br>1: UI FSYNC interrupt routed to INT2|
|5|PLL_RDY_INT2_EN|0: PLL ready interrupt not routed to INT2<br>1: PLL readyinterrupt routed to INT2|
|4|RESET_DONE_INT2_EN|0: Reset done interrupt not routed to INT2<br>1: Reset done interrupt routed to INT2|
|3|UI_DRDY_INT2_EN|0: UI data ready interrupt not routed to INT2<br>1: UI data readyinterrupt routed to INT2|
|2|FIFO_THS_INT2_EN|0: FIFO threshold interrupt not routed to INT2<br>1: FIFO threshold interrupt routed to INT2|
|1|FIFO_FULL_INT2_EN|0: FIFO full interrupt not routed to INT2<br>1: FIFO full interrupt routed to INT2|
|0|UI_AGC_RDY_INT2_EN|0: UI AGC ready interrupt not routed to INT2<br>1: UI AGC readyinterrupt routed to INT2|
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## **INT_SOURCE4**
Name: INT_SOURCE4 Address: 105 (69h) Serial IF: R/W Reset value: 0x00 Clock Domain: SCLK_UI
|**BIT**|**NAME**|**FUNCTION**|
|---|---|---|
|7|-|Reserved|
|6|I3C_PROTOCOL_ERROR_IN<br>T2_EN|0: I3CSMprotocol error interrupt not routed to INT2<br>1: I3CSM protocol error interrupt routed to INT2|
|5:4|-|Reserved|
|3|SMD_INT2_EN|0: SMD interrupt not routed to INT2<br>1: SMD interrupt routed to INT2|
|2|WOM_Z_INT2_EN|0: Z-axis WOM interrupt not routed to INT2<br>1: Z-axis WOM interrupt routed to INT2|
|1|WOM_Y_INT2_EN|0: Y-axis WOM interrupt not routed to INT2<br>1: Y-axis WOM interrupt routed to INT2|
|0|WOM_X_INT2_EN|0: X-axis WOM interrupt not routed to INT2<br>1: X-axis WOM interrupt routed to INT2|
## **FIFO_LOST_PKT0**
Name: FIFO_LOST_PKT0 Address: 108 (6Ch) Serial IF: R Reset value: 0x00 Clock Domain: SCLK_UI **BIT NAME FUNCTION** 7:0 FIFO_LOST_PKT_CNT[7:0] Low byte, number of packets lost in the FIFO
## **FIFO_LOST_PKT1**
Name: FIFO_LOST_PKT1 Address: 109 (6Dh) Serial IF: R Reset value: 0x00 Clock Domain: SCLK_UI **BIT NAME FUNCTION** 7:0 FIFO_LOST_PKT_CNT[15:8] High byte, number of packets lost in the FIFO
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## **SELF_TEST_CONFIG**
|**SELF_TEST_CONFIG**<br>14.57|**SELF_TEST_CONFIG**<br>14.57|**SELF_TEST_CONFIG**<br>14.57|
|---|---|---|
|Name: SELF_TEST_CONFIG<br>Address: 112 (70h)<br>Serial IF: R/W<br>Reset value: 0x00<br>Clock Domain: SCLK_UI|||
|**BIT**|**NAME**|**FUNCTION**|
|7|-|Reserved|
|6|ACCEL_ST_POWER|Set to 1 for accel self-test<br>Otherwise set to 0;Set to 0 after self-test is completed|
|5|EN_AZ_ST|Enable Z-accel self-test|
|4|EN_AY_ST|Enable Y-accel self-test|
|3|EN_AX_ST|Enable X-accel self-test|
|2|EN_GZ_ST|Enable Z-gyro self-test|
|1|EN_GY_ST|Enable Y-gyro self-test|
|0|EN_GX_ST|Enable X-gyro self-test|
## **WHO_AM_I**
|**WHO_AM_I**<br>14.58|**WHO_AM_I**<br>14.58|**WHO_AM_I**<br>14.58|
|---|---|---|
|Name: WHO_AM_I<br>Address: 117 (75h)<br>Serial IF: R<br>Reset value: 0x6F<br>Clock Domain: SCLK_UI|||
|**BIT**|**NAME**|**FUNCTION**|
|7:0|WHOAMI|Register to indicate to user which device is beingaccessed|
## Description:
This register is used to verify the identity of the device. The contents of WHOAMI is an 8-bit device ID. The default value of the register is 0x6F. This is different from the I[2] C address of the device as seen on the slave I[2] C controller by the applications processor.
## **REG_BANK_SEL**
Note: This register is accessible from all register banks
|Name: REG_BANK_SEL|Name: REG_BANK_SEL||
|---|---|---|
|Address: 118 (76h)|||
|Serial IF: R/W|Serial IF: R/W||
|Reset value: 0x00|Reset value: 0x00||
|Clock Domain: ALL|Clock Domain: ALL||
|**BIT**|**NAME**|**FUNCTION**|
|7:3|-|Reserved|
|||Register bank selection|
|||000: Bank 0 (default)|
|||001: Bank 1|
|||010: Bank 2|
|2:0|BANK_SEL|011: Bank 3|
|||100: Bank 4|
|||101: Reserved|
|||110: Reserved|
|||111: Reserved|
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## _**15 USER BANK 1 REGISTER MAP – DESCRIPTIONS**_
This section describes the function and contents of each register within USR Bank 1.
## **SENSOR_CONFIG0**
|**SENSOR_CONFIG0**||
|---|---|
|Name: SENSOR_CONFIG0||
|Address: 03 (03h)||
|Serial IF: R/W||
|Reset value: 0x80||
|Clock Domain: SCLK_UI||
|**BIT**<br>**NAME**|**FUNCTION**|
|7:6<br>-|Reserved|
|5<br>ZG_DISABLE|0: Z gyroscope is on<br>1: Zgyroscope is disabled|
|4<br>YG_DISABLE|0: Y gyroscope is on<br>1: Ygyroscope is disabled|
|3<br>XG_DISABLE|0: X gyroscope is on<br>1: Xgyroscope is disabled|
|2<br>ZA_DISABLE|0: Z accelerometer is on<br>1: Z accelerometer is disabled|
|1<br>YA_DISABLE|0: Y accelerometer is on<br>1: Y accelerometer is disabled|
|0<br>XA_DISABLE|0: X accelerometer is on<br>1: X accelerometer is disabled|
## **GYRO_CONFIG_STATIC2**
|**GYRO_CONFIG_STATIC2**|**GYRO_CONFIG_STATIC2**|**GYRO_CONFIG_STATIC2**|
|---|---|---|
|Name: GYRO_CONFIG_STATIC2<br>Address: 11 (0Bh)<br>Serial IF: R/W<br>Reset value: 0xA0<br>Clock Domain: SCLK_UI|||
|**BIT**|**NAME**|**FUNCTION**|
|7:2|-|Reserved|
|1|GYRO_AAF_DIS|0: Enable Anti-Aliasing/Low Pass Filter<br>1: Disable Anti-Aliasing/Low Pass Filter|
|0|GYRO_NF_DIS|0: Enable Notch Filter<br>1: Disable Notch Filter|
## **GYRO_CONFIG_STATIC3**
|**GYRO_CONFIG_STATIC3**|**GYRO_CONFIG_STATIC3**|**GYRO_CONFIG_STATIC3**|
|---|---|---|
|Name: GYRO_CONFIG_STATIC3<br>Address: 12 (0Ch)<br>Serial IF: R/W<br>Reset value: 0x0D<br>Clock Domain: SCLK_UI|||
|**BIT**|**NAME**|**FUNCTION**|
|7:6|-|Reserved|
|5:0|GYRO_AAF_DELT|Controls bandwidth of the gyroscope anti-alias filter<br>See section 5.3 for details|
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## **GYRO_CONFIG_STATIC4**
|**GYRO_CONFIG_STATIC4**|**GYRO_CONFIG_STATIC4**|**GYRO_CONFIG_STATIC4**|
|---|---|---|
|Name: GYRO_CONFIG_STATIC4<br>Address: 13 (0Dh)<br>Serial IF: R/W<br>Reset value: 0xAA<br>Clock Domain: SCLK_UI|||
|**BIT**|**NAME**|**FUNCTION**|
|7:0|GYRO_AAF_DELTSQR[7:0]|Controls bandwidth of the gyroscope anti-alias filter<br>See section 5.3 for details|
## **GYRO_CONFIG_STATIC5**
|Name: GYRO_CONFIG_STATIC5<br>Address: 14 (0Eh)<br>Serial IF: R/W<br>Reset value: 0x80<br>Clock Domain: SCLK_UI|Name: GYRO_CONFIG_STATIC5<br>Address: 14 (0Eh)<br>Serial IF: R/W<br>Reset value: 0x80<br>Clock Domain: SCLK_UI|Name: GYRO_CONFIG_STATIC5<br>Address: 14 (0Eh)<br>Serial IF: R/W<br>Reset value: 0x80<br>Clock Domain: SCLK_UI|
|---|---|---|
|**BIT**|**NAME**|**FUNCTION**|
|7:4|GYRO_AAF_BITSHIFT|Controls bandwidth of the gyroscope anti-alias filter<br>See section 5.3 for details|
|3:0|GYRO_AAF_DELTSQR[11:8]|Controls bandwidth of the gyroscope anti-alias filter<br>See section for details|
## **GYRO_CONFIG_STATIC6**
Name: GYRO_CONFIG_STATIC6 Address: 15 (0Fh) Serial IF: R/W Reset value: 0xXX (Factory trimmed on an individual device basis) Clock Domain: SCLK_UI **BIT NAME FUNCTION** Used for gyroscope X-axis notch filter frequency selection 7:0 GYRO_X_NF_COSWZ[7:0] See section 5.1 for details
## **GYRO_CONFIG_STATIC7**
|Name: GYRO_CONFIG_STATIC7<br>Address: 16 (10h)<br>Serial IF: R/W<br>Reset value: 0xXX (Factory trimmed on an individual device basis)<br>Clock Domain: SCLK_UI|Name: GYRO_CONFIG_STATIC7<br>Address: 16 (10h)<br>Serial IF: R/W<br>Reset value: 0xXX (Factory trimmed on an individual device basis)<br>Clock Domain: SCLK_UI|Name: GYRO_CONFIG_STATIC7<br>Address: 16 (10h)<br>Serial IF: R/W<br>Reset value: 0xXX (Factory trimmed on an individual device basis)<br>Clock Domain: SCLK_UI|
|---|---|---|
|**BIT**|**NAME**|**FUNCTION**|
|7:0|GYRO_Y_NF_COSWZ[7:0]|Used for gyroscope Y-axis notch filter frequency selection<br>See section 5.1 for details|
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## **GYRO_CONFIG_STATIC8**
|**GYRO_CONFIG_STATIC8**|**GYRO_CONFIG_STATIC8**|**GYRO_CONFIG_STATIC8**|
|---|---|---|
|Name: GYRO_CONFIG_STATIC8<br>Address: 17 (11h)<br>Serial IF: R/W<br>Reset value: 0xXX (Factory trimmed on an individual device basis)<br>Clock Domain: SCLK_UI|||
|**BIT**|**NAME**|**FUNCTION**|
|7:0|GYRO_Z_NF_COSWZ[7:0]|Used for gyroscope Z-axis notch filter frequency selection<br>See section 5.1 for details|
## **GYRO_CONFIG_STATIC9**
Name: GYRO_CONFIG_STATIC9 Address: 18 (12h) Serial IF: R/W Reset value: 0xXX (Factory trimmed on an individual device basis) Clock Domain: SCLK_UI
|**BIT**|**NAME**|**FUNCTION**|
|---|---|---|
|7:6|-|Reserved|
|5|GYRO_Z_NF_COSWZ_SEL[0]|Used for gyroscope Z-axis notch filter frequency selection<br>See section 5.1 for details|
|4|GYRO_Y_NF_COSWZ_SEL[0]|Used for gyroscope Y-axis notch filter frequency selection<br>See section 5.1 for details|
|3|GYRO_X_NF_COSWZ_SEL[0]|Used for gyroscope X-axis notch filter frequency selection<br>See section 5.1 for details|
|2|GYRO_Z_NF_COSWZ[8]|Used for gyroscope Z-axis notch filter frequency selection<br>See section 5.1 for details|
|1|GYRO_Y_NF_COSWZ[8]|Used for gyroscope Y-axis notch filter frequency selection<br>See section 5.1 for details|
|0|GYRO_X_NF_COSWZ[8]|Used for gyroscope X-axis notch filter frequency selection<br>See section 5.1 for details|
## **GYRO_CONFIG_STATIC10**
Name: GYRO_CONFIG_STATIC10 Address: 19 (13h) Serial IF: R/W Reset value: 0x11 Clock Domain: SCLK_UI
|**BIT**|**NAME**|**FUNCTION**|
|---|---|---|
|7|-|Reserved|
|6:4|GYRO_NF_BW_SEL|Selects bandwidth for gyroscope notch filter<br>See section 5.1 for details|
|3:1|GYRO_HPF_BW_IND|Selects HPF 3dB cutoff frequency bandwidth<br>See section 0 for details|
|||Selects HPF filter order (see section 0 for details)|
|0|GYRO_HPF_ORD_IND|0: 1storder HPF|
|||1: 2ndorder HPF|
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**XG_ST_DATA** Name: XG_ST_DATA Address: 95 (5Fh) Serial IF: R/W Reset value: 0xXX (The value in this register indicates the self-test output generated during manufacturing tests) Clock Domain: SCLK_UI **BIT NAME FUNCTION** ~~————~~ 7:0 XG_ST_DATA X-gyro self-test data **YG_ST_DATA** Name: YG_ST_DATA Address: 96 (60h) Serial IF: R/W Reset value: 0xXX (The value in this register indicates the self-test output generated during manufacturing tests) Clock Domain: SCLK_UI **BIT NAME FUNCTION** ~~———~~ 7:0 YG_ST_DATA Y-gyro self-test data
**ZG_ST_DATA** Name: ZG_ST_DATA Address: 97 (61h) Serial IF: R/W Reset value: 0xXX (The value in this register indicates the self-test output generated during manufacturing tests) Clock Domain: SCLK_UI **BIT NAME FUNCTION** ~~————~~ 7:0 ZG_ST_DATA Z-gyro self-test data **TMSTVAL0** Name: TMSTVAL0 Address: 98 (62h) Serial IF: R Reset value: 0x00 Clock Domain: SCLK_UI **BIT NAME FUNCTION** When TMST_STROBE is programmed, the current value of the internal 7:0 TMST_VALUE[7:0] counter is latched to this register. Allows the full 20-bit precision of the time ~~oe~~ stamp to be read back.
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## **TMSTVAL1**
|**TMSTVAL1**<br>15.15|**TMSTVAL1**<br>15.15|**TMSTVAL1**<br>15.15|
|---|---|---|
|Name: TMSTVAL1<br>Address: 99 (63h)<br>Serial IF: R<br>Reset value: 0x00<br>Clock Domain: SCLK_UI|||
|**BIT**|**NAME**|**FUNCTION**|
|7:0|TMST_VALUE[15:8]|When TMST_STROBE is programmed, the current value of the internal<br>counter is latched to this register. Allows the full 20-bit precision of the time<br>stampto be read back.|
## **TMSTVAL2**
|**TMSTVAL2**<br>15.16|**TMSTVAL2**<br>15.16|**TMSTVAL2**<br>15.16|
|---|---|---|
|Name: TMSTVAL2<br>Address: 100 (64h)<br>Serial IF: R<br>Reset value: 0x00<br>Clock Domain: SCLK_UI|||
|**BIT**|**NAME**|**FUNCTION**|
|7:4|-|Reserved|
|3:0|TMST_VALUE[19:16]|When TMST_STROBE is programmed, the current value of the internal<br>counter is latched to this register. Allows the full 20-bit precision of the time<br>stampto be read back.|
## **INTF_CONFIG4**
Name: INTF_CONFIG4 Address: 122 (7Ah) Serial IF: R/W Reset value: 0x03 Clock Domain: SCLK_UI
|**BIT**|**NAME**|**FUNCTION**|
|---|---|---|
|7|-|Reserved|
|6|I3C_BUS_MODE|0: Device is on a bus with I2C and I3CSMdevices<br>1: Device is on a bus with I3CSMdevices only|
|5:2|-|Reserved|
|1|SPI_AP_4WIRE|0: AP interface uses 3-wire SPI mode<br>1: AP interface uses 4-wire SPI mode(default)|
|0|-|Reserved|
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## **INTF_CONFIG5**
|**INTF_CONFIG5**|**INTF_CONFIG5**|**INTF_CONFIG5**|
|---|---|---|
|Name: INTF_CONFIG5<br>Address: 123 (7Bh)<br>Serial IF: R/W<br>Reset value: 0x20<br>Clock Domain: SCLK_UI|||
|**BIT**|**NAME**|**FUNCTION**|
|7:3|-|Reserved|
|2:1|PIN9_FUNCTION|Selects among the following functionalities for pin 9<br>00: INT2<br>01: FSYNC<br>10: CLKIN<br>11: Reserved|
|0|-|Reserved|
## **INTF_CONFIG6**
|**INTF_CONFIG6**|**INTF_CONFIG6**|**INTF_CONFIG6**|
|---|---|---|
|Name: INTF_CONFIG6<br>Address: 124 (7Ch)<br>Serial IF: R/W<br>Reset value: 0x5F<br>Clock Domain: SCLK_UI|||
|**BIT**|**NAME**|**FUNCTION**|
|7|ASYNCTIME0_DIS|0: I3CSMAsynchronous Mode 0 timing control is enabled<br>1: I3CSMAsynchronous Mode 0 timingcontrol is disabled|
|6:5|-|Reserved|
|4|I3C_EN|0: I3CSMslave not enabled<br>1: I3CSMslave enabled|
|3|I3C_IBI_BYTE_EN|0: I3CSMIBI payload function not enabled<br>1: I3CSMIBIpayload function enabled|
|2|I3C_IBI_EN|0: I3CSMIBI function not enabled<br>1: I3CSMIBI function enabled|
|1|I3C_DDR_EN|0: I3CSMDDR mode not enabled<br>1: I3CSMDDR mode enabled|
|0|I3C_SDR_EN|0: I3CSMSDR mode not enabled<br>1: I3CSMSDR mode enabled|
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## _**16 USER BANK 2 REGISTER MAP – DESCRIPTIONS**_
This section describes the function and contents of each register within USR Bank 2.
## **ACCEL_CONFIG_STATIC2**
|Name: ACCEL_CONFIG_STATIC2<br>Address: 03 (03h)<br>Serial IF: R/W<br>Reset value: 0x30<br>Clock Domain: SCLK_UI|Name: ACCEL_CONFIG_STATIC2<br>Address: 03 (03h)<br>Serial IF: R/W<br>Reset value: 0x30<br>Clock Domain: SCLK_UI|Name: ACCEL_CONFIG_STATIC2<br>Address: 03 (03h)<br>Serial IF: R/W<br>Reset value: 0x30<br>Clock Domain: SCLK_UI|
|---|---|---|
|**BIT**|**NAME**|**FUNCTION**|
|7|-|Reserved|
|6:1|ACCEL_AAF_DELT|Controls bandwidth of the accelerometer anti-alias filter<br>See section 5.2 for details|
|0|ACCEL_AAF_DIS|0: Enable accelerometer anti-aliasing filter<br>1: Disable accelerometer anti-aliasingfilter|
## **ACCEL_CONFIG_STATIC3**
|Name: ACCEL_CONFIG_STATIC3<br>Address: 04 (04h)<br>Serial IF: R/W<br>Reset value: 0x40<br>Clock Domain: SCLK_UI|Name: ACCEL_CONFIG_STATIC3<br>Address: 04 (04h)<br>Serial IF: R/W<br>Reset value: 0x40<br>Clock Domain: SCLK_UI|Name: ACCEL_CONFIG_STATIC3<br>Address: 04 (04h)<br>Serial IF: R/W<br>Reset value: 0x40<br>Clock Domain: SCLK_UI|
|---|---|---|
|**BIT**|**NAME**|**FUNCTION**|
|7:0|ACCEL_AAF_DELTSQR[7:0]|Controls bandwidth of the accelerometer anti-alias filter<br>See section 5.2 for details|
## **ACCEL_CONFIG_STATIC4**
|Name: ACCEL_CONFIG_STATIC4<br>Address: 05 (05h)<br>Serial IF: R/W<br>Reset value: 0x62<br>Clock Domain: SCLK_UI|Name: ACCEL_CONFIG_STATIC4<br>Address: 05 (05h)<br>Serial IF: R/W<br>Reset value: 0x62<br>Clock Domain: SCLK_UI|Name: ACCEL_CONFIG_STATIC4<br>Address: 05 (05h)<br>Serial IF: R/W<br>Reset value: 0x62<br>Clock Domain: SCLK_UI|
|---|---|---|
|**BIT**|**NAME**|**FUNCTION**|
|7:4|ACCEL_AAF_BITSHIFT|Controls bandwidth of the accelerometer anti-alias filter<br>See section 5.2 for details|
|3:0|ACCEL_AAF_DELTSQR[11:8]|Controls bandwidth of the accelerometer anti-alias filter<br>See section 5.2 for details|
## **XA_ST_DATA**
Name: XA_ST_DATA Address: 59 (3Bh) Serial IF: R/W Reset value: 0xXX (The value in this register indicates the self-test output generated during manufacturing tests) Clock Domain: SCLK_UI **BIT NAME FUNCTION** 7:0 XA_ST_DATA X-accel self-test data
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## **YA_ST_DATA**
Name: YA_ST_DATA Address: 60 (3Ch) Serial IF: R/W Reset value: 0xXX (The value in this register indicates the self-test output generated during manufacturing tests) Clock Domain: SCLK_UI **BIT NAME FUNCTION** 7:0 YA_ST_DATA Y-accel self-test data
## **ZA_ST_DATA**
Name: ZA_ST_DATA Address: 61 (3Dh) Serial IF: R/W Reset value: 0xXX (The value in this register indicates the self-test output generated during manufacturing tests) Clock Domain: SCLK_UI **BIT NAME FUNCTION** 7:0 ZA_ST_DATA Z-accel self-test data
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## _**17 USER BANK 3 REGISTER MAP – DESCRIPTIONS**_
This section describes the function and contents of each register within USR Bank 3.
## **PU_PD_CONFIG1**
|**PU_PD_CONFIG1**|**PU_PD_CONFIG1**|**PU_PD_CONFIG1**|
|---|---|---|
|Name: PU_PD_CONFIG1<br>Address: 06 (06h)<br>Serial IF: R/W<br>Reset value: 0x88<br>Clock Domain: SCLK_UI|||
|**BIT**|**NAME**|**FUNCTION**|
|7|PIN11_PU_EN|Pull-up control for pin 11<br>0: Pull-up is disabled<br>1: Pull-upis enabled|
|6|PIN7_PU_EN|Pull-up control for pin 7 if triple interface mode is used. Must be set to 0 if<br>single/dual interface mode is used.<br>0: Pull-up is disabled<br>1: Pull-upis enabled|
|5|-|Reserved|
|4|PIN9_PD_EN|Pull-down control for pin 9 in single/dual interface mode. Must be set to 0 if<br>triple interface mode is used.<br>0: Pull-down is disabled<br>1: Pull-down is enabled|
|3|PIN10_PU_EN|Pull-up control for pin 10<br>0: Pull-up is disabled<br>1: Pull-upis enabled|
|2|PIN3_PU_EN|Pull-up control for pin 3<br>0: Pull-up is disabled<br>1: Pull-upis enabled|
|1|PIN2_PU_EN|Pull-up control for pin 2<br>0: Pull-up is disabled<br>1: Pull-upis enabled|
|0|PIN4_PD_EN|Pull-down control for pin 4<br>0: Pull-down is disabled<br>1: Pull-down is enabled|
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## **PU_PD_CONFIG2**
|**PU_PD_CONFIG2**|**PU_PD_CONFIG2**|**PU_PD_CONFIG2**|
|---|---|---|
|Name: PU_PD_CONFIG2<br>Address: 14 (0Eh)<br>Serial IF: R/W<br>Reset value: 0x20<br>Clock Domain: SCLK_UI|||
|**BIT**|**NAME**|**FUNCTION**|
|7|PIN1_PU_EN|Pull-up control for pin 1. See bit 6 description for pull-down control for pin<br>1. Note that both pull-up and pull-down must not be simultaneously<br>enabled for the same pin.<br>0: Pull-up is disabled<br>1: Pull-upis enabled|
|6|PIN1_PD_EN|Pull-down control for pin 1. See bit 7 description for pull-up control for pin<br>1. Note that both pull-up and pull-down must not be simultaneously<br>enabled for the same pin.<br>0: Pull-down is disabled<br>1: Pull-down is enabled|
|5|PIN12_PU_EN|Pull-up control for pin 12. See bit 4 description for pull-down control for pin<br>12. Note that both pull-up and pull-down must not be simultaneously<br>enabled for the same pin.<br>0: Pull-up is disabled<br>1: Pull-upis enabled|
|4|PIN12_PD_EN|Pull-down control for pin 12. See bit 5 description for pull-up control for pin<br>12. Note that both pull-up and pull-down must not be simultaneously<br>enabled for the same pin.<br>0: Pull-down is disabled<br>1: Pull-down is enabled|
|3|PIN14_PU_EN|Pull-up control for pin 14. See bit 2 description for pull-down control for pin<br>14. Note that both pull-up and pull-down must not be simultaneously<br>enabled for the same pin.<br>0: Pull-up is disabled<br>1: Pull-upis enabled|
|2|PIN14_PD_EN|Pull-down control for pin 14. See bit 3 description for pull-up control for pin<br>14. Note that both pull-up and pull-down must not be simultaneously<br>enabled for the same pin.<br>0: Pull-down is disabled<br>1: Pull-down is enabled|
|1|PIN13_PU_EN|Pull-up control for pin 13. See bit 0 description for pull-down control for pin<br>13. Note that both pull-up and pull-down must not be simultaneously<br>enabled for the same pin.<br>0: Pull-up is disabled<br>1: Pull-upis enabled|
|0|PIN13_PD_EN|Pull-down control for pin 13. See bit 1 description for pull-up control for pin<br>13. Note that both pull-up and pull-down must not be simultaneously<br>enabled for the same pin.<br>0: Pull-down is disabled<br>1: Pull-down is enabled|
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## _**18 USER BANK 4 REGISTER MAP – DESCRIPTIONS**_
This section describes the function and contents of each register within USR Bank 4.
## **FDR_CONFIG**
|**FDR_CONFIG**|**FDR_CONFIG**|**FDR_CONFIG**|
|---|---|---|
|Name: FDR_CONFIG<br>Address: 09 (09h)<br>Serial IF: R/W<br>Reset value: 0x00<br>Clock Domain: SCLK_UI|||
|**BIT**|**NAME**|**FUNCTION**|
|7|-|Reserved|
|6:0|FDR_SEL|FIFO packet rate decimation factor. Sets the number of discarded FIFO<br>packets. Valid range is 0 to 127. User must disable sensors when initializing<br>FDR_SEL value or making changes to it.<br>0000000: Decimation is disabled, all packets are sent to FIFO<br>0000001: 1 packet out of 2 is sent to FIFO<br>0000010: 1 packet out of 3 is sent to FIFO<br>0000011: 1 packet out of 4 is sent to FIFO<br>…<br>1111111: 1packet out of 128 is sent to FIFO|
## **APEX_CONFIG1**
|Name: APEX_CONFIG1<br>Address: 64 (40h)<br>Serial IF: R/W<br>Reset value: 0xA2<br>Clock Domain: SCLK_UI|Name: APEX_CONFIG1<br>Address: 64 (40h)<br>Serial IF: R/W<br>Reset value: 0xA2<br>Clock Domain: SCLK_UI|Name: APEX_CONFIG1<br>Address: 64 (40h)<br>Serial IF: R/W<br>Reset value: 0xA2<br>Clock Domain: SCLK_UI|
|---|---|---|
|**BIT**|**NAME**|**FUNCTION**|
|7:4|LOW_ENERGY_AMP_TH_SEL|Pedometer Low Energy mode amplitude threshold selection<br>Use default value 1010b|
|3:0|DMP_POWER_SAVE_TIME_SEL|When the DMP is in power save mode, it is awakened by the WOM and<br>will wait for a certain duration before going back to sleep. This bitfield<br>configures this duration.<br>0000: 0 seconds<br>0001: 4 seconds<br>0010: 8 seconds<br>0011: 12 seconds<br>0100: 16 seconds<br>0101: 20 seconds<br>0110: 24 seconds<br>0111: 28 seconds<br>1000: 32 seconds<br>1001: 36 seconds<br>1010: 40 seconds<br>1011: 44 seconds<br>1100: 48 seconds<br>1101: 52 seconds<br>1110: 56 seconds<br>1111: 60 seconds|
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## **APEX_CONFIG2**
|**APEX_CONFIG2**|**APEX_CONFIG2**|**APEX_CONFIG2**|
|---|---|---|
|Name: APEX_CONFIG2<br>Address: 65 (41h)<br>Serial IF: R/W<br>Reset value: 0x85<br>Clock Domain: SCLK_UI|||
|**BIT**|**NAME**|**FUNCTION**|
|7:4|PED_AMP_TH_SEL|Pedometer amplitude threshold selection<br>Use default value 1000b|
|3:0|PED_STEP_CNT_TH_SEL|Pedometer step count detection window<br>Use default value 0101b<br>0000: 0 steps<br>0001: 1 step<br>0010: 2 steps<br>0011: 3 steps<br>0100: 4 steps<br>0101: 5 steps (default)<br>0110: 6 steps<br>0111: 7 steps<br>1000: 8 steps<br>1001: 9 steps<br>1010: 10 steps<br>1011: 11 steps<br>1100: 12 steps<br>1101: 13 steps<br>1110: 14 steps<br>1111: 15 steps|
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## **APEX_CONFIG3**
|**APEX_CONFIG3**|**APEX_CONFIG3**|**APEX_CONFIG3**|
|---|---|---|
|Name: APEX_CONFIG3<br>Address: 66 (42h)<br>Serial IF: R/W<br>Reset value: 0x51<br>Clock Domain: SCLK_UI|||
|**BIT**|**NAME**|**FUNCTION**|
|7:5|PED_STEP_DET_TH_SEL|Pedometer step detection threshold selection<br>Use default value 010b<br>000: 0 steps<br>001: 1 step<br>010: 2 steps (default)<br>011: 3 steps<br>100: 4 steps<br>101: 5 steps<br>110: 6 steps<br>111: 7 steps|
|4:2|PED_SB_TIMER_TH_SEL|Pedometer step buffer timer threshold selection<br>Use default value 100b<br>000: 0 samples<br>001: 1 sample<br>010: 2 samples<br>011: 3 samples<br>100: 4 samples (default)<br>101: 5 samples<br>110: 6 samples<br>111: 7 samples|
|1:0|PED_HI_EN_TH_SEL|Pedometer high energy threshold selection<br>Use default value 01b|
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## **APEX_CONFIG4**
|**APEX_CONFIG4**|**APEX_CONFIG4**|**APEX_CONFIG4**|
|---|---|---|
|Name: APEX_CONFIG4<br>Address: 67 (43h)<br>Serial IF: R/W<br>Reset value: 0xA4<br>Clock Domain: SCLK_UI|||
|**BIT**|**NAME**|**FUNCTION**|
|7:6|TILT_WAIT_TIME_SEL|Configures duration of delay after tilt is detected before interrupt is<br>triggered<br>00: 0s<br>01: 2s<br>10: 4s (default)<br>11: 6s|
|5:3|LOWG_PEAK_TH_HYST_SEL|This threshold is added to the LOWG peak threshold after the initial<br>threshold is met. The threshold values corresponding to parameter values<br>are shown below:<br>000: 31mgee<br>001: 63mgee<br>010: 94mgee<br>011: 125mgee<br>100: 156mgee (default)<br>101: 188mgee<br>110: 219mgee<br>111: 250mgee|
|2:0|HIGHG_PEAK_TH_HYST_SEL|This threshold is added to the HIGHG peak threshold after the initial<br>threshold is met. The threshold values corresponding to parameter values<br>are shown below:<br>000: 31mgee<br>001: 63mgee<br>010: 94mgee<br>011: 125mgee<br>100: 156mgee (default)<br>101: 188mgee<br>110: 219mgee<br>111: 250mgee|
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## **APEX_CONFIG5**
|**APEX_CONFIG5**|**APEX_CONFIG5**|**APEX_CONFIG5**|
|---|---|---|
|Name: APEX_CONFIG5<br>Address: 68 (44h)<br>Serial IF: R/W<br>Reset value: 0x8C<br>Clock Domain: SCLK_UI|||
|**BIT**|**NAME**|**FUNCTION**|
|7:3|LOWG_PEAK_TH_SEL|This parameter defines the threshold for accelerometer values below<br>which the algorithm considers it has entered low-g state. The threshold<br>values corresponding to parameter values are shown below:<br>00000: 31mgee<br>00001: 63mgee<br>00010: 94mgee<br>00011: 125mgee<br>00100: 156mgee<br>00101: 188mgee<br>00110: 219mgee<br>00111: 250mgee<br>01000: 281mgee<br>01001: 313mgee<br>01010: 344mgee<br>01011: 375mgee<br>01100: 406mgee<br>01101: 438mgee<br>01110: 469mgee<br>01111: 500mgee<br>10000: 531mgee<br>10001: 563mgee (default)<br>10010: 594mgee<br>10011: 625mgee<br>10100: 656mgee<br>10101: 688mgee<br>10110: 719mgee<br>10111: 750mgee<br>11000: 781mgee<br>11001: 813mgee<br>11010: 844mgee<br>11011: 875mgee<br>11100: 906mgee<br>11101: 938mgee<br>11110: 969mgee<br>11111: 1000mgee|
|2:0|LOWG_TIME_TH_SEL|This parameter defines the number of samples for which the device should<br>stay in low-g before triggering interrupt.<br>Number of samples = LOWG_TIME_TH_SEL + 1<br>Default value is 4(i.e. 5 samples)|
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## **APEX_CONFIG6**
|**APEX_CONFIG6**|**APEX_CONFIG6**|**APEX_CONFIG6**|
|---|---|---|
|Name: APEX_CONFIG6<br>Address: 69 (45h)<br>Serial IF: R/W<br>Reset value: 0x5C<br>Clock Domain: SCLK_UI|||
|**BIT**|**NAME**|**FUNCTION**|
|7:3|HIGHG_PEAK_TH_SEL|This parameter defines the threshold for accelerometer values above<br>which the algorithm considers it has entered high-g state. The threshold<br>values corresponding to parameter values are shown below:<br>00000: 250mgee<br>00001: 500mgee<br>00010: 750mgee<br>00011: 1000mgee<br>00100: 1250mgee<br>00101: 1500mgee<br>00110: 1750mgee<br>00111: 2000mgee<br>01000: 2250mgee<br>01001: 2500mgee<br>01010: 2750mgee<br>01011: 3000mgee<br>01100: 3250mgee<br>01101: 3500mgee<br>01110: 3750mgee<br>01111: 4000mgee<br>10000: 4250mgee<br>10001: 4500mgee<br>10010: 4750mgee<br>10011: 5000mgee<br>10100: 5250mgee<br>10101: 5500mgee<br>10110: 5750mgee<br>10111: 6000mgee<br>11000: 6250mgee<br>11001: 6500mgee<br>11010: 6750mgee<br>11011: 7000mgee<br>11100: 7250mgee<br>11101: 7500mgee<br>11110: 7750mgee<br>11111: 8000mgee|
|2:0|HIGHG_TIME_TH_SEL|This parameter defines the number of samples for which the device should<br>stay in high-g before triggering interrupt.<br>Number of samples = HIGHG_TIME_TH_SEL + 1<br>Default value is 4(i.e. 5 samples)|
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## **APEX_CONFIG7**
|**APEX_CONFIG7**|**APEX_CONFIG7**|**APEX_CONFIG7**|
|---|---|---|
|Name: APEX_CONFIG7<br>Address: 70 (46h)<br>Serial IF: R/W<br>Reset value: 0x45<br>Clock Domain: SCLK_UI|||
|**BIT**|**NAME**|**FUNCTION**|
|7:2|TAP_MIN_JERK_THR|Tap Detection minimum jerk threshold<br>Use default value 010001b|
|1:0|TAP_MAX_PEAK_TOL|Tap Detection maximum peak tolerance<br>Use default value 01b|
## **APEX_CONFIG8**
Name: APEX_CONFIG8 Address: 71 (47h) Serial IF: R/W Reset value: 0x5B Clock Domain: SCLK_UI
|**BIT**|**NAME**|**FUNCTION**|
|---|---|---|
|7|-|Reserved|
|6:5|TAP_TMAX|Tap measurement window (number of samples)<br>Use default value 10b|
|4:3|TAP_TAVG|Tap energy measurement window (number of samples)<br>Use default value 11b|
|2:0|TAP_TMIN|Single tap window (number of samples)<br>Use default value 011b|
## **APEX_CONFIG9**
Name: APEX_CONFIG9 Address: 72 (48h) Serial IF: R/W Reset value: 0x00 Clock Domain: SCLK_UI
|**BIT**|**NAME**|**FUNCTION**|
|---|---|---|
|7:1|-|Reserved|
|||0: Low power mode at accelerometer ODR 25 Hz; High performance mode|
|0|SENSITIVITY_MODE|at accelerometer ODR ≥ 50 Hz<br>1: Low power and slow walk mode at accelerometer ODR 25 Hz; Slow walk|
|||mode at accelerometer ODR ≥ 50 Hz|
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## **APEX_CONFIG10**
|Name: APEX_CONFIG10<br>Address: 73 (49h)<br>Serial IF: R/W<br>Reset value: 0x00<br>Clock Domain: SCLK_UI|Name: APEX_CONFIG10<br>Address: 73 (49h)<br>Serial IF: R/W<br>Reset value: 0x00<br>Clock Domain: SCLK_UI|Name: APEX_CONFIG10<br>Address: 73 (49h)<br>Serial IF: R/W<br>Reset value: 0x00<br>Clock Domain: SCLK_UI|
|---|---|---|
|**BIT**|**NAME**|**FUNCTION**|
|7:5|FF_MIN_DURATION_CM|This parameter defines the minimum freefall length that the algorithm<br>should report. Freefalls smaller than this value are ignored. Freefall lengths<br>corresponding to parameter values are shown below:<br>000: 13cm (default)<br>001: 19cm<br>010: 28cm<br>011: 38cm<br>100: 50cm<br>101: 64cm<br>110: 78cm<br>111: 95cm|
|4:2|FF_MAX_DURATION_CM|This parameter defines the maximum freefall length that the algorithm<br>should report. Freefalls longer than this value are ignored. Freefall lengths<br>corresponding to parameter values are shown below:<br>000: 113cm (default)<br>001: 154cm<br>010: 201cm<br>011: 255cm<br>100: 314cm<br>101: 380cm<br>110: 452cm<br>111: 531cm|
|1:0|FF_DEBOUNCE_DURATION|This parameter defines the time during which low-g and high-g events are<br>not taken into account after a high-g event. It helps to avoid detecting<br>bounces as free fall. Debounce durations corresponding to parameter<br>values are shown below:<br>00: 0s<br>01: 1s<br>10: 2s<br>11: 3s|
## **ACCEL_WOM_X_THR**
|Name: ACCEL_WOM_X_THR<br>Address: 74 (4Ah)<br>Serial IF: R/W<br>Reset value: 0x00<br>Clock Domain: SCLK_UI|Name: ACCEL_WOM_X_THR<br>Address: 74 (4Ah)<br>Serial IF: R/W<br>Reset value: 0x00<br>Clock Domain: SCLK_UI|Name: ACCEL_WOM_X_THR<br>Address: 74 (4Ah)<br>Serial IF: R/W<br>Reset value: 0x00<br>Clock Domain: SCLK_UI|
|---|---|---|
|**BIT**|**NAME**|**FUNCTION**|
|7:0|WOM_X_TH|Threshold value for the Wake on Motion Interrupt for X-axis accelerometer<br>WoM thresholds are expressed in fixed “mg” independent of the selected<br>Range[0g: 1g];Resolution 1g/256=~3.9mg|
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## **ACCEL_WOM_Y_THR**
|**ACCEL_WOM_Y_THR**<br>18.13|**ACCEL_WOM_Y_THR**<br>18.13|**ACCEL_WOM_Y_THR**<br>18.13|
|---|---|---|
|Name: ACCEL_WOM_Y_THR<br>Address: 75 (4Bh)<br>Serial IF: R/W<br>Reset value: 0x00<br>Clock Domain: SCLK_UI|||
|**BIT**|**NAME**|**FUNCTION**|
|7:0|WOM_Y_TH|Threshold value for the Wake on Motion Interrupt for Y-axis accelerometer<br>WoM thresholds are expressed in fixed “mg” independent of the selected<br>Range[0g: 1g];Resolution 1g/256=~3.9mg|
## **ACCEL_WOM_Z_THR**
|**ACCEL_WOM_Z_THR**<br>18.14|**ACCEL_WOM_Z_THR**<br>18.14|**ACCEL_WOM_Z_THR**<br>18.14|
|---|---|---|
|Name: ACCEL_WOM_Z_THR<br>Address: 76 (4Ch)<br>Serial IF: R/W<br>Reset value: 0x00<br>Clock Domain: SCLK_UI|||
|**BIT**|**NAME**|**FUNCTION**|
|7:0|WOM_Z_TH|Threshold value for the Wake on Motion Interrupt for Z-axis accelerometer<br>WoM thresholds are expressed in fixed “mg” independent of the selected<br>Range[0g: 1g];Resolution 1g/256=~3.9mg|
## **INT_SOURCE6**
Name: INT_SOURCE6 Address: 77 (4Dh) Serial IF: R/W Reset value: 0x00 Clock Domain: SCLK_UI
|**BIT**|**NAME**|**FUNCTION**|
|---|---|---|
|7:6|-|Reserved|
|5|STEP_DET_INT1_EN|0: Step detect interrupt not routed to INT1<br>1: Stepdetect interrupt routed to INT1|
|4|STEP_CNT_OFL_INT1_EN|0: Step count overflow interrupt not routed to INT1<br>1: Stepcount overflow interrupt routed to INT1|
|3|TILT_DET_INT1_EN|0: Tilt detect interrupt not routed to INT1<br>1: Tile detect interrupt routed to INT1|
|2|-|Reserved|
|1|FREEFALL_DET_INT1_EN|0: Freefall detect interrupt not routed to INT1<br>1: Freefall detect interrupt routed to INT1|
|0|TAP_DET_INT1_EN|0: Tap detect interrupt not routed to INT1<br>1: Tapdetect interrupt routed to INT1|
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## **INT_SOURCE7**
Name: INT_SOURCE7 Address: 78 (4Eh) Serial IF: R/W Reset value: 0x00 Clock Domain: SCLK_UI
|**BIT**|**NAME**|**FUNCTION**|
|---|---|---|
|7:6|-|Reserved|
|5|STEP_DET_INT2_EN|0: Step detect interrupt not routed to INT2<br>1: Stepdetect interrupt routed to INT2|
|4|STEP_CNT_OFL_INT2_EN|0: Step count overflow interrupt not routed to INT2<br>1: Stepcount overflow interrupt routed to INT2|
|3|TILT_DET_INT2_EN|0: Tilt detect interrupt not routed to INT2<br>1: Tile detect interrupt routed to INT2|
|2|-|Reserved|
|1|FREEFALL_DET_INT2_EN|0: Freefall detect interrupt not routed to INT2<br>1: Freefall detect interrupt routed to INT2|
|0|TAP_DET_INT2_EN|0: Tap detect interrupt not routed to INT2<br>1: Tapdetect interrupt routed to INT2|
## **INT_SOURCE8**
Name: INT_SOURCE8 Address: 79 (4Fh) Serial IF: R/W Reset value: 0x00 Clock Domain: SCLK_UI
|**BIT**|**NAME**|**FUNCTION**|
|---|---|---|
|7:6|-|Reserved|
|5|FSYNC_IBI_EN|0: FSYNC interrupt not routed to IBI<br>1: FSYNC interrupt routed to IBI|
|4|PLL_RDY_IBI_EN|0: PLL ready interrupt not routed to IBI<br>1: PLL readyinterrupt routed to IBI|
|3|UI_DRDY_IBI_EN|0: UI data ready interrupt not routed to IBI<br>1: UI data readyinterrupt routed to IBI|
|2|FIFO_THS_IBI_EN|0: FIFO threshold interrupt not routed to IBI<br>1: FIFO threshold interrupt routed to IBI|
|1|FIFO_FULL_IBI_EN|0: FIFO full interrupt not routed to IBI<br>1: FIFO full interrupt routed to IBI|
|0|AGC_RDY_IBI_EN|0: AGC ready interrupt not routed to IBI<br>1: AGC readyinterrupt routed to IBI|
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## **INT_SOURCE9**
Name: INT_SOURCE9 Address: 80 (50h) Serial IF: R/W Reset value: 0x00 Clock Domain: SCLK_UI
|**BIT**|**NAME**|**FUNCTION**|
|---|---|---|
|7|I3C_PROTOCOL_ERROR_IBI<br>_EN|0: I3CSMprotocol error interrupt not routed to IBI<br>1: I3CSM protocol error interrupt routed to IBI|
|6:5|-|Reserved|
|4|SMD_IBI_EN|0: SMD interrupt not routed to IBI<br>1: SMD interrupt routed to IBI|
|3|WOM_Z_IBI_EN|0: Z-axis WOM interrupt not routed to IBI<br>1: Z-axis WOM interrupt routed to IBI|
|2|WOM_Y_IBI_EN|0: Y-axis WOM interrupt not routed to IBI<br>1: Y-axis WOM interrupt routed to IBI|
|1|WOM_X_IBI_EN|0: X-axis WOM interrupt not routed to IBI<br>1: X-axis WOM interrupt routed to IBI|
|0|-|Reserved|
## **INT_SOURCE10**
Name: INT_SOURCE10 Address: 81 (51h) Serial IF: R/W Reset value: 0x00 Clock Domain: SCLK_UI
|**BIT**|**NAME**|**FUNCTION**|
|---|---|---|
|7:6|-|Reserved|
|5|STEP_DET_IBI_EN|0: Step detect interrupt not routed to IBI<br>1: Stepdetect interrupt routed to IBI|
|4|STEP_CNT_OFL_IBI_EN|0: Step count overflow interrupt not routed to IBI<br>1: Stepcount overflow interrupt routed to IBI|
|3|TILT_DET_IBI_EN|0: Tilt detect interrupt not routed to IBI<br>1: Tile detect interrupt routed to IBI|
|2|-|Reserved|
|1|FREEFALL_DET_IBI_EN|0: Freefall detect interrupt not routed to IBI<br>1: Freefall detect interrupt routed to IBI|
|0|TAP_DET_IBI_EN|0: Tap detect interrupt not routed to IBI<br>1: Tapdetect interrupt routed to IBI|
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**OFFSET_USER0**
Name: OFFSET_USER0 Address: 119 (77h) Serial IF: R/W Reset value: 0x00 Clock Domain: SCLK_UI **BIT NAME FUNCTION** Lower bits of X-gyro offset programmed by user. Max value is ±64 dps, 7:0 GYRO_X_OFFUSER[7:0] resolution is 1/32 dps. ~~—$—_~~ 18.21 **OFFSET_USER1** Name: OFFSET_USER1 Address: 120 (78h) Serial IF: R/W Reset value: 0x00 Clock Domain: SCLK_UI **BIT NAME FUNCTION** Upper bits of Y-gyro offset programmed by user. Max value is ±64 dps, 7:4 GYRO_Y_OFFUSER[11:8] resolution is 1/32 dps. Upper bits of X-gyro offset programmed by user. Max value is ±64 dps, 3:0 GYRO_X_OFFUSER[11:8] resolution is 1/32 dps. ~~ne~~ 18.22 **OFFSET_USER2** Name: OFFSET_USER2 Address: 121 (79h) Serial IF: R/W Reset value: 0x00 Clock Domain: SCLK_UI **BIT NAME FUNCTION** Lower bits of Y-gyro offset programmed by user. Max value is ±64 dps, 7:0 GYRO_Y_OFFUSER[7:0] ~~—~~ resolution is 1/32 dps. 18.23 **OFFSET_USER3** Name: OFFSET_USER3 Address: 122 (7Ah) Serial IF: R/W Reset value: 0x00 Clock Domain: SCLK_UI **BIT NAME FUNCTION** Lower bits of Z-gyro offset programmed by user. Max value is ±64 dps, 7:0 GYRO_Z_OFFUSER[7:0] resolution is 1/32 dps. ~~——~~ Page 114 of 120 Document Number: DS-000401 Revision: 1.3
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**OFFSET_USER4**
Name: OFFSET_USER4 Address: 123 (7Bh) Serial IF: R/W Reset value: 0x00 Clock Domain: SCLK_UI **BIT NAME FUNCTION** Upper bits of X-accel offset programmed by user. Max value is ±1g, 7:4 ACCEL_X_OFFUSER[11:8] resolution is 0.5 mg. Upper bits of Z-gyro offset programmed by user. Max value is ±64 dps, 3:0 GYRO_Z_OFFUSER[11:8] resolution is 1/32 dps. ~~ne~~ 18.25 **OFFSET_USER5** Name: OFFSET_USER5 Address: 124 (7Ch) Serial IF: R/W Reset value: 0x00 Clock Domain: SCLK_UI **BIT NAME FUNCTION** Lower bits of X-accel offset programmed by user. Max value is ±1g, 7:0 ACCEL_X_OFFUSER[7:0] ~~—~~ resolution is 0.5mg. 18.26 **OFFSET_USER6** Name: OFFSET_USER6 Address: 125 (7Dh) Serial IF: R/W Reset value: 0x00 Clock Domain: SCLK_UI **BIT NAME FUNCTION** Lower bits of Y-accel offset programmed by user. Max value is ±1g, 7:0 ACCEL_Y_OFFUSER[7:0] ~~—~~ resolution is 0.5mg. 18.27 **OFFSET_USER7** Name: OFFSET_USER7 Address: 126 (7Eh) Serial IF: R/W Reset value: 0x00 Clock Domain: SCLK_UI **BIT NAME FUNCTION** Upper bits of Z-accel offset programmed by user. Max value is ±1g, 7:4 ACCEL_Z_OFFUSER[11:8] resolution is 0.5mg. Upper bits of Y-accel offset programmed by user. Max value is ±1g, 3:0 ACCEL_Y_OFFUSER[11:8] resolution is 0.5mg. ~~re~~
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## **OFFSET_USER8**
|**OFFSET_USER8**|**OFFSET_USER8**|**OFFSET_USER8**|
|---|---|---|
|Name: OFFSET_USER8<br>Address: 127 (7Fh)<br>Serial IF: R/W<br>Reset value: 0x00<br>Clock Domain: SCLK_UI|||
|**BIT**|**NAME**|**FUNCTION**|
|7:0|ACCEL_Z_OFFUSER[7:0]|Lower bits of Z-accel offset programmed by user. Max value is ±1g,<br>resolution is 0.5 mg.|
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## _**19 REFERENCE**_
Please refer to “InvenSense MEMS Handling Application Note (AN-IVS-0002A-00)” for the following information:
- Manufacturing Recommendations
- Assembly Guidelines and Recommendations
- PCB Design Guidelines and Recommendations
- MEMS Handling Instructions
- ESD Considerations
- Reflow Specification
- Storage Specifications
- Package Marking Specification
- Tape & Reel Specification
- Reel & Pizza Box Label
- Packaging
- Representative Shipping Carton Label
- Compliance
- Environmental Compliance
- DRC Compliance
- Compliance Declaration Disclaimer
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## _**20 SMARTINDUSTRIAL FAMILY**_
TDK’s SmartIndustrial™ portfolio of 6-axis IMU and 3-axis Accelerometer products delivers the precise motion, vibration and inclination measurements that industrial applications need. These products offer the ability to take precise measurements in harsh environments with vibration and wide temperature variations.
TDK’s broad portfolio of Industrial Motion Sensing solutions offers customers a range of performance and cost choices, enabling a wide variety of Industrial navigation, stabilization, and monitoring applications.
By combining its innovative MEMS Motion Sensor technologies with its expertise of Industrial applications, TDK offers unique capabilities such as Fault-tolerant motion sensing solution.
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## _**21 REVISION HISTORY**_
|**REVISION DATE**|**REVISION**|**DESCRIPTION**|
|---|---|---|
|01/07/2021|1.0|Initial release|
|07/27/2021|1.1|Updated anti-aliasing filter reference in Chapter 15.3, 15.4 and 15.5 from Chapter<br>5.2 to Chapter 5.3.<br>Chapter 15.1 reset Value 0xB0 changed to 0x80<br>Remove the FIFO_WM_EN reference on sections 14.46 & 14.47<br>Updated section 12.7 “FIFO Timestamp Interval Scaling”<br>Added section 12.9 on register value modification<br>Updated bit 3 description on Section 14.4|
|10/01/2021|1.2|Updated Sections 14.43, 17.1, 17.2<br>Updated SmartIndustrial formatting|
|02/14/2022|1.3|Updated Section 9.4<br>Added longevity information|
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https://invensense.tdk.com/longevity/
This information furnished by InvenSense or its affiliates (“TDK InvenSense”) is believed to be accurate and reliable. However, no responsibility is assumed by TDK InvenSense for its use, or for any infringements of patents or other rights of third parties that may result from its use. Specifications are subject to change without notice. TDK InvenSense reserves the right to make changes to this product, including its circuits and software, in order to improve its design and/or performance, without prior notice. TDK InvenSense makes no warranties, neither expressed nor implied, regarding the information and specifications contained in this document. TDK InvenSense assumes no responsibility for any claims or damages arising from information contained in this document, or from the use of products and services detailed therein. This includes, but is not limited to, claims or damages based on the infringement of patents, copyrights, mask work and/or other intellectual property rights.
Certain intellectual property owned by InvenSense and described in this document is patent protected. No license is granted by implication or otherwise under any patent or patent rights of InvenSense. This publication supersedes and replaces all information previously supplied. Trademarks that are registered trademarks are the property of their respective companies. TDK InvenSense sensors should not be used or sold in the development, storage, production or utilization of any conventional or mass-destructive weapons or for any other weapons or life threatening applications, as well as in any other life critical applications such as medical equipment, transportation, aerospace and nuclear instruments, undersea equipment, power plant equipment, disaster prevention and crime prevention equipment.
©2021—2022 InvenSense. All rights reserved. InvenSense, MotionTracking, MotionProcessing, MotionProcessor, MotionFusion, MotionApps, DMP, AAR, and the InvenSense logo are trademarks of InvenSense, Inc. The TDK logo is a trademark of TDK Corporation. Other cocmpany and product names may be trademarks of the respective companies with which they are associated.
©2021—2022 InvenSense. All rights reserved.
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Updated at April 17, 2026
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