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ICM-42670-P
MEMS Module, 1.71 V, 3.6 V, LGA, 14 Pins
⚠️ Reference pricing provided. In case of supply shortages, we will connect you with our trusted procurement partners to ensure your project's continuity.
- Manufacturer: TDK INVENSENSE
- Product type: MEMS Modules
- MSL: MSL 1 - Unlimited
- SVHC: No SVHC (25-Jun-2025)
- No. of Pins: 14Pins
- Product Range: -
- Sensor Case Style: LGA
- Supply Voltage Max: 3.6V
- Supply Voltage Min: 1.71V
- MEMS Module Function: Tri-Axis Gyroscope, Tri-Axis Accelerometer
- Sensor Case / Package: LGA
- Sensing Range - Gyroscope: ± 250°/s, ± 500°/s, ± 1000°/s, ± 2000°/s
- Sensing Range - Accelerometer: ± 2g, ± 4g, ± 8g, ± 16g
| Delivery and price | |
|---|---|
| Units per pack | 1000 |
| Price | 1.71 € |
| Current stock | 10+ |
| Lead time | 30 days |
Datasheet
## _**ICM-42670-P Datasheet**_
## High Performance 6-Axis MotionTracking[TM] IMU
## **ICM-42670-P HIGHLIGHTS**
## **ICM-42670-P FEATURES**
The ICM-42670-P is a high performance 6-axis MEMS MotionTracking device that combines a 3-axis gyroscope and a 3-axis accelerometer. It has a configurable host interface that supports I3C[SM] , I[2] C, and SPI serial communication, features up to 2.25 Kbytes FIFO and 2 programmable interrupts with ultra-lowpower wake-on-motion support to minimize system power consumption.
The ICM-42670-P supports the lowest gyro and accel sensor noise in this IMU class, and has the highest stability against temperature, shock (up to 20,000g) or SMT/bend induced offset as well as immunity against out-of-band vibration induced noise.
Other industry-leading features include on-chip APEX Motion Processing engine for gesture recognition, and pedometer, along with programmable digital filters, and an embedded temperature sensor.
The device supports a VDD operating range of 1.71V to 3.6V, and a separate VDDIO operating range from 1.71V to 3.6V.
- Low-Noise mode 6-axis current consumption of 0.55 mA
- Low-Power mode support for always-on experience
- Sleep Mode Current Consumption: 3.5µA
- User selectable Gyro Full-scale range (dps): ± 250/500/1000/2000
- User selectable Accelerometer Full-scale range (g): ± 2/4/8/16
- User-programmable digital filters for gyro, accel, and temp sensor
- APEX Motion Functions: Pedometer, Tilt Detection, Low-g Detection, Freefall Detection, Wake on Motion, Significant Motion Detection
- Host interface: 12.5 MHz I3C[SM] , 1 MHz I[2] C, 24 MHz SPI
## **APPLICATIONS**
- Wearables (Fitness Bands, SmartWatches, Healthcare wearables)
- Hearables (True Wireless Headsets)
- Gaming Controllers
- Smart Home Appliances
- Smart TV remotes
- Drones
- Robotics
- Augmented Reality/Virtual Reality
## **BLOCK DIAGRAM**
## **ORDERING INFORMATION**
|**PART**|**TEMP RANGE**|**PACKAGE**|
|---|---|---|
|ICM-42670-P†|−40°C to +85°C|2.5x3mm 14-Pin<br>LGA|
†Denotes RoHS and Green-Compliant Package
InvenSense Inc. reserves the right to change specifications and information herein without notice unless the product is in mass production and the datasheet has been designated by InvenSense in writing as subject to a specified Product / Process Change Notification Method regulation.
Document Number: DS-000451 Revision: 1.0 Rev. Date: 04/15/2021
**InvenSense, a TDK Group Company** 1745 Technology Drive, San Jose, CA 95110 U.S.A +1(408) 988–7339 invensense.tdk.com
_**ICM-42670-P**_
## **TABLE OF CONTENTS**
|**TABLE OF CONTENTS**|**TABLE OF CONTENTS**|
|---|---|
|ICM-42670-P Highlights ...................................................................................................................................... 1||
|Block Diagram ..................................................................................................................................................... 1|Block Diagram ..................................................................................................................................................... 1|
|ICM-42670-P Features ........................................................................................................................................ 1||
|Applications ........................................................................................................................................................ 1||
|Ordering Information ......................................................................................................................................... 1||
|Introduction ........................................................................................................................................................ 8||
|1.1|Purpose and Scope .................................................................................................................................. 8|
|1.2|Product Overview .................................................................................................................................... 8|
|1.3|Applications ............................................................................................................................................. 8|
|Features .............................................................................................................................................................. 9||
|2.1|Gyroscope Features ................................................................................................................................. 9|
|2.2|Accelerometer Features .......................................................................................................................... 9|
|2.3|Motion Features ...................................................................................................................................... 9|
|2.4|Additional Features .................................................................................................................................. 9|
|Electrical Characteristics ................................................................................................................................... 10||
|3.1|Gyroscope Specifications ....................................................................................................................... 10|
|3.2|Accelerometer Specifications ................................................................................................................ 11|
|3.3|Electrical Specifications ......................................................................................................................... 12|
|3.4|I2C Timing Characterization ................................................................................................................... 14|
|3.5|SPI Timing Characterization – 4-Wire SPI Mode .................................................................................... 15|
|3.6|SPI Timing Characterization – 3-Wire SPI Mode .................................................................................... 16|
|3.7|Absolute Maximum Ratings ................................................................................................................... 17|
|Applications Information .................................................................................................................................. 18||
|4.1|Pin Out Diagram and Signal Description ................................................................................................ 18|
|4.2|Typical Operating Circuit ........................................................................................................................ 19|
|4.3|Bill of Materials for External Components ............................................................................................. 20|
|4.4|System Block Diagram ........................................................................................................................... 20|
|4.5|Overview ................................................................................................................................................ 20|
|4.6|Three-Axis MEMS Gyroscope ................................................................................................................. 20|
|4.7|Three-Axis MEMS Accelerometer .......................................................................................................... 20|
|4.8|I3CSM, I2C and SPI Host Interface ............................................................................................................ 21|
|4.9|Self-Test ................................................................................................................................................. 21|
|4.10|Sensor Data Registers ........................................................................................................................ 21|
|4.11|Interrupts ........................................................................................................................................... 21|
|4.12|Digital-Output Temperature Sensor .................................................................................................. 21|
|4.13|Bias and LDOs .................................................................................................................................... 21|
|4.14|Charge Pump ..................................................................................................................................... 21|
|4.15|Standard Power Modes ..................................................................................................................... 22|
|Signal Path ........................................................................................................................................................ 23|Signal Path ........................................................................................................................................................ 23|
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_**ICM-42670-P**_
|FIFO ................................................................................................................................................................... 24|FIFO ................................................................................................................................................................... 24|
|---|---|
|6.1|Packet Structure .................................................................................................................................... 24|
|6.2|FIFO Header ........................................................................................................................................... 26|
|6.3|Maximum FIFO Storage ......................................................................................................................... 27|
|Programmable Interrupts ................................................................................................................................. 28||
|APEX Motion Functions .................................................................................................................................... 29||
|Digital Interface ................................................................................................................................................ 30||
|9.1|I3CSM, I2C and SPI Serial Interfaces ......................................................................................................... 30|
|9.2|I3CSMInterface ....................................................................................................................................... 30|
|9.3|I2C Interface ........................................................................................................................................... 32|
|9.4|I2C Communications Protocol ................................................................................................................ 32|
|9.5|I2C Terms ................................................................................................................................................ 34|
|9.6|SPI Interface ........................................................................................................................................... 35|
|Assembly........................................................................................................................................................... 36||
|10.1|Orientation of Axes ........................................................................................................................... 36|
|10.2|Package Dimensions .......................................................................................................................... 37|
|Part Number Package Marking ......................................................................................................................... 38||
|Use Notes ......................................................................................................................................................... 39||
|12.1|Gyroscope Power On to Power Off Transition .................................................................................. 39|
|Accessing MREG1, MREG2 And MREG3 Registers ............................................................................................ 40||
|Register Map .................................................................................................................................................... 41||
|14.1|User Bank 0 Register Map ................................................................................................................. 41|
|14.2|User Bank MREG1 Register Map ....................................................................................................... 42|
|14.3|User Bank MREG2 Register Map ....................................................................................................... 43|
|14.4|User Bank MREG3 Register Map ....................................................................................................... 43|
|User Bank 0 Register Map – Descriptions......................................................................................................... 45||
|15.1|MCLK_RDY ......................................................................................................................................... 45|
|15.2|DEVICE_CONFIG ................................................................................................................................ 45|
|15.3|SIGNAL_PATH_RESET ........................................................................................................................ 46|
|15.4|DRIVE_CONFIG1 ................................................................................................................................ 47|
|15.5|DRIVE_CONFIG2 ................................................................................................................................ 48|
|15.6|DRIVE_CONFIG3 ................................................................................................................................ 49|
|15.7|INT_CONFIG ....................................................................................................................................... 50|
|15.8|TEMP_DATA1 .................................................................................................................................... 50|
|15.9|TEMP_DATA0 .................................................................................................................................... 51|
|15.10|ACCEL_DATA_X1 ................................................................................................................................ 51|
|15.11|ACCEL_DATA_X0 ................................................................................................................................ 51|
|15.12|ACCEL_DATA_Y1 ................................................................................................................................ 51|
|15.13|ACCEL_DATA_Y0 ................................................................................................................................ 52|
|15.14|ACCEL_DATA_Z1 ................................................................................................................................ 52|
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ACCEL_DATA_Z0 ................................................................................................................................ 52 GYRO_DATA_X1 ................................................................................................................................. 52 GYRO_DATA_X0 ................................................................................................................................. 52 GYRO_DATA_Y1 ................................................................................................................................. 53 GYRO_DATA_Y0 ................................................................................................................................. 53 GYRO_DATA_Z1 ................................................................................................................................. 53 GYRO_DATA_Z0 ................................................................................................................................. 53 TMST_FSYNCH ................................................................................................................................... 53 TMST_FSYNCL .................................................................................................................................... 54 APEX_DATA4 ..................................................................................................................................... 54 APEX_DATA5 ..................................................................................................................................... 54 PWR_MGMT0 .................................................................................................................................... 55 GYRO_CONFIG0 ................................................................................................................................. 56 ACCEL_CONFIG0 ................................................................................................................................ 57 TEMP_CONFIG0 ................................................................................................................................. 58 GYRO_CONFIG1 ................................................................................................................................. 58 ACCEL_CONFIG1 ................................................................................................................................ 59 APEX_CONFIG0 .................................................................................................................................. 59 APEX_CONFIG1 .................................................................................................................................. 60 WOM_CONFIG ................................................................................................................................... 61 FIFO_CONFIG1 ................................................................................................................................... 61 FIFO_CONFIG2 ................................................................................................................................... 62 FIFO_CONFIG3 ................................................................................................................................... 62 INT_SOURCE0 .................................................................................................................................... 63 INT_SOURCE1 .................................................................................................................................... 63 INT_SOURCE3 .................................................................................................................................... 64 INT_SOURCE4 .................................................................................................................................... 64 FIFO_LOST_PKT0 ............................................................................................................................... 65 FIFO_LOST_PKT1 ............................................................................................................................... 65 APEX_DATA0 ..................................................................................................................................... 65 APEX_DATA1 ..................................................................................................................................... 65 APEX_DATA2 ..................................................................................................................................... 65 APEX_DATA3 ..................................................................................................................................... 66 INTF_CONFIG0 ................................................................................................................................... 66 INTF_CONFIG1 ................................................................................................................................... 67 INT_STATUS_DRDY ............................................................................................................................ 67 INT_STATUS ....................................................................................................................................... 68 INT_STATUS2 ..................................................................................................................................... 68 INT_STATUS3 ..................................................................................................................................... 68 FIFO_COUNTH ................................................................................................................................... 69
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_**ICM-42670-P**_
|15.55|FIFO_COUNTL .................................................................................................................................... 69|
|---|---|
|15.56|FIFO_DATA......................................................................................................................................... 69|
|15.57|WHO_AM_I ....................................................................................................................................... 69|
|15.58|BLK_SEL_W ........................................................................................................................................ 70|
|15.59|MADDR_W......................................................................................................................................... 70|
|15.60|M_W .................................................................................................................................................. 70|
|15.61|BLK_SEL_R ......................................................................................................................................... 70|
|15.62|MADDR_R .......................................................................................................................................... 71|
|15.63|M_R ................................................................................................................................................... 71|
|User Bank MREG1 Register Map – Descriptions ............................................................................................... 72||
|16.1|TMST_CONFIG1 ................................................................................................................................. 72|
|16.2|FIFO_CONFIG5 ................................................................................................................................... 73|
|16.3|FIFO_CONFIG6 ................................................................................................................................... 74|
|16.4|FSYNC_CONFIG .................................................................................................................................. 75|
|16.5|INT_CONFIG0 ..................................................................................................................................... 75|
|16.6|INT_CONFIG1 ..................................................................................................................................... 76|
|16.7|SENSOR_CONFIG3 ............................................................................................................................. 76|
|16.8|ST_CONFIG ........................................................................................................................................ 77|
|16.9|SELFTEST ............................................................................................................................................ 78|
|16.10|INTF_CONFIG6 ................................................................................................................................... 78|
|16.11|INTF_CONFIG10 ................................................................................................................................. 78|
|16.12|INTF_CONFIG7 ................................................................................................................................... 79|
|16.13|OTP_CONFIG...................................................................................................................................... 79|
|16.14|INT_SOURCE6 .................................................................................................................................... 80|
|16.15|INT_SOURCE7 .................................................................................................................................... 80|
|16.16|INT_SOURCE8 .................................................................................................................................... 81|
|16.17|INT_SOURCE9 .................................................................................................................................... 81|
|16.18|INT_SOURCE10 .................................................................................................................................. 82|
|16.19|APEX_CONFIG2 .................................................................................................................................. 83|
|16.20|APEX_CONFIG3 .................................................................................................................................. 84|
|16.21|APEX_CONFIG4 .................................................................................................................................. 85|
|16.22|APEX_CONFIG5 .................................................................................................................................. 86|
|16.23|APEX_CONFIG9 .................................................................................................................................. 87|
|16.24|APEX_CONFIG10 ................................................................................................................................ 88|
|16.25|APEX_CONFIG11 ................................................................................................................................ 89|
|16.26|ACCEL_WOM_X_THR......................................................................................................................... 90|
|16.27|ACCEL_WOM_Y_THR ......................................................................................................................... 90|
|16.28|ACCEL_WOM_Z_THR ......................................................................................................................... 90|
|16.29|OFFSET_USER0 .................................................................................................................................. 90|
|16.30|OFFSET_USER1 .................................................................................................................................. 91|
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|16.31|OFFSET_USER2 .................................................................................................................................. 91|
|---|---|
|16.32|OFFSET_USER3 .................................................................................................................................. 91|
|16.33|OFFSET_USER4 .................................................................................................................................. 91|
|16.34|OFFSET_USER5 .................................................................................................................................. 92|
|16.35|OFFSET_USER6 .................................................................................................................................. 92|
|16.36|OFFSET_USER7 .................................................................................................................................. 92|
|16.37|OFFSET_USER8 .................................................................................................................................. 92|
|16.38|ST_STATUS1 ....................................................................................................................................... 93|
|16.39|ST_STATUS2 ....................................................................................................................................... 93|
|16.40|FDR_CONFIG ...................................................................................................................................... 94|
|16.41|APEX_CONFIG12 ................................................................................................................................ 95|
|User Bank MREG2 Register Map – Descriptions ............................................................................................... 96||
|17.1|OTP_CTRL7 ........................................................................................................................................ 96|
|User Bank MREG3 Register Map – Descriptions ............................................................................................... 97||
|18.1|XA_ST_DATA ...................................................................................................................................... 97|
|18.2|YA_ST_DATA ...................................................................................................................................... 97|
|18.3|ZA_ST_DATA ...................................................................................................................................... 97|
|18.4|XG_ST_DATA...................................................................................................................................... 97|
|18.5|YG_ST_DATA ...................................................................................................................................... 97|
|18.6|ZG_ST_DATA ...................................................................................................................................... 98|
|SmartMotion Product Family ........................................................................................................................... 99||
|Reference ....................................................................................................................................................... 100||
|Revision History .............................................................................................................................................. 101|Revision History .............................................................................................................................................. 101|
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_**ICM-42670-P**_
## **TABLE OF FIGURES**
|Figure 1. I|Figure 1. I2C Bus Timing Diagram ................................................................................................................................. 14|
|---|---|
|Figure 2. 4-Wire SPI Bus Timing Diagram .................................................................................................................... 15|Figure 2. 4-Wire SPI Bus Timing Diagram .................................................................................................................... 15|
|Figure 3. 3-Wire SPI Bus Timing Diagram .................................................................................................................... 16|Figure 3. 3-Wire SPI Bus Timing Diagram .................................................................................................................... 16|
|Figure 4. Pin Out Diagram for ICM-42670-P 2.5x3.0x0.76 mm LGA ............................................................................ 18|Figure 4. Pin Out Diagram for ICM-42670-P 2.5x3.0x0.76 mm LGA ............................................................................ 18|
|Figure 5. ICM-42670-P Application Schematic (I3C|Figure 5. ICM-42670-P Application Schematic (I3CSM/ I2C Interface to Host) ............................................................. 19|
|Figure 6. ICM-42670-P Application Schematic (SPI Interface to Host) ........................................................................ 19|Figure 6. ICM-42670-P Application Schematic (SPI Interface to Host) ........................................................................ 19|
|Figure 7. ICM-42670-P System Block Diagram............................................................................................................. 20|Figure 7. ICM-42670-P System Block Diagram............................................................................................................. 20|
|Figure 8. ICM-42670-P Signal Path .............................................................................................................................. 23|Figure 8. ICM-42670-P Signal Path .............................................................................................................................. 23|
|Figure 9. FIFO Packet Structure ................................................................................................................................... 24|Figure 9. FIFO Packet Structure ................................................................................................................................... 24|
|Figure 10. Maximum FIFO Storage .............................................................................................................................. 27|Figure 10. Maximum FIFO Storage .............................................................................................................................. 27|
|Figure 11. START and STOP Conditions ....................................................................................................................... 32|Figure 11. START and STOP Conditions ....................................................................................................................... 32|
|Figure 12. Acknowledge on the I|Figure 12. Acknowledge on the I2C Bus ....................................................................................................................... 33|
|Figure 13. Complete I|Figure 13. Complete I2C Data Transfer ........................................................................................................................ 33|
|Figure 14. Typical SPI Master/Slave Configuration ...................................................................................................... 35|Figure 14. Typical SPI Master/Slave Configuration ...................................................................................................... 35|
|Figure 15. Orientation of Axes of Sensitivity and Polarity of Rotation ........................................................................ 36|Figure 15. Orientation of Axes of Sensitivity and Polarity of Rotation ........................................................................ 36|
## **TABLE OF TABLES**
|Table 1. Gyroscope Specifications ............................................................................................................................... 10|Table 1. Gyroscope Specifications ............................................................................................................................... 10|
|---|---|
|Table 2. Accelerometer Specifications ........................................................................................................................ 11|Table 2. Accelerometer Specifications ........................................................................................................................ 11|
|Table 3. D.C. Electrical Characteristics ......................................................................................................................... 12|Table 3. D.C. Electrical Characteristics ......................................................................................................................... 12|
|Table 4. A.C. Electrical Characteristics ......................................................................................................................... 13|Table 4. A.C. Electrical Characteristics ......................................................................................................................... 13|
|Table 5. I|Table 5. I2C Timing Characteristics ............................................................................................................................... 14|
|Table 6. 4-Wire SPI Timing Characteristics (24-MHz Operation) ................................................................................. 15|Table 6. 4-Wire SPI Timing Characteristics (24-MHz Operation) ................................................................................. 15|
|Table 7. 3-Wire SPI Timing Characteristics (24-MHz Operation) ................................................................................. 16|Table 7. 3-Wire SPI Timing Characteristics (24-MHz Operation) ................................................................................. 16|
|Table 8. Absolute Maximum Ratings ........................................................................................................................... 17|Table 8. Absolute Maximum Ratings ........................................................................................................................... 17|
|Table 9. Signal Descriptions ......................................................................................................................................... 18|Table 9. Signal Descriptions ......................................................................................................................................... 18|
|Table 10. Bill of Materials ............................................................................................................................................ 20|Table 10. Bill of Materials ............................................................................................................................................ 20|
|Table 11. Standard Power Modes for ICM-42670-P .................................................................................................... 22|Table 11. Standard Power Modes for ICM-42670-P .................................................................................................... 22|
|Table 12. I3C|Table 12. I3CSMCCC Commands................................................................................................................................... 32|
|Table 13. I|Table 13. I2C Terms ...................................................................................................................................................... 34|
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Document Number: DS-000451 Revision: 1.0
_**ICM-42670-P**_
## _**INTRODUCTION**_
## **PURPOSE AND SCOPE**
This document is a product specification, providing a description, specifications, and design related information on the ICM-42670-P Single-Interface MotionTracking device. The device is housed in a small 2.5x3x0.76 mm 14-pin LGA package.
## **PRODUCT OVERVIEW**
The ICM-42670-P is a 6-axis MotionTracking device that combines a 3-axis gyroscope and a 3-axis accelerometer in a small 2.5x3x0.76 mm (14-pin LGA) package. It also features up to 2.25 Kbytes FIFO that can lower the traffic on the serial bus interface and reduce power consumption by allowing the system processor to burst read sensor data and then go into a low-power mode. ICM-42670-P, with its 6-axis integration, enables manufacturers to eliminate the costly and complex selection, qualification, and system level integration of discrete devices, guaranteeing optimal motion performance for consumers.
The gyroscope supports four programmable full-scale range settings from ±250 dps to ±2000 dps and the accelerometer supports four programmable full-scale range settings from ±2g to ±16g.
Other industry-leading features include on-chip 16-bit ADCs, programmable digital filters, an embedded temperature sensor, and programmable interrupts. The device features I3C[SM] , I[2] C, and SPI serial interfaces, a VDD operating range of 1.71V to 3.6V, and a separate VDDIO operating range of 1.71V to 3.6V.
The host interface can be configured to support I3C[SM] slave, I[2] C slave, or SPI slave modes. The I3C[SM] interface supports speeds up to 12.5 MHz (data rates up to 12.5 Mbps in SDR mode, 25 Mbps in DDR mode), the I[2] C interface supports speeds up to 1 MHz, and the SPI interface supports speeds up to 24 MHz.
The device provides high robustness by supporting 20,000 _g_ shock reliability.
## **APPLICATIONS**
- Wearables (Fitness Bands, SmartWatches, Healthcare wearables)
- Hearables (True Wireless Headsets)
- Gaming Controllers
- Smart Home Appliances
- Smart TV remotes
- Drones
- Robotics
- Augmented Reality/Virtual Reality
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Document Number: DS-000451 Revision: 1.0
_**ICM-42670-P**_
## _**FEATURES**_
## **GYROSCOPE FEATURES**
The triple-axis MEMS gyroscope in the ICM-42670-P includes a wide range of features:
- Digital-output X-, Y-, and Z-axis angular rate sensors (gyroscopes) with programmable full-scale range of ±250, ±500, ±1000, and ±2000 degrees/sec
- Low Noise (LN) power mode support
- Digitally programmable low-pass filters
- Factory calibrated sensitivity scale factor
- Self-test
## **ACCELEROMETER FEATURES**
The triple-axis MEMS accelerometer in ICM-42670-P includes a wide range of features:
- Digital-output X-, Y-, and Z-axis accelerometer with programmable full-scale range of ±2 _g_ , ±4 _g_ , ±8 _g_ and ±16 _g_
- Low Noise (LN) and Low Power (LP) power modes support
- User-programmable interrupts
- Wake-on-motion interrupt for low power operation of applications processor
- Self-test
## **MOTION FEATURES**
ICM-42670-P includes the following motion features, also known as APEX ( **A** dvanced **P** edometer and **E** vent Detection – ne **X** t gen)
- Pedometer: Tracks step count and issues a step detect Interrupt.
- Tilt Detection: Issues an interrupt when the Tilt angle exceeds 35 degrees for more than a programmable time.
- Low-g Detection: Triggers an interrupt when absolute value of accelerometer combined axis falls below a programmable threshold and stays below the threshold for a programmable time.
- Freefall Detection: Triggers an interrupt when device freefall is detected and outputs freefall duration.
- Wake on Motion (WoM): Detects motion when accelerometer samples exceed a programmable threshold. This motion event can be used to enable device operation from sleep mode.
- Significant Motion Detector (SMD): Detects significant motion based on accelerometer data.
## 2.4 **ADDITIONAL FEATURES**
ICM-42670-P includes the following additional features:
- Up to 2.25 Kbytes FIFO buffer enables the applications processor to read the data in bursts
- User-programmable digital filters for gyroscope, accelerometer, and temperature sensor
- 12.5M Hz I3C[SM] (data rates up to 12.5 Mbps in SDR mode, 25 Mbps in DDR mode) / 1 MHz I[2] C / 24 MHz SPI slave host interface
- Digital-output temperature sensor
- Smallest and thinnest LGA package for portable devices: 2.5x3x0.76 mm (14-pin LGA)
- 20,000 _g_ shock tolerant
- MEMS structure hermetically sealed and bonded at wafer level
- RoHS and Green compliant
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Document Number: DS-000451 Revision: 1.0
_**ICM-42670-P**_
## _**ELECTRICAL CHARACTERISTICS**_
## **GYROSCOPE SPECIFICATIONS**
Typical Operating Conditions, VDD = 1.8V, VDDIO = 1.8V, TA=25°C, unless otherwise noted.
|**PARAMETER**|**CONDITIONS**|**MIN**<br>||**TYP**|**MAX**|**UNITS**<br>||**NOTES**|
|---|---|---|---|---|---|---|
|**GYROSCOPE SENSITIVITY**<br>~~Ce~~|||||||
|Full-Scale Range<br>~~Re~~|GYRO_UI_FS_SEL=0<br>~~a~~|~~a~~|±2000<br>~~a~~|~~a~~|º/s<br>~~a~~|2<br>~~a~~|
||GYRO_UI_FS_SEL=1<br>~~es~~|~~es~~|±1000<br>~~es~~|~~es~~|º/s<br>~~es~~|2<br>~~es~~|
||GYRO_UI_FS_SEL=2<br>~~es~~|~~es~~|±500<br>~~es~~|~~es~~|º/s<br>~~es~~|2<br>~~es~~|
||GYRO_UI_FS_SEL=3<br>~~GO~~|~~GO~~|±250<br>~~GO~~|~~GO~~|º/s<br>~~GO~~|2<br>~~GO~~|
|Gyroscope ADC Word Length<br>~~Re~~|Output in two’s complement format<br>~~GO~~|~~GO~~|16<br>~~GO~~|~~GO~~|bits<br>~~GO~~|2, 5<br>~~GO~~|
|Sensitivity Scale Factor<br>~~Re~~|GYRO_UI_FS_SEL=0<br>~~GO~~<br>~~GG~~|~~GO~~<br>~~GG~~|16.4<br>~~GO~~<br>~~GG~~|~~GO~~<br>~~GG~~|LSB/(º/s)<br>~~GO~~<br>~~GG~~|2<br>~~GO~~<br>~~GG~~|
||GYRO_UI_FS_SEL=1<br>~~es~~|~~es~~|32.8<br>~~es~~|~~es~~|LSB/(º/s)<br>~~es~~|2<br>~~es~~|
||GYRO_UI_FS_SEL=2<br>~~GG~~|~~GG~~|65.5<br>~~GG~~|~~GG~~|LSB/(º/s)<br>~~GG~~|2<br>~~GG~~|
||GYRO_UI_FS_SEL=3<br>~~GG~~<br>~~GG~~|~~GG~~<br>~~GG~~|131<br>~~GG~~<br>~~GG~~|~~GG~~<br>~~GG~~|LSB/(º/s)<br>~~GG~~<br>~~GG~~|2<br>~~GG~~<br>~~GG~~|
|SensitivityScale Factor Initial Tolerance<br>~~Ge~~|25°C<br>~~Ge~~|~~Ge~~|±1<br>~~Ge~~|~~Ge~~|%<br>~~Ge~~|1, 7<br>~~Ge~~|
|Sensitivity Scale Factor Variation Over<br>Temperature|-40°C to +85°C; Board-Level||±0.007||%/ºC|3, 6|
|Nonlinearity<br>~~Ge~~|Best fit straight line; 25°C; Board-Level<br>~~Ge~~|~~Ge~~|±0.1<br>~~Ge~~|~~Ge~~<br>~~ee~~|%<br>~~Ge~~<br>~~ee~~|3, 6<br>~~Ge~~|
|Cross-Axis Sensitivity<br>~~GO~~|Board-level<br>~~GO~~|~~GO~~|±2<br>~~GO~~|~~GO~~<br>~~ee~~|%<br>~~GO~~<br>~~ee~~|3, 6<br>~~GO~~|
|**ZERO-RATE OUTPUT(ZRO)**<br>~~GO~~<br>~~ee~~<br>~~Ce~~|||||||
|Initial ZRO Tolerance<br>~~Ce~~<br>~~CG~~|25°C<br>~~Ce~~<br>~~CG~~|~~Ce~~<br>~~CG~~|±1<br>~~Ce~~<br>~~CG~~|~~Ce~~<br>~~CG~~|º/s<br>~~Ce~~<br>~~CG~~|1, 7<br>~~Ce~~<br>~~CG~~|
|ZRO Variation vs. Temperature<br>~~CG~~<br>~~Ge~~<br>~~Cn~~|-40°C to +85°C; Board-Level<br>~~CG~~<br>~~Ge~~|~~CG~~<br>~~Ge~~|±0.015<br>~~CG~~<br>~~Ge~~|~~CG~~<br>~~Ge~~|º/s/ºC<br>~~CG~~<br>~~Ge~~|3, 6<br>~~CG~~<br>~~Ge~~|
|**OTHER PARAMETERS**<br>~~Cn~~<br>~~GOO~~|||||||
|Rate Noise Spectral Density<br>~~Cn~~<br>~~RG~~|@ 10 Hz<br>~~RG~~|~~RG~~<br>~~GOO~~|0.007<br>~~RG~~<br>~~GOO~~|~~RG~~<br>~~GOO~~|º/s /√Hz<br>~~RG~~<br>~~GOO~~|1<br>~~RG~~|
|Total RMS Noise<br>~~RG~~<br>~~CO~~|Bandwidth = 100 Hz<br>~~RG~~<br>~~CO~~|~~RG~~<br>~~GOO~~<br>~~CO~~|0.07<br>~~RG~~<br>~~GOO~~<br>~~CO~~|~~RG~~<br>~~GOO~~<br>~~CO~~|º/s-rms<br>~~RG~~<br>~~GOO~~<br>~~CO~~|4<br>~~RG~~<br>~~CO~~|
|Gyroscope Mechanical Frequencies<br>~~CO~~<br>~~GO~~|~~CO~~<br>~~GO~~|25<br>~~CO~~<br>~~GO~~|28<br>~~CO~~<br>~~GO~~|30<br>~~CO~~<br>~~GO~~|kHz<br>~~CO~~<br>~~GO~~|1<br>~~CO~~<br>~~GO~~|
|Low Pass Filter Response<br>~~GO~~<br>~~GO~~|~~GO~~<br>~~GO~~|16<br>~~GO~~<br>~~GO~~|~~GO~~<br>~~GO~~|180<br>~~GO~~<br>~~GO~~|Hz<br>~~GO~~<br>~~GO~~|2<br>~~GO~~<br>~~GO~~|
|Gyroscope Start-UpTime<br>~~OG~~|Time fromgyro enable togyro drive ready<br>~~OG~~|~~OG~~|30<br>~~OG~~|~~OG~~|ms<br>~~OG~~|3<br>~~OG~~|
|Output Data Rate<br>~~OG~~<br>~~a~~|~~OG~~<br>~~a~~|12.5<br>~~OG~~<br>~~a~~|~~OG~~<br>~~a~~|1600<br>~~OG~~<br>~~a~~|Hz<br>~~OG~~<br>~~a~~|2<br>~~OG~~<br>~~a~~|
## **Table 1. Gyroscope Specifications**
## **Notes:**
1. Tested in production at component-level.
2. Guaranteed by design.
3. Derived from validation or characterization of parts, not tested in production.
4. Calculated from Rate Noise Spectral Density.
5. 20-bits data format supported in FIFO, see section 6.1.
6. Board-level spec values depend on specific board design. For design information of boards used for device characterization, that forms the basis of the spec values reported here, please contact your local TDK InvenSense FAE.
7. Value after factory test and trim.
Page 10 of 102
Document Number: DS-000451 Revision: 1.0
_**ICM-42670-P**_
## **ACCELEROMETER SPECIFICATIONS**
Typical Operating Conditions, VDD = 1.8V, VDDIO = 1.8V, TA=25°C, unless otherwise noted.
|**PARAMETER**<br>~~Re~~|**CONDITIONS**<br>~~ss~~|**MIN**<br>~~ss~~|**TYP**<br>~~ss~~|**MAX**<br>~~ss~~|**UNITS**<br>~~ss~~|**NOTES**<br>~~ss~~|
|---|---|---|---|---|---|---|
|**ACCELEROMETER SENSITIVITY**<br>~~Ress~~|||||||
|Full-Scale Range<br>~~Re ~~|ACCEL_UI_FS_SEL=0<br> ~~ss~~|~~ss~~|±16<br>~~ss~~|~~ss~~|_g_<br>~~ss~~|2<br>~~ss~~|
||ACCEL_UI_FS_SEL=1<br>~~ss~~|~~ss~~|±8<br>~~ss~~|~~ss~~|_g_<br>~~ss~~|2<br>~~ss~~|
||ACCEL_UI_FS_SEL=2<br>~~ss~~|~~ss~~|±4<br>~~ss~~|~~ss~~|_g_<br>~~ss~~|2<br>~~ss~~|
||ACCEL_UI_FS_SEL=3<br>~~ss~~|~~ss~~|±2<br>~~ss~~|~~ss~~|_g_<br>~~ss~~|2<br>~~ss~~|
|ADC Word Length<br>~~OO~~<br>~~a~~|Output in two’s complement format<br>~~OO~~<br>~~a~~|~~OO~~<br>~~es~~<br>|16<br>~~OO~~<br>|~~OO~~<br>|bits<br>~~OO~~<br>|2, 5<br>~~OO~~<br>|
|Sensitivity Scale Factor<br>~~a~~<br>~~**e**e es~~|ACCEL_UI_FS_SEL=0<br>~~es~~<br>~~a~~|~~es~~<br>~~es~~<br>|2,048<br>~~es~~<br>|~~es~~<br>|LSB/_g_<br>~~es~~<br>|2<br>~~es~~<br>|
||ACCEL_UI_FS_SEL=1<br>~~a~~|~~es~~<br>|4,096<br>||LSB/_g_<br>|2<br>|
||ACCEL_UI_FS_SEL=2<br>~~ass~~|~~es~~<br>~~ss~~|8,192<br>~~ss~~|~~ss~~|LSB/_g_<br>~~ss~~|2<br>~~ss~~|
||ACCEL_UI_FS_SEL=3<br>~~es~~||16,384<br>||LSB/_g_<br>|2<br>|
|Sensitivity Scale Factor Initial<br>Tolerance<br>~~**e**e es~~|25°C<br>~~es~~||±1<br>||%<br>|1, 7<br>|
|SensitivityChange vs. Temperature<br>~~**e**e es~~|-40°C to +85°C; Board-Level<br>~~ess~~|~~s~~|±0.01<br>~~s~~|~~s~~|%/ºC<br>~~s~~|3, 6<br>~~s~~|
|Nonlinearity<br><br>~~OG~~|Best Fit Straight Line, ±2g; Board-Level<br>~~s~~<br>~~OG~~|~~s~~<br>~~OG~~|±0.1<br>~~s~~<br>~~OG~~|~~s~~<br>~~OG~~|%<br>~~s~~<br>~~OG~~|3, 6<br>~~s~~<br>~~OG~~|
|Cross-Axis Sensitivity<br>~~OG~~<br>~~I~~|Board-level<br>~~OG~~<br>~~I~~|~~OG~~<br>~~I~~|±1<br>~~OG~~<br>~~I~~|~~OG~~<br>~~I~~|%<br>~~OG~~<br>~~I~~|3, 6<br>~~OG~~<br>~~I~~|
|**ZERO-G OUTPUT**<br>~~|~~|||||||
|Initial Tolerance<br>~~sO~~<br>~~a~~|25°C<br>~~sO~~<br>|~~sO~~<br>|±25<br>~~sO~~<br>|~~sO~~<br>|m_g_<br>~~sO~~<br>|1, 7<br>~~sO~~<br>|
|Zero-G Level Change vs. Temperature<br>~~a~~|-40°C to +85°C; Board-Level<br>||±0.15<br>||m_g/_ºC<br>|3, 6<br>|
|**OTHER PARAMETERS**<br>~~a|~~|||||||
|Power Spectral Density<br>~~|~~<br>~~I~~|@ 10 Hz<br>~~|~~<br>~~I~~|~~|~~<br>~~I~~|100<br>~~|~~<br>~~I~~|~~|~~<br>~~I~~|µ_g_/√Hz<br>~~|~~<br>~~I~~|1<br>~~|~~<br>~~I~~|
|RMS Noise<br>~~a~~|Bandwidth = 100 Hz<br>~~a~~|~~a~~|1.0<br>~~a~~|~~a~~|mg-rms<br>~~a~~|4<br>~~a~~|
|Low Pass Filter Response<br>~~a~~|~~a~~|16<br>~~a~~|~~a~~|180<br>~~a~~|Hz<br>~~a~~|2<br>~~a~~|
|Accelerometer StartupTime<br>~~GO~~|From sleepmode to valid data<br>~~GO~~|~~GO~~|10<br>~~GO~~|~~GO~~|ms<br>~~GO~~|3<br>~~GO~~|
|Output Data Rate<br>~~GG~~|~~GG~~|1.5625<br>~~GG~~|~~GG~~|1600<br>~~GG~~|Hz<br>~~GG~~|2<br>~~GG~~|
**Table 2. Accelerometer Specifications**
## **Notes:**
1. Tested in production at component-level.
2. Guaranteed by design.
3. Derived from validation or characterization of parts, not tested in production.
4. Calculated from Power Spectral Density.
5. 20-bits data format supported in FIFO, see section 6.1.
6. Board-level spec values depend on specific board design. For design information of boards used for device characterization, that forms the basis of the spec values reported here, please contact your local TDK InvenSense FAE.
7. Value after factory test and trim.
Page 11 of 102
Document Number: DS-000451 Revision: 1.0
_**ICM-42670-P**_
## **ELECTRICAL SPECIFICATIONS**
## **3.3.1 D.C. Electrical Characteristics**
Typical Operating Conditions, VDD = 1.8V, VDDIO = 1.8V, TA=25°C, unless otherwise noted.
|**PARAMETER**|**CONDITIONS**|**MIN**|**TYP**|**MAX**|**UNITS**|**NOTES**|
|---|---|---|---|---|---|---|
|**SUPPLY VOLTAGES**<br>~~ee~~<br>~~sO~~<br>~~Re~~|||||||
|VDD<br>~~eG~~<br>~~Re~~|~~eG~~<br>|1.71<br>~~eG~~<br>~~sO~~<br>|1.8<br>~~eG~~<br>~~sO~~<br>|3.6<br>~~eG~~<br>|V<br>~~eG~~<br>|1<br>~~eG~~<br>|
|VDDIO<br>~~Re~~||1.71<br>~~sO~~<br>|1.8<br>~~sO~~<br>|3.6<br>|V<br>|1<br>|
|**SUPPLY CURRENTS**<br>~~sO~~<br>~~ReCe~~|||||||
|Low-Noise Mode<br>~~a~~<br>~~re~~|6-Axis Gyroscope + Accelerometer<br>~~a~~<br>~~a~~||0.55<br>||mA<br>|2<br>|
||3-Axis Accelerometer<br>~~a~~||0.20<br>||mA<br>|2<br>|
||3-Axis Gyroscope<br>~~aVe~~<br>|~~Ve~~<br>|0.42<br>~~Ve~~<br>|~~Ve~~|mA<br>~~Ve~~|2<br>~~Ve~~|
|Full-ChipSleepMode<br><br>~~re~~|At 25ºC<br>~~Ve~~<br>~~GO~~|~~Ve~~<br>~~GO~~|3.5<br>~~Ve~~<br>~~GO~~|~~Ve~~|µA<br>~~Ve~~|2<br>~~Ve~~|
|**TEMPERATURE RANGE**<br>~~Ve~~<br>~~re~~<br>~~ee~~|||||||
|Specified Temperature Range|Performance parameters are not applicable<br>beyond Specified Temperature Range|-40||+85|°C|1|
**Table 3. D.C. Electrical Characteristics**
## **Notes:**
1. Guaranteed by design.
2. Derived from validation or characterization of parts, not tested in production.
Page 12 of 102
Document Number: DS-000451 Revision: 1.0
_**ICM-42670-P**_
## **3.3.2 A.C. Electrical Characteristics**
Typical Operating Conditions, VDD = 1.8V, VDDIO = 1.8V, TA=25°C, unless otherwise noted.
|**PARAMETER**<br>|<br>~~RC~~|**CONDITIONS**<br>||**MIN**|**TYP**|**MAX**|**UNITS**|**NOTES**|
|---|---|---|---|---|---|---|
|**SUPPLIES**<br>~~RC~~<br>~~es~~|||||||
|Supply Ramp Time<br>~~RC~~<br>~~es~~<br>~~es~~|Valid power-on RESET|0.1||3|ms|1|
|Power Supply Noise<br>~~es~~<br>~~es~~|||10||mV<br>peak-peak|1|
|**TEMPERATURE SENSOR**<br>~~es~~<br>~~Ce~~|||||||
|OperatingRange<br>~~a~~|Ambient<br>~~COC~~|-40<br>~~COC~~|~~COC~~<br>~~OO~~|85<br>~~COC~~<br>~~OO~~|°C<br>~~COC~~|1<br>~~COC~~|
|25°C Output<br>~~CG~~|Output in two’s complement format<br>~~CG~~|~~CG~~|0<br>~~CG~~<br>~~OO~~<br>~~QO~~|~~CG~~<br>~~OO~~<br>~~OC~~|LSB<br>~~CG~~<br>~~OC~~|3<br>~~CG~~|
|ADC Resolution<br>~~GG~~<br>~~a~~|~~GG~~|~~GG~~<br>~~GC~~|16<br>~~OO~~<br>~~GG~~<br>~~QO~~<br>~~GC~~|~~OO~~<br>~~GG~~<br>~~OC~~<br>~~GC~~|bits<br>~~GG~~<br>~~OC~~<br>~~GC~~|2<br>~~GG~~|
|ODR<br>~~Ge~~<br>~~a~~|With Filter<br>~~Ge~~|1.5625<br>~~Ge~~<br>~~GC~~|~~QO~~<br>~~Ge~~<br>~~GC~~|1600<br>~~OC~~<br>~~Ge~~<br>~~GC~~<br>~~OO~~|Hz<br>~~OC~~<br>~~Ge~~<br>~~GC~~<br>~~OO~~|2,4<br>~~Ge~~|
|Room Temperature Offset<br>~~a~~|25°C<br>~~QC~~|-3<br>~~GC~~<br>~~QC~~|~~GC~~<br>~~QC~~|3<br>~~GC~~<br>~~QC~~<br>~~OO~~|°C<br>~~GC~~<br>~~QC~~<br>~~OO~~|3<br>~~QC~~|
|Stabilization Time (fixed number of clock<br>cycles)<br>~~a~~||||0.64<br>~~OO~~<br>~~GO~~|sec<br>~~OO~~<br>~~GO~~|2|
|Sensitivity<br>~~a~~<br>~~a~~|Trimmed<br>~~CC~~|125<br>~~CC~~|126.9<br>~~CC~~|129<br>~~CC~~<br>~~GO~~|LSB/°C<br>~~CC~~<br>~~GO~~|1<br>~~CC~~|
|Sensitivityfor FIFO data<br>~~a~~|Trimmed<br>~~GO~~|1.95<br>~~GO~~|1.983<br>~~GO~~|2.01<br>~~GO~~<br>~~GO~~|LSB/°C<br>~~GO~~<br>~~GO~~|1<br>~~GO~~|
|**POWER-ON RESET**<br>~~GO~~<br>~~a~~<br>~~GO~~<br>~~CT~~|||||||
|Start-uptime for register read/write<br>~~QO~~|Frompower-up<br>~~QO~~|~~QO~~|~~QO~~|1<br>~~QO~~|ms<br>~~QO~~|1<br>~~QO~~|
|**I2C ADDRESS**<br>~~Le~~<br>~~a~~|||||||
|**I2C ADDRESS**<br>~~Le~~<br>~~a~~|AP_AD0 = 0<br>AP_AD0 = 1<br>~~Le~~<br>|~~Le~~<br>|1101000<br>1101001<br>~~Le~~<br>|~~Le~~<br>|~~Le~~<br>|~~Le~~<br>|
|**DIGITAL INPUTS(FSYNC, SCLK, SDI, CS)**<br>~~aCe~~<br>~~———~~<br>~~ee~~<br>~~ee~~|||||||
|VIH, High Level Input Voltage<br>~~Ce~~<br>~~sO~~<br>~~———~~|~~Ce~~<br>~~sO~~<br>~~ee~~|0.7*VDDIO<br>~~Ce~~<br>~~sO~~<br>~~ee~~|~~Ce~~<br>~~sO~~<br>~~ee~~|~~Ce~~<br>~~sO~~|V<br>~~Ce~~<br>~~sO~~|1<br>~~Ce~~|
|VIL, Low Level Input Voltage<br>~~sO~~<br>~~———~~|~~sO~~<br>~~ee~~|~~sO~~<br>~~ee~~|~~sO~~<br>~~ee~~|0.3*VDDIO<br>~~sO~~|V<br>~~sO~~||
|CI, Input Capacitance<br>~~———~~<br>~~eG~~|~~ee~~<br>~~eG~~|~~ee~~<br>~~eG~~|<10<br>~~ee~~<br>~~eG~~|~~eG~~|pF<br>~~eG~~||
|**DIGITAL OUTPUT(SDO, INT1, INT2)**<br>~~———~~<br>~~ee~~<br>~~ee~~<br>~~eG~~<br>~~Ce~~<br>~~——~~|||||||
|VOH, High Level Output Voltage<br>~~Ce~~<br>~~sO~~<br>~~——~~|RLOAD=1 MΩ;<br>~~Ce~~<br>~~sO~~|0.9*VDDIO<br>~~Ce~~<br>~~sO~~|~~Ce~~<br>~~sO~~|~~Ce~~<br>~~sO~~|V<br>~~Ce~~<br>~~sO~~|1<br>~~Ce~~|
|VOL1, LOW-Level Output Voltage<br>~~sO~~<br>~~——~~|RLOAD=1 MΩ;<br>~~sO~~|~~sO~~|~~sO~~|0.1*VDDIO<br>~~sO~~|V<br>~~sO~~||
|VOL.INT, INT Low-Level Output Voltage<br>~~——~~|OPEN=1, 0.3 mA sink<br>Current|||0.1|V||
|Output Leakage Current<br>~~——~~<br>~~es~~|OPEN=1<br>~~es~~|~~es~~|100<br>~~es~~|~~es~~|nA<br>~~es~~||
|tINT, INT Pulse Width<br>~~——~~<br>~~sO~~|int_tpulse_duration= 0 , 1 (100us, 8us ) ;<br>~~sO~~|8<br>~~sO~~|~~sO~~|100<br>~~sO~~|µs<br>~~sO~~||
|**I2C I/O (SCL, SDA)**<br>~~——~~<br>~~Se~~|||||||
|VIL, LOW-Level Input Voltage<br>~~Se~~<br>~~sO~~|~~Se~~<br>~~sO~~|-0.5V<br>~~Se~~<br>~~sO~~|~~Se~~<br>~~sO~~|0.3*VDDIO<br>~~Se~~<br>~~sO~~|V<br>~~Se~~<br>~~sO~~|1<br>~~Se~~|
|VIH, HIGH-Level Input Voltage<br>~~sO~~|~~sO~~|0.7*VDDIO<br>~~sO~~|~~sO~~|VDDIO +<br>0.5V<br>~~sO~~|V<br>~~sO~~||
|Vhys, Hysteresis<br>~~sO~~|~~sO~~|~~sO~~|0.1*VDDIO<br>~~sO~~|~~sO~~|V<br>~~sO~~||
|VOL, LOW-Level Output Voltage<br>~~sO~~<br>~~sO~~|3 mA sink current<br>~~sO~~<br>~~sO~~|0<br>~~sO~~<br>~~sO~~|~~sO~~<br>~~sO~~|0.4<br>~~sO~~<br>~~sO~~|V<br>~~sO~~<br>~~sO~~||
|IOL, LOW-Level Output Current<br>~~sO~~|VOL=0.4 V<br>VOL=0.6 V<br>~~sO~~|~~sO~~|3<br>6<br>~~sO~~|~~sO~~|mA<br>mA<br>~~sO~~||
|Output Leakage Current<br>~~sO~~|~~sO~~|~~sO~~|100<br>~~sO~~|~~sO~~|nA<br>~~sO~~||
|tof, Output Fall Time from VIHmaxto VILmax<br>~~sD~~|Cbbus capacitance in pf<br>~~sD~~|20+0.1Cb<br>~~sD~~|~~sD~~|300<br>~~sD~~|ns<br>~~sD~~||
|**INTERNAL CLOCK SOURCE**<br>~~Ce~~<br>~~OO~~<br>~~——~~|||||||
|Clock Frequency Initial Tolerance<br>~~Ce~~<br>~~OO~~|CLKSEL=2b00 or gyro inactive; 25°C<br>~~Ce~~<br>~~OO~~|-3<br>~~Ce~~<br>~~OO~~|~~Ce~~<br>~~——~~|+3<br>~~Ce~~<br>~~——~~|%<br>~~Ce~~<br>~~——~~|1<br>~~Ce~~<br>~~——~~|
||CLKSEL=2b01 and gyro active; 25°C<br>~~OO~~<br>~~QQ~~|-1<br>~~OO~~<br>~~QQ~~|~~——~~<br>~~QQ~~|+1<br>~~——~~<br>~~QQ~~|%<br>~~——~~<br>~~QQ~~|1<br>~~——~~<br>~~QQ~~|
|Frequency Variation over Temperature<br>~~OO~~<br>~~e~~|CLKSEL=2b00 or gyro inactive; -40°C to +85°C<br>~~OO~~<br>~~e~~~~**e**~~|~~OO~~|~~——~~|±3<br>~~——~~|%<br>~~——~~|1<br>~~——~~|
||CLKSEL=2b01 and gyro active; -40oC to +85oC<br>~~e~~~~**e**~~|~~s~~|~~s~~|±1<br>~~s~~|%<br>~~s~~|1<br>~~s~~|
## **Table 4. A.C. Electrical Characteristics**
## **Notes:**
1. Expected results based on design, will be updated after characterization. Not tested in production. 2. Guaranteed by design.
3. Production tested.
4. Temperature sensor ODR is the higher value between gyroscope and accelerometer ODR.
Page 13 of 102
Document Number: DS-000451 Revision: 1.0
_**ICM-42670-P**_
## 3.4 **I[2] C TIMING CHARACTERIZATION**
Typical Operating Conditions, VDD = 1.8V, VDDIO = 1.8V, TA=25°C, unless otherwise noted. Slew Rate can be configured by the user using register DRIVE_CONFIG2.
|**PARAMETERS**|**CONDITIONS**|**MIN**|**TYP**|**MAX**<br>~~|~~|**UNITS**<br>~~|~~|**NOTES**<br>~~|~~|
|---|---|---|---|---|---|---|
|**I2C TIMING**<br>~~I~~|**I2C FAST-MODE PLUS**<br>~~I~~|~~I~~|~~I~~|~~I~~|~~I~~|~~I~~|
|fSCL, SCL Clock Frequency<br>~~a~~|~~a~~|~~a~~|~~a~~|1<br>~~a~~|MHz<br>~~a~~|1<br>~~a~~|
|tHD.STA, (Repeated) START Condition Hold Time<br>~~GG~~|~~GG~~|0.26<br>~~GG~~|~~GG~~|~~GG~~|µs<br>~~GG~~|1<br>~~GG~~|
|tLOW, SCL Low Period<br>~~GO~~|~~GO~~|0.5<br>~~GO~~|~~GO~~|~~GO~~|µs<br>~~GO~~|1<br>~~GO~~|
|tHIGH, SCL High Period<br>~~a~~|~~a~~|0.26<br>~~a~~|~~a~~|~~a~~|µs<br>~~a~~|1<br>~~a~~|
|tSU.STA, Repeated START Condition SetupTime<br>~~I~~|~~I~~|0.26<br>~~I~~|~~I~~|~~I~~|µs<br>~~I~~|1<br>~~I~~|
|tHD.DAT, SDA Data Hold Time<br>~~a~~|~~a~~|0<br>~~a~~|~~a~~|~~a~~|µs<br>~~a~~|1<br>~~a~~|
|tSU.DAT, SDA Data SetupTime<br>~~GO~~|~~GO~~|50<br>~~GO~~|~~GO~~|~~GO~~|ns<br>~~GO~~|1<br>~~GO~~|
|tSU.STO, STOP Condition SetupTime<br>~~I~~|~~I~~|0.5<br>~~I~~|~~I~~|~~I~~|µs<br>~~I~~|1<br>~~I~~|
|tBUF, Bus Free Time Between STOP and START<br>Condition||0.5|||µs|1|
|Cb, Capacitive Load for each Bus Line<br>~~a~~|~~a~~|~~a~~|~~a~~|550<br>~~a~~|pF<br>~~a~~|1<br>~~a~~|
|tVD.DAT, Data Valid Time<br>~~a~~<br>~~I~~|~~a~~<br>~~I~~|~~a~~<br>~~I~~|~~a~~<br>~~I~~|0.45<br>~~a~~<br>~~I~~|µs<br>~~a~~<br>~~I~~|1<br>~~a~~<br>~~I~~|
|tVD.ACK, Data Valid Acknowledge Time<br>~~a~~|~~a~~|~~a~~|~~a~~|0.45<br>~~a~~|µs<br>~~a~~|1<br>~~a~~|
**Table 5. I[2] C Timing Characteristics**
- **Notes:** 1. Based on characterization of 5 parts over temperature and voltage as mounted on evaluation board or in sockets
**==> picture [472 x 143] intentionally omitted <==**
**----- Start of picture text -----**<br>
tf tr tSU.DAT<br>SDA 70% 70%<br>30% 30%<br>tf continued below at A<br>tr tVD.DAT<br>SCL 70% tHD.DAT 70%<br>30% 30%<br>tHD.STA 1/fSCL tLOW 9 [th] clock cycle<br>S 1 [st] clock cycle tHIGH<br>tBUF<br>SDA 70%<br>A 30%<br>tSU.STA tHD.STA tVD.ACK tSU.STO<br>SCL 70%<br>30%<br>Sr 9 [th] clock cycle P S<br>**----- End of picture text -----**<br>
**Figure 1. I[2] C Bus Timing Diagram**
Page 14 of 102
Document Number: DS-000451 Revision: 1.0
_**ICM-42670-P**_
## **SPI TIMING CHARACTERIZATION – 4-WIRE SPI MODE**
Typical Operating Conditions, VDD = 1.8V, VDDIO = 1.8V, TA=25°C, unless otherwise noted. Slew Rate can be configured by the user using register DRIVE_CONFIG3.
|**PARAMETERS**|**CONDITIONS**<br>~~nD~~|**MIN**<br>~~I~~|**TYP**<br>~~I (~~|**MAX**<br>~~(~~|**UNITS**<br>||**NOTES**|
|---|---|---|---|---|---|---|
|**SPI TIMING**<br>~~es~~|~~es~~<br>~~nD~~<br>~~nD~~|~~es~~<br>~~I~~<br>~~(RU~~|~~es~~<br>~~I (~~<br>~~(RU~~|~~es~~<br>~~(~~|~~es~~|~~es~~|
|fSPC, SCLK Clock Frequency<br>~~ns~~|Default<br>~~nD~~<br>~~ns~~<br>~~nD~~<br>~~nD~~|~~I~~<br>~~ns~~<br>~~(RU~~<br>~~(RU~~|~~I (~~<br>~~ns~~<br>~~(RU~~<br>~~(RU~~|24<br>~~(~~<br>~~ns~~|MHz<br>~~ns~~|1<br>~~ns~~|
|tLOW, SCLK Low Period<br>~~ns~~|~~nD~~<br>~~ns~~<br>~~nD~~<br>~~nD~~|17<br>~~(RU~~<br>~~ns~~<br>~~(RU~~<br>~~(RU~~|~~(RU~~<br>~~ns~~<br>~~(RU~~<br>~~(RU~~|~~ns~~|ns<br>~~ns~~|1<br>~~ns~~|
|tHIGH, SCLK High Period<br>~~ns~~|~~nD~~<br>~~ns~~<br>~~nD~~<br>~~nD~~|17<br>~~(RU~~<br>~~ns~~<br>~~(RU~~<br>~~(RU~~|~~(RU~~<br>~~ns~~<br>~~(RU~~<br>~~(RU~~|~~ns~~|ns<br>~~ns~~|1<br>~~ns~~|
|tSU.CS, CS Setup Time<br>~~ns~~|~~nD~~<br>~~ns~~<br>~~nD~~<br>~~nD~~|17<br>~~(RU~~<br>~~ns~~<br>~~(RU~~<br>~~(RU~~|~~(RU~~<br>~~ns~~<br>~~(RU~~<br>~~(RU~~|~~ns~~|ns<br>~~ns~~|1<br>~~ns~~|
|tHD.CS, CS Hold Time<br>~~ns~~|~~nD~~<br>~~ns~~<br>~~nD~~<br>~~nD~~|5<br>~~(RU~~<br>~~ns~~<br>~~(RU~~<br>~~(RU~~|~~(RU~~<br>~~ns~~<br>~~(RU~~<br>~~(RU~~|~~ns~~|ns<br>~~ns~~|1<br>~~ns~~|
|tSU.SDI, SDI Setup Time<br>~~ns~~|~~nD~~<br>~~ns~~<br>~~nD~~<br>~~nD~~|13<br>~~(RU~~<br>~~ns~~<br>~~(RU~~<br>~~(RU~~|~~(RU~~<br>~~ns~~<br>~~(RU~~<br>~~(RU~~|~~ns~~|ns<br>~~ns~~|1<br>~~ns~~|
|tHD.SDI, SDI Hold Time<br>~~ns~~|~~nD~~<br>~~ns~~<br>~~nD~~<br>~~nD~~|8<br>~~(RU~~<br>~~ns~~<br>~~(RU~~<br>~~(RU~~|~~(RU~~<br>~~ns~~<br>~~(RU~~<br>~~(RU~~|~~ns~~|ns<br>~~ns~~|1<br>~~ns~~|
|tVD.SDO, SDO Valid Time<br>~~ns~~|Cload= 20 pF<br>~~nD~~<br>~~ns~~<br>~~nD~~<br>~~nD~~|~~(RU~~<br>~~ns~~<br>~~(RU~~<br>~~(RU~~|~~(RU~~<br>~~ns~~<br>~~(RU~~<br>~~(RU~~|18.5<br>~~ns~~|ns<br>~~ns~~|1<br>~~ns~~|
|tHD.SDO, SDO Hold Time<br>~~ns~~|Cload= 20 pF<br>~~nD~~<br>~~ns~~<br>~~nD~~<br>~~nD~~|3.5<br>~~(RU~~<br>~~ns~~<br>~~(RU~~<br>~~(RO~~|~~(RU~~<br>~~ns~~<br>~~(RU~~<br>~~(~~|~~ns~~|ns<br>~~ns~~|1<br>~~ns~~|
|tDIS.SDO, SDO Output Disable Time<br>~~ns~~|~~nD~~<br>~~ns~~<br>~~nD~~|~~(RU~~<br>~~ns~~<br>~~(RO~~|~~(RU~~<br>~~ns~~<br>~~(~~|18.5<br>~~ns~~|ns<br>~~ns~~|1<br>~~ns~~|
**Table 6. 4-Wire SPI Timing Characteristics (24-MHz Operation)**
**==> picture [405 x 18] intentionally omitted <==**
**----- Start of picture text -----**<br>
Notes:<br>1. Based on characterization of 5 parts over temperature and voltage as mounted on evaluation board or in sockets<br>**----- End of picture text -----**<br>
**==> picture [475 x 148] intentionally omitted <==**
**----- Start of picture text -----**<br>
CS 70%<br>30%<br>tFall tRise tHD;CS<br>tSU;CS tHIGH 1/fCLK<br>SCLK 70%<br>30%<br>tSU;SDI tHD;SDI tLOW<br>! = |<br>SDI 70% MSB IN LSB IN<br>30%<br>tVD;SDO tHD;SDO Xx tDIS;SDO<br>SDO 70%<br>MSB OUT LSB OUT<br>30%<br>$FE>E<br>**----- End of picture text -----**<br>
**Figure 2. 4-Wire SPI Bus Timing Diagram**
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_**ICM-42670-P**_
## **SPI TIMING CHARACTERIZATION – 3-WIRE SPI MODE**
Typical Operating Conditions, VDD = 1.8V, VDDIO = 1.8V, TA=25°C, unless otherwise noted. Slew Rate can be configured by the user using register DRIVE_CONFIG3.
|**PARAMETERS**|**CONDITIONS**<br>~~nD~~|**MIN**<br>~~I~~|**TYP**<br>~~I (~~|**MAX**<br>~~(~~|**UNITS**<br>||**NOTES**|
|---|---|---|---|---|---|---|
|**SPI TIMING**<br>~~es~~|~~es~~<br>~~nD~~<br>~~nD~~|~~es~~<br>~~I~~<br>~~(RU~~|~~es~~<br>~~I (~~<br>~~(RU~~|~~es~~<br>~~(~~|~~es~~|~~es~~|
|fSPC, SCLK Clock Frequency<br>~~ns~~|Default<br>~~nD~~<br>~~ns~~<br>~~nD~~<br>~~nD~~|~~I~~<br>~~ns~~<br>~~(RU~~<br>~~(RU~~|~~I (~~<br>~~ns~~<br>~~(RU~~<br>~~(RU~~|24<br>~~(~~<br>~~ns~~|MHz<br>~~ns~~|1<br>~~ns~~|
|tLOW, SCLK Low Period<br>~~ns~~|~~nD~~<br>~~ns~~<br>~~nD~~<br>~~nD~~|17<br>~~(RU~~<br>~~ns~~<br>~~(RU~~<br>~~(RU~~|~~(RU~~<br>~~ns~~<br>~~(RU~~<br>~~(RU~~|~~ns~~|ns<br>~~ns~~|1<br>~~ns~~|
|tHIGH, SCLK High Period<br>~~ns~~|~~nD~~<br>~~ns~~<br>~~nD~~<br>~~nD~~|17<br>~~(RU~~<br>~~ns~~<br>~~(RU~~<br>~~(RU~~|~~(RU~~<br>~~ns~~<br>~~(RU~~<br>~~(RU~~|~~ns~~|ns<br>~~ns~~|1<br>~~ns~~|
|tSU.CS, CS Setup Time<br>~~ns~~|~~nD~~<br>~~ns~~<br>~~nD~~<br>~~nD~~|17<br>~~(RU~~<br>~~ns~~<br>~~(RU~~<br>~~(RU~~|~~(RU~~<br>~~ns~~<br>~~(RU~~<br>~~(RU~~|~~ns~~|ns<br>~~ns~~|1<br>~~ns~~|
|tHD.CS, CS Hold Time<br>~~ns~~|~~nD~~<br>~~ns~~<br>~~nD~~<br>~~nD~~|5<br>~~(RU~~<br>~~ns~~<br>~~(RU~~<br>~~(RU~~|~~(RU~~<br>~~ns~~<br>~~(RU~~<br>~~(RU~~|~~ns~~|ns<br>~~ns~~|1<br>~~ns~~|
|tSU.SDIO, SDIO Input Setup Time<br>~~ns~~|~~nD~~<br>~~ns~~<br>~~nD~~<br>~~nD~~|13<br>~~(RU~~<br>~~ns~~<br>~~(RU~~<br>~~(RU~~|~~(RU~~<br>~~ns~~<br>~~(RU~~<br>~~(RU~~|~~ns~~|ns<br>~~ns~~|1<br>~~ns~~|
|tHD.SDIO, SDIO Input Hold Time<br>~~ns~~|~~nD~~<br>~~ns~~<br>~~nD~~<br>~~nD~~|8<br>~~(RU~~<br>~~ns~~<br>~~(RU~~<br>~~(RU~~|~~(RU~~<br>~~ns~~<br>~~(RU~~<br>~~(RU~~|~~ns~~|ns<br>~~ns~~|1<br>~~ns~~|
|tVD.SDIO, SDIO Output Valid Time<br>~~ns~~|Cload= 20 pF<br>~~nD~~<br>~~ns~~<br>~~nD~~<br>~~nD~~|~~(RU~~<br>~~ns~~<br>~~(RU~~<br>~~(RU~~|~~(RU~~<br>~~ns~~<br>~~(RU~~<br>~~(RU~~|18.5<br>~~ns~~|ns<br>~~ns~~|1<br>~~ns~~|
|tHD.SDIO, SDIO Output Hold Time<br>~~ns~~|Cload= 20 pF<br>~~nD~~<br>~~ns~~<br>~~nD~~<br>~~nD~~|3.5<br>~~(RU~~<br>~~ns~~<br>~~(RU~~<br>~~(RO~~|~~(RU~~<br>~~ns~~<br>~~(RU~~<br>~~(~~|~~ns~~|ns<br>~~ns~~|1<br>~~ns~~|
|tDIS.SDIO, SDIO Output Disable Time<br>~~ns~~|~~nD~~<br>~~ns~~<br>~~nD~~|~~(RU~~<br>~~ns~~<br>~~(RO~~|~~(RU~~<br>~~ns~~<br>~~(~~|18.5<br>~~ns~~|ns<br>~~ns~~|1<br>~~ns~~|
**Table 7. 3-Wire SPI Timing Characteristics (24-MHz Operation)**
- **Notes:** 1. Based on characterization of 5 parts over temperature and voltage as mounted on evaluation board or in sockets
**==> picture [475 x 149] intentionally omitted <==**
**----- Start of picture text -----**<br>
CS 70%<br>30%<br>tFall tRise tHD;CS<br>tSU;CS tHIGH 1/fCLK<br>SCLK 70%<br>30%<br>tSU;SDIO tHD;SDIO tLOW<br>! = |<br>I 70% MSB IN LSB IN<br>30%<br>tVD;SDIO tHD;SDIO i: tDIS;SDIO<br>O 70%<br>MSB OUT LSB OUT<br>30%<br>a TD Si CaasGas<br>SDIO<br>**----- End of picture text -----**<br>
**Figure 3. 3-Wire SPI Bus Timing Diagram**
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_**ICM-42670-P**_
## **ABSOLUTE MAXIMUM RATINGS**
Stresses above those listed as “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to the absolute maximum ratings conditions for extended periods may affect device reliability.
|**PARAMETER**|**RATING**|
|---|---|
|Supply Voltage, VDD|-0.5V to 4V|
|Supply Voltage, VDDIO|-0.5V to 4V|
|Input Voltage Level (FSYNC, SCL, SDA)|-0.5V to VDDIO + 0.5 V|
|Acceleration (Any Axis, unpowered)|20,000g for 0.2 ms|
|Operating Temperature Range|-40°C to +85°C|
|Storage Temperature Range|-40°C to +125°C|
|Electrostatic Discharge (ESD) Protection|2 kV (HBM);<br>500V (CDM)|
|Latch-up|JEDEC Class II (2),125°C<br>±100 mA|
**Table 8. Absolute Maximum Ratings**
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_**ICM-42670-P**_
## _**APPLICATIONS INFORMATION**_
## **PIN OUT DIAGRAM AND SIGNAL DESCRIPTION**
|**PIN NUMBER**|**PIN NAME**|**PIN DESCRIPTION**|
|---|---|---|
|1|AP_SDO / AP_AD0|AP_SDO: AP SPI serial data output (4-wire mode);<br>AP_AD0: AP I3CSM /I2C slave address LSB|
|2|RESV|No Connect or Connect to GND or Connect to VDDIO|
|3|RESV|No Connect or Connect to GND or Connect to VDDIO|
|4|INT1 / INT|INT1: Interrupt 1 (Note: INT1 can be push-pull or open drain)<br>INT: All interrupts mapped topin 4|
|5|VDDIO|IO power supply voltage|
|6|GND|Power supply ground|
|7|FSYNC|Frame sync input; Connect to GND if FSYNC not used|
|8|VDD|Power supply voltage|
|9|INT2|INT2: Interrupt 2 (Note: INT2 can be push-pull or open drain)|
|10|RESV|No Connect or Connect to GND or Connect to VDDIO|
|11|RESV|No Connect or Connect to GND or Connect to VDDIO|
|12|AP_CS|AP SPI Chip select (AP SPI interface); Connect to VDDIO if using AP<br>I3CSM /I2C interface|
|13|AP_SCL / AP_SCLK|AP_SCL: AP I3CSM/ I2C serial clock; AP_SCLK: AP SPI serial clock|
|14|AP_SDA / AP_SDIO /<br>AP_SDI|AP_SDA: AP I3CSM/ I2C serial data; AP_SDIO: AP SPI serial data I/O<br>(3-wire mode); AP_SDI: AP SPI serial data input (4-wire mode)|
**Table 9. Signal Descriptions**
**==> picture [376 x 238] intentionally omitted <==**
**----- Start of picture text -----**<br>
AP_SDO / AP_AD0 1 11 RESV +Z<br>RESV 2 10 RESV<br>ICM-42670-P <5 +Z +Y<br>RESV 3 9 INT2<br>; +Y<br>INT1 / INT 4 8 VDD<br>+X +X<br>AP_SCL / AP_SCLK AP_CS<br>14<br>VDDIO GND FSYNC<br>AP_SDA / AP_SDIO / AP_SDI<br>13 12<br>5 6 7<br>**----- End of picture text -----**<br>
**Figure 4. Pin Out Diagram for ICM-42670-P 2.5x3.0x0.76 mm LGA**
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_**ICM-42670-P**_
**TYPICAL OPERATING CIRCUIT**
**==> picture [275 x 194] intentionally omitted <==**
**----- Start of picture text -----**<br>
VDDIO<br>14 13 12<br>AP_AD0 1 11 RESV<br>RESV 2 10 RESV<br>ICM-42670-P INT2<br>RESV 3 9<br> – 3.6VDC<br>INT1 / INT 4 8 VDD<br>5 6 7<br>C1, 0.1 mF C2, 2.2 mF<br> – 3.6VDC<br>th.<br>C3, 10 nF<br>AP<br>_<br>AP_SDA SCL<br>VDDIO GND FSYNC<br>**----- End of picture text -----**<br>
**Figure 5. ICM-42670-P Application Schematic (I3C[SM] / I[2] C Interface to Host)**
**Note** : I[2] C lines are open drain and pull-up resistors (e.g. 10 kΩ) are required.
**==> picture [272 x 194] intentionally omitted <==**
**----- Start of picture text -----**<br>
AP_CS<br>14 13 12<br>AP_SDO 1 11 RESV<br>RESV 2 10 RESV<br>ICM-42670-P INT2<br>RESV 3 9<br> – 3.6VDC<br>INT1 / INT 4 8 VDD<br>5 6 7<br>C1, 0.1 mF C2, 2.2 mF<br> – 3.6VDC<br>fh<br>C3, 10 nF<br>AP<br>_<br>AP_SDI AP_SDIO / SCLK<br>VDDIO GND FSYNC<br>**----- End of picture text -----**<br>
**Figure 6. ICM-42670-P Application Schematic (SPI Interface to Host)**
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_**ICM-42670-P**_
## **BILL OF MATERIALS FOR EXTERNAL COMPONENTS**
|**COMPONENT**|**LABEL**|**SPECIFICATION**|**QUANTITY**|
|---|---|---|---|
|VDD Bypass Capacitors|C1<br>C2|X7R, 0.1µF ±10%<br>X7R, 2.2µF ±10%|1<br>1|
|VDDIO Bypass Capacitor|C3|X7R, 10nF ±10%|1|
## **Table 10. Bill of Materials**
## 4.4 **SYSTEM BLOCK DIAGRAM**
## **Figure 7. ICM-42670-P System Block Diagram**
**Note** : The above block diagram is an example. Please refer to the pin-out (section 4.1) for other configuration options.
## **OVERVIEW**
The ICM-42670-P is comprised of the following key blocks and functions:
- Three-axis MEMS gyroscope
- Three-axis MEMS accelerometer
- I3C[SM] , I[2] C, and SPI serial communications interfaces to Host
- Self-Test
- Sensor Data Registers
- FIFO
- Interrupts
- Digital-Output Temperature Sensor
- Bias and LDOs
- Charge Pump
- Standard Power Modes
## **THREE-AXIS MEMS GYROSCOPE**
The ICM-42670-P includes a vibratory MEMS rate gyroscope, which detects rotation about the X-, Y-, and Z- Axes. When the gyroscope is rotated about any of the sense axes, the Coriolis Effect causes a vibration that is detected by a capacitive pickoff. The resulting signal is amplified, demodulated, and filtered to produce a voltage that is proportional to the angular rate. This voltage is digitized using on-chip Analog-to-Digital Converter (ADC) to sample each axis. The full-scale range of the gyro sensor may be digitally programmed to ±250, ±500, ±1000, and ±2000 degrees per second (dps).
## **THREE-AXIS MEMS ACCELEROMETER**
The ICM-42670-P includes a 3-Axis MEMS accelerometer. Acceleration along a particular axis induces displacement of a proof mass in the MEMS structure, and capacitive sensors detect the displacement. The ICM-42670-P architecture reduces the accelerometers’ susceptibility to fabrication variations as well as to thermal drift. When the device is placed on a flat surface, it will measure 0 _g_ on the X- and Y-axes and +1 _g_ on the Z-axis. The accelerometers’ scale factor is calibrated at the factory and is nominally independent of supply voltage. The fullscale range of the digital output can be adjusted to ±2 _g_ , ±4 _g_ , ±8 _g_ and ±16 _g_ .
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_**ICM-42670-P**_
## **I3C[SM] , I[2] C AND SPI HOST INTERFACE**
The ICM-42670-P communicates to the application processor using an I3C[SM] , I[2] C, or SPI serial interface. The ICM42670-P always acts as a slave when communicating to the application processor.
## **SELF-TEST**
Self-test allows for the testing of the mechanical and electrical portions of the sensors. The self-test for each measurement axis can be activated by means of the gyroscope and accelerometer self-test registers. When the self-test is activated, the electronics cause the sensors to be actuated and produce an output signal. The output signal is used to observe the self-test response. The self-test response is defined as follows:
SELF-TEST RESPONSE = SENSOR OUTPUT WITH SELF-TEST ENABLED – SENSOR OUTPUT WITH SELF-TEST DISABLED
When the value of the self-test response is within the specified min/max limits, the part has passed self-test. When the self-test response exceeds the min/max values, the part is deemed to have failed self-test.
## **SENSOR DATA REGISTERS**
The sensor data registers contain the latest gyroscope, accelerometer, and temperature measurement data. They are read-only registers and are accessed via the serial interface. Data from these registers may be read any time.
## **INTERRUPTS**
Interrupt functionality is configured via the Interrupt Configuration register. Items that are configurable include the interrupt pins configuration, the interrupt latching and clearing method, and triggers for the interrupt. Items that can trigger an interrupt are (1) new data is available to be read (from the FIFO and Data registers); (2) accelerometer event interrupts; (3) FIFO watermark; (4) FIFO full. The interrupt status can be read from the Interrupt Status register.
## **DIGITAL-OUTPUT TEMPERATURE SENSOR**
An on-chip temperature sensor and ADC are used to measure the ICM-42670-P die temperature. The readings from the ADC can be read from the FIFO or the Sensor Data registers.
Temperature sensor ODR is the higher value between gyroscope and accelerometer ODR.
## **BIAS AND LDOS**
The bias and LDO section generate the internal supply and the reference voltages and currents required by the ICM-42670-P.
## 4.14 **CHARGE PUMP**
An on-chip charge pump generates the high voltage required for the MEMS oscillator.
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_**ICM-42670-P**_
## **STANDARD POWER MODES**
The following table lists the user-accessible power modes for ICM-42670-P.
|**MODE**|**NAME**|**GYRO**|**ACCEL**|
|---|---|---|---|
|1|SleepMode|Off|Off|
|2|StandbyMode|Drive On|Off|
|3|Accelerometer Low-Power Mode|Off|Duty-Cycled|
|4|Accelerometer Low-Noise Mode|Off|On|
|5|Gyroscope Low-Noise Mode|On|Off|
|6|6-Axis Low-Noise Mode|On|On|
**Table 11. Standard Power Modes for ICM-42670-P**
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_**ICM-42670-P**_
## 5 _**SIGNAL PATH**_
The following figure shows a block diagram of the signal path for ICM-42670-P.
**==> picture [475 x 192] intentionally omitted <==**
**----- Start of picture text -----**<br>
Low-Noise Mode<br>Anti-Alias 1 [st] Order<br>ADC<br>Filter (AAF) LPF<br>ODR Sensor<br>UI Interface<br>Selection Registers<br>Low-Power Mode (Accel Only)<br>Average FSR Selection<br>- a =.<br>ACCEL_MODE<br>Figure 8. ICM-42670-P Signal Path<br>The signal path starts with ADCs for the gyroscope and accelerometer. Low-Noise Mode and Low-Power Mode<br>options are available for the accelerometer and are selectable using register field ACCEL_MODE. Only Low-Noise<br>Mode is available for gyroscope.<br>**----- End of picture text -----**<br>
In Low-Noise Mode, the ADC output is sent through an Anti-Alias Filter (AAF). The AAF is a filter with fixed coefficients (not user configurable), also the AAF cannot be bypassed. The AAF is followed by a 1[st] Order Low Pass Filter (LPF) with user selectable filter bandwidth options using register fields ACCEL_UI_FILT_BW and GYRO_UI_FILT_BW.
In Low-Power Mode, the accelerometer ADC output is sent through an Average filter, with user configurable average filter setting using register field ACCEL_UI_AVG.
The output of 1[st] Order LPF in Low-Noise Mode, or Average filter in Low-Power Mode is subject to ODR selection, with user selectable ODR using register fields GYRO_ODR and ACCEL_ODR. This is followed by Full Scale Range (FSR) selection based on user configurable settings for register fields GYRO_UI_FS_SEL and ACCEL_UI_FS_SEL.
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_**ICM-42670-P**_
## 6 _**FIFO**_
The ICM-42670-P contains up to 2.25Kbyte FIFO register that is accessible via the serial interface. Shared SRAM is used for FIFO and APEX features. Default configuration of the device provides 1Kbyte FIFO and rest of the SRAM is used for APEX. User may disable APEX features to extend FIFO size to 2.25 Kbytes using register field APEX_DISABLE in register SENSOR_CONFIG3.
User can configure the FIFO Data Rate (FDR) to control the rate at which FIFO packets are written to the FIFO. Register field FDR_SEL in register FDR_CONFIG (register 0x66h in Bank MREG1) provides FDR control, based on settings for FIFO packet rate decimation factor. User must disable sensors when initializing FDR_SEL value or making changes to it.
## **PACKET STRUCTURE**
Figure 9 shows the FIFO packet structures supported in ICM-42670-P. Base data format for gyroscope and accelerometer is 16-bits per element. 20-bits data format support is included in one of the packet structures. When 20-bits data format is used, gyroscope data consists of 19-bits of actual data and the LSB is always set to 0, accelerometer data consists of 18-bits of actual data and the two lowest order bits are always set to 0. When 20bits data format is used, the only FSR settings that are operational are ±2000 dps for gyroscope and ±16g for accelerometer, even if the FSR selection register settings are configured for other FSR values. The corresponding sensitivity scale factor values are 131 LSB/dps for gyroscope and 8192 LSB/g for accelerometer.
**==> picture [490 x 308] intentionally omitted <==**
**----- Start of picture text -----**<br>
Header Header Header Header<br>(1 byte) (1 byte) (1 byte) (1 byte)<br>Accelerometer Data Gyroscope Data Accelerometer Data Accelerometer Data<br> (6 bytes) (6 bytes) (6 bytes) (6 bytes)<br>Temperature Data Temperature Data<br>(1 byte) (1 byte)<br>Gyroscope Data Gyroscope Data<br>Packet 1 Packet 2<br>(6 bytes) (6 bytes)<br>Temperature Data Temperature Data<br>(1 byte) (2 bytes)<br>TimeStamp TimeStamp<br>(2 bytes) (2 bytes)<br>Packet 3<br>20-bit Extension<br>(3 bytes)<br>Packet 4<br>**----- End of picture text -----**<br>
**Figure 9. FIFO Packet Structure**
The rest of this sub-section describes how individual data is packaged in the different FIFO packet structures.
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_**ICM-42670-P**_
**Packet 1:** Individual data is packaged in Packet 1 as shown below.
|**BYTE**|**CONTENT**|
|---|---|
|0x00|FIFO Header|
|0x01|Accel X[15:8]|
|0x02|Accel X[7:0]|
|0x03|Accel Y[15:8]|
|0x04|Accel Y[7:0]|
|0x05|Accel Z[15:8]|
|0x06|Accel Z[7:0]|
|0x07|Temperature[7:0]|
**Packet 2:** Individual data is packaged in Packet 2 as shown below.
|**BYTE**|**CONTENT**|
|---|---|
|0x00|FIFO Header|
|0x01|Gyro X[15:8]|
|0x02|Gyro X[7:0]|
|0x03|Gyro Y[15:8]|
|0x04|Gyro Y[7:0]|
|0x05|Gyro Z[15:8]|
|0x06|Gyro Z[7:0]|
|0x07|Temperature[7:0]|
**Packet 3:** Individual data is packaged in Packet 3 as shown below.
|**BYTE**|**CONTENT**|
|---|---|
|0x00|FIFO Header|
|0x01|Accel X[15:8]|
|0x02|Accel X[7:0]|
|0x03|Accel Y[15:8]|
|0x04|Accel Y[7:0]|
|0x05|Accel Z[15:8]|
|0x06|Accel Z[7:0]|
|0x07|Gyro X[15:8]|
|0x08|Gyro X[7:0]|
|0x09|Gyro Y[15:8]|
|0x0A|Gyro Y[7:0]|
|0x0B|Gyro Z[15:8]|
|0x0C|Gyro Z[7:0]|
|0x0D|Temperature[7:0]|
|0x0E|TimeStamp[15:8]|
|0x0F|TimeStamp[7:0]|
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_**ICM-42670-P**_
**Packet 4:** Individual data is packaged in Packet 4 as shown below.
|**BYTE**|**CONTENT**|**CONTENT**|
|---|---|---|
|0x00|FIFO Header||
|0x01|Accel X[19:12]||
|0x02|Accel X[11:4]||
|0x03|Accel Y[19:12]||
|0x04|Accel Y[11:4]||
|0x05|Accel Z[19:12]||
|0x06|Accel Z[11:4]||
|0x07|Gyro X[19:12]||
|0x08|Gyro X[11:4]||
|0x09|Gyro Y[19:12]||
|0x0A|Gyro Y[11:4]||
|0x0B|Gyro Z[19:12]||
|0x0C|Gyro Z[11:4]||
|0x0D|Temperature[15:8]||
|0x0E|Temperature[7:0]||
|0x0F|TimeStamp[15:8]||
|0x10|TimeStamp[7:0]||
|0x11|Accel X[3:0]|Gyro X[3:0]|
|0x12|Accel Y[3:0]|Gyro Y[3:0]|
|0x13|Accel Z[3:0]|Gyro Z[3:0]|
## **FIFO HEADER**
The following table shows the structure of the 1byte FIFO header.
|**BIT FIELD**|**ITEM**|**DESCRIPTION**|
|---|---|---|
|7|HEADER_MSG|1: FIFO is empty<br>0: Packet contains sensor data|
|6|HEADER_ACCEL|1: Packet is sized so that accel data have location in the packet, FIFO_ACCEL_EN must be 1<br>0: Packet does not contain accel sample|
|5|HEADER_GYRO|1: Packet is sized so that gyro data have location in the packet, FIFO_GYRO_EN must be 1<br>0: Packet does not containgyro sample|
|4|HEADER_20|1: Packet has a new and valid sample of extended 20-bit data for gyro and/or accel<br>0: Packet does not contain a new and valid extended 20-bit data|
|3:2|HEADER_TIMESTAMP_FSYNC|00: Packet does not contain timestamp or FSYNC time data<br>01: Reserved<br>10: Packet contains ODR Timestamp<br>11: Packet contains FSYNC time, and this packet is flagged as first ODR after FSYNC (only if<br>FIFO_TMST_FSYNC_EN is 1)|
|1|HEADER_ODR_ACCEL|1: The ODR for accel is different for this accel data packet compared to the previous accel<br>packet<br>0: The ODR for accel is the same as thepreviouspacket with accel|
|0|HEADER_ODR_GYRO|1: The ODR for gyro is different for this gyro data packet compared to the previous gyro<br>packet<br>0: The ODR forgyro is the same as thepreviouspacket withgyro|
Note at least HEADER_ACCEL or HEADER_GYRO must be set for a sensor data packet to be set.
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The maximum number of packets that can be stored in FIFO is a variable quantity depending on the use case. As shown in Figure 10, the physical FIFO size is 1 Kbytes or 2.25 Kbytes (depending on APEX_DISABLE setting as described above). A number of bytes equal to the packet size selected (see section 6.1) is reserved to prevent reading a packet during write operation. Additionally, a read cache 2 packets wide is available.
The total storage available is up to the maximum number of packets that can be accommodated in 1 Kbytes (or 2.25 Kbytes) plus 40 cache bytes. Note: the cache can hold 5 packets instead of 2 in the specific case when the packet size is 8bytes and the FIFO mode is Stop-on-full.
**==> picture [66 x 9] intentionally omitted <==**
**----- Start of picture text -----**<br>
2 Packet Size<br>**----- End of picture text -----**<br>
Read Cache 1Kbytes or 2.25Kbytes – packet size
**MAXIMUM FIFO STORAGE** The maximum number of packets that can be stored in FIFO is a variable quantity depending on the use case. As shown in Figure 10, the physical FIFO size is 1 Kbytes or 2.25 Kbytes (depending on APEX_DISABLE setting as described above). A number of bytes equal to the packet size selected (see section 6.1) is reserved to prevent reading a packet during write operation. Additionally, a read cache 2 packets wide is available. The total storage available is up to the maximum number of packets that can be accommodated in 1 Kbytes (or 2.25 Kbytes) plus 40 cache bytes. Note: the cache can hold 5 packets instead of 2 in the specific case when the packet size is 8bytes and the FIFO mode is Stop-on-full. FIFO 1Kbytes or 2.25Kbytes 1Kbytes or 2.25Kbytes – packet size 1 Packet Size Reserved to prevent reading a packet during write operation **Figure 10. Maximum FIFO Storage** ~~[_—]~~ Page 27 of 102 Document Number: DS-000451 Revision: 1.0
_**ICM-42670-P**_
## 7 _**PROGRAMMABLE INTERRUPTS**_
The ICM-42670-P has a programmable interrupt system that can generate an interrupt signal on the INT pins. Status flags indicate the source of an interrupt. Interrupt sources may be enabled and disabled individually. There are two interrupt outputs. Any interrupt may be mapped to either interrupt pin as explained in the register section. The following configuration options are available for the interrupts
- INT1 and INT2 can be push-pull or open drain
- Level or pulse mode
- Active high or active low
Additionally, ICM-42670-P includes In-band Interrupt (IBI) support for the I3C[SM] interface.
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## 8 _**APEX MOTION FUNCTIONS**_
The APEX ( **A** dvanced **P** edometer and **E** vent Detection – ne **X** t gen) features of ICM-42670-P consist of:
- Pedometer: Tracks step count and issues a step detect Interrupt.
- Tilt Detection: Issues an interrupt when the Tilt angle exceeds 35 degrees for more than a programmable time.
- Low-g Detection: Triggers an interrupt when absolute value of accelerometer combined axis falls below a programmable threshold and stays below the threshold for a programmable time.
- Freefall Detection: Triggers an interrupt when device freefall is detected and outputs freefall duration.
- Wake on Motion (WoM): Detects motion when accelerometer samples exceed a programmable threshold. This motion event can be used to enable device operation from sleep mode.
- Significant Motion Detector (SMD): Detects significant motion based on accelerometer data.
Shared SRAM is used for FIFO and APEX features. Default configuration of the device provides 1Kbyte FIFO and rest of the SRAM is used for APEX. User may disable APEX features to extend FIFO size to 2.25 Kbytes using register field APEX_DISABLE in register SENSOR_CONFIG3.
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## 9 _**DIGITAL INTERFACE**_
## **I3C[SM] , I[2] C AND SPI SERIAL INTERFACES**
The internal registers and memory of the ICM-42670-P can be accessed using I3C[SM] at 12.5 MHz (data rates up to 12.5 Mbps in SDR mode, 25 Mbps in DDR mode), I[2] C at 1 MHz or SPI at 24 MHz. SPI operates in 3-wire or 4-wire mode. Pin assignments for serial interfaces are described in Section 4.1.
## **I3C[SM] INTERFACE**
I3C[SM] is a new 2-wire digital interface comprised of the signals serial data (SDA) and serial clock (SCLK). I3C[SM] is intended to improve upon the I[2] C interface, while preserving backward compatibility. The I3C[SM] capability of this device is compliant with Version 1.0 of the MIPI Alliance Specification for I3C[SM] .
I3C[SM] carries the advantages of I²C in simplicity, low pin count, easy board design, and multi-drop (vs. point to point), but provides the higher data rates, simpler pads, and lower power of SPI. I3C[SM] adds higher throughput for a given frequency, in-band interrupts (from slave to master), dynamic addressing.
ICM-42670-P supports the following features of I3C[SM] :
- SDR data rate up to 12.5 Mbps
- DDR data rate up to 25 Mbps
- Dynamic address allocation
- In-band Interrupt (IBI) support
- Support for asynchronous timing control mode 0
- Error detection (CRC and/or Parity)
- Common Command Code (CCC)
The ICM-42670-P always operates as an I3C[SM] slave device when communicating to the system processor, which thus acts as the I3C[SM] master. I3C[SM] master controls an active pullup resistance on SDA, which it can enable and disable. The pullup resistance may be a board level resistor controlled by a pin, or it may be internal to the I3C[SM] master.
The following table shows I3C[SM] Common Command Code (CCC) commands supported by the device.
|**CCC Description**|**Required or**<br>**Optional per I3C**<br>**v1.0**|**Supported by**<br>**ICM-42670-P**|
|---|---|---|
|1<br>ENEC, broadcast mode. (Enable Events)<br>~~a~~|Required<br>~~a~~|Yes<br>~~a~~|
|2<br>DISEC, broadcast mode. (Disable Events)<br>~~a~~|Required<br>~~a~~|Yes<br>~~a~~|
|3<br>ENTAS0, broadcast mode. (Enter Activity State 0)<br>~~a~~|Required<br>~~a~~|Yes<br>~~a~~|
|4<br>ENTAS1, broadcast mode. (Enter ActivityState 1)<br>~~a~~|Optional<br>~~a~~|No<br>~~a~~|
|5<br>ENTAS2, broadcast mode. (Enter ActivityState 0)<br>~~a~~|Optional<br>~~a~~|No<br>~~a~~|
|6<br>ENTAS3, broadcast mode. (Enter Activity State 0)<br>~~a~~|Optional<br>~~a~~|No<br>~~a~~|
|7<br>RSTDAA, broadcast mode. (Reset dynamic address assignment)<br>~~a~~|Required<br>~~a~~|Yes<br>~~a~~|
|8<br>ENTDAA, broadcast mode. (Enter dynamic address assignment)<br>~~a~~|Required<br>~~a~~|Yes<br>~~a~~|
|9<br>DEFSLVS, broadcast mode. (Define list of slaves)<br>~~ee~~|Optional<br>~~ee~~|No<br>~~ee~~|
|10<br>SETMWL, broadcast mode. (Set Max Write Length)<br>~~a~~|Required<br>~~a~~|Yes<br>~~a~~|
|11<br>SETMRL, broadcast mode. (Set Max Read Length)<br>~~a~~|Required<br>~~a~~|Yes<br>~~a~~|
|12<br>ENTTM, broadcast mode. (Enter Test Mode)<br>~~a~~|Optional<br>~~a~~|No<br>~~a~~|
|13<br>ENTHDR0, broadcast mode. (Enter HDR DDR mode)<br>~~a~~|Optional<br>~~a~~|Yes<br>~~a~~|
|14<br>ENTHDR1, broadcast mode. (Enter HDR TSP mode)<br>~~a~~|Optional<br>~~a~~|No<br>~~a~~|
|15<br>ENTHDR2, broadcast mode. (Enter HDR TSL mode)<br>~~a~~|Optional<br>~~a~~|No<br>~~a~~|
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|<br>**_ICM-42670-P_**<br>TDK InvenSense|<br>**_ICM-42670-P_**<br>TDK InvenSense|<br>**_ICM-42670-P_**<br>TDK InvenSense|
|---|---|---|
|16<br>SETXTIME, broadcast mode. (Exchange TimingInformation)|||
|16.1<br>Definingbyte = 0x7F (ST)|Optional|No|
|16.2<br>Definingbyte = 0xBF (DT)|Optional|No|
|16.3<br>Definingbyte = 0xDF (Enter Async Mode 0)|Optional|Yes|
|16.4<br>Definingbyte = 0xEF (Enter Async Mode 1)|Optional|No|
|16.5<br>Definingbyte = 0xF7 (Enter Async Mode 2)|Optional|No|
|16.6<br>Definingbyte = 0xFB (Enter Async Mode 3)|Optional|No|
|16.7<br>Defining byte = 0xFD (Async Trigger for Async Mode<br>3)|Optional|No|
|16.8<br>Definingbyte = 0x3F (TPH)|Optional|No|
|16.9<br>Definingbyte = 0x9f (TU)|Optional|No|
|16.10<br>Definingbyte = 0x8F (ODR)|Optional|No|
|16.11<br>Defining byte = 0xff (disable all timing control<br>function)|Optional|Yes|
|17<br>ENEC, direct mode. (Enable Events)|Required|Yes|
|18<br>DISEC, direct mode. (Disable Events)|Required|Yes|
|19<br>ENTAS0, direct mode. (Enter Activity State 0)|Required|Yes|
|20<br>ENTAS1, direct mode. (Enter ActivityState 1)|Optional|No|
|21<br>ENTAS2, direct mode. (Enter ActivityState 2)|Optional|No|
|22<br>ENTAS3, direct mode. (Enter Activity State 3)|Optional|No|
|23<br>RSTDAA, direct mode. (Reset dynamic address assignment)|Required|Yes|
|24<br>SETDASA, direct mode. (Set Dynamic address from static<br>address)|Optional|Yes|
|25<br>SETNEWDA, direct mode. (Set new dynamic address)|Required|Yes|
|26<br>SETMWL, direct mode. (Set Max Write Length)|Required|Yes|
|27<br>SETMRL, direct mode. (Set Max Read length)|Required|Yes|
|28<br>GETMWL, direct mode. (Get Max write length)|Required|Yes|
|29<br>GETMRL, direct mode. (Get Max Read length)|Required|Yes|
|30<br>GETPID, direct mode. (Getprovisional ID)|Required|Yes|
|31<br>GETBCR, direct mode. (Get Bus Characteristics Register)|Required|Yes|
|32<br>GETDCR, direct mode. (Get Device Characteristics Register)|Required|Yes|
|33<br>GETSTATUS, direct mode. (Get Device Status)|Required|Yes|
|34<br>GETACCMST, direct mode. (Get Accept Mastership)|Optional|No|
|35<br>SETBRGTGT, direct mode. (Set Bridge Targets)|Optional|No|
|36<br>GETMXDS, direct mod. (Get Max Data Speed)|Optional|Yes|
|37<br>GETHDRCAP, direct mode. (Get HDR capability)|Optional|Yes|
|38<br>SETXTIME, direct mode. (Set Exchange Timinginformation)|||
|38.1<br>Definingbyte = 0x7F (ST)|Optional|No|
|38.2<br>Definingbyte = 0xBF (DT)|Optional|No|
|38.3<br>Definingbyte = 0xDF (Enter Async Mode 0)|Optional|Yes|
|38.4<br>Definingbyte = 0xEF (Enter Async Mode 1)|Optional|No|
|38.5<br>Definingbyte = 0xF7 (Enter Async Mode 2)|Optional|No|
|38.6<br>Definingbyte = 0xFB (Enter Async Mode 3)|Optional|No|
|38.7<br>Defining byte = 0xFD (Async Trigger for Async Mode<br>3)|Optional|No|
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|38.8<br>Definingbyte = 0x3F (TPH)|Optional|No|
|---|---|---|
|38.9<br>Definingbyte = 0x9f (TU)|Optional|No|
|38.10<br>Definingbyte = 0x8F (ODR)|Optional|No|
|38.11<br>Defining byte = 0xff (disable all timing control<br>function)|Optional|Yes|
|39<br>GETXTIME, direct mode. (Get Exchange TimingInformation)|Optional|Yes|
## **Table 12. I3C[SM] CCC Commands**
## **I[2] C INTERFACE**
I[2] C is a two-wire interface comprised of the signals serial data (SDA) and serial clock (SCL). In general, the lines are open-drain and bi-directional. In a generalized I[2] C interface implementation, attached devices can be a master or a slave. The master device puts the slave address on the bus, and the slave device with the matching address acknowledges the master.
The ICM-42670-P always operates as a slave device when communicating to the system processor, which thus acts as the master. SDA and SCL lines typically need pull-up resistors to VDDIO. The maximum bus speed is 1 MHz.
The slave address of the ICM-42670-P is b110100X, which is 7 bits long. The LSB bit of the 7-bit address is determined by the logic level on pin AP_AD0. This allows two ICM-42670-Ps to be connected to the same I[2] C bus. When used in this configuration, the address of one of the devices should be b1101000 (pin AP_AD0 is logic low) and the address of the other should be b1101001 (pin AP_AD0 is logic high).
## 9.4 **I[2] C COMMUNICATIONS PROTOCOL**
## _START (S) and STOP (P) Conditions_
Communication on the I[2] C bus starts when the master puts the START condition (S) on the bus, which is defined as a HIGH-to-LOW transition of the SDA line while SCL line is HIGH (see figure below). The bus is considered to be busy until the master puts a STOP condition (P) on the bus, which is defined as a LOW to HIGH transition on the SDA line while SCL is HIGH (see Figure 11).
Additionally, the bus remains busy if a repeated START (Sr) is generated instead of a STOP condition.
**==> picture [360 x 79] intentionally omitted <==**
**----- Start of picture text -----**<br>
SDA<br>| |<br>SCL<br>S P<br>| | “—_Y \—_/ ||<br>START condition STOP condition<br>**----- End of picture text -----**<br>
**Figure 11. START and STOP Conditions**
## _Data Format / Acknowledge_
I[2] C data bytes are defined to be 8-bits long. There is no restriction to the number of bytes transmitted per data transfer. Each byte transferred must be followed by an acknowledge (ACK) signal. The clock for the acknowledge signal is generated by the master, while the receiver generates the actual acknowledge signal by pulling down SDA and holding it low during the HIGH portion of the acknowledge clock pulse.
If a slave is busy and cannot transmit or receive another byte of data until some other task has been performed, it can hold SCL LOW, thus forcing the master into a wait state. Normal data transfer resumes when the slave is ready and releases the clock line (refer to Figure 12).
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**==> picture [398 x 146] intentionally omitted <==**
**----- Start of picture text -----**<br>
DATA OUTPUT BY<br>TRANSMITTER (SDA)<br>N L OOK<br>not acknowledge<br>DATA OUTPUT BY<br>RECEIVER (SDA)<br>+a, acknowledge<br>7<br>SCL FROM<br>1 2 8 9<br>MASTER<br>clock pulse for<br>START acknowledgement<br>condition<br>**----- End of picture text -----**<br>
**Figure 12. Acknowledge on the I[2] C Bus**
## _Communications_
After beginning communications with the START condition (S), the master sends a 7-bit slave address followed by an 8[th] bit, the read/write bit. The read/write bit indicates whether the master is receiving data from or is writing to the slave device. Then, the master releases the SDA line and waits for the acknowledge signal (ACK) from the slave device. Each byte transferred must be followed by an acknowledge bit. To acknowledge, the slave device pulls the SDA line LOW and keeps it LOW for the high period of the SCL line. Data transmission is always terminated by the master with a STOP condition (P), thus freeing the communications line. However, the master can generate a repeated START condition (Sr), and address another slave without first generating a STOP condition (P). A LOW to HIGH transition on the SDA line while SCL is HIGH defines the stop condition. All SDA changes should take place when SCL is low, with the exception of start and stop conditions.
**==> picture [396 x 110] intentionally omitted <==**
**----- Start of picture text -----**<br>
SDA<br>SCL 1 – 7 8 9 1 – 7 8 9 1 – 7 8 9<br>V S A V AVAWA V AVAUU A VAUE : P<br>START ee ADDRESS R/W ACK DATA | ACK ee ee DATA | ACK ee STOP<br>condition condition<br>**----- End of picture text -----**<br>
**Figure 13. Complete I[2] C Data Transfer**
To write the internal ICM-42670-P registers, the master transmits the start condition (S), followed by the I[2] C address and the write bit (0). At the 9[th] clock cycle (when the clock is high), the ICM-42670-P acknowledges the transfer. Then the master puts the register address (RA) on the bus. After the ICM-42670-P acknowledges the reception of the register address, the master puts the register data onto the bus. This is followed by the ACK signal, and data transfer may be concluded by the stop condition (P). To write multiple bytes after the last ACK signal, the master can continue outputting data rather than transmitting a stop signal. In this case, the ICM-42670-P automatically increments the register address and loads the data to the appropriate register. The following figures show single and two-byte write sequences.
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## _Single-Byte Write Sequence_
|Master|S|AD+W||||RA||||DATA||||P||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|Slave||||ACK||||ACK||||ACK||||||
|_Burst Write Sequence_||||||||||||||||||
|Master|S|AD+W||||RA||||DATA|||DATA||||P|
|Slave||||ACK||||ACK|||ACK|||||ACK||
## _Burst Write Sequence_
To read the internal ICM-42670-P registers, the master sends a start condition, followed by the I[2] C address and a write bit, and then the register address that is going to be read. Upon receiving the ACK signal from the ICM42670-P, the master transmits a start signal followed by the slave address and read bit. As a result, the ICM-42670P sends an ACK signal and the data. The communication ends with a not acknowledge (NACK) signal and a stop bit from master. The NACK condition is defined such that the SDA line remains high at the 9[th] clock cycle. The following figures show single and two-byte read sequences.
## _Single-Byte Read Sequence_
||Master|S|AD+W|||RA||||S|S|AD+R||||||NACK|NACK|P||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
||Slave|||ACK||||ACK||||||ACK||DATA||||||||
|_Burst Read Sequence_||||||||||||||||||||||||
||Master|S|AD+W|||RA||||S||AD+R|||||ACK|||||NACK|P|
||Slave|||ACK||||ACK|||||ACK||DATA||||DATA|||||
## **I[2] C TERMS**
|**SIGNAL**|**DESCRIPTION**|
|---|---|
|S|Start Condition: SDAgoes from high to low while SCL is high|
|AD|Slave I2C address|
|W|Write bit(0)|
|R|Read bit(1)|
|ACK|Acknowledge: SDA line is low while the SCL line is high at the 9thclock cycle|
|NACK|Not-Acknowledge: SDA line stays high at the 9thclock cycle|
|RA|ICM-42670-P internal register address|
|DATA|Transmit or received data|
|P|Stopcondition: SDAgoingfrom low to high while SCL is high|
**Table 13. I[2] C Terms**
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## **SPI INTERFACE**
The ICM-42670-P supports 3-wire or 4-wire SPI for the host interface. The ICM-42670-P always operates as a Slave device during standard Master-Slave SPI operation.
With respect to the Master, the Serial Clock output (SCLK), the Serial Data Output (SDO), the Serial Data Input (SDI), and the Serial Data IO (SDIO) are shared among the Slave devices. Each SPI slave device requires its own Chip Select (CS) line from the master.
CS goes low (active) at the start of transmission and goes back high (inactive) at the end. Only one CS line is active at a time, ensuring that only one slave is selected at any given time. The CS lines of the non-selected slave devices are held high, causing their SDO lines to remain in a high-impedance (high-z) state so that they do not interfere with any active devices.
## _SPI Operational Features_
1. Data is delivered MSB first and LSB last
2. Data is latched on the rising edge of SCLK
3. Data should be transitioned on the falling edge of SCLK
4. The maximum frequency of SCLK is 24 MHz
5. SPI read and write operations are completed in 16 or more clock cycles (two or more bytes). The first byte contains the Register Address, and the following byte(s) contain(s) the SPI data. The first bit of the first byte contains the Read/Write bit and indicates the Read (1) operation. The following 7 bits contain the Register Address. In cases of multiple-byte Reads, data is two or more bytes:
|_Register Address format_|_Register Address format_|_Register Address format_|_Register Address format_|_Register Address format_||||
|---|---|---|---|---|---|---|---|
|**MSB**|||||||**LSB**|
|R/W|A6|A5|A4|A3|A2|A1|A0|
|_SPI Data format_||||||||
|**MSB**|||||||**LSB**|
|D7|D6|D5|D4|D3|D2|D1|D0|
6. Supports Single or Burst Read/Writes.
**==> picture [190 x 118] intentionally omitted <==**
**----- Start of picture text -----**<br>
SCLK<br>SDIO<br>SPI Master SPI Slave 1<br>CS1 nCS<br>CS2<br>SCLK<br>SDIO<br>SPI Slave 2<br>nCS<br>**----- End of picture text -----**<br>
**Figure 14. Typical SPI Master/Slave Configuration**
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## 10 _**ASSEMBLY**_
This section provides general guidelines for assembling Micro Electro-Mechanical Systems (MEMS) devices packaged in LGA package.
## **ORIENTATION OF AXES**
The diagram below shows the orientation of the axes of sensitivity and the polarity of rotation. Note the pin 1 identifier (•) in the figure.
**==> picture [77 x 109] intentionally omitted <==**
**----- Start of picture text -----**<br>
+Z<br>+Z +Y<br>RY +Y<br>+X +X<br>**----- End of picture text -----**<br>
**Figure 15. Orientation of Axes of Sensitivity and Polarity of Rotation**
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_**ICM-42670-P**_
## **PACKAGE DIMENSIONS**
14 Lead LGA (2.5x3x0.76) mm NiAu pad finish
|~~a~~|**SYMBOLS**<br>~~ee~~|**DIMENSIONS IN MILLIMETERS**<br>~~eee~~|**DIMENSIONS IN MILLIMETERS**<br>~~eee~~|**DIMENSIONS IN MILLIMETERS**<br>~~eee~~|
|---|---|---|---|---|
|||**MIN**<br>~~eee~~|**NOM**<br>~~eee~~|**MAX**<br>~~eee~~|
|**Total Thickness**<br>~~a~~<br>~~RD~~<br>~~RD~~|**A**<br>~~ee~~<br>~~RD~~<br>~~PO~~<br>|0.71<br>~~eee~~<br>~~RD~~<br>|0.76<br>~~eee~~<br>~~RD~~<br>|0.81<br>~~eee~~<br>~~RD~~<br>|
|**Substrate Thickness**<br>~~RD~~<br>~~es~~|**c**<br>~~PO~~<br>~~**QO**~~|0.1 REF<br>~~**QO**~~|||
|**Mold Thickness**<br>~~RD ~~<br>~~es~~|**A3**<br>~~PO~~<br> ~~**QO**~~|0.65 REF<br>~~**QO**~~|||
|**Body Size**<br> <br>~~es~~<br>~~EEE~~|**E**<br> ~~**QO**~~<br>~~EEE~~|2.45<br>~~**QO**~~<br>~~EEE~~<br>~~es~~|2.50<br>~~**QO**~~<br>~~EEE~~<br>~~ee~~|2.55<br>~~**QO**~~<br>~~EEE~~|
||**D**<br>~~EEE~~<br>~~ee~~|2.95<br>~~EEE~~<br>~~ee~~<br>~~es~~|3.00<br>~~EEE~~<br>~~ee~~<br>~~ee~~|3.05<br>~~EEE~~<br>~~ee~~|
|**Lead Width**<br>~~es~~|**b**<br>~~es~~|0.20<br>~~es ~~<br>~~es~~|0.25<br> ~~ee~~<br>~~es~~|0.30<br>~~es~~|
|**Lead Length**<br>~~a~~<br>~~es~~|**L3**<br>~~QO~~|0.425<br>~~QO~~|0.475<br>~~QO~~|0.525<br>~~QO~~|
|**Lead Pitch**<br>~~es~~|**e**<br>~~QO~~|0.5<br>~~QO~~|||
|**Lead Count**<br>~~es~~<br>~~a~~|~~QO~~|14<br>~~QO~~|||
|**Edge Pin Center to Center**|**e*3**<br>~~ee~~|1.5<br>~~ee~~|||
||**e*2**<br>~~ee~~|1<br>~~ee~~|||
|**Body Center to Contact Pin**<br>~~Rs~~|**e/2 **<br>~~Rs~~|0.25<br>~~Rs~~|||
|**Package Edge Tolerance**<br>~~es~~<br>~~ee~~|~~es~~<br>~~GO~~|0.05<br>~~es~~<br>~~GO~~|||
|**Pad-End to Package Tolerance**<br>~~ee~~|~~GO~~|0.05<br>~~GO~~|0.1<br>~~GO~~|0.15|
|**Mold Flatness**<br>~~ee~~<br>~~QO~~|~~GO~~<br>~~QO~~|~~GO~~<br>~~QO~~|~~GO~~<br>~~QO~~|0.1<br>~~QO~~|
|**Coplanarity**<br>~~es~~|~~es~~|~~es~~|~~es~~|0.08<br>~~es~~|
Page 37 of 102
Document Number: DS-000451 Revision: 1.0
_**ICM-42670-P**_
## _**PART NUMBER PACKAGE MARKING**_
The part number package marking for ICM-42670-P devices is summarized below:
**==> picture [367 x 210] intentionally omitted <==**
**----- Start of picture text -----**<br>
PART NUMBER PART NUMBER PACKAGE MARKING<br>ICM-42670-P I460P<br>TOP VIEW<br>Part Number I460P<br>Lot Traceability Code X X X X X X<br> YYWW<br>Y Y = Year Code<br>W W = Work Week<br>**----- End of picture text -----**<br>
Page 38 of 102
Document Number: DS-000451 Revision: 1.0
_**ICM-42670-P**_
## 12 _**USE NOTES**_
## **GYROSCOPE POWER ON TO POWER OFF TRANSITION**
After powering the gyroscope off, a period of > 20ms should be allowed to elapse before it is powered back on.
Page 39 of 102
Document Number: DS-000451 Revision: 1.0
_**ICM-42670-P**_
## _**ACCESSING MREG1, MREG2 AND MREG3 REGISTERS**_
The following procedure must be used to access registers in user banks MREG1, MREG2, and MREG3.
MREG1, MREG2, and MREG3 registers are accessed indirectly, using the following registers in Bank 0 (_W registers for Write, _R registers for Read)
- BLK_SEL_W
- MADDR_W
- M_W
- BLK_SEL_R
- MADDR_R
- M_R
For MREG1 write access, BLK_SEL_W must be set to 0x00. For MREG2 write access, BLK_SEL_W must be set to 0x28. For MREG3 write access, BLK_SEL_W must be set to 0x50.
For MREG1 read access, BLK_SEL_R must be set to 0x00. For MREG2 read access, BLK_SEL_R must be set to 0x28. For MREG3 read access, BLK_SEL_R must be set to 0x50.
User must ensure BLK_SEL_W and BLK_SEL_R are set to 0x00 after completing MREG1, MREG2, or MREG3 access.
Example: To write a value to an MREG1 register at address 0x14 use the following steps:
- BLK_SEL_W must be set to 0
- MADDR_W must be set to 0x14 (address of the MREG1 register being accessed)
- M_W must be set to the desired value
- Wait for 10 µs
Example: To read the value of an MREG1 register at address 0x14 use the following steps:
- BLK_SEL_R must be set to 0
- MADDR_R must be set to 0x14 (address of the MREG1 register being accessed)
- • Wait for 10µs
- Read register M_R to access the value in MREG1 register 0x14
- Wait for 10 µs
Host must not access any other register for 10 µs once MREG1, MREG2 or MREG3 access is kicked off.
Additionally, please note the following for MREG1, MREG2 or MREG3 register accesses:
- User must check that register field MCLK_RDY is at value 1, to confirm that internal clock is running before initiating MREG register access.
- MREG1, MREG2, or MREG3 read and write operations cannot happen in all power modes. Sleep mode, and Accelerometer low power mode with WUOSC do not support MREG1, MREG2 or MREG3 access. When in sleep mode or accelerometer LP mode with WUOSC, MREG1, MREG2 or MREG3 read/write operations require the user to power on the RC oscillator using register field IDLE from register PWR_MGMT0.
- It can take up to 10 µs for MREG1, MREG2 or MREG3 read/write operations to be effective. No register access must be performed during this period
- Multiple serial protocol transactions are needed for a single data byte transfer, please refer to the examples provided.
- Data transfers through indirect access are only supported for single byte transfers and burst data transfer is not supported for read or write operations.
Page 40 of 102
Document Number: DS-000451 Revision: 1.0
_**ICM-42670-P**_
## _**REGISTER MAP**_
This section lists the register map for the ICM-42670-P, for user banks 0, MREG1, MREG2 and MREG3.
## **USER BANK 0 REGISTER MAP**
|**ADDR**<br>**(HEX)**<br>|<br>||**ADDR**<br>**(DEC)**<br>|**REGISTER NAME**<br>|**SERIAL**<br>**I/F**<br>|**BIT7**<br>|**BIT6**<br>|**BIT5**<br>|**BIT4**<br>|**BIT3**<br>|**BIT2**<br>|**BIT1**<br>|**BIT0**<br>|
|---|---|---|---|---|---|---|---|---|---|---|---|
|00<br>~~OO~~|00<br>~~OO~~|MCLK_RDY<br>~~OO~~|R<br>~~OO~~|-<br>~~OO~~||||MCLK_RDY<br>~~OO~~|-<br>~~OO~~|||
|01<br>~~a~~|01<br>~~a~~|DEVICE_CONFIG<br>~~a~~|R/W<br>~~ee~~|-<br>~~eeee~~<br>~~ee~~|||||SPI_AP_4WIR<br>E<br>~~ee~~|-<br>~~ee~~|SPI_MODE<br>~~ee~~|
|02<br>~~a~~|02<br>~~a~~|SIGNAL_PATH_RESET<br>~~a~~|R/W<br>~~ee~~|-<br>~~ee~~|||SOFT_RESET_<br>DEVICE_CON<br>FIG<br>~~ee~~|-<br>~~ee~~|FIFO_FLUSH<br>~~ee~~|-<br>~~ee~~||
|03<br>~~a~~<br>~~sO~~<br>~~es nO~~|03<br>~~a~~<br>~~sO~~<br>~~nO~~|DRIVE_CONFIG1<br>~~a~~<br>~~sO~~<br>~~nO~~|R/W<br>~~ee ~~<br>~~sO~~|-<br> ~~ee~~<br>~~sO~~<br>~~a~~||I3C_DDR_SLEW_RATE<br>~~ee ee~~<br>~~ee~~<br>~~sO~~|||I3C_SDR_SLEW_RATE<br>~~ee~~<br>~~ee~~<br>~~sO~~|||
|04<br>~~es nO~~|04<br>~~nO~~|DRIVE_CONFIG2<br>~~nO~~|R/W|-<br>~~a~~||I2C_SLEW_RATE|||ALL_SLEW_RATE|||
|05<br>~~es nO~~<br>~~Pp~~<br>~~a~~|05<br>~~nO~~<br>~~Pp~~<br>|DRIVE_CONFIG3<br>~~nO~~<br>~~Pp~~|R/W<br>~~Pp~~|-<br>~~a~~<br>~~Pp~~<br>~~tstees~~|||||SPI_SLEW_RATE<br>~~Pp~~<br>~~es~~|||
|06<br>~~es~~<br>~~a~~<br>~~es~~|06<br>~~es~~<br>~~a~~|INT_CONFIG<br>~~es~~<br>~~es~~|R/W<br>~~es~~<br>~~es~~|-<br>~~es~~||INT2_MODE<br>~~es~~<br>~~ts~~|INT2_DRIVE_<br>CIRCUIT<br>~~es~~<br>~~te~~|INT2_POLARI<br>TY<br>~~es~~<br>~~es~~|INT1_MODE<br>~~es~~<br>~~es~~|INT1_DRIVE_<br>CIRCUIT<br>~~es~~|INT1_POLARI<br>TY<br>~~es~~|
|09<br>~~a~~<br>~~es~~|09<br>~~a~~|TEMP_DATA1<br>~~es~~|R<br>~~es~~|TEMP_DATA[15:8]<br>~~tsteeses~~||||||||
|0A<br>~~a ~~<br>~~es~~<br>~~a~~|10<br> ~~a~~<br>~~re~~|TEMP_DATA0<br>~~es~~<br>~~Oa~~<br>~~es es~~|R<br>~~es~~<br>~~Oa~~<br>~~es~~|TEMP_DATA[7:0]<br>~~ts te es es~~||||||||
|0B<br> <br>~~es~~<br>~~a~~<br>~~es~~|11<br> ~~a~~<br>~~re~~|ACCEL_DATA_X1<br>~~es~~<br>~~es es~~<br>~~Oa~~|R<br>~~es~~<br>~~es~~<br>~~Oa~~|ACCEL_DATA_X[15:8]||||||||
|0C<br>~~a~~<br>~~es~~<br>~~a~~|12<br>~~re ~~<br>~~re~~|ACCEL_DATA_X0<br> ~~es es~~<br>~~Oa~~<br>~~es es~~|R<br>~~es~~<br>~~Oa~~<br>~~es~~|ACCEL_DATA_X[7:0]||||||||
|0D<br>~~es~~<br>~~a~~<br>~~es~~|13<br>~~re~~|ACCEL_DATA_Y1<br>~~Oa~~<br>~~es es~~<br>~~Oa~~|R<br>~~Oa~~<br>~~es~~<br>~~Oa~~|ACCEL_DATA_Y[15:8]||||||||
|0E<br>~~a~~<br>~~es~~<br>~~a~~|14<br>~~re ~~<br>~~re~~|ACCEL_DATA_Y0<br> ~~es es~~<br>~~Oa~~<br>~~es es~~|R<br>~~es~~<br>~~Oa~~<br>~~es~~|ACCEL_DATA_Y[7:0]||||||||
|0F<br>~~es~~<br>~~a~~<br>~~es~~|15<br>~~re~~|ACCEL_DATA_Z1<br>~~Oa~~<br>~~es es~~<br>~~Oa~~|R<br>~~Oa~~<br>~~es~~<br>~~Oa~~|ACCEL _DATA_Z[15:8]||||||||
|10<br>~~a~~<br>~~es~~<br>~~a~~|16<br>~~re ~~<br>~~re~~|ACCEL _DATA_Z0<br> ~~es es~~<br>~~Oa~~<br>~~es es~~|R<br>~~es~~<br>~~Oa~~<br>~~es~~|ACCEL _DATA_Z[7:0]||||||||
|11<br>~~es~~<br>~~a~~<br>~~es~~|17<br>~~re~~|GYRO _DATA_X1<br>~~Oa~~<br>~~es es~~<br>~~Oa~~|R<br>~~Oa~~<br>~~es~~<br>~~Oa~~|GYRO _DATA_X[15:8]||||||||
|12<br>~~a~~<br>~~es~~<br>~~a~~|18<br>~~re ~~<br>~~re~~|GYRO _DATA_X0<br> ~~es es~~<br>~~Oa~~<br>~~es es~~|R<br>~~es~~<br>~~Oa~~<br>~~es~~|GYRO _DATA_X[7:0]||||||||
|13<br>~~es~~<br>~~a~~<br>~~es~~|19<br>~~re~~|GYRO _DATA_Y1<br>~~Oa~~<br>~~es es~~<br>~~Oa~~|R<br>~~Oa~~<br>~~es~~<br>~~Oa~~|GYRO_DATA_Y[15:8]||||||||
|14<br>~~a~~<br>~~es~~<br>~~a~~|20<br>~~re ~~<br>~~re~~|GYRO _DATA_Y0<br> ~~es es~~<br>~~Oa~~<br>~~es es~~|R<br>~~es~~<br>~~Oa~~<br>~~es~~|GYRO_DATA_Y[7:0]||||||||
|15<br>~~es~~<br>~~a~~<br>~~a~~|21<br>~~re~~<br>~~a~~|GYRO_DATA_Z1<br>~~Oa~~<br>~~es es~~<br>~~es es~~|R<br>~~Oa~~<br>~~es~~<br>~~es~~|GYRO_DATA_Z[15:8]||||||||
|16<br>~~a~~<br>~~a~~<br>~~es~~|22<br>~~re ~~<br>~~a~~|GYRO_DATA_Z0<br> ~~es es~~<br>~~es es~~<br>~~SO~~|R<br>~~es~~<br>~~es~~<br>~~SO~~|GYRO_DATA_Z[7:0]||||||||
|17<br>~~a ~~<br>~~es~~<br>~~a~~|23<br> ~~a~~<br>~~a~~|TMST_FSYNCH<br>~~es es~~<br>~~SO~~<br>~~es es~~|R<br>~~es~~<br>~~SO~~<br>~~es~~|TMST_FSYNC_DATA[15:8]||||||||
|18<br>~~es~~<br>~~a~~<br>~~es~~|24<br>~~a~~|TMST_FSYNCL<br>~~SO~~<br>~~es es~~<br>~~SO~~|R<br>~~SO~~<br>~~es~~<br>~~SO~~|TMST_FSYNC_DATA[7:0]||||||||
|1D<br>~~a ~~<br>~~es~~<br>~~a~~|29<br> ~~a ~~<br>~~ee~~|APEX_DATA4<br> ~~es es~~<br>~~SO~~<br>~~es es~~|R<br>~~es~~<br>~~SO~~<br>~~es~~|FF_DUR[7:0]||||||||
|1E<br>~~es~~<br>~~a~~<br>~~a~~|30<br>~~ee~~<br>~~a~~|APEX_DATA5<br>~~SO~~<br>~~es es~~<br>~~ee~~|R<br>~~SO~~<br>~~es~~<br>~~ee~~|FF_DUR[15:8]<br>~~eees ts~~||||||||
|1F<br>~~a~~<br>~~a~~<br>~~ns~~|31<br>~~ee ~~<br>~~a~~<br>~~OO~~|PWR_MGMT0<br> ~~es es~~<br>~~ee~~<br>~~OO~~|R/W<br>~~es~~<br>~~ee~~<br>~~OO~~|ACCEL_LP_CL<br>K_SEL<br>~~ee~~<br>~~OO~~|-<br>~~es ts~~<br>~~OO~~||IDLE<br>~~ts~~<br>~~OO~~|GYRO_MODE<br>~~OO~~||ACCEL_MODE<br>~~OO~~||
|20<br>~~a~~<br>~~ns~~<br>~~a~~|32<br>~~a~~<br>~~OO~~<br>~~a~~|GYRO_CONFIG0<br>~~ee~~<br>~~OO~~<br>~~es~~|R/W<br>~~ee~~<br>~~OO~~<br>~~rs~~|-<br>~~ee~~<br>~~OO~~<br>~~es~~|GYRO_UI_FS_SEL<br>~~es ts~~<br>~~OO~~<br>~~es~~||-<br>~~ts~~<br>~~OO~~|GYRO_ODR<br>~~OO~~||||
|21<br>~~ns~~<br>~~a~~|33<br>~~OO~~<br>~~a~~|ACCEL_CONFIG0<br>~~OO~~<br>~~es~~|R/W<br>~~OO~~<br>~~rs~~|-<br>~~OO~~<br>~~es~~|ACCEL_UI_FS_SEL<br>~~OO~~<br>~~es~~||-<br>~~OO~~|ACCEL_ODR<br>~~OO~~||||
|22<br>~~a~~<br>~~sO~~<br>~~a~~|34<br>~~a~~<br>~~sO~~<br>~~a~~|TEMP_CONFIG0<br>~~es ~~<br>~~sO~~<br>~~es~~|R/W<br> ~~rs~~<br>~~sO~~<br>~~rs~~|-<br>~~es~~<br>~~sO~~<br>~~ne~~|TEMP_FILT_BW<br>~~es~~<br>~~sO~~<br>~~ne~~|||-<br>~~sO~~||||
|23<br>~~a~~<br>~~a~~|35<br>~~a~~<br>|GYRO_CONFIG1<br>~~es~~<br>|R/W<br>~~rs~~<br>|-<br>~~ne~~<br>~~a~~<br>~~OO~~<br>|||||GYRO_UI_FILT_BW<br>~~OO~~<br>|||
|24<br>~~a~~<br>~~sO~~<br>~~a~~<br>~~a~~|36<br>~~a ~~<br>~~sO~~<br>|ACCEL_CONFIG1<br> ~~es ~~<br>~~sO~~<br>|R/W<br> ~~rs~~<br>~~sO~~<br>|-<br>~~ne~~<br>~~sO~~<br>~~a~~<br>|ACCEL_UI_AVG<br>~~ne~~<br>~~sO~~<br>~~OO~~<br>|||-<br>~~sO~~<br>~~OO~~<br><br>~~ts ts~~|ACCEL_UI_FILT_BW<br>~~sO~~<br>~~OO~~<br><br>~~ts ts~~|||
|25<br>~~a~~<br>~~a~~<br>~~ee~~|37<br>~~Pe~~|APEX_CONFIG0<br>~~Pe~~<br>~~ee~~|R/W<br>~~Pe~~<br>~~ee~~|-<br>~~a~~<br>~~OO~~<br>~~Pe~~<br>~~eeesre te~~||||DMP_POWE<br>R_SAVE_EN<br>~~OO~~<br>~~Pe~~<br>~~ts ts~~<br>~~ss~~|DMP_INIT_E<br>N<br>~~OO~~<br>~~Pe~~<br>~~ts ts~~<br>~~ss~~|-<br>~~OO~~<br>~~Pe~~|DMP_MEM_<br>RESET_EN<br>~~OO~~<br>~~Pe~~|
|26<br>~~a~~<br>~~ee~~|38|APEX_CONFIG1<br>~~ee~~<br>~~es~~|R/W<br>~~ee~~<br>~~ee~~|-<br>~~ee~~|SMD_ENABL<br>E<br>~~es~~|FF_ENABLE<br>~~re te~~|TILT_ENABLE<br>~~te~~|PED_ENABLE<br>~~ts ts~~<br>~~ss~~|-<br>~~ts ts~~<br>~~ss~~|DMP_ODR||
|27<br>~~ee~~|39|WOM_CONFIG<br>~~ee~~<br>~~es~~|R/W<br>~~ee~~<br>~~ee~~|-<br>~~eeesre te~~|||WOM_INT_DUR<br>~~tess~~||WOM_INT_<br>MODE<br>~~ss~~|WOM_MODE|WOM_EN|
|28<br>~~ee~~<br>~~Poop~~|40<br>~~Poop~~|FIFO_CONFIG1<br>~~ee~~<br>~~es ~~<br>~~Poop~~|R/W<br>~~ee~~<br> ~~ee~~<br>~~Poop~~|-<br>~~ee es re te ss~~<br>~~Poop~~||||||FIFO_MODE<br>~~Poop~~|FIFO_BYPASS<br>~~Poop~~|
|29<br>~~Poop~~<br>~~sO~~<br>~~ns~~|41<br>~~Poop~~<br>~~sO~~<br>~~OO~~|FIFO_CONFIG2<br>~~Poop~~<br>~~sO~~<br>~~OO~~|R/W<br>~~Poop~~<br>~~sO~~<br>~~OO~~|FIFO_WM[7:0]<br>~~Poop~~<br>~~sO~~<br>~~OO~~||||||||
|2A<br>~~ns~~<br>~~a~~|42<br>~~OO~~<br>~~a~~|FIFO_CONFIG3<br>~~OO~~<br>~~ee~~|R/W<br>~~OO~~<br>~~ee~~|-<br>~~OO~~<br>~~eeesrste~~||||FIFO_WM[11:8]<br>~~OO~~<br>~~ss~~||||
|2B<br>~~ns~~<br>~~a~~|43<br>~~OO~~<br>~~a~~|INT_SOURCE0<br>~~OO~~<br>~~ee~~|R/W<br>~~OO~~<br>~~ee~~|ST_INT1_EN<br>~~OO~~<br>~~ee~~|FSYNC_INT1_<br>EN<br>~~OO~~<br>~~es~~|PLL_RDY_INT<br>1_EN<br>~~OO~~<br>~~rs~~|RESET_DONE<br>_INT1_EN<br>~~OO~~<br>~~te~~|DRDY_INT1_<br>EN<br>~~OO~~<br>~~ss~~|FIFO_THS_IN<br>T1_EN<br>~~OO~~<br>~~ss~~|FIFO_FULL_I<br>NT1_EN<br>~~OO~~|AGC_RDY_IN<br>T1_EN<br>~~OO~~|
|2C<br>~~a~~|44<br>~~a~~|INT_SOURCE1<br>~~ee~~|R/W<br>~~ee~~|-<br>~~ee ~~|I3C_PROTOC<br>OL_ERROR_I<br>NT1_EN<br> ~~es ~~|-<br> ~~rs te ~~||SMD_INT1_E<br>N<br> ~~ss~~|WOM_Z_INT<br>1_EN<br>~~ss~~|WOM_Y_INT<br>1_EN|WOM_X_INT<br>1_EN|
|2D<br>~~Pi~~|45<br>~~Pi~~<br>~~|~~|INT_SOURCE3<br>~~=f~~|R/W<br>~~=f~~<br>~~|~~|ST_INT2_EN<br>~~|~~|FSYNC_INT2_<br>EN<br>~~|~~|PLL_RDY_INT<br>2_EN|RESET_DONE<br>_INT2_EN<br>~~ft~~|DRDY_INT2_<br>EN<br>~~ft~~|FIFO_THS_IN<br>T2_EN<br>|FIFO_FULL_I<br>NT2_EN<br>|AGC_RDY_IN<br>T2_EN<br>|
|2E<br>~~Pi~~|46<br>~~Pi~~<br>~~|~~|INT_SOURCE4<br>~~=f~~|R/W<br>~~=f~~<br>~~|~~|-<br>~~|~~|I3C_PROTOC<br>OL_ERROR_I<br>NT2_EN<br>~~|~~|-<br>~~ft~~||SMD_INT2_E<br>N<br>~~ftfT~~|WOM_Z_INT<br>2_EN<br>~~fT~~|WOM_Y_INT<br>2_EN<br>~~fT~~|WOM_X_INT<br>2_EN<br>~~fT~~|
Page 41 of 102
Document Number: DS-000451 Revision: 1.0
_**ICM-42670-P**_
|**ADDR**<br>**(HEX)**<br>~~_~~|**ADDR**<br>**(DEC)**|**REGISTER NAME**|**SERIAL**<br>**I/F**|**BIT7**|**BIT6**|**BIT5**|**BIT4**|**BIT3**|**BIT2**|**BIT1**|**BIT0**|
|---|---|---|---|---|---|---|---|---|---|---|---|
|2F<br>~~a ~~|47<br> ~~a~~|FIFO_LOST_PKT0|R|FIFO_LOST_PKT_CNT[7:0]||||||||
|30<br>~~aa~~<br><br>~~a~~|48<br>~~aa~~<br>~~**a** De~~<br>|FIFO_LOST_PKT1<br>~~aa~~<br>~~De ee~~<br>|R<br>~~ee~~<br>|FIFO_LOST_PKT_CNT[15:8]||||||||
|31<br>~~a~~<br>~~a~~|49<br>~~a~~~~**a** De~~<br>|APEX_DATA0<br>~~De ee~~<br>|R<br>~~ee~~<br>|STEP_CNT[7:0]||||||||
|32<br><br>~~aa~~|50<br>~~**a** De~~<br>~~a De~~|APEX_DATA1<br>~~De ee~~<br>~~De ee~~|R<br>~~ee~~<br>~~ee~~|STEP_CNT[15:8]||||||||
|33<br>~~a~~|51<br>~~a De~~|APEX_DATA2<br>~~De ee~~|R<br>~~ee~~|STEP_CADENCE||||||||
|34<br>~~a ~~<br>~~a ~~<br>~~a~~|52<br> ~~a De~~<br> ~~a~~<br>|APEX_DATA3<br>~~De ee~~<br>~~DO~~<br>|R<br>~~ee~~<br>~~DO~~<br>~~ee~~<br>|-<br>~~DO~~<br>~~ee~~|||||DMP_IDLE<br>~~DO~~|ACTIVITY_CLASS<br>~~DO~~||
|35<br>~~Oe~~<br>~~a~~|53<br>~~Oe~~<br>~~a De~~|INTF_CONFIG0<br>~~Oe~~<br>~~De ee~~|R/W<br>~~Oe~~<br>~~ee~~<br>~~ee~~|-<br>~~Oe~~<br>~~ee~~|FIFO_COUNT<br>_FORMAT<br>~~Oe~~|FIFO_COUNT<br>_ENDIAN<br>~~Oe~~|SENSOR_DAT<br>A_ENDIAN<br>~~Oe~~|-<br>~~Oe~~||||
|36<br>~~a ~~|54<br> ~~a De~~|INTF_CONFIG1<br>~~De ee~~|R/W<br>~~ee~~<br>~~ee~~|-<br>~~ee~~||||I3C_SDR_EN|I3C_DDR_EN|CLKSEL||
|39<br> <br>~~a~~<br>~~a~~|57<br> ~~a De~~<br>~~a~~<br>|INT_STATUS_DRDY<br>~~De ee~~<br>|R/C<br>~~ee~~<br>|-<br>~~ee~~|||||||DATA_RDY_I<br>NT<br>~~ee~~|
|3A<br>~~a~~<br>~~a~~|58<br>~~a~~<br>~~Re~~|INT_STATUS<br>~~ee~~<br>~~Re ee~~|R/C<br>~~ee~~<br>~~ee~~|ST_INT<br>~~ee~~|FSYNC_INT<br>~~ee~~|PLL_RDY_INT<br>~~ee~~|RESET_DONE<br>_INT<br>~~ee~~|-<br>~~ee~~|FIFO_THS_IN<br>T<br>~~ee~~<br>~~ee~~|FIFO_FULL_I<br>NT<br>~~ee~~<br>~~ee~~|AGC_RDY_IN<br>T<br>~~ee~~<br>~~ee~~|
|3B<br>~~a ~~<br>~~a~~|59<br> ~~Re~~<br>~~a~~|INT_STATUS2<br>~~Re ee~~<br>~~a~~|R/C<br>~~ee~~|-<br>~~ee~~||||SMD_INT<br>~~ee~~|WOM_X_INT<br>~~ee~~<br>~~ee~~|WOM_Y_INT<br>~~ee~~|WOM_Z_INT<br>~~ee~~|
|3C<br> <br>~~a~~|60<br> ~~Re~~<br>~~a~~|INT_STATUS3<br>~~Re ee~~<br>~~a~~|R/C<br>~~ee~~|-<br>~~ee~~||STEP_DET_IN<br>T<br>~~ee~~|STEP_CNT_O<br>VF_INT<br>~~ee~~|TILT_DET_IN<br>T<br>~~ee~~|FF_DET_INT<br>~~ee~~|LOWG_DET_I<br>NT|-|
|3D<br>~~a~~<br>~~a ~~|61<br>~~a ~~<br> ~~a~~|FIFO_COUNTH<br> ~~a~~<br>|R<br>|FIFO_COUNT[15:8]<br>~~ee ee~~<br>||||||||
|3E<br>~~eG~~|62<br>~~eG~~|FIFO_COUNTL<br>~~eG~~|R<br>~~eG~~|FIFO_COUNT[7:0]<br>~~eG~~||||||||
|3F<br>~~eG~~<br>~~a ~~|63<br>~~eG~~<br> ~~a~~|FIFO_DATA<br>~~eG~~<br>~~eG~~|R<br>~~eG~~<br>~~eG~~|FIFO_DATA<br>~~eG~~||||||||
|75<br>~~eG~~|117<br>~~eG~~|WHO_AM_I<br>~~eG~~|R<br>~~eG~~|WHOAMI<br>~~eG~~||||||||
|79<br>~~eG~~<br>~~a ~~|121<br>~~eG~~<br> ~~a~~|BLK_SEL_W<br>~~eG~~<br>~~eG~~|R/W<br>~~eG~~<br>~~eG~~|BLK_SEL_W<br>~~eG~~||||||||
|7A<br>~~eG~~|122<br>~~eG~~|MADDR_W<br>~~eG~~|R/W<br>~~eG~~|MADDR_W<br>~~eG~~||||||||
|7B<br>~~eG~~<br>~~a ~~|123<br>~~eG~~<br> ~~a~~|M_W<br>~~eG~~<br>~~eG~~|R/W<br>~~eG~~<br>~~eG~~|M_W<br>~~eG~~||||||||
|7C<br>~~eG~~|124<br>~~eG~~|BLK_SEL_R<br>~~eG~~|R/W<br>~~eG~~|BLK_SEL_R<br>~~eG~~||||||||
|7D<br>~~eG~~<br>~~a ~~|125<br>~~eG~~<br> ~~a~~|MADDR_R<br>~~eG~~<br>~~eG~~|R/W<br>~~eG~~<br>~~eG~~|MADDR_R<br>~~eG~~||||||||
|7E<br>~~eG~~|126<br>~~eG~~|M_R<br>~~eG~~|R/W<br>~~eG~~|M_R<br>~~eG~~||||||||
## **USER BANK MREG1 REGISTER MAP**
|**ADDR**<br>**(HEX)**<br>~~a~~|**ADDR**<br>**(DEC)**|**REGISTER NAME**|**SERIAL**<br>**I/F**|**BIT7**|**BIT6**|**BIT5**|**BIT4**|**BIT3**|**BIT2**|**BIT1**|**BIT0**|
|---|---|---|---|---|---|---|---|---|---|---|---|
|00<br>~~SE~~|00<br>~~SE~~|TMST_CONFIG1<br>~~SEPe~~|R/W<br>~~Pe~~|-<br>~~Pe~~|||TMST_ON_S<br>REG_EN|TMST_RES|TMST_DELTA<br>_EN|TMST_FSYNC<br>_EN|TMST_EN|
|01<br>~~SE~~|01<br>~~SE~~|FIFO_CONFIG5<br>~~SEPe~~|R/W<br>~~Pe~~|-<br>~~Pe~~||FIFO_WM_G<br>T_TH|FIFO_RESUM<br>E_PARTIAL_R<br>D|FIFO_HIRES_<br>EN|FIFO_TMST_F<br>SYNC_EN|FIFO_GYRO_<br>EN|FIFO_ACCEL_<br>EN|
|02<br>~~SE~~|02<br>~~SE~~|FIFO_CONFIG6<br>~~SE Pe~~|R/W<br>~~Pe~~|-<br>~~Pe~~|||FIFO_EMPTY<br>_INDICATOR_<br>DIS|-|||RCOSC_REQ_<br>ON_FIFO_TH<br>S_DIS|
|03|03|FSYNC_CONFIG|R/W|-|FSYNC_UI_SEL|||-||FSYNC_UI_FL<br>AG_CLEAR_S<br>EL|FSYNC_POLA<br>RITY|
|04<br>~~GG~~|04<br>~~GG~~|INT_CONFIG0<br>~~GG~~|R/W<br>~~GG~~|-<br>~~GG~~||UI_DRDY_INT_CLEAR<br>~~GG~~||FIFO_THS_INT_CLEAR<br>~~GG~~||FIFO_FULL_INT_CLEAR<br>~~GG~~||
|05<br>~~GG~~<br>~~a~~|05<br>~~GG~~<br>~~a~~|INT_CONFIG1<br>~~GG~~|R/W<br>~~GG~~|-<br>~~GG~~|INT_TPULSE_<br>DURATION<br>~~GG~~|-<br>~~GG~~|INT_ASYNC_<br>RESET<br>~~GG~~|-<br>~~GG~~||||
|06<br>~~a~~<br>~~a~~|06<br>~~a~~<br>~~a~~|SENSOR_CONFIG3<br>~~ee~~|R/W<br>~~ee~~|-|APEX_DISABL<br>E|-||||||
|13<br>~~a~~<br>~~a~~|19<br>~~ee~~<br>~~a~~|ST_CONFIG<br>~~ee~~|R/W<br>~~ee~~<br>~~ee~~|-<br>~~ee~~<br>~~ee~~|ST_NUMBER<br>_SAMPLE<br>~~ee~~<br>~~ee~~|ACCEL_ST_LIM<br>~~ee~~<br>~~ee~~|||GYRO_ST_LIM<br>~~ee~~<br>~~ee~~|||
|14<br>~~a~~<br>~~a~~|20<br>~~a~~<br>~~a~~|SELFTEST<br>|R/W<br>~~ee~~|GYRO_ST_EN<br>~~ee~~|ACCEL_ST_E<br>N<br>~~ee~~|-<br>~~ee~~<br>~~ee~~||||||
|23<br>~~a~~<br>~~a~~<br>~~a~~<br>~~a~~|35<br>~~a~~<br>~~a~~<br>~~a~~<br>~~a~~|INTF_CONFIG6<br>~~ee~~<br>~~**a**~~|R/W<br>~~ee~~<br>~~ee~~<br>~~ee~~|-<br>~~eeee~~<br>~~ee~~<br>~~eeee~~|||I3C_TIMEOU<br>T_EN<br>~~ee~~<br>~~ee~~<br>~~ee~~|I3C_IBI_BYTE<br>_EN<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|I3C_IBI_EN<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|-<br>~~ee~~<br>~~ee~~<br>~~ee~~||
|25<br>~~a~~<br>~~a~~|37<br>~~a ~~<br>~~a~~|INTF_CONFIG10<br> ~~**a**~~|R/W<br>~~ee~~|ASYNCTIME0<br>_DIS<br>~~ee~~|-<br>~~ee~~<br>~~ee~~|||||||
|28<br><br>~~a~~<br>~~a~~|40<br> <br>~~a~~<br>~~a~~|INTF_CONFIG7<br> ~~**a**~~<br>~~ee~~|R/W<br>~~ee~~<br>~~ee~~|-<br>~~eeee~~<br>~~ee~~||||I3C_DDR_WR<br>_MODE<br>~~ee~~<br>~~ee~~|-<br>~~ee~~<br>~~ee~~|||
|2B<br>~~a~~<br>~~PR~~|43<br>~~a~~|OTP_CONFIG<br>~~ee~~<br>~~ee~~|R/W<br>~~ee~~|-<br>~~ee~~||||OTP_COPY_MODE||-||
|2F<br>~~a ~~<br>~~PR~~<br>~~Oe~~|47<br> ~~a ~~<br>~~Oe~~|INT_SOURCE6<br> ~~ee~~<br>~~ee~~<br>~~ee~~|R/W<br>~~ee~~<br>~~ee~~|FF_INT1_EN<br>~~ee~~<br>~~ee~~|LOWG_INT1_<br>EN<br>~~ee~~<br>~~ee~~|STEP_DET_IN<br>T1_EN|STEP_CNT_O<br>FL_INT1_EN|TILT_DET_IN<br>T1_EN|-|||
|30<br>~~PR~~<br>~~Oe~~|48<br>~~Oe~~|INT_SOURCE7<br>~~ee~~<br>~~ee~~|R/W<br>~~ee~~<br>~~ee~~|FF_INT2_EN<br>~~ee~~<br>~~ee~~|LOWG_INT2_<br>EN<br>~~ee~~<br>~~ee~~|STEP_DET_IN<br>T2_EN|STEP_CNT_O<br>FL_INT2_EN|TILT_DET_IN<br>T2_EN|-|||
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_**ICM-42670-P**_
|**ADDR**<br>**(HEX)**<br>||**ADDR**<br>**(DEC)**|**REGISTER NAME**|**SERIAL**<br>**I/F**|**BIT7**|**BIT6**|**BIT5**|**BIT4**|**BIT3**|**BIT2**|**BIT1**|**BIT0**|
|---|---|---|---|---|---|---|---|---|---|---|---|
|31<br>~~ee~~|49<br>~~ee~~|INT_SOURCE8<br>~~ee~~|R/W<br>~~ee~~|-<br>~~ee~~||FSYNC_IBI_E<br>N<br>~~eee~~|PLL_RDY_IBI_<br>EN<br>~~eee~~|UI_DRDY_IBI<br>_EN<br>~~eee~~|FIFO_THS_IBI<br>_EN<br>~~eee~~|FIFO_FULL_IB<br>I_EN<br>~~eee~~|AGC_RDY_IBI<br>_EN<br>~~eee~~|
|32<br>~~ee~~|50<br>~~ee~~|INT_SOURCE9<br>~~ee~~|R/W<br>~~ee~~|I3C_PROTOC<br>OL_ERROR_I<br>BI_EN<br>~~ee~~|FF_IBI_EN<br>~~ee~~|LOWG_IBI_E<br>N<br>~~eee~~|SMD_IBI_EN<br>~~eee~~|WOM_Z_IBI_<br>EN<br>~~eee~~<br>~~ee~~|WOM_Y_IBI_<br>EN<br>~~eee~~|WOM_X_IBI_<br>EN<br>~~eee~~|ST_DONE_IBI<br>_EN<br>~~eee~~|
|33<br>~~ee~~<br>~~a~~|51<br>~~ee~~<br>~~a~~|INT_SOURCE10<br>~~ee ~~<br>~~ee~~|R/W<br> ~~ee~~<br>~~ee~~|-<br>~~ee ~~<br>~~ee~~||STEP_DET_IB<br>I_EN<br> ~~eee~~<br>~~ee~~|STEP_CNT_O<br>FL_IBI_EN<br>~~eee~~<br>~~ee~~|TILT_DET_IBI<br>_EN<br>~~eee ~~<br>~~ee~~<br>~~ee~~|-<br> ~~eee~~<br>~~ee~~|||
|44<br>~~Ge~~|68<br>~~Ge~~|APEX_CONFIG2<br>~~Ge~~|R/W<br>~~Ge~~|LOW_ENERGY_AMP_TH_SEL<br>~~Ge~~||||DMP_POWER_SAVE_TIME_SEL<br>~~ee~~<br>~~Ge~~||||
|45<br>~~a~~|69|APEX_CONFIG3|R/W|PED_AMP_TH_SEL||||PED_STEP_CNT_TH_SEL||||
|46<br>~~a~~|70<br>|APEX_CONFIG4<br>|R/W<br>|PED_STEP_DET_TH_SEL<br>|||PED_SB_TIMER_TH_SEL<br>|||PED_HI_EN_TH_SEL<br>||
|47<br>~~sf~~|71<br>~~sf~~|APEX_CONFIG5<br>~~sf~~|R/W<br>~~sf~~|TILT_WAIT_TIME_SEL<br>~~sf~~||LOWG_PEAK_TH_HYST_SEL<br>~~sf~~|||HIGHG_PEAK_TH_HYST_SEL<br>~~sf~~|||
|48<br>~~a~~|72<br>~~a~~|APEX_CONFIG9<br>~~ee~~|R/W<br>~~ee~~|FF_DEBOUNCE_DURATION_SEL<br>~~ee~~||||SMD_SENSITIVITY_SEL<br>~~ee~~|||SENSITIVITY_<br>MODE<br>~~ee~~|
|49<br>~~ee~~|73<br>~~ee~~|APEX_CONFIG10<br>~~ee~~|R/W<br>~~ee~~|LOWG_PEAK_TH_SEL<br>~~ee~~|||||LOWG_TIME_TH_SEL<br>~~ee~~|||
|4A<br>~~a~~|74<br>|APEX_CONFIG11<br>|R/W<br>|HIGHG_PEAK_TH_SEL<br>|||||HIGHG_TIME_TH_SEL<br>|||
|4B<br>~~ee~~|75<br>~~ee~~|ACCEL_WOM_X_THR<br>~~ee~~|R/W<br>~~ee~~|WOM_X_TH<br>~~ee~~||||||||
|4C<br>~~a~~|76<br>|ACCEL_WOM_Y_THR<br>|R/W<br>|WOM_Y_TH<br>||||||||
|4D<br>~~ee~~|77<br>~~ee~~|ACCEL_WOM_Z_THR<br>~~ee~~|R/W<br>~~ee~~|WOM_Z_TH<br>~~ee~~||||||||
|4E<br>~~a~~|78<br>|OFFSET_USER0<br>|R/W<br>|GYRO_X_OFFUSER[7:0]<br>||||||||
|4F<br>~~eG~~|79<br>~~eG~~|OFFSET_USER1<br>~~eG~~|R/W<br>~~eG~~|GYRO_Y_OFFUSER[11:8]<br>~~eG~~||||GYRO_X_OFFUSER[11:8]<br>~~eG~~||||
|50<br>~~a~~|80<br>|OFFSET_USER2<br>|R/W<br>|GYRO_Y_OFFUSER[7:0]<br>||||||||
|51<br>~~Ds~~|81<br>~~Ds~~|OFFSET_USER3<br>~~Ds~~|R/W<br>~~Ds~~|GYRO_Z_OFFUSER[7:0]<br>~~Ds~~||||||||
|52<br>~~Ds~~<br>~~a~~|82<br>~~Ds~~<br>|OFFSET_USER4<br>~~Ds~~<br>|R/W<br>~~Ds~~<br>|ACCEL_X_OFFUSER[11:8]<br>~~Ds~~<br>||||GYRO_Z_OFFUSER[11:8]<br>~~Ds~~<br>||||
|53<br>~~eG~~|83<br>~~eG~~|OFFSET_USER5<br>~~eG~~|R/W<br>~~eG~~|ACCEL_X_OFFUSER[7:0]<br>~~eG~~||||||||
|54<br>~~a~~|84<br>|OFFSET_USER6<br>|R/W<br>|ACCEL_Y_OFFUSER[7:0]<br>||||||||
|55<br>~~eG~~|85<br>~~eG~~|OFFSET_USER7<br>~~eG~~|R/W<br>~~eG~~|ACCEL_Z_OFFUSER[11:8]<br>~~eG~~||||ACCEL_Y_OFFUSER[11:8]<br>~~eG~~||||
|56<br>~~se~~|86<br>~~se~~|OFFSET_USER8<br>~~se~~|R/W<br>~~se~~|ACCEL_Z_OFFUSER[7:0]<br>~~se~~||||||||
|63<br>~~ee~~|99<br>~~ee~~|ST_STATUS1<br>~~ee~~|R<br>~~ee~~|-<br>~~ee~~||ACCEL_ST_P<br>ASS<br>~~ee~~|ACCEL_ST_D<br>ONE<br>~~ee~~|AZ_ST_PASS<br>~~ee~~|AY_ST_PASS<br>~~ee~~|AX_ST_PASS<br>~~ee~~|-<br>~~ee~~|
|64<br>a|100<br>~~ee~~|ST_STATUS2<br>~~ee~~|R<br>~~ee~~|-<br>~~ee~~|ST_INCOMPL<br>ETE<br>~~ee~~|GYRO_ST_PA<br>SS<br>~~ee~~|GYRO_ST_DO<br>NE<br>~~ee~~|GZ_ST_PASS<br>~~ee~~|GY_ST_PASS<br>~~ee~~|GX_ST_PASS<br>~~ee~~|-<br>~~ee~~|
|66<br>~~aa~~|102<br>~~aa~~|FDR_CONFIG<br>~~aa~~|R/W|-||||FDR_SEL||||
|67<br>~~aa~~<br>~~a~~|103<br>~~aa~~<br>~~a~~|APEX_CONFIG12<br>~~aa~~|R/W|FF_MAX_DURATION_SEL||||FF_MIN_DURATION_SEL||||
## **USER BANK MREG2 REGISTER MAP**
|**ADDR**<br>**(HEX)**|**ADDR**<br>**(DEC)**|**REGISTER NAME**|**SERIAL**<br>**I/F**|**BIT7**|**BIT6**|**BIT5**|**BIT4**|**BIT3**|**BIT2**|**BIT1**|**BIT0**|
|---|---|---|---|---|---|---|---|---|---|---|---|
|06|06|OTP_CTRL7|R/W|-||||OTP_RELOAD|-|OTP_PWR_D<br>OWN|-|
## **USER BANK MREG3 REGISTER MAP**
|**ADDR**<br>**(HEX)**|**ADDR**<br>**(DEC)**|**REGISTER NAME**|**SERIAL**<br>**I/F**|**BIT7**|**BIT6**|**BIT5**|**BIT4**|**BIT3**|**BIT2**|**BIT1**|**BIT0**|
|---|---|---|---|---|---|---|---|---|---|---|---|
|00|00|XA_ST_DATA|R|XA_ST_DATA||||||||
|01|01|YA_ST_DATA|R|YA_ST_DATA||||||||
|02|02|ZA_ST_DATA|R|ZA_ST_DATA||||||||
|03|03|XG_ST_DATA|R|XG_ST_DATA||||||||
|04|04|YG_ST_DATA|R|YG_ST_DATA||||||||
|05|05|ZG_ST_DATA|R|ZG_ST_DATA||||||||
Page 43 of 102
Document Number: DS-000451 Revision: 1.0
_**ICM-42670-P**_
Detailed register descriptions are provided in the sections that follow.
Register fields marked as Reserved must not be modified by the user. The Reset Value of the register can be used to determine the default value of reserved register fields, and unless otherwise noted this default value must be maintained even if the values of other register fields are modified by the user.
In the sections that follow, some register fields are described as can be changed on-the-fly even if sensor is on. These are the only register fields that can be changed on-the-fly even if sensor is on. Register fields not described as such must not be changed on-the-fly if sensor is on.
Page 44 of 102
Document Number: DS-000451 Revision: 1.0
_**ICM-42670-P**_
## 15 _**USER BANK 0 REGISTER MAP – DESCRIPTIONS**_
This section describes the function and contents of each register within user bank 0.
**Note:** The device powers up in sleep mode.
## **MCLK_RDY**
Name: MCLK_RDY Address: 00 (00h) Serial IF: R Reset value: 0x00 at power-up, changes to 0x01 after OTP load is completed
|**BIT**|**NAME**|**FUNCTION**|
|---|---|---|
|7:4|-|Reserved|
|3|MCLK_RDY|0: Indicates internal clock is currently not running<br>1: Indicates internal clock is currentlyrunning|
|2:0|-|Reserved|
## **DEVICE_CONFIG**
Name: DEVICE_CONFIG Address: 01 (01h) Serial IF: R/W Reset value: 0x04
|**DEVICE_CONFIG**<br>15.2|**DEVICE_CONFIG**<br>15.2|**DEVICE_CONFIG**<br>15.2|
|---|---|---|
|Name: DEVICE_CONFIG<br>Address: 01 (01h)<br>Serial IF: R/W<br>Reset value: 0x04|||
|**BIT**|**NAME**|**FUNCTION**|
|7:3|-|Reserved|
|2|SPI_AP_4WIRE|0: AP interface uses 3-wire SPI mode<br>1: AP interface uses 4-wire SPI mode|
|1|-|Reserved|
|0|SPI_MODE|SPI mode selection<br>0: Mode 0 and Mode 3<br>1: Mode 1 and Mode 2<br>If device is operating in non-SPI mode, user is not allowed to change the<br>power-on default setting of this register. Change of this register setting will<br>not take effect till AP_CS = 1.|
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Document Number: DS-000451 Revision: 1.0
_**ICM-42670-P**_
## **SIGNAL_PATH_RESET**
Name: SIGNAL_PATH_RESET Address: 02 (02h) Serial IF: R/W Reset value: 0x00
|**SIGNAL_PATH_RESET**<br>15.3|**SIGNAL_PATH_RESET**<br>15.3|**SIGNAL_PATH_RESET**<br>15.3|
|---|---|---|
|Name: SIGNAL_PATH_RESET<br>Address: 02 (02h)<br>Serial IF: R/W<br>Reset value: 0x00|||
|**BIT**|**NAME**|**FUNCTION**|
|7:5|-|Reserved|
|4|SOFT_RESET_DEVICE_CON<br>FIG|Software Reset (auto clear bit)<br>0: Software reset not enabled<br>1: Software reset enabled|
|3|-|Reserved|
|2|FIFO_FLUSH|When set to 1, FIFO will get flushed.<br>FIFO flush requires the following programming sequence:<br>•<br>Write FIFO_FLUSH =1<br>•<br>Wait for 1.5 µs<br>•<br>Read FIFO_FLUSH, it should now be 0<br>Host can only program this register bit to 1.|
|1:0|-|Reserved|
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Document Number: DS-000451 Revision: 1.0
_**ICM-42670-P**_
## 15.4 **DRIVE_CONFIG1**
Name: DRIVE_CONFIG1 Address: 03 (03h) Serial IF: R/W Reset value: 0x2B
|**DRIVE_CONFIG1**<br>15.4|**DRIVE_CONFIG1**<br>15.4|**DRIVE_CONFIG1**<br>15.4|
|---|---|---|
|Name: DRIVE_CONFIG1<br>Address: 03 (03h)<br>Serial IF: R/W<br>Reset value: 0x2B|||
|**BIT**|**NAME**|**FUNCTION**|
|7:6|-|Reserved|
|5:3|I3C_DDR_SLEW_RATE|Controls slew rate for output pin 14 when device is in I3CSMDDR protocol.<br>While in I3CSMoperation, the device automatically switches to use<br>I3C_DDR_SLEW_RATE after receiving ENTHDR0 ccc command from the host.<br>The device automatically switches back to I3C_SDR_SLEW_RATE after the<br>host issues HDR_EXIT pattern.<br>000: MIN: 20 ns; TYP: 40 ns; MAX: 60 ns<br>001: MIN: 12 ns; TYP: 24 ns; MAX: 36 ns<br>010: MIN: 6 ns; TYP: 12 ns; MAX: 19 ns<br>011: MIN: 4 ns; TYP: 8 ns; MAX: 14 ns<br>100: MIN: 2 ns; TYP: 4 ns; MAX: 8 ns<br>101: MAX: 2 ns<br>110: Reserved<br>111: Reserved<br>This register field should not beprogrammed in I3C/DDR mode.|
|2:0|I3C_SDR_SLEW_RATE|Controls slew rate for output pin 14 in I3CSMSDR protocol.<br>After device reset, I2C_SLEW_RATE is used by default. If I3CSMfeature is<br>enabled, the device automatically switches to use I3C_SDR_SLEW_RATE<br>after receiving 0x7E+W message (an I3CSMbroadcast message).<br>000: MIN: 20 ns; TYP: 40 ns; MAX: 60 ns<br>001: MIN: 12 ns; TYP: 24 ns; MAX: 36 ns<br>010: MIN: 6 ns; TYP: 12 ns; MAX: 19 ns<br>011: MIN: 4 ns; TYP: 8 ns; MAX: 14 ns<br>100: MIN: 2 ns; TYP: 4 ns; MAX: 8 ns<br>101: MAX: 2 ns<br>110: Reserved<br>111: Reserved<br>This register field should not beprogrammed in I3C/DDR mode|
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Document Number: DS-000451 Revision: 1.0
_**ICM-42670-P**_
## **DRIVE_CONFIG2**
Name: DRIVE_CONFIG2 Address: 04 (04h) Serial IF: R/W Reset value: 0x0D
|**DRIVE_CONFIG2**<br>15.5|**DRIVE_CONFIG2**<br>15.5|**DRIVE_CONFIG2**<br>15.5|
|---|---|---|
|Name: DRIVE_CONFIG2<br>Address: 04 (04h)<br>Serial IF: R/W<br>Reset value: 0x0D|||
|**BIT**|**NAME**|**FUNCTION**|
|7:6|-|Reserved|
|5:3|I2C_SLEW_RATE|Controls slew rate for output pin 14 in I2C mode.<br>After device reset, the I2C_SLEW_RATE is used by default. If the 1st write<br>operation from host is an SPI transaction, the device automatically switches<br>to SPI_SLEW_RATE. If I3CSMfeature is enabled, the device automatically<br>switches to I3C_SDR_SLEW_RATE after receiving 0x7E+W message (an I3C<br>broadcast message).<br>000: MIN: 20 ns; TYP: 40 ns; MAX: 60 ns<br>001: MIN: 12 ns; TYP: 24 ns; MAX: 36 ns<br>010: MIN: 6 ns; TYP: 12 ns; MAX: 19 ns<br>011: MIN: 4 ns; TYP: 8 ns; MAX: 14 ns<br>100: MIN: 2 ns; TYP: 4 ns; MAX: 8 ns<br>101: MAX: 2 ns<br>110: Reserved<br>111: Reserved<br>This register field should not beprogrammed in I3C/DDR mode|
|2:0|ALL_SLEW_RATE|Configure drive strength for all output pins in all modes (SPI3, SPI4, I2C,<br>I3CSM) excluding pin 14.<br>000: MIN: 20 ns; TYP: 40 ns; MAX: 60 ns<br>001: MIN: 12 ns; TYP: 24 ns; MAX: 36 ns<br>010: MIN: 6 ns; TYP: 12 ns; MAX: 19 ns<br>011: MIN: 4 ns; TYP: 8 ns; MAX: 14 ns<br>100: MIN: 2 ns; TYP: 4 ns; MAX: 8 ns<br>101: MAX: 2 ns<br>110: Reserved<br>111: Reserved<br>This register field should not beprogrammed in I3C/DDR mode|
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## 15.6 **DRIVE_CONFIG3**
Name: DRIVE_CONFIG3 Address: 05 (05h) Serial IF: R/W Reset value: 0x05
|**DRIVE_CONFIG3**<br>15.6|**DRIVE_CONFIG3**<br>15.6|**DRIVE_CONFIG3**<br>15.6|
|---|---|---|
|Name: DRIVE_CONFIG3<br>Address: 05 (05h)<br>Serial IF: R/W<br>Reset value: 0x05|||
|**BIT**|**NAME**|**FUNCTION**|
|7:3|-|Reserved|
|2:0|SPI_SLEW_RATE|Controls slew rate for output pin 14 in SPI 3-wire mode. In SPI 4-wire mode<br>this register controls the slew rate of pin 1 as it is used as an output in SPI 4-<br>wire mode only. After chip reset, the I2C_SLEW_RATE is used by default for<br>pin 14 pin. If the 1st write operation from the host is an SPI3/4 transaction,<br>the device automatically switches to SPI_SLEW_RATE.<br>000: MIN: 20 ns; TYP: 40 ns; MAX: 60 ns<br>001: MIN: 12 ns; TYP: 24 ns; MAX: 36 ns<br>010: MIN: 6 ns; TYP: 12 ns; MAX: 19 ns<br>011: MIN: 4 ns; TYP: 8 ns; MAX: 14 ns<br>100: MIN: 2 ns; TYP: 4 ns; MAX: 8 ns<br>101: MAX: 2 ns<br>110: Reserved<br>111: Reserved<br>This register field should not beprogrammed in I3C/DDR mode|
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## **INT_CONFIG**
Name: INT_CONFIG Address: 06 (06h) Serial IF: R/W Reset value: 0x00
|**BIT**|**NAME**||**FUNCTION**|
|---|---|---|---|
|7:6|-|Reserved||
|||INT2 interrupt mode||
|5|INT2_MODE|0: Pulsed mode||
|||1: Latched mode||
|||INT2 drive circuit||
|4|INT2_DRIVE_CIRCUIT|0: Open drain||
|||1: Pushpull||
|||INT2 interrupt polarity||
|3|INT2_POLARITY|0: Active low||
|||1: Active high||
|||INT1 interrupt mode||
|2|INT1_MODE|0: Pulsed mode||
|||1: Latched mode||
|||INT1 drive circuit||
|1|INT1_DRIVE_CIRCUIT|0: Open drain||
|||1: Pushpull||
|||INT1 interrupt polarity||
|0|INT1_POLARITY|0: Active low||
|||1: Active high||
## **TEMP_DATA1**
|**TEMP_DATA1**<br>15.8|**TEMP_DATA1**<br>15.8|**TEMP_DATA1**<br>15.8|
|---|---|---|
|Name: TEMP_DATA1<br>Address: 09 (09h)<br>Serial IF: R<br>Reset value: 0x80|||
|**BIT**|**NAME**|**FUNCTION**|
|7:0|TEMP_DATA[15:8]|Upper byte of temperature data|
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## **TEMP_DATA0**
Name: TEMP_DATA0 Address: 10 (0Ah) Serial IF: R Reset value: 0x00 **BIT NAME FUNCTION** 7:0 TEMP_DATA[7:0] Lower byte of temperature data
Temperature data value from the sensor data registers can be converted to degrees centigrade by using the following formula:
- Temperature in Degrees Centigrade = (TEMP_DATA / 128) + 25
Temperature data stored in FIFO can be an 8-bit or 16-bit quantity, depending on packet format. It can be converted to degrees centigrade by using the following formulas:
- 8-bit quantity: Temperature in Degrees Centigrade = (TEMP_DATA / 2) + 25; where TEMP_DATA refers to the 8 MSBs of the 16-bit word coming from the temperature sensor. In this mode the 8 LSBs are set to ‘0’.
- 16-bit quantity: Temperature in Degrees Centigrade = (TEMP_DATA / 128) + 25
## **ACCEL_DATA_X1**
Name: ACCEL_DATA_X1 Address: 11 (0Bh) Serial IF: R Reset value: 0x80 **BIT NAME FUNCTION** 7:0 ACCEL_DATA_X[15:8] Upper byte of Accel X-axis data
## **ACCEL_DATA_X0**
Name: ACCEL_DATA_X0 Address: 12 (0Ch) Serial IF: R Reset value: 0x00 **BIT NAME FUNCTION** 7:0 ACCEL_DATA_X[7:0] Lower byte of Accel X-axis data
## **ACCEL_DATA_Y1**
Name: ACCEL_DATA_Y1 Address: 13 (0Dh) Serial IF: R Reset value: 0x80 **BIT NAME FUNCTION** 7:0 ACCEL_DATA_Y[15:8] Upper byte of Accel Y-axis data
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15.13 **ACCEL_DATA_Y0** Name: ACCEL_DATA_Y0 Address: 14 (0Eh) Serial IF: R Reset value: 0x00 **BIT NAME FUNCTION** ~~a~~ 7:0 ACCEL_DATA_Y[7:0] Lower byte of Accel Y-axis data 15.14 **ACCEL_DATA_Z1** Name: ACCEL_DATA_Z1 Address: 15 (0Fh) Serial IF: R Reset value: 0x80 **BIT NAME FUNCTION** ~~a~~ 7:0 ACCEL_DATA_Z[15:8] Upper byte of Accel Z-axis data 15.15 **ACCEL_DATA_Z0** Name: ACCEL_DATA_Z0 Address: 16 (10h) Serial IF: R Reset value: 0x00 **BIT NAME FUNCTION** ~~a~~ 7:0 ACCEL_DATA_Z[7:0] Lower byte of Accel Z-axis data
15.16 **GYRO_DATA_X1** Name: GYRO_DATA_X1 Address: 17 (11h) Serial IF: R Reset value: 0x80 **BIT NAME FUNCTION** ~~a~~ 7:0 GYRO_DATA_X[15:8] Upper byte of Gyro X-axis data 15.17 **GYRO_DATA_X0** Name: GYRO_DATA_X0 Address: 18 (12h) Serial IF: R Reset value: 0x00 **BIT NAME FUNCTION** 7:0 GYRO_DATA_X[7:0] Lower byte of Gyro X-axis data ~~———~~
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15.18 **GYRO_DATA_Y1** Name: GYRO_DATA_Y1 Address: 19 (13h) Serial IF: R Reset value: 0x80 **BIT NAME FUNCTION** ~~a~~ 7:0 GYRO_DATA_Y[15:8] Upper byte of Gyro Y-axis data 15.19 **GYRO_DATA_Y0** Name: GYRO_DATA_Y0 Address: 20 (14h) Serial IF: R Reset value: 0x00 **BIT NAME FUNCTION** 7:0 GYRO_DATA_Y[7:0] Lower byte of Gyro Y-axis data ~~—~~
15.20 **GYRO_DATA_Z1** Name: GYRO_DATA_Z1 Address: 21 (15h) Serial IF: R Reset value: 0x80 **BIT NAME FUNCTION** ~~a~~ 7:0 GYRO_DATA_Z[15:8] Upper byte of Gyro Z-axis data 15.21 **GYRO_DATA_Z0** Name: GYRO_DATA_Z0 Address: 22 (16h) Serial IF: R Reset value: 0x00 **BIT NAME FUNCTION** ~~a~~ 7:0 GYRO_DATA_Z[7:0] Lower byte of Gyro Z-axis data 15.22 **TMST_FSYNCH** Name: TMST_FSYNCH Address: 23 (17h) Serial IF: SYNCR Reset value: 0x00 **BIT NAME FUNCTION** Stores the upper byte of the time delta from the rising edge of FSYNC to 7:0 TMST_FSYNC_DATA[15:8] the latest ODR until the UI Interface reads the FSYNC tag in the status ~~a~~ register Page 53 of 102 Document Number: DS-000451 Revision: 1.0
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## **TMST_FSYNCL**
|**TMST_FSYNCL**<br>15.23|**TMST_FSYNCL**<br>15.23|**TMST_FSYNCL**<br>15.23|
|---|---|---|
|Name: TMST_FSYNCL<br>Address: 24 (18h)<br>Serial IF: SYNCR<br>Reset value: 0x00|||
|**BIT**|**NAME**|**FUNCTION**|
|7:0|TMST_FSYNC_DATA[7:0]|Stores the lower byte of the time delta from the rising edge of FSYNC to<br>the latest ODR until the UI Interface reads the FSYNC tag in the status<br>register|
## **APEX_DATA4**
|**APEX_DATA4**<br>15.24|**APEX_DATA4**<br>15.24|**APEX_DATA4**<br>15.24|
|---|---|---|
|Name: APEX_DATA4<br>Address: 29 (1Dh)<br>Serial IF: R<br>Reset value: 0x00|||
|**BIT**|**NAME**|**FUNCTION**|
|7:0|FF_DUR[7:0]|Lower byte of Freefall Duration<br>The duration is given in number of samples and it can be converted to<br>freefall distance in meters by applying the following formula:<br>FF_DISTANCE = 0.5*9.81*(FF_DUR*DMP_ODR_S)^2<br>Note: DMP_ODR_S is the duration of DMP_ODR expressed in seconds.|
## **APEX_DATA5**
|**APEX_DATA5**<br>15.25|**APEX_DATA5**<br>15.25|**APEX_DATA5**<br>15.25|
|---|---|---|
|Name: APEX_DATA5<br>Address: 30 (1Eh)<br>Serial IF: R<br>Reset value: 0x00|||
|**BIT**|**NAME**|**FUNCTION**|
|7:0|FF_DUR[15:8]|Upper byte of Freefall Duration<br>The duration is given in number of samples and it can be converted to<br>freefall distance in meters by applying the following formula:<br>FF_DISTANCE = 0.5*9.81*(FF_DUR*DMP_ODR_S)^2<br>Note: DMP_ODR_S is the duration of DMP_ODR expressed in seconds.|
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## **PWR_MGMT0**
|**PWR_MGMT0**<br>15.26|**PWR_MGMT0**<br>15.26|**PWR_MGMT0**<br>15.26|
|---|---|---|
|Name: PWR_MGMT0<br>Address: 31 (1Fh)<br>Serial IF: R/W<br>Reset value: 0x00|||
|**BIT**|**NAME**|**FUNCTION**|
|7|ACCEL_LP_CLK_SEL|0: Accelerometer LP mode uses Wake Up oscillator clock. This is the lowest<br>power consumption mode and it is the recommended setting.<br>1: Accelerometer LP mode uses RC oscillator clock<br>This field can be changed on-the-flyeven if accel sensor is on|
|6:5|-|Reserved|
|4|IDLE|If this bit is set to 1, the RC oscillator is powered on even if Accel and Gyro<br>are powered off.<br>Nominally this bit is set to 0, so when Accel and Gyro are powered off,<br>the chip will go to OFF state, since the RC oscillator will also be powered off<br>This field can be changed on-the-flyeven if a sensor is on|
|3:2|GYRO_MODE|00: Turns gyroscope off<br>01: Places gyroscope in Standby Mode<br>10: Reserved<br>11: Places gyroscope in Low Noise (LN) Mode<br>Gyroscope needs to be kept ON for a minimum of 45ms. When transitioning<br>from OFF to any of the other modes, do not issue any register writes for<br>200 µs.<br>This field can be changed on-the-flyeven ifgyro sensor is on|
|1:0|ACCEL_MODE|00: Turns accelerometer off<br>01: Turns accelerometer off<br>10: Places accelerometer in Low Power (LP) Mode<br>11: Places accelerometer in Low Noise (LN) Mode<br>When selecting LP Mode please refer to ACCEL_LP_CLK_SEL setting, bit[7] of<br>this register.<br>Before entering LP mode and during LP Mode the following combinations of<br>ODR and averaging are not permitted:<br>1) ODR=1600 Hz or ODR=800 Hz: any averaging.<br>2) ODR=400 Hz: averaging=16x, 32x or 64x.<br>3) ODR=200 Hz: averaging=64x.<br>When transitioning from OFF to any of the other modes, do not issue any<br>register writes for 200 µs.<br>This field can be changed on-the-flyeven if accel sensor is on|
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## **GYRO_CONFIG0**
|**GYRO_CONFIG0**<br>15.27|**GYRO_CONFIG0**<br>15.27|**GYRO_CONFIG0**<br>15.27|
|---|---|---|
|Name: GYRO_CONFIG0<br>Address: 32 (20h)<br>Serial IF: R/W<br>Reset value: 0x06|||
|**BIT**|**NAME**|**FUNCTION**|
|7|-|Reserved|
|6:5|GYRO_UI_FS_SEL|Full scale select for gyroscope UI interface output<br>00: ±2000 dps<br>01: ±1000 dps<br>10: ±500 dps<br>11: ±250 dps<br>This field can be changed on-the-flyeven ifgyro sensor is on|
|4|-|Reserved|
|3:0|GYRO_ODR|Gyroscope ODR selection for UI interface output<br>0000: Reserved<br>0001: Reserved<br>0010: Reserved<br>0011: Reserved<br>0100: Reserved<br>0101: 1.6k Hz<br>0110: 800 Hz<br>0111: 400 Hz<br>1000: 200 Hz<br>1001: 100 Hz<br>1010: 50 Hz<br>1011: 25 Hz<br>1100: 12.5 Hz<br>1101: Reserved<br>1110: Reserved<br>1111: Reserved<br>This field can be changed on-the-flyeven ifgyro sensor is on|
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## **ACCEL_CONFIG0**
Name: ACCEL_CONFIG0 Address: 33 (21h) Serial IF: R/W Reset value: 0x06
|**ACCEL_CONFIG0**<br>15.28|**ACCEL_CONFIG0**<br>15.28|**ACCEL_CONFIG0**<br>15.28|
|---|---|---|
|Name: ACCEL_CONFIG0<br>Address: 33 (21h)<br>Serial IF: R/W<br>Reset value: 0x06|||
|**BIT**|**NAME**|**FUNCTION**|
|7|-|Reserved|
|6:5|ACCEL_UI_FS_SEL|Full scale select for accelerometer UI interface output<br>00: ±16g<br>01: ±8g<br>10: ±4g<br>11: ±2g<br>This field can be changed on-the-flyeven if accel sensor is on|
|4|-|Reserved|
|3:0|ACCEL_ODR|Accelerometer ODR selection for UI interface output<br>0000: Reserved<br>0001: Reserved<br>0010: Reserved<br>0011: Reserved<br>0100: Reserved<br>0101: 1.6 kHz (LN mode)<br>0110: 800 Hz (LN mode)<br>0111: 400 Hz (LP or LN mode)<br>1000: 200 Hz (LP or LN mode)<br>1001: 100 Hz (LP or LN mode)<br>1010: 50 Hz (LP or LN mode)<br>1011: 25 Hz (LP or LN mode)<br>1100: 12.5 Hz (LP or LN mode)<br>1101: 6.25 Hz (LP mode)<br>1110: 3.125 Hz (LP mode)<br>1111: 1.5625 Hz (LP mode)<br>This field can be changed on-the-flywhen accel sensor is on|
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## **TEMP_CONFIG0**
|**TEMP_CONFIG0**<br>15.29|**TEMP_CONFIG0**<br>15.29|**TEMP_CONFIG0**<br>15.29|
|---|---|---|
|Name: TEMP_CONFIG0<br>Address: 34 (22h)<br>Serial IF: R/W<br>Reset value: 0x00|||
|**BIT**|**NAME**|**FUNCTION**|
|7|-|Reserved|
|6:4|TEMP_FILT_BW|Sets the bandwidth of the temperature signal DLPF<br>000: DLPF bypassed<br>001: DLPF BW = 180 Hz<br>010: DLPF BW = 72 Hz<br>011: DLPF BW = 34 Hz<br>100: DLPF BW = 16 Hz<br>101: DLPF BW = 8 Hz<br>110: DLPF BW = 4 Hz<br>111: DLPF BW = 4 Hz<br>This field can be changed on-the-flyeven if sensor is on|
|3:0|-|Reserved|
## 15.30 **GYRO_CONFIG1**
Name: GYRO_CONFIG1 Address: 35 (23h) Serial IF: R/W Reset value: 0x31
|Name: GYRO_CONFIG1<br>Address: 35 (23h)<br>Serial IF: R/W<br>Reset value: 0x31|Name: GYRO_CONFIG1<br>Address: 35 (23h)<br>Serial IF: R/W<br>Reset value: 0x31|Name: GYRO_CONFIG1<br>Address: 35 (23h)<br>Serial IF: R/W<br>Reset value: 0x31|
|---|---|---|
|**BIT**|**NAME**|**FUNCTION**|
|7:3|-|Reserved|
|2:0|GYRO_UI_FILT_BW|Selects GYRO UI low pass filter bandwidth<br>000: Low pass filter bypassed<br>001: 180 Hz<br>010: 121 Hz<br>011: 73 Hz<br>100: 53 Hz<br>101: 34 Hz<br>110: 25 Hz<br>111: 16 Hz<br>This field can be changed on-the-flyeven ifgyro sensor is on|
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## **ACCEL_CONFIG1**
|**ACCEL_CONFIG1**<br>15.31|**ACCEL_CONFIG1**<br>15.31|**ACCEL_CONFIG1**<br>15.31|
|---|---|---|
|Name: ACCEL_CONFIG1<br>Address: 36 (24h)<br>Serial IF: R/W<br>Reset value: 0x41|||
|**BIT**|**NAME**|**FUNCTION**|
|7|-|Reserved|
|6:4|ACCEL_UI_AVG|Selects averaging filter setting to create accelerometer output in<br>accelerometer low power mode (LPM)<br>000: 2x average<br>001: 4x average<br>010: 8x average<br>011: 16x average<br>100: 32x average<br>101: 64x average<br>110: 64x average<br>111: 64x average<br>This field cannot be changed when the accel sensor is in LPM|
|3|-|Reserved|
|2:0|ACCEL_UI_FILT_BW|Selects ACCEL UI low pass filter bandwidth<br>000: Low pass filter bypassed<br>001: 180 Hz<br>010: 121 Hz<br>011: 73 Hz<br>100: 53 Hz<br>101: 34 Hz<br>110: 25 Hz<br>111: 16 Hz<br>This field can be changed on-the-flyeven if accel sensor is on|
## **APEX_CONFIG0**
|**APEX_CONFIG0**<br>15.32|**APEX_CONFIG0**<br>15.32|**APEX_CONFIG0**<br>15.32|
|---|---|---|
|Name: APEX_CONFIG0<br>Address: 37 (25h)<br>Serial IF: R/W<br>Reset value: 0x08|||
|**BIT**|**NAME**|**FUNCTION**|
|7:4|-|Reserved|
|3|DMP_POWER_SAVE_EN|When this bit is set to 1, power savingis enabled for DMP algorithms|
|2|DMP_INIT_EN|When this bit is set to 1, DMP runs DMP SW initialization procedure. Bit is<br>reset by hardware when the procedure is finished. All other APEX features<br>are ignored as long as DMP_INIT_EN is set.<br>This field can be changed on-the-flyeven if accel sensor is on.|
|1|-|Reserved|
|0|DMP_MEM_RESET_EN|When this bit is set to 1, it clears DMP SRAM for APEX operation or Self-test<br>operation.|
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## **APEX_CONFIG1**
|**APEX_CONFIG1**<br>15.33|**APEX_CONFIG1**<br>15.33|**APEX_CONFIG1**<br>15.33|
|---|---|---|
|Name: APEX_CONFIG1<br>Address: 38 (26h)<br>Serial IF: R/W<br>Reset value: 0x02|||
|**BIT**|**NAME**|**FUNCTION**|
|7|-|Reserved|
|6|SMD_ENABLE|0: Significant Motion Detection not enabled<br>1: Significant Motion Detection enabled<br>This field can be changed on-the-flyeven if accel sensor is on|
|5|FF_ENABLE|0: Freefall Detection not enabled<br>1: Freefall Detection enabled<br>This field can be changed on-the-flyeven if accel sensor is on|
|4|TILT_ENABLE|0: Tilt Detection not enabled<br>1: Tilt Detection enabled<br>This field can be changed on-the-flyeven if accel sensor is on|
|3|PED_ENABLE|0: Pedometer not enabled<br>1: Pedometer enabled<br>This field can be changed on-the-flyeven if accel sensor is on|
|2|-|Reserved|
|1:0|DMP_ODR|00: 25 Hz<br>01: 400 Hz<br>10: 50 Hz<br>11: 100 Hz<br>The ACCEL_ODR field must be configured to an ODR equal or greater to the<br>DMP_ODR field, for correct device operation.<br>This field can be changed on-the-flyeven if accel sensor is on|
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## **WOM_CONFIG**
Name: WOM_CONFIG Address: 39 (27h) Serial IF: R/W Reset value: 0x00
|**WOM_CONFIG**<br>15.34|**WOM_CONFIG**<br>15.34|**WOM_CONFIG**<br>15.34|
|---|---|---|
|Name: WOM_CONFIG<br>Address: 39 (27h)<br>Serial IF: R/W<br>Reset value: 0x00|||
|**BIT**|**NAME**|**FUNCTION**|
|7:5|-|Reserved|
|4:3|WOM_INT_DUR|Selects Wake on Motion interrupt assertion from among the following<br>options<br>00: WoM interrupt asserted at first overthreshold event<br>01: WoM interrupt asserted at second overthreshold event<br>10: WoM interrupt asserted at third overthreshold event<br>11: WoM interrupt asserted at fourth overthreshold event<br>This field can be changed on-the-fly even if accel sensor is on, but it cannot<br>be changed if WOM_EN is alreadyenabled|
|2|WOM_INT_MODE|0: Set WoM interrupt on the OR of all enabled accelerometer thresholds<br>1: Set WoM interrupt on the AND of all enabled accelerometer thresholds<br>This field can be changed on-the-fly even if accel sensor is on, but it cannot<br>be changed if WOM_EN is alreadyenabled|
|1|WOM_MODE|0: Initial sample is stored. Future samples are compared to initial sample<br>1: Compare current sample to previous sample<br>This field can be changed on-the-fly even if accel sensor is on, but it cannot<br>be changed if WOM_EN is alreadyenabled|
|0|WOM_EN|0: WOM disabled<br>1: WOM enabled<br>This field can be changed on-the-flyeven if accel sensor is on|
## **FIFO_CONFIG1**
|**FIFO_CONFIG1**<br>15.35|**FIFO_CONFIG1**<br>15.35|**FIFO_CONFIG1**<br>15.35|
|---|---|---|
|Name: FIFO_CONFIG1<br>Address: 40 (28h)<br>Serial IF: R/W<br>Reset value: 0x01|||
|**BIT**|**NAME**|**FUNCTION**|
|7:2|-|Reserved|
|1|FIFO_MODE|FIFO mode control<br>0: Stream-to-FIFO Mode<br>1: STOP-on-FULL Mode|
|0|FIFO_BYPASS|FIFO bypass control<br>0: FIFO is not bypassed<br>1: FIFO is bypassed|
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## **FIFO_CONFIG2**
Name: FIFO_CONFIG2 Address: 41 (29h) Serial IF: R/W Reset value: 0x00
|**FIFO_CONFIG2**<br>15.36|**FIFO_CONFIG2**<br>15.36|**FIFO_CONFIG2**<br>15.36|
|---|---|---|
|Name: FIFO_CONFIG2<br>Address: 41 (29h)<br>Serial IF: R/W<br>Reset value: 0x00|||
|**BIT**|**NAME**|**FUNCTION**|
|7:0|FIFO_WM[7:0]|Lower bits of FIFO watermark. Generate interrupt when the FIFO reaches<br>or exceeds FIFO_WM size in bytes or records according to<br>FIFO_COUNT_FORMAT setting. FIFO_WM_EN must be zero before writing<br>this register. Interrupt only fires once. This register should be set to non-<br>zero value, before choosing this interrupt source.<br>This field should be changed when FIFO is empty to avoid spurious<br>interrupts.|
## **FIFO_CONFIG3**
Name: FIFO_CONFIG3 Address: 42 (2Ah) Serial IF: R/W Reset value: 0x00
|**FIFO_CONFIG3**<br>15.37|**FIFO_CONFIG3**<br>15.37|**FIFO_CONFIG3**<br>15.37|
|---|---|---|
|Name: FIFO_CONFIG3<br>Address: 42 (2Ah)<br>Serial IF: R/W<br>Reset value: 0x00|||
|**BIT**|**NAME**|**FUNCTION**|
|7:4|-|Reserved|
|3:0|FIFO_WM[11:8]|Upper bits of FIFO watermark. Generate interrupt when the FIFO reaches<br>or exceeds FIFO_WM size in bytes or records according to<br>FIFO_COUNT_FORMAT setting. FIFO_WM_EN must be zero before writing<br>this register. Interrupt only fires once. This register should be set to non-<br>zero value, before choosing this interrupt source.<br>This field should be changed when FIFO is empty to avoid spurious<br>interrupts.|
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## **INT_SOURCE0**
Name: INT_SOURCE0 Address: 43 (2Bh) Serial IF: R/W Reset value: 0x10
|**INT_SOURCE0**<br>15.38|**INT_SOURCE0**<br>15.38|**INT_SOURCE0**<br>15.38|
|---|---|---|
|Name: INT_SOURCE0<br>Address: 43 (2Bh)<br>Serial IF: R/W<br>Reset value: 0x10|||
|**BIT**|**NAME**|**FUNCTION**|
|7|ST_INT1_EN|0: Self-Test Done interrupt not routed to INT1<br>1: Self-Test Done interrupt routed to INT1|
|6|FSYNC_INT1_EN|0: FSYNC interrupt not routed to INT1<br>1: FSYNC interrupt routed to INT1|
|5|PLL_RDY_INT1_EN|0: PLL ready interrupt not routed to INT1<br>1: PLL readyinterrupt routed to INT1|
|4|RESET_DONE_INT1_EN|0: Reset done interrupt not routed to INT1<br>1: Reset done interrupt routed to INT1|
|3|DRDY_INT1_EN|0: Data Ready interrupt not routed to INT1<br>1: Data Readyinterrupt routed to INT1|
|2|FIFO_THS_INT1_EN|0: FIFO threshold interrupt not routed to INT1<br>1: FIFO threshold interrupt routed to INT1|
|1|FIFO_FULL_INT1_EN|0: FIFO full interrupt not routed to INT1<br>1: FIFO full interrupt routed to INT1<br>To avoid FIFO FULL interrupts while reading FIFO, this bit should be disabled<br>while readingFIFO|
|0|AGC_RDY_INT1_EN|0: UI AGC ready interrupt not routed to INT1<br>1: UI AGC readyinterrupt routed to INT1|
## **INT_SOURCE1**
|**INT_SOURCE1**<br>15.39|**INT_SOURCE1**<br>15.39|**INT_SOURCE1**<br>15.39|
|---|---|---|
|Name: INT_SOURCE1<br>Address: 44 (2Ch)<br>Serial IF: R/W<br>Reset value: 0x00|||
|**BIT**|**NAME**|**FUNCTION**|
|7|-|Reserved|
|6|I3C_PROTOCOL_ERROR_IN<br>T1_EN|0: I3CSMprotocol error interrupt not routed to INT1<br>1: I3CSM protocol error interrupt routed to INT1|
|5:4|-|Reserved|
|3|SMD_INT1_EN|0: SMD interrupt not routed to INT1<br>1: SMD interrupt routed to INT1|
|2|WOM_Z_INT1_EN|0: Z-axis WOM interrupt not routed to INT1<br>1: Z-axis WOM interrupt routed to INT1|
|1|WOM_Y_INT1_EN|0: Y-axis WOM interrupt not routed to INT1<br>1: Y-axis WOM interrupt routed to INT1|
|0|WOM_X_INT1_EN|0: X-axis WOM interrupt not routed to INT1<br>1: X-axis WOM interrupt routed to INT1|
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## **INT_SOURCE3**
|**INT_SOURCE3**<br>15.40|**INT_SOURCE3**<br>15.40|**INT_SOURCE3**<br>15.40|
|---|---|---|
|Name: INT_SOURCE3<br>Address: 45 (2Dh)<br>Serial IF: R/W<br>Reset value: 0x00|||
|**BIT**|**NAME**|**FUNCTION**|
|7|ST_INT2_EN|0: Self-Test Done interrupt not routed to INT2<br>1: Self-Test Done interrupt routed to INT2|
|6|FSYNC_INT2_EN|0: FSYNC interrupt not routed to INT2<br>1: FSYNC interrupt routed to INT2|
|5|PLL_RDY_INT2_EN|0: PLL ready interrupt not routed to INT2<br>1: PLL readyinterrupt routed to INT2|
|4|RESET_DONE_INT2_EN|0: Reset done interrupt not routed to INT2<br>1: Reset done interrupt routed to INT2|
|3|DRDY_INT2_EN|0: Data Ready interrupt not routed to INT2<br>1: Data Readyinterrupt routed to INT2|
|2|FIFO_THS_INT2_EN|0: FIFO threshold interrupt not routed to INT2<br>1: FIFO threshold interrupt routed to INT2|
|1|FIFO_FULL_INT2_EN|0: FIFO full interrupt not routed to INT2<br>1: FIFO full interrupt routed to INT2|
|0|AGC_RDY_INT2_EN|0: AGC ready interrupt not routed to INT2<br>1: AGC readyinterrupt routed to INT2|
## **INT_SOURCE4**
Name: INT_SOURCE4 Address: 46 (2Eh) Serial IF: R/W Reset value: 0x00
|**BIT**|**NAME**|**FUNCTION**|
|---|---|---|
|7|-|Reserved|
|6|I3C_PROTOCOL_ERROR_IN<br>T2_EN|0: I3CSMprotocol error interrupt not routed to INT2<br>1: I3CSM protocol error interrupt routed to INT2|
|5:4|-|Reserved|
|3|SMD_INT2_EN|0: SMD interrupt not routed to INT2<br>1: SMD interrupt routed to INT2|
|2|WOM_Z_INT2_EN|0: Z-axis WOM interrupt not routed to INT2<br>1: Z-axis WOM interrupt routed to INT2|
|1|WOM_Y_INT2_EN|0: Y-axis WOM interrupt not routed to INT2<br>1: Y-axis WOM interrupt routed to INT2|
|0|WOM_X_INT2_EN|0: X-axis WOM interrupt not routed to INT2<br>1: X-axis WOM interrupt routed to INT2|
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**FIFO_LOST_PKT0**
Name: FIFO_LOST_PKT0 Address: 47 (2Fh) Serial IF: R Reset value: 0x00 **BIT NAME FUNCTION** ~~a~~ 7:0 FIFO_LOST_PKT_CNT[7:0] Low byte, number of packets lost in the FIFO 15.43 **FIFO_LOST_PKT1** Name: FIFO_LOST_PKT1 Address: 48 (30h) Serial IF: R Reset value: 0x00 **BIT NAME FUNCTION** 7:0 FIFO_LOST_PKT_CNT[15:8] High byte, number of packets lost in the FIFO ~~—~~
15.44 **APEX_DATA0** Name: APEX_DATA0 Address: 49 (31h) Serial IF: SYNCR Reset value: 0x00 **BIT NAME FUNCTION** 7:0 STEP_CNT[7:0] Pedometer Output: Lower byte of Step Count measured by pedometer ~~——————~~ 15.45 **APEX_DATA1** Name: APEX_DATA1 Address: 50 (32h) Serial IF: SYNCR Reset value: 0x00 **BIT NAME FUNCTION** ~~a~~ 7:0 STEP_CNT[15:8] Pedometer Output: Upper byte of Step Count measured by pedometer 15.46 **APEX_DATA2** Name: APEX_DATA2 Address: 51 (33h) Serial IF: R Reset value: 0x00 **BIT NAME FUNCTION** Pedometer Output: Walk/run cadency in number of samples. Format is u6.2. 7:0 STEP_CADENCE e.g. At 50 Hz ODR and 2 Hz walk frequency, the cadency is 25 samples and the register will output 100. ~~———~~
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## **APEX_DATA3**
Name: APEX_DATA3 Address: 52 (34h) Serial IF: R Reset value: 0x04
|**BIT**|**NAME**|**FUNCTION**|
|---|---|---|
|7:3|-|Reserved|
|2|DMP_IDLE|0: Indicates DMP is running<br>1: Indicates DMP is idle|
|||Pedometer Output: Detected activity|
|1:0|ACTIVITY_CLASS|00: Unknown<br>01: Walk|
|||10: Run|
|||11: Reserved|
## 15.48 **INTF_CONFIG0**
|**INTF_CONFIG0**<br>15.48|**INTF_CONFIG0**<br>15.48|**INTF_CONFIG0**<br>15.48|
|---|---|---|
|Name: INTF_CONFIG0<br>Address: 53 (35h)<br>Serial IF: R/W<br>Reset value: 0x30|||
|**BIT**|**NAME**|**FUNCTION**|
|7|-|Reserved|
|6|FIFO_COUNT_FORMAT|0: FIFO count is reported in bytes<br>1: FIFO count is reported in records (1 record = 16 bytes for header + gyro +<br>accel + temp sensor data + time stamp, or 8 bytes for header + gyro/accel +<br>tempsensor data)|
|5|FIFO_COUNT_ENDIAN|This bit applies to FIFO Count and Lost Packet Count<br>0: Reported in Little Endian format<br>1: Reported in BigEndian format|
|4|SENSOR_DATA_ENDIAN|0: Sensor data is reported in Little Endian format<br>1: Sensor data is reported in BigEndian format|
|3:0|-|Reserved|
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## **INTF_CONFIG1**
Name: INTF_CONFIG1 Address: 54 (36h) Serial IF: R/W Reset value: 0x4D
|**INTF_CONFIG1**<br>15.49|**INTF_CONFIG1**<br>15.49|**INTF_CONFIG1**<br>15.49|
|---|---|---|
|Name: INTF_CONFIG1<br>Address: 54 (36h)<br>Serial IF: R/W<br>Reset value: 0x4D|||
|**BIT**|**NAME**|**FUNCTION**|
|7:4|-|Reserved|
|3|I3C_SDR_EN|0: I3CSMSDR mode not enabled<br>1: I3CSMSDR mode enabled<br>Device will be inpure I2C mode if{I3C_SDR_EN,I3C_DDR_EN}= 00|
|2|I3C_DDR_EN|0: I3CSMDDR mode not enabled<br>1: I3CSMDDR mode enabled<br>This bit will not take effect unless I3C_SDR_EN = 1.|
|1:0|CLKSEL|00: Always select internal RC oscillator<br>01: Select PLL when available, else select RC oscillator (default)<br>10: Reserved<br>11: Disable all clocks|
## **INT_STATUS_DRDY**
|Name: INT_STATUS_DRDY<br>Address: 57 (39h)<br>Serial IF: R/C<br>Reset value: 0x00|Name: INT_STATUS_DRDY<br>Address: 57 (39h)<br>Serial IF: R/C<br>Reset value: 0x00|Name: INT_STATUS_DRDY<br>Address: 57 (39h)<br>Serial IF: R/C<br>Reset value: 0x00|
|---|---|---|
|**BIT**|**NAME**|**FUNCTION**|
|7:1|-|Reserved|
|0|DATA_RDY_INT|This bit automatically sets to 1 when a Data Ready interrupt is generated.<br>The bit clears to 0 after the register has been read.|
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## **INT_STATUS**
Name: INT_STATUS Address: 58 (3Ah) Serial IF: R/C Reset value: 0x10
|**INT_STATUS**<br>15.51|**INT_STATUS**<br>15.51|**INT_STATUS**<br>15.51|
|---|---|---|
|Name: INT_STATUS<br>Address: 58 (3Ah)<br>Serial IF: R/C<br>Reset value: 0x10|||
|**BIT**|**NAME**|**FUNCTION**|
|7|ST_INT|This bit automatically sets to 1 when a Self Test done interrupt is generated.<br>The bit clears to 0 after the register has been read.|
|6|FSYNC_INT|This bit automatically sets to 1 when an FSYNC interrupt is generated. The<br>bit clears to 0 after the register has been read.|
|5|PLL_RDY_INT|This bit automatically sets to 1 when a PLL Ready interrupt is generated. The<br>bit clears to 0 after the register has been read.|
|4|RESET_DONE_INT|This bit automatically sets to 1 when software reset is complete. The bit<br>clears to 0 after the register has been read.|
|3|-|Reserved|
|2|FIFO_THS_INT|This bit automatically sets to 1 when the FIFO buffer reaches the threshold<br>value. The bit clears to 0 after the register has been read.|
|1|FIFO_FULL_INT|This bit automatically sets to 1 when the FIFO buffer is full. The bit clears to 0<br>after the register has been read.|
|0|AGC_RDY_INT|This bit automatically sets to 1 when an AGC Ready interrupt is generated.<br>The bit clears to 0 after the register has been read.|
## **INT_STATUS2**
Name: INT_STATUS2 Address: 59 (3Bh) Serial IF: R/C Reset value: 0x00
|**BIT**|**NAME**|**FUNCTION**|
|---|---|---|
|7:4|-|Reserved|
|3|SMD_INT|Significant Motion Detection Interrupt,clears on read|
|2|WOM_X_INT|Wake on Motion Interrupt on X-axis,clears on read|
|1|WOM_Y_INT|Wake on Motion Interrupt on Y-axis,clears on read|
|0|WOM_Z_INT|Wake on Motion Interrupt on Z-axis,clears on read|
## **INT_STATUS3**
|**INT_STATUS3**<br>15.53|**INT_STATUS3**<br>15.53|**INT_STATUS3**<br>15.53|
|---|---|---|
|Name: INT_STATUS3<br>Address: 60 (3Ch)<br>Serial IF: R/C<br>Reset value: 0x00|||
|**BIT**|**NAME**|**FUNCTION**|
|7:6|-|Reserved|
|5|STEP_DET_INT|StepDetection Interrupt,clears on read|
|4|STEP_CNT_OVF_INT|StepCount Overflow Interrupt,clears on read|
|3|TILT_DET_INT|Tilt Detection Interrupt,clears on read|
|2|FF_DET_INT|Freefall Interrupt,clears on read|
|1|LOWG_DET_INT|LowG Interrupt,clears on read|
|0|-|Reserved|
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## **FIFO_COUNTH**
Name: FIFO_COUNTH Address: 61 (3Dh) Serial IF: R Reset value: 0x00
|**BIT**|**NAME**|**FUNCTION**|
|---|---|---|
|||High Bits, count indicates the number of records or bytes available in FIFO|
|7:0|FIFO_COUNT[15:8]|according to FIFO_COUNT_FORMAT setting.<br>Note: Must read FIFO_COUNTL to latch new data for both FIFO_COUNTH|
|||and FIFO_COUNTL.|
## **FIFO_COUNTL**
|**FIFO_COUNTL**<br>15.55|**FIFO_COUNTL**<br>15.55|**FIFO_COUNTL**<br>15.55|
|---|---|---|
|Name: FIFO_COUNTL<br>Address: 62 (3Eh)<br>Serial IF: R<br>Reset value: 0x00|||
|**BIT**|**NAME**|**FUNCTION**|
|7:0|FIFO_COUNT[7:0]|Low Bits, count indicates the number of records or bytes available in FIFO<br>according to FIFO_COUNT_REC setting.<br>Reading this byte latches the data for both FIFO_COUNTH, and<br>FIFO_COUNTL.|
15.56 **FIFO_DATA**
|Name: FIFO_DATA<br>Address: 63 (3Fh)<br>Serial IF: R<br>Reset value: 0xFF|Name: FIFO_DATA<br>Address: 63 (3Fh)<br>Serial IF: R<br>Reset value: 0xFF|Name: FIFO_DATA<br>Address: 63 (3Fh)<br>Serial IF: R<br>Reset value: 0xFF|
|---|---|---|
|**BIT**|**NAME**|**FUNCTION**|
|7:0|FIFO_DATA|FIFO dataport|
## **WHO_AM_I**
Name: WHO_AM_I Address: 117 (75h) Serial IF: R Reset value: 0x67 **BIT NAME FUNCTION** 7:0 WHOAMI Register to indicate to user which device is being accessed
## **Description:**
This register is used to verify the identity of the device. The contents of WHOAMI is an 8-bit device ID. The default value of the register is 0x67. This is different from the I[2] C address of the device as seen on the slave I[2] C controller by the applications processor.
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**BLK_SEL_W**
Name: BLK_SEL_W Address: 121 (79h) Serial IF: R/W Reset value: 0x00 **BIT NAME FUNCTION** Block address for accessing MREG1 or MREG2 register space for register 7:0 BLK_SEL_W write operation ~~—E~~ 15.59 **MADDR_W** Name: MADDR_W Address: 122 (7Ah) Serial IF: R/W Reset value: 0x00 **BIT NAME FUNCTION** To write to a register in MREG1 or MREG2 space, set this register field to the 7:0 MADDR_W address of the register in MREG1 or MREG2 space. ~~—EE~~
15.60 **M_W** Name: M_W Address: 123 (7Bh) Serial IF: R/W Reset value: 0x00 **BIT NAME FUNCTION** To write a value to a register in MREG1 or MREG2 space, that value must be 7:0 M_W written to M_W. ~~—E~~ 15.61 **BLK_SEL_R** Name: BLK_SEL_R Address: 124 (7Ch) Serial IF: R/W Reset value: 0x00 **BIT NAME FUNCTION** Block address for accessing MREG1 or MREG2 register space for register 7:0 BLK_SEL_R read operation ~~—E~~
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## **MADDR_R**
|**MADDR_R**<br>15.62|**MADDR_R**<br>15.62|**MADDR_R**<br>15.62|
|---|---|---|
|Name: MADDR_R<br>Address: 125 (7Dh)<br>Serial IF: R/W<br>Reset value: 0x00|||
|**BIT**|**NAME**|**FUNCTION**|
|7:0|MADDR_R|To read the value of a register in MREG1 or MREG2 space, set this register<br>field to the address of the register in MREG1 or MREG2 space.|
## **M_R**
|**M_R**<br>15.63|**M_R**<br>15.63|**M_R**<br>15.63|
|---|---|---|
|Name: M_R<br>Address: 126 (7Eh)<br>Serial IF: R/W<br>Reset value: 0x00|||
|**BIT**|**NAME**|**FUNCTION**|
|7:0|M_R|To read the value of a register in MREG1 or MREG2 space, that value is<br>accessed from M_R.|
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## 16 _**USER BANK MREG1 REGISTER MAP – DESCRIPTIONS**_
This section describes the function and contents of each register within user bank MREG1. The procedure for accessing MREG1 registers is described in section 12.
## **TMST_CONFIG1**
Name: TMST_CONFIG1 Address: 00 (00h) Serial IF: R/W Reset value: 0x02
|**TMST_CONFIG1**<br>16.1|**TMST_CONFIG1**<br>16.1|**TMST_CONFIG1**<br>16.1|
|---|---|---|
|Name: TMST_CONFIG1<br>Address: 00 (00h)<br>Serial IF: R/W<br>Reset value: 0x02|||
|**BIT**|**NAME**|**FUNCTION**|
|7:5|-|Reserved|
|4|TMST_ON_SREG_EN|0: TMST_FSYNCH and TMST_FSYNCL registers report the delta time from<br>FSYNC to next ODR<br>1: TMST_FSYNCH and TMST_FSYNCL registers report: absolute timestamp<br>when FSYNC even is not present; delta time from FSYNC to next ODR when<br>FSYNC event ispresent|
|3|TMST_RES|Time Stamp resolution: When set to 0 (default), time stamp resolution is 1<br>µs. When set to 1,resolution is 16 µs|
|2|TMST_DELTA_EN|Time Stamp delta enable: When set to 1, the time stamp field contains the<br>measurement of time since the last occurrence of ODR.|
|1|TMST_FSYNC_EN|Time Stamp register FSYNC enable (default). When set to 1, the contents of<br>the Timestamp feature of FSYNC is enabled. The user also needs to select<br>FIFO_TMST_FSYNC_EN in order to propagate the timestamp value to the<br>FIFO.|
|0|TMST_EN|0: Time Stamp register disable<br>1: Time Stampregister enable|
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## **FIFO_CONFIG5**
|**FIFO_CONFIG5**<br>16.2|**FIFO_CONFIG5**<br>16.2|**FIFO_CONFIG5**<br>16.2|
|---|---|---|
|Name: FIFO_CONFIG5<br>Address: 01 (01h)<br>Serial IF: R/W<br>Reset value: 0x20|||
|**BIT**|**NAME**|**FUNCTION**|
|7:6|-|Reserved|
|5|FIFO_WM_GT_TH|0: Trigger FIFO Watermark interrupt when FIFO_COUNT =<br>FIFO_WM<br>1: Trigger FIFO Watermark interrupt on every ODR if FIFO_COUNT<br>= FIFO_WM|
|4|FIFO_RESUME_PARTIAL_RD|0: FIFO is read in packets. If a partial packet is read, then the<br>subsequent read will start from the beginning of the un-read<br>packet.<br>1: FIFO can be read partially. When read is resumed, FIFO bytes<br>will continue from last read point. The SW driver is responsible for<br>cascading previous read and present read and for maintaining<br>frame boundaries.|
|3|FIFO_HIRES_EN|0: 20-bit resolution not enabled in the FIFO packet readout<br>1: 20-bit resolution enabled in the FIFOpacket readout|
|2|FIFO_TMST_FSYNC_EN|0: TMST in the FIFO cannot be replaced by the FSYNC timestamp<br>1: Allows the TMST in the FIFO to be replaced by the FSYNC<br>timestamp|
|1|FIFO_GYRO_EN|0: Gyro packets not enabled to go to FIFO<br>1: Enables Gyropackets togo to FIFO|
|0|FIFO_ACCEL_EN|0: Accel packets not enabled to go to FIFO<br>1: Enables Accelpackets togo to FIFO|
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## **FIFO_CONFIG6**
|**FIFO_CONFIG6**<br>16.3|**FIFO_CONFIG6**<br>16.3|**FIFO_CONFIG6**<br>16.3|
|---|---|---|
|Name: FIFO_CONFIG6<br>Address: 02 (02h)<br>Serial IF: R/W<br>Reset value: 0x00|||
|**BIT**|**NAME**|**FUNCTION**|
|7:5|-|Reserved|
|4|FIFO_EMPTY_INDICATOR_DIS|0: 0xFF is sent out as FIFO data when FIFO is empty.<br>1: The last FIFO data is sent out when FIFO is empty.|
|3:1|-|Reserved|
|0|RCOSC_REQ_ON_FIFO_THS_DIS|0: When the FIFO is operating in ALP+WUOSC mode and the<br>watermark (WM) interrupt is enabled, the FIFO wakes up the<br>system oscillator (RCOSC) as soon as the watermark level is<br>reached. The system oscillator remains enabled until a Host<br>FIFO read operation happens. This will temporarily cause a<br>small increase in the power consumption due to the enabling<br>of the system oscillator.<br>1: The system oscillator is not automatically woken-up by the<br>FIFO/INT when the WM interrupt is triggered. The side effect<br>is that the host can receive invalid packets until the system<br>oscillator is off after it has been turned on for other reasons<br>not related to a WM interrupt.<br>The recommended setting of this bit is ‘1’ before entering and<br>during all power modes excluding ALP with WUOSC. This is in<br>order to avoid having to do a FIFO access/flush before entering<br>sleep mode. During ALP with WUOSC it is recommended to set<br>this bit to ‘0’. It is recommended to reset this bit back to ‘1’<br>before exiting ALP+WUOSC with a wait time of 1 ODR or<br>higher.|
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## 16.4 **FSYNC_CONFIG**
|**FSYNC_CONFIG**<br>16.4|**FSYNC_CONFIG**<br>16.4|**FSYNC_CONFIG**<br>16.4|
|---|---|---|
|Name: FSYNC_CONFIG<br>Address: 03 (03h)<br>Serial IF: R/W<br>Reset value: 0x00|||
|**BIT**|**NAME**|**FUNCTION**|
|7|-|Reserved|
|6:4|FSYNC_UI_SEL|000: Do not tag FSYNC flag<br>001: Tag FSYNC flag to TEMP_OUT LSB<br>010: Tag FSYNC flag to GYRO_XOUT LSB<br>011: Tag FSYNC flag to GYRO_YOUT LSB<br>100: Tag FSYNC flag to GYRO_ZOUT LSB<br>101: Tag FSYNC flag to ACCEL_XOUT LSB<br>110: Tag FSYNC flag to ACCEL_YOUT LSB<br>111: TagFSYNC flagto ACCEL_ZOUT LSB|
|3:2|-|Reserved|
|1|FSYNC_UI_FLAG_CLEAR_SEL|0: FSYNC flag is cleared when UI sensor register is updated<br>1: FSYNC flag is cleared when UI interface reads the sensor register LSB of<br>FSYNC tagged axis|
|0|FSYNC_POLARITY|0: Start from Rising edge of FSYNC pulse to measure FSYNC interval<br>1: Start from Fallingedge of FSYNCpulse to measure FSYNC interval|
## **INT_CONFIG0**
|**INT_CONFIG0**<br>16.5|**INT_CONFIG0**<br>16.5|**INT_CONFIG0**<br>16.5|
|---|---|---|
|Name: INT_CONFIG0<br>Address: 04 (04h)<br>Serial IF: R/W<br>Reset value: 0x00|||
|**BIT**|**NAME**|**FUNCTION**|
|7:6|-|Reserved|
|5:4|UI_DRDY_INT_CLEAR|Data Ready Interrupt Clear Option (latched mode)<br>00: Clear on Status Bit Read<br>01: Clear on Status Bit Read<br>10: Clear on Sensor Register Read<br>11: Clear on Status Bit Read OR on Sensor Register read|
|3:2|FIFO_THS_INT_CLEAR|FIFO Threshold Interrupt Clear Option (latched mode)<br>00: Clear on Status Bit Read<br>01: Clear on Status Bit Read<br>10: Clear on FIFO data 1Byte Read<br>11: Clear on Status Bit Read OR on FIFO data 1 byte read|
|1:0|FIFO_FULL_INT_CLEAR|FIFO Full Interrupt Clear Option (latched mode)<br>00: Clear on Status Bit Read<br>01: Clear on Status Bit Read<br>10: Clear on FIFO data 1Byte Read<br>11: Clear on Status Bit Read OR on FIFO data 1 byte read|
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## 16.6 **INT_CONFIG1**
Name: INT_CONFIG1 Address: 05 (05h) Serial IF: R/W Reset value: 0x10
|**INT_CONFIG1**<br>16.6|**INT_CONFIG1**<br>16.6|**INT_CONFIG1**<br>16.6|
|---|---|---|
|Name: INT_CONFIG1<br>Address: 05 (05h)<br>Serial IF: R/W<br>Reset value: 0x10|||
|**BIT**|**NAME**|**FUNCTION**|
|7|-|Reserved|
|6|INT_TPULSE_DURATION|Interrupt pulse duration<br>0: Interrupt pulse duration is 100 µs<br>1: Interruptpulse duration is 8µs|
|5|-|Reserved|
|4|INT_ASYNC_RESET|0: The interrupt pulse is reset as soon as the interrupt status register is read<br>if the pulse is still active.<br>1: The interrupt pulse remains high for the intended duration independent<br>of when the interrupt status register is read. This is the default and<br>recommended setting. In this case, when in ALP with the WUOSC clock, the<br>clearing of the interrupt status register requires up to one ODR period after<br>reading.|
|3:0|-|Reserved|
## **SENSOR_CONFIG3**
Name: SENSOR_CONFIG3 Address: 06 (06h) Serial IF: R/W Reset value: 0x00
|**BIT**|**NAME**|**FUNCTION**|
|---|---|---|
|7|-|Reserved|
|6|APEX_DISABLE|1: Disable APEX features to extend FIFO size to 2.25 Kbytes|
|5:0|-|Reserved|
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## 16.8 **ST_CONFIG**
Name: ST_CONFIG Address: 19 (13h) Serial IF: R/W Reset value: 0x00
|**ST_CONFIG**<br>16.8|**ST_CONFIG**<br>16.8|**ST_CONFIG**<br>16.8|
|---|---|---|
|Name: ST_CONFIG<br>Address: 19 (13h)<br>Serial IF: R/W<br>Reset value: 0x00|||
|**BIT**|**NAME**|**FUNCTION**|
|7|-|Reserved|
|6|ST_NUMBER_SAMPLE|This bit selects the number of sensor samples that should be used to process<br>self-test<br>0: 16 samples<br>1: 200 samples|
|5:3|ACCEL_ST_LIM|These bits control the tolerated ratio between self-test processed values and<br>reference (fused) ones for accelerometer<br>000 to 110: Reserved<br>111: 50%|
|2:0|GYRO_ST_LIM|These bits control the tolerated ratio between self-test processed values and<br>reference (fused) ones for gyroscope<br>000 to 110: Reserved<br>111: 50%|
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## **SELFTEST**
|**SELFTEST**<br>16.9|**SELFTEST**<br>16.9|**SELFTEST**<br>16.9|
|---|---|---|
|Name: SELFTEST<br>Address: 20 (14h)<br>Serial IF: R/W<br>Reset value: 0x00|||
|**BIT**|**NAME**|**FUNCTION**|
|7|GYRO_ST_EN|1: Enable gyro self-test operation. Host needs to program this bit to 0 to<br>move device out of self-test mode. If host programs this bit to 0 while<br>ST_BUSY = 1 and ST_DONE = 0, the current running self-test operation is<br>terminated byhost.|
|6|ACCEL_ST_EN|1: Enable accel self-test operation. Host needs to program this bit to 0 to<br>move device out of self-test mode. If host programs this bit to 0 while<br>ST_BUSY = 1 and ST_DONE = 0, the current running self-test operation is<br>terminated byhost.|
|5:0|-|Reserved|
## 16.10 **INTF_CONFIG6**
|**INTF_CONFIG6**<br>16.10|**INTF_CONFIG6**<br>16.10|**INTF_CONFIG6**<br>16.10|
|---|---|---|
|Name: INTF_CONFIG6<br>Address: 35 (23h)<br>Serial IF: R/W<br>Reset value: 0x7C|||
|**BIT**|**NAME**|**FUNCTION**|
|7:5|-|Reserved|
|4|I3C_TIMEOUT_EN|0: I2C/I3CSMtimeout function not enabled<br>1: I2C/I3CSMtimeout function enabled|
|3|I3C_IBI_BYTE_EN|0: I3CSMIBI payload function not enabled<br>1: I3CSMIBIpayload function enabled|
|2|I3C_IBI_EN|0: I3CSMIBI function not enabled<br>1: I3CSMIBI function enabled|
|1:0|-|Reserved|
## **INTF_CONFIG10**
|**INTF_CONFIG10**<br>16.11|**INTF_CONFIG10**<br>16.11|**INTF_CONFIG10**<br>16.11|
|---|---|---|
|Name: INTF_CONFIG10<br>Address: 37 (25h)<br>Serial IF: R/W<br>Reset value: 0x00|||
|**BIT**|**NAME**|**FUNCTION**|
|7|ASYNCTIME0_DIS|0: I3CSMAsynchronous Mode 0 timing control is enabled<br>1: I3CSMAsynchronous Mode 0 timingcontrol is disabled|
|6:0|-|Reserved|
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## **INTF_CONFIG7**
Name: INTF_CONFIG7 Address: 40 (28h) Serial IF: R/W Reset value: 0x0C
|**INTF_CONFIG7**<br>16.12|**INTF_CONFIG7**<br>16.12|**INTF_CONFIG7**<br>16.12|
|---|---|---|
|Name: INTF_CONFIG7<br>Address: 40 (28h)<br>Serial IF: R/W<br>Reset value: 0x0C|||
|**BIT**|**NAME**|**FUNCTION**|
|7:4|-|Reserved|
|3|I3C_DDR_WR_MODE|This bit controls how I3CSMslave treats the 1st 2-byte data from host in a<br>DDR write operation.<br>0: (a) The 1st-byte in DDR-WR configures the starting register address where<br>the write operation should occur. (b) The 2nd-byte in DDR-WR is ignored and<br>dropped. (c) The 3rd-byte in DDR-WR will be written into the register with<br>address specified by the 1st-byte. Or, the next DDR-RD will be starting from<br>the address specified by the 1st-byte of previous DDR-WR.<br>1: (a) The 1st-byte in DDR-WR configures the starting register address where<br>the write operation should occur. (b) The 2nd-byte in DDR-WR will be<br>written into the register with address specified bythe 1st-byte.|
|2:0|-|Reserved|
## **OTP_CONFIG**
|Name: OTP_CONFIG<br>Address: 43 (2Bh)<br>Serial IF: R/W<br>Reset value: 0x06|Name: OTP_CONFIG<br>Address: 43 (2Bh)<br>Serial IF: R/W<br>Reset value: 0x06|Name: OTP_CONFIG<br>Address: 43 (2Bh)<br>Serial IF: R/W<br>Reset value: 0x06|
|---|---|---|
|**BIT**|**NAME**|**FUNCTION**|
|7:4|-|Reserved|
|3:2|OTP_COPY_MODE|00: Reserved<br>01: Enable copying OTP block to SRAM<br>10: Reserved<br>11: Enable copyingself-test data from OTP memoryto SRAM|
|1:0|-|Reserved|
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## **INT_SOURCE6**
Name: INT_SOURCE6 Address: 47 (2Fh) Serial IF: R/W Reset value: 0x00
|**BIT**|**NAME**|**FUNCTION**|
|---|---|---|
|7|FF_INT1_EN|0: Freefall interrupt not routed to INT1<br>1: Freefall interrupt routed to INT1|
|6|LOWG_INT1_EN|0: Low-g interrupt not routed to INT1<br>1: Low-ginterrupt routed to INT1|
|5|STEP_DET_INT1_EN|0: Step detect interrupt not routed to INT1<br>1: Stepdetect interrupt routed to INT1|
|4|STEP_CNT_OFL_INT1_EN|0: Step count overflow interrupt not routed to INT1<br>1: Stepcount overflow interrupt routed to INT1|
|3|TILT_DET_INT1_EN|0: Tilt detect interrupt not routed to INT1<br>1: Tile detect interrupt routed to INT1|
|2:0|-|Reserved|
## **INT_SOURCE7**
|**INT_SOURCE7**<br>16.15|**INT_SOURCE7**<br>16.15|**INT_SOURCE7**<br>16.15|
|---|---|---|
|Name: INT_SOURCE7<br>Address: 48 (30h)<br>Serial IF: R/W<br>Reset value: 0x00|||
|**BIT**|**NAME**|**FUNCTION**|
|7|FF_INT2_EN|0: Freefall interrupt not routed to INT2<br>1: Freefall interrupt routed to INT2|
|6|LOWG_ INT2_EN|0: Low-g interrupt not routed to INT2<br>1: Low-ginterrupt routed to INT2|
|5|STEP_DET_INT2_EN|0: Step detect interrupt not routed to INT2<br>1: Stepdetect interrupt routed to INT2|
|4|STEP_CNT_OFL_INT2_EN|0: Step count overflow interrupt not routed to INT2<br>1: Stepcount overflow interrupt routed to INT2|
|3|TILT_DET_INT2_EN|0: Tilt detect interrupt not routed to INT2<br>1: Tile detect interrupt routed to INT2|
|2:0|-|Reserved|
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## **INT_SOURCE8**
Name: INT_SOURCE8 Address: 49 (31h) Serial IF: R/W Reset value: 0x00
|**BIT**|**NAME**|**FUNCTION**|
|---|---|---|
|7:6|-|Reserved|
|5|FSYNC_IBI_EN|0: FSYNC interrupt not routed to IBI<br>1: FSYNC interrupt routed to IBI|
|4|PLL_RDY_IBI_EN|0: PLL ready interrupt not routed to IBI<br>1: PLL readyinterrupt routed to IBI|
|3|UI_DRDY_IBI_EN|0: UI data ready interrupt not routed to IBI<br>1: UI data readyinterrupt routed to IBI|
|2|FIFO_THS_IBI_EN|0: FIFO threshold interrupt not routed to IBI<br>1: FIFO threshold interrupt routed to IBI|
|1|FIFO_FULL_IBI_EN|0: FIFO full interrupt not routed to IBI<br>1: FIFO full interrupt routed to IBI|
|0|AGC_RDY_IBI_EN|0: AGC ready interrupt not routed to IBI<br>1: AGC readyinterrupt routed to IBI|
## **INT_SOURCE9**
|Name: INT_SOURCE9<br>Address: 50 (32h)<br>Serial IF: R/W<br>Reset value: 0x00|Name: INT_SOURCE9<br>Address: 50 (32h)<br>Serial IF: R/W<br>Reset value: 0x00|Name: INT_SOURCE9<br>Address: 50 (32h)<br>Serial IF: R/W<br>Reset value: 0x00|
|---|---|---|
|**BIT**|**NAME**|**FUNCTION**|
|7|I3C_PROTOCOL_ERROR_IBI<br>_EN|0: I3CSMprotocol error interrupt not routed to IBI<br>1: I3CSM protocol error interrupt routed to IBI|
|6|FF_IBI_EN|0: Freefall interrupt not routed to IBI<br>1: Freefall interrupt routed to IBI|
|5|LOWG_IBI_EN|0: Low-g interrupt not routed to IBI<br>1: Low-ginterrupt routed to IBI|
|4|SMD_IBI_EN|0: SMD interrupt not routed to IBI<br>1: SMD interrupt routed to IBI|
|3|WOM_Z_IBI_EN|0: Z-axis WOM interrupt not routed to IBI<br>1: Z-axis WOM interrupt routed to IBI|
|2|WOM_Y_IBI_EN|0: Y-axis WOM interrupt not routed to IBI<br>1: Y-axis WOM interrupt routed to IBI|
|1|WOM_X_IBI_EN|0: X-axis WOM interrupt not routed to IBI<br>1: X-axis WOM interrupt routed to IBI|
|0|ST_DONE_IBI_EN|0: Self-test done interrupt not routed to IBI<br>1: Self-test done interrupt routed to IBI|
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## **INT_SOURCE10**
Name: INT_SOURCE10 Address: 51 (33h) Serial IF: R/W Reset value: 0x00
|**BIT**|**NAME**|**FUNCTION**|
|---|---|---|
|7:6|-|Reserved|
|5|STEP_DET_IBI_EN|0: Step detect interrupt not routed to IBI<br>1: Stepdetect interrupt routed to IBI|
|4|STEP_CNT_OFL_IBI_EN|0: Step count overflow interrupt not routed to IBI<br>1: Stepcount overflow interrupt routed to IBI|
|3|TILT_DET_IBI_EN|0: Tilt detect interrupt not routed to IBI<br>1: Tile detect interrupt routed to IBI|
|2:0|-|Reserved|
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## **APEX_CONFIG2**
|**APEX_CONFIG2**<br>16.19|**APEX_CONFIG2**<br>16.19|**APEX_CONFIG2**<br>16.19|
|---|---|---|
|Name: APEX_CONFIG2<br>Address: 68 (44h)<br>Serial IF: R/W<br>Reset value: 0xA2|||
|**BIT**|**NAME**|**FUNCTION**|
|7:4|LOW_ENERGY_AMP_TH_S<br>EL|Threshold to select a valid step. Used to increase step detection for slow<br>walk use case.<br>0000: 30 mg<br>0001: 35 mg<br>0010: 40 mg<br>0011: 45 mg<br>0100: 50 mg<br>0101: 55 mg<br>0110: 60 mg<br>0111: 65 mg<br>1000: 70 mg<br>1001: 75 mg<br>1010: 80 mg (default)<br>1011: 85 mg<br>1100: 90 mg<br>1101: 95 mg<br>1110: 100 mg<br>1111: 105 mg|
|3:0|DMP_POWER_SAVE_TIME<br>_SEL|Duration of the period while the DMP stays awake after receiving a WOM<br>event.<br>0000: 0 seconds<br>0001: 4 seconds<br>0010: 8 seconds (default)<br>0011: 12 seconds<br>0100: 16 seconds<br>0101: 20 seconds<br>0110: 24 seconds<br>0111: 28 seconds<br>1000: 32 seconds<br>1001: 36 seconds<br>1010: 40 seconds<br>1011: 44 seconds<br>1100: 48 seconds<br>1101: 52 seconds<br>1110: 56 seconds<br>1111: 60 seconds|
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## **APEX_CONFIG3**
Name: APEX_CONFIG3 Address: 69 (45h) Serial IF: R/W Reset value: 0x85
|**APEX_CONFIG3**<br>16.20|**APEX_CONFIG3**<br>16.20|**APEX_CONFIG3**<br>16.20|
|---|---|---|
|Name: APEX_CONFIG3<br>Address: 69 (45h)<br>Serial IF: R/W<br>Reset value: 0x85|||
|**BIT**|**NAME**|**FUNCTION**|
|7:4|PED_AMP_TH_SEL|Threshold of step detection sensitivity.<br>Low values increase detection sensitivity: reduce miss-detection.<br>High values reduce detection sensitivity: reduce false-positive.<br>0000: 30 mg<br>0001: 34 mg<br>0010: 38 mg<br>0011: 42 mg<br>0100: 46 mg<br>0101: 50 mg<br>0110: 54 mg<br>0111: 58 mg<br>1000: 62 mg (default)<br>1001: 66 mg<br>1010: 70 mg<br>1011: 74 mg<br>1100: 78 mg<br>1101: 82 mg<br>1110: 86 mg<br>1111: 90 mg|
|3:0|PED_STEP_CNT_TH_SEL|Minimum number of steps that must be detected before step count is<br>incremented.<br>Low values reduce latency but increase false positives.<br>High values increase step count accuracy but increase latency.<br>0000: 0 steps<br>0001: 1 step<br>0010: 2 steps<br>0011: 3 steps<br>0100: 4 steps<br>0101: 5 steps (default)<br>0110: 6 steps<br>0111: 7 steps<br>1000: 8 steps<br>1001: 9 steps<br>1010: 10 steps<br>1011: 11 steps<br>1100: 12 steps<br>1101: 13 steps<br>1110: 14 steps<br>1111: 15 steps|
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## **APEX_CONFIG4**
Name: APEX_CONFIG4 Address: 70 (46h) Serial IF: R/W Reset value: 0x51
|**APEX_CONFIG4**<br>16.21|**APEX_CONFIG4**<br>16.21|**APEX_CONFIG4**<br>16.21|
|---|---|---|
|Name: APEX_CONFIG4<br>Address: 70 (46h)<br>Serial IF: R/W<br>Reset value: 0x51|||
|**BIT**|**NAME**|**FUNCTION**|
|7:5|PED_STEP_DET_TH_SEL|Minimum number of steps that must be detected before step event is<br>signaled.<br>Low values reduce latency but increase false positives.<br>High values increase step event validity but increase latency.<br>000: 0 steps<br>001: 1 step<br>010: 2 steps (default)<br>011: 3 steps<br>100: 4 steps<br>101: 5 steps<br>110: 6 steps<br>111: 7 steps|
|4:2|PED_SB_TIMER_TH_SEL|Duration before algorithm considers that user has stopped taking steps.<br>000: 50 samples<br>001: 75 sample<br>010: 100 samples<br>011: 125 samples<br>100: 150 samples (default)<br>101: 175 samples<br>110: 200 samples<br>111: 225 samples|
|1:0|PED_HI_EN_TH_SEL|Threshold to classify acceleration signal as motion not due to steps.<br>High values improve vibration rejection.<br>Low values improve detection.<br>00: 87.89 mg<br>01: 104.49 mg (default)<br>10: 132.81 mg<br>11: 155.27 mg|
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## **APEX_CONFIG5**
|**APEX_CONFIG5**<br>16.22|**APEX_CONFIG5**<br>16.22|**APEX_CONFIG5**<br>16.22|
|---|---|---|
|Name: APEX_CONFIG5<br>Address: 71 (47h)<br>Serial IF: R/W<br>Reset value: 0x80|||
|**BIT**|**NAME**|**FUNCTION**|
|7:6|TILT_WAIT_TIME_SEL|Minimum duration for which the device should be tilted before signaling<br>event.<br>00: 0s<br>01: 2s<br>10: 4s (default)<br>11: 6s|
|5:3|LOWG_PEAK_TH_HYST_SEL|Hysteresis value added to the low-g threshold after exceeding it.<br>000: 31 mg (default)<br>001: 63 mg<br>010: 94 mg<br>011: 125 mg<br>100: 156 mg<br>101: 188 mg<br>110: 219 mg<br>111: 250 mg|
|2:0|HIGHG_PEAK_TH_HYST_SEL|Hysteresis value subtracted from the high-g threshold after exceeding it.<br>000: 31 mg (default)<br>001: 63 mg<br>010: 94 mg<br>011: 125 mg<br>100: 156 mg<br>101: 188 mg<br>110: 219 mg<br>111: 250 mg|
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## **APEX_CONFIG9**
|**APEX_CONFIG9**<br>16.23|**APEX_CONFIG9**<br>16.23|**APEX_CONFIG9**<br>16.23|
|---|---|---|
|Name: APEX_CONFIG9<br>Address: 72 (48h)<br>Serial IF: R/W<br>Reset value: 0x00|||
|**BIT**|**NAME**|**FUNCTION**|
|7:4|FF_DEBOUNCE_DURATION_<br>SEL|Period after a freefall is signaled during which a new freefall will not be<br>detected. Prevents false detection due to bounces.<br>0000: 0 ms<br>0001: 1250 ms<br>0010: 1375 ms<br>0011: 1500 ms<br>0100: 1625 ms<br>0101: 1750 ms<br>0110: 1875 ms<br>0111: 2000 ms<br>1000: 2125 ms (default)<br>1001: 2250 ms<br>1010: 2375 ms<br>1011: 2500 ms<br>1100: 2625 ms<br>1101: 2750 ms<br>1110: 2875 ms<br>1111: 3000 ms|
|3:1|SMD_SENSITIVITY_SEL|Parameter to tune SMD algorithm robustness to rejection, ranging from 0<br>to 4 (values higher than 4 are reserved).<br>Low values increase detection rate but increase false positives.<br>High values reduce false positives but reduce detection rate (especially for<br>transport use cases).<br>Default value is 0.|
|0|SENSITIVITY_MODE|Pedometer sensitivity mode<br>0: Normal (default)<br>1: Slow walk<br>Slow walk mode improves slow walk detection (<1 Hz) but the number of<br>falsepositives mayincrease.|
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## **APEX_CONFIG10**
|**APEX_CONFIG10**<br>16.24|**APEX_CONFIG10**<br>16.24|**APEX_CONFIG10**<br>16.24|
|---|---|---|
|Name: APEX_CONFIG10<br>Address: 73 (49h)<br>Serial IF: R/W<br>Reset value: 0x00|||
|**BIT**|**NAME**|**FUNCTION**|
|7:3|LOWG_PEAK_TH_SEL|Threshold for accel values below which low-g state is detected.<br>00000: 31 mg (default)<br>00001: 63 mg<br>00010: 94 mg<br>00011: 125 mg<br>00100: 156 mg<br>00101: 188 mg<br>00110: 219 mg<br>00111: 250 mg<br>01000: 281 mg<br>01001: 313 mg<br>01010: 344 mg<br>01011: 375 mg<br>01100: 406 mg<br>01101: 438 mg<br>01110: 469 mg<br>01111: 500 mg<br>10000: 531 mg<br>10001: 563 mg<br>10010: 594 mg<br>10011: 625 mg<br>10100: 656 mg<br>10101: 688 mg<br>10110: 719 mg<br>10111: 750 mg<br>11000: 781 mg<br>11001: 813 mg<br>11010: 844 mg<br>11011: 875 mg<br>11100: 906 mg<br>11101: 938 mg<br>11110: 969 mg<br>11111: 1000 mg|
|2:0|LOWG_TIME_TH_SEL|Number of samples required to enter low-g state.<br>000: 1 sample (default)<br>001: 2 samples<br>010: 3 samples<br>011: 4 samples<br>100: 5 samples<br>101: 6 samples<br>110: 7 samples<br>111: 8 samples|
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## **APEX_CONFIG11**
|**APEX_CONFIG11**<br>16.25|**APEX_CONFIG11**<br>16.25|**APEX_CONFIG11**<br>16.25|
|---|---|---|
|Name: APEX_CONFIG11<br>Address: 74 (4Ah)<br>Serial IF: R/W<br>Reset value: 0x00|||
|**BIT**|**NAME**|**FUNCTION**|
|7:3|HIGHG_PEAK_TH_SEL|Threshold for accel values above which high-g state is detected.<br>00000: 250 mg (default)<br>00001: 500 mg<br>00010: 750 mg<br>00011: 1000 mg<br>00100: 1250 mg<br>00101: 1500 mg<br>00110: 1750 mg<br>00111: 2000 mg<br>01000: 2250 mg<br>01001: 2500 mg<br>01010: 2750 mg<br>01011: 3000 mg<br>01100: 3250 mg<br>01101: 3500 mg<br>01110: 3750 mg<br>01111: 4000 mg<br>10000: 4250 mg<br>10001: 4500 mg<br>10010: 4750 mg<br>10011: 5000 mg<br>10100: 5250 mg<br>10101: 5500 mg<br>10110: 5750 mg<br>10111: 6000 mg<br>11000: 6250 mg<br>11001: 6500 mg<br>11010: 6750 mg<br>11011: 7000 mg<br>11100: 7250 mg<br>11101: 7500 mg<br>11110: 7750 mg<br>11111: 8000 mg|
|2:0|HIGHG_TIME_TH_SEL|Number of samples required to enter high-g state.<br>000: 1 sample (default)<br>001: 2 samples<br>010: 3 samples<br>011: 4 samples<br>100: 5 samples<br>101: 6 samples<br>110: 7 samples<br>111: 8 samples|
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**ACCEL_WOM_X_THR**
Name: ACCEL_WOM_X_THR Address: 75 (4Bh) Serial IF: R/W Reset value: 0x00 **BIT NAME FUNCTION** Threshold value for the Wake on Motion Interrupt for X-axis accelerometer 7:0 WOM_X_TH WoM thresholds are expressed in fixed “mg” independent of the selected Range [0g : 1g]; Resolution 1g/256=~3.9 mg ~~—————~~ 16.27 **ACCEL_WOM_Y_THR** Name: ACCEL_WOM_Y_THR Address: 76 (4Ch) Serial IF: R/W Reset value: 0x00 **BIT NAME FUNCTION** Threshold value for the Wake on Motion Interrupt for Y-axis accelerometer 7:0 WOM_Y_TH WoM thresholds are expressed in fixed “mg” independent of the selected Range [0g : 1g]; Resolution 1g/256=~3.9ge [0g : 1g]; Resolution 1g/256=~3.9e [0g : 1g]; Resolution 1g/256=~3.9[0g : 1g]; Resolution 1g/256=~3.90g : 1g]; Resolution 1g/256=~3.9g : 1g]; Resolution 1g/256=~3.9 : 1g]; Resolution 1g/256=~3.9g]; Resolution 1g/256=~3.9 Resolution 1g/256=~3.9g/256=~3.9256=~3.9 mgg ~~———_—~~
Name: ACCEL_WOM_Y_THR Address: 76 (4Ch) Serial IF: R/W Reset value: 0x00 **BIT NAME FUNCTION** Threshold value for the Wake on Motion Interrupt for Y-axis accelerometer 7:0 WOM_Y_TH WoM thresholds are expressed in fixed “mg” independent of the selected Range [0g : 1g]; Resolution 1g/256=~3.9ge [0g : 1g]; Resolution 1g/256=~3.9e [0g : 1g]; Resolution 1g/256=~3.9[0g : 1g]; Resolution 1g/256=~3.90g : 1g]; Resolution 1g/256=~3.9g : 1g]; Resolution 1g/256=~3.9 : 1g]; Resolution 1g/256=~3.9g]; Resolution 1g/256=~3.9 Resolution 1g/256=~3.9g/256=~3.9256=~3.9 mgg ~~———_—~~ 16.28 **ACCEL_WOM_Z_THR** Name: ACCEL_WOM_Z_THR Address: 77 (4Dh) Serial IF: R/W Reset value: 0x00 **BIT NAME FUNCTION** Threshold value for the Wake on Motion Interrupt for Z-axis accelerometer 7:0 WOM_Z_TH WoM thresholds are expressed in fixed “mg” independent of the selected Range [0g : 1g]; Resolution 1g/256=~3.9 mg ~~—————~~ 16.29 **OFFSET_USER0** Name: OFFSET_USER0 Address: 78 (4Eh) Serial IF: R/W Reset value: 0x00 **BIT NAME FUNCTION** Lower bits of X-gyro offset programmed by user. Max value is ±64 dps, 7:0 GYRO_X_OFFUSER[7:0] resolution is 1/32 dps. ~~—E~~
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**OFFSET_USER1**
Name: OFFSET_USER1 Address: 79 (4Fh) Serial IF: R/W Reset value: 0x00 **BIT NAME FUNCTION** Upper bits of Y-gyro offset programmed by user. Max value is ±64 dps, 7:4 GYRO_Y_OFFUSER[11:8] resolution is 1/32 dps. Upper bits of X-gyro offset programmed by user. Max value is ±64 dps, 3:0 GYRO_X_OFFUSER[11:8] resolution is 1/32 dps. ~~re~~ 16.31 **OFFSET_USER2** Name: OFFSET_USER2 Address: 80 (50h) Serial IF: R/W Reset value: 0x00 **BIT NAME FUNCTION** Lower bits of Y-gyro offset programmed by user. Max value is ±64 dps, 7:0 GYRO_Y_OFFUSER[7:0] resolution is 1/32 dps. ~~—EE~~ 16.32 **OFFSET_USER3** Name: OFFSET_USER3 Address: 81 (51h) Serial IF: R/W Reset value: 0x00 **BIT NAME FUNCTION** Lower bits of Z-gyro offset programmed by user. Max value is ±64 dps, 7:0 GYRO_Z_OFFUSER[7:0] resolution is 1/32 dps. ~~—E~~ 16.33 **OFFSET_USER4** Name: OFFSET_USER4 Address: 82 (52h) Serial IF: R/W Reset value: 0x00 Clock Domain: SCLK_UI **BIT NAME FUNCTION** Upper bits of X-accel offset programmed by user. Max value is ±1g, 7:4 ACCEL_X_OFFUSER[11:8] resolution is 0.5 mg. Upper bits of Z-gyro offset programmed by user. Max value is ±64 dps, 3:0 GYRO_Z_OFFUSER[11:8] resolution is 1/32 dps. ~~oe~~
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## **OFFSET_USER5**
|**OFFSET_USER5**<br>16.34|**OFFSET_USER5**<br>16.34|**OFFSET_USER5**<br>16.34|
|---|---|---|
|Name: OFFSET_USER5<br>Address: 83 (53h)<br>Serial IF: R/W<br>Reset value: 0x00|||
|**BIT**|**NAME**|**FUNCTION**|
|7:0|ACCEL_X_OFFUSER[7:0]|Lower bits of X-accel offset programmed by user. Max value is ±1g,<br>resolution is 0.5 mg.|
## **OFFSET_USER6**
|Name: OFFSET_USER6<br>Address: 84 (54h)<br>Serial IF: R/W<br>Reset value: 0x00|Name: OFFSET_USER6<br>Address: 84 (54h)<br>Serial IF: R/W<br>Reset value: 0x00|Name: OFFSET_USER6<br>Address: 84 (54h)<br>Serial IF: R/W<br>Reset value: 0x00|
|---|---|---|
|**BIT**|**NAME**|**FUNCTION**|
|7:0|ACCEL_Y_OFFUSER[7:0]|Lower bits of Y-accel offset programmed by user. Max value is ±1g,<br>resolution is 0.5 mg.|
## 16.36 **OFFSET_USER7**
|Name: OFFSET_USER7<br>Address: 85 (55h)<br>Serial IF: R/W<br>Reset value: 0x00<br>Clock Domain: SCLK_UI|Name: OFFSET_USER7<br>Address: 85 (55h)<br>Serial IF: R/W<br>Reset value: 0x00<br>Clock Domain: SCLK_UI|Name: OFFSET_USER7<br>Address: 85 (55h)<br>Serial IF: R/W<br>Reset value: 0x00<br>Clock Domain: SCLK_UI|
|---|---|---|
|**BIT**|**NAME**|**FUNCTION**|
|7:4|ACCEL_Z_OFFUSER[11:8]|Upper bits of Z-accel offset programmed by user. Max value is ±1g,<br>resolution is 0.5 mg.|
|3:0|ACCEL_Y_OFFUSER[11:8]|Upper bits of Y-accel offset programmed by user. Max value is ±1g,<br>resolution is 0.5 mg.|
## **OFFSET_USER8**
|Name: OFFSET_USER8<br>Address: 86 (56h)<br>Serial IF: R/W<br>Reset value: 0x00|Name: OFFSET_USER8<br>Address: 86 (56h)<br>Serial IF: R/W<br>Reset value: 0x00|Name: OFFSET_USER8<br>Address: 86 (56h)<br>Serial IF: R/W<br>Reset value: 0x00|
|---|---|---|
|**BIT**|**NAME**|**FUNCTION**|
|7:0|ACCEL_Z_OFFUSER[7:0]|Lower bits of Z-accel offset programmed by user. Max value is ±1g,<br>resolution is 0.5 mg.|
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## **ST_STATUS1**
Name: ST_STATUS1 Address: 99 (63h) Serial IF: R Reset value: 0x00
|**BIT**|**NAME**|**FUNCTION**|
|---|---|---|
|7:6|-|Reserved|
|5|ACCEL_ST_PASS|1: Accel self-testpassed for all the 3 axes|
|4|ACCEL_ST_DONE|1: Accel self-test done for all the 3 axes|
|3|AZ_ST_PASS|1: Accel Z-axis self-testpassed|
|2|AY_ST_PASS|1: Accel Y-axis self-testpassed|
|1|AX_ST_PASS|1: Accel X-axis self-testpassed|
|0|-|Reserved|
## **ST_STATUS2**
|**ST_STATUS2**<br>16.39|**ST_STATUS2**<br>16.39|**ST_STATUS2**<br>16.39|
|---|---|---|
|Name: ST_STATUS2<br>Address: 100 (64h)<br>Serial IF: R<br>Reset value: 0x00|||
|**BIT**|**NAME**|**FUNCTION**|
|7|-|Reserved|
|6|ST_INCOMPLETE|1: Self-test is incomplete.<br>This bit is set to 1 if the self-test was aborted.<br>One possible cause of aborting the self-test may be the detection of<br>significant movement in the gyro when the self-test for gyro and/or accel is<br>beingexecuted.|
|5|GYRO_ST_PASS|1: Gyro self-testpassed for all the 3 axes|
|4|GYRO_ST_DONE|1: Gyro self-test done for all the 3 axes|
|3|GZ_ST_PASS|1: Gyro Z-axis self-testpassed|
|2|GY_ST_PASS|1: Gyro Y-axis self-testpassed|
|1|GX_ST_PASS|1: Gyro X-axis self-testpassed|
|0|-|Reserved|
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## **FDR_CONFIG**
|**FDR_CONFIG**<br>16.40|**FDR_CONFIG**<br>16.40|**FDR_CONFIG**<br>16.40|
|---|---|---|
|Name: FDR_CONFIG<br>Address: 102 (66h)<br>Serial IF: R/W<br>Reset value: 0x00|||
|**BIT**|**NAME**|**FUNCTION**|
|7:4|-|Reserved|
|3:0|FDR_SEL|FIFO packet rate decimation factor. Sets the number of discarded FIFO<br>packets. User must disable sensors when initializing FDR_SEL value or<br>making changes to it.<br>0xxx: Decimation is disabled, all packets are sent to FIFO<br>1000: 1 packet out of 2 is sent to FIFO<br>1001: 1 packet out of 4 is sent to FIFO<br>1010: 1 packet out of 8 is sent to FIFO<br>1011: 1 packet out of 16 is sent to FIFO<br>1100: 1 packet out of 32 is sent to FIFO<br>1101: 1 packet out of 64 is sent to FIFO<br>1110: 1 packet out of 128 is sent to FIFO<br>1111: 1packet out of 256 is sent to FIFO|
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## **APEX_CONFIG12**
|**APEX_CONFIG12**<br>16.41|**APEX_CONFIG12**<br>16.41|**APEX_CONFIG12**<br>16.41|
|---|---|---|
|Name: APEX_CONFIG12<br>Address: 103 (67h)<br>Serial IF: R/W<br>Reset value: 0x00|||
|**BIT**|**NAME**|**FUNCTION**|
|7:4|FF_MAX_DURATION_SEL|Maximum freefall length. Longer freefalls are ignored.<br>0000: 102 cm (default)<br>0001: 120 cm<br>0010: 139 cm<br>0011: 159 cm<br>0100: 181 cm<br>0101: 204 cm<br>0110: 228 cm<br>0111: 254 cm<br>1000: 281 cm<br>1001: 310 cm<br>1010: 339 cm<br>1011: 371 cm<br>1100: 403 cm<br>1101: 438 cm<br>1110: 473 cm<br>1111: 510 cm|
|3:0|FF_MIN_DURATION_SEL|Minimum freefall length. Shorter freefalls are ignored.<br>0000: 10 cm (default)<br>0001: 12 cm<br>0010: 13 cm<br>0011: 16 cm<br>0100: 18 cm<br>0101: 20 cm<br>0110: 23 cm<br>0111: 25 cm<br>1000: 28 cm<br>1001: 31 cm<br>1010: 34 cm<br>1011: 38 cm<br>1100: 41 cm<br>1101: 45 cm<br>1110: 48 cm<br>1111: 52 cm|
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## 17 _**USER BANK MREG2 REGISTER MAP – DESCRIPTIONS**_
This section describes the function and contents of each register within user bank MREG2. The procedure for accessing MREG2 registers is described in section 12.
## **OTP_CTRL7**
Name: OTP_CTRL7 Address: 06 (06h) Serial IF: RWS Reset value: 0x06 (initial reset value is 0x0C, it changes to 0x06 after OTP load completes)
|**OTP_CTRL7**<br>17.1|**OTP_CTRL7**<br>17.1|**OTP_CTRL7**<br>17.1|
|---|---|---|
|Name: OTP_CTRL7<br>Address: 06 (06h)<br>Serial IF: RWS<br>Reset value: 0x06 (initial reset value is 0x0C, it changes to 0x06 after OTP load completes)(initial reset value is 0x0C, it changes to 0x06 after OTP load completes)initial reset value is 0x0C, it changes to 0x06 after OTP load completes), it changes to 0x06 after OTP load completes)it changes to 0x06 after OTP load completes)ges to 0x06 after OTP load completes)es to 0x06 after OTP load completes)pletes)letes))|||
|**BIT**|**NAME**|**FUNCTION**|
|7:4|-|Reserved|
|3|OTP_RELOAD|Settingthis bit to 1 triggers OTP copyoperation.|
|2|-|Reserved|
|1|OTP_PWR_DOWN|0: Power up OTP to copy from OTP to SRAM<br>1: Power down OTP<br>This bit is automaticallyset to 1 when OTP copyoperation is complete.|
|0|-|Reserved|
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## 18 _**USER BANK MREG3 REGISTER MAP – DESCRIPTIONS**_
This section describes the function and contents of each register within user bank MREG3. The procedure for accessing MREG3 registers is described in section 12.
## **XA_ST_DATA**
Name: XA_ST_DATA Address: 00 (00h) Serial IF: R Reset value: 0x00 **BIT NAME FUNCTION** 7:0 XA_ST_DATA Accel X-axis factory trimmed self-test response.
## **YA_ST_DATA**
Name: YA_ST_DATA Address: 01 (01h) Serial IF: R Reset value: 0x00 **BIT NAME FUNCTION** 7:0 YA_ST_DATA Accel Y-axis factory trimmed self-test response.
## **ZA_ST_DATA**
Name: ZA_ST_DATA Address: 02 (02h) Serial IF: R Reset value: 0x00 **BIT NAME FUNCTION** 7:0 ZA_ST_DATA Accel Z-axis factory trimmed self-test response.
## **XG_ST_DATA**
Name: XG_ST_DATA Address: 03 (03h) Serial IF: R Reset value: 0x00 **BIT NAME FUNCTION** 7:0 XG_ST_DATA Gyro X-axis factory trimmed self-test response.
## **YG_ST_DATA**
Name: YG_ST_DATA Address: 04 (04h) Serial IF: R Reset value: 0x00 **BIT NAME FUNCTION** 7:0 YG_ST_DATA Gyro Y-axis factory trimmed self-test response.
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## 18.6 **ZG_ST_DATA**
|**ZG_ST_DATA**<br>18.6|**ZG_ST_DATA**<br>18.6|**ZG_ST_DATA**<br>18.6|
|---|---|---|
|Name: ZG_ST_DATA<br>Address: 05 (05h)<br>Serial IF: R<br>Reset value: 0x00|||
|**BIT**|**NAME**|**FUNCTION**|
|7:0|ZG_ST_DATA|Gyro Z-axis factorytrimmed self-test response.|
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## 19 _**SMARTMOTION PRODUCT FAMILY**_
ICM-42670-P is a member of the SmartMotion™ family of MEMS motion sensors with 1-, 2-, 3-, 6-, 7-, and 9-axis IMU platforms addressing the emerging need of many mass-market consumer applications via improved performance, accuracy, and intuitive motion and gesture-based interfaces.
For more information, please visit invensense.tdk.com.
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## 20 _**REFERENCE**_
Please refer to the following application notes for additional information.
- InvenSense MEMS Handling Application Note (AN-IVS-0002A-00) for the following information:
- Manufacturing Recommendations
- Assembly Guidelines and Recommendations
- PCB Design Guidelines and Recommendations
- MEMS Handling Instructions
- ESD Considerations
- Reflow Specification
- Storage Specifications
- Package Marking Specification
- Tape & Reel Specification
- Reel & Pizza Box Label
- Packaging
- Representative Shipping Carton Label
- Compliance
- Environmental Compliance
- DRC Compliance
- Compliance Declaration Disclaimer
- Understanding IMU Sensor Offset (AN-000257)
- ICM-42607x DMP Mode Accelerometer and Gyroscope Self-Test (AN-000258)
- ICM-42607x/42670x Products PCB Board Design Guide (AN-000262)
- TDK InvenSense IMU Calibration Application Note (AN-000265)
- ICM-42607x/42670x Accelerometer Low Power Mode Implementation (AN-000266)
- ICM-42607x and ICM-42670x Errata (AN-000273)
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## _**REVISION HISTORY**_
|**REVISION DATE**|**REVISION**||**DESCRIPTION**|
|---|---|---|---|
|04/15/2021|1.0|Initial Release||
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This information furnished by InvenSense or its affiliates (“TDK InvenSense”) is believed to be accurate and reliable. However, no responsibility is assumed by TDK InvenSense for its use, or for any infringements of patents or other rights of third parties that may result from its use. Specifications are subject to change without notice. TDK InvenSense reserves the right to make changes to this product, including its circuits and software, in order to improve its design and/or performance, without prior notice. TDK InvenSense makes no warranties, neither expressed nor implied, regarding the information and specifications contained in this document. TDK InvenSense assumes no responsibility for any claims or damages arising from information contained in this document, or from the use of products and services detailed therein. This includes, but is not limited to, claims or damages based on the infringement of patents, copyrights, mask work and/or other intellectual property rights.
Certain intellectual property owned by InvenSense and described in this document is patent protected. No license is granted by implication or otherwise under any patent or patent rights of InvenSense. This publication supersedes and replaces all information previously supplied. Trademarks that are registered trademarks are the property of their respective companies. TDK InvenSense sensors should not be used or sold in the development, storage, production or utilization of any conventional or mass-destructive weapons or for any other weapons or life threatening applications, as well as in any other life critical applications such as medical equipment, transportation, aerospace and nuclear instruments, undersea equipment, power plant equipment, disaster prevention and crime prevention equipment.
©2020—2021 InvenSense. All rights reserved. InvenSense, MotionTracking, MotionProcessing, MotionProcessor, MotionFusion, MotionApps, DMP, AAR, and the InvenSense logo are trademarks of InvenSense, Inc. The TDK logo is a trademark of TDK Corporation. Other company and product names may be trademarks of the respective companies with which they are associated.
©2020—2021 InvenSense. All rights reserved.
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Updated at April 17, 2026
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