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ICE5LP4K-SWG36ITR
FPGA, iCE40 Ultra, PLL, 26 I/O's, 3520 Cell, 1.14 V to 1.26 V in, WLCSP-36
⚠️ Reference pricing provided. In case of supply shortages, we will connect you with our trusted procurement partners to ensure your project's continuity.
- Manufacturer: LATTICE SEMICONDUCTOR
- Product type: FPGAs
- MSL: MSL 3 - 168 hours
- SVHC: No SVHC (25-Jun-2025)
- FPGA Type: SRAM based FPGA
- FPGA Family: iCE40 Ultra
- IC Mounting: Surface Mount
- No. of Pins: 36Pins
- Speed Grade: -
- No. of I/O's: 26I/O's
- Product Range: -
- Qualification: -
- Total RAM Bits: 56Kbit
- No.of User I/Os: 26I/O's
- Clock Management: PLL
- Logic Case Style: WLCSP
- IC Case / Package: WLCSP
- No. of Macrocells: 3520Macrocells
- I/O Supply Voltage: 3.46V
- No. of Logic Cells: 3520Logic Cells
- Process Technology: 40nm (CMOS)
- No. of Logic Blocks: 3520
- Core Supply Voltage Max: 1.26V
- Core Supply Voltage Min: 1.14V
- Operating Frequency Max: 1MHz
- Operating Temperature Max: 100°C
- Operating Temperature Min: -40°C
| Delivery and price | |
|---|---|
| Units per pack | 250 |
| Price | 6.59 € |
| Current stock | 10+ |
| Lead time | 30 days |
Datasheet
## Os
## **iCE40 Ultra Family Data Sheet**
## **Data Sheet**
FPGA-DS-02028-2.4
August 2020
**iCE40 Ultra Family Data Sheet Data Sheet**
## **Disclaimers**
Lattice makes no warranty, representation, or guarantee regarding the accuracy of information contained in this document or the suitability of its products for any particular purpose. All information herein is provided AS IS and with all faults, and all risk associated with such information is entirely with Buyer. Buyer shall not rely on any data and performance specifications or parameters provided herein. Products sold by Lattice have been subject to limited testing and it is the Buyer's responsibility to independently determine the suitability of any products and to test and verify the same. No Lattice products should be used in conjunction with mission- or safety-critical or any other application in which the failure of Lattice’s product could create a situation where personal injury, death, severe property or environmental damage may occur. The information provided in this document is proprietary to Lattice Semiconductor, and Lattice reserves the right to make any changes to the information in this document or to any products at any time without notice.
© 2018-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
2
FPGA-DS-02028-2.4
**iCE40 Ultra Family Data Sheet Data Sheet**
## **Contents**
|**Contents**|**Contents**|**Contents**|
|---|---|---|
|Acronyms in This Document ................................................................................................................................................. 6|||
|1.|General Description ...................................................................................................................................................... 7||
||1.1.|Features .............................................................................................................................................................. 7|
|2.|Product Family .............................................................................................................................................................. 8||
||2.1.|Overview ............................................................................................................................................................. 8|
|3.|Architecture .................................................................................................................................................................. 9||
||3.1.|Architecture Overview ........................................................................................................................................ 9|
||3.1.1.|PLB Blocks ..................................................................................................................................................... 10|
||3.1.2.|Routing .......................................................................................................................................................... 11|
||3.1.3.|Clock/Control Distribution Network ............................................................................................................. 11|
||3.1.4.|sysCLOCK Phase Locked Loops (PLLs) ........................................................................................................... 11|
||3.1.5.|sysMEM Embedded Block RAM Memory ..................................................................................................... 13|
||3.1.6.|sysDSP ........................................................................................................................................................... 15|
||3.1.7.|sysIO Buffer Banks ........................................................................................................................................ 19|
||3.1.8.|sysIO Buffer ................................................................................................................................................... 22|
||3.1.9.|On-Chip Oscillator ......................................................................................................................................... 23|
||3.1.10.<br>User I2C IP ................................................................................................................................................. 23||
||3.1.11.<br>User SPI IP ................................................................................................................................................. 23||
||3.1.12.<br>High Current LED Drive I/O Pins ............................................................................................................... 23||
||3.1.13.<br>Embedded PWM IP ................................................................................................................................... 24||
||3.1.14.<br>Non-Volatile Configuration Memory ........................................................................................................ 24||
||3.2.|iCE40 Ultra Programming and Configuration .................................................................................................... 25|
||3.2.1.|Device Programming ..................................................................................................................................... 25|
||3.2.2.|Device Configuration .................................................................................................................................... 25|
||3.2.3.|Power Saving Options ................................................................................................................................... 25|
|4.|DC and Switching Characteristics ............................................................................................................................... 26||
||4.1.|Absolute Maximum Ratings .............................................................................................................................. 26|
||4.2.|Recommended Operating Conditions ............................................................................................................... 26|
||4.3.|Power Supply Ramp Rates ................................................................................................................................ 27|
||4.4.|Power-On Reset ................................................................................................................................................ 27|
||4.5.|Power-up Supply Sequence............................................................................................................................... 27|
||4.6.|External Reset ................................................................................................................................................... 27|
||4.7.|Power-On-Reset Voltage Levels ........................................................................................................................ 28|
||4.8.|ESD Performance .............................................................................................................................................. 29|
||4.9.|DC Electrical Characteristics .............................................................................................................................. 29|
||4.10.|Supply Current .................................................................................................................................................. 30|
||4.11.|User I2C Specifications ....................................................................................................................................... 30|
||4.12.|User SPI Specifications ...................................................................................................................................... 31|
||4.13.|Internal Oscillators (HFOSC, LFOSC) .................................................................................................................. 31|
||4.14.|sysI/O Recommended Operating Conditions .................................................................................................... 31|
||4.15.|sysI/O Single-Ended DC Electrical Characteristics ............................................................................................. 32|
||4.16.|Differential Comparator Electrical Characteristics ............................................................................................ 32|
||4.17.|Typical Building Block Function Performance ................................................................................................... 32|
||4.17.1.<br>Pin-to-Pin Performance (LVCMOS25) ....................................................................................................... 32||
||4.17.2.<br>Register-to-Register Performance ............................................................................................................ 33||
||4.18.|Derating Logic Timing ........................................................................................................................................ 33|
||4.19.|Maximum sysIO Buffer Performance ................................................................................................................ 33|
||4.20.|iCE40 Ultra Family Timing Adders ..................................................................................................................... 34|
||4.21.|iCE40 Ultra External Switching Characteristics ................................................................................................. 34|
||4.22.|sysCLOCK PLL Timing ......................................................................................................................................... 35|
||4.23.|sysDSP Timing ................................................................................................................................................... 36|
||4.24.|SPI Master or NVCM Configuration Time .......................................................................................................... 36|
© 2018-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02028-2.4
3
**iCE40 Ultra Family Data Sheet Data Sheet**
**==> picture [486 x 217] intentionally omitted <==**
**----- Start of picture text -----**<br>
|||
|---|---|
|4.25.|sysCONFIG Port Timing Specifications ............................................................................................................... 37|
|4.26.|RGB LED and IR LED Drive.................................................................................................................................. 38|
|4.27.|Switching Test Conditions ................................................................................................................................. 38|
|5.|Pinout Information ..................................................................................................................................................... 39|
|5.1.|Signal Descriptions ............................................................................................................................................ 39|
|5.1.1.|Power Supply Pins ......................................................................................................................................... 39|
|5.1.2.|Configuration Pins ......................................................................................................................................... 39|
|5.1.3.|Configuration SPI Pins ................................................................................................................................... 40|
|5.1.4.|Global Pins .................................................................................................................................................... 41|
|5.1.5.|LED Pins ......................................................................................................................................................... 41|
|5.2.|Pin Information Summary ................................................................................................................................. 42|
|5.3.|iCE40 Ultra Part Number Description ................................................................................................................ 43|
|5.3.1.|Tape and Reel Quantity ................................................................................................................................ 43|
|5.4.|Ordering Part Numbers ..................................................................................................................................... 43|
|5.4.1.|Industrial ....................................................................................................................................................... 43|
|References .......................................................................................................................................................................... 45|
|Technical Support ............................................................................................................................................................... 46|
|Revision History .................................................................................................................................................................. 47|
**----- End of picture text -----**<br>
**Figures** Figure 3.1. iCE5LP-4K Device, Top View ................................................................................................................................ 9 Figure 3.2. PLB Block Diagram ............................................................................................................................................ 10 Figure 3.3. PLL Diagram ...................................................................................................................................................... 12 Figure 3.4. sysMEM Memory Primitives ............................................................................................................................. 14 Figure 3.5. sysDSP Functional Block Diagram (16-bit x 16-bit Multiply-Accumulate) ......................................................... 16 Figure 3.6. sysDSP 8-bit x 8-bit Multiplier ........................................................................................................................... 18 Figure 3.7. DSP 16-bit x 16-bit Multiplier ............................................................................................................................ 19 Figure 3.8. I/O Bank and Programmable I/O Cell ................................................................................................................ 20 Figure 3.9. I/O Register Block Diagram ............................................................................................................................... 21 Figure 4.1. Power Up Sequence with SPI_VCCIO1 and VPP_2V5 Not Connected Together ....................................................... 28 Figure 4.2. Power Up Sequence with All Supplies Connected Together ............................................................................. 28 Figure 4.3. Output Test Load, LVCMOS Standards .............................................................................................................. 38
© 2018-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02028-2.4
4
**iCE40 Ultra Family Data Sheet Data Sheet**
## **Tables**
|Table 2.1. iCE40 Ultra Family Selection Guide ...................................................................................................................... 8|Table 2.1. iCE40 Ultra Family Selection Guide ...................................................................................................................... 8|
|---|---|
|Table 3.1. Logic Cell Signal Descriptions ............................................................................................................................. 10|Table 3.1. Logic Cell Signal Descriptions ............................................................................................................................. 10|
|Table 3.2. Global Buffer (GBUF) Connections to Programmable Logic Blocks ................................................................... 11|Table 3.2. Global Buffer (GBUF) Connections to Programmable Logic Blocks ................................................................... 11|
|Table 3.3. PLL Signal Descriptions ....................................................................................................................................... 13|Table 3.3. PLL Signal Descriptions ....................................................................................................................................... 13|
|Table 3.4. sysMEM Block Configurations* .......................................................................................................................... 14|Table 3.4. sysMEM Block Configurations* .......................................................................................................................... 14|
|Table 3.5. EBR Signal Descriptions ...................................................................................................................................... 15|Table 3.5. EBR Signal Descriptions ...................................................................................................................................... 15|
|Table 3.6. Output Block Port Description ........................................................................................................................... 16|Table 3.6. Output Block Port Description ........................................................................................................................... 16|
|Table 3.7. PIO Signal List ..................................................................................................................................................... 21|Table 3.7. PIO Signal List ..................................................................................................................................................... 21|
|Table 3.8. Supported Input Standards ................................................................................................................................ 22|Table 3.8. Supported Input Standards ................................................................................................................................ 22|
|Table 3.9. Supported Output Standards ............................................................................................................................. 22|Table 3.9. Supported Output Standards ............................................................................................................................. 22|
|Table 3.10. iCE40 Ultra Power Saving Features Description ............................................................................................... 25|Table 3.10. iCE40 Ultra Power Saving Features Description ............................................................................................... 25|
|Table 4.1. Absolute Maximum Ratings|Table 4.1. Absolute Maximum Ratings1, 2. 3........................................................................................................................ 26|
|Table 4.2. Recommended Operating Conditions|Table 4.2. Recommended Operating Conditions1............................................................................................................. 26|
|Table 4.3. Power Supply Ramp Rates|Table 4.3. Power Supply Ramp Rates1, 2............................................................................................................................. 27|
|Table 4.4. Power-On-Reset Voltage Levels* ....................................................................................................................... 28|Table 4.4. Power-On-Reset Voltage Levels* ....................................................................................................................... 28|
|Table 4.5. DC Electrical Characteristics ............................................................................................................................... 29|Table 4.5. DC Electrical Characteristics ............................................................................................................................... 29|
|Table 4.6. Supply Current|Table 4.6. Supply Current1, 2, 3, 4, 5....................................................................................................................................... 30|
|Table 4.7. User I|Table 4.7. User I2C Specifications........................................................................................................................................ 30|
|Table 4.8. User SPI Specifications|Table 4.8. User SPI Specifications1, 2................................................................................................................................... 31|
|Table 4.9. Internal Oscillators (HFOSC, LFOSC)* ................................................................................................................. 31|Table 4.9. Internal Oscillators (HFOSC, LFOSC)* ................................................................................................................. 31|
|Table 4.10. sysI/O Recommended Operating Conditions ................................................................................................... 31|Table 4.10. sysI/O Recommended Operating Conditions ................................................................................................... 31|
|Table 4.11. sysI/O Single-Ended DC Electrical Characteristics ............................................................................................ 32|Table 4.11. sysI/O Single-Ended DC Electrical Characteristics ............................................................................................ 32|
|Table 4.12. Differential Comparator Electrical Characteristics ........................................................................................... 32|Table 4.12. Differential Comparator Electrical Characteristics ........................................................................................... 32|
|Table 4.13. Pin-to-Pin Performance (LVCMOS25)|Table 4.13. Pin-to-Pin Performance (LVCMOS25)1, 2.......................................................................................................... 32|
|Table 4.14. Register-to-Register Performance|Table 4.14. Register-to-Register Performance1, 2............................................................................................................... 33|
|Table 4.15. Maximum sysIO Buffer Performance* ............................................................................................................. 33|Table 4.15. Maximum sysIO Buffer Performance* ............................................................................................................. 33|
|Table 4.16. iCE40 Ultra Family Timing Adders|Table 4.16. iCE40 Ultra Family Timing Adders1, 2, 3............................................................................................................. 34|
|Table 4.17. iCE40 Ultra External Switching Characteristics ................................................................................................ 34|Table 4.17. iCE40 Ultra External Switching Characteristics ................................................................................................ 34|
|Table 4.18. sysCLOCK PLL Timing ........................................................................................................................................ 35|Table 4.18. sysCLOCK PLL Timing ........................................................................................................................................ 35|
|Table 4.19. sysDSP Timing .................................................................................................................................................. 36|Table 4.19. sysDSP Timing .................................................................................................................................................. 36|
|Table 4.20. SPI Master or NVCM Configuration Time|Table 4.20. SPI Master or NVCM Configuration Time1, 2.................................................................................................... 36|
|Table 4.21. sysCONFIG Port Timing Specifications ............................................................................................................. 37|Table 4.21. sysCONFIG Port Timing Specifications ............................................................................................................. 37|
|Table 4.22. RGB LED and IR LED Drive ................................................................................................................................ 38|Table 4.22. RGB LED and IR LED Drive ................................................................................................................................ 38|
|Table 4.23. Test Fixture Required Components, Non-Terminated Interfaces .................................................................... 38|Table 4.23. Test Fixture Required Components, Non-Terminated Interfaces .................................................................... 38|
© 2018-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02028-2.4
5
**iCE40 Ultra Family Data Sheet Data Sheet**
## **Acronyms in This Document**
A list of acronyms used in this document.
|**Acronym **|**Definition**|
|---|---|
|DFF|D-style Flip-Flop|
|EBR|Embedded Block RAM|
|HFOSC|High FrequencyOscillator|
|I2C|Inter-Integrated Circuit|
|LFOSC|Low FrequencyOscillator|
|LC|Logic Cell|
|LUT|Look UpTable|
|LVCMOS|Low-Voltage ComplementaryMetal Oxide Semiconductor|
|NVCM|Non Volatile Configuration Memory|
|PFU|Programmable Functional Unit|
|PLB|Programmable Logic Blocks|
|PLL|Phase Locked Loops|
|SPI|Serial Peripheral Interface|
|WLCSP|Wafer Level ChipScale Packaging|
© 2018-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02028-2.4
6
**iCE40 Ultra Family Data Sheet Data Sheet**
## **1. General Description**
iCE40 Ultra™ family from Lattice Semiconductor is an ultra-low power FPGA and sensor manager designed for ultra-low power mobile applications, such as smartphones, tablets and hand-held devices. The iCE40 Ultra family includes integrated SPI and I[2] C blocks to interface with virtually all mobile sensors and application processors. The iCE40 Ultra family also features two on-chip oscillators, 10 kHz and 48 MHz. The LFOSC (10 kHz) is ideal for low power function in always-on applications, while HFOSC (48 MHz) can be used for awaken activities.
The iCE40 Ultra family also features DSP functional block to off-load Application Processor to pre-process information sent from the mobile sensors. The embedded RGB PWM IP, with the three 24 mA constant current RGB outputs on the iCE40 Ultra provides all the necessary logic to directly drive the service LED, without the need of external MOSFET or buffer.
The 500 mA constant current IR driver output provides a direct interface to external LED for application such as IrDA functions. Users simply implement the modulation logic that meets his needs, and connect the IR driver directly to the LED, without the need of external MOSFET or buffer. This high current IR driver can also be used as Barcode Emulation, sending barcode information to external Barcode Reader.
The iCE40 Ultra family of devices are targeting for mobile applications to perform functions such as IrDA, Service LED, Barcode Emulation, GPIO Expander, SDIO Level Shift, and other custom functions.
The iCE40 Ultra family features three device densities, from 1100 to 3520 Look Up Tables (LUTs) of logic with programmable I/Os that can be used as either SPI/I[2] C interface ports or general purpose I/Os. It also has up to 80 kbits of Block RAMs to work with user logic.
## **1.1. Features**
- Flexible Logic Architecture
- Three devices with 1100 to 3520 LUTs
- Offered in WLCS, ucfBGA and QFN packages
- Ultra-low Power Devices
- Advanced 40 nm ultra-low power process
- As low as 71 µA standby current typical
- Embedded Memory
- Up to 80 kbits sysMEM™ Embedded Block RAM
- Two Hardened I[2] C Interfaces
- Two Hardened SPI Interfaces
- Two On-Chip Oscillators
- Low Frequency Oscillator – 10 kHz
- High Frequency Oscillator – 48 MHz
- 24 mA Current Drive RGB LED Outputs
- Three drive outputs in each device
- User selectable sink current up to 24 mA
- 500 mA Current Drive IR LED Output
- One IR drive output in each device
- User selectable sink current up to 500 mA
- On-chip DSP
- Signed and unsigned 8-bit or 16-bit functions
- Functions include Multiplier, Accumulator, and Multiply-Accumulate (MAC)
- Flexible On-Chip Clocking
- Eight low skew global signal resource, six can be directly driven from external pins
- One PLL with dynamic interface per device
- Flexible Device Configuration
- SRAM is configured through:
- Standard SPI Interface
- Internal Nonvolatile Configuration Memory (NVCM)
- Ultra-Small Form Factor
- As small as 2.078 mm x 2.078 mm
- Applications
- Smartphones
- Tablets and Consumer Handheld Devices
- Handheld Commercial and Industrial Devices
- Multi Sensor Management Applications
- Sensor Pre-processing and Sensor Fusion
- Always-On Sensor Applications
- USB 3.1 Type C Cable Detect/Power Delivery Applications
© 2018-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02028-2.4
7
**iCE40 Ultra Family Data Sheet Data Sheet**
## **2. Product Family**
Table 2.1 lists device information and packages of the iCE40 Ultra family.
**Table 2.1. iCE40 Ultra Family Selection Guide**
|**Part Number**<br>~~LG~~|**iCE5LP1K**<br>~~LG~~|**iCE5LP2K**<br>~~LG~~|**iCE5LP4K**<br>~~LG~~|
|---|---|---|---|
|**Logic Cells (LUT + Flip-Flop)**<br>~~a~~|**1100**<br>~~GC~~|**2048**<br>~~GC~~|**3520**<br>~~GC~~|
|EBR Memory Blocks<br>~~a~~|16|20|20|
|EBR Memory Bits<br>~~eG~~|64 k<br>~~eG~~|80 k<br>~~eG~~|80 k<br>~~eG~~|
|PLL Block<br>~~a~~|1|1|1|
|NVCM<br>~~a~~|Yes|Yes|Yes|
|DSP Blocks (MULT16 with 32-bit Accumulator)<br>~~Ge~~|2<br>~~Ge~~|4<br>~~Ge~~|4<br>~~Ge~~|
|Hardened I2C, SPI<br>~~eG~~|1,1<br>~~eG~~|2,2<br>~~eG~~|2,2<br>~~eG~~|
|HF Oscillator (48 MHz)<br>~~eG~~|1<br>~~eG~~|1<br>~~eG~~|1<br>~~eG~~|
|LF Oscillator (10 kHz)<br>~~eG~~|1<br>~~eG~~|1<br>~~eG~~|1<br>~~eG~~|
|24 mA LED Sink<br>~~a~~|3|3|3|
|500 mA LED Sink<br>~~a~~|1|1|1|
|Embedded PWM IP<br>~~eG~~|Yes<br>~~eG~~|Yes<br>~~eG~~|No<br>~~eG~~|
|**Packages, Ball Pitch, Dimension**<br>~~RG~~|**Total User I/O Count**<br>~~RG~~|||
|36-ball WLCSP, 0.35 mm, 2.078 mm x 2.078 mm<br>~~a~~|26<br>~~a~~|26<br>~~a~~|26<br>~~a~~|
|36-ball ucfBGA, 0.40 mm, 2.5 mm x 2.5 mm<br>~~a~~|26<br>~~a~~|26<br>~~a~~|26<br>~~a~~|
|48-pin QFN Package, 0.5 mm, 7.0 mm x 7.0 mm<br>~~a~~|39<br>~~a~~|39<br>~~a~~|39<br>~~a~~|
## **2.1. Overview**
The iCE40 Ultra family of ultra-low power FPGAs has three devices with densities ranging from 1100 to 3520 Look-Up Tables (LUTs) fabricated in a 40 nm Low Power CMOS process. In addition to LUT-based, low-cost programmable logic, these devices also feature Embedded Block RAM (EBR), on-chip Oscillators (LFOSC, HFOSC), two hardened I[2] C Controllers, two hardened SPI Controllers, three 24 mA RGB LED open-drain drivers, a 500 mA IR LED open-drain drivers, and DSP blocks. These features allow the devices to be used in low-cost, high-volume consumer and mobile applications.
The iCE40 Ultra FPGAs are available in very small form factor packages, as small as 2.078 mm x 2.078 mm. The small form factor allows the device to easily fit into a lot of mobile applications, where space can be limited. Table 2.1 shows the LUT densities, package and I/O pin count.
The iCE40 Ultra devices offer I/O features such as pull-up resistors. Pull-up features are controllable on a “per-pin” basis. The iCE40 Ultra devices also provide flexible, reliable and secure configuration from on-chip NVCM. These devices can also configure themselves from external SPI Flash, or be configured by an external master such as a CPU.
Lattice provides a variety of design tools that allow complex designs to be efficiently implemented using the iCE40 Ultra family of devices. Popular logic synthesis tools provide synthesis library support for iCE40 Ultra. Lattice design tools use the synthesis tool output along with the user-specified preferences and constraints to place and route the design in the iCE40 Ultra device. These tools extract the timing from the routing and back-annotate it into the design for timing verification.
Lattice provides in the iCE40 Ultra 1K and 2K device the embedded RGB PWM IP at no extra cost of LUT available to the user, to perform controlling the RGB LED function. This embedded IP allow users to control color, LED ON/ OFF time, and breathe rate of the LED. For more information, refer to Usage Guide in Lattice Design Software.
Lattice provides many pre-engineered IP (Intellectual Property) modules, including a number of reference designs, licensed free of charge, optimized for the iCE40 Ultra FPGA family. Lattice also can provide fully verified bitstream for some of the widely used target functions in mobile device applications, such as ultra-low power sensor management, gesture recognition, IR remote, barcode emulator functions. Users can use these functions as offered by Lattice, or they can use the design to create their own unique required functions. For more information regarding Lattice's reference designs or fully-verified bitstreams, please contact your local Lattice representative.
© 2018-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
8
FPGA-DS-02028-2.4
**iCE40 Ultra Family Data Sheet Data Sheet**
## **3. Architecture**
## **3.1. Architecture Overview**
The iCE40 Ultra family architecture contains an array of Programmable Logic Blocks (PLB), two Oscillator Generators, two user configurable I[2] C controllers, two user configurable SPI controllers, and blocks of sysMEM™ Embedded Block RAM (EBR) surrounded by Programmable I/O (PIO). Figure 3.1 shows the block diagram of the iCE5LP-4K device.
**==> picture [152 x 232] intentionally omitted <==**
**----- Start of picture text -----**<br>
ze it \<br>= | L T<br>* |<br>|) eo<br>JN a(ce<br>Carry Logic aea n e<br>4-Input Look-up<br>Table (LUT) Flip-flop with Enable<br>and Reset Controls<br>8 Logic Cells = Programmable Logic Block<br>**----- End of picture text -----**<br>
**Figure 3.1. iCE5LP-4K Device, Top View**
The Programmable Logic Blocks (PLB) and sysMEM EBR blocks, are arranged in a two-dimensional grid with rows and columns. Each column has either PLB or EBR blocks. The PIO cells are located at the top and bottom of the device, arranged in banks. The PLB contains the building blocks for logic, arithmetic, and register functions. The PIOs utilize a flexible I/O buffer referred to as a sysIO buffer that supports operation with a variety of interface standards. The blocks are connected with many vertical and horizontal routing channel resources. The place and route software tool automatically allocates these routing resources.
In the iCE40 Ultra family, there are three sysIO banks, one on top and two at the bottom. User can connect some VCCIOs together, if all the I/Os are using the same voltage standard. Refer to the details in later sections of this document on Power Up Sequence. The sysMEM EBRs are large 4 kbit, dedicated fast memory blocks. These blocks can be configured as RAM, ROM or FIFO with user logic using PLBs.
Every device in the family has two user SPI ports, one of these (right side) SPI port also supports programming and configuration of the device. The iCE40 Ultra also includes two user I[2] C ports, two Oscillators, and high current RGB and IR LED sinks.
© 2018-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02028-2.4
9
**iCE40 Ultra Family Data Sheet Data Sheet**
## **3.1.1. PLB Blocks**
The core of the iCE40 Ultra device consists of Programmable Logic Blocks (PLB) which can be programmed to perform logic and arithmetic functions. Each PLB consists of eight interconnected Logic Cells (LC) as shown in Figure 3.2. Each LC contains one LUT and one register.
**==> picture [366 x 267] intentionally omitted <==**
**----- Start of picture text -----**<br>
Shared Block-Level Controls<br>Programmable Clock<br>Logic Block (PLB)<br>Enable<br>FCOUT 1<br>Set/Reset<br>0 Logic Cell<br>eo -<br>Carry Logic<br>DFF O<br>I0 D Q<br>EN<br>I1<br>LUT SR<br>I2<br>I3<br>FCIN<br>Four-input Flip-flop with<br>Look-Up Table optional enable and<br>(LUT) set or reset controls<br>= Statically defined by configuration program<br>8 Logic Cells (LCs)<br>**----- End of picture text -----**<br>
**Figure 3.2. PLB Block Diagram**
## **3.1.1.1. Logic Cells**
Each Logic Cell includes three primary logic elements shown in Figure 3.2.
- A four-input Look-Up Table (LUT) builds any combinational logic function, of any complexity, requiring up to four inputs. Similarly, the LUT element behaves as a 16x1 Read-Only Memory (ROM). Combine and cascade multiple LUTs to create wider logic functions.
- A ‘D’-style Flip-Flop (DFF), with an optional clock-enable and reset control input, builds sequential logic functions. Each DFF also connects to a global reset signal that is automatically asserted immediately following device configuration.
- Carry Logic boosts the logic efficiency and performance of arithmetic functions, including adders, subtracters, comparators, binary counters and some wide, cascaded logic functions.
Table 3.1 lists the logic cell signals.
**Table 3.1. Logic Cell Signal Descriptions**
|**Function**|**Type**|**Signal Name**|**Description**|
|---|---|---|---|
|Input|Data signal|I0, I1, I2, I3|Inputs to LUT|
|Input|Control signal|Enable|Clock enable shared by all LCs in the PLB|
|Input|Control signal|Set/Reset*|Asynchronous or synchronous local set/reset shared by<br>all LCs in the PLB.|
|Input|Control signal|Clock|Clock one of the eight Global Buffers, or from the<br>general-purpose interconnects fabric shared by all LCs<br>in the PLB|
|Input|Inter-PLB signal|FCIN|Fast carry in|
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**iCE40 Ultra Family Data Sheet Data Sheet**
|**Function**|**Type**|**Signal Name**|**Description**|
|---|---|---|---|
|Output|Data signals|O|LUT or registered output|
|Output|Inter-PFU signal|FCOUT|Fast carry out|
***Note** : If Set/Reset is not used, then the flip-flop is never set/reset, except when cleared immediately after configuration.
## **3.1.2. Routing**
There are many resources provided in the iCE40 Ultra devices to route signals individually with related control signals. The routing resources consist of switching circuitry, buffers and metal interconnect (routing) segments.
The inter-PLB connections are made with three different types of routing resources: Adjacent (spans two PLBs), x4 (spans five PLBs) and x12 (spans thirteen PLBs). The adjacent, x4 and x12 connections provide fast and efficient connections in the diagonal, horizontal and vertical directions.
The design tool takes the output of the synthesis tool and places and routes the design.
## **3.1.3. Clock/Control Distribution Network**
Each iCE40 Ultra device has six global inputs, two pins on the top bank and four pins on the bottom bank.
These global inputs can be used as high fanout nets, clock, reset or enable signals. The dedicated global pins are identified as Gxx and each drives one of the eight global buffers. The global buffers are identified as GBUF[7:0]. These six inputs may be used as general purpose I/O if they are not used to drive the clock nets.
Table 3.2 lists the connections between a specific global buffer and the inputs on a PLB. All global buffers optionally connect to the PLB CLK input. Any four of the eight global buffers can drive logic inputs to a PLB. Even-numbered global buffers optionally drive the Set/Reset input to a PLB. Similarly, odd-numbered buffers optionally drive the PLB clockenable input. GBUF[7:6, 3:0] can connect directly to G[7:6, 3:0] pins respectively. GBUF4 and GBUF5 can connect to the two on-chip Oscillator Generators (GBUF4 connects to LFOSC, GBUF5 connects to HFOSC).
**Table 3.2. Global Buffer (GBUF) Connections to Programmable Logic Blocks**
|**Global Buffer**|**LUT Inputs**|**Clock**|**Reset**|**Clock Enable**|
|---|---|---|---|---|
|GBUF0|Yes, any 4 of 8<br>GBUF Inputs|||—|
|GBUF1|||—||
|GBUF2||||—|
|GBUF3|||—||
|GBUF4||||—|
|GBUF5|||—||
|GBUF6||||—|
|GBUF7|||—||
The maximum frequency for the global buffers are listed in Table 4.17.
## **3.1.3.1. Global Hi-Z Control**
The global high-impedance control signal, GHIZ, connects to all I/O pins on the iCE40 Ultra device. This GHIZ signal is automatically asserted throughout the configuration process, forcing all user I/O pins into their high-impedance state.
## **3.1.3.2. Global Reset Control**
The global reset control signal connects to all PLB and PIO flip-flops on the iCE40 Ultra device. The global reset signal is automatically asserted throughout the configuration process, forcing all flip-flops to their defined wake-up state. For PLB flip-flops, the wake-up state is always reset, regardless of the PLB flip-flop primitive used in the application.
## **3.1.4. sysCLOCK Phase Locked Loops (PLLs)**
The sysCLOCK PLLs provide the ability to synthesize clock frequencies. The iCE40 Ultra devices have one sysCLOCK PLL. REFERENCECLK is the reference frequency input to the PLL and its source can come from an external I/O pin, the internal Oscillator Generators from internal routing. EXTFEEDBACK is the feedback signal to the PLL which can come
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**iCE40 Ultra Family Data Sheet Data Sheet**
from internal routing or an external I/O pin. The feedback divider is used to multiply the reference frequency and thus synthesize a higher frequency clock output.
The PLLOUT output has an output divider, thus allowing the PLL to generate different frequencies for each output. The output divider can have a value from 1 to 64 (in increments of 2X). The PLLOUT outputs can all be used to drive the iCE40 Ultra global clock network directly or general purpose routing resources can be used.
The LOCK signal is asserted when the PLL determines it has achieved lock and de-asserted if a loss of lock is detected. A block diagram of the PLL is shown in Figure 3.3.
The timing of the device registers can be optimized by programming a phase shift into the PLLOUT output clock which will advance or delay the output clock with reference to the REFERENCECLK clock. This phase shift can be either programmed during configuration or can be adjusted dynamically. In dynamic mode, the PLL may lose lock after a phase adjustment on the output used as the feedback source and not relock until the tLOCK parameter has been satisfied.
For more details, refer to iCE40 sysCLOCK PLL Design and Usage Guide (FPGA-TN-02052).
**==> picture [448 x 198] intentionally omitted <==**
**----- Start of picture text -----**<br>
RESET<br>BYPASS<br>BYPASS<br>GNDPLL VCCPLL<br>Phase<br>REFERENCECLK DIVR Detector RANGE Voltage DIVQ<br>Input Low-Pass Controlled VCO<br>Divider Filter Oscillator Divider<br>(VCO)<br>SIMPLE<br>DIVF<br>PLLOUTCORE<br>Feedback Divider Fine Delay<br>Fine Delay Adjustment<br>Adjustment Shifter Phase Output Port PLLOUTGLOBAL<br>Feedback<br>Feedback_Path<br>DYNAMICDELAY[7:0] LOCK<br>EXTFEEDBACK EXTERNAL<br>LATCHINPUTVALUE Low Power mode<br>(iCEgate enabled)<br>**----- End of picture text -----**<br>
**Figure 3.3. PLL Diagram**
Table 3.3 provides signal descriptions of the PLL block.
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**iCE40 Ultra Family Data Sheet Data Sheet**
**Table 3.3. PLL Signal Descriptions**
|**Signal Name**|**Direction**|**Description**|
|---|---|---|
|REFERENCECLK|Input|Input reference clock|
|BYPASS|Input|The BYPASS control selects which clock signal connects to the PLLOUT output.<br>0 – PLL generated signal<br>1 – REFERENCECLK|
|EXTFEEDBACK|Input|External feedback input to PLL. Enabled when the FEEDBACK_PATH attribute is set<br>to EXTERNAL.|
|DYNAMICDELAY[7:0]|Input|Fine delay adjustment control inputs. Enabled when DELAY_ADJUSTMENT_MODE<br>is set to DYNAMIC.|
|LATCHINPUTVALUE|Input|When enabled, puts the PLL into low-power mode; PLL output is held static at the<br>last input clock value. Set ENABLE ICEGATE_PORTA and PORTB to ‘1’ to enable.|
|PLLOUTGLOBAL|Output|Output from the Phase-Locked Loop (PLL). Drives a global clock network on the<br>FPGA. The port has optimal connections to global clock buffers GBUF4 and GBUF5.|
|PLLOUTCORE|Output|Output clock generated by the PLL, drives regular FPGA routing. The frequency<br>generated on this output is the same as the frequency of the clock signal generated<br>on the PLLOUTLGLOBALport.|
|LOCK|Output|When High, indicates that the PLL output is phase aligned or locked to the input<br>reference clock.|
|RESET|Input|Active low reset.|
|SCLK|Input|Input, Serial Clock used for re-programming PLL settings.|
|SDI|Input|Input, Serial Data used for re-programming PLL settings.|
## **3.1.5. sysMEM Embedded Block RAM Memory**
Larger iCE40 Ultra device includes multiple high-speed synchronous sysMEM Embedded Block RAMs (EBRs), each 4 kbit in size. This memory can be used for a wide variety of purposes including data buffering and FIFO.
## **3.1.5.1. sysMEM Memory Block**
The sysMEM block can implement single port, pseudo dual port, or FIFO memories with programmable logic resources. Each block can be used in a variety of depths and widths as listed in Table 3.4.
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**iCE40 Ultra Family Data Sheet Data Sheet**
**Table 3.4. sysMEM Block Configurations***
|**Block RAM**<br>**Configuration**|**Block RAM**<br>**Configuration**<br>**and Size**|**WADDR Port**<br>**Size (Bits)**|**WDATA Port**<br>**Size (Bits)**|**RADDR Port**<br>**Size (Bits)**|**RDATA Port**<br>**Size (Bits)**|**MASK Port**<br>**Size (Bits)**|
|---|---|---|---|---|---|---|
|SB_RAM256x16<br>SB_RAM256x16NR<br>SB_RAM256x16NW<br>SB_RAM256x16NRNW|256x16 (4 k)|8 [7:0]|16 [15:0]|8 [7:0]|16 [15:0]|16 [15:0]|
|SB_RAM512x8<br>SB_RAM512x8NR<br>SB_RAM512x8NW<br>SB_RAM512x8NRNW|512x8 (4 k)|9 [8:0]|8 [7:0]|9 [8:0]|8 [7:0]|No Mask Port|
|SB_RAM1024x4<br>SB_RAM1024x4NR<br>SB_RAM1024x4NW<br>SB_RAM1024x4NRNW|1024x4 (4 k)|10 [9:0]|4 [3:0]|10 [9:0]|4 [3:0]|No Mask Port|
|SB_RAM2048x2<br>SB_RAM2048x2NR<br>SB_RAM2048x2NW<br>SB_RAM2048x2NRNW|2048x2 (4 k)|11 [10:0]|2 [1:0]|11 [10:0]|2 [1:0]|No Mask Port|
***Note** : For iCE40 Ultra, the primitive name without “Nxx” uses rising-edge Read and Write clocks. “NR” uses rising-edge Write clock and falling-edge Read clock. “NW” uses falling-edge Write clock and rising-edge Read clock. “NRNW” uses failing-edge clocks on both Read and Write.
## **3.1.5.2. RAM Initialization and ROM Operation**
If desired, the contents of the RAM can be pre-loaded during device configuration.
By preloading the RAM block during the chip configuration cycle and disabling the write controls, the sysMEM block can also be utilized as a ROM.
## **3.1.5.3. Memory Cascading**
Larger and deeper blocks of RAM can be created using multiple EBR sysMEM Blocks.
## **3.1.5.4. RAM4k Block**
Figure 3.4 shows the 256x16 memory configurations and their input/output names. In all the sysMEM RAM modes, the input data and addresses for the ports are registered at the input of the memory array.
**==> picture [248 x 201] intentionally omitted <==**
**----- Start of picture text -----**<br>
Write Port Read Port<br>a<br>WDATA[15:0] RDATA[15:0]<br>MASK[15:0]<br>WADDR[7:0] RADDR[7:0]<br>RAM4K<br>RAM Block<br>WE RE<br>(256x16)<br>WCLKE RCLKE<br>WCLK RCLK<br>_ _<br>**----- End of picture text -----**<br>
## **Figure 3.4. sysMEM Memory Primitives**
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**iCE40 Ultra Family Data Sheet Data Sheet**
Table 3.5 lists the EBR signals.
**Table 3.5. EBR Signal Descriptions**
|**Signal Name**|**Direction**|**Description**|
|---|---|---|
|WDATA[15:0]|Input|Write Data input.|
|MASK[15:0]|Input|Masks write operations for individual data bit-lines.<br>0 – Write bit<br>1 – Do not write bit|
|WADDR[7:0]|Input|Write Address input. Selects one of 256 possible RAM locations.|
|WE|Input|Write Enable input.|
|WCLKE|Input|Write Clock Enable input.|
|WCLK|Input|Write Clock input. Default rising-edge, but with falling-edge option.|
|RDATA[15:0]|Output|Read Data output.|
|RADDR[7:0]|Input|Read Address input. Selects one of 256 possible RAM locations.|
|RE|Input|Read Enable input.|
|RCLKE|Input|Read Clock Enable input.|
|RCLK|Input|Read Clock input. Default rising-edge, but with falling-edge option.|
For further information on the sysMEM EBR block, refer to Memory Usage Guide for iCE40 Devices (FPGA-TN-02002).
## **3.1.6. sysDSP**
The iCE40 Ultra family provides an efficient sysDSP architecture that is very suitable for low-cost Digital Signal Processing (DSP) functions for mobile applications. Typical functions used in these applications are Multiply, Accumulate, and Multiply-Accumulate. The block can also be used for simple Add and Subtract functions.
## **3.1.6.1. iCE40 Ultra sysDSP Architecture Features**
The iCE40 Ultra sysDSP supports many functions that include the following:
- Single 16-bit x 16-bit Multiplier, or two independent 8-bit x 8-bit Multipliers
- Optional independent pipeline control on Input Register, Output Register, and Intermediate Register for faster clock performance
- Single 32-bit Accumulator, or two independent 16-bit Accumulators
- Single 32-bit, or two independent 16-bit Adder/Subtracter functions, registered or asynchronous
- Cascadable to create wider Accumulator blocks
Figure 3.5 shows the block diagram of the sysDSP block. The block consists of a Multiplier section followed by an Accumulator, with optional Input Register, Output Register and Intermediate Register for faster clock performance.
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**iCE40 Ultra Family Data Sheet Data Sheet**
**Figure 3.5. sysDSP Functional Block Diagram (16-bit x 16-bit Multiply-Accumulate)**
**Table 3.6. Output Block Port Description**
|**Primitive**<br>**Port Name**<br>**Width**|**Width**|**Input/**<br>**Output**|**Function**|**Default**|
|---|---|---|---|---|
|CLK|1|Input|Clock Input. Applies to all clocked elements in the sysDSP<br>block|—|
|CE|1|Input|Clock Enable Input. Applies to all clocked elements in the<br>sysDSP block.<br>0 – Not enabled<br>1 – Enabled|0 – Enabled|
|A[15:0]|16|Input|Input to the A Register. Feeds the Multiplier or is a direct<br>input to the Adder Accumulator|16'b0|
|B[15:0]|16|Input|Input to the B Register. Feeds the Multiplier or is a direct<br>input to the Adder Accumulator|16'b0|
|C[15:0]|16|Input|Input to the C Register. It is a direct input to the Adder<br>Accumulator|16'b0|
|D[15:0]|16|Input|Input to the D Register. It is a direct input to the Adder<br>Accumulator|16'b0|
|AHOLD|1|Input|A Register Hold.<br>0 – Update<br>1 – Hold|0 – Update|
|BHOLD|1|Input|B Register Hold.<br>0 – Update<br>1 – Hold|0 – Update|
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**iCE40 Ultra Family Data Sheet Data Sheet**
|**Primitive**<br>**Port Name**|**Width**|**Input/**<br>**Output**|**Function**|**Default**|
|---|---|---|---|---|
|CHOLD<br>~~ee~~|1<br>~~ee~~|Input<br>~~ee~~|C Register Hold.<br>0 – Update<br>1 – Hold<br>~~ee~~|0 – Update<br>~~ee~~|
|DHOLD|1|Input|D Register Hold.<br>0 – Update<br>1 – Hold|0 – Update|
|IRSTTOP|1|Input|Reset input to A and C input registers, and the pipeline<br>registers in the upper half of the Multiplier Section.<br>0 – No reset<br>1 – Reset|0 – No reset|
|IRSTBOT|1|Input|Reset input to B and D input registers, and the pipeline<br>registers in the lower half of the Multiplier Section. It also<br>resets the Multiplier result pipeline register.<br>0 – No reset<br>1 – Reset|0 – No reset|
|O[31:0]|32|Output|Output of the sysDSP block. This output can be:<br><br>O[31:0] – 32-bit result of 16x16 Multiplier or MAC<br><br>O[31:16] – 16-bit result of 8x8 upper half Multiplier<br>or MAC<br><br>O[15:0] – 16-bit result of 8x8 lower half Multiplier or<br>MAC|—|
|OHOLDTOP|1|Input|High-order (upper half) Accumulator Register Hold.<br>0 – Update<br>1 – Hold|0 – Update|
|ORSTTOP|1|Input|Reset input to high-order (upper half) bits of the<br>Accumulator Register.<br>0 – No reset<br>1 – Reset|0 – No reset|
|OLOADTOP|1|Input|High-order (upper half) Accumulator Register<br>Accumulate/Load control.<br>0 – Accumulate, register is loaded with Adder/Subtracter<br>results<br>1 – Load, register is loaded with Input C or C Register|0 – Accumulate|
|ADDSUBTOP|1|Input|High-order (upper half) Accumulator Add or Subtract<br>select.<br>0 – Add<br>1 – Subtract|0 – Add|
|OHOLDBOT|1|Input|Low-order (lower half) Accumulator Register Hold.<br>0 – Update<br>1 – Hold|0 – Update|
|ORSTBOT|1|Input|Reset input to Low-order (lower half) bits of the<br>Accumulator Register.<br>0 –No reset<br>1 – Reset|0 – No reset|
|OLOADBOT|1|Input|Low-order (lower half) Accumulator Register<br>Accumulate/Load control.<br>0 – Accumulate, register is loaded with Adder/Subtracter<br>results<br>1 – Load, register is loaded with Input C or C Register|0 – Accumulate|
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**iCE40 Ultra Family Data Sheet Data Sheet**
|**Primitive**<br>**Port Name**|**Width**|**Input/**<br>**Output**|**Function**|**Default**|
|---|---|---|---|---|
|ADDSUBBOT|1|Input|Low-order (lower half) Accumulator Add or Subtract<br>select.<br>0 – Add<br>1 – Subtract|0 – Add|
|ACCUMCI|1|Input|Cascade Carry/Borrow input from previous sysDSP block|—|
|CI|1|Input|Carry/Borrow input from lower logic tile|—|
|ACCUMCO|1|Output|Cascade Carry/Borrow output to next sysDSP block|—|
|CO|1|Output|Carry/Borrow output to higher logic tile|—|
|SIGNEXTIN|1|Input|Sign extension input from previous sysDSP block|—|
|SIGNEXTOUT|1|Output|Sing extension output to next sysDSP block|—|
The iCE40 Ultra sysDSP can support the following functions:
- 8-bit x 8-bit Multiplier
- 16-bit x 16-bit Multiplier
- 16-bit Adder/Subtracter
- 32-bit Adder/Subtracter
- 16-bit Accumulator
- 32-bit Accumulator
- 8-bit x 8-bit Multiply-Accumulate
- 16-bit x 16-bit Multiply-Accumulate
Figure 3.6 shows the path for an 8-bit x 8-bit Multiplier using the upper half of sysDSP block.
**==> picture [472 x 309] intentionally omitted <==**
**----- Start of picture text -----**<br>
Input Registers Multiplier SIGNE XTOUT ACCUMCO CO Accumulator<br>Q [3 1:1 6]<br>ADDSUBT OP<br>0 W<br>C[1 5 :0 ]CHOLD DHLDR Q 01C 0 C 16 x16 Pipeline 1C12 X ± 01 P DHLDR Q Q 0123 O [ 3 1 :1 6 ]<br>[15 :0] Registers 0 X [ 1 5] C9 High<br>A [1 5:0 ]AHOLD DHLDR Q 01C 1 A A[15B[15 :8]A[7 :0 ]:8 ] 8 x 8 D R Q 010C 4 [[15:0]15:0 ]FJ 8 x 8 =1 6[7:0][15:8] + P[31: 24] 16 x16 C10123 C11 HCI C 8 ORST TOOHOL DTOPOLO ADT OPP<br>IRST TOP B[15 :8 ] 8 x 8 C22 DHLD8 x8 Pow erS av eR Q 1C 6 [15:8] [15:8] + P[23: 16] L DPipeline RegisterQ 01 1 6 x1 6 =3 2H [31: 16 ] LCO<br>A[15 :8 ] 0 [15: 0]K HLDR C 7 [15: 0 ] LACCUMCO0 1<br>B[7 :0 ] 8 x 8 DHLDR Q 1C 6 [7:0] [7:0] + P[15: 8] Q [1 5:0]0 Y ADDSUBBOT<br>B [1 5:0 ]BHOLD DHLDR Q 01C 2 B A[7 :0 ]B[7 :0 ] 8 x 8 D R Q 01C 5 [15: 0]G [158 x8 = 1 6[7:0]:8 ] P[7: 0 ] 10C19Z [1 5] Z ± 01 R HLDD R Q S 0123 C16 O [ 1 5 :0 ]Low<br>1 C15<br>2 ORST BOTOHOL DBOT<br>3 LCI OLO ADBOT<br>0 D C17 C18<br>D[1 5 :0 ] D Q 1<br>DHOLD HLD<br>R C 3 ASGND =C2 3<br>BSGND=C2 4<br>IRST BOT<br>CLK 0 1<br>CE<br>SIGNE XTIN ACCUMCI CI (25 -FEB -2012 )<br>1<br>C13<br>0 1 2 3 C14<br>0<br>C21<br>0 1 2 3<br>0<br>1<br>C20<br>**----- End of picture text -----**<br>
**Figure 3.6. sysDSP 8-bit x 8-bit Multiplier**
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**iCE40 Ultra Family Data Sheet Data Sheet**
Figure 3.7 shows the path for a 16-bit x 16-bit Multiplier using both halves of sysDSP block.
**==> picture [460 x 321] intentionally omitted <==**
**----- Start of picture text -----**<br>
Input Registers Multiplier SIGNEXTOUT AC CUMC O CO Accumulator<br>Q[31:16]<br>ADDSUB TOP<br>0 W<br>CCHOLD[15:0] HL DD R Q 01C0 C 16x16 Pipeline 1C1 2 X ± 01 P DHL DR Q Q 0123 O[ 31:16]<br>[15:0] Registers 0 X[ 15] C9 High<br>AAHOLD[15:0] HL DD R Q 01C1 A AB[[A1515[7:::880]]] 8x8 D R Q 010C4 [[ 1515FJ::0]0] 8[[7x15:08:]8=]16 + P[31:24] 16x16 C1231 0 C1 1 HCI C8 ORSTTOPOHOLDTOPOLOA DTOP<br>B[15:8] 8x8 DHL DR Q 1C6 [15:8] [15:8] + P[23:16] Pipeline Register16x16=32 [31:16]<br>0 H<br>IRSTT OP C2 2 8x8 Pow erSave L D Q 1 LCO<br>A[15:8] 0 K[15:0] HL DR C7 [15:0] LAC CUMC O0 1<br>B[7:0] 8x8 DHL DR Q 1C6 [7:0] [7:0] + P[15:8] Q[150:0 Y ADDSUB BOT<br>B[15:0] D Q 01 AB[[77::00]] 8x8 D R Q 01C5 [15G:0] [815[7x::880]]=16 P[7:0] 1C1 9 Z ± 01 R DHL DR Q S 0123 O[ 15:0]<br>BHOLD HL DR C2 B 0 Z[15] C1 6 Low<br>1 C1 5<br>| 2 L id ORSTB OTOHOLDBOT<br>3 LCI OLOA DBOT<br>0 D C1 7 C1 8<br>DHOLDD[15:0] a HL DD R Q 1C3 ASGND=23BSG ND=24<br>IRSTB OT<br>CLK 0 1<br>CE<br>SIGNEXTIN AC CUMC I CI (25-FEB-2012)<br>0 2<br>0<br>2<br>0<br>0 1<br>1C3<br>1 3 1C4<br>1<br>1<br>C<br>0 1 2 3 2C<br>**----- End of picture text -----**<br>
**Figure 3.7. DSP 16-bit x 16-bit Multiplier**
## **3.1.7. sysIO Buffer Banks**
iCE40 Ultra devices have up to three I/O banks with independent VCCIO rails. The configuration SPI interface signals are powered by SPI_VCCIO1. On the 16 WLCSP package, VCCIO1 and VPP_2V5 are connected to the same pin on the package, and must meet the voltage requirement of both supplies. Refer to the
Pin Information Summary table.
## **3.1.7.1. Programmable I/O (PIO)**
The programmable logic associated with an I/O is called a PIO. The individual PIOs are connected to their respective sysIO buffers and pads. The PIOs are placed on the top and bottom of the devices.
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**iCE40 Ultra Family Data Sheet Data Sheet**
**Figure 3.8. I/O Bank and Programmable I/O Cell**
The PIO contains three blocks: an input register block, output register block iCEGate™ and tri-state register block. To save power, the optional iCEGate latch can selectively freeze the state of individual, non-registered inputs within an I/O bank. Note that the freeze signal is common to the bank. These blocks can operate in a variety of modes along with the necessary clock and selection logic.
## **3.1.7.2. Input Register Block**
The input register blocks for the PIOs on all edges contain registers that can be used to condition high-speed interface signals before they are passed to the device core.
## **3.1.7.3. Output Register Block**
The output register block can optionally register signals from the core of the device before they are passed to the sysIO buffers.
Figure 3.9 shows the input/output register block for the PIOs.
© 2018-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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**iCE40 Ultra Family Data Sheet Data Sheet**
**==> picture [335 x 420] intentionally omitted <==**
**----- Start of picture text -----**<br>
CLOCK_ENABLE PIO Pair<br>OUTPUT_CLK<br>INPUT_CLK<br>(1,0)<br>LATCH_INPUT_VALUE<br>D_IN_1<br>D_IN_0<br>Pad<br>D_OUT_1<br>D_OUT_0<br>(1,0)<br>0<br>1<br>OUTPUT_ENABLE = ,<br>(1,0)<br>LATCH_INPUT_VALUE<br>En<br>D_IN_1<br>D_IN_0 jee<br>Pad<br>D_OUT_1<br>D_OUT_0<br>(1,0)<br>0<br>1<br>OUTPUT_ENABLE<br>= Statically defined by configuration program.<br>**----- End of picture text -----**<br>
**Figure 3.9. I/O Register Block Diagram**
**Table 3.7. PIO Signal List**
|**Pin Name**|**I/O Type**|**Description**|
|---|---|---|
|OUTPUT_CLK|Input|Output register clock|
|CLOCK_ENABLE|Input|Clock enable|
|INPUT_CLK|Input|Input register clock|
|OUTPUT_ENABLE|Input|Output enable|
|D_OUT_0/1|Input|Data from the core|
|D_IN_0/1|Output|Data to the core|
|LATCH_INPUT_VALUE|Input|Latches/holds the Input Value|
© 2018-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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**iCE40 Ultra Family Data Sheet Data Sheet**
## **3.1.8. sysIO Buffer**
Each I/O is associated with a flexible buffer referred to as a sysIO buffer. These buffers are arranged around the periphery of the device in groups referred to as banks. The sysIO buffers allow users to implement a wide variety of standards that are found in today’s systems with LVCMOS interfaces.
## **3.1.8.1. Typical I/O Behavior during Power-up**
The internal power-on-reset (POR) signal is deactivated when VCC, SPI_VCCIO1 and VPP_2V5 reach the level defined in Table 4.4. After the POR signal is deactivated, the FPGA core logic becomes active. You must ensure that all VCCIO banks are active with valid input logic levels to properly control the output logic states of all the I/O banks that are critical to the application. The default configuration of the I/O pins in a device prior to configuration is tri-stated with a weak pull-up to VCCIO. The I/O pins maintain the pre-configuration state until VCC, SPI_VCCIO1 and VPP_2V5 reach the defined levels. The I/Os take on the software user-configured settings only after POR signal is deactivated and the device performs a proper download/configuration. Unused I/Os are automatically blocked and the pull-up termination is disabled.
## **3.1.8.2. Supported Standards**
The iCE40 Ultra sysIO buffer supports both single-ended input/output standards, and used as differential comparators. The buffer supports the LVCMOS 1.8 V, 2.5 V, and 3.3 V standards. The buffer has individually configurable options for bus maintenance (weak pull-up or none).
Table 3.8 and Table 3.9 show the I/O standards (together with their supply and reference voltages) supported by the iCE40 Ultra devices.
## **3.1.8.3. Differential Comparators**
The iCE40 Ultra devices provide differential comparator on pairs of I/O pins. These comparators are useful in some mobile applications. See the
Pin Information Summary section to locate the corresponding paired I/Os with differential comparators.
**Table 3.8. Supported Input Standards**
|**I/O Standard**|**VCCIO(Typical)**|**VCCIO(Typical)**|**VCCIO(Typical)**|
|---|---|---|---|
||**3.3 V**|**2.5 V**|**1.8 V**|
|**Single-Ended Interfaces**||||
|LVCMOS33|Yes|—|—|
|LVCMOS25|—|Yes|—|
|LVCMOS18|—|—|Yes|
## **Table 3.9. Supported Output Standards**
|**I/O Standard**|**VCCIO(Typical)**|
|---|---|
|**Single-Ended Interfaces**||
|LVCMOS33|3.3 V|
|LVCMOS25|2.5 V|
|LVCMOS18|1.8 V|
© 2018-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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FPGA-DS-02028-2.4
**iCE40 Ultra Family Data Sheet Data Sheet**
## **3.1.9. On-Chip Oscillator**
The iCE40 Ultra devices feature two different frequency Oscillator. One is tailored for low-power operation that runs at low frequency (LFOSC). Both Oscillators are controlled with internally generated current.
The LFOSC runs at nominal frequency of 10 kHz. The high frequency oscillator (HFOSC) runs at a nominal frequency of 48 MHz, divisible to 24 MHz, 12 MHz, or 6 MHz by user option. The LFOSC can be used to perform all always-on functions, with the lowest power possible. The HFOSC can be enabled when the always-on functions detect a condition that would need to wake up the system to perform higher frequency functions.
## **3.1.10. User I[2] C IP**
The iCE40 Ultra devices have two I[2] C IP cores. Either of the two cores can be configured either as an I[2] C master or as an I[2] C slave. The pins for the I[2] C interface are not pre-assigned. User can use any General Purpose I/O pins.
In each of the two cores, there are options to delay the either the input or the output, or both, by 50 ns nominal, using dedicated on-chip delay elements. This provides an easier interface with any external I[2] C components.
When the IP core is configured as master, it will be able to control other devices on the I[2] C bus through the preassigned pin interface. When the core is configured as the slave, the device will be able to provide I/O expansion to an I[2] C Master. The I[2] C cores support the following functionality:
- Master and Slave operation
- 7-bit and 10-bit addressing
- Multi-master arbitration support
- Clock stretching
- Up to 400 kHz data transfer speed
- General Call support
- Optionally delaying input or output data, or both
For further information on the User I[2] C, refer to iCE40 SPI/I2C Hardened IP Usage Guide (FPGA-TN-02010).
## **3.1.11. User SPI IP**
The iCE40 Ultra devices have two SPI IP cores. The pins for the SPI interface are not pre-assigned. User can use any General Purpose I/O pins. Both SPI IP cores can be configured as a SPI master or as a slave. When the SPI IP core is configured as a master, it controls the other SPI enabled devices connected to the SPI Bus. When SPI IP core is configured as a slave, the device will be able to interface to an external SPI master.
The SPI IP core supports the following functions:
- Configurable Master and Slave modes
- Full-Duplex data transfer
- Mode fault error flag with CPU interrupt capability
- Double-buffered data register
- Serial clock with programmable polarity and phase
- LSB First or MSB First Data Transfer
For further information on the User SPI, refer to iCE40 SPI/I2C Hardened IP Usage Guide (FPGA-TN-02010).
## **3.1.12. High Current LED Drive I/O Pins**
The iCE40 Ultra family devices offer multiple high current LED drive outputs in each device in the family to allow the iCE40 Ultra product to drive LED signals directly on mobile applications.
There are three outputs on each device that can sink up to 24 mA current. These outputs are open-drain outputs, and provides sinking current to an LED connecting to the positive supply. These three outputs are designed to drive the RBG LEDs, such as the service LED found in a lot of mobile devices. An embedded RGB PWM IP is also offered in the family. This RGB drive current is user programmable from 4 mA to 24 mA, in increments of 4 mA. This output functions as General Purpose I/O with open-drain when the high current LED drive is not needed.
© 2018-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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**iCE40 Ultra Family Data Sheet Data Sheet**
There is one output on each device that can sink up to 500 mA current. This output is open-drain, and provides sinking current to drive an external IR LED connecting to the positive supply. This IR drive current is user programmable from 50 mA to 500 mA in increments of 50 mA. This output functions as General Purpose I/O with opendrain when the high current LED drive is not needed.
## **3.1.13. Embedded PWM IP**
To provide an easier usage of the RGB high current drivers to drive RGB LED, a Pulse-Width Modulator IP can be embedded into the user design. This PWM IP provides the flexibility for user to dynamically change the settings on the ON-time duration, OFF-time duration, and ability to turn the LED lights on and off gradually with user set breath-on and breath-off time.
- For additional information on the PWM IP, refer to iCE40 LED Driver Usage Guide (FPGA-TN-02021).
## **3.1.14. Non-Volatile Configuration Memory**
All iCE40 Ultra devices provide a Non-Volatile Configuration Memory (NVCM) block which can be used to configure the device.
- For more information on the NVCM, refer to iCE40 Programming and Configuration (FPGA-TN-02001).
© 2018-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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FPGA-DS-02028-2.4
**iCE40 Ultra Family Data Sheet Data Sheet**
## **3.2. iCE40 Ultra Programming and Configuration**
This section describes the programming and configuration of the iCE40 Ultra family.
## **3.2.1. Device Programming**
The NVCM memory can be programmed through the SPI port. The SPI port is located in Bank 1, using SPI_VCCIO1 power supply.
## **3.2.2. Device Configuration**
There are various ways to configure the Configuration RAM (CRAM), using SPI port, including:
- From an SPI Flash (Master SPI mode)
- System microprocessor to drive a Serial Slave SPI port (SSPI mode)
- For more details on configuring the iCE40 Ultra, refer to iCE40 Programming and Configuration (FPGA-TN-02001)
## **3.2.3. Power Saving Options**
The iCE40 Ultra devices feature iCEGate and PLL low power mode to allow users to meet the static and dynamic power requirements of their applications. Table 3.10 describes the function of these features.
**Table 3.10. iCE40 Ultra Power Saving Features Description**
|**Device Subsystem**|**Feature Description**|
|---|---|
|PLL|When LATCHINPUTVALUE is enabled, puts the PLL into low-power mode; PLL output held static at last<br>input clock value.|
|iCEGate|To save power, the optional iCEGate latch can selectively freeze the state of individual, non-registered<br>inputs within an I/O bank. Registered inputs are effectively frozen by their associated clock or clock-<br>enable control.|
© 2018-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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**iCE40 Ultra Family Data Sheet Data Sheet**
## **4. DC and Switching Characteristics**
## **4.1. Absolute Maximum Ratings**
**Table 4.1. Absolute Maximum Ratings[1, 2. 3]**
|**Parameter**|**Min**|**Max**|**Unit**|
|---|---|---|---|
|Supply Voltage VCC|–0.5|1.42|V|
|Output Supply Voltage VCCIO|–0.5|3.60|V|
|NVCM Supply Voltage VPP_2V5|–0.5|3.60|V|
|PLL Supply Voltage VCCPLL|–0.5|1.42|V|
|I/O Tri-state Voltage Applied|–0.5|3.60|V|
|Dedicated Input Voltage Applied|–0.5|3.60|V|
|Storage Temperature (Ambient)|–65|150|°C|
|Junction Temperature (TJ)|–65|125|°C|
## **Notes** :
1. Stress above those listed under Absolute Maximum Ratings may cause permanent damage to the device. Functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
2. Compliance with Thermal Management document is required.
3. All voltages referenced to GND.
## **4.2. Recommended Operating Conditions**
**Table 4.2. Recommended Operating Conditions[1]**
|**Symbol**<br>~~a~~|**Parameter**|**Parameter**|**Min**|**Max**|**Unit**|
|---|---|---|---|---|---|
|VCC1<br>~~a~~|Core Supply Voltage||1.14|1.26|V|
|VPP_2V5<br>~~**e**e~~|VPP_2V5NVCM<br>Programming and<br>Operating Supply Voltage|Slave SPI Configuration<br>~~es~~|1.714<br>~~es~~|3.46<br>~~es~~|V<br>~~es~~|
|||Master SPI Configuration<br>~~es~~<br>~~es~~|2.30<br>~~es~~<br>~~es~~|3.46<br>~~es~~<br>~~es~~|V<br>~~es~~<br>~~es~~|
|||Configuration from NVCM<br>~~es~~|2.30<br>~~es~~|3.46<br>~~es~~|V<br>~~es~~|
|||NVCM Programming<br>~~es~~<br>~~ed~~|2.30<br>~~es~~<br>~~ed~~|3.00<br>~~es~~<br>~~ed~~|V<br>~~es~~<br>~~ed~~|
|VCCIO1, 2, 3<br>~~**e**e~~|I/O Driver SupplyVoltage|VCCIO_0, SPI_VCCIO1, VCCIO_2<br>~~ed~~|1.71<br>~~ed~~|3.46<br>~~ed~~|V<br>~~ed~~|
|VCCPLL<br>~~**e**e~~|PLL SupplyVoltage<br>~~ed~~<br>~~e~~||1.14<br>~~ed~~<br>~~e~~|1.26<br>~~ed~~<br>~~e~~|V<br>~~ed~~<br>~~e~~|
|tJCOM<br>~~a~~|Junction Temperature Commercial Operation<br>||0<br>|85<br>|°C<br>|
|tJIND<br>~~eG~~|Junction Temperature, Industrial Operation<br>~~eG~~||–40<br>~~eG~~|100<br>~~eG~~|°C<br>~~eG~~|
|tPROG<br>~~eG~~<br>~~a~~|Junction Temperature NVCM Programming<br>~~eG~~||10<br>~~eG~~|30<br>~~eG~~|°C<br>~~eG~~|
**Notes** :
1. Like power supplies must be tied together if they are at the same supply voltage and they meet the power up sequence requirement. See the Power-up Supply Sequence section. VCC and VCCPLL are recommended to be tied together to the same supply with an RC-based noise filter between them. Refer to iCE40 Hardware Checklist (FPGA-TN-02006).
2. See recommended voltages by I/O standard in subsequent table.
3. VCCIO pins of unused I/O banks should be connected to the VCC power supply on boards.
4. VPP_2V5 can, optionally, be connected to a 1.8 V (+/-5%) power supply in Slave SPI Configuration modes subject to the condition that none of the HFOSC/LFOSC and RGB LED driver features are used. Otherwise, VPP_2V5 must be connected to a power supply with a minimum 2.30 V level.
© 2018-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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**iCE40 Ultra Family Data Sheet Data Sheet**
## **4.3. Power Supply Ramp Rates**
**Table 4.3. Power Supply Ramp Rates[1, 2]**
|**Symbol**|**Parameter**|**Min**|**Max**|**Unit**|
|---|---|---|---|---|
|tRAMP|Power supply ramp rates for all power supplies|0.6|10|V/ms|
**Notes** :
1. Assumes monotonic ramp rates.
2. Power up sequence must be followed. See the Power-up Supply Sequence section.
## **4.4. Power-On Reset**
All iCE40 Ultra devices have on-chip Power-On-Reset (POR) circuitry to ensure proper initialization of the device. Only three supply rails are monitored by the POR circuitry as follows: (1) VCC, (2) SPI_VCCIO1 and (3) VPP_2V5. All other supply pins have no effect on the power-on reset feature of the device. Note that all supply voltage pins must be connected to power supplies for normal operation (including device configuration).
## **4.5. Power-up Supply Sequence**
It is recommended to bring up the power supplies in the following order. Note that there is no specified timing delay between the power supplies, however, there is a requirement for each supply to reach a level of 0.5 V, or higher, before any subsequent power supplies in the sequence are applied.
1. **VCC** and **VCCPLL** should be the first two supplies to be applied. Note that these two supplies can be tied together subject to the recommendation to include an RC-based noise filter on the VCCPLL. Refer to iCE40 Hardware Checklist (FPGA-TN-02006).
2. **SPI_VCCIO1** should be the next supply, and can be applied anytime after the previous supplies (VCC and VCCPLL) have reached a level of 0.5 V or higher.
3. **VPP_2V5** should be the next supply, and can be applied anytime after previous supplies (VCC, VCCPLL and SPI_VCCIO1) have reached a level of 0.5 V or higher.
4. **Other Supplies** (VCCIO0 and VCCIO2) do not affect device power-up functionality, and they can be applied any time after the initial power supplies (VCC and VCCPLL) have reached a level of 0.5 V or greater.
There is no power down sequence required. However, when partial power supplies are powered down, it is required that the above sequence is followed when these supplies are powered up again.
## **4.6. External Reset**
When all power supplies have reached their minimum operating voltage defined in Table 4.2, it is required to either keep CRESET_B LOW, or toggle CRESET_B from HIGH to LOW, for a duration of tCRESET_B, and release it to go HIGH, to start configuration download from either the internal NVCM or the external Flash memory.
Figure 4.1 shows Power-Up sequence when SPI_VCCIO1 and VPP_2V5 are not connected together, and the CRESET_B signal triggers configuration download. Figure 4.2 shows when SPI_VCCIO1 and VPP_2V5 connected together.
All power supplies should be powered up during configuration. Before and during configuration, the I/Os are held in tristate. I/Os are released to user functionality once the device has finished configuration.
© 2018-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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**iCE40 Ultra Family Data Sheet Data Sheet**
**==> picture [312 x 112] intentionally omitted <==**
**----- Start of picture text -----**<br>
V VPP_2V5, VCCIO0 and VCCIO2= 2.5 V / 3.3 V<br>SUPPLY(MIN)<br>SPI_VCCIO1 = 1.8 V<br>VCC/VCC_PLL = 1.2 V<br>CRESET_B<br>t<br>0.5 V CRESET_B<br>**----- End of picture text -----**<br>
**Figure 4.1. Power Up Sequence with SPI_VCCIO1 and VPP_2V5 Not Connected Together**
**==> picture [355 x 74] intentionally omitted <==**
**----- Start of picture text -----**<br>
VSUPPLY(MIN) SPI_VCCIO, VPP_2V5, VCCIO0 and VCCIO2= 1.8 V / 2.5 V / 3.3 V<br>VCC/VCC_PLL = 1.2 V<br>CRESET_B<br>t<br>CRESET_B<br>0.5 V<br>**----- End of picture text -----**<br>
**Figure 4.2. Power Up Sequence with All Supplies Connected Together**
## **4.7. Power-On-Reset Voltage Levels**
**Table 4.4. Power-On-Reset Voltage Levels***
|**Symbol**|**Parameter**|**Parameter**|**Min**|**Max**|**Unit**|
|---|---|---|---|---|---|
|VPORUP|Power-On-Reset ramp up trip point (circuit<br>monitoring VCC, SPI_VCCIO1, and VPP_2V5)|VCC|0.62|0.92|V|
|||SPI_VCCIO1|0.87|1.50|V|
|||VPP_2V5|0.90|1.53|V|
|VPORDN|Power-On-Reset ramp down trip point (circuit<br>monitoring VCC, SPI_VCCIO1, and VPP_2V5)|VCC|—|0.79|V|
|||SPI_VCCIO1|—|1.50|V|
|||VPP_2V5|—|1.53|V|
**Note** : These POR trip points are only provided for guidance. Device operation is only characterized for power supply voltages specified under recommended operating conditions.
© 2018-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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**iCE40 Ultra Family Data Sheet Data Sheet**
## **4.8. ESD Performance**
Please contact Lattice Semiconductor for additional information.
## **4.9. DC Electrical Characteristics**
Over recommended operating conditions.
**Table 4.5. DC Electrical Characteristics**
|**Symbol**<br>~~a ~~<br>~~a~~<br>~~a~~|**Parameter**<br> ~~a~~<br>~~a~~<br>|**Condition**<br>~~GG~~<br>~~Ge~~<br>|**Min**<br>~~GG~~<br>~~GG~~<br>|**Typ**<br>~~GG~~<br>~~GO~~<br>~~GG~~<br>|**Max**<br>~~GG~~<br>~~GO~~<br>|**Unit**<br>~~GG~~<br>|
|---|---|---|---|---|---|---|
|IIL, IIH1, 3, 4<br>~~a ~~<br>~~a~~|Input or I/O Leakage<br> ~~a~~<br>|0 V < VIN< VCCIO+ 0.2 V<br>~~Ge~~<br>|—<br>~~GG~~<br>|—<br>~~GO~~<br>~~GG~~<br>|±10<br>~~GO~~<br>|µA<br>|
|C1<br> <br>~~a~~|I/O Capacitance2<br> ~~a~~<br>~~ee~~|VCCIO= 3.3 V, 2.5 V, 1.8 V<br>VCC= Typ, VIO= 0 to VCCIO+ 0.2 V<br>~~Ge~~<br>~~ee~~|—<br>~~GG~~<br>~~ee~~|6<br>~~GG~~<br>~~ee~~|—<br>~~ee~~|pf<br>~~ee~~|
|C2<br>~~a~~|Global Input Buffer<br>Capacitance2<br>~~ee~~|VCCIO= 3.3 V, 2.5 V, 1.8 V<br>VCC= Typ, VIO= 0 to VCCIO+ 0.2 V<br>~~ee~~|—<br>~~ee~~|6<br>~~ee~~|—<br>~~ee~~|pf<br>~~ee~~|
|C3<br>~~a ~~|24 mA LED I/O Capacitance<br> ~~GG~~|VCC= Typ, VIO= 0 to 35 V<br>~~GG~~|—<br>~~GG~~|15<br>~~GG~~|—<br>~~GG~~|pf<br>~~GG~~|
|C4<br>~~GGG~~|400 mA LED I/O Capacitance<br>~~GGG~~|VCC= Typ, VIO= 0 to 35 V<br>~~GGG~~|—<br>~~GGG~~|53<br>~~GGG~~|—<br>~~GGG~~|pf<br>~~GGG~~|
|VHYST<br>~~GGG~~<br>~~a~~|Input Hysteresis<br>~~GGG~~<br>~~GGG~~|VCCIO= 1.8 V, 2.5 V, 3.3 V<br>~~GGG~~<br>~~GGG~~|—<br>~~GGG~~<br>~~GGG~~|200<br>~~GGG~~<br>~~GGG~~|—<br>~~GGG~~<br>~~GGG~~|mV<br>~~GGG~~<br>~~GGG~~|
|IPU<br>~~Pf~~|Internal PIO Pull-up Current<br>~~Pf~~|VCCIO= 1.8 V, 0 ≤ VIN≤ 0.65 VCCIO<br>~~**e**s~~|−3<br>~~s~~|—<br>~~s~~|−31<br>~~s~~|µA<br>~~s~~|
|||VCCIO= 2.5 V, 0 ≤ VIN≤ 0.65 VCCIO<br>~~**e**s~~|−8<br>~~s~~|—<br>~~s~~|−72<br>~~s~~|µA<br>~~s~~|
|||VCCIO= 3.3 V, 0 ≤ VIN≤ 0.65 VCCIO<br>~~**e**s~~<br>~~G~~|−11<br>~~s~~<br>~~G~~|—<br>~~s~~<br>~~G~~|−128<br>~~s~~<br>~~G~~|µA<br>~~s~~<br>~~G~~|
## **Notes:**
1. Input or I/O leakage current is measured with the pin configured as an input or as an I/O with the output driver tri-stated. It is not measured with the output driver active. Internal pull-up resistors are disabled.
2. TJ 25 °C, f = 1.0 MHz.
3. Refer to VIL and VIH in Table 4.11 on page 32.
4. Input pins are clamped to VCCIO and GND by a diode. When input is higher than VCCIO or lower than GND, the Input Leakage current will be higher than the IIL and IIH.
© 2018-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02028-2.4
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**iCE40 Ultra Family Data Sheet Data Sheet**
## **4.10.Supply Current**
**Table 4.6. Supply Current[1, 2, 3, 4, 5]**
|**Symbol**|**Parameter**|**Typ VCC =1.2 V4**|**Unit**|
|---|---|---|---|
|ICCSTDBY|Core Power SupplyStatic Current|71|µA|
|IPP2V5STDBY|VPP_2V5Power SupplyStatic Current|0.55|µA|
|ISPI_VCCIO1STDBY|SPI_VCCIO1Power SupplyStatic Current|0.5|µA|
|ICCIOSTDBY|VCCIOPower SupplyStatic Current|0.5|µA|
|ICCPEAK|Core Power SupplyStartupPeak Current|8.0|mA|
|IPP_2V5PEAK|VPP_2V5Power SupplyStartupPeak Current|7.0|mA|
|ISPI_VCCIO1PEAK|SPI_VCCIO1Power SupplyStartupPeak Current|9.0|mA|
|ICCIOPEAK|VCCIOPower SupplyStartupPeak Current|7.5|mA|
**Notes** :
1. Assumes blank pattern with the following characteristics: all outputs are tri-stated, all inputs are configured as LVCMOS and held at VCCIO or GND, on-chip PLL is off. For more detail with your specific design, use the Power Calculator tool. Power specified with master SPI configuration mode. Other modes may be up to 25% higher.
2. Frequency = 0 MHz.
3. TJ = 25°C, power supplies at nominal voltage.
4. Does not include pull-up.
5. Startup Peak Currents are measured with decoupling capacitance of 0.1 uF, 10 nF, and 1 nF to the power supply. Higher decoupling capacitance causes higher current.
## **4.11.User I[2] C Specifications**
**Table 4.7. User I[2] C Specifications**
|**Symbol**<br>~~ee~~|**Parameter**<br>~~ee~~|**STD Mode**<br>~~es~~<br>~~ee~~<br>~~ce ee eee~~|**STD Mode**<br>~~es~~<br>~~ee~~<br>~~ce ee eee~~|**STD Mode**<br>~~es~~<br>~~ee~~<br>~~ce ee eee~~|**FAST Mode**<br>~~es~~<br>~~ee~~<br>~~eee~~|**FAST Mode**<br>~~es~~<br>~~ee~~<br>~~eee~~|**FAST Mode**<br>~~es~~<br>~~ee~~<br>~~eee~~|**Unit**<br>~~ee~~<br>~~eee~~|
|---|---|---|---|---|---|---|---|---|
|||**Min**<br>~~es~~<br>~~ee~~<br>~~ce ee~~|**Typ**<br>~~es~~<br>~~ee~~<br>~~ee~~|**Max**<br>~~es~~<br>~~ee~~<br>~~ee eee~~|**Min**<br>~~es~~<br>~~ee~~<br>~~eee~~|**Typ**<br>~~es~~<br>~~ee~~<br>~~eee~~|**Max**<br>~~es~~<br>~~ee~~<br>~~eee~~||
|fSCL<br>~~OG~~<br>~~a~~|Maximum SCL clock frequency<br>~~OG~~<br>|—<br>~~ce ee~~<br>~~OG~~<br>|—<br>~~ee~~<br>~~OG~~<br>~~GG~~<br>|100<br>~~ee eee~~<br>~~OG~~<br>~~GG~~<br>|—<br>~~eee~~<br>~~OG~~<br>~~GG~~<br>|—<br>~~eee~~<br>~~OG~~<br>~~GG~~<br>|400<br>~~eee~~<br>~~OG~~<br>|kHz<br>~~eee~~<br>~~OG~~<br>|
|tHI<br>~~Ge~~<br>~~a~~|SCL clock HIGH Time<br>~~Ge~~<br>|4<br>~~Ge~~<br>|—<br>~~Ge~~<br>~~GG~~<br>|—<br>~~Ge~~<br>~~GG~~<br>|0.6<br>~~Ge~~<br>~~GG~~<br>|—<br>~~Ge~~<br>~~GG~~<br>|—<br>~~Ge~~<br>|µs<br>~~Ge~~<br>|
|tLO<br>~~Ge~~<br>~~a~~|SCL clock LOW Time<br>~~Ge~~<br>~~eG~~|4.7<br>~~Ge~~<br>~~eG~~|—<br>~~Ge~~<br>~~GG~~<br>~~eG~~|—<br>~~Ge~~<br>~~GG~~<br>~~eG~~|1.3<br>~~Ge~~<br>~~GG~~<br>~~eG~~|—<br>~~Ge~~<br>~~GG~~<br>~~eG~~|—<br>~~Ge~~<br>~~eG~~|µs<br>~~Ge~~<br>~~eG~~|
|tSU,DAT<br>~~a~~<br>~~a~~|Setuptime(DATA)<br>~~eG~~<br>|250<br>~~eG~~<br>|—<br>~~GG~~<br>~~eG~~<br>|—<br>~~GG~~<br>~~eG~~<br>|100<br>~~GG~~<br>~~eG~~<br>|—<br>~~GG~~<br>~~eG~~<br>|—<br>~~eG~~<br>|ns<br>~~eG~~<br>|
|tHD,DAT<br>~~aeG~~|Hold time(DATA)<br>~~eG~~|0<br>~~eG~~|—<br>~~eG~~|—<br>~~eG~~|0<br>~~eG~~|—<br>~~eG~~|—<br>~~eG~~|ns<br>~~eG~~|
|tSU,STA<br>~~a ~~<br>~~a~~|Setuptime(START condition)<br> ~~OG~~<br>|4.7<br>~~OG~~<br>|—<br>~~OG~~<br>~~Ge~~<br>|—<br>~~OG~~<br>~~Ge~~<br>|0.6<br>~~OG~~<br>|—<br>~~OG~~<br>|—<br>~~OG~~<br>|µs<br>~~OG~~<br>|
|tHD,STA<br>~~Ge~~<br>~~a~~|Hold time(START condition)<br>~~Ge~~<br>|4<br>~~Ge~~<br>|—<br>~~Ge~~<br>~~Ge~~<br>|—<br>~~Ge~~<br>~~Ge~~<br>|0.6<br>~~Ge~~<br>|—<br>~~Ge~~<br>|—<br>~~Ge~~<br>|µs<br>~~Ge~~<br>|
|tSU,STO<br>~~Ge~~<br>~~a~~|Setuptime(STOP condition)<br>~~Ge~~<br>~~eG~~|4<br>~~Ge~~<br>~~eG~~|—<br>~~Ge~~<br>~~Ge~~<br>~~eG~~|—<br>~~Ge~~<br>~~Ge~~<br>~~eG~~|0.6<br>~~Ge~~<br>~~eG~~|—<br>~~Ge~~<br>~~eG~~|—<br>~~Ge~~<br>~~eG~~|µs<br>~~Ge~~<br>~~eG~~|
|tBUF<br>~~a~~<br>~~OG~~|Bus free time between STOP and START<br>~~eG~~<br>~~OG~~|4.7<br>~~eG~~<br>~~OG~~|—<br>~~Ge~~<br>~~eG~~<br>~~OG~~|—<br>~~Ge~~<br>~~eG~~<br>~~OG~~|1.3<br>~~eG~~<br>~~OG~~|—<br>~~eG~~<br>~~OG~~|—<br>~~eG~~<br>~~OG~~|µs<br>~~eG~~<br>~~OG~~|
|tCO,DAT<br>~~OG~~<br>~~eo~~|SCL LOW to DATAOUT valid<br>~~OG~~<br>~~eo~~|—<br>~~OG~~<br>~~eo~~|—<br>~~OG~~<br>~~eo~~|3.4<br>~~OG~~<br>~~eo~~|—<br>~~OG~~<br>~~eo~~|—<br>~~OG~~<br>~~eo~~|0.9<br>~~OG~~<br>~~eo~~|µs<br>~~OG~~<br>~~eo~~|
© 2018-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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## **4.12.User SPI Specifications**
**Table 4.8. User SPI Specifications[ 1, 2]**
|**Symbol**|**Parameter**|**STD Mode**|**STD Mode**|**STD Mode**|**Unit**|
|---|---|---|---|---|---|
|||**Min**|**Typ**|**Max**||
|fMAX|Maximum SCK clock frequency|—|—|45|MHz|
## **Notes:**
1. All setup and hold time parameters on external SPI interface are design-specific and, therefore, generated by the Lattice Design Software tools. These parameters include the following:
- tSUmaster master Setup time (master mode)
- tHOLDmaster master Hold time (master mode)
- tSUslave slave Setup time (slave mode)
- tHOLDslave slave Hold time (slave mode) tSCK2OUT SCK to out (slave mode)
2. The SCLK duty cycle needs to be specified in the Lattice Design Software as a timing constraint in order to ensure proper timing check on SCLK HIGH and LOW (tHI, tLO) time.
## **4.13.Internal Oscillators (HFOSC, LFOSC)**
## **Table 4.9. Internal Oscillators (HFOSC, LFOSC)***
|**Parameter**<br>~~ee~~<br>~~es~~<br>~~eeeee~~|**Parameter**<br>~~ee~~<br>~~es~~<br>~~eeeee~~|**Parameter Description**<br>~~A~~<br>~~eee~~|**Spec/Recommended**<br>~~eeee~~<br>~~ee~~|**Spec/Recommended**<br>~~eeee~~<br>~~ee~~|**Spec/Recommended**<br>~~eeee~~<br>~~ee~~|**Unit**<br>~~ee~~|
|---|---|---|---|---|---|---|
|**Symbol**<br>~~ee~~<br>~~ee~~<br>~~2~~|**Conditions**<br>~~es~~<br>~~eee~~<br>~~Se~~||**Min**<br>~~ee~~<br>~~ee~~<br>~~ee~~|**Typ**<br>~~ee~~<br>~~ee~~<br>~~ee~~|**Max**<br>~~ee~~||
|fCLKHF<br>~~ee~~<br>~~ee ~~<br>~~2~~<br>~~re~~|Commercial Temp<br>~~es~~<br> ~~eee~~<br>~~Se~~|HFOSC clock frequency (tJ= 0°C–85°C)<br>~~A~~<br>~~eee~~|–10%<br>~~ee ~~<br>~~ee~~<br>~~ee~~|48<br> ~~ee~~<br>~~ee~~<br>~~ee~~|10%<br>~~ee~~|MHz<br>~~ee~~|
||Industrial Temp<br>~~Se~~<br>~~a~~<br>|HFOSC clock frequency (tJ= –40°C–100°C)<br>~~eee~~<br>|–20%<br>~~ee~~<br>|48<br>~~ee~~<br>|20%<br>~~ee~~<br>|MHz<br>~~ee~~<br>|
|fCLKLF<br>~~2 ~~<br>~~re~~<br>~~ee~~|—<br> ~~Se ~~<br>~~a~~<br>~~eG~~<br>~~ee ee~~|LFOSC CLKK clock frequency<br> ~~eee ~~<br>~~eG~~<br>~~ee~~|–10%<br> ~~ee~~<br>~~eG~~<br>~~ee~~|10<br>~~ee~~<br>~~eG~~<br>~~ee~~|10%<br>~~ee~~<br>~~eG~~|kHz<br>~~ee~~<br>~~eG~~|
|DCHCLKHF<br>~~re~~<br>~~ee~~|Commercial Temp<br>~~a~~<br><br>~~ee ee~~|HFOSC Duty Cycle (tJ= 0°C–85°C)<br><br>~~ee~~|45<br><br>~~ee~~|50<br><br>~~ee~~|55<br>|%<br>|
||Industrial Temp<br>~~ee ee~~<br>~~a~~|HFOSC Duty Cycle (tJ= –40°C–100°C)<br>~~ee~~|40<br>~~ee~~|50<br>~~ee~~|60|%|
|DCHCLKLF<br>~~ee~~<br>~~se~~<br>~~re~~|—<br>~~ee ee~~<br>~~se~~<br>~~eG~~|LFOSC DutyCycle(Clock High Period)<br>~~ee ~~<br>~~Ge~~<br>~~eG~~|45<br> ~~ee~~<br>~~Ge~~<br>~~eG~~|50<br>~~ee~~<br>~~Ge~~<br>~~eG~~|55<br>~~Ge~~<br>~~eG~~|%<br>~~Ge~~<br>~~eG~~|
|Tsync_on<br>~~se~~<br>~~re~~<br>~~ee~~|—<br>~~se ~~<br>~~eG~~<br>~~eG~~|Oscillator output synchronizer delay<br> ~~Ge~~<br>~~eG~~<br>~~eG~~|—<br>~~Ge~~<br>~~eG~~<br>~~eG~~|—<br>~~Ge~~<br>~~eG~~<br>~~eG~~|5<br>~~Ge~~<br>~~eG~~<br>~~eG~~|Cycles<br>~~Ge~~<br>~~eG~~<br>~~eG~~|
|Tsync_off<br>~~re~~<br>~~ee~~|—<br>~~eG~~<br>~~eG~~|Oscillator output disable delay<br>~~eG~~<br>~~eG~~|—<br>~~eG~~<br>~~eG~~|—<br>~~eG~~<br>~~eG~~|5<br>~~eG~~<br>~~eG~~|Cycles<br>~~eG~~<br>~~eG~~|
***Note:** Glitchless enabling and disabling OSC clock outputs.
## **4.14. sysI/O Recommended Operating Conditions**
**Table 4.10. sysI/O Recommended Operating Conditions**
|**Standard**|**VCCIO (V)**|**VCCIO (V)**|**VCCIO (V)**|
|---|---|---|---|
||**Min**|**Typ**|**Max**|
|LVCMOS 3.3|3.14|3.3|3.46|
|LVCMOS 2.5|2.37|2.5|2.62|
|LVCMOS 1.8|1.71|1.8|1.89|
© 2018-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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## **4.15.sysI/O Single-Ended DC Electrical Characteristics**
**Table 4.11. sysI/O Single-Ended DC Electrical Characteristics**
|**Input/Output**<br>**Standard**<br>~~ee~~<br>~~persed~~|**VIL**<br>~~ee~~<br>~~persed~~|**VIL**<br>~~ee~~<br>~~persed~~|**VIH**<br>~~ee~~<br>~~persed~~|**VIH**<br>~~ee~~<br>~~persed~~|**VOL Max**<br>**(V)**<br>~~persed~~|**VOH Min**<br>**(V)**<br>~~persed~~|**IOL**<br>**(mA)**<br>~~persed~~|**IOH Max**<br>**(mA)**<br>~~persed~~|
|---|---|---|---|---|---|---|---|---|
||**Min(V)**<br>~~persed~~|**Max(V)**<br>~~persed~~|**Min(V)**<br>~~persed~~|**Max(V)**<br>~~persed~~|||||
|LVCMOS 3.3<br>~~persed~~<br>~~ep~~|–0.3<br>~~persed~~<br>~~ep~~|0.8<br>~~persed~~<br>~~ep~~|2.0<br>~~persed~~<br>~~ep~~|VCCIO + 0.2 V<br>~~persed~~<br>~~ep~~|0.4<br>~~persed~~<br>~~ep~~|VCCIO− 0.4<br>~~persed~~<br>~~ep~~|8<br>~~persed~~<br>~~ep~~|–8<br>~~persed~~<br>~~ep~~|
||||||0.2<br>~~ep~~|VCCIO− 0.2<br>~~ep~~|0.1<br>~~ep~~<br>~~eee~~|–0.1<br>~~ep~~<br>~~eee~~|
|LVCMOS 2.5<br>~~a~~|–0.3<br>a~~ee~~|0.7<br>~~ee~~|1.7<br>~~ee~~|VCCIO + 0.2 V<br>~~ee~~|0.4<br>~~ee~~|VCCIO− 0.4<br>~~ee~~|6<br>~~ee~~<br>~~eee~~|–6<br>~~ee~~<br>~~eee~~|
||||||0.2<br>~~ee~~|VCCIO− 0.2<br>~~ee~~|0.1<br>~~ee~~<br>~~eee~~|–0.1<br>~~ee~~<br>~~eee~~|
|LVCMOS 1.8<br>~~pry~~|–0.3<br>~~pry~~|0.35 VCCIO<br>~~pry~~|0.65 VCCIO<br>~~pry~~|VCCIO + 0.2 V<br>~~pry~~|0.4<br>~~pry~~|VCCIO− 0.4<br>~~pry~~|4<br>~~eee~~<br>~~pry~~|–4<br>~~eee~~<br>~~pry~~|
||||||0.2<br>~~pry~~|VCCIO− 0.2<br>~~pry~~|0.1<br>~~pry~~|–0.1<br>~~pry~~|
## **4.16.Differential Comparator Electrical Characteristics**
**Table 4.12. Differential Comparator Electrical Characteristics**
|**Parameter**<br>**Symbol**|**Parameter Description**|**Test Conditions**|**Min**|**Max**|**Unit**|
|---|---|---|---|---|---|
|VREF|Reference Voltage to compare, on VINM|VCCIO= 2.5 V|0.25|VCCIO- 0.25 V|V|
|VDIFFIN_H|Differential input HIGH(VINP- VINM)|VCCIO= 2.5 V|250|—|mV|
|VDIFFIN_L|Differential input LOW(VINP- VINM)|VCCIO= 2.5 V|—|–250|mV|
|IIN|Input Current, VINPand VINM|VCCIO= 2.5 V|–10|10|µA|
## **4.17.Typical Building Block Function Performance**
## **4.17.1. Pin-to-Pin Performance (LVCMOS25)**
**Table 4.13. Pin-to-Pin Performance (LVCMOS25)[ 1, 2]**
|**Function**|**Timing**|**Unit**|
|---|---|---|
|16-bit decoder|16.5|ns|
|4:1 MUX|18.0|ns|
|16:1 MUX|19.5|ns|
## **Notes:**
1. The above timing numbers are generated using the Lattice Design Software tool. Exact performance may vary with device and tool version. The tool uses internal parameters that have been characterized but are not tested on every device.
2. Under worst case operating conditions.
© 2018-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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## **4.17.2. Register-to-Register Performance**
**Table 4.14. Register-to-Register Performance[ 1, 2]**
|**Function**|**Timing**|**Unit**|
|---|---|---|
|**Basic Function**|||
|16:1 MUX|110|MHz|
|16-bit adder|100|MHz|
|16-bit counter|100|MHz|
|64-bit counter|40|MHz|
|**Embedded Memory Function**|||
|256x16 Pseudo-Dual Port RAM|150|MHz|
## **Notes:**
1. The above timing numbers are generated using the Lattice Design Software tool. Exact performance may vary with device and tool version. The tool uses internal parameters that have been characterized but are not tested on every device.
2. Under worst case operating conditions.
## **4.18.Derating Logic Timing**
Logic timing provided in the following sections of the data sheet and the Lattice design tools are worst case numbers in the operating range. Actual delays may be much faster. Lattice design tools can provide logic timing numbers at a particular temperature and voltage.
## **4.19.Maximum sysIO Buffer Performance**
**Table 4.15. Maximum sysIO Buffer Performance***
|**I/O Standard**|**Max Speed**|**Unit**|
|---|---|---|
|**Inputs**|||
|LVCMOS33|250|MHz|
|LVCMOS25|250|MHz|
|LVCMOS18|250|MHz|
|**Outputs**|||
|LVCMOS33|250|MHz|
|LVCMOS25|250|MHz|
|LVCMOS18|155|MHz|
***Note** : Measured with a toggling pattern.
© 2018-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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## **4.20.iCE40 Ultra Family Timing Adders**
Over recommended operating conditions.
**Table 4.16. iCE40 Ultra Family Timing Adders[ 1, 2, 3]**
|**Buffer Type **|**Description**|**Timing (Typ)**|**Unit**|
|---|---|---|---|
|**Global Clock**||||
|LVCMOS33|LVCMOS, VCCIO= 3.3 V|0.18|ns|
|LVCMOS25|LVCMOS, VCCIO= 2.5 V|0|ns|
|LVCMOS18|LVCMOS, VCCIO= 1.8 V|0.19|ns|
|**Pin-LUT-Pin Propagation Delay**||||
|LVCMOS33|LVCMOS, VCCIO= 3.3 V|–0.12|ns|
|LVCMOS25|LVCMOS, VCCIO= 2.5 V|0|ns|
|LVCMOS18|LVCMOS, VCCIO= 1.8 V|1.32|ns|
## **Notes:**
1. Timing adders are relative to LVCMOS25 and characterized but not tested on every device.
2. LVCMOS timing measured with the load specified in Switching Test Condition table.
3. Commercial timing numbers are shown.
## **4.21.iCE40 Ultra External Switching Characteristics**
Over recommended commercial operating conditions.
**Table 4.17. iCE40 Ultra External Switching Characteristics**
|**Parameter**<br>~~es~~|**Description**<br>~~GG~~|**Device**<br>~~GG~~|**Min**<br>~~GG~~|**Max**<br>~~GG~~|**Unit**<br>~~GG~~|
|---|---|---|---|---|---|
|**Global Clock**<br>~~esGG~~<br>~~pT~~||||||
|fMAX_GBUF<br>~~GO~~|Frequencyfor Global Buffer Clock network<br>~~GO~~|All Devices<br>~~GO~~|—<br>~~GO~~|185<br>~~GO~~|MHz<br>~~GO~~|
|tW_GBUF<br>~~a~~<br>~~es~~|Clock Pulse Width for Global Buffer<br>~~GC~~<br>~~eG~~|All Devices<br>~~GC~~<br>~~eG~~|2<br>~~GC~~<br>~~eG~~|—<br>~~GC~~<br>~~eG~~|ns<br>~~GC~~<br>~~eG~~|
|tISKEW_GBUF<br>~~a ~~<br>~~es~~|Global Buffer Clock Skew Within a Device<br> ~~GC~~<br>~~eG~~|All Devices<br>~~GC~~<br>~~eG~~|—<br>~~GC~~<br>~~eG~~|500<br>~~GC~~<br>~~eG~~|ps<br>~~GC~~<br>~~eG~~|
|**Pin-LUT-Pin Propagation Delay**<br>~~eseG~~<br>~~pT~~||||||
|tPD|Best case propagation delay through one<br>LUT logic|All Devices|—|9.0|ns|
|**General I/O Pin Parameters(Using Global Buffer Clock without PLL)* **<br>~~ee~~||||||
|tSKEW_IO<br>~~ee~~|Data bus skew across a bank of IOs|All Devices|—|410|ps|
|tCO<br>~~ee~~<br>~~a~~<br>~~es~~|Clock to Output – PIO Output Register<br>~~GO~~|All Devices<br>~~GO~~|—<br>~~GO~~|9.0<br>~~GO~~|ns<br>~~GO~~|
|tSU<br>~~a ~~<br>~~es~~<br>~~es~~|Clock to Data Setup– PIO Input Register<br> ~~GO~~<br>~~GG~~|All Devices<br>~~GO~~<br>~~GG~~|−0.5<br>~~GO~~<br>~~GG~~|—<br>~~GO~~<br>~~GG~~|ns<br>~~GO~~<br>~~GG~~|
|tH<br>~~es~~<br>~~es~~|Clock to Data Hold – PIO Input Register<br>~~GG~~|All Devices<br>~~GG~~|5.55<br>~~GG~~|—<br>~~GG~~|ns<br>~~GG~~|
|**General I/O Pin Parameters(Using Global Buffer Clock with PLL)**<br>~~esGG~~<br>~~es~~||||||
|tCOPLL<br>~~es~~|Clock to Output – PIO Output Register|All Devices|—|2.9|ns|
|tSUPLL<br>~~es~~<br>~~a~~<br>~~es~~|Clock to Data Setup– PIO Input Register<br>~~GC~~|All Devices<br>~~GC~~|7.9<br>~~GC~~|—<br>~~GC~~|ns<br>~~GC~~|
|tHPLL<br>~~a ~~<br>~~es~~|Clock to Data Hold – PIO Input Register<br> ~~GC~~|All Devices<br>~~GC~~|−0.6<br>~~GC~~|—<br>~~GC~~|ns<br>~~GC~~|
***Note:** All the data is from the worst case.
© 2018-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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## **4.22.sysCLOCK PLL Timing**
Over recommended operating conditions.
**Table 4.18. sysCLOCK PLL Timing**
|**Parameter**|**Descriptions**|**Conditions**|**Min**|**Max**|**Unit**|
|---|---|---|---|---|---|
|fIN<br>~~a~~|Input Clock Frequency (REFERENCECLK,<br>EXTFEEDBACK)<br>~~ee~~|—<br>~~ee~~|10<br>~~ee~~|133<br>~~ee~~|MHz<br>~~ee~~|
|fOUT<br>~~GO~~|Output Clock Frequency (PLLOUT)<br>~~GO~~|—<br>~~GO~~|16<br>~~GO~~|275<br>~~GO~~|MHz<br>~~GO~~|
|fVCO<br>~~OO~~<br>~~es~~|PLL VCO Frequency<br>~~OO~~<br>|—<br>~~OO~~<br>|533<br>~~OO~~<br>|1066<br>~~OO~~<br>|MHz<br>~~OO~~<br>|
|fPFD3<br>~~OO~~<br>~~es~~|Phase Detector Input Frequency<br>~~OO~~<br>|—<br>~~OO~~<br>|10<br>~~OO~~<br>|133<br>~~OO~~<br>|MHz<br>~~OO~~<br>|
|**AC Characteristics**<br>~~espn~~<br>~~DO~~||||||
|tDT<br>~~i~~|Output Clock DutyCycle<br>~~i~~|—<br>~~i~~<br>~~DO~~|40<br>~~i~~<br>~~DO~~|60<br>~~i~~|%<br>~~i~~|
|tPH<br>~~GO~~|Output Phase Accuracy<br>~~GO~~<br>~~ee~~|—<br>~~DO~~<br>~~GO~~<br>~~es~~|—<br>~~DO~~<br>~~GO~~<br>~~es~~|±12<br>~~GO~~<br>~~es~~|deg<br>~~GO~~<br>~~es~~|
|tOPJIT1, 5, 6|Output Clock Period Jitter<br>~~ee~~|fOUT>= 100 MHz<br>~~es~~|—<br>~~es~~<br>~~ee~~|450<br>~~es~~|psp-p<br>~~es~~|
|||fOUT< 100 MHz<br>~~es~~|—<br>~~es~~<br>~~ee~~|0.05<br>~~es~~|UIPP<br>~~es~~|
||Output Clock Cycle-to-Cycle Jitter<br>~~ee~~<br>~~ye~~|fOUT>= 100 MHz<br>~~es~~<br>~~ye~~|—<br>~~es~~<br>~~ee~~<br>~~ye~~|750<br>~~es~~<br>~~ye~~|psp-p<br>~~es~~<br>~~ye~~|
|||fOUT< 100 MHz<br>~~ye~~<br>~~po~~<br>~~ee~~|—<br>~~ye~~<br>~~po~~<br>~~ee~~|0.10<br>~~ye~~<br>~~po~~<br>~~eee~~|UIPP<br>~~ye~~<br>~~po~~<br>~~eee~~|
||Output Clock Phase Jitter<br>~~a~~|fPFD>= 25 MHz<br>~~a~~<br>~~ee~~|—<br>~~a~~<br>~~ee~~|275<br>~~a~~<br>~~eee~~|psp-p<br>~~a~~<br>~~eee~~|
|||fPFD< 25 MHz<br>~~a~~<br>~~ee~~<br>~~ee~~|—<br>~~a~~<br>~~ee~~<br>~~ee~~|0.05<br>~~a~~<br>~~eee~~<br>~~ee~~|UIPP<br>~~a~~<br>~~eee~~<br>~~ee~~|
|tW<br>~~OO~~|Output Clock Pulse Width<br>~~OO~~|At 90% or 10%<br>~~ee ~~<br>~~OO~~|1.33<br> ~~ee ~~<br>~~OO~~|—<br> ~~eee~~<br>~~OO~~|ns<br>~~eee~~<br>~~OO~~|
|tLOCK 2, 3<br>~~OO~~<br>~~GO~~<br>~~a~~|PLL Lock-in Time<br>~~OO~~<br>~~GO~~|—<br>~~OO~~<br>~~GO~~|—<br>~~OO~~<br>~~GO~~<br>~~D~~|50<br>~~OO~~<br>~~GO~~|µs<br>~~OO~~<br>~~GO~~|
|tUNLOCK<br>~~a~~|PLL Unlock Time|—|—<br>~~D~~|50|ns|
|tIPJIT 4<br>~~a~~<br>~~SS~~|Input Clock Period Jitter<br>~~SS~~|fPFD≥ 20 MHz<br>~~SS~~|—<br>~~D~~<br>~~SS~~|1000<br>~~SS~~|ps p-p<br>~~SS~~|
|||fPFD< 20 MHz<br>~~SS~~<br>~~ee~~|—<br>~~SS~~<br>~~ee~~|0.02<br>~~SS~~<br>~~ee~~|UIPP<br>~~SS~~<br>~~ee~~|
|tSTABLE 3<br>~~DO~~|LATCHINPUTVALUE LOW to PLL Stable<br>~~DO~~|—<br>~~DO~~|—<br>~~DO~~|500<br>~~DO~~|ns<br>~~DO~~|
|tSTABLE_PW 3<br>~~DO~~|LATCHINPUTVALUE Pulse Width<br>~~DO~~|—<br>~~DO~~|100<br>~~DO~~|—<br>~~DO~~|ns<br>~~DO~~|
|tRST<br>~~a~~<br>~~es~~|RESET Pulse Width<br>~~a~~<br>~~CO~~|—<br>~~a~~<br>~~CO~~|10<br>~~a~~<br>~~CO~~|—<br>~~a~~<br>~~CO~~|ns<br>~~a~~<br>~~CO~~|
|tRSTREC<br>~~a~~<br>~~es~~|RESET RecoveryTime<br>~~a~~<br>~~CO~~|—<br>~~a~~<br>~~CO~~|10<br>~~a~~<br>~~CO~~|—<br>~~a~~<br>~~CO~~|µs<br>~~a~~<br>~~CO~~|
|tDYNAMIC_WD<br>~~es~~<br>~~OO~~|DYNAMICDELAY Pulse Width<br>~~CO~~<br>~~OO~~|—<br>~~CO~~<br>~~OO~~|100<br>~~CO~~<br>~~OO~~|—<br>~~CO~~<br>~~OO~~|VCO Cycles<br>~~CO~~<br>~~OO~~|
**Notes:**
1. Period jitter sample is taken over 10,000 samples of the primary PLL output with a clean reference clock. Cycle-to-cycle jitter is taken over 1000 cycles. Phase jitter is taken over 2000 cycles. All values per JESD65B.
2. Output clock is valid after tLOCK for PLL reset and dynamic delay adjustment.
3. At minimum fPFD. As the fPFD increases the time will decrease to approximately 60% the value listed.
4. Maximum limit to prevent PLL unlock from occurring. Does not imply the PLL will operate within the output specifications listed in this table.
5. The jitter values will increase with loading of the PLD fabric and in the presence of SSO noise.
© 2018-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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## **4.23.sysDSP Timing**
Over recommended operating conditions.
**Table 4.19. sysDSP Timing**
|**Parameter**|**Description**|**Min**|**Max**|**Unit**|
|---|---|---|---|---|
|fMAX8x8SMULT|Max frequency signed MULT8x8 bypassing<br>pipeline register|50|—|MHz|
|fMAX16x16SMULT|Max frequency signed MULT16x16 bypassing<br>pipeline register|50|—|MHz|
## **4.24.SPI Master or NVCM Configuration Time**
**Table 4.20. SPI Master or NVCM Configuration Time[ 1, 2]**
|**Symbol**|**Parameter**|**Conditions**|**Max**|**Unit**|
|---|---|---|---|---|
|tCONFIG|POR/CRESET_B to Device I/O Active|All devices – Low Frequency (Default)|95|ms|
|||All devices – Medium frequency|35|ms|
|||All devices – High frequency|18|ms|
**Notes** :
1. Assumes sysMEM Block is initialized to an all zero pattern if they are used.
2. The NVCM download time is measured with a fast ramp rate starting from the maximum voltage of POR trip point.
© 2018-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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## **4.25.sysCONFIG Port Timing Specifications**
Over recommended operating conditions.
**Table 4.21. sysCONFIG Port Timing Specifications**
|**Symbol**<br>~~DO~~|**Parameter**<br>~~DO~~|**Conditions**<br>~~DO~~|**Min**<br>~~DO~~|**Typ**<br>~~DO~~<br>~~OO~~|**Max**<br>~~DO~~|**Unit**<br>~~DO~~|
|---|---|---|---|---|---|---|
|**All Configuration Mode**<br>~~DO~~<br>~~OO~~|||||||
|tCRESET_B<br>~~a~~|Minimum CRESET_B LOW pulse width required to<br>restart configuration, from fallingedge to risingedge|—|200|—|—|ns|
|tDONE_IO<br>~~a~~|Number of configuration clock cycles after CDONE<br>goes HIGH before the PIOpins are activated|—|49|—|—|Clock<br>Cycles|
|**Slave SPI**|||||||
|tCR_SCK|Minimum time from a rising edge on CRESET_B until<br>the first SPI WRITE operation, first SPI_SCK clock.<br>During this time, the iCE40 Ultra device is clearing its<br>internal configuration memory|—|1200|—|—|µs|
|fMAX<br>~~rrr~~|CCLK clock frequency<br>~~rrr~~|Write<br>~~rrr~~|1<br>~~rrr~~<br>~~ee~~|—<br>~~rrr~~<br>~~ee~~|25<br>~~rrr~~<br>~~ee~~|MHz<br>~~rrr~~<br>~~ee~~|
|||Read1<br>~~rrr~~<br>~~ee~~|—<br>~~rrr~~<br>~~ee~~<br>~~ee~~|15<br>~~rrr~~<br>~~ee~~<br>~~ee~~|—<br>~~rrr~~<br>~~ee~~<br>~~ee~~|MHz<br>~~rrr~~<br>~~ee~~<br>~~ee~~|
|tCCLKH<br>~~eG~~|CCLK clockpulsewidth HIGH<br>~~eG~~|—<br>~~eG~~|20<br>~~ee ~~<br>~~eG~~|—<br> ~~ee ~~<br>~~eG~~|—<br> ~~ee ~~<br>~~eG~~|ns<br> ~~ee~~<br>~~eG~~|
|tCCLKL<br>~~eG~~|CCLK clockpulsewidth LOW<br>~~eG~~|—<br>~~eG~~<br>~~GO~~|20<br>~~eG~~<br>~~GO~~|—<br>~~eG~~|—<br>~~eG~~|ns<br>~~eG~~|
|tSTSU<br>~~Ge~~<br>~~es~~|CCLK setuptime<br>~~Ge~~|—<br>~~Ge~~<br>~~GO~~<br>~~OO~~|12<br>~~Ge~~<br>~~GO~~<br>~~OO~~|—<br>~~Ge~~|—<br>~~Ge~~|ns<br>~~Ge~~|
|tSTH<br>~~Ge~~<br>~~es~~|CCLK hold time<br>~~Ge~~|—<br>~~GO~~<br>~~Ge~~<br>~~OO~~|12<br>~~GO~~<br>~~Ge~~<br>~~OO~~|—<br>~~Ge~~|—<br>~~Ge~~|ns<br>~~Ge~~|
|tSTCO<br>~~Ge~~<br>~~es~~|CCLK fallingedge to valid output<br>~~Ge~~|—<br>~~Ge~~<br>~~OO~~|13<br>~~Ge~~<br>~~OO~~|—<br>~~Ge~~|—<br>~~Ge~~|ns<br>~~Ge~~|
|**Master SPI3 **<br>~~OO~~<br>~~es~~<br>~~pn~~|||||||
|fMCLK|MCLK clock frequency<br>~~—~~|Low<br>Frequency<br>(Default)|7.0|12.0|17.0|MHz|
|||Medium<br>Frequency2<br>~~—~~<br>~~|~~|21.0<br>~~|~~|33.0<br>~~|}~~|45.0<br>~~|}~~|MHz<br>~~|}~~|
|||High<br>Frequency2<br>~~—~~<br>~~|~~|33.0<br>~~|~~|53.0<br>~~|}~~|71.0<br>~~|}~~|MHz<br>~~|}~~|
|tMCLK<br>~~eG~~<br>~~ee~~|CRESET_B HIGH to first MCLK edge<br>~~—~~<br>~~eG~~|—<br>~~—~~<br>~~|~~<br>~~eG~~|1200<br>~~|~~<br>~~eG~~|—<br>~~|}~~<br>~~eG~~|—<br>~~|}~~<br>~~eG~~|µs<br>~~|}~~<br>~~eG~~|
|tSU<br>~~ee~~|CCLK setuptime4|—|9.9|—|—|ns|
|THD<br>~~ee~~<br>~~a~~|CCLK hold time|—|1|—|—|ns|
**Notes** :
1. Supported with 1.2 V VCC and at 25 ° C.
2. Extended range fMAX Write operations support up to 53 MHz with 1.2 V VCC and at 25 ° C.
3. tSU and tHD timing must be met for all MCLK frequency choices.
4. For considerations of SPI Master Configuration Mode, please refer to iCE40 Programming and Configuration (FPGA-TN-02001).
© 2018-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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**iCE40 Ultra Family Data Sheet Data Sheet**
**4.26.RGB LED and IR LED Drive Table 4.22. RGB LED and IR LED Drive Symbol Parameter Min Max Unit** RGB0, RGB1, RGB2 Sink Current Accuracy to ILED_ACCURACY selected current @ VLEDOUT >= 0.5 V –12 +12 % RGB0, RGB1, RGB2 Sink Current Matching ILED_MATCH –5 +5 % among the 3 outputs @ VLEDOUT >= 0.5 V IR LED Sink Current Accuracy to selected IIR_ACCURACY current @ VIROUT >= 0.8 V –14 +14 % ~~=~~ **4.27.Switching Test Conditions** Figure 4.3 shows the output test load that is used for AC testing. The specific values for resistance, capacitance, voltage, and other test conditions are listed in Table 4.23. V T R1 DUT Test Point CL ~~ay~~ **Figure 4.3. Output Test Load, LVCMOS Standards Table 4.23. Test Fixture Required Components, Non-Terminated Interfaces Test Condition R1 CL Timing Reference VT** LVCMOS 3.3 = 1.5 V — LVCMOS settings (L ≥ H, H ≥ L) ∞ 0 pF LVCMOS 2.5 = VCCIO/2 — LVCMOS 1.8 = VCCIO/2 — LVCMOS 3.3 (Z ≥ H) 1.5 V VOL LVCMOS 3.3 (Z ≥ L) 1.5 V VOH Other LVCMOS (Z ≥ H) VCCIO/2 VOL 188 0 pF Other LVCMOS (Z ≥ L) VCCIO/2 VOH LVCMOS (H ≥ Z) VOH – 0.15 V VOL ~~=~~ LVCMOS (L ≥ Z) VOL – 0.15 V VOH **Note** : Output test conditions for all other interfaces are determined by the respective standards. © 2018-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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## **5. Pinout Information**
## **5.1. Signal Descriptions**
## **5.1.1. Power Supply Pins**
|**Signal Name**|**Function**|**I/O**|**Description**|
|---|---|---|---|
|VCC|Power|—|Core Power Supply|
|VCCIO_0, SPI_VCCIO1, VCCIO_2|Power|—|Power for I/Os in Bank 0, 1, and 2.|
|VPP_2V5|Power|—|Power for NVCMprogrammingand operations.|
|VCCPLL|Power|—|Power for PLL.|
|GND|GROUND|—|Ground|
|GND_LED|GROUND|—|Ground for LED drivers. Should connect to GND on board.|
## **5.1.2. Configuration Pins**
|**Signal Name**|**Function**|**I/O**|**Description**|
|---|---|---|---|
|CRESETB|Configuration|I|Configuration Reset, active LOW. No internal pull-up resistor.<br>Either actively driven externally or connect a 10 kΩ pull-up to<br>VCCIO_1.|
|CDONE|Configuration|I/O|Configuration Done. Includes a weak pull-up resistor to<br>SPI_VCCIO1.|
||General I/O|I/O|In user mode, after configuration, this pin can be programmed as<br>general I/O in user function.|
© 2018-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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## **5.1.3. Configuration SPI Pins**
|**Signal Name**|**Signal Name**|**Function**|**I/O**|**Description**|
|---|---|---|---|---|
|**Primary**|**Secondary**||||
|CRESETB<br>~~a~~<br>~~Cf)~~|—<br>~~Cf)~~|Configuration<br>|I<br>|Configuration Reset, active LOW. No internal pull-up resistor.<br>Either actively driven externally or connect a 10 kΩ pull-up to<br>SPI_VCCIO1.<br>|
|PIOB_xx<br>~~Cf)~~|CDONE<br>~~Cf)ee~~|Configuration<br>~~ee~~|I<br>~~ee~~|Configuration Done. Includes a weak pull-up resistor to<br>SPI_VCCIO1.<br>~~ee~~|
|||General I/O<br>~~ee~~|I/O<br>~~ee~~|In user mode, after configuration, this pin can be programmed as<br>general I/O in user function.<br>~~ee~~|
|PIOB_34a<br>~~Cf)~~<br>~~{ep~~<br>~~ef~~|SPI_SCK<br>~~Cf)~~<br>~~{ep~~<br>~~ef~~|Configuration<br><br>~~{ep~~|I/O<br><br>~~{ep~~|This pin is shared with device configuration. During<br>configuration:<br>In Master SPI mode, this pin outputs the clock to external SPI<br>memory.<br>In Slave SPI mode, this pin inputs the clock from external<br>processor.<br>|
|||General I/O<br>~~{ep~~<br>~~epp~~|I/O<br>~~{ep~~<br>~~epp~~|In user mode, after configuration, this pin can be programmed as<br>general I/O in user function.<br>~~epp~~|
|PIOB_32a<br>~~ef~~|SPI_SO<br>~~ef~~|Configuration<br>~~epp~~|Output<br>~~epp~~|This pin is shared with device configuration. During<br>configuration:<br>In Master SPI mode, this pin outputs the command data to<br>external SPI memory.<br>In Slave SPI mode, this pin connects to the MISO pin of the<br>externalprocessor.<br>~~epp~~|
|||General I/O<br>~~epp~~|I/O<br>~~epp~~|In user mode, after configuration, this pin can be programmed as<br>general I/O in user function.<br>~~epp~~|
|PIOB_33b<br>~~ef~~<br>{<br>~~)|~~|SPI_SI<br>~~ef ~~<br>{~~ep~~<br>~~)|~~|Configuration<br> ~~epp~~<br>~~ep~~|Input<br>~~epp~~<br>~~ep~~|This pin is shared with device configuration. During<br>configuration:<br>In Master SPI mode, this pin receives data from external SPI<br>memory.<br>In Slave SPI mode, this pin connects to the MOSI pin of the<br>externalprocessor.<br>~~epp~~|
|||General I/O<br>~~ep~~<br>~~Ey}~~|I/O<br>~~ep~~<br>~~Ey}~~|In user mode, after configuration, this pin can be programmed as<br>general I/O in user function.|
|PIOB_35b<br>~~)|~~|SPI_SS<br>~~)|~~|Configuration<br>~~Ey}~~|I/O<br>~~Ey}~~|This pin is shared with device configuration. During<br>configuration:<br>In Master SPI mode, this pin outputs to the external SPI memory.<br>In Slave SPI mode, this pin inputs CSN from the external<br>processor.|
|||General I/O<br>~~Ey}~~|I/O<br>~~Ey}~~|In user mode, after configuration, this pin can be programmed as<br>general I/O in user function.|
© 2018-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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## **5.1.4. Global Pins**
**Signal Name Function I/O Description Primary Secondary** ~~es~~ PIOT_46b G0 ~~es A~~ General I/O I/O In user mode, after configuration, this pin can be programmed as general I/O in user function. Global Input Global input used for high fanout, or clock/ reset net. The G0 pin ~~aa~~ drives the GBUF0 global buffer. PIOT_45a G1 General I/O I/O In user mode, after configuration, this pin can be programmed as general I/O in user function. Global Input Global input used for high fanout, or clock/ reset net. The G1 pin ~~eea~~ drives the GBUF1 global buffer. PIOT_25b G3 General I/O I/O In user mode, after configuration, this pin can be programmed as general I/O in user function. Global Input Global input used for high fanout, or clock/ reset net. The G3 pin ~~ee~~ drives the GBUF3 global buffer. PIOT_12a G4 General I/O I/O In user mode, after configuration, this pin can be programmed as general I/O in user function. Global Input Global input used for high fanout, or clock/ reset net. The G4 pin ~~Sp~~ ~~**a**~~ drives the GBUF4 global buffer. PIOT_11b G5 General I/O I/O In user mode, after configuration, this pin can be programmed as general I/O in user function. Global Input Global input used for high fanout, or clock/ reset net. The G5 pin ~~i~~ drives the GBUF5 global buffer. PIOB_3b G6 General I/O I/O In user mode, after configuration, this pin can be programmed as general I/O in user function. Global Input Global input used for high fanout, or clock/ reset net. The G6 pin ~~aa~~ drives the GBUF6 global buffer.
## **5.1.5. LED Pins**
|**Signal Name**|**Function**|**I/O**|**Description**|
|---|---|---|---|
|RGB0|General I/O|Open-Drain I/O|In user mode, with user's choice, this pin can be<br>programmed as open drain I/O in user function.|
||LED|Open-Drain<br>Output|In user mode, with user's choice, this pin can be<br>programmed as open drain 24 mA output to drive external<br>LED.|
|RGB1|General I/O|Open-Drain I/O|In user mode, with user's choice, this pin can be<br>programmed as open drain I/O in user function.|
||LED|Open-Drain<br>Output|In user mode, with user's choice, this pin can be<br>programmed as open drain 24 mA output to drive external<br>LED.|
|RGB2|General I/O|Open-Drain I/O|In user mode, with user's choice, this pin can be<br>programmed as open drain I/O in user function.|
||LED|Open-Drain<br>Output|In user mode, with user's choice, this pin can be<br>programmed as open drain 24 mA output to drive external<br>LED.|
|IRLED|General I/O|Open-Drain I/O|In user mode, with user's choice, this pin can be<br>programmed as open drain I/O in user function.|
||LED|Open-Drain<br>Output|In user mode, with user's choice, this pin can be<br>programmed as open drain 400 mA output to drive external<br>LED.|
|PIOT_xx|General I/O|I/O|In user mode, with user's choice, this pin can be<br>programmed as I/O in user function in the top (xx = I/O|
© 2018-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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|**Signal Name**|**Function**|**I/O**|**Description**|
|---|---|---|---|
||||location).|
|PIOB_xx|General I/O|I/O|In user mode, with user's choice, this pin can be<br>programmed as I/O in user function in the bottom (xx = I/ O<br>location).|
## **5.2. Pin Information Summary**
|**Pin Type**<br>~~eee~~<br>~~Rs~~|**Pin Type**<br>~~eee~~<br>~~Rs~~|**iCE5LP1K**<br>~~a~~<br>~~eee~~|**iCE5LP1K**<br>~~a~~<br>~~eee~~|**iCE5LP1K**<br>~~a~~<br>~~eee~~|**iCE5LP2K**<br>~~eee~~|**iCE5LP2K**<br>~~eee~~|**iCE5LP2K**<br>~~eee~~|**iCE5LP4K**<br>~~eee~~|**iCE5LP4K**<br>~~eee~~|**iCE5LP4K**<br>~~eee~~|
|---|---|---|---|---|---|---|---|---|---|---|
|||**CM36**<br>~~eee~~<br>~~ee~~|**SWG36**<br>~~eee~~<br>~~ee~~|**SG48***<br>~~eee~~|**CM36**<br>~~eee~~<br>~~GG~~|**SWG36**<br>~~eee~~<br>~~GG~~|**SG48***<br>~~GG~~|**CM36**<br>~~eee~~|**SWG36**<br>~~eee~~|**SG48***<br>~~eee~~|
|General Purpose<br>I/O Per Bank<br>~~po~~<br>~~po~~<br>~~pO~~|Bank 0<br>~~Rs~~<br>~~po~~|12<br>~~ee~~|5<br>~~ee~~|17|12<br>~~GG~~|5<br>~~GG~~|17<br>~~GG~~|12|5|17|
||Bank 1<br>~~Rs ~~<br>~~po~~<br>~~po~~|4<br> ~~ee~~|15<br>~~ee~~|14|4<br>~~GG~~|15<br>~~GG~~|14<br>~~GG~~|4|15|14|
||Bank 2<br>~~po~~<br>~~po~~|10|6|8|10|6|8|10|6|8|
|Total General Purpose I/Os<br>~~po~~<br>~~pO~~<br>~~po Rs~~||26<br>~~ee~~|26<br>~~ee~~|39<br>|26<br>~~GG~~|26<br>~~GG~~|39<br>~~GG~~|26|26|39|
|VCC<br>~~po~~<br>~~pO~~<br>~~po Rs~~||1<br>~~ee~~|1<br>~~ee~~|2<br>|1<br>~~GG~~|1<br>~~GG~~|2<br>~~GG~~|1|1|2|
|VCCIO<br>~~po Rs~~<br>~~po~~<br>~~po~~<br>~~pO~~|Bank 0<br>~~Rs~~<br>~~po~~|1<br>~~ee~~|1<br>~~ee~~|1<br>|1<br>~~GG~~|1<br>~~GG~~|1<br>~~GG~~|1|1|1|
||Bank 1<br>~~Rs ~~<br>~~po~~<br>~~po~~|1<br> ~~ee~~|1<br>~~ee ~~|1<br>|1<br> ~~GG~~|1<br>~~GG~~|1<br>~~GG~~|1|1|1|
||Bank 2<br>~~po~~<br>~~po~~|1|1|1|1|1|1|1|1|1|
|VCCPLL<br>~~po~~<br>~~pO~~<br>~~po~~||1|1|1|1|1|1|1|1|1|
|VPP_2V5<br>~~po~~<br>~~pO~~<br>~~po~~<br>~~po~~||1|1|1|1|1|1|1|1|1|
|Dedicated ConfigPins<br>~~po~~<br>~~po~~<br>~~po~~||1|1|2|1|1|2|1|1|2|
|GND<br>~~po~~<br>~~po~~<br>~~po~~||2|2|0|2|2|0|2|2|0|
|GND_LED<br>~~po~~<br>~~po~~<br>~~po~~||1|1|0|1|1|0|1|1|0|
|Total Balls<br>~~po~~<br>~~po~~||36|36|48|36|36|48|36|36|48|
***Note:** 48-pin QFN package (SG48) requires the package paddle to be connected to GND.
© 2018-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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**iCE40 Ultra Family Data Sheet Data Sheet 5.3. iCE40 Ultra Part Number Description** iCE5LPXX - XXXXXITR **Device Family Shipping Method** iCE40 Ultra FPGA TR = Tape and Reel (See quantity below) TR50 = Tape and Reel, 50 units **Logic Cells** TR1K = Tape and Reel, 1,000 units 1K = 1,100 Logic Cells 2K = 2,048 Logic Cells **Grade** 4K = 3,520 Logic Cells I = Industrial | **Package** CM36 = 36-Ball ucfBGA (0.40 mm Ball Pitch) SWG36 = 36-Ball WLCSP (0.35 mm Ball Pitch) SG48 = 48-Pin QFN (0.50 mm Pin Pitch) **5.3.1. Tape and Reel Quantity Package TR Quantity** CM36 4,000 SWG36 5,000 SG48 2,000 **5.4. Ordering Part Numbers 5.4.1. Industrial Part Number LUTs Supply Voltage Package Pins Temperature** iCE5LP1K-CM36ITR 1100 1.2 V Halogen-Free ucfBGA 36 IND iCE5LP1K-CM36ITR50 1100 1.2 V Halogen-Free ucfBGA 36 IND iCE5LP1K-CM36ITR1K 1100 1.2 V Halogen-Free ucfBGA 36 IND iCE5LP1K-SWG36ITR 1100 1.2 V Halogen-Free WLCSP 36 IND iCE5LP1K-SWG36ITR50 1100 1.2 V Halogen-Free WLCSP 36 IND iCE5LP1K-SWG36ITR1K 1100 1.2 V Halogen-Free WLCSP 36 IND iCE5LP1K-SG48ITR 1100 1.2 V Halogen-Free QFN 48 IND iCE5LP1K-SG48ITR50 1100 1.2 V Halogen-Free QFN 48 IND iCE5LP2K-CM36ITR 2048 1.2 V Halogen-Free ucfBGA 36 IND iCE5LP2K-CM36ITR50 2048 1.2 V Halogen-Free ucfBGA 36 IND iCE5LP2K-CM36ITR1K 2048 1.2 V Halogen-Free ucfBGA 36 IND iCE5LP2K-SWG36ITR 2048 1.2 V Halogen-Free WLCSP 36 IND iCE5LP2K-SWG36ITR50 2048 1.2 V Halogen-Free WLCSP 36 IND iCE5LP2K-SWG36ITR1K 2048 1.2 V Halogen-Free WLCSP 36 IND iCE5LP2K-SG48ITR 2048 1.2 V Halogen-Free QFN 48 IND iCE5LP2K-SG48ITR50 2048 1.2 V Halogen-Free QFN 48 IND iCE5LP4K-CM36ITR 3520 1.2 V Halogen-Free ucfBGA 36 IND iCE5LP4K-CM36ITR50 3520 1.2 V Halogen-Free ucfBGA 36 IND iCE5LP4K-CM36ITR1K 3520 1.2 V Halogen-Free ucfBGA 36 IND iCE5LP4K-SWG36ITR 3520 1.2 V Halogen-Free WLCSP 36 IND ~~=~~ iCE5LP4K-SWG36ITR50 ~~.~~ 3520 1.2 V Halogen-Free WLCSP 36 IND © 2018-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02028-2.4 43
**iCE40 Ultra Family Data Sheet Data Sheet**
|**Part Number**|**LUTs**|**Supply Voltage **|**Package **|**Pins**|**Temperature**|
|---|---|---|---|---|---|
|iCE5LP4K-SWG36ITR1K|3520|1.2 V|Halogen-Free WLCSP|36|IND|
|iCE5LP4K-SG48ITR|3520|1.2 V|Halogen-Free QFN|48|IND|
|iCE5LP4K-SG48ITR50|3520|1.2 V|Halogen-Free QFN|48|IND|
© 2018-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02028-2.4
44
**iCE40 Ultra Family Data Sheet Data Sheet**
## **References**
For more information, refer to the following resources:
- iCE40 Programming and Configuration (FPGA-TN-02001)
- iCE40 SPI/I2C Hardened IP Usage Guide (FPGA-TN-02010)
- Advanced iCE40 SPI/I2C Hardened IP Usage Guide (FPGA-TN-02011)
- Memory Usage Guide for iCE40 Devices (FPGA-TN-02002)
- iCE40 sysCLOCK PLL Design and Usage Guide (FPGA-TN-02052)
- iCE40 Hardware Checklist (FPGA-TN-02006)
- iCE40 LED Driver Usage Guide (FPGA-TN-02021)
- DSP Function Usage Guide for iCE40 Devices (FPGA-TN-02007)
- iCE40 Oscillator Usage Guide (FPGA-TN-02008)
- iCE40 Ultra Pinout Files
- iCE40 Ultra Pin Migration Files
- Thermal Management
- Lattice design tools
- Schematic Symbols
- Package Diagrams
© 2018-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02028-2.4
45
**iCE40 Ultra Family Data Sheet Data Sheet**
## **Technical Support**
For assistance, submit a technical support case at www.latticesemi.com/techsupport.
© 2018-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02028-2.4
46
**iCE40 Ultra Family Data Sheet Data Sheet**
## **Revision History**
|**Revision History**||
|---|---|
|**Revision 2.4, August 2020**||
|**Section**<br>**Change Summary**<br>Disclaimers<br>Added this section.<br>Architecture<br><br>Removed paragraph regarding SCLK and SDI inputs fromsysCLOCK Phase Locked Loops<br>(PLLs)section.<br><br>Updated linked reference.<br><br>ModifiedFigure 3.3. PLL Diagram.<br>References<br>Updated document ID of sysCLOCK PLL Design and Usage Guide.<br>~~_—~~||
|**Revision 2.3, August 2018**||
|**Section**<br>**Change Summary**<br>DC and Switching Characteristics<br>Updated sysCONFIG Port Timing Specifications section. Updated tCR_SCKparameter in Table<br>4.21.<br>Pinout Information<br>Updated Configuration SPI Pins section.<br>Updated secondarysignal names from SPI_SDO to SPI_SO and from SPI_SS_B to SPI_SS.<br>~~——~~||
|**Revision 2.2, March 2018**||
|**Section**|**Change Summary**|
|Architecture|Updated sysDSP section.|
||<br>In supported functions list, corrected “Intermediate Reg” to “Intermediate Register for”.|
||<br>Revised description of sysDSP block diagram.|
||<br>Revised port names in Figure 3.5, Figure 3.6 and Figure 3.7.|
||<br>Removed Signal column from Table 3.6.|
||<br>Revised description of Figure 3.7 to “usingboth halves of sysDSP block”.|
|**Revision 2.1, January 2018**<br>**Section**<br>**Change Summary**<br>All<br><br>Changed document number from DS1048 to FPGA-DS-02028.<br><br>Updated document template.<br><br>Updated linked references.<br>Product Family<br>Updated Product Family section. In Table 2.1. iCE40 Ultra Family Selection Guide, changed<br>48-ball QFN to 48-pin QFN.<br>Architecture<br>Updated sysDSP section.<br><br>In supported functions list, corrected “Intermediate Reg” to “Intermediate Register for”.<br><br>Revised description of sysDSP block diagram.<br><br>Revised port names in Figure 3.5, Figure 3.6 and Figure 3.7.<br><br>Removed Signal column from Table 3.6.<br><br>Revised description of Figure 3.7 to “usingboth halves of sysDSP block”.<br>References<br><br>Updated Corrected link to Schematic Symbols.<br><br>Added link to the iCE40 Ultra Pinout Files and the iCE40 Ultra Pin Migration Files.<br><br>Added reference to the Package Diagrams Data Sheet.<br>~~—~~||
|© 2018-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed atwww.latticesemi.com/legal.<br>All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.<br>**Revision 2.0, June 2016**<br>**Section**<br>**Change Summary**<br>General Description<br>Updated General Description section. Changed “high current driver” to “high current IR<br>driver”.<br>Product Family<br>Updated Product Family section. In Table 2.1. iCE40 Ultra Family Selection Guide, corrected<br>HF Oscillator (48 kHz) to (48 MHz).<br><br>Added “RGB LED and IR LED” to configurable Controllers.<br><br>Added “LED” to RGB control functions.<br>~~——~~||
|FPGA-DS-02028-2.4|47|
47
**iCE40 Ultra Family Data Sheet Data Sheet**
|**Section**|**Change Summary**|
|---|---|
|Architecture|Updated Architecture Overview section.<br><br>Changed content to “The Programmable Logic Blocks (PLB) and sysMEM EBR blocks, are<br>arranged in a two-dimensional grid with rows and columns. Each column has either PLB<br>or EBR blocks."<br><br>Changed “high current LED sink” to "high current RGB and IR LED sinks".|
||Updated sysCLOCK Phase Locked Loops (PLLs) section. Corrected VCCPLLcharacter format in<br>Figure 3.3. PLL Diagram.|
||Updated sysMEM Embedded Block RAM Memory section. Updated footnote in Table 3.4.<br>sysMEM Block Configurations*.|
||Updated sysIO Buffer Banks section.<br><br>Changed statement to “The configuration SPI interface signals are powered by<br>SPI_VCCIO1.”<br><br>Corrected VCCIOcharacter format in Figure 3.8. I/O Bank and Programmable I/O Cell.|
||Updated Typical I/O Behavior duringPower-upsection. Modified text content.|
||Updated Supported Standards section. Changed statement to “The iCE40 Ultra sysIO buffer<br>supports both single-ended input/output standards, and used as differential comparators.”|
||Updated On-Chip Oscillator section. Changed statement to “The high frequency oscillator<br>(HFOSC) runs at a nominal frequency of 48 MHz, divisible to 24 MHz, 12 MHz, or 6 MHz by<br>user option.”|
||Updated section heading to High Current LED Drive I/O Pins. Changed “high current drive” to<br>“high current LED drive”.|
||Removed Power On Reset section.|
|DC and Switching Characteristics|Updated Absolute Maximum Ratings section. Corrected symbol character format.|
||Updated Recommended Operating Conditions section.<br><br>Corrected symbol character format.<br><br>Revised footnote 1.<br><br>Added footnote 4.|
||Updated Power Supply Ramp Rates section. Changed tRAMPMax. value.|
||Updated section headingto Power-upSupplySequence. Revised text content.|
||Added the following sections:<br><br>Power-On Reset<br><br>External Reset|
||Updated DC Electrical Characteristics section. Revised footnote 4.|
||Updated Supply Current section.<br><br>Corrected IPP2V5STDBYparameter.<br><br>Added Typ. VCC = 1.2 V values for ICCPEAK, IPP_2V5PEAK, ISPI_VCCIO1PEAK, and ICCIOPEAK.<br><br>Added footnote 5.<br><br>Corrected SPI_VCCIO1character format.|
||Updated User SPI Specifications section. Removedparameters and added footnotes.|
||Updated Internal Oscillators (HFOSC, LFOSC) section. Added Commercial and Industrial Temp<br>values for fCLKHFand DCHCLKHF.|
||Updated sysI/O Single-Ended DC Electrical Characteristics section. Removed footnotes.|
||Updated Register-to-Register Performance section. Revised footnotes.|
||Updated iCE40 Ultra External SwitchingCharacteristics section. Revised footnote.|
||Updated sysCLOCK PLL Timingsection. Revised tOPJIT conditions.|
||Updated sysCONFIG Port Timing Specifications section.<br><br>Modified tCR_SCKMin. value.<br><br>Added footnote 4 to tSUparameter.<br><br>Modified tSUMin. value.|
© 2018-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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FPGA-DS-02028-2.4
**iCE40 Ultra Family Data Sheet Data Sheet**
|**Section**|**Change Summary**|
|---|---|
||<br>Modified tHDparameter.|
||Updated section heading to RGB LED and IR LED Drive. Modified ILED_ACCURACY and<br>IIR_ACCURACYparameters, Min. and Max. values.|
|Pinout Information|Updated Signal Descriptions section. Changed VCCIO_1 to SPI_VCCIO1 in the CDONE,<br>CRESETB and PIOB_xx descriptions.|
||Updated Pin Information Summarysection.<br><br>Corrected symbol character format.<br><br>Corrected VCPP_2V5to VPP_2V5.|
## **Revision 1.9, June 2016**
|**Section**|**Change Summary**|
|---|---|
|General Information|Updated Features section. Updated BGApackage to ucfBGA.|
|DC and Switching Characteristics|Updated Differential Comparator Electrical Characteristics section. Corrected typo in VREF<br>Max. value.|
|Pinout Information|Updated Signal Descriptions section section.<br><br>Changed PIOB_12a to PIOB_xx.<br><br>Changed SPI_CSN to SPI_SS_B and revised description when in Slave SPI mode.<br><br>Corrected minor typo errors.<br><br>Corrected formattingerrors.|
||Updated Pin Information Summarysection. Added footnote to SG48.|
||Updated iCE40 Ultra Part Number Description. Updated BGApackage to ucfBGA.|
||Updated OrderingPart Numbers section. Updated BGApackage to ucfBGA.|
Updated Ordering Part Numbers section. Updated BGA package to ucfBGA.
**Revision 1.8, June 2015 Section Change Summary** DC and Switching Characteristics Updated Internal Oscillators (HFOSC, LFOSC) section. Removed decimals. Pinout Information Updated iCE40 Ultra Part Number Description section. Added TR items. Corrected formatting errors. ~~———~~ Updated Ordering Part Numbers section. Updated CM36 and SG48 packages. **Revision 1.7, April 2015 Section Change Summary** Architecture Updated sysDSP section. Revised the following figures: Figure 3.5. sysDSP Functional Block Diagram (16-bit x 16-bit Multiply-Accumulate) Figure 3.6. sysDSP 8-bit x 8-bit Multiplier Figure 3.7. DSP 16-bit x 16-bit Multiplier Ordering Information Updated iCE5LP Part Number Description section. Added TR items. Updated Ordering Part Numbers section. Added CM36, SW36 and SG48 part numbers. ~~aE~~ **Revision 1.6, March 2015 Section Change Summary** General Information Updated Features section. Added BGA and QFN packages in Flexible Logic Architecture. Added USB 3.1 Type C Cable Detect / Power Delivery Applications in Applications. Product Family Updated Table 2.1. iCE40 Ultra Family Selection Guide. Added 36- ball ucfBGA and 48-pin QFN packages. Changed subheading to Total User I/O Count. Changed RBW IP to PWM IP. Deleted footnotes. ~~on~~ © 2018-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02028-2.4
49
**iCE40 Ultra Family Data Sheet Data Sheet**
|**Section**|**Change Summary**|
|---|---|
|DC and Switching Characteristics|<br>Updated Power-up Supply Sequence section. Indicated all devices in second paragraph.<br><br>Updated sysI/O Single-Ended DC Electrical Characteristics section. Changed LVCMOS 3.3<br>and LVCMOS 2. 5 VOH Min. (V) from 0.5 to 0.4.<br><br>Replaced the Differential Comparator Electrical Characteristics table.|
|Pinout Information|Updated Pin Information Summary section.<br><br>Added CM36 and SG48 values.<br><br>Changed CRESET_B to Dedicated ConfigPins.|
||Updated iCE40 Ultra Part Number Description section.<br><br>Added CM36 and SG48 package.<br><br>Added TR items.|
||Updated OrderingPart Numbers section. Added CM36, SW36 and SG48part numbers.|
## **Revision 1.5, October 2014**
|**Section**|**Change Summary**|
|---|---|
|General Information|Updated Features section.|
||<br>Removed 26 I/O pins for 36-pin WLCSP under Flexible Logic Archi- tecture.|
||<br>Changed form factor to 2.078 mm x 2.078 mm.|
|Product Family|<br>Updated Table 2.1. iCE40 Ultra Family Selection Guide. Removed 20-Ball WLCSP.|
||<br>Updated Overview section. Changed form factor to 2.078 mm x 2.078 mm.|
|Architecture|Updated sysCLOCK Phase Locked Loops (PLLs) section. Removed note in heading regarding|
||sysCLOCK PLL support.|
|DC and Switching Characteristics|<br>Updated Recommended Operating Conditions section. Removed footnote on sysCLOCK|
||PLL support.|
||<br>Updated Power-up Supply Sequence section. Removed information on 20-pin WLCSP.|
|Pinout Information|<br>Updated Signal Descriptions section. Removed references 20-pin WLCSP.|
||<br>Updated Pin Information Summary section. Removed references to UWG20 values.|
||<br>Updated iCE40 Ultra Part Number Description section. Removed 20-ball WLCSP.|
||<br>Updated Ordering Part Numbers section. Removed UWG20 part numbers.|
|Further Information|Added technical note references.|
|**Revision 1.4, August 2014**<br>**Section**<br>**Change Summary**<br>All<br>Removed Preliminarydocument status.<br>General Information<br>Updated General Description section. Added information on high cur- rent driver.<br>Updated Features section.<br><br>Changed standby current typical to as low as 71 µA.<br><br>Changed feature to Embedded Memory.<br>Product Family<br>Updated Table 2.1. iCE40 Ultra Family Selection Guide. Added<br>NVCM and Embedded PWM IP rows. Added (MULT16 with 32-bit Accu- mulator) to DSP<br>Block. Added Total I/O (Dedicated I/O) Count data.<br>General update to Introduction section.<br>Architecture<br>Updated Architecture Overview section.<br><br>Revised and added information on sysIO banks.<br><br>Updated reference for embedded PWM IP.<br>Updated iCE40 Ultra Programming and Configuration section.<br><br>Changed SPI1 to SPI.<br><br>Changed VCCIO_1 to SPI_VCCIO1.<br>~~=~~||
|© 2018-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed atwww.latticesemi.com/legal.||
|All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.||
|50|FPGA-DS-02028-2.4|
FPGA-DS-02028-2.4
**iCE40 Ultra Family Data Sheet Data Sheet**
|**Section**|**Change Summary**|
|---|---|
|DC and Switching Characteristics|Updated Absolute Maximum Ratings section. Changed PLL SupplyVoltage VCCPLL value.|
||Updated Recommended OperatingConditions section. Added footnote to VCCPLL.|
||Updated Power-upSupplySequence section. General update.|
||Updated Power-On-Reset Voltage Levels section. Changed the VPORUPVCCMax.value.|
||Updated DC Electrical Characteristics section. Added C3and C4information.|
||Updated Supply Current section.<br><br>Completed Typ. VCC =1.2 V4 data.<br><br>Changed symbols to ISPI_VCCIO1STDBYand ISPI_VCCIO1PEAK.<br><br>Added information to footnote 3.|
||Updated Internal Oscillators(HFOSC, LFOSC)section. General update.|
||Updated iCE40 Ultra External Switching Characteristics section. Added Max. value for<br>tCOPLL. Added Min. values for tSUPLLand tHPLL.|
||Updated sysCLOCK PLL Timing section. Added Max. value for tOPJIT.|
||Updated sysCONFIG Port Timing Specifications section.<br><br>Added TSUand THDinformation.<br><br>Added footnote 3 to Master SPI.|
||Updated High Current LED and IR LED Drive section. Updated Min. value.|
|**Section**|**Change Summary**|
|---|---|
|All|Changed document status from Advance to Preliminary.|
|General Information|Updated Features section. Adjusted Ultra-low Power Devices standbycurrent.|
|DC and SwitchingCharacteristics|Updated AC/DC specifications numbers.|
## **Revision 1.2, June 2014**
|**Section**|**Change Summary**|
|---|---|
|All|Product name changed to iCE40 Ultra.|
|Product Family|Updated Table 2.1. iCE40 Ultra FamilySelection Guide.. Removed 30- ball WLCSP.|
|DC and Switching Characteristics|Updated values in the following sections:<br><br>Supply Current<br><br>Internal Oscillators (HFOSC, LFOSC)<br><br>Power Supply Ramp Rates<br><br>Power-On-Reset Voltage Levels<br><br>SPI Master or NVCM Configuration Time|
||Indicated TBD for values to be determined.|
|Pinout Information|Updated Signal Descriptions section. Removed 30-pin WLCSP.|
||Updated Pin Information Summarysection. Removed SWG30 values.|
||Updated iCE40 Ultra Part Number Description section. Removed 30-ball WLCSP.|
||Updated OrderingPart Numbers section. Removed SWG30 and UWG30part numbers.|
© 2018-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02028-2.4
51
**iCE40 Ultra Family Data Sheet Data Sheet**
## **Revision 1.1, May 2014**
|**Section**|**Change Summary**|
|---|---|
|General Information|Updated General Description and Features sections. Removed hardened RGB PWM IP<br>information.|
|Product Family|Updated Overview section. Removed hardened RGB PWM IP information.|
|Architecture|Updated Architecture Overview section. Removed the RGB IP block in Figure 3.1. iCE5LP-4K<br>Device, TopView, Figure 3.8. I/O Bank and Programmable I/O Cell, and in the text content.|
||Updated High Current LED Drive I/O Pins section. Removed hardened RGB PWM IP<br>information.|
||Replaced RGB PWM Block section with Embedded PWM IP section.|
|DC and Switching Characteristics|Updated Power On Reset section. Removed content on Vccio_2power down option.|
||Removed RGB PWM Block Timingsection.|
|**Revision 1.0**|**Revision 1.0**|**Revision 1.0, April 2014**|**ril 2014**||
|---|---|---|---|---|
||**Section**|||**Change Summary**|
||All|||Initial release|
© 2018-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
52
FPGA-DS-02028-2.4
www.latticesemi.com
Updated at April 17, 2026
Lattice Semiconductor is a premier developer of low-power, programmable design solutions, specializing in Field-Programmable Gate Arrays (FPGAs) and Programmable Logic Devices (PLDs). Recognized for driving innovation in cost-effective and power-efficient architectures, the company provides essential semiconductor components for consumer, mobile, and industrial design applications. Our selection of Lattice Semiconductor products is focused on their highly regarded FPGA integrated circuits. Devices from industry-leading families like the iCE40, MachXO, and LatticeECP series offer designers an exceptional combination of high system integration and industry-low power consumption. These FPGAs are engineered to handle complex tasks such as sensor management, custom connectivity, and advanced video processing while minimizing overall board footprint. To ensure seamless integration from concept to production, Lattice backs its hardware with a comprehensive support ecosystem. Engineers can accelerate their development cycles utilizing intuitive tools like the Lattice Diamond design software, paired with flexible IP cores and reference designs that reduce design risk and increase system reliability.
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