ICE40UP5K-UWG30ITR1K

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## **iCE40 UltraPlus Family Data Sheet** 

## **Data Sheet** 

FPGA-DS-02008-1.9 

December 2020 

**iCE40 UltraPlus Family Data Sheet Data Sheet** 

## **Disclaimers** 

Lattice makes no warranty, representation, or guarantee regarding the accuracy of information contained in this document or the suitability of its products for any particular purpose. All information herein is provided AS IS and with all faults, and all risk associated with such information is entirely with Buyer. Buyer shall not rely on any data and performance specifications or parameters provided herein. Products sold by Lattice have been subject to limited testing and it is the Buyer's responsibility to independently determine the suitability of any products and to test and verify the same. No Lattice products should be used in conjunction with mission- or safety-critical or any other application in which the failure of Lattice’s product could create a situation where personal injury, death, severe property or environmental damage may occur. The information provided in this document is proprietary to Lattice Semiconductor, and Lattice reserves the right to make any changes to the information in this document or to any products at any time without notice. 

© 2018-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

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**iCE40 UltraPlus Family Data Sheet Data Sheet** 

## **Contents** 

|**Contents**|**Contents**|**Contents**|
|---|---|---|
|Acronyms in This Document ................................................................................................................................................. 7|||
|1.|1.<br>General Description ...................................................................................................................................................... 8||
||1.1.|Features .............................................................................................................................................................. 8|
|2.|2.<br>Product Family .............................................................................................................................................................. 9||
||2.1.|Overview ............................................................................................................................................................. 9|
|3.|3.<br>Architecture ................................................................................................................................................................ 11||
||3.1.|Architecture Overview ...................................................................................................................................... 11|
||3.1.1.|3.1.1.<br>PLB Blocks ..................................................................................................................................................... 12|
||3.1.2.|3.1.2.<br>Routing .......................................................................................................................................................... 13|
||3.1.3.|3.1.3.<br>Clock/Control Distribution Network ............................................................................................................. 13|
||3.1.4.|3.1.4.<br>sysCLOCK Phase Locked Loops (PLLs) ........................................................................................................... 14|
||3.1.5.|3.1.5.<br>sysMEM Embedded Block RAM Memory ..................................................................................................... 15|
||3.1.6.|3.1.6.<br>sysMEM Single Port RAM Memory (SPRAM) ................................................................................................ 17|
||3.1.7.|3.1.7.<br>sysDSP ........................................................................................................................................................... 18|
||3.1.8.|3.1.8.<br>sysI/O Buffer Banks ....................................................................................................................................... 23|
||3.1.9.|3.1.9.<br>sysI/O Buffer ................................................................................................................................................. 26|
||3.1.10. On-Chip Oscillator ......................................................................................................................................... 26||
||3.1.11. User I2C IP ..................................................................................................................................................... 27||
||3.1.12. User SPI IP ..................................................................................................................................................... 27||
||3.1.13. RGB High Current Drive I/O Pins ................................................................................................................... 27||
||3.1.14. RGB PWM IP ................................................................................................................................................. 27||
||3.1.15. Non-Volatile Configuration Memory ............................................................................................................ 28||
||3.2.|iCE40 UltraPlus Programming and Configuration ............................................................................................. 28|
||3.2.1.|3.2.1.<br>Device Programming ..................................................................................................................................... 28|
||3.2.2.|3.2.2.<br>Device Configuration .................................................................................................................................... 28|
||3.2.3.|3.2.3.<br>Power Saving Options ................................................................................................................................... 28|
|4.|4.<br>DC and Switching Characteristics ............................................................................................................................... 29||
||4.1.|Absolute Maximum Ratings .............................................................................................................................. 29|
||4.2.|Recommended Operating Conditions ............................................................................................................... 29|
||4.3.|Power Supply Ramp Rates ................................................................................................................................ 30|
||4.4.|Power-On Reset ................................................................................................................................................ 30|
||4.5.|Power-up Supply Sequence............................................................................................................................... 30|
||4.6.|External Reset ................................................................................................................................................... 30|
||4.7.|Power-On-Reset Voltage Levels ........................................................................................................................ 31|
||4.8.|ESD Performance .............................................................................................................................................. 31|
||4.9.|DC Electrical Characteristics .............................................................................................................................. 32|
||4.10.|Supply Current .................................................................................................................................................. 32|
||4.11.|User I2C Specifications ....................................................................................................................................... 33|
||4.12.|I2C 50 ns Delay ................................................................................................................................................... 33|
||4.13.|I2C 50 ns Filter ................................................................................................................................................... 33|
||4.14.|User SPI Specifications ...................................................................................................................................... 33|
||4.15.|Internal Oscillators (HFOSC, LFOSC) .................................................................................................................. 34|
||4.16.|sysI/O Recommended Operating Conditions .................................................................................................... 34|
||4.17.|sysI/O Single-Ended DC Electrical Characteristics ............................................................................................. 34|
||4.18.|Differential Comparator Electrical Characteristics ............................................................................................ 35|
||4.19.|Typical Building Block Function Performance ................................................................................................... 35|
||4.19.1. Pin-to-Pin Performance (LVCMOS25) ........................................................................................................... 35||
||4.19.2. Register-to-Register Performance ................................................................................................................ 35||
||4.20.|sysDSP Timing ................................................................................................................................................... 36|
||4.21.|SPRAM Timing ................................................................................................................................................... 36|
||4.22.|Derating Logic Timing ........................................................................................................................................ 36|
||4.23.|Maximum sysI/O Buffer Performance .............................................................................................................. 36|



© 2018-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

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**iCE40 UltraPlus Family Data Sheet Data Sheet** 

||4.24.|iCE40 UltraPlus Family Timing Adders ............................................................................................................... 37|
|---|---|---|
||4.25.|iCE40 UltraPlus External Switching Characteristics ........................................................................................... 37|
||4.26.|sysCLOCK PLL Timing ......................................................................................................................................... 38|
||4.27.|SPI Master or NVCM Configuration Time .......................................................................................................... 38|
||4.28.|sysCONFIG Port Timing Specifications ............................................................................................................... 39|
||4.29.|RGB LED Drive ................................................................................................................................................... 40|
||4.30.|Switching Test Conditions ................................................................................................................................. 40|
|5.|5.<br>Pinout Information ..................................................................................................................................................... 41||
||5.1.|Signal Descriptions ............................................................................................................................................ 41|
||5.1.1.|5.1.1.<br>Power Supply Pins ......................................................................................................................................... 41|
||5.1.2.|5.1.2.<br>Configuration Pins ......................................................................................................................................... 41|
||5.1.3.|5.1.3.<br>Configuration SPI Pins ................................................................................................................................... 42|
||5.1.4.|5.1.4.<br>Global Pins .................................................................................................................................................... 43|
||5.1.5.|5.1.5.<br>General I/O, LED Pins .................................................................................................................................... 44|
||5.2.|Pin Information Summary ................................................................................................................................. 45|
||5.3.|iCE40UP Part Number Description .................................................................................................................... 46|
||5.3.1.|5.3.1.<br>Tape and Reel Quantity ................................................................................................................................ 46|
||5.4.|Ordering Part Numbers ..................................................................................................................................... 46|
||5.4.1.|5.4.1.<br>Industrial ....................................................................................................................................................... 46|
|Supplemental Information .................................................................................................................................................. 47|||
|Technical Support ............................................................................................................................................................... 48|||
|Revision History .................................................................................................................................................................. 49|||



© 2018-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02008-1.9 

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**iCE40 UltraPlus Family Data Sheet Data Sheet** 

## **Figures** 

|Figure 3.1. iCE40UP5K Device, Top View ............................................................................................................................ 11|Figure 3.1. iCE40UP5K Device, Top View ............................................................................................................................ 11|
|---|---|
|Figure 3.2. PLB Block Diagram ............................................................................................................................................ 12|Figure 3.2. PLB Block Diagram ............................................................................................................................................ 12|
|Figure 3.3. PLL Diagram ...................................................................................................................................................... 14|Figure 3.3. PLL Diagram ...................................................................................................................................................... 14|
|Figure 3.4. sysMEM Memory Primitives ............................................................................................................................. 16|Figure 3.4. sysMEM Memory Primitives ............................................................................................................................. 16|
|Figure 3.5. SPRAM Primitive ............................................................................................................................................... 17|Figure 3.5. SPRAM Primitive ............................................................................................................................................... 17|
|Figure 3.6. sysDSP Functional Block Diagram (16-bit x 16-bit Multiply-Accumulate) ........................................................ 19|Figure 3.6. sysDSP Functional Block Diagram (16-bit x 16-bit Multiply-Accumulate) ........................................................ 19|
|Figure 3.7. sysDSP 8-bit x 8-bit Multiplier ........................................................................................................................... 22|Figure 3.7. sysDSP 8-bit x 8-bit Multiplier ........................................................................................................................... 22|
|Figure 3.8. DSP 16-bit x 16-bit Multiplier ........................................................................................................................... 23|Figure 3.8. DSP 16-bit x 16-bit Multiplier ........................................................................................................................... 23|
|Figure 3.9. I/O Bank and Programmable I/O Cell ............................................................................................................... 24|Figure 3.9. I/O Bank and Programmable I/O Cell ............................................................................................................... 24|
|Figure 3.10. iCE I/O Register Block Diagram ....................................................................................................................... 25|Figure 3.10. iCE I/O Register Block Diagram ....................................................................................................................... 25|
|Figure 4.1. Power Up Sequence with SPE_VCCIO1 and VPP_2V5 Not Connected Together .............................................. 31|Figure 4.1. Power Up Sequence with SPE_VCCIO1 and VPP_2V5 Not Connected Together .............................................. 31|
|Figure 4.2. Power Up Sequence with All Supplies Connected Together to 1.8 V ............................................................... 31|Figure 4.2. Power Up Sequence with All Supplies Connected Together to 1.8 V ............................................................... 31|
|Figure 4.3. Output Test Load, LVCMOS Standards ............................................................................................................. 40|Figure 4.3. Output Test Load, LVCMOS Standards ............................................................................................................. 40|



© 2018-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02008-1.9 

5 

**iCE40 UltraPlus Family Data Sheet Data Sheet** 

## **Tables** 

|Table 2.1. iCE40 UltraPlus Family Selection Guide ............................................................................................................... 9|Table 2.1. iCE40 UltraPlus Family Selection Guide ............................................................................................................... 9|
|---|---|
|Table 3.1. Logic Cell Signal Descriptions ............................................................................................................................. 13|Table 3.1. Logic Cell Signal Descriptions ............................................................................................................................. 13|
|Table 3.2. Global Buffer (GBUF) Connections to Programmable Logic Blocks .................................................................... 13|Table 3.2. Global Buffer (GBUF) Connections to Programmable Logic Blocks .................................................................... 13|
|Table 3.3. PLL Signal Descriptions ....................................................................................................................................... 15|Table 3.3. PLL Signal Descriptions ....................................................................................................................................... 15|
|Table 3.4. sysMEM Block Configurations ............................................................................................................................ 15|Table 3.4. sysMEM Block Configurations ............................................................................................................................ 15|
|Table 3.5. EBR Signal Descriptions ...................................................................................................................................... 16|Table 3.5. EBR Signal Descriptions ...................................................................................................................................... 16|
|Table 3.6. SPRAM Signal Descriptions ................................................................................................................................ 18|Table 3.6. SPRAM Signal Descriptions ................................................................................................................................ 18|
|Table 3.7. Output Block Port Description ........................................................................................................................... 19|Table 3.7. Output Block Port Description ........................................................................................................................... 19|
|Table 3.8. PIO Signal List ..................................................................................................................................................... 25|Table 3.8. PIO Signal List ..................................................................................................................................................... 25|
|Table 3.9. Supported Input Standards ................................................................................................................................ 26|Table 3.9. Supported Input Standards ................................................................................................................................ 26|
|Table 3.10. Supported Output Standards ........................................................................................................................... 26|Table 3.10. Supported Output Standards ........................................................................................................................... 26|
|Table 3.11. iCE40 UltraPlus Power Saving Features Description ........................................................................................ 28|Table 3.11. iCE40 UltraPlus Power Saving Features Description ........................................................................................ 28|
|Table 4.1. Absolute Maximum Ratings ............................................................................................................................... 29|Table 4.1. Absolute Maximum Ratings ............................................................................................................................... 29|
|Table 4.2. Recommended Operating Conditions ................................................................................................................ 29|Table 4.2. Recommended Operating Conditions ................................................................................................................ 29|
|Table 4.3. Power Supply Ramp Rates ................................................................................................................................. 30|Table 4.3. Power Supply Ramp Rates ................................................................................................................................. 30|
|Table 4.4. Power-On-Reset Voltage Levels ......................................................................................................................... 31|Table 4.4. Power-On-Reset Voltage Levels ......................................................................................................................... 31|
|Table 4.5. DC Electrical Characteristics ............................................................................................................................... 32|Table 4.5. DC Electrical Characteristics ............................................................................................................................... 32|
|Table 4.6. Supply Current ................................................................................................................................................... 32|Table 4.6. Supply Current ................................................................................................................................................... 32|
|Table 4.7. User I|Table 4.7. User I2C Specifications ........................................................................................................................................ 33|
|Table 4.8. I|Table 4.8. I2C 50 ns Delay .................................................................................................................................................... 33|
|Table 4.9. I|Table 4.9. I2C 50 ns Filter .................................................................................................................................................... 33|
|Table 4.10. User SPI Specifications ..................................................................................................................................... 33|Table 4.10. User SPI Specifications ..................................................................................................................................... 33|
|Table 4.11. Internal Oscillators (HFOSC, LFOSC) ................................................................................................................. 34|Table 4.11. Internal Oscillators (HFOSC, LFOSC) ................................................................................................................. 34|
|Table 4.12. sysI/O Recommended Operating Conditions ................................................................................................... 34|Table 4.12. sysI/O Recommended Operating Conditions ................................................................................................... 34|
|Table 4.13. sysI/O Single-Ended DC Electrical Characteristics ............................................................................................ 34|Table 4.13. sysI/O Single-Ended DC Electrical Characteristics ............................................................................................ 34|
|Table 4.14. Differential Comparator Electrical Characteristics ........................................................................................... 35|Table 4.14. Differential Comparator Electrical Characteristics ........................................................................................... 35|
|Table 4.15. Pin-to-Pin Performance (LVCMOS25)............................................................................................................... 35|Table 4.15. Pin-to-Pin Performance (LVCMOS25)............................................................................................................... 35|
|Table 4.16. Register-to-Register Performance.................................................................................................................... 35|Table 4.16. Register-to-Register Performance.................................................................................................................... 35|
|Table 4.17. sysDSP Timing .................................................................................................................................................. 36|Table 4.17. sysDSP Timing .................................................................................................................................................. 36|
|Table 4.18. Single Port RAM Timing .................................................................................................................................... 36|Table 4.18. Single Port RAM Timing .................................................................................................................................... 36|
|Table 4.19. Maximum sysI/O Buffer Performance ............................................................................................................. 36|Table 4.19. Maximum sysI/O Buffer Performance ............................................................................................................. 36|
|Table 4.20. iCE40 UltraPlus Family Timing Adders ............................................................................................................. 37|Table 4.20. iCE40 UltraPlus Family Timing Adders ............................................................................................................. 37|
|Table 4.21. iCE40 UltraPlus External Switching Characteristics .......................................................................................... 37|Table 4.21. iCE40 UltraPlus External Switching Characteristics .......................................................................................... 37|
|Table 4.22. sysCLOCK PLL Timing ........................................................................................................................................ 38|Table 4.22. sysCLOCK PLL Timing ........................................................................................................................................ 38|
|Table 4.23. SPI Master or NVCM Configuration Time ......................................................................................................... 38|Table 4.23. SPI Master or NVCM Configuration Time ......................................................................................................... 38|
|Table 4.24. sysCONFIG Port Timing Specifications ............................................................................................................. 39|Table 4.24. sysCONFIG Port Timing Specifications ............................................................................................................. 39|
|Table 4.25. RGB LED ............................................................................................................................................................ 40|Table 4.25. RGB LED ............................................................................................................................................................ 40|
|Table 4.26. Test Fixture Required Components, Non-Terminated Interfaces .................................................................... 40|Table 4.26. Test Fixture Required Components, Non-Terminated Interfaces .................................................................... 40|



© 2018-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02008-1.9 

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**iCE40 UltraPlus Family Data Sheet Data Sheet** 

## **Acronyms in This Document** 

A list of acronyms used in this document. 

|**Acronym **|**Definition**|
|---|---|
|DFF|D-style Flip-Flop|
|DSP|Digital Signal Processor|
|EBR|Embedded Block RAM|
|HFOSC|High FrequencyOscillator|
|I2C|Inter-Integrated Circuit|
|LFOSC|Low FrequencyOscillator|
|LUT|Look UpTable|
|LVCMOS|Low-Voltage ComplementaryMetal Oxide Semiconductor|
|NVCM|Non Volatile Configuration Memory|
|PCLK|PrimaryClock|
|PFU|Programmable Functional Unit|
|PIC|Programmable I/O Cells|
|PLB|Programmable Logic Blocks|
|PLL|Phase Locked Loops|
|SoC|System on a Chip|
|SPI|Serial Peripheral Interface|
|SPR|Single Port RAM|
|WLCSP|Wafer Level ChipScale Packaging|



© 2018-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02008-1.9 

7 

**iCE40 UltraPlus Family Data Sheet Data Sheet** 

## **1. General Description** 

iCE40 UltraPlus™ family from Lattice Semiconductor is an ultra-low power FPGA and sensor manager designed for ultra-low power mobile applications, such as smartphones, tablets and hand-held devices. iCE40 UltraPlus is compatible with Lattice's iCE40 Ultra family devices, containing all the functions iCE40 Ultra family has except the high current IR LED driver. In addition, the iCE40 UltraPlus features an additional 1 Mb SRAM, additional DSP blocks, with additional LUTs, all which can be used to support an always-on Voice Recognition function in the mobile devices, without the need to keep the higher power consuming voice codec on all the time. 

The iCE40 UltraPlus family includes integrated SPI and I[2] C blocks to interface with virtually all mobile sensors and application processors. In addition, the iCE40 UltraPlus family also features two I/O pins that can support the interface to I3C devices. There are two on-chip oscillators, 10 kHz and 48 MHz, the LFOSC (10 kHz) is ideal for low power function in always-on applications, while HFOSC (48 MHz) can be used for awaken activities. 

The iCE40 UltraPlus family also features DSP functional block to off-load Application Processor to pre-process information sent from the mobile device, such as voice data. The RGB PWM IP, with the three 24 mA constant current RGB outputs on the iCE40 UltraPlus provides all the necessary logic to directly drive the service LED, without the need of external MOSFET or buffer. 

The iCE40 UltraPlus family of devices are targeting for mobile applications to perform all the functions in iCE40 Ultra devices, such as Service LED, GPIO Expander, SDIO Level Shift, and other custom functions. In addition, the iCE40 UltraPlus family devices are also targeting for Voice Recognition application. 

The iCE40 UltraPlus family features two device densities, 2800 to 5280 Look Up Tables (LUTs) of logic with programmable I/Os that can be used as either SPI/I[2] C interface ports or general purpose I/O’s. Two of the iCE40 UltraPlus I/Os can be used to interface to higher performance I3C. It also has up to 120 kb of Block RAMs, plus 1024 kb of Single Port SRAMs to work with user logic. 

## **1.1. Features** 

- Flexible Logic Architecture 

   - Two devices with 2800 to 5280 LUTs 

   - Offered in WLCS and QFN packages 

- Ultra-low Power Devices 

   - Advanced 40 nm low power process 

   - As low as 100 µA standby current typical 

- Embedded Memory 

   - Up to 1024 kb Single Port SRAM 

   - Up to 120 kb sysMEM™ Embedded Block RAM 

- Two Hardened I[2] C Interfaces 

   - Two I/O pins to support I3C interface 

- Two Hardened SPI Interfaces 

- Two On-Chip Oscillators 

   - Low Frequency Oscillator – 10 kHz 

   - High Frequency Oscillator – 48 MHz 

- 24 mA Current Drive RGB LED Outputs 

   - Three drive outputs in each device 

   - User selectable sink current up to 24 mA 

- On-chip DSP 

   - Signed and unsigned 8-bit or 16-bit functions 

   - Functions include Multiplier, Accumulator, and Multiply-Accumulate (MAC) 

- Flexible On-Chip Clocking 

   - Eight low skew global signal resource, six can be directly driven from external pins 

   - One PLL with dynamic interface per device 

- Flexible Device Configuration 

   - SRAM is configured through: 

   - Standard SPI Interface 

   - Internal Nonvolatile Configuration Memory (NVCM) 

- Ultra-Small Form Factor 

   - As small as 2.11 mm × 2.54 mm 

- Applications 

   - Always-On Voice Recognition Application 

   - Smartphones 

   - Tablets and Consumer Handheld Devices 

   - Handheld Commercial and Industrial Devices 

   - Multi Sensor Management Applications 

   - Sensor Pre-processing and Sensor Fusion 

   - Always-On Sensor Applications 

   - USB 3.1 Type C Cable Detect / Power Delivery Applications 

© 2018-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

8 

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**iCE40 UltraPlus Family Data Sheet Data Sheet** 

## **2. Product Family** 

Table 2.1 lists device information and packages of the iCE40 UltraPlus family. 

**Table 2.1. iCE40 UltraPlus Family Selection Guide** 

|**Part Number**<br>~~a~~|**iCE40UP3K**<br>~~a~~|**iCE40UP5K**<br>~~a~~|
|---|---|---|
|**Logic Cells (LUT + Flip-Flop)**<br>~~GC~~|**2800**<br>~~GC~~|**5280**<br>~~GC~~|
|EBR Memory Blocks<br>~~GC~~<br>~~a~~|20<br>~~GC~~|30<br>~~GC~~|
|EBR Memory Bits (Kbits)<br>~~GO~~|80<br>~~GO~~|120<br>~~GO~~|
|SPRAM Memory Blocks<br>~~GO~~<br>~~a~~|4<br>~~GO~~<br>~~a~~|4<br>~~GO~~<br>~~a~~|
|SPRAM Memory Bits (Kbits)<br>~~a~~|1024<br>~~a~~|1024<br>~~a~~|
|NVCM<br>~~GD~~|Yes<br>~~GD~~|Yes<br>~~GD~~|
|PLL<br>~~a~~|1<br>~~a~~|1<br>~~a~~|
|DSP Blocks (MULT16 with 32-bit Accumulator<br>~~a~~|4<br>~~a~~|8<br>~~a~~|
|Hardened I2C, SPI<br>~~a~~|2, 2<br>~~a~~|2, 2<br>~~a~~|
|HF Oscillator (48 MHz)<br>~~a~~|1<br>~~a~~|1<br>~~a~~|
|LF Oscillator (10 KHz)<br>~~a~~|1<br>~~a~~|1<br>~~a~~|
|24 mA LED Sink<br>~~a~~<br>~~a~~|3<br>~~a~~<br>~~a~~|3<br>~~a~~<br>~~a~~|
|PWM IP Block<br>~~GD~~|Yes<br>~~GD~~|Yes<br>~~GD~~|
|**Packages, ball pitch, dimension**<br>~~GD~~<br>~~a~~|**Total User I/O Count**<br>~~GD~~||
|30-ball WLCSP, 0.4 mm, 2.11 mm × 2.54 mm<br>~~a~~|21|21|
|48-ball QFN, 0.5 mm, 7.0 mm × 7.0 mm<br>~~a~~|-|39|



## **2.1. Overview** 

The iCE40 UltraPlus family of ultra-low power FPGAs has three devices with densities ranging from 2800 to 5280 LookUp Tables (LUTs) fabricated in a 40 nm Low Power CMOS process. In addition to LUT-based, low-cost programmable logic, these devices also feature Embedded Block RAM (EBR), Single Port RAM (SPRAM), on-chip Oscillators (LFOSC, HFOSC), two hardened I[2] C Controllers, two hardened SPI Controllers, PWM IP, three 24 mA RGB LED open-drain drivers, I3C interface pins, and DSP blocks. These features allow the devices to be used in low-cost, high-volume consumer and mobile applications. 

The iCE40 UltraPlus FPGAs are available in very small form factor packages, as small as 2.11 mm × 2.54 mm. The small form factor allows the device to easily fit into a lot of mobile applications, where space can be limited. Table 2.1 lists the LUT densities, package and I/O pin count. 

The iCE40 UltraPlus devices offer I/O features such as pull-up resistors. Pull-up features are controllable on a “per pin” basis. In addition, the iCE40 UltraPlus devices offer two I/Os with dynamic control on the pull-up resistors to support I3C interface. 

The RGB PWM IP in the iCE40 UltraPlus devices provides controls for driving the 24 mA LED Sink driver, including color controls, LED ON/OFF time, and breathe rate. 

The iCE40 UltraPlus devices also provide flexible, reliable and secure configuration from on-chip NVCM. These devices can also configure themselves from external SPI Flash, or be configured by an external master such as a CPU. 

© 2018-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02008-1.9 

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**iCE40 UltraPlus Family Data Sheet Data Sheet** 

Lattice provides a variety of design tools that allow complex designs to be efficiently implemented using the iCE40 UltraPlus family of devices. Popular logic synthesis tools provide synthesis library support for iCE40 UltraPlus. Lattice design tools use the synthesis tool output along with the user-specified preferences and constraints to place and route the design in the iCE40 UltraPlus device. These tools extract the timing from the routing and back-annotate it into the design for timing verification. 

Lattice provides many pre-engineered IP (Intellectual Property) modules, including a number of reference designs, licensed free of charge, optimized for the iCE40 UltraPlus FPGA family. Lattice also can provide fully verified bitstream for some of the widely used target functions in mobile device applications, such as ultra-low power sensor management, gesture recognition, IR remote, barcode emulator functions. Users can use these functions as offered by Lattice, or they can use the design to create their own unique required functions. For more information regarding Lattice's reference designs or fully-verified bitstreams, contact your local Lattice representative. 

© 2018-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

10 

FPGA-DS-02008-1.9 

**iCE40 UltraPlus Family Data Sheet Data Sheet** 

## **3. Architecture** 

## **3.1. Architecture Overview** 

The iCE40 UltraPlus family architecture contains an array of Programmable Logic Blocks (PLB), two Oscillator Generators, two user configurable I[2] C controllers, two user configurable SPI controllers, blocks of sysMEM™ Embedded Block RAM (EBR) and Single Port RAM (SPRAM) surrounded by Programmable I/O (PIO). Figure 3.1 shows the block diagram of the iCE40UP5K device. 

**==> picture [469 x 312] intentionally omitted <==**

**----- Start of picture text -----**<br>
PLB<br>I [2] C I/O Bank 0 I [2] C<br>HFOSC PLL LFOSC 50 ns Delay<br>50 ns Delay<br>50 ns Filter<br>50 ns Filter<br>5 PLB Rows<br>config<br>256 Kb 256 Kb 256 Kb 256 Kb<br>SPRAM SPRAM SPRAM SPRAM<br>config<br>SPI I/O Bank 2 I/O Bank 1_SPI SPI Carry Logic<br>4-Input Look-up<br>GO ft JG Table (LUT) gp<br>Flip-flop with Enableand Reset Controls<br>DSP DSP<br>DSP DSP<br>DSP DSP<br>DSP DSP<br>5  4 Kb DPRAM 5  4 Kb DPRAM<br>5  4 Kb DPRAM 5  4 Kb DPRAM<br>5  4 Kb DPRAM 5  4 Kb DPRAM<br>8 Logic Cells = Programmable Logic Block<br>RGB I/O RGB I/O RGB I/O I3C I/O I3C I/O<br>PWM IP<br>NVCM<br>**----- End of picture text -----**<br>


**Figure 3.1. iCE40UP5K Device, Top View** 

The Programmable Logic Blocks (PLB) and sysMEM EBR blocks, are arranged in a two-dimensional grid with rows and columns. Each column has either PLB or EBR blocks. The PIO cells are located at the top and bottom of the device, arranged in banks. The PLB contains the building blocks for logic, arithmetic, and register functions. The PIOs utilize a flexible I/O buffer referred to as a sysI/O buffer that supports operation with a variety of interface standards. The blocks are connected with many vertical and horizontal routing channel resources. The place and route software tool automatically allocates these routing resources. 

In the iCE40 UltraPlus family, there are three sysI/O banks, one on top and two at the bottom. User can connect some VCCIOs together, if all the I/Os are using the same voltage standard. See the Power-up Supply Sequence section. The sysMEM EBRs are large 4 kb, dedicated fast memory blocks. These blocks can be configured as RAM, ROM or FIFO with user logic using PLBs. 

In addition to the EBR, the iCE40 UltraPlus devices also feature four 256 kb SPRAM blocks that can be cascaded to create up to 1 Mb block. It is useful for temporary storage of large quantities of information. 

© 2018-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

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**iCE40 UltraPlus Family Data Sheet Data Sheet** 

Every device in the family has two user SPI ports, one of these (right side) SPI ports also supports programming and configuration of the device. The iCE40 UltraPlus also includes two user I[2] C ports, two oscillators, and high current RGB LED sink. 

## **3.1.1. PLB Blocks** 

The core of the iCE40 UltraPlus device consists of Programmable Logic Blocks (PLB) which can be programmed to perform logic and arithmetic functions. Each PLB consists of eight interconnected Logic Cells (LC) as shown in Figure 3.2. Each LC contains one LUT and one register. 

**==> picture [368 x 269] intentionally omitted <==**

**----- Start of picture text -----**<br>
Shared Block-Level Controls<br>Programmable  Clock<br>Logic Block (PLB)<br>Enable<br>FCOUT 1<br>Set/Reset<br>0 Logic Cell<br>Carry Logic<br>DFF O<br>I0 D Q<br>EN<br>I1<br>LUT SR<br>I2<br>I3<br>FCIN<br>Four-input Flip-flop with<br>Look-Up Table optional enable and<br>(LUT) set or reset controls<br>= Statically defined by configuration program<br>8 Logic Cells (LCs)<br>**----- End of picture text -----**<br>


**Figure 3.2. PLB Block Diagram** 

## **Logic Cells** 

Each Logic Cell includes three primary logic elements shown in Figure 3.2. 

- A four-input Look-Up Table (LUT) builds any combinational logic function, of any complexity, requiring up to four inputs. Similarly, the LUT element behaves as a 16x1 Read-Only Memory (ROM). Combine and cascade multiple LUTs to create wider logic functions. 

- A ‘D’-style Flip-Flop (DFF), with an optional clock-enable and reset control input, builds sequential logic functions. Each DFF also connects to a global reset signal that is automatically asserted immediately following device configuration. 

- Carry Logic boosts the logic efficiency and performance of arithmetic functions, including adders, subtracters, comparators, binary counters and some wide, cascaded logic functions. 

© 2018-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

12 

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**iCE40 UltraPlus Family Data Sheet Data Sheet** 

Table 3.1 lists the logic cell signals. 

**Table 3.1. Logic Cell Signal Descriptions** 

|**Function**|**Type**|**Signal Name**|**Description**|
|---|---|---|---|
|Input|Data signal|I0, I1, I2, I3|Inputs to LUT|
|Input|Control signal|Enable|Clock enable shared by all LCs in the PLB|
|Input|Control signal|Set/Reset*|Asynchronous or synchronous local set/reset shared by|
|Input|Control signal|Clock|Clock one of the eight Global Buffers, or from the|
|Input|Inter-PLB signal|FCIN|Fast carry in|
|Output|Data signals|O|LUT or registered output|
|Output|Inter-PFU signal|FCOUT|Fast carry out|



***Note** : If Set/Reset is not used, then the flip-flop is never set/reset, except when cleared immediately after configuration. 

## **3.1.2. Routing** 

There are many resources provided in the iCE40 UltraPlus devices to route signals individually with related control signals. The routing resources consist of switching circuitry, buffers and metal interconnect (routing) segments. 

The inter-PLB connections are made with three different types of routing resources: Adjacent (spans two PLBs), x4 (spans five PLBs) and x12 (spans thirteen PLBs). The Adjacent, x4 and x12 connections provide fast and efficient connections in the diagonal, horizontal and vertical directions. 

The design tool takes the output of the synthesis tool and places and routes the design. 

## **3.1.3. Clock/Control Distribution Network** 

Each iCE40 UltraPlus device has six global inputs, two pins on the top bank and four pins on the bottom bank. These global inputs can be used as high fanout nets, clock, reset or enable signals. The dedicated global pins are identified as Gxx and each drives one of the eight global buffers. The global buffers are identified as GBUF[7:0]. These six inputs may be used as general purpose I/O if they are not used to drive the clock nets. 

Table 3.2 lists the connections between a specific global buffer and the inputs on a PLB. All global buffers optionally connect to the PLB CLK input. Any four of the eight global buffers can drive logic inputs to a PLB. Even-numbered global buffers optionally drive the Set/Reset input to a PLB. Similarly, odd-numbered buffers optionally drive the PLB clockenable input. GBUF[7:6, 3:0] can connect directly to G[7:6, 3:0] pins respectively. GBUF4 and GBUF5 can connect to the two on-chip Oscillator Generators (GBUF4 connects to LFOSC, GBUF5 connects to HFOSC). 

**Table 3.2. Global Buffer (GBUF) Connections to Programmable Logic Blocks** 

|**Global Buffer**|**LUT Inputs**|**Clock**|**Reset**|**Clock Enable**|
|---|---|---|---|---|
|GBUF0|Yes, any 4 of 8 GBUF<br>Inputs|||—|
|GBUF1|||—||
|GBUF2||||—|
|GBUF3|||—||
|GBUF4||||—|
|GBUF5|||—||
|GBUF6||||—|
|GBUF7|||—||



© 2018-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

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**iCE40 UltraPlus Family Data Sheet Data Sheet** 

The maximum frequency for the global buffers are listed in Table 4.21. 

## **Global Hi-Z Control** 

The global high-impedance control signal, GHIZ, connects to all I/O pins on the iCE40 UltraPlus device. This GHIZ signal is automatically asserted throughout the configuration process, forcing all user I/O pins into their high-impedance state. 

## **Global Reset Control** 

The global reset control signal connects to all PLB and PIO flip-flops on the iCE40 UltraPlus device. The global reset signal is automatically asserted throughout the configuration process, forcing all flip-flops to their defined wake-up state. For PLB flip-flops, the wake-up state is always reset, regardless of the PLB flip-flop primitive used in the application. 

## **3.1.4. sysCLOCK Phase Locked Loops (PLLs)** 

The sysCLOCK PLLs provide the ability to synthesize clock frequencies. The iCE40 UltraPlus devices have one sysCLOCK PLL. REFERENCECLK is the reference frequency input to the PLL and its source can come from an external I/O pin, the internal Oscillator Generators from internal routing. EXTFEEDBACK is the feedback signal to the PLL which can come from internal routing or an external I/O pin. The feedback divider is used to multiply the reference frequency and thus synthesize a higher frequency clock output. 

The PLLOUT output has an output divider, thus allowing the PLL to generate different frequencies for each output. The output divider can have a value from 1 to 64 (in increments of 2X). The PLLOUT outputs can all be used to drive the iCE40 UltraPlus global clock network directly or general purpose routing resources can be used. 

The LOCK signal is asserted when the PLL determines it has achieved lock and de-asserted if a loss of lock is detected. A block diagram of the PLL is shown in Figure 3.3. 

The timing of the device registers can be optimized by programming a phase shift into the PLLOUT output clock which will advance or delay the output clock with reference to the REFERENCECLK clock. This phase shift can be either programmed during configuration or can be adjusted dynamically. In dynamic mode, the PLL may lose lock after a phase adjustment on the output used as the feedback source and not relock until the tLOCK parameter has been satisfied. For more details, refer to iCE40 sysCLOCK PLL Design and Usage Guide (FPGA-TN-02052). 

**==> picture [448 x 198] intentionally omitted <==**

**----- Start of picture text -----**<br>
RESET<br>BYPASS<br>BYPASS<br>GNDPLL VCCPLL<br>Phase<br>REFERENCECLK DIVR Detector RANGE Voltage  DIVQ<br>Input  Low-Pass  Controlled  VCO<br>Divider Filter Oscillator  Divider<br>(VCO)<br>SIMPLE<br>DIVF<br>PLLOUTCORE<br>Feedback Divider Fine Delay<br>Fine Delay Adjustment<br>Adjustment Shifter Phase  Output Port PLLOUTGLOBAL<br>Feedback<br>Feedback_Path<br>DYNAMICDELAY[7:0] LOCK<br>EXTFEEDBACK EXTERNAL<br>LATCHINPUTVALUE Low Power mode<br>(iCEgate enabled)<br>**----- End of picture text -----**<br>


**Figure 3.3. PLL Diagram** 

Table 3.3 provides signal descriptions of the PLL block. 

© 2018-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

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**iCE40 UltraPlus Family Data Sheet Data Sheet** 

**Table 3.3. PLL Signal Descriptions** 

|**Signal Name**|**Direction**|**Description**|
|---|---|---|
|REFERENCECLK|Input|Input reference clock|
|BYPASS|Input|The BYPASS control selects which clock signal connects to the PLLOUT output.<br>0 – PLL generated signal<br>1 – REFERENCECLK|
|EXTFEEDBACK|Input|External feedback input to PLL. Enabled when the FEEDBACK_PATH attribute is set<br>to EXTERNAL.|
|DYNAMICDELAY[7:0]|Input|Fine delay adjustment control inputs. Enabled when DELAY_ADJUSTMENT_MODE<br>is set to DYNAMIC.|
|LATCHINPUTVALUE|Input|When enabled, puts the PLL into low-power mode; PLL output is held static at the<br>last input clock value. Set ENABLE ICEGATE_PORTA and PORTB to ‘1’ to enable.|
|PLLOUTGLOBAL|Output|Output from the Phase-Locked Loop (PLL). Drives a global clock network on the<br>FPGA. The port has optimal connections to global clock buffers GBUF4 and GBUF5.|
|PLLOUTCORE|Output|Output clock generated by the PLL, drives regular FPGA routing. The frequency<br>generated on this output is the same as the frequency of the clock signal generated<br>on the PLLOUTLGOBALport.|
|LOCK|Output|When High, indicates that the PLL output is phase aligned or locked to the input<br>reference clock.|
|RESET|Input|Active low reset.|
|SCLK|Input|Input, Serial Clock used for re-programming PLL settings.|
|SDI|Input|Input, Serial Data used for re-programming PLL settings.|



## **3.1.5. sysMEM Embedded Block RAM Memory** 

Larger iCE40 UltraPlus device includes multiple high-speed synchronous sysMEM Embedded Block RAMs (EBRs), each 4 kbit in size. This memory can be used for a wide variety of purposes including data buffering and FIFO. 

## **sysMEM Memory Block** 

The sysMEM block can implement single port, pseudo dual port, or FIFO memories with programmable logic resources. Each block can be used in a variety of depths and widths as listed in Table 3.4. 

**Table 3.4. sysMEM Block Configurations** 

|**Block RAM**<br>**Configuration**|**Block RAM**<br>**Configuration**<br>**and Size**|**WADDR Port**<br>**Size (Bits)**|**WDATA Port**<br>**Size (Bits)**|**RADDR Port**<br>**Size (Bits)**|**RDATA Port**<br>**Size (Bits)**|**MASK Port**<br>**Size (Bits)**|
|---|---|---|---|---|---|---|
|SB_RAM256x16<br>SB_RAM256x16NR<br>SB_RAM256x16NW<br>SB_RAM256x16NRNW|256x16 (4 k)|8 [7:0]|16 [15:0]|8 [7:0]|16 [15:0]|16 [15:0]|
|SB_RAM512x8<br>SB_RAM512x8NR<br>SB_RAM512x8NW<br>SB_RAM512x8NRNW|512x8 (4 k)|9 [8:0]|8 [7:0]|9 [8:0]|8 [7:0]|No Mask Port|
|SB_RAM1024x4<br>SB_RAM1024x4NR<br>SB_RAM1024x4NW<br>SB_RAM1024x4NRNW|1024x4 (4 k)|10 [9:0]|4 [3:0]|10 [9:0]|4 [3:0]|No Mask Port|
|SB_RAM2048x2<br>SB_RAM2048x2NR<br>SB_RAM2048x2NW<br>SB_RAM2048x2NRNW|2048x2 (4 k)|11 [10:0]|2 [1:0]|11 [10:0]|2 [1:0]|No Mask Port|



**Note** : For iCE40 UltraPlus, the primitive name without “Nxx” uses rising-edge Read and Write clocks. “NR” uses rising-edge Write clock and falling-edge Read clock. “NW” uses falling-edge Write clock and rising-edge Read clock. “NRNW” uses failing-edge clocks on both Read and Write. 

© 2018-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

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**iCE40 UltraPlus Family Data Sheet Data Sheet** 

## **RAM Initialization and ROM Operation** 

If desired, the contents of the RAM can be pre-loaded during device configuration. 

By preloading the RAM block during the chip configuration cycle and disabling the write controls, the sysMEM block can also be utilized as a ROM. 

## **Memory Cascading** 

Larger and deeper blocks of RAM can be created using multiple EBR sysMEM Blocks. 

## **RAM4k Block** 

Figure 3.4 shows the 256x16 memory configurations and their input/output names. In all the sysMEM RAM modes, the input data and addresses for the ports are registered at the input of the memory array. 

**==> picture [230 x 174] intentionally omitted <==**

**----- Start of picture text -----**<br>
Write Port Read Port<br>>——.7<br>WDATA[15:0] RDATA[15:0]<br>MASK[15:0]<br>WADDR[7:0] RADDR[7:0]<br>RAM4K<br>RAM Block<br>WE RE<br>(256x16)<br>WCLKE RCLKE<br>WCLK RCLK<br>**----- End of picture text -----**<br>


**Figure 3.4. sysMEM Memory Primitives** 

Table 3.5 lists the EBR signals. 

**Table 3.5. EBR Signal Descriptions** 

|**Signal Name**|**Direction**|**Description**|
|---|---|---|
|WDATA[15:0]|Input|Write Data input.|
|MASK[15:0]|Input|Masks write operations for individual data bit-lines.<br>0 – Write bit<br>1 – Do not write bit|
|WADDR[7:0]|Input|Write Address input. Selects one of 256 possible RAM locations.|
|WE|Input|Write Enable input.|
|WCLKE|Input|Write Clock Enable input.|
|WCLK|Input|Write Clock input. Default rising-edge, but with falling-edge option.|
|RDATA[15:0]|Output|Read Data output.|
|RADDR[7:0]|Input|Read Address input. Selects one of 256 possible RAM locations.|
|RE|Input|Read Enable input.|
|RCLKE|Input|Read Clock Enable input.|
|RCLK|Input|Read Clock input. Default rising-edge, but with falling-edge option.|



For further information on the sysMEM EBR block, refer to Memory Usage Guide for iCE40 Devices (FPGA-TN-02002). 

© 2018-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

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**iCE40 UltraPlus Family Data Sheet Data Sheet** 

## **3.1.6. sysMEM Single Port RAM Memory (SPRAM)** 

The SPRAM block is implemented to be accessed only as single port. Each block of SPRAM is designed to be 16K x 16 (256 kbits) in size. See Figure 3.5. 

## **SPRAM Data Width** 

The SPRAM is designed with fixed 16-bit data width. However, the block contains nibble mask control on the write input that allows the user logic to operate the SPRAM as x4 or x8 with this control on the write side, and user logic to select which nibble/byte in the read side. 

## **SPRAM Initialization and ROM Operation** 

There is no pre-load into the SPRAM during device configuration, therefore, the SPRAM is not initialized after configuration. 

## **SPRAM Cascading** 

Deeper SPRAM can be created using multiple SPRAM blocks, up to four blocks (64K x 16) 

## **SPRAM Power Modes** 

There are three power modes in the SPRAM that the users can select during normal operation. This reduces the SPRAM block power when it Is not needed, allow lower power consumption in an always-on application. These modes are: 

- **Standby Mode** : SPRAM stops all activity, and SPRAM freezes in its current state. Memory contents are retained, memory outputs are retained, and all register contents are retained. 

- **Sleep Mode** : SPRAM block is shut down on all peripheral circuit, except the memory core. Memory contents are retained, memory outputs and register contents are clear and become unknown. 

- **Power Off Mode** : Power source to the SPRAM is disconnected. This is the lowest power state. Memory contents are lost. Memory outputs are unknown. 

**==> picture [378 x 214] intentionally omitted <==**

**----- Start of picture text -----**<br>
MASKWREN [3:0] ———=>| DATAOUT [15:0]<br>WREN ————=><br>MASKWREN [3:0]<br>WREN<br>Single Port RAM Primitive<br>SB_SPRAM256KA<br>CHIPSELECT<br>CLOCK<br>STANDBY<br>SLEEP<br>POWEROFFN<br>**----- End of picture text -----**<br>


**Figure 3.5. SPRAM Primitive** 

© 2018-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

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**iCE40 UltraPlus Family Data Sheet Data Sheet** 

**Table 3.6. SPRAM Signal Descriptions** 

|**Signal Name**|**Direction**|**Description**|
|---|---|---|
|ADDRESS[13:0]|Input|Address input|
|DATAIN[15:0]|Input|Write Data input|
|MASKWREN[3:0]|Input|Nibble WE control|
|WREN|Input|Write Enable|
|CHIPSELECT|Input|Enable SPRAM|
|CLOCK|Input|Clock input|
|STANDY|Input|Standby Mode|
|SLEEP|Input|Sleep Mode|
|POWEROFF|Input|Switch off power source to SPRAM|
|DATAOUT[15:0]|Output|Output Data|



For further information on sysMEM SPRAM block, refer to iCE40 SPRAM Usage Guide (FPGA-TN-02022). 

## **3.1.7. sysDSP** 

The iCE40 UltraPlus family provides an efficient sysDSP architecture that is very suitable for low-cost Digital Signal Processing (DSP) functions for mobile applications. Typical functions used in these applications are Multiply, Accumulate, and Multiply-Accumulate. The block can also be used for simple Add and Subtract functions. 

## **iCE40 UltraPlus sysDSP Architecture Features** 

The iCE40 UltraPlus sysDSP supports many functions that include the following: 

- Single 16-bit x 16-bit Multiplier, or two independent 8-bit x 8-bit Multipliers 

- Optional independent pipeline control on Input Register, Output Register, and Intermediate Reg faster clock performance 

- Single 32-bit Accumulator, or two independent 16-bit Accumulators 

- Single 32-bit, or two independent 16-bit Adder/Subtracter functions, registered or asynchronous 

- Cascadable to create wider Accumulator blocks 

Figure 3.6 shows the block diagram of the sysDSP block. The block consists of the Multiplier section with a bypassable Output register, Input Register, and Intermediate register between Multiplier and AC timing to achieve the highest performance. 

© 2018-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

18 

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**iCE40 UltraPlus Family Data Sheet Data Sheet** 

**==> picture [460 x 331] intentionally omitted <==**

**----- Start of picture text -----**<br>
Input Registers Multiplier SIGNEXTOUT COCAS CO Accumulator<br>Q[31:16]<br>OHADS<br>0 W<br>C [15:0] D Q 01 C 1 ± 0 P Q 0<br>CHLD HLDR C 0 16x16 Pipeline C 12 X 1 DHLDR Q 123 O[31:16]<br>[15:0] Registers 0 X[15] C 9 Hi<br>A[15:0]AHLD a DHLDR Q 01C 1 A A[15:8]B [15:8]A[7:0] 8x8 D R Q 010C 4 [15:0][15:0]FJ 8x8=16[7:0][15:8] + P [31:24] 16x16 C 10123 C 11 HCI , C 8 OHLDAOHRSTOHHLD<br>B [15:8] 8x8 DHLDR Q 1C 6 [15:8] [15:8] + P[23:16] RegisterPipeline0 16x16=32H [31:16]<br>IHRST C 22 8x8 PowerSave L D Q 1 LCO<br>A[15:8] 0 K[15:0] HLDR C 7 [15:0] LCOCA0 1<br>B [7:0] 8x8 DHLDR Q 1C 6 [7:0] [7:0] + P [15:8] Q[15:00 Y S OLADS<br>B [15:0]BHLD DHLDR Q 01C 2 B A[7:0]B [7:0] 8x8 D R Q 01C 5 [15:0]G [15:8][7:0]8x8=16 P [7:0] 1C 190 Z[15] Z ± 01 R DHLDR Q S 0123 C 16 O[15:0]Lo<br>1 C 15<br>2 OLRSTOLHLD<br>3 LCI OLLDA<br>0 D C 18<br>C 17<br>D[15:0] D Q 1<br>DHLD HLD<br>R C 3 ASGND=C23<br>BSGND=C24<br>ILRST<br>CLK 0 1<br>ENA<br>SIGNEXTIN CICAS CI<br>0 1<br>C 13<br>0 1 2 3 C 14<br>0 1<br>C 21<br>0 1 2 3 C 20<br>CSA<br>CSA<br>**----- End of picture text -----**<br>


**Figure 3.6. sysDSP Functional Block Diagram (16-bit x 16-bit Multiply-Accumulate)** 

**Table 3.7. Output Block Port Description** 

**Primitive Input/ Signal Width Function Default** ~~ee~~ **Port Name Output** CLK CLK 1 Input Clock Input. Applies to all clocked elements in the — ~~a~~ sysDSP block ENA CE 1 Input Clock Enable Input. Applies to all clocked elements 0 – Enabled in the sysDSP block. 0 – Not enabled 1 – Enabled ~~{tf Pe;~~ A[15:0] A[15:0] 16 Input Input to the A Register. Feeds the Multiplier or is a 16'b0 ~~a~~ direct input to the Adder Accumulator B[15:0] B[15:0] 16 Input Input to the B Register. Feeds the Multiplier or is a 16'b0 ~~I~~ direct input to the Adder Accumulator C[15:0] C[15:0] 16 Input Input to the C Register. It is a direct input to the 16'b0 Adder Accumulator ~~a~~ D[15:0] D[15:0] 16 Input Input to the D Register. It is a direct input to the 16'b0 Adder Accumulator ~~I~~ AHLD AHOLD 1 Input A Register Hold. 0 – Update 0 – Update 1 – Hold ~~a~~ BHLD BHOLD 1 Input B Register Hold. 0 – Update 0 – Update 1 – Hold ~~a~~ 

© 2018-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02008-1.9 

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**iCE40 UltraPlus Family Data Sheet Data Sheet** 

|**Signal**<br>~~ee~~|**Primitive**<br>**Port Name**<br>~~ee~~|**Width**<br>~~ee~~|**Input/**<br>**Output**<br>~~ee~~|**Function**<br>~~ee~~|**Default**<br>~~ee~~|
|---|---|---|---|---|---|
|CHLD<br>~~ee~~|CHOLD<br>~~ee~~|1<br>~~ee~~|Input<br>~~ee~~|C Register Hold.<br>0 – Update<br>1 – Hold<br>~~ee~~|0 – Update<br>~~ee~~|
|DHLD<br>~~ee~~|DHOLD<br>~~ee~~|1<br>~~ee~~|Input<br>~~ee~~|D Register Hold.<br>0 – Update<br>1 – Hold<br>~~ee~~|0 – Update<br>~~ee~~|
|IHRST|IRSTTOP|1|Input|Reset input to A and C input registers, and the<br>pipeline registers in the upper half of the Multiplier<br>Section.<br>0 – No reset<br>1 – Reset|0 – No reset|
|ILRST|IRSTBOT|1|Input|Reset input to B and D input registers, and the<br>pipeline registers in the lower half of the Multiplier<br>Section. It also resets the Multiplier result pipeline<br>register.<br>0 – No reset<br>1 – Reset|0 – No reset|
|O[31:0]|O[31:0]|32|Output|Output of the sysDSP block. This output can be:<br><br>O[31:0] – 32-bit result of 16x16 Multiplier or<br>MAC<br><br>O[31:16] – 16-bit result of 8x8 upper half<br>Multiplier or MAC<br>O[15:0] – 16-bit result of 8x8 lower half Multiplier<br>or MAC|—|
|OHHLD|OHOLDTOP|1|Input|High-order (upper half) Accumulator Register Hold.<br>0 – Update<br>1 – Hold|0 – Update|
|OHRST|ORSTTOP|1|Input|Reset input to high-order (upper half) bits of the<br>Accumulator Register.<br>0 – No reset<br>1 – Reset|0 – No reset|
|OHLDA|OLOADTOP|1|Input|High-order (upper half) Accumulator Register<br>Accumulate/Load control.<br>0 – Accumulate, register is loaded with<br>Adder/Subtracter results<br>1 – Load, register is loaded with Input C or C<br>Register|0 –<br>Accumulate|
|OHADS|ADDSUBTOP|1|Input|High-order (upper half) Accumulator Add or<br>Subtract select.<br>0 – Add<br>1 – Subtract|0 – Add|
|OLHLD|OHOLDBOT|1|Input|Low-order (lower half) Accumulator Register Hold.<br>0 – Update<br>1 – Hold|0 – Update|
|OLRST|ORSTBOT|1|Input|Reset input to Low-order (lower half) bits of the<br>Accumulator Register.<br>0 –No reset<br>1 – Reset|0 – No reset|



© 2018-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

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|**Signal**<br>~~a~~|**Primitive**<br>**Port Name**|**Width**|**Input/**<br>**Output**|**Function**|**Default**|
|---|---|---|---|---|---|
|OLLDA|OLOADBOT|1|Input|Low-order (lower half) Accumulator Register<br>Accumulate/Load control.<br>0 – Accumulate, register is loaded with<br>Adder/Subtracter results<br>1 – Load, register is loaded with Input C or C<br>Register|0 –<br>Accumulate|
|OLADS|ADDSUBBOT|1|Input|Low-order (lower half) Accumulator Add or<br>Subtract select.<br>0 – Add<br>1 – Subtract|0 – Add|
|CICAS<br>~~a ~~<br>~~pO~~|ACCUMCI<br> ~~a ee~~<br>~~pO~~|1<br>~~ee~~|Input<br>~~ee~~|Cascade Carry/Borrow input from previous sysDSP<br>block<br>~~ee~~|—<br>~~ee~~|
|CI<br>~~pO~~|CI<br>~~pO~~|1|Input|Carry/Borrow input from lower logic tile|—|
|COCAS<br>~~pO~~<br>~~eG~~<br>~~pO~~|ACCUMCO<br>~~pO~~<br>~~eG~~<br>|1<br>~~eG~~<br>|Output<br>~~GG~~<br>|Cascade Carry/Borrow output to next sysDSP block<br>~~GG~~<br>|—|
|CO<br>~~eG~~<br>~~pOeG~~|CO<br>~~eG~~<br>~~eG~~|1<br>~~eG ~~<br>~~eG~~|Output<br> ~~GG~~<br>~~GeO~~|Carry/Borrow output to higher logic tile<br>~~GG~~<br>~~GeO~~|—|
|SIGNEXTIN<br>~~pOeG~~<br>~~pO~~|SIGNEXTIN<br>~~eG~~<br>~~pO~~|1<br>~~eG~~|Input<br>~~GeO~~|Sign extension input fromprevious sysDSP block<br>~~GeO~~|—|
|SIGNEXTOUT<br>~~eG~~<br>~~pO~~|SIGNEXTOUT<br>~~eG~~<br>~~pO~~|1<br>~~eG ~~|Output<br> ~~GeO~~|Singextension output to next sysDSP block<br>~~GeO~~|—|



The iCE40 UltraPlus sysDSP can support the following functions: 

- 8-bit x 8-bit Multiplier 

- 16-bit x 16-bit Multiplier 

- 16-bit Adder/Subtracter 

- 32-bit Adder/Subtracter 

- 16-bit Accumulator 

- 32-bit Accumulator 

- 8-bit x 8-bit Multiply-Accumulate 

- 16-bit x 16-bit Multiply-Accumulate 

Figure 3.7 shows the path for an 8-bit x 8-bit Multiplier using the upper half of sysDSP block. 

© 2018-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02008-1.9 

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**iCE40 UltraPlus Family Data Sheet Data Sheet** 

**==> picture [475 x 311] intentionally omitted <==**

**----- Start of picture text -----**<br>
Input Registers Multiplier SIGNEXTOUT COCAS CO Accumulator<br>Q [31 :16 ]<br>OHADS<br>0 W<br>C[15CHLD:0 ] DHLDR Q 01C 0 C 16 x16 Pipeline  1C12 X ± 01 P DHLD R Q Q 0123 O [ 31 :16 ]<br>[ 15 :0 ] Registers 0 X [ 15 ] C 9 High<br>A[15AHLD:0 ] DHLDR Q 01C 1 A A[ 15B [ 15A[ 7 :0 ]:8 ]:8 ] 8 x8 D R Q 010C4 [[15:0 ]15:0 ]FJ 8 x8 =16[7:0][15:8] + P [ 31: 24] 16 x 16  C 10123 C 11 HCI C 8 OHLDAOHRSTOHHLD<br>IHRST B [ 15 :8 ] 8 x8 C 22 DHLD8 x8 PowerSaveR Q 1C6 [15:8] [15:8] + P [ 23: 16] L DPipeline RegisterQ 01 16 x16H=32 [ 31: 16 ] LCO<br>A[ 15 :8 ] 0 K[ 15: 0 ] HLDR C 7 [ 15: 0 ] LCOCAS0 1<br>B[ 7 :0 ] 8 x8 DHLDR Q 1C 6 [7:0] [7:0] + P [ 15: 8 ] Q [15:0]0 Y OLADS<br>B[15 :0 ] D Q 01 A[ 7 :0 ]B[ 7 :0 ] 8 x8 D R Q 01C 5 [ 15: 0 ]G [ 158 x8 = 16[7:0]:8 ] P [ 7: 0 ] 1C19 Z ± 01 R HLDD R Q S 0123 O [ 15 :0 ]<br>BHLD HLDR C 2 B bears  tt  teak 0 Z [15 ] C 16 Low<br>1 C 15<br>2 OLRSTOLHLD<br>3 LCI OLLDA<br>0 D C 17 C 18<br>D[15 :0 ] D Q 1<br>DHLD HLD<br>R C 3 ASGND=C23<br>BSGND=C24<br>ILRST<br>CLK 0 1<br>ENA<br>( 25 - FEB - 2012 )<br>SIGNEXTIN CICAS CI<br>0 1<br>C13<br>0 1 2 3 C14<br>0 1<br>C21<br>0 1 2 3 C20<br>CSA<br>CSA<br>**----- End of picture text -----**<br>


**Figure 3.7. sysDSP 8-bit x 8-bit Multiplier** 

Figure 3.8 shows the path for an 16-bit x 16-bit Multiplier using the upper half of sysDSP block. 

© 2018-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

22 

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**iCE40 UltraPlus Family Data Sheet Data Sheet** 

**==> picture [457 x 321] intentionally omitted <==**

**----- Start of picture text -----**<br>
Input Registers Multiplier SIGNEXTOUT COCAS CO Accumulator<br>Q[31:16]<br>OHADS<br>0 W<br>C[CHLD15:0] HLDD R Q 01C0 C 16x16 Pipeline  1C12 X ± 01 P DHLDR Q Q 0123 O[31:16]<br>[15:0] Registers 0 X[15] C9 High<br>A[AHLD15:0] HLDD R Q 01C1 A AB[[A1515[7:::880]]] 8x8 D R Q 010C4 [[ 1515FJ::00]] 8[[7x15:08:]8=]16 + P[31:24] 16x16  C12310 C11 HCI C8 OHRSTOHHLDOHLDA<br>B[15:8] 8x8 DHLDR Q 1C6 [15:8] [15:8] + P[23:16] Pipeline Register16x16=32 [31:16]<br>0 H<br>IHRST C22 8x8 PowerSave L D Q 1 LCO<br>A[15:8] 0 K[15:0] HLDR C7 [15:0] LCOCAS0 1<br>B[7:0] 8x8 DHLDR Q 1C6 [7:0] [7:0] + P[15:8] Q[150:0 Y OLADS<br>B[15:0] D Q 01 AB[[77::00]] 8x8 D R Q 01C5 [15G:0] [815[7x::880]]=16 P[7:0] 1C19 Z ± 01 R DHLDR Q S 0123 O[15:0]<br>BHLD HLDR C2 B 0 Z[15] C16 Low<br>1 C15<br>2 OLRSTOLHLD<br>3 LCI OLLDA<br>0 D C17 C18<br>D[15:0] D Q 1<br>DHLD HLDR C3 ASGND=23BSGND=24<br>ILRST<br>CLK 0 1<br>ENA<br>SIGNEXTIN CICAS CI (25-FEB-2012)<br>0 1<br>1C3<br>0 1 2 3 1C4<br>0 1<br>1C2<br>0 1 2 3 0C2<br>CSA<br>CSA<br>**----- End of picture text -----**<br>


**Figure 3.8. DSP 16-bit x 16-bit Multiplier** 

## **3.1.8. sysI/O Buffer Banks** 

iCE40 UltraPlus devices have up to three I/O banks with independent VCCIO rails. The configuration SPI interface signals are powered by SPI_VCCIO1. Refer to the Pin Information Summary table. 

## **Programmable I/O (PIO)** 

The programmable logic associated with an I/O is called a PIO. The individual PIOs are connected to their respective sysI/O buffers and pads. The PIOs are placed on the top and bottom of the devices. 

© 2018-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02008-1.9 

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**iCE40 UltraPlus Family Data Sheet Data Sheet** 

**==> picture [334 x 271] intentionally omitted <==**

**----- Start of picture text -----**<br>
VCCIO<br>I/O Bank 0 or 2<br>Voltage Supply<br>0 = Hi-Z<br>Enabled ‘1’<br>1 = Output<br>Disabled ‘0’       Enabled<br>fe)SSFe) 2 Pull-up<br>OE '<br>50 ns Delay Pull-up<br>50 ns Delay Enable<br> eeeLFOSC a 50 ns Filter OUTCLK [|<br>— 50 ns Filter '<br>i}<br>5 PLB Rows OUT i} PAD<br>en vi<br>OUTCLK Latch inhibits  t ‘ss0?“4<br>iCEGATE switching for  1 i) “ yy<br>HOLD HD power saving \i [an<br>I<br>< ¢ - 1 '<br>IN<br>t<br>256Kb ( ~ 4 Gxx pins optionally connect directly to<br>SPRAM > ' an associated GBUF global<br>INCLK buffer<br><<— .<br>**----- End of picture text -----**<br>


**Figure 3.9. I/O Bank and Programmable I/O Cell** 

The PIO contains three blocks: an input register block, output register block iCEGate™ and tri-state register block. To save power, the optional iCEGate™ latch can selectively freeze the state of individual, non-registered inputs within an I/O bank. Note that the freeze signal is common to the bank. These blocks can operate in a variety of modes along with the necessary clock and selection logic. 

## **Input Register Block** 

The input register blocks for the PIOs on all edges contain registers that can be used to condition high-speed interface signals before they are passed to the device core. 

## **Output Register Block** 

The output register block can optionally register signals from the core of the device before they are passed to the sysI/O buffers. 

Figure 3.10 shows the input/output register block for the PIOs. 

© 2018-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

24 

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**iCE40 UltraPlus Family Data Sheet Data Sheet** 

**==> picture [334 x 420] intentionally omitted <==**

**----- Start of picture text -----**<br>
CLOCK_ENABLE PIO Pair<br>OUTPUT_CLK<br>INPUT_CLK<br>(1,0)<br>LATCH_INPUT_VALUE<br>D_IN_1<br>D_IN_0 ai.<br>Pad<br>D_OUT_1<br>D_OUT_0<br>(1,0)<br>0<br>1<br>OUTPUT_ENABLE = ——},_ , .<br>(1,0)<br>LATCH_INPUT_VALUE<br>D_IN_1<br>Ez,<br>D_IN_0 rh.<br>Pad<br>D_OUT_1<br>D_OUT_0<br>(1,0)<br>0<br>1<br>OUTPUT_ENABLE<br>= Statically defined by configuration program.<br>**----- End of picture text -----**<br>


**Figure 3.10. iCE I/O Register Block Diagram** 

**Table 3.8. PIO Signal List** 

|**Pin Name**|**I/O Type**|**Description**|
|---|---|---|
|OUTPUT_CLK|Input|Output register clock|
|CLOCK_ENABLE|Input|Clock enable|
|INPUT_CLK|Input|Input register clock|
|OUTPUT_ENABLE|Input|Output enable|
|D_OUT_0/1|Input|Data from the core|
|D_IN_0/1|Output|Data to the core|
|LATCH_INPUT_VALUE|Input|Latches/holds the Input Value|



© 2018-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

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**iCE40 UltraPlus Family Data Sheet Data Sheet** 

## **3.1.9. sysI/O Buffer** 

Each I/O is associated with a flexible buffer referred to as a sysI/O buffer. These buffers are arranged around the periphery of the device in groups referred to as banks. The sysI/O buffers allow users to implement a wide variety of standards that are found in today’s systems with LVCMOS interfaces. 

## **Typical I/O Behavior During Power-up** 

The internal power-on-reset (POR) signal is deactivated when VCC, SPI_VCCIO1 and VPP_2V5 reach the level defined in Table 4.4. After the POR signal is deactivated, the FPGA core logic becomes active. You must ensure that all VCCIO banks are active with valid input logic levels to properly control the output logic states of all the I/O banks that are critical to the application. The default configuration of the I/O pins in a device prior to configuration is tri-stated with a weak pull-up to VCCIO. The I/O pins maintain the pre-configuration state until VCC, SPI_VCCIO1 and VPP_2V5 reach the defined levels. The I/Os take on the software user-configured settings only after POR signal is deactivated and the device performs a proper download/configuration. Unused I/Os are automatically blocked and the pull-up termination is disabled. 

## **Supported Standards** 

The iCE40 UltraPlus sysI/O buffer supports both single-ended input/output standards, and used as differential comparators. The buffer supports the LVCMOS 1.8 V, 2.5 V, and 3.3 V standards. The buffer has individually configurable options for bus maintenance (weak pull-up or none). 

Table 3.9 and Table 3.10 show the I/O standards (together with their supply and reference voltages) supported by the iCE40 UltraPlus devices. 

## **Differential Comparators** 

The iCE40 UltraPlus devices provide differential comparator on pairs of I/O pins. These comparators are useful in some mobile applications. See the Pin Information Summary section to locate the corresponding paired I/Os with differential comparators. 

## **Table 3.9. Supported Input Standards** 

|**I/O Standard**|**VCCIO(Typical)**|**VCCIO(Typical)**|**VCCIO(Typical)**|
|---|---|---|---|
||**3.3 V**|**2.5 V**|**1.8 V**|
|**Single-Ended Interfaces**||||
|LVCMOS33|Yes|—|—|
|LVCMOS25|—|Yes|—|
|LVCMOS18|—|—|Yes|



**Table 3.10. Supported Output Standards** 

|**I/O Standard**|**VCCIO(Typical)**|
|---|---|
|**Single-Ended Interfaces**||
|LVCMOS33|3.3 V|
|LVCMOS25|2.5 V|
|LVCMOS18|1.8 V|



## **3.1.10. On-Chip Oscillator** 

The iCE40 UltraPlus devices feature two different frequency Oscillator. One is tailored for low-power operation that runs at low frequency (LFOSC). Both Oscillators are controlled with internally generated current. 

The LFOSC runs at nominal frequency of 10 kHz. The high frequency oscillator (HFOSC) runs at a nominal frequency of 48 MHz, divisible to 24 MHz, 12 MHz, or 6 MHz by user option. The LFOSC can be used to perform all always-on functions, with the lowest power possible. The HFOSC can be enabled when the always-on functions detect a condition that would need to wake up the system to perform higher frequency functions. 

© 2018-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

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**iCE40 UltraPlus Family Data Sheet Data Sheet** 

## **3.1.11. User I[2] C IP** 

The iCE40 UltraPlus devices have two I[2] C IP cores. Either of the two cores can be configured either as an I[2] C master or as an I[2] C slave. The pins for the I[2] C interface are not pre-assigned. User can use any General Purpose I/O pins. 

In each of the two cores, there are options to delay the either the input or the output, or both, by 50 ns nominal, using dedicated on-chip delay elements. This provides an easier interface with any external I[2] C components. 

When the IP core is configured as master, it will be able to control other devices on the I[2] C bus through the preassigned pin interface. When the core is configured as the slave, the device will be able to provide I/O expansion to an I[2] C Master. The I[2] C cores support the following functionality: 

- Master and Slave operation 

- 7-bit and 10-bit addressing 

- Multi-master arbitration support 

- Clock stretching 

- Up to 400 kHz data transfer speed 

- General Call support 

- Optionally delaying input or output data, or both 

- Optional filter on SCL input 

For further information on the User I[2] C, refer to iCE40 SPI/I2C Hardened IP Usage Guide (FPGA-TN-02011). 

## **3.1.12. User SPI IP** 

The iCE40 UltraPlus devices have two SPI IP cores. The pins for the SPI interface are not pre-assigned. User can use any General Purpose I/O pins. Both SPI IP cores can be configured as a SPI master or as a slave. When the SPI IP core is configured as a master, it controls the other SPI enabled devices connected to the SPI Bus. When SPI IP core is configured as a slave, the device will be able to interface to an external SPI master. 

The SPI IP core supports the following functions: 

- Configurable Master and Slave modes 

- Full-Duplex data transfer 

- Mode fault error flag with CPU interrupt capability 

- Double-buffered data register 

- Serial clock with programmable polarity and phase 

- LSB First or MSB First Data Transfer 

For further information on the User SPI, refer to iCE40 SPI/I2C Hardened IP Usage Guide (FPGA-TN-02011). 

## **3.1.13. RGB High Current Drive I/O Pins** 

The iCE40 UltraPlus family devices offer multiple high current LED drive outputs in each device in the family to allow the iCE40 UltraPlus product to drive LED signals directly on mobile applications. 

There are three outputs on each device that can sink up to 24 mA current. These outputs are open-drain outputs, and provides sinking current to an LED connecting to the positive supply. These three outputs are designed to drive the RBG LEDs, such as the service LED found in a lot of mobile devices. This RGB drive current is user programmable from 4 mA to 24 mA, in increments of 4 mA. This output functions as General Purpose I/O with open-drain when the high current drive is not needed. 

## **3.1.14. RGB PWM IP** 

To provide an easier usage of the RGB high current drivers to drive RGB LED, a Pulse-Width Modulator IP can be used in the user design. This PWM IP provides the flexibility for user to dynamically change the modulation width of each of the RGB LED driver, which changes the color.  Also, the user can dynamically change the settings on the ON-time duration, OFF-time duration, and ability to turn the LED lights on and off gradually with user set breath-on and breathoff time. 

For additional information on the PWM IP, refer to iCE40 LED Driver Usage Guide (FPGA-TN-02021). 

© 2018-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02008-1.9 

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**iCE40 UltraPlus Family Data Sheet Data Sheet** 

## **3.1.15. Non-Volatile Configuration Memory** 

All iCE40 UltraPlus devices provide a Non-Volatile Configuration Memory (NVCM) block which can be used to configure the device. 

For more information on the NVCM, refer to iCE40 Programming and Configuration (FPGA-TN-02001). 

## **3.2. iCE40 UltraPlus Programming and Configuration** 

This section describes the programming and configuration of the iCE40 UltraPlus family. 

## **3.2.1. Device Programming** 

The NVCM memory can be programmed through the SPI port. The SPI port is located in Bank 1, using SPI_VCCIO1 power supply. 

## **3.2.2. Device Configuration** 

There are various ways to configure the Configuration RAM (CRAM), using SPI port, including: 

- From a SPI Flash (Master SPI mode) 

- System microprocessor to drive a Serial Slave SPI port (SSPI mode) 

For more details on configuring the iCE40 UltraPlus, refer to iCE40 Programming and Configuration (FPGA-TN-02001) 

## **3.2.3. Power Saving Options** 

The iCE40 UltraPlus devices feature iCEGate and PLL low power mode to allow users to meet the static and dynamic power requirements of their applications. Table 3.11 describes the function of these features. 

**Table 3.11. iCE40 UltraPlus Power Saving Features Description** 

|**Device Subsystem**|**Feature Description**|
|---|---|
|PLL|When LATCHINPUTVALUE is enabled, puts the PLL into low-power mode; PLL output held static at last<br>input clock value.|
|iCEGate|To save power, the optional iCEGate latch can selectively freeze the state of individual, non-registered<br>inputs within an I/O bank. Registered inputs are effectively frozen by their associated clock or clock-<br>enable control.|



© 2018-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

28 

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**iCE40 UltraPlus Family Data Sheet Data Sheet** 

## **4. DC and Switching Characteristics** 

## **4.1. Absolute Maximum Ratings** 

**Table 4.1. Absolute Maximum Ratings** 

|**Parameter**|**Min**|**Max**|**Unit**|
|---|---|---|---|
|Supply Voltage VCC|–0.5|1.42|V|
|Output Supply Voltage VCCIO|–0.5|3.60|V|
|NVCM Supply Voltage VPP_2V5|–0.5|3.60|V|
|PLL Supply Voltage VCCPLL|–0.5|1.42|V|
|I/O Tri-state Voltage Applied|–0.5|3.60|V|
|Dedicated Input Voltage Applied|–0.5|3.60|V|
|Storage Temperature (Ambient)|–65|150|°C|
|Junction Temperature (TJ)|–65|125|°C|



**Notes** : 

- Stress above those listed under the _Absolute Maximum Ratings_ may cause permanent damage to the device. Functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. 

- Compliance with the Thermal Management document is required. 

- All voltages referenced to GND. 

## **4.2. Recommended Operating Conditions** 

**Table 4.2. Recommended Operating Conditions** 

|**Symbol**<br>~~a ~~|**Parameter**<br> ~~C(O~~|**Parameter**<br> ~~C(O~~|**Min**<br>~~C(O~~|**Max**<br>~~C(O~~|**Unit**<br>~~C(O~~|
|---|---|---|---|---|---|
|VCC<br>1<br>~~a GO~~|Core Supply Voltage<br>~~GO~~||1.14<br>~~GO~~|1.26<br>~~GO~~|V<br>~~GO~~|
|VPP_2V5|VPP_2V5NVCM<br>Programming and<br>Operating Supply Voltage|Slave SPI Configuration<br>~~a~~|1.714|3.46|V|
|||Master SPI Configuration<br>~~a~~<br>~~es~~|2.30<br>~~es~~|3.46<br>~~es~~|V<br>~~es~~|
|||Configuration from NVCM<br>~~es~~|2.30<br>~~es~~|3.46<br>~~es~~|V<br>~~es~~|
|||NVCM Programming<br>~~es~~|2.30<br>~~es~~|3.00<br>~~es~~|V<br>~~es~~|
|VCCIO1, 2, 3<br>~~a~~|I/O Driver SupplyVoltage|VCCIO_0, SPI_VCCIO1, VCCIO_2<br>~~es~~|1.71<br>~~es~~|3.46<br>~~es~~|V<br>~~es~~|
|VCCPLL<br>~~a~~<br>~~a~~|PLL SupplyVoltage||1.14|1.26|V|
|tJCOM<br>~~a~~|Junction Temperature Commercial Operation||0|85|°C|
|tJIND<br>~~a~~|Junction Temperature, Industrial Operation<br>||–40<br>|100<br>|°C<br>|
|tPROG<br>~~eG~~|Junction Temperature NVCM Programming<br>~~eG~~||10.00<br>~~eG~~|30.00<br>~~eG~~|°C<br>~~eG~~|



## **Notes** : 

1. Like power supplies must be tied together if they are at the same supply voltage and they meet the power up sequence requirement. See the Power-up Supply Sequence section. VCC and VCCPLL are recommended to be tied together to the same supply with an RC-based noise filter between them. Refer to iCE40 Hardware Checklist (FPGA-TN-02006). 

2. See recommended voltages by I/O standard in subsequent table. 

3. VCCIO pins of unused I/O banks should be connected to the VCC power supply on boards. 

4. VPP_2V5 can, optionally, be connected to a 1.8 V (+/–5%) power supply in Slave SPI Configuration modes subject to the condition that none of the HFOSC/LFOSC and RGB LED driver features are used. Otherwise, VPP_2V5 must be connected to a power supply with a minimum 2.30 V level. 

© 2018-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02008-1.9 

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**iCE40 UltraPlus Family Data Sheet Data Sheet** 

## **4.3. Power Supply Ramp Rates** 

## **Table 4.3. Power Supply Ramp Rates** 

|**Symbol**|**Parameter**|**Min**|**Max**|**Unit**|
|---|---|---|---|---|
|tRAMP|Power supply ramp rates for all power supplies|0.6|10|V/ms|



**Notes** : 

- Assumes monotonic ramp rates. 

- Power up sequence must be followed. See the Power-up Supply Sequence section below. 

## **4.4. Power-On Reset** 

All iCE40 UltraPlus devices have on-chip Power-On-Reset (POR) circuitry to ensure proper initialization of the device. Only three supply rails are monitored by the POR circuitry as follows: (1) VCC, (2) SPI_VCCIO1 and (3) VPP_2V5. All other supply pins have no effect on the power-on reset feature of the device. Note that all supply voltage pins must be connected to power supplies for normal operation (including device configuration). 

## **4.5. Power-up Supply Sequence** 

It is recommended to bring up the power supplies in the following order. Note that there is no specified timing delay between the power supplies, however, there is a requirement for each supply to reach a level of 0.5 V, or higher, before any subsequent power supplies in the sequence are applied. 

1. **VCC** and **VCCPLL** should be the first two supplies to be applied. Note that these two supplies can be tied together subject to the recommendation to include a RC-based noise filter on the VCCPLL. Refer to iCE40 Hardware Checklist (FPGA-TN-02006). 

2. **SPI_VCCIO1** should be the next supply, and can be applied any time after the previous supplies (VCC and VCCPLL) have reached as level of 0.5 V or higher. 

3. **VPP_2V5** should be the next supply, and can be applied any time after previous supplies (VCC, VCCPLL and SPI_VCCIO1) have reached a level of 0.5 V or higher. 

4. **Other Supplies** (VCCIO0 and VCCIO2) do not affect device power-up functionality, and they can be applied any time after the initial power supplies (VCC and VCCPLL) have reached a level of 0.5 V or greater. There is no power down sequence required. However, when partial power supplies are powered down, it is required the above sequence to be followed when these supplies are re-powered up again. 

## **4.6. External Reset** 

When all power supplies have reached their minimum operating voltage defined in Table 4.2, it is required to either keep CRESET_B LOW, or toggle CRESET_B from HIGH to LOW, for a duration of tCRESET_B, and release it to go HIGH, to start configuration download from either the internal NVCM or the external Flash memory. Figure 4.1 shows Power-Up sequence when SPI_VCCIO1 and VPP_2V5 are not connected together, and the CRESET_B signal triggers configuration download. Figure 4.2 shows when SPI_VCCIO1 and VPP_2V5 connected together. All power supplies should be powered up during configuration. Before and during configuration, the I/Os are held in tri-state. I/Os are released to user functionality once the device has finished configuration. 

© 2018-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

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**Figure 4.1. Power Up Sequence with SPE_VCCIO1 and VPP_2V5 Not Connected Together** 

**Figure 4.2. Power Up Sequence with All Supplies Connected Together to 1.8 V** 

## **4.7. Power-On-Reset Voltage Levels** 

**Table 4.4. Power-On-Reset Voltage Levels** 

|**Symbol**|**Parameter**|**Parameter**|**Min**|**Max**|**Unit**|
|---|---|---|---|---|---|
|VPORUP|Power-On-Reset ramp up trip point (circuit<br>monitoring VCC, SPI_VCCIO1, andVPP_2V5)|VCC|0.62|0.92|V|
|||SPI_VCCIO1|0.87|1.50|V|
|||VPP_2V5|0.90|1.53|V|
|VPORDN|Power-On-Reset ramp down trip point (circuit<br>monitoring VCC, SPI_VCCIO1, andVPP_2V5)|VCC|—|0.79|V|
|||SPI_VCCIO1|—|1.50|V|
|||VPP_2V5|—|1.53|V|



**Note** : These POR trip points are only provided for guidance. Device operation is only characterized for power supply voltages specified under recommended operating conditions. 

## **4.8. ESD Performance** 

Please contact Lattice Semiconductor for additional information. 

© 2018-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

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## **4.9. DC Electrical Characteristics** 

Over recommended operating conditions. 

**Table 4.5. DC Electrical Characteristics** 

|**Symbol**<br>**Parameter**<br>**Condition**<br>**Min**<br>**Typ**<br>**Max**<br>**Unit**<br>~~GG~~|
|---|
|IIL, IIH1, 3, 4<br>Input or I/O Leakage<br>0 V < VIN< VCCIO+ 0.2 V<br>—<br>—<br>±10<br>µA|
|C1<br>I/O Capacitance, excluding<br>LED Drivers2<br>VCCIO= 3.3 V, 2.5 V, 1.8 V<br>VCC= Typ, VIO= 0 to VCCIO + 0.2 V<br>—<br>6<br>—<br>pf<br>~~ee~~|
|C2<br>Global Input Buffer<br>Capacitance2<br>VCCIO= 3.3 V, 2.5 V, 1.8 V<br>VCC= Typ, VIO= 0 to VCCIO + 0.2 V<br>—<br>6<br>—<br>pf|
|C3<br>RGB Pin Capacitance2<br>VCC= Typ, VIO= 0 to 3.5 V<br>—<br>15<br>—<br>pf<br>C4<br>IRLED Pin Capacitance2<br>VCC= Typ, VIO= 0 to 3.5 V<br>—<br>53<br>—<br>pf<br>VHYST<br>Input Hysteresis<br>VCCIO= 1.8 V, 2.5 V, 3.3 V<br>—<br>200<br>—<br>mV<br>~~Ge~~<br>~~Ge~~<br>~~GO~~<br>~~GC~~|
|VCCIO= 1.8 V, 0 ≤ VIN≤ 0.65 * VCCIO<br>−3<br>—<br>−31<br>µA<br>~~po~~|
|IPU<br>Internal PIO Pull-up Current<br>VCCIO= 2.5 V, 0 ≤ VIN≤ 0.65 * VCCIO<br>−8<br>—<br>−72<br>µA<br>~~po~~|
|VCCIO= 3.3 V, 0 ≤ VIN≤ 0.65 * VCCIO<br>−11<br>—<br>−128<br>µA<br>~~po~~|
|**Notes:**|
|1.<br>Input or I/O leakage current is measured with the pin configured as an input or as an I/O with the output driver tri-stated. It is|
|not measured with the output driver active. Internal pull-up resistors are disabled.|
|2.<br>TJ25oC, f = 1.0 MHz.|
|3.<br>Refer to VILand VIHinTable 4.13.|
|4.<br>Input pins are clamped to VCCIOand GND by a diode.  When input is higher than VCCIOor lower than GND, the Input Leakage|
|current will be higher than the IILand IIH.|
|**4.10. Supply Current**|
|**Table 4.6. Supply Current**|
|**Symbol**<br>**Parameter**<br>**Typ**<br>**VCC =1.2 V**<br>**Unit**|
|ICCSTDBY<br>Core Power Supply Static Current<br>75<br>µA|
|IPP2V5STDBY<br>VPP_2V5Power Supply Static Current<br>0.55<br>µA|
|ISPI_VCCIO1STDBY<br>SPI_VCCIO1Power Supply Static Current<br>0.5<br>µA|
|ICCIOSTDBY<br>VCCIOPower Supply Static Current<br>0.5<br>µA|
|ICCPEAK<br>Core Power Supply Startup Peak Current<br>12<br>mA|
|IPP_2V5PEAK<br>VPP_2V5Power Supply Startup Peak Current<br>2.5<br>mA|
|ISPI_VCCIO1PEAK<br>SPI_VCCIO1Power Supply Startup Peak Current<br>9.0<br>mA|
|ICCIOPEAK<br>VCCIOPower Supply Startup Peak Current<br>2.0<br>mA|



## **Notes:** 

1. Input or I/O leakage current is measured with the pin configured as an input or as an I/O with the output driver tri-stated. It is not measured with the output driver active. Internal pull-up resistors are disabled. 

2. TJ 25[o] C, f = 1.0 MHz. 

3. Refer to VIL and VIH in Table 4.13. 

4. Input pins are clamped to VCCIO and GND by a diode.  When input is higher than VCCIO or lower than GND, the Input Leakage current will be higher than the IIL and IIH. 

## **4.10. Supply Current** 

**Table 4.6. Supply Current** 

## **Notes** : 

- Assumes blank pattern with the following characteristics: all outputs are tri-stated, all inputs are configured as LVCMOS and held at VCCIO or GND, on-chip PLL is off. For more detail with your specific design, use the Power Calculator tool. Power specified with master SPI configuration mode. Other modes may be up to 25% higher. 

- Frequency = 0 MHz. 

- TJ = 25 °C, power supplies at nominal voltage, on devices processed in nominal process conditions. 

- Does not include pull-up. 

- Startup Peak Currents are measured with decoupling capacitances of 0.1 uF, 10 nF, and 1 nF to the power supply.  Higher decoupling capacitance causes higher current. 

© 2018-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

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## **4.11. User I[2] C Specifications** 

**Table 4.7. User I[2] C Specifications** 

|**Symbol**|**Parameter**|**Spec (STD Mode)**|**Spec (STD Mode)**|**Spec (STD Mode)**|**Spec (FAST Mode)**|**Spec (FAST Mode)**|**Spec (FAST Mode)**|**Unit**|
|---|---|---|---|---|---|---|---|---|
|||**Min**|**Typ**|**Max**|**Min**|**Typ**|**Max**||
|fSCL|Maximum SCL clock frequency|—|—|100|—|—|400|kHz|
|tHI|SCL clock HIGH Time|4|—|—|0.6|—|—|µs|
|tLO|SCL clock LOW Time|4.7|—|—|1.3|—|—|µs|
|tSU,DAT|Setup time (DATA)|250|—|—|100|—|—|ns|
|tHD,DAT|Hold time (DATA)|0|—|—|0|—|—|ns|
|tSU,STA|Setup time (START condition)|4.7|—|—|0.6|—|—|µs|
|tHD,STA|Hold time (START condition)|4|—|—|0.6|—|—|µs|
|tSU,STO|Setup time (STOP condition)|4|—|—|0.6|—|—|µs|
|tBUF|Bus free time between STOP and START|4.7|—|—|1.3|—|—|µs|
|tCO,DAT|SCL LOW to DATAOUT valid|—|—|3.4|—|—|0.9|µs|



## **4.12. I[2] C 50 ns Delay** 

**Table 4.8. I[2] C 50 ns Delay** 

|**Symbol**<br>~~————————————~~|**Parameter**<br>~~————————————~~|**Spec**<br>~~————————————~~|**Spec**<br>~~————————————~~|**Spec**<br>~~————————————~~|**Unit**<br>~~————————————~~|
|---|---|---|---|---|---|
|||**Min**<br>~~————————————~~|**Typ**<br>~~————————————~~|**Max**<br>~~————————————~~||
|TDELAY<br>~~————————————~~|Delay through 50 ns Delay Block<br>~~————————————~~|—<br>~~————————————~~|50<br>~~————————————~~|—<br>~~————————————~~|ns<br>~~————————————~~|



## **4.13. I[2] C 50 ns Filter** 

**Table 4.9. I[2] C 50 ns Filter** 

|**Symbol**|**Parameter**|**Spec**|**Spec**|**Spec**|**Unit**|
|---|---|---|---|---|---|
|||**Min**|**Typ**|**Max**||
|TFILTER-H|HIGH Pulse Filter through 50 ns Filter Block|—|50|—|ns|
|TFILTER-L|LOW Pulse Filter through 50 ns Filter Block|—|50|—|ns|



## **4.14. User SPI Specifications** 

|**Table 4.10. User SPI Specifications**<br>**Symbol**<br>**Parameter**<br>**Min**<br>**Typ**<br>**Max**<br>**Unit**<br>fMAX<br>Maximum SCK clock frequency<br>—<br>—<br>45<br>MHz<br>~~—————~~|
|---|
|**Notes**:|



- All setup and hold time parameters on external SPI interface are design-specific and, therefore, generated by the Lattice Design Software too.  These parameters include the following: 

   - tSUmaster master Setup Time (master mode) 

   - tHOLDmaster master Hold time (master mode) 

   - tSUslave slave Setup Time (slave mode) 

   - tHOLDslave slave Hold time (slave mode) 

   - tSCK2OUT SCK to Out Delay (slave mode) 

- The SCLK duty cycle needs to be specified in the Lattice Design Software as a timing constraint in order to ensure proper timing check on SCLK HIGH and LOW (tHI, tLO) time. 

© 2018-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

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**iCE40 UltraPlus Family Data Sheet Data Sheet** 

## **4.15. Internal Oscillators (HFOSC, LFOSC)** 

|**Parameter**<br>~~$<~~|**Parameter**<br>~~$<~~|**Parameter Description**<br>~~$<~~|**Spec/Recommended**<br>~~BeOOO~~|**Spec/Recommended**<br>~~BeOOO~~|**Spec/Recommended**<br>~~BeOOO~~|**Unit**<br>~~OOO~~|
|---|---|---|---|---|---|---|
|**Symbol**<br>~~$<~~|**Conditions**<br>~~$<~~||**Min**<br>~~Be~~|**Typ**<br>~~OOO~~|**Max**<br>~~OOO~~||
|fCLKHF<br>~~$<~~<br>~~|~~|Commercial Temp<br>~~$<~~<br>~~a|~~|HFOSC clock frequency (tJ= 0°C–85°C)<br>~~$<~~<br>~~|~~|–10%<br>~~Be ~~<br>~~|~~|48<br> ~~OOO~~<br>~~|~~|10%<br>~~OOO~~<br>~~|~~|MHz<br>~~OOO~~<br>~~|~~|
||Industrial Temp<br>~~|~~|HFOSC clock frequency (tJ= –40°C–100°C)<br>~~|~~|–20%<br>~~|~~|48<br>~~|~~|20%<br>~~|~~|MHz<br>~~|~~|
|fCLKLF<br>~~|~~<br>~~GG~~<br>~~ee~~|—<br>~~|~~<br>~~GG~~|LFOSC CLKK clock frequency<br>~~|~~<br>~~GG~~<br>~~_~~|–10%<br>~~|~~<br>~~GG~~|10<br>~~|~~<br>~~GG~~|10%<br>~~|~~<br>~~GG~~|kHz<br>~~|~~<br>~~GG~~|
|DCHCLKHF<br>~~ee~~<br>~~Ce~~|Commercial Temp|HFOSC Duty Cycle (tJ= 0°C–85°C)<br>~~_~~|45|50|55|%|
||Industrial Temp<br>~~Ce~~|HFOSC Duty Cycle (tJ= –40°C–100°C)<br>~~_~~<br>~~Ge~~|40|50|60|%|
|DCHCLKLF<br>~~ee~~<br>~~Ce~~|—<br>~~Ce~~|LFOSC Duty Cycle (Clock High Period)<br>~~_~~<br>~~Ge~~|45|50|55|%|
|Tsync_on<br>~~Ce~~<br>~~GO~~|—<br>~~Ce~~<br>~~GO~~|Oscillator output synchronizer delay<br>~~Ge~~<br>~~GO~~|—<br>~~GO~~|—<br>~~GO~~|5<br>~~GO~~|Cycles<br>~~GO~~|
|Tsync_off<br>~~GO~~<br>~~a~~|—<br>~~GO~~<br>~~a ~~|Oscillator output disable delay<br>~~GO~~<br> ~~GG~~|—<br>~~GO~~<br>~~GG~~|—<br>~~GO~~<br>~~GG~~|5<br>~~GO~~<br>~~GG~~|Cycles<br>~~GO~~<br>~~GG~~|



**Note** : Glitchless enabling and disabling OSC clock outputs. 

## **4.16. sysI/O Recommended Operating Conditions** 

**Table 4.12. sysI/O Recommended Operating Conditions** 

|**Standard**|**VCCIO (V)**|**VCCIO (V)**|**VCCIO (V)**|
|---|---|---|---|
||**Min**|**Typ**|**Max**|
|LVCMOS 3.3|3.14|3.3|3.46|
|LVCMOS 2.5|2.37|2.5|2.62|
|LVCMOS 1.8|1.71|1.8|1.89|



## **4.17. sysI/O Single-Ended DC Electrical Characteristics** 

**Table 4.13. sysI/O Single-Ended DC Electrical Characteristics** 

|**Input/Output**<br>**Standard**<br>~~p~~<br>~~eee~~|**VIL**<br>~~ee~~<br>~~pee~~|**VIL**<br>~~ee~~<br>~~pee~~|**VIH**<br>~~ee~~<br>~~ee~~|**VIH**<br>~~ee~~<br>~~ee~~|**VOL Max**<br>**(V)**<br>~~ee~~|**VOH Min**<br>**(V)**<br>~~ee~~<br>~~eee~~|**IOL**<br>**(mA)**<br>~~ee~~<br>~~eee~~|**IOH Max**<br>**(mA)**<br>~~ee~~<br>~~eee~~|
|---|---|---|---|---|---|---|---|---|
||**Min (V)**<br>~~p~~<br>~~eee~~|**Max (V)**<br>~~pee~~<br>~~eee~~|**Min (V)**<br>~~ee~~<br>~~eee~~|**Max (V)**<br>~~ee~~<br>~~eee~~|||||
|LVCMOS 3.3<br>~~p~~<br>~~eee~~<br>~~a~~|–0.3<br>~~p~~<br>~~eee~~<br>|0.8<br>~~pee~~<br>~~eee~~<br>|2.0<br>~~ee~~<br>~~eee~~<br>|VCCIO+0.2 V<br>~~ee~~<br>~~eee~~<br>|0.4<br>~~ee~~|VCCIO− 0.4<br>~~ee~~<br>~~eee~~|8<br>~~ee~~<br>~~eee~~|–8<br>~~ee~~<br>~~eee~~|
||||||0.2<br>~~ee~~<br>|VCCIO− 0.2<br>~~eee~~<br>~~ee~~<br>|0.1<br>~~eee~~<br>~~ee~~<br>|–0.1<br>~~eee~~<br>~~ee~~<br>|
|LVCMOS 2.5<br>~~eee~~<br>~~a eee~~|–0.3<br>~~eee~~<br>~~eee~~|0.7<br>~~eee~~<br>~~eee~~|1.7<br>~~eee~~<br>~~eee~~|VCCIO+0.2 V<br>~~eee~~<br>~~eee~~|0.4<br>~~ee~~<br>~~eee~~|VCCIO− 0.4<br>~~eee~~<br>~~ee~~<br>~~eee~~|6<br>~~eee~~<br>~~ee~~<br>~~eee~~|–6<br>~~eee~~<br>~~ee~~<br>~~eee~~|
||||||0.2<br>~~ee~~<br>~~eee~~|VCCIO− 0.2<br>~~ee~~<br>~~eee~~|0.1<br>~~ee~~<br>~~eee~~<br>~~ye~~|–0.1<br>~~ee~~<br>~~eee~~<br>~~ye~~|
|LVCMOS 1.8<br>~~ep~~|–0.3<br>~~ep~~|0.35 VCCIO<br>~~ep~~|0.65 VCCIO<br>~~ep~~|VCCIO+0.2 V<br>~~ep~~|0.4<br>~~ep~~|VCCIO− 0.4<br>~~ep~~|4<br>~~ep~~<br>~~ye~~|–4<br>~~ep~~<br>~~ye~~|
||||||0.2<br>~~ep~~|VCCIO− 0.2<br>~~ep~~|0.1<br>~~ep~~<br>~~ye~~|–0.1<br>~~ep~~<br>~~ye~~|



© 2018-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

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## **4.18. Differential Comparator Electrical Characteristics** 

|**Parameter**<br>**Symbol**<br>~~—_———~~|**Parameter Description**<br>~~—_———~~|**Test Conditions**<br>~~—_———~~|**Min**<br>~~—_———~~|**Max**<br>~~—_———~~|**Unit**<br>~~—_———~~|
|---|---|---|---|---|---|
|VREF<br>~~—_———~~|Reference Voltage to compare, on VINM<br>~~—_———~~|VCCIO= 2.5 V<br>~~—_———~~|0.25<br>~~—_———~~|VCCIO- 0.25 V<br>~~—_———~~|V<br>~~—_———~~|
|VDIFFIN_H<br>~~—_———~~|Differential input HIGH (VINP- VINM)<br>~~—_———~~|VCCIO= 2.5 V<br>~~—_———~~|250<br>~~—_———~~|—<br>~~—_———~~|mV<br>~~—_———~~|
|VDIFFIN_L<br>~~—_———~~|Differential input LOW (VINP- VINM)<br>~~—_———~~|VCCIO= 2.5 V<br>~~—_———~~|—<br>~~—_———~~|–250<br>~~—_———~~|mV<br>~~—_———~~|
|IIN<br>~~—_———~~|Input Current, VINPand VINM<br>~~—_———~~|VCCIO= 2.5 V<br>~~—_———~~|–10<br>~~—_———~~|10<br>~~—_———~~|µA<br>~~—_———~~|



## **4.19. Typical Building Block Function Performance** 

**4.19.1. Pin-to-Pin Performance (LVCMOS25) Table 4.15. Pin-to-Pin Performance (LVCMOS25) Function Timing Unit Basic Functions** 16-Bit Decoder 16.5 ns 4:1 Mux 18.0 ns 16:1 Mux 19.5 ns ~~————~~ **Notes** :  The above timing numbers are generated using the Lattice Design Software tool. Exact performance may vary with device and tool version. The tool uses internal parameters that have been characterized but are not tested on every device. 

- Using a VCC of 1.14 V at Junction Temperature 85 ° C. 

## **4.19.2. Register-to-Register Performance** 

**Table 4.16. Register-to-Register Performance Function Timing Unit Basic Functions** 16:1 Mux 110 MHz 16-Bit Adder 100 MHz 16-Bit Counter 100 MHz 64-Bit Counter 40 MHz **Embedded Memory Functions** 256 x 16 Pseudo-Dual Port RAM 150 MHz ~~=——==~~ **Notes** :  The above timing numbers are generated using the Lattice Design Software tool. Exact performance may vary with device and tool version. The tool uses internal parameters that have been characterized but are not tested on every device. 

- Under worst case operating conditions. 

© 2018-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

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**iCE40 UltraPlus Family Data Sheet Data Sheet** 

## **4.20. sysDSP Timing** 

Over recommended operating conditions. 

## **Table 4.17. sysDSP Timing** 

|**Parameter**|**Description**|**Min**|**Max**|**Unit**|
|---|---|---|---|---|
|fMAX8x8SMULT|Max frequencysigned MULT8x8 bypassing pipeline register|—|50|MHz|
|fMAX16x16SMULT|Max frequencysigned MULT16x16 bypassing pipeline register|—|50|MHz|



## **4.21. SPRAM Timing** 

Over recommended operating conditions. 

|**Table 4.18. Single Port RAM Timing**|
|---|
|**Parameter**<br>**Description**<br>**Min**<br>**Max**<br>**Unit**<br>fMAXSRAM<br>Max frequency SPRAM (4/8/16-bit Read and Write)<br>70<br>—<br>MHz<br>~~ee~~<br>~~ee~~|



## **4.22. Derating Logic Timing** 

Logic timing provided in the following sections of the data sheet and the Lattice design tools are worst case numbers in the operating range. Actual delays may be much faster. Lattice design tools can provide logic timing numbers at a particular temperature and voltage. 

## **4.23. Maximum sysI/O Buffer Performance** 

## **Table 4.19. Maximum sysI/O Buffer Performance** 

|**I/O Standard**|**Max Speed**|**Unit**|
|---|---|---|
|**Inputs**|||
|LVCMOS33|250|MHz|
|LVCMOS25|250|MHz|
|LVCMOS18|250|MHz|
|**Outputs**|||
|LVCMOS33|250|MHz|
|LVCMOS25|250|MHz|
|LVCMOS18|155|MHz|
|LVCMOS12|70|MHz|



**Note** : Measured with a toggling pattern. 

© 2018-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

36 

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## **4.24. iCE40 UltraPlus Family Timing Adders** 

Over recommended commercial operating conditions. 

**Table 4.20. iCE40 UltraPlus Family Timing Adders** 

|**Buffer Type**|**Description**|**Timing (Typ)**|**Units**|
|---|---|---|---|
|**Input Adjusters**||||
|LVCMOS33|LVCMOS, VCCIO= 3.3 V|0.18|ns|
|LVCMOS25|LVCMOS, VCCIO= 2.5 V|0|ns|
|LVCMOS18|LVCMOS, VCCIO= 1.8 V|0.19|ns|
|**Output Adjusters**||||
|LVCMOS33|LVCMOS, VCCIO= 3.3 V|–0.12|ns|
|LVCMOS25|LVCMOS, VCCIO= 2.5 V|0|ns|
|LVCMOS18|LVCMOS, VCCIO= 1.8 V|1.32|ns|
|LVCMOS12|LVCMOS, VCCIO= 1.2 V|5.38|ns|



**Notes** : 

- Timing adders are relative to LVCMOS25 and characterized but not tested on every device. 

- LVCMOS timing measured with the load specified in the Switching Test Conditions table. 

- Commercial timing numbers are shown. 

## **4.25. iCE40 UltraPlus External Switching Characteristics** 

Over recommended commercial operating conditions. 

**Table 4.21. iCE40 UltraPlus External Switching Characteristics** 

|**Parameter**<br>~~po~~|**Description**<br>~~po~~|**Device**<br>~~po~~|**Min**<br>~~po~~|**Max**<br>~~po~~|**Unit**<br>~~po~~|
|---|---|---|---|---|---|
|**Clocks**<br>~~pe~~||||||
|**Global Clock**<br>~~pe~~||||||
|fMAX_GBUF<br>~~eC~~|Frequencyfor Global Buffer Clock network<br>~~eC~~|All Devices<br>~~eC~~<br>~~CO~~|—<br>~~eC~~<br>~~CO~~|185<br>~~eC~~<br>~~CO~~|MHz<br>~~eC~~|
|tW_GBUF<br>~~Ge~~|Clock Pulse Width for Global Buffer<br>~~Ge~~|All Devices<br>~~Ge~~<br>~~CO~~|2<br>~~Ge~~<br>~~CO~~|—<br>~~Ge~~<br>~~CO~~|ns<br>~~Ge~~|
|tISKEW_GBUF<br>~~ee~~|Global Buffer Clock Skew Within a Device<br>~~ee~~|All Devices<br>~~CO~~<br>~~ee~~|—<br>~~CO~~<br>~~ee~~|530<br>~~CO~~<br>~~ee~~|ps<br>~~ee~~|
|**Pin-LUT-Pin Propagation Delay**<br>~~Re~~||||||
|tPD|Best case propagation delay through one<br>LUT logic|All Devices|—|9.0|ns|
|**General I/O Pin Parameters(Using Global Buffer Clock without PLL)* **<br>~~|~~<br>~~CO~~||||||
|tSKEW_IO<br>~~Ge~~<br>~~a~~|Data bus skew across a bank of IOs<br>~~Ge~~<br>|All Devices<br>~~Ge~~<br>~~CO~~<br>~~GO~~<br>|—<br>~~Ge~~<br>~~CO~~<br>~~GO~~<br>|510<br>~~Ge~~<br>~~CO~~<br>~~GO~~<br>|ps<br>~~Ge~~<br>|
|tCO<br>~~Ge~~<br>~~a~~|Clock to Output – PIO Output Register<br>~~Ge~~<br>|All Devices<br>~~CO~~<br>~~Ge~~<br>~~GO~~<br>|—<br>~~CO~~<br>~~Ge~~<br>~~GO~~<br>|10.0<br>~~CO~~<br>~~Ge~~<br>~~GO~~<br>|ns<br>~~Ge~~<br>|
|tSU<br>~~a~~|Clock to Data Setup– PIO Input Register<br>~~GO~~|All Devices<br>~~GO~~<br>~~GO~~<br>~~F~~|−0.5<br>~~GO~~<br>~~GO~~<br>~~F~~|—<br>~~GO~~<br>~~GO~~|ns<br>~~GO~~|
|tH<br>~~a ~~<br>~~A~~|Clock to Data Hold – PIO Input Register<br> ~~GO~~<br>~~A~~|All Devices<br>~~GO~~<br>~~GO~~<br>~~A~~<br>~~F~~|5.55<br>~~GO~~<br>~~GO~~<br>~~A~~<br>~~F~~|—<br>~~GO~~<br>~~GO~~<br>~~A~~|ns<br>~~GO~~<br>~~A~~|
|**General I/O Pin Parameters(Using Global Buffer Clock with PLL)**<br>~~F~~<br>~~CO~~||||||
|tCOPLL<br>~~Ge~~|Clock to Output – PIO Output Register<br>~~Ge~~|All Devices<br>~~Ge~~<br>~~CO~~|—<br>~~Ge~~<br>~~CO~~|2.4<br>~~Ge~~<br>~~CO~~|ns<br>~~Ge~~|
|tSUPLL<br>~~CO~~|Clock to Data Setup– PIO Input Register<br>~~CO~~|All Devices<br>~~CO~~<br>~~CO~~<br>~~CO~~|7.3<br>~~CO~~<br>~~CO~~<br>~~CO~~|—<br>~~CO~~<br>~~CO~~<br>~~CO~~|ns<br>~~CO~~|
|tHPLL<br>~~eG~~|Clock to Data Hold – PIO Input Register<br>~~eG~~|All Devices<br>~~eG~~<br>~~CO~~|−1.1<br>~~eG~~<br>~~CO~~|—<br>~~eG~~<br>~~CO~~|ns<br>~~eG~~|



***Note** : All the data is from the worst case. 

© 2018-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02008-1.9 

37 

**iCE40 UltraPlus Family Data Sheet Data Sheet** 

## **4.26. sysCLOCK PLL Timing** 

Over recommended operating conditions. 

**Table 4.22. sysCLOCK PLL Timing** 

|**Parameter**<br>~~a~~|**Descriptions**<br>~~ee~~|**Conditions**|**Min**|**Max**|**Unit**|
|---|---|---|---|---|---|
|fIN<br>~~a~~<br>~~es~~|Input Clock Frequency (REFERENCECLK,<br>EXTFEEDBACK)<br>~~ee~~<br>|—<br>|10<br>|133<br>|MHz<br>|
|fOUT<br>~~a~~<br>~~es~~|Output Clock Frequency (PLLOUT)<br>~~ee~~<br>|—<br>|16<br>|275<br>|MHz<br>|
|fVCO<br>~~esDO~~|PLL VCO Frequency<br>~~DO~~|—<br>~~DO~~|533<br>~~DO~~|1066<br>~~DO~~|MHz<br>~~DO~~|
|fPFD3<br>~~DO~~|Phase Detector Input Frequency<br>~~DO~~|—<br>~~DO~~|10<br>~~DO~~|133<br>~~DO~~|MHz<br>~~DO~~|
|**AC Characteristics**||||||
|tDT<br>~~eG~~|Output Clock DutyCycle<br>~~eG~~|—<br>~~eG~~|40<br>~~eG~~|60<br>~~eG~~|%<br>~~eG~~|
|tPH<br>~~OO~~|Output Phase Accuracy<br>~~OO~~|—<br>~~OO~~|—<br>~~OO~~|±12<br>~~OO~~|deg<br>~~OO~~|
|tOPJIT1, 5, 6<br>~~OO~~|Output Clock Period Jitter<br>~~OO~~<br>~~yy~~|fOUT>= 100 MHz<br>~~OO~~<br>~~yy~~|—<br>~~OO~~<br>~~yy~~|450<br>~~OO~~<br>~~yy~~|psp-p<br>~~OO~~<br>~~yy~~|
|||fOUT< 100 MHz<br>~~yy~~<br>~~es~~<br>~~ed~~|—<br>~~yy~~<br>~~es~~<br>~~ee~~|0.05<br>~~yy~~<br>~~es~~<br>~~eee~~|UIPP<br>~~yy~~<br>~~es~~<br>~~eee~~|
||Output Clock Cycle-to-Cycle Jitter<br>~~ee~~|fOUT>= 100 MHz<br>~~ee~~<br>~~ed~~|—<br>~~ee~~<br>~~ee~~<br>~~ee~~|750<br>~~ee~~<br>~~eee~~|psp-p<br>~~ee~~<br>~~eee~~|
|||fOUT< 100 MHz<br>~~ee~~<br>~~ed~~<br>~~es~~|—<br>~~ee~~<br>~~ee~~<br>~~es~~<br>~~ee~~|0.10<br>~~ee~~<br>~~eee~~<br>~~es~~|UIPP<br>~~ee~~<br>~~eee~~<br>~~es~~|
||Output Clock Phase Jitter<br>~~ee~~<br>~~yy~~|fPFD>= 25 MHz<br>~~ee~~<br>~~ed ~~<br>~~es~~<br>~~yy~~|—<br>~~ee~~<br> ~~ee ~~<br>~~es~~<br>~~ee~~<br>~~yy~~|275<br>~~ee~~<br> ~~eee~~<br>~~es~~<br>~~yy~~|psp-p<br>~~ee~~<br>~~eee~~<br>~~es~~<br>~~yy~~|
|||fPFD< 25 MHz<br>~~yy~~<br>~~ee~~|—<br>~~yy~~<br>~~ee~~|0.05<br>~~yy~~<br>~~ee~~|UIPP<br>~~yy~~<br>~~ee~~|
|tW<br>~~DO~~|Output Clock Pulse Width<br>~~DO~~|At 90% or 10%<br>~~DO~~|1.33<br>~~DO~~|—<br>~~DO~~|ns<br>~~DO~~|
|tLOCK2, 3<br>~~a~~|PLL Lock-in Time<br>~~a~~|—|—|50|µs|
|tUNLOCK<br>~~a ~~<br>~~DO~~|PLL Unlock Time<br> ~~a~~<br>~~DO~~|—<br>~~DO~~|—<br>~~DO~~|50<br>~~DO~~|ns<br>~~DO~~|
|tIPJIT4<br>~~yy~~|Input Clock Period Jitter<br>~~yy~~|fPFD≥ 20 MHz<br>~~yy~~|—<br>~~yy~~|1000<br>~~yy~~|psp-p<br>~~yy~~|
|||fPFD< 20 MHz<br>~~yy~~<br>~~po~~|—<br>~~yy~~<br>~~po~~|0.02<br>~~yy~~<br>~~po~~|UIPP<br>~~yy~~<br>~~po~~|
|tSTABLE3<br>~~OO~~<br>~~es~~|LATCHINPUTVALUE LOW to PLL Stable<br>~~OO~~|—<br>~~OO~~|—<br>~~OO~~<br>~~D~~|500<br>~~OO~~|ns<br>~~OO~~|
|tSTABLE_PW3<br>~~OO~~<br>~~es~~|LATCHINPUTVALUE Pulse Width<br>~~OO~~|—<br>~~OO~~|100<br>~~OO~~<br>~~D~~|—<br>~~OO~~|ns<br>~~OO~~|
|tRST<br>~~es~~<br>~~DO~~|RESET Pulse Width<br>~~DO~~|—<br>~~DO~~|10<br>~~D~~<br>~~DO~~|—<br>~~DO~~|ns<br>~~DO~~|
|tRSTREC<br>~~a~~|RESET RecoveryTime<br>~~a~~|—|10|—|µs|
|tDYNAMIC_WD<br>~~a ~~<br>~~DO~~|DYNAMICDELAY Pulse Width<br> ~~a~~<br>~~DO~~|—<br>~~DO~~|100<br>~~DO~~|—<br>~~DO~~|VCO Cycles<br>~~DO~~|



## **Notes:** 

1. Period jitter sample is taken over 10,000 samples of the primary PLL output with a clean reference clock. Cycle-to-cycle jitter is taken over 1000 cycles. Phase jitter is taken over 2000 cycles. All values per JESD65B. 

2. Output clock is valid after tLOCK for PLL reset and dynamic delay adjustment. 

3. At minimum fPFD. As the fPFD increases the time will decrease to approximately 60% the value listed. 

4. Maximum limit to prevent PLL unlock from occurring. Does not imply the PLL will operate within the output specifications listed in this table. 

5. The jitter values will increase with loading of the PLD fabric and in the presence of SSO noise. 

## **4.27. SPI Master or NVCM Configuration Time** 

**Table 4.23. SPI Master or NVCM Configuration Time[1, 2]** 

|**Symbol**|**Parameter**|**Conditions**|**Max**|**Unit**|
|---|---|---|---|---|
|tCONFIG|POR/CRESET_B to Device I/O Active|All devices – Low Frequency (Default)|140|ms|
|||All devices – Medium frequency|50|ms|
|||All devices – High frequency3|||



**Notes** : 

1. Assumes sysMEM Block is initialized to an all zero pattern if they are used. 

2. The NVCM download time is measured with a fast ramp rate starting from the maximum voltage of POR trip point. 

3. High frequency is supported only on SPI Master. 

© 2018-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

38 

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**iCE40 UltraPlus Family Data Sheet Data Sheet** 

## **4.28. sysCONFIG Port Timing Specifications** 

Over recommended operating conditions. 

**Table 4.24. sysCONFIG Port Timing Specifications** 

|**Symbol**<br>~~pO~~|**Parameter**<br>~~pO~~|**Conditions**<br>~~pO~~|**Min**<br>~~pO~~|**Typ**<br>~~pO~~|**Max**<br>~~pO~~|**Unit**<br>~~pO~~|
|---|---|---|---|---|---|---|
|**All Configuration Mode**<br>~~Re~~|||||||
|tCRESET_B|Minimum CRESET_B LOW pulse width<br>required to restart configuration, from<br>falling edge to rising edge|—|200|—|—|ns|
|tDONE_IO|Number of configuration clock cycles after<br>CDONE goes HIGH before the PIO pins are<br>activated|—|49|—|—|Clock<br>Cycles|
|**Slave SPI**<br>~~Pe~~|||||||
|tCR_SCK<br>~~pe~~|Minimum time from a rising edge on<br>CRESET_B until the first SPI WRITE<br>operation, first SPI_SCK clock. During this<br>time, the iCE40 UltraPlus device is clearing<br>its internal configuration memory|—<br>~~————————~~|1200<br>~~————————~~|—<br>~~————————~~|—<br>~~————————~~|µs<br>~~————————~~|
|fMAX<br>~~pe~~|CCLK clock frequency<br>~~pO~~|Write<br>~~————————~~<br>~~pO~~|1<br>~~————————~~|—<br>~~————————~~|25<br>~~————————~~|MHz<br>~~————————~~|
|||Read1<br>~~————————~~<br>~~pO~~|—<br>~~————————~~|15<br>~~————————~~|—<br>~~————————~~|MHz<br>~~————————~~|
|tCCLKH<br>~~pe~~<br>~~GG~~|CCLK clock pulsewidth HIGH<br>~~pO~~<br>~~GG~~|—<br>~~————————~~<br>~~pO~~<br>~~GG~~|20<br>~~————————~~<br>~~GG~~<br>~~GG~~|—<br>~~————————~~<br>~~GG~~<br>~~GG~~|—<br>~~————————~~<br>~~GG~~<br>~~GG~~|ns<br>~~————————~~<br>~~GG~~|
|tCCLKL<br>~~GG~~<br>~~eG~~|CCLK clock pulsewidth LOW<br>~~GG~~<br>~~eG~~|—<br>~~GG~~<br>~~eG~~|20<br>~~GG~~<br>~~eG~~<br>~~GG~~|—<br>~~GG~~<br>~~eG~~<br>~~GG~~|—<br>~~GG~~<br>~~eG~~<br>~~GG~~|ns<br>~~GG~~<br>~~eG~~|
|tSTSU<br>~~GG~~<br>~~es~~|CCLK setup time<br>~~GG~~<br>~~GC~~|—<br>~~GG~~<br>~~GC~~|12<br>~~GG~~<br>~~GG~~<br>~~GC~~|—<br>~~GG~~<br>~~GG~~<br>~~GC~~|—<br>~~GG~~<br>~~GG~~<br>~~GC~~|ns<br>~~GG~~<br>~~GC~~|
|tSTH<br>~~GG~~<br>~~es~~|CCLK hold time<br>~~GG~~<br>~~GC~~|—<br>~~GG~~<br>~~GC~~|12<br>~~GG~~<br>~~GC~~<br>~~GG~~|—<br>~~GG~~<br>~~GC~~<br>~~GG~~|—<br>~~GG~~<br>~~GC~~<br>~~GG~~|ns<br>~~GG~~<br>~~GC~~|
|tSTCO<br>~~es~~<br>~~eG~~|CCLK falling edge to valid output<br>~~GC~~<br>~~eG~~|—<br>~~GC~~<br>~~eG~~|13<br>~~GC~~<br>~~eG~~<br>~~GG~~|—<br>~~GC~~<br>~~eG~~<br>~~GG~~|—<br>~~GC~~<br>~~eG~~<br>~~GG~~|ns<br>~~GC~~<br>~~eG~~|
|**Master SPI3 **<br>~~GG~~<br>~~|~~|||||||
|fMCLK|MCLK clock frequency|Low Frequency<br>~~a~~|7.0<br>~~a~~|12.0<br>~~a~~|17.0<br>~~a~~|MHz<br>~~a~~|
|||Medium Frequency2<br>~~a~~<br>~~es~~|21.0<br>~~a~~<br>~~es~~|33.0<br>~~a~~<br>~~es~~|45.0<br>~~a~~<br>~~es~~|MHz<br>~~a~~<br>~~es~~|
|||High Frequency2<br>~~po~~|33.0<br>~~po~~|53.0<br>~~po~~|71.0<br>~~po~~|MHz<br>~~po~~|
|tMCLK<br>~~Ge~~|CRESET_B HIGH to first MCLK edge<br>~~Ge~~|—<br>~~po~~<br>~~GG~~|1200<br>~~po~~<br>~~GG~~|—<br>~~po~~<br>~~GG~~<br>~~GO~~|—<br>~~po~~|µs<br>~~po~~|
|tSU<br>~~Ge~~<br>~~DG~~|CCLK setup time<br>~~Ge~~<br>~~DG~~|—<br>~~GG~~<br>~~DG~~|6.16<br>~~GG~~<br>~~DG~~|—<br>~~GG~~<br>~~DG~~<br>~~GO~~|—<br>~~DG~~|ns<br>~~DG~~|
|tHD<br>~~DG~~<br>~~pf~~|CCLK hold time<br>~~DG~~<br>~~pf~~|—<br>~~DG~~<br>~~pf~~|1<br>~~DG~~<br>~~pf~~|—<br>~~DG~~<br>~~GO~~<br>~~pf~~|—<br>~~DG~~<br>~~pf~~|ns<br>~~DG~~<br>~~pf~~|



**Notes** : 

1. Supported with 1.2 V VCC and at 25 ° C. 

2. Extended range fMAX Write operations support up to 53 MHz with 1.2 V VCC and at 25 ° C. 

3. tSU and tHD timing must be met for all MCLK frequency choices. 

© 2018-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02008-1.9 

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**iCE40 UltraPlus Family Data Sheet Data Sheet** 

## **4.29. RGB LED Drive** 

**Table 4.25. RGB LED Symbol Parameter Min Max Unit** ILED_ACCURACY RGB0, RGB1, RGB2 Sink Current Accuracy to selected current @ VLEDOUT >= 0.5 V –12 +12 % ILED_MATCH RGB0, RGB1, RGB2 Sink Current Matching among the 3 outputs @ VLEDOUT >= 0.5 –5 +5 % ~~ee~~ 

## **4.30. Switching Test Conditions** 

Figure 4.3 shows the output test load that is used for AC testing. The specific values for resistance, capacitance, voltage, and other test conditions are listed in Table 4.26. 

V T R1 DUT Test Point CL ~~coe~~ 

**Figure 4.3. Output Test Load, LVCMOS Standards** 

**Table 4.26. Test Fixture Required Components, Non-Terminated Interfaces** 

|**Test Condition**|**R1 **|**CL **|**Timing Reference**|**VT **|
|---|---|---|---|---|
|LVCMOS settings (L ≥ H, H ≥ L)|∞|0 pF|LVCMOS 3.3 = 1.5 V|—|
||||LVCMOS 2.5 = VCCIO/2|—|
||||LVCMOS 1.8 = VCCIO/2|—|
|LVCMOS 3.3 (Z ≥ H)|188|0 pF|1.5 V|VOL|
|LVCMOS 3.3 (Z ≥ L)|||1.5 V|VOH|
|Other LVCMOS (Z ≥ H)|||VCCIO/2|VOL|
|Other LVCMOS (Z ≥ L)|||VCCIO/2|VOH|
|LVCMOS (H ≥ Z)|||VOH– 0.15 V|VOL|
|LVCMOS (L ≥ Z)|||VOL– 0.15 V|VOH|



**Note** : Output test conditions for all other interfaces are determined by the respective standards. 

© 2018-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

40 

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## **5. Pinout Information** 

## **5.1. Signal Descriptions** 

## **5.1.1. Power Supply Pins** 

|**Signal Name**|**Function**|**I/O**|**Description**|
|---|---|---|---|
|VCC|Power|—|Core Power Supply|
|VCCIO_0, SPI_VCCIO1, VCCIO_2|Power|—|Power for I/Os in Bank 0, 1, and 2.|
|VPP_2V5|Power|—|Power for NVCMprogrammingand operations.|
|VCCPLL|Power|—|Power for PLL.|
|GND|GROUND|—|Ground|
|GND_LED|GROUND|—|Ground for LED drivers. Should connect to GND on board.|



## **5.1.2. Configuration Pins** 

|**Signal Name**|**Signal Name**|**Function**|**I/O**|**Description**|
|---|---|---|---|---|
|**General I/O**|**Shared**<br>**Function**||||
|CRESET_B|—|Configuration|I|Configuration Reset, active LOW. No internal pull-up resistor.<br>Either actively driven externally or connect an 10 kΩ pull-up to<br>SPI_VCCIO1.|
|IOB_xxx|CDONE|Configuration|I/O|Configuration Done. Includes a weak pull-up resistor to<br>SPI_VCCIO1.|
|||General I/O|I/O|In user mode, after configuration, this pin can be programmed<br>as general I/O in user function. In 30-pin WLCSP, this pin<br>connects to IOB_12a, which also is shared as global signal G4<br>in user mode.|



© 2018-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02008-1.9 

41 

**iCE40 UltraPlus Family Data Sheet Data Sheet** 

## **5.1.3. Configuration SPI Pins** 

|**Signal Name**|**Signal Name**|**Function**|**I/O**|**Description**|
|---|---|---|---|---|
|**General I/O**|**Shared**<br>**Function**||||
|IOB_34a|SPI_SCK|Configuration|I/O|This pin is shared with device configuration. During configuration:<br>In Master SPI mode, this pin outputs the clock to external SPI<br>memory.<br>In Slave SPI mode, this pin inputs the clock from external<br>processor.|
|||General I/O|I/O|In user mode, after configuration, this pin can be programmed as<br>general I/O in user function.|
|IOB_32a|SPI_SO|Configuration|Output|This pin is shared with device configuration. During configuration:<br>In Master SPI mode, this pin outputs the command data to<br>external SPI memory.<br>In Slave SPI mode, this pin connects to the MISO pin of the<br>externalprocessor.|
|||General I/O|I/O|In user mode, after configuration, this pin can be programmed as<br>general I/O in user function.|
|IOB_33b|SPI_SI|Configuration|Input|This pin is shared with device configuration. During configuration:<br>In Master SPI mode, this pin receives data from external SPI<br>memory.<br>In Slave SPI mode, this pin connects to the MOSI pin of the<br>externalprocessor.|
|||General I/O|I/O|In user mode, after configuration, this pin can be programmed as<br>general I/O in user function.|
|IOB_35b|SPI_SS|Configuration|I/O|This pin is shared with device configuration. During configuration:<br>In Master SPI mode, this pin outputs to the external SPI memory.<br>In Slave SPI mode, this pin inputs CSN from the external<br>processor.|
|||General I/O|I/O|In user mode, after configuration, this pin can be programmed as<br>general I/O in user function.|



© 2018-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

42 

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## **5.1.4. Global Pins** 

|**Signal Name**<br>~~po~~<br>~~feesfees~~|**Signal Name**<br>~~po~~<br>~~feesfees~~|**Function**|**I/O**|**Description**|
|---|---|---|---|---|
|**General I/O**<br>~~fees~~|**Shared**<br>**Function**<br>~~fees~~||||
|IOT_46b<br>~~fees ~~<br>~~a~~|G0<br> ~~fees~~|General I/O<br>~~ee~~|I/O<br>~~ee eee~~|In user mode, after configuration, this pin can be<br>programmed asgeneral I/O in user function.<br>~~eee~~|
|||Global<br>~~ee~~<br>~~i~~|Input<br>~~ee eee~~|Global input used for high fanout, or clock/ reset net. The<br>G0pin drives the GBUF0global buffer.<br>~~eee~~|
|IOT_45a<br>~~ee~~|G1<br>~~ee~~|General I/O<br>~~ee~~<br>~~ee~~|I/O<br>~~ee~~|In user mode, after configuration, this pin can be<br>programmed asgeneral I/O in user function.<br>~~ee~~|
|||Global<br>~~ee~~<br>~~ee~~|Input<br>~~ee~~|Global input used for high fanout, or clock/ reset net. The<br>G1pin drives the GBUF1global buffer.<br>~~ee~~|
|IOB_25b<br>~~ee~~<br>~~a~~|G3<br>~~ee~~|General I/O<br>~~ee~~<br>~~ee~~<br>~~ee~~|I/O<br>~~ee~~|In user mode, after configuration, this pin can be<br>programmed asgeneral I/O in user function.<br>~~ee~~|
|||Global<br>~~ee~~<br>~~ee~~|Input<br>~~ee~~|Global input used for high fanout, or clock/ reset net. The<br>G3pin drives the GBUF3global buffer.<br>~~ee~~|
|IOB_12a<br>~~a~~<br>~~a~~|G4|General I/O<br>~~ee~~<br>~~ee~~<br>~~ee~~|I/O<br>~~ee eee~~|In user mode, after configuration, this pin can be<br>programmed asgeneral I/O in user function.<br>~~eee~~|
|||Global<br>~~ee~~<br>~~ee~~<br>~~ee~~|Input<br>~~ee eee~~|Global input used for high fanout, or clock/ reset net. The<br>G4pin drives the GBUF4global buffer.<br>~~eee~~|
|IOB_11b<br>~~a~~|G5|General I/O<br>~~ee~~<br>~~ee~~<br>~~ee~~|I/O<br>~~ee eee~~|In user mode, after configuration, this pin can be<br>programmed asgeneral I/O in user function.<br>~~eee~~|
|||Global<br>~~ee~~<br>~~ee~~<br>~~ee~~|Input<br>~~ee eee~~|Global input used for high fanout, or clock/ reset net. The<br>G5pin drives the GBUF5global buffer.<br>~~eee~~|
|IOB_3b<br>~~a~~|G6<br>~~a~~|General I/O<br>~~ee~~<br>~~a~~<br>~~ee~~|I/O<br>~~a~~|In user mode, after configuration, this pin can be<br>programmed asgeneral I/O in user function.<br>~~a~~|
|||Global<br>~~a~~<br>~~ee~~|Input<br>~~a~~|Global input used for high fanout, or clock/ reset net. The<br>G6pin drives the GBUF6global buffer.<br>~~a~~|



© 2018-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02008-1.9 

43 

**iCE40 UltraPlus Family Data Sheet Data Sheet** 

## **5.1.5. General I/O, LED Pins** 

|**Signal Name**|**Signal Name**|**Function**|**I/O**|**Description**|
|---|---|---|---|---|
|**General I/O**|**Shared Function**||||
|RGB0|—|General I/O|Open-<br>Drain I/O|In user mode, when RGB function is not used, this pin can<br>be connected to any user logic and used as open-drain I/O.<br>Thispin is located in Bank 0.|
|||LED|Open-<br>Drain<br>Output|In user mode, when using RGB function, this pin can be<br>programmed as open drain 24 mA output to drive external<br>LED.|
|RGB1|—|General I/O|Open-<br>Drain I/O|In user mode, when RGB function is not used, this pin can<br>be connected to any user logic and used as open-drain I/O.<br>Thispin is located in Bank 0.|
|||LED|Open-<br>Drain<br>Output|In user mode, when using RGB function, this pin can be<br>programmed as open drain 24 mA output to drive external<br>LED.|
|RGB2|—|General I/O|Open-<br>Drain I/O|In user mode, when RGB function is not used, this pin can<br>be connected to any user logic and used as open-drain I/O.<br>Thispin is located in Bank 0.|
|||LED|Open-<br>Drain<br>Output|In user mode, when using RGB function, this pin can be<br>programmed as open drain 24 mA output to drive external<br>LED.|
|PIOT_xx|—|General I/O|I/O|In user mode, with user's choice, this pin can be<br>programmed as I/O in user function in the top (xx = I/O<br>location).  Thesepins are located in Bank 0.|
|PIOB_xx|—|General I/O|I/O|In user mode, with user's choice, this pin can be<br>programmed as I/O in user function in the bottom (xx = I/O<br>location).  Pins with xx <= 9 are located in Bank 2, pins with<br>xx> are located in Bank 1.|



© 2018-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

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**iCE40 UltraPlus Family Data Sheet Data Sheet** 

|**Pin Type**<br>~~a~~|**Pin Type**<br>~~a~~|**iCE40UP3K**<br>~~a~~<br>~~ee~~|**iCE40UP5K**<br>~~a~~<br>~~ee~~<br>~~eee~~<br>~~ee~~|**iCE40UP5K**<br>~~a~~<br>~~ee~~<br>~~eee~~<br>~~ee~~|
|---|---|---|---|---|
|||**UWG30**<br>~~a~~<br>~~ee~~<br>~~ee~~|**UWG30**<br>~~a~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|**SG48**<br>~~a~~<br>~~eee~~<br>~~ee~~|
|General Purpose I/O Per<br>Bank|Bank 0<br>~~es~~|7<br>~~ee ~~<br>~~es~~|7<br> ~~ee~~<br>~~ee~~<br>~~es~~|17<br>~~eee~~<br>~~es~~|
||Bank 1<br>~~es~~<br>~~es~~|10<br>~~es~~<br>~~es~~|10<br>~~es~~<br>~~es~~|14<br>~~es~~<br>~~es~~|
||Bank 2<br>~~es~~|4<br>~~es~~|4<br>~~es~~|8<br>~~es~~|
|Total General Purpose I/Os<br>~~a~~<br>~~aes~~||21<br>~~es~~|21<br>~~es~~|39<br>~~es~~|
|VCC<br>~~aes~~||1<br>~~es~~|1<br>~~es~~|2<br>~~es~~|
|VCCIO<br>~~a ~~|Bank 0<br>~~es~~|1<br>~~es~~|1<br>~~es~~|1<br>~~es~~|
||Bank 1<br> ~~es~~<br>~~es~~|1<br>~~es~~<br>~~es~~|1<br>~~es~~<br>~~es~~|1<br>~~es~~<br>~~es~~|
||Bank 2<br>~~es~~|1<br>~~es~~|1<br>~~es~~|1<br>~~es~~|
|VCCPLL<br>~~a~~||1<br>~~a~~|1<br>~~a~~|1<br>~~a~~|
|VPP_2V5<br>~~I~~||1<br>~~I~~|1<br>~~I~~|1<br>~~I~~|
|Dedicated ConfigPins<br>~~a~~||1<br>~~a~~|1<br>~~a~~|2<br>~~a~~|
|GND<br>~~a~~<br>~~a~~<br>~~a~~||2<br>~~a~~<br>~~a~~|2<br>~~a~~<br>~~a~~|0*<br>~~a~~<br>~~a~~|
|Total Balls<br>~~a~~||30|30|48|



***Note** : 48-pin QFN package (SG48) requires the package paddle to be connected to GND. 

© 2018-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

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**iCE40 UltraPlus Family Data Sheet Data Sheet** 

## **5.3. iCE40UP Part Number Description** 

**==> picture [132 x 9] intentionally omitted <==**

**----- Start of picture text -----**<br>
iCE40UPXX - XXXXXITR<br>**----- End of picture text -----**<br>


**==> picture [433 x 133] intentionally omitted <==**

**----- Start of picture text -----**<br>
Device Family        TR<br>iCE40UP FPGA <blank> =  Default Tape and Reel<br>                   for SG48 (See quantity below)<br>TR =  Tape and Reel (See quantity below)<br>Logic Cells<br>TR50 = Tape and Reel, 50 units<br>3K = 2,800 Logic Cells<br>TR1K = Tape and Reel, 1,000 units<br>5K = 5,280 Logic Cells<br>Grade<br>    I = Industrial<br>Package<br>UWG30 = 30-Ball WLCSP (0.40 mm Ball Pitch)<br>All parts are shipped in tape-and-reel. SG48 = 48-Pin QFN (0.50 mm Pin Pitch)<br>**----- End of picture text -----**<br>


**5.3.1. Tape and Reel Quantity Package TR Quantity** UWG30 5,000 ~~——_—————~~ SG48 2,000 

## **5.4. Ordering Part Numbers** 

## **5.4.1. Industrial** 

|**Part Number**|**LUTs**|**Supply Voltage **|**Package **|**Pins**|**Temperature**|
|---|---|---|---|---|---|
|iCE40UP3K-UWG30ITR|2800|1.2 V|Halogen-Free WLCSP|30|IND|
|iCE40UP3K-UWG30ITR1K|2800|1.2 V|Halogen-Free WLCSP|30|IND|
|iCE40UP3K-UWG30ITR50|2800|1.2 V|Halogen-Free WLCSP|30|IND|
|iCE40UP5K-SG48I|5280|1.2 V|Halogen-Free QFN|48|IND|
|iCE40UP5K-SG48ITR50|5280|1.2 V|Halogen-Free QFN|48|IND|
|iCE40UP5K-UWG30ITR|5280|1.2 V|Halogen-Free WLCSP|30|IND|
|iCE40UP5K-UWG30ITR1K|5280|1.2 V|Halogen-Free WLCSP|30|IND|
|iCE40UP5K-UWG30ITR50|5280|1.2 V|Halogen-Free WLCSP|30|IND|



© 2018-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02008-1.9 

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**iCE40 UltraPlus Family Data Sheet Data Sheet** 

## **Supplemental Information** 

## **For Further Information** 

A variety of technical documents for the iCE40 UltraPlus family are available on the Lattice web site. 

- iCE40 Programming and Configuration (FPGA-TN-02001) 

- iCE40 SPI/I2C Hardened IP Usage Guide (FPGA-TN-02010) 

- Advanced iCE40 SPI/I2C Hardened IP Usage Guide (FPGA-TN-02011) 

- Memory Usage Guide for iCE40 Devices (FPGA-TN-02002) 

- iCE40 sysCLOCK PLL Design and Usage Guide (FPGA-TN-02052) 

- iCE40 Hardware Checklist (FPGA-TN-02006) 

- iCE40 LED Driver Usage Guide (FPGA-TN-02021) 

- DSP Function Usage Guide for iCE40 Devices (FPGA-TN-02007) 

- iCE40 Oscillator Usage Guide (FPGA-TN-02008) 

- iCE40 SPRAM Usage Guide (FPGA-TN-02022) 

- iCE40 UltraPlus Pinout Files 

- iCE40 UltraPlus Pin Migration Files 

- Thermal Management 

- Package Diagrams 

- Lattice design tools 

© 2018-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02008-1.9 

47 

**iCE40 UltraPlus Family Data Sheet Data Sheet** 

## **Technical Support** 

For assistance, submit a technical support case at www.latticesemi.com/techsupport. 

© 2018-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

48 

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**iCE40 UltraPlus Family Data Sheet Data Sheet** 

## **Revision History** 

## **Revision 1.9, December 2020** 

|**Section**|**Change Summary**|
|---|---|
|DC and Switching Characteristics|<br>Updated values inTable 4.17. sysDSP Timing.<br><br>Updated footnotes inTable 4.23. SPI Master or NVCM Configuration Time.|
|—|Minor style adjustments|



## **Revision 1.8, August 2020** 

|**Section**|**Change Summary**|
|---|---|
|Architecture|<br>Removed paragraph regarding SCLK and SDI inputs from sysCLOCK Phase Locked Loops<br>(PLLs) section.<br><br>Updated linked reference.<br><br>Modified Figure 3.3. PLL Diagram.|
|Supplemental Information|Updated document ID of sysCLOCK PLL Design and Usage Guide in For Further Information<br>section.|



**Revision 1.7, February 2020** 

**Section Change Summary** Disclaimers Added this section. ~~————————~~ **Revision 1.6, November 2018 Section Change Summary** General Description Corrected product dimensions from 2.15 mm × 2.55 mm to 2.11 mm × 2.54 mm. ~~a~~ Product Family 

## **Revision 1.5, August 2018** 

||**Section**|**Change Summary**|
|---|---|---|
||All|Removed Copyrightpage.|
||DC and Switching Characteristics|Updated sysCONFIG Port Timing Specifications section. Updated tCR_SCKparameter in Table|
|||4.24.|
||Pinout Information|Updated Configuration SPI Pins section.|
|||Updated secondarysignal name from SPI_SS_B to SPI_SS.|
||Supplemental Information|Updated iCE40 Programmingand Configuration document number.|
|**Revision 1.4, August 2017**|||
|**Section**<br>**Change Summary**<br>All<br><br>Changed document number from DS1056 to FPGA-DS-02008.<br><br>Removed Preliminaryfrom document coverpage and header.<br>~~a~~|||



© 2018-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02008-1.9 

49 

**iCE40 UltraPlus Family Data Sheet Data Sheet** 

## **Revision 1.3, August 2017** 

|**Section**|**Change Summary**|
|---|---|
|All|<br>Changed document status from Advance to Preliminary.<br><br>Updated footer.|
|Architecture|<br>Corrected link to iCE40 LED Driver Usage Guide (TN1288).<br><br>Added link to iCE40 SPRAM Usage Guide(TN1314).|
|DC and Switching Characteristics|<br>Updated Typ VCC=1.2 V values for IPP_2VSPEAKand ICOOPEAKin Table 4.6. Supply Current.<br><br>Added Min value for fMAXSRAMto Table 4.18. Single Port RAM Timing.<br><br>Added LVCMOS12 information to Table 4.19. Maximum sysI/O Buffer Performance and<br>Table 4.20. iCE40 UltraPlus Family Timing Adders.<br><br>Updated Table 4.21. iCE40 UltraPlus External Switching Characteristics. Revised Max<br>values for tISKEW_GBUF, tSKEW_IO, tCO, tCOPLL, and Min values for tSUPLL, tHPLL.<br><br>Added Max values to Table 4.23. SPI Master or NVCM Configuration Time.|
|Pinout Information|<br>Updated TR description in the iCE40UP Part Number Description section.<br><br>Updatedpart number information in the OrderingPart Numbers section.|
|Supplemental Information|<br>Corrected link to iCE40 LED Driver Usage Guide (TN1288).<br><br>Added link to iCE40 SPRAM Usage Guide (TN1314).<br><br>Added link to Package Diagrams.|



## **Revision 1.2, June 2016** 

|**Section**|**Change Summary**|
|---|---|
|All|Updated template.|
|Introduction|Added QFNpackage in features list.|
|Product Family|<br>Added packages to Table 2.1. iCE40 UltraPlus Family Selection Guide.<br><br>Added information on RGB PWM IP in Overview.|
|Architecture|<br>Performed minor editorial changes.<br><br>Added information on 256 kb SPRAM blocks.<br><br>Changed headings in Table 3.2. Global Buffer (GBUF) Connections to Programmable<br>Logic Blocks.<br><br>Corrected VCCPLL format in Figure 3.3. PLL Diagram.<br><br>Updated note in Table 3.4. sysMEM Block Configurations.<br><br>Added reference to iCE40 SPRAM Usage Guide (TN1314).<br><br>Revised sysI/O Buffer Banks information.<br><br>Corrected VCCIO format in Figure 3.9. I/O Bank and Programmable I/O Cell.<br><br>Revised Typical I/O Behavior During Power-up information.<br><br>Revised Supported Standards information.<br><br>Revised heading in Table 3.9. Supported Input Standards.<br><br>Revised heading and removed LVCMOS12 in Table 3.10Table 3.10. Supported Output<br>Standards.<br><br>Revised HFOSC information in On-Chip Oscillator section.<br><br>Removed "An RGB PWM IP is also offered in the family." in RGB High Current Drive I/O<br>Pins section.|
|DC and Switching Characteristics|<br>Added the following figures:<br><br>Figure 4.1. Power Up Sequence with SPE_VCCIO1 and VPP_2V5 Not Connected<br>Together.<br><br>Figure 4.2. Power Up Sequence with All Supplies Connected Together to 1.8 V.<br><br>Updated note in Table 4.5. DC Electrical Characteristics.<br><br>Added note in Table 4.6. Supply Current.<br><br>Revised User SPI Specifications 1, 2 section.<br><br>Removed symbols.<br><br>Added notes.<br><br>Revised Table 4.11. Internal Oscillators(HFOSC, LFOSC).|



© 2018-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

50 

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**iCE40 UltraPlus Family Data Sheet Data Sheet** 

|**Section**|**Change Summary**|
|---|---|
||<br>Removed note in Table 4.13. sysI/O Single-Ended DC Electrical Characteristics.<br><br>Changed to Lattice Design Software tool in Table 4.15. Pin-to-Pin Performance<br>(LVCMOS25).<br><br>Changed to Lattice Design Software tool and revised note in Table 4.16. Register-to-<br>Register Performance.<br><br>Added sysDSP Timing section.<br><br>Added SPRAM Timing section.<br><br>Removed LVCMOS12 and added timing values in Table 4.19. Maximum I/O Buffer<br>Performance.<br><br>Removed LVCMOS12 and added timing values in Table 4.20. iCE40 UltraPlus Family<br>Timing Adders.<br><br>Revised max values in Table 4.23. SPI Master or NVCM Configuration Time.<br><br>Removed TBD conditions in Table 4.24. sysCONFIG Port Timing Specifications. Revised<br>tHD parameter.<br><br>Revised Table 4.25. High Current RGB LED and IR LED Drive.|
|Pinout Information|<br>General update to Signal Descriptions section.<br><br>Updated the iCE40UP Part Number Description section. Added FGW49 package.<br><br>Added OPNs.|
|Supplemental Information|Added reference to FPGA-TN-02022, iCE40 SPRAM Usage Guide .|



## **Revision 1.1, September 2015** 

|**Section**|**Change Summary**|
|---|---|
|Architecture|Updated Architecture section. Replaced iCE5UP with iCE40UP.|
|Pinout Information|Updated Pin Information section.<br><br>Replaced iCE5UP with iCE40UP.<br><br>Replaced SWG30 with UWG30.|
|Ordering Information|Updated iCE40UP Part Number Description section.<br><br>Replaced iCE5UP with iCE40UP.<br><br>Replaced SWG30 with UWG30.<br>Updated OrderingPart Numbers section. Replaced the table ofpart|
|Further Information|Removed reference to Schematic Symbols.|



## **Revision 1.0, August 2015** 

|**Section**|**Change Summary**|
|---|---|
|All|Initial release.|



© 2018-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02008-1.9 

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