ICE40UL1K-SWG16ITR

FPGA, iCE40, PLL, 10 I/O's, 1248 Cell, 1.14 V to 1.26 V in, WLCSP-16

⚠️ Reference pricing provided. In case of supply shortages, we will connect you with our trusted procurement partners to ensure your project's continuity.
Manufacturer: LATTICE SEMICONDUCTOR
Product type: FPGAs
MSL: MSL 3 - 168 hours
SVHC: No SVHC (25-Jun-2025)
FPGA Type: SRAM based FPGA
FPGA Family: iCE40
IC Mounting: Surface Mount
No. of Pins: 16Pins
Speed Grade: -
No. of I/O's: 10I/O's
Product Range: -
Qualification: -
Total RAM Bits: 56Kbit
No.of User I/Os: 10I/O's
Clock Management: PLL
Logic Case Style: WLCSP
IC Case / Package: WLCSP
No. of Macrocells: 1248Macrocells
I/O Supply Voltage: 3.46V
No. of Logic Cells: 1248Logic Cells
Process Technology: 40nm (CMOS)
No. of Logic Blocks: 1248
Core Supply Voltage Max: 1.26V
Core Supply Voltage Min: 1.14V
Operating Frequency Max: 1MHz
Operating Temperature Max: 100°C
Operating Temperature Min: -40°C
Delivery and price
Units per pack	1000
Price	1.77 €
Current stock	10+
Lead time	30 days
Datasheet
## Os 

## **iCE40 UltraLite Family Data Sheet** 

## **Data Sheet** 

FPGA-DS-02027-1.7 

October 2020 

aLATTICE 

**iCE40 UltraLite Family Data Sheet Data Sheet** 

## **Disclaimers** 

Lattice makes no warranty, representation, or guarantee regarding the accuracy of information contained in this document or the suitability of its products for any particular purpose. All information herein is provided AS IS and with all faults, and all risk associated with such information is entirely with Buyer. Buyer shall not rely on any data and performance specifications or parameters provided herein. Products sold by Lattice have been subject to limited testing and it is the Buyer's responsibility to independently determine the suitability of any products and to test and verify the same. No Lattice products should be used in conjunction with mission- or safety-critical or any other application in which the failure of Lattice’s product could create a situation where personal injury, death, severe property or environmental damage may occur. The information provided in this document is proprietary to Lattice Semiconductor, and Lattice reserves the right to make any changes to the information in this document or to any products at any time without notice. 

© 2018-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

2 

FPGA-DS-02027-1.7 

**iCE40 UltraLite Family Data Sheet Data Sheet** 

## **Contents** 

|**Contents**|**Contents**|
|---|---|
|Acronyms in This Document ................................................................................................................................................. 6||
|1.|General Description ...................................................................................................................................................... 7|
||1.1.<br>Features .............................................................................................................................................................. 7|
|2.|Product Family .............................................................................................................................................................. 8|
||2.1.<br>Overview ............................................................................................................................................................. 8|
|3.|Architecture .................................................................................................................................................................. 9|
||3.1.<br>Architecture Overview ........................................................................................................................................ 9|
||3.1.1.<br>PLB Blocks ..................................................................................................................................................... 10|
||3.1.1.1.<br>Logic Cells ............................................................................................................................................. 10|
||3.1.2.<br>Routing .......................................................................................................................................................... 11|
||3.1.3.<br>Clock/Control Distribution Network ............................................................................................................. 11|
||3.1.3.1.<br>Global Hi-Z Control ............................................................................................................................... 12|
||3.1.3.2.<br>Global Reset Control ............................................................................................................................ 12|
||3.1.4.<br>sysCLOCK Phase Locked Loops (PLLs) (sysCLOCK PLL is only supported in 36-ball ucBGA package) ............ 12|
||3.1.5.<br>sysMEM Embedded Block RAM Memory ..................................................................................................... 13|
||3.1.5.1.<br>sysMEM Memory Block ........................................................................................................................ 13|
||3.1.5.2.<br>RAM Initialization and ROM Operation ............................................................................................... 14|
||3.1.5.3.<br>Memory Cascading ............................................................................................................................... 14|
||3.1.5.4.<br>RAM4K Block ........................................................................................................................................ 14|
||3.1.6.<br>sysI/O Buffer Banks ....................................................................................................................................... 15|
||3.1.6.1.<br>Programmable I/O (PIO) ...................................................................................................................... 15|
||3.1.6.2.<br>Input Register Block ............................................................................................................................. 16|
||3.1.6.3.<br>Output Register Block .......................................................................................................................... 16|
||3.1.7.<br>sysI/O Buffer ................................................................................................................................................. 18|
||3.1.7.1.<br>Typical I/O Behavior During Power-up ................................................................................................. 18|
||3.1.7.2.<br>Supported Standards ........................................................................................................................... 18|
||3.1.7.3.<br>Programmable Pull Up Resistors .......................................................................................................... 18|
||3.1.7.4.<br>Differential Comparators ..................................................................................................................... 18|
||3.1.8.<br>On-Chip Oscillator ......................................................................................................................................... 19|
||3.1.9.<br>User I2C IP ..................................................................................................................................................... 19|
||3.1.10.<br>High Current LED Drive I/O Pins ............................................................................................................... 19|
||3.1.11.<br>Hardened RGB PWM IP ............................................................................................................................ 20|
||3.1.12.<br>Hardened IR Transceiver IP ...................................................................................................................... 20|
||3.1.13.<br>Non-Volatile Configuration Memory ........................................................................................................ 20|
||3.1.14.<br>Power On Reset ........................................................................................................................................ 20|
||3.2.<br>iCE40 UltraLite Programming and Configuration .............................................................................................. 21|
||3.2.1.<br>Device Programming ..................................................................................................................................... 21|
||3.2.2.<br>Device Configuration .................................................................................................................................... 21|
||3.2.3.<br>Power Saving Options ................................................................................................................................... 21|
|4.|DC and Switching Characteristics ............................................................................................................................... 22|
||4.1.<br>Absolute Maximum Ratings .............................................................................................................................. 22|
||4.2.<br>Recommended Operating Conditions ............................................................................................................... 22|
||4.3.<br>Power Supply Ramp Rates ................................................................................................................................ 23|
||4.4.<br>Power-On Reset ................................................................................................................................................ 23|
||4.5.<br>Power-up Supply Sequence............................................................................................................................... 23|
||4.6.<br>External Reset ................................................................................................................................................... 23|
||4.7.<br>Power-On-Reset Voltage Levels ........................................................................................................................ 24|
||4.8.<br>ESD Performance .............................................................................................................................................. 25|
||4.9.<br>DC Electrical Characteristics .............................................................................................................................. 25|
||4.10.<br>Supply Current .................................................................................................................................................. 26|
||4.11.<br>Internal Pull-Up Resistor Specifications ............................................................................................................ 26|
||4.12.<br>User I2C Specifications ....................................................................................................................................... 27|



© 2018-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02027-1.7 

3 

aLATTICE 

**iCE40 UltraLite Family Data Sheet Data Sheet** 

||4.13.|Internal Oscillators (HFOSC, LFOSC) .................................................................................................................. 27|
|---|---|---|
||4.14.|sysI/O Recommended Operating Conditions .................................................................................................... 27|
||4.15.|sysI/O Single-Ended DC Electrical Characteristics ............................................................................................. 27|
||4.16.|Differential Comparator Electrical Characteristics ............................................................................................ 28|
||4.17.|Derating Logic Timing ........................................................................................................................................ 28|
||4.18.|Maximum sysI/O Buffer Performance ............................................................................................................... 28|
||4.19.|iCE40 UltraLite External Switching Characteristics ............................................................................................ 29|
||4.20.|sysCLOCK PLL Timing ......................................................................................................................................... 29|
||4.21.|SPI Master or NVCM Configuration Time .......................................................................................................... 30|
||4.22.|sysCONFIG Port Timing Specifications ............................................................................................................... 30|
||4.23.|High Current LED, IR LED and Barcode LED Drives*........................................................................................... 31|
||4.24.|RGB LED Timing Specification ............................................................................................................................ 32|
||4.25.|IR Transceiver IP Timing Specification ............................................................................................................... 32|
||4.26.|Switching Test Conditions ................................................................................................................................. 32|
|5.|Pinout Information ..................................................................................................................................................... 33||
||5.1.|Signal Descriptions ............................................................................................................................................ 33|
||5.1.1.|Power Supply Pins ......................................................................................................................................... 33|
||5.1.2.|Configuration Pins ......................................................................................................................................... 33|
||5.1.3.|Configuration SPI Pins ................................................................................................................................... 34|
||5.1.4.|Global Pins .................................................................................................................................................... 34|
||5.1.5.|General I/O, LED Pins .................................................................................................................................... 35|
||5.2.|Pin Information Summary ................................................................................................................................. 36|
||5.3.|iCE40 Ultra Lite Part Number Description ......................................................................................................... 37|
||5.3.1.|Tape and Reel Quantity ................................................................................................................................ 37|
||5.4.|Ordering Part Numbers ..................................................................................................................................... 37|
||5.4.1.|Industrial ....................................................................................................................................................... 37|
|Supplemental Information .................................................................................................................................................. 38|||
|Technical Support ............................................................................................................................................................... 39|||
|Revision History .................................................................................................................................................................. 40|||



## **Figures** 

|Figure 3.1. iCE40UL-1K Device, Top View ............................................................................................................................. 9|Figure 3.1. iCE40UL-1K Device, Top View ............................................................................................................................. 9|
|---|---|
|Figure 3.2. PLB Block Diagram ............................................................................................................................................ 10|Figure 3.2. PLB Block Diagram ............................................................................................................................................ 10|
|Figure 3.3. PLL Diagram ...................................................................................................................................................... 12|Figure 3.3. PLL Diagram ...................................................................................................................................................... 12|
|Figure 3.4. sysMEM Memory Primitives ............................................................................................................................. 14|Figure 3.4. sysMEM Memory Primitives ............................................................................................................................. 14|
|Figure 3.5. I/O Bank and Programmable I/O Cell ................................................................................................................ 16|Figure 3.5. I/O Bank and Programmable I/O Cell ................................................................................................................ 16|
|Figure 3.6. iCE I/O Register Block Diagram ......................................................................................................................... 17|Figure 3.6. iCE I/O Register Block Diagram ......................................................................................................................... 17|
|Figure 4.1. Power Up Sequence with SPI_V|Figure 4.1. Power Up Sequence with SPI_VCCIO1and VPP_2V5Not Connected Together ....................................................... 24|
|Figure 4.2. Power Up Sequence with All Supplies Connected Together ............................................................................. 24|Figure 4.2. Power Up Sequence with All Supplies Connected Together ............................................................................. 24|
|Figure 4.3. Output Test Load, LVCMOS Standards .............................................................................................................. 32|Figure 4.3. Output Test Load, LVCMOS Standards .............................................................................................................. 32|



© 2018-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02027-1.7 

4 

**iCE40 UltraLite Family Data Sheet Data Sheet** 

## **Tables** 

|Table 2.1. iCE40 UltraLite Family Selection Guide ................................................................................................................ 8|Table 2.1. iCE40 UltraLite Family Selection Guide ................................................................................................................ 8|
|---|---|
|Table 3.1. Logic Cell Signal Descriptions ............................................................................................................................. 11|Table 3.1. Logic Cell Signal Descriptions ............................................................................................................................. 11|
|Table 3.2. Global Buffer (GBUF) Connections to Programmable Logic Blocks ................................................................... 11|Table 3.2. Global Buffer (GBUF) Connections to Programmable Logic Blocks ................................................................... 11|
|Table 3.3. PLL Signal Descriptions ....................................................................................................................................... 13|Table 3.3. PLL Signal Descriptions ....................................................................................................................................... 13|
|Table 3.4. sysMEM Block Configurations* .......................................................................................................................... 14|Table 3.4. sysMEM Block Configurations* .......................................................................................................................... 14|
|Table 3.5. EBR Signal Descriptions ...................................................................................................................................... 15|Table 3.5. EBR Signal Descriptions ...................................................................................................................................... 15|
|Table 3.6. PIO Signal List ..................................................................................................................................................... 17|Table 3.6. PIO Signal List ..................................................................................................................................................... 17|
|Table 3.7. Supported Input Standards ................................................................................................................................ 18|Table 3.7. Supported Input Standards ................................................................................................................................ 18|
|Table 3.8. Supported Output Standards ............................................................................................................................. 18|Table 3.8. Supported Output Standards ............................................................................................................................. 18|
|Table 3.9. Current Drive ...................................................................................................................................................... 20|Table 3.9. Current Drive ...................................................................................................................................................... 20|
|Table 3.10. iCE40 UltraLite Power Saving Features Description ......................................................................................... 21|Table 3.10. iCE40 UltraLite Power Saving Features Description ......................................................................................... 21|
|Table 4.1. Absolute Maximum Ratings ............................................................................................................................... 22|Table 4.1. Absolute Maximum Ratings ............................................................................................................................... 22|
|Table 4.2. Recommended Operating Conditions ................................................................................................................ 22|Table 4.2. Recommended Operating Conditions ................................................................................................................ 22|
|Table 4.3. Power Supply Ramp Rates ................................................................................................................................. 23|Table 4.3. Power Supply Ramp Rates ................................................................................................................................. 23|
|Table 4.4. Power-On-Reset Voltage Levels* ....................................................................................................................... 24|Table 4.4. Power-On-Reset Voltage Levels* ....................................................................................................................... 24|
|Table 4.5. DC Electrical Characteristics ............................................................................................................................... 25|Table 4.5. DC Electrical Characteristics ............................................................................................................................... 25|
|Table 4.6. Supply Current|Table 4.6. Supply Current1, 2, 3, 4, 5....................................................................................................................................... 26|
|Table 4.7. Internal Pull-Up Resistor Specifications ............................................................................................................. 26|Table 4.7. Internal Pull-Up Resistor Specifications ............................................................................................................. 26|
|Table 4.8. User I|Table 4.8. User I2C Specifications1...................................................................................................................................... 27|
|Table 4.9. Internal Oscillators (HFOSC, LFOSC) ................................................................................................................... 27|Table 4.9. Internal Oscillators (HFOSC, LFOSC) ................................................................................................................... 27|
|Table 4.10. sysI/O Recommended Operating Conditions ................................................................................................... 27|Table 4.10. sysI/O Recommended Operating Conditions ................................................................................................... 27|
|Table 4.11. sysI/O Single-Ended DC Electrical Characteristics ............................................................................................ 27|Table 4.11. sysI/O Single-Ended DC Electrical Characteristics ............................................................................................ 27|
|Table 4.12. Differential Comparator Electrical Characteristics ........................................................................................... 28|Table 4.12. Differential Comparator Electrical Characteristics ........................................................................................... 28|
|Table 4.13. Maximum sysI/O Buffer Performance|Table 4.13. Maximum sysI/O Buffer Performance1............................................................................................................ 28|
|Table 4.14. iCE40 UltraLite External Switching Characteristics .......................................................................................... 29|Table 4.14. iCE40 UltraLite External Switching Characteristics .......................................................................................... 29|
|Table 4.15. sysCLOCK PLL Timing ........................................................................................................................................ 29|Table 4.15. sysCLOCK PLL Timing ........................................................................................................................................ 29|
|Table 4.16. SPI Master or NVCM Configuration Time ......................................................................................................... 30|Table 4.16. SPI Master or NVCM Configuration Time ......................................................................................................... 30|
|Table 4.17. sysCONFIG Port Timing Specifications ............................................................................................................. 30|Table 4.17. sysCONFIG Port Timing Specifications ............................................................................................................. 30|
|Table 4.18. RGB LED ............................................................................................................................................................ 31|Table 4.18. RGB LED ............................................................................................................................................................ 31|
|Table 4.19. Test Fixture Required Components, Non-Terminated Interfaces .................................................................... 32|Table 4.19. Test Fixture Required Components, Non-Terminated Interfaces .................................................................... 32|



© 2018-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02027-1.7 

5 

m@LATTICE 

**iCE40 UltraLite Family Data Sheet Data Sheet** 

## **Acronyms in This Document** 

A list of acronyms used in this document. 

|**Acronym **|**Definition**|
|---|---|
|DFF|D-style Flip-Flop|
|EBR|Embedded Block RAM|
|HFOSC|High FrequencyOscillator|
|I2C|Inter-Integrated Circuit|
|LFOSC|Low FrequencyOscillator|
|LUT|Look UpTable|
|LVCMOS|Low-Voltage ComplementaryMetal Oxide Semiconductor|
|NVCM|Non Volatile Configuration Memory|
|PFU|Programmable Functional Unit|
|PLB|Programmable Logic Blocks|
|PLL|Phase Locked Loops|
|SPI|Serial Peripheral Interface|
|WLCSP|Wafer Level ChipScale Packaging|



© 2018-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02027-1.7 

6 

**iCE40 UltraLite Family Data Sheet Data Sheet** 

## **1. General Description** 

iCE40 UltraLite™ family from Lattice Semiconductor is an optimum logic, smallest footprint, low I/O count ultra-low power FPGA and sensor manager. It is designed for ultra-low power mobile applications, such as smartphones, tablets and hand-held devices. The iCE40 UltraLite family includes integrated blocks to interface with virtually all mobile sensors and application processors. The iCE40 UltraLite family also features two on-chip oscillators, 10 kHz and 48 MHz. The LFOSC (10 kHz) is ideal for low power function in always-on applications, while HFOSC (48 MHz) can be used for awaken activities. 

The hardened RGB PWM IP, with the three 24 mA constant current RGB LED outputs on the iCE40 UltraLite provides all the necessary logic to directly drive the service LED, without the need of external MOSFET or buffer. 

The 400 mA constant current IR driver output provides a direct interface to external LED for application such as IrDA functions. Users simply implement the hardened TX/RX pulse logic that meets their needs, and connect the IR driver directly to the LED, without the need of external MOSFET or buffer. The 100 mA Barcode Emulation driver output provides a direct interface for applications such as barcode scanning. The 100 mA and 400 mA drivers can also be combined to be used as a 500 mA IR driver if higher than 400 mA current drive is required. 

The iCE40 UltraLite family of devices are targeting for mobile applications to perform functions such as IrDA, Service LED, Barcode Emulation, GPIO Expander, SDIO Level Shift, and other custom functions. 

The iCE40 UltraLite family features two device densities of 640 or 1 K Look Up Tables (LUTs) of logic with programmable I/Os that can be used as an interface port or general purpose I/O. It also has up to 56 kbits of Block RAMs to work with user logic. 

## **1.1. Features** 

- Flexible Logic Architecture 

   - Two devices with 640 or 1K LUTs 

   - Offered in 16-ball WLCSP package 

   - Offered in 36-ball ucBGA package 

- Ultra-low Power Devices 

   - Advanced 40 nm low power process 

   - Typical 35 µA standby current which equals 42 uW standby power consumption 

- Embedded and Distributed Memory 

   - Up to 56 kbits sysMEM™ Embedded Block RAM 

- Two Hardened Interfaces 

   - Two optional FIFO mode I²C interface up to 1 MHz 

   - Either master or slave 

- Two On-Chip Oscillators 

   - Low Frequency Oscillator – 10 kHz 

   - High Frequency Oscillator – 48 MHz 

- Hardened PWM circuit for RGB 

- Hardened TX/RX Pulse Logic circuit for IR LED 

- 24 mA Current Drive RGB LED Outputs 

   - Three drive outputs in each device 

   - User selectable sink current up to 24 mA 

- 400 or 500 mA Current Drive IR LED Output 

   - One IR drive output in each device 

   - User selectable sink current up to 400 mA 

   - Can be combined with 100 mA Barcode driver to form 500 mA IR driver 

- 100 mA Current Drive Barcode Emulator 

   - One barcode driver output in each device 

   - User selectable sink current up to 100 mA 

   - Can be combined with 400 mA IR driver to use as 500 mA IR driver 

- Flexible On-Chip Clocking 

   - Eight low skew global signal resource, six can be directly driven from external pins 

   - One PLL with dynamic interface per device 

- Flexible Device Configuration 

   - SRAM is configured through: 

   - Standard SPI Interface 

   - Internal Nonvolatile Configuration Memory (NVCM) 

- Ultra-Small Form Factor 

   - As small as 1.409 mm × 1.409 mm 

- Applications 

   - Smartphones 

   - Tablets and Consumer Handheld Devices 

   - Multi Sensor Management Applications 

   - IR Remote, Barcode Emulator 

   - RGB Light Control 

© 2018-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02027-1.7 

7 

m@LATTICE 

**iCE40 UltraLite Family Data Sheet Data Sheet** 

## **2. Product Family** 

|**Part Number**<br>~~amae~~|**iCE40UL-640**<br>~~mae~~|**iCE40UL-1K**<br>~~mae~~|
|---|---|---|
|**Logic Cells (LUT + Flip-Flop)**<br>~~mae~~|**640**<br>~~mae~~|**1248**<br>~~mae~~|
|EBR Memory Blocks<br>~~mae~~<br>~~a~~|14<br>~~mae~~<br>~~a~~|14<br>~~mae~~<br>~~a~~|
|EBR Memory Bits (Kbits)<br>~~mae~~<br>~~GC~~|56 k<br>~~mae~~<br>~~GC~~|56 k<br>~~mae~~<br>~~GC~~|
|PLL Block*<br>~~mae~~<br>~~GC~~<br>~~a~~|1<br>~~mae~~<br>~~GC~~<br>~~a~~|1<br>~~mae~~<br>~~GC~~<br>~~a~~|
|Hardened I2C<br>~~mae~~<br>~~a~~|2<br>~~mae~~<br>~~a~~|2<br>~~mae~~<br>~~a~~|
|Hardened IR TX/RX<br>~~mae~~<br>~~a~~|1<br>~~mae~~<br>~~a~~|1<br>~~mae~~<br>~~a~~|
|Hardened RGB PWM IP<br>~~mae~~<br>~~a~~|1<br>~~mae~~<br>~~a~~|1<br>~~mae~~<br>~~a~~|
|HF Oscillator (48 MHz)<br>~~mae~~<br>~~a~~|1<br>~~mae~~<br>~~a~~|1<br>~~mae~~<br>~~a~~|
|LF Oscillator (10 KHz)<br>~~mae~~<br>~~a~~<br>~~a~~|1<br>~~mae~~<br>~~a~~<br>~~a~~|1<br>~~mae~~<br>~~a~~<br>~~a~~|
|24 mA LED Sink<br>~~mae~~<br>~~GC~~|3<br>~~mae~~<br>~~GC~~|3<br>~~mae~~<br>~~GC~~|
|100 mA LED Sink<br>~~mae~~<br>~~GC~~<br>~~a~~|1<br>~~mae~~<br>~~GC~~|1<br>~~mae~~<br>~~GC~~|
|400 mA LED Sink<br>~~mae~~<br>~~GD~~|1<br>~~mae~~<br>~~GD~~|1<br>~~mae~~<br>~~GD~~|
|**Packages, ball pitch, dimension**<br>~~mae~~<br>~~GD~~<br>~~a~~|**Programmable I/O Count**<br>~~mae~~<br>~~GD~~<br>~~a~~||
|16-ball WLCSP, 0.35 mm, 1.409 mm x 1.409 mm<br>~~mae~~<br>~~a~~|10<br>~~mae~~<br>~~a~~|10<br>~~mae~~<br>~~a~~|
|36-ball ucBGA, 0.40 mm, 2.5 mm x 2.5 mm<br>~~mae~~<br>~~a~~|26<br>~~mae~~<br>~~a~~|26<br>~~mae~~<br>~~a~~|



The iCE40 UltraLite devices are fabricated on a 40 nm CMOS low power process. The device architecture has several features such as user configurable RGB LED and IR LED Controllers, and two Oscillators. 

The iCE40 UltraLite FPGAs are available in very small form factor packages, as small as 1.409 mm x 1.409 mm. The small form factor allows the device to easily fit into a lot of mobile applications. Table 2.1 shows the LUT densities, package and I/O pin count. 

The iCE40 UltraLite devices offer I/O features such as programmable multiple value pull-up resistors. Pull-up features are controllable on a per-pin basis. 

The iCE40 UltraLite devices also provide flexible, reliable and secure configuration from on-chip NVCM. These devices can also configure themselves from external SPI Flash, or be configured by an external master such as a CPU. 

Lattice provides a variety of design tools that allow complex designs to be efficiently implemented using the iCE40 UltraLite family of devices. Popular logic synthesis tools provide synthesis library support for iCE40 UltraLite. Lattice design tools use the synthesis tool output along with the user-specified preferences and constraints to place and route the design in the iCE40 UltraLite device. These tools extract the timing from the routing and back-annotate it into the design for timing verification. 

Lattice provides many pre-engineered IP (Intellectual Property) modules, including a number of reference designs, licensed free of charge, optimized for the iCE40 UltraLite FPGA family. Lattice also can provide fully verified bitstream for some of the widely used target functions in mobile device applications, such as ultra-low power sensor management, gesture recognition, IR remote, barcode emulator functions. Users can use these functions as offered by Lattice, or they can use the design to create their own unique required functions. For more information regarding Lattice's reference designs or fully-verified bitstreams, contact your local Lattice representative. 

© 2018-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

8 

FPGA-DS-02027-1.7 

**iCE40 UltraLite Family Data Sheet Data Sheet** 

## **3. Architecture** 

## **3.1. Architecture Overview** 

The iCE40 UltraLite family architecture contains an array of Programmable Logic Blocks (PLB), two Oscillator Generators, two user configurable I[2] C controllers, two user configurable SPI controllers, blocks of sysMEM™ Embedded Block RAM (EBR) and Single Port RAM (SPRAM) surrounded by Programmable I/O (PIO). Figure 3.1 shows the block diagram of the iCE40UL-1K device. 

**==> picture [152 x 233] intentionally omitted <==**

**----- Start of picture text -----**<br>
2<br>s || jae LD<br>Ne e<br>a<br>|) eo<br>AS<br>H y()<br>AaFS n "<br>Carry Logic fp)<br>4-Input Look-up<br>Table (LUT) Flip-flop with Enable<br>and Reset Controls<br>8 Logic Cells = Programmable Logic Block<br>**----- End of picture text -----**<br>


**Figure 3.1. iCE40UL-1K Device, Top View** 

The logic blocks, Programmable Logic Blocks (PLB) and sysMEM EBR blocks, are arranged in a two-dimensional grid with rows and columns. Each column has either PLB or EBR blocks. The PIO cells are located at the top and bottom of the device, arranged in banks. The PLB contains the building blocks for logic, arithmetic, and register functions. The PIOs utilize a flexible I/O buffer referred to as a sysI/O™ buffer that supports operation with a variety of interface standards. The blocks are connected with many vertical and horizontal routing channel resources. The place and route software tool automatically allocates these routing resources. 

In the iCE40 UltraLite family, there are three sysI/O banks, one on top and two at the bottom. User can connect all VCCIOs together, if all the I/Os are using the same voltage standard. Refer to the details in later sections of this document. The sysMEM EBRs are large 4 kbit, dedicated fast memory blocks. These blocks can be configured as RAM, ROM or FIFO with user logic using PLBs. 

The iCE40 UltraLite also includes two user I[2] C ports, two Oscillators, and high current RGB and IR LED sinks, and a 100 mA Barcode emulation output. 

© 2018-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02027-1.7 

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## **3.1.1. PLB Blocks** 

The core of the iCE40 UltraLite device consists of Programmable Logic Blocks (PLB) which can be programmed to perform logic and arithmetic functions. Each PLB consists of eight interconnected Logic Cells (LC) as shown in Figure 3.2 Each LC contains one LUT and one register. 

**==> picture [366 x 267] intentionally omitted <==**

**----- Start of picture text -----**<br>
Shared Block-Level Controls<br>Programmable  Clock<br>Logic Block (PLB)<br>Enable<br>FCOUT 1<br>Set/Reset<br>a D e 0 Logic Cell<br>Carry Logic<br>DFF O<br>I0 D Q<br>EN<br>I1<br>LUT SR<br>I2<br>I3<br>| / =<br>FCIN<br>Four-input Flip-flop with<br>Look-Up Table optional enable and<br>(LUT) set or reset controls<br>= Statically defined by configuration program<br>8 Logic Cells (LCs)<br>**----- End of picture text -----**<br>


**Figure 3.2. PLB Block Diagram** 

## **3.1.1.1. Logic Cells** 

Each Logic Cell includes three primary logic elements shown in Figure 3.2. 

- A four-input Look-Up Table (LUT) builds any combinational logic function, of any complexity, requiring up to four inputs. Similarly, the LUT element behaves as a 16x1 Read-Only Memory (ROM). Combine and cascade multiple LUTs to create wider logic functions. 

- A D-style Flip-Flop (DFF), with an optional clock-enable and reset control input, builds sequential logic functions. Each DFF also connects to a global reset signal that is automatically asserted immediately following device configuration. 

- Carry Logic boosts the logic efficiency and performance of arithmetic functions, including adders, subtracters, comparators, binary counters and some wide, cascaded logic functions. 

Table 3.1 lists the logic cell signals. 

© 2018-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

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**Table 3.1. Logic Cell Signal Descriptions** 

|**Function**|**Type**|**Signal Name**|**Description**|
|---|---|---|---|
|Input|Data signal|I0, I1, I2, I3|Inputs to LUT|
|Input|Control signal|Enable|Clock enable shared by all LCs in the PLB|
|Input|Control signal|Set/Reset*|Asynchronous or synchronous local set/reset shared by<br>all LCs in the PLB.|
|Input|Control signal|Clock|Clock one of the eight Global Buffers, or from the<br>general-purpose interconnects fabric shared by all LCs<br>in the PLB.|
|Input|Inter-PLB signal|FCIN|Fast carry in|
|Output|Data signals|O|LUT or registered output|
|Output|Inter-PFU signal|FCOUT|Fast carry out|



* **Note** : If Set/Reset is not used, then the flip-flop is never set/reset, except when cleared immediately after configuration. 

## **3.1.2. Routing** 

There are many resources provided in the iCE40 UltraLite devices to route signals individually with related control signals. The routing resources consist of switching circuitry, buffers and metal interconnect (routing) segments. The inter-PLB connections are made with three different types of routing resources: Adjacent (spans two PLBs), x4 (spans five PLBs) and x12 (spans thirteen PLBs). The adjacent, x4 and x12 connections provide fast and efficient connections in the diagonal, horizontal and vertical directions. 

The design tool takes the output of the synthesis tool and places and routes the design. 

## **3.1.3. Clock/Control Distribution Network** 

Each iCE40 UltraLite device has six global inputs, two pins on the top bank and four pins on the bottom bank. 

These global inputs can be used as high fanout nets, clock, reset or enable signals. The dedicated global pins are identified as Gxx and each drives one of the eight global buffers. The global buffers are identified as GBUF[7:0]. These six inputs may be used as general purpose I/O if they are not used to drive the clock nets. 

Table 3.2 lists the connections between a specific global buffer and the inputs on a PLB. All global buffers optionally connect to the PLB CLK input. Any four of the eight global buffers can drive logic inputs to a PLB. Even-numbered global buffers optionally drive the Set/Reset input to a PLB. Similarly, odd-numbered buffers optionally drive the PLB clockenable input. GBUF[7:6, 3:0] can connect directly to G[7:6, 3:0] pins respectively. GBUF4 and GBUF5 can connect to the two on-chip Oscillator Generators (GBUF4 connects to LFOSC, GBUF5 connects to HFOSC). 

**Table 3.2. Global Buffer (GBUF) Connections to Programmable Logic Blocks** 

|**Global Buffer**|**LUT Inputs**|**Clock**|**Reset**|**Clock Enable**|
|---|---|---|---|---|
|GBUF0|Yes, any 4 of 8 GBUF<br>Inputs|Yes|Yes|—|
|GBUF1||Yes|—|Yes|
|GBUF2||Yes|Yes|—|
|GBUF3||Yes|—|Yes|
|GBUF4||Yes|Yes|—|
|GBUF5||Yes|—|Yes|
|GBUF6||Yes|Yes|—|
|GBUF7||Yes|—|Yes|



The maximum frequency for the global buffers are listed in Table 4.14. 

© 2018-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

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## **3.1.3.1. Global Hi-Z Control** 

The global high-impedance control signal, GHIZ, connects to all I/O pins on the iCE40 UltraLite device. This GHIZ signal is automatically asserted throughout the configuration process, forcing all user I/O pins into their high-impedance state. 

## **3.1.3.2. Global Reset Control** 

The global reset control signal connects to all PLB and PIO flip-flops on the iCE40 UltraLite device. The global reset signal is automatically asserted throughout the configuration process, forcing all flip-flops to their defined wake-up state. For PLB flip-flops, the wake-up state is always reset, regardless of the PLB flip-flop primitive used in the application. 

## **3.1.4. sysCLOCK Phase Locked Loops (PLLs) (sysCLOCK PLL is only supported in 36-ball ucBGA package)** 

The sysCLOCK PLLs provide the ability to synthesize clock frequencies. The iCE40 UltraLite devices have one sysCLOCK PLL. REFERENCECLK is the reference frequency input to the PLL and its source can come from an external I/O pin, the internal Oscillator Generators from internal routing. EXTFEEDBACK is the feedback signal to the PLL which can come from internal routing or an external I/O pin. The feedback divider is used to multiply the reference frequency and thus synthesize a higher frequency clock output. 

The PLLOUT output has an output divider, thus allowing the PLL to generate different frequencies for each output. The output divider can have a value from 1 to 64 (in increments of 2X). The PLLOUT outputs can all be used to drive the iCE40 UltraLite global clock network directly or general purpose routing resources can be used. 

The LOCK signal is asserted when the PLL determines it has achieved lock and de-asserted if a loss of lock is detected. A block diagram of the PLL is shown in Figure 3.3. 

The timing of the device registers can be optimized by programming a phase shift into the PLLOUT output clock which will advance or delay the output clock with reference to the REFERENCECLK clock. This phase shift can be either programmed during configuration or can be adjusted dynamically. In dynamic mode, the PLL may lose lock after a phase adjustment on the output used as the feedback source and not relock until the tLOCK parameter has been satisfied. For more details, refer to iCE40 sysCLOCK PLL Design and Usage Guide (FPGA-TN-02052). 

**==> picture [448 x 198] intentionally omitted <==**

**----- Start of picture text -----**<br>
RESET<br>BYPASS<br>BYPASS<br>GNDPLL VCCPLL<br>Phase<br>REFERENCECLK DIVR Detector RANGE Voltage  DIVQ<br>Input  Low-Pass  Controlled  VCO<br>Divider Filter Oscillator  Divider<br>(VCO)<br>SIMPLE<br>DIVF<br>PLLOUTCORE<br>Feedback Divider Fine Delay<br>Fine Delay Adjustment<br>Adjustment Shifter Phase  Output Port PLLOUTGLOBAL<br>Feedback<br>Feedback_Path<br>DYNAMICDELAY[7:0] LOCK<br>EXTFEEDBACK EXTERNAL<br>LATCHINPUTVALUE Low Power mode<br>(iCEgate enabled)<br>**----- End of picture text -----**<br>


**Figure 3.3. PLL Diagram** 

© 2018-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

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Table 3.3 provides signal descriptions of the PLL block. 

**Table 3.3. PLL Signal Descriptions** 

|**Signal Name**|**Direction**|**Description**|
|---|---|---|
|REFERENCECLK|Input|Input reference clock|
|BYPASS|Input|The BYPASS control selects which clock signal connects to the PLLOUT output.<br>0 – PLL generated signal<br>1 – REFERENCECLK|
|EXTFEEDBACK|Input|External feedback input to PLL. Enabled when the FEEDBACK_PATH attribute is set<br>to EXTERNAL.|
|DYNAMICDELAY[7:0]|Input|Fine delay adjustment control inputs. Enabled when DELAY_ADJUSTMENT_MODE<br>is set to DYNAMIC.|
|LATCHINPUTVALUE|Input|When enabled, puts the PLL into low-power mode; PLL output is held static at the<br>last input clock value. Set ENABLE ICEGATE_PORTA and PORTB to 1 to enable.|
|PLLOUTGLOBAL|Output|Output from the Phase-Locked Loop (PLL). Drives a global clock network on the<br>FPGA. The port has optimal connections to global clock buffers GBUF4 and GBUF5.|
|PLLOUTCORE|Output|Output clock generated by the PLL, drives regular FPGA routing. The frequency<br>generated on this output is the same as the frequency of the clock signal generated<br>on the PLLOUTLGOBALport.|
|LOCK|Output|When High, indicates that the PLL output is phase aligned or locked to the input<br>reference clock.|
|RESET|Input|Active low reset.|
|SCLK|Input|Input, Serial Clock used for re-programming PLL settings.|
|SDI|Input|Input, Serial Data used for re-programming PLL settings.|



## **3.1.5. sysMEM Embedded Block RAM Memory** 

Larger iCE40 UltraLite device includes multiple high-speed synchronous sysMEM Embedded Block RAMs (EBRs), each 4 kbit in size. This memory can be used for a wide variety of purposes including data buffering and FIFO. 

## **3.1.5.1. sysMEM Memory Block** 

The sysMEM block can implement single port, pseudo dual port, or FIFO memories with programmable logic resources. Each block can be used in a variety of depths and widths as listed in Table 3.4. 

© 2018-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

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**Table 3.4. sysMEM Block Configurations*** 

|**Block RAM**<br>**Configuration**|**Block RAM**<br>**Configuration**<br>**and Size**|**WADDR Port**<br>**Size (Bits)**|**WDATA Port**<br>**Size (Bits)**|**RADDR Port**<br>**Size (Bits)**|**RDATA Port**<br>**Size (Bits)**|**MASK Port**<br>**Size (Bits)**|
|---|---|---|---|---|---|---|
|SB_RAM256x16<br>SB_RAM256x16NR<br>SB_RAM256x16NW<br>SB_RAM256x16NRNW|256 x 16 (4 K)|8 [7:0]|16 [15:0]|8 [7:0]|16 [15:0]|16 [15:0]|
|SB_RAM512x8<br>SB_RAM512x8NR<br>SB_RAM512x8NW<br>SB_RAM512x8NRNW|512 x 8 (4 K)|9 [8:0]|8 [7:0]|9 [8:0]|8 [7:0]|No Mask Port|
|SB_RAM1024x4<br>SB_RAM1024x4NR<br>SB_RAM1024x4NW<br>SB_RAM1024x4NRNW|1024 x 4 (4 K)|10 [9:0]|4 [3:0]|10 [9:0]|4 [3:0]|No Mask Port|
|SB_RAM2048x2<br>SB_RAM2048x2NR<br>SB_RAM2048x2NW<br>SB_RAM2048x2NRNW|2048 x 2 (4 K)|11 [10:0]|2 [1:0]|11 [10:0]|2 [1:0]|No Mask Port|



***Note** : For iCE40 UltraLite, the primitive name without Nxx uses rising-edge Read and Write clocks. NR uses rising-edge Write clock and falling-edge Read clock. NW uses falling-edge Write clock and rising-edge Read clock. NRNW uses failing-edge clocks on both Read and Write. 

## **3.1.5.2. RAM Initialization and ROM Operation** 

If desired, the contents of the RAM can be pre-loaded during device configuration. 

By preloading the RAM block during the chip configuration cycle and disabling the write controls, the sysMEM block can also be utilized as a ROM. 

## **3.1.5.3. Memory Cascading** 

Larger and deeper blocks of RAM can be created using multiple EBR sysMEM Blocks. 

## **3.1.5.4. RAM4K Block** 

Figure 3.4 shows the 256 x 16 memory configurations and their input/output names. In all the sysMEM RAM modes, the input data and addresses for the ports are registered at the input of the memory array. 

**==> picture [264 x 186] intentionally omitted <==**

**----- Start of picture text -----**<br>
W tir e P o r t R e a d P o r t<br> oa<br>WDATA[15:0] RDATA[15:0]<br>MASK[15:0]<br>WADDR[7:0] RADDR[7:0]<br>RAM4K<br>RAM Block<br>WE (256 x 16) RE<br>WCLKE RCLKE<br>WCLK RCLK<br>**----- End of picture text -----**<br>


**Figure 3.4. sysMEM Memory Primitives** 

© 2018-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

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Table 3.5 lists the EBR signals. 

**Table 3.5. EBR Signal Descriptions** 

|**Signal Name**|**Direction**|**Description**|
|---|---|---|
|WDATA[15:0]|Input|Write Data input.|
|MASK[15:0]|Input|Masks write operations for individual data bit-lines.<br>0 – Write bit<br>1 – Do not write bit|
|WADDR[7:0]|Input|Write Address input. Selects one of 256 possible RAM locations.|
|WE|Input|Write Enable input.|
|WCLKE|Input|Write Clock Enable input.|
|WCLK|Input|Write Clock input. Default rising-edge, but with falling-edge option.|
|RDATA[15:0]|Output|Read Data output.|
|RADDR[7:0]|Input|Read Address input. Selects one of 256 possible RAM locations.|
|RE|Input|Read Enable input.|
|RCLKE|Input|Read Clock Enable input.|
|RCLK|Input|Read Clock input. Default rising-edge, but with falling-edge option.|



For further information on the sysMEM EBR block, refer to Memory Usage Guide for iCE40 Devices (FPGA-TN-02002). 

## **3.1.6. sysI/O Buffer Banks** 

iCE40 UltraLite devices have up to three I/O banks with independent VCCIO rails. The configuration SPI interface signals are powered by SPI_VCCIO1. On the 16 WLCSP package, VCCIO1 and VPP_2V5 are connected to the same pin on the package, and must meet the voltage requirement of both supplies. Refer to the Pin Information Summary table. 

## **3.1.6.1. Programmable I/O (PIO)** 

The programmable logic associated with an I/O is called a PIO. The individual PIOs are connected to their respective sysI/O buffers and pads. The PIOs are placed on the top and bottom of the devices. 

© 2018-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

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**Figure 3.5. I/O Bank and Programmable I/O Cell** 

The PIO contains three blocks: an input register block, output register block iCEGate™ and tri-state register block. To save power, the optional iCEGate latch can selectively freeze the state of individual, non-registered inputs within an I/O bank. Note that the freeze signal is common to the bank. These blocks can operate in a variety of modes along with the necessary clock and selection logic. 

## **3.1.6.2. Input Register Block** 

The input register blocks for the PIOs on all edges contain registers that can be used to condition high-speed interface signals before they are passed to the device core. 

## **3.1.6.3. Output Register Block** 

The output register block can optionally register signals from the core of the device before they are passed to the sysI/O buffers. 

Figure 3.6 shows the input/output register block for the PIOs. 

© 2018-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

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**==> picture [335 x 421] intentionally omitted <==**

**----- Start of picture text -----**<br>
CLOCK_ENABLE PIO Pair<br>OUTPUT_CLK<br>INPUT_CLK<br>(1,0)<br>LATCH_INPUT_VALUE<br>D_IN_1<br>D_IN_0 Ena<br>Pad<br>D_OUT_1<br>D_OUT_0<br>(1,0)<br>0<br>1<br>OUTPUT_ENABLE dL.<br>(1,0)<br>LATCH_INPUT_VALUE<br>D_IN_1<br>az)<br>D_IN_0 ap<br>Pad<br>D_OUT_1<br>D_OUT_0<br>(1,0)<br>0<br>1<br>OUTPUT_ENABLE<br>= Statically defined by configuration program.<br>**----- End of picture text -----**<br>


**Figure 3.6. iCE I/O Register Block Diagram** 

**Table 3.6. PIO Signal List** 

|**Pin Name**|**I/O Type**|**Description**|
|---|---|---|
|OUTPUT_CLK|Input|Output register clock|
|CLOCK_ENABLE|Input|Clock enable|
|INPUT_CLK|Input|Input register clock|
|OUTPUT_ENABLE|Input|Output enable|
|D_OUT_0/1|Input|Data from the core|
|D_IN_0/1|Output|Data to the core|
|LATCH_INPUT_VALUE|Input|Latches/holds the Input Value|



© 2018-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

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## **3.1.7. sysI/O Buffer** 

Each I/O is associated with a flexible buffer referred to as a sysI/O buffer. These buffers are arranged around the periphery of the device in groups referred to as banks. The sysI/O buffers allow users to implement a wide variety of standards that are found in today’s systems with LVCMOS interfaces. 

## **3.1.7.1. Typical I/O Behavior During Power-up** 

The internal power-on-reset (POR) signal is deactivated when VCC, SPI_VCCIO1 and VPP_2V5 reach the level defined in Table 4.4. After the POR signal is deactivated, the FPGA core logic becomes active. You must ensure that all VCCIO banks are active with valid input logic levels to properly control the output logic states of all the I/O banks that are critical to the application. The default configuration of the I/O pins in a device prior to configuration is tri-stated with a weak pull-up to VCCIO. The I/O pins maintain the pre-configuration state until VCC, SPI_VCCIO1 and VPP_2V5 reach the defined levels. The I/Os take on the software user-configured settings only after POR signal is deactivated and the device performs a proper download/configuration. Unused I/Os are automatically blocked and the pull-up termination is disabled. 

## **3.1.7.2. Supported Standards** 

The iCE40 UltraLite sysI/O buffer supports both single-ended input/output standards, and used as differential comparators. The buffer supports the LVCMOS 1.8 V, 2.5 V, and 3.3 V standards. The buffer has individually configurable options for bus maintenance (weak pull-up or none). 

Table 3.7 and Table 3.8 show the I/O standards (together with their supply and reference voltages) supported by the iCE40 UltraLite devices. 

## **3.1.7.3. Programmable Pull Up Resistors** 

The iCE40 UltraLite sysI/O buffer can be configured with programmable pull up resistors on every I/O. The options are 3.3 kΩ, 6.8 kΩ, 10 kΩ, or 100 kΩ (default). This feature is useful in supporting the I²C interface. The user can also use it for other purposes. 

## **3.1.7.4. Differential Comparators** 

The iCE40 UltraLite devices provide differential comparator on pairs of I/O pins. These comparators are useful in some mobile applications. See the Pin Information Summary section to locate the corresponding paired I/Os with differential comparators. 

**Table 3.7. Supported Input Standards** 

|**Input Standard**|**VCCIO(Typical)**|**VCCIO(Typical)**|**VCCIO(Typical)**|
|---|---|---|---|
||**3.3 V**|**2.5 V**|**1.8 V**|
|**Single-Ended Interfaces**||||
|LVCMOS33|Yes|—|—|
|LVCMOS25|—|Yes|—|
|LVCMOS18*|—|—|Yes|



***Note** : Not supported in Bank 0 for 16-WLCP package. 

**Table 3.8. Supported Output Standards** 

|**Output Standard**|**VCCIO(Typical)**|
|---|---|
|**Single-Ended Interfaces**||
|LVCMOS33|3.3 V|
|LVCMOS25|2.5 V|
|LVCMOS18*|1.8 V|



***Note** : Not supported in Bank 0 for 16-WLCP package. 

© 2018-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

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## **3.1.8. On-Chip Oscillator** 

The iCE40 UltraLite devices feature two different frequency Oscillator. One is tailored for low-power operation that runs at low frequency (LFOSC). Both Oscillators are controlled with internally generated current. 

The LFOSC runs at nominal frequency of 10 kHz. The high frequency oscillator (HFOSC) runs at a nominal frequency of 48 MHz, divisible to 24 MHz, 12 MHz, or 6 MHz by user option. The LFOSC can be used to perform all always-on functions, with the lowest power possible. The HFOSC can be enabled when the always-on functions detect a condition that would need to wake up the system to perform higher frequency functions. 

## **3.1.9. User I[2] C IP** 

The iCE40 UltraLite devices have two I[2] C IP cores. Either of the two cores can be configured either as an I[2] C master or as an I[2] C slave. The pins for the I[2] C interface are not pre-assigned. User can use any General Purpose I/O pins. 

In each of the two cores, there are options to delay the either the input or the output, or both, by 50 ns nominal, using dedicated on-chip delay elements. This provides an easier interface with any external I[2] C components. 

In optional FIFO mode, FIFOs are used for storing multiple bytes of data for transmit and / or receive in order to efficiently support the I[2] C sensor applications. 

When the IP core is configured as master, it will be able to control other devices on the I[2] C bus through the preassigned pin interface. When the core is configured as the slave, the device will be able to provide I/O expansion to an I[2] C Master. The I[2] C cores support the following functionality: 

- Master and Slave operation 

- 7-bit and 10-bit addressing 

- Multi-master arbitration support 

- Clock stretching 

- Up to 1 MHz data transfer speed 

- General Call support 

- Optionally delaying input or output data, or both 

- Optional FIFO mode 

- Transmit FIFO size is 10 bits x 16 bytes, receive FIFO size is 10 bits x 32 bytes 

For further information on the User I[2] C, refer to iCE40 SPI/I2C Hardened IP Usage Guide (FPGA-TN-02010). 

## **3.1.10. High Current LED Drive I/O Pins** 

The iCE40 UltraLite family devices offer multiple high current LED drive outputs in each device in the family to allow the iCE40 UltraLite product to drive LED signals directly on mobile applications. 

There are three outputs on each device that can sink up to 24 mA current. These outputs are open-drain outputs, and provides sinking current to an LED connecting to the positive supply. These three outputs are designed to drive the RBG LEDs, such as the service LED found in a lot of mobile devices. An embedded RGB PWM IP is also offered in the family. This RGB drive current is user programmable from 4 mA to 24 mA, in increments of 4 mA in full current mode or from 2 mA to 12 mA, in increments of 2 mA in half current mode. This output functions as General Purpose I/O with opendrain when the high current drive is not needed. 

There is one output on each device that can sink up to 100 mA current. This output is open-drain, and provides sinking current to drive an external Barcode LED connecting to the positive supply. This Barcode drive current is user programmable from 16.6 mA to100 mA in increments of 16.6 mA in full current mode or 8.3 mA to 50 mA in increments of 8.3 mA in half current mode. This output functions as General Purpose I/O with open drain when the high current drive is not needed. 

There is one output on each device that can sink up to 400 mA current. This output is open-drain, and provides sinking current to drive an external IR LED connecting to the positive supply. This IR drive current is user programmable from 50 mA to 400 mA in increments of 50 mA in full current mode or from 25 mA to 200 mA in increments of 25 mA in half current mode. This output functions as General Purpose I/O with open-drain when the high current drive is not needed. This output pin can also bond together with the Barcode output to drive higher current for IR LED. The 400 mA IR LED drive output and the 100 mA Barcode LED drive output can be connected together to drive up to 500 mA IR LED, if higher than 400 mA driving capability is needed. 

© 2018-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

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Table 3.9 shows the different LED driving current in the different selected Current Modes. IR500 LED applies with both IR LED and Barcode LED pins connected together. 

**Table 3.9. Current Drive** 

||**Full Current Mode**|**Full Current Mode**|**Half Current Mode**|**Half Current Mode**|
|---|---|---|---|---|
||**mA(VCCIO = 3.3 V)**|**mA(VCCIO=2.5 V)**|**mA(VCCIO= 3.3 V)**|**mA(VCCIO=2.5 V)**|
|RGB LED|0, 4, 8, 12, 16, 20, 24|Not allowed|0, 2, 4, 6, 8, 10, 12|0, 2, 4, 6, 8, 10, 12|
|BARCODE LED|0, 16.6, 33.3, 50, 66.6,<br>83.3, 100|Not allowed|0, 8.3, 16.6, 25, 33.3,<br>41.6, 50|Not allowed|
|IR400 LED|0, 50, 100, 150, 200,<br>250, 300, 350, 400|Not allowed|0, 25, 50, 75, 100, 125,<br>150, 175, 200|0, 25, 50, 75, 100, 125,<br>150, 175, 200|
|IR500 LED|0, 50, 100, 150, 200,<br>250, 300, 350, 400,<br>450, 500|Not allowed|0, 25, 50, 75, 100, 125,<br>150, 175, 200, 225, 250|0, 25, 50, 75, 100, 125,<br>150, 175, 200, 225, 250|



## **3.1.11. Hardened RGB PWM IP** 

To provide an easier usage of the RGB high current drivers to drive RGB LED, a Pulse-Width Modulator IP can be used in the user design. This PWM IP provides the flexibility for user to dynamically change the modulation width of each of the RGB LED driver, which changes the color.  Also, the user can dynamically change the settings on the ON-time duration, OFF-time duration, and ability to turn the LED lights on and off gradually with user set breath-on and breathoff time. 

For additional information on the PWM IP, refer to iCE40 LED Driver Usage Guide (FPGA-TN-02021). 

## **3.1.12. Hardened IR Transceiver IP** 

The IR Transceiver hard IP provides logic function to transmit and receive data through the Infrared LED data link. It takes the data residing inside the FPGA fabric to transmit with user specified frequency. In user enabled learning mode, it receives data from Infrared receiver and send the received data back to the FPGA fabric along with the measured receiving frequency.. 

For additional information on IR Transceiver IP, refer to iCE40 LED Driver Usage Guide (FPGA-TN-02021). 

## **3.1.13. Non-Volatile Configuration Memory** 

All iCE40 UltraLite devices provide a Non-Volatile Configuration Memory (NVCM) block which can be used to configure the device. 

For more information on the NVCM, refer to iCE40 Programming and Configuration (FPGA-TN-02001). 

## **3.1.14. Power On Reset** 

iCE40 UltraLite devices have power-on reset circuitry to monitor VCC, SPI_VCCIO1 and VPP_2V5 voltage levels during powerup and operation. At power-up, the POR circuitry monitors these voltage levels. It then triggers download from either the internal NVCM or the external Flash memory after reaching the power-up levels specified in the Power-On-Reset Voltage table in the DC and Switching Characteristics section of this data sheet. All power supplies should be powered up during configuration. Before and during configuration, the I/Os are held in tri-state. I/Os are released to user functionality once the device has finished configuration. 

© 2018-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

20 

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## **3.2. iCE40 UltraLite Programming and Configuration** 

This section describes the programming and configuration of the iCE40 UltraLite family. 

## **3.2.1. Device Programming** 

The NVCM memory can be programmed through the SPI port. The SPI port is located in Bank 1, using SPI_VCCIO1 power supply. 

## **3.2.2. Device Configuration** 

There are various ways to configure the Configuration RAM (CRAM), using SPI port, including: 

- From an SPI Flash (Master SPI mode) 

- System microprocessor to drive a Serial Slave SPI port (SSPI mode) 

For more details on configuring the iCE40 UltraLite, refer to iCE40 Programming and Configuration (FPGA-TN-02001) 

## **3.2.3. Power Saving Options** 

The iCE40 UltraLite devices feature iCEGate and PLL low power mode to allow users to meet the static and dynamic power requirements of their applications. Table 3.10 describes the function of these features. 

**Table 3.10. iCE40 UltraLite Power Saving Features Description** 

|**Device Subsystem**|**Feature Description**|
|---|---|
|PLL|When LATCHINPUTVALUE is enabled, it forces the PLL into low-power mode; PLL output is held static<br>at last input clock value.|
|iCEGate|To save power, the optional iCEGate latch can selectively freeze the state of individual, non-registered<br>inputs within an I/O bank. Registered inputs are effectively frozen by their associated clock or clock-<br>enable control.|



© 2018-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02027-1.7 

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**iCE40 UltraLite Family Data Sheet Data Sheet** 

## **4. DC and Switching Characteristics** 

## **4.1. Absolute Maximum Ratings** 

**Table 4.1. Absolute Maximum Ratings** 

|**Parameter**|**Min**|**Max**|**Unit**|
|---|---|---|---|
|Supply Voltage VCC|–0.5|1.42|V|
|Output SupplyVoltageVCCIO|–0.5|3.60|V|
|NVCM SupplyVoltageVPP_2V5|–0.5|3.60|V|
|PLL SupplyVoltageVCCPLL|–0.5|1.30|V|
|I/O Tri-state Voltage Applied|–0.5|3.60|V|
|Dedicated Input Voltage Applied|–0.5|3.60|V|
|Storage Temperature(Ambient)|–65|150|°C|
|Junction Temperature(TJ)|–65|125|°C|



**Notes** : 

- Stress above those listed under Absolute Maximum Ratings may cause permanent damage to the device. Functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. 

- Compliance with Thermal Management document is required. 

- All voltages referenced to GND. 

## **4.2. Recommended Operating Conditions** 

**Table 4.2. Recommended Operating Conditions** 

|**Symbol**<br>~~es~~|**Parameter**<br>~~(en~~|**Parameter**<br>~~(en~~|**Min**<br>~~OO~~|**Max**<br>~~OO~~|**Unit**|
|---|---|---|---|---|---|
|VCC<br>1<br>~~es~~<br>~~a~~|Core Supply Voltage<br>~~(en~~||1.14<br>~~OO~~|1.26<br>~~OO~~|V|
|VPP_2V5|VPP_2V5NVCM<br>Programming and<br>Operating Supply Voltage|Slave SPI Configuration<br>~~Ge~~|1.714<br>~~Ge~~|3.46<br>~~Ge~~|V<br>~~Ge~~|
|||Master SPI Configuration<br>~~Ge~~|2.30<br>~~Ge~~|3.46<br>~~Ge~~|V<br>~~Ge~~|
|||Configuration from NVCM<br>~~ed~~|2.30<br>~~ed~~|3.46<br>~~ed~~|V<br>~~ed~~|
|||NVCM Programming<br>~~ed~~<br>~~Ge~~|2.30<br>~~ed~~<br>~~Ge~~|3.00<br>~~ed~~<br>~~Ge~~|V<br>~~ed~~<br>~~Ge~~|
|VCCIO1, 2, 3<br>~~CG~~|I/O Driver Supply Voltage<br>~~CG~~|VCCIO_0, SPI_VCCIO1, VCCIO_2<br>~~Ge~~<br>~~CG~~|1.71<br>~~Ge~~<br>~~CG~~|3.46<br>~~Ge~~<br>~~CG~~|V<br>~~Ge~~<br>~~CG~~|
|VCCPLL<br>~~a~~|PLL Supply Voltage||1.14|1.26|V|
|tJCOM<br>~~a~~<br>~~a~~|Junction Temperature Commercial Operation<br>~~Ge~~||0<br>~~Ge~~|85<br>~~Ge~~|°C<br>~~Ge~~|
|tJIND<br>~~a~~<br>~~a~~|Junction Temperature Industrial Operation<br>~~Ge~~<br>~~a~~||–40<br>~~Ge~~<br>~~a~~|100<br>~~Ge~~<br>~~a~~|°C<br>~~Ge~~<br>~~a~~|
|tPROG<br>~~a~~|Junction Temperature NVCM Programming<br>~~a~~||10<br>~~a~~|30<br>~~a~~|°C<br>~~a~~|



1. Like power supplies must be tied together if they are at the same supply voltage and they meet the power up sequence requirement. See the Power-up Supply Sequence section.[V] CC and[V] CCPLL are recommended to be tied together to the same supply with an RC-based noise filter between them. Refer to iCE40 Hardware Checklist (FPGA-TN-02006). 

2. See recommended voltages by I/O standard in subsequent table. 

3. VCCIO pins of unused I/O banks should be connected to the VCC power supply on boards. 

4. VPP_2V5 can, optionally, be connected to a 1.8 V (+/-5%) power supply in Slave SPI Configuration modes subject to the condition that none of the HFOSC/LFOSC and RGB LED driver features are used. Otherwise,[V] PP_2V5 must be connected to a power supply with a minimum 2.30 V level. 

© 2018-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

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**iCE40 UltraLite Family Data Sheet Data Sheet** 

## **4.3. Power Supply Ramp Rates** 

## **Table 4.3. Power Supply Ramp Rates** 

|**Symbol**|**Parameter**|**Min**|**Max**|**Unit**|
|---|---|---|---|---|
|tRAMP|Power supply ramp rates for all power supplies|0.6|10|V/ms|



**Notes** : 

- Assumes monotonic ramp rates. 

- Power up sequence must be followed. See the Power-up Supply Sequence section. 

## **4.4. Power-On Reset** 

All iCE40 UltraLite devices have on-chip Power-On-Reset (POR) circuitry to ensure proper initialization of the device. Only three supply rails are monitored by the POR circuitry as follows: (1) VCC, (2) SPI_VCCIO1 and (3) VPP_2V5. All other supply pins have no effect on the power-on reset feature of the device. Note that all supply voltage pins must be connected to power supplies for normal operation (including device configuration). 

## **4.5. Power-up Supply Sequence** 

It is recommended to bring up the power supplies in the following order. Note that there is no specified timing delay between the power supplies, however, there is a requirement for each supply to reach a level of 0.5 V, or higher, before any subsequent power supplies in the sequence are applied. 

- **VCC** and **VCCPLL** should be the first two supplies to be applied. Note that these two supplies can be tied together subject to the recommendation to include a RC-based noise filter on the VCCPLL. Refer to iCE40 Hardware Checklist (FPGA-TN-02006). 

- **SPI_VCCIO1** should be the next supply, and can be applied any time after the previous supplies (VCC and VCCPLL) have reached a level of 0.5 V or higher. 

- **VPP_2V5** should be the next supply, and can be applied any time after previous supplies (VCC, VCCPLL and SPI_VCCIO1) have reached a level of 0.5 V or higher. 

- **Other Supplies** (VCCIO0 and VCCIO2) do not affect device power-up functionality, and they can be applied any time after the initial power supplies (VCC and VCCPLL) have reached a level of 0.5 V or greater. _On the 16 WLCSP package,_ 

_VCCIO0 and VPP_2V5 are connected to the same pin on the package, and should be powered as VPP_2V5 in the sequence._ 

There is no power down sequence required. However, when partial power supplies are powered down, it is required that the above sequence is followed when these supplies are powered up again. 

## **4.6. External Reset** 

When all power supplies have reached their minimum operating voltage defined in Table 4.2, it is required to either keep CRESET_B LOW, or toggle CRESET_B from HIGH to LOW, for a duration of tCRESET_B, and release it to go HIGH, to start configuration download from either the internal NVCM or the external Flash memory. 

Figure 4.1 shows Power-Up sequence when SPI_VCCIO1 and VPP_2V5 are not connected together, and the CRESET_B signal triggers configuration download. Figure 4.2 shows when SPI_VCCIO1 and VPP_2V5 connected together. If the supply sequence is not followed, extra peak current may be observed on the supplies during power up. 

All power supplies should be powered up during configuration. Before and during configuration, the I/Os are held in tristate. I/Os are released to user functionality once the device has finished configuration. 

© 2018-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02027-1.7 

23 

**iCE40 UltraLite Family Data Sheet Data Sheet** 

**==> picture [312 x 113] intentionally omitted <==**

**----- Start of picture text -----**<br>
V VPP_2V5, VCCIO0 and VCCIO2= 2.5 V / 3.3 V<br>SUPPLY(MIN)<br>SPI_VCCIO1 = 1.8 V<br>VCC/VCC_PLL = 1.2 V<br>CRESET_B<br>t<br>0.5 V  CRESET_B<br>**----- End of picture text -----**<br>


**Figure 4.1. Power Up Sequence with SPI_VCCIO1 and VPP_2V5 Not Connected Together** 

**==> picture [354 x 74] intentionally omitted <==**

**----- Start of picture text -----**<br>
VSUPPLY(MIN)  SPI_VCCIO, VPP_2V5, VCCIO0 and VCCIO2= 1.8 V / 2.5 V / 3.3 V<br>VCC/VCC_PLL = 1.2 V<br>CRESET_B<br>t<br>CRESET_B<br>0.5 V<br>**----- End of picture text -----**<br>


**Figure 4.2. Power Up Sequence with All Supplies Connected Together** 

## **4.7. Power-On-Reset Voltage Levels** 

**Table 4.4. Power-On-Reset Voltage Levels*** 

|**Symbol**|**Parameter**|**Parameter**|**Min**|**Max**|**Unit**|
|---|---|---|---|---|---|
|VPORUP|Power-On-Reset ramp up trip point (circuit<br>monitoring VCC, SPI_VCCIO1, and VPP_2V5)|VCC|0.6|1|V|
|||SPI_VCCIO1|0.7|1.6|V|
|||VPP_2V5|0.7|1.6|V|
|VPORDN|Power-On-Reset ramp down trip point (circuit<br>monitoring VCC, SPI_VCCIO1, and VPP_2V5)|VCC|—|0.85|V|
|||SPI_VCCIO1|—|1.6|V|
|||VPP_2V5|—|1.6|V|



***Note** : These POR trip points are only provided for guidance. Device operation is only characterized for power supply voltages specified under recommended operating conditions. 

© 2018-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

24 

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**iCE40 UltraLite Family Data Sheet Data Sheet** 

## **4.8. ESD Performance** 

Please contact Lattice Semiconductor for additional information. 

## **4.9. DC Electrical Characteristics** 

Over recommended operating conditions. 

**Table 4.5. DC Electrical Characteristics** 

|**Symbol**<br>~~GO~~|**Parameter**<br>~~GO~~|**Condition**<br>~~GO~~|**Min**<br>~~GO~~|**Typ**<br>~~GO~~|**Max**<br>~~GO~~|**Unit**<br>~~GO~~|
|---|---|---|---|---|---|---|
|IIL, IIH1, 3, 4<br>~~CG~~|Input or I/O Leakage<br>~~CG~~|0 V < VIN< VCCIO+ 0.2 V<br>~~CG~~|—<br>~~CG~~|—<br>~~CG~~|±10<br>~~CG~~|µA<br>~~CG~~|
|C1<br>~~CG~~<br>~~a~~|I/O Capacitance2<br>~~CG~~<br>~~ee~~|VCCIO= 3.3 V, 2.5 V, 1.8 V<br>VCC= Typ, VIO= 0 to VCCIO+ 0.2 V<br>~~CG~~<br>~~ee~~|—<br>~~CG~~<br>~~ee~~|6<br>~~CG~~<br>~~ee~~|—<br>~~CG~~<br>~~ee~~|pf<br>~~CG~~<br>~~ee~~|
|C2<br>~~a~~<br>~~a~~|Global Input Buffer<br>Capacitance2<br>~~ee~~<br>|VCCIO= 3.3 V, 2.5 V, 1.8 V<br>VCC= Typ, VIO= 0 to VCCIO+ 0.2 V<br>~~ee~~<br>|—<br>~~ee~~<br>|6<br>~~ee~~<br>~~ee~~<br>|—<br>~~ee~~<br>~~ee~~<br>|pf<br>~~ee~~<br>~~ee~~<br>|
|C3<br>~~a~~<br>~~a~~|24 mA LED I/O Capacitance<br>~~ee~~<br>|VCCIO= 3.3 V, 2.5 V, 1.8 V<br>VCC= Typ, VIO= 0 to VCCIO+ 0.2 V<br>~~ee~~<br>|—<br>~~ee~~<br>|20<br>~~ee~~<br>~~ee~~<br>|—<br>~~ee~~<br>~~ee~~<br>|pf<br>~~ee~~<br>~~ee~~<br>|
|C4<br>~~a~~<br>~~a~~|400 mA LED I/O Capacitance<br>~~ee~~<br>~~ee~~|VCCIO= 3.3 V, 2.5 V, 1.8 V<br>VCC= Typ, VIO= 0 to VCCIO+ 0.2 V<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~|53<br>~~ee~~<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~<br>~~ee~~|pf<br>~~ee~~<br>~~ee~~<br>~~ee~~|
|C5<br>~~a~~|100 mA LED I/O Capacitance<br>~~ee~~|VCCIO= 3.3 V, 2.5 V, 1.8 V<br>VCC= Typ, VIO= 0 to VCCIO+ 0.2 V<br>~~ee~~|—<br>~~ee~~|20<br>~~ee~~|—<br>~~ee~~|pf<br>~~ee~~|
|VHYST<br>~~DG~~<br>~~Se~~|Input Hysteresis<br>~~DG~~<br>~~Se~~|VCCIO= 1.8 V, 2.5 V, 3.3 V<br>~~DG~~<br>~~——————~~|—<br>~~DG~~<br>~~——————~~|200<br>~~DG~~<br>~~——————~~|—<br>~~DG~~<br>~~——————~~|mV<br>~~DG~~<br>~~——————~~|
|IPU<br>~~DG~~<br>~~Se~~|Internal PIO Pull-up Current<br>~~DG~~<br>~~Se~~|VCCIO= 1.8 V, 0 ≤ VIN≤ 0.65 VCCIO<br>~~DG~~<br>~~——————~~|−3<br>~~DG~~<br>~~——————~~|—<br>~~DG~~<br>~~——————~~|−31<br>~~DG~~<br>~~——————~~|µA<br>~~DG~~<br>~~——————~~|
|||VCCIO= 2.5 V, 0 ≤ VIN≤ 0.65 VCCIO<br>~~——————~~<br>~~po~~|−8<br>~~——————~~<br>~~po~~|—<br>~~——————~~<br>~~po~~|−72<br>~~——————~~<br>~~po~~|µA<br>~~——————~~<br>~~po~~|
|||VCCIO= 3.3 V, 0 ≤ VIN≤ 0.65 VCCIO<br>~~——————~~<br>~~po~~|−11<br>~~——————~~<br>~~po~~|—<br>~~——————~~<br>~~po~~|−128<br>~~——————~~<br>~~po~~|µA<br>~~——————~~<br>~~po~~|



2. TJ 25 °C, f = 1.0 MHz. 

3. Refer to VIL and VIH in Table 4.11. 

4. Input pins are clamped to VCCIO and GND by a diode. When input is higher than VCCIO or lower than GND, the Input Leakage current will be higher than the IIL and IIH. 

© 2018-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02027-1.7 

25 

m@LATTICE 

**iCE40 UltraLite Family Data Sheet Data Sheet** 

## **4.10. Supply Current** 

**Table 4.6. Supply Current[1, 2, 3, 4, 5]** 

|**Symbol**|**Parameter**|**Typ VCC =1.2 V4**|**Unit**|
|---|---|---|---|
|ICCSTDBY|Core Power Supply Static Current|35|µA|
|IPP2V5STDBY|VPP_2V5Power Supply Static Current|1|µA|
|ISPI_VCCIO1STDBY|SPI_VCCIO1Power Supply Static Current|1|µA|
|ICCIOSTDBY|VCCIOPower Supply Static Current|1 at VCCIOequal or less<br>2.5 V; 5 at VCCIOequal<br>or less 3.465 V|µA|
|ICCPEAK|Core Power Supply Startup Peak Current|3.06|mA|
|IPP_2V5PEAK|VPP_2V5Power Supply Startup Peak Current|2.15|mA|
|ISPI_VCCIO1PEAK|SPI_VCCIO1Power Supply Startup Peak Current|3.066|mA|
|ICCIOPEAK|VCCIOPower Supply Startup Peak Current|4.65 for config bank,<br>0.25 for regular I/O<br>bank|mA|



## **Notes** : 

1. VCCIO or GND, on-chip PLL is off. For more detail with your specific design, use the Power Calculator tool. Power specified with master SPI configuration mode. Other modes may be up to 25% higher. 

2. Frequency = 0 MHz. 

3. TJ = 25 °C, power supplies at nominal voltage. 

4. Does not include pull-up. 

5. Peak current is the in rush current - highest current during power supply start up within the power supply ramp rate. See Power Supply Ramp Rates section. These currents are measured with decoupling capacitance of 0.1 uF, 10 nF, and 1 nF to the power supply. Higher decoupling capacitance causes higher current. 

6. PLL power supply shared with Core Power supply. 

## **4.11. Internal Pull-Up Resistor Specifications** 

**Table 4.7. Internal Pull-Up Resistor Specifications** 

|**Parameter**|**Condition**|**Spec**|**Spec**|**Spec**|**Unit**|
|---|---|---|---|---|---|
|||**Min**|**Typ**|**Max**||
|Resistor_3.3K|1.71 < VCCIO< 3.47 V|2.64|3.3|3.96|kΩ|
|Resistor_6.8K|1.71 < VCCIO< 3.47 V|5.44|6.8|8.16|kΩ|
|Resistor_10K|1.71 < VCCIO< 3.47 V|8|10|12|kΩ|
|Weak pull-up resistor|1.71 < VCCIO< 1.89 V|—|100|—|kΩ|
||2.38 < VCCIO< 2.63 V|—|55|—|kΩ|
||3.13 < VCCIO< 3.47 V|—|40|—|kΩ|



© 2018-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

26 

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**iCE40 UltraLite Family Data Sheet Data Sheet** 

## **4.12. User I[2] C Specifications** 

**Table 4.8. User I[2] C Specifications[1]** 

|**SN**|**Symbol**|**Parameter**|**STD Mode**|**STD Mode**|**FAST Mode**|**FAST Mode**|**FAST Mode Plus**|**FAST Mode Plus**|**Unit**|
|---|---|---|---|---|---|---|---|---|---|
||||**Min**|**Max**|**Min**|**Max**|**Min**|**Max**||
|1|fSCL|SCL clock frequency|—|100|—|400|—|10002|kHz|



## **Notes:** 

1. Refer to the I[2] C specification for timing requirements. 

2. Fast Mode Plus maximum speed may be achieved by using external pull up resistor on I[2] C bus. Internal pull up may not be sufficient to support the maximum speed. 

## **4.13. Internal Oscillators (HFOSC, LFOSC)** 

**Table 4.9. Internal Oscillators (HFOSC, LFOSC)** 

|**Parameter**<br>~~ee~~<br>~~eeeee~~|**Parameter**<br>~~ee~~<br>~~eeeee~~|**Parameter Description**<br>~~ee~~<br>~~a~~|**Spec/Recommended**<br>~~ee~~<br>~~eeee~~<br>~~nei~~|**Spec/Recommended**<br>~~ee~~<br>~~eeee~~<br>~~nei~~|**Spec/Recommended**<br>~~ee~~<br>~~eeee~~<br>~~nei~~|**Unit**<br>~~ae~~|
|---|---|---|---|---|---|---|
|**Symbol**<br>~~ee~~<br>~~ee~~|**Conditions**<br>~~ee~~<br>~~eee~~||**Min**<br>~~ee~~<br>~~ee~~<br>~~ne~~|**Typ**<br>~~ee~~<br>~~ee~~<br>~~ne~~|**Max**<br>~~ee~~<br>~~i~~||
|fCLKHF<br>~~ee~~<br>~~ee ~~<br>~~eee~~<br>~~I~~|Commercial Temp<br>~~ee~~<br> ~~eee~~<br>~~eee~~<br>~~ee~~<br>|HFOSC clock frequency (tJ= 0°C–85°C)<br>~~ee~~<br>~~a~~<br>~~eee~~<br>|–10%<br>~~ee~~<br>~~ee ~~<br>~~ne~~<br>~~eee~~<br>|48<br>~~ee~~<br> ~~ee~~<br>~~ne ~~<br>~~eee~~<br>|10%<br>~~ee~~<br> ~~i ~~<br>~~eee~~<br>|MHz<br> ~~ae~~<br>~~eee~~<br>|
||Industrial Temp<br>~~eee~~<br>~~ee~~<br>|HFOSC clock frequency (tJ= –40°C–100°C)<br>~~eee~~<br>|–20%<br>~~eee~~<br>|48<br>~~eee~~<br>|20%<br>~~eee~~<br>|MHz<br>~~eee~~<br>|
|fCLKLF<br>~~Iee~~|—<br>~~ee~~<br>~~eee~~|LFOSC CLKK clock frequency<br>~~eee~~|–10%<br>~~eee~~|10<br>~~eee~~|10%<br>~~eee~~|kHz<br>~~eee~~|
|DCHCLKHF<br>~~ee~~<br>~~I~~|Commercial Temp<br>~~eee~~<br>~~ee~~<br>|HFOSC Duty Cycle (tJ= 0°C–85°C)<br>~~eee~~|45<br>~~eee~~|50<br>~~eee~~|55<br>~~eee~~|%<br>~~eee~~|
||Industrial Temp<br>~~eee~~<br>~~ee~~<br>|HFOSC Duty Cycle (tJ= –40°C–100°C)<br>~~eee~~|40<br>~~eee~~|50<br>~~eee~~|60<br>~~eee~~|%<br>~~eee~~|
|DCHCLKLF<br>~~ee ~~<br>~~I~~|—<br> ~~eee~~<br>~~ee~~<br>|LFOSC Duty Cycle (Clock High Period)<br>~~eee~~|45<br>~~eee~~|50<br>~~eee~~|55<br>~~eee~~|%<br>~~eee~~|
|tWAKEUP<br>~~a~~<br>~~pO~~|—<br>~~a~~|Delay OSC Enable to output enable delay|—|—|100|µs|
|Tsync_on<br>~~pO~~<br>~~ee~~|—<br>~~GOO~~|Oscillator output synchronizer delay<br>~~GOO~~|—<br>~~GOO~~|—<br>~~GOO~~|5<br>~~GOO~~|Cycles<br>~~GOO~~|
|Tsync_off<br>~~pO~~<br>~~ee~~|—<br>~~GOO~~|Oscillator output disable delay<br>~~GOO~~|—<br>~~GOO~~|—<br>~~GOO~~|5<br>~~GOO~~|Cycles<br>~~GOO~~|



## **4.14. sysI/O Recommended Operating Conditions** 

**Table 4.10. sysI/O Recommended Operating Conditions** 

|**Standard**|**VCCIO (V)**|**VCCIO (V)**|**VCCIO (V)**|
|---|---|---|---|
||**Min**|**Typ**|**Max**|
|LVCMOS 3.3|3.14|3.3|3.46|
|LVCMOS 2.5|2.37|2.5|2.62|
|LVCMOS 1.8|1.71|1.8|1.89|



## **4.15. sysI/O Single-Ended DC Electrical Characteristics** 

|**Input/Output**<br>**Standard**<br>~~ee~~|**VIL**<br>~~ee~~<br>~~ee~~|**VIL**<br>~~ee~~<br>~~ee~~|**VIH**<br>~~ee~~<br>~~ee~~|**VIH**<br>~~ee~~<br>~~ee~~|**VOL Max**<br>**(V)**<br>~~ee~~<br>~~ee~~|**VOH Min**<br>**(V)**<br>~~ee~~<br>~~ee~~|**IOL**<br>**(mA)**<br>~~ee~~|**IOH Max**<br>**(mA)**<br>~~ee~~|
|---|---|---|---|---|---|---|---|---|
||**Min(V)**<br>~~ee~~|**Max(V)**<br>~~ee~~|**Min(V)**<br>~~ee~~|**Max(V)**<br>~~ee~~|||||
|LVCMOS 3.3<br>~~ee~~|–0.3<br>~~ee~~|0.8<br>~~ee~~|2.0<br>~~ee~~|VCCIO+ 0.2 V<br>~~ee~~|0.4<br>~~ee~~<br>~~ee~~<br>~~ee~~|VCCIO− 0.4<br>~~ee~~<br>~~ee~~<br>~~ee~~|8<br>~~ee~~<br>~~ee~~|–8<br>~~ee~~<br>~~ee~~|
||||||0.2<br>~~ee~~<br>~~ee~~<br>~~ee~~|VCCIO− 0.2<br>~~ee~~<br>~~ee~~<br>~~ee~~|0.1<br>~~ee~~<br>~~ee~~|–0.1<br>~~ee~~<br>~~ee~~|
|LVCMOS 2.5<br>~~TT~~|–0.3<br>~~TT~~|0.7<br>|1.7<br>|VCCIO+ 0.2 V<br>|0.4<br>~~ee~~<br>~~ee~~<br>|VCCIO− 0.4<br>~~ee~~<br>~~ee~~<br>|6<br>~~ee ~~<br>~~ee~~<br>|–6<br> ~~ee~~<br>~~ee~~<br>|
||||||0.2<br>~~ee~~<br>|VCCIO− 0.2<br>~~ee~~<br>|0.1<br>~~ee~~<br>|–0.1<br>~~ee~~<br>|
|LVCMOS 1.8<br>~~TT~~|–0.3<br>~~TT~~|0.35 VCCIO<br>~~—~~|0.65 VCCIO<br>~~—~~|VCCIO+ 0.2 V<br>~~—~~|0.4<br>~~ee~~<br>~~—~~<br>~~ee~~|VCCIO− 0.4<br>~~ee~~<br>~~—~~<br>~~ee~~|4<br>~~ee~~<br>~~—~~<br>~~ee~~|–4<br>~~ee~~<br>~~—~~<br>~~ee~~|
||||||0.2<br>~~ee~~<br>~~—~~<br>~~ee~~|VCCIO− 0.2<br>~~ee~~<br>~~—~~<br>~~ee~~|0.1<br>~~ee~~<br>~~—~~<br>~~ee~~|–0.1<br>~~ee~~<br>~~—~~<br>~~ee~~|



27 

m@LATTICE 

**iCE40 UltraLite Family Data Sheet Data Sheet** 

## **4.16. Differential Comparator Electrical Characteristics** 

**Table 4.12. Differential Comparator Electrical Characteristics** 

|**Parameter**<br>**Symbol**|**Parameter Description**|**Test Conditions**|**Min**|**Max**|**Unit**|
|---|---|---|---|---|---|
|VREF|Reference Voltage to compare, on VINM|VCCIO= 2.5 V|0.25|VCCIO- 0.25 V|V|
|VDIFFIN_H|Differential input HIGH (VINP- VINM)|VCCIO= 2.5 V|250|—|mV|
|VDIFFIN_L|Differential input LOW (VINP- VINM)|VCCIO= 2.5 V|—|–250|mV|
|IIN|Input Current, VINPand VINM|VCCIO= 2.5 V|–10|10|µA|



## **4.17. Derating Logic Timing** 

Logic timing provided in the following sections of the data sheet and the Lattice design tools are worst case numbers in the operating range. Actual delays may be much faster. Lattice design tools can provide logic timing numbers at a particular temperature and voltage. 

## **4.18. Maximum sysI/O Buffer Performance** 

**Table 4.13. Maximum sysI/O Buffer Performance[1]** 

|**I/O Standard**|**Max Speed**|**Unit**|
|---|---|---|
|**Inputs**|||
|LVCMOS33|250|MHz|
|LVCMOS25|250|MHz|
|LVCMOS18|250|MHz|
|LED I/O used as GPIO open drain|50|MHz|
|**Outputs**|||
|LVCMOS33|250|MHz|
|LVCMOS25|250|MHz|
|LVCMOS18|155|MHz|
|LED I/O used as GPIO open drain|502|MHz|



**Notes** : 

1. Measured with a toggling pattern. 

2. With external resistor from 180 Ω to 250 Ω and capacity of no more than 15 pF. 

© 2018-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

28 

FPGA-DS-02027-1.7 

**iCE40 UltraLite Family Data Sheet Data Sheet** 

## **4.19. iCE40 UltraLite External Switching Characteristics** 

Over recommended commercial operating conditions. 

**Table 4.14. iCE40 UltraLite External Switching Characteristics** 

|**Parameter**<br>~~a~~|**Description**<br>~~a~~|**Device**<br>~~C(O~~|**Min**<br>~~C(O~~|**Max**<br>~~C(O~~|**Unit**|
|---|---|---|---|---|---|
|**Global Clock**<br>~~a a~~<br>~~C(O~~||||||
|fMAX_GBUF<br>~~a~~|Frequency for Global Buffer Clock network|All Devices|—|185|MHz|
|tW_GBUF<br>~~a~~<br>~~ee~~|Clock Pulse Width for Global Buffer|All Devices|2|—|ns|
|tISKEW_GBUF<br>~~a~~<br>~~ee~~|Global Buffer Clock Skew Within a Device|All Devices|—|500|ps|
|**Pin-LUT-Pin Propagation Delay**<br>~~ee~~<br>~~pC~~||||||
|tPD|Best case propagation delay through one<br>LUT logic|All Devices|—|9.0|ns|
|**General I/O Pin Parameters(Using Global Buffer Clock without PLL)* **<br>~~Rn~~||||||
|tSKEW_IO<br>~~a~~|Data bus skew across a bank of IOs|All Devices|—|410|ps|
|tCO<br>~~a~~<br>~~a~~|Clock to Output – PIO Output Register|All Devices|—|9.0|ns|
|tSU<br>~~a~~|Clock to Data Setup – PIO Input Register|All Devices|−0.5|—|ns|
|tH<br>~~a~~|Clock to Data Hold – PIO Input Register|All Devices|5.55|—|ns|
|**General I/O Pin Parameters(Using Global Buffer Clock with PLL)**||||||
|tCOPLL<br>~~a~~|Clock to Output – PIO Output Register<br>~~a~~|All Devices<br>~~a~~|—<br>~~a~~|2.9<br>~~a~~|ns<br>~~a~~|
|tSUPLL<br>~~a~~|Clock to Data Setup – PIO Input Register|All Devices|7.9|—|ns|
|tHPLL<br>~~a~~<br>~~a~~|Clock to Data Hold – PIO Input Register|All Devices|−0.6|—|ns|



***Note** : All the data is from the worst case. 

## **4.20. sysCLOCK PLL Timing** 

Over recommended operating conditions. 

**Table 4.15. sysCLOCK PLL Timing** 

|**Parameter**<br>~~a~~|**Descriptions**<br>~~ee~~|**Conditions**<br>~~ee eee~~|**Min**<br>~~eee~~|**Max**<br>~~eee~~|**Unit**<br>~~ee~~|
|---|---|---|---|---|---|
|fIN<br>~~a~~<br>~~a~~|Input Clock Frequency (REFERENCECLK,<br>EXTFEEDBACK)<br>~~a~~<br>~~ee~~|—<br>~~ee eee~~|10<br>~~eee~~|133<br>~~eee~~|MHz<br>~~ee~~|
|fOUT<br>~~a~~|Output Clock Frequency (PLLOUT)<br>~~ee~~|—<br>~~ee eee~~|16<br>~~eee~~|275<br>~~eee ~~|MHz<br> ~~ee~~|
|fVCO<br>~~a~~|PLL VCO Frequency|—|533|1066|MHz|
|fPFD3<br>~~a~~<br>~~a~~|Phase Detector Input Frequency<br>~~CC~~|—<br>~~CC~~|10<br>~~CC~~|133<br>~~CC~~|MHz<br>~~CC~~|
|**AC Characteristics**<br>~~Re~~||||||
|tDT<br>~~CG~~|Output Clock Duty Cycle<br>~~CG~~|—<br>~~CG~~|40<br>~~CG~~|60<br>~~CG~~|%<br>~~CG~~|
|tPH<br>~~CG~~<br>~~CO~~|Output Phase Accuracy<br>~~CG~~<br>~~CO~~<br>~~ee~~|—<br>~~CG~~<br>~~CO~~<br>~~ee~~|—<br>~~CG~~<br>~~CO~~<br>~~ee~~|±12<br>~~CG~~<br>~~CO~~|deg<br>~~CG~~<br>~~CO~~|
|tOPJIT1, 5<br>~~CO~~<br>~~a~~|Output Clock Period Jitter<br>~~CO~~<br>~~ee~~<br>~~ee~~|fOUT>= 100 MHz<br>~~CO~~<br>~~ee~~|—<br>~~CO~~<br>~~ee~~|450<br>~~CO~~|psp-p<br>~~CO~~|
|||fOUT< 100 MHz<br>~~ee~~<br>~~**ee**~~<br>~~ee~~|—<br>~~ee~~<br>~~**ee**~~<br>~~e~~|0.05<br>~~**ee**~~|UIPP<br>~~**ee**~~|
||Output Clock Cycle-to-Cycle Jitter<br>~~ee ~~<br>~~ee~~|fOUT>= 100 MHz<br> ~~ee ~~<br>~~**ee**~~<br>~~ee~~|—<br> ~~ee~~<br>~~**ee**~~<br>~~e~~|750<br>~~**ee**~~|psp-p<br>~~**ee**~~|
|||fOUT< 100 MHz<br>~~**ee**~~<br>~~ee~~|—<br>~~**ee**~~<br>~~e~~|0.10<br>~~**ee**~~|UIPP<br>~~**ee**~~|
||Output Clock Phase Jitter<br>~~ee ~~<br>~~EE~~<br>|fPFD>= 25 MHz<br>~~**ee**~~<br> ~~ee~~<br>~~EE~~<br>|—<br>~~**ee**~~<br>~~e~~<br>~~EE~~<br>~~ee~~<br>|275<br>~~**ee**~~<br>~~EE~~<br>~~ee~~<br>|psp-p<br>~~**ee**~~<br>~~EE~~<br>|
|||fPFD< 25 MHz<br>~~EE~~<br>~~a~~<br>|—<br>~~EE~~<br>~~a~~<br>~~ee~~<br>|0.05<br>~~EE~~<br>~~a~~<br>~~ee~~<br>|UIPP<br>~~EE~~<br>~~a~~<br>|
|tW<br>~~a CC~~|Output Clock Pulse Width<br>~~CC~~|At 90% or 10%<br>~~CC~~|1.33<br>~~ee~~<br>~~CC~~|—<br>~~ee~~<br>~~CC~~|ns<br>~~CC~~|
|tLOCK2, 3<br>~~a~~<br>~~a~~|PLL Lock-in Time<br>~~CC~~<br>~~ee~~|—<br>~~CC~~|—<br>~~CC~~|50<br>~~CC~~|µs<br>~~CC~~|
|tUNLOCK<br>~~a~~|PLL Unlock Time<br>~~ee~~|—|—|50|ns|



© 2018-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02027-1.7 

29 

sLATTICE 

**iCE40 UltraLite Family Data Sheet Data Sheet** 

|**Parameter**<br>~~a~~|**Descriptions**<br>|**Conditions**<br>|**Min**<br><br>~~**ee**~~|**Max**<br><br>~~**ee**~~|**Unit**<br><br>~~e~~~~**e**~~|
|---|---|---|---|---|---|
|tIPJIT4<br>~~es~~<br>~~a~~|Input Clock Period Jitter<br>~~es~~|fPFD≥ 20 MHz<br>~~es~~|—<br>~~es~~<br>~~**ee**~~|1000<br>~~es~~<br>~~**ee**~~|ps p-p<br>~~es~~<br>~~e~~~~**e**~~<br>~~e~~|
|||fPFD< 20 MHz<br>~~es~~<br>~~ee~~|—<br>~~es~~<br>~~**ee**~~<br>~~ee~~|0.02<br>~~es~~<br>~~**ee**~~<br>~~ee~~|UIPP<br>~~es~~<br>~~e~~~~**e**~~<br>~~ee~~<br>~~e~~|
|tSTABLE3<br>~~es~~<br>~~a~~<br>~~Rs~~|LATCHINPUTVALUE LOW to PLL Stable<br>~~es~~|—<br>~~es~~<br>~~ee~~|—<br>~~es~~<br>~~**ee**~~<br>~~ee~~|500<br>~~es~~<br>~~**ee** ~~<br>~~ee~~|ns<br>~~es~~<br> ~~e~~~~**e**~~<br>~~ee~~<br>~~e~~|
|tSTABLE_PW3<br>~~Rs~~<br>~~ns~~|LATCHINPUTVALUE Pulse Width|—|100|—|ns|
|tRST<br>~~Rs~~<br>~~ns~~|RESET Pulse Width|—|10|—|ns|
|tRSTREC<br>~~ns~~<br>~~a~~|RESET Recovery Time|—|10|—|µs|
|tDYNAMIC_WD<br>~~a~~|DYNAMICDELAY Pulse Width|—|100|—|VCO Cycles|



## **Notes:** 

1. Period jitter sample is taken over 10,000 samples of the primary PLL output with a clean reference clock. Cycle-to-cycle jitter is taken over 1000 cycles. Phase jitter is taken over 2000 cycles. All values per JESD65B. 

2. Output clock is valid after tLOCK for PLL reset and dynamic delay adjustment. 

3. At minimum fPFD. As the fPFD increases the time will decrease to approximately 60% the value listed. 

4. Maximum limit to prevent PLL unlock from occurring. Does not imply the PLL will operate within the output specifications listed in this table. 

5. The jitter values will increase with loading of the PLD fabric and in the presence of SSO noise. 

## **4.21. SPI Master or NVCM Configuration Time** 

**Table 4.16. SPI Master or NVCM Configuration Time** 

|**Symbol**|**Parameter**|**Conditions**|**Max**|**Unit**|
|---|---|---|---|---|
|tCONFIG|POR/CRESET_B to Device I/O Active|All devices – Low Frequency (Default)|53|ms|
|||All devices – Medium frequency|25|ms|
|||All devices – High frequency|13|ms|



**Notes** : 

- Assumes sysMEM Block is initialized to an all zero pattern if they are used. 

- The NVCM download time is measured with a fast ramp rate starting from the maximum voltage of POR trip point. 

## **4.22. sysCONFIG Port Timing Specifications** 

Over recommended operating conditions. 

**Table 4.17. sysCONFIG Port Timing Specifications** 

|**Symbol**<br>~~a~~|**Parameter**<br>|**Conditions**<br>|**Min**<br>|**Typ**<br>|**Max**<br>|**Unit**<br>|
|---|---|---|---|---|---|---|
|**All Configuration Mode**<br>~~TT~~|||||||
|tCRESET_B<br>~~TT~~<br>~~a~~|Minimum CRESET_B LOW pulse width required to<br>restart configuration, from fallingedge to risingedge.<br>~~TT~~|—<br>~~TT~~|200<br>~~TT~~|—<br>~~TT~~|—<br>~~TT~~|ns<br>~~TT~~|
|tDONE_IO<br>~~a~~<br>~~a~~|Number of configuration clock cycles after CDONE<br>goes HIGH before the PIOpins are activated.<br>|—<br>|49<br>|—<br>|—<br>|Clock<br>Cycles<br>|
|**Slave SPI**<br>~~aOO~~|||||||
|tCR_SCK<br>~~OO~~<br>~~pf~~<br>~~ee~~|Minimum time from a rising edge on CRESET_B until<br>the first SPI WRITE operation, first SPI_SCK clock.<br>During this time, the iCE40 UltraLite device is clearing<br>its internal configuration memory.<br>~~OO~~<br>~~pf~~|—<br>~~OO~~<br>~~pf~~|1200<br>~~OO~~<br>~~pf~~|—<br>~~OO~~<br>~~pf~~<br>~~ee ee~~|—<br>~~OO~~<br>~~pf~~<br>~~ee~~|µs<br>~~OO~~<br>~~pf~~<br>~~ee~~|
|fMAX<br>~~pf~~<br>~~a eee~~<br>~~ee~~|CCLK clock frequency<br>~~pf~~<br>~~eee~~|Write<br>~~pf~~<br>~~eee~~|1<br>~~pf~~<br>~~eee~~|—<br>~~pf~~<br>~~eee~~<br>~~ee ee~~|25<br>~~pf~~<br>~~eee~~<br>~~ee~~|MHz<br>~~pf~~<br>~~eee~~<br>~~ee~~|
|||Read1<br>~~pf~~<br>~~eee~~|—<br>~~pf~~<br>~~eee~~|15<br>~~pf~~<br>~~eee~~<br>~~ee ee~~|—<br>~~pf~~<br>~~eee~~<br>~~ee~~|MHz<br>~~pf~~<br>~~eee~~<br>~~ee~~|
|tCCLKH<br>~~a eee~~<br>~~ee~~<br>~~ee~~|CCLK clock pulsewidth HIGH<br>~~eee~~|—<br>~~eee~~|20<br>~~eee~~|—<br>~~eee~~<br>~~ee ee~~|—<br>~~eee~~<br>~~ee~~|ns<br>~~eee~~<br>~~ee~~|
|tCCLKL<br>~~ee~~<br>~~ee~~<br>~~Re~~|CCLK clock pulsewidth LOW|—|20|—<br>~~ee ee~~|—<br>~~ee~~|ns<br>~~ee~~|
|tSTSU<br>~~ee~~<br>~~Re~~|CCLK setup time|—|12|—|—|ns|



© 2018-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

30 

FPGA-DS-02027-1.7 

**iCE40 UltraLite Family Data Sheet** 

**Data Sheet** 

~~a~~ **Symbol Parameter Conditions Min Typ Max Unit** ~~a~~ tSTH CCLK hold time — 12 — — ns tSTCO CCLK falling edge to valid output — 13 — — ns ~~a |~~ **Master SPI[3 ]** fMCLK MCLK clock frequency Low 7.0 12.0 17.0 MHz Frequency (Default) Medium 21.0 33.0 45.0 MHz Frequency[2] High 33.0 53.0 71.0 MHz Frequency[2] ~~Pf~~ tMCLK CRESET_B HIGH to first MCLK edge ~~|~~ — 1200 ~~|~~ — ~~|}~~ — µs ~~a a~~ tMTSU MCLK setup time[4] — 9.9 — — ns tMTH MCLK hold time — 1 — — ns ~~a~~ **Notes** : 

1. Supported with 1.2 V VCC and at 25 ° C. 

2. Extended range fMAX Write operations support up to 53 MHz with 1.2 V VCC and at 25 ° C. 

3. tSU and tHD timing must be met for all MCLK frequency choices. 

4. For considerations of SPI Master Configuration Mode, please refer to iCE40 Programming and Configuration (FPGA-TN-02001). 

## **4.23. High Current LED, IR LED and Barcode LED Drives[*]** 

**Table 4.18. RGB LED** 

|**Symbol**<br>~~EE~~<br>~~po~~|**Parameter**<br>~~EE~~<br>~~_————eeEEe~~|**VCCIO = 3.3 V**<br>~~_————eeEEe~~|**VCCIO = 3.3 V**<br>~~_————eeEEe~~|**VCCIO = 3.3 V**<br>~~_————eeEEe~~|**VCCIO = 2.5 V**<br>~~_————eeEEe~~|**VCCIO = 2.5 V**<br>~~_————eeEEe~~|**VCCIO = 2.5 V**<br>~~_————eeEEe~~|
|---|---|---|---|---|---|---|---|
|||**Min**<br>~~_————eeEEe~~|**Max**<br>~~_————eeEEe~~|**Unit**<br>~~_————eeEEe~~|**Min**<br>~~_————eeEEe~~|**Max**<br>~~_————eeEEe~~|**Unit**<br>~~_————eeEEe~~|
|IRGB_ACCURACY_FULL<br>~~EE~~<br>~~po~~|RGB LED0, LED1, LED2 Sink<br>Current Accuracy to selected<br>current @VPAD= 0.5 ~ 2.5 V<br>~~EE~~<br>~~_————eeEEe~~|–12<br>~~_————eeEEe~~|+12<br>~~_————eeEEe~~|%<br>~~_————eeEEe~~|not<br>allowed<br>~~_————eeEEe~~|not<br>allowed<br>~~_————eeEEe~~|%<br>~~_————eeEEe~~|
|IRGB_ACCURACY_HALF<br>~~po~~|RGB LED0, LED1, LED2 Sink<br>Current Accuracy to selected<br>current @VPAD= 0.35 ~ 2.5 V|–14|+14|%|–14|+14|%|
|IRGB_MATCH|RGB LED0, LED1, LED2 Sink<br>Current Matching among the 3<br>outputs @VPAD= 0.35 ~ 2.5 V|–5|+5|%|–5|+5|%|
|IIR_ACCURACY_FULL|IR LED Sink Current Accuracy<br>to selected current @ VPAD=<br>0.8 V ~ 2 V|–12|+12|%|not<br>allowed|not<br>allowed|%|
|IIR_ACCURACY_HALF|IR LED Sink Current Accuracy<br>to selected current @ VPAD=<br>0.55 V ~ 2 V|–12|+12|%|–12|+12|%|
|IBARCODE_ACCURACY_FULL|BARCODE LED Sink Current<br>Accuracy to selected current @<br>VPAD=0.8 V ~ 2 V|–12|+12|%|not<br>allowed|not<br>allowed|%|
|IBARCODE_ACCURACY_HALF|BARCODE LED Sink Current<br>Accuracy to selected current @<br>VPAD=0.55 V ~ 2 V|–12|+12|%|not<br>allowed|not<br>allowed|%|



***Note** : Refer to Table 3.9 for valid current settings. 

© 2018-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02027-1.7 

31 

**iCE40 UltraLite Family Data Sheet Data Sheet** 

## **4.24. RGB LED Timing Specification** 

|**SN**|**Symbol**|**Parameter**||**Min**|**Max**|**Unit**|
|---|---|---|---|---|---|---|
|1|FPWM_OUT_X<br>FR250= 0|Frequency of the PWM output for color LED;<br>When FR250= 0|—|125|—|Hz|
|2|FPWM_OUT_X<br>FR250= 1|Frequency of the PWM output for color LED;<br>When FR250= 1|—|250|—|Hz|
|3|THIGH_X|PWM High percentage for color LED.|0||99|%|
|4|THIGH_STEP_X|PWM High percentage incremental step.|—|1/256|—|%|



**==> picture [485 x 161] intentionally omitted <==**

**----- Start of picture text -----**<br>
4.25. IR Transceiver IP Timing Specification<br>SN  Symbol  Parameter  Min  Max  Unit<br>1  FIR_OUT Frequency of the IR output  25  —  120  kHz<br>2  FIR_IN Frequency of the IR input  25  —  120  kHz<br>3  THIGH (DUTY1/3 = 0) Duty Cycle when DUTY1/3 = 0.  —  50  —  %<br>4  THIGH (DUTY1/3 = 1) Duty Cycle when DUTY1/3 = 1.  —  33.33  —  %<br>— Se<br>4.26. Switching Test Conditions<br>Figure 4.3 shows the output test load that is used for AC testing. The specific values for resistance, capacitance,<br>voltage, and other test conditions are listed in Table 4.19.<br>**----- End of picture text -----**<br>


V T R1 DUT Test Point CL ~~ae~~ 

**Figure 4.3. Output Test Load, LVCMOS Standards** 

**Table 4.19. Test Fixture Required Components, Non-Terminated Interfaces** 

|**Test Condition**|**R1 **|**CL **|**Timing Reference**|**VT **|
|---|---|---|---|---|
|LVCMOS settings (L ≥ H, H ≥ L)|∞|0 pF|LVCMOS 3.3 = 1.5 V|—|
||||LVCMOS 2.5 = VCCIO/2|—|
||||LVCMOS 1.8 = VCCIO/2|—|
|LVCMOS 3.3 (Z ≥ H)|188|0 pF|1.5 V|VOL|
|LVCMOS 3.3 (Z ≥ L)|||1.5 V|VOH|
|Other LVCMOS (Z ≥ H)|||VCCIO/2|VOL|
|Other LVCMOS (Z ≥ L)|||VCCIO/2|VOH|
|LVCMOS (H ≥ Z)|||VOH– 0.15 V|VOL|
|LVCMOS (L ≥ Z)|||VOL– 0.15 V|VOH|



**Note** : Output test conditions for all other interfaces are determined by the respective standards. 

© 2018-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

32 

FPGA-DS-02027-1.7 

**iCE40 UltraLite Family Data Sheet Data Sheet** 

## **5. Pinout Information** 

## **5.1. Signal Descriptions** 

## **5.1.1. Power Supply Pins** 

|**Signal Name**|**Function**|**I/O**|**Description**|
|---|---|---|---|
|VCC|Power|—|Core Power Supply|
|VCCIO_0, SPI_VCCIO1, VCCIO_2|Power|—|Power for I/Os in Bank 0, 1, and 2. VCCIO0is tied with VPP_2V5and<br>VCCIO2is tied with SPI_VCCIO1in 16 WLCS package.|
|VPP_2V5|Power|—|Power for NVCM programming and operations.|
|VCCPLL|Power|—|Power for PLL.|
|GND|GROUND|—|Ground|
|GND_LED|GROUND|—|Ground for LED drivers. Should connect to GND on board.|



## **5.1.2. Configuration Pins** 

|**Signal Name**|**Signal Name**|**Function**|**I/O**|**Description**|
|---|---|---|---|---|
|**Primary**|**Secondary**||||
|CRESET_B|—|Configuration|I|Configuration Reset, active LOW. Include a weak internal pull-<br>up resistor to VCCIO_2. Or actively driven externally or connect<br>an 10 kΩ pull-up to VCCIO_2.|
|PIOB_8a|CDONE|Configuration|I/O|Configuration Done. Includes a weak pull-up resistor to<br>SPI_VCCIO2. In 16 WLCS CDONE shared with PIOB_8a.|
|||General I/O|I/O|In user mode, after configuration, this pin can be programmed<br>asgeneral I/O in user function.|
|PIOB_11b|CDONE|Configuration|I/O|Configuration Done. Includes a weak pull-up resistor to<br>SPI_VCCIO2. In 36-ball ucBGA package CDONE shared with<br>PIOB_11b.|
|||General I/O|I/O|In user mode, after configuration, this pin can be programmed<br>asgeneral I/O in user function.|



© 2018-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02027-1.7 

33 

m@LATTICE 

**iCE40 UltraLite Family Data Sheet Data Sheet** 

## **5.1.3. Configuration SPI Pins** 

|**Signal Name**|**Signal Name**|**Function**|**I/O**|**Description**|
|---|---|---|---|---|
|**Primary**|**Secondary**||||
|PIOB_16a|SPI_SCK|Configuration|I/O|This pin is shared with device configuration. During configuration:<br>In Master SPI mode, this pin outputs the clock to external SPI<br>memory.<br>In Slave SPI mode, this pin inputs the clock from external<br>processor.|
|||General I/O|I/O|In user mode, after configuration, this pin can be programmed as<br>general I/O in user function.|
|PIOB_14a|SPI_SO|Configuration|Output|This pin is shared with device configuration. During configuration:<br>In Master SPI mode, this pin outputs the command data to<br>external SPI memory.<br>In Slave SPI mode, this pin connects to the MISO pin of the<br>externalprocessor.|
|||General I/O|I/O|In user mode, after configuration, this pin can be programmed as<br>general I/O in user function.|
|PIOB_15b|SPI_SI|Configuration|Input|This pin is shared with device configuration. During configuration:<br>In Master SPI mode, this pin receives data from external SPI<br>memory.<br>In Slave SPI mode, this pin connects to the MOSI pin of the<br>externalprocessor.|
|||General I/O|I/O|In user mode, after configuration, this pin can be programmed as<br>general I/O in user function.|
|PIOB_17b|SPI_SS|Configuration|I/O|This pin is shared with device configuration. During configuration:<br>In Master SPI mode, this pin outputs to the external SPI memory.<br>In Slave SPI mode, this pin inputs CSN from the external<br>processor.|
|||General I/O|I/O|In user mode, after configuration, this pin can be programmed as<br>general I/O in user function.|



## **5.1.4. Global Pins** 

|**Signal Name**|**Signal Name**|**Function**|**I/O**|**Description**|
|---|---|---|---|---|
|**Primary**|**Secondary**||||
|PIOT_22b|G0|General I/O|I/O|In user mode, after configuration, this pin can be<br>programmed asgeneral I/O in user function.|
|||Global|Input|Global input used for high fanout, or clock/reset net. The<br>G0pin drives the GBUF0global buffer.|
|PIOT_21a|G1|General I/O|I/O|In user mode, after configuration, this pin can be<br>programmed asgeneral I/O in user function.|
|||Global|Input|Global input used for high fanout, or clock/reset net. The<br>G1pin drives the GBUF1global buffer.|
|PIOB_13b|G3|General I/O|I/O|In user mode, after configuration, this pin can be<br>programmed asgeneral I/O in user function.|
|||Global|Input|Global input used for high fanout, or clock/reset net. The<br>G3pin drives the GBUF3global buffer.|
|PIOB_8a|G4|General I/O|I/O|In user mode, after configuration, this pin can be<br>programmed asgeneral I/O in user function.|
|||Global|Input|Global input used for high fanout, or clock/reset net. The<br>G4pin drives the GBUF4global buffer.|
|PIOB_7b|G5|General I/O|I/O|In user mode, after configuration, this pin can be<br>programmed asgeneral I/O in user function.|



© 2018-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

34 

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|**Signal Name**|**Signal Name**|**Function**|**I/O**|**Description**|
|---|---|---|---|---|
|**Primary**|**Secondary**||||
|||Global|Input|Global input used for high fanout, or clock/reset net. The<br>G5pin drives the GBUF5global buffer.|
|PIOB_3b|G6|General I/O|I/O|In user mode, after configuration, this pin can be<br>programmed asgeneral I/O in user function.|
|||Global|Input|Global input used for high fanout, or clock/reset net. The<br>G6pin drives the GBUF6global buffer.|



**5.1.5. General I/O, LED Pins** 

|**Signal Name**<br>~~GG~~|**Function**<br>~~GG~~|**I/O**<br>~~GG~~|**Description**<br>~~GG~~|
|---|---|---|---|
|RGB0<br>~~a ~~|General I/O<br>~~ee~~|Open-Drain I/O<br>~~ee~~|In user mode, with user's choice, this pin can be<br>programmed as open drain I/O in user function.|
||LED<br> ~~ee~~|Open-Drain Output<br>~~ee~~|In user mode, with user's choice, this pin can be<br>programmed as open drain 24 mA output to drive<br>external LED.|
|RGB1<br>~~——~~|General I/O<br>~~——~~|Open-Drain I/O<br>~~——~~|In user mode, with user's choice, this pin can be<br>programmed as open drain I/O in user function.|
||LED<br>~~——~~<br>~~ee~~|Open-Drain Output<br>~~——~~<br>~~ee~~|In user mode, with user's choice, this pin can be<br>programmed as open drain 24 mA output to drive<br>external LED.<br>~~ee~~|
|RGB2<br>~~pp~~|General I/O<br>~~pp~~|Open-Drain I/O<br>~~pp~~|In user mode, with user's choice, this pin can be<br>programmed as open drain I/O in user function.<br>~~pp~~|
||LED<br>~~pp~~<br>~~ee~~|Open-Drain Output<br>~~pp~~<br>~~ee~~|In user mode, with user's choice, this pin can be<br>programmed as open drain 24 mA output to drive<br>external LED.<br>~~pp~~<br>~~ee~~|
|IRLED<br>~~pp~~<br>~~pp~~<br>~~po~~|General I/O<br>~~pp~~<br>~~ee~~<br>~~pp~~|Open-Drain I/O<br>~~pp~~<br>~~ee~~<br>~~pp~~|In user mode, with user's choice, this pin can be<br>programmed as open drain I/O in user function.<br>~~pp~~<br>~~ee~~<br>~~pp~~|
||LED<br>~~pp~~<br>~~ee~~<br>|Open-Drain Output<br>~~pp~~<br>~~ee~~<br>|In user mode, with user's choice, this pin can be<br>programmed as open drain 400 mA output to drive<br>external LED.<br>~~pp~~<br>~~ee~~<br>|
|BARCODE<br>~~pp~~<br>~~po~~<br>~~ee~~|General I/O<br>~~pp~~<br>~~ee~~<br>|Open-Drain I/O<br>~~pp~~<br>~~ee~~<br>|In user mode, with user's choice, this pin can be<br>programmed as open drain I/O in user function.<br>~~pp~~<br>~~ee~~<br>|
||LED<br>~~ee~~<br>~~ee~~<br>~~ee~~|Open-Drain Output<br>~~ee~~<br>~~ee~~<br>~~ee~~|In user mode, with user's choice, this pin can be<br>programmed as open drain 100 mA output to drive<br>external LED.<br>~~ee~~<br>~~ee~~|
|PIOT_xx<br>~~po~~<br>~~ee~~|General I/O<br>~~ee~~<br>~~ee~~<br>~~ee~~|I/O<br>~~ee~~<br>~~ee~~<br>~~ee~~|In user mode, with user's choice, this pin can be<br>programmed as I/O in user function in the top (xx = I/O<br>location).<br>~~ee~~<br>~~ee~~|
|PIOB_xx<br><br>~~ee~~<br>~~ee~~|General I/O<br>~~ee~~<br>~~ee~~<br>~~ee~~|I/O<br>~~ee~~<br>~~ee~~<br>~~ee~~|In user mode, with user's choice, this pin can be<br>programmed as I/O in user function in the bottom (xx = I/<br>O location).<br>~~ee~~<br>~~ee~~|



© 2018-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02027-1.7 

35 

**iCE40 UltraLite Family Data Sheet Data Sheet** 

## HLATTICE 

## **5.2. Pin Information Summary** 

|**Pin Type**<br>~~ee~~<br>~~es~~|**Pin Type**<br>~~ee~~<br>~~es~~|**iCE40UL1K**<br>~~a~~<br>~~ee~~<br>~~es~~|**iCE40UL1K**<br>~~a~~<br>~~ee~~<br>~~es~~|**iCE40UL640**<br>~~a~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|**iCE40UL640**<br>~~a~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|
|---|---|---|---|---|---|
|||**SWG16**<br>~~ee~~|**36 ucBGA**<br>~~ee~~<br>~~es~~|**SWG16**<br>~~ee~~<br>~~ee~~|**36 ucBGA**<br>~~ee~~<br>~~ee~~|
|General Purpose<br>I/O Per Bank|Bank 0<br>~~es~~<br>~~es~~|5|12<br>~~es~~|5<br>~~ee~~|12<br>~~ee~~|
||Bank 1<br>~~es~~<br>~~es~~<br>~~es~~|4<br>~~sO~~|4<br>~~es ~~<br>~~sO~~|4<br> ~~ee~~|4<br>~~ee~~|
||Bank 2<br>~~es~~<br>~~es~~|1<br>~~sO~~|10<br>~~sO~~|1|10|
|Total General Purpose I/Os<br>~~es~~<br>~~a~~||10<br>~~sO~~|26<br>~~sO~~|10|26|
|VCC<br>~~aes~~||1|1|1|1|
|VCCIO<br>|Bank 0<br>~~es~~<br>~~es~~|0|1|0|1|
||Bank 1<br>~~es~~<br>~~es~~<br>~~es~~|0<br>~~sO~~|1<br>~~sO~~|0|1|
||Bank 2<br>~~es~~<br>~~es~~|1<br>~~sO~~|1<br>~~sO~~|1|1|
|VCCPLL<br>~~es~~<br>~~a~~||0<br>~~sO~~|1<br>~~sO~~|0|1|
|VPP_2V5<br>~~a~~<br>~~a~~||1<br>|1<br>|1<br>|1<br>|
|CRESET_B<br>~~a~~||1<br>|1<br>|1<br>|1<br>|
|CDONE<br>~~aOO~~||0<br>~~OO~~|0<br>~~OO~~|0<br>~~OO~~|0<br>~~OO~~|
|GND<br>~~po~~||1<br>~~po~~|2<br>~~po~~|1<br>~~po~~|2<br>~~po~~|
|GND_LED<br>~~po~~||1<br>~~po~~|1<br>~~po~~|1<br>~~po~~|1<br>~~po~~|
|Total Balls<br>~~a~~||16|36|16|36|



© 2018-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

36 

FPGA-DS-02027-1.7 

**iCE40 UltraLite Family Data Sheet Data Sheet** 

## **5.3. iCE40 Ultra Lite Part Number Description** 

iCE40ULXX- XXXXXITR 

**Device Family Shipping Method** iCE40 UltraLite FPGA <blank> =  Trays TR =  Tape and Reel (See quantity below) **Logic Cells** TR1K = Tape and Reel, 1,000 units 640 = 640 Logic Cells 1K = 1,248 Logic Cells **Grade** I = Industrial IE **Package** SWG16 = 16-Ball WLCSP (0.35 mm Ball Pitch) CM36A = 36-Ball ucBGA (0.40 mm Ball Pitch) **5.3.1. Tape and Reel Quantity Package TR Quantity** CM36A 4,000 SWG16 5,000 ~~es~~ **5.4. Ordering Part Numbers 5.4.1. Industrial Part Number LUTs Supply Voltage Package Pins Temperature** ICE40UL1K-SWG16ITR 1248 1.2 Halogen-Free WLCSP 16 IND ICE40UL1K-CM36AITR 1248 1.2 36-Ball ucBGA 36 IND ICE40UL1K-CM36AITR1K 1248 1.2 36-Ball ucBGA 36 IND ICE40UL640-SWG16ITR 640 1.2 Halogen-Free WLCSP 16 IND ICE40UL640-CM36AITR 640 1.2 36-Ball ucBGA 36 IND ICE40UL640-CM36AITR1K 640 1.2 36-Ball ucBGA 36 IND ~~==~~ 

© 2018-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02027-1.7 

37 

aLATTICE 

**iCE40 UltraLite Family Data Sheet Data Sheet** 

## **Supplemental Information** 

## **For Further Information** 

A variety of technical documents for the iCE40 UltraLite family are available on the Lattice web site. 

- iCE40 Programming and Configuration (FPGA-TN-02001) 

- iCE40 SPI/I2C Hardened IP Usage Guide (FPGA-TN-02010) 

- Advanced iCE40 SPI/I2C Hardened IP Usage Guide (FPGA-TN-02011) 

- Memory Usage Guide for iCE40 Devices (FPGA-TN-02002) 

- iCE40 sysCLOCK PLL Design and Usage Guide (FPGA-TN-02052) 

- iCE40 Hardware Checklist (FPGA-TN-02006) 

- iCE40 LED Driver Usage Guide (FPGA-TN-02021) 

- iCE40 UltraLite Pinout Files 

- iCE40 UltraLite Pin Migration Files 

- Thermal Management 

- Lattice design tools 

- Schematic Symbols 

© 2018-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

38 

FPGA-DS-02027-1.7 

**iCE40 UltraLite Family Data Sheet Data Sheet** 

## **Technical Support** 

For assistance, submit a technical support case at www.latticesemi.com/techsupport. 

© 2018-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02027-1.7 

39 

**iCE40 UltraLite Family Data Sheet Data Sheet** 

## **Revision History** 

## **Revision 1.7, October 2020** 

|**Section**|**Change Summary**|
|---|---|
|Disclaimers|Added this section.|
|Introduction|<br>Removed "with instant on capability" from initial statement.|
||<br>Changed QFN to ucBGA inTable 2.1. iCE40 UltraLite FamilySelection Guide.|
|Architecture|<br>Removed paragraph regarding SCLK and SDI inputs fromsysCLOCK Phase Locked Loops|
||(PLLs) (sysCLOCK PLL is only supported in 36-ball ucBGA package)section.|
||<br>Updated linked reference.|
||<br>ModifiedFigure 3.3. PLL Diagram.|
|Supplemental Information|UpdatedFor Further Informationsection. Changed document IDs.|
|—|Minor changes in formatting/style.|
|**Revision 1.6, August 2018**||
|**Section**|**Change Summary**|
|All|General update.|
|General Description|Updated Features section.|
||<br>Removed Two Hardened SPI Interfaces from the list.|
||<br>Updated Two Hardened Interfaces list.|
|Architecture|Updated Architecture Overview section. Corrected iCE40UP5K device to iCE40UL-1K device.|
|DC and SwitchingCharacteristics|Updated sysCONFIG Port TimingSpecifications section. Changed SPI_XCK to SPI_SCK.|
|Pinout Information|Updated Signal Descriptions section. Changed SPI_SS_B to SPI_SS.|
|Supplemental Information|Updated For Further Information section. Changed document ID of iCE40 Programming and|
||Configuration to FPGA-TN-02001.|
|Revision History|Updated revision historytable to new template.|



## **Revision 1.6, August 2018** 

## **Revision 1.5, September 2017** 

|**Section**|**Change Summary**|
|---|---|
|All|<br>Changed document number from DS1050 to FPGA-DS-02027.<br><br>Updated document template.|



**Revision 1.4, November 2016** 

|**Section**|**Change Summary**|
|---|---|
|General Description|Updated General Description section.<br><br>Changed embedded RGB PWM IP to hardened RGB PWM IP.<br><br>Changed modulation logic to hardened TX/RX pulse logic.<br><br>Updated information on the use of 500 mA IR driver.|
|Product Family|Updated Product Family section.<br><br>Added RGB LED and IR LED to configurable Controllers.<br><br>Added LED to RGB control functions.|
|Architecture|<br>Updated Architecture Overview section.<br><br>Changed caption to Figure 3.1. iCE40UL-1K Device, Top View.<br><br>Changed logic blocks to PLB.<br><br>Changed LED sink to RGB and IR LED sinks, and a 100 mA Barcode emulation output.<br><br>Corrected headings in Table 3.2. Global Buffer (GBUF) Connections to Programmable<br>Logic Blocks.<br><br>Updated footnote in Table 3.4. sysMEM Block Configurations*.|



© 2018-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

40 

FPGA-DS-02027-1.7 

**iCE40 UltraLite Family Data Sheet Data Sheet** 

|**Section**|**Change Summary**|
|---|---|
||<br>Updated sysI/O Buffer Banks section.<br><br>Corrected VCCIO format in Figure 3.5. I/O Bank and Programmable I/O Cell.<br><br>Updated Typical I/O Behavior During Power-up section.<br><br>Updated Supported Standards section.<br><br>Updated Programmable Pull Up Resistors section.<br><br>Changed more than one byte to multiple bytes in User I²C IPsection.<br><br>Updated High Current LED Drive I/O Pins section. Changed heading to High Current LED<br>Drive I/O Pins. Added LED to high current drive. Added information on use of 500 mA IR<br>LED. Added paragraph to reference Table 2-9.<br><br>Changed heading to Hardened RGB PWM IP.<br><br>Changed heading to Hardened IR Transceiver IP.<br><br>Updated iCE40 UltraLite Programming and Configuration section. Changed VCCIO_1to<br>SPI_VCCIO1in Device Programming.|
|DC and Switching Characteristics|<br>Updated Absolute Maximum Ratings section. Corrected VPP_2V5and VCCPLLformat.<br><br>Updated Recommended Operating Conditions section.<br><br>Changed heading to Hardened RGB PWM IP.<br><br>Updated footnote.<br><br>Removed Power-up Sequence section.<br><br>Added the following sections:<br><br>Power-On Reset<br><br>Power-up Supply Sequence<br><br>External Reset<br><br>Updated DC Electrical Characteristics section. Revised footnote 4.<br><br>Updated Supply Current section.<br><br>Changed VPP_2V5format.<br><br>Updated footnote 5.<br><br>Updated Internal Oscillators (HFOSC, LFOSC) section. Added Commercial and Industrial<br>Temp values for fCLKHFand DCHCLKHF.<br><br>Updated Differential Comparator Electrical Characteristics section.<br><br>Updated iCE40 UltraLite External Switching Characteristics section. Revised footnote.<br><br>Updated sysCLOCK PLL Timing section. Revised tOPJIT conditions.<br><br>Updated sysCONFIG Port Timing Specification section.<br><br>Added footnote to Master SPI.<br><br>Added footnote to MCLK setup time.<br><br>Revised tMTSUminimum value.<br><br>Added footnotes 3 and 4.|
|Supplemental Information|Updated For Further Information section. Added reference to iCE40 Hardware Checklist<br>(FPGA-TN-02006).|



© 2018-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02027-1.7 

41 

**iCE40 UltraLite Family Data Sheet Data Sheet** 

## **Revision 1.2, April 2016** 

|**Section**|**Change Summary**|
|---|---|
|General Description|Updated Features section.<br><br>Updated BGA package to ucBGA.<br><br>Corrected HF Oscillator unit in Table 2.1. iCE40 UltraLite Family Selection Guide.|
|Architecture|Updated sysCLOCK Phase Locked Loops (PLLs)_(sysCLOCK PLL is only supported in 36-ball_<br>_ucBGApackage)_section. Updated BGApackage to ucBGA in heading.|
|DC and Switching Characteristics|Updated Recommended Operating Conditions section. Added footnote 4 regarding VPP_2V5.|
|Pinout Information|Updated Signals Descriptions and Pinout Information Summary section.<br><br>Updated BGA package to ucBGA.<br><br>Changed SPI_CSN to SPI_SS_B.<br><br>Corrected minor typo errors.|
|Ordering Information|<br>Updated iCE40 Ultra Lite Part Number Description section.<br><br>Added shipment types.<br><br>Updated BGA package to ucBGA.<br><br>Added Tape and Reel Quantity section.<br><br>Updated Ordering Part Numbers section.<br><br>Added part numbers.<br><br>Updated BGApackage to ucBGA.|



## **Revision 1.1, March 2015** 

|**Section**|**Change Summary**|
|---|---|
|All|Document status changed from Preliminaryto Final.|
|General Description|Updated General Description and Features sections. Changed the LFOSC frequency value<br>from 9.7 kHz to 10 kHz.|
|Architecture|Updated On-Chip Oscillator section. Changed the LFOSC frequency value from 9.7 kHz to 10<br>kHz.|
|DC and Switching Characteristics|<br>Updated Power-up Supply Sequence section. Revised power-up sequence description<br>for 16-ball WLCSP. Added Power-up Sequence table.<br><br>Updated User I2C Specifications section. Added footnote 2.<br><br>Updated Internal Oscillators (HFOSC, LFOSC) section. Added and revised values.<br>Removed footnote.<br><br>Updated Maximum sysI/O Buffer Performance section. Revised value for LED I/O used<br>as GPIO open drain.<br><br>Updated High Current LED, IR LED and Barcode LED Drives section. Revised values.|



## **Revision 1.0, January 2015** 

© 2018-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

42 

FPGA-DS-02027-1.7 

www.latticesemi.com
Updated at April 17, 2026
Lattice Semiconductor is a premier developer of low-power, programmable design solutions, specializing in Field-Programmable Gate Arrays (FPGAs) and Programmable Logic Devices (PLDs). Recognized for driving innovation in cost-effective and power-efficient architectures, the company provides essential semiconductor components for consumer, mobile, and industrial design applications. Our selection of Lattice Semiconductor products is focused on their highly regarded FPGA integrated circuits. Devices from industry-leading families like the iCE40, MachXO, and LatticeECP series offer designers an exceptional combination of high system integration and industry-low power consumption. These FPGAs are engineered to handle complex tasks such as sensor management, custom connectivity, and advanced video processing while minimizing overall board footprint. To ensure seamless integration from concept to production, Lattice backs its hardware with a comprehensive support ecosystem. Engineers can accelerate their development cycles utilizing intuitive tools like the Lattice Diamond design software, paired with flexible IP cores and reference designs that reduce design risk and increase system reliability.
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