ICE40LP1K-CM36A

FPGA, iCE40LP, PLL, 25 I/O's, 1280 Cell, 1.14 V to 1.26 V in, UCBGA-36

⚠️ Reference pricing provided. In case of supply shortages, we will connect you with our trusted procurement partners to ensure your project's continuity.
Manufacturer: LATTICE SEMICONDUCTOR
Product type: FPGAs
MSL: MSL 3 - 168 hours
SVHC: No SVHC (25-Jun-2025)
FPGA Type: SRAM based FPGA
FPGA Family: iCE40LP
IC Mounting: Surface Mount
No. of Pins: 36Pins
Speed Grade: -
No. of I/O's: 25I/O's
Product Range: -
Qualification: -
Total RAM Bits: 128Kbit
No.of User I/Os: 25I/O's
Clock Management: PLL
Logic Case Style: UCBGA
IC Case / Package: UCBGA
No. of Macrocells: 1280Macrocells
I/O Supply Voltage: 3.46V
No. of Logic Cells: 1280Logic Cells
Process Technology: 40nm (CMOS)
No. of Logic Blocks: 1280
Core Supply Voltage Max: 1.26V
Core Supply Voltage Min: 1.14V
Operating Frequency Max: 275MHz
Operating Temperature Max: 100°C
Operating Temperature Min: -40°C
Delivery and price
Units per pack	500
Price	3.94 €
Current stock	10+
Lead time	30 days
Datasheet
ili 7s 

## **iCE40 LP/HX Family** 

## **Data Sheet** 

FPGA-DS-02029-3.9 

July 2022 

**iCE40 LP/HX Family Data Sheet** 

## **Disclaimers** 

Lattice makes no warranty, representation, or guarantee regarding the accuracy of information contained in this document or the suitability of its products for any particular purpose. All information herein is provided AS IS, with all faults and associated risk the responsibility entirely of the Buyer. Buyer shall not rely on any data and performance specifications or parameters provided herein. Products sold by Lattice have been subject to limited testing and it is the Buyer's responsibility to independently determine the suitability of any products and to test and verify the same. No Lattice products should be used in conjunction with mission- or safety-critical or any other application in which the failure of Lattice’s product could create a situation where personal injury, death, severe property or environmental damage may occur. The information provided in this document is proprietary to Lattice Semiconductor, and Lattice reserves the right to make any changes to the information in this document or to any products at any time without notice. 

© 2011-2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

2 

FPGA-DS-02029-3.9 

**iCE40 LP/HX Family Data Sheet** 

## **Contents** 

|**Contents**|**Contents**|**Contents**|
|---|---|---|
|Acronyms in This Document ................................................................................................................................................. 7|||
|1.|General Description ...................................................................................................................................................... 8||
||1.1.|Features .............................................................................................................................................................. 8|
|2.|Product Family .............................................................................................................................................................. 9||
|3.|Architecture ................................................................................................................................................................ 10||
||3.1.|Architecture Overview ...................................................................................................................................... 10|
||3.1.1.|PLB Blocks ..................................................................................................................................................... 11|
||3.1.2.|Routing .......................................................................................................................................................... 12|
||3.1.3.|Clock/Control Distribution Network ............................................................................................................. 12|
||3.1.4.|sysCLOCK Phase Locked Loops (PLLs) ........................................................................................................... 13|
||3.1.5.|sysMEM Embedded Block RAM Memory ..................................................................................................... 14|
||3.1.6.|sysI/O ............................................................................................................................................................ 16|
||3.1.7.|sysI/O Buffer ................................................................................................................................................. 19|
||3.1.8.|Non-Volatile Configuration Memory ............................................................................................................ 20|
||3.1.9.|Power On Reset ............................................................................................................................................ 20|
||3.2.|Programming and Configuration ....................................................................................................................... 20|
||3.2.1.|Power Saving Options ................................................................................................................................... 20|
|4.|DC and Switching Characteristics ............................................................................................................................... 21||
||4.1.|Absolute Maximum Ratings .............................................................................................................................. 21|
||4.2.|Recommended Operating Conditions ............................................................................................................... 21|
||4.3.|Power Supply Ramp Rates ................................................................................................................................ 22|
||4.4.|Power-On-Reset Voltage Levels ........................................................................................................................ 22|
||4.5.|Power-up Supply Sequence............................................................................................................................... 23|
||4.6.|ESD Performance .............................................................................................................................................. 23|
||4.7.|DC Electrical Characteristics .............................................................................................................................. 23|
||4.8.|Static Supply Current – LP Devices .................................................................................................................... 24|
||4.9.|Static Supply Current – HX Devices ................................................................................................................... 24|
||4.10.|Programming NVCM Supply Current – LP Devices ............................................................................................ 25|
||4.11.|Programming NVCM Supply Current – HX Devices ........................................................................................... 25|
||4.12.|Peak Startup Supply Current – LP Devices ........................................................................................................ 26|
||4.13.|Peak Startup Supply Current – HX Devices ....................................................................................................... 27|
||4.14.|sysI/O Recommended Operating Conditions .................................................................................................... 27|
||4.15.|sysI/O Single-Ended DC Electrical Characteristics ............................................................................................. 27|
||4.16.|sysI/O Differential Electrical Characteristics ..................................................................................................... 28|
||4.16.1.<br>LVDS25 ...................................................................................................................................................... 28||
||4.16.2.<br>subLVDS .................................................................................................................................................... 28||
||4.17.|LVDS25E Emulation ........................................................................................................................................... 28|
||4.18.|SubLVDS Emulation ........................................................................................................................................... 29|
||4.19.|Typical Building Block Function Performance – LP Devices* ............................................................................ 30|
||4.19.1.<br>Pin-to-Pin Performance (LVCMOS25) – LP Devices .................................................................................. 30||
||4.19.2.<br>Register-to-Register Performance – LP Devices ....................................................................................... 30||
||4.20.|Typical Building Block Function Performance – HX Devices* ............................................................................ 30|
||4.20.1.<br>Pin-to-Pin Performance (LVCMOS25) – HX Devices ................................................................................. 30||
||4.20.2.<br>Register-to-Register Performance – HX Devices ...................................................................................... 31||
||4.21.|Derating Logic Timing ........................................................................................................................................ 31|
||4.22.|Maximum sysI/O Buffer Performance .............................................................................................................. 31|
||4.23.|Timing Adders ................................................................................................................................................... 32|
||4.24.|External Switching Characteristics – LP Devices ................................................................................................ 33|
||4.25.|External Switching Characteristics – HX Devices ............................................................................................... 34|
||4.26.|sysClock PLL Timing ........................................................................................................................................... 35|
||4.27.|SPI Master or NVCM Configuration Time .......................................................................................................... 36|
||4.28.|sysCONFIG Port Timing Specifications .............................................................................................................. 37|



© 2011-2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02029-3.9 

3 

**iCE40 LP/HX Family Data Sheet** 

||4.29.|Switching Test Conditions ................................................................................................................................. 38|
|---|---|---|
|5.|Pinout Information ..................................................................................................................................................... 39||
||5.1.|Signal Descriptions ............................................................................................................................................ 39|
||5.1.1.|General Purpose ........................................................................................................................................... 39|
||5.1.2.|PLL and Global Functions (Used as user-programmable I/O pins when not used for PLL or clock pins) ...... 39|
||5.1.3.|Programming and Configuration .................................................................................................................. 40|
||5.2.|Pin Information Summary ................................................................................................................................. 41|
||5.3.|iCE40 LP/HX Part Number Description .............................................................................................................. 44|
||5.3.1.|Ultra Low Power (LP) Devices ....................................................................................................................... 44|
||5.3.2.|High Performance (HX) Devices .................................................................................................................... 44|
||5.4.|Ordering Information ........................................................................................................................................ 45|
||5.5.|Ordering Part Numbers ..................................................................................................................................... 45|
||5.5.1.|Ultra Low Power Industrial Grade Devices, Halogen Free (RoHS) Packaging ............................................... 45|
||5.5.2.|High-Performance Industrial Grade Devices, Halogen Free (RoHS) Packaging ............................................. 46|
|Supplemental Information .................................................................................................................................................. 47|||
|Technical Support ............................................................................................................................................................... 48|||
|Revision History .................................................................................................................................................................. 49|||



© 2011-2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02029-3.9 

4 

**iCE40 LP/HX Family Data Sheet** 

## **Figures** 

|Figure 3.1. iCE40LP/HX1K Device, Top View ....................................................................................................................... 10|Figure 3.1. iCE40LP/HX1K Device, Top View ....................................................................................................................... 10|
|---|---|
|Figure 3.2. PLB Block Diagram ............................................................................................................................................ 11|Figure 3.2. PLB Block Diagram ............................................................................................................................................ 11|
|Figure 3.3. PLL Diagram ...................................................................................................................................................... 13|Figure 3.3. PLL Diagram ...................................................................................................................................................... 13|
|Figure 3.4. sysMEM Memory Primitives ............................................................................................................................. 16|Figure 3.4. sysMEM Memory Primitives ............................................................................................................................. 16|
|Figure 3.5. I/O Bank and Programmable I/O Cell ............................................................................................................... 17|Figure 3.5. I/O Bank and Programmable I/O Cell ............................................................................................................... 17|
|Figure 3.6. iCE I/O Register Block Diagram ......................................................................................................................... 18|Figure 3.6. iCE I/O Register Block Diagram ......................................................................................................................... 18|
|Figure 4.1. LVDS25E Using External Resistors ..................................................................................................................... 28|Figure 4.1. LVDS25E Using External Resistors ..................................................................................................................... 28|
|Figure 4.2. subLVDSE DC Conditions ................................................................................................................................... 29|Figure 4.2. subLVDSE DC Conditions ................................................................................................................................... 29|
|Figure 4.3. Output Test Load, LVCMOS Standards ............................................................................................................. 38|Figure 4.3. Output Test Load, LVCMOS Standards ............................................................................................................. 38|
|Figure 5.1. Low Power (LP) Devices .................................................................................................................................... 44|Figure 5.1. Low Power (LP) Devices .................................................................................................................................... 44|
|Figure 5.2. High Performance (HX) Devices ........................................................................................................................ 44|Figure 5.2. High Performance (HX) Devices ........................................................................................................................ 44|
|Figure 5.3. High Performance (HX) Devices ........................................................................................................................ 45|Figure 5.3. High Performance (HX) Devices ........................................................................................................................ 45|



© 2011-2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02029-3.9 

5 

**iCE40 LP/HX Family Data Sheet** 

## **Tables** 

|Table 2.1. iCE40 LP/HX Family Selection Guide .................................................................................................................... 9|Table 2.1. iCE40 LP/HX Family Selection Guide .................................................................................................................... 9|
|---|---|
|Table 3.1. Logic Cell Signal Descriptions ............................................................................................................................. 12|Table 3.1. Logic Cell Signal Descriptions ............................................................................................................................. 12|
|Table 3.2. Global Buffer (GBUF) Connections to Programmable Logic Blocks .................................................................... 12|Table 3.2. Global Buffer (GBUF) Connections to Programmable Logic Blocks .................................................................... 12|
|Table 3.3. PLL Signal Descriptions ....................................................................................................................................... 14|Table 3.3. PLL Signal Descriptions ....................................................................................................................................... 14|
|Table 3.4. sysMEM Block Configurations* .......................................................................................................................... 15|Table 3.4. sysMEM Block Configurations* .......................................................................................................................... 15|
|Table 3.5. EBR Signal Descriptions ...................................................................................................................................... 16|Table 3.5. EBR Signal Descriptions ...................................................................................................................................... 16|
|Table 3.6. PIO Signal List ..................................................................................................................................................... 18|Table 3.6. PIO Signal List ..................................................................................................................................................... 18|
|Table 3.7. Supported Input Standards ................................................................................................................................ 19|Table 3.7. Supported Input Standards ................................................................................................................................ 19|
|Table 3.8. Supported Output Standards ............................................................................................................................. 19|Table 3.8. Supported Output Standards ............................................................................................................................. 19|
|Table 3.9. Power Saving Features Description .................................................................................................................... 20|Table 3.9. Power Saving Features Description .................................................................................................................... 20|
|Table 4.1. Absolute Maximum Ratings ............................................................................................................................... 21|Table 4.1. Absolute Maximum Ratings ............................................................................................................................... 21|
|Table 4.2. Recommended Operating Conditions ................................................................................................................ 21|Table 4.2. Recommended Operating Conditions ................................................................................................................ 21|
|Table 4.3. Power Supply Ramp Rates* ............................................................................................................................... 22|Table 4.3. Power Supply Ramp Rates* ............................................................................................................................... 22|
|Table 4.4. Power-On-Reset Voltage Levels* ....................................................................................................................... 22|Table 4.4. Power-On-Reset Voltage Levels* ....................................................................................................................... 22|
|Table 4.5. DC Electrical Characteristics ............................................................................................................................... 23|Table 4.5. DC Electrical Characteristics ............................................................................................................................... 23|
|Table 4.6. Supply Current– LP Devices|Table 4.6. Supply Current– LP Devices1, 2, 3, 4....................................................................................................................... 24|
|Table 4.7. Supply Current– HX Devices|Table 4.7. Supply Current– HX Devices1, 2, 3, 4...................................................................................................................... 24|
|Table 4.8. Programming NVCM Supply Current – LP Devices|Table 4.8. Programming NVCM Supply Current – LP Devices1, 2, 3, 4.................................................................................... 25|
|Table 4.9. Programming NVCM Supply Current – HX Devices|Table 4.9. Programming NVCM Supply Current – HX Devices1, 2, 3, 4................................................................................... 25|
|Table 4.10. Peak Startup Supply Current – LP Devices ....................................................................................................... 26|Table 4.10. Peak Startup Supply Current – LP Devices ....................................................................................................... 26|
|Table 4.11. Peak Startup Supply Current – HX Devices ...................................................................................................... 27|Table 4.11. Peak Startup Supply Current – HX Devices ...................................................................................................... 27|
|Table 4.12. sysI/O Recommended Operating Conditions ................................................................................................... 27|Table 4.12. sysI/O Recommended Operating Conditions ................................................................................................... 27|
|Table 4.13. sysI/O Single-Ended DC Electrical Characteristics ............................................................................................ 27|Table 4.13. sysI/O Single-Ended DC Electrical Characteristics ............................................................................................ 27|
|Table 4.14. LVDS25 ............................................................................................................................................................. 28|Table 4.14. LVDS25 ............................................................................................................................................................. 28|
|Table 4.15. subLVDS ............................................................................................................................................................ 28|Table 4.15. subLVDS ............................................................................................................................................................ 28|
|Table 4.16. LVDS25E DC Conditions .................................................................................................................................... 29|Table 4.16. LVDS25E DC Conditions .................................................................................................................................... 29|
|Table 4.17. subLVDSE DC Conditions .................................................................................................................................. 29|Table 4.17. subLVDSE DC Conditions .................................................................................................................................. 29|
|Table 4.18. Pin-to-Pin Performance (LVCMOS25) – LP Devices .......................................................................................... 30|Table 4.18. Pin-to-Pin Performance (LVCMOS25) – LP Devices .......................................................................................... 30|
|Table 4.19. Register-to-Register Performance – LP Devices ............................................................................................... 30|Table 4.19. Register-to-Register Performance – LP Devices ............................................................................................... 30|
|Table 4.20. Pin-to-Pin Performance (LVCMOS25) – HX Devices ......................................................................................... 30|Table 4.20. Pin-to-Pin Performance (LVCMOS25) – HX Devices ......................................................................................... 30|
|Table 4.21. Register-to-Register Performance – HX Devices .............................................................................................. 31|Table 4.21. Register-to-Register Performance – HX Devices .............................................................................................. 31|
|Table 4.22. Register-to-Register Performance|Table 4.22. Register-to-Register Performance1.................................................................................................................. 31|
|Table 4.23. Timing Adders – LP Devices* ............................................................................................................................ 32|Table 4.23. Timing Adders – LP Devices* ............................................................................................................................ 32|
|Table 4.24. Timing Adders – HX Devices* ........................................................................................................................... 33|Table 4.24. Timing Adders – HX Devices* ........................................................................................................................... 33|
|Table 4.25. External Switching Characteristics – LP Devices|Table 4.25. External Switching Characteristics – LP Devices1, 2........................................................................................... 33|
|Table 4.26. External Switching Characteristics – HX Devices|Table 4.26. External Switching Characteristics – HX Devices1, 2.......................................................................................... 34|
|Table 4.27. sysClock PLL Timing .......................................................................................................................................... 35|Table 4.27. sysClock PLL Timing .......................................................................................................................................... 35|
|Table 4.28. SPI Master or NVCM Configuration Time|Table 4.28. SPI Master or NVCM Configuration Time1, 2..................................................................................................... 36|
|Table 4.29. sysCONFIG Port Timing Specifications|Table 4.29. sysCONFIG Port Timing Specifications1............................................................................................................ 37|
|Table 4.30. Test Fixture Required Components, Non-Terminated Interfaces* .................................................................. 38|Table 4.30. Test Fixture Required Components, Non-Terminated Interfaces* .................................................................. 38|



© 2011-2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02029-3.9 

6 

**iCE40 LP/HX Family Data Sheet** 

## **Acronyms in This Document** 

A list of acronyms used in this document. 

|**Acronym **|**Definition**|
|---|---|
|DFF|D-style Flip-Flop|
|DSP|Digital Signal Processor|
|EBR|Embedded Block RAM|
|HFOSC|High FrequencyOscillator|
|I2C|Inter-Integrated Circuit|
|LFOSC|Low FrequencyOscillator|
|LUT|Look UpTable|
|LVCMOS|Low-Voltage ComplementaryMetal Oxide Semiconductor|
|NVCM|Non Volatile Configuration Memory|
|PFU|Programmable Functional Unit|
|PLB|Programmable Logic Blocks|
|PLL|Phase Locked Loops|
|SPI|Serial Peripheral Interface|
|WLCSP|Wafer Level ChipScale Packaging|



© 2011-2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02029-3.9 

7 

**iCE40 LP/HX Family Data Sheet** 

## **1. General Description** 

The iCE40™ LP/HX family of ultra-low power, nonvolatile FPGAs has five devices with densities ranging from 384 to 7,680 Look-Up Tables (LUTs). In addition to LUT-based, low-cost programmable logic, these devices feature Embedded Block RAM (EBR), Nonvolatile Configuration Memory (NVCM) and Phase Locked Loops (PLLs). These features allow the devices to be used in low-cost, high-volume consumer and system applications. Select packages offer HighCurrent drivers that are ideal to drive three white LEDs, or one RGB LED. 

The iCE40 LP/HX devices are fabricated on a 40 nm CMOS low power process. The device architecture has several features such as programmable low-swing differential I/O and the ability to turn off on-chip PLLs dynamically. These features help manage static and dynamic power consumption, resulting in low static power for all members of the family. The iCE40 LP/HX devices are available in two versions – ultra low power (LP) and high performance (HX) devices. 

The iCE40 LP/HX FPGAs are available in a broad range of advanced halogen-free packages ranging from the space saving 1.40 x 1.48 mm WLCSP to the PCBfriendly 20 x 20 mm TQFP. Table 2.1 shows the LUT densities, package and I/O options, along with other key parameters. 

The iCE40 LP/HX devices offer enhanced I/O features such as pull-up resistors. Pull-up features are controllable on a per-pin basis. 

The iCE40 LP/HX devices also provide flexible, reliable and secure configuration from on-chip NVCM. These devices can also configure themselves from external SPI Flash or be configured by an external master such as a CPU. 

Lattice provides a variety of design tools that allow complex designs to be efficiently implemented using the iCE40 LP/HX family of devices. Popular logic synthesis tools provide synthesis library support for iCE40 LP/HX. Lattice design tools use the synthesis tool output along with the user-specified preferences and constraints to place and route the design in the iCE40 LP/HX device. These tools extract the timing from the routing and back-annotate it into the design for timing verification. 

Lattice provides many pre-engineered IP (Intellectual Property) modules, including a number of reference designs, licensed free of charge, optimized for the iCE40 LP/HX FPGA family. By using these configurable soft core IP cores as standardized blocks, users are free to concentrate on the unique aspects of their design, increasing their productivity. 

## **1.1. Features** 

- Flexible Logic Architecture 

   - Five devices with 384 to 7,680 LUT4s and 10 to 206 I/O 

- Ultra-low Power Devices 

   - Advanced 40 nm low power process 

   - As low as 21 µA standby power 

   - Programmable low swing differential I/O 

- Embedded and Distributed Memory 

- Up to 128 kb sysMEM™ Embedded Block RAM 

- • Pre-Engineered Source Synchronous I/O 

   - DDR registers in I/O cells 

- High Current LED Drivers 

   - Three High Current Drivers used for three different LEDs or one RGB LED 

- High Performance, Flexible I/O Buffer 

   - Programmable sysI/O™ buffer supports wide range of interfaces: 

   - LVCMOS 3.3/2.5/1.8 

   - LVDS25E, subLVDS 

   - Schmitt trigger inputs, to 200 mV typical hysteresis 

- Programmable pull-up mode 

- Flexible On-Chip Clocking 

   - Eight low skew global signal resources 

   - Up to two analog PLLs per device 

- Flexible Device Configuration 

   - SRAM is configured through: 

   - Standard SPI Interface 

   - Internal Nonvolatile Configuration Memory (NVCM) 

- Broad Range of Package Options 

   - WLCSP, QFN, VQFP, TQFP, ucBGA, caBGA, and csBGA package options 

   - Small footprint package options 

   - As small as 1.40 x 1.48 mm 

   - Advanced halogen-free packaging 

© 2011-2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

8 

FPGA-DS-02029-3.9 

**iCE40 LP/HX Family Data Sheet** 

## **2. Product Family** 

Table 2.1 lists device information and packages of the iCE40 LP/HX family. 

**Table 2.1. iCE40 LP/HX Family Selection Guide** 

|**Part Number**<br>~~po~~<br>~~po~~|**Part Number**<br>~~po~~<br>~~po~~|**LP384**|**LP640**|**LP1K**|**LP4K**|**LP8K**|**HX1K**|**HX4K**|**HX8K**|
|---|---|---|---|---|---|---|---|---|---|
|**Logic Cells(LUT + Flip-Flop)**<br>~~po~~<br>~~po~~<br>~~po~~||**384**|**640**|**1,280**|**3,520**|**7,680**|**1,280**|**3,520**|**7,680**|
|RAM4K MemoryBlocks<br>~~po~~<br>~~po~~<br>~~po~~||0|8<br>~~COG~~|16<br>~~COG~~|20<br>~~COG~~|32|16|20|32|
|RAM4K RAM bits<br>~~po~~<br>~~Ge~~<br>~~po~~||0<br>~~Ge~~|32K<br>~~Ge~~<br>~~COG~~|64K<br>~~Ge~~<br>~~COG~~|80K<br>~~Ge~~<br>~~COG~~|128K<br>~~Ge~~|64K<br>~~Ge~~|80K<br>~~Ge~~|128K<br>~~Ge~~|
|Phase-Locked Loops(PLLs)<br>~~Ge~~<br>~~po~~<br>~~po~~||0<br>~~Ge~~|0<br>~~Ge~~<br>~~COG~~|11<br>~~Ge~~<br>~~COG~~|22<br>~~Ge~~<br>~~COG~~|22<br>~~Ge~~|11<br>~~Ge~~|2<br>~~Ge~~|2<br>~~Ge~~|
|Maximum Programmable I/O Pins<br>~~po~~<br>~~po~~<br>~~po~~||63|25<br>~~COG~~|95<br>~~COG~~|167<br>~~COG~~|178|95|95|206|
|Maximum Differential Input Pairs<br>~~po~~<br>~~po~~||8|3|12|20|23|11|12|26|
|High Current LED Drivers<br>~~po~~<br>~~a~~||0|3|3|0|0|0|0|0|
|**Package **<br>~~a~~|**Code**|**Programmable I/O: Max Input(LVDS25)**||||||||
|16 WLCSP<br>(1.40 x 1.48 mm, 0.35 mm)<br>~~a~~<br>~~a~~|SWG16<br>~~ee~~|~~ee~~|10(0)1|10(0)|—|—|—|—|—|
|32 QFN<br>(5 x 5 mm, 0.5 mm)<br>~~a ~~<br>~~a ee~~|SG32<br> ~~ee~~<br>~~ee~~|21(3)<br>~~ee~~<br>~~ee~~|—<br>~~ee~~|—<br>~~ee~~|—<br>~~ee~~|—<br>~~ee~~|—<br>~~ee~~|—<br>~~ee~~|—<br>~~ee~~|
|36 ucBGA<br>(2.5 x 2.5 mm, 0.4 mm)<br>~~a ~~<br>~~a~~|CM36<br> ~~ee~~<br>~~a~~|25(3)<br>~~ee~~<br>~~ee~~|—|25(3)|—|—|—|—|—|
|49 ucBGA<br>(3 x 3 mm, 0.4 mm)<br>~~a~~|CM49<br>~~a~~|37(6)<br>~~ee~~|—|35(5)|—|—|—|—|—|
|81 ucBGA<br>(4 x 4 mm, 0.4 mm)<br>~~a ~~<br>~~a ~~|CM81<br> ~~a ~~<br> ~~ee~~|—<br> ~~ee~~<br>~~ee~~|—|63(8)<br>~~ee~~|63(9)2<br>~~ee~~|63(9)2<br>~~ee~~|—|—|—|
|81 csBGA<br>(5 x 5 mm, 0.5 mm)<br>~~a ~~|CB81<br> ~~ee~~|—<br>~~ee~~|—|62(9)<br>~~ee~~|—<br>~~ee~~|—<br>~~ee~~|—|—|—|
|84 QFN<br>(7 x 7 mm, 0.5 mm)<br>~~ee~~|QN84<br>~~ee~~|—<br>~~ee~~|—<br>~~ee~~|67(7)<br>~~ee~~|—<br>~~ee~~|—<br>~~ee~~|—<br>~~ee~~|—<br>~~ee~~|—<br>~~ee~~|
|100 VQFP<br>(14 x 14 mm, 0.5 mm)<br>~~ee~~<br>~~a~~|VQ100<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~|—<br>~~ee~~|—<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~|72(9)1<br>~~ee~~|—<br>~~ee~~|—<br>~~ee~~|
|121 ucBGA<br>(5 x 5 mm, 0.4 mm)<br>~~a~~<br>~~a ~~|CM121<br>~~ee~~<br> ~~ee~~|—<br>~~ee~~<br>~~ee~~|—<br>~~ee~~|95(12)<br>~~ee~~<br>~~ee~~|93(13)<br>~~ee~~<br>~~ee~~|93(13)<br>~~ee~~<br>~~ee~~|—<br>~~ee~~|—<br>~~ee~~|—<br>~~ee~~|
|121 csBGA<br>(6 x 6 mm, 0.5 mm)<br>~~ee~~|CB121<br>~~ee~~|—<br>~~ee~~|—<br>~~ee~~|92(12)<br>~~ee~~|—<br>~~ee~~|—<br>~~ee~~|—<br>~~ee~~|—<br>~~ee~~|—<br>~~ee~~|
|121 caBGA<br>(9 x 9 mm, 0.8 mm)<br>~~a ee~~|BG121<br>~~ee~~|—<br>~~ee~~|—<br>~~ee~~|—<br>~~ee~~|—<br>~~ee~~|—<br>~~ee~~|—<br>~~ee~~|93(13)<br>~~ee~~|93(13)<br>~~ee~~|
|132 csBGA<br>(8 x 8 mm, 0.5 mm)<br>~~a~~|CB132<br>~~ee~~|—<br>~~ee~~|—<br>~~ee~~|—|—|—|95(11)|95(12)|95(12)|
|144 TQFP<br>(20 x 20 mm, 0.5 mm)<br>~~a~~|TQ144|—<br>~~ee~~|—<br>~~ee~~|—<br>~~ee~~|—<br>~~ee~~|—|96(12)|107(14)|—|
|225 ucBGA<br>(7 x 7 mm, 0.4 mm)<br>~~a~~<br>~~a~~|CM225<br>~~ee~~|—<br>~~ee~~<br>~~ee~~|—<br>~~ee~~|—<br>~~ee~~<br>~~ee~~|178(23)<br>~~ee~~<br>~~ee~~|178(23)<br>~~ee~~|—|—|178(23)|
|256-ball caBGA<br>(14 x 14 mm, 0.8 mm)<br>~~a~~<br>~~ee~~|CT256<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~|—<br>~~ee~~|—<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~|—<br>~~ee~~|—<br>~~ee~~|206(26)<br>~~ee~~|



## **Notes:** 

1. No PLL available on the 16 WLCSP, 36 ucBGA, 81 csBGA, 84 QFN, and 100 VQFP packages. 

2. Only one PLL available on the 81 ucBGA package. 

3. High Current I/O only available on the 16 WLCSP package. 

© 2011-2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02029-3.9 

9 

**iCE40 LP/HX Family Data Sheet** 

## **3. Architecture** 

## **3.1. Architecture Overview** 

The iCE40 LP/HX family architecture contains an array of Programmable Logic Blocks (PLB), sysCLOCK™ PLLs, Nonvolatile Programmable Configuration Memory (NVCM) and blocks of sysMEM Embedded Block RAM (EBR) surrounded by Programmable I/O (PIO). Figure 3.1 shows the block diagram of the iCE40LP/HX1K device. 

**==> picture [428 x 408] intentionally omitted <==**

**----- Start of picture text -----**<br>
Programmable<br>Logic Block (PLB)<br>= ip<br>I/O Bank 0<br>Programmable Interconnect<br># Op<br>#><br>#Op<br># OD<br>= ><br>NVCM PLL<br>SPI<br>I/O Bank 2<br>Bank<br>Non-volatile  Phase-Locked Carry Logic<br>Configuration Memory  Loop<br>(NVCM) 4-Input Look-up<br>Table (LUT4) Flip-flop with Enable<br>and Reset Controls<br>PLB PLB PLB PLB PLB PLB PLB PLB<br>4 kbit RAM<br>PLB PLB PLB PLB PLB PLB PLB PLB<br>I/O Bank 3 I/O Bank 1<br>PLB PLB PLB PLB PLB PLB PLB PLB<br>Programmable Interconnect Programmable Interconnect<br>4 kbit RAM<br>PLB PLB PLB PLB PLB PLB PLB PLB<br>8 Logic Cells = Programmable Logic Block<br>**----- End of picture text -----**<br>


**Figure 3.1. iCE40LP/HX1K Device, Top View** 

The logic blocks, Programmable Logic Blocks (PLB) and sysMEM EBR blocks, are arranged in a two-dimensional grid with rows and columns. Each column has either logic blocks or EBR blocks. The PIO cells are located at the periphery of the device, arranged in banks. The PLB contains the building blocks for logic, arithmetic, and register functions. The PIOs utilize a flexible I/O buffer referred to as a sysI/O buffer that supports operation with a variety of interface standards. The blocks are connected with many vertical and horizontal routing channel resources. The place and route software tool automatically allocates these routing resources. 

In the iCE40 LP/HX family, there are up to four independent sysI/O banks. Note on some packages VCCIO banks are tied together. There are different types of I/O buffers on the different banks. Refer to the details in later sections of this 

© 2011-2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

10 

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**iCE40 LP/HX Family Data Sheet** 

document. The sysMEM EBRs are large 4 kbit, dedicated fast memory blocks. These blocks can be configured as RAM, ROM or FIFO. 

The iCE40 LP/HX architecture also provides up to two sysCLOCK Phase Locked Loop (PLL) blocks. The PLLs have multiply, divide, and phase shifting capabilities that are used to manage the frequency and phase relationships of the clocks. 

Every device in the family has a SPI port that supports programming and configuration of the device. The iCE40 LP/HX includes on-chip, Nonvolatile Configuration Memory (NVCM). 

## **3.1.1. PLB Blocks** 

The core of the iCE40 LP/HX device consists of Programmable Logic Blocks (PLB) which can be programmed to perform logic and arithmetic functions. Each PLB consists of eight interconnected Logic Cells (LC) as shown in Figure 3.2. Each LC contains one LUT and one register. 

**==> picture [9 x 67] intentionally omitted <==**

**----- Start of picture text -----**<br>
8 Logic Cells (LCs)<br>**----- End of picture text -----**<br>


**Figure 3.2. PLB Block Diagram** 

## **Logic Cells** 

Each Logic Cell includes three primary logic elements shown in Figure 3.2. 

- A four-input Look-Up Table (LUT) builds any combinational logic function, of any complexity, requiring up to four inputs. Similarly, the LUT4 element behaves as a 16 x 1 Read-Only Memory (ROM). Combine and cascade multiple LUT4s to create wider logic functions. 

- A D-style Flip-Flop (DFF), with an optional clock-enable and reset control input, builds sequential logic functions. Each DFF also connects to a global reset signal that is automatically asserted immediately following device configuration. 

- Carry Logic boosts the logic efficiency and performance of arithmetic functions, including adders, subtracters, comparators, binary counters and some wide, cascaded logic functions. 

Table 3.1 lists the logic cell signals. 

© 2011-2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02029-3.9 

11 

**iCE40 LP/HX Family Data Sheet** 

**Table 3.1. Logic Cell Signal Descriptions** 

|**Function**|**Type**|**Signal Name**|**Description**|
|---|---|---|---|
|Input|Data signal|I0, I1, I2, I3|Inputs to LUT4|
|Input|Control signal|Enable|Clock enable shared by all LCs in the PLB|
|Input|Control signal|Set/Reset1|Asynchronous or synchronous local set/reset shared by<br>all LCs in the PLB.|
|Input|Control signal|Clock|Clock one of the eight Global Buffers, or from the<br>general-purpose interconnects fabric shared by all LCs<br>in the PLB.|
|Input|Inter-PLB signal|FCIN|Fast carry in|
|Output|Data signals|O|LUT4 or registered output|
|Output|Inter-PFU signal|FCOUT|Fast carry out|



**Note** : 

1. If Set/Reset is not used, then the flip-flop is never set/reset, except when cleared immediately after configuration. 

## **3.1.2. Routing** 

There are many resources provided in the iCE40 LP/HX devices to route signals individually with related control signals. The routing resources consist of switching circuitry, buffers, and metal interconnect (routing) segments. 

The inter-PLB connections are made with three different types of routing resources: Adjacent (spans two PLBs), x4 (spans five PLBs) and x12 (spans thirteen PLBs). The Adjacent, x4, and x12 connections provide fast and efficient connections in the diagonal, horizontal and vertical directions. 

The design tool takes the output of the synthesis tool and places and routes the design. 

## **3.1.3. Clock/Control Distribution Network** 

Each iCE40 LP/HX device has eight global inputs, two pins on each side of the device. Note that not all GBINs are available in all packages. 

These global inputs can be used as high fanout nets, clock, reset or enable signals. The dedicated global pins are identified as GBIN[7:0] and the global buffers are identified as-GBUF[7:0]. These eight inputs may be used as general purpose I/O if they are not used to drive the clock nets. Global buffer GBUF7 in I/O Bank 3 also provides an optional direct LVDS25 or subLVDS differential clock input. 

Table 3.2 lists the connections between a specific global buffer and the inputs on a PLB. All global buffers optionally connect to the PLB CLK input. Any four of the eight global buffers can drive logic inputs to a PLB. Even-numbered global buffers optionally drive the Set/Reset input to a PLB. Similarly, odd-numbered buffers optionally drive the PLB clockenable input. 

**Table 3.2. Global Buffer (GBUF) Connections to Programmable Logic Blocks** 

|**Global Buffer**|**LUT Inputs**|**Clock**|**Reset**|**Clock Enable**|
|---|---|---|---|---|
|GBUF0|Yes, any 4 of 8 GBUF<br>Inputs|Yes|Yes|—|
|GBUF1||Yes|—|Yes|
|GBUF2||Yes|Yes|—|
|GBUF3||Yes|—|Yes|
|GBUF4||Yes|Yes|—|
|GBUF5||Yes|—|Yes|
|GBUF6||Yes|Yes|—|
|GBUF7||Yes|—|Yes|



The maximum frequency for the global buffers are listed in the External Switching Characteristics tables in this document. 

© 2011-2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

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**iCE40 LP/HX Family Data Sheet** 

## **3.1.3.1. Global Hi-Z Control** 

The global high-impedance control signal, GHIZ, connects to all I/O pins on the iCE40 LP/HX device. This GHIZ signal is automatically asserted throughout the configuration process, forcing all user I/O pins into their high-impedance state. 

## **3.1.3.2. Global Reset Control** 

The global reset control signal connects to all PLB and PIO flip-flops on the iCE40 LP/HX device. The global reset signal is automatically asserted throughout the configuration process, forcing all flip-flops to their defined wake-up state. For PLB flip-flops, the wake-up state is always reset, regardless of the PLB flip-flop primitive used in the application. 

## **3.1.4. sysCLOCK Phase Locked Loops (PLLs)** 

The sysCLOCK PLLs provide the ability to synthesize clock frequencies. The iCE40 LP/HX devices have one sysCLOCK PLL. REFERENCECLK is the reference frequency input to the PLL and its source can come from an external I/O pin, the internal Oscillator Generators from internal routing. EXTFEEDBACK is the feedback signal to the PLL which can come from internal routing or an external I/O pin. The feedback divider is used to multiply the reference frequency and thus synthesize a higher frequency clock output. 

The PLLOUT output has an output divider, thus allowing the PLL to generate different frequencies fo r each output. The output divider can have a value from 1 to 64 (in increments of 2X). The PLLOUT outputs can all be used to drive the iCE40 LP/HX global clock network directly or general purpose routing resources can be used. 

The LOCK signal is asserted when the PLL determines it has achieved lock and de-asserted if a loss of lock is detected. A block diagram of the PLL is shown in Figure 3.3. 

The timing of the device registers can be optimized by programming a phase shift into the PLLOUT output clock which will advance or delay the output clock with reference to the REFERENCECLK clock. This phase shift can be either programmed during configuration or can be adjusted dynamically. In dynamic mode, the PLL may lose lock after a phase adjustment on the output used as the feedback source and not relock until the tLOCK parameter has been satisfied. 

**==> picture [448 x 199] intentionally omitted <==**

**----- Start of picture text -----**<br>
RESET<br>BYPASS<br>BYPASS<br>GNDPLL VCCPLL<br>Phase<br>REFERENCECLK DIVR Detector RANGE Voltage  DIVQ<br>Input  Low-Pass  Controlled  VCO<br>Divider Filter Oscillator  Divider<br>(VCO)<br>SIMPLE<br>DIVF<br>PLLOUTCORE<br>Feedback Divider Fine Delay<br>Fine Delay Adjustment<br>Adjustment Shifter Phase  Output Port PLLOUTGLOBAL<br>Feedback<br>Feedback_Path<br>DYNAMICDELAY[7:0] LOCK<br>EXTFEEDBACK EXTERNAL<br>LATCHINPUTVALUE Low Power mode<br>(iCEgate enabled)<br>**----- End of picture text -----**<br>


**Figure 3.3. PLL Diagram** 

Table 3.3 provides signal descriptions of the PLL block. 

© 2011-2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02029-3.9 

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**iCE40 LP/HX Family Data Sheet** 

**Table 3.3. PLL Signal Descriptions** 

|**Signal Name**|**Direction**|**Description**|
|---|---|---|
|REFERENCECLK|Input|Input reference clock|
|BYPASS|Input|The BYPASS control selects which clock signal connects to the PLLOUT output.<br>0 – PLL generated signal<br>1 – REFERENCECLK|
|EXTFEEDBACK|Input|External feedback input to PLL. Enabled when the FEEDBACK_PATH attribute is set<br>to EXTERNAL.|
|DYNAMICDELAY[7:0]|Input|Fine delay adjustment control inputs. Enabled when DELAY_ADJUSTMENT_MODE<br>is set to DYNAMIC.|
|LATCHINPUTVALUE|Input|When enabled, puts the PLL into low-power mode; PLL output is held static at the<br>last input clock value. Set ENABLE ICEGATE_PORTA and PORTB to 1 to enable.|
|PLLOUTGLOBAL|Output|Output from the Phase-Locked Loop (PLL). Drives a global clock network on the<br>FPGA. The port has optimal connections to global clock buffers GBUF4 and GBUF5.|
|PLLOUTCORE|Output|Output clock generated by the PLL, drives regular FPGA routing. The frequency<br>generated on this output is the same as the frequency of the clock signal generated<br>on the PLLOUTLGOBALport.|
|LOCK|Output|When High, indicates that the PLL output is phase aligned or locked to the input<br>reference clock.|
|RESET|Input|Active low reset.|
|SCLK|Input|Input, Serial Clock used for re-programming PLL settings.|
|SDI|Input|Input, Serial Data used for re-programming PLL settings.|



## **3.1.5. sysMEM Embedded Block RAM Memory** 

Larger iCE40 LP/HX device includes multiple high-speed synchronous sysMEM Embedded Block RAMs (EBRs), each 4 kbit in size. This memory can be used for a wide variety of purposes including data buffering and FIFO. 

## **3.1.5.1. sysMEM Memory Block** 

The sysMEM block can implement single port, pseudo dual port, or FIFO memories with programmable logic resources. Each block can be used in a variety of depths and widths as listed in Table 3.4. 

© 2011-2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02029-3.9 

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**iCE40 LP/HX Family Data Sheet** 

**Table 3.4. sysMEM Block Configurations[1]** 

|**Block RAM**<br>**Configuration**|**Block RAM**<br>**Configuration**<br>**and Size**|**WADDR Port**<br>**Size (Bits)**|**WDATA Port**<br>**Size (Bits)**|**RADDR Port**<br>**Size (Bits)**|**RDATA Port**<br>**Size (Bits)**|**MASK Port**<br>**Size (Bits)**|
|---|---|---|---|---|---|---|
|SB_RAM256x16<br>SB_RAM256x16NR<br>SB_RAM256x16NW<br>SB_RAM256x16NRNW|256 x 16 (4 k)|8 [7:0]|16 [15:0]|8 [7:0]|16 [15:0]|16 [15:0]|
|SB_RAM512x8<br>SB_RAM512x8NR<br>SB_RAM512x8NW<br>SB_RAM512x8NRNW|512 x 8 (4 k)|9 [8:0]|8 [7:0]|9 [8:0]|8 [7:0]|No Mask Port|
|SB_RAM1024x4<br>SB_RAM1024x4NR<br>SB_RAM1024x4NW<br>SB_RAM1024x4NRNW|1024 x 4 (4 k)|10 [9:0]|4 [3:0]|10 [9:0]|4 [3:0]|No Mask Port|
|SB_RAM2048x2<br>SB_RAM2048x2NR<br>SB_RAM2048x2NW<br>SB_RAM2048x2NRNW|2048 x 2 (4 k)|11 [10:0]|2 [1:0]|11 [10:0]|2 [1:0]|No Mask Port|



**Note** : 

1. For iCE40 LP/HX EBR primitives with a negative-edged Read or Write clock, the base primitive name is appended with a ‘N’ and a ‘R’ or W depending on the clock that is affected. 

## **3.1.5.2. RAM Initialization and ROM Operation** 

If desired, the contents of the RAM can be pre-loaded during device configuration. 

By preloading the RAM block during the chip configuration cycle and disabling the write controls, the sysMEM block can also be utilized as a ROM. 

Note that the sysMEM Embedded Block RAM Memory address 0 cannot be initialized. 

## **3.1.5.3. Memory Cascading** 

Larger and deeper blocks of RAM can be created using multiple EBR sysMEM Blocks. 

© 2011-2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02029-3.9 

15 

**iCE40 LP/HX Family Data Sheet** 

## **3.1.5.4. RAM4k Block** 

Figure 3.4 shows the 256 x 16 memory configurations and their input/output names. In all the sysMEM RAM modes, the input data and addresses for the ports are registered at the input of the memory array. 

**==> picture [232 x 175] intentionally omitted <==**

**----- Start of picture text -----**<br>
Write Port Read Port<br>WDATA[15:0] RDATA[15:0]<br>MASK[15:0]<br>WADDR[7:0] RADDR[7:0]<br>RAM4K<br>RAM Block<br>WE RE<br>(256 x 16)<br>WCLKE RCLKE<br>WCLK RCLK<br>**----- End of picture text -----**<br>


**Figure 3.4. sysMEM Memory Primitives** 

Table 3.5 lists the EBR signals. 

**Table 3.5. EBR Signal Descriptions** 

|**Signal Name**|**Direction**|**Description**|
|---|---|---|
|WDATA[15:0]|Input|Write Data input.|
|MASK[15:0]|Input|Masks write operations for individual data bit-lines.<br>0 – Write bit<br>1 – Do not write bit|
|WADDR[7:0]|Input|Write Address input. Selects one of 256 possible RAM locations.|
|WE|Input|Write Enable input.|
|WCLKE|Input|Write Clock Enable input.|
|WCLK|Input|Write Clock input. Default rising-edge, but with falling-edge option.|
|RDATA[15:0]|Output|Read Data output.|
|RADDR[7:0]|Input|Read Address input. Selects one of 256 possible RAM locations.|
|RE|Input|Read Enable input.|
|RCLKE|Input|Read Clock Enable input.|
|RCLK|Input|Read Clock input. Default rising-edge, but with falling-edge option.|



For further information on the sysMEM EBR block, refer to Memory Usage Guide for iCE40 Devices (FPGA-TN-02002). 

## **3.1.6. sysI/O** 

## **Buffer Banks** 

iCE40 LP/HX devices have up to four I/O banks with independent VCCIO rails with an additional configuration bank VCC_SPI for the SPI I/O. 

© 2011-2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02029-3.9 

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**iCE40 LP/HX Family Data Sheet** 

## **Programmable I/O (PIO)** 

The programmable logic associated with an I/O is called a PIO. The individual PIOs are connected to their respective sysI/O buffers and pads. The PIOs are placed on the top and bottom of the devices. 

**==> picture [458 x 316] intentionally omitted <==**

**----- Start of picture text -----**<br>
VCCIO<br>I/O Bank 0, 1, 2, or 3<br>Voltage Supply<br>0 = Hi-Z<br>Enabled  1<br>1 = Output<br>Disabled  0        Enabled<br>Pull-up<br>OE<br>VCC VCCIO_0<br>Pull-up<br>Internal Core<br>Enable<br>OUTCLK<br>I/O Bank 0<br>General-Purpose I/O Liaise<br>OUT<br>PIO PAD<br>Latch inhibits<br>OUTCLK switching for<br>iCEGATE lowest power<br>HOLD HD<br>ININ<br>GBIN pins optionally<br>I/O Bank 2 SPI INCLK connect directly to anassociated GBUF global<br>General-Purpose I/O Bank buffer<br>Programmable Input/Output<br>VCC_SPI<br>VCCIO_2 = Statically defined by configuration program<br>I/O Bank 3 I/O Bank 1<br>Special/LVDS I/O<br>General-Purpose I/O<br>VCCIO_3 VCCIO_1<br>**----- End of picture text -----**<br>


**Figure 3.5. I/O Bank and Programmable I/O Cell** 

The PIO contains three blocks: an input register block, output register block iCEgate™ and tri-state register block. To save power, the optional iCEgate latch can selectively freeze the state of individual, non-registered inputs within an I/O bank. Note that the freeze signal is common to the bank. These blocks can operate in a variety of modes along with the necessary clock and selection logic. 

## **Input Register Block** 

The input register blocks for the PIOs on all edges contain registers that can be used to condition high-speed interface signals before they are passed to the device core. In Generic DDR mode, two registers are used to sample the data on the positive and negative edges of the system clock signal, creating two data streams. 

## **Output Register Block** 

The output register block can optionally register signals from the core of the device before they are passed to the sysI/O buffers. In Generic DDR mode, two registers are used to capture the data on the positive and negative edge of the system clock and then muxed creating one data stream. 

Figure 3.6 shows the input/output register block for the PIOs. 

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FPGA-DS-02029-3.9 

17 

**iCE40 LP/HX Family Data Sheet** 

**==> picture [336 x 419] intentionally omitted <==**

**----- Start of picture text -----**<br>
CLOCK_ENABLE PIO Pair<br>OUTPUT_CLK<br>INPUT_CLK<br>(1,0)<br>LATCH_INPUT_VALUE<br>D_IN_1<br>D_IN_0<br>Pad<br>D_OUT_1<br>D_OUT_0<br>(1,0)<br>0<br>1<br>OUTPUT_ENABLE = .<br>(1,0)<br>LATCH_INPUT_VALUE<br>D_IN_1<br>D_IN_0 a.<br>Pad<br>D_OUT_1<br>D_OUT_0<br>(1,0)<br>0<br>1<br>OUTPUT_ENABLE<br>= Statically defined by configuration program.<br>**----- End of picture text -----**<br>


**Figure 3.6. iCE I/O Register Block Diagram** 

**Table 3.6. PIO Signal List** 

|**Pin Name**|**I/O Type**|**Description**|
|---|---|---|
|OUTPUT_CLK|Input|Output register clock|
|CLOCK_ENABLE|Input|Clock enable|
|INPUT_CLK|Input|Input register clock|
|OUTPUT_ENABLE|Input|Output enable|
|D_OUT_0/1|Input|Data from the core|
|D_IN_0/1|Output|Data to the core|
|LATCH_INPUT_VALUE|Input|Latches/holds the Input Value|



© 2011-2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

18 

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**iCE40 LP/HX Family Data Sheet** 

## **3.1.7. sysI/O Buffer** 

Each I/O is associated with a flexible buffer referred to as a sysI/O buffer. These buffers are arranged around the periphery of the device in groups referred to as banks. The sysI/O buffers allow users to implement a wide variety of standards that are found in today’s systems including LVCMOS and LVDS25. 

High Current LED Drivers combine three sysI/O buffers together. This allows for programmable drive strength. This also allows for high current drivers that are ideal to drive three white LEDs, or one RGB LED. Each bank is capable of supporting multiple I/O standards including single-ended LVCMOS buffers and differential LVDS25E output buffers. Bank 3 additionally supports differential LVDS25 input buffers. Each sysI/O bank has its own dedicated power supply. 

## **Typical I/O Behavior During Power-up** 

The internal power-on-reset (POR) signal is deactivated when VCC, VCCIO_2, VPP_2V5, and VCC_SPI have reached the level defined in Table 4.4. After the POR signal is deactivated, the FPGA core logic becomes active. It is your responsibility to ensure that all VCCIO banks are active with valid input logic levels to properly control the output logic states of all the I/O banks that are critical to the application. The default configuration of the I/O pins in a device prior to configuration is tri-stated with a weak pull-up to VCCIO. The I/O pins will maintain the pre-configuration state until VCC and VCCIO (for I/O banks containing configuration I/O) have reached levels, at which time the I/O will take on the software userconfigured settings only after a proper download/configuration. Unused I/O are automatically blocked and the pull-up termination is disabled. 

## **Supported Standards** 

The iCE40 LP/HX sysI/O buffer supports both single-ended input/output standards, and used as differential comparators. The buffer supports the LVCMOS 1.8 V, 2.5 V, and 3.3 V standards. The buffer has individually configurable options for bus maintenance (weak pull-up or none). 

Table 3.7 and Table 3.8 show the I/O standards (together with their supply and reference voltages) supported by the iCE40 LP/HX devices. 

## **Table 3.7. Supported Input Standards** 

|**I/O Standard**|**VCCIO(Typical)**|**VCCIO(Typical)**|**VCCIO(Typical)**|
|---|---|---|---|
||**3.3 V**|**2.5 V**|**1.8 V**|
|**Single-Ended Interfaces**||||
|LVCMOS33|Yes|—|—|
|LVCMOS25|—|Yes|—|
|LVCMOS18|—|—|Yes|
|**Differential Interfaces**||||
|LVDS251|—|Yes|—|
|SubLVDS1|—|—|Yes|



**Note:** 

1. Bank 3 only. 

**Table 3.8. Supported Output Standards** 

|**I/O Standard**|**VCCIO(Typical)**|
|---|---|
|**Single-Ended Interfaces**||
|LVCMOS33|3.3 V|
|LVCMOS25|2.5 V|
|LVCMOS18|1.8 V|
|**Differential Interfaces**||
|LVDS251|—|
|SubLVDS1|—|



**Note:** 

1. These interfaces can be emulated with external resistors in all devices. 

© 2011-2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02029-3.9 

19 

**iCE40 LP/HX Family Data Sheet** 

## **3.1.8. Non-Volatile Configuration Memory** 

All iCE40 LP/HX devices provide a Non-Volatile Configuration Memory (NVCM) block which can be used to configure the device. 

For more information on the NVCM, refer to iCE40 Programming and Configuration (FPGA-TN-02001). 

## **3.1.9. Power On Reset** 

iCE40 LP/HX devices have power-on reset circuitry to monitor VCC, VCCIO_2, VPP_2V5, and VCC_SPI voltage levels during power-up and operation. At power-up, the POR circuitry monitors VCC, VCCIO_2, VPP_2V5, and VCC_SPI (controls configuration) voltage levels. It then triggers download from the on-chip NVCM or external Flash memory after reaching the power-up levels specified in the Power-On-Reset Voltage table in the DC and Switching Characteristics section of this data sheet. Before and during configuration, the I/O are held in tri-state. I/O are released to user functionality once the device has finished configuration. 

## **3.2. Programming and Configuration** 

This section describes the programming and configuration of the iCE40 LP/HX family. 

## **Device Programming** 

The NVCM memory can be programmed through the SPI port. 

## **Device Configuration** 

There are various ways to configure the Configuration RAM (CRAM) including: Internal NVCM Download 

- From an SPI Flash (Master SPI mode) 

- System microprocessor to drive a Serial Slave SPI port (SSPI mode) 

The image to configure the CRAM can be selected by the user on power up (Cold Boot) or once powered up (Warm Boot). 

For more details on configuring the iCE40 LP/HX device, refer to iCE40 Programming and Configuration (FPGA-TN02001). 

## **3.2.1. Power Saving Options** 

iCE40 LP/HX devices are available in two options for maximum flexibility: LP and HX devices. The LP devices have ultra low static and dynamic power consumption. HX devices are designed to provide high performance. Both the LP and the HX devices operate at 1.2 V VCC. 

iCE40 LP/HX devices feature iCEGate and PLL low power mode to allow users to meet the static and dynamic power requirements of their applications. While these features are available in both device types, these features are mainly intended for use with iCE40 LP devices to manage power consumption. 

**Table 3.9. Power Saving Features Description** 

|**Device Subsystem**|**Feature Description**|
|---|---|
|PLL|When LATCHINPUTVALUE is enabled, puts the PLL into low-power mode; PLL output held static at last<br>input clock value.|
|iCEGate|To save power, the optional iCEGate latch can selectively freeze the state of individual, non-registered<br>inputs within an I/O bank. Registered inputs are effectively frozen by their associated clock or clock-<br>enable control.|



© 2011-2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

20 

FPGA-DS-02029-3.9 

**iCE40 LP/HX Family Data Sheet** 

## **4. DC and Switching Characteristics** 

## **4.1. Absolute Maximum Ratings** 

**Table 4.1. Absolute Maximum Ratings** 

|**Parameter**|**Min**|**Max**|**Unit**|
|---|---|---|---|
|Supply Voltage VCC|–0.5|1.42|V|
|Output Supply Voltage VCCIO|–0.5|3.60|V|
|NVCM Supply Voltage VPP_2V5|–0.5|3.60|V|
|PLL Supply Voltage VCCPLL|–0.5|1.42|V|
|I/O Tri-state Voltage Applied|–0.5|3.60|V|
|Dedicated Input Voltage Applied|–0.5|3.60|V|
|Storage Temperature (Ambient)|–65|150|°C|
|Junction Temperature (TJ)|–55|125|°C|



**Notes** : 

- Stress above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. Functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. 

- Compliance with the Thermal Management document is required. 

- All voltages referenced to GND. 

- I/O can support a 200 mV Overshoot above the Recommended Operating Conditions VCCIO (Max) and -200 mV Undershoot below VIL (Min). Overshoot and Undershoot is permitted for 25% duty cycle but must not exceed 1.6 ns. 

## **4.2. Recommended Operating Conditions** 

**Table 4.2. Recommended Operating Conditions** 

|**Symbol**<br>~~a~~|**Parameter**<br>~~a~~|**Parameter**<br>~~a~~|**Min**<br>~~a~~|**Max**<br>~~a~~|**Unit**<br>~~a~~|
|---|---|---|---|---|---|
|VCC<br>1<br>~~a~~<br>~~OC‘~~|Core Supply Voltage<br>~~a~~<br>~~OC‘~~||1.14<br>~~a~~<br>~~OC‘~~|1.26<br>~~a~~<br>~~OC‘~~|V<br>~~a~~<br>~~OC‘~~|
|VPP_2V5<br>~~OC‘~~<br>~~a~~|VPP_2V5NVCM Programming<br>and Operating Supply<br>Voltage<br>~~OC‘~~|Slave SPI Configuration<br>~~OC‘~~<br>~~a~~|1.71<br>~~OC‘~~|3.46<br>~~OC‘~~|V<br>~~OC‘~~|
|||Master SPI Configuration<br>~~a~~|2.30|3.46|V|
|||Configuration from NVCM<br>~~es~~|2.30<br>~~es~~<br>~~es~~|3.46<br>~~es~~|V<br>~~es~~|
|||NVCM Programming<br>~~es~~|2.30<br>~~es~~<br>~~es~~|3.00<br>~~es~~|V<br>~~es~~|
|VPP_FAST4<br>~~a~~<br>~~ee~~|Optional fast NVCMprogrammingsupply. Leave unconnected.<br>~~es~~||N/A<br>~~es~~<br>~~es~~|N/A<br>~~es~~|V<br>~~es~~|
|VCCPLL5,6<br>~~a~~<br>~~ee~~|PLL SupplyVoltage||1.14<br>~~es~~|1.26|V|
|VCCIO1,2,3<br>~~ee~~<br>~~PP~~<br>~~es~~|I/O Driver Supply Voltage<br>~~PP~~<br>|VCCIO0-3<br>~~Ff~~|1.71<br>~~Ff~~|3.46<br>~~Ff~~|V|
|||VCC_SPI<br>~~Ff~~<br>~~es~~<br>|1.71<br>~~Ff~~<br>~~es~~<br>|3.46<br>~~Ff~~<br>~~es~~<br>|V<br>~~es~~<br>|
|tJIND<br>~~PP~~<br>~~es~~<br>~~es~~|Junction Temperature, Industrial Operation<br>~~PP Ff~~<br>~~es~~<br>~~ee~~||–40<br>~~Ff~~<br>~~es~~<br>~~ee~~|100<br>~~Ff~~<br>~~es~~<br>~~ee~~|°C<br>~~es~~<br>~~ee~~|
|tPROG<br>~~es~~<br>~~es~~|Junction Temperature NVCM Programming<br>~~es~~<br>~~ee~~||10.00<br>~~es~~<br>~~ee~~|30.00<br>~~es~~<br>~~ee~~|°C<br>~~es~~<br>~~ee~~|



1. Like power supplies must be tied together. For example, if VCCIO and VCC_SPI are both the same voltage, they must also be the same supply. 

2. See recommended voltages by I/O standard in subsequent table. 

3. VCCIO pins of unused I/O banks should be connected to the VCC power supply on boards. 

4. VPP_FAST, used only for fast production programming, must be left floating or unconnected in applications, except CM36 and CM49 packages MUST have the VPP_FAST ball connected to VCCIO_0_1 ball externally. 

5. No PLL available on the iCE40LP384 and iCE40LP640 device. 

6. VCCPLL is tied to VCC internally in packages without PLL pins. 

© 2011-2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02029-3.9 

21 

**iCE40 LP/HX Family Data Sheet** 

## **4.3. Power Supply Ramp Rates** 

**Table 4.3. Power Supply Ramp Rates[1,2]** 

|**Symbol**|**Parameter**|**Parameter**|**Min**|**Max**|**Unit**|
|---|---|---|---|---|---|
|tRAMP|Power supply ramp rates for all<br>power supplies|All configuration modes. No power<br>supply sequencing.|0.40|10|V/ms|
|||Configuring from Slave SPI. No power<br>supply sequencing,|0.01|10|V/ms|
|||Configuring from NVCM. VCCand VPP_2V5<br>to be powered 0.25 ms before VCC_SPI.|0.01|10|V/ms|
|||Configuring from MSPI. VCCand VPP_SPIto<br>be powered 0.25 ms before VPP_2V5.|0.01|10|V/ms|



**Notes** : 

1. Assumes monotonic ramp rates. 

2. iCE40LP384 requires VCC to be greater than 0.7 V when VCCIO and VCC_SPI are above GND. 

## **4.4. Power-On-Reset Voltage Levels** 

**Table 4.4. Power-On-Reset Voltage Levels[1]** 

|**Symbol**<br>~~eG~~|**Device**<br>~~eG~~|**Parameter**<br>~~eG~~<br>~~—~~|**Parameter**<br>~~eG~~<br>~~—~~|**Min**<br>~~eG~~<br>|**Max**<br>~~eG~~<br>|**Unit**<br>~~eG~~<br>|
|---|---|---|---|---|---|---|
|VPORUP<br>~~eG~~|iCE40LP384<br>~~eG~~|Power-On-Reset ramp-up trip point (band gap<br>based circuit monitoring VCC, VCCIO_2, VCC_SPIand<br>VPP_2V5)<br>~~eG~~<br>~~—~~<br>~~_~~<br>~~—~~<br>~~—_~~|VCC<br>~~eG~~<br>~~—ff~~<br>~~_~~<br>~~|~~|0.67<br>~~eG~~<br>~~ff~~<br>~~|~~<br>~~|~~|0.99<br>~~eG~~<br>~~ff~~<br>~~|~~|V<br>~~eG~~<br>~~ff~~<br>~~|~~|
||||VCCIO_2<br>~~—ff~~<br>~~_~~<br>~~|~~<br>~~a~~|0.70<br>~~ff~~<br>~~|~~<br>~~|~~<br>~~a~~|1.59<br>~~ff~~<br>~~|~~<br>~~ee~~|V<br>~~ff~~<br>~~|~~|
||||VCC_SPI<br>~~_~~<br>~~|~~<br>~~a~~<br>~~—~~<br>~~|~~|0.70<br>~~|~~<br>~~|~~<br>~~a~~<br>~~|~~<br>~~|~~|1.59<br>~~|~~<br>~~ee~~<br>~~ft~~|V<br>~~|~~<br>~~ft~~|
||||VPP_2V5<br>~~a ~~<br>~~—~~<br>~~|~~<br>~~—_~~<br>~~|~~|0.70<br> ~~a~~<br>~~|~~<br>~~|~~<br>~~|~~<br>~~|~~|1.59<br>~~ee~~<br>~~ft~~<br>~~|~~|V<br>~~ft~~<br>~~|~~|
||iCE40LP640,<br>iCE40LP/HX1K,<br>iCE40LP/HX4K,<br>iCE40LP/HX8K|Power-On-Reset ramp-up trip point (band gap<br>based circuit monitoring VCC, VCCIO_2, VCC_SPIand<br>VPP_2V5)<br>~~—~~<br>~~—_~~<br>~~_~~<br>~~—_~~<br>~~—~~<br>~~_~~|VCC<br>~~—~~<br>~~|~~<br>~~—_~~<br>~~|~~<br>~~_~~<br>~~|~~|0.55<br>~~|~~<br>~~|~~<br>~~|~~<br>~~|~~<br>~~|~~<br>~~|~~|0.75<br>~~ft~~<br>~~|~~<br>~~|~~|V<br>~~ft~~<br>~~|~~<br>~~|~~|
||||VCCIO_2<br>~~—_~~<br>~~|~~<br>~~_~~<br>~~|~~<br>~~—_~~<br>~~|~~|0.86<br>~~|~~<br>~~|~~<br>~~|~~<br>~~|~~<br>~~|~~<br>~~|~~|1.29<br>~~|~~<br>~~|~~<br>~~|~~|V<br>~~|~~<br>~~|~~<br>~~|~~|
||||VCC_SPI<br>~~_~~<br>~~|~~<br>~~—_~~<br>~~|~~<br>~~—~~|0.86<br>~~|~~<br>~~|~~<br>~~|~~<br>~~|~~<br>|1.29<br>~~|~~<br>~~|~~<br>|V<br>~~|~~<br>~~|~~<br>|
||||VPP_2V5<br>~~—_~~<br>~~|~~<br>~~—ff~~<br>~~_~~<br>~~|~~|0.86<br>~~|~~<br>~~|~~<br>~~ff~~<br>~~|~~<br>~~|~~|1.33<br>~~|~~<br>~~ff~~<br>~~|~~|V<br>~~|~~<br>~~ff~~<br>~~|~~|
|VPORDN|iCE40LP384|Power-On-Reset ramp-down trip point (band gap<br>based circuit monitoring VCC, VCCIO_2, VCC_SPIand<br>VPP_2V5)<br>~~—~~<br>~~_~~<br>~~_~~<br>~~—_~~<br>~~—~~<br>~~_~~|VCC<br>~~—ff~~<br>~~_~~<br>~~|~~<br>~~_~~<br>~~|~~|—<br>~~ff~~<br>~~|~~<br>~~|~~<br>~~|~~<br>~~|~~|0.64<br>~~ff~~<br>~~|~~<br>~~|~~|V<br>~~ff~~<br>~~|~~<br>~~|~~|
||||VCCIO_2<br>~~_~~<br>~~|~~<br>~~_~~<br>~~|~~<br>~~—_~~<br>~~|~~|—<br>~~|~~<br>~~|~~<br>~~|~~<br>~~|~~<br>~~|~~<br>~~|~~|1.59<br>~~|~~<br>~~|~~<br>~~|~~|V<br>~~|~~<br>~~|~~<br>~~|~~|
||||VCC_SPI<br>~~_~~<br>~~|~~<br>~~—_~~<br>~~|~~<br>~~—~~|—<br>~~|~~<br>~~|~~<br>~~|~~<br>~~|~~<br>|1.59<br>~~|~~<br>~~|~~<br>|V<br>~~|~~<br>~~|~~<br>|
||||VPP_2V5<br>~~—_~~<br>~~|~~<br>~~—ff~~<br>~~_~~<br>~~|~~|—<br>~~|~~<br>~~|~~<br>~~ff~~<br>~~|~~<br>~~|~~|1.59<br>~~|~~<br>~~ff~~<br>~~|~~|V<br>~~|~~<br>~~ff~~<br>~~|~~|
||iCE40LP640,<br>iCE40LP/HX1K,<br>iCE40LP/HX4K,<br>iCE40LP/HX8K|Power-On-Reset ramp-down trip point (band gap<br>based circuit monitoring VCC, VCCIO_2, VCC_SPIand<br>VPP_2V5)<br>~~—~~<br>~~_~~<br>~~_~~<br>~~—_~~<br>~~—~~|VCC<br>~~—ff~~<br>~~_~~<br>~~|~~<br>~~_~~<br>~~|~~|—<br>~~ff~~<br>~~|~~<br>~~|~~<br>~~|~~<br>~~|~~|0.75<br>~~ff~~<br>~~|~~<br>~~|~~|V<br>~~ff~~<br>~~|~~<br>~~|~~|
||||VCCIO_2<br>~~_~~<br>~~|~~<br>~~_~~<br>~~|~~<br>~~—_~~<br>~~|~~|—<br>~~|~~<br>~~|~~<br>~~|~~<br>~~|~~<br>~~|~~<br>~~|~~|1.29<br>~~|~~<br>~~|~~<br>~~|~~|V<br>~~|~~<br>~~|~~<br>~~|~~|
||||VCC_SPI<br>~~_~~<br>~~|~~<br>~~—_~~<br>~~|~~<br>~~—~~|—<br>~~|~~<br>~~|~~<br>~~|~~<br>~~|~~<br>|1.29<br>~~|~~<br>~~|~~<br>|V<br>~~|~~<br>~~|~~<br>|
||||VPP_2V5<br>~~—_~~<br>~~|~~<br>~~—ff~~|—<br>~~|~~<br>~~|~~<br>~~ff~~|1.33<br>~~|~~<br>~~ff~~|V<br>~~|~~<br>~~ff~~|



**Note** : 

1. These POR trip points are only provided for guidance. Device operation is only characterized for power supply voltages specified under recommended operating conditions. 

© 2011-2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

22 

FPGA-DS-02029-3.9 

**iCE40 LP/HX Family Data Sheet** 

## **4.5. Power-up Supply Sequence** 

It is recommended to bring up the power supplies in the order below. 

**Note:** There is no specified timing delay between the power supplies. There is, however, a requirement for each supply to reach a level of 0.5 V, or higher, before any subsequent power supplies in the sequence are applied. 

1. VCC and VCCPLL should be the first two supplies to be applied. Note that these two supplies can be tied together subject to the recommendation to include a RC-based noise filter on the VCCPLL. Refer to iCE40 Hardware Checklist (FPGA-TN-02006). 

2. SPI_VCCIO1 should be the next supply, and can be applied any time after the previous supplies (VCC and VCCPLL) have reached as level of 0.5 V or higher. 

3. VPP_2V5 should be the next supply, and can be applied any time after previous supplies (VCC, VCCPLL and SPI_VCCIO1) have reached a level of 0.5 V or higher. 

4. Other Supplies (VCCIO0 and VCCIO2) do not affect device power-up functionality, and they can be applied any time after the initial power supplies (VCC and VCCPLL) have reached a level of 0.5 V or greater. There is no power down sequence required. However, when partial power supplies are powered down, it is required the above sequence to be followed when these supplies are re-powered up again. 

## **4.6. ESD Performance** 

Please refer to the iCE40 Product Family Qualification Summary for complete qualification data, including ESD performance. 

## **4.7. DC Electrical Characteristics** 

Over recommended operating conditions. 

**Table 4.5. DC Electrical Characteristics** 

|**Symbol**<br>~~SC~~|**Parameter**<br>~~SC~~|**Condition**<br>~~SC~~|**Min**<br>~~SC~~|**Typ**<br>~~SC~~|**Max**<br>~~SC~~|**Unit**<br>~~SC~~|
|---|---|---|---|---|---|---|
|IIL, IIH1, 3, 4, 5, 6, 7<br>~~SC~~|Input or I/O Leakage<br>~~SC~~|0 V < VIN< VCCIO+ 0.2 V<br>~~SC~~|—<br>~~SC~~|—<br>~~SC~~|±10<br>~~SC~~|µA<br>~~SC~~|
|C16, 7<br>~~a~~|I/O Capacitance2<br>~~ee~~|VCCIO= 3.3 V, 2.5 V, 1.8 V<br>VCC= Typ, VIO= 0 to VCCIO + 0.2 V<br>~~ee~~|—<br>~~ee~~|6<br>~~ee~~|—<br>~~ee~~|pf<br>~~ee~~|
|C26, 7|Global Input Buffer<br>Capacitance2|VCCIO= 3.3 V, 2.5 V, 1.8 V<br>VCC= Typ, VIO= 0 to VCCIO + 0.2 V|—|6|—|pf|
|VHYST<br>~~a Ge~~|Input Hysteresis<br>~~Ge~~|VCCIO= 1.8 V, 2.5 V, 3.3 V<br>~~Ge~~|—<br>~~Ge~~|200<br>~~Ge~~|—<br>~~Ge~~|mV<br>~~Ge~~|
|IPU6, 7<br>~~a Ge~~|Internal PIO Pull-up<br>~~Ge~~|VCCIO= 1.8 V, 0 ≤ VIN≤ 0.65 * VCCIO<br>~~Ge~~<br>~~es~~|−3<br>~~Ge~~<br>~~es~~|—<br>~~Ge~~<br>~~es~~|−31<br>~~Ge~~<br>~~es~~|µA<br>~~Ge~~<br>~~es~~|
|||VCCIO= 2.5 V, 0 ≤ VIN≤ 0.65 * VCCIO<br>~~es~~<br>~~es~~|−8<br>~~es~~<br>~~es~~|—<br>~~es~~<br>~~es~~|−72<br>~~es~~<br>~~es~~|µA<br>~~es~~<br>~~es~~|
|||VCCIO= 3.3 V, 0 ≤ VIN≤ 0.65 * VCCIO<br>~~es~~<br>~~po~~|−11<br>~~es~~<br>~~po~~|—<br>~~es~~<br>~~po~~|−128<br>~~es~~<br>~~po~~|µA<br>~~es~~<br>~~po~~|



## **Notes:** 

1. Input or I/O leakage current is measured with the pin configured as an input or as an I/O with the output driver tri-stated. It is not measured with the output driver active. Internal pull-up resistors are disabled. 

2. TJ 25[o] C, f = 1.0 MHz. 

3. Refer to VIL and VIH in the sysI/O Single-Ended DC Electrical Characteristics table. 

4. Only applies to I/O in the SPI bank following configuration. 

5. Some products are clamped to a diode when VIN is larger than VCCIO. 

6. High current I/O has three sysI/O buffers connected together. 

7. The iCE40LP640 and iCE40LP1K SWG16 package has CDONE and a sysI/O buffer are connected together. 

© 2011-2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02029-3.9 

23 

**iCE40 LP/HX Family Data Sheet** 

## **4.8. Static Supply Current – LP Devices** 

**Table 4.6. Supply Current– LP Devices[1, 2, 3, 4]** 

|**Symbol**|**Parameter**|**Device**|**Typ VCC4**|**Unit**|
|---|---|---|---|---|
|ICC|Core Power Supply|iCE40LP384|21|µA|
|||iCE40LP640|100|µA|
|||iCE40LP1K|100|µA|
|||iCE40LP4K|250|µA|
|||iCE40LP8K|250|µA|
|ICCPLL5, 6|PLL Power Supply|All devices|0.5|µA|
|IPP_2V5|NVCM Power Supply|All devices|1.0|µA|
|ICCIO, ICC_SPI|Bank Power Supply4<br>VCCIO= 2.5 V|All devices|3.5|µA|



## **Notes** : 

1. Assumes blank pattern with the following characteristics: all outputs are tri-stated, all inputs are configured as LVCMOS and held at VCCIO or GND, on-chip PLL is off. For more detail with your specific design, use the Power Calculator tool. Power specified with master SPI configuration mode. Other modes may be up to 25% higher. 

2. Frequency = 0 MHz. 

3. TJ = 25 °C, power supplies at nominal voltage. 

4. Does not include pull-up. 

5. No PLL available on the iCE40LP384 and iCE40LP640 device. 

6. VCCPLL is tied to VCC internally in packages without PLL pins. 

## **4.9. Static Supply Current – HX Devices** 

**Table 4.7. Supply Current– HX Devices[1, 2, 3, 4]** 

|**Symbol**|**Parameter**|**Device**|**Typ VCC4**|**Unit**|
|---|---|---|---|---|
|ICC|Core Power Supply|iCE40HX1K|296|µA|
|||iCE40HX4K|1140|µA|
|||iCE40HX8K|1140|µA|
|ICCPLL5|PLL Power Supply|All devices|0.5|µA|
|IPP_2V5|NVCM Power Supply|All devices|1.0|µA|
|ICCIO, ICC_SPI|Bank Power Supply4<br>VCCIO= 2.5 V|All devices|3.5|µA|



## **Notes** : 

1. Assumes blank pattern with the following characteristics: all outputs are tri-stated, all inputs are configured as LVCMOS and held at VCCIO or GND, on-chip PLL is off. For more detail with your specific design, use the Power Calculator tool. Power specified with master SPI configuration mode. Other modes may be up to 25% higher. 

2. Frequency = 0 MHz. 

3. TJ = 25 °C, power supplies at nominal voltage. 

4. Does not include pull-up. 

5. VCCPLL is tied to VCC internally in packages without PLL pins. 

© 2011-2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

24 

FPGA-DS-02029-3.9 

**iCE40 LP/HX Family Data Sheet** 

## **4.10. Programming NVCM Supply Current – LP Devices** 

**Table 4.8. Programming NVCM Supply Current – LP Devices[1,2,3,4 ]** 

|**Symbol**|**Parameter**|**Device**|**Typ VCC5**|**Unit**|
|---|---|---|---|---|
|ICC|Core Power Supply|iCE40LP384|60|µA|
|||iCE40LP640|120|µA|
|||iCE40LP1K|120|µA|
|||iCE40LP4K|350|µA|
|||iCE40LP8K|350|µA|
|||All devices|0.5|µA|
|ICCPLL6, 7|PLL Power Supply|All devices|2.5|mA|
|IPP_2V5|NVCM Power Supply|All devices|3.5|mA|
|ICCIO8,ICC_SPI|Bank Power Supply4|iCE40LP384|60|µA|



## **Notes:** 

1. Assumes all inputs are held at VCCIO or GND and all outputs are tri-stated. 

2. Typical user pattern. 

3. SPI programming is at 8 MHz. 

4. TJ = 25 °C, power supplies at nominal voltage. 

5. Per bank. VCCIO = 2.5 V. Does not include pull-up. 

6. No PLL available on the iCE40LP384 and iCE40LP640 devices. 

7. VCCPLL is tied to VCC internally in packages without PLLs pins. 

8. VPP_FAST, used only for fast production programming, must be left floating or unconnected in applications, except the CM36 and CM49 packages which MUST have the VPP_FAST ball connected to VCCIO_0_1 ball externally. 

## **4.11. Programming NVCM Supply Current – HX Devices** 

**Table 4.9. Programming NVCM Supply Current – HX Devices[1, 2, 3, 4 ]** 

|**Symbol**|**Parameter**|**Device**|**Typ. VCC5**|**Units**|
|---|---|---|---|---|
|ICC|Core Power Supply|iCE40HX1K|278|µA|
|||iCE40HX4K|1174|µA|
|||iCE40HX8K|1174|µA|
|ICCPLL6, 7|PLL Power Supply|All devices|0.5|µA|
|IPP_2V5|NVCM Power Supply|All devices|2.5|mA|
|ICCIO7, ICC_SPI|Bank Power Supply5|All devices|3.5|mA|



## **Notes:** 

1. Assumes all inputs are held at VCCIO or GND and all outputs are tri-stated. 

2. Typical user pattern. 

3. SPI programming is at 8 MHz. 

4. TJ = 25 °C, power supplies at nominal voltage. 

5. Per bank. VCCIO = 2.5 V. Does not include pull-up. 

6. VCCPLL is tied to VCC internally in packages without PLL pins. 

7. VPP_FAST, used only for fast production programming, must be left floating or unconnected in applications. 

© 2011-2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02029-3.9 

25 

**iCE40 LP/HX Family Data Sheet** 

## **4.12. Peak Startup Supply Current – LP Devices** 

|**Symbol**<br>~~CO~~<br>~~of~~|**Parameter**<br>~~CO~~<br>~~of~~|**Device**<br>~~CO~~|**Max**<br>~~CO~~|**Units**<br>~~CO~~<br>~~(OO~~|
|---|---|---|---|---|
|ICCPEAK<br>~~of~~|Core Power Supply<br>~~of~~|iCE40LP384|7.7|mA<br>~~(OO~~|
|||iCE40LP640<br>~~a~~|6.4|mA<br>~~(OO~~|
|||iCE40LP1K<br>~~ee~~|6.4<br>~~ee~~|mA<br>~~(OO~~<br>~~ee~~|
|||iCE40LP4K<br>~~ee~~|15.7<br>~~ee~~|mA<br>~~(OO~~<br>~~ee~~|
|||iCE40LP8K<br>~~ee~~<br>~~a~~|15.7<br>~~ee~~|mA<br>~~(OO~~<br>~~ee~~|
|ICCPLLPEAK1, 2, 4<br>~~of~~<br>~~|~~|PLL Power Supply<br>~~of~~|iCE40LP1K<br>~~a~~|1.5|mA<br>~~(OO~~|
|||iCE40LP640<br>~~a~~|1.5|mA|
|||iCE40LP4K<br>~~a~~<br>~~ee~~|8.0<br>~~ee~~|mA<br>~~ee~~|
|||iCE40LP8K<br>~~a~~<br>~~ee~~|8.0<br>~~ee~~|mA<br>~~ee~~|
|IPP_2V5PEAK<br>~~|~~<br>~~E~~<br>~~Bf~~|NVCM Power Supply<br>~~EEE~~<br>~~Bf~~|iCE40LP384<br>~~a~~<br>~~ee~~<br>~~EE~~|3.0<br>~~ee~~<br>~~EE~~|mA<br>~~ee~~<br>~~EE~~|
|||iCE40LP640<br>~~EE~~<br>~~a~~|7.7<br>~~EE~~|mA<br>~~EE~~|
|||iCE40LP1K<br>~~EE~~<br>~~a~~|7.7<br>~~EE~~|mA<br>~~EE~~|
|||iCE40LP4K<br>~~EE~~<br>~~ee~~|4.2<br>~~EE~~<br>~~ee~~|mA<br>~~EE~~<br>~~ee~~|
|||iCE40LP8K<br>~~EE~~<br>~~ee~~<br>|4.2<br>~~EE~~<br>~~ee~~<br>|mA<br>~~EE~~<br>~~ee~~<br>|
|IPP_FASTPEAK3<br>~~E~~<br>~~Bf~~<br>~~of~~|NVCM Programming<br>Supply<br>~~EEE~~<br>~~Bf ~~<br>~~of~~|iCE40LP384<br>~~EE~~<br>~~ee~~<br>~~ep~~|5.7<br>~~EE~~<br>~~ee~~<br>~~ep~~|mA<br>~~EE~~<br>~~ee~~<br>~~ep~~|
|||iCE40LP640<br>~~ee~~<br>~~ep~~<br>~~a~~|8.1<br>~~ee~~<br>~~ep~~<br>|mA<br>~~ee~~<br>~~ep~~<br>|
|||iCE40LP1K<br>~~ee~~<br> ~~ep~~<br>~~**ee**~~|8.1<br>~~ee~~<br>~~ep~~<br>~~**ee**~~|mA<br>~~ee~~<br>~~ep~~<br>~~**ee**~~|
|ICCIOPEAK5, ICC_SPIPEAK<br>~~Bf~~<br>~~of~~|Bank Power Supply<br>~~Bf ~~<br>~~of~~|iCE40LP384<br>~~ee~~<br> <br>~~**ee**~~|8.4<br>~~ee~~<br><br>~~**ee**~~|mA<br>~~ee~~<br><br>~~**ee**~~|
|||iCE40LP640<br>~~**ee**~~<br>~~ee~~|3.3<br>~~**ee**~~<br>~~ee~~|mA<br>~~**ee**~~<br>~~ee~~|
|||iCE40LP1K<br>~~**ee**~~<br>~~ee~~|3.3<br>~~**ee**~~<br>~~ee~~|mA<br>~~**ee**~~<br>~~ee~~|
|||iCE40LP4K<br>~~**ee**~~<br>~~ee~~<br>~~a~~|8.2<br>~~**ee**~~<br>~~ee~~|mA<br>~~**ee**~~<br>~~ee~~|
|||iCE40LP8K<br>~~**ee**~~|8.2<br>~~**ee**~~|mA<br>~~**ee**~~|



1. No PLL available on the iCE40LP384 and iCE40LP640 device. 

2. VCCPLL is tied to VCC internally in packages without PLLs pins. 

3. VPP_FAST, used only for fast production programming, must be left floating or unconnected in applications, except the CM36 and CM49 packages which MUST have the VPP_FAST ball connected to VCCIO_0_1 ball externally. 

4. While no PLL is available in the iCE40LP640 the ICCPLLPEAK is additive to ICCPEAK. 

5. iCE40LP384 requires VCC to be greater than 0.7 V when VCCIO and VCC_SPI are above GND. 

© 2011-2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

26 

FPGA-DS-02029-3.9 

**iCE40 LP/HX Family Data Sheet** 

## **4.13. Peak Startup Supply Current – HX Devices** 

**Table 4.11. Peak Startup Supply Current – HX Devices** 

|**Symbol**<br>~~a ~~<br>~~Bf~~|**Parameter**<br> ~~C(O~~<br>~~f~~|**Device**<br>~~C(O~~<br>~~ee~~<br>|**Max**<br>~~C(O~~<br>~~ee~~|**Units**<br>~~C(O~~<br>~~ee~~|
|---|---|---|---|---|
|ICCPEAK<br>~~Bf~~<br>~~Bf~~|Core Power Supply<br>~~f~~<br>~~f~~|iCE40HX1K<br>~~ee~~<br>|6.9<br>~~ee~~|mA<br>~~ee~~|
|||iCE40HX4K<br>~~ee~~<br>|22.3<br>~~ee~~|mA<br>~~ee~~|
|||iCE40HX8K<br>~~ee~~<br>~~**a**~~<br>~~eee~~|22.3<br>~~ee~~<br>~~eee~~|mA<br>~~ee~~<br>~~eee~~|
|ICCPLLPEAK1<br>~~Bf~~<br>~~Bf~~|PLL Power Supply<br>~~f ~~<br>~~f~~|iCE40HX1K<br>~~ee~~<br> ~~**a**~~<br>~~eee~~|1.8<br>~~ee~~<br>~~eee~~|mA<br>~~ee~~<br>~~eee~~|
|||iCE40HX4K<br> ~~**a**~~<br>~~eee~~<br>~~ee~~|6.4<br>~~eee~~<br>~~ee~~|mA<br>~~eee~~<br>~~ee~~|
|||iCE40HX8K<br> ~~**a**~~<br>~~eee~~|6.4<br>~~eee~~|mA<br>~~eee~~|
|IPP_2V5PEAK<br><br>~~Bf~~<br>~~Cf~~|NVCM Power Supply<br> <br>~~f~~<br>~~Cf~~|iCE40HX1K<br> ~~**a**~~<br>~~eee~~<br>~~a~~|2.8<br>~~eee~~|mA<br>~~eee~~|
|||iCE40HX4K<br>~~a~~|4.1|mA|
|||iCE40HX8K<br>~~a~~<br>~~ee~~|4.1<br>~~ee~~|mA<br>~~ee~~|
|ICCIOPEAK, ICC_SPIPEAK<br>~~es~~|Bank Power Supply<br>~~es~~|iCE40HX1K<br>~~es~~|6.8<br>~~es~~|mA<br>~~es~~|
|||iCE40HX4K<br>~~es~~<br>~~ee~~|6.8<br>~~es~~<br>~~ee~~|mA<br>~~es~~<br>~~ee~~|
|||iCE40HX8K<br>~~es~~<br>~~ee~~|6.8<br>~~es~~<br>~~ee~~|mA<br>~~es~~<br>~~ee~~|



## **4.14. sysI/O Recommended Operating Conditions** 

**Table 4.12. sysI/O Recommended Operating Conditions** 

|**Input/Output Standard**|**VCCIO (V)**|**VCCIO (V)**|**VCCIO (V)**|
|---|---|---|---|
||**Min.**|**Typ. **|**Max.**|
|LVCMOS 3.3|3.14|3.3|3.46|
|LVCMOS 2.5|2.37|2.5|2.62|
|LVCMOS 1.8|1.71|1.8|1.89|
|LVDS25E1, 2|2.37|2.5|2.62|
|subLVDSE1, 2|1.71|1.8|1.89|



**Notes:** 

1. Inputs on-chip. Outputs are implemented with the addition of external resistors. 

2. Does not apply to Configuration Bank VCC_SPI. 

## **4.15. sysI/O Single-Ended DC Electrical Characteristics** 

**Table 4.13. sysI/O Single-Ended DC Electrical Characteristics** 

|**Input/Output**<br>**Standard**<br>~~ee~~|**VIL**<br>~~ee~~<br>~~ee~~|**VIL**<br>~~ee~~<br>~~ee~~|**VIH1**<br>~~ee~~<br>~~ee~~<br>~~ee eee~~|**VIH1**<br>~~ee~~<br>~~ee~~<br>~~ee eee~~|**VOL Max.**<br>**(V)**<br>~~ee~~<br>~~ee~~<br>~~eee~~|**VOH Min.**<br>**(V)**<br>~~ee~~<br>~~eee~~|**IOL Max.**<br>**(mA)**<br>~~ee~~|**IOH Max.**<br>**(mA)**<br>~~ee~~|
|---|---|---|---|---|---|---|---|---|
||**Min.(V)**<br>~~ee~~<br>~~ee~~|**Max.(V)**<br>~~ee~~<br>~~ee~~|**Min.(V)**<br>~~ee~~<br>~~ee~~<br>~~ee eee~~|**Max.(V)**<br>~~ee~~<br>~~ee~~<br>~~eee~~|||||
|LVCMOS 3.3<br>~~ee~~|–0.3<br>~~ee~~|0.8<br>~~ee~~|2.0<br>~~ee~~<br>~~ee eee~~|VCCIO+ 0.2 V<br>~~ee~~<br>~~eee~~|0.4<br>~~ee~~<br>~~eee~~<br>~~ee~~|VCCIO –0.4<br>~~ee~~<br>~~eee~~<br>~~ee~~|8, 162, 242<br>~~ee~~<br>~~ee~~|–8,–162,<br>–242<br>~~ee~~<br>~~eee~~|
||||||0.2<br>~~ee~~|VCCIO –0.2<br>~~ee~~|0.1<br>~~ee~~|–0.1<br>~~eee~~|
|LVCMOS 2.5|–0.3|0.7|1.7|VCCIO+ 0.2 V|0.4<br>~~ee~~<br>~~ee~~|VCCIO –0.4<br>~~ee~~<br>~~ee~~|6, 122, 182<br>~~ee~~<br>~~ee~~|–6,–122,<br>–182<br>~~eee~~<br>~~ee~~|
||||||0.2<br>~~ee~~|VCCIO –0.2<br>~~ee~~|0.1<br>~~ee~~|–0.1<br>~~ee~~|
|LVCMOS 1.8|–0.3|0.35VCCIO|0.65VCCIO|VCCIO+ 0.2 V|0.4<br>~~ee~~<br>~~ee~~|VCCIO –0.4<br>~~ee~~<br>~~ee~~|4, 82, 122<br>~~ee ~~<br>~~ee~~|–4,–82,–<br>122<br> ~~ee~~<br>~~ee~~<br>~~ee~~|
||||||0.2<br>~~ee~~|VCCIO –0.2<br>~~ee~~|0.1<br>~~ee~~|–0.1<br>~~ee~~<br>~~ee~~|



## **Notes:** 

1. Some products are clamped to a diode when VIN is larger than VCCIO. 2. Only for High Drive LED outputs. 

© 2011-2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02029-3.9 

27 

**iCE40 LP/HX Family Data Sheet** 

## **4.16. sysI/O Differential Electrical Characteristics** 

The LVDS25E/subLVDSE differential output buffers are available on all banks but the LVDS/subLVDS input buffers are only available on Bank 3 of iCE40 LP/HX devices. 

## **4.16.1. LVDS25** 

Over recommended operating conditions. 

**Table 4.14. LVDS25** 

|**Parameter**<br>**Symbol**|**Parameter Description**|**Test**<br>**Conditions**|**Min.**|**Typ.**|**Max.**|**Units**|
|---|---|---|---|---|---|---|
|VINP,VINM|Input Voltage|VCCIO1= 2.5|0|—|2.5|V|
|VTHD|Differential Input Threshold|—|250|350|450|mV|
|VCM|Input Common Mode<br>Voltage|VCCIO1= 2.5|(VCCIO/2) - 0.3|VCCIO/2|(VCCIO/2) + 0.3|V|
|IIN|Input Current|Power on|—|—|±10|µA|



**Note:** 

1. Typical 

## **4.16.2. subLVDS** 

Over recommended operating conditions. 

**Table 4.15. subLVDS** 

|**Parameter**<br>**Symbol**|**Parameter Description**|**Test**<br>**Conditions**|**Min.**|**Typ.**|**Max.**|**Units**|
|---|---|---|---|---|---|---|
|VINP,VINM|Input Voltage|VCCIO1= 1.8|0|—|1.8|V|
|VTHD|Differential Input Threshold|—|100|150|200|mV|
|VCM|Input Common Mode<br>Voltage|VCCIO1= 1.8|(VCCIO/2) -<br>0.25|VCCIO/2|(VCCIO/2) +<br>0.25|V|
|IIN|Input Current|Power on|—|—|±10|µA|



**Note:** 

1. Typical 

## **4.17. LVDS25E Emulation** 

iCE40 LP/HX devices can support LVDSE outputs via emulation on all banks. The output is emulated using complementary LVCMOS outputs in conjunction with resistors across the driver outputs on all devices. The scheme shown in Figure 4.1. LVDS25E Using External Resistors  is one possible solution for LVDS25E standard implementation. Resistor values in Figure 4.1. LVDS25E Using External Resistors  are industry standard values for 1% resistors. 

**==> picture [448 x 121] intentionally omitted <==**

**----- Start of picture text -----**<br>
V CCIO<br>oo 1% R Output common mode voltage outputDifferential voltage<br>T ------= VOUT_B a yocttt<br>R p OD<br>x ]H R Ss =sase= VouT_A 777777750% / /x A \ \> VMannan / / )<br>(> n Vv OCM<br>Differential<br>Output Pair<br>**----- End of picture text -----**<br>


**Figure 4.1. LVDS25E Using External Resistors** 

© 2011-2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

28 

FPGA-DS-02029-3.9 

**iCE40 LP/HX Family Data Sheet** 

Over recommended operating conditions. 

**Table 4.16. LVDS25E DC Conditions** 

|**Parameter**|**Description**|**Typ. **|**Units**|
|---|---|---|---|
|ZOUT|Output impedance|20|Ω|
|RS|Driver series resistor|150|Ω|
|RP|Driverparallel resistor|140|Ω|
|RT|Receiver termination|100|Ω|
|VOH|Output high voltage|1.43|V|
|VOL|Output low voltage|1.07|V|
|VOD|Output differential voltage|0.30|V|
|VCM|Output common mode voltage|1.25|V|
|ZBACK|Back impedance|100.5|Ω|
|IDC|DC output current|6.03|mA|



## **4.18. SubLVDS Emulation** 

The iCE40 LP/HX family supports the differential subLVDS standard. The output standard is emulated using complementary LVCMOS outputs in conjunction with resistors across the driver outputs on all banks of the devices. The subLVDS input standard is supported by the LVDS25 differential input buffer. The scheme shown in Figure 4.2 is one possible solution for subLVDSE output standard implementation. Use LVDS25E mode with suggested resistors for subLVDSE operation. Resistor values in Figure 4.2 are industry standard values for 1% resistors. 

**==> picture [444 x 110] intentionally omitted <==**

**----- Start of picture text -----**<br>
V CCIO<br>Differential<br>1 R 5 1% Output common mode voltage output voltage<br>~->>->-= VOUT_B Onn yoo<br>iH<br>R p OD<br>H R Ss 50% / /x ( \ \ V / / )<br>>a Vv OCM<br>Differential<br>Output Pair<br>**----- End of picture text -----**<br>


**Figure 4.2. subLVDSE DC Conditions** 

Over recommended operating conditions. 

**Table 4.17. subLVDSE DC Conditions** 

|**Parameter**|**Description**|**Typ. **|**Units**|
|---|---|---|---|
|ZOUT|Output impedance|20|Ω|
|RS|Driver series resistor|270|Ω|
|RP|Driverparallel resistor|120|Ω|
|RT|Receiver termination|100|Ω|
|VOH|Output high voltage|1.43|V|
|VOL|Output low voltage|1.07|V|
|VOD|Output differential voltage|0.35|V|
|VCM|Output common mode voltage|0.9|V|
|ZBACK|Back impedance|100.5|Ω|
|IDC|DC output current|2.8|mA|



© 2011-2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02029-3.9 

29 

**iCE40 LP/HX Family Data Sheet** 

## **4.19. Typical Building Block Function Performance – LP Devices**[1,2] 

## **4.19.1. Pin-to-Pin Performance (LVCMOS25) – LP Devices** 

**Table 4.18. Pin-to-Pin Performance (LVCMOS25) – LP Devices Function Timing Units Basic Functions** 16-bit decoder 11.0 ns 4:1 MUX 12.0 ns 16:1 MUX 13.0 ns ~~ae~~ **4.19.2. Register-to-Register Performance – LP Devices Table 4.19. Register-to-Register Performance – LP Devices Function Timing Units Basic Functions** 16:1 MUX 190 MHz 16-bit adder 160 MHz 16-bit counter 175 MHz **Embedded Memory Functions** 256 x 16 Pseudo-Dual Port RAM 240 MHz ~~a~~ **Notes:** 1. The above timing numbers are generated using the iCECube2 design tool. Exact performance may vary with device and tool version. The tool uses internal parameters that have been characterized but are not tested on every device. 

2. Using a VCC of 1.14 V at Junction Temp 85 °C. 

## **4.20. Typical Building Block Function Performance – HX Devices**[1,2] 

## **4.20.1. Pin-to-Pin Performance (LVCMOS25) – HX Devices** 

|**Function**<br>~~a~~|**Timing**<br>~~a~~|**Units**<br>~~a~~|
|---|---|---|
|**Basic Functions**<br>~~a~~|||
|16-bit decoder<br>~~a~~|10.0<br>~~a~~|ns<br>~~a~~|
|4:1 MUX<br>~~a~~|9.0<br>~~a~~|ns<br>~~a~~|
|16:1 MUX<br>~~a~~|9.5<br>~~a~~|ns<br>~~a~~|



© 2011-2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

30 

FPGA-DS-02029-3.9 

**iCE40 LP/HX Family Data Sheet** 

## **4.20.2. Register-to-Register Performance – HX Devices** 

**Table 4.21. Register-to-Register Performance – HX Devices** 

|**Function**|**Timing**|**Units**|
|---|---|---|
|**Basic Functions**|||
|16:1 MUX|305|MHz|
|16-bit adder|220|MHz|
|16-bit counter|255|MHz|
|64-bit counter|105|MHz|
|**Embedded Memory Functions**|||
|256 x 16 Pseudo-Dual Port RAM|403|MHz|



## **Notes:** 

1. The above timing numbers are generated using the iCECube2 design tool. Exact performance may vary with device and tool version. The tool uses internal parameters that have been characterized but are not tested on every device. 

2. Using a VCC of 1.14 V at Junction Temp 85 °C. 

## **4.21. Derating Logic Timing** 

Logic timing provided in the following sections of the data sheet and the Lattice design tools are worst case numbers in the operating range. Actual delays may be much faster. Lattice design tools can provide logic timing numbers at a particular temperature and voltage. 

## **4.22. Maximum sysI/O Buffer Performance** 

**Table 4.22. Register-to-Register Performance**[1] 

|**I/O Standard**|**Max. Speed**|**Units**|
|---|---|---|
|**Inputs**|||
|LVDS252|400|MHz|
|subLVDS182|400|MHz|
|LVCMOS33|250|MHz|
|LVCMOS25|250|MHz|
|LVCMOS18|250|MHz|
|**Outputs**|||
|LVDS25E|250|MHz|
|subLVDS18E|155|MHz|
|LVCMOS33|250|MHz|
|LVCMOS25|250|MHz|
|LVCMOS18|155|MHz|



## **Notes:** 

1. Measured with a toggling pattern. 

2. Supported in Bank 3 only. 

© 2011-2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02029-3.9 

31 

**iCE40 LP/HX Family Data Sheet** 

## **4.23. Timing Adders** 

Over recommended operating conditions. 

**Table 4.23. Timing Adders – LP Devices**[1,2,3,4,5] 

|**Input Adjusters**|**Input Adjusters**|**Input Adjusters**|**Input Adjusters**|
|---|---|---|---|
|LVDS25|LVDS, VCCIO= 2.5 V|–0.18|ns|
|subLVDS|subLVDS, VCCIO= 1.8 V|0.82|ns|
|LVCMOS33|LVCMOS, VCCIO= 3.3 V|0.18|ns|
|LVCMOS25|LVCMOS, VCCIO= 2.5 V|0.00|ns|
|LVCMOS18|LVCMOS, VCCIO= 1.8 V|0.19|ns|
|**Output Adjusters**||||
|LVDS25E|LVDS, Emulated, VCCIO= 2.5 V|0.00|ns|
|subLVDSE|subLVDS, Emulated, VCCIO= 1.8 V|1.32|ns|
|LVCMOS33|LVCMOS, VCCIO= 3.3 V|–0.12|ns|
|LVCMOS25|LVCMOS, VCCIO= 2.5 V|0.00|ns|
|LVCMOS18|LVCMOS, VCCIO= 1.8 V|1.32|ns|



## **Notes:** 

1. Timing adders are relative to LVCMOS25 and characterized but not tested on every device. 

2. LVCMOS timing measured with the load specified in the Switching Test Condition table. 

3. All other standards tested according to the appropriate specifications. 

4. Commercial timing numbers are shown. 

5. Not all I/O standards are supported for all banks. See the Architecture section of this data sheet for details. 

© 2011-2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

32 

FPGA-DS-02029-3.9 

**iCE40 LP/HX Family Data Sheet** 

Over recommended operating conditions. 

**Table 4.24. Timing Adders – HX Devices**[1,2,3,4,5] 

|**Input Adjusters**|**Input Adjusters**|**Input Adjusters**|**Input Adjusters**|
|---|---|---|---|
|LVDS25|LVDS, VCCIO= 2.5 V|0.13|ns|
|subLVDS|subLVDS, VCCIO= 1.8 V|1.03|ns|
|LVCMOS33|LVCMOS, VCCIO= 3.3 V|0.16|ns|
|LVCMOS25|LVCMOS, VCCIO= 2.5 V|0.00|ns|
|LVCMOS18|LVCMOS, VCCIO= 1.8 V|0.23|ns|
|**Output Adjusters**||||
|LVDS25E|LVDS, Emulated, VCCIO= 2.5 V|0.00|ns|
|subLVDSE|subLVDS, Emulated, VCCIO= 1.8 V|1.76|ns|
|LVCMOS33|LVCMOS, VCCIO= 3.3 V|0.17|ns|
|LVCMOS25|LVCMOS, VCCIO= 2.5 V|0.00|ns|
|LVCMOS18|LVCMOS, VCCIO= 1.8 V|1.76|ns|



## **Notes:** 

1. Timing adders are relative to LVCMOS25 and characterized but not tested on every device. 

2. LVCMOS timing measured with the load specified in the Switching Test Condition table. 

3. All other standards tested according to the appropriate specifications. 

4. Commercial timing numbers are shown. 

5. Not all I/O standards are supported for all banks. See the Architecture section of this data sheet for details. 

## **4.24. External Switching Characteristics – LP Devices** 

Over recommended operating conditions. 

**Table 4.25. External Switching Characteristics – LP Devices[1, 2 ]** 

|**Parameter**<br>~~a ~~|**Description**<br> ~~C~~|**Device**<br>~~C~~|**Min.**<br>~~C~~|**Max.**<br>~~C~~|**Units**<br>~~C~~|
|---|---|---|---|---|---|
|**Clock**<br>~~pe~~||||||
|**Global Clocks**||||||
|fMAX_GBUF<br>~~a~~|Frequencyfor Global Buffer Clock network|All iCE40 LP devices|—|275|MHz|
|tW_GBUF<br>~~a~~<br>~~a~~|Clock Pulse Width for Global Buffer|All iCE40 LP devices|0.92|—|ns|
|tSKEW_GBUF|Global Buffer Clock Skew Within a Device|iCE40LP384<br>~~ee~~|—<br>~~ee~~<br>~~ee~~|370<br>~~ee~~<br>~~ee~~|ps<br>~~ee~~|
|||iCE40LP640<br>~~ee~~|—<br>~~ee~~<br>~~ee~~<br>~~ee~~|230<br>~~ee~~<br>~~ee~~<br>~~ee~~|ps<br>~~ee~~|
|||iCE40LP1K<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|230<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|ps<br>~~ee~~<br>~~ee~~|
|||iCE40LP4K<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|340<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|ps<br>~~ee~~<br>~~ee~~|
|||iCE40LP8K<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~<br>~~ee~~|340<br>~~ee~~<br>~~ee~~<br>~~ee~~|ps<br>~~ee~~<br>~~ee~~|
|**Pin-LUT-Pin Propagation Delay**||||||
|tPD<br>~~eC~~|Best casepropagation delaythrough one LUT-4<br>~~eC~~|All iCE40 LP devices<br>~~eC~~|—<br>~~eC~~|9.36<br>~~eC~~|ns<br>~~eC~~|
|**General I/O Pin Parameters(Using Global Buffer Clock without PLL)**3<br>~~ee~~<br>~~ee~~||||||
|tSKEW_IO|Data bus skew across a bank of IOs|iCE40LP384<br>~~ee~~|—<br>~~ee~~<br>~~ee~~<br>~~ee~~|300<br>~~ee~~<br>~~ee~~|ps<br>~~ee~~|
|||iCE40LP640<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|200<br>~~ee~~<br>~~ee~~<br>~~ee~~|ps<br>~~ee~~<br>~~ee~~|
|||iCE40LP1K<br>~~ee~~|—<br>~~ee~~<br>~~ee~~<br>~~ee~~|200<br>~~ee~~|ps<br>~~ee~~|
|||iCE40LP4K<br>~~ee~~|—<br>~~ee~~<br>~~ee~~<br>~~ee~~|280<br>~~ee~~<br>~~ee~~|ps<br>~~ee~~|
|||iCE40LP8K<br>~~ee~~|—<br>~~ee~~<br>~~ee~~<br>~~ee~~|280<br>~~ee~~<br>~~ee~~<br>~~ee~~|ps<br>~~ee~~|
|tCO|Clock to Output - PIO Output Register|iCE40LP384<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|6.33<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|ns<br>~~ee~~<br>~~ee~~|
|||iCE40LP640<br>~~ee~~<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>|5.91<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>|ns<br>~~ee~~<br>~~ee~~|
|||iCE40LP1K<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>|5.91<br>~~ee~~<br>~~ee~~<br>|ns<br>~~ee~~|
|||iCE40LP4K<br>~~ee ~~|—<br>~~ee~~<br> ~~ee~~<br>~~ee ee~~|6.58<br>~~ee~~<br>~~ee~~<br>~~ee~~|ns|
|||iCE40LP8K<br>~~ee ~~<br>~~ee~~|—<br>~~ee ~~<br> <br>~~ee~~<br>~~ee ee~~|6.58<br> ~~ee~~<br><br>~~ee~~<br>~~ee~~|ns<br>~~ee~~|



© 2011-2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02029-3.9 

33 

**iCE40 LP/HX Family Data Sheet** 

|**Parameter**<br>~~eC~~|**Description**<br>~~eC~~|**Device**<br>~~eC~~|**Min.**<br>~~eC~~<br>~~ee~~|**Max.**<br>~~eC~~<br>~~ee~~|**Units**<br>~~eC~~<br>~~ee~~|
|---|---|---|---|---|---|
|tSU|Clock to Data Setup - PIO Input Register|iCE40LP384<br>~~ee~~|–0.08<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~|ns<br>~~ee~~<br>~~ee~~|
|||iCE40LP640<br>~~ee~~|–0.33<br>~~ee ~~<br>~~ee~~<br>~~ee~~|—<br> ~~ee~~<br>~~ee~~<br>~~ee~~|ns<br>~~ee~~<br>~~ee~~|
|||iCE40LP1K<br>~~ee~~<br>~~ee~~|–0.33<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|ns<br>~~ee~~<br>~~ee~~<br>~~ee~~|
|||iCE40LP4K<br>~~ee~~|–0.63<br>~~ee ~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|—<br> ~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|ns<br>~~ee~~<br>~~ee~~<br>~~ee~~|
|||iCE40LP8K<br>~~ee~~|–0.63<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|ns<br>~~ee~~<br>~~ee~~<br>~~ee~~|
|tH|Clock to Data Hold - PIO Input Register|iCE40LP384<br>~~ee~~|1.99<br>~~ee ~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|—<br> ~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|ns<br>~~ee~~<br>~~ee~~<br>~~ee~~|
|||iCE40LP640<br>~~ee~~<br>~~ee~~<br>~~ee~~|2.81<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>|—<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>|ns<br>~~ee~~<br>~~ee~~<br>~~ee~~|
|||iCE40LP1K<br>~~ee~~<br>~~ee~~|2.81<br>~~ee ~~<br>~~ee~~<br>~~ee~~<br>|—<br> ~~ee~~<br>~~ee~~<br>|ns<br>~~ee~~<br>~~ee~~|
|||iCE40LP4K<br>~~ee ~~|3.48<br>~~ee~~<br> ~~ee~~|—<br>~~ee~~|ns|
|||iCE40LP8K<br>~~ee ~~<br>~~ee~~|3.48<br>~~ee~~<br> <br>~~ee~~|—<br><br>~~ee~~|ns<br>~~ee~~|
|**General I/O Pin Parameters(Using Global Buffer Clock with PLL)3**<br>~~eeee~~||||||
|tCOPLL|Clock to Output - PIO Output Register|iCE40LP1K<br>~~ee~~|—<br>~~ee~~<br>~~ee~~|2.20<br>~~ee~~|ns|
|||iCE40LP4K<br>~~ee ~~<br>~~ee~~|—<br> ~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|2.30<br>~~ee~~<br>~~ee~~<br>~~ee~~|ns<br>~~ee~~<br>~~ee~~|
|||iCE40LP8K<br>~~ee~~|—<br>~~ee~~<br>~~ee~~<br>~~ee~~|2.30<br>~~ee~~<br>~~ee~~|ns<br>~~ee~~<br>~~ee~~|
|tSUPLL|Clock to Data Setup - PIO Input Register|iCE40LP1K<br>~~ee~~|5.23<br>~~ee ~~<br>~~ee~~<br>~~ee~~|—<br> ~~ee~~<br>~~ee~~<br>~~ee~~|ns<br>~~ee~~<br>~~ee~~|
|||iCE40LP4K<br>~~ee~~<br>~~ee~~|6.13<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>|—<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>|ns<br>~~ee~~<br>~~ee~~|
|||iCE40LP8K<br>~~ee~~<br>~~ee~~<br>~~ee~~|6.13<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>|—<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>|ns<br>~~ee~~<br>~~ee~~<br>~~ee~~|
|tHPLL|Clock to Data Hold - PIO Input Register|iCE40LP1K<br>~~ee ~~|–0.90<br>~~ee~~<br> ~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~|ns<br>~~ee~~|
|||iCE40LP4K<br>~~ee ~~<br>~~ee~~|–0.80<br>~~ee ~~<br> <br>~~ee~~<br>~~ee~~|—<br> ~~ee ~~<br><br>~~ee~~|ns<br> ~~ee~~<br>~~ee~~|
|||iCE40LP8K<br>~~ee~~|–0.80<br>~~ee~~<br>~~ee~~|—<br>~~ee~~|ns<br>~~ee~~|



## **Notes:** 

1. Exact performance may vary with device and design implementation. Commercial timing numbers are shown at 85°C and 1.14 V. Other operating conditions can be extracted from the iCECube2 software. 

2. General I/O timing numbers based on LVCMOS 2.5, 0 pf load. 

3. Supported on devices with a PLL. 

## **4.25. External Switching Characteristics – HX Devices** 

Over recommended operating conditions. 

**Table 4.26. External Switching Characteristics – HX Devices[1, 2 ]** 

|**Parameter**<br>~~a~~|**Description**<br>~~a~~|**Device**<br>~~a~~<br>~~C~~|**Min.**<br>~~a~~|**Max.**<br>~~a~~|**Units**<br>~~a~~|
|---|---|---|---|---|---|
|**Clock**<br>~~C~~<br>~~pe~~||||||
|**Global Clocks**||||||
|fMAX_GBUF<br>~~a ~~|Frequencyfor Global Buffer Clock network<br> ~~eG~~|All iCE40 HX devices<br>~~eG~~|—<br>~~eG~~|275<br>~~eG~~|MHz<br>~~eG~~|
|tW_GBUF<br>~~a ~~|Clock Pulse Width for Global Buffer<br> ~~G~~|All iCE40 HX devices<br>~~G~~|0.88<br>~~G~~|—<br>~~G~~|ns<br>~~G~~|
|tSKEW_GBUF|Global Buffer Clock Skew Within a Device|iCE40HX1K<br>~~ee~~|—<br>~~ee~~<br>~~ee~~|727<br>~~ee~~<br>~~ee~~|ps<br>~~ee~~|
|||iCE40HX4K<br>~~ee~~|—<br>~~ee~~<br>~~ee~~<br>~~ee~~|300<br>~~ee~~<br>~~ee~~<br>~~ee~~|ps<br>~~ee~~|
|||iCE40HX8K<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|300<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|ps<br>~~ee~~<br>~~ee~~|
|**Pin-LUT-Pin Propagation Delay**<br>~~ee~~<br>~~ee~~<br>~~ee~~||||||
|tPD<br>~~a~~|Best casepropagation delaythrough one LUT-4<br>|All iCE40 HX devices<br>|—<br>|7.30<br>|ns<br>|
|**General I/O Pin Parameters(Using Global Buffer Clock without PLL)**<br>~~pt~~<br>~~ee~~<br>~~ee~~||||||
|tSKEW_IO|Data bus skew across a bank of IOs|iCE40HX1K<br>~~ee~~|—<br>~~ee~~<br>~~ee~~<br>~~ee~~|696<br>~~ee~~<br>~~ee~~<br>~~ee~~|ps<br>~~ee~~|
|||iCE40HX4K<br>~~ee~~<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>|290<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>|ps<br>~~ee~~<br>~~ee~~|
|||iCE40HX8K<br>~~ee~~<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>|290<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>|ps<br>~~ee~~<br>~~ee~~|
|tCO|Clock to Output - PIO Output Register|iCE40HX1K<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~<br>|5.00<br>~~ee~~<br>~~ee~~<br>|ns|
|||iCE40HX4K<br>~~ee ~~<br>~~ee ~~|—<br>~~ee ~~<br> ~~ee~~<br> ~~ee~~<br>~~ee ee~~|5.41<br> ~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|ns|
|||iCE40HX8K<br> <br>~~ee ~~<br>~~ee~~|—<br> ~~ee~~<br> <br>~~ee~~<br>~~ee ee~~|5.41<br>~~ee~~<br><br>~~ee~~<br>~~ee~~|ns<br>~~ee~~|



© 2011-2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

34 

FPGA-DS-02029-3.9 

**iCE40 LP/HX Family Data Sheet** 

|**Parameter**<br>~~eC~~|**Description**<br>~~eC~~|**Device**<br>~~eC~~|**Min.**<br>~~eC~~<br>~~ee~~|**Max.**<br>~~eC~~|**Units**<br>~~eC~~|
|---|---|---|---|---|---|
|tSU|Clock to Data Setup - PIO Input Register|iCE40HX1K<br>~~ee~~|–0.23<br>~~ee~~<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~|ns<br>~~ee~~|
|||iCE40HX4K<br>~~ee~~<br>~~ee~~|–0.43<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~<br>~~ee~~|ns<br>~~ee~~|
|||iCE40HX8K<br>~~ee~~<br>~~ee~~<br>~~ee~~|–0.43<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|ns<br>~~ee~~<br>~~ee~~|
|tH|Clock to Data Hold - PIO Input Register|iCE40HX1K<br>~~ee~~|1.92<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~|ns|
|||iCE40HX4K<br>~~ee~~<br>~~ee~~|2.38<br>~~ee ~~<br>~~ee~~|—<br> ~~ee~~<br>~~ee~~|ns<br>~~ee~~|
|||iCE40HX8K<br>~~es~~|2.38<br>~~es~~|—<br>~~es~~|ns<br>~~es~~|
|**General I/O Pin Parameters(Using Global Buffer Clock with PLL)3**<br>~~eeee~~||||||
|tCOPLL|Clock to Output - PIO Output Register|iCE40HX1K<br>~~ee~~|—<br>~~ee~~<br>~~ee~~|2.96<br>~~ee~~|ns|
|||iCE40HX4K<br>~~ee ~~<br>~~ee~~|—<br> ~~ee~~<br>~~ee~~<br>~~ee~~|2.51<br>~~ee~~<br>~~ee~~|ns<br>~~ee~~|
|||iCE40HX8K<br>~~ee~~|—<br>~~ee~~<br>~~ee~~|2.51<br>~~ee~~|ns<br>~~ee~~|
|tSUPLL|Clock to Data Setup - PIO Input Register|iCE40HX1K<br>~~ee~~|3.10<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~|ns<br>~~ee~~|
|||iCE40HX4K<br>~~ee~~<br>~~ee~~|4.16<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>|—<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>|ns<br>~~ee~~<br>~~ee~~|
|||iCE40HX8K<br>~~ee~~<br>~~ee~~<br>~~ee~~|4.16<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>|—<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>|ns<br>~~ee~~<br>~~ee~~<br>~~ee~~|
|tHPLL|Clock to Data Hold - PIO Input Register|iCE40HX1K<br>~~ee~~<br>~~ee~~|–0.60<br>~~ee~~<br>~~ee~~<br>|—<br>~~ee~~<br>~~ee~~<br>|ns<br>~~ee~~|
|||iCE40HX4K<br>~~ee ~~<br>~~ee ~~|–0.53<br>~~ee ~~<br> ~~ee~~<br> ~~ee~~|—<br> ~~ee ~~<br>~~ee~~<br>~~ee~~|ns<br> ~~ee~~|
|||iCE40HX8K<br> <br>~~ee ~~<br>~~ee~~|–0.53<br> ~~ee~~<br> <br>~~ee~~|—<br>~~ee~~<br><br>~~ee~~|ns<br>~~ee~~|



## **Notes:** 

1. Exact performance may vary with device and design implementation. Commercial timing numbers are shown at 85 °C and 1.14 V. Other operating conditions, including industrial, can be extracted from the iCECube2 software. 

2. General I/O timing numbers based on LVCMOS 2.5, 0pf load. 

3. Supported on devices with a PLL. 

## **4.26. sysClock PLL Timing** 

|**Parameter**<br>~~ee~~|**Descriptions**|**Conditions**|**Min.**|**Max.**|**Units**|
|---|---|---|---|---|---|
|fIN<br>~~ee~~|Input Clock Frequency<br>(REFERENCECLK, EXTFEEDBACK)|—|10|133|MHz|
|fOUT<br>~~ee~~<br>~~a~~|Output Clock Frequency (PLLOUT)|—|16|275|MHz|
|fVCO<br>~~ee~~<br>~~a~~<br>~~a~~|PLL VCO Frequency|—|533|1066|MHz|
|**AC Characteristics**||||||
|tDT<br>~~a~~|Output Clock Duty Cycle<br>~~ee~~<br>~~ee~~|fOUT< 175 MHz<br>~~ee~~|40<br>~~ee~~|50<br>~~ee~~|%<br>~~ee~~|
|||175 MHz < fOUT< 275<br>MHz<br>~~ee~~<br>~~ee~~|35<br>~~ee~~<br>~~ee~~|65<br>~~ee~~|"%<br>~~ee~~|
|tPH<br>~~eG~~|Output Phase Accuracy<br>~~eG~~<br>~~ee~~|—<br>~~eG~~<br>~~ee~~|—<br>~~eG~~<br>~~ee~~|+/–12<br>~~eG~~|deg<br>~~eG~~|
|tOPJIT1, 5<br>~~eG~~<br>~~a~~|Output Clock Period Jitter<br>~~eG~~<br>~~ee~~<br>~~OO~~|fOUT<= 100 MHz<br>~~eG~~<br>~~ee~~<br>|—<br>~~eG~~<br>~~ee~~<br>~~**e**e~~<br>|450<br>~~eG~~|psp-p<br>~~eG~~|
|||fOUT> 100 MHz<br>~~ee~~<br>~~ee~~<br>|—<br>~~ee~~<br>~~ee~~<br>~~**e**e~~<br>|0.05<br>~~ee~~|UIPP<br>~~ee~~|
||Output Clock Cycle-to-cycle Jitter<br>~~ee ~~<br>~~OO~~|fOUT<= 100 MHz<br>~~ee~~<br>|—<br>~~ee~~<br>~~**e**e~~<br>|750|psp-p|
|||fOUT> 100 MHz<br> ~~ee~~<br>~~e~~|—<br>~~ee~~<br>~~**e**e~~<br>~~e~~|0.10|UIPP|
||Output Clock Phase Jitter<br>~~ee~~|fPFD<= 25 MHz<br>~~ee~~|—<br>~~ee~~<br>~~ee~~|275<br>~~ee~~<br>~~ee~~|psp-p<br>~~ee~~|
|||fPFD> 25 MHz<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~<br>~~ee~~|0.05<br>~~ee~~<br>~~ee~~<br>~~ee~~|UIPP<br>~~ee~~<br>~~ee~~|
|tW<br>~~a~~|Output Clock Pulse Width<br>~~ee~~|At 90% or 10%<br>~~ee~~<br>~~ee~~|1.3<br>~~ee~~<br>~~ee~~<br>~~ee ~~|—<br>~~ee~~<br>~~ee~~<br> ~~ee~~|ns<br>~~ee~~<br>~~ee~~|
|tLOCK2, 3<br>~~a~~|PLL Lock-in Time<br>|—<br>|—<br>|50<br>|us<br>|
|tUNLOCK<br>~~eC~~|PLL Unlock Time<br>~~eC~~|—<br>~~eC~~|—<br>~~eC~~|50<br>~~eC~~|ns<br>~~eC~~|
|tIPJIT4<br>~~a~~|Input Clock Period Jitter|fPFD 20 MHz<br>~~ee~~|—<br>~~ee~~<br>~~ee~~|1000<br>~~ee~~<br>~~ee~~|ps p-p<br>~~ee~~|
|||fPFD< 20 MHz<br>~~ee~~|—<br>~~ee~~<br>~~ee~~|0.02<br>~~ee~~<br>~~ee~~|UIPP<br>~~ee~~|



© 2011-2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02029-3.9 

35 

**iCE40 LP/HX Family Data Sheet** 

|**Parameter**<br>~~a eC~~|**Descriptions**<br>~~eC~~|**Conditions**<br>~~eC~~|**Min.**<br>~~eC~~|**Max.**<br>~~eC~~|**Units**<br>~~eC~~|
|---|---|---|---|---|---|
|tFDTAP<br>~~a eG~~|Fine Delayadjustment,per Tap<br>~~eG~~|—<br>~~eG~~|147<br>~~eG~~|195<br>~~eG~~|ps<br>~~eG~~|
|tSTABLE3<br>~~a~~|LATCHINPUTVALUE LOW to PLL Stable|—|—|500|ns|
|tSTABLE_PW3<br>~~a~~|LATCHINPUTVALUE Pulse Width|—|—|100|ns|
|tRST<br>~~a~~<br>~~a eG~~|RESET Pulse Width<br>~~eG~~|—<br>~~eG~~|10<br>~~eG~~|—<br>~~eG~~|ns<br>~~eG~~|
|tRSTREC|RESET RecoveryTime|—|10|—|us|
|tDYNAMIC_WD<br>~~a~~|DYNAMICDELAY Pulse Width<br>|—<br>|100<br>|—<br>|VCO<br>Cycles<br>|
|tPDBYPASS<br>~~py~~|Propagation delay with the PLL in bypass mode<br>~~py~~|iCE40 LP<br>~~py~~|1.18<br>~~py~~|4.68<br>~~py~~|ns<br>~~py~~|
|||iCE40 HX<br>~~py~~<br>~~ee~~|1.73<br>~~py~~<br>~~ee~~|4.07<br>~~py~~<br>~~ee~~|ns<br>~~py~~<br>~~ee~~|



1. Period jitter sample is taken over 10,000 samples of the primary PLL output with a clean reference clock. Cycle-to-cycle jitter is taken over 1000 cycles. Phase jitter is taken over 2000 cycles. All values per JESD65B. 

2. Output clock is valid after tLOCK for PLL reset and dynamic delay adjustment. 

3. At minimum fPFD. As the fPFD increases the time will decrease to approximately 60% the value listed. 

4. Maximum limit to prevent PLL unlock from occurring. Does not imply the PLL will operate within the output specifications listed in this table. 

5. The jitter values will increase with loading of the PLD fabric and in the presence of SSO noise. 

## **4.27. SPI Master or NVCM Configuration Time** 

**Table 4.28. SPI Master or NVCM Configuration Time[1, 2 ]** 

|**Symbol**<br>~~a~~|**Parameter**|**Condition**|**Typ. **|**Units**|
|---|---|---|---|---|
|tCONFIG|POR/CRESET_B to<br>Device I/O Active|iCE40LP384 - Low Frequency (Default)<br>~~a~~|25<br>~~a~~|ms<br>~~a~~|
|||iCE40LP384 - Medium Frequency<br>~~a~~|15<br>~~a~~|ms<br>~~a~~|
|||iCE40LP384 - High Frequency<br>~~ee~~|11<br>~~ee~~|ms<br>~~ee~~|
|||iCE40LP640 - Low Frequency (Default)<br>~~ee~~<br>~~pf~~|53<br>~~ee~~<br>~~pf~~|ms<br>~~ee~~<br>~~pf~~|
|||iCE40LP640 - Medium Frequency<br>~~po~~|25<br>~~po~~|ms<br>~~po~~|
|||iCE40LP640 - High Frequency<br>~~ee~~|13<br>~~ee~~|ms<br>~~ee~~|
|||iCE40LP/HX1K - Low Frequency (Default)<br>~~ee~~<br>~~ee~~|53<br>~~ee~~<br>~~ee~~|ms<br>~~ee~~<br>~~ee~~|
|||iCE40LP/HX1K - Medium Frequency<br>~~ee~~<br>~~a~~|25<br>~~ee~~<br>~~a~~|ms<br>~~ee~~<br>~~a~~|
|||iCE40LP/HX1K - High Frequency<br>~~a~~<br>~~a~~|13<br>~~a~~<br>~~a~~|ms<br>~~a~~<br>~~a~~|
|||iCE40LP/HX4K - Low Frequency (Default)<br>~~po~~|230<br>~~po~~|ms<br>~~po~~|
|||iCE40LP/HX4K - Medium Frequency<br>~~ee~~|110<br>~~ee~~|ms<br>~~ee~~|
|||iCE40LP/HX4K - High Frequency<br>~~ee~~|70<br>~~ee~~|ms<br>~~ee~~|
|||iCE40LP/HX8K - Low Frequency (Default)<br>~~ee~~<br>~~a~~|230<br>~~ee~~<br>~~a~~|ms<br>~~ee~~<br>~~a~~|
|||iCE40LP/HX8K - Medium Frequency<br>~~a~~<br>~~a~~|110<br>~~a~~<br>~~a~~|ms<br>~~a~~<br>~~a~~|
|||iCE40LP/HX8K - High Frequency<br>~~a~~|70<br>~~a~~|ms<br>~~a~~|



## **Notes:** 

1. Assumes sysMEM Block is initialized to an all zero pattern if they are used. 

2. The NVCM download time is measured with a fast ramp rate starting from the maximum voltage of POR trip point. 

© 2011-2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

36 

FPGA-DS-02029-3.9 

**iCE40 LP/HX Family Data Sheet** 

## **4.28. sysCONFIG Port Timing Specifications** 

|**Symbol**<br>~~es~~|**Parameter**<br>|**Parameter**<br>|**Min**<br>|**Typ**<br>|**Max**<br>|**Unit**<br>|
|---|---|---|---|---|---|---|
|**All Configuration Modes**<br>~~es|~~|||||||
|tCRESET_B|Minimum CRESET_B Low<br>pulse width required to<br>restart configuration, from<br>fallingedge to risingedge|—|200|—|—|ns|
|tDONE_IO<br>~~a~~|Number of configuration<br>clock cycles after CDONE goes<br>High before the PIO pins are<br>activated<br>~~a~~|—<br>~~a~~|49<br>~~a~~|—<br>~~a~~|—<br>~~a~~|Clock<br>Cycles<br>~~a~~|
|**Slave SPI**<br>~~a~~|||||||
|tCR_SCK<br>~~a~~<br>~~|~~|Minimum time from a rising<br>edge on CRESET_B until the<br>first SPI write operation, first<br>SPI_SCK. During this time, the<br>iCE40 device is clearing its<br>internal configuration<br>memory.<br>~~a~~|iCE40LP384<br>~~a~~<br>~~a~~<br>~~ee~~<br>~~At~~|600<br>~~a~~<br>~~a~~<br>~~ee~~<br>~~At~~|—<br>~~a~~<br>~~a~~<br>~~ee~~<br>~~At~~|—<br>~~a~~<br>~~a~~<br>~~ee~~<br>~~At~~|us<br>~~a~~<br>~~a~~<br>~~ee~~<br>~~At~~|
|||iCE40LP640, iCE40LP/HX1K<br>~~a~~<br>~~ee~~<br>~~At~~|800<br>~~a~~<br>~~ee~~<br>~~At~~|—<br>~~a~~<br>~~ee~~<br>~~At~~|—<br>~~a~~<br>~~ee~~<br>~~At~~|us<br>~~a~~<br>~~ee~~<br>~~At~~|
|||iCE40LP/HX4K<br>~~ee~~<br>~~At~~|1200<br>~~ee~~<br>~~At~~|—<br>~~ee~~<br>~~At~~|—<br>~~ee~~<br>~~At~~|us<br>~~ee~~<br>~~At~~|
|||iCE40LP/HX8K<br>~~ee~~<br>~~At~~|1200<br>~~ee~~<br>~~At~~|—<br>~~ee~~<br>~~At~~|—<br>~~ee~~<br>~~At~~|us<br>~~ee~~<br>~~At~~|
|fMAX<br>~~=~~|CCLK clock frequency<br>~~=~~|Write<br>~~a~~|1<br>~~a~~|—<br>~~a~~|25<br>~~a~~|MHz<br>~~a~~|
|||Read iCE40LP3842<br>~~a~~<br>~~====~~|—<br>~~a~~<br>~~====~~|15<br>~~a~~<br>~~====~~|—<br>~~a~~<br>~~====~~|MHz<br>~~a~~<br>~~====~~|
|||Read iCE40LP640, iCE40LP/HX1K2<br>~~a~~<br>~~====~~<br>~~ee~~|—<br>~~a~~<br>~~====~~<br>~~ee~~|15<br>~~a~~<br>~~====~~<br>~~ee~~|—<br>~~a~~<br>~~====~~<br>~~ee~~|MHz<br>~~a~~<br>~~====~~<br>~~ee~~|
|||Read iCE40LP/HX4K2<br>~~a~~<br>~~ee~~<br>~~ee~~|—<br>~~a~~<br>~~ee~~<br>~~ee~~|15<br>~~a~~<br>~~ee~~<br>~~ee~~|—<br>~~a~~<br>~~ee~~<br>~~ee~~|MHz<br>~~a~~<br>~~ee~~<br>~~ee~~|
|||Read iCE40LP/HX8K2<br>~~a~~<br>~~ee~~<br>~~ee~~|—<br>~~a~~<br>~~ee~~<br>~~ee~~|15<br>~~a~~<br>~~ee~~<br>~~ee~~|—<br>~~a~~<br>~~ee~~<br>~~ee~~|MHz<br>~~a~~<br>~~ee~~<br>~~ee~~|
|tCCLKH<br>~~=~~<br>~~a~~|CCLK clockpulse width high<br>~~=~~<br>~~a~~|—<br>~~a~~<br>~~ee~~<br>~~a~~|20<br>~~a~~<br>~~ee~~<br>~~a~~|—<br>~~a~~<br>~~ee~~<br>~~a~~|—<br>~~a~~<br>~~ee~~<br>~~a~~|ns<br>~~a~~<br>~~ee~~<br>~~a~~|
|tCCLKL<br>~~a~~<br>~~a~~|CCLK clockpulse width low<br>~~a~~<br>~~a~~|—<br>~~a~~<br>~~a~~|20<br>~~a~~<br>~~a~~|—<br>~~a~~<br>~~a~~|—<br>~~a~~<br>~~a~~|ns<br>~~a~~<br>~~a~~|
|tSTSU<br>~~a~~|CCLK setuptime<br>~~a~~|—<br>~~a~~|12<br>~~a~~|~~a~~|—<br>~~a~~|ns<br>~~a~~|
|tSTH<br>~~a~~<br>~~a~~<br>~~ee~~|CCLK hold time<br>~~a~~<br>~~a~~<br>~~ee~~|—<br>~~a~~<br>~~a~~<br>~~ee~~|12<br>~~a~~<br>~~a~~<br>~~eee~~|—<br>~~a~~<br>~~a~~<br>~~eee~~|—<br>~~a~~<br>~~a~~<br>~~ee~~|ns<br>~~a~~<br>~~a~~<br>~~ee~~|
|tSTCO<br>~~a~~<br>~~ee~~|CCLK falling edge to valid<br>output<br>~~a~~<br>~~ee~~|—<br>~~a~~<br>~~ee~~|13<br>~~a~~<br>~~eee~~|—<br>~~a~~<br>~~eee~~|—<br>~~a~~<br>~~ee~~|ns<br>~~a~~<br>~~ee~~|
|**Master SPI**<br>~~ee ee eee ee~~<br>~~a~~<br>~~-=-=~~|||||||
|fMCLK<br>~~a~~<br>~~a~~|MCLK clock frequency<br>~~a~~<br>~~a~~|Off<br>~~a~~<br>~~a~~<br>~~-=-=~~|—<br>~~a~~<br>~~a~~<br>~~-=-=~~|0<br>~~a~~<br>~~a~~<br>~~-=-=~~|—<br>~~a~~<br>~~a~~<br>~~-=-=~~|MHz<br>~~a~~<br>~~a~~<br>~~-=-=~~|
|||Low Frequency (Default)<br>~~a~~<br>~~-=-=~~<br>~~a~~|—<br>~~a~~<br>~~-=-=~~<br>~~a~~|7.5<br>~~a~~<br>~~-=-=~~<br>~~a~~|—<br>~~a~~<br>~~-=-=~~<br>~~a~~|MHz<br>~~a~~<br>~~-=-=~~<br>~~a~~|
|||Medium Frequency3<br>~~a~~<br>~~-=-=~~<br>~~a~~|—<br>~~a~~<br>~~-=-=~~<br>~~a~~|24<br>~~a~~<br>~~-=-=~~<br>~~a~~|—<br>~~a~~<br>~~-=-=~~<br>~~a~~|MHz<br>~~a~~<br>~~-=-=~~<br>~~a~~|
|||High Frequency3<br>~~a~~<br>~~-=-=~~<br>~~a~~|—<br>~~a~~<br>~~-=-=~~<br>~~a~~|40<br>~~a~~<br>~~-=-=~~<br>~~a~~|—<br>~~a~~<br>~~-=-=~~<br>~~a~~|MHz<br>~~a~~<br>~~-=-=~~<br>~~a~~|
|tMCLK<br>~~a~~|CRESET_B high to first MCLK<br>edge<br>~~a~~|iCE40LP384 - Low Frequency (Default)<br>~~a~~<br>~~-=-=~~<br>~~a~~<br>~~a~~|600<br>~~a~~<br>~~-=-=~~<br>~~a~~<br>~~a~~|—<br>~~a~~<br>~~-=-=~~<br>~~a~~<br>~~a~~|—<br>~~a~~<br>~~-=-=~~<br>~~a~~<br>~~a~~|us<br>~~a~~<br>~~-=-=~~<br>~~a~~<br>~~a~~|
|||iCE40LP384 - Medium Frequency<br>~~a~~<br>~~er~~|600<br>~~a~~<br>~~er~~|—<br>~~a~~<br>~~er~~|—<br>~~a~~<br>~~er~~|us<br>~~a~~<br>~~er~~|
|||iCE40LP384 - High Frequency<br>~~er~~<br>~~a~~|600<br>~~er~~<br>~~a~~<br>~~ee ee~~|—<br>~~er~~<br>~~a~~<br>~~ee~~|—<br>~~er~~<br>~~a~~<br>~~ee~~|us<br>~~er~~<br>~~a~~<br>~~ee~~|
|||iCE40LP640, iCE40LP/HX1K - Low<br>Frequency (Default)<br>~~ee~~|800<br>~~ee~~<br>~~ee ee~~<br>~~ee ee~~|—<br>~~ee~~<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~<br>~~ee~~|us<br>~~ee~~<br>~~ee~~<br>~~ee~~|
|||iCE40LP640, iCE40LP/HX1K - Medium<br>Frequency<br>~~ee~~|800<br>~~ee ee~~<br>~~ee~~<br>~~ee ee~~<br>~~ee ee~~|—<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|us<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|
|||iCE40LP640, iCE40LP/HX1K - High<br>Frequency<br>~~ee~~|800<br>~~ee ee~~<br>~~ee~~<br>~~ee ee~~|—<br>~~ee~~<br>~~ee~~<br>~~ee~~|—<br>~~ee~~<br>~~ee~~<br>~~ee~~|us<br>~~ee~~<br>~~ee~~<br>~~ee~~|
|||iCE40LP/HX1K -Low Frequency (Default)<br>~~ee~~<br>~~a~~|800<br>~~ee~~<br>~~ee ee~~<br>~~a~~|—<br>~~ee~~<br>~~ee~~<br>~~a~~|—<br>~~ee~~<br>~~ee~~<br>~~a~~|us<br>~~ee~~<br>~~ee~~<br>~~a~~|
|||iCE40LP/HX1K - Medium Frequency<br>~~a~~|800<br>~~a~~|—<br>~~a~~|—<br>~~a~~|us<br>~~a~~|
|||iCE40LP/HX1K - High Frequency<br>~~a~~<br>~~a~~|800<br>~~a~~<br>~~a~~|—<br>~~a~~<br>~~a~~|—<br>~~a~~<br>~~a~~|us<br>~~a~~<br>~~a~~|
|||iCE40LP/HX4K - Low Frequency (Default)<br>~~a~~<br>~~a~~|1200<br>~~a~~<br>~~a~~|—<br>~~a~~<br>~~a~~|—<br>~~a~~<br>~~a~~|us<br>~~a~~<br>~~a~~|
|||iCE40LP/HX4K - Medium Frequency<br>~~OO~~|1200<br>~~OO~~|—<br>~~OO~~|—<br>~~OO~~|us<br>~~OO~~|



© 2011-2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02029-3.9 

37 

**iCE40 LP/HX Family Data Sheet** 

|**Symbol**|**Parameter**|**Parameter**|**Min**|**Typ**|**Max**|**Unit**|
|---|---|---|---|---|---|---|
|||iCE40LP/HX4K - high frequency|1200|—|—|us|
|||iCE40LP/HX8K - Low Frequency (Default)|1200|—|—|us|
|||iCE40LP/HX8K - Medium Frequency|1200|—|—|us|
|||iCE40LP/HX8K - High Frequency|1200|—|—|us|



## **Notes:** 

1. Does not apply for NVCM. 

2. Supported only with 1.2 V VCC and at 25 °C. 

3. Extended range fMAX Write operations support up to 53 MHz only with 1.2 V VCC and at 25 °C. 

## **4.29. Switching Test Conditions** 

Figure 4.3 shows the output test load that is used for AC testing. The specific values for resistance, capacitance, voltage, and other test conditions are listed in Table 4.30. 

**==> picture [169 x 81] intentionally omitted <==**

**----- Start of picture text -----**<br>
V T<br>R1<br>DUT Test Point<br>CL<br>**----- End of picture text -----**<br>


**Figure 4.3. Output Test Load, LVCMOS Standards** 

**Table 4.30. Test Fixture Required Components, Non-Terminated Interfaces**[1] 

|**Test Condition**|**R1**|**CL**|**Timing Reference**|**VT**|
|---|---|---|---|---|
|LVCMOS settings (L ≥ H, H ≥ L)|∞|0 pF|LVCMOS 3.3 = 1.5 V|—|
||||LVCMOS 2.5 = VCCIO/2|—|
||||LVCMOS 1.8 = VCCIO/2|—|
|LVCMOS 3.3(Z ≥ H)|188|0 pF|1.5 V|VOL|
|LVCMOS 3.3(Z ≥ L)|||1.5 V|VOH|
|Other LVCMOS(Z ≥ H)|||VCCIO/2|VOL|
|Other LVCMOS(Z ≥ L)|||VCCIO/2|VOH|
|LVCMOS(H ≥ Z)|||VOH– 0.15 V|VOL|
|LVCMOS(L ≥ Z)|||VOL– 0.15 V|VOH|



**Note** : 

1. Output test conditions for all other interfaces are determined by the respective standards. 

© 2011-2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

38 

FPGA-DS-02029-3.9 

**iCE40 LP/HX Family Data Sheet** 

## **5. Pinout Information** 

## **5.1. Signal Descriptions** 

## **5.1.1. General Purpose** 

|**Signal Name**|**I/O**|**Description**|
|---|---|---|
|IO[Bank]_[Row/Column<br>Number][A/B]|I/O|[Bank] indicates the bank of the device on which the pad is located.<br>[Number] indicates I/O number on the device.|
|IO[Bank]_[Row/Column<br>Number][A/B]|I/O|[Bank] indicates the bank of the device on which the pad is located.<br>[Number] indicates I/O number on the device.<br>[A/B] indicates the differential I/O. 'A' = negative input. 'B' = positive input.|
|HCIO[Bank]_[Number]|I/O|High Current I/O. [Bank] indicates the bank of the device on which the pad<br>is located. [Number] indicates IO number.|
|NC|—|No connect|
|GND|—|GND – Ground. Dedicated pins. It is recommended that all GNDs are tied<br>together.|
|VCC|—|VCC – The power supply pins for core logic. Dedicated pins. It is<br>recommended that all VCCs are tied to the same supply.|
|VCCIO_x|—|VCCIO– The power supply pins for I/O Bank x. Dedicated pins. All VCCIOs<br>located in the same bank are tied to the same supply.|



## **5.1.2. PLL and Global Functions (Used as user-programmable I/O pins when not used for PLL or clock pins)** 

|**Signal Name**|**I/O**|**Description**|
|---|---|---|
|VCCPLLx|—|PLL VCC – Power. Dedicated pins. The PLL requires a separate power and<br>ground that is quiet and stable to reduce the output clock jitter of the PLL.|
|GNDPLLx|—|PLL GND – Ground. Dedicated pins. The sysCLOCK PLL has the DC ground<br>connection made on the FPGA, so the external PLL ground connection<br>(GNDPLL) must NOT be connected to the board’s ground.|
|GBINx|—|Global pads. Two per side.|



© 2011-2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02029-3.9 

39 

**iCE40 LP/HX Family Data Sheet** 

## **5.1.3. Programming and Configuration** 

|**Signal Name**|**I/O**|**Description**|
|---|---|---|
|CBSEL[0:1]|I/O|Dual function pins. I/O when not used as CBSEL. Optional ColdBoot<br>configuration Select input, if ColdBoot mode is enabled.|
|CRESET_B|I|Configuration Reset, active Low. Dedicated input. No internal pull-up<br>resistor. Either actively drive externally or connect a 10 kΩ pull-up resistor<br>to VCCIO_2.|
|CDONE|I/O|Configuration Done. Includes a permanent weak pull-up resistor to VCCIO_2.<br>If driving external devices with CDONE output, an external pull-up resistor<br>to VCCIO_2may be required. Refer to theiCE40 Programming and<br>Configuration (FPGA-TN-02001)for more details. Following device<br>configuration the iCE40LP640 and iCE40LP1K in the SWG16 package CDONE<br>pin can be used as a user output.|
|VCC_SPI|—|SPI interface voltage supply input. Must have a valid voltage even if<br>configuring from NVCM.|
|SPI_SCK|I/O|Input Configuration Clock for configuring an FPGA in Slave SPI mode.<br>Output Configuration Clock for configuring an FPGA configuration modes.|
|SPI_SS|I/O|SPI Slave Select. Active Low. Includes an internal weak pull-up resistor to<br>VCC_SPI during configuration. During configuration, the logic level sampled<br>on this pin determines the configuration mode used by the iCE40 LP/HX<br>device. An input when sampled at the start of configuration. An input when<br>in SPI Peripheral configuration mode (SPI_SS = Low). An output when in<br>Master SPI Flash configuration mode.|
|SPI_SI|I/O|Slave SPI serial data input and master SPI serial data output|
|SPI_SO|I/O|Slave SPI serial data output and master SPI serial data input|
|VPP_FAST|—|Optional fast NVCM programming supply. VPP_FAST, used only for fast<br>production programming, must be left floating or unconnected in<br>applications, except the CM36 and CM49 packages which MUST have the<br>VPP_FASTball connected to VCCIO_0_1ball externally.|
|VPP_2V5|—|VPP_2V5NVCM programming and operating supply|



© 2011-2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

40 

FPGA-DS-02029-3.9 

**iCE40 LP/HX Family Data Sheet** 

## **5.2. Pin Information Summary** 

|~~po~~|**iCE40LP384**<br>~~ee~~<br>~~po~~|**iCE40LP384**<br>~~ee~~<br>~~po~~|**iCE40LP384**<br>~~ee~~<br>~~po~~|**iCE40LP640**|**iCE40LP1K**|**iCE40LP1K**|**iCE40LP1K**|**iCE40LP1K**|**iCE40LP1K**|**iCE40LP1K**|**iCE40LP1K**|**iCE40LP1K**|
|---|---|---|---|---|---|---|---|---|---|---|---|---|
||**SG32**<br>~~ee~~<br>~~po~~|**CM362**<br>~~ee~~|**CM492**<br>~~ee~~|**SWG16**|**SWG16**|**CM361,**|**CM491,**|**CM81**|**CB81**|**QN84**|**CM121**|**CB121**|
|**General Purpose I/O per Bank**<br>~~po~~<br>~~|~~<br>~~po~~|||||||||||||
|Bank 0<br>~~po~~<br>~~po~~|6|4|10|3|3|4|10|17|17|17|24|24|
|Bank 1<br>~~po~~<br>~~po~~<br>~~po~~|5|7|7|0|0|7|7|15|16|17|25|21|
|Bank 2<br>~~po~~<br>~~po~~<br>~~po~~|0|4|4|1|1|4|4|11|8|11|18|19|
|Bank 3<br>~~po~~<br>~~po~~|6|6|12|2|2|6|10|16|17|18|24|24|
|Configuration<br>~~po~~<br>~~ot]~~|4<br>~~ot]~~|4<br>~~ot]~~<br>~~|~~|4<br>~~|~~|4<br>~~tT~~|4<br>~~tT~~<br>~~|~~|4<br>~~ET~~|4<br>~~ET~~|4<br>~~ET~~|4<br>~~ET~~|4<br>~~ET~~|4<br>~~ET~~|4<br>~~ET~~|
|Total General<br>Purpose Single<br>dd/<br>~~ot]~~|21<br>~~ot]~~|25<br>~~ot]~~<br>~~|~~|37<br>~~|~~|10<br>~~tT~~|10<br>~~tT~~<br>~~|~~|25<br>~~ET~~|35<br>~~ET~~|63<br>~~ET~~|62<br>~~ET~~|67<br>~~ET~~|95<br>~~ET~~|92<br>~~ET~~|
|d d /<br>**High Current Outputs per Bank**<br>~~ot]~~<br>~~|~~<br>~~|~~<br>~~tT~~<br>~~|ET~~<br>~~|~~<br>~~po~~|||||||||||||
|Bank 0<br>~~po~~<br>~~po~~|0|0|0|3|3|0|0|0|0|0|0|0|
|Bank 1<br>~~po~~<br>~~po~~<br>~~po~~|0|0|0|0|0|0|0|0|0|0|0|0|
|Bank 2<br>~~po~~<br>~~po~~<br>~~po~~|0|0|0|0|0|0|0|0|0|0|0|0|
|Bank 3<br>~~po~~<br>~~po~~<br>~~po~~|0<br>|0<br>|0<br>|0<br>|0<br>|0<br>|0<br>|0<br>|0<br>|0<br>|0<br>|0<br>|
|Total Current<br>~~po~~<br>~~po~~|0<br>|0<br>|0<br>|3<br>|3<br>|0<br>|0<br>|0<br>|0<br>|0<br>|0<br>|0<br>|
|**Differential Inputs per Bank**<br>~~po|~~<br>~~po~~|||||||||||||
|Bank 0<br>~~po~~<br>~~po~~|0|0|0|0|0|0|0|0|0|0|0|0|
|Bank 1<br>~~po~~<br>~~po~~<br>~~po~~|0|0|0|0|0|0|0|0|0|0|0|0|
|Bank 2<br>~~po~~<br>~~po~~<br>~~po~~|0|0|0|0|0|0|0|0|0|0|0|0|
|Bank 3<br>~~po~~<br>~~po~~<br>~~po~~|3<br>|3<br>|6<br>|1<br>|1<br>|3<br>|5<br>|8<br>|9<br>|7<br>|12<br>|12<br>|
|Total Differential<br>~~po~~<br>~~po~~|3<br>|3<br>|6<br>|1<br>|1<br>|3<br>|5<br>|8<br>|9<br>|7<br>|12<br>|12<br>|
|**Dedicated Inputs per Bank**<br>~~po|~~<br>~~po~~|||||||||||||
|Bank 0<br>~~po~~<br>~~po~~|0|0|0|0|0|0|0|0|0|0|0|0|
|Bank 1<br>~~po~~<br>~~po~~<br>~~po~~|0|0|0|0|0|0|0|0|0|0|0|0|
|Bank 2<br>~~po~~<br>~~po~~<br>~~pO~~|2|2|2|1|1|2|2|2|2|2|2|2|
|Bank 3<br>~~po~~<br>~~pO~~<br>~~po~~|0|0|0|0|0|0|0|0|0|0|0|0|
|Configuration<br>~~pO~~<br>~~po~~<br>~~po~~|0<br>|0<br>|0<br>|0<br>|0<br>|0<br>|0<br>|0<br>|0<br>|0<br>|0<br>|0<br>|
|Total Dedicated<br>~~po~~<br>~~po~~|2<br>|2<br>|2<br>|1<br>|1<br>|2<br>|2<br>|2<br>|2<br>|2<br>|2<br>|2<br>|
|**Vccio Pins**<br>~~po|~~<br>~~po~~|||||||||||||
|Bank 0<br>~~po~~<br>~~po~~|1|1|1|1|1|1|1|1|1|1|2|1|
|Bank 1<br>~~po~~<br>~~po~~<br>~~po~~|1|1|1|0|0|0|0|1|1|1|2|1|
|Bank 2<br>~~po~~<br>~~po~~<br>~~po~~|1|1|1|1|1|1|1|1|1|1|2|1|
|Bank 3<br>~~po~~<br>~~po~~<br>~~po~~|1|0|0|0|0|0|0|1|1|1|2|2|
|VCC<br>~~po~~<br>~~po~~<br>~~po~~|1|1|2|1|1|1|2|3|3|4|4|4|
|VCC_SPI<br>~~po~~<br>~~po~~<br>~~po~~|1|1|1|0|0|1|1|1|1|1|1|1|
|VPP_2V5<br>~~po~~<br>~~po~~<br>~~po~~|1|1|1|0|0|1|1|1|1|1|1|1|
|VPP_FAST3<br>~~po~~<br>~~po~~<br>~~po~~|0|0|0|0|0|1|1|1|0|1|1|1|
|VCCPLL<br>~~po~~<br>~~po~~<br>~~po~~|0|0|0|0|0|0|1|1|0|0|1|1|
|GND<br>~~po~~<br>~~po~~<br>~~po~~|2|3|3|2|2|3|4|5|8|4|8|11|
|NC<br>~~po~~<br>~~po~~|0|0|0|0|0|0|0|0|0|0|0|3|
|Total Count of<br>Bonded Pins<br>~~po~~|32|36|49|16|16|36|49|81|81|84|121|121|



**Notes** : 

1. VCCIO0 and VCCIO1 are connected together. 

2. VCCIO2 and VCCIO3 are connected together. 

3. VPP_FAST, used only for fast production programming, must be left floating or unconnected in applications, except the CM36 and CM49 packages which MUST have the VPP_FAST ball connected to VCCIO_0_1 ball externally. 

© 2011-2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02029-3.9 

41 

**iCE40 LP/HX Family Data Sheet** 

||**iCE40LP4K**<br>~~CO~~|**iCE40LP4K**<br>~~CO~~|**iCE40LP4K**<br>~~CO~~|**iCE40LP8K**<br>~~CO~~|**iCE40LP8K**<br>~~CO~~|**iCE40LP8K**<br>~~CO~~|**iCE40HX1K**<br>~~CO~~|**iCE40HX1K**<br>~~CO~~|**iCE40HX1K**<br>~~CO~~|
|---|---|---|---|---|---|---|---|---|---|
||**CM81**<br>~~a~~|**CM121**|**CM225**|**CM81**|**CM121**|**CM225**|**VQ100**|**CB132**|**TQ144**|
|**General Purpose I/O per Bank**<br>~~TTT~~||||||||||
|Bank 0<br>~~SS~~<br>~~SO~~|17<br>~~SS~~<br>~~SO~~|23<br>~~OO~~<br>|46<br>~~OO~~<br>|17<br>~~OO~~<br>|23<br>~~SO~~<br>~~S~~~~**O**~~<br>|46<br>~~SO~~<br>~~**O**~~|19|24|23|
|Bank 1<br>~~CO~~<br>~~SO~~|15<br>~~CO~~<br>~~SO~~|21<br>~~CO~~<br>|42<br>~~CO~~<br>|15<br>~~CO~~<br>|21<br>~~CO~~<br>~~S~~~~**O**~~<br>|42<br>~~CO~~<br>~~**O**~~|19<br>~~CO~~|25<br>~~CO~~|25<br>~~CO~~|
|Bank 2<br>~~SO~~|9<br>~~SO ~~|19<br> ~~O~~|40<br>~~O~~|9<br>~~O~~|19<br>~~S~~~~**O**~~<br>~~O~~|40<br>~~**O**~~|12|20|20|
|Bank 3<br>~~SO~~|18<br>~~SO ~~|26<br> ~~OO~~|46<br>~~OO~~|18<br>~~OO~~|26<br>~~OO~~|46<br>~~OO~~|18<br>~~OO~~|22<br>~~OO~~|24<br>~~OO~~|
|Configuration<br>~~a~~|4<br>~~ee~~|4<br>~~ee~~|4<br>~~ee~~|4<br>~~ee~~|4<br>~~ee~~|4|4|4|4|
|Total General<br>Purpose<br>~~a~~|63<br>~~ee~~|93<br>~~ee~~|178<br>~~ee~~|63<br>~~ee~~|93<br>~~ee~~|178|72|95|96|
|**High Current Outputs per Bank**<br>~~a~~<br>~~ee ee~~<br>~~ee~~<br>~~TTT~~<br>~~S~~~~**O**~~<br>~~SO~~||||||||||
|Bank 0<br>~~GO~~<br>~~SO~~|0<br>~~GO~~<br>~~SO~~|0<br>~~GO~~<br>|0<br>~~GO~~<br>|0<br>~~GO~~<br>|0<br>~~GO~~<br>~~S~~~~**O**~~<br>|0<br>~~GO~~<br>~~**O**~~|0<br>~~GO~~|0<br>~~GO~~|0<br>~~GO~~|
|Bank 1<br>~~SO~~|0<br>~~SO ~~|0<br> ~~O~~|0<br>~~O~~|0<br>~~O~~|0<br>~~S~~~~**O**~~<br>~~O~~|0<br>~~**O**~~|0|0|0|
|Bank 2<br>~~SO~~|0<br>~~SO ~~|0<br> ~~OO~~|0<br>~~OO~~|0<br>~~OO~~|0<br>~~OO~~|0<br>~~OO~~|0<br>~~OO~~|0<br>~~OO~~|0<br>~~OO~~|
|Bank 3<br>~~SO~~|0<br>~~SO ~~|0<br> ~~OO~~|0<br>~~OO~~|0<br>~~OO~~|0<br>~~OO~~|0<br>~~OO~~|0<br>~~OO~~|0<br>~~OO~~|0<br>~~OO~~|
|Total Differential<br>~~a~~|0<br>~~a~~|0<br>~~A~~|0|0|0<br>~~O~~|0<br>~~O~~|0|0|0|
|**Differential Inputs per Bank**<br>~~TTT~~<br>~~S~~~~**O**~~<br>~~SO~~||||||||||
|Bank 0<br>~~GO~~<br>~~SO~~|0<br>~~GO~~<br>~~SO~~|0<br>~~GO~~<br>|0<br>~~GO~~<br>|0<br>~~GO~~<br>|0<br>~~GO~~<br>~~S~~~~**O**~~<br>|0<br>~~GO~~<br>~~**O**~~|0<br>~~GO~~|0<br>~~GO~~|0<br>~~GO~~|
|Bank 1<br>~~SO~~|0<br>~~SO ~~|0<br> ~~O~~|0<br>~~O~~|0<br>~~O~~|0<br>~~S~~~~**O**~~<br>~~O~~|0<br>~~**O**~~|0|0|0|
|Bank 2<br>~~SO~~|0<br>~~SO ~~|0<br> ~~OO~~|0<br>~~OO~~|0<br>~~OO~~|0<br>~~OO~~|0<br>~~OO~~|0<br>~~OO~~|0<br>~~OO~~|0<br>~~OO~~|
|Bank 3<br>~~SO~~|9<br>~~SO ~~|13<br> ~~OO~~|23<br>~~OO~~|9<br>~~OO~~|13<br>~~OO~~|23<br>~~OO~~|9<br>~~OO~~|11<br>~~OO~~|12<br>~~OO~~|
|Total Differential<br>~~a~~|9<br>~~a~~|13<br>~~A~~|23|9|13<br>~~O~~|23<br>~~O~~|9|11|12|
|**Dedicated Inputs per Bank**<br>~~TTT~~<br>~~S~~~~**O**~~<br>~~SO~~||||||||||
|Bank 0<br>~~GO~~<br>~~SO~~|0<br>~~GO~~<br>~~SO~~|0<br>~~GO~~<br>|0<br>~~GO~~<br>|0<br>~~GO~~<br>|0<br>~~GO~~<br>~~S~~~~**O**~~<br>|0<br>~~GO~~<br>~~**O**~~|0<br>~~GO~~|0<br>~~GO~~|0<br>~~GO~~|
|Bank 1<br>~~SO~~|0<br>~~SO ~~|0<br> ~~O~~|1<br>~~O~~|0<br>~~O~~|0<br>~~S~~~~**O**~~<br>~~O~~|1<br>~~**O**~~|0|0|0|
|Bank 2<br>~~SO~~|2<br>~~SO ~~|2<br> ~~OO~~|2<br>~~OO~~|2<br>~~OO~~|2<br>~~OO~~|2<br>~~OO~~|2<br>~~OO~~|2<br>~~OO~~|2<br>~~OO~~|
|Bank 3<br>~~SO~~|0<br>~~SO ~~|0<br> ~~OO~~|0<br>~~OO~~|0<br>~~OO~~|0<br>~~OO~~|0<br>~~OO~~|0<br>~~OO~~|0<br>~~OO~~|0<br>~~OO~~|
|Configuration<br>~~yO~~<br>~~a~~|0<br>~~yO ~~<br>~~a~~|0<br> ~~OO~~<br>~~A~~|0<br>~~OO~~<br>|0<br>~~OO~~<br>|0<br>~~SO~~<br>|0<br>~~SO~~<br>|0<br>|0<br>|0<br>|
|Total Dedicated<br>~~a~~|2<br>~~a~~|2<br>~~AOO~~|3<br>~~OO~~|2<br>~~OO~~|2<br>~~OO~~|3<br>~~OO~~|2<br>~~OO~~|2<br>~~OO~~|2<br>~~OO~~|
|**Vccio Pins**<br>~~a A~~<br>~~TT~~||||||||||
|Bank 0<br>~~SO~~<br>~~a~~|1<br>~~SO~~<br>~~CG~~|1<br>~~CG~~|3<br>~~OO~~<br>|1<br>~~OO~~<br>|1<br>~~OO~~<br>|3<br>~~OO~~<br>|2<br>|2<br>|2<br>|
|Bank 1<br>~~a~~<br>~~a~~|1<br>~~CG~~<br>~~CG~~|1<br>~~CGOO~~<br>~~CG~~|3<br>~~OO~~<br>|1<br>~~OO~~<br>|1<br>~~OO~~<br>|3<br>~~OO~~<br>|2<br>~~OO~~<br>|2<br>~~OO~~<br>|2<br>~~OO~~<br>|
|Bank 2<br>~~a~~<br>~~a~~<br>~~a~~|1<br>~~CG~~<br>~~CG~~<br>~~CG~~|1<br>~~CG~~<br>~~CGOO~~<br>~~CG~~|3<br><br>~~OO~~<br>|1<br><br>~~OO~~<br>|1<br><br>~~OO~~<br>|3<br><br>~~OO~~<br>|2<br><br>~~OO~~<br>|2<br><br>~~OO~~<br>|2<br><br>~~OO~~<br>|
|Bank 3<br>~~a~~<br>~~a~~<br>~~a~~|1<br>~~CG~~<br>~~CG~~<br>~~CG~~|2<br>~~CG~~<br>~~CGOO~~<br>~~CG~~|4<br><br>~~OO~~<br>|1<br><br>~~OO~~<br>|2<br><br>~~OO~~<br>|4<br><br>~~OO~~<br>|3<br><br>~~OO~~<br>|3<br><br>~~OO~~<br>|2<br><br>~~OO~~<br>|
|VCC<br>~~a~~<br>~~a~~<br>~~a~~|3<br>~~CG~~<br>~~CG~~<br>~~CG~~|4<br>~~CG~~<br>~~CGOO~~<br>~~CG~~|8<br><br>~~OO~~<br>|3<br><br>~~OO~~<br>|4<br><br>~~OO~~<br>|8<br><br>~~OO~~<br>|4<br><br>~~OO~~<br>|5<br><br>~~OO~~<br>|4<br><br>~~OO~~<br>|
|VCC_SPI<br>~~a~~<br>~~a~~<br>~~a~~|1<br>~~CG~~<br>~~CG~~<br>~~CG~~|1<br>~~CG~~<br>~~CGOO~~<br>~~CG~~|1<br><br>~~OO~~<br>|1<br><br>~~OO~~<br>|1<br><br>~~OO~~<br>|1<br><br>~~OO~~<br>|1<br><br>~~OO~~<br>|1<br><br>~~OO~~<br>|1<br><br>~~OO~~<br>|
|VPP_2V5<br>~~a~~<br>~~a~~<br>~~a~~|1<br>~~CG~~<br>~~CG~~<br>~~CG~~|1<br>~~CG~~<br>~~CGOO~~<br>~~CG~~|1<br><br>~~OO~~<br>|1<br><br>~~OO~~<br>|1<br><br>~~OO~~<br>|1<br><br>~~OO~~<br>|1<br><br>~~OO~~<br>|1<br><br>~~OO~~<br>|1<br><br>~~OO~~<br>|
|VPP_FAST1<br>~~a~~<br>~~a~~<br>~~a~~|1<br>~~CG~~<br>~~CG~~<br>~~CG~~|1<br>~~CG~~<br>~~CGOO~~<br>~~CG~~|1<br><br>~~OO~~<br>|1<br><br>~~OO~~<br>|1<br><br>~~OO~~<br>|1<br><br>~~OO~~<br>|1<br><br>~~OO~~<br>|1<br><br>~~OO~~<br>|1<br><br>~~OO~~<br>|
|VCCPLL<br>~~a~~<br>~~a~~<br>~~a~~|1<br>~~CG~~<br>~~CG~~<br>~~CG~~|2<br>~~CG~~<br>~~CGOO~~<br>~~CG~~|2<br><br>~~OO~~<br>|1<br><br>~~OO~~<br>|2<br><br>~~OO~~<br>|2<br><br>~~OO~~<br>|0<br><br>~~OO~~<br>|1<br><br>~~OO~~<br>|1<br><br>~~OO~~<br>|
|GND<br>~~a~~<br>~~a~~<br>~~a~~|5<br>~~CG~~<br>~~CG~~<br>~~CG~~|12<br>~~CG~~<br>~~CGOO~~<br>~~CG~~|18<br><br>~~OO~~<br>|5<br><br>~~OO~~<br>|12<br><br>~~OO~~<br>|18<br><br>~~OO~~<br>|10<br><br>~~OO~~<br>|14<br><br>~~OO~~<br>|10<br><br>~~OO~~<br>|
|NC<br>~~a~~<br>~~a~~|0<br>~~CG~~<br>~~CG~~|0<br>~~CG~~<br>~~CGOO~~|0<br><br>~~OO~~|0<br><br>~~OO~~|0<br><br>~~OO~~|0<br><br>~~OO~~|0<br><br>~~OO~~|2<br><br>~~OO~~|19<br><br>~~OO~~|
|Total Count of<br>Bonded Pins<br>~~a~~|81<br>~~CG~~|121<br>~~CG~~|225<br>|81<br>|121<br>|225<br>|100<br>|132<br>|144<br>|



**Note** : 

1. VPP_FAST, used only for fast production programming, must be left floating or unconnected in applications 

© 2011-2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

42 

FPGA-DS-02029-3.9 

**iCE40 LP/HX Family Data Sheet** 

||**iCE40HX4K**<br>~~a~~|**iCE40HX4K**<br>~~a~~|**iCE40HX4K**<br>~~a~~|**iCE40HX8K**|**iCE40HX8K**|**iCE40HX8K**|**iCE40HX8K**|
|---|---|---|---|---|---|---|---|
||**BG121**<br>~~a~~|**CB132**<br>~~a~~|**TQ144**|**BG121**|**CB132**|**CM225**|**CT256**|
|**General Purpose I/O per Bank**<br>~~TT~~||||||||
|Bank 0<br>~~a~~|23<br>~~OO~~|24<br>~~OO~~|27<br>~~OO~~|23<br>~~OO~~|24<br>~~OO~~|46<br>~~OO~~|52<br>~~OO~~|
|Bank 1<br>~~a~~|21<br>~~OG~~|25<br>~~OG~~|29<br>~~OG~~|21<br>~~OG~~|25<br>~~OG~~|42<br>~~OG~~|52<br>~~OG~~|
|Bank 2<br>~~a~~|19<br>~~OO~~|18<br>~~OO~~|19<br>~~OO~~|19<br>~~OO~~|18<br>~~OO~~|40<br>~~OO~~|46<br>~~OO~~|
|Bank 3<br>~~a~~|26<br>~~OO~~|24<br>~~OO~~|28<br>~~OO~~|26<br>~~OO~~|24<br>~~OO~~|46<br>~~OO~~|52<br>~~OO~~|
|Configuration|4<br>~~ee~~|4<br>~~ee~~|4<br>~~ee~~|4<br>~~ee~~|4|4|4|
|Total General Purpose Single<br>Ended I/O<br>~~ee~~|93<br>~~ee~~<br>~~ee~~|95<br>~~ee~~<br>~~ee~~|107<br>~~ee~~<br>~~ee~~|93<br>~~ee~~<br>~~ee~~|95<br>~~ee~~|178<br>~~ee~~|206<br>~~ee~~|
|**High Current Outputs per Bank**<br>~~ee ee~~<br>~~TT~~||||||||
|Bank 0<br>~~a~~|0|0|0|0|0|0|0|
|Bank 1<br>~~a~~|0<br>~~OO~~|0<br>~~OO~~|0<br>~~OO~~|0<br>~~OO~~|0<br>~~OO~~|0<br>~~OO~~|0<br>~~OO~~|
|Bank 2<br>~~a~~|0<br>~~OO~~|0<br>~~OO~~|0<br>~~OO~~|0<br>~~OO~~|0<br>~~OO~~|0<br>~~OO~~|0<br>~~OO~~|
|Bank 3<br>~~a~~|0<br>~~OO~~|0<br>~~OO~~|0<br>~~OO~~|0<br>~~OO~~|0<br>~~OO~~|0<br>~~OO~~|0<br>~~OO~~|
|Total Differential Inputs<br>~~a~~|0|0|0|0|0|0|0|
|**Differential Inputs per Bank**<br>~~TT~~||||||||
|Bank 0<br>~~a~~|0|0|0|0|0|0|0|
|Bank 1<br>~~a~~|0<br>~~OO~~|0<br>~~OO~~|0<br>~~OO~~|0<br>~~OO~~|0<br>~~OO~~|0<br>~~OO~~|0<br>~~OO~~|
|Bank 2<br>~~a~~|0<br>~~OO~~|0<br>~~OO~~|0<br>~~OO~~|0<br>~~OO~~|0<br>~~OO~~|0<br>~~OO~~|0<br>~~OO~~|
|Bank 3<br>~~a~~|13<br>~~OO~~|12<br>~~OO~~|14<br>~~OO~~|13<br>~~OO~~|12<br>~~OO~~|23<br>~~OO~~|26<br>~~OO~~|
|Total Differential Inputs<br>~~a~~|13|12|14|13|12|23|26|
|**Dedicated Inputs per Bank**<br>~~TT~~||||||||
|Bank 0<br>~~a~~|0|0|0|0|0|0|0|
|Bank 1<br>~~a~~|0<br>~~OO~~|0<br>~~OO~~|0<br>~~OO~~|0<br>~~OO~~|0<br>~~OO~~|0<br>~~OO~~|0<br>~~OO~~|
|Bank 2<br>~~a~~|2<br>~~OO~~|2<br>~~OO~~|2<br>~~OO~~|2<br>~~OO~~|2<br>~~OO~~|2<br>~~OO~~|2<br>~~OO~~|
|Bank 3<br>~~a~~|0<br>~~OO~~|0<br>~~OO~~|0<br>~~OO~~|0<br>~~OO~~|0<br>~~OO~~|0<br>~~OO~~|0<br>~~OO~~|
|Configuration<br>~~a~~|0|0|0|0|0|0|0|
|Total Dedicated Inputs<br>~~a~~|2|2|2|2|2|2|2|
|**Vccio Pins**<br>~~TT~~||||||||
|Bank 0<br>~~a~~|1<br>~~OO~~|2<br>~~OO~~|2<br>~~OO~~|1<br>~~OO~~|2<br>~~OO~~|3<br>~~OO~~|4<br>~~OO~~|
|Bank 1<br>~~a~~|1<br>~~OO~~|2<br>~~OO~~|2|1|2|3|4|
|Bank 2<br>~~a~~|1<br>~~OO~~|2<br>~~OO~~|2|1|2|3|4|
|Bank 3<br>~~a~~|2<br>~~OO~~|3<br>~~OO~~|2|2|3|4|4|
|VCC<br>~~a~~|4<br>~~OO~~|5<br>~~OO~~|4|4|5|8|6|
|VCC_SPI<br>~~a~~|1<br>~~OO~~|1<br>~~OO~~|1|1|1|1|1|
|VPP_2V5<br>~~a~~|1<br>~~OO~~|1<br>~~OO~~|1|1|1|1|1|
|VPP_FAST1<br>~~a~~|1<br>~~OO~~|1<br>~~OO~~|1|1|1|1|1|
|VCCPLL<br>~~a~~|2<br>~~OO~~|2<br>~~OO~~|2|2|2|2|2|
|GND<br>~~a~~|12<br>~~OO~~|15<br>~~OO~~|11|12|15|18|20|
|NC<br>~~a~~|0<br>~~OO~~|0<br>~~OO~~|6|0|0|0|0|
|Total Count of Bonded Pins<br>~~a~~|121<br>~~A~~|132|144|121|132|225|256|



1. VPP_FAST, used only for fast production programming, must be left floating or unconnected in applications. 

© 2011-2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02029-3.9 

43 

**iCE40 LP/HX Family Data Sheet** 

## **5.3. iCE40 LP/HX Part Number Description** 

## **5.3.1. Ultra Low Power (LP) Devices** 

– ICE40LPXXX XXXXXXX **Device Family** iCE40 FPGA **Series** — ~~]~~ LP = Low Power Series 

## **Logic Cells** 

384 = 384 Logic Cells 640 = 640 Logic Cells 1K = 1,280 Logic Cells 4K = 3,520 Logic Cells 8K = 7,680 Logic Cells 

## **Shipping Method** 

TR = Tape and Reel TR50 = Tape and Reel 50 units TR1K = Tape and Reel 1,000 units 

## **Package** 

SWG16 = 16-Ball WLCSP (0.35 mm Pitch) CM36  = 36-Ball ucBGA (0.4 mm Pitch) CM49 = 49-Ball ucBGA (0.4 mm Pitch) CM81 = 81-Ball ucBGA (0.4 mm Pitch) CB81 = 81-Ball csBGA (0.5 mm Pitch) CM121 = 121-Ball ucBGA (0.4 mm Pitch) CB121 = 121-Ball csBGA (0.5 mm Pitch) CM225 = 225-Ball ucBGA (0.4 mm Pitch) SG32 = 32-Pin QFN (0.5 mm Pitch) QN84 = 84-Pin QFN (0.5 mm Pitch) 

**Figure 5.1. Low Power (LP) Devices** 

## **5.3.2. High Performance (HX) Devices** 

ICE40HXXX – XXXXXXX **Device Family Shipping Method** iCE40 Mobile FPGA TR = Tape and Reel **Series** HX = High Performance Series ~~ee~~ **Package Logic Cells** CB132 = 132-Ball csBGA (0.5 mm Pitch) 1K = 1,280 Logic Cells CM225 = 225-Ball ucBGA (0.4 mm Pitch) 4K = 3,520 Logic Cells CT256 = 256-Ball caBGA (0.8 mm Pitch) 8K = 7,680 Logic Cells TQ144 = 144-Pin TQFP (0.5 mm Pitch) VQ100 = 100-Pin VQFP (0.5 mm Pitch) BG121 = 121-Ball caBGA (0.8 mm Pitch) 

**Figure 5.2. High Performance (HX) Devices** 

**Note** : All parts shipped in trays unless noted. 

© 2011-2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02029-3.9 

44 

**iCE40 LP/HX Family Data Sheet** 

## **5.4. Ordering Information** 

iCE40 LP/HX devices have top-side markings as shown below: 

## Industrial 

**==> picture [46 x 33] intentionally omitted <==**

**----- Start of picture text -----**<br>
iCE40HX8K<br>CM225<br>Datecode<br>**----- End of picture text -----**<br>


**Figure 5.3. High Performance (HX) Devices** 

**Note** : Markings are abbreviated for small packages. 

## **5.5. Ordering Part Numbers** 

## **5.5.1. Ultra Low Power Industrial Grade Devices, Halogen Free (RoHS) Packaging** 

|**Part Number**|**LUTs**|**Supply Voltage**|**Package**|**Leads**|**Temperature**|
|---|---|---|---|---|---|
|ICE40LP384-CM36|384|1.2 V|Halogen-Free ucBGA|36|IND|
|ICE40LP384-CM36TR|384|1.2 V|Halogen-Free ucBGA|36|IND|
|ICE40LP384-CM36TR1K|384|1.2 V|Halogen-Free ucBGA|36|IND|
|ICE40LP384-CM49|384|1.2 V|Halogen-Free ucBGA|49|IND|
|ICE40LP384-CM49TR|384|1.2 V|Halogen-Free ucBGA|49|IND|
|ICE40LP384-CM49TR1K|384|1.2 V|Halogen-Free ucBGA|49|IND|
|ICE40LP384-SG32|384|1.2 V|Halogen-Free QFN|32|IND|
|ICE40LP384-SG32TR|384|1.2 V|Halogen-Free QFN|32|IND|
|ICE40LP384-SG32TR1K|384|1.2 V|Halogen-Free QFN|32|IND|
|ICE40LP640-SWG16TR|640|1.2 V|Halogen-Free WLCSP|16|IND|
|ICE40LP640-SWG16TR1K|640|1.2 V|Halogen-Free WLCSP|16|IND|
|ICE40LP640-CM36A|640|1.2 V|Halogen-Free ucBGA|36|IND|
|ICE40LP1K-SWG16TR|1280|1.2 V|Halogen-Free WLCSP|16|IND|
|ICE40LP1K-SWG16TR1K|1280|1.2 V|Halogen-Free WLCSP|16|IND|
|ICE40LP1K-CM36|1280|1.2 V|Halogen-Free ucBGA|36|IND|
|ICE40LP1K-CM36A|1280|1.2 V|Halogen-Free ucBGA|36|IND|
|ICE40LP1K-CM36TR|1280|1.2 V|Halogen-Free ucBGA|36|IND|
|ICE40LP1K-CM36TR1K|1280|1.2 V|Halogen-Free ucBGA|36|IND|
|ICE40LP1K-CM49|1280|1.2 V|Halogen-Free ucBGA|49|IND|
|ICE40LP1K-CM49TR|1280|1.2 V|Halogen-Free ucBGA|49|IND|
|ICE40LP1K-CM49TR1K|1280|1.2 V|Halogen-Free ucBGA|49|IND|
|ICE40LP1K-CM81|1280|1.2 V|Halogen-Free ucBGA|81|IND|
|ICE40LP1K-CM81TR|1280|1.2 V|Halogen-Free ucBGA|81|IND|
|ICE40LP1K-CM81TR1K|1280|1.2 V|Halogen-Free ucBGA|81|IND|
|ICE40LP1K-CB81|1280|1.2 V|Halogen-Free csBGA|81|IND|
|ICE40LP1K-CM121|1280|1.2 V|Halogen-Free ucBGA|121|IND|
|ICE40LP1K-CM121TR|1280|1.2 V|Halogen-Free ucBGA|121|IND|
|ICE40LP1K-CM121TR1K|1280|1.2 V|Halogen-Free ucBGA|121|IND|



© 2011-2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02029-3.9 

45 

**iCE40 LP/HX Family Data Sheet** 

|**Part Number**<br>**LUTs**<br>**Supply Voltage**<br>**Package**<br>**Leads**<br>**Temperature**<br>ICE40LP1K-CB121<br>1280<br>1.2 V<br>Halogen-Free csBGA<br>121<br>IND<br>ICE40LP1K-QN84<br>1280<br>1.2 V<br>Halogen-Free QFN<br>84<br>IND<br>ICE40LP4K-CM81<br>3520<br>1.2 V<br>Halogen-Free ucBGA<br>81<br>IND<br>ICE40LP4K-CM81TR<br>3520<br>1.2 V<br>Halogen-Free ucBGA<br>81<br>IND<br>ICE40LP4K-CM81TR1K<br>3520<br>1.2 V<br>Halogen-Free ucBGA<br>81<br>IND<br>~~eses~~<br>~~es GG~~<br>~~es sf~~<br>~~es~~<br>~~es sf~~<br>~~ss~~|
|---|
|ICE40LP4K-CM121<br>3520<br>1.2 V<br>Halogen-Free ucBGA<br>121<br>IND<br>ICE40LP4K-CM121TR<br>3520<br>1.2 V<br>Halogen-Free ucBGA<br>121<br>IND<br>ICE40LP4K-CM121TR1K<br>3520<br>1.2 V<br>Halogen-Free ucBGA<br>121<br>IND<br>~~es~~<br>~~es sf~~<br>~~ss~~|
|ICE40LP4K-CM225<br>3520<br>1.2 V<br>Halogen-Free ucBGA<br>225<br>IND<br>ICE40LP8K-CM81<br>7680<br>1.2 V<br>Halogen-Free ucBGA<br>81<br>IND<br>ICE40LP8K-CM81TR<br>7680<br>1.2 V<br>Halogen-Free ucBGA<br>81<br>IND<br>~~es~~<br>~~es sf~~<br>~~ss~~|
|ICE40LP8K-CM81TR1K<br>7680<br>1.2 V<br>Halogen-Free ucBGA<br>81<br>IND<br>ICE40LP8K-CM121<br>7680<br>1.2 V<br>Halogen-Free ucBGA<br>121<br>IND<br>ICE40LP8K-CM121TR<br>7680<br>1.2 V<br>Halogen-Free ucBGA<br>121<br>IND<br>~~es~~<br>~~es sf~~<br>~~ss~~|
|ICE40LP8K-CM121TR1K<br>7680<br>1.2 V<br>Halogen-Free ucBGA<br>121<br>IND<br>ICE40LP8K-CM225<br>7680<br>1.2 V<br>Halogen-Free ucBGA<br>225<br>IND<br>~~es~~<br>~~es~~<br>~~Qe~~|
|**5.5.2. High-Performance Industrial Grade Devices, Halogen Free(RoHS) Packaging**|
|**Part Number**<br>**LUTs**<br>**Supply Voltage**<br>**Package**<br>**Leads**<br>**Temperature**<br>ICE40HX1K-CB132<br>1280<br>1.2 V<br>Halogen-Free csBGA<br>132<br>IND<br>ICE40HX1K-VQ100<br>1280<br>1.2 V<br>Halogen-Free VQFP<br>100<br>IND<br>ICE40HX1K-TQ144<br>1280<br>1.2 V<br>Halogen-Free TQFP<br>144<br>IND<br>ICE40HX4K-BG121<br>3520<br>1.2 V<br>Halogen-Free caBGA<br>121<br>IND<br>ICE40HX4K-BG121TR<br>3520<br>1.2 V<br>Halogen-Free caBGA<br>121<br>IND<br>ICE40HX4K-CB132<br>3520<br>1.2 V<br>Halogen-Free csBGA<br>132<br>IND<br>ICE40HX4K-TQ144<br>3520<br>1.2 V<br>Halogen-Free TQFP<br>144<br>IND<br>ICE40HX8K-BG121<br>7680<br>1.2 V<br>Halogen-Free caBGA<br>121<br>IND<br>ICE40HX8K-BG121TR<br>7680<br>1.2 V<br>Halogen-Free caBGA<br>121<br>IND<br>ICE40HX8K-CB132<br>7680<br>1.2 V<br>Halogen-Free csBGA<br>132<br>IND<br>ICE40HX8K-CM225<br>7680<br>1.2 V<br>Halogen-Free ucBGA<br>225<br>IND<br>ICE40HX8K-CT256<br>7680<br>1.2 V<br>Halogen-Free caBGA<br>256<br>IND<br>~~es~~<br>~~es~~<br>~~eG~~<br>~~es se~~<br>~~a~~<br>~~a~~<br>~~es sf~~<br>~~ss~~<br>~~es sf~~<br>~~es se~~<br>~~es~~<br>~~es sf~~<br>~~es se~~<br>~~es~~<br>~~esse~~|



© 2011-2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02029-3.9 

46 

**iCE40 LP/HX Family Data Sheet** 

## **Supplemental Information** 

## **For Further Information** 

A variety of technical documents for the iCE40 LP/HX family are available on the Lattice web site. 

- iCE40 Programming and Configuration (FPGA-TN-02001) 

- Memory Usage Guide for iCE40 Devices (FPGA-TN-02002) 

- iCE40 sysCLOCK PLL Design and Usage Guide (FPGA-TN-02009) 

- iCE40 Hardware Checklist (FPGA-TN-02006) 

- Using Differential I/O LVDS Sub-LVDS in iCE40 Devices (FPGA-TN-02213) 

- PCB Layout Recommendations for BGA Packages (FPGA-TN-02010) 

- iCE40 LED Driver Usage Guide (FPGA-TN-02021) 

- iCE40 Pinout Files 

- Thermal Management 

- Lattice design tools 

- IBIS 

- Package Diagrams 

- Schematic Symbols 

© 2011-2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02029-3.9 

47 

**iCE40 LP/HX Family Data Sheet** 

## **Technical Support** 

For assistance, submit a technical support case at www.latticesemi.com/techsupport. 

© 2011-2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

48 

FPGA-DS-02029-3.9 

**iCE40 LP/HX Family Data Sheet** 

## **Revision History** 

**Revision 3.9, July 2022** 

**Section Change Summary** Pinout Information Updated ordering part numbers list for Ultra Low Power Industrial Grade Devices, Halogen Free (RoHS) Packaging: • Added part numbers ICE40LP640-CM36A and ICE40LP1K-CM36A • Deleted part numbers ICE40LP640-SWG16TR50, ICE40LP1K-SWG16TR50, ICE40LP1K- ~~pp~~ CB81TR, and ICE40LP1K-CB81TR1K **Revision 3.8, April 2022 Section Change Summary** DC and Switching Characteristics • Updated the definition of VPP_FAST. • Updated footnote 4 in Table 4.2. Recommended Operating Conditions. • Updated footnote 8 in Table 4.8. Programming NVCM Supply Current – LP Devices. • Updated footnote 3 in Table 4.10. Peak Startup Supply Current – LP Devices. ~~|~~ Pinout Information Updated footnote 3 in section Pin Information Summary. **Revision 3.7, October 2020 Section Change Summary** DC and Switching Characteristics Updated Table 4.29. sysCONFIG Port Timing Specifications1. ~~————_—______~~ Changed duplicated tCR_SCK entry to fMAX and corrected parameter. **Revision 3.6, October 2020 Section Change Summary** Disclaimers Added this section. Product Family Updated Table 2.1. iCE40 LP/HX Family Selection Guide. Architecture Updated Figure 3.3. PLL Diagram. DC and Switching Characteristics • Added Power-up Supply Sequence section. ~~———————~~ • Updated Test Conditions values in Table 4.15. subLVDS. **Revision 3.5, September 2018 Section Change Summary** All • Changed document number from DS1040 to FPGA-DS-02029. • Updated document template. ~~pf~~ Pinout Information Changed signal name from SPI_SS_B to SPI_SS in Signal Descriptions table. **Revision 3.4, October 2017 Section Change Summary** Pin Information Modified the dedicated inputs for Bank 1 of iCE40HX1K (CB132, TQ144), iCE40HX4K (CB132, ~~—E=__~~ TQ144) and iCE40HX8K (CB132, CM225, CT256). 

© 2011-2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02029-3.9 

49 

**iCE40 LP/HX Family Data Sheet** 

## **Revision 3.3, March 2017** 

|**Section**|**Change Summary**|
|---|---|
|Introduction|Updated Features section. Added 121-ball caBGA package for ICE40 HX4K/8K to Table 2.1,<br>iCE40 LP/HX FamilySelection Guide.|
|Architecture|Updated PLB Blocks section. Changed “subtracters” to “subtractors” in the Carry Logic<br>description.|
||Updated Clock/Control Distribution Network section. Switched the Clock Enable and the<br>Reset headings in Table 3.1, Global Buffer (GBUF) Connections to Programmable Logic<br>Blocks.|
|Pinout Information|Updated Pin Information Summary section. Added BG121 information under iCE40HX4K and<br>iCE40HX8K.|
|Ordering Information|Updated iCE40 LP/HX Part Number Description section. Added Shipping Method and BG121<br>package under High Performance(HX)Devices.|
||Updated Ordering Information section. Added part numbers for BG121 under High-<br>Performance Industrial Grade Devices,Halogen Free(RoHS)Packaging.|
|Supplemental Information|Corrected reference to “Package Diagrams Data Sheet”.|



|**Revision 3.2, October 2015**|**Revision 3.2, October 2015**||
|---|---|---|
||**Section**|**Change Summary**|
||Introduction|Updated Features section. Added footnote to 16 WLCSP Programmable I/O: Max Inputs|
|||(LVDS25)in Table 2.1, iCE40 LP/HX FamilySelection Guide.|
||DC and Switching Characteristics|Updated sysCLOCK PLL Timingsection. Changed tDT conditions.|
|||Updated Programming NVCM Supply Current – LP Devices section. Changed IPP_2V5 and|
|||ICCIO,ICC_SPI units.|
|**Revision 3.1, March 2015**<br>**Section**<br>**Change Summary**<br>DC and Switching Characteristics<br>Updated sysI/O Single-Ended DC Electrical Characteristics section. Changed LVCMOS 3.3 and<br>LVCMOS 2. 5 VOH Min.(V)from 0.5 to 0.4.<br>~~————~~|||
|**Revision 3.0, July 2014**|||
||**Section**|**Change Summary**|
||DC and Switching Characteristics|Revised and/or added Typ. VCCdata in the following sections.|
|||•<br>Static Supply Current – LP Devices|
|||•<br>Static Supply Current – HX Devices|
|||•<br>Programming NVCM Supply Current – LP Devices|
|||•<br>Programming NVCM Supply Current – HX Devices|
|||In each section table, the footnote indicatingAdvanced device status was removed.|
||Pinout Information|Updated Pin Information Summarysection. Added footnote 1 to CM49 under iCE40LP1K.|



|**Section**<br>~~a~~|**Change Summary**|
|---|---|
|Ordering Information<br>~~a~~|Changed “i” to “I” inpart number description and ordering part numbers.|
||Added part numbers to the Ultra Low Power Industrial Grade Devices, Halogen Free (RoHS)<br>Packagingtable.|



© 2011-2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

50 

FPGA-DS-02029-3.9 

**iCE40 LP/HX Family Data Sheet** 

## **Revision 2.8, February 2014** 

|**Section**|**Change Summary**|
|---|---|
|DC and Switching Characteristics|Updated Features section.<br>•<br>Corrected standby power units.<br>•<br>Included High Current LED Drivers.|
||•<br>Updated Table 2.1, iCE40 LP/HX Family Selection Guide.<br>•<br>Removed LP384 Programmable I/O for 81 ucBGApackage.|
|Architecture|Updated Supported Standards section. Added information on High Current LED drivers.|
|DC and Switching Characteristics|Corrected typos.|
||Added footnote to the Peak StartupSupplyCurrent – LP Devices table.|
|Ordering Information|Updatedpart number description in the Ultra Low Power(LP)Devices section.|
||Added part numbers to the Ultra Low Power Industrial Grade Devices, Halogen Free (RoHS)<br>Packagingtable.|



## **Revision 2.7, October 2013** 

|**Section**|**Change Summary**|
|---|---|
|Introduction|Updated Features list and iCE40 LP/HX FamilySelection Guide table.|
|Architecture|Revised iCE40-1K device to iCE40LP/HX1K device.|
|DC and SwitchingCharacteristics|Added iCE40LP640 device information.|
|Pinout Information|Added iCE40LP640 and iCE40LP1K information.|
|OrderingInformation|Added iCE40LP640 and iCE40LP1K information.|



**Revision 2.6, September 2013** 

|**Section**<br>DC and Switching Characteristics<br>Pinout Information<br>**Revision 2.5, August 2013**<br>~~—~~|**Change Summary**<br>Updated Absolute Maximum Ratings section.<br>Updated sysCLOCK PLL Timing– Preliminarytable.<br>Updated Pin Information Summarytable.|
|---|---|



|**Section**|**Change Summary**|
|---|---|
|Introduction|Updated the iCE40 LP/HX FamilySelection Guide table.|
|DC and Switching Characteristics|Updated the following tables:<br>•<br>Absolute Maximum Ratings<br>•<br>Power-On-Reset Voltage Levels<br>•<br>Static Supply Current – LP Devices<br>•<br>Static Supply Current – HX Devices<br>•<br>Programming NVCM Supply Current – LP Devices<br>•<br>Programming NVCM Supply Current – HX Devices<br>•<br>Peak Startup Supply Current – LP Devices<br>•<br>sysI/O Recommended Operating Conditions<br>•<br>Typical Building Block Function Performance – HX Devices<br>•<br>External Switching Characteristics – HX Devices<br>•<br>sysCLOCK PLL Timing – Preliminary<br>•<br>SPI Master or NVCM Configuration Time|
|Pinout Information|Updated the Pin Information Summarytable.|



© 2011-2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02029-3.9 

51 

**iCE40 LP/HX Family Data Sheet** 

## **Revision 2.4, July 2013** 

|**Section**|**Change Summary**|
|---|---|
|Introduction|Updated the iCE40 LP/HX FamilySelection Guide table.|
|DC and Switching Characteristics|Updated the sysCONFIG Port TimingSpecifications table.|
||Updated footnote in DC Electrical Characteristics table.|
||GDDR tables removed. Support to beprovided in a technical note.|
|Pinout Information|Updated the Pin Information Summarytable.|
|Ordering Information|Updated the top-side markings figure.|
||Updated the Ultra Low Power Industrial Grade Devices, Halogen Free (RoHS) Packaging<br>table.|



## **Revision 2.3, May 2013** 

|**Section**|**Change Summary**|
|---|---|
|DC and SwitchingCharacteristics|Added new data from Characterization.|



## **Revision 2.2, April 2013** 

|**Section**|**Change Summary**|
|---|---|
|Introduction|Added the LP8K 81 ucBGA.|
|Architecture|Corrected typos.|
|DC and SwitchingCharacteristics|Corrected typos.|
|Pinout Information|Added 7:1 LVDS waveforms.|
|OrderingInformation|Corrected typos in signal descriptions.|



## **Revision 2.1, March 2013** 

||**Section**|**Change Summary**|
|---|---|---|
||DC and Switching Characteristics|Recommended operatingconditions added requirement for Master SPI.|
|||Updated Recommended OperatingConditions for VPP_2V5.|
|||Updated Power-On-Reset Voltage Levels and sequence requirements.|
|||Updated Static SupplyCurrent conditions.|
|||Changed unit for tSKEW_IO from ns tops.|
|||Updated range of CCLK fMAX.|
||OrderingInformation|Updated orderinginformation to include tape and reelpart numbers.|
|**Revision 2.0, September 2012**|||
|**Section**<br>All<br>~~ee~~||**Change Summary**<br>Merged SiliconBlue iCE40 LP and HX data sheets and updated to Lattice format.|
|**Revision 1.31, September 2012**|||
|**Section**<br>Introduction<br>~~ee~~||**Change Summary**<br>Updated Table 3.1.|
|**Revision 1.3, September 2012**|||
||**Section**|**Change Summary**|
||All|Production release.|
||Architecture|•<br>Updated notes on Table 3.2: Recommended Operating Conditions.|
|||•<br>Updated values in Table 3.3 and Table 3.4.|
||DC and SwitchingCharacteristics|Updated values in Table 4.2, Table 4.3 and Table 4.7.|
|**Revision 1.21, September 2012**|||
|**Section**<br>Architecture<br>~~ee~~||**Change Summary**<br>Updated Figure 3.3 and Figure 3.4 to specifyiCE40.|



© 2011-2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

52 

FPGA-DS-02029-3.9 

**iCE40 LP/HX Family Data Sheet** 

|**Revision 1.2**|**Revision 1.2**|**Revision 1.2**|**Revision 1.2, August 2012**||
|---|---|---|---|---|
|||**Section**||**Change Summary**|
|||All||Updated companyname.|
|**Revision 1.1**|||**Revision 1.1, July 2011**||
|||**Section**||**Change Summary**|
|||Product Family|Product Family|Movedpackage specifications to iCE40pinout Excel files.|
|||||Updated Table 2.1 maximum I/O.|
|**Revision 1.01**|||**Revision 1.01, July 2011**||
|||**Section**||**Change Summary**|
|||Product Famil|Product Family|Added 640, 1K and 4K to Table 4.3 configuration times. Updated Table 2.1 maximum I/O.|
|**Revision 1.0**|||**Revision 1.0, July 2011**||
|||**Section**||**Change Summary**|
|||All||Initial release.|



© 2011-2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

FPGA-DS-02029-3.9 

53 

www.latticesemi.com
Updated at April 17, 2026
Lattice Semiconductor is a premier developer of low-power, programmable design solutions, specializing in Field-Programmable Gate Arrays (FPGAs) and Programmable Logic Devices (PLDs). Recognized for driving innovation in cost-effective and power-efficient architectures, the company provides essential semiconductor components for consumer, mobile, and industrial design applications. Our selection of Lattice Semiconductor products is focused on their highly regarded FPGA integrated circuits. Devices from industry-leading families like the iCE40, MachXO, and LatticeECP series offer designers an exceptional combination of high system integration and industry-low power consumption. These FPGAs are engineered to handle complex tasks such as sensor management, custom connectivity, and advanced video processing while minimizing overall board footprint. To ensure seamless integration from concept to production, Lattice backs its hardware with a comprehensive support ecosystem. Engineers can accelerate their development cycles utilizing intuitive tools like the Lattice Diamond design software, paired with flexible IP cores and reference designs that reduce design risk and increase system reliability.
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