HV9925SG-G

**HV9925** 

## **Programmable-Current LED Lamp Driver IC with PWM Dimming** 

## **Features** 

- Programmable output current to 50mA 

- PWM dimming / enable 

- Universal 85 - 264VAC operation 

- Fixed off-time buck converter 

- Internal 475V power MOSFET 

- Over-temperature protection with hysteresis 

## **Applications** 

## **General Description** 

LED driver control IC with PWM dimming capabilities. It allows efficient operation of high brightness LED strings from voltage sources ranging up to 400VDC. The HV9925 includes an internal high-voltage switching MOSFET controlled with a fixed off-time (TOFF) of approximately 10.5µs. The LED string is driven at constant current, thus providing constant light output and enhanced reliability. Selecting a value of a current sense resistor can externally program the output LED current of the HV9925. 

- Decorative lighting 

- 

The peak current control scheme provides good regulation of the output current throughout the universal AC line voltage range of 85 to 264VAC or DC input voltage of 20 to 400V. The HV9925 is designed with a built in thermal shutdown to prevent excessive power dissipation in the IC. 

## **Typical Application Circuit** 

**==> picture [188 x 244] intentionally omitted <==**

●  1235 Bordeaux Drive, Sunnyvale, CA 94089  ●  Tel: 408-222-8888  ●  www.supertex.com 

**HV9925** 

## **Ordering Information** 

|**Device**<br>~~ee~~|**Package Option**|
|---|---|
||**8-Lead SOIC (w/Heat Slug)**<br>**_4.90x3.90mm body_**<br>**_1.70mm height (max)_**<br>**_1.27mm pitch_**|
|HV9925<br>~~ee~~|HV9925SG-G|



_-G indicates package is RoHS compliant (‘Green’)_ 

## **Absolute Maximum Ratings** 

|**Parameter**|**Value**|
|---|---|
|Supply voltage, VDD|-0.3 to +10V|
|PWMD, RSENSEvoltage|-0.3 to +10V|
|Supply current, IDD|+5mA|
|Operating ambient temperature range|-40°C to +85°C|
|Operating junction temperature range|-40°C to +125°C|
|Storage temperature range|-65°C to +150°C|
|Power dissipation @ 25°C|800mW**|



_All voltages referenced to GND pin._ 

_**The power dissipation is given for the standard minimum pad without a heat slug, and based on RθJA = 125°C/W. RθJA is the sum of the junction-to-case and case-to-ambient thermal resistance, where the latter is determined by the user’s board design. The junction-to-ambient thermal resistance is RθJA= 105°C/W when the part is mounted on a 0.04 in[2] pad of 1 oz copper, and RθJA= 60°C/W when mounted on a 1.0in[2] pad of 1 oz copper._ 

## 

**==> picture [185 x 73] intentionally omitted <==**

**----- Start of picture text -----**<br>
RSENSE 1 8 DRAIN<br>[| je, | |<br>GND 2 7 DRAIN<br>= [1]<br>PWMD | 3 | i LJ 6 DRAIN<br>VDD fn 4 eee 5 NC<br>Heat Slug<br>**----- End of picture text -----**<br>


**8-Lead SOIC (SG)** _**(top view) Heat slug is at ground potential.**_ 

## **Product Marking** 

Y = Year Sealed **YWW** WW = Week Sealed **H9925** L = Lot Number **L L L L** = “Green” Packaging 

## **8-Lead SOIC (SG)** 

## **Electrical Characteristics** _(The specifications are at TA = 25°C and VDRAIN = 50V, unless otherwise noted.)_ 

|**Sym**|**Parameter**||**Min**|**Typ**|**Max**|**Units**|**Conditions**|
|---|---|---|---|---|---|---|---|
|VDD|VDDregulator output|-|-|7.5|-|V|---|
|VUVLO|VDDundervoltage threshold|-|4.8|-|-|V|---|
|ΔVUVLO|VDDundervoltage lockout hysteresis|-|-|200|-|mV|---|
|IDD|Operating supply current|-|-|300|500|μA|VDD(EXT) = 8.5V|
|**Output(DRAIN)**||||||||
|VBR|Breakdown voltage|*|475|-|-|V|---|
|VDRAIN|VDRAINsupply voltage|-|20|-|-|V|---|
|RON|On-resistance|-|-|100|200|Ω|IDRAIN= 50mA|
|CDRAIN|Output capacitance|#|-|1.0|5.0|pF|VDRAIN= 400V|
|ISAT|DRAIN saturation current|-|100|150|-|mA|---|



## **Output (DRAIN)** 

## _**Notes:**_ 

_A < +85°C. #    Denotes guaranteed by design._ 

●  1235 Bordeaux Drive, Sunnyvale, CA 94089  ●  Tel: 408-222-8888  ●  www.supertex.com 

2 

**HV9925** 

**Electrical Characteristics** _(cont.) (The specifications are at TA = 25°C and VDRAIN = 50V, unless otherwise noted.)_ 

**==> picture [542 x 254] intentionally omitted <==**

**----- Start of picture text -----**<br>
Sym Parameter Min Typ Max Units Conditions<br>Current Sense Comparator<br>VTH Threshold voltage - 0.435 0.470 0.525 V ---<br>TBLANK Leading edge blanking delay # 200 300 400 ns ---<br>T Minimum on time - - - 650 ns ---<br>ON(MIN)<br>Off-Time Generator<br>TOFF Off time - 8.0 10.5 13 μs ---<br>PWM Dimming<br>VPWMD,HI PWMD input high voltage - 2.0 - - V ---<br>VPWMD,LO PWMD input low voltage - - - 0.8 V ---<br>RPWMD PWMD pull down resistance - 100 200 300 kΩ VPWMD = 5.0V<br>Thermal Shutdown<br>TOT Over temperature trip limit # - 140 - °C ---<br>THYST Temperature hysteresis # - 60 - °C ---<br>**----- End of picture text -----**<br>


## _**Notes:**_ 

_A < +85°C. #     Denotes guaranteed by design._ 

## **Functional Block Diagram** 

**==> picture [355 x 282] intentionally omitted <==**

●  1235 Bordeaux Drive, Sunnyvale, CA 94089  ●  Tel: 408-222-8888  ●  www.supertex.com 3 

**HV9925** 

## **Typical Performance Characteristics** _(TJ = 25[O] C unless otherwise noted)_ 

**==> picture [236 x 190] intentionally omitted <==**

**----- Start of picture text -----**<br>
Threshold Voltage VTH vs Temperature TJ<br>0.485<br>0.480<br>0.475<br>0.470<br>0.465<br>0.460<br>-40 -15 10 35 60 85 110<br>Junction Temperature, °C<br>Current Sense Threshold, V<br>**----- End of picture text -----**<br>


**==> picture [235 x 189] intentionally omitted <==**

**----- Start of picture text -----**<br>
OFF Time TOFF vs Temperature TJ<br>13.0<br>12.5<br>12.0<br>11.5<br>11.0<br>10.5<br>10.0<br>9.5<br>9.0<br>-40 -15 10 35 60 85 110<br>Junction Temperature, °C<br>OFF Time, μs<br>**----- End of picture text -----**<br>


**==> picture [233 x 406] intentionally omitted <==**

**----- Start of picture text -----**<br>
ON Resistance RON vs Temperature TJ<br>200<br>180<br>160<br>140<br>120<br>100<br>80<br>60<br>40<br>-40 -15 10 35 60 85 110<br>Junction Temperature, °C<br>Output Capacitance CDRAIN vs VDRAIN<br>1000<br>100<br>10<br>1<br>0 10 20 30 40<br>DRAIN Voltage, V<br>ON Resistance, Ohm<br>DRAIN Capacitance, pF<br>**----- End of picture text -----**<br>


DRAIN Breakdown Voltage BV vs TJ 

**==> picture [234 x 176] intentionally omitted <==**

**----- Start of picture text -----**<br>
580<br>570<br>560<br>550<br>540<br>530<br>520<br>510<br>500<br>490<br>-40 -15 10 35 60 85 110<br>Junction Temperature, °C<br>DRAIN Breakdown Voltage, V<br>**----- End of picture text -----**<br>


Output Characteristics IDRAIN vs VDRAIN 

**==> picture [223 x 177] intentionally omitted <==**

**----- Start of picture text -----**<br>
180<br>160 TJ = 25 [O] C<br>140 TJ = 125 [O] C<br>120<br>100<br>80<br>60<br>40<br>20<br>0<br>0 10 20 30 40<br>DRAIN Voltage, V<br>DRAIN Current, mA<br>**----- End of picture text -----**<br>


●  1235 Bordeaux Drive, Sunnyvale, CA 94089  ●  Tel: 408-222-8888  ●  www.supertex.com 

4 

**HV9925** 

## **Functional Description** 

The HV9925 is a PWM peak current control IC for driving a buck converter topology in continuous conduction mode (CCM). The HV9925 controls the output current (rather than output voltage) of the converter that can be programmed by a single external resistor (RSENSE), for the purpose of driving a string of light emitting diodes (LED).  An external enable input (PWMD) is provided that can be utilized for PWM dimming of an LED string. The typical rising and falling edge transitions of the LED current when using the PWM dimming feature of the HV9925 are shown in Fig. 6 and Fig. 7. 

When the input voltage of 20 to 400V appears at the DRAIN pin, the internal linear regulator seeks to maintain a voltage of 7.5VDC at the VDD pin. Until this voltage exceeds the internally programmed under-voltage threshold, no output switching occurs. When the threshold is exceeded, the integrated high-voltage switch turns on, pulling the DRAIN low. A 200mV hysteresis is incorporated with  the undervoltage comparator to prevent oscillation. 

When the voltage at RSENSE exceeds 0.47V, the switch turns off and the DRAIN output becomes high impedance. At the same time, a one-shot circuit is activated that determines the off-time of the switch (10.5µs typ.). 

A “blanking” delay of 300ns is provided upon the turn-on of the switch that prevents false triggering of the current sense comparator due to the leading edge spike caused by circuit parasitics. 

## **Application Information** 

## **Selecting L1 and D1** 

The required value of L1 is inversely proportional to the ripple current ∆IO in it. Setting the relative peak-to-peak ripple to 20~30% is a good practice to ensure noise immunity of the current sense comparator. 

**==> picture [264 x 12] intentionally omitted <==**

VO is the forward voltage of the LED string. TOFF is the offtime of the HV9925. The output current in the LED string (IO) is calculated then as: 

**==> picture [264 x 12] intentionally omitted <==**

where VTH is the current sense comparator threshold, and RSENSE is the current sense resistor. The ripple current introduces a peak-to-average error in the output current setting that needs to be accounted for. Due to the constant off-time control technique used in the HV9925, the ripple current is nearly independent of the input AC or DC voltage variation. Therefore, the output current will remain unaffected by the varying input voltage. 

the output current ripple even further, thus permitting a reduced value of L1. However, one must keep in mind that the peak-to-average current error is affected by the variation be sacrificed at large ripple current in L1.of TOFF. Therefore, the initial output current accuracy might 

Another important aspect of designing an LED driver with HV9925 is related to certain parasitic elements of the circuit, including distributed coil capacitance of L1, junction capacitance, and reverse recovery of the rectifier diode D1, capacitance of the printed circuit board traces CPCB and output capacitance Celements affect the efficiency of the switching converter and DRAIN of the controller itself. These parasitic could potentially cause false triggering of the current sense comparator if not properly managed. Minimizing these parasitics is essential for efficient and reliable operation of HV9925. 

Coil capacitance of inductors is typically provided in the manufacturer’s data books either directly or in terms of the self-resonant frequency (SRF). 

SRF = 1 / (2π√(L • CL)) 

where L is the inductance value, and CL is the coil capacitance. Charging and discharging this capacitance every switching cycle causes high-current spikes in the LED string. Therefore, connecting a small capacitor CO (~10nF) is recommended to bypass these spikes. 

achieve high efficiency and reduce the risk of false triggering of the current sense comparator. Using diodes with shorter reverse recovery time _trr,_ and lower junction capacitance CJ, achieves better performance. The reverse voltage rating VR of the diode must be greater than the maximum input voltage of the LED lamp. 

The total parasitic capacitance present at the DRAIN output of the HV9925 can be calculated as: 

**==> picture [264 x 12] intentionally omitted <==**

When the switch turns on, the capacitance CP is discharged into the DRAIN output of the IC. The discharge current is limited to about 150mA typically. However, it may become lower at increased junction temperature. The duration of the leading edge current spike can be estimated as: 

**==> picture [264 x 12] intentionally omitted <==**

●  1235 Bordeaux Drive, Sunnyvale, CA 94089  ●  Tel: 408-222-8888  ●  www.supertex.com 

5 

**HV9925** 

In order to avoid false triggering of the current sense comparator, CP must be minimized in accordance with the following expression: 

When the LED driver is powered from the full-wave rectified AC line input, the exact equation for calculating the conduction loss is more cumbersome. However, it can be estimated using the following equation: 

**==> picture [13 x 11] intentionally omitted <==**

where TBLANK(MIN) is the minimum blanking time of 200ns, and VIN(MAX) is the maximum instantaneous input voltage. 

The typical DRAIN and RSENSE voltage waveforms are shown in Fig. 3 and Fig. 4. 

## **Estimating Power Loss** 

Discharging the parasitic capacitance CP into the DRAIN output of the HV9925 is responsible for the bulk of the switching power loss. It can be estimated using the following equation: 

**==> picture [13 x 11] intentionally omitted <==**

where FS is the switching frequency and ISAT is the saturated DRAIN current of the HV9925. The switching loss is the greatest at the maximum input voltage. 

Disregarding the voltage drop at HV9925 and D1, the switching frequency is given by the following: 

**==> picture [264 x 28] intentionally omitted <==**

When the HV9925 LED driver is powered from the full-wave rectified AC input, the switching power loss can be estimated as: 

**==> picture [13 x 10] intentionally omitted <==**

VAC is the input AC line voltage. 

The switching power loss associated with turn-off transitions of the DRAIN output can be disregarded. Due to the large amount of parasitic capacitance connected to this switching node, the turn-off transition occurs essentially at zerovoltage. 

When the HV9925 LED driver is powered from DC input voltages, conduction power loss  can be calculated as: 

**==> picture [263 x 12] intentionally omitted <==**

PCOND = (KC • IO2 • RON) + (KD • IDD • VAC)                           (10) where VAC is the input AC line voltage. The coefficients KC and Kd can be determined from the minimum duty ratio Dm=0.71Vo/(VAC). 

**==> picture [214 x 198] intentionally omitted <==**

**----- Start of picture text -----**<br>
0.7<br>0.6<br>0.5<br>KD (DM )<br>0.4<br>KC(DM )<br>0.3<br>0.2<br>0.1<br>0 0.1 0.2 0.3 0.4 0.5 0.6 0.7<br>DM<br>**----- End of picture text -----**<br>


**Figure 1.** C and Kd 

## **EMI Filter** 

to obtaining good EMI. A switching side capacitor, albeit of small value, is necessary in order to ensure low impedance to the high frequency switching currents of the converter. As a rule of thumb, this capacitor should be approximately 0.10.2 µF/W of LED output power. A recommended input filter is shown in Figure 2 for the following design example. 

## **Design Example 1** 

Let us design an HV9925 LED lamp driver meeting the following specifications: 

Input: Universal AC, 85-264VAC Output Current: 20mA Load: String of 10 LED (LW541C by OSRAM VF = 4.1V max. each) 

The schematic diagram of the LED driver is shown in Figure 2. 

where D = VO /VIN  is the duty ratio, RON is the ON resistance, IDD is the internal linear regulator current. 

●  1235 Bordeaux Drive, Sunnyvale, CA 94089  ●  Tel: 408-222-8888  ●  www.supertex.com 

6 

**HV9925** 

## **Step 1.** Calculating L1. 

The output voltage VO = 10 · VF ≈ 41V (max.). Use equation (1) assuming a 30% peak-to-peak ripple. 

L1 = (41V • 10.5µs) / (0.3 • 20mA) = 72mH 

Select L1 68mH, I=30mA. Typical SRF = 170KHz. Calculate the coil capacitance. 

**==> picture [11 x 7] intentionally omitted <==**

## **Step 2.** Selecting D1 

Usually, the reverse recovery characteristics of ultrafast rectifiers at IF = 20~50mA are not provided in the manufacturer’s data books. The designer may want to experiment with different diodes to achieve the best result. 

Select D1 MUR160 with VR = 600V, _trr_ ≈ 20ns (IF = 20mA, IRR = 100mA) and CJ ≈ 8pF (VF>50V). 

**Step 3.** Calculate total parasitic capacitance using (3): 

CP = 5pF + 5pF +13pF + 8pF = 31pF 

**Step 4.** Calculating the leading edge spike duration using (4) and (5): 

## Total power dissipation at V ~~A~~ C(max): 

P = 130mW + 50mW = 180mW TOTAL 

**Step 6.** Selecting input capacitor CIN 

Output Power = 41V  • 20mA = 820mW 

Select CIN ECQ-E4104KF by Panasonic (0.1µF, 400V, Metalized Polyester Film). 

## **Design Example 2** 

Let us now design a PWM-dimmable LED lamp driver using the HV9925: 

Input: Universal AC, 85-135VAC Output Current: 50mA Load: String of 12 LED (Power TOPLED[®] by OSRAM, VF = 2.5V max. each) 

The schematic diagram of the LED driver is shown in Fig.3. We will use an aluminum electrolytic capacitor for CIN in order to prevent interruptions of the LED current at zero crossings of the input voltage. As a “rule of thumb”, 2~3μF per each watt of the input power is required for CIN in this case. 

## **Step 1.** Calculating L1. 

The output voltage VO = 12 · VF = 30V (max.). Use equation (1) assuming a 30% peak-to-peak ripple. 

L1 = (30V • 10.5µs) / (0.3 • 50mA) = 21mH 

**Step 5.** Estimating power dissipation in HV9925 at 264VAC using (8) and (10) 

Select L1 22mH, I = 60mA. Typical SRF = 270KHz. Calculate the coil capacitance. 

## Switching power loss: 

10.5µs 

**Step 2.** Selecting D1 

P ≈ 130mW SWITCH 

Minimum duty ratio: 

DM = (0.71 • 41V) / 264V ≈ 0.11 

## Conduction power loss: 

P = COND 

0.20 • (20mA)[2] • 210Ω + 0.63 • 200µA • 264V ≈ 50mW 

Select D1 ES1G with VR = 400V, _trr_ ≈ 35ns and CJ < 8.0pF. 

**Step 3.** Calculating total parasitic capacitance using (3): 

CP = 5pF + 5pF +15pF + 8pF = 33pF 

**Step 4.** Calculating the leading edge spike duration using (4) and (5): 

**==> picture [142 x 23] intentionally omitted <==**

**Step 5.** Estimating power dissipation in HV9925 at 135VAC using (6), (7) and (9) 

●  1235 Bordeaux Drive, Sunnyvale, CA 94089  ●  Tel: 408-222-8888  ●  www.supertex.com 7 

**HV9925** 

## **Switching power loss:** 

## **Conduction power loss:** 

## 80kHz 10.5µs 

( ) 

P = SWITCH (33pF • (135V)[2] + 135V • √2 x 100mA • 35ns) • 80kHz 2 P ≈ 78mW SWITCH 

## **Minimum duty ratio:** 

DM = 30V / (135V • √2) ≈ 0.16 

P = 170mW COND 

## **Total power dissipation in HV9925:** 

P = 78mW + 170mW = 248mW TOTAL 

**Step 6.** Selecting input capacitor CIN 

Output Power = 30V • 50mA = 1.5W 

Select CIN 3.3µF, 250V. 

**Figure 2. Universal 85-264VAC LED Lamp Driver** 

_(IO = 20mA, VO = 50V) from Example 1_ 

**==> picture [385 x 181] intentionally omitted <==**

## **Figure 3.  85-135VAC LED Lamp Driver with PWM Dimming** 

●  1235 Bordeaux Drive, Sunnyvale, CA 94089  ●  Tel: 408-222-8888  ●  www.supertex.com 

8 

**HV9925** 

Figure 4. Switching Waveforms. CH1: VRSENSE, CH2: VDRAIN 

Figure 5. Switch-On Transition – Leading Edge Spike. CH1: VRSENSE, CH2: VDRAIN 

**==> picture [33 x 15] intentionally omitted <==**

**----- Start of picture text -----**<br>
TORU<br>**----- End of picture text -----**<br>


Figure 6. PWM Dimming – Rising Edge. CH4: 10×IOUT 

Figure 7. PWM Dimming – Falling Edge. CH4: 10×IOUT 

## **Pin Description** 

|**Pin #**|**Function **|**Description**|
|---|---|---|
|1|RSENSE|Source terminal of the output switching MOSFET provided for current sense resistor connection.|
|2|GND|Common connection for all circuits.|
|3|PWMD|PWM Dimming input to the IC.|
|4|VDD|Power supply pin for internal control circuits. Bypass this pin with a 0.1uF low impedance capacitor.|
|5|NC|No connection.|
|6|DRAIN|Drain terminal of the output switching MOSFET and a linear regulator input.|
|7|||
|8|||



●  1235 Bordeaux Drive, Sunnyvale, CA 94089  ●  Tel: 408-222-8888  ●  www.supertex.com 

9 

**HV9925** 

## **8-Lead SOIC (Narrow Body w/Heat Slug) Package Outline (SG)** _**4.90x3.90mm body, 1.70mm height (max), 1.27mm pitch**_ 

**==> picture [356 x 147] intentionally omitted <==**

**----- Start of picture text -----**<br>
D1<br>D<br>8 8<br>Exposed<br>Thermal<br>Pad Zone<br>E1 E E2<br>Note 1<br>(Index Area<br>D/2 x E1/2)<br>1 1<br>**----- End of picture text -----**<br>


## **Top View** 

## **Bottom View** 

**==> picture [510 x 139] intentionally omitted <==**

**----- Start of picture text -----**<br>
θ1<br>View B<br>h<br>h<br>A A2 Seating Note 1 L2 GaugePlane<br>Plane<br>A1 e b L θ Seating<br>L1 Plane<br>Side View View A - A View B<br>A<br>A<br>**----- End of picture text -----**<br>


## _**Notes:**_ 

_1. a molded mark/identifier; an embedded metal marker; or a printed indicator._ 

**==> picture [541 x 62] intentionally omitted <==**

**----- Start of picture text -----**<br>
Symbol A A1 A2 b D D1 E E1 E2 e h L L1 L2 θ θ1<br>MIN 1.25* 0.00 1.25 0.31 4.80* 3.30 [†] 5.80* 3.80* 2.29 [†] 0.25 0.40 0 [O] 5 [O]<br>Dimension 1.27 1.04 0.25<br>NOM - - - - 4.90 - 6.00 3.90 - - - - -<br>(mm) BSC REF BSC<br>MAX 1.70 0.15 1.55* 0.51 5.00* 3.81 [†] 6.20* 4.00* 2.79 [†] 0.50 1.27 8 [O] 15 [O]<br>**----- End of picture text -----**<br>


_JEDEC Registration MS-012, Variation BA, Issue E, Sept. 2005._ 

_† This dimension is a non-JEDEC dimension._ 

_**Drawings not to scale.**_ 

_**Supertex Doc. #:** DSPD-8SOSG, Version C090408._ 

_information go to http://www.supertex.com/packaging.html.)_ 

**Supertex inc.** does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such applications unless it receives an adequate “product liability indemnification insurance agreement.” **Supertex inc.** does not assume responsibility for use of devices described, and limits its liability to the replacement of the devices determined defective due to workmanship. No responsibility is assumed for possible omissions and inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications refer to the **Supertex inc.** website: http//www.supertex.com. 

> ©2008 All rights reserved. Unauthorized use or reproduction is prohibited. 

1235 Bordeaux Drive, Sunnyvale, CA 94089 Tel: 408-222-8888 _**www.supertex.com**_ 

_Doc.# DSFP-HV9925 A091708_ 

10