FSB70325

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## **FSB70325 Motion SPM[®] 7 Series** 

## **Features** 

- UL Certified No. E209204 (UL1557) 

- High Performance PQFN Package 

- 250 V RDS(on) = 1.4 Max FRFET MOSFET 3-Phase Inverter with Gate Drivers and Protection 

- Separate Open-Source Pins from Low-Side MOSFETs for Three-Phase Current-Sensing 

- Active-HIGH Interface, Works with 3.3 / 5 V Logic, Schmitt-trigger Input 

- Optimized for Low Electromagnetic Interference 

- HVIC Temperature-Sensing Built-In for Temperature Monitoring 

- HVIC for Gate Driving with Under-Voltage Protection and Interlock Function 

- Isolation Rating: 1500 Vrms / min. 

- Moisture Sensitive Level (MSL) 3 

- RoHS Compliant 

## **Application** 

- 3-Phase Inverter Driver for Small Power AC Motor Drives 

## **Related Source** 

- _AN-9077 - Motion SPM® 7 Series User’s Guide_ 

- _AN-9078 - Surface Mount Guidelines for Motion SPM® 7 Series_ 

## **General Description** 

The FSB70325 is an advanced Motion SPM **[®]** 7 module providing a fully-featured, high-performance inverter output stage for AC Induction, BLDC and PMSM motors. These modules integrate optimized gate drive of the built-in MOSFETs (FRFET **[®]** technology) to minimize EMI and losses, while also providing multiple on-module protection features including under-voltage lockouts, thermal monitoring, fault reporting and interlock function. The built-in one HVIC translates the incoming logic-level gate inputs to the high-voltage, high-current drive signals required to properly drive the module's internal MOSFETs.  Separate open-souce MOSFET terminals are available for each phase to support the widest variety of control algorithms. 

## 

## **Package Marking & Ordering Information** 

|**Device Marking**<br>~~a~~|**Device**<br>~~a~~|**Package**<br>~~ee~~|**Reel Size**<br>~~ee~~|**Tape Width**|**Quantity**|
|---|---|---|---|---|---|
|FSB70325<br>~~a~~|FSB70325<br>~~a~~|PQFN27A<br>~~ee~~|13’’<br>~~ee~~|24 mm|1000 units|



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## **Absolute Maximum Ratings** 

**Inverter Part** (each MOSFET unless otherwise specified.) 

|**Symbol**|**Parameter**|**Conditions**|**Rating**|**Unit**|
|---|---|---|---|---|
|VDSS|Drain-Source Voltage of Each MOSFET||250|V|
|*ID 25|Each MOSFET Drain Current, Continuous|TCB= 25°C (1st Notes 1)|4.1|A|
|*ID 80|Each MOSFET Drain Current, Continuous|TCB= 80°C|3.1|A|
|*IDP|Each MOSFET Drain Current, Peak|TCB= 25°C, PW < 100s|8.2|A|
|*PD|Maximum Power Dissipation|TCB= 25°C, For Each MOSFET|49|W|



**Control Part** (each HVIC unless otherwise specified.) 

|**Symbol**|**Parameter**|**Conditions**|**Rating**|**Unit**|
|---|---|---|---|---|
|VDD|Control Supply Voltage|Applied Between VDDand COM|20|V|
|VBS|High-side Bias Voltage|Applied Between VBand VS|20|V|
|VIN|Input Signal Voltage|Applied Between IN and COM|-0.3 ~ VDD+ 0.3|V|
|VFO|Fault Output Supply Voltage|Applied Between FO and COM|-0.3 ~ VDD+ 0.3|V|
|IFO|Fault Output Current|Sink Current FO Pin|5|mA|
|VCSC|Current Sensing Input Voltage|Applied Between Csc and COM|-0.3 ~ VDD+ 0.3|V|



## **Total System** 

|**Symbol**|**Parameter**|**Conditions**|**Rating**|**Unit**|
|---|---|---|---|---|
|TJ|Operating Junction Temperature||-40 ~ 150|°C|
|TSTG|Storage Temperature||-40 ~ 125|°C|
|VISO|Isolation Voltage|60 Hz, Sinusoidal, 1 Minute, Con-<br>nection Pins to Heat Sink Plate|1500|Vrms|



## **1st Notes:** 

1. TCB  is pad temperature of case bottom. 

2. Marking  “ * ” is  calculation value or design factor. 

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## **Pin descriptions** 

|**Pin Number**|**Pin Name**|**Pin Description**|
|---|---|---|
|1|/FO|Fault Output|
|2|VTS|Voltage Output of HVIC Temperature|
|3|Cfod|Capacitor for Duration of Fault Output|
|4|Csc|Capacitor (Low-pass Filter) for Short-circuit Current Detection Input|
|5|VDD|Supply Bias Voltage for IC and MOSFETs Driving|
|6|IN_UH|Signal Input for High-side U Phase|
|7|IN_VH|Signal Input for High-side V Phase|
|8 (8a)|COM|Common Supply Ground|
|9|IN_WH|Signal Input for High-side W Phase|
|10|IN_UL|Signal Input for Low-side U Phase|
|11|IN_VL|Signal Input for Low-side V Phase|
|12|IN_WL|Signal Input for Low-side W Phase|
|13|Nu|Negative DC-Link Input for U Phase|
|14|U|Output for U Phase|
|15|Nv|Negative DC-Link Input for V Phase|
|16|V|Output for V Phase|
|17|W|Output for W Phase|
|18|Nw|Negative DC-Link Input for W Phase|
|19|VS(W)|High-side Bias Voltage Ground for W phase Mosfet driving|
|20|PW|Positive DC-Link Input for W Phase|
|21|PV|Positive DC-Link Input for V Phase|
|22|PU|Positive DC-Link Input for U Phase|
|23 (23a)|VS(V)|High-side Bias Voltage Ground for V phase Mosfet driving|
|24 (24a)|VS(U)|High-side Bias Voltage Ground for U phase Mosfet driving|
|25|VB(U)|High-side Bias Voltage for U phase Mosfet driving|
|26|VB(V)|High-side Bias Voltage for V phase Mosfet driving|
|27|VB(W)|High-side Bias Voltage for W phase Mosfet driving|



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(19) VS(W) (22) Pu<br>(24), (24a) V(23), (23a) VS(U)S(V) (21) Pv<br>OUT(UH) (20) Pw<br>(25) VB(U) VB(U)<br>(26) VB(V) VB(V) VS(U) (14) U<br>(27) VB(W) VB(W)<br>OUT(VH)<br>VS(V) (16) V<br>(5) VDD VDD<br>(8),(8a) COM COM OUT(WH)<br>(7) IN_VH(6) IN_UH UHVH VS(W) (17) W<br>(9) IN_WH WH<br>(10) IN_UL UL OUT(UL)<br>(11) IN_VL VL<br>(12) IN_WL WL (13) Nu<br>(1) /Fo /Fo<br>(2) VTS VTS OUT(VL)<br>(4) Csc(3) Cfod CfodCsc (15) Nv<br>OUT(WL)<br>(18) Nw<br>**----- End of picture text -----**<br>


## **Figure 1. Pin Configuration and Internal Block Diagram** 

**1st Notes:** 

4. Source terminal of each low-side MOSFET is not connected to supply ground or bias voltage ground inside Motion SPM[®] 7 product. External connections should be made as indicated in Figure 2. 

5. The suffix -a pad is connected with same number pin. ex) 8 and 8a is connected inside. 

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**Electrical Characteristics** (TJ = 25°C, VDD = VBS = 15 V unless otherwise specified.) 

**Inverter Part** (each MOSFET unless otherwise specified.) 

|**Symbol**|**Parameter**|**Conditions**|**Conditions**|**Min**|**Typ**|**Max**|**Unit**|
|---|---|---|---|---|---|---|---|
|BVDSS|Drain - Source<br>Breakdown Voltage|VIN= 0 V, ID= 1 mA (2nd Notes 1)||250|-|-|V|
|IDSS|Zero Gate Voltage<br>Drain Current|VIN= 0 V, VDS= 250 V||-|-|1|mA|
|RDS(on)|Static Drain - Source<br>Turn-On Resistance|VDD= VBS= 15 V, VIN= 5 V, ID= 1.0 A||-|1.1|1.4||
|VSD|Drain - Source Diode<br>Forward Voltage|VDD= VBS= 15V, VIN= 0 V, ID= -1.0 A||-|0.9|1.2|V|
|tON|Switching Times|VPN= 150 V, VDD= VBS= 15 V, ID= 1.0 A<br>VIN= 0 V5 V, Inductive Load L = 3 mH<br>Low-Side MOSFET Switching<br>(2nd Notes 2)||-|460|-|ns|
|tD(ON)||||-|405|-|ns|
|tOFF||||-|340|-|ns|
|tD(OFF)||||-|280|-|ns|
|Irr||||-|1.3|-|A|
|trr||||-|72|-|ns|
|EON||||-|25|-|J|
|EOFF||||-|22|-|J|
|**Control Part**(each HVIC unless otherwise specified.)||||||||
|**Symbol**|**Parameter**|**Conditions**||**Min**|**Typ**|**Max**|**Units**|
|IQDD|Quiescent VDDCurrent|VDD=15V, VIN=0V|VDD- COM|-|1.7|3.0|mA|
|IQBS|Quiescent VBSCurrent|VBS=15V, VIN=0V|VB(X)-VS(X),VB(V)-VS(V),<br>VB(W)-VS(W)|-|45|70|A|
|IPDD|Operating VDDCurrent|VDD=15V,FPWM=20kHz,<br>duty=50%, PWM signal<br>input for Low side|VDD- COM|-|1.9|3.2|mA|
|IPBS|Operating VBSCurrent|VBS=15V,FPWM=20kHz,<br>duty=50%, PWM signal<br>input for High side|VB(U)-VS(U),VB(V)-VS(V),<br>VB(W)-VS(W)|-|300|400|A|
|UVDDD|Low-side Undervoltage<br>Protection (Figure 6)|VDDUndervoltage Protection Detection Level||7.4|8.0|9.4|V|
|UVDDR||VDDUndervoltage Protection Reset Level||8.0|8.9|9.8|V|
|UVBSD|High-side  Undervoltage<br>Protection (Figure 7)|VBSUndervoltage Protection Detection Level||7.4|8.0|9.4|V|
|UVBSR||VBSUndervoltage Protection Reset Level||8.0|8.9|9.8|V|
|VTS|HVIC Temperature sens-<br>ing voltage output|VDD=15V, THVIC=25°C  (2nd Notes 3)||580|675|770|mV|
|VIH|ON Threshold Voltage|Logic High Level|IN - COM|-|-|2.4|V|
|VIL|OFF Threshold Voltage|Logic Low Level||0.8|-|-|V|
|VSC(ref)|SC Current Trip Level|VDD=15V|CSC- COM|0.45|0.5|0.55|V|
|tFOD|Fault-out Pulse Width|CFOD=33nF (2nd Notes 4)||1.0|1.4|1.8|ms|



## **2nd Notes:** 

1. BVDSS is the absolute maximum voltage rating between drain and source terminal of each MOSFET inside Motion SPM[®] 7 product. VPN should be sufficiently less than this value considering the effect of the stray inductance so that VPN should not exceed BVDSS in any case. 

2. tON and tOFF include the propagation delay of the internal drive IC. Listed values are measured at the laboratory test condition, and they can be different according to the field applications due to the effect of different printed circuit boards and wirings. Please see Figure 3 for the switching time definition with the switching test circuit of Figure 4. 

3. VTS is only for sensing-temperature of module and cannot shutdown MOSFETs automatically. 

4. The fault-out pulse width tFOD depends on the capacitance value of CFOD according to the following approximate equation : CFOD = 24 x 10[-6] x tFOD [F] 

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## **Recommended Operating Condition** 

|**Symbol**|**Parameter**|**Conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|VPN|Supply Voltage|Applied Between P and N|-|150|200|V|
|VDD|Control Supply Voltage|Applied Between VDDand COM|13.5|15.0|16.5|V|
|VBS|High-Side Bias Voltage|Applied Between VBand VS|13.5|15.0|16.5|V|
|dVDD/dt,<br>dVBS/dt|Control Supply Variation||-1.0|-|1.0|V/s|
|tdead|Blanking Time for Preventing<br>Arm-Short|VDD= VBS= 13.5 ~ 16.5 V, TJ 150°C|500|-|-|ns|
|fPWM|PWM Switching Frequency|TJ 150°C|-|15|-|kHz|



## **Thermal Resistance** 

|**Symbol**|**Parameter**|**Conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|RJCB|Junction to Case Bottom<br>Thermal Resistance|Single MOSFET Operating Condition<br>(3rd Notes 1)|-|2.0|-|°C/W|



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These values depend on PWM<br>5-V 15-V  control algorithm<br>Line Line One-Leg Diagram of SPM<br>C1<br>VB P VPN<br>Micom R5 HINLINVDD HOVS OutputInverter C3<br>/Fo<br>C5 VTS LO<br>C 4 CSC N R3<br>COM<br>10F C2 C 6<br>R2 * Example of bootstrap paramters:<br>    C 1  = C 2  = 1  F ceramic capacitor,<br>**----- End of picture text -----**<br>


## **Figure 2. Recommended MCU Interface and Bootstrap Circuit with Parameters** 

## **3rd Notes:** 

1.  RJCB is simulation value with application board layout. (Please refer user’s guide SPM7 series) 

2. Parameters for bootsrap circuit elements are dependent on PWM algorithm. For 15 kHz of switching frequency, typical example of parameters is shown above. 3. RC coupling(R5 and C5) at each input (indicated as dotted lines) may be used to prevent improper input signal due to surge noise. Signal input of SPM[® ] is compatible with standard CMOS or LSTTL outptus. 

4. Bold lines should be short and thick in PCB pattern to have small stray inductance of circuit, which results in the reduction of surge voltage. 

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1 0 0 %  I D 1 2 0 %  I D<br>t r r<br>I r r<br>V D S I D I D V D S<br>V I N V I N<br>t D ( O N ) t D ( O F F )<br>t O N t O F F<br>V I N ( O N ) 1 0 %  I D 9 0 %  I D V I N ( O F F ) 9 0 %  I D 1 0 %  I D<br>( a )  T u r n - o n ( b )  T u r n - o f f<br>0<br>**----- End of picture text -----**<br>


**Figure 3. Switching Time Definition** 

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5-V 15-V<br>Line Line<br>ID<br>HINVDD HOVB L VDC<br>LIN VS<br>+<br>/Fo LO V DS<br>VTS -<br>COM<br>**----- End of picture text -----**<br>


**Figure 4. Switching Test Circuit (Low-side)** 

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Input Signal<br>UV ProtectionStatus RESET DETECTION RESET<br>High-side/Low-side UVBSR(DDR)<br>UVBSD(DDD)<br>MOSFET Drain Current<br>Fault Output<br>(Only Low-side UV protection)<br>**----- End of picture text -----**<br>


**Figure 5. Under Voltage Protection** 

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Control input c6 c7<br>Protection<br>Circuit state SET RESET<br>Internal MOSFET c4<br>Gate-Source Voltage c3<br>c2<br>SC<br>c1<br>Output Current c8<br>SC Reference Voltage<br>Sensing Voltage<br>of the shunt<br>resistance CR circuit time<br>constant delay<br>Fault Output Signal c5<br>**----- End of picture text -----**<br>


**Figure 6. Short-Circuit Current Protection** 

(with the external shunt resistance and CR connection) 

c1 : Normal operation: MOSFET ON and carrying current. c2 : Short circuit current detection (SC trigger). c3 : Hard MOSFET gate interrupt. 

c4 : MOSFET turns OFF. 

c5 : Fault output timer operation start : Fault-out width (tFOD) 

- c6 : Input “L” : MOSFET OFF state. 

c7 : Input “H”: MOSFET ON state, but during the active period of fault output the MOSFET doesn’t turn ON. c8 : MOSFET OFF state 

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Hin<br>Lin<br>Ho<br>Lo<br>**----- End of picture text -----**<br>


**Figure 7. Timing Chart of Interlock Function** 

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4.0<br> Min.<br>3.5  Typ.<br> Max.<br>3.0 Typ. 2.57V@125°Ｃ<br>2.5 Typ. 2.10V@100°Ｃ 125±5°Ｃ<br>2.0<br>100±5°Ｃ<br>1.5 Typ. 1.15V@50°Ｃ<br>1.0 50±5°Ｃ<br>0.5<br>0.0<br>0 25 50 75 100 125 150 175<br>HVIC Temperature, THVIC  [°Ｃ]<br>[V]<br>TS<br>Temperature Sensing Voltage, V<br>**----- End of picture text -----**<br>


## **Figure 8. Temperature profile VTS vs. THVIC** 

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 VS(W)<br> VVS(U)S(V) P<br>C1  VB(U) OUT(UH)<br> VVBB(V)(W) VB(U)VB(V) VS(U) U<br>VB(W)<br>OUT(VH)<br>V<br>VS(V) M<br>C3 VDC<br>15V<br>5V VDD VDD OUT(WH)<br>C2  COM COM VS(W) W<br>MCU R5 IN_VLINININ_WHIN_ULIN_WL/Fo__VHUH /FoUHVHWHULVLWL OUT(UL)OUT(VL) NuNv R3<br>C8 C5 CfodVTS Vts OUT(WL)<br>Csc Cfod Nw<br>Csc<br>C4 C7 R2<br>C6<br>**----- End of picture text -----**<br>


## **Figure 9. Example of Application Circuit** 

## **4th Notes:** 

1. RC-coupling (R5 and C5, R2 and C6) and C1, C5, C7, C8 at each input of Motion SPM[®] 7 product and MCU are useful to prevent improper input signal caused by surge-noise. 

2. Ground-wires and output terminals, should be thick and short in order to avoid surge-voltage and malfunction of HVIC. 

3. All the filter capacitors should be connected close to Motion SPM 7 product, and they should have good characteristics for rejecting high-frequency ripple current. 

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0.10 C A B<br>0.75<br>0.65<br>0.55 [(9X)]<br>1 2 3 4 5 6 7 8 9 10 11 12 13<br>6.45<br>5.85 27<br>5.80<br>5.60<br>5.05<br>4.75<br>4.50<br>26 14<br>0.40 3.90<br>0.20 [(26X)] 8a<br>2.85<br>(1.15)<br>15 2.25<br>1.85 25 2.05<br>1.55<br>1.15 24 (1.50) (1.60) 1.00<br>16<br>0.45 0.60<br>0.00 24a<br>0.15 23 23a 0.65 16 0.80<br>0.20<br>1.20<br>0.30 1.10<br>2.25<br>2.50 2.65<br>2.75 22 17<br>2.90<br>17 4.05<br>4.40 4.45<br>22<br>4.90<br>5.60<br>5.95 6.10<br>22<br>6.45<br>22 21 21 20 20 19 18 18 0.35<br>0.35 0.15 [(6X)]<br>0.15 1.65<br>(4X) 1.45<br>BOTTOM VIEW<br>13.00 SCALE: 2:1<br>A<br>12.80<br>PKG<br>CL<br>22 21 21 20 20 19 18 18 B<br>22<br>22 0.10 C<br>17<br>22 1.40<br>17 1.20<br>13.00<br>23a 16 12.80 0.08 C<br>PKG [C] L23 24a C<br>2425 16 0.300.20 0.050.00 SEATING<br>15 PLANE<br>8a<br>26 14 SCALE: 2:1<br>27<br>PIN 1 1 2 3 4 5 6 7 8 9 10 1112 13<br>QUADRANT TOP VIEW<br>SEE DETAIL 'A'<br>0.10 C<br>1.40<br>1.20 FRONT VIEW<br>0.00<br>6.45 5.80 4.70 4.60 0.25 1.35 4.75 5.28 5.55 5.80 6.08<br>6.45 6.10 5.07 3.80 3.20 2.50 1.20 1.00 0.40 1.70 2.75 3.25 4.53<br>**----- End of picture text -----**<br>


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0.35<br>0.55<br>22 21 21 20 20 19 18 18<br>6.88<br>6.13 22 6.13<br>0.35 5.58<br>TYP 4.88<br>4.40 22 17 4.48<br>4.05<br>2.73 22<br>2.65<br>2.48 17<br>2.23<br>1.55 1.65<br>23a 1.23<br>0.98<br>0.80<br>0.20 23 24a 0.70 16<br>0.00 0.65<br>0.48 16 0.60<br>1.15 24 1.05 1.03<br>1.53<br>1.85 25 2.03<br>15 2.23<br>1.11 (9X) 8a 2.88<br>3.42<br>3.88<br>4.50 26 14<br>4.78<br>5.08<br>27 5.58<br>5.85<br>5.78<br>0.35 6.23<br>1 2 3 4 5 6 7 8 9 10 11 12 13 6.88<br>0.65<br>TYP 0.30<br>0.00<br>6.88 6.12 5.07 3.77 3.22 2.50 2.03 1.05 0.97 0.42 1.55 1.73 3.00 4.50 6.10 6.13 6.88<br>5.78 4.72 4.63 0.10 0.28 1.33 2.70 2.73 4.78 5.25 5.80 6.10<br>**----- End of picture text -----**<br>


LAND PATTERN RECOMMENDATION 

SCALE: 2:1 

## NOTES: UNLESS OTHERWISE SPECIFIED 

- A)  THIS PACKAGE IS NOT PRESENTLY REGISTERED TO ANY STANDARD COMMITTEE. 

- B)  DIMENSIONS DO NOT INCLUDE BURRS    OR MOLD FLASH. MOLD FLASH OR BURRS DOES NOT EXCEED 0.10MM. 

- C)  ALL DIMENSIONS ARE IN MILLIMETERS. 

- D)  DRAWING CONFORMS TO ASME Y14.5M-1994. 

- E)  LAND PATTERN REFERENCE: QFN65P1290X1290X140-40N-40N 

- F)  DRAWING FILE NAME: MKT-PQFN27AREV3. 

- G)  IT IS NOT  NECESSARY  TO SOLDER  23a AND 

- 24a, AND CAN BE OMITTED FROM THE FOOTPRINT 

- H)  FAIRCHILD SEMICONDUCTOR 

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