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FSB50550BS
Intelligent Power Module (IPM), MOSFET, 500 V, 7 A, 1500 Vrms, SPM5Q-023, SPM5
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- Manufacturer: ONSEMI
- Product type: Intelligent Power Modules
- IPM Power Device:MOSFET; Voltage Rating (Vces / Vdss):500V; Current Rating (Ic / Id):7A; Isolation Voltage:1500Vrms; IPM Case Style:SPM5Q-023; IPM Series:SPM5; Product Range:Motio
- SVHC: Lead (25-Jun-2025)
- IPM Series: SPM5
- Product Range: Motion SPM 5 Series
- IPM Case Style: SPM5Q-023
- IPM Power Device: MOSFET
- Isolation Voltage: 1500Vrms
- Current Rating (Ic / Id): 7A
- Voltage Rating (Vces / Vdss): 500V
| Delivery and price | |
|---|---|
| Units per pack | 250 |
| Price | 3.54 € |
| Current stock | 200+ |
| Lead time | 30 days |
Datasheet
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February 2017 ## **FSB50550B / FSB50550BS Motion SPM[®] 5 Series** ## **Features** - UL Certified No. E209204 (UL1557) - Optimized for over 10 kHz Switching Frequency - 500 V FRFET MOSFET 3-Phase Inverter with Gate Drivers and Protection ## **Related Source** - _RD-FSB50450AS - Reference Design for Motion SPM 5 Series Ver.2_ - _AN-9082 - Motion SPM5 Series Thermal Performance by Contact Pressure_ - Built-In Bootstrap Diodes Simplify PCB Layout - Separate Open-Source Pins from Low-Side MOSFETs for Three-Phase Current-Sensing - Active-HIGH Interface, Works with 3.3 / 5 V Logic, Schmitt-trigger Input - Optimized for Low Electromagnetic Interference - HVIC Temperature-Sensing Built-In for Temperature Monitoring - HVIC for Gate Driving and Under-Voltage Protection - Isolation Rating: 1500 Vrms / min. - RoHS Complia - Moisture Sensitive Level (MSL) 3 for SMD PKG ## **Applications** - 3-Phase Inverter Driver for Small Power AC Motor Drives ## **General Description** The FSB50550B / FSB50550BS is an advanced Motion SPM **[®]** 5 module providing a fully-featured, highperformance inverter output stage for AC Induction, BLDC and PMSM motors. These modules integrate optimized gate drive of the built-in MOSFETs (FRFET **[®]** technology) to minimize EMI and losses, while also providing multiple on-module protection features including under-voltage lockouts and thermal monitoring. The built-in high-speed HVIC requires only a single supply voltage and translates the incoming logic-level gate inputs to the high-voltage, high-current drive signals required to properly drive the module's internal MOSFETs. Separate open-source MOSFET terminals are available for each phase to support the widest variety of control algorithms. **< FSB50550B > <FSB50550BS > Figure 1. 3D Package Drawing (Click to Activate 3D Content)** **Package Marking & Ordering Information** **Device Device Marking Package Packing Type Reel Size Quantity** FSB50550B FSB50550B SPM5P-023 Rail NA 15 FSB50550BS FSB50550BS SPM5Q-023 Tape & Reel 330mm 450 ~~Be~~ Semiconductor Components Industries, LLC, 2017 www.fairchildsemi.com FSB50550B / FSB50550BS **[.]** Rev. 1.2 www.onsemi.com **1** ## **Absolute Maximum Ratings** **Inverter Part** (each MOSFET unless otherwise specified.) |**Symbol**|**Parameter**|**Conditions**|**Rating**|**Unit**| |---|---|---|---|---| |VDSS|Drain-Source Voltage of Each MOSFET||500|V| |*ID 25|Each MOSFET Drain Current, Continuous|TC= 25°C|3.0|A| |*ID 80|Each MOSFET Drain Current, Continuous|TC= 80°C|1.9|A| |*IDP|Each MOSFET Drain Current, Peak|TC= 25°C, PW < 100μs|7.0|A| |*IDRMS|Each MOSFET Drain Current, Rms|TC= 80°C, FPWM< 20 kHz|1.3|Arms| **Control Part** (each HVIC unless otherwise specified.) |**Symbol**|**Parameter**|**Conditions**|**Rating**|**Unit**| |---|---|---|---|---| |VDD|Control Supply Voltage|Applied between VDDand COM|20|V| |VBS|High-side Bias Voltage|Applied between VBand VS|20|V| |VIN|Input Signal Voltage|Applied between VINand COM|-0.3 ~ VDD+ 0.3|V| **Bootstrap Diode Part** (each bootstrap diode unless otherwise specified.) |**Symbol**|**Parameter**|**Conditions**|**Rating**|**Unit**| |---|---|---|---|---| |VRRMB|Maximum Repetitive Reverse Voltage||500|V| |* IFB|Forward Current|TC= 25°C|0.5|A| |* IFPB|Forward Current (Peak)|TC= 25°C, Under 1ms Pulse Width|2.0|A| ## **Thermal Resistance** |**Symbol**|**Parameter**|**Conditions**|**Rating**|**Unit**| |---|---|---|---|---| |Rth(j-c)Q|Junction to Case Thermal Resistance<br>( Note1 )|Inverter MOSFET part, (Per Module)|2.2|°C/W| |**Total System**||||| |**Symbol**|**Parameter**|**Conditions**|**Rating**|**Unit**| |TJ|Operating Junction Temperature||-40 ~ 150|°C| |TSTG|Storage Temperature||-40 ~ 125|°C| |VISO|Isolation Voltage|60 Hz, Sinusoidal, 1 Minute, Con-<br>nect Pins to Heat Sink Plate|1500|Vrms| ## **Notes:** 1. For the measurement point of case temperature TC, please refer to Figure 4. 2. Marking “ * “ is calculation value or design factor. Semiconductor Components Industries, LLC, 2017 www.fairchildsemi.com FSB50550B / FSB50550BS **[.]** Rev. 1.2 www.onsemi.com **2** ## **Pin descriptions** |**Pin Number**|**Pin Name**|**Pin Description**| |---|---|---| |1|COM|IC Common Supply Ground| |2|VB(U)|Bias Voltage for U-Phase High-Side MOSFET Driving| |3|VDD(U)|Bias Voltage for U-Phase IC and Low-Side MOSFET Driving| |4|IN(UH)|Signal Input for U-Phase High-Side| |5|IN(UL)|Signal Input for U-Phase Low-Side| |6|N.C|No Connection| |7|VB(V)|Bias Voltage for V-Phase High Side MOSFET Driving| |8|VDD(V)|Bias Voltage for V-Phase IC and Low Side MOSFET Driving| |9|IN(VH)|Signal Input for V-Phase High-Side| |10|IN(VL)|Signal Input for V-Phase Low-Side| |11|VTS|Output for HVIC Temperature Sensing| |12|VB(W)|Bias Voltage for W-Phase High-Side MOSFET Driving| |13|VDD(W)|Bias Voltage for W-Phase IC and Low-Side MOSFET Driving| |14|IN(WH)|Signal Input for W-Phase High-Side| |15|IN(WL)|Signal Input for W-Phase Low-Side| |16|N.C|No Connection| |17|P|Positive DC-Link Input| |18|U, VS(U)|Output for U-Phase & Bias Voltage Ground for High-Side MOSFET Driving| |19|NU|Negative DC-Link Input for U-Phase| |20|NV|Negative DC-Link Input for V-Phase| |21|V, VS(V)|Output for V-Phase & Bias Voltage Ground for High-Side MOSFET Driving| |22|NW|Negative DC-Link Input for W-Phase| |23|W, VS(W)|Output for W Phase & Bias Voltage Ground for High-Side MOSFET Driving| |(1) COM<br>(2) VB(U)<br>(3) VDD(U)<br>(4) IN (UH)<br>(5) IN (UL)<br>(6) N.C<br>(7) VB(V)<br>(8) VDD(V)<br>(9) IN (VH)<br>(10) IN (VL)<br>(11) VTS<br>(12) V B(W)<br>(13) VDD(W)<br>(14) IN (WH)<br>(15) IN (WL)<br>(16)<br>N.C|||||||||(17) P<br>(18) U, VS(U)<br>(19) NU<br>(20) NV<br>(21) V, VS(V)<br>(22) NW<br>(23) W, VS(W)| |---|---|---|---|---|---|---|---|---|---| |||VDD<br>VB|||||||| ||||COM<br>LIN<br>HIN<br>HO<br>VS<br>LO||||||| ||||||||||| ||||||||||| ||||||||||| ||||COM<br>VDD<br>LIN<br>HIN<br>VB<br>HO<br>VS<br>LO<br>VTS||||||| ||||||||||| ||||||||||| ||||||||||| ||||||||||| ||||||||||| |||VDD<br>VB|||||||| ||||COM<br><br>LIN<br>HIN<br><br>HO<br>VS<br>LO||||||| ||||||||||| ||||||||||| ||||||||||| ## **Figure 2. Pin Configuration and Internal Block Diagram (Bottom View)** **Notes:** 3. Source terminal of each low-side MOSFET is not connected to supply ground or bias voltage ground inside Motion SPM[®] 5 product. External connections should be made as indicated in Figure 3. Semiconductor Components Industries, LLC, 2017 www.fairchildsemi.com FSB50550B / FSB50550BS **[.]** Rev. 1.2 www.onsemi.com **3** **Electrical Characteristics** (TJ = 25°C, VDD = VBS = 15 V unless otherwise specified.) **Inverter Part** (each MOSFET unless otherwise specified.) |**Symbol**|**Parameter**|**Conditions**|**Conditions**|**Min**|**Typ**|**Max**|**Unit**| |---|---|---|---|---|---|---|---| |BVDSS|Drain - Source<br>Breakdown Voltage|VIN= 0 V, ID= 1 mA ( Note 4)||500|-|-|V| |IDSS|Zero Gate Voltage<br>Drain Current|VIN= 0 V, VDS= 500 V||-|-|1|mA| |RDS(on)|Static Drain - Source<br>Turn-On Resistance|VDD= VBS= 15 V, VIN= 5 V, ID= 1.0 A||-|2.3|3.0|Ω| |VSD|Drain - Source Diode<br>Forward Voltage|VDD= VBS= 15V, VIN= 0 V, ID= -1.0 A||-|-|1.3|V| |tON|Switching Times|VPN= 300 V, VDD= VBS= 15 V, ID= 1.0 A<br>VIN= 0 V↔5 V, Inductive Load L = 3 mH<br>High- and Low-Side MOSFET Switching<br>( Note 5)||-|350|-|ns| |tOFF||||-|500|-|ns| |trr||||-|60|-|ns| |EON||||-|22|-|μJ| |EOFF||||-|3|-|μJ| |RBSOA|Reverse Bias Safe Oper-<br>ating Area|VPN= 400 V, VDD= VBS= 15 V, ID= (TBD), VDS=<br>BVDSS, TJ= 150°C<br>High- and Low-Side MOSFET Switching ( Note 6)||<br>Full Square|||| |**Control Part**(each HVIC unless otherwise specified.)|||||||| |**Symbol**|**Parameter**|**Conditions**||**Min**|**Typ**|**Max**|**Unit**| |IQDD|Quiescent VDDCurrent|VDD= 15 V,<br>VIN= 0 V|Applied between VDDand COM|-|-|200|μA| |IQBS|Quiescent VBSCurrent|VBS= 15 V,<br>VIN= 0 V|Applied between VB(U)- U,<br>VB(V)- V, VB(W)- W|-|-|100|μA| |IPDD|Operating<br>VDD<br>Supply<br>Current|<br>VDD- COM|VDD= 15 V, fPWM= 20 kHz, duty<br>= 50%, Applied to One PWM Sig-<br>nal Input for Low-Side|<br>-|-|900|μA| |IPBS|Operating<br>VBS<br>Supply<br>Current|<br>VB(U)- VS(U), VB(V)<br>- VS(V), VB(W)-<br>VS(W)|VDD= VBS= 15 V, fPWM= 20 kHz,<br>Duty = 50%, Applied to One PWM<br>Signal Input for High-Side|<br> <br>-|-|800|μA| |UVDDD|Low-Side Under-Voltage<br>Protection (Figure 8)|VDDUnder-Voltage Protection Detection Level||7.4|8.0|9.4|V| |UVDDR||VDDUnder-Voltage Protection Reset Level||8.0|8.9|9.8|V| |UVBSD|High-Side Under-Voltage<br>Protection (Figure 9)|VBSUnder-Voltage Protection Detection Level||7.4|8.0|9.4|V| |UVBSR||VBSUnder-Voltage Protection Reset Level||8.0|8.9|9.8|V| |VTS|HVIC Temperature Sens-<br>ing Voltage Output|VDD= 15 V, THVIC= 25°C ( Note 7)||600|790|980|mV| |VIH|ON Threshold Voltage|Logic HIGH Level|Applied between VINand COM|-|-|2.9|V| |VIL|OFF Threshold Voltage|Logic LOW Level||0.8|-|-|V| |**Bootstrap Diode Part**(each bootstrap diode unless otherwise specified.)|**Bootstrap Diode Part**(each bootstrap diode unless otherwise specified.)|**Bootstrap Diode Part**(each bootstrap diode unless otherwise specified.)|**Bootstrap Diode Part**(each bootstrap diode unless otherwise specified.)|**Bootstrap Diode Part**(each bootstrap diode unless otherwise specified.)|**Bootstrap Diode Part**(each bootstrap diode unless otherwise specified.)|**Bootstrap Diode Part**(each bootstrap diode unless otherwise specified.)| |---|---|---|---|---|---|---| |**Symbol**|**Parameter**|**Conditions**|**Min**|**Typ**|**Max**|**Unit**| |VFB|Forward Voltage|IF= 0.1 A, TC= 25°C (Note 8)|-|2.5|-|V| |trrB|Reverse Recovery Time|IF= 0.1 A, TC= 25°C|-|80|-|ns| Semiconductor Components Industries, LLC, 2017 www.fairchildsemi.com FSB50550B / FSB50550BS **[.]** Rev. 1.2 www.onsemi.com **4** ## **Recommended Operating Condition** |**Symbol**|**Parameter**|**Conditions**|**Min.**|**Typ.**|**Max.**|**Unit**| |---|---|---|---|---|---|---| |VPN|Supply Voltage|Applied between P and N|-|300|400|V| |VDD|Control Supply Voltage|Applied between VDDand COM|13.5|15.0|16.5|V| |VBS|High-Side Bias Voltage|Applied between VBand VS|13.5|15.0|16.5|V| |VIN(ON)|Input ON Threshold Voltage|Applied between VINand COM|3.0|-|VDD|V| |VIN(OFF)|Input OFF Threshold Voltage||0|-|0.6|V| |tdead|Blanking Time for Preventing<br>Arm-Short|VDD= VBS= 13.5 ~ 16.5 V, TJ ≤150°C|1.0|-|-|μs| |fPWM|PWM Switching Frequency|TJ ≤150°C|-|15|-|kHz| ## **Built-In Bootstrap Diode VF-IF Characteristic** **==> picture [306 x 204] intentionally omitted <==** **----- Start of picture text -----**<br> 1.0<br>0.9<br>0.8<br>0.7<br>0.6<br>0.5<br>0.4<br>0.3<br>0.2<br>0.1<br>0.0<br>0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15<br>VF [V] TC = 25°C<br> [A]<br>IF<br>**----- End of picture text -----**<br> ## **Figure 3. Built-In Bootstrap Diode Characteristics (Typical)** ## **Notes:** 4. BVDSS is the absolute maximum voltage rating between drain and source terminal of each MOSFET inside Motion SPM[®] 5 product. VPN should be sufficiently less than this value considering the effect of the stray inductance so that VPN should not exceed BVDSS in any case. 5. tON and tOFF include the propagation delay of the internal drive IC. Listed values are measured at the laboratory test condition, and they can be different according to the field applications due to the effect of different printed circuit boards and wirings. Please see Figure 6 for the switching time definition with the switching test circuit of Figure 7. 6. The peak current and voltage of each MOSFET during the switching operation should be included in the Safe Operating Area (SOA). Please see Figure 7 for the RBSOA test circuit that is same as the switching test circuit. 7. Vts is only for sensing-temperature of module and cannot shutdown MOSFETs automatically. 8. Built-in bootstrap diode includes around 15 Ω resistance characteristic. Please refer to Figure 2. Semiconductor Components Industries, LLC, 2017 www.fairchildsemi.com FSB50550B / FSB50550BS **[.]** Rev. 1.2 www.onsemi.com **5** **==> picture [460 x 602] intentionally omitted <==** **----- Start of picture text -----**<br> These values depend on PWM control algorithm<br>+15 V C1 * Example Circuit : V phase<br>Sh<br>VDC<br>P HIN LIN Output Note<br>VDD VB Inverter 0 0 Z Both FRFET Off<br>R5 HIN HO V Output 0 1 0 Low side FRFET On<br>?<br>foe LIN VS C3 1 0 VDC High side FRFET On<br>es C5 COM LO | 1 1 Forbidden Shoot through<br>VTS N R3 Open Open Z Same as (0,0)<br>Se<br>10 μF C2 C4 One Leg Diagram of Motion SPM [®] 5 Product<br>* Example of Bootstrap Paramters:<br>C1 = C2 = 1 μF Ceramic Capacitor<br>Figure 4. Recommended MCU Interface and Bootstrap Circuit with Parameters<br>Notes:<br>9. Parameters for bootstrap circuit elements are dependent on PWM algorithm. For 15 kHz of switching frequency, typical example of parameters is shown above.<br>10.RC-coupling (R5 and C5) and C4 at each input of Motion SPM 5 product and MCU (Indicated as Dotted Lines) may be used to prevent improper signal due to surge-noise. 5 and C5) and C4 at each input of Motion SPM 5 product and MCU (Indicated as Dotted Lines) may be used to prevent improper signal due to surge-noise. and C5) and C4 at each input of Motion SPM 5 product and MCU (Indicated as Dotted Lines) may be used to prevent improper signal due to surge-noise. 5) and C4 at each input of Motion SPM 5 product and MCU (Indicated as Dotted Lines) may be used to prevent improper signal due to surge-noise. ) and C4 at each input of Motion SPM 5 product and MCU (Indicated as Dotted Lines) may be used to prevent improper signal due to surge-noise. 4 at each input of Motion SPM 5 product and MCU (Indicated as Dotted Lines) may be used to prevent improper signal due to surge-noise. at each input of Motion SPM 5 product and MCU (Indicated as Dotted Lines) may be used to prevent improper signal due to surge-noise.<br>11. Bold lines should be short and thick in PCB pattern to have small stray inductance of circuit, which results in the reduction of surge-voltage. Bypass capacitors such as C11, C2<br>and C3 should have good high-frequency characteristics to absorb high-frequency ripple-current. 3 should have good high-frequency characteristics to absorb high-frequency ripple-current. should have good high-frequency characteristics to absorb high-frequency ripple-current.<br>ARATARALARERARAAURORORARERORORE,<br>a, uo<br>MOSFET Case Temperature(Tc)<br>Detecting Point<br>Figure 5. Case Temperature Measurement<br>Notes:<br>12. Attach the thermocouple on top of the heat-sink of SPM 5 package (between SPM 5 package and heatsink if applied) to get the correct temperature measurement.<br>3.5<br>3.0<br>Pf | ft<br>2.5<br>2.0<br>1.5<br>1.0<br>0.5<br>20 40 60 80 100 120 140 160<br>THVIC [oC]<br>MCU<br>[V]<br>TS<br>V<br>**----- End of picture text -----**<br> - 10.RC-coupling (R5 and C5) and C4 at each input of Motion SPM 5 product and MCU (Indicated as Dotted Lines) may be used to prevent improper signal due to surge-noise. 5 and C5) and C4 at each input of Motion SPM 5 product and MCU (Indicated as Dotted Lines) may be used to prevent improper signal due to surge-noise. and C5) and C4 at each input of Motion SPM 5 product and MCU (Indicated as Dotted Lines) may be used to prevent improper signal due to surge-noise. 5) and C4 at each input of Motion SPM 5 product and MCU (Indicated as Dotted Lines) may be used to prevent improper signal due to surge-noise. ) and C4 at each input of Motion SPM 5 product and MCU (Indicated as Dotted Lines) may be used to prevent improper signal due to surge-noise. 4 at each input of Motion SPM 5 product and MCU (Indicated as Dotted Lines) may be used to prevent improper signal due to surge-noise. at each input of Motion SPM 5 product and MCU (Indicated as Dotted Lines) may be used to prevent improper signal due to surge-noise. 11. Bold lines should be short and thick in PCB pattern to have small stray inductance of circuit, which results in the reduction of surge-voltage. Bypass capacitors such as C11, C2 and C3 should have good high-frequency characteristics to absorb high-frequency ripple-current. 3 should have good high-frequency characteristics to absorb high-frequency ripple-current. should have good high-frequency characteristics to absorb high-frequency ripple-current. **Figure 6. Temperature Profile of VTS (Typical)** Semiconductor Components Industries, LLC, 2017 www.fairchildsemi.com FSB50550B / FSB50550BS **[.]** Rev. 1.2 www.onsemi.com **6** **==> picture [373 x 302] intentionally omitted <==** **----- Start of picture text -----**<br> VIN VIN<br>Irr<br>100% of ID 120% of ID<br>VDS ID<br>10% of ID<br>ID VDS<br>tON trr tOFF<br>(a) Turn-on (b) Turn-off<br>Figure 7. Switching Time Definitions<br>CBS<br>VDD ID<br>VDD VB<br>HIN HO L VDC<br>LIN VS<br>+<br>COM LO V DS<br>VTS -<br>One Leg Diagram of Motion SPM [®] 5 Product<br>**----- End of picture text -----**<br> **Figure 8. Switching and RBSOA (Single-Pulse) Test Circuit (Low-side)** **==> picture [313 x 287] intentionally omitted <==** **----- Start of picture text -----**<br> Input Signal<br>UV Protection<br>RESET SET RESET<br>Status<br>UVDDR<br>Low- side Supply, VDD<br>UVDDD<br>MOSFET Current<br>Figure 9. Under-Voltage Protection (Low-Side)<br>Input Signal<br>UV Protection<br>RESET SET RESET<br>Status<br>UVBSR<br>High- side Supply, VBS<br>UVBSD<br>MOSFET Current<br>**----- End of picture text -----**<br> **Figure 10. Under-Voltage Protection (High-Side)** Semiconductor Components Industries, LLC, 2017 www.fairchildsemi.com FSB50550B / FSB50550BS **[.]** Rev. 1.2 www.onsemi.com **7** **==> picture [467 x 357] intentionally omitted <==** **----- Start of picture text -----**<br> C1<br>(1) COM<br>(2) VB(U) (17) P<br>(3) VDD(U)<br>VDD VB<br>R5 (4) IN(UH)<br>(5) IN(UL) HINLIN HOVS (18) U, VS(U) C3 VDC<br>C5 C2 COM LO<br>(6) N.C<br>(19) NU<br>(7) VB(V)<br>(8) VDD(V) (20) NV<br>VDD VB<br>(9) IN(VH)<br>HIN HO<br>(10) IN(VL) (21) V, VS(V)<br>LIN VS M<br>COM LO<br>(11) VTS<br>VTS<br>(12) VB(W)<br>(13) VDD(W) (22) NW<br>VDD VB<br>(14) IN(WH)<br>HIN HO<br>(15) IN(WL) (23) W, VS(W)<br>LIN VS<br>COM LO<br>(16) N.C<br>C4<br>For current-sensing and protection R4<br>15 V<br>Supply C6 R3<br>Micom<br>**----- End of picture text -----**<br> ## **Figure 11. Example of Application Circuit** ## **Notes:** 13. About pin position, refer to Figure 1. 14. RC-coupling (R5 and C5, R4 and C6) and C4 at each input of Motion SPM[®] 5 product and MCU are useful to prevent improper input signal caused by surge-noise. 15. The voltage-drop across R3 affects the low-side switching performance and the bootstrap characteristics since it is placed between COM and the source terminal of the lowside MOSFET. For this reason, the voltage-drop across R3 should be less than 1 V in the steady-state. 16. Ground-wires and output terminals, should be thick and short in order to avoid surge-voltage and malfunction of HVIC. 17. All the filter capacitors should be connected close to Motion SPM 5 product, and they should have good characteristics for rejecting high-frequency ripple current. Semiconductor Components Industries, LLC, 2017 www.fairchildsemi.com FSB50550B / FSB50550BS **[.]** Rev. 1.2 www.onsemi.com **8** ## **Detailed Package Outline Drawings ( FSB50550B )** **==> picture [357 x 317] intentionally omitted <==** **----- Start of picture text -----**<br> Max 1.00<br>0.50?0.10 16X<br>(0.20) 13X<br>(1.165) 15X1.778=26.67 [?0.30] (1.165)<br>(1.80)<br>13.34 [?0.30] 13.34 [?0.30]<br>(1.00)<br>1 16<br>17 23<br>3.15?0.20<br>(2.275) 12.23 [?0.30] 13.13 [?0.30] (1.375)<br>(6.05)<br>29.00?0.20<br>(R0.40)<br>2?~6?<br>0.450.60<br>?0.20 ?0.30<br>14.00<br>12.00 14.55<br>**----- End of picture text -----**<br> **==> picture [216 x 129] intentionally omitted <==** **----- Start of picture text -----**<br> 1.95?0.30<br>3.90 [?0.30] 2X 2.48 [?0.30] 3.90 [?0.30] 4X<br>17 19 23<br>(0.30)<br>0.60 [?0.10] 5X 0.50 [?0.10] 2X<br>PIN19,20<br>Max 1.00<br>(0.17)<br>?0.50<br>2.95<br>**----- End of picture text -----**<br> NOTES: UNLESS OTHERWISE SPECIFIED A) THIS PACKAGE DOES NOT COMPLY TO ANY CURRENT PACKAGING STANDARD B) ALL DIMENSIONS ARE IN MILLIMETERS C) DIMENSIONS ARE EXCLUSIVE OF BURRS, MOLD FLASH, AND TIE BAR EXTRUSIONS D) ( ) IS REFERENCE E) [ ] IS ASS'Y QUALITY F) DRAWING FILENAME: MOD23DCREV4.0 G) FAIRCHILD SEMICONDUCTOR **==> picture [77 x 42] intentionally omitted <==** Semiconductor Components Industries, LLC, 2017 www.fairchildsemi.com FSB50550B / FSB50550BS **[.]** Rev. 1.2 www.onsemi.com **9** ## **Detailed Package Outline Drawings ( FSB50550BS )** **==> picture [458 x 563] intentionally omitted <==** **----- Start of picture text -----**<br> Max 1.00<br>0.60 [?0.10] 16X<br>(1.165) 15X1.778=26.67 [?0.30] (1.165)<br>(1.80)<br>13.34 [?0.30] 13.34 [?0.30] (1.00)<br>1 16<br>(2.50)<br>GAGE PLANE<br>1.50 [?0.20]<br>17 23 SEATING PLANE<br>(1.30)<br>(2.275) 12.23?0.30 13.13?0.30 (1.375)<br>3.15?0.20<br>29.00 [?0.20]<br>1.95?0.30 1.778 15X 0.889<br>1 16<br>3.90 [?0.30] 2X 2.48 [?0.30] 3.90 [?0.30] 4X<br>1.3<br>17 19 23<br>0.60?0.10 5X 0.50?0.10 2X<br>Max 1.00 PIN19,20 3.90 2X 3.90 4X<br>NOTES: UNLESS OTHERWISE SPECIFIED<br> A) THIS PACKAGE DOES NOT COMPLY 17 23<br> TO ANY CURRENT PACKAGING STANDARD 1.95<br> B) ALL DIMENSIONS ARE IN MILLIMETERS<br>2.475<br> C) DIMENSIONS ARE EXCLUSIVE OF BURRS,<br> MOLD FLASH, AND TIE BAR EXTRUSIONS<br>LAND PATTERN RECOMMENDATIONS<br> D) ( ) IS REFERENCE<br> E) DRAWING FILENAME: MOD23DGREV6.0<br> F) FAIRCHILD SEMICONDUCTOR<br>0.60<br>0.45<br>2~8?<br>(R0.40) 0.508<br>?0.20 ?0.20 Max 3.50<br>12.00 17.00<br>0.30 0.05<br>2.80<br>7.55<br>7.55<br>**----- End of picture text -----**<br> Semiconductor Components Industries, LLC, 2017 www.fairchildsemi.com FSB50550B / FSB50550BS **[.]** Rev. 1.2 www.onsemi.com **10** ON Semiconductor and the ON Semiconductor logo are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. 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"Typical" parameters which may be provided in ON Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. 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ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. ## **PUBLICATION ORDERING INFORMATION** **N. American Technical Support** : 800−282−9855 Toll Free **ON Semiconductor Website** : **www.onsemi.com** USA/Canada ## **LITERATURE FULFILLMENT** : Literature Distribution Center for ON Semiconductor **Order Literature** : http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative 19521 E. 32nd Pkwy, Aurora, Colorado 80011 USA **Europe, Middle East and Africa Technical Support: Phone** : 303−675−2175 or 800−344−3860 Toll Free USA/Canada Phone: 421 33 790 2910 **Fax** : 303−675−2176 or 800−344−3867 Toll Free USA/Canada **Japan Customer Focus Center Email** : orderlit@onsemi.com Phone: 81−3−5817−1050 © Semiconductor Components Industries, LLC www.onsemi.com **www.onsemi.com** **1**
Updated at April 27, 2026
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