FS1603A-3300-AL

**FS1603A POL[™] µ** 

## **3A Rated µPOL[™]** DC-DC Converter with Integrated Inductor, Telemetry and Digital Power System Management 

## **Features** 

- µPOL™ package with output inductor included 

- Small size: 3.3mm x 3.3mm x 1.35mm 

- Continuous 3A load capability 

- Plug and play: no external compensation required 

- Programmable operation using the I[2] C serial bus 

- Voltage, current and temperature telemetry 

- Operating temperature from -40°C to +125°C 

- Wide input voltage range: 4.5V–16V 

- Preset output voltage: 3.3V or 5.0V 

- Enable input with precise threshold 

- Programmable under-voltage lock-out (UVLO) 

- Open-drain power-good indicator 

- Built-in protection features 

- Servo loop for high-precision VOUT regulation 

- Offers eight I[2] C addresses 

- Lead-free and halogen-free 

## **Applications** 

- Telecom and networking applications 

- Data center applications 

- 5G, AI applications 

- Industrial applications 

- Storage applications 

- Distributed point-of-load power architectures 

## **Description** 

The FS1603A is an easy-to-use, fully integrated and highly efficient micro-point-of-load (µPOL™) voltage regulator. The on-chip pulse-width modulation (PWM) controller and integrated MOSFETs, plus incorporated inductor and capacitors, result in an extremely compact and accurate regulator. The low-profile package is suitable for automated assembly using standard surface-mount equipment. 

Developed by a cross-functional engineering team, the design exemplifies best practice and uses class-leading technologies. From early in the integrated circuit design phase, designers worked with application and packaging engineers to select compatible technologies and implement them in ways that reduce compromise. The ability to program aspects of the FS1603A’s operation using the InterIntegrated Circuit (I[2] C) protocol is unique in this class of product. Developing and optimizing all these elements together has yielded the smallest, most efficient, and fully featured 3A µPOL™ currently available. 

The built-in protection features include pre-biased start-up, soft-start protection, over-voltage protection, thermally compensated over-current protection with hiccup mode, thermal shut-down with auto-recovery. 

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PVIN PVIN VOUT VOUT <22:53.0<br>VIN 2<br>= 3 2.0<br>me]<br>SDA Fb :oO° 1.5<br>SCL Ss —12V to 5.0V,<br>ADDRPG PGnd E=oO 0.51.0 no airflow<br>AGnd<br>S En a<br>**----- End of picture text -----**<br>


**Rev 1.0, May 14, 2025** 

**Page 1** Patent Protected: US 9,729,059 B1; US 10,193,442 B2 Copyright© 2024–25  TDK Corporation. All rights reserved. All registered trademarks and trademarks are the property of their respective owners. Lead Halogen Data and specifications subject to change without notice. 

**FS1603A POL[™] µ** ~~ee~~ 

## **Pin Configuration** 

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1 15 14 13<br>ra eT<br>cl 3 i<br>2 -= 16 oo 17 12 7<br>=a enng ee<br>3 11<br>ry p ul 07<br>4 10<br>3) L— oo<br>5 9<br>PJ eee<br>si<br>en<br>6 7 8<br>TT |<br>**----- End of picture text -----**<br>


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13 14 15 1<br>Cr 10<br>12 2<br>17 16<br>=<br>11 3<br>C _<br>10 4<br>= =<br>9 5<br>= a<br>8 7 6<br>ne<br>**----- End of picture text -----**<br>


_**Pin layout (top view)**_ 

Figure 2 _**Pin layout (bottom view)**_ 

## **Pin Functions** 

|1<br>SDA<br>**I**2**C Data Serial Input/Output line.**Pull up to bus voltage with a 4.99kΩ resistor. If unused, connect<br>to AGnd.|1<br>SDA<br>**I**2**C Data Serial Input/Output line.**Pull up to bus voltage with a 4.99kΩ resistor. If unused, connect<br>to AGnd.|1<br>SDA<br>**I**2**C Data Serial Input/Output line.**Pull up to bus voltage with a 4.99kΩ resistor. If unused, connect<br>to AGnd.|
|---|---|---|
|2<br>PG<br>**Power Good status.**Open drain of an internal MOSFET.<br>Pull upto VCC (pin 10)or an external bias voltage,with a 49.9kΩ resistor(Figure 7).|||
|3<br>En<br>**Enable.**Switches the FS1603A on and off. Can be used with two external resistors to set an external<br>UVLO(Figure 6).|||
|4<br>SCL<br>**I2C Clock line.**Pull upto bus voltage with a 4.99kΩ resistor. If unused,tie to AGnd.|||
|5<br>Fb<br>**Feedback.**Connect directlyto VOUT on the application board.|||
|6<br>ADDR<br>**Address.**Connect to AGnd through a resistor to program FS1603A address (see ‘I2C Base Address<br>and Offsets’ on page 15 and ‘Switching Frequency and Minimum Values for On-time, Off-time and<br>PVIN’ onpage 15). Maybe shorted to AGnd or left open if I2C communication is not used.|||
|7<br>VOUT<br>**Regulator output voltage.**Place output capacitors between thispin and PGnd(pins 8 and 16).|||
|8,16<br>PGnd<br>**Powerground.**Serves as a separateground for the MOSFETs. Connect to thepowergroundplane.|||
|9<br>AGnd<br>**Signal ground.**Serves as the ground for the internal reference and control circuitry. Connect to<br>pin 8 and also to thepowergroundplane through vias.|||
|10<br>VCC<br>**Supply voltage.**Output of the internal LDO regulator. It may also be used to apply an external VCC<br>voltage – when used in this way,connect VINto VCC.|||
|11<br>VIN<br>**Input voltage.**Input for the internal LDO regulator. For single supply applications, connect to PVIN<br>usinga 2.7Ω resistor. When usinga separate VCC,connect VINto VCC.|||
|12,13,14,17 PVIN<br>**Power input voltage.**Input for the MOSFETs.|||
|15|VSW|**Testpoint for internal V**SW**.**Connect to an isolatedpad on the PCB.|



**Page 2** 

**Rev 1.0, May 14, 2025** 

Patent Protected: US 9,729,059 B1; US 10,193,442 B2 Copyright© 2024–25  TDK Corporation. All rights reserved. All registered trademarks and trademarks are the property of their respective owners. Data and specifications subject to change without notice. 

**FS1603A POL[™] µ** ~~ee~~ 

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Block Diagram<br>VIN VCC<br>AGnd<br>Low Drop-Out<br>fault (LDO)<br>Internal Reference VOUT PVIN Regulator<br>(Digital-to-Analog VCC<br>Converter (DAC))<br>Pulse Generator<br>Fb for Pulse Width PWM PVIN<br>Soft signal<br>Modulation (PWM) HDrv<br>SDA I [2] C + Start SS Gate Drive<br>signal<br>SCL Memory Logic and L<br>ADDR Gen, Address OTP faultshut-downthermal VCC HDrvfault DeadtimeControl LDrv VCC VOUT<br>Detector<br>adjustment/margining<br>Control PGnd<br>En<br>and Fault<br>PG Logic Telemetry<br>(PVIN, Fb, VOUT, IOUT,<br>address,temperature) temperature sense<br>= power-on reset<br>**----- End of picture text -----**<br>


_**FS1603A µPOL™**_ 

## **Typical Applications** 

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12V VOUT 12V VOUT<br>PVIN VOUT PVIN VOUT<br>VIN VIN<br>V<br>CC<br>SDA Fb 5V SDA Fb<br>SCL SCL<br>ADDR ADDR<br>PGnd PGnd<br>PG PG<br>En AGnd En AGnd<br>**----- End of picture text -----**<br>


_**Single supply applications circuit**_ 

_**Dual supply applications circuit**_ 

**Page 3** 

**Rev 1.0, May 14, 2025** 

Patent Protected: US 9,729,059 B1; US 10,193,442 B2 Copyright© 2024–25  TDK Corporation. All rights reserved. All registered trademarks and trademarks are the property of their respective owners. Data and specifications subject to change without notice. 

**FS1603A POL[™] µ** 

## **Absolute Maximum Ratings** 

**Warning:** Stresses beyond those shown may cause permanent damage to the FS1603A. 

**Note:** Functional operation of the FS1603A is not implied under these or any other conditions beyond those stated in the FS1603A specification. 

|**Reference**|**Range **|
|---|---|
|PVIN,VIN,En to PGnd|-0.3V to 18V(Note 1, page 9)|
|VCCto PGnd|-0.3V to 6V(Note 2, page 9)|
|Fb to AGnd|-0.3V to VCC(Note 2, page 9)|
|PG to AGnd|-0.3V to VCC(Note 2, page 9)|
|PGnd to AGnd|-0.3V to +0.3V|
|ESD Classification|2kV(HBM JESD22-A114)|
|Moisture SensitivityLevel|MSL 3(JEDEC J-STD-020)|



**Thermal Information Range** Junction-to-Ambient Thermal Resistance ƟJA 22.6°C/W Junction to PCB Thermal Resistance Ɵ J-c (bottom) 2.36°C/W Storage Temperature Range -55°C to 150°C Junction Temperature Range -40°C to 150°C Note: ƟJA : FS1603A evaluation board and JEDEC specifications JESD 51-2A ƟJ-c (bottom) : JEDEC specification JESD 51-8 ~~a~~ 

**Page 4** 

**Rev 1.0, May 14, 2025** 

Patent Protected: US 9,729,059 B1; US 10,193,442 B2 Copyright© 2024–25  TDK Corporation. All rights reserved. All registered trademarks and trademarks are the property of their respective owners. Data and specifications subject to change without notice. 

**FS1603A POL[™] µ** ~~ee~~ 

## **Order Information** 

## **Package Details** 

The FS1603A uses a µPOL™ 3.3 mm x 3.3 mm package delivered in tape-and-reel format (page 27). For more information on the tape-and-reel specification, go to: 

- - https://product.tdk.com/en/products/power/switching power/micro pol/designtool.html 

## **Standard Part Numbers** 

Output voltages of 3.3V and 5.0V are available. 

|**Part Number**|**VOUT (V)**|**Quantity per Reel**|**Package Description***|**Package Designator**|
|---|---|---|---|---|
|FS1603A-3300-AL|3.3|3,000|17L Open Top LGA SiP|A01|
|FS1603A-5000-AL|5.0|3,000|17L Open Top LGA SiP|A01|



- Compliant with EU Directives REACH and RoHS. RoHS is defined as semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances. 

## **Package Markings** 

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FS1603A<br>Product  Marking Code (Z)<br>ae a ee<br>FS1603A-3300  K<br>FS1603A-5000  S<br>oo<br>Z:  VOUT<br>XXXXXX:  Assembly Lot Code<br>**----- End of picture text -----**<br>


**Page 5** 

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 Rev 1.0, May 14, 2025<br>**----- End of picture text -----**<br>


Patent Protected: US 9,729,059 B1; US 10,193,442 B2 Copyright© 2024–25  TDK Corporation. All rights reserved. All registered trademarks and trademarks are the property of their respective owners. Data and specifications subject to change without notice. 

**FS1603A POL[™] µ** 

## **Recommended Operating Conditions** 

## **3.3V Output Voltage** 

|**Definition**<br>**Symbol**<br>**Min**<br>**Max**<br>**Units**<br>Input Voltage Range with External VCC (Note 3, Note 5)<br>PVIN<br>4.5<br>16<br>V<br>Input Voltage Range with Internal LDO(Note 4, Note 5)<br>PVIN, VIN<br>4.5<br>16<br>SupplyVoltage Range (Note 2)<br>VCC<br>4.5<br>5.5<br>Continuous Output Current Range<br>IO<br>0<br>3<br>A<br>OperatingJunction Temperature<br>TJ<br>-40<br>125<br>°C<br>~~sees~~|
|---|
|**5.0V Output Voltage**|
|**Definition**<br>**Symbol**<br>**Min**<br>**Max**<br>**Units**<br>Input Voltage Range(Note 3, Note 4 and Note 5)<br>PVIN<br>6.75<br>16<br>V<br>SupplyVoltage Range(Note 2)<br>VCC<br>4.5<br>5.5<br>Continuous Output Current Range<br>IO<br>0<br>3<br>A<br>OperatingJunction Temperature<br>TJ<br>-40<br>125<br>°C<br>~~ss~~|
|**Electrical Characteristics**<br>**ELECTRICAL CHARACTERISTICS**<br>**Unless otherwise stated, these specifications apply over: 4.5V < PVIN = VIN < 16V, 0°C < TJ < 125°C**<br>**Typical values are specified at TA = 25°C**<br>**Parameter**<br>**Symbol**<br>**Conditions**<br>**Min**<br>**Typ**<br>**Max**<br>**Unit**<br>**Supply Current**<br>VINSupplyCurrent(Standby)<br>IIN(STANDBY)<br>Enable low<br>2.1<br>mA<br>VINSupplyCurrent(Static)<br>IIN(STATIC)<br>No switching,En = 2V<br>3.6<br>VINSupply Current (Dynamic)<br>IIN (DYN)<br>En high, VIN= PVIN= 12V,<br>VOUT= 5.0V,FSW= 1.4MHz<br>15.8 18.6<br>**Soft-Start**<br>Soft-Start Rate<br>SSRATE(default)<br>(Note 7)<br>1<br>V/ms<br>**Output Voltage **<br>Output Voltage Range<br>VOUT (default)<br>5<br>V<br>V(resolution)<br>10<br>mV<br>Accuracy<br>TJ= 25°C, PVIN= 12V, VOUT= 5.0V<br>(Note 4)<br>±0.5<br>%<br>25°C < TJ< 125°C, PVIN= 12V,<br>VOUT= 3.3V(Note 4)<br>-1<br>1<br>25°C < TJ< 125°C, PVIN= 12V,<br>VOUT= 5.0V(Note 4)<br>-1<br>1<br>~~ain~~|
|**Page 6**<br>**Rev 1.0, May 14, 2025**|
|Patent Protected: US 9,729,059 B1; US 10,193,442 B2|
|Copyright© 2024–25  TDK Corporation. All rights reserved.|
|All registered trademarks and trademarks are the property of their respective owners.|
|Data and specifications subject to change without notice.|



**FS1603A POL[™] µ** ~~ee~~ 

|**ELECTRICAL CHARACTERISTICS**<br>**Unless otherwise stated, these specifications apply over: 4.5V < PVIN = VIN < 16V, 0°C < TJ < 125°C**<br>**Typical values are specified at TA = 25°C**<br>**Parameter**<br>**Symbol**<br>**Conditions**<br>**Min**<br>**Typ**<br>**Max**<br>**Unit**<br>**On-Time Timer Control**<br>~~a~~<br>~~ee~~<br>~~ee~~|
|---|
|On Time<br>TON<br>PVIN= 12V, VOUT= 5.0V, FSW=1.4<br>MHz<br>275 305<br>330<br>ns<br>Minimum On-Time<br>TON(MIN)<br>(Note 7)<br>30<br>~~pf~~<br>~~Ce~~|
|Minimum Off-Time<br>TOFF(MIN)<br>120<br>150<br>~~fe~~|
|**Internal Low Drop-Out(LDO) Regulator**<br>LDO Regulator Output Voltage<br>VCC<br>5.5V < VIN= 16V,0 – 20mA<br>4.9 5.2<br>5.5<br>V<br>4.5V ≤ VIN< 5.5V,0 – 20mA<br>4.3<br>**Thermal Shut-Down**<br>~~a~~<br>~~ee~~<br>~~ee ne~~<br>~~a~~|
|Thermal Shut-Down<br>TSD(default)<br>(Note 7)<br>145<br>°C<br>Hysteresis<br>25<br>~~nn~~<br>~~fe~~|
|**Under-Voltage Lock-Out**<br>VCCStart Threshold<br>VCC_UVLO(START)<br>VCCRisingTripLevel<br>3.95 4.15 4.35<br>V<br>VCCStopThreshold<br>VCC_UVLO(STOP)<br>VCCFallingTripLevel<br>3.6 3.8<br>3.95<br>Enable Threshold<br>En(HIGH)<br>RampingUp<br>1.1<br>1.2<br>1.3<br>En(LOW)<br>RampingDown<br>0.9 1<br>1.06<br>Input Impedance<br>REN<br>500 1000 1500<br>kΩ<br>~~a~~<br>~~RG~~<br>~~eG~~<br>~~eeGe~~<br>~~Df~~|
|**Current Limit**<br>~~a~~|
|Current Limit Threshold<br>IOC (default)<br>TJ= 25°C<br>3.6 4<br>4.3<br>A<br>~~a~~|
|HiccupBlankingTime<br>TBLK(HICCUP)<br>20<br>ms<br>~~Df~~|
|**Over-Voltage Protection**<br>~~a~~|
|Output Over-Voltage Protection<br>Threshold<br>VOVP(default)<br>OVP Detect (Note 7)<br>115 120<br>125<br>Fb%<br>~~ee~~|
|Output Over-voltage Protection Delay TOVPDEL<br>5<br>µs<br>~~fe~~|
|**Power Good(PG)**<br>Power Good Upper Threshold<br>VPG(UPPER) (default)<br>VOUTRising<br>85<br>90<br>95<br>Fb%<br>Power Good Hysteresis<br>VPG(LOWER)<br>VOUT Falling<br>5<br>Power Good Sink Current<br>IPG<br>PG = 0.5V,En = 2V<br>9<br>mA<br>~~a~~<br>~~**e**s~~<br>~~ns Ee~~<br>~~ee~~<br>~~G~~<br>~~eG~~|
|**Telemetry**<br>~~Ce~~|
|Input voltage reporting accuracy<br>PVIN_report_pc<br>PVIN= 12V,TJ = 25°C<br>-0.8<br>0.8<br>%<br>6.75V < PVIN< 16V, -40°C <<br>TJ< 125°C(Note 6)<br>-1.5 <br>1.5<br>%<br>Output voltage reporting accuracy<br>VOUT_report_pc<br>VOUT= VFB= 3.3V, -40°C < TJ<125°C<br>(Note 6)<br>-2<br>2<br>%<br>VOUT= VFB=5.0 V, -40°C < TJ<125°C<br>(Note 6)<br>-2<br>2<br>%<br>Output current reporting accuracy<br>IOUT_report_acc<br>PVIN= 12V, TJ= 25°C, VOUT=<br>3.3V,5.0V,IOUT=0 A<br>0<br>550<br>mA<br>PVIN= 12V, -40°C < TJ<125°C,<br>VOUT= 3.3V,5.0V,IOUT= 0A(Note 6) 0<br>650<br>mA<br>Temperature reportingaccuracy<br>T_report_acc<br>-40°C < TJ<125°C(Note 7)<br>-10<br>10<br>°C<br>~~e~~~~**e**~~<br>~~e~~<br>~~ee~~<br>~~a~~<br>~~ee eee~~<br>~~ee~~<br>~~ee~~<br>~~a~~<br>~~ee eee~~<br>~~ee~~<br>~~ee~~<br>~~fe~~|



**Rev 1.0, May 14, 2025** 

**Page 7** 

Patent Protected: US 9,729,059 B1; US 10,193,442 B2 Copyright© 2024–25  TDK Corporation. All rights reserved. All registered trademarks and trademarks are the property of their respective owners. Data and specifications subject to change without notice. 

**FS1603A POL[™] µ** ~~ee~~ 

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||||||||||
|---|---|---|---|---|---|---|---|---|
|ELECTRICAL CHARACTERISTICS|
|Pe|
|Unless otherwise stated, these specifications apply over: 4.5V < PVIN = VIN < 16V, 0°C < T < 125°C|
|ee|Typical values are specified at TA = 25°C|
|eG|Parameter|Symbol|Conditions|Fast-mode|Fast-mode Plus|
|(Note 7 for all|Unit|
|I|[2]|C parameters|Min|Max|Min|Max|
|i|parameters)|
|I|[2]|C bus voltage|VBUS|1.8|5.5|1.8|5.5|
|————_———|LOW-level input voltage|VIL|−0.5|0.3VBUS|−0.5|0.3VBUS|
|HIGH-level input voltage|VIH|0.7VBUS|0.7VBUS|
|Hysteresis|VHYS|0.05VBUS|0.05VBUS|
|———|(open-drain or open-|—_——|V|
|LOW-level output voltage 1|VOL1|collector) at 3mA sink|0|0.4|0|0.4|
|current; VDD > 2 V,|
|(open-drain or open-|
|LOW-level output voltage 2|VOL2|collector) at 2mA sink|0|0.2VBUS|0|0.2VBUS|
|SSS|current; VDD ≤ 2 V,|
|a|VOL = 0.4 V,|ee|3|-|eee|3|-|
|LOW-level output current|IOL|mA|
|————$_—_—|VOL = 0.6 V|6|-|6|-|
|20 × (VBUS/5.5|
|Output fall time|TOF|From VIHmin to VILmax|20 × (VBUS/5.5 V)|250|125|
|Sn|V)|
|Pulse width of spikes that|ns|
|must be suppressed by the|TSP|0|50|0|50|
|input filter|
|eee|Input current each I/O pin|II|−10|10|−10|10|μA|
|Capacitance for each I/O pin|CI|-|10|-|10|pF|
|——————|SCL clock frequency|FSCL|0|400|0|1000|kHz|
|Hold time (repeated) START|After this time, the first|
|a|condition|THD;STA|clock pulse is generated|0.6|-|0.26|-|
|LOW period of the SCL clock|TLOW|1.3|-|0.5|-|
|HIGH period of the SCL clock|THIGH|0.6|-|0.26|-|μs|
|——|Set-up time for a repeated|———|
|a|START condition|TSU;STA|0.6|-|0.26|-|
|Data hold time|THD;DAT|I|[2]|C-bus devices|0|-|0|-|
|Data set-up time|TSU;DAT|100|-|50|-|
|———|Rise time of SDA and SCL|—_——|
|TR|20|300|-|120|
|ee|signals|ns|
|Fall time of SDA and SCL|
|TF|20 × (VDD/5.5 V)|300|20 × (VDD/5.5 V)|120|
|a|signals|
|Set-up time for STOP|
|a|condition|TSU;STO|ee|0.6|-|0.26|-|
|μs|
|Bus free time between a|
|a|STOP and START condition|TBUF|1.3|-|0.5|-|
|Page 8|Rev 1.0, May 14, 2025|
|Patent Protected: US 9,729,059 B1; US 10,193,442 B2|
|Copyright© 2024–25  TDK Corporation. All rights reserved.|

**----- End of picture text -----**<br>


All registered trademarks and trademarks are the property of their respective owners. Data and specifications subject to change without notice. 

**FS1603A POL[™] µ** ~~ee~~ 

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ELECTRICAL CHARACTERISTICS<br>a<br>Unless otherwise stated, these specifications apply over: 4.5V < PVIN = VIN < 16V, 0°C < T < 125°C<br>> Typical values are specified at TA = 25°C<br>Parameter  Symbol Conditions  Fast-mode  Fast-mode Plus<br>(Note 7 for all  Unit<br>I [2] C parameters  Min  Max  Min  Max<br>are p a arameters) re<br>Capacitive load for each bus<br>CB -  400  -  550  pF<br>line<br>LS Data valid time  TVD es ;DAT ee ee -  0.9  eee -  0.45<br>μs<br>aGe Data valid acknowledge time TVD;ACK -  0.9  -  0.45<br>Noise margin at the LOW<br>VNL For each connected  0.1VDD -  0.1VDD -<br>level<br>device, including  V<br>Noise margin at the HIGH<br>VNH hysteresis  0.2VDD -  0.2VDD -<br>level<br>PoGO SDA timeout  TTO ee 200   ee 200  μs<br>**----- End of picture text -----**<br>


## **Notes** 

- 1 PGnd pin and AGnd pin are connected together 

- 2  Must not exceed 6V 

- 3 VIN is connected to VCC to bypass the internal Low Drop-Out (LDO) regulator 

- 4 VIN is connected to PVIN (for single-rail applications with PVIN = VIN = 4.5V–16V) 

- 5 Maximum switch node voltage should not exceed 22V 

- 6 Hot and cold temperature performance is assured by correlation using statistical quality control, but not tested in production; performance at 25°C is tested and guaranteed in production environment 

- 7  Guaranteed by design but not tested in production 

**Page 9** 

**Rev 1.0, May 14, 2025** 

Patent Protected: US 9,729,059 B1; US 10,193,442 B2 Copyright© 2024–25  TDK Corporation. All rights reserved. All registered trademarks and trademarks are the property of their respective owners. Data and specifications subject to change without notice. 

**FS1603A POL[™] µ** 

## **Temperature Characteristics** 

## **Output Voltage** 

## **VIN Supply Current (Dynamic)** 

## **Enable Start Threshold** 

## **Enable Stop Threshold** 

## **Page 10** 

## **Rev 1.0, May 14, 2025** 

Patent Protected: US 9,729,059 B1; US 10,193,442 B2 Copyright© 2024–25  TDK Corporation. All rights reserved. All registered trademarks and trademarks are the property of their respective owners. Data and specifications subject to change without notice. 

## **FS1603A POL[™] µ** 

## **VCC Start Threshold** 

## **On Time** 

## **Soft-Start Rate** 

**Page 11** 

## **VCC Stop Threshold** 

## **Switching Frequency** 

## **Current Limit Threshold** 

## **Rev 1.0, May 14, 2025** 

Patent Protected: US 9,729,059 B1; US 10,193,442 B2 Copyright© 2024–25  TDK Corporation. All rights reserved. All registered trademarks and trademarks are the property of their respective owners. Data and specifications subject to change without notice. 

**FS1603A POL[™] µ** ~~|~~ 

## **Efficiency Characteristics** 

## **Typical efficiency and power loss at PVIN = 12V** 

PVIN = 12V, Internal LDO used, IOUT = 0A–3A, room temperature, no air flow, all losses included 

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95<br>90<br>85<br>5V<br>80<br>75<br>0.0 0.5 1.0 1.5 2.0 2.5 3.0<br>IOUT (A)<br>1.2<br>0.9<br>0.6<br>5V<br>0.3<br>0.0<br>0.0 0.5 1.0 1.5 2.0 2.5 3.0<br>IOUT (A)<br>Efficiency (%)<br> (W)<br>LOSS<br>P<br>**----- End of picture text -----**<br>


**Page 12** 

**Rev 1.0, May 14, 2025** 

Patent Protected: US 9,729,059 B1; US 10,193,442 B2 Copyright© 2024–25  TDK Corporation. All rights reserved. All registered trademarks and trademarks are the property of their respective owners. Data and specifications subject to change without notice. 

**FS1603A POL[™] µ** ~~ee~~ 

## **Applications Information** 

## **Overview** 

The FS1603A is an easy-to-use, fully integrated, and highly efficient DC/DC regulator. Aspects of its operation, including output voltage and system optimization parameters, can be programmed using the I[2] C protocol. It uses a proprietary modulator to deliver fast transient responses. The modulator has internal stability compensation so that it can be used in a wide range of applications, with various types of output capacitors, without loop stability issues. An added servo loop ensures precise output voltage regulation. 

## **Bias Voltage** 

The FS1603A has an integrated Low Drop-Out (LDO) regulator, providing the DC bias voltage for the internal circuitry. The typical LDO regulator output voltage is 5.2V. For internally biased singlerail operation, the VIN pin should be connected to the PVIN pin (Figure 6). If an external bias voltage is used, the VIN pin should be connected to the VCC pin to bypass the internal LDO regulator (Figure 7). 

The supply voltage (internal or external) rises with VIN and does not need to be enabled using the En pin. Consequently, I[2] C communication can begin as soon as: 

- VCC_UVLO start threshold is exceeded 

- Memory contents are loaded 

- Initialization is complete 

- Address offset is read 

The I[2] C bus may be pulled up either to VCC or to a system I[2] C bus voltage. The FS1603A offers two ranges for the I[2] C bus voltage, defined by the user register bit **Bus_voltage_sel** . 

|0x1A|[1]|**Bus_voltage_sel**<br>0:1.8–2.5V (default),<br>1: 3.3–5.0V|
|---|---|---|



**==> picture [21 x 13] intentionally omitted <==**

**----- Start of picture text -----**<br>
PV<br>IN<br>**----- End of picture text -----**<br>


PV V IN IN R EN1 En **FS** 1603A 1603 R EN2 ~~Ta~~ _**Single supply configuration: internal LDO regulator, adjustable PVIN_UVLO**_ 

**==> picture [190 x 125] intentionally omitted <==**

**----- Start of picture text -----**<br>
PV Ext V<br>IN CC<br>PV V<br>IN IN<br>V<br>En CC<br>FS 1603A1603<br>(optional)<br>fH<br>**----- End of picture text -----**<br>


## _**Using an external bias voltage**_ 

**Rev 1.0, May 14, 2025** 

**Page 13** 

Patent Protected: US 9,729,059 B1; US 10,193,442 B2 Copyright© 2024–25  TDK Corporation. All rights reserved. All registered trademarks and trademarks are the property of their respective owners. Data and specifications subject to change without notice. 

**FS1603A POL[™] µ** ~~Fo~~ 

## **Soft-Start and Target Output Voltage** 

The FS1603A has an internal digital soft-start circuit to control output voltage rise-time and limit current surge at start-up. When VCC exceeds its start threshold (VCC_UVLO(START)), the FS1603A exits reset mode; this initiates loading of the contents of the non-volatile memory into the working registers and calculates the address offset as described above. 

Once initialization is complete and the Enable (En) pin has been asserted (Figure 8), the internal reference soft-starts to the target output voltage at the rate defined by the user register bit **SS_rate** . 

|**Register**<br>**Bits**<br>**Name/Description**|**Register**<br>**Bits**<br>**Name/Description**|**Register**<br>**Bits**<br>**Name/Description**|
|---|---|---|
|0x14|[3]|**SS_rate**<br>0: 1mV/µs (default),<br>1: 2mV/µs|



|**Register**<br>**Bits**<br>**Name/Description**|**Register**<br>**Bits**<br>**Name/Description**|**Register**<br>**Bits**<br>**Name/Description**|
|---|---|---|
|0x12<br>[0]<br>**Vout_high_byte**|||
|0x13|[7:0]|**Vout_low_byte**|



VOUT is set in 10mV increments. Use the following equation to calculate the VOUT code to enter into **Vout_high_byte** and **Vout_low_byte** [7:0]: 

**==> picture [188 x 32] intentionally omitted <==**

All voltages and resolutions are in Volts. 

## _For example:_ 

To set VOUT = 5.0V (resolution of 10mV): 

**==> picture [148 x 31] intentionally omitted <==**

420 is 1A4 in hexadecimal, therefore: 

**==> picture [107 x 10] intentionally omitted <==**

During initial start-up, the FS1603A operates with a minimum-width high-drive (HDrv) pulses until the output voltage increases (see ‘I[2] C Base Address and Offsets’ on page 15 and ‘Switching Frequency and Minimum Values for On-time, Off-time and PVIN’ on page 15). On-time is increased until VOUT reaches the target value defined by the user register bit **Vout_high_byte** and user register **Vout_low_byte** [7:0]. 

## En ~~JS~~ Initialization done 

**==> picture [188 x 74] intentionally omitted <==**

**----- Start of picture text -----**<br>
PG<br>V<br>OUT<br>0.9*V<br>OUT<br>V<br>OUT<br>SS-Time<br>**----- End of picture text -----**<br>


_**Theoretical operational waveforms during soft-start**_ 

Set **Vout_low_byte** to A4 or (10100100)b 

Over-current protection (OCP) and over-voltage protection (OVP) is enabled during soft-start to protect the FS1603A from short circuits and excess voltages respectively. 

For maximum system accuracy, the recommended way to set the output voltage is by programming the user registers with the appropriate code. For optimum performance when using this approach, the change in output voltage should not exceed ±20% of the pre-set default output voltage. 

## **Pre-biased Start-up** 

The FS1603A can start up into a pre-charged output smoothly, without causing oscillations and disturbances of the output voltage. When it starts up in this way, the Control and Synchronous MOSFETs are forced off until the internal Soft-Start (SS) signal exceeds the sensed output voltage at the Fb pin. Only then is the first gate signal of the Control MOSFET generated, followed by complementary turn on of the Synchronous MOSFET. The Power Good (PG) function is not active until this point. 

**Page 14** 

**Rev 1.0, May 14, 2025** 

Patent Protected: US 9,729,059 B1; US 10,193,442 B2 Copyright© 2024–25  TDK Corporation. All rights reserved. All registered trademarks and trademarks are the property of their respective owners. Data and specifications subject to change without notice. 

**FS1603A POL[™] µ** ~~ee~~ 

## **Shut-down Mechanisms** 

The FS1603A has two shut-down mechanisms: 

- _Hard shut-down or decay according to load_ Initiated by de-asserting the En pin. Both drivers switch off and the digital-toanalog converter (DAC) and soft-start are pulled down instantaneously. 

- _Soft-Stop or controlled ramp down_ Initiated by setting user register bit **SoftStopEnable** to 1 _**and**_ user register bit **SoftDisable** to 1. The SS signal falls to 0 at the same rate as it rises during start-up; the drivers are disabled only when it reaches 0. The output voltage then follows the SS signal down to 0. 

The **SoftDisable** bit must not be toggled while the part is enabled and switching. Instead, for applications requiring soft-stop, this bit must be set to 1 and, with the En pin asserted, the **SoftStopEnable** bit must be toggled to softstart or soft-stop the device. 

By default, both the **SoftDisable** bit and the **SoftStopEnable** bit are 0, which means that soft-stop operation is disabled by default. 

|**Register**<br>**Bits**<br>**Name/Description**|**Register**<br>**Bits**<br>**Name/Description**|**Register**<br>**Bits**<br>**Name/Description**|
|---|---|---|
|0x14<br>[2]<br>**SoftStopEnable**|||
|0x1C|[3]|**SoftDisable**|



## **I[2] C Base Address and Offsets** 

The FS1603A has a user register called **Base_address** [7:0] stored in memory that sets its base I[2] C address. The default base address is 0x08. An offset of 0 to 7 is then defined by connecting the ADDR pin to the AGnd pin either directly or through a resistor (1% or better). An address detector reads the resistance of the connection at startup and uses it to set the offset, which is added to the base I[2] C address to set the address at which the I[2] C master device will communicate with the FS1603A. 

To select offsets of 0 to 7, connect the pins as shown in Table 1. 

## _**Address Offset Resistance Values**_ 

|**Resistor(kΩ)**|**Addr Offset**|
|---|---|
|0*|**0**|
|10|**+1**|
|20|**+2**|
|30.1|**+3**|
|39|**+4**|
|47|**+5**|
|56<br>68|**+6**<br>**+7**|
|* Short ADDR to AGnd.||



## **Switching Frequency and Minimum Values for On-time, Off-time and PVIN** 

The switching frequency of the FS1603A depends on the output voltage. For an output voltage of 3.3V, the switching frequency is nominally 1.1MHz; for an output voltage of 5.0V, the switching frequency is nominally 1.4MHz. These are set at the factory. 

As a result, system designers need not concern themselves with selecting the switching frequency and have one fewer design task to manage. 

When input voltage is high relative to target output voltage, the Control MOSFET is switched on for shorter periods. The shortest period for which it can reliably be switched on is defined by minimum on-time (TON(MIN)) , nominally 30ns. During start-up, when the output voltage is very small, the FS1603A operates with minimum on-time. 

When input voltage is low relative to target output voltage, the Control MOSFET is switched on for longer periods. The shortest period for which it can be switched off is defined by minimum off-time (TOFF(MIN)), nominally 120ns. The Synchronous MOSFET stays on during this period and its current is detected for over-current protection. This dictates the minimum input voltage that can still allow the device to regulate its output at the target voltage. 

**Page 15** 

**Rev 1.0, May 14, 2025** 

Patent Protected: US 9,729,059 B1; US 10,193,442 B2 Copyright© 2024–25  TDK Corporation. All rights reserved. All registered trademarks and trademarks are the property of their respective owners. Data and specifications subject to change without notice. 

**FS1603A POL[™] µ** ~~ee~~ 

The minimum input voltage required for operation over the entire load range is 4.50V for 3.3V output and 6.75V for 5.0V output voltage. However, as these values are affected by both efficiency and dynamic load requirements, system designers should validate it in their own applications. 

PVIN = VIN = 12V 

**==> picture [469 x 529] intentionally omitted <==**

**----- Start of picture text -----**<br>
V<br>should validate it in their own applications.  CC<br>En threshold<br>0V<br>Enable (En) Pin  VCC _UVLO<br>7<br>The Enable (En) pin has several functions:  0V VOUT<br> It is used to switch the FS1603A on and off. It<br>0.9*V<br>has a precise threshold, which is internally  REF<br>monitored by the UVLO circuit. If it is left  a<br>0V<br>floating, an internal 1MΩ resistor pulls it down<br>to prevent the FS1603A being switched on  PG stays at logic low PG<br>0V<br>unintentionally.<br> It can be used to implement a precise input<br>voltage UVLO. The input of the En pin is  Start-up: PVIN, VIN tied together, En<br>derived from the PVIN voltage by a set of  connected to resistor divider from PVIN<br>resistive dividers, REN1 and REN2 (Figure 6).  PG pin pulled up to an external supply<br>Users can program the UVLO threshold voltage<br>PV  = V  = 12V<br>by selecting different ratios. This is a useful  IN IN<br>feature that stops the FS1603A regulating<br>when PVIN is lower than the desired voltage.<br> It can be used to monitor other rails for a<br>specific power sequencing scheme (Figure 9).  VCC _UVLO VCC<br>0V<br>PV<br>IN 0V A Initialization done ,<br>Rail #2<br>0V En > 1.2V<br>R PVIN VIN VOUT<br>EN1 0V<br>0.9*V<br>REF<br>0V<br>En PG<br>FS 1603A1603<br>0V<br>PG stays at logic low<br>R<br>EN2 e Start-up: En pin asserted after PV e IN and VIN,<br>PG pin pulled up to an external supply<br>i ———<br>En pin used to monitor other rails<br>for sequencing purposes<br>Page 16  Rev 1.0, May 14, 2025<br>**----- End of picture text -----**<br>


**Page 16** 

Patent Protected: US 9,729,059 B1; US 10,193,442 B2 Copyright© 2024–25  TDK Corporation. All rights reserved. All registered trademarks and trademarks are the property of their respective owners. Data and specifications subject to change without notice. 

**FS1603A POL[™] µ** ~~ee~~ 

For VOUT to start up as defined by the soft-start rate requires correct sequencing: 

- PVIN must start up before VCC and/or Enable. 

- PVIN must ramp down only after VCC has ramped down below its UVLO threshold and/or Enable has been de-asserted. 

## **Over-current Protection (OCP)** 

Over-current protection (OCP) is provided by sensing the current through the RDS(on) of the Synchronous MOSFET. When this current exceeds the OCP threshold, a fault condition is generated. This method provides several benefits: 

- Provides accurate overcurrent protection without reducing converter efficiency (the current sensing is lossless) 

- Reduces cost by eliminating a current-sense resistor 

- Reduces any layout-related noise issues. 

The OCP threshold is set to 4A. The threshold is internally compensated so that it remains almost constant at different ambient temperatures. 

When the current exceeds the OCP threshold, the PG and SS signals are pulled low. The Synchronous MOSFET remains on until the current falls to 0, then the FS1603A enters hiccup mode (Figure 12). Both the Control MOSFET and the Synchronous MOSFET remain off for the hiccup-blanking time. After this time, the FS1603A tries to restart. If an over-current fault is still detected, the preceding actions are repeated. The FS1603A remains in hiccup mode until the over-current fault is remedied. 

**==> picture [207 x 151] intentionally omitted <==**

**----- Start of picture text -----**<br>
current limit<br>hiccup<br>blanking time<br>inductor current<br>HDrv<br>LDrv<br>fine inn<br>PG<br>**----- End of picture text -----**<br>


## _**Illustration of OCP in hiccup mode**_ 

## **Over-voltage Protection (OVP)** 

Over-voltage protection (OVP) is provided by sensing the voltage at the Fb pin. When Fb exceeds the output OVP threshold for longer than the output OVP delay (typically 5μs), a fault condition is generated. 

The OVP threshold is defined by the user register bits **OV_Threshold** . 

|**Register**<br>**Bits**<br>**Name/Description**|**Register**<br>**Bits**<br>**Name/Description**|**Register**<br>**Bits**<br>**Name/Description**|
|---|---|---|
|0x17|[1:0]|**OV_Threshold**<br>0:105% of VOUT<br>1:110% of VOUT<br>2:115% of VOUT<br>3:120% of VOUT (default)|



The Control MOSFET is switched off immediately and the PG pin is pulled low. The Synchronous MOSFET is switched on to discharge the output capacitor. 

The Control MOSFET remains latched off until reset by cycling either VCC or En. The voltage at the Fb pin falling below the output OVP threshold (with 5% hysteresis) does not switch on the Control MOSFET but it does switch off the Synchronous MOSFET to prevent build-up of negative current. 

**Rev 1.0, May 14, 2025** 

**Page 17** 

Patent Protected: US 9,729,059 B1; US 10,193,442 B2 Copyright© 2024–25  TDK Corporation. All rights reserved. All registered trademarks and trademarks are the property of their respective owners. Data and specifications subject to change without notice. 

## **FS1603A POL[™] µ** ~~ee~~ 

Figure 13 shows a timing diagram for over-voltage protection. 

**==> picture [211 x 127] intentionally omitted <==**

**----- Start of picture text -----**<br>
HDrv<br>LDrv<br>1.2*VOUT 1.15*VOUT<br>VOUT 0.9*VOUT<br>PG<br>OVP del<br>**----- End of picture text -----**<br>


## _**Illustration of latched OVP**_ 

## **Over-temperature Protection (OTP)** 

Temperature sensing is provided inside the FS1603A. The OTP threshold is defined by the user register bits **OT_Threshold** . 

|**Register**<br>**Bits**<br>**Name/Description**|**Register**<br>**Bits**<br>**Name/Description**|**Register**<br>**Bits**<br>**Name/Description**|
|---|---|---|
|0x19|[1:0]|**OT_Threshold**<br>0:75°C<br>1: 85°C<br>2: 125°C<br>3: 145°C(default)|



When the threshold is exceeded, thermal shutdown switches off both MOSFETs and resets the internal soft-start, but the internal LDO regulator is still in operation. 

Automatic restart is initiated when the sensed temperature drops within the operating range. There is a 25°C hysteresis in the OTP threshold. 

## **Telemetry (ADC)** 

FS1603A has telemetry through I[2] C. Parameters PVIN, VOUT, Fb, IOUT, and temperature can be read through the telemetry. 

|**Telemetry**|**Resolution**|**Min**|**Max**|
|---|---|---|---|
|VIN(V)<br>VOUT (V)|1/16<br>0.02|0<br>3.3|15.9375<br>5.0|
|IOUT (A)<br>Temperature(°C)|0.03125<br>1|0<br>-40|3<br>145|



PVIN reporting is calculated by dividing the decimal equivalent of the contents of register 0x0C by 16. VOUT is calculated from the contents of register 0x0D; multiplying the decimal equivalent by 20mV and then adding 600mV to it. The decimal equivalent of the contents of register 0x0E is divided by 32 to calculate the IOUT reporting. Finally, register 0x0F reports the temperature in 1°C resolution. 

## **Servo Loop and Precision Output Voltage** 

FS1603A has an internal servo loop to minimize VOUT error at steady state. Load and line regulation better than ±1% is achieved. 

## **Power Good (PG)** 

Power Good (PG) behavior is defined by the user register bits **PGControl** and **PG_Threshold** . 

|**Register**<br>**Bits**<br>**Name/Description**|**Register**<br>**Bits**<br>**Name/Description**|**Register**<br>**Bits**<br>**Name/Description**|
|---|---|---|
|0x18<br>[1:0]<br>**PG_Threshold**<br>0:80% of VOUT<br>1: 85% of VOUT<br>2: 90% of VOUT(default)<br>3: 95% of VOUT|||
|0x14|[0]|**PG_Control**<br>1:Threshold based (default)<br>0: DAC based|



**Page 18** 

**Rev 1.0, May 14, 2025** 

Patent Protected: US 9,729,059 B1; US 10,193,442 B2 Copyright© 2024–25  TDK Corporation. All rights reserved. All registered trademarks and trademarks are the property of their respective owners. Data and specifications subject to change without notice. 

## **FS1603A POL[™] µ** 

## **PG_Threshold Bit** 

The user register bit **PG_Threshold** defines the PG threshold as a percentage of VOUT. Hysteresis of 5% is applied to this, giving a lower threshold. 

When Fb rises above the upper threshold, the PG signal is pulled high. When Fb drops below the lower threshold, the PG signal is pulled low. 

## **PGControl Bit Set to 1 (default)** 

Figure 14 shows PG behavior in this situation. 

The behavior is the same at start-up and during normal operation. The PG signal is asserted when: 

- En and VCC are both above their thresholds 

- No fault has occurred (including over-current, over-voltage and over-temperature) 

- VOUT is within the target range (determined by continuously monitoring whether Fb is above the PG threshold) 

**==> picture [214 x 98] intentionally omitted <==**

**----- Start of picture text -----**<br>
0.9*VOUT VOUT<br>VOUT 0.85*VOUT 0.9*VOUT<br>PG<br>**----- End of picture text -----**<br>


## **PGControl Bit Set to 0** 

Figure 15 shows PG behavior in this situation. 

In normal operation, the PG signal behaves in the same way as when the **PGControl** bit is 1. 

At start-up, however, the PG signal is asserted after soft-start is within 2% of target output voltage, not when Fb exceeds the upper PG threshold. 

For pre-biased start-up, the PG signal is not active until the first gate signal of the Control MOSFET is generated. 

FS1603A also integrates an additional PMOS in parallel to the NMOS internally connected to the PG pin (Figure 3). This PMOS allows the PG signal to stay at logic low, even if VCC is low and the PG pin is pulled up to an external voltage not VCC (Figure 10 and Figure 11). 

**==> picture [214 x 117] intentionally omitted <==**

**----- Start of picture text -----**<br>
0.9*VOUT VOUT<br>0.85*VOUT 0.9*VOUT<br>VOUT<br>Internal<br>SS<br>PG<br>**----- End of picture text -----**<br>


_**PG signal when PGControl bit=1**_ 

_**PG signal when PGControl bit=0**_ 

**Page 19** 

**Rev 1.0, May 14, 2025** 

Patent Protected: US 9,729,059 B1; US 10,193,442 B2 Copyright© 2024–25  TDK Corporation. All rights reserved. All registered trademarks and trademarks are the property of their respective owners. Data and specifications subject to change without notice. 

**FS1603A POL[™] µ** 

## **Design Example** 

Let us now consider a simple design example, using the FS1603A for the following design parameters: 

- PVIN = VIN = 12V 

- VOUT = 5.0V 

- FSW = 1.4MHz 

- COUT = 2 x 22μF 

- CIN = 2 x 22μF 

- Ripple Voltage = ±1% * VOUT 

- ΔVOUT(MAX) = ±3% * VOUT (for 50% load transient) 

## **Input Capacitor** 

The input capacitor selected for this design must: 

- Handle the peak and root mean square (RMS) input currents required by the FS1603A 

- Have low equivalent series resistance and inductance (ESR and ESL) to reduce input voltage ripple 

MLCCs (multi-layer ceramic capacitors) are ideal. Typically, in 0805 case size, they can handle 2A RMS current with less than 5°C temperature rise. 

For a buck converter operating at duty cycle D and output current IO, the RMS value of the input current is: 

## **Output Voltage and Output Capacitor** 

The FS1603A is supplied pre-programmed and factory-trimmed in a closed loop to the target voltage specified for the part number. As a result, no external resistor divider is required and resistor tolerances are eliminated from the error budget. 

The design requires minimal output capacitance to meet the target output voltage ripple and target maximum output voltage deviation under load transient conditions. 

For the FS1603A, the minimum number of output capacitors required to achieve target peak-to-peak VOUT ripple is: 

**==> picture [208 x 26] intentionally omitted <==**

where: 

- _N_ MIN = minimum number of output capacitors 

- _D_ = duty cycle 

- _C_ = equivalent capacitance of each output capacitor 

- _F_ SW = switching frequency 

- _ESR_ = equivalent series resistance of each output capacitor 

- _ESL_ = equivalent series inductance of each output capacitor 

- ∆ UTripple(p—p) 

- = target peak-to-peak VOUT ripple 

In this application, IO = 3A and 𝐷= = 0.416 

Therefore, _I_ RMS = 1.48A and we can select two 22μF 16V ceramic capacitors for the input capacitors (C3216X5R1C226M160AB from TDK). 

If the FS1603A is not located close to the 12V power supply, a bulk capacitor (68–330μF) may be used in addition to the ceramic capacitors. 

This design uses C2012X5R0J226K125AB from TDK; this is a 22μF MLCC, 0805 case size, rated at 6.3V. At 5.0V, accounting for DC bias and AC ripple derating, it has an equivalent capacitance of 5μF ( _C_ ). Equivalent series resistance is 3mΩ (ESR) and equivalent series inductance is 0.44nH (ESL). 

Putting these parameters into the equation gives: 

_N_ MIN = 0.45 

For VIN, which is the input to the LDO, it is recommended to use a 1μF capacitor very close to the pin. The VIN pin should be connected to PVIN through a 2.7Ω resistor. Together, the 2.7Ω resistor and 1μF capacitor filter noise on PVIN. 

**Page 20** 

**Rev 1.0, May 14, 2025** 

All registered trademarks and trademarks are the property of their respective owners. Data and specifications subject to change without notice. 

Patent Protected: US 9,729,059 B1; US 10,193,442 B2 Copyright© 2024–25  TDK Corporation. All rights reserved. 

## **FS1603A POL[™] µ** 

To meet the maximum voltage deviation _ΔVo_ max under a ∆ load transient, the minimum required number of output capacitors is: 

**==> picture [85 x 22] intentionally omitted <==**

where: 

- ∆ = load step 

- ∆ UTmax = target maximum voltage deviation 

- UT = output voltage 

- _C_ = equivalent capacitance of each output capacitor 

Again, using _C_ = 5μF, it can be seen that the minimum number of output capacitors required is 0.3. 

In our design intended for space-constrained applications, we use two C2012X5R0J226K125AB capacitors. 

It should be noted here that the calculation for the minimum number of output capacitors under a load transient makes some assumptions: 

- a) No ESR or ESL 

- b) Converter can saturate its duty cycle instantly 

- c) No latency 

Assumptions (a), (b) and (c) are liberal, whereas (d) is conservative. Therefore, in a real application, additional capacitance may be required to meet transient requirements and should be carefully considered by the system designer. 

It should be noted that even in the absence of a target VOUT ripple or target maximum voltage deviation under load transient, at least one 22μF capacitor is still required in order to ensure stable operation without excessive jitter. 

Up to six 22μF capacitors may be used in the design. If more capacitance is required, it is recommended to use a capacitor with relatively high ESR (>3mΩ), such as POSCAP or specialty polymer capacitors. 

## **VCC Capacitor Selection** 

FS1603A uses an on-package VCC capacitor to ensure effective high-frequency bypassing. However, especially for applications that use an external VCC supply, it is recommended that system designers place a 2.2μF/0603/X7R/10V capacitor on the application board as close as possible to the VCC pin. 

- d) Step load (infinite slew rate) 

**Page 21** 

**Rev 1.0, May 14, 2025** 

Patent Protected: US 9,729,059 B1; US 10,193,442 B2 Copyright© 2024–25  TDK Corporation. All rights reserved. All registered trademarks and trademarks are the property of their respective owners. Data and specifications subject to change without notice. 

**FS1603A POL[™] µ** ~~ee~~ 

**==> picture [460 x 245] intentionally omitted <==**

**----- Start of picture text -----**<br>
V<br>C OUT<br>PVIN (12V) IN PVIN SDA SCL VOUT<br>2.7Ω (5.0V)<br>== V Fb<br>IN<br>=<br>V C<br>CC OUT<br>C<br>Vcc<br>= 49.9kΩ<br>PGnd<br>PG<br>I En ADDR AGnd<br>=<br>C<br>IN 1 X 68µF/25V (optional)<br>R<br>+ 2 X 22µF/0805/X5R/16V ADDR<br>COUT 2 X 22µF/0805/X5R/6.3V<br>CVcc 2.2µF/0603/X5R/10V<br>**----- End of picture text -----**<br>


Note: For values of RADDR, see Table 1 on page 15. 

_**Application circuit for a single supply, PVIN = 12V, VOUT = 5.0V, 3A**_ 

**Page 22** 

**Rev 1.0, May 14, 2025** 

Patent Protected: US 9,729,059 B1; US 10,193,442 B2 Copyright© 2024–25  TDK Corporation. All rights reserved. All registered trademarks and trademarks are the property of their respective owners. Data and specifications subject to change without notice. 

**FS1603A POL[™] µ** ~~|~~ 

## **Layout Recommendations** 

FS1603A is a highly integrated device with very few external components, which simplifies PCB layout. However, to achieve the best performance, these general PCB design guidelines should be followed: 

- Bypass capacitors, including input/output capacitors and the VCC bypass capacitor (if used), should be placed as close as possible to the FS1603A pins. 

- Output voltage should be sensed with a separated trace directly from the output capacitor. 

- Analog ground and power ground are connected through a single-point connection. 

- To aid thermal dissipation, the PGnd pad should be connected to the power ground plane using vias. Copper-filled vias are preferred but plated-through-hole vias are acceptable, provided that they are not filled with resin or covered with solder mask. 

- Adequate numbers of vias should be used to make connections between layers, especially for the power traces. 

- To minimize power losses and thermal dissipation, wide copper polygons should be used for input and output power connections. 

- SCL and SDA traces must be at least 10mil wide, with 20–30mil spacing between them. 

## **Thermal Considerations** 

The FS1603A has been thermally tested and modeled in accordance with JEDEC specifications JESD 51-2A and JESD 51-8. It has been tested using a 4-layer application PCB, with thermal vias under the device to assist cooling (for details of the PCB, refer to the application notes). 

The FS1603A has two significant sources of heat: 

- The power MOSFET section of the IC 

- The inductor 

The IC is well coupled to the PCB, which provides its primary cooling path. Although the inductor is also connected to the PCB, its primary cooling path is through convection. The cooling process for both heat sources is ultimately through convection. The PCB can be seen as a heat-spreader or, to some degree, a heat-sink. 

Inductor Thermal Output 

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_**Heat sources in the FS1603A**_ 

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Patent Protected: US 9,729,059 B1; US 10,193,442 B2 Copyright© 2024–25  TDK Corporation. All rights reserved. All registered trademarks and trademarks are the property of their respective owners. Data and specifications subject to change without notice. 

Junction Ambient 

## **FS1603A POL[™] µ** 

Figure 18 shows the thermal resistances in the FS1603A, where: 

- **ϴ** JA is the measure of natural convection from the assembled test sample within a confined enclosure of approximately 30x30x30cm. The air is passive within this environment and the only air movement is due to convection from the device on test. 

- **ϴ** JCbottom is the heat flow from the IC to the bottom of the package, to which it is well coupled. The testing method adopts the method outlined in JESD 51-8, where the test PCB is clamped between cold plates at defined distances from the device. 

- **ϴ** JCtop is theoretically the heat flow from the IC to the top of the package. This is not representative for the FS1603A for two reasons: firstly, it is not the primary conduction path of the IC and, more importantly, the inductor is positioned directly over the IC. As the inductor is a heat source, generating a similar amount of heat to the IC, a meaningful value for junction-to-case (top) cannot be derived. 

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Junction-to-case (top) Top-to-ambient<br>ϴ ϴ<br>JCtop topA<br>[low contribution] [low contribution]<br>Junction- Bottom- PCB-<br>co to-case to-PCB ™ to-ambient<br>(bottom) (solder) (PCB)<br>ϴ<br>JCbottom<br>os<br>µPOL™ device External<br>**----- End of picture text -----**<br>


## _**Thermal resistances of the FS1603A**_ 

The values of the thermal resistances are: 

- **ϴ** JA = 22.6°C/W 

- **ϴ** JCbottom = 2.36°C/W 

Although these values indicate how the FS1603A compares with similar point-of-load products tested using the same conditions and specifications, they cannot be used to predict overall thermal performance. For accurate modeling of the µPOL™’s interaction with its environment, computational fluid dynamics (CFD) simulation software is needed to calculate combined routes of conduction and convection simultaneously. 

Note: In all tests, airflow has been considered as passive or static; applications using forced air may achieve a greater cooling effect. 

**Page 24** 

**Rev 1.0, May 14, 2025** 

Patent Protected: US 9,729,059 B1; US 10,193,442 B2 Copyright© 2024–25  TDK Corporation. All rights reserved. All registered trademarks and trademarks are the property of their respective owners. Data and specifications subject to change without notice. 

**FS1603A POL[™] µ** ~~ee~~ 

## **I[2] C Protocol** 

S = Start bit W = Write bit (‘0’) White bits = Issued by master P = Stop bit R = Read (‘1’) Grey bits = Sent by slave A = Ack Sr = Repeated start (FS160XA) N = Nack 

## **Write transaction** 

1 7 1 1 8 1 8 1 1 S Slave Address W A Register Address A Data Byte A P ~~ee~~ **Read transaction** 1 7 1 1 8 1 1 7 1 1 8 1 1 S Slave Address W A Register Address A Sr Slave Address R A Data Byte N P ~~On~~ 

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**Rev 1.0, May 14, 2025** 

Patent Protected: US 9,729,059 B1; US 10,193,442 B2 Copyright© 2024–25  TDK Corporation. All rights reserved. All registered trademarks and trademarks are the property of their respective owners. Data and specifications subject to change without notice. 

**FS1603A POL[™] µ** ~~ee~~ 

## **Package Description** 

The FS1603A is designed for use with standard surface-mount technology (SMT) population techniques. It has a positive (raised) footprint, with the pads being higher than the surrounding substrate. 

surface wets easily and the positive footprint accommodates processing variations. 

- Note: Refer to the Design Guidelines for more information about TDK’s µPOL™ package series P11F1, including important guidance on checking the compatibility of manufacturing processes such as cleanable flux systems. 

As a result of these properties, the FS1603A works extremely well in lead-free environments. The 

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3.300<br>1.140<br>0.360<br>Pin1<br>i es ot<br>> 0.18 > 0.18<br>|<br>ia‘i sg<br>1.350 1.350<br>0.850 0.850 1 x (1.70 x 0.40)<br>1 x (0.30 x 0.70)<br>i aes<br>12 x (0.40 x 0.30)<br>1 x (1.10 x 0.30) 1.100<br>1 x (0.30 x 0.30)<br>0.700<br>0.300<br>> 0.25<br>> 0.25<br>0.775<br>3.300<br>0.775<br>> 0.25<br>> 0.25<br>yp.<br>0.550 T<br>1.375 1.325<br>0.750 0.825<br>1.750 1.35<br>0.575<br>0.925<br>**----- End of picture text -----**<br>


~~aes~~ Tolerances: ±0.100mm on dimensions given to 3 decimal places ±0.150mm on dimensions given to 2 decimal places 

## _**Dimensioned drawings**_ 

**Page 26** 

## **Rev 1.0, May 14, 2025** 

Patent Protected: US 9,729,059 B1; US 10,193,442 B2 Copyright© 2024–25  TDK Corporation. All rights reserved. All registered trademarks and trademarks are the property of their respective owners. Data and specifications subject to change without notice. 

**FS1603A POL[™] µ** 

## **Tape and Reel Information** 

## **Reel Dimensions** 

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Reel Diameter  Reel Width<br>A (mm) W1 (mm)<br>330  12.8<br>—_| |<br>**----- End of picture text -----**<br>


## **Tape Dimensions** 

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Dimension  (mm)<br>P1  8.0<br>W 12.0<br>A0  3.6<br>B0  3.6<br>K0 1.8<br>**----- End of picture text -----**<br>


## **Pin 1 Orientation in Carrier Tape** 

**Page 27** 

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Patent Protected: US 9,729,059 B1; US 10,193,442 B2 Copyright© 2024–25  TDK Corporation. All rights reserved. All registered trademarks and trademarks are the property of their respective owners. Data and specifications subject to change without notice. 

**FS1603A POL[™] µ** ~~Oe~~ 

## **REMINDERS FOR USING THESE PRODUCTS** 

Before using these products, be sure to request the delivery specifications. 

## SAFETY REMINDERS 

Please pay sufficient attention to the warnings for safe designing when using these products. 

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The products listed on this specification sheet are intended for use in general electric equipment (AV equipment, telecommunication equipment, home appliances, amusement equipment, computer equipment, personal equipment, office equipment, measurement equipment, industrial robots) under a normal condition and use condition. 

The products are not designed or warranted to meet the requirements of the applications listed below, whose performance and/or quality require a more stringent level of safety or reliability, or whose failure, malfunction or trouble could cause serious damage to sociality, person or property. Please understand that we are not responsible for any damage or liability caused by use of the products in any of the applications below or for any other use exceeding the range or conditions set forth in this specification sheet. 

1. Aerospace/Aviation equipment 

2. Transportation equipment (cars, electric trains, ships, etc.) 

3. Medical equipment 

4. Power-generation control equipment 

5. Atomic energy related equipment 

6. Seabed equipment 

7. Transportation control equipment 

8. Public Information-processing equipment 

9. Military equipment 

10. Electric heating apparatus, burning equipment 

11. Disaster prevention/crime prevention equipment 

12. Safety equipment 

13. Other applications that are not considered general-purpose applications 

When using this product in general-purpose application, you are kindly requested to take into consideration securing protection circuit/ equipment or providing backup circuits, etc., to ensure higher safety. To allow flexibility in the applications of the FS160x device family, some parameters are accessible to the users through an I[2] C/PMBus™ interface. These parameters can only be changed within limits that are acceptable to the device. However, it is the responsibility of the user to ensure that any parameter change, whether it be deliberate or inadvertent, does not violate the specifications of the end user system. 

**Page 28** 

**Rev 1.0, May 14, 2025** 

Patent Protected: US 9,729,059 B1; US 10,193,442 B2 Copyright© 2024–25  TDK Corporation. All rights reserved. 

All registered trademarks and trademarks are the property of their respective owners. Data and specifications subject to change without notice.