FL7733AMX

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## Primary-Side-Regulated LED Driver with Power Factor Correction 

**SOIC8 CASE 751EB** 

## FL7733A 

## **MARKING DIAGRAM** 

## **Description** 

The FL7733A is a highly−integrated PWM controller  with advanced Primary−Side Regulation (PSR) technique to minimize components in low−to−mid−power LED lighting converters. 

Using an innovative TRUECURRENT[®] technology to provide tight tolerance constant−current output, this LED driver enables designs with constant current (CC) tolerance of less than ±1% over the universal line voltage range to meet stringent LED brightness requirements. 

By minimizing turn−on time fluctuation, high power factor and low THD over the universal line range are obtained in the FL7733A. An integrated high−voltage startup circuit implements fast startup and high system efficiency. During startup, adaptive feedback loop control anticipates the steady−state condition and sets initial feedback condition close to the steady state to ensure no overshoot or undershoot of LED current. 

The FL7733A also provides powerful protections, such as LED short / open, output diode short, sensing  resistor short / open, and over−temperature for high system reliability. 

The FL7733A controller is available in an 8−pin Small−Outline Package (SOP). 

## **Features** 

## _Performance_ 

- <±3% Total Constant Current Tolerance Over All Conditions <±1% Over Universal Line Voltage Variation 

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ZXYTT<br>7733A<br>TM<br>7733A = Device Code<br>Z = Plant Code<br>X = 1−Digit Year Code<br>Y = 1−Digit Week Code<br>TT = 2−Digit Die Run Code<br>T = Package Type (M = SOP)<br>M = Manufacture Flow Code<br>**----- End of picture text -----**<br>


## **PIN CONFIGURATION** 

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CS 1 8 HV<br>GATE 2 7 NC<br>GND 33 36 COMI<br>VDD 4 5 VS<br>Top View<br>**----- End of picture text -----**<br>


   - <±1% from 50% to 100% Load Voltage Variation 

   - <±1% with ±20% Magnetizing Inductance Variation 

- Primary−Side Regulation (PSR) Control for Cost−Effective Solution without Requiring Input Bulk Capacitor and Secondary Feedback Circuitry 

- Application Input Voltage Range: 80 VAC − 308 VAC 

- High PF of >0.9, and Low THD of <10% Over Universal Line Input Range 

- Fast <200 ms Start−up (at 85 VAC) Using Internal High−Voltage Startup with VDD Regulation 

- Adaptive Feedback Loop Control for Startup without Overshoot 

## **ORDERING INFORMATION** 

See detailed ordering and shipping information on page 12 of this data sheet. 

## _System Protection (continued)_ 

- All Protections are Auto Restart (AR) 

- Cycle−by−Cycle Current Limit 

- Over−Temperature Protection (OTP) 

- All Protections are Auto Restart (AR) 

- Cycle−by−Cycle Current Limit 

## _System Protection_ 

- LED Short / Open Protection 

- Output Diode Short Protection 

- Sensing Resistor Short / Open Protection 

- VDD Over−Voltage Protection (OVP) 

- VDD Under−Voltage Lockout (UVLO) 

## **Applications** 

- Low to Mid Power LED Lighting Systems of 5 W to Greater than 60 W Compatible with Analog Dimming Function 

## **Related Product Resources** 

_FL7733A Product Folder_ 

Publication Order Number: **FL7733A/D** 

**1** 

© Semiconductor Components Industries, LLC, 2014 **January, 2023 − Rev. 3** 

**FL7733A** 

**APPLICATION DIAGRAM** 

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+<br>DC Output<br>−<br>AC Input<br>2<br>GATE<br>8 HV CS 1<br>6 COMI VDD 4<br>3 GND VS 5<br>NC<br>7<br>**----- End of picture text -----**<br>


**Figure 1. Typical Application** 

## **BLOCK DIAGRAM** 

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Shutdown<br>HV 8 Max. DutyController Gate Driver 2 GATE<br>250 ms<br>Timer S Q EAV 1.35 V +− OCP<br>Current Limit<br>VDD 4 + GoodVDD R Control MonitorSRSP SRSP<br>− VCS−CL<br>VOVP +<br>−<br>0.1 V<br>LEB 1 CS<br>Sawtooth<br>Generator<br>VDD Internal<br>OVP Bias<br>OSC 6 COMI<br>S Q EAI<br>GND 3<br>Error<br>SLP R Amp. VREF Line<br>OCP Compensator<br>DCM<br>OTP VDD  Good Controller tDIS TRUECURRENT<br>SRSP Detector Calculation<br>VS OVP<br>3 V<br>VS OVP<br>N.C 7<br>EAV<br>SLP Sample & Hold 5 VS<br>SLP<br>Monitor 0.3 V<br>− +<br>+ −<br>−<br>+<br>−<br>+<br>−<br>+<br>−<br>+<br>**----- End of picture text -----**<br>


**Figure 2. Functional Block Diagram** 

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**2** 

**FL7733A** 

## **PIN DESCRIPTION** 

|**Pin No.**|**Name**|**Description**|
|---|---|---|
|1|CS|_Current Sense_. This pin connects a current−sense resistor to detect the MOSFET current for constant<br>output current regulation.|
|2|GATE|_PWM Signal Output_. This pin uses the internal totem−pole output driver to drive the power MOSFET.|
|3|GND|_Ground_|
|4|VDD|_Power Supply_. IC operating current and MOSFET driving current are supplied using this pin.|
|5|VS|_Voltage Sense_. This pin detects the output voltage and discharge time information for CC regulation. This<br>pin is connected to the auxiliary winding of the transformer via a resistor divider.|
|6|COMI|_Constant Current Loop Compensation_. This pin is connected to a capacitor between COMI and GND for<br>compensating the current loop gain.|
|7|NC|No Connect|
|8|HV|_High Voltage_. This pin is connected to the rectified input voltage via a resistor.|



## **ABSOLUTE MAXIMUM RATINGS** 

|**Symbol**|**Parameter**|**Min**|**Max**|**Unit**|
|---|---|---|---|---|
|HV|HV Pin Voltage|−|700|V|
|VVDD|DC Supply Voltage (Note 1, 2)|−|30|V|
|VVS|VS Pin Input Voltage|−0.3|6.0|V|
|VCS|CS Pin Input Voltage|−0.3|6.0|V|
|VCOMI|COMI Pin Input Voltage|−0.3|6.0|V|
|VGATE|GATE Pin Input Voltage|−0.3|30.0|V|
|PD|Power Dissipation (TA< 50°C)|−|633|mW|
|TJ|Maximum Junction Temperature|−|150|°C|
|TSTG|Storage Temperature Range|−55|150|°C|
|TL|Lead Temperature (Soldering) 10 Seconds|−|260|°C|



Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 

1. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. 

2. All voltage values, except differential voltages, are given with respect to GND pin. 

## **THERMAL IMPEDANCE** (TA = 25 ° C, unless otherwise specified.) 

|**THERMAL**|**IMPEDANCE**(TA= 25°C, unless otherwise specified.)|||
|---|---|---|---|
|**Symbol**|**Parameter**|**Value**|**Unit**|
|�JA|Junction−to−Ambient Thermal Impedance|158|°C/W|
|�JC|Junction−to−Case Thermal Impedance|39|°C/W|



3. Referenced the JEDEC recommended environment, JESD51−2, and test board, JESD51−3, 1S1P with minimum land pattern. 

## **ESD CAPABILITY** 

|**Symbol**|**Parameter**|**Value**|**Unit**|
|---|---|---|---|
|ESD|Human Body Model, ANSI/ESDA/JEDEC JS−001−2012|5|kV|
||Charged Device Model, JESD22−C101|2||



4. Meets JEDEC standards JESD22−A114 and JESD 22−C101. 

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**3** 

## **FL7733A** 

**ELECTRICAL CHARACTERISTICS** (VDD = 15 V, TJ = −40 to +125 ° C, unless otherwise specified. Currents are defined as positive into the device and negative out of device.) 

|**Symbol**|**Parameter**|**Test Condition**|**Min**|**Typ**|**Max**|**Unit**|
|---|---|---|---|---|---|---|
|VDD−ON|Turn−On Threshold Voltage||14.5|16.0|17.5|V|
|VDD−OFF|Turn−Off Threshold Voltage||6.75|7.75|8.75|V|
|IDD−OP|Operating Current|CL= 1 nF, f = fMAX−CC|3|4|5|mA|
|IDD−ST|Startup Current|VDD= VDD−ON– 1.6 V|−|50|100|�A|
|VVDD−OVP|VDDOver−Voltage Protection Level||23|24|25.5|V|
|**GATE SECTION**|||||||
|VOL|Output Voltage Low|TA= 25°C, VDD= 20 V,<br>IDD_GATE= 1 mA|−|−|1.5|V|
|VOH|Output Voltage High|TA= 25°C, VDD= 10 V,<br>IDD= 1 mA|5|−|−|V|
|ISOURCE|Peak Sourcing Current (Note 5)|VDD= 10~20 V|−|−60|−|mA|
|ISINK|Peak Sinking Current (Note 5)|VDD= 10~20 V|−|180|−|mA|
|tR|Rising Time|TA= 25°C, VDD= 15 V,<br>CLOAD= 1 nF|100|150|200|ns|
|tF|Falling Time|TA= 25°C, VDD= 15 V,<br>CLOAD= 1 nF|20|60|100|ns|
|VCLAMP|Output Clamp Voltage|VDD= 20 V, VCS= 0 V,<br>VVS= 0 V, VCOM= 0 V|12|15|18|V|
|**HV STARTUP SECTION**|||||||
|IHV|Supply Current From HV Pin|TA= 25°C, VIN= 90 VAC,<br>VDD= 0 V|−|−|9|mA|
|IHV−LC|Leakage Current after Startup||−|1|10|�A|
|tR−JFET|JFET Regulation Time after Startup (Note 5)|TA= 25°C|190|250|310|ms|
|VJFET−HL|JFET Regulation High Limit Voltage||17.5|19.0|20.5|V|
|VJFET−LL|JFET Regulation Low Limit Voltage||11.5|13.0|14.5|V|
|**CURRENT−ERROR−AMPLIFIER SECTION**|||||||
|gM|Transconductance (Note 5)|TA=25°C|11|17|23|�mho|
|ICOMI−SINK|COMI Sink Current|TA= 25°C, VEAI= 2.55 V,<br>VCOMI= 5 V|12|18|24|�A|
|ICOMI−SOURCE||COMI Source Current||TA= 25°C, VEAI= 0.45 V,<br>VCOMI= 0 V|12|18|24|�A|
|VCOMI−HGH|COMI High Voltage|VEAI= 0 V|4.7|−|−|V|
|VCOMI−LOW|COMI Low Voltage|VEAI= 5 V|−|−|0.1|V|
|VCOMI_INT.CLP|Initial COMI Clamping Voltage (Note 5)||−|1.2|−|V|
|tCOMI_INT.CLP|Time for Initial COMI Clamping (Note 5)||−|15|−|ms|
|**VOLTAGE−SENSE SECTION**|||||||
|tDIS−BNK|tDISBlanking Time of VS(Note 5)||0.85|1.15|1.45|�s|
|IVS−BNK|VSCurrent for VS Blanking||−75|−90|−105|�A|
|VVS−OVP|VSLevel for Output Over−Voltage Protection||2.95|3.00|3.15|V|
|VVS−LOW−CL−EN|VSThreshold Voltage to Enable Low Current Limit<br>(Note 5)||0.25|0.30|0.35|V|
|VVS−HIGH−CL−DIS|VSThreshold Voltage to Disable Low Current Limit<br>(Note 5)||0.54|0.60|0.66|V|
|VVS−SLP−TH|VSThreshold Voltage for Output Short−LED Protection||0.25|0.30|0.35|V|
|tSLP−BNK|VSDetection Disable Time after Startup (Note 5)|TA= 25°C|−|15|−|ms|



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## **FL7733A** 

**ELECTRICAL CHARACTERISTICS** (VDD = 15 V, TJ = −40 to +125 ° C, unless otherwise specified. Currents are defined as positive into the device and negative out of device.) (continued) 

|**Symbol**|**Parameter**|**Test Condition**|**Min**|**Typ**|**Max**|**Unit**|
|---|---|---|---|---|---|---|
|**CURRENT−SENSE SECTION**|||||||
|VRV|Reference Voltage|TA= 25°C|1.485|1.500|1.515|V|
|tLEB|Leading−Edge Blanking Time (Note 5)||−|300|−|ns|
|tMIN|Minimum On Time in CC (Note 5)|VCOMI= 0 V|−|500|−|ns|
|tPD|Propagation Delay to GATE Output||50|100|150|ns|
|VCS−HIGH−CL|High Current Limit Threshold||0.9|1.0|1.1|V|
|VCS−LOW−CL|Low Current Limit Threshold||0.16|0.20|0.24|V|
|tLOW−CM|Low Current Mode Operation Time at Startup (Note 5)||−|20|−|ms|
|VCS−SRSP|VCSThreshold Voltage for Sensing Resistor Short<br>Protection||−|−|0.1|V|
|VCS−OCP|VCSThreshold Voltage for Over−Current Protection|TA= 25°C|1.20|1.35|1.50|V|
|VCS/ IVS|Relation of Line Compensation Voltage and VS<br>Current (Note 5)||−|21.5|−|V/A|
|**OSCILLATOR SECTION**|||||||
|fMAX−CC|Maximum Frequency in CC|TA= 25°C, VS= 3.0 V|65|70|75|kHz|
|fMIN−CC|Minimum Frequency in CC|TA= 25°C, VS= 0.3 V|24.0|29.5|33.0|kHz|
|tON−MAX|Maximum Turn−On Time|TA= 25°C, f = fMAX−CC|11.0|13.5|16.0|�s|
|**OVER−TEMPERATURE−PROTECTION SECTION**|||||||
|TOTP|Threshold Temperature for OTP (Note 5)||−|150|−|°C|
|TOTP−HYS|Restart Junction Temperature Hysteresis (Note 5)||−|10|−|°C|



Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 5. These parameters, although guaranteed by design, are not production tested. 

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**FL7733A** 

## **TYPICAL PERFORMANCE CHARACTERISTICS** 

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1.5<br>1.3<br>1.1<br>0.9<br>0.7<br>0.5<br>−40 −20 0 25 50 75 100 125<br>Temperature ( ° C)<br>Figure 3. VDD−ON vs. Temperature<br>1.5<br>1.3<br>1.1<br>0.9<br>0.7<br>0.5<br>−40 −20 0 25 50 75 100 125<br>Temperature ( ° C)<br>Normalized<br>Normalized<br>**----- End of picture text -----**<br>


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1.5<br>1.3<br>1.1<br>0.9<br>0.7<br>0.5<br>−40 −20 0 25 50 75 100 125<br>Temperature ( ° C)<br>Normalized<br>**----- End of picture text -----**<br>


**Figure 4. VDD−OFF vs. Temperature** 

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1.5<br>1.3<br>1.1<br>0.9<br>0.7<br>0.5<br>−40 −20 0 25 50 75 100 125<br>Temperature ( ° C)<br>Normalized<br>**----- End of picture text -----**<br>


**Figure 5. IDD−OP vs. Temperature** 

**Figure 6. VDD−OVP vs. Temperature** 

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1.5<br>1.3<br>1.1<br>0.9<br>0.7<br>0.5<br>−40 −20 0 25 50 75 100 125<br>Temperature ( ° C)<br>Normalized<br>**----- End of picture text -----**<br>


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1.5<br>1.3<br>1.1<br>0.9<br>0.7<br>0.5<br>−40 −20 0 25 50 75 100 125<br>Temperature ( ° C)<br>Normalized<br>**----- End of picture text -----**<br>


**Figure 7. fMAX−CC vs. Temperature** 

**Figure 8. fMIN−CC vs. Temperature** 

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**6** 

**FL7733A** 

## **TYPICAL PERFORMANCE CHARACTERISTICS** (Continued) 

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1.5<br>1.3<br>1.1<br>0.9<br>0.7<br>0.5<br>−40 −20 0 25 50 75 100 125<br>Temperature ( ° C)<br>Normalized<br>**----- End of picture text -----**<br>


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1.5<br>1.3<br>1.1<br>0.9<br>0.7<br>0.5<br>−40 −20 0 25 50 75 100 125<br>Temperature ( ° C)<br>Normalized<br>**----- End of picture text -----**<br>


**Figure 9. VVR vs. Temperature** 

**Figure 10. Gm vs. Temperature** 

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1.5<br>1.3<br>1.1<br>0.9<br>0.7<br>0.5<br>−40 −20 0 25 50 75 100 125<br>Temperature ( ° C)<br>Normalized<br>**----- End of picture text -----**<br>


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1.5<br>1.3<br>1.1<br>0.9<br>0.7<br>0.5<br>−40 −20 0 25 50 75 100 125<br>Temperature ( ° C)<br>Normalized<br>**----- End of picture text -----**<br>


**Figure 11. ICOMI−SOURCE vs. Temperature** 

**Figure 12. ICOMI−SINK vs. Temperature** 

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1.5<br>1.3<br>1.1<br>0.9<br>0.7<br>0.5<br>−40 −20 0 25 50 75 100 125<br>Temperature ( ° C)<br>Normalized<br>**----- End of picture text -----**<br>


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1.5<br>1.3<br>1.1<br>0.9<br>0.7<br>0.5<br>−40 −20 0 25 50 75 100 125<br>Temperature ( ° C)<br>Normalized<br>**----- End of picture text -----**<br>


**Figure 13. VVS−OVP vs. Temperature** 

**Figure 14. VCS−OCP vs. Temperature** 

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**FL7733A** 

## **FUNCTIONAL DESCRIPTION** 

FL7733A is AC−DC PWM controller for LED lighting applications. TRUECURRENT technology regulate accurate constant LED current independent of input voltage, output voltage, and magnetizing inductance variations. The DCM control in the oscillator reduces conduction loss and maintains DCM operation over a wide range of output voltage, which implements high power factor correction in a single−stage flyback or buck−boost topology. A variety of protections, such as LED short / open protection, sensing resistor short / open protection, over−current protection, over−temperature protection, and cycle−by−cycle current limitation stabilize system operation and protect external components. 

## **Startup** 

At startup, an internal high−voltage JFET supplies startup current and VDD capacitor charging current, as shown in Figure 15. When VDD reaches 16 V, switching begins and the internal high−voltage JFET continues to supply VDD operating current for an initial 250 ms to maintain VDD voltage higher than VDD−OFF. As the output voltage increases, the auxiliary winding becomes the dominant VDD supply current source. 

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VDC<br>RVS1<br>CVDD<br>RVS2<br>HV VDD<br>8 4<br>VS<br>250 ms 5<br>Timer<br>Internal VDD +<br>Bias −<br>16 V /<br>7.75 V<br>**----- End of picture text -----**<br>


**Figure 15. Startup Block** 

Switching is controlled by current−mode for 20 ms after VDD−ON. During current−mode switching with the flyback or buck−boost topology, output current is only determined by output voltage. Therefore, the output voltage increases with constant slope, regardless of line voltage variation. Short−LED Protection (SLP) is enabled after the 15 ms SLP blanking time so that the output voltage is higher than SLP threshold voltage and successful startup is guaranteed without SLP in normal condition. 

During current−mode switching, COMI voltage, which determines turn−on time in voltage mode, is adjusted close to the steady state level. The COMI capacitor is charged to 1.2 V for 15 ms and adjusted to a modulated level inversely proportional to VIN peak value for 5 ms. Turn−on time right after 20 ms startup time can be controlled close to steady state on time so that voltage mode is smoothly entered without LED current overshoot or undershoot. 

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VDD = VDD_ON<br>VIN High Line<br>Low line<br>VCS Current Mode Voltage MODE<br>0.2 V<br>VCOMI Low line<br>High Line<br>1.0 V<br>15 ms<br>ILED Startup Time 20 ms<br>Time<br>**----- End of picture text -----**<br>


**Figure 16. Startup Sequence** 

## **PFC and THD** 

In the flyback or the buck−boost topology, constant turn−on time and constant frequency in Discontinuous Conduction Mode (DCM) operation can achieve high PF and low THD, as shown in Figure 17. Constant turn−on time is maintained by the internal error amplifier and a large external COMI capacitor (typically over 1 �F) at COMI pin. Constant frequency and DCM operation are managed by DCM control. 

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Primary current Secondary current<br>peak envelope peak envelope<br>Average<br>input current<br>Constant t ON Constant t OFF<br>**----- End of picture text -----**<br>


**Figure 17. Power Factor Correction** 

## **Constant−Current Regulation** 

The output current can be estimated using the peak drain current and inductor current discharge time because output current is the same as the average of the diode current in steady state. The peak value of the drain current is determined by the CS peak voltage detector. The inductor current discharge time (tDIS) is sensed by a tDIS detector. With peak drain current, inductor current discharging time and operating switching period information, the TRUECURRENT calculation block estimates output current as follows: 

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**FL7733A** 

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where, _nPS_ is the primary−to−secondary turn ratio and _RS_ is a sensing resistor connected between the source terminal of the MOSFET and ground. 

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VCS<br>I �<br>pk RS ID.pk<br>IO<br>IDS ID<br>VF  � Na<br>Ns<br>Vo  � NNas<br>tON tDIS<br>tS<br>**----- End of picture text -----**<br>


**Figure 18. Key Waveforms for Primary−Side Regulation** 

The output of the current calculation is compared with an internal precise voltage reference to generate an error voltage (VCOMI), which determines the MOSFET’s turn−on time in voltage−mode control. With this innovative TRUECURRENT technology from **onsemi** , constant−current output can be precisely controlled. Although the output current is calculated with accurate method the output current at high input voltage may still be higher than that at low input voltage due to MOSFET’s turn off propagation delay caused by high Qg. To maintain tight CC regulation over the entire input voltage range, a line compensation resistor of 100~500 � can be inserted between the CS pin and the source terminal of the MOSFET. The voltage across by compensation resistor is dependent on current flow out of the CS pin for MOSFET turn−on and it is proportional to input voltage. 

## **DCM Control** 

As mentioned above, DCM should be guaranteed for high power factor in flyback topology. To maintain DCM across a wide range of output voltage, the switching frequency is linearly adjusted by the output voltage in linear frequency control in the whole Vs range. Output voltage is detected by the auxiliary winding and the resistive divider connected to the VS pin, as shown in Figure 19. When the output voltage decreases, secondary diode conduction time is increased and the DCM control lengthens the switching period, which 

retains DCM operation over the wide output voltage range, as shown in Figure 20. The frequency control lowers the primary rms current with better power efficiency in full−load condition. 

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Gate<br>2 GATE<br>Driver<br>CC<br>OSC<br>Control<br>t DIS VOUT<br>Detector<br>VS<br>5<br>DCM<br>S/H<br>Controller<br>**----- End of picture text -----**<br>


**Figure 19. DCM and BCM Control** 

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**----- Start of picture text -----**<br>
nVo Ipk � Tdis<br>Ipk Lm Iavg � T<br>Tdis T<br>Ipk � (4 � 3) � Tdis<br>n [3] 4 Vo Iavg � (4 � 3) � T<br>Lm<br>Ipk<br>4<br>4 T<br>Tdis 3<br>3 Ipk � (5 � 3) � Tdis<br>n  [3] 5 Vo Iavg � (5 � 3) � T<br>Lm<br>Ipk<br>5<br>5 T<br>Tdis 3<br>3<br>**----- End of picture text -----**<br>


**Figure 20. Primary and Secondary Current** 

## **BCM Control** 

The end of secondary diode conduction time could possibly be behind the end of a switching period set by DCM control. In this case, the next switching cycle starts at the end of secondary diode conduction time since FL7733A doesn’t allow CCM. Consequently, the operation mode changes from DCM to Boundary Conduction Mode (BCM). 

## **Analog Dimming Function** 

Analog dimming function can be implemented by controlling COMI voltage which determines the turn−on time of main power MOSFET. Figure 21 shows an example analog dimming circuit for the FL7733A which uses a photo−coupler so the LED current can be controlled by the dimming signal, A−Dim, from the secondary side of the isolation transformer. 

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**FL7733A** 

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**----- Start of picture text -----**<br>
COMI<br>VDC<br>ICOMI<br>CCOMI<br>A−Dim Signal<br>(0~VDC)<br>**----- End of picture text -----**<br>


**Figure 21. Analog Dimming Control** 

## **Short−LED Protection (SLP)** 

In case of a short−LED condition, the secondary diode is stressed by high current. When VS voltage is lower than 0.3 V due to a short−LED condition, the cycle−by−cycle current limit level changes to 0.2 V from 1.0 V and SLP is triggered if the VS voltage is less than 0.3 V for four (4) consecutive  switching cycles.  Figure 22 and Figure 23 show the SLP block and operational waveforms during LED−short condition. To set enough auto−restart time for system safety under protection conditions, VDD is maintained between 13 V and 19 V, which is higher than UVLO, for 250 ms after VDD−ON. SLP is disabled for an initial 15 ms to ensure successful startup in normal LED condition. 

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VDD − 8 HV<br>+<br>19 V /<br>13 V<br>250 ms<br>Timer<br>VDD<br>Good 4 VDD<br>SLP is disabled 15 msTimer 7.75 V16 V /<br>for initial 15 ms<br>SLP − S/H 5 VS<br>+<br>0.3 V<br>+<br>−<br>**----- End of picture text -----**<br>


**Figure 22. Internal SLP Block** 

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LED short<br>V IN<br>V CS<br>0.2 V<br>V DD<br>19 V<br>V DD−ON<br>13 V<br>V DD OFF<br>250 ms JFET regulation<br>Gate<br>15 ms 15 ms<br>**----- End of picture text -----**<br>


## **Open−LED Protection** 

FL7733A protects external components, such as output diodes and output capacitors, during open−LED condition. During switch turn−off, the auxiliary winding voltage is applied as the reflected output voltage. Because the VDD and VS voltages have output voltage information through the auxiliary winding, the internal voltage comparators in the VDD and VS pins can trigger output Over−Voltage Protection (OVP), as shown in Figure 24 and Figure 25. 

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VDD − 8 HV<br>+<br>19 V /<br>13 V<br>250 ms<br>Timer<br>4 VDD<br>VDD<br>Good 16 V /<br>7.75 V<br>VDD  OVP<br>VDD−OVP<br>EAV<br>S/H 5 VS<br>VS  OVP<br>VS−OVP<br>+<br>−<br>+<br>−<br>+<br>−<br>**----- End of picture text -----**<br>


**Figure 24. Internal OVP Block** 

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V OUT LED Open<br>Ns<br>VDD−OVP x Na<br>EAV<br>3 V<br>V DD<br>V DD−OVP<br>19 V<br>V DD ON<br>13 V<br>V DD OFF<br>250 ms JFET regulation<br>Gate<br>**----- End of picture text -----**<br>


**Figure 25. Waveforms in LED Open Condition** 

## **Sensing Resistor Short Protection (SRSP)** 

In a sensing resistor short condition, the VCS level is almost zero and pulse−by−pulse current limit or OCP is not effective. The FL7733A is designed to provide sensing resistor short protection for both current and voltage mode operation. If the VCS level is less than 0.1 V in the first switching cycle, the GATE output is stopped by current−mode SRSP. After 20 ms startup time, the GATE is shut down by the voltage−mode  SRSP if VCS level is less than 0.1 V at over 60% level of peak VIN. 

**Figure 23. Waveforms in Short−LED Condition** 

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**10** 

**FL7733A** 

## **Under−Voltage Lockout (UVLO)** 

The VDD turn−on and turn−off thresholds are fixed internally at 16 V and 7.75 V, respectively. During startup, the VDD capacitor must be charged to 16 V through the high−voltage JFET to enable the FL7733A. The VDD capacitor continues to supply VDD until auxiliary power is delivered from the auxiliary winding of the main transformer. VDD should remain higher than 7.75 V during this startup process. Therefore, the VDD capacitor must be adequate to keep VDD over the UVLO threshold until the auxiliary winding voltage is above 7.75 V. 

## **Over−Current Protection (OCP)** 

When an output diode or secondary winding are shorted, switch current with extremely high di/dt  can flow through the MOSFET even by minimum turn−on time. The 

FL7733A is designed to protect the system against this excessive current. When the CS voltage across the sensing resistor is higher than 1.35 V, the OCP comparator output shuts down GATE switching. 

In a sensing resistor open condition, the sensing resistor voltage can’t be detected and output current is not regulated properly. If the sensing resistor is damaged open−circuit, the parasitic capacitor in the CS pin is charged by internal CS current sources. Therefore, the VCS level is built up to the OCP threshold voltage and then switching is shut down immediately. 

## **Over−Temperature Protection (OTP)** 

The temperature−sensing circuit shuts down PWM output if the junction temperature exceeds 150°C. The hysteresis temperature after OTP triggering is 10°C. 

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**FL7733A** 

## **PCB LAYOUT GUIDANCE** 

PCB layout for a power converter is as important as circuit design because PCB layout with high parasitic inductance or resistance can lead to severe switching noise with system instability. PCB should be designed to minimize switching noise into control signals. 

1. The signal ground and power ground should be separated and connected only at one position (GND pin) to avoid ground loop noise. The power ground path from the bridge diode to the sensing resistors should be short and wide. 

2. Gate−driving current path (GATE – RGATE – MOSFET – RCS – GND) must be as short as possible. 

3. Control pin components; such as CCOMI, CVS, and RVS2; should be placed close to the assigned pin and signal ground. 

4. High−voltage traces related to the drain of MOSFET and RCD snubber should be kept far way from control circuits to avoid unnecessary interference. 

5. If a heat sink is used for the MOSFET, connect this heat sink to power ground. 

6. The auxiliary winding ground should be connected closer to the GND pin than the control pin components’ ground. 

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+<br>DC Output<br>Power<br>ground 5 −<br>AC Input<br>2<br>RCS<br>4<br>FL7733A<br>CS HV<br>GATE NC<br>CCOMI<br>1 GND COMI<br>CVS<br>3<br>VDD VS<br>CVDD RVS2<br>Signal<br>6 ground<br>RVS1<br>R<br>GATE<br>**----- End of picture text -----**<br>


**Figure 26. Layout Example** 

## **ORDERING INFORMATION** 

|**ORDERING INFORMATION**||||
|---|---|---|---|
|**Part Number**|**Operating Temperature Range**|**Package**|**Shipping**†|
|FL7733AMX|−40°C to +125°C|SOIC8, 8−Lead, Small Outline<br>Package (SOP−8)<br>(Pb−Free)|2500 / Tape & Reel|



- †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. 

TRUECURRENT is registered trademark of Semiconductor Components Industries, LLC dba “ **onsemi** ” or its affiliates and/or subsidiaries in the United States and/or other countries. 

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**12** 

MECHANICAL CASE OUTLINE **PACKAGE DIMENSIONS** 

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SOIC8<br>CASE 751EB<br>ISSUE A<br>DATE 24 AUG 2017<br>**----- End of picture text -----**<br>


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