FDY2000PZ
Dual MOSFET, P Channel, 20 V, 350 mA, 1.2 ohm, SC-89, Surface Mount
- Manufacturer: ONSEMI
- Product type: Dual MOSFETs
- No. of Pins: 6Pins
- Channel Type: P Channel
- Transistor Mounting: Surface Mount
- Transistor Polarity: P Channel
- Power Dissipation Pd: 625mW
- Rds(on) Test Voltage: 4.5V
- On Resistance Rds(on): 1.2ohm
- Transistor Case Style: SC-89
- Drain Source Voltage Vds: 20V
- Operating Temperature Max: 150°C
- Continuous Drain Current Id: 350mA
- Power Dissipation P Channel: 625mW
- Gate Source Threshold Voltage Max: 1.03V
- Drain Source Voltage Vds P Channel: 20V
- Continuous Drain Current Id P Channel: 350mA
- Drain Source On State Resistance P Channel: 1.2ohm
| Delivery and price | |
|---|---|
| Units per pack | 5 |
| Price | 0.122 € |
| Current stock | 10+ |
| Lead time | 30 days |
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ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. **==> picture [63 x 11] intentionally omitted <==** **----- Start of picture text -----**<br> January 2006<br>**----- End of picture text -----**<br> ## **FDY2000PZ** ## **Dual P-Channel (– 2.5V) Specified PowerTrench[] MOSFET** ## **General Description** ## **Features** **==> picture [414 x 64] intentionally omitted <==** **----- Start of picture text -----**<br> This Dual P-Channel MOSFET has been designed using Fairchild Semiconductor’s advanced Power • – 350 mA, – 20 V RDS(ON) = 1.2 Ω @ VGS = – 4.5 V<br>Trench process to optimize the RDS(ON) @ VGS = – 2.5v. RDS(ON) = 1.6 Ω @ VGS = – 2.5 V<br>Applications • ESD protection diode (note 3)<br>• Li-Ion Battery Pack Li-Ion Battery Pack • RoHS Compliant<br>**----- End of picture text -----**<br> **==> picture [174 x 151] intentionally omitted <==** **----- Start of picture text -----**<br> • Li-Ion Battery Pack Li-Ion Battery Pack<br>6<br>5<br>4<br>1<br>2<br>3<br>**----- End of picture text -----**<br> **==> picture [406 x 331] intentionally omitted <==** **----- Start of picture text -----**<br> 4 S1 1 6 D1<br>G1 2 5 G2<br>1<br>2 D2 3 4 S2<br>3<br>Absolute Maximum Ratings TA=25 [o] C unless otherwise noted<br>Symbol Parameter Ratings Unit<br>s<br>VDSS Drain-Source Voltage – 20 V<br>VGSS Gate-Source Voltage ± 8 V<br>ID Drain Current – Continuous (Note 1a) – 350 mA<br>– Pulsed – 1000<br>PD Power Dissipation (Steady State) (Note 1a) 625 mW<br>(Note 1b) 446<br>TJ, TSTG Operating and Storage Junction Temperature –55 to +150 °C<br>Range<br>Thermal Characteristics<br>RθJA Thermal Resistance, Junction-to-Ambient (Note 1a) 200 °C/W<br>RθJA Thermal Resistance, Junction-to-Ambient (Note 1b) 280<br>Package Marking and Ordering Information<br>Device Marking Device Reel Size Tape width Quantity<br>A FDY2000PZ 7 ’’ 8 mm 3000 units<br>**----- End of picture text -----**<br> 2006 Fairchild Semiconductor Corporation FDY2000PZ Rev A www.fairchildsemi.com |**Electrical Characteristics**<br>**Symbol**<br>**Parameter**<br>**Off Characteristics**<br>BVDSS<br>Drain–Source Breakdown<br>Voltage<br>∆BVDSS<br>∆TJ<br>Breakdown Voltage Temperature<br>Coefficient<br>IDSS<br>Zero Gate Voltage Drain Current<br>IGSS<br>Gate–BodyLeakage,<br>**On Characteristics**<br>**(Note 2)**<br>VGS(th)<br>Gate Threshold Voltage<br>∆V<br>GS(th)<br>∆TJ<br>Gate Threshold Voltage<br>Temperature Coefficient<br>RDS(on)<br>Static Drain–Source<br>On–Resistance<br>gFS<br>ForwardTransconductance<br>**Dynamic Characteristics**<br>Ciss<br>Input Capacitance<br>Coss<br>Output Capacitance<br>Crss<br>Reverse Transfer Capacitance<br>**Switching Characteristics(Note 2)**<br>td(on)<br>Turn–On DelayTime<br>tr<br>Turn–On Rise Time<br>td(off)<br>Turn–Off DelayTime<br>tf<br>Turn–Off Fall Time<br>Qg<br>Total Gate Charge<br>Qgs<br>Gate–Source Charge<br>Qgd<br>Gate–Drain Charge|TA= 25°C unless otherwise noted<br>**Test Conditions**<br>VGS= 0 V,<br>ID= – 250µA<br>ID= – 250µA, Referenced to 25°C<br>VDS= – 16 V,VGS= 0 V<br>VGS=± 8V,<br>VDS=0V<br>VDS= VGS,<br>ID= – 250 µA<br>ID= 250µA, Referenced to 25°C<br>VGS= – 4.5 V, ID= – 350 mA<br>VGS= – 2.5 V, ID= – 300 mA<br>VGS= – 1.8 V, ID= – 150 mA<br>VGS= – 4.5 V, ID= – 350 mA,<br>TJ= 125°C<br>VDS= –5V,<br>ID= –350mA<br>VDS= – 10 V, VGS= 0 V,<br>f = 1.0 MHz<br>VDD= – 10 V, ID= – 0.5 A,<br>VGS= – 4.5 V, RGEN= 6Ω<br>VDS= – 10 V, ID= – 350 mA,<br>VGS= – 4.5 V|**Min**<br>– 20<br>– 0.65|**Typ**<br>14<br>–1.03<br>–3<br>0.5<br>0.8<br>1.3<br>0.7<br>1.04<br>100<br>30<br>15<br>6<br>13<br>8<br>1<br>1.0<br>0.2<br>0.3|**Max**<br>– 3<br>±10<br>– 1.5<br>1.2<br>1.6<br>2.7<br>1.6<br>12<br>23<br>16<br>2<br>1.4|**Units**<br>V<br>mV/°C<br>µA<br>µA<br>V<br>mV/°C<br>Ω<br>S<br>pF<br>pF<br>pF<br>ns<br>ns<br>ns<br>ns<br>nC<br>nC<br>nC| |---|---|---|---|---|---| |**Drain–Source Diode Characteristics and Maximum Ratings**|||||| |VSD<br>Drain–Source Diode Forward|VGS= 0 V,<br>IS= – 150 m A(Note 2)||– 0.8|– 1.2|V| |Voltage|||||| |trr<br>Diode Reverse Recovery Time|IF= – 350 mA,||10||ns| |Qrr<br>Diode Reverse Recovery Charge|dIF/dt = 100 A/µs||1.5||nC| **Notes:** - **1** . RθJA is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. RθJC is guaranteed by design while RθCA is determined by the user's board design - a) 200°C/W when mounted on a 1in[2] pad of 2 oz copper - b) 280°C/W when mounted on a minimum pad of 2 oz copper Scale 1 : 1 on letter size paper - 2 **.** Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0% 3. The diode connected between the gate and source serves only as protection againts ESD. No gate overvoltage rating is implied. FDY200PZ Rev A www.fairchildsemi.com ## **Typical Characteristics** **==> picture [417 x 523] intentionally omitted <==** **----- Start of picture text -----**<br> 1 2.6<br>VGS= -4.5V -2.5V VGS=-1.8V<br>0.8 2.2<br>-4.0V -3.0V<br> -2.0V<br>0.6 1.8<br> -2.0V<br> -2.5V<br>0.4 1.4<br> - 1.8V -3.0V<br> -3.5V<br>-4.0V<br>0.2 1 -4.5V<br>0 0.6<br>0 0.5 1 1.5 2 0 0.2 0.4 0.6 0.8 1<br>-VDS, DRAIN TO SOURCE VOLTAGE (V) -ID, DRAIN CURRENT (A)<br>Figure 1. On-Region Characteristics. Figure 2. On-Resistance Variation with<br>Drain Current and Gate Voltage.<br>1.6 2.25<br>VIDGS = -0.35A = -4.5V ID = -0.175A<br>1.4<br>1.75<br>1.2<br>1.25<br>1<br>TA = 125 [o] C<br>0.75<br>0.8<br>TA = 25 [o] C<br>0.6 0.25<br>-50 -25 0 25 50 75 100 125 150 0 2 4 6 8 10<br>TJ, JUNCTION TEMPERATURE ( [o] C) -VGS, GATE TO SOURCE VOLTAGE (V)<br>Figure 3. On-Resistance Variation with Figure 4. On-Resistance Variation with<br>Temperature. Gate-to-Source Voltage.<br>1 1<br>VDS = -5V VGS = 0V<br>0.8<br>0.1<br>0.6<br>0.01<br>0.4 TA = 125 [o] C<br>TA = 125 [o] C -55 [o] C<br>0.001 25 [o] C<br>0.2<br>-55 [o] C<br>25 [o] C<br>0 0.0001<br>0.5 1 1.5 2 2.5 0 0.2 0.4 0.6 0.8 1 1.2 1.4<br>-VGS, GATE TO SOURCE VOLTAGE (V) -VSD, BODY DIODE FORWARD VOLTAGE (V)<br>Figure 5. Transfer Characteristics. Figure 6. Body Diode Forward Voltage Variation<br>with Source Current and Temperature.<br>, NORMALIZED<br>, DRAIN CURRENT (A)D RDS(ON)<br>-I<br>DRAIN-SOURCE ON-RESISTANCE<br>, NORMALIZED<br>DS(ON) , ON-RESISTANCE (OHM)<br>R DS(ON)<br>R<br> DRAIN-SOURCE ON-RESISTANCE<br>, DRAIN CURRENT (A)-ID<br>, REVERSE DRAIN CURRENT (A)-IS<br>**----- End of picture text -----**<br> FDY200PZ Rev A www.fairchildsemi.com ## **Typical Characteristics** **==> picture [411 x 518] intentionally omitted <==** **----- Start of picture text -----**<br> 10 150<br>ID = -0.35A Vf = 1 MHzGS = 0 V<br>8 125<br>VDS = -5V<br>-15V 100<br>6 Ciss<br>75<br>-10V<br>4<br>50<br>Coss<br>2<br>25<br>Crss<br>0 0<br>0 0.5 1 1.5 2 2.5 0 4 8 12 16 20<br>Qg, GATE CHARGE (nC) -VDS, DRAIN TO SOURCE VOLTAGE (V)<br>Figure 7. Gate Charge Characteristics. Figure 8. Capacitance Characteristics.<br>10 10<br>SINGLE PULSE<br>1 100µs 8 RθJTA = 280°C/WA = 25°C<br>RDS(ON) LIMIT 10ms1ms 6<br>100ms<br>1s<br>10s<br>0.1 VGS = -4.5V DC 4<br>SINGLE PULSE<br>RθJA = 280 [o] C/W 2<br>TA = 25 [o] C<br>0.01<br>0.01 0.1 1 10 100 0<br>-VDS, DRAIN-SOURCE VOLTAGE (V) 0.0001 0.001 0.01 t1, TIME (sec) 0.1 1 10 100<br>Figure 9. Maximum Safe Operating Area. Figure 10. Single Pulse Maximum<br>Power Dissipation.<br>1<br>D = 0.5 R θJA (t) = r(t) * R θJA<br>RθJA =280 °C/W<br>0.2<br>0.1 P(pk)<br>0.1<br>0.05 t1<br>0.02 t2<br>0.01 TJ - TA = P * RθJA(t)<br>Duty Cycle, D = t1 / t2<br>SINGLE PULSE<br>0.01<br>0.0001 0.001 0.01 0.1 1 10 100 1000<br>t1, TIME (sec)<br>Figure 11. Transient Thermal Response Curve.<br> Thermal characterization performed using the conditions described in Note 1b.<br> Transient thermal response will change depending on the circuit board design.<br>CAPACITANCE (pF)<br>, GATE-SOURCE VOLTAGE (V)<br>GS<br>-V<br>, DRAIN CURRENT (A)-ID<br>P(pk), PEAK TRANSIENT POWER (W)<br>THERMAL RESISTANCE<br>r(t), NORMALIZED EFFECTIVE TRANSIENT<br>**----- End of picture text -----**<br> FDY200PZ Rev A www.fairchildsemi.com Dimensional Outline and Pad Layout **==> picture [396 x 469] intentionally omitted <==** **----- Start of picture text -----**<br> 1.70<br>0.50<br>1.50<br>0.30 0.50<br>0.15<br>6 4<br>1.70<br>1.20 BSC 1.25 1.80<br>1.55<br>1 3<br>(0.20) 0.30 0.55<br>0.50<br>LAND PATTERN RECOMMENDATION<br>1.00<br>0.60 0.18<br>0.56 SEE DETAIL A 0.10<br>0.35 BSC<br>0.20 BSC<br>DETAIL A<br>0.10<br>0.00 SCALE 2 : 1<br>NOTES: UNLESS OTHERWISE SPECIFIED<br> A) THIS PACKAGE CONFORMS TO EIAJ<br> SC89 PACKAGING STANDARD.<br> B) ALL DIMENSIONS ARE IN MILLIMETERS.<br> C) DIMENSIONS ARE EXCLUSIVE OF BURRS,<br> MOLD FLASH, AND TIE BAR EXTRUSIONS.<br>**----- End of picture text -----**<br> FDY200PZ Rev A www.fairchildsemi.com ## **TRADEMARKS** The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. |<br>ACEx™<br>ActiveArray™<br>Bottomless™|<br>FAST®<br>FASTr™<br>FPS™|ISOPLANAR™<br>LittleFET™<br>MICROCOUPLER™|PowerSaver™<br>PowerTrench®<br>QFET®|SuperSOT™-6<br>SuperSOT™-8<br>SyncFET™| |---|---|---|---|---| |Build it Now™|FRFET™|MicroFET™|QS™<br>|TCM™| |CoolFET™|GlobalOptoisolator™|MicroPak™|QT Optoelectronics™<br>|TinyLogic®| |_CROSSVOLT_™|GTO™|MICROWIRE™|Quiet Series™|TINYOPTO™| |DOME™|HiSeC™|MSX™|RapidConfigure™|TruTranslation™| |EcoSPARK™<br>E2CMOS™|I2C™<br>_i-Lo_™|MSXPro™<br>OCX™|RapidConnect™<br>μSerDes™|UHC™<br>UltraFET®| |EnSigna™<br>FACT™|ImpliedDisconnect™<br>IntelliMAX™|OCXPro™<br>OPTOLOGIC®|ScalarPump™<br>SILENT SWITCHER®|UniFET™<br>VCX™| |FACT Quiet Series™||OPTOPLANAR™|SMART START™|Wire™| |Across the board. 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