FDS8978

**DATA SHEET www.onsemi.com** 

## MOSFET – N-Channel, POWERTRENCH[�] 

## 30 V, 7.5 A, 18 m **�** 

## FDS8978, FDS8978-F40 

## **General Description** 

This N−Channel MOSFET has been designed specifically to improve the overall efficiency of DC/DC converters using either synchronous or conventional switching PWM controllers. It has been optimized for low gate charge, low rDS(on) and fast switching speed. 

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VDSS MAX rDS(on) MAX ID MAX<br>30 V 18 m �  @ 10 V 7.5 A<br>21 m �  @ 4.5 V<br>**----- End of picture text -----**<br>


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D2<br>D2<br>D1<br>D1<br>G2<br>S2<br>G1<br>Pin 1 S1<br>SOIC8<br>CASE 751EB<br>**----- End of picture text -----**<br>


## **Features** 

- rDS(on) = 18 m�, VGS = 10 V, ID = 7.5 A 

## **MARKING DIAGRAM** 

- rDS(on) = 21 m�, VGS = 4.5 V, ID = 6.9 A 

- High Performance Trench Technology for Extremely Low rDS(on) 

- Low Gate Charge 

- High Power and Current Handling Capability 

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FDS8978<br>ALYW<br>**----- End of picture text -----**<br>


- 100% Rg Tested 

- These Devices are Pb−Free and are RoHS Compliant 

## **Applications** 

- DC/DC Converters 

FDS8978 = Device Code A = Assembly Site L = Wafer Lot Number YW = Assembly Start Week 

**MOSFET MAXIMUM RATINGS** (TA = 25 ° C unless otherwise noted) 

|**MOSFE**|**T MAXIMUM RATINGS**(TA= 25°C unles|**T MAXIMUM RATINGS**(TA= 25°C unles|s otherwise no|ted)|
|---|---|---|---|---|
|**Symbol**|**Parameter**||**Ratings**|**Unit**|
|VDSS|Drain to Source Voltage||30|V|
|VGS|Gate to Source Voltage||±20|V|
|ID|Drain<br>Current|Continuous (TA= 25°C,<br>VGS= 10 V, R�JA= 50°C/W)|7.5|A|
|||Continuous (TA= 25°C,<br>VGS= 4.5 V, R�JA= 50°C/W)|6.9|A|
|||Pulsed|49|A|
|EAS|Single Pulse Avalanche Energy (Note 1)||57|mJ|
|PD|Power Dissipation||1.6|W|
||Derate above 25°C||13|mW/°C|
|TJ, TSTG|Operating and Storage Temperature||–55 to 150|°C|



Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 

## **PIN CONNECTIONS** 

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D2 G2<br>  5   4<br>D2   6  Q2   3 S2<br>D1   7  2 G1<br>D1   8  Q1  1 S1<br>**----- End of picture text -----**<br>


## **ORDERING INFORMATION** 

See detailed ordering and shipping information on page 13 of this data sheet. 

1. Starting TJ = 25 ° C, L = 1 mH, IAS = 7.5 A, VDD = 30 V, VGS = 10 V. 

Publication Order Number: 

**1** 

© Semiconductor Components Industries, LLC, 2007 **February, 2022 − Rev. 3** 

**FDS8978/D** 

**FDS8978, FDS8978−F40** 

## **THERMAL CHARACTERISTICS** 

|**Symbol**|**Parameter**|**Ratings**|**Unit**|
|---|---|---|---|
|R�JC|Thermal Resistance, Junction to Case (Note 2)|40|°C/W|
|R�JA|Thermal Resistance, Junction to Ambient (Note 2a)|78|°C/W|
|R�JA|Thermal Resistance, Junction to Ambient (Note 2b)|135|°C/W|



2. R � JA is the sum of the junction−to−case and case−to−ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. R � JC is guaranteed by design while R � JA is determined by the user’s board design. a. 78 ° C/W when mounted on a 0.5 in[2] pad of 2 oz copper. 

- b. 125 ° C/W when mounted on a 0.02 in[2] pad of 2 oz copper. 

- c. 135 ° C/W when mounted on a minimum pad. 

## **ELECTRICAL CHARACTERISTICS** (TJ = 25 ° C unless otherwise noted) 

|**ELECTRIC**|**AL CHARACTERISTICS**(TJ= 25°C|unless otherwise noted)|||||
|---|---|---|---|---|---|---|
|**Symbol**|**Parameter**|**Test Conditions**|**Min**|**Typ**|**Max**|**Unit**|
|**OFF CHARACTERISTICS**|||||||
|BVDSS|Drain to Source Breakdown Voltage|ID= 250�A, VGS= 0 V|30|−|−|V|
|IDSS|Zero Gate Voltage Drain Current|VDS= 24V, VGS= 0 V|−|−|1|�A|
|||VDS= 24 V, VGS= 0 V, TJ= 150°C|−|−|250||
|IGSS|Gate to Source Leakage Current|VGS=±20 V|−|−|±100|nA|
|**ON CHARACTERISTICS**|||||||
|VGS(TH)|Gate to Source Threshold Voltage|VGS= VDS, ID= 250�A|1.2|−|2.5|V|
|rDS(on)|Drain to Source On Resistance|ID= 7.5 A, VGS= 10 V|−|14|18|m�|
|||ID= 6.9 A, VGS= 4.5 V|−|17|21||
|||ID= 7.5 A, VGS= 10 V, TJ= 150°C|−|22|29||
|**DYNAMIC CHARACTERISTICS**|||||||
|CISS|Input Capacitance|VDS= 15 V, VGS= 0 V, f = 1 MHz|−|907|1270|pF|
|COSS|Output Capacitance||−|191|−|pF|
|CRSS|Reverse Transfer Capacitance||−|112|−|pF|
|RG|Gate Resistance|VGS= 0.5 V, f = 1 MHz|−|1.2|4.0|�|
|Qg(TOT)|Total Gate Charge at 10 V|VGS= 0 V to 10 V, VDD= 15 V, ID= 7.5 A|−|17|26|nC|
|Qg(5)|Total Gate Charge at 5 V|VGS= 0 V to 5 V, VDD= 15 V, ID= 7.5 A|−|9|14|nC|
|Qgs|Gate to Source Gate Charge|VDD= 15 V, ID= 7.5 A|−|2.3|−|nC|
|Qgs2|Gate Charge Threshold to Plateau||−|1.5|−|nC|
|Qgd|Gate to Drain “Miller” Charge||−|3.3|−|nC|
|**SWITCHING CHARACTERISTICS**(VGS= 10 V)|||||||
|tON|Turn−On Time|VDD= 15 V, ID= 7.5 A, VGS= 10 V,<br>RGS= 16�|−|44|66|ns|
|td(ON)|Turn−On Delay Time||−|7|10.5|ns|
|tr|Rise Time||−|37|55.5|ns|
|td(OFF)|Turn−Off Delay Time||−|48|72|ns|
|tf|Fall Time||−|24|36|ns|
|tOFF|Turn−Off Time||−|72|108|ns|
|**DRAIN−SOURCE DIODE CHARACTERISTICS**|||||||
|VSD|Source to Drain Diode Voltage|ISD= 7.5 A|−|−|1.25|V|
|||ISD= 2.1 A|−|−|1.0|V|
|trr|Reverse Recovery Time|ISD= 7.5 A, dISD/dt = 100 A/�s|−|19|25|ns|
|QRR|Reverse Recovered Charge|ISD= 7.5 A, dISD/dt = 100 A/�s|−|10|13|nC|



Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 

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**2** 

**FDS8978, FDS8978−F40** 

## **TYPICAL CHARACTERISTICS** 

(TJ = 25 ° C unless otherwise noted) 

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1.2 8<br>7<br>1.0<br>6<br>0.8 VGS = 10 VGS = 10 V = 10 V<br>5<br>0.6 4<br>VGS = 4.5 VGS = 4.5 V = 4.5 V<br>3<br>0.4<br>2<br>0.2<br>1 R � JA  = 78 ° C/W<br>0 0<br>0 25 50 75 100 125 150 25 50 75 100 125<br>TA, AMBIENT TEMPERATURE ( ° C) TA, AMBIENT TEMPERATURE (A, AMBIENT TEMPERATURE (, AMBIENT TEMPERATURE ( ° C)<br>Figure 1. Normalized Power Dissipation vs. Figure 2. Maximum Continuous Drain Current vs.<br>Ambient Temperature Ambient Temperature<br>2<br>1 DUTY CYCLE−DESCENDING ORDER<br>D =0.5<br>      0.2<br>      0.1<br>0.1       0.05<br>      0.02<br>      0.01<br>0.01<br>SINGLE PULSE<br>R � JA  = 135 ° C/W<br>0.001<br>10 [−4] 10 [−3] 10 [−2] 10 [−1] 10 [0] 10 [1] 10 [2] 10 [3]<br>t, RECTANGULAR PULSE DURATION (s)<br>, DRAI N CURRENT (A)<br>IDD<br>POWER DISSIPATION MULTIPLIER<br>, NORMALIZED THERMAL IMPEDANCE<br>JA<br>�<br>Z<br>**----- End of picture text -----**<br>


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8<br>7<br>6<br>VGS = 10 VGS = 10 V = 10 V<br>5<br>4<br>VGS = 4.5 VGS = 4.5 V = 4.5 V<br>3<br>2<br>1 R � JA  = 78 ° C/W<br>0<br>25 50 75 100 125 150<br>TA, AMBIENT TEMPERATURE (A, AMBIENT TEMPERATURE (, AMBIENT TEMPERATURE ( ° C)<br>, DRAI N CURRENT (A)<br>IDD<br>**----- End of picture text -----**<br>


**Figure 2. Maximum Continuous Drain Current vs. Ambient Temperature** 

**Figure 3. Normalized Maximum Transient Thermal Impedance** 

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1000<br>VGS = 10 V SINGLE PULSE<br>R � JA  = 135 ° C/W<br>TA = 25 ° C<br>100<br>10<br>1<br>0.5<br>10−4 10 [−3] 10 [−2] 10 [−1] 10 [0] 10 [1] 10 [2] 10 [3]<br>t, PULSE WIDTH (s)<br>, PEAK TRANSIENT POWER (W)<br>(PK)<br>P<br>**----- End of picture text -----**<br>


**Figure 4. Single Pulse Maximum Power Dissipation** 

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**3** 

**FDS8978, FDS8978−F40** 

## **TYPICAL CHARACTERISTICS** 

(TJ = 25 ° C unless otherwise noted) (continued) 

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100<br>If R = 0<br>tAV = (L) (IAS) / (1.3 * RATED BVDSS − VDD)<br>If R  ≠  0<br>tAV = (L / R) ln [(IAS x R) / (1.3 x RATED BVDSS − VDD) +1]<br>10<br>STARTING TJ = 25 ° C<br>STARTING TJ = 150 ° C<br>1<br>0.01 0.1 1 10 100<br>, AVALANCHE CURRENT (A)<br>IAS<br>**----- End of picture text -----**<br>


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tAV, TIME IN AVALANCHE (ms)<br>**----- End of picture text -----**<br>


NOTE: Refer to **onsemi** Application Notes AN−7514 and AN−7515 

**Figure 5. Unclamped Inductive Switching Capability** 

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50<br>PULSE DURATION = 80  � s<br>DUTY CYCLE = 0.5% MAX<br>40<br>VGS = 10 V VGS = 4.5 V<br>30 VGS = 5 V V GS = 3.5 V<br>20<br>VGS = 3 V<br>10<br>0<br>0 0.2 0.4 0.6 0.8 1<br>, DRAI N CURRENT (A)<br>ID<br>**----- End of picture text -----**<br>


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VDS, DRAIN TO SOURCE VOLTAGE (V)<br>**----- End of picture text -----**<br>


**Figure 7. Saturation Characteristics** 

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50<br>PULSE DURATION = 80  � s<br>DUTY CYCLE = 0.5% MAX<br>40 V DS = 5 V<br>30<br>TJ = 25 ° C<br>20<br>10 TJ = 150 ° C<br>TJ = −55 ° C<br>0<br>1 2 3 4 5<br>VGS, GATE TO SOURCE VOLTAGE (V)<br>Figure 6. Transfer Characteristics<br>50<br>PULSE DURATION = 80  � s<br>DUTY CYCLE = 0.5% MAX<br>40<br>ID = 10.2 A<br>30<br>20<br>10<br>ID = 1 A<br>0<br>2 4 6 8 10<br>VGS, GATE TO SOURCE VOLTAGE (V)<br>, DRAI N CURRENT (A)<br>ID<br>) �<br>, DRAIN TO SOURCE<br>ON RESISTANCE (m<br>rDS(ON)<br>**----- End of picture text -----**<br>


**Figure 8. Drain to Source On Resistance vs. Gate Voltage and Drain Current** 

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1.6<br>PULSE DURATION = 80  � s<br>DUTY CYCLE = 0.5% MAX<br>1.4<br>1.2<br>1.0<br>0.8<br>VGS = 10 V, ID = 10.2 A<br>0.6<br>−80 −40 0 40 80 120 160<br>TJ, JUNCTION TEMPERATURE ( ° C)<br>NORMALIZED DRAIN TO<br>SOURCE ON RESISTANCE<br>**----- End of picture text -----**<br>


**Figure 9. Normalized Drain to Source On Resistance vs. Junction Temperature** 

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1.2<br>VGS = VDS, ID = 250  � A<br>1.0<br>0.8<br>0.6<br>−80 −40 0 40 80 120 160<br>TJ, JUNCTION TEMPERATURE ( ° C)<br>VOLTAGE<br>NORMALIZED GATE THRESHOLD<br>**----- End of picture text -----**<br>


**Figure 10. Normalized Gate Threshold Voltage vs. Junction Temperature** 

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**4** 

**FDS8978, FDS8978−F40** 

## **TYPICAL CHARACTERISTICS** 

(TJ = 25 ° C unless otherwise noted) (continued) 

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1.10<br>ID = 250  � A<br>1.05<br>1.00<br>0.95<br>0.90<br>−80 −40 0 40 80 120 160<br>TJ, JUNCTION TEMPERATURE ( ° C)<br>BREAKDOWN VOLTAGE<br>NORMALIZED DRAIN TO SOURCE<br>**----- End of picture text -----**<br>


**Figure 11. Normalized Drain to Source Breakdown Voltage vs. Junction Temperature** 

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10<br>VDD = 15 V<br>8<br>6<br>4<br>WAVEFORMS IN<br>DESCENDING ORDER:<br>2<br>ID = 7.5 A<br>ID = 1 A<br>0<br>0 3 6 9 12 15 18<br>Qg, GATE CHARGE (nC)<br>, GATE TO SOURCE VOLTAGE (V)<br>GS<br>V<br>**----- End of picture text -----**<br>


**Figure 13. Gate Charge Waveforms for Constant Gate Currents** 

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2000<br>CISS = CGS + CGD<br>1000<br>COSS ≅  CDS + CGD<br>CRSS = CGD<br>VGS = 0 V, f = 1 MHz<br>10<br>0.1 1 10 30<br>VDS, DRAIN TO SOURCE VOLTAGE (V)<br>Figure 12. Capacitance vs. Drain to Source Voltage<br>60<br>100 � s<br>10<br>1ms<br>1 10ms<br>THIS AREA IS<br>LIMITED BY rDS(on) 100ms<br>0.1 SINGLE PULSE 1s<br>TJ = MAX RATED 10s<br>R TA �  = 25 JA = 125 ° C ° C/W DC<br>0.01<br>0.01 0.1 1 10 100<br>VDS, DRAIN TO SOURCE VOLTAGE (V)<br>C, CAPACITANCE (pF)<br>, DRAIN CURRENT (A)<br>ID<br>**----- End of picture text -----**<br>


**Figure 12. Capacitance vs. Drain to Source Voltage** 

**Figure 14. Forward Bis Safe Operating Area** 

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**5** 

**FDS8978, FDS8978−F40** 

## **TEST CIRCUITS AND WAVEFORMS** 

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V DS<br>L<br>VARY tP TO OBTAIN<br>REQUIRED PEAK IAS RG +VDD<br>VGS −<br>DUT<br>t P<br>0 V IAS<br>0.01  �<br>**----- End of picture text -----**<br>


**Figure 15. Unclamped Energy Test Circuit** 

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BVDSS<br>t P<br>VDS<br>IAS<br>VDD<br>0<br>t AV<br>**----- End of picture text -----**<br>


**Figure 16. Unclamped Energy Waveforms** 

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VDS<br>L<br>VGS +<br>VDD<br>−<br>DUT<br>Ig(REF)<br>**----- End of picture text -----**<br>


**Figure 17. Gate Charge Test Circuit** 

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VDD Qg(TOT)<br>VDS VGS<br>VGS = 10 V<br>Qg(5)<br>Qgs2 VGS = 5 V<br>VGS = 1 V<br>0<br>Qg(TH)<br>Qgs Qgd<br>Ig(REF)<br>0<br>**----- End of picture text -----**<br>


**Figure 18. Gate Charge Waveforms** 

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VDS<br>RL<br>VGS +VDD<br>−<br>DUT<br>RGS<br>VGS<br>**----- End of picture text -----**<br>


**Figure 19. Switching Time Test Circuit** 

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t ON t OFF<br>t d(ON) t d(OFF)<br>tr tf<br>VDS<br>90% 90%<br>10 % 10%<br>0<br>90%<br>VGS 50% 50%<br>PULSE WIDTH<br>10%<br>0<br>**----- End of picture text -----**<br>


**Figure 20. Switching Time Waveforms** 

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**6** 

**FDS8978, FDS8978−F40** 

## **THERMAL RESISTANCE VS. MOUNTING PAD AREA** 

Thermal resistances corresponding to other copper areas can be obtained from Figure 21 or by calculation using Equation 2. The area, in square inches is the top copper area including the gate and source pads. 

The maximum rated junction temperature, TJM, and the thermal resistance of the heat dissipating path determines the maximum allowable device power dissipation, PDM, in an application. Therefore the application’s ambient ° ° temperature, TA ( C), and thermal resistance R�JA ( C/W) must be reviewed to ensure that TJM is never exceeded. Equation 1 mathematically represents the relationship and serves as the basis for establishing the rating of the part. 

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The transient thermal impedance (Z�JA) is also effected by varied top copper board area. Figure 22 shows the effect of copper pad area on single pulse transient thermal impedance. Each trace represents a copper pad area in square inches corresponding to the descending list in the graph. Spice and SABER thermal models are provided for each of the listed pad areas. 

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In using surface mount devices such as the SO8 package, the environment in which it is applied will have a significant influence on the part’s current and maximum power dissipation ratings. Precise determination of PDM is complex and influenced by many factors: 

Copper pad area has no perceivable effect on transient thermal impedance for pulse widths less than 100 ms. For pulse widths less than 100 ms the transient thermal impedance is determined by the die and package. Therefore, CTHERM1 through CTHERM5 and RTHERM1 through RTHERM5 remain constant for each of the thermal models. A listing of the model component values is available in Table 1. 

1. Mounting pad area onto which the device is attached and whether there is copper on one side or both sides of the board. 

2. The number of copper layers and the thickness of the board. 

3. The use of external heat sinks. 

4. The use of thermal vias. 

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200<br>5. Air flow and board orientation.<br>6. For non steady state applications, the pulse width, R � JA = 64 + 26 / (0.23 + Area)<br>the duty cycle and the transient thermal response of<br>the part, the board and the environment they are in. 150<br> provides thermal information to assist the<br>designer’s preliminary application evaluation. Figure 21<br>�JA for the device as a function of the top copperJA for the device as a function of the top copperfor the device as a function of the top copper<br>(component side) area. This is for a horizontally positioned 100<br>FR−4 board with 1 oz copper after 1000 seconds of steady<br>state power with no air flow. This graph provides the<br>necessary information for calculation of the steady state<br>50<br>temperature  or  power  dissipation.  Pulse 0.001 0.01 0.1 1 10<br>applications can be evaluated using the  onsemi  device Spice<br>AREA, TOP COPPER AREA (in [2] )<br>thermal model or manually utilizing the normalized<br>maximum transient thermal impedance curve. Figure 21. Thermal Resistance vs. Mounting Pad Area<br>150<br>COPPER BOARD AREA − DESCENDING ORDER<br>0.04 in [2]<br>120<br>0.28 in [2]<br>0.52 in [2]<br>90 0.76 in [2]<br>1.00 in [2]<br>60<br>30<br>0<br>10 [−1] 10 [0] 10 [1] 10 [2] 10 [3]<br>t, RECTANGULAR PULSE DURATION (s)<br>C/W)<br>°<br> (<br>JA<br>�<br>R<br>C/W)<br>°<br>, THERMAL IMPEDANCE (<br>JA<br>�<br>Z<br>**----- End of picture text -----**<br>


5. Air flow and board orientation. 

6. For non steady state applications, the pulse width, 

**onsemi** provides thermal information to assist the designer’s preliminary application evaluation. Figure 21 defines the R�JA for the device as a function of the top copperJA for the device as a function of the top copperfor the device as a function of the top copper (component side) area. This is for a horizontally positioned FR−4 board with 1 oz copper after 1000 seconds of steady state power with no air flow. This graph provides the necessary information for calculation of the steady state junction temperature or power dissipation. Pulse applications can be evaluated using the **onsemi** device Spice thermal model or manually utilizing the normalized maximum transient thermal impedance curve. 

**Figure 21. Thermal Resistance vs. Mounting Pad Area** 

**Figure 22. Thermal Impedance vs. Mounting Pad Area** 

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**7** 

**FDS8978, FDS8978−F40** 

## **PSPICE ELECTRICAL MODEL** 

.SUBCKT FDS8978 2 1 3 *February 2005 Ca 12 8 7.8e−10 Cb 15 14 7.8e−10 Cin 6 8 .78e−9 Dbody 7 5 DbodyMOD Dbreak 5 11 DbreakMOD Dplcap 10 5 DplcapMOD 

Ebreak 11 7 17 18 32.9 Eds 14 8 5 8 1 Egs 13 8 6 8 1 Esg 6 10 6 8 1 Evthres 6 21 19 8 1 Evtemp 20 6 18 22 1 

It 8 17 1 Lgate 1 9 5.29e−9 Ldrain 2 5 1.0e−9 Lsource 3 7 0.18e−9 RLgate 1 9 52.9 RLdrain 2 5 10 RLsource 3 7 1.8 Mmed 16 6 8 8 MmedMOD Mstro 16 6 8 8 MstroMOD Mweak 16 21 8 8 MweakMOD Rbreak 17 18 RbreakMOD 1 Rdrain 50 16 RdrainMOD 1.6e−3 Rgate 9 20 2.3 RSLC1 5 51 RSLCMOD 1e−6 RSLC2 5 50 1e3 Rsource 8 7 RsourceMOD 8.9e−3 Rvthres 22 8 RvthresMOD 1 Rvtemp 18 19 RvtempMOD 1 S1a 6 12 13 8 S1AMOD S1b 13 12 13 8 S1BMOD S2a 6 15 14 13 S2AMOD S2b 13 15 14 13 S2BMOD 

Vbat 22 19 DC 1 

ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e−6*170),5))} 

.MODEL DbodyMOD D (IS=2.0E−12 IKF=10 N=1.01 RS=7.0e−3 TRS1=8e−4 TRS2=2e−7 +CJO=3.5e−10 M=0.55 TT=7e−11 XTI=2) .MODEL DbreakMOD D (RS=0.2 TRS1=1e−3 TRS2=−8.9e−6) .MODEL DplcapMOD D (CJO=3.8e−10 IS=1e−30 N=10 M=0.45) .MODEL MstroMOD NMOS (VTO=2.36 KP=150 IS=1e−30 N=10 TOX=1 L=1u W=1u) .MODEL MmedMOD NMOS (VTO=1.95 KP=5.0 IS=1e−30 N=10 TOX=1 L=1u W=1u RG=2.3) .MODEL MweakMOD NMOS (VTO=1.57 KP=0.02 IS=1e−30 N=10 TOX=1 L=1u W=1u RG=23 RS=0.1) 

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**8** 

**FDS8978, FDS8978−F40** 

.MODEL RbreakMOD RES (TC1=8.3e−4 TC2=−8e−7) .MODEL RdrainMOD RES (TC1=15e−3 TC2=0.1e−5) .MODEL RSLCMOD RES (TC1=1e−4 TC2=1e−6) .MODEL RsourceMOD RES (TC1=1e−3 TC2=3e−6) .MODEL RvtempMOD RES (TC1=−1.8e−3 TC2=2e−7) .MODEL RvthresMOD RES (TC1=−2.0e−3 TC2=−6e−6) .MODEL S1AMOD VSWITCH (RON=1e−5 ROFF=0.1 VON=−4 VOFF=−3.5) .MODEL S1BMOD VSWITCH (RON=1e−5 ROFF=0.1 VON=−3.5 VOFF=−4) .MODEL S2AMOD VSWITCH (RON=1e−5 ROFF=0.1 VON=−1.5 VOFF=−1.0) .MODEL S2BMOD VSWITCH (RON=1e−5 ROFF=0.1 VON=−1.0 VOFF=−1.5) 

.ENDS 

NOTE: For further discussion of the PSPICE model, consult **A New PSPICE Sub−Circuit for the Power MOSFET Featuring Global Temperature Options** ; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley. 

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**----- Start of picture text -----**<br>
LDRAIN<br>DPLCAP 5 DRAIN<br>2<br>10<br>RLDRAIN<br>RSLC1<br>51 DBREAK<br>RSLC2<br>515 ESLC 11<br>ESG +− 68 EVTHRES RDRAIN50 16 EBREAK +−1718 DBODY<br>LGATE EVTEMP + 198 − 21 MWEAK<br>GATE RGATE + 18 − 6<br>1 9 20 22 MMED<br>RLGATE MSTRO<br>LSOURCE<br>CIN 8 7 SOURCE3<br>RSOURCE<br>RLSOURCE<br>S1A S2A<br>12 13 14 15 17 RBREAK 18<br>8 13<br>S1B S2B RVTEMP<br>CA 13+ CB+ 14 IT −19<br>EGS 68 EDS 58 + VBAT<br>− − 8<br>22<br>RVTHRES<br>+<br>−<br>**----- End of picture text -----**<br>


**Figure 23.** 

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**9** 

**FDS8978, FDS8978−F40** 

## **SABER ELECTRICAL MODEL** 

REV February 2005 template FDS8978 n2,n1,n3 electrical n2,n1,n3 { var i iscl 

dp..model dbodymod = (isl=2.0e−12,ikf=10,nl=1.01,rs=7.0e−3,trs1=8e−4,trs2=2e−7,cjo=3.5e−10,m=0.55,tt=7e−11,xti=2) dp..model dbreakmod = (rs=0.2,trs1=1e−3,trs2=−8.9e−6) dp..model dplcapmod = (cjo=3.8e−10,isl=10e−30,nl=10,m=0.45) m..model mstrongmod = (type=_n,vto=2.36,kp=150,is=1e−30, tox=1) m..model mmedmod = (type=_n,vto=1.95,kp=5.0,is=1e−30, tox=1) m..model mweakmod = (type=_n,vto=1.57,kp=0.02,is=1e−30, tox=1,rs=0.1) sw_vcsp..model s1amod = (ron=1e−5,roff=0.1,von=−4,voff=−3.5) sw_vcsp..model s1bmod = (ron=1e−5,roff=0.1,von=−3.5,voff=−4) sw_vcsp..model s2amod = (ron=1e−5,roff=0.1,von=−1.5,voff=−1.0) sw_vcsp..model s2bmod = (ron=1e−5,roff=0.1,von=−1.0,voff=−1.5) c.ca n12 n8 = 7.8e−10 c.cb n15 n14 = 7.8e−10 c.cin n6 n8 = .78e−9 

dp.dbody n7 n5 = model=dbodymod dp.dbreak n5 n11 = model=dbreakmod dp.dplcap n10 n5 = model=dplcapmod 

spe.ebreak n11 n7 n17 n18 = 32.9 spe.eds n14 n8 n5 n8 = 1 spe.egs n13 n8 n6 n8 = 1 spe.esg n6 n10 n6 n8 = 1 spe.evthres n6 n21 n19 n8 = 1 spe.evtemp n20 n6 n18 n22 = 1 

i.it n8 n17 = 1 l.lgate n1 n9 = 5.29e−9 l.ldrain n2 n5 = 1.0e−9 l.lsource n3 n7 = 0.18e−9 

res.rlgate n1 n9 = 52.9 res.rldrain n2 n5 = 10 res.rlsource n3 n7 = 1.8 

m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u 

res.rbreak n17 n18 = 1, tc1=8.3e−4,tc2=−8e−7 res.rdrain n50 n16 = 1.6e−3, tc1=15e−3,tc2=0.1e−5 res.rgate n9 n20 = 2.3 res.rslc1 n5 n51 = 1e−6, tc1=1e−4,tc2=1e−6 res.rslc2 n5 n50 = 1e3 res.rsource n8 n7 = 8.9e−3, tc1=1e−3,tc2=3e−6 res.rvthres n22 n8 = 1, tc1=−2.0e−3,tc2=−6e−6 res.rvtemp n18 n19 = 1, tc1=−1.8e−3,tc2=2e−7 sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod 

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**10** 

**FDS8978, FDS8978−F40** 

v.vbat n22 n19 = dc=1 equations { i (n51−>n50) +=iscl iscl: v(n51,n50) = ((v(n5,n51)/(1e−9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/170))** 5)) } } 

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**----- Start of picture text -----**<br>
LDRAIN<br>DPLCAP 5 DRAIN<br>2<br>10<br>RLDRAIN<br>RSLC1<br>RSLC2<br>ISCL<br>− 50 DBREAK<br>6 RDRAIN<br>ESG + 8 EVTHRES 16 11 DBODY<br>LGATE EVTEMP + 198 − 21 MWEAK<br>GATE1 9RGATE20+ 1822 − 6 MMED EBREAK+<br>RLGATE MSTRO 17<br>CIN 8 −18 7 LSOURCE SOURCE3<br>RSOURCE<br>RLSOURCE<br>S1A S2A<br>12 13 14 15 17 RBREAK 18<br>8 13<br>S1B S2B RVTEMP<br>CA 13+ CB+ 14 IT −19<br>EGS 68 EDS 58 + VBAT<br>− − 8<br>22<br>RVTHRES<br>**----- End of picture text -----**<br>


**Figure 24.** 

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**11** 

**FDS8978, FDS8978−F40** 

## **SPICE THERMAL MODEL** 

REV February 2005 template FDS8878 n2,n1,n3 Copper Area =1.0 in[2] CTHERM1 TH 8 2.0e−3 CTHERM2 8 7 5.0e−3 CTHERM3 7 6 1.0e−2 CTHERM4 6 5 4.0e−2 CTHERM5 5 4 9.0e−2 CTHERM6 4 3 2e−1 CTHERM7 3 2 1 CTHERM8 2 TL 3 

RTHERM1 TH 8 1e−1 RTHERM2 8 7 5e−1 RTHERM3 7 6 1 RTHERM4 6 5 5 RTHERM5 5 4 8 RTHERM6 4 3 12 RTHERM7 3 2 18 RTHERM8 2 TL 25 

## **SABER THERMAL MODEL** 

Copper Area = 1.0 in[2] template thermal_model th tl thermal_c th, tl { ctherm.ctherm1 th 8 =2.0e−3 ctherm.ctherm2 8 7 =5.0e−3 ctherm.ctherm3 7 6 =1.0e−2 ctherm.ctherm4 6 5 =4.0e−2 ctherm.ctherm5 5 4 =9.0e−2 ctherm.ctherm6 4 3 =2e−1 ctherm.ctherm7 3 2 1 ctherm.ctherm8 2 tl 3 

rtherm.rtherm1 th 8 =1e−1 rtherm.rtherm2 8 7 =5e−1 rtherm.rtherm3 7 6 =1 rtherm.rtherm4 6 5 =5 rtherm.rtherm5 5 4 =8 rtherm.rtherm6 4 3 =12 rtherm.rtherm7 3 2 =18 rtherm.rtherm8 2 tl =25 } 

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**----- Start of picture text -----**<br>
th JUNCTION<br>RTHERM1 CTHERM1<br>8<br>RTHERM2 CTHERM2<br>7<br>RTHERM3 CTHERM3<br>6<br>RTHERM4 CTHERM4<br>5<br>RTHERM5 CTHERM5<br>4<br>RTHERM6 CTHERM6<br>3<br>RTHERM7 CTHERM7<br>2<br>RTHERM8 CTHERM8<br>tl CASE<br>Figure 25.<br>**----- End of picture text -----**<br>


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**12** 

**FDS8978, FDS8978−F40** 

**Table 1. THERMAL MODELS** 

|**COMPONANT**|**0.04 in2**|**0.28 in2**|**0.52 in2**|**0.76 in2**|**1.0 in2**|
|---|---|---|---|---|---|
|CTHERM6|1.2e−1|1.5e−1|2.0e−1|2.0e−1|2.0e−1|
|CTHERM7|0.5|1.0|1.0|1.0|1.0|
|CTHERM8|1.3|2.8|3.0|3.0|3.0|
|RTHERM6|26|20|15|13|12|
|RTHERM7|39|24|21|19|18|
|RTHERM8|55|38.7|31.3|29.7|25|



## **PACKAGE MARKING AND ORDERING INFORMATION** 

|**Device**|**Device Marking**|**Package Type**|**Shipping**†|
|---|---|---|---|
|FDS8978|FDS8978|SOIC8 (Pb−Free)|2500 / Tape & Reel|
|FDS8978−F40|FDS8978|SOIC8 (Pb−Free)|2500 / Tape & Reel|



†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. 

POWERTRENCH is registered trademark of Semiconductor Components Industries, LLC dba “ **onsemi** ” or its affiliates and/or subsidiaries in the United States and/or other countries. 

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**13** 

MECHANICAL CASE OUTLINE **PACKAGE DIMENSIONS** 

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SOIC8<br>CASE 751EB<br>ISSUE A<br>DATE 24 AUG 2017<br>**----- End of picture text -----**<br>


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