FDS89161LZ

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## **FDS89161LZ** 

**Dual N-Channel Shielded Gate PowerTrench[®] MOSFET 100 V, 2.7 A, 105 m** Ω 

## **Features** 

Shielded Gate MOSFET Technology 

Max rDS(on) = 105 mΩ at VGS = 10 V, ID = 2.7 A Max rDS(on) = 160 mΩ at VGS = 4.5 V, ID = 2.1 A High performance trench technology for extremely low rDS(on) 

High power and current handling capability in a widely used surface mount package 

CDM ESD protection level > 2KV typical (Note 4) 100% UIL Tested 

## **General Description** 

This N-Channel logic Level MOSFETs are produced using Fairchild Semiconductor‘s advanced PowerTrench **[®]** process that incorporates Shielded Gate technology. This process has been optimized for the on-state resisitance and yet maintain superior switching performance. G-S zener has been added to enhance ESD voltage level. 

## **Application** 

DC-DC conversion 

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RoHS Compliant<br>D2<br>D2<br>D1 D2 5 4 G2<br>D1<br>D2 6 Q2 3 S2<br>BY<br>G2<br>D1 7 2 G1<br>S2<br>G1 Q1<br>eo D1 8 Ore 1 S1<br>S1<br>Pin 1<br>SO-8<br>MOSFET Maximum Ratings TA = 25 °C unless otherwise noted<br>Symbol Parameter Ratings Units<br>VDS Drain to Source Voltage 100 V<br>VGS Gate to Source Voltage ±20 V<br>Drain Current   -Continuous            2.7<br>ID        -Pulsed 15 A<br>EAS Single Pulse Avalanche Energy (Note 3) 13 mJ<br>PD Power DissiPower Dissippation   ation              TTCA = 25 °C   = 25 °C     (Note1a) 1.631 W<br>TJ, TSTG Operating and Storage Junction Temperature Range -55 to +150 °C<br>Thermal Characteristics<br>RθJC Thermal Resistance, Junction to Case   (Note 1) 40<br>°C/W<br>ee RθJA Thermal Resistance, Junction to Ambient    (Note 1a) 78<br>Package Marking and Ordering Information<br>Device Marking Device Package Reel Size Tape Width Quantity<br>FDS89161LZ FDS89161LZ SO-8 13 ’’ 12 mm 2500 units<br>[[_i]<br>**----- End of picture text -----**<br>


©2011 Fairchild Semiconductor Corporation FDS89161LZ  Rev. 1.2 

www.fairchildsemi.com 

**1** 

## **Electrical Characteristics** TJ = 25°C unless otherwise noted 

|**Off Characteristics**<br>**On Characteristics**<br>**Dynamic Characteristics**<br>**Switching Characteristics**<br>**Symbol**<br>**Parameter**<br>**Test Conditions**<br>**Min**<br>**Typ**<br>**Max**<br>**Units**<br>BVDSS<br>Drain to Source Breakdown Voltage<br>ID= 250μA, VGS= 0 V<br>100<br>V<br>ΔBVDSS<br>ΔTJ<br>Breakdown Voltage Temperature<br>Coefficient<br>ID= 250μA, referenced to 25 °C<br>68<br>mV/°C<br>IDSS<br>Zero Gate Voltage Drain Current<br>VDS= 80 V, VGS = 0 V<br>1<br>μA<br>IGSS<br>Gate to Source Leakage Current<br>VGS= ±20 V, VDS = 0 V<br>±10<br>μA<br>VGS(th)<br>Gate to Source Threshold Voltage<br>VGS= VDS,  ID= 250μA<br>1<br>1.7<br>2.2<br>V<br>ΔVGS(th)<br>ΔTJ<br>Gate to Source Threshold Voltage<br>Temperature Coefficient<br>ID= 250μA, referenced to 25 °C<br>-6<br>mV/°C<br>rDS(on)<br>Static Drain to Source On Resistance<br>VGS= 10 V,  ID= 2.7 A<br>81<br>105<br>mΩ<br>VGS= 4.5 V, ID= 2.1 A<br>110<br>160<br>VGS= 10 V,  ID= 2.7 A, TJ= 125 °C<br>140<br>182<br>gFS<br>Forward Transconductance<br>VDS= 10 V,  ID= 2.7 A<br>7.8<br>S<br>Ciss<br>Input Capacitance<br>VDS= 50 V, VGS= 0 V,<br>f = 1MHz<br>227<br>302<br>pF<br>Coss<br>Output Capacitance<br>44<br>58<br>pF<br>Crss<br>Reverse Transfer Capacitance<br>3<br>4<br>pF<br>Rg<br>Gate Resistance<br>0.9<br>Ω<br>td(on)<br>Turn-On DelayTime<br>VDD= 50 V, ID= 2.7 A,<br>VGS= 10 V, RGEN= 6Ω<br>3.8<br>10<br>ns<br>tr<br>Rise Time<br>1.2<br>10<br>ns<br>td(off)<br>Turn-Off DelayTime<br>9.5<br>17<br>ns<br>tf<br>Fall Time<br>1.6<br>10<br>ns<br>Qg(TOT)<br>Total Gate Charge<br>VGS = 0 V to 10 V<br>VDD= 50 V,<br>ID= 2.7 A<br>3.8<br>5.3<br>nC<br>Qg(TOT)<br>Total Gate Charge<br>VGS = 0 V to 5 V<br>2.1<br>2.9<br>nC<br>Qgs<br>Gate to Source Charge<br>0.7<br>nC<br>Qgd<br>Gate to Drain “Miller” Charge<br>0.7<br>nC<br>~~re~~<br>~~——-—e~~<br>~~—————~~<br>~~ae~~<br>~~———~~|**Off Characteristics**<br>**On Characteristics**<br>**Dynamic Characteristics**<br>**Switching Characteristics**<br>**Symbol**<br>**Parameter**<br>**Test Conditions**<br>**Min**<br>**Typ**<br>**Max**<br>**Units**<br>BVDSS<br>Drain to Source Breakdown Voltage<br>ID= 250μA, VGS= 0 V<br>100<br>V<br>ΔBVDSS<br>ΔTJ<br>Breakdown Voltage Temperature<br>Coefficient<br>ID= 250μA, referenced to 25 °C<br>68<br>mV/°C<br>IDSS<br>Zero Gate Voltage Drain Current<br>VDS= 80 V, VGS = 0 V<br>1<br>μA<br>IGSS<br>Gate to Source Leakage Current<br>VGS= ±20 V, VDS = 0 V<br>±10<br>μA<br>VGS(th)<br>Gate to Source Threshold Voltage<br>VGS= VDS,  ID= 250μA<br>1<br>1.7<br>2.2<br>V<br>ΔVGS(th)<br>ΔTJ<br>Gate to Source Threshold Voltage<br>Temperature Coefficient<br>ID= 250μA, referenced to 25 °C<br>-6<br>mV/°C<br>rDS(on)<br>Static Drain to Source On Resistance<br>VGS= 10 V,  ID= 2.7 A<br>81<br>105<br>mΩ<br>VGS= 4.5 V, ID= 2.1 A<br>110<br>160<br>VGS= 10 V,  ID= 2.7 A, TJ= 125 °C<br>140<br>182<br>gFS<br>Forward Transconductance<br>VDS= 10 V,  ID= 2.7 A<br>7.8<br>S<br>Ciss<br>Input Capacitance<br>VDS= 50 V, VGS= 0 V,<br>f = 1MHz<br>227<br>302<br>pF<br>Coss<br>Output Capacitance<br>44<br>58<br>pF<br>Crss<br>Reverse Transfer Capacitance<br>3<br>4<br>pF<br>Rg<br>Gate Resistance<br>0.9<br>Ω<br>td(on)<br>Turn-On DelayTime<br>VDD= 50 V, ID= 2.7 A,<br>VGS= 10 V, RGEN= 6Ω<br>3.8<br>10<br>ns<br>tr<br>Rise Time<br>1.2<br>10<br>ns<br>td(off)<br>Turn-Off DelayTime<br>9.5<br>17<br>ns<br>tf<br>Fall Time<br>1.6<br>10<br>ns<br>Qg(TOT)<br>Total Gate Charge<br>VGS = 0 V to 10 V<br>VDD= 50 V,<br>ID= 2.7 A<br>3.8<br>5.3<br>nC<br>Qg(TOT)<br>Total Gate Charge<br>VGS = 0 V to 5 V<br>2.1<br>2.9<br>nC<br>Qgs<br>Gate to Source Charge<br>0.7<br>nC<br>Qgd<br>Gate to Drain “Miller” Charge<br>0.7<br>nC<br>~~re~~<br>~~——-—e~~<br>~~—————~~<br>~~ae~~<br>~~———~~|
|---|---|
|**Drain-Source Diode Characteristics**||
|VSD<br>Source to Drain Diode  Forward Voltage<br>VGS = 0 V, IS = 2.7 A(Note 2)<br>0.8<br>1.3<br>V<br>VGS = 0 V, IS = 2 A(Note 2)<br>0.8<br>1.2<br>trr<br>Reverse RecoveryTime<br>IF= 2.7 A, di/dt = 100 A/μs<br>31<br>56<br>ns<br>Qrr<br>Reverse RecoveryCharge<br>20<br>36<br>nC<br>~~———~~||
|NOTES:||
|1. RθJAis determined with the device mounted on a 1in2pad 2 oz copper pad on a 1.5 x 1.5 in. board of FR-4 material. RθJCis guaranteed by design while RθCAis determined by||
|the user's board design.||



a) 78°C/W when b) 135°C/W when mounted on a  1 in[2] mounted on a pad of 2 oz copper minimun pad 

3. Starting TJ = 25 °C,  L = 0.3 mH, IAS =25 A, VDD = 27 V, VGS = 10V. 

4. The diode connected between gate and source serves only as protection against ESD. No gate overvoltage rating is implied. 

2. Pulse Test: Pulse Width < 300μs, Duty cycle < 2.0%. 

©2011 Fairchild Semiconductor Corporation **2** www.fairchildsemi.com FDS89161LZ  Rev. 1.2 

**Typical Characteristics ( N-Channel)** TJ = 25°C unless otherwise noted 

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15 4<br>VGS =  10 V VGS =  8 V VGS = 3.5 V VGS =  4 V<br>12 V GS = 6 V<br>VGS =5 V 3<br>9 VGS = 4 V<br>VGS =  5 V<br>2<br>VGS = 6 V<br>6<br>VGS = 3.5 V<br>3 PULSE DURATION = 80  μ s 1 PULSE DURATION = 80  μ s VGS = 8 V VGS =  10 V<br>DUTY CYCLE = 0.5% MAX DUTY CYCLE = 0.5% MAX<br>0 0<br>0 1 2 3 4 5 0 3 6 9 12 15<br>VDS, DRAIN TO SOURCE VOLTAGE (V) ID, DRAIN CURRENT (A)<br>Figure 1.  On-Region Characteristics Figure 2.  Normalized On-Resistance<br>vs Drain Current and Gate Voltage<br>2.0 500<br>1.8 ID = 2.7 A ID = 2.7 A PULSE DURATION = 80 DUTY CYCLE = 0.5% MAX μ s<br>VGS = 10 V 400<br>1.6<br>300<br>1.4<br>TJ = 125  [o] C<br>1.2 200<br>1.0<br>100<br>0.8 TJ = 25 [ o] C<br>0.6 0<br>-75 -50 -25 0 25 50 75 100 125 150 2 4 6 8 10<br>TJ, JUNCTION TEMPERATURE ( [o] C) VGS, GATE TO SOURCE VOLTAGE (V)<br>Figure 3.  Normalized  On-Resistance                                         Figure 4.   On-Resistance vs  Gate to<br>vs Junction Temperature Source Voltage<br>15 20<br>10 VGS = 0 V<br>12<br>1 TJ = 150  [o] C<br>9 VDS = 50 V TJ = 25 [ o] C<br>PULSE DURATION = 80  μ s 0.1<br>6 DUTY CYCLE = 0.5% MAX<br>TJ = 150 [ o] C<br>3 0.01 TJ = -55 [ o] C<br>TJ = 25 [ o] C TJ = -55  [o] C<br>0 0.001<br>0 2 4 6 8 10 0.0 0.2 0.4 0.6 0.8 1.0 1.2<br>VGS, GATE TO SOURCE VOLTAGE (V) VSD, BODY DIODE FORWARD VOLTAGE (V)<br>NORMALIZED<br>DRAIN CURRENT (A)<br>,<br>ID<br>DRAIN TO SOURCE ON-RESISTANCE<br>)<br>Ω<br>m<br>(<br>DRAIN TO<br>NORMALIZED rDS(on),<br>SOURCE ON-RESISTANCE<br> DRAIN TO SOURCE ON-RESISTANCE<br>, DRAIN CURRENT (A)<br>ID<br>, REVERSE DRAIN CURRENT (A)<br>IS<br>**----- End of picture text -----**<br>


**Figure 5.  Transfer Characteristics** 

**Figure 6. Forward Voltage vs Source Current** 

©2011 Fairchild Semiconductor Corporation **3** www.fairchildsemi.com FDS89161LZ  Rev. 1.2 

**Typical Characteristics ( N-Channel)** TJ = 25°C unless otherwise noted 

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10 400<br>ID = 2.7 A VDD = 25 V<br>Ciss<br>8<br>100<br>VDD = 50 V<br>6<br>C oss<br>VDD = 75 V<br>4 10<br>2<br>f = 1 MHz<br>V GS  = 0 V C rss<br>0 1<br>0 1 2 3 4 5 0.1 1 10 100<br>Qg, GATE CHARGE (nC) VDS, DRAIN TO SOURCE VOLTAGE (V)<br>Figure 7.  Gate Charge Characteristics Figure 8.  Capacitance vs Drain<br>to Source Voltage<br>3.0 4<br>2.5 3<br>TJ = 25  [o] C VGS = 10 V<br>2.0 2<br>TJ = 100  [o] C VGS = 6 V<br>1.5 1<br>TJ = 125 [ o] C R θ JA = 78 oC/W<br>1.0 0<br>0.01 0.1 1 2 25 50 75 100 125 150<br>tAV, TIME IN AVALANCHE (ms) TA, Ambient TEMPERATURE (oC)<br>Figure 9. Unclamped Inductive                                  Figure 10.  Maximum Continuous Drain<br>Switching Capability Current  vs Ambient Temperature<br>10-1 20<br>10-2 VDS = 0 V 10<br>10-3 100 us<br>10-4 1 1 ms<br>10-5 TJ = 125 [ o] C THIS AREA IS  10 ms<br>10-6 TJ = 25  [o] C 0.1 LIMITED BY r SING DS LE P (on) ULSE 100 ms<br>10-7 T J = MAX RATED 1 s<br>10-8 R θ JA = 135 [ o] C/W 10 s<br>0.01 TA = 25  [o] C DC<br>10-9 0.005<br>0 5 10 15 20 25 30 35 0.1 1 10 100 400<br>VGS, GATE TO SOURCE VOLTAGE (V) VDS, DRAIN to SOURCE VOLTAGE (V)<br>Figure 11.  Gate  Leakage Current vs                                        Figure 12.  Forward Bias Safe<br>Gate to Source Voltage   Operating Area<br>CAPACITANCE (pF)<br>, GATE TO SOURCE VOLTAGE (V)<br>GS<br>V<br>DRAIN CURRENT (A)<br>,<br>ID<br>, AVALANCHE CURRENT (A)<br>IAS<br>, DRAIN CURRENT (A)<br>ID<br>GATE LEAKAGE CURRENT (A)<br>,<br>Ig<br>**----- End of picture text -----**<br>


©2011 Fairchild Semiconductor Corporation **4** www.fairchildsemi.com FDS89161LZ  Rev. 1.2 

## **Typical Characteristics ( N-Channel)** TJ = 25°C unless otherwise noted 

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1000<br>100<br>10<br>SINGLE PULSE<br>R θ JA = 135  [o] C/W<br>1 TA = 25  [o] C<br>0.5<br>10-4 10-3 10-2 10-1 1 10 102 103<br>t, PULSE WIDTH (sec)<br>Figure 13.   Single  Pulse Maximum Power  Dissipation<br>2<br>DUTY CYCLE-DESCENDING ORDER<br>1<br>D = 0.5<br>0.1       0.2<br>      0.1 PDM<br>      0.05<br>      0.02<br>      0.01 t 1<br>0.01 t2<br>SINGLE PULSE NOTES:<br>DUTY FACTOR: D = t1/t2<br>R θ JA = 135  [o] C/W PEAK T J  = P DM  x Z θJA  x R θJA  + T A<br>0.001<br>10-4 10-3 10-2 10-1 1 10 100 1000<br>t, RECTANGULAR PULSE DURATION (sec)<br>Figure 14.  Junction-to-Ambient Transient Thermal Response Curve<br>, PEAK TRANSIENT POWER (W)<br>(PK)<br>P<br>Z JA θ<br>IMPEDANCE,<br>NORMALIZED THERMAL<br>**----- End of picture text -----**<br>


©2011 Fairchild Semiconductor Corporation **5** www.fairchildsemi.com FDS89161LZ  Rev. 1.2 

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ON Semiconductor and      are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. 

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