FDS6982AS

## **Is Now Part of** 

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## FAIRCHILD 

## **FDS6982AS** 

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May  2008<br>tmM<br>**----- End of picture text -----**<br>


## **Dual Notebook Power Supply N-Channel PowerTrench**[®] **SyncFET[™] General Description Features** 

The FDS6982AS is designed to replace two single SO8  MOSFETs and Schottky diode in synchronous DC:DC power supplies that provide various peripheral voltages for notebook computers and other battery powered electronic devices. FDS6982AS contains two unique 30V, N-channel, logic level, PowerTrench MOSFETs designed to maximize power conversion efficiency. The high-side switch (Q1) is designed with specific emphasis on reducing switching losses while the low-side switch (Q2) is optimized to reduce conduction losses.  Q2 also includes an integrated Schottky diode using Fairchild’s monolithic SyncFET technology. 

## **Applications** 

   - **Q2** : Optimized to minimize conduction losses Includes SyncFET Schottky body diode 

   - 8.6A,  30V RDS(on) max= 13.5mΩ @ VGS = 10V RDS(on) max= 16.5mΩ @ VGS = 4.5V 

   - •   Low gate charge (21nC typical) • **Q1** : Optimized for low switching losses 

   - 6.3A,  30V RDS(on) max= 28.0mΩ @ VGS = 10V RDS(on) max= 35.0mΩ @ VGS = 4.5V 

   - Low gate charge (11nC typical) 

- Notebook 

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D1<br>D1 5 4<br>D2<br>6 Q1 3<br>D2<br>i<br>7 2<br>a Q2<br>ad S1 [G1] 8 1<br>SO-8<br>y G2<br>S2<br>**----- End of picture text -----**<br>


## **Absolute Maximum Ratings** TA = 25°C unless otherwise noted 

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Symbol  Parameter  Q2 Q1  Units<br>VDSS Drain-Source Voltage  30  30  V<br>VGSS Gate-Source Voltage  ±20  ±20  V<br>ID Drain Current  - Continuous   (Note 1a) 8.6  6.3  A<br>- Pulsed  30  20<br>PD Power Dissipation for Dual Operation  2  W<br>Power Dissipation for Single Operation  (Note 1a) 1.6<br>(Note 1b) 1<br>(Note 1c) 0.9<br>TJ, TSTG Operating and Storage Junction Temperature Range  –55 to +150  °C<br>Thermal Characteristics<br>RθJA Thermal Resistance, Junction-to-Ambient   (Note 1a) 78  °C/W<br>RθJC Thermal Resistance, Junction-to-Case  (Note 1) 40  °C/W<br>Package Marking and Ordering Information<br>Device Marking Device Reel Size Tape width  Quantity<br>FDS6982AS  FDS6982AS  13” 12mm  2500 units<br>**----- End of picture text -----**<br>


©2008 Fairchild Semiconductor Corporation 

FDS6982AS Rev B1 

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Electrical Characteristics  TA = 25°C unless otherwise noted<br>Symbol Parameter  Test Conditions  Type Min Typ Max Units<br>Off Characteristics<br>BVDSS Drain-Source Breakdown  VGS = 0 V,  ID = 1 mA  Q2  30  V<br>Voltage   VGS = 0 V, ID = 250 uA  Q1  30<br>∆BVDSS Breakdown Voltage  ID = 1 mA, Referenced to 25°C  Q2  28  mV/°C<br>   ∆TJ Temperature Coefficient   ID = 250 µA, Referenced to 25°C  Q1  24<br>IDSS Zero Gate Voltage Drain  VDS = 24 V,  VGS = 0 V  Q2  500  µA<br>Current  Q1  1<br>IGSS Gate-Body Leakage  VGS = ±20 V, VDS = 0 V  Q2  ±100  nA<br>Q1<br>On Characteristics (Note 2)<br>VGS(th) Gate Threshold Voltage   VDS = VGS,  ID = 1 mA  Q2  1  1.4  3  V<br>VDS = VGS, ID = 250 µA  Q1  1  1.9  3<br>∆VGS(th) Gate Threshold Voltage  ID = 1 mA, Referenced to 25°C  Q2  –3.1  mV/°C<br>   ∆TJ Temperature Coefficient  ID = 250 uA, Referenced to 25°C  Q1  –4.3<br>RDS(on) Static Drain-Source   VGS = 10 V, ID = 8.6 A  Q2  11  13.5  mΩ<br>On-Resistance  VGS = 10 V, ID = 8.6 A, TJ = 125°C  16  20.0<br>VGS = 4.5 V, ID = 7.5 A  13  16.5<br>VGS = 10 V, ID = 6.3 A  Q1  20  28<br>VGS = 10 V, ID = 6.3 A, TJ = 125°C  26  33<br>VGS = 4.5 V, ID = 5.6 A  25  35<br>ID(on) On-State Drain Current  VGS = 10 V,  VDS = 5 V  Q2  30  A<br>Q1  20<br>gFS Forward Transconductance  VDS = 5 V,  ID = 8.6 A  Q2  32  S<br>VDS = 5 V, ID = 6.3 A  Q1  19<br>Dynamic Characteristics<br>Ciss Input Capacitance  VDS = 10 V,  VGS = 0 V,  Q2  1250  pF<br> f = 1.0 MHz  Q1  610<br>Coss Output Capacitance  Q2  410  pF<br>Q1  180<br>Crss Reverse Transfer Capacitance  Q2  130  pF<br>Q1  85<br>RG Gate Resistance  VGS = 15mV,  f = 1.0 MHz  Q2  1.4  Ω<br>Q1  2.2<br>Switching Characteristics (Note 2)<br>td(on) Turn-On Delay Time  VDD = 15 V,  ID = 1 A,  Q2  9  18  ns<br>VGS = 10V, RGEN = 6 Ω Q1  10  20<br>tr Turn-On Rise Time  Q2  6  12  ns<br>Q1  7  14<br>td(off) Turn-Off Delay Time  Q2  27  44  ns<br>Q1  24  39<br>tf Turn-Off Fall Time  Q2  11  20  ns<br>Q1  3  6<br>td(on) Turn-On Delay Time  VDD = 15 V,  ID = 1 A,  Q2  12  22  ns<br>VGS = 4.5V, RGEN = 6 Ω Q1  12  22<br>tr Turn-On Rise Time  Q2  13  23  ns<br>Q1  14  25<br>td(off) Turn-Off Delay Time  Q2  19  34  ns<br>Q1  15  27<br>tf Turn-Off Fall Time  Q2  10  20  ns<br>Q1  5  10<br>**----- End of picture text -----**<br>


FDS6982AS Rev B1 

|**Electrical Characteristics(continued)**<br>TA= 25°C unless otherw|**Electrical Characteristics(continued)**<br>TA= 25°C unless otherw|**Electrical Characteristics(continued)**<br>TA= 25°C unless otherw|ise noted|||||
|---|---|---|---|---|---|---|---|
|**Symbol**|**Parameter**|**Test Conditions**|**Type**<br>|**Min**|**Typ**|**Max**|**Units**|
|**Switching Characteristics ** (Note 2)||||||||
|Qg(TOT)<br>|Total Gate Charge at Vgs=10V|<br>Q2:<br>VDS= 15 V, ID= 11.5A<br>Q1:<br>VDS= 15 V, ID= 6.3A|Q2<br>Q1||21<br>11|30<br>15|nC|
|Qg<br>|Total Gate Charge at Vgs=5V||Q2<br>Q1||12<br>6|16<br>9|nC|
|Qgs<br>|Gate–Source Charge||Q2<br>Q1||3.1<br>1.8||nC|
|Qgd<br>|Gate–Drain Charge||Q2<br>Q1||3.6<br>2.4||nC|
|**Drain–Source Diode Characteristics and Maximum Ratings**||||||||
|IS<br>|Maximum Continuous Drain-Source Diode Forward Current||Q2<br>Q1|||3.0<br>1.3|A|
|Trr<br>|Reverse Recovery Time|IF= 11.5 A,<br>diF/dt= 300 A/µs<br>(Note 3)|Q2||19||ns|
|Qrr<br>|Reverse Recovery Charge||||12||nC|
|Trr<br>|Reverse Recovery Time|IF= 6.3 A,<br>diF/dt= 100 A/µs<br>(Note 3)|Q1||20||ns|
|Qrr<br>|Reverse Recovery Charge||||9||nC|
|VSD<br> <br>|Drain-Source Diode Forward<br>Voltage|VGS= 0 V, IS= 3 A<br>(Note 2)<br>VGS= 0 V, IS= 6 A<br>(Note 2)<br>VGS= 0 V,IS= 1.3 A<br>(Note 2)|Q2<br>Q2<br>Q1||0.5<br>0.6<br>0.8|0.7<br>1.0<br>1.2|V|



**Notes:** 

**1.** RθJA is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins.  RθJC is guaranteed by design while RθCA is determined by the user's board design. 

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a) 78°C/W when b) 125°C/W when c) 135°C/W when mounted on a mounted on a mounted on a 0.5in[2] pad of 2 0.02 in[2] pad of minimum pad. oz copper 2 oz copper 

Scale 1 : 1 on letter size paper 

**2.** Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0% 

**3.** See “SyncFET Schottky body diode characteristics” below. 

**4** 

**5** 

FDS6982AS Rev B1 

## **Typical Characteristics:   Q2** 

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30 2.6<br>VGS = 10V 3.0V 2.4 VGS = 2.5V<br>2.2<br>4.5V 3.5V<br>20 2<br>1.8<br>1.6<br>3.0V<br>10 2.5V 1.4 3.5V<br>1.2 4.0V 4.5V<br>6.0V<br>1 10V<br>0 0.8<br>0 0.5 1 1.5 2 0 10 20 30<br>VDS, DRAIN-SOURCE VOLTAGE (V) ID, DRAIN CURRENT (A)<br>Figure 1. On-Region Characteristics.  Figure 2. On-Resistance Variation with<br>Drain Current and Gate Voltage.<br>1.4 0.05<br>ID = 8.6A ID = 4.3 A<br>VGS = 10V<br>0.04<br>1.2<br>0.03<br>1 TA = 125 [o] C<br>0.02<br>0.8<br>0.01 TA = 25 [o] C<br>0.6 0<br>-50 -25 0 25 50 75 100 125 2 4 6 8 10<br>TJ, JUNCTION TEMPERATURE ( [o] C) VGS, GATE TO SOURCE VOLTAGE (V)<br>Figure 3. On-Resistance Variation with  Figure 4. On-Resistance Variation with<br>Temperature.  Gate-to-Source Voltage.<br>30 10<br>VDS = 5V VGS = 0V<br>25<br>20 1 TA = 125 [o] C<br>15 TA = 125 [o] C 25 [o] C<br>10 -55 [o] C 0.1 -55 [o] C<br>5<br>25 [o] C<br>0 0.01<br>1 1.5 2 2.5 3 3.5 0 0.2 0.4 0.6 0.8<br>VGS, GATE TO SOURCE VOLTAGE (V) VSD, BODY DIODE FORWARD VOLTAGE (V)<br>Figure 5. Transfer Characteristics.  Figure 6. Body Diode Forward Voltage Variation<br>with Source Current and Temperature.<br>, NORMALIZED<br>, DRAIN CURRENT (A)ID RDS(ON)<br>DRAIN-SOURCE ON-RESISTANCE<br>, NORMALIZED<br>DS(ON) , ON-RESISTANCE (OHM)<br>R DS(ON)<br>R<br> DRAIN-SOURCE ON-RESISTANCE<br>, DRAIN CURRENT (A)ID<br>, REVERSE DRAIN CURRENT (A)IS<br>**----- End of picture text -----**<br>


FDS6982AS Rev B1 

## **Typical Characteristics:   Q2** 

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10 2000<br>ID = 8.6A Vf = 1MHzGS = 0 V<br>8 1600<br>VDS = 10V<br>20V<br>6 1200<br>Ciss<br>15V<br>4 800<br>Coss<br>2 400<br>Crss<br>0 0<br>0 5 10 15 20 25 0 5 10 15 20 25 30<br>Qg, GATE CHARGE (nC) VDS, DRAIN TO SOURCE VOLTAGE (V)<br>Figure 7. Gate Charge Characteristics.  Figure 8. Capacitance Characteristics.<br>100 50<br>RDS(ON) LIMIT SINGLE PULSE<br>100 µ s RθJA = 135°C/W<br>10 1ms 40 T A  = 25°C<br>10ms<br>100ms 30<br>1s<br>1 10s<br>DC 20<br>VGS = 10V<br>0.1 SINGLE PULSE<br>RθJA = 135 [o] C/W 10<br>TA = 25 [o] C<br>0.01 0<br>0.1 1 10 100 0.001 0.01 0.1 1 10 100 1000<br>VDS, DRAIN-SOURCE VOLTAGE (V) t1, TIME (sec)<br>Figure 9. Maximum Safe Operating Area.  Figure 10. Single Pulse Maximum<br>Power Dissipation.<br>1<br>D = 0.5<br>0.2 RθJA(t) = r(t) * RθJA<br>0.1 0.1 RθJA = 135°C/W<br>0.05<br>P(pk)<br>0.02<br>0.01 t1<br>0.01 t2<br>SINGLE PULSE TJ - TA = P * RθJA(t)<br>Duty Cycle, D = t1 / t2<br>0.001<br>0.0001 0.001 0.01 0.1 1 10 100 1000<br>t1, TIME (sec)<br>Figure 11. Transient Thermal Response Curve.<br> Thermal characterization performed using the conditions described in Note 1c.<br>  Transient thermal response will change depending on the circuit board design.<br>CAPACITANCE (pF)<br>, GATE-SOURCE VOLTAGE (V)<br>GS<br>V<br>, DRAIN CURRENT (A)ID<br>P(pk), PEAK TRANSIENT POWER (W)<br>r(t), NORMALIZED EFFECTIVE<br>TRANSIENT THERMAL RESISTANCE<br>**----- End of picture text -----**<br>


FDS6982AS Rev B1 

## **Typical Characteristics Q1** 

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20 2.6<br>VGS = 10V 4.0V 3.5V VGS = 3.0V<br>16 2.2<br>6.0V<br>12 4.5V 1.8<br>3.5V<br>8 1.4 4.0V<br>3.0V 4.5V<br>6.0V<br>4 1 10V<br>0 0.6<br>0 1 2 0 5 10 15 20<br>VDS, DRAIN-SOURCE VOLTAGE (V) ID, DRAIN CURRENT (A)<br>Figure 12. On-Region Characteristics.  Figure 13. On-Resistance Variation with<br>Drain Current and Gate Voltage.<br>1.6 0.1<br>VIDGS = 6.3A = 10V ID = 3.15 A<br>1.4 0.08<br>1.2 0.06<br>TA = 125 [o] C<br>1 0.04<br>0.8 0.02 TA = 25 [o] C<br>0.6 0<br>-50 -25 0 25 50 75 100 125 150 2 4 6 8 10<br>TJ, JUNCTION TEMPERATURE ( [o] C) VGS, GATE TO SOURCE VOLTAGE (V)<br>Figure 14. On-Resistance Variation with  Figure 15. On-Resistance Variation with<br>Temperature.  Gate-to-Source Voltage.<br>20 100<br>VDS = 5V V GS  = 0V<br>10<br>15<br>1 T A  = 125 [o] C<br>25 [o] C<br>10 0.1<br>TA = 125 [o] C -55 [o] C<br>-55 [o] C 0.01<br>5<br>0.001<br>25 [o] C<br>0 0.0001<br>1 1.5 2 2.5 3 3.5 0 0.2 0.4 0.6 0.8 1 1.2 1.4<br>VGS, GATE TO SOURCE VOLTAGE (V) VSD, BODY DIODE FORWARD VOLTAGE (V)<br>Figure 16. Transfer Characteristics.  Figure 17. Body Diode Forward Voltage Variation<br>with Source Current and Temperature.<br>, NORMALIZED<br>, DRAIN CURRENT (A)ID RDS(ON)<br>DRAIN-SOURCE ON-RESISTANCE<br>, NORMALIZED<br>DS(ON) , ON-RESISTANCE (OHM)<br>R DS(ON)<br>R<br> DRAIN-SOURCE ON-RESISTANCE<br>, DRAIN CURRENT (A)ID<br>, REVERSE DRAIN CURRENT (A)IS<br>**----- End of picture text -----**<br>


FDS6982AS Rev B1 

## **Typical Characteristics  Q1** 

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10 800<br>ID = 6.3A Vf = 1MHzGS = 0 V<br>8<br>600<br>VDS = 10V Ciss<br>6 20V<br>400<br>4 15V Coss<br>200<br>2<br>Crss<br>0 0<br>0 3 6 9 12 0 5 10 15 20<br>Qg, GATE CHARGE (nC) VDS, DRAIN TO SOURCE VOLTAGE (V)<br>Figure 18. Gate Charge Characteristics.  Figure 19. Capacitance Characteristics.<br>100 50<br>SINGLE PULSE<br>RDS(ON) LIMIT 100µs RθJA = 135°C/W<br>10 1ms 40 TA = 25°C<br>10ms<br>100ms 30<br>1 1s<br>10s<br>V GS  = 10V DC 20<br>0.1 SINGLE PULSE<br>RθJA = 135 [o] C/W 10<br>TA = 25 [o] C<br>0.01<br>0<br>0.1 1 10 100<br>0.001 0.01 0.1 1 10 100 1000<br>VDS, DRAIN-SOURCE VOLTAGE (V) t1, TIME (sec)<br>Figure 20. Maximum Safe Operating Area.  Figure 21. Single Pulse Maximum<br>Power Dissipation.<br>1<br>D = 0.5<br>0.2 R θJA (t) = r(t) * R θJA<br>0.1 0.1 RθJA = 135°C/W<br>0.05<br>P(pk)<br>0.02<br>0.01 t 1<br>0.01 t2<br>SINGLE PULSE TJ - TA = P * RθJA(t)<br>Duty Cycle, D = t 1  / t 2<br>0.001<br>0.0001 0.001 0.01 0.1 1 10 100 1000<br>t1, TIME (sec)<br>CAPACITANCE (pF)<br>, GATE-SOURCE VOLTAGE (V)<br>GS<br>V<br>, DRAIN CURRENT (A)ID<br>P(pk), PEAK TRANSIENT POWER (W)<br>r(t), NORMALIZED EFFECTIVE<br>TRANSIENT THERMAL RESISTANCE<br>**----- End of picture text -----**<br>


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Figure 22. Transient Thermal Response Curve.<br>                                                          Thermal characterization performed using the conditions described in Note 1c.<br>                                                          Transient thermal response will change depending on the circuit board design.<br>**----- End of picture text -----**<br>


FDS6982AS Rev B1 

## **Typical Characteristics** (continued) 

## **SyncFET Schottky Body Diode Characteristics** 

Fairchild’s SyncFET process embeds a Schottky diode in parallel with PowerTrench MOSFET.  This diode exhibits similar characteristics to a discrete external Schottky diode in parallel with a MOSFET. **Figure 23** shows the reverse recovery characteristic of the FDS6982AS. 

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Time: 10nS/DIV<br>For comparison purposes,  Figure 24<br>(FDS6982).<br>Time: 10nS/DIV<br>Current: 1.6A/DIV<br>Current: 1.6A/DIV<br>**----- End of picture text -----**<br>


**Figure 23. FDS6982AS SyncFET body diode reverse recovery characteristic.** 

For comparison purposes, **Figure 24** shows the reverse recovery characteristics of the body diode of an equivalent size MOSFET produced without SyncFET (FDS6982). 

Schottky barrier diodes exhibit significant leakage at high temperature and high reverse voltage.  This will increase the power in the device. 

0.1 0.01 ~~T~~ A ~~= 125[o] C~~ 0.001 ~~T~~ A ~~= 100[o] C~~ 0.0001 0.00001 ~~a TA = 25[o] C~~ 0.000001 0 5 10 15 20 25 30 **VDS, REVERSE VOLTAGE (V) Figure 25. SyncFET body diode reverse leakage versus drain-source voltage and** ~~oe~~ **temperature** 

**Figure 24. Non-SyncFET (FDS6982) body diode reverse recovery characteristic.** 

FDS6982AS Rev B1 

## **Typical Characteristics** 

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L<br>VDS  BVDSS<br>VGS  tP VDS<br>RGE DUT + IAS<br>VDD  VDD<br>0V -<br>VGS  tp IAS<br>vary tP to obtain<br>required peak IAS  0.01Ω<br>tAV<br>Figure 26. Unclamped Inductive Load Test      Figure 27. Unclamped Inductive<br>Circuit  Waveforms<br>Drain Current<br>Same type as<br>+<br>50kΩ<br>10V<br>-  10µF  1µF  +<br>- VDD  QG(TOT)<br>VGS  10V<br>DUT<br>VGS  QGS  QGD<br>Ig(REF<br>Charge, (nC)<br>Figure 28. Gate Charge Test Circuit  Figure 29. Gate Charge Waveform<br>tON  tOFF<br>RL  td(ON)  td(OFF<br>VDS  VDS  90% tr ) tf 90%<br>VGS  +<br>10% 10%<br>RGEN  DUT VDD  0V<br>- 90%<br>VGS<br>VGS  50% 50%<br>Pulse Width ≤ 1µs<br>Duty Cycle ≤ 0.1% 0V 10% Pulse Width<br>Figure 30. Switching Time Test  Figure 31. Switching Time Waveforms<br>Circuit<br>**----- End of picture text -----**<br>


FDS6982AS Rev B1 

## **TRADEMARKS** 

The following includes registered and unregistered trademarks and service marks, owned by Fairchild Semiconductor and/or its global subsidianries, and is not intended to be an exhaustive list of all such trademarks. 

ACEx[®] FPS™ PDP-SPM™ The Power Franchise[®] Build it Now™ F-PFS™ Power-SPM™ the wer CorePLUS™ FRFET[®] PowerTrench[®] Paw tm CorePOWER™ Global Power Resource[SM] Programmable Active Droop™ TinyBoost™ _CROSSVOLT_ ™ Green FPS™ QFET[®] TinyBuck™ CTL™ Green FPS™ e-Series™ QS™ TinyLogic[®] Current Transfer Logic™ GTO™ Quiet Series™ TINYOPTO™ EcoSPARK[®] IntelliMAX™ RapidConfigure™ TinyPower™ EfficentMax™ ISOPLANAR™ Saving our world 1mW at a time™ TinyPWM™ EZSWITCH™ * MegaBuck™ SmartMax™ TinyWire™ ™ MICROCOUPLER™ SMART START™ µSerDes™ MicroFET™ SPM[®] ® MicroPak™ STEALTH™ ~~-~~ "ZZ... Fairchild[®] MillerDrive™ SuperFET™ UHC[®] Fairchild Semiconductor[®] MotionMax™ SuperSOT™-3 Ultra FRFET™ FACT Quiet Series™ Motion-SPM™ SuperSOT™-6 UniFET™ FACT[®] OPTOLOGIC[®] SuperSOT™-8 VCX™ FAST[®] OPTOPLANAR[®] SuperMOS™ VisualMax™ FastvCore™ ® ® FlashWriter[® ] * tm Te ceNeRAL 

* EZSWITCH™ and FlashWriter[®] are trademarks of System General Corporation, used under license by Fairchild Semiconductor. 

## **DISCLAIMER** 

FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. THESE SPECIFICATIONS DO NOT EXPAND THE TERMS OF FAIRCHILD’S WORLDWIDE TERMS AND CONDITIONS, SPECIFICALLY THE WARRANTY THEREIN, WHICH COVERS THESE PRODUCTS. 

**LIFE SUPPORT POLICY** FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. 

- As used herein: 

1. Life support devices or systems are devices or systems which, 2. A critical component in any component of a life support, (a) are intended for surgical implant into the body or (b) device, or system whose failure to perform can be reasonably support or sustain life, and (c) whose failure to perform when expected to cause the failure of the life support device or properly used in accordance with instructions for use provided system, or to affect its safety or effectiveness. in the labeling, can be reasonably expected to result in a significant injury of the user. 

## **PRODUCT STATUS DEFINITIONS Definition of Terms** 

|**Definition of Terms**|||
|---|---|---|
|**Datasheet Identification**|**Product Status**|**Definition**|
|Advance Information|Formative or In Design|This datasheet contains the design specifications for product development.<br>Specifications may change in any manner without notice.|
|Preliminary|First Production|This datasheet contains preliminary data; supplementary data will be pub-<br>lished at a later date. Fairchild Semiconductor reserves the right to make<br>changes at any time without notice to improve design.|
|No Identification Needed|Full Production|This datasheet contains final specifications. Fairchild Semiconductor reserves<br>the right to make changes at any time without notice to improve the design.|
|Obsolete|Not In Production|This datasheet contains specifications on a product that is discontinued by<br>Fairchild Semiconductor. The datasheet is for reference information only.|



Rev. I34 

FDS6982AS Rev.B1 

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