FDS6912A

**DATA SHEET www.onsemi.com** 

## MOSFET – Dual, N-Channel, Logic Level, POWERTRENCH[�] 

## 30 V, 6 A, 28 m **�** 

## FDS6912A 

## **General Description** 

These N−Channel Logic Level MOSFETs are produced using **onsemi** ’s advanced POWERTRENCH process that has been especially tailored to minimize the on−state resistance and yet maintain superior switching performance. 

These devices are well suited for low voltage and battery powered applications where low in−line power loss and fast switching are required. 

## **Features** 

- 6.0 A, 30 V 

   - RDS(ON) = 28 m� @ VGS = 10 V 

   - RDS(ON) = 35 m� @ VGS = 4.5 V 

- Fast Switching Speed 

- Low Gate Charge 

- High Performance Trench Technology for Extremely Low RDS(ON) 

- High Power and Current Handling Capability 

|**VDSS**|**RDS(ON) MAX**|**ID MAX**|
|---|---|---|
|30 V|28 m�@ VGS= 10 V|6.0 A|
||35 m�@ VGS= 4.5 V|5.0 A|



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D1 [D1]<br>D2<br>D2<br>G1<br>S1<br>G2<br>S2<br>Pin 1<br>SOIC8<br>CASE 751EB<br>**----- End of picture text -----**<br>


## **MARKING DIAGRAM** 

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FDS6912A<br>ALYW<br>FDS6912A = Specific Device Code<br>A = Assembly Site<br>L = Wafer Lot Number<br>YW = Assembly Start Week<br>**----- End of picture text -----**<br>


- This Device is Pb−Free and Halogen Free 

## **PIN ASSIGNMENT** 

## **ABSOLUTE MAXIMUM RATINGS** (TA = 25 ° C unless otherwise noted) 

|**Symbol**|**Parameter**|**Parameter**|**Ratings**|**Unit**|
|---|---|---|---|---|
|VDSS|Drain−Source Voltage||30|V|
|VGSS|Gate−Source Voltage||±20|V|
|ID|Drain Current|− Continuous (Note 1a)|6|A|
|||− Pulsed|20||
|PD|Power Dissipation<br>for Single<br>Operation|(Note 1a)|1.6|W|
|||(Note 1b)|1.0||
|||(Note 1c)|0.9||
|TJ, TSTG|Operating and Storage<br>Junction Temperature Range||−55 to +150|°C|



Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 

## **THERMAL CHARACTERISTICS** 

|**Symbol**|**Parameter**|**Ratings**|**Unit**|
|---|---|---|---|
|R�JA|Thermal Resistance, Junction−to−Ambient<br>(Note 1a)|78|°C/W|
|R�JC|Thermal Resistance, Junction−to−Case<br>(Note 1)|40|°C/W|



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**Dual N−Channel MOSFET** 

## **ORDERING INFORMATION** 

|**Device**|**Pack**|**age**<br>**Shipping**†|
|---|---|---|
|FDS6912A|SOI<br>(Pb−F|C8<br>ree)<br>2500 /<br>Tape & Reel|



†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. 

Publication Order Number: 

**1** 

© Semiconductor Components Industries, LLC, 2003 **January, 2022 − Rev. 5** 

**FDS6912A/D** 

**FDS6912A** 

**ELECTRICAL CHARACTERISTICS** (TA = 25 ° C unless otherwise noted) 

|**ELECTRI**|**ELECTRI**|**CAL CHARACTERISTICS** (TA= 25°C u|nless otherwise noted)|||||
|---|---|---|---|---|---|---|---|
|**Symbol**||**Parameter**|**Test Conditions**|**Min**|**Typ**|**Max**|**Unit**|
|**OFF CHARACTERISTICS**||||||||
||BVDSS|Drain–Source Breakdown Voltage|VGS= 0 V, ID= 250�A|30|−|−|V|
||�BVDSS<br>�TJ|Breakdown Voltage Temperature<br>Coefficient|ID= 250�A, Referenced to 25°C|−|25|−|mV/°C|
||IDSS|Zero Gate Voltage Drain Current|VDS= 24 V, VGS= 0 V<br>VDS= 24 V, VGS= 0 V, TJ= 55°C|−<br>−|−<br>−|1<br>10|�A|
||IGSS|Gate–Source Leakage|VGS=±20 V, VDS= 0 V|−|−|±100|nA|
|**ON CHARACTERISTICS**(Note 2)||||||||
||VGS(th)|Gate Threshold Voltage|VDS= VGS, ID= 250�A|1|1.9|3|V|
||�VGS(th)<br>�TJ|Gate Threshold Voltage Temperature<br>Coefficient|ID= 250�A, Referenced to 25°C|−|−4.5|−|mV/°C|
||RDS(on)|Static Drain–Source On–Resistance|VGS= 10 V, ID= 6 A<br>VGS= 4.5 V, ID= 5 A<br>VGS= 10 V, ID= 6 A, TJ= 125°C|−<br>−<br>−|19<br>24<br>27|28<br>35<br>44|m�|
||ID(on)|On−State Drain Current|VGS= 10 V, VDS= 5 V|20|−|−|A|
||gFS|Forward Transconductance|VDS= 10 V, ID= 6 A|−|25|−|S|
|**DYNAMIC CHARACTERISTICS**||||||||
|Ciss||Input Capacitance|VDS= 15 V, VGS= 0 V, f = 1.0 MHz|−|575|−|pF|
|Coss||Output Capacitance||−|145|−|pF|
|Crss||Reverse Transfer Capacitance||−|65|−|pF|
|RG||Gate Resistance|VGS= 15 mV, f = 1.0 MHz|−|2.1|−|�|
|**SWITCHING CHARACTERISTICS**(Note 2)||||||||
|td(on)||Turn–On Delay Time|VDD= 15 V, ID= 1 A,<br>VGS= 10 V, RGEN= 6�|−|8|16|ns|
|tr||Turn–On Rise Time||−|5|10|ns|
|td(off)||Turn–Off Delay Time||−|23|37|ns|
|tf||Turn–Off Fall Time||−|3|6|ns|
|Qg||Total Gate Charge|VDS= 15 V, ID= 6 A, VGS= 5 V|−|5.8|8.1|nC|
|Qgs||Gate–Source Charge||−|1.7|−|nC|
|Qgd||Gate–Drain Charge||−|2.1|−|nC|
|**DRAIN−SOURCE DIODE CHARACTERISTICS**||||||||
|IS||Maximum Continuous Drain–Source Diode Forward Current||−|−|1.3|A|
|VSD||Drain–Source Diode Forward Voltage|VGS= 0 V, IS= 1.3 A (Note 2)|−|0.75|1.2|V|
|trr||Diode Reverse Recovery Time|IF= 6 A, diF/dt= 100 A/�s|−|20|−|ns|
|Qrr||Diode Reverse Recovery Charge||−|10|−|nC|



Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 

## NOTES: 

1. R � JA is the sum of the junction−to−case and case−to−ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. R � JC is guaranteed by design while R � CA is determined by the user’s board design. 

a. 78 ° C/W when mounted on a 0.5 in[2] pad of 2 oz copper 

b. 125 ° C/W when mounted on a 0.02 in[2] pad of 2 oz copper 

c. 135 ° C/W when mounted on a minimum mounting pad. 

Scale 1 : 1 on letter size paper 

2. Pulse Test: Pulse Width < 300 � s, Duty Cycle < 2.0%. 

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**2** 

**FDS6912A** 

## **TYPICAL ELECTRICAL CHARACTERISTICS** 

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2.2<br>1.8<br>V GS  = 3.5 V<br>1.4 4.0 V<br>4.5 V<br>5.0 V<br>6.0 V<br>1.0 10.0 V<br>0.6<br>0 4 8 12 16 20<br>ID, DRAIN CURRENT (A)D, DRAIN CURRENT (A), DRAIN CURRENT (A)<br> NORMALIZED DRAIN<br>DS(ON)<br>R TO SOURCE ON−RESISTANCE<br>**----- End of picture text -----**<br>


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20 2.2<br>16 VG S = 10.0 V<br>V VGSGS = 6.0 V = 4.5 V 1.8 V GS  = 3.5 V<br>12<br>VGS = 4.0 V 1.4 4.0 V<br>8 VGS = 3.5 V 4.5 V<br>5.0 V<br>6.0 V<br>4 VGS = 3.0 V 1.0 10.0 V<br>0 0.6<br>0 0.5 1 1.5 2 0 4 8 12 16 20<br>VDS, DRAIN TO SOURCE VOLTAGE (V) ID, DRAIN CURRENT (A)D, DRAIN CURRENT (A), DRAIN CURRENT (A)<br>Figure 1. On−Region Characteristics Figure 2. On−Resistance Variation with Drain<br>Current and Gate Voltage<br>1.6 0.08<br>ID = 6 A ID = 3 A<br>VGS = 10 V 0.07<br>1.4<br>0.06<br>1.2<br>0.05<br>TA = 125 ° C<br>1 0.04<br>0.03<br>0.8<br>0.02 °<br>T A  = 25 C<br>0.6 0.01<br>−50 −25 0 25 50 75 100 125 150 2 4 6 8 10<br>TJ, JUNCTION TEMPERATURE ( ° C) VGS, GATE TO SOURCE VOLTAGE (V)<br>Figure 3. On−Resistance Variation with Figure 4. On−Resistance Variation with Gate<br>Temperature to Source Voltage<br>20 100<br>VDS = 5 V VGS = 0 V<br>10<br>16<br>1 T A  = 125 ° C<br>12<br>8 TA = 125 ° C TA = 25 ° C 0.1 T A  = 25 ° C<br>0.01<br>4 T A  = −55 ° C 0.001 T A  = −55 ° C<br>0 0.0001<br>1.5 2 2.5 3 3.5 4 0 0.2 0.4 0.6 0.8 1 1.2<br>VGS, GATE TO SOURCE VOLTAGE (V) VSD, BODY DIODE FORWARD VOLTAGE (V)<br> NORMALIZED DRAIN<br>, DRAIN CURRENT (A)<br>ID<br>DS(ON)<br>R TO SOURCE ON−RESISTANCE<br> NORMALIZED DRAIN  , ON−RESISTANCE () �<br>DS(ON) DS(ON)<br>R TO SOURCE ON−RESISTANCE R<br>, DRAIN CURRENT (A)<br>ID<br>, REVERSE DRAIN CURRENT (A)<br>IS<br>**----- End of picture text -----**<br>


**Figure 5. Transfer Characteristics** 

**Figure 6. Body Diode Forward Voltage Variation with Source Current and Temperature** 

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**3** 

**FDS6912A** 

## **TYPICAL ELECTRICAL CHARACTERISTICS** (continued) 

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10 800<br>ID = 6 A f = 1 MHz<br>VDS = 10 V VGS = 0 V<br>8<br>600<br>Ciss<br>6<br>VDS = 15 V 400<br>4<br>VDS = 20 V Coss<br>200<br>2<br>Crss<br>0 0<br>0 2 4 6 8 10 12 0 5 10 15 20<br>Qg, GATE CHARGE (nC) VDS, DRAIN TO SOURCE VOLTAGE (V)<br>Figure 7. Gate Charge Characteristics Figure 8. Capacitance Characteristics<br>100 50<br>RDS(ON) LIMIT SINGLE PULSER � JA = 135 ° C/W<br>40 T A  = 25 ° C<br>10 100  � s<br>1 ms<br>30<br>1 10 ms<br>100 ms 20<br>0.1 VGS = 10 V 1 s<br>SINGLE PULSE 10<br>R � JA = 135 ° C/W 10 s<br>TA = 25 ° C DC<br>0.01 0<br>0.1 1 10 100 0.001 0.01 0.1 1 10 100 1000<br>VDS, DRAIN TO SOURCE VOLTAGE (V) t1, TIME (s)<br>CAPACITANCE (pF)<br>, GATE TO SOURCE VOLTAGE (V)<br>GS<br>V<br>, DRAIN CURRENT (A)<br>ID<br>, PEAK TRANSIENT POWER (W)<br>(pk)<br>P<br>**----- End of picture text -----**<br>


**Figure 9. Maximum Safe Operating Area** 

**Figure 10. Single Pulse Maximum Power Dissipation** 

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1<br>D = 0.5<br>R � JA(t) = r(t) * R � JA<br>0.2 R � JA = 135 ° C/W<br>0.1 0.1<br>0.05<br>0.02<br>0.01 t1<br>0.01<br>SINGLE PULSE t2<br>TJ − TA = P * R � JA(t)<br>Duty Cycle, D = t 1 / t 2<br>0.001<br>0.0001 0.001 0.01 0.1 1 10 100 1000<br>t1, TIME (s)<br>P(pk)<br>r(t), NORMALIZED EFFECTIVE<br>TRANSIENT THERMAL RESISTANCE<br>**----- End of picture text -----**<br>


**Figure 11. Transient Thermal Response Curve** 

(Thermal characterization performed using the conditions described in Note 1c. Transient thermal response will change depending on the circuit board design.) 

POWERTRENCH is a trademark of Semiconductor Components Industries, LLC dba “ **onsemi** ” or its affiliates and/or subsidiaries in the United States and/or other countries. 

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**4** 

MECHANICAL CASE OUTLINE **PACKAGE DIMENSIONS** 

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SOIC8<br>CASE 751EB<br>ISSUE A<br>DATE 24 AUG 2017<br>**----- End of picture text -----**<br>


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