FDS3992

## **Is Now Part of** 

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**April 2013** 

## **FDS3992** 

## **Dual N-Channel PowerTrench**[®] **MOSFET** 

## **100V, 4.5A, 62m** Ω 

## **Features** 

- rDS(ON) = 54mΩ (Typ.), VGS = 10V, ID = 4.5A 

- • Qg(tot) = 11nC (Typ.), VGS = 10V 

- Low Miller Charge 

## **Applications** 

   - DC/DC converters and Off-Line UPS 

   - Distributed Power Architectures and VRMs 

   - Primary Switch for 24V and 48V Systems 

- Low QRR Body Diode 

   - High Voltage Synchronous Rectifier 

- Optimized efficiency at high frequencies 

- Direct Injection / Diesel Injection Systems 

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• UIS Capability (Single Pulse and Repetitive Pulse)<br>• 42V Automotive Load Control<br>Formerly developmental type 82745 • Electronic Valve Train Systems<br>ee<br>Branding Dash (1)<br>y (2) I<br>5 1<br>1 ; (3)<br>2 ® > 1<br>3 (4)<br>4 !<br>SO-8 !<br>**----- End of picture text -----**<br>


**(1) (8) (2)** ~~I~~ **(7)** ~~1~~ **(3) (6)** 1 1 **(4) (5)** 

**MOSFET Maximum Ratings** TA = 25°C unless otherwise noted 

|**Symbol**|**Parameter**||**Ratings**|**Ratings**||**Units**|
|---|---|---|---|---|---|---|
|VDSS|Drain to Source Voltage||100|||V|
|VGS|Gate to Source Voltage||±20|||V|
||Drain Current||||||
|ID|Continuous(TA= 25oC, VGS= 10V, RθJA= 50oC/W)<br>Continuous(TA= 100oC, VGS= 10V, RθJA= 50oC/W)||4.5<br>2.8|||A<br>A|
||Pulsed||Figure 4|||A|
|EAS|Single Pulse Avalanche Energy (Note 1)||167|||mJ|
|PD|Total Package Power Dissipation<br>Derate above 25oC||2.5<br>20|||W<br>mW/oC|
|TJ, TSTG|Operatingand Storage Temperature||-55 to 150|||oC|
|**Thermal Characteristics**|**Thermal Characteristics**||||||
|RθJA|Thermal Resistance, Junction to Ambient at 10 seconds(Note 3)||50|||oC/W|
|RθJA|Thermal Resistance, Junction to Ambient at 1000 seconds(Note 3)||85|||oC/W|
|RθJC|Thermal Resistance, Junction to Case(Note 2)||25|||oC/W|
|**Package Marking and Ordering Information**|**Package Marking and Ordering Information**||||||
|**Device Marking**<br>**Device**<br>**Package**||**Reel Size**|**Tape Width**||**Quantity**||
|FDS3992<br>FDS3992<br>SO-8||13’’|12mm||2500 units|2500 units|



©2004 Fairchild Semiconductor Corporation 

FDS3992 Rev. C 

|**Electrical Characteristics**TA= 25°C unless otherwise noted|**Electrical Characteristics**TA= 25°C unless otherwise noted|**Electrical Characteristics**TA= 25°C unless otherwise noted|**Electrical Characteristics**TA= 25°C unless otherwise noted|||||
|---|---|---|---|---|---|---|---|
|**Symbol**|**Parameter**|**Test Conditions**||**Min**|**Typ**|**Max**|**Units**|
|**Off Characteristics**||||||||
|BVDSS|Drain to Source Breakdown Voltage|ID= 250µA, VGS|= 0V|100|-|-|V|
|IDSS|Zero Gate Voltage Drain Current|VDS= 80V<br>VGS= 0V||-|-|1|µA|
||||TC = 150oC|-|-|250||
|IGSS|Gate to Source Leakage Current|VGS=±20V||-|-|±100|nA|
|**On Characteristics**||||||||
|VGS(TH)|Gate to Source Threshold Voltage|VGS= VDS, ID= 250µA||2|-|4|V|
|rDS(ON)|Drain to Source On Resistance|ID= 4.5A, VGS = 10V||-|0.054|0.062|Ω|
|||ID= 2A, VGS= 6V||-|0.072|0.108||
|||ID=  4.5A, VGS=  10V,<br>TC = 150oC||-|0.107|0.123||
|**Dynamic Characteristics**||||||||
|CISS|Input Capacitance|VDS= 25V, VGS= 0V,<br>f = 1MHz||-|750|-|pF|
|COSS|Output Capacitance|||-|118|-|pF|
|CRSS|Reverse Transfer Capacitance|||-|27|-|pF|
|Qg(TOT)|Total Gate Charge at 10V|VGS= 0V to 10V||-|11|15|nC|
|Qg(TH)|Threshold Gate Charge|VGS= 0V to 2V||-|1.4|1.9|nC|
|Qgs|Gate to Source Gate Charge|||-|3.5|-|nC|
|Qgs2|Gate Charge Threshold to Plateau|||-|2.1|-|nC|
|Qgd|Gate to Drain “Miller” Charge|||-|2.8|-|nC|
|**Switching Characteristics**(VGS= 10V)||||||||
|tON|Turn-On Time|VDD= 50V, ID= 4.5A<br>VGS= 10V, RGS= 27Ω||-|-|47|ns|
|td(ON)|Turn-On Delay Time|||-|8|-|ns|
|tr|Rise Time|||-|23|-|ns|
|td(OFF)|Turn-Off Delay Time|||-|28|-|ns|
|tf|Fall Time|||-|26|-|ns|
|tOFF|Turn-Off Time|||-|-|81|ns|
|**Drain-Source Diode Characteristics**||||||||
|VSD|Source to Drain Diode Voltage|ISD= 4.5A||-|-|1.25|V|
|||ISD= 2A||-|-|1.0|V|
|trr|Reverse RecoveryTime|ISD= 4.5A, dISD/dt= 100A/µs||-|-|48|ns|
|QRR|Reverse RecoveryCharge|ISD= 4.5A, dISD/dt= 100A/µs||-|-|65|nC|



**Notes:** 

- **1:** EAS of 167mJ is based on starting T J = 25°C, L = 37mH, IAS = 3A. 100% test at L = 1mH, I     = 10.3A.AS **2:** RθJA is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins.  RθJC is guaranteed by design while RθCA  is determined by the user’s board design. 

- **3:** RθJA is measured with 1.0 in[2] copper on FR-4 board 

©2004 Fairchild Semiconductor Corporation 

FDS3992 Rev. C 

**Typical Characteristics** TA = 25°C unless otherwise noted 

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1.2 5<br>VGS = 10V<br>1.0<br>4<br>0.8<br>3<br>0.6<br>2<br>0.4<br>1<br>0.2<br>0<br>0<br>0 25 50 75 100 125 150 25 50 75 100 125 150<br>TA, AMBIENT TEMPERATURE ( [o] C) TA, AMBIENT TEMPERATURE ( [o] C)<br>Figure 1.  Normalized Power Dissipation vs  Figure 2.  Maximum Continuous Drain Current vs<br>Ambient Temperature Ambient Temperature<br>2<br>DUTY CYCLE - DESCENDING ORDER<br>1 0.5<br>0.2 R θ JA=50 [o] C/W<br>0.1<br>0.05<br>0.02<br>0.01<br>0.1<br>PDM<br>0.01 t1<br>SINGLE PULSE t 2<br>NOTES:<br>DUTY FACTOR: D = t 1 /t 2<br>PEAK TJ = PDM x Z θ JA x R θ JA + TA<br>0.001<br>10 [-5] 10 [-4] 10 [-3] 10 [-2] 10 [-1] 10 [0] 10 [1] 10 [2] 10 [3]<br>t, RECTANGULAR PULSE DURATION (s)<br>Figure 3.  Normalized Maximum Transient Thermal Impedance<br>200<br>TRANSCONDUCTANCE TA = 25 [o] C<br>MAY LIMIT CURRENT<br>100 IN THIS REGION FOR TEMPERATURES<br>ABOVE 25 [o] C DERATE PEAK<br>CURRENT AS FOLLOWS:<br>V GS  = 10V I = I 25  150 - TC<br>125<br>10<br>1<br>10 [-5] 10 [-4] 10 [-3] 10 [-2] 10 [-1] 10 [0] 10 [1] 10 [2] 10 [3]<br>t, PULSE WIDTH (s)<br>Figure 4.  Peak Current Capability<br>, DRAIN CURRENT (A)<br>ID<br>POWER DISSIPATION MULTIPLIER<br>, NORMALIZED<br>ZJA θ<br>THERMAL IMPEDANCE<br>, PEAK CURRENT (A)<br>IDM<br>**----- End of picture text -----**<br>


©2004 Fairchild Semiconductor Corporation 

FDS3992 Rev. C 

## **Typical Characteristics** TA = 25°C unless otherwise noted 

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200 7<br>100<br>10 µ s<br>STARTING TJ = 25 [o] C<br>10<br>100 µ s STARTING TJ = 150 [o] C<br>1<br>1 1ms<br>OPERATION IN THIS<br>AREA MAY BE 10ms<br>LIMITED BY rDS(ON) 100ms<br>0.1<br>SINGLE PULSE If R = 0<br>TJ = MAX RATED tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD)<br>T C  = 25 [o] C 1s If R tAV =   ≠  0 (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1]<br>0.01 0.1<br>0.1 1 10 100 300 0.01 0.1 1 10 100<br>VDS, DRAIN TO SOURCE VOLTAGE (V) tAV, TIME IN AVALANCHE (ms)<br>Figure 5.  Forward Bias Safe Operating Area NOTE: Refer to Fairchild Application Notes AN7514 and AN7515<br>Figure 6.  Unclamped Inductive Switching<br>Capability<br>30 30<br>DUTY CYCLE = 0.5% MAXPULSE DURATION = 80 µ s  TA = 25 [o] C VGS = 10V<br>25 VDD = 15V 25<br>20 20<br>VGS = 7V<br>15 15<br> TJ = 150 [o] C VGS = 6V<br>10  TJ = 25 [o] C 10 VGS = 5V<br> TJ = -55 [o] C<br>5 5<br>PULSE DURATION = 80 µ s<br>DUTY CYCLE = 0.5% MAX<br>0 0<br>3.5 4.0 4.5 5.0 5.5 6.0 6.5 0 0.5 1.0 1.5 2.0<br>VGS, GATE TO SOURCE VOLTAGE (V) VDS, DRAIN TO SOURCE VOLTAGE (V)<br>Figure 7.  Transfer Characteristics Figure 8.  Saturation Characteristics<br>80 2.5<br>PULSE DURATION = 80 µ s<br>VGS = 6V DUTY CYCLE = 0.5% MAX<br>75<br>2.0<br>70<br>65 1.5<br>PULSE DURATION = 80 µ s<br>DUTY CYCLE = 0.5% MAX<br>60<br>1.0<br>VGS = 10V<br>55<br>VGS = 10V, ID = 4.5A<br>50 0.5<br>1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 -80 -40 0 40 80 120 160<br>ID, DRAIN CURRENT (A) TJ, JUNCTION TEMPERATURE ( [o] C)<br>Figure 9.  Drain to Source On Resistance vs Drain  Figure 10.  Normalized Drain to Source On<br>Current Resistance vs Junction Temperature<br>, DRAIN CURRENT (A)<br>ID , AVALANCHE CURRENT (A)<br>IAS<br>, DRAIN CURRENT (A)ID , DRAIN CURRENT (A)ID<br>) Ω<br>ON RESISTANCE<br>NORMALIZED DRAIN TO SOURCE<br>DRAIN TO SOURCE ON RESISTANCE (m<br>**----- End of picture text -----**<br>


**Figure 9.  Drain to Source On Resistance vs Drain Current** 

©2004 Fairchild Semiconductor Corporation 

FDS3992 Rev. C 

**Typical Characteristics** TA = 25°C unless otherwise noted 

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1.2 1.2<br>VGS = VDS, ID = 250 µ A  ID = 250 µ A<br>1.0 1.1<br>0.8 1.0<br>0.6 0.9<br>-80 -40 0 40 80 120 160 -80 -40 0 40 80 120 160<br>TJ, JUNCTION TEMPERATURE ( [o] C) TJ, JUNCTION TEMPERATURE ( [o] C)<br>Figure 11.  Normalized Gate Threshold Voltage vs  Figure 12.  Normalized Drain to Source<br>Junction Temperature Breakdown Voltage vs Junction Temperature<br>2000 10<br>CISS  =  CGS + CGD VDD = 50V<br>1000<br>8<br>C OSS  ≅  C DS  + C GD<br>6<br>100 CRSS  =  CGD<br>4<br>2 WAVEFORMS IN<br>DESCENDING ORDER:<br>VGS = 0V, f = 1MHz IIDD = 4.5A = 2A<br>10<br>0<br>0.1 1 10 100 0 2 4 6 8 10 12<br>VDS, DRAIN TO SOURCE VOLTAGE (V) Qg, GATE CHARGE (nC)<br>NORMALIZED GATE BREAKDOWN VOLTAGE<br>THRESHOLD VOLTAGE<br>NORMALIZED DRAIN TO SOURCE<br>C, CAPACITANCE (pF)<br>, GATE TO SOURCE VOLTAGE (V)<br>GS<br>V<br>**----- End of picture text -----**<br>


**Figure 11.  Normalized Gate Threshold Voltage vs Junction Temperature** 

**Figure 13.  Capacitance vs Drain to Source Figure 14.  Gate Charge Waveforms for Constant Voltage Gate Currents** 

©2004 Fairchild Semiconductor Corporation 

FDS3992 Rev. C 

## **Test Circuits and Waveforms** 

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VDS BVDSS<br>tP<br>L VDS<br>IAS<br>VARY tP TO OBTAIN + VDD<br>REQUIRED PEAK IAS RG VDD<br>VGS -<br>DUT<br>tP<br>0V IAS 0<br>0.01 Ω<br>tAV<br>**----- End of picture text -----**<br>


**Figure 15.  Unclamped Energy Test Circuit** 

**Figure 16.  Unclamped Energy Waveforms** 

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VDS<br>L<br>VGS +<br>VDD<br>-<br>DUT<br>Ig(REF)<br>**----- End of picture text -----**<br>


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VDD Qg(TOT)<br>VDS<br>VGS = 10V<br>VGS<br>VGS = 2V<br>0 Qgs2<br>Qg(TH)<br>Qgs Qgd<br>Ig(REF)<br>0<br>**----- End of picture text -----**<br>


**Figure 17.  Gate Charge Test Circuit** 

**Figure 18.  Gate Charge Waveforms** 

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VDS tON tOFF<br>td(ON) td(OFF)<br>RL tr tf<br>VDS<br>90% 90%<br>VGS +<br>VDD 10% 10%<br>- 0<br>DUT 90%<br>RGS<br>VGS 50% 50%<br>PULSE WIDTH<br>VGS 0 10%<br>**----- End of picture text -----**<br>


**Figure 19.  Switching Time Test Circuit** 

**Figure 20.  Switching Time Waveforms** 

©2004 Fairchild Semiconductor Corporation 

FDS3992 Rev. C 

## _**Thermal Resistance vs. Mounting Pad Area**_ 

The maximum rated junction temperature, TJM, and the thermal resistance of the heat dissipating path determines the maximum allowable device power dissipation, PDM, in an application. Therefore the application’s ambient temperature, TA ([o] C), and thermal resistance RθJA ([o] C/W) must be reviewed to ensure that TJM is never exceeded. Equation 1 mathematically represents the relationship and serves as the basis for establishing the rating of the part. 

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In using surface mount devices such as the SO8 package, the environment in which it is applied will have a significant influence on the part’s current and maximum power dissipation ratings. Precise determination of PDM is complex and influenced by many factors: 

1. Mounting pad area onto which the device is attached and whether there is copper on one side or both sides of the board. 

2. The number of copper layers and the thickness of the board. 

3. The use of external heat sinks. 

maximum transient thermal impedance curve. 

Thermal resistances corresponding to other copper areas can be obtained from Figure 21 or by calculation using Equation 2.  The area, in square inches is the top copper area including the gate and source pads. 

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The transient thermal impedance (ZθJA) is also effected by varied top copper board area. Figure 22 shows the effect of copper pad area on single pulse transient thermal impedance. Each trace represents a copper pad area in square inches corresponding to the descending list in the graph. Spice and SABER thermal models are provided for each of the listed pad areas. 

Copper pad area has no perceivable effect on transient thermal impedance for pulse widths less than 100ms. For pulse widths less than 100ms the transient thermal impedance is determined by the die and package. Therefore, CTHERM1 through CTHERM5 and RTHERM1 through RTHERM5 remain constant for each of the thermal models. A listing of the model component values is available in Table 1. 

4. The use of thermal vias. 

5. Air flow and board orientation. 

6. For non steady state applications, the pulse width, the duty cycle and the transient thermal response of the part, the board and the environment they are in. 

Fairchild provides thermal information to assist the designer’s preliminary application evaluation. Figure 21 defines the RθJA for the device as a function of the top copper (component side) area. This is for a horizontally positioned FR-4 board with 1oz copper after 1000 seconds of steady state power with no air flow. This graph provides the necessary information for calculation of the steady state junction temperature or power dissipation. Pulse applications can be evaluated using the Fairchild device Spice thermal model or manually utilizing the normalized 

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200<br>R θ JA = 64 + 26/(0.23+Area)<br>150<br>100<br>50<br>0.001 0.01 0.1 1 10<br>AREA, TOP COPPER AREA (in [2] )<br>Figure 21.  Thermal Resistance vs Mounting<br>Pad Area<br>oC/W)( RJA  θ<br>**----- End of picture text -----**<br>


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150<br>COPPER BOARD AREA - DESCENDING ORDER<br>0.04 in [2]<br>120 0.28 in [2]<br>0.52 in [2]<br>0.76 in [2]<br>90 1.00 in [2]<br>60<br>30<br>0<br>10 [-1] 10 [0] 10 [1] 10 [2] 10 [3]<br>t, RECTANGULAR PULSE DURATION (s)<br>oC/W)<br>, THERMAL<br>ZJA θ<br>MPEDANCE (I<br>**----- End of picture text -----**<br>


**Figure 22.  Thermal Impedance vs Mounting Pad Area** 

©2004 Fairchild Semiconductor Corporation 

FDS3992 Rev. C 

## _**PSPICE Electrical Model**_ 

.SUBCKT FDS3992 2 1 3 ; rev Aug 2002 Ca 12 8 2.3e-10 Cb 15 14 3.5e-10 Cin 6 8 7.47e-10 

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LDRAIN<br>DPLCAP 5 DRAIN<br>2<br>10<br>RLDRAIN<br>RSLC1<br>51 DBREAK<br>RSLC2<br>515 ESLC 11<br>ESG +- 68 EVTHRES RDRAIN50 16 EBREAK +-1718 DBODY<br>LGATE EVTEMP + 198 - 21 MWEAK<br>GATE RGATE + 18 - 6<br>1 9 20 22 MMED<br>RLGATE MSTRO<br>LSOURCE<br>CIN 8 7 SOURCE3<br>RSOURCE<br>RLSOURCE<br>S1A S2A<br>12 13 14 15 17 RBREAK 18<br>8 13<br>S1B S2B RVTEMP<br>CA 13+ CB+ 14 IT -19<br>EGS 68 EDS 58 + VBAT<br>- - 8<br>22<br>RVTHRES<br>+<br>-<br>**----- End of picture text -----**<br>


Dbody 7 5 DbodyMOD Dbreak 5 11 DbreakMOD Dplcap 10 5 DplcapMOD 

Ebreak 11 7 17 18 108 Eds 14 8 5 8 1 Egs 13 8 6 8 1 Esg 6 10 6 8 1 Evthres 6 21 19 8 1 Evtemp 20 6 18 22 1 

It 8 17 1 

Lgate 1 9 5.61e-9 Ldrain 2 5 1e-9 Lsource 3 7 1.98e-9 

RLgate 1 9 56.1 RLdrain 2 5 10 RLsource 3 7 19.8 

Mmed 16 6 8 8 MmedMOD Mstro 16 6 8 8 MstroMOD Mweak 16 21 8 8 MweakMOD 

Rbreak 17 18 RbreakMOD 1 Rdrain 50 16 RdrainMOD 25.e-3 Rgate 9 20 3.7 RSLC1 5 51 RSLCMOD 1e-6 RSLC2 5 50 1e3 Rsource 8 7 RsourceMOD 20e-3 Rvthres 22 8 Rvthresmod 1 Rvtemp 18 19 RvtempMOD 1 S1a 6 12 13 8 S1AMOD S1b 13 12 13 8 S1BMOD S2a 6 15 14 13 S2AMOD S2b 13 15 14 13 S2BMOD 

Vbat 22 19 DC 1 

ESLC 51 50  VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*45),2.5))} 

.MODEL DbodyMOD D (IS=2.4E-12 N=1.04 RS=13e-3 TRS1=2.1e-3 TRS2=4.7e-7 + CJO=5.5e-10 M=0.57 TT=3.25e-8 XTI=4.6) .MODEL DbreakMOD D (RS=1.6 TRS1=2.4e-3 TRS2=-1e-5) .MODEL DplcapMOD D (CJO=1.6e-10 IS=1e-30 N=10 M=0.54) 

.MODEL MmedMOD NMOS (VTO=3.8 KP=2 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=3.7) .MODEL MstroMOD NMOS (VTO=4.35 KP=28 IS=1e-30 N=10 TOX=1 L=1u W=1u) .MODEL MweakMOD NMOS (VTO=3.26 KP=0.04 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=37 RS=0.1) 

.MODEL RbreakMOD RES (TC1=1.1e-3 TC2=-1e-8) .MODEL RdrainMOD RES (TC1=1.15e-2 TC2=2.8e-5) .MODEL RSLCMOD RES (TC1=3.3e-3 TC2=1e-6) .MODEL RsourceMOD RES (TC1=1e-3 TC2=1e-6) .MODEL RvthresMOD RES (TC1=-4.8e-3 TC2=-1.1e-5) .MODEL RvtempMOD RES (TC1=-3e-3 TC2=1.5e-6) 

.MODEL S1AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-3 VOFF=-2) .MODEL S1BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-2 VOFF=-3) .MODEL S2AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-1.5 VOFF=1) .MODEL S2BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=1 VOFF=-1.5) 

.ENDS 

Note: For further discussion of the PSPICE model, consult **A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global Temperature Options** ; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley. 

©2004 Fairchild Semiconductor Corporation 

FDS3992 Rev. C 

## _**SABER Electrical Model**_ 

REV Aug 2002 template FDS3992 n2,n1,n3 electrical n2,n1,n3 { var i iscl 

dp..model dbodymod =  (isl=2.4e-12,nl=1.04,rs=13e-3,trs1=2.1e-3,trs2=4.7e-7,cjo=5.5e-10,m=0.57,tt=3.25e-8,xti=4.6) dp..model dbreakmod = (rs=1.6,trs1=2.4e-3,trs2=-1.0e-5) 

dp..model dplcapmod =  (cjo=1.6e-10,isl=10e-30,nl=10,m=0.54) m..model mmedmod = (type=_n,vto=3.8,kp=2.0,is=1e-30, tox=1) 

m..model mstrongmod = (type=_n,vto=4.35,kp=28,is=1e-30, tox=1) m..model mweakmod = (type=_n,vto=3.26,kp=0.04,is=1e-30, tox=1,rs=0.1) sw_vcsp..model s1amod =  (ron=1e-5,roff=0.1,von=-3.0,voff=-2.0) sw_vcsp..model s1bmod =  (ron=1e-5,roff=0.1,von=-2.0,voff=-3.0) sw_vcsp..model s2amod =  (ron=1e-5,roff=0.1,von=-1.5,voff=1.0) sw_vcsp..model s2bmod =  (ron=1e-5,roff=0.1,von=1.0,voff=-1.5) **10** c.ca n12 n8 = 2.3e-10 c.cb n15 n14 = 3.5e-10 c.cin n6 n8 = 7.47e-10 **RSLC2** 

**==> picture [433 x 257] intentionally omitted <==**

**----- Start of picture text -----**<br>
LDRAIN<br>sw_vcsp..model s1bmod =  (ron=1e-5,roff=0.1,von=-2.0,voff=-3.0) DPLCAP 5 DRAIN<br>sw_vcsp..model s2amod =  (ron=1e-5,roff=0.1,von=-1.5,voff=1.0) 2<br>sw_vcsp..model s2bmod =  (ron=1e-5,roff=0.1,von=1.0,voff=-1.5) 10 RLDRAIN<br>c.ca n12 n8 = 2.3e-10 RSLC1<br>c.cb n15 n14 = 3.5e-10 51<br>c.cin n6 n8 = 7.47e-10 RSLC2<br>ISCL<br>dp.dbody n7 n5 = model=dbodymoddp.dbreak n5 n11 = model=dbreakmod - 50 DBREAK<br>6 RDRAIN<br>dp.dplcap n10 n5 = model=dplcapmod ESG + 8 EVTHRES 16 11 DBODY<br>spe.ebreak n11 n7 n17 n18 = 108spe.eds n14 n8 n5 n8 = 1spe.egs n13 n8 n6 n8 = 1spe.esg n6 n10 n6 n8 = 1spe.evthres n6 n21 n19 n8 = 1spe.evtemp n20 n6 n18 n22 = 1 GATE1 RLGATELGATE 9RGATE20EVTEMP+ 1822 - 6 + 198 CIN- MSTRO21 8 MMED MWEAKEBREAK+-1718 7 LSOURCE SOURCE3<br>i.it n8 n17 = 1 RSOURCE<br>RLSOURCE<br>S1A S2A<br>l.lgate n1 n9 = 5.61e-9l.ldrain n2 n5 = 1e-9 12 13 14 15 17 RBREAK 18<br>8 13<br>l.lsource n3 n7 = 1.98e-9<br>S1B S2B RVTEMP<br>res.rlgate n1 n9 = 56.1res.rldrain n2 n5 = 10 CA 13+ CB+ 14 IT -19<br>res.rlsource n3 n7 = 19.8 EGS 68 EDS 58 + VBAT<br>m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u - - 8 22<br>m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u  RVTHRES<br>**----- End of picture text -----**<br>


m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u 

res.rbreak n17 n18  = 1, tc1=1.1e-3,tc2=-1e-8 res.rdrain n50 n16  = 25e-3, tc1=1.15e-2,tc2=2.8e-5 res.rgate n9 n20 = 3.7 res.rslc1 n5 n51  = 1e-6, tc1=3.3e-3,tc2=1e-6 res.rslc2 n5 n50 = 1e3 res.rsource n8 n7  = 20e-3, tc1=1e-3,tc2=1e-6 res.rvthres n22 n8  = 1, tc1=-4.8e-3,tc2=-1.1e-5 res.rvtemp n18 n19  = 1, tc1=-3e-3,tc2=1.5e-6 sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod 

v.vbat n22 n19 = dc=1 equations { i (n51->n50) +=iscl iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/45))** 2.5)) } 

©2004 Fairchild Semiconductor Corporation 

FDS3992 Rev. C 

||**_SPICE Thermal Model_**<br>REV Aug 2002<br>FDS3992<br>Copper Area =1.0 in2<br>CTHERM1 TH 8 4e-4<br>CTHERM2 8 7 5e-3<br>CTHERM3 7 6 6e-2<br>CTHERM4 6 5 9e-2<br>CTHERM5 5 4 3e-1<br>CTHERM6 4 3 4e-1<br>CTHERM7 3 2 9e-1<br>CTHERM8 2 TL 2<br>RTHERM1 TH 8 5e-1<br>RTHERM2 8 7 6e-1<br>RTHERM3 7 6 4<br>RTHERM4 6 5 5<br>RTHERM5 5 4 8<br>RTHERM6 4 3 9<br>RTHERM7 3 2 15<br>RTHERM8 2 TL 23<br>**_SABER Thermal Model_**<br>Copper Area = 1.0 in2<br>template thermal_model th tl<br>thermal_c th, tl<br>{<br>CTHERM1 TH 8 4e-4<br>CTHERM2 8 7 5e-3<br>CTHERM3 7 6 6e-2<br>CTHERM4 6 5 9e-2<br>CTHERM5 5 4 3e-1<br>CTHERM6 4 3 4e-1<br>CTHERM7 3 2 9e-1<br>CTHERM8 2 TL 2<br>RTHERM1 TH 8 5e-1<br>RTHERM2 8 7 6e-1<br>RTHERM3 7 6 4<br>RTHERM4 6 5 5<br>RTHERM5 5 4 8<br>RTHERM6 4 3 9<br>RTHERM7 3 2 15<br>RTHERM8 2 TL 23<br>}<br>**RTHERM6**<br>**RTHERM8**<br>**RTHERM7**<br>**RTHERM5**<br>**RTHERM4**<br>**RTHERM3**<br>**RTHERM2**<br>**RTHERM1**<br>**TABLE 1. THERMAL MODELS**|**_SPICE Thermal Model_**<br>REV Aug 2002<br>FDS3992<br>Copper Area =1.0 in2<br>CTHERM1 TH 8 4e-4<br>CTHERM2 8 7 5e-3<br>CTHERM3 7 6 6e-2<br>CTHERM4 6 5 9e-2<br>CTHERM5 5 4 3e-1<br>CTHERM6 4 3 4e-1<br>CTHERM7 3 2 9e-1<br>CTHERM8 2 TL 2<br>RTHERM1 TH 8 5e-1<br>RTHERM2 8 7 6e-1<br>RTHERM3 7 6 4<br>RTHERM4 6 5 5<br>RTHERM5 5 4 8<br>RTHERM6 4 3 9<br>RTHERM7 3 2 15<br>RTHERM8 2 TL 23<br>**_SABER Thermal Model_**<br>Copper Area = 1.0 in2<br>template thermal_model th tl<br>thermal_c th, tl<br>{<br>CTHERM1 TH 8 4e-4<br>CTHERM2 8 7 5e-3<br>CTHERM3 7 6 6e-2<br>CTHERM4 6 5 9e-2<br>CTHERM5 5 4 3e-1<br>CTHERM6 4 3 4e-1<br>CTHERM7 3 2 9e-1<br>CTHERM8 2 TL 2<br>RTHERM1 TH 8 5e-1<br>RTHERM2 8 7 6e-1<br>RTHERM3 7 6 4<br>RTHERM4 6 5 5<br>RTHERM5 5 4 8<br>RTHERM6 4 3 9<br>RTHERM7 3 2 15<br>RTHERM8 2 TL 23<br>}<br>**RTHERM6**<br>**RTHERM8**<br>**RTHERM7**<br>**RTHERM5**<br>**RTHERM4**<br>**RTHERM3**<br>**RTHERM2**<br>**RTHERM1**<br>**TABLE 1. THERMAL MODELS**|**_SPICE Thermal Model_**<br>REV Aug 2002<br>FDS3992<br>Copper Area =1.0 in2<br>CTHERM1 TH 8 4e-4<br>CTHERM2 8 7 5e-3<br>CTHERM3 7 6 6e-2<br>CTHERM4 6 5 9e-2<br>CTHERM5 5 4 3e-1<br>CTHERM6 4 3 4e-1<br>CTHERM7 3 2 9e-1<br>CTHERM8 2 TL 2<br>RTHERM1 TH 8 5e-1<br>RTHERM2 8 7 6e-1<br>RTHERM3 7 6 4<br>RTHERM4 6 5 5<br>RTHERM5 5 4 8<br>RTHERM6 4 3 9<br>RTHERM7 3 2 15<br>RTHERM8 2 TL 23<br>**_SABER Thermal Model_**<br>Copper Area = 1.0 in2<br>template thermal_model th tl<br>thermal_c th, tl<br>{<br>CTHERM1 TH 8 4e-4<br>CTHERM2 8 7 5e-3<br>CTHERM3 7 6 6e-2<br>CTHERM4 6 5 9e-2<br>CTHERM5 5 4 3e-1<br>CTHERM6 4 3 4e-1<br>CTHERM7 3 2 9e-1<br>CTHERM8 2 TL 2<br>RTHERM1 TH 8 5e-1<br>RTHERM2 8 7 6e-1<br>RTHERM3 7 6 4<br>RTHERM4 6 5 5<br>RTHERM5 5 4 8<br>RTHERM6 4 3 9<br>RTHERM7 3 2 15<br>RTHERM8 2 TL 23<br>}<br>**RTHERM6**<br>**RTHERM8**<br>**RTHERM7**<br>**RTHERM5**<br>**RTHERM4**<br>**RTHERM3**<br>**RTHERM2**<br>**RTHERM1**<br>**TABLE 1. THERMAL MODELS**|**_SPICE Thermal Model_**<br>REV Aug 2002<br>FDS3992<br>Copper Area =1.0 in2<br>CTHERM1 TH 8 4e-4<br>CTHERM2 8 7 5e-3<br>CTHERM3 7 6 6e-2<br>CTHERM4 6 5 9e-2<br>CTHERM5 5 4 3e-1<br>CTHERM6 4 3 4e-1<br>CTHERM7 3 2 9e-1<br>CTHERM8 2 TL 2<br>RTHERM1 TH 8 5e-1<br>RTHERM2 8 7 6e-1<br>RTHERM3 7 6 4<br>RTHERM4 6 5 5<br>RTHERM5 5 4 8<br>RTHERM6 4 3 9<br>RTHERM7 3 2 15<br>RTHERM8 2 TL 23<br>**_SABER Thermal Model_**<br>Copper Area = 1.0 in2<br>template thermal_model th tl<br>thermal_c th, tl<br>{<br>CTHERM1 TH 8 4e-4<br>CTHERM2 8 7 5e-3<br>CTHERM3 7 6 6e-2<br>CTHERM4 6 5 9e-2<br>CTHERM5 5 4 3e-1<br>CTHERM6 4 3 4e-1<br>CTHERM7 3 2 9e-1<br>CTHERM8 2 TL 2<br>RTHERM1 TH 8 5e-1<br>RTHERM2 8 7 6e-1<br>RTHERM3 7 6 4<br>RTHERM4 6 5 5<br>RTHERM5 5 4 8<br>RTHERM6 4 3 9<br>RTHERM7 3 2 15<br>RTHERM8 2 TL 23<br>}<br>**RTHERM6**<br>**RTHERM8**<br>**RTHERM7**<br>**RTHERM5**<br>**RTHERM4**<br>**RTHERM3**<br>**RTHERM2**<br>**RTHERM1**<br>**TABLE 1. THERMAL MODELS**|**_SPICE Thermal Model_**<br>REV Aug 2002<br>FDS3992<br>Copper Area =1.0 in2<br>CTHERM1 TH 8 4e-4<br>CTHERM2 8 7 5e-3<br>CTHERM3 7 6 6e-2<br>CTHERM4 6 5 9e-2<br>CTHERM5 5 4 3e-1<br>CTHERM6 4 3 4e-1<br>CTHERM7 3 2 9e-1<br>CTHERM8 2 TL 2<br>RTHERM1 TH 8 5e-1<br>RTHERM2 8 7 6e-1<br>RTHERM3 7 6 4<br>RTHERM4 6 5 5<br>RTHERM5 5 4 8<br>RTHERM6 4 3 9<br>RTHERM7 3 2 15<br>RTHERM8 2 TL 23<br>**_SABER Thermal Model_**<br>Copper Area = 1.0 in2<br>template thermal_model th tl<br>thermal_c th, tl<br>{<br>CTHERM1 TH 8 4e-4<br>CTHERM2 8 7 5e-3<br>CTHERM3 7 6 6e-2<br>CTHERM4 6 5 9e-2<br>CTHERM5 5 4 3e-1<br>CTHERM6 4 3 4e-1<br>CTHERM7 3 2 9e-1<br>CTHERM8 2 TL 2<br>RTHERM1 TH 8 5e-1<br>RTHERM2 8 7 6e-1<br>RTHERM3 7 6 4<br>RTHERM4 6 5 5<br>RTHERM5 5 4 8<br>RTHERM6 4 3 9<br>RTHERM7 3 2 15<br>RTHERM8 2 TL 23<br>}<br>**RTHERM6**<br>**RTHERM8**<br>**RTHERM7**<br>**RTHERM5**<br>**RTHERM4**<br>**RTHERM3**<br>**RTHERM2**<br>**RTHERM1**<br>**TABLE 1. THERMAL MODELS**|**CTHERM4**<br>**CTHERM6**<br>**CTHERM5**<br>**CTHERM3**<br>**CTHERM2**<br>**CTHERM1**<br>**tl**<br>**2**<br>**3**<br>**4**<br>**5**<br>**6**<br>**7**<br>**JUNCTION**<br>**CASE**<br>**8**<br>**th**<br>**CTHERM7**<br>**CTHERM8**<br>**0.76 in2**<br>**1.0 in2**<br>4.0e-1<br>4.0e-1<br>9.0e-1<br>9.0e-1<br>2.0<br>2.0<br>10<br>9<br>16<br>15<br>28<br>23|**CTHERM4**<br>**CTHERM6**<br>**CTHERM5**<br>**CTHERM3**<br>**CTHERM2**<br>**CTHERM1**<br>**tl**<br>**2**<br>**3**<br>**4**<br>**5**<br>**6**<br>**7**<br>**JUNCTION**<br>**CASE**<br>**8**<br>**th**<br>**CTHERM7**<br>**CTHERM8**<br>**0.76 in2**<br>**1.0 in2**<br>4.0e-1<br>4.0e-1<br>9.0e-1<br>9.0e-1<br>2.0<br>2.0<br>10<br>9<br>16<br>15<br>28<br>23|**FDS3992**|
|---|---|---|---|---|---|---|---|---|
||**COMPONANT**|**0.04 in2**|**0.28 in2**|**0.52 in2**||**0.76 in2**|**1.0 in2**||
||CTHERM6|3.2e-1|3.5e-1|4.0e-1||4.0e-1|4.0e-1||
||CTHERM7|8.5e-1|9.0e-1|9.0e-1||9.0e-1|9.0e-1||
||CTHERM8|0.3|1.8|2.0||2.0|2.0||
||RTHERM6|24|18|12||10|9||
||RTHERM7|36|21|18||16|15||
||RTHERM8|53|37|30||28|23||
||||||||||



©2004 Fairchild Semiconductor Corporation 

FDS3992 Rev. C 

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