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FDPC5018SG
Dual MOSFET, N Channel, 30 V, 30 V, 109 A, 109 A, 1400 µohm
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- Manufacturer: ONSEMI
- Product type: Dual MOSFETs
- Transistor Polarity:Dual N Channel; Continuous Drain Current Id:109A; Drain Source Voltage Vds:30V; On Resistance Rds(on):0.0014ohm; Rds(on) Test Voltage Vgs:10V; Threshold Voltage
- MSL: MSL 1 - Unlimited
- SVHC: Lead (25-Jun-2025)
- No. of Pins: 8Pins
- Channel Type: N Channel
- Product Range: PowerTrench Series
- Qualification: -
- Transistor Case Style: PQFN
- Operating Temperature Max: 150°C
- Power Dissipation N Channel: 29W
- Power Dissipation P Channel: 29W
- Drain Source Voltage Vds N Channel: 30V
- Drain Source Voltage Vds P Channel: 30V
- Continuous Drain Current Id N Channel: 109A
- Continuous Drain Current Id P Channel: 109A
- Drain Source On State Resistance N Channel: 1400µohm
- Drain Source On State Resistance P Channel: 1400µohm
| Delivery and price | |
|---|---|
| Units per pack | 1500 |
| Price | 0.661 € |
| Current stock | 1000+ |
| Lead time | 30 days |
Datasheet
## **Is Now Part of** ## **To learn more about ON Semiconductor, please visit our website at www.onsemi.com** Please note: As part of the Fairchild Semiconductor integration, some of the Fairchild orderable part numbers will need to change in order to meet ON Semiconductor’s system requirements. Since the ON Semiconductor product management systems do not have the ability to manage part nomenclature that utilizes an underscore (_), the underscore (_) in the Fairchild part numbers will be changed to a dash (-). This document may contain device numbers with an underscore (_). Please check the ON Semiconductor website to verify the updated device numbers. The most current and up-to-date ordering information can be found at www.onsemi.com. Please email any questions regarding the system integration to Fairchild_questions@onsemi.com. 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This literature is subject to all applicable copyright laws and is not for resale in any manner. **==> picture [70 x 9] intentionally omitted <==** **----- Start of picture text -----**<br> September 2015<br>**----- End of picture text -----**<br> ## **FDPC5018SG** ## **PowerTrench[®] Power Clip 30V Asymmetric Dual N-Channel MOSFET** ## **General Description** ## **Features** Q1: N-Channel This device includes two specialized N-Channel MOSFETs in a dual package. The switch node has been internally connected to enable easy placement and routing of synchronous buck converters. The control MOSFET (Q1) and synchronous SyncFET[TM] (Q2) have been designed to provide optimal power efficiency. - Max rDS(on) = 5.0 mΩ at VGS = 10 V, ID = 17 A i[|] Max rDS(on) = 6.5 mΩ at VGS = 4.5 V, ID = 14 A - Q2: N-Channel Max rDS(on) = 1.6 mΩ at VGS = 10 V, ID = 32 A Max rDS(on) = 2.0 mΩ at VGS = 4.5 V, ID = 28 A ## **Applications** Low Inductance Packaging Shortens Rise/Fall Times, Resulting in Lower Switching Losses i | Computing . MOSFET Integration Enables Optimum Layout for i| Communications Lower Circuit Inductance and Reduced SwitchNode Ringing foto fo 7 General Purpose Point of Load RoHS Compliant ||**PIN1**|||**PIN1**|**PAD10**<br>**V+(HSD)**||||||||||| |---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---| |||||**HSG**|||||**LSG**|**HSG**|||||**LSG**| |||||**GR**<br>=|=|:|**PAD9**<br>boa|~|**SW**|**GR**||r|**SW**<br>a2|a|**SW**| |||||**V+**|||**GND(LSS)**||**SW**|**V+**|||||**SW**| |||||||||-||||||a|| |||||**V+**|||||**SW**|**V+**|||||**SW**| ||**Top**<br>**Power Clip 5X6**|**Bottom**|||||||||||||| |**Pin**|**Name**<br>**Description**|**Pin**||**Name**|**Description**||||**Pin**|||**Name**||**Description**|| |1|HSG<br>High Side Gate 3,4,10|h Side Gate 3,4,10||V+(HSD)<br>High Side Drain|||||8|||LSG||Low Side Gate|| |2|GR<br>Gate Return|5,6,7||SW<br>SwitchingNode, Low Side Drain|||Node, Low Side Drain|Node, Low Side Drain 9||||GND(LSS)||Low Side Source|| |**MOSFET Maximum Ratings **|||TA= 25 °C unless otherwise noted.||||||||||||| |**MOSFET Maximum Ratings**<br>~~Re~~|**MOSFET Maximum Ratings **TA= 25 °C unless otherwise noted.|||| |---|---|---|---|---| |**Symbol**<br>~~Re~~<br>~~Re~~|**Parameter**|**Q1**|**Q2**|**Units**| |VDS<br>~~Re~~<br>~~Re~~<br>~~Re~~|Drain to Source Voltage|30|30|V| |Bvdsst<br>~~Re~~<br>~~Re~~<br>~~Rea~~|Bvdsst(transient)< 100nS<br>~~a~~|32.5<br>~~a~~|32.5<br>~~a~~|V| |VGS<br>~~Re~~<br>~~Rea~~|Gate to Source Voltage<br>~~a~~|±20<br>~~a~~|±12<br>~~a~~|V| |ID<br>~~Rea~~<br>~~RR~~<br>~~RR~~<br>~~**a**~~<br>~~Re~~|Drain Current -Continuous<br>TC = 25 °C(Note 5)<br>~~a~~|56<br>~~a~~|109<br>~~a~~|A| ||-Continuous<br>TC = 100 °C(Note 5)<br>~~a~~<br>~~RR~~|35<br>~~a~~<br>~~RR~~|69<br>~~a~~<br>~~RR~~|| ||-Continuous<br>TA= 25 °C<br>~~RR~~<br>~~RR~~|17Note1a<br>~~RR~~<br>~~RR~~|32Note1b<br>~~RR~~<br>~~RR~~|| ||-Pulsed<br>TA= 25 °C(Note 4)<br>~~RR~~<br>~~**a**~~<br>|227<br>~~RR~~<br>~~**a**~~<br>|704<br>~~RR~~<br>~~**a**~~<br>|| |EAS<br>~~**a**~~<br>~~Re~~|Single Pulse Avalanche Energy<br> (Note 3)<br>~~**a**~~<br>|54<br>~~**a**~~<br>|181<br>~~**a**~~<br>|mJ| |PD<br>~~**a**~~<br>~~ReRR~~<br>~~RO~~|Power Dissipation for Single Operation<br>TC = 25 °C<br>~~**a**~~<br>|23<br>~~**a**~~<br>|29<br>~~**a**~~<br>|W| ||Power Dissipation for Single Operation<br>TA= 25 °C<br>~~RR~~|2.1Note1a<br>~~RR~~|2.3Note1b<br>~~RR~~|| ||Power Dissipation for Single Operation<br>TA= 25 °C<br>~~RR~~<br>~~RO~~|1.0Note1c<br>~~RR~~<br>~~RO~~|1.1Note1d<br>~~RR~~<br>~~RO~~|| |TJ, TSTG<br>~~RO~~<br>~~Ce~~|Operatingand Storage Junction Temperature Range<br>~~RO~~<br>~~Ce~~|-55 to +150<br>~~RO~~<br>~~Ce~~||°C<br>~~Ce~~| ## **Thermal Characteristics** |RθJC|Thermal Resistance, Junction to Case|5.6|4.3|°C/W| |---|---|---|---|---| |RθJA|Thermal Resistance, Junction to Ambient|60Note1a|55Note1b|| |RθJA|Thermal Resistance, Junction to Ambient|130Note1c|120Note1d|| ©2015 Fairchild Semiconductor Corporation FDPC5018SG Rev.1.1 www.fairchildsemi.com **1** ## **Package Marking and Ordering Information** |**Device Marking**|**Device Marking**|**Device**|**Package**|**Package**|**Reel Size**||**Tape Width**|**Tape Width**|**Tape Width**|**Tape Width**|**Quantity**|**Quantity**| |---|---|---|---|---|---|---|---|---|---|---|---|---| |FDPC5018SG||FDPC5018SG|Power Clip56||13 ”||12 mm||||3000 units|| |**Electrical Characteristics**TJ= 25 °C unless otherwise noted.||||||||||||| |**Symbol**|**Parameter**|||**Test Conditions**||**Type**||**Min**||**Typ**|**Max**|**Units**| |**Off Characteristics**||||||||||||| |BVDSS|Drain to Source Breakdown Voltage|||ID= 250μA, VGS= 0 V<br>ID= 1 mA, VGS= 0 V||Q1<br>Q2||30<br>30||||V| |ΔBVDSS<br>ΔTJ|Breakdown Voltage Temperature<br>Coefficient|||ID= 250μA, referenced to 25 °C<br>ID= 10 mA, referenced to 25 °C||Q1<br>Q2||||15<br>19||mV/°C| |IDSS|Zero Gate Voltage Drain Current|||VDS= 24 V, VGS= 0 V<br>VDS= 24 V, VGS = 0 V||Q1<br>Q2|||||1<br>500|μA<br>μA| |IGSS|Gate to Source Leakage Current,<br>Forward|||VGS= 20 V, VDS= 0 V<br>VGS= 12 V, VDS= 0 V||Q1<br>Q2|||||100<br>100|nA<br>nA| |**On Characteristics**||||||||||||| |VGS(th)|Gate to Source Threshold Voltage|||VGS= VDS, ID= 250μA<br>VGS= VDS, ID= 1 mA||Q1<br>Q2||1.0<br>1.0||1.7<br>1.6|3.0<br>3.0|V| |ΔVGS(th)<br>ΔTJ|Gate to Source Threshold Voltage<br>Temperature Coefficient|||ID= 250μA, referenced to 25 °C<br>ID= 10 mA, referenced to 25 °C||Q1<br>Q2||||-5<br>-3||mV/°C| |rDS(on)|Drain to Source On Resistance|||VGS= 10V, ID= 17 A<br>VGS= 4.5 V, ID= 14 A<br>VGS= 10 V, ID= 17 A,TJ=125 °C||Q1||||4.1<br>5.4<br>5.7|5.0<br>6.5<br>7.0|mΩ| |||||VGS= 10V, ID= 32 A<br>VGS= 4.5 V, ID= 28 A<br>VGS= 10 V, ID= 32 A ,TJ=125 °C||Q2||||1.4<br>1.7<br>2.1|1.6<br>2.0<br>2.4|| |gFS|Forward Transconductance|||VDS= 5 V, ID= 17 A<br>VDS= 5 V, ID= 32 A||Q1<br>Q2||||93<br>188||S| |**Dynamic Characteristics**||||||||||||| |Ciss|Input Capacitance|||Q1:<br>VDS= 15 V, VGS= 0 V, f = 1 MHZ<br>Q2:<br>VDS= 15 V, VGS= 0 V, f = 1 MHZ||Q1<br>Q2||||1224<br>4593|1715<br>6430|pF| |Coss|Output Capacitance|||||Q1<br>Q2||||397<br>1210|560<br>1695|pF| |Crss|Reverse Transfer Capacitance|||||Q1<br>Q2||||42<br>80|60<br>115|pF| |Rg|Gate Resistance|||||Q1<br>Q2||0.1<br>0.1||0.5<br>0.8|1.5<br>2.4|Ω| |**Switching Characteristics**||||||||||||| |td(on)|Turn-On Delay Time|||Q1:<br>VDD= 15 V, ID= 17 A, RGEN= 6Ω<br>Q2:<br>VDD= 15 V, ID= 32 A, RGEN= 6Ω||Q1<br>Q2||||8<br>14|16<br>25|ns| |tr|Rise Time|||||Q1<br>Q2||||2<br>5|10<br>10|ns| |td(off)|Turn-Off Delay Time|||||Q1<br>Q2||||18<br>38|33<br>61|ns| |tf|Fall Time|||||Q1<br>Q2||||2<br>4|10<br>10|ns| |Qg|Total Gate Charge|||VGS= 0 V to 10 V|Q1<br>VDD= 15 V, ID<br>= 17 A<br>Q2<br>VDD= 15 V, ID<br>= 32 A|Q1<br>Q2||||17<br>62|24<br>87|nC| |Qg|Total Gate Charge|||VGS= 0 V to 4.5 V||Q1<br>Q2||||8<br>28|11<br>40|nC| |Qgs|Gate to Source Gate Charge|||||Q1<br>Q2||||3.1<br>11||nC| |Qgd|Gate to Drain “Miller” Charge|||||Q1<br>Q2||||2.0<br>5.3||nC| ©2015 Fairchild Semiconductor Corporation **2** www.fairchildsemi.com FDPC5018SG Rev.1.1 ## **Electrical Characteristics** TJ = 25 °C unless otherwise noted. |VSD|Source to Drain Diode Forward Voltage|VGS= 0 V, IS= 17 A (Note 2)<br>VGS = 0 V, IS = 32 A(Note 2)|Q1<br>Q2||0.8<br>0.8|1.2<br>1.2|V| |---|---|---|---|---|---|---|---| |trr|Reverse Recovery Time|Q1<br>IF= 17 A, di/dt = 100 A/μs<br>Q2<br>IF= 32 A, di/dt = 240 A/μs|Q1<br>Q2||23<br>32|37<br>51|ns| |Qrr|Reverse Recovery Charge||Q1<br>Q2||8<br>40|16<br>64|nC| Notes: 1.RθJA is determined with the device mounted on a 1 in[2] pad 2 oz copper pad on a 1.5 x 1.5 in. board of FR-4 material, R θCA is determined by the user's board design. b. 55 °C/W when mounted on a. 60 °C/W when mounted on a 1 in[2 ] pad of 2 oz copper a 1 in[2 ] pad of 2 oz copper 00000 00000 c. 130 °C/W when mounted on a d. 120 °C/W when mounted on a minimum pad of 2 oz copper minimum pad of 2 oz copper | 90 00000 - 2 Pulse Test: Pulse Width < 300 μs, Duty cycle < 2.0%. 3. Q1 :EAS of 54 mJ is based on starting TJ = 25[o] C; L = 3 mH, IAS = 6 A, VDD = 30 V, VGS = 10 V. 100% tested at L = 0.1 mH, IAS =20 A. Q2: EAS of 181 mJ is based on starting TJ = 25[o] C; L = 3 mH, IAS = 11 A, VDD = 30 V, VGS = 10 V.100% tested at L = 0.1 mH, IAS =36 A. 4. Pulsed Id refer to Fig.11 and Fig.24 SOA curve for more details. 5. Computed continuous current limited to Max Junction Temperature only, actual continuous current will be limited by thermal & electro-mechanical application board design. ©2015 Fairchild Semiconductor Corporation **3** www.fairchildsemi.com FDPC5018SG Rev.1.1 **Typical Characteristics (Q1 N-Channel)** TJ = 25°C unless otherwise noted. **==> picture [455 x 584] intentionally omitted <==** **----- Start of picture text -----**<br> 60 6.0<br>VGS = 10 V VGS = 4.5 V VGS = 3 V PULSE DURATION = 80 μ s<br>VGS = 6 V DUTY CYCLE = 0.5% MAX<br>VGS = 3.5 V<br>45 4.5<br>30 3.0<br>VGS = 3.5 V<br>15 VGS = 3 V 1.5 VGS = 4.5 V<br>PULSE DURATION = 80 μ s<br>DUTY CYCLE = 0.5% MAX VGS = 6 V VGS = 10 V<br>0 0.0<br>0.0 0.2 0.4 0.6 0.8 1.0 0 15 30 45 60<br>VDS, DRAIN TO SOURCE VOLTAGE (V) ID, DRAIN CURRENT (A)<br>Figure 1. On Region Characteristics Figure 2. Normalized On-Resistance<br>vs. Drain Current and Gate Voltage<br>1.6 40<br>1.5 V IDGS = 17 A = 10 V PULSE DURATION = 80 DUTY CYCLE = 0.5% MAX μ s<br>1.4 30<br>ID = 17 A<br>1.3<br>1.2 20<br>1.1<br>1.0 10 TJ = 125 [o] C<br>0.9<br>TJ = 25 [o] C<br>0.8 0<br>-75 -50 -25 0 25 50 75 100 125 150 2 3 4 5 6 7 8 9 10<br>TJ, JUNCTION TEMPERATURE ( [o] C) VGS, GATE TO SOURCE VOLTAGE (V)<br>Figure 3. Normalized On Resistance Figure 4. On-Resistance vs. Gate to<br>vs. Junction Temperature Source Voltage<br>60 60<br>PULSE DURATION = 80 μ s VGS = 0 V<br>DUTY CYCLE = 0.5% MAX 10<br>45<br>VDS = 5 V<br>1<br>30 0.1 T J = 150 [o] C TJ = 25 [ o] C<br>TJ = 150 [o] C TJ = 25 [o] C<br>15 T J = -55 [o] C<br>0.01<br>TJ = -55 [o] C<br>0 0.001<br>0 1 2 3 4 5 0.0 0.2 0.4 0.6 0.8 1.0 1.2<br>VGS, GATE TO SOURCE VOLTAGE (V) VSD, BODY DIODE FORWARD VOLTAGE (V)<br>NORMALIZED<br>, DRAIN CURRENT (A)<br>ID<br>DRAIN TO SOURCE ON-RESISTANCE<br>) Ω<br>(m<br>DRAIN TO<br>NORMALIZED rDS(on),<br>SOURCE ON-RESISTANCE<br> DRAIN TO SOURCE ON-RESISTANCE<br>, DRAIN CURRENT (A)<br>ID<br>, REVERSE DRAIN CURRENT (A)<br>IS<br>**----- End of picture text -----**<br> **Figure 5. Transfer Characteristics** **Figure 6. Forward Voltage vs. Source Current** ©2015 Fairchild Semiconductor Corporation **4** www.fairchildsemi.com FDPC5018SG Rev.1.1 ## **Typical Characteristics (Q1 N-Channel)** TJ = 25°C unless otherwise noted. **==> picture [454 x 582] intentionally omitted <==** **----- Start of picture text -----**<br> 10 3000<br>ID = 17 A C iss<br>8 1000<br>VDD = 10 V Coss<br>6<br>VDD = 15 V VDD = 20 V<br>4 100 Crss<br>2<br>f = 1 MHz<br>VGS = 0 V<br>0 10<br>0 4 8 12 16 20 0.1 1 10 30<br>Qg, GATE CHARGE (nC) VDS, DRAIN TO SOURCE VOLTAGE (V)<br>Figure 7. Gate Charge Characteristics Figure 8. Capacitance vs. Drain<br>to Source Voltage<br>30 60<br>45<br>10 VGS = 10 V<br>30<br>T J = 25 [ o] C<br>VGS = 4.5 V<br>TJ = 125 [o] C 15<br>R θ JC = 5.6 [o] C/W<br>1 0<br>0.001 0.01 0.1 1 10 100 25 50 75 100 125 150<br>tAV, TIME IN AVALANCHE (ms) TC, CASE TEMPERATURE (oC)<br>Figure 9. Unclamped Inductive Figure 10. Maximum Continuous Drain<br>Switching Capability Current vs. Case Temperature<br>500 5000<br>SINGLE PULSE<br>100 R θ JC = 5.6 [o] C/W<br>1000 TC = 25 [o] C<br>10 μ s<br>10<br>THIS AREA IS<br>LIMITED BY r<br>DS(on)<br>100 μ s 100<br>SINGLE PULSE<br>1 1 ms<br>TJ = MAX RATED 10 ms<br>R θ JC = 5.6 [ o] C/W CURVE BENT TO DC<br>T C = 25 [o] C MEASURED DATA<br>0.1 10<br>0.1 1 10 80 10-5 10-4 10-3 10-2 10-1 1<br>VDS, DRAIN to SOURCE VOLTAGE (V) t, PULSE WIDTH (sec)<br>CAPACITANCE (pF)<br>, GATE TO SOURCE VOLTAGE (V)<br>GS<br>V<br>DRAIN CURRENT (A)<br>,<br>ID<br>, AVALANCHE CURRENT (A)<br>IAS<br>, DRAIN CURRENT (A)<br>ID<br>PEAK TRANSIENT POWER (W)<br>,<br>(PK)<br>P<br>**----- End of picture text -----**<br> **Operating Area** **Power Dissipation** ©2015 Fairchild Semiconductor Corporation **5** www.fairchildsemi.com FDPC5018SG Rev.1.1 **==> picture [456 x 195] intentionally omitted <==** **----- Start of picture text -----**<br> Typical Characteristics (Q1 N-Channel) TJ = 25°C unless otherwise noted.<br>2<br>DUTY CYCLE-DESCENDING ORDER<br>1<br>D = 0.5<br> 0.2<br> 0.1<br> 0.05 PDM<br>0.1<br> 0.02<br> 0.01<br>t 1<br>t 2<br>SINGLE PULSE<br>0.01 NOTES:<br>Z θ JC(t) = r(t) x R θ JC<br>R θ JC = 5.6 [o] C/W<br>Peak TJ = PDM x Z θ JC(t) + TC<br>Duty Cycle, D = t1 / t2<br>0.001<br>10-5 10-4 10-3 10-2 10-1 1<br>t, RECTANGULAR PULSE DURATION (sec)<br>THERMAL RESISTANCE<br>r(t), NORMALIZED EFFECTIVE TRANSIENT<br>**----- End of picture text -----**<br> **Figure 13. Junction-to-Case Transient Thermal Response Curve** ©2015 Fairchild Semiconductor Corporation **6** www.fairchildsemi.com FDPC5018SG Rev.1.1 ## **Typical Characteristics (Q2 N-Channel)** TJ = 25 °C unless otherwise noted. **==> picture [456 x 594] intentionally omitted <==** **----- Start of picture text -----**<br> 120 10<br>PULSE DURATION = 80 DUTY CYCLE = 0.5% MAX μ s VGS = 2.5 V PULSE DURATION = 80DUTY CYCLE = 0.5% MAX μ s<br>8<br>90<br>VGS = 10 V<br>6<br>VGS = 4.5 V<br>60<br>VGS = 3.5 V 4 VGS = 3 V<br>VGS = 3 V VGS = 2.5 V<br>30 2 VGS = 3.5 V<br>0 0 VGS = 4.5 V VGS = 10 V<br>0 0.3 0.6 0.9 1.2 1.5 0 24 48 72 96 120<br>VDS, DRAIN TO SOURCE VOLTAGE (V) ID, DRAIN CURRENT (A)<br>Figure 14. On- Region Characteristics Figure 15. Normalized on-Resistance vs. Drain<br>Current and Gate Voltage<br>1.8 12<br>ID = 32 A PULSE DURATION = 80 μ s<br>1.6 V GS = 10 V DUTY CYCLE = 0.5% MAX<br>9<br>1.4 ID = 32 A<br>1.2 6<br>1.0 TJ = 125 [o] C<br>3<br>0.8<br>TJ = 25 [o] C<br>0.6 0<br>-75 -50 -25 0 25 50 75 100 125 150 2 3 4 5 6 7 8 9 10<br>TJ, JUNCTION TEMPERATURE ( [o] C) VGS, GATE TO SOURCE VOLTAGE (V)<br>Figure 16. Normalized On-Resistance Figure 17. On-Resistance vs. Gate to<br> vs. Junction Temperature Source Voltage<br>120 200<br>PULSE DURATION = 80 μ s 100 VGS = 0 V<br>DUTY CYCLE = 0.5% MAX<br>96<br>VDS = 5 V 10<br>72<br>1<br>TJ = 125 [o] C TJ = 25 [o] C TJ = 125 [o] C TJ = 25 [ o] C<br>48 0.1<br>TJ = -55 [o] C TJ = -55 [o] C<br>24 0.01<br>0 0.001<br>0 1 2 3 4 0.0 0.2 0.4 0.6 0.8 1.0 1.2<br>VGS, GATE TO SOURCE VOLTAGE (V) VSD, BODY DIODE FORWARD VOLTAGE (V)<br>NORMALIZED<br>, DRAIN CURRENT (A)<br>ID<br>DRAIN TO SOURCE ON-RESISTANCE<br>) Ω<br>(m<br>DRAIN TO<br>NORMALIZED rDS(on),<br>SOURCE ON-RESISTANCE<br> DRAIN TO SOURCE ON-RESISTANCE<br>, DRAIN CURRENT (A)<br>ID<br>, REVERSE DRAIN CURRENT (A)<br>IS<br>**----- End of picture text -----**<br> **Figure 18. Transfer Characteristics** **Figure 19. Source to Drain Diode Forward Voltage vs. Source Current** ©2015 Fairchild Semiconductor Corporation **7** www.fairchildsemi.com FDPC5018SG Rev.1.1 ## **Typical Characteristics (Q2 N-Channel)** TJ = 25°C unless otherwise noted. **==> picture [458 x 580] intentionally omitted <==** **----- Start of picture text -----**<br> 10 10000<br>ID = 32 A<br>8 C iss<br>VDD = 10 V<br>VDD = 15 V 1000<br>6 Coss<br>VDD = 20 V<br>4<br>100<br>2 C rss<br>f = 1 MHz<br>VGS = 0 V<br>0 10<br>0 14 28 42 56 70 0.1 1 10 30<br>Qg, GATE CHARGE (nC) VDS, DRAIN TO SOURCE VOLTAGE (V)<br>Figure 20. Gate Charge Characteristics Figure 21. Capacitance vs. Drain<br>to Source Voltage<br>100 120<br>96<br>VGS = 10 V<br>TJ = 25 [ o] C<br>72<br>10 TJ = 100 [o] C<br>VGS = 4.5 V<br>48<br>T J = 125 [o] C 24<br>R θ JC = 4.3 [o] C/W<br>1 0<br>0.001 0.01 0.1 1 10 100 1000 25 50 75 100 125 150<br>tAV, TIME IN AVALANCHE (ms) TC, CASE TEMPERATURE (oC)<br>Figure 22. Unclamped Inductive Figure 23. Maximum Continuous Drain<br>Switching Capability Current vs. Case Temperature<br>1000 10000<br>SINGLE PULSE<br>10 μ s R θ JC = 4.3 [o] C/W<br>100 T C = 25 [o] C<br>1000<br>100 μ s<br>10 THIS AREA IS<br>LIMITED BY rDS(on) 1 ms<br>100<br>SINGLE PULSE 10 ms<br>1 TJ = MAX RATED 100 ms/DC<br>R θ JC = 4.3 [ o] C/W CURVE BENT TO<br>T C = 25 [o] C MEASURED DATA<br>0.1 10<br>0.1 1 10 100 200 10-5 10-4 10-3 10-2 10-1 1<br>VDS, DRAIN to SOURCE VOLTAGE (V) t, PULSE WIDTH (sec)<br>CAPACITANCE (pF)<br>, GATE TO SOURCE VOLTAGE (V)<br>GS<br>V<br>DRAIN CURRENT (A)<br>,<br>ID<br>, AVALANCHE CURRENT (A)<br>IAS<br>, DRAIN CURRENT (A)<br>ID<br>PEAK TRANSIENT POWER (W)<br>,<br>(PK)<br>P<br>**----- End of picture text -----**<br> **Operating Area** **Figure 25. Single Pulse Maximum Power Dissipation** ©2015 Fairchild Semiconductor Corporation **8** www.fairchildsemi.com FDPC5018SG Rev.1.1 **==> picture [454 x 193] intentionally omitted <==** **----- Start of picture text -----**<br> Typical Characteristics (Q2 N-Channel) TJ = 25 °C unless otherwise noted.<br>2<br>DUTY CYCLE-DESCENDING ORDER<br>1<br>D = 0.5<br> 0.2<br> 0.1<br>0.1 0.05 PDM<br>0.02<br> 0.01<br>t 1<br>t 2<br>0.01 NOTES:<br>Z θ JC(t) = r(t) x R θ JC<br>SINGLE PULSE R θ JC = 4.3 [o] C/W<br>Peak TJ = PDM x Z θ JC(t) + TC<br>Duty Cycle, D = t1 / t2<br>0.001<br>10-5 10-4 10-3 10-2 10-1 1<br>t, RECTANGULAR PULSE DURATION (sec)<br>THERMAL RESISTANCE<br>r(t), NORMALIZED EFFECTIVE TRANSIENT<br>**----- End of picture text -----**<br> **==> picture [278 x 9] intentionally omitted <==** **----- Start of picture text -----**<br> Figure 26. Junction-to-Case Transient Thermal Response Curve<br>**----- End of picture text -----**<br> ©2015 Fairchild Semiconductor Corporation **9** www.fairchildsemi.com FDPC5018SG Rev.1.1 ## **Typical Characteristics** (continued) ## **SyncFET[TM] Schottky Body Diode Characteristics** Fairchild’s SyncFET[TM] process embeds a Schottky diode in parallel with PowerTrench **[®]** MOSFET. This diode exhibits similar characteristics to a discrete external Schottky diode in parallel with a MOSFET. Figure 27 shows the reverse recovery characteristic of the FDPC5018SG. Schottky barrier diodes exhibit significant leakage at high temperature and high reverse voltage. This will increase the power in the device. **==> picture [457 x 171] intentionally omitted <==** **----- Start of picture text -----**<br> 35 10-2<br>28 T J = 125 [o] C<br>10-3<br>21<br>di/dt = 240 A/ μ s T J = 100 [o] C<br>14 10-4<br>7<br>10-5 TJ = 25 [o] C<br>0<br>10-6<br>0 100 200 300 400 500 0 5 10 15 20 25 30<br>TIME (ns) VDS, REVERSE VOLTAGE (V)<br>CURRENT (A)<br>, REVERSE LEAKAGE CURRENT (A)<br>IDSS<br>**----- End of picture text -----**<br> **Figure 27. FDPC5018SG SyncFET[TM] Body Diode Reverse Recovery Characteristic** **Figure 28. SyncFET[TM] Body Diode Reverse Leakage vs. Drain-Source Voltage** ©2015 Fairchild Semiconductor Corporation **10** www.fairchildsemi.com FDPC5018SG Rev.1.1 **==> picture [398 x 487] intentionally omitted <==** **----- Start of picture text -----**<br> 5.00<br>4.56<br>4.20<br>0.10 C 54.90.10 A<br>2X PKG 1.27<br>CL B 4 3 2 1<br>4 1 3.30<br>2.48<br>2.08<br>1.01<br>6.60<br>PKG CL 6.105.90 0.00 2.65 0.400.83<br>1.43<br>1.98<br>2.48<br>0.82<br>3.30<br>PIN #1 5 8 0.10 C 5 6 7 8<br>2X<br>INDICATOR TOP VIEW 0.75<br>SEE<br>DETAIL A<br>RECOMMENDED LAND PATTERN<br>SIDE VIEW<br>0.10 C A B<br>3.15±.05 0.05 C<br>3.81<br>1.27<br>0.51<br>5 6 7 8<br>0.65±.05 1.57±.05<br>NOTES: UNLESS OTHERWISE SPECIFIED<br>0.65±.05<br>2.46±.05<br>1.37±.05 A) DOES NOT FULLY CONFORM TO<br>0.53±.05 JEDEC REGISTRATION, MO-229,<br>0.91±.05 DATED 11/2001.<br>B) ALL DIMENSIONS ARE IN<br>0.49±.05 0.48±.05 MILLIMETERS.<br>4 3 2 1<br>C) DIMENSIONS DO NOT INCLUDE<br>0.51±.05 BURRS OR MOLD FLASH. MOLD<br>3.90±.05 FLASH OR BURRS DOES NOT<br>4.22±.05 EXCEED 0.10MM.<br>5.00±.05<br>D) DIMENSIONING AND TOLERANCING<br>BOTTOM VIEW<br>1.53 1.01 0.00 1.08 1.48 1.53 2.29<br>**----- End of picture text -----**<br> NOTES: UNLESS OTHERWISE SPECIFIED - D) DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994. - E) DRAWING FILE NAME: PQFN08KREV2 **==> picture [202 x 98] intentionally omitted <==** **----- Start of picture text -----**<br> 0.10 C<br>0.08 C<br>0.80 0.30 0.05 C<br>0.70 0.20 0.00 SEATING<br>PLANE<br>(SCALE: 2X)<br>**----- End of picture text -----**<br> ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. 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