FDMS7602S

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## **FDMS7602S** 

## **Dual N-Channel PowerTrench[®] MOSFET Q1: 30 V, 30 A, 7.5 m** Ω **Q2: 30 V, 30 A, 5.0 m** Ω 

## **Features** 

Q1: N-Channel 

Max rDS(on) = 7.5 mΩ at VGS = 10 V, ID = 12 A Max rDS(on) = 12 mΩ at VGS = 4.5 V, ID = 10 A 

Q2: N-Channel Max rDS(on) = 5.0 mΩ at VGS = 10 V, ID = 17 A Max rDS(on) = 6.8 mΩ at VGS = 4.5 V, ID = 14 A RoHS Compliant 

## **General Description** 

This device includes two specialized N-Channel MOSFETs in a dual MLP package.The switch node has been internally connected to enable easy placement and routing of synchronous buck converters. The control MOSFET (Q1) and synchronous SyncFET[TM ] (Q2) have been designed to provide optimal power efficiency. 

## **Applications** 

Computing 

Communications 

General Purpose Point of Load 

Notebook VCORE 

|**S2S2S2G2**<br>**D1D1**<br>**D1 G1**<br>**D1**<br>**S1/D2**<br>**Top**<br>**Bottom**<br>nin|**S2S2S2G2**<br>**D1D1**<br>**D1 G1**<br>**D1**<br>**S1/D2**<br>**Top**<br>**Bottom**<br>nin|**S2**<br>**S2**<br>**S2**<br>**G2**|**5**<br>**6**<br>**7**<br>**8**|**5**<br>**6**<br>**7**<br>**8**|**Q** **2**|**Q** **2**||**4**<br>**3**<br>**2**<br>**1**<br>**Q** **1**|**D1**<br>**D1**<br>**D1**<br>**G1**|
|---|---|---|---|---|---|---|---|---|---|
|**Power 56**||||||||||
|**MOSFET Maximum Ratings  **TA= 25 °C unless otherwise noted||||||||||
|**Symbol**<br>**Parameter**|||||**Q1**|||**Q2**|**Units**|
|VDS<br>Drain to Source Voltage|||||30|||30|V|
|VGS<br>Gate to Source Voltage|(Note 3)||||±20|||±20|V|
|Drain Current      -Continuous|TC = 25 °C|= 25 °C|||30|||30||
|ID<br>-Continuous|TA= 25 °C|= 25 °C|||121a|||171b|A|
|-Pulsed|||||40|||60||
|PD<br>Power Dissipation  for Single Operation<br>Power Dissipation  for Single Operation|TA= 25 °C<br>TA= 25 °C|= 25 °C<br>= 25 °C|||2.21a<br>1.01c|||2.51b<br>1.01d|W|
|TJ, TSTG<br>Operatingand Storage Junction Temperature Range|||||-55 to +150|||-55 to +150|°C|
|**Thermal Characteristics**||||||||||
|RθJA<br>Thermal Resistance, Junction to Ambient<br>571a<br>501b<br>°C/W<br>RθJA<br>Thermal Resistance, Junction to Ambient<br>1251c<br>1201d<br>RθJC<br>Thermal Resistance, Junction to Case<br>3.5<br>2<br>~~————~~||||||||||
|**Package Marking and Ordering Information**||||||||||
|**Device Marking**<br>**Device**<br>**Package**<br>**Reel Size**<br>**Tape Width**<br>**Quantity**<br>FDMS7602S<br>FDMS7602S<br>Power 56<br>13 ”<br>12 mm<br>3000 units<br>~~ee~~||||||||||



©2010 Fairchild Semiconductor Corporation **1** FDMS7602S Rev.C2 

www.fairchildsemi.com 

## **Electrical Characteristics** TJ = 25 °C unless otherwise noted 

|**Electrica**|**l Characteristics**TJ= 25 °C u|nless otherwise noted||||||||
|---|---|---|---|---|---|---|---|---|---|
|**Symbol**|**Parameter**|**Test Conditions**|**Type**|**Min**||**Typ**|**Max**||**Units**|
|**Off Characteristics**||||||||||
|BVDSS|Drain to Source Breakdown Voltage|ID= 250μA, VGS= 0 V<br>ID= 1 mA, VGS= 0 V|Q1<br>Q2|30<br>30|||||V|
|ΔBVDSS<br>ΔTJ|Breakdown Voltage Temperature<br>Coefficient|ID= 250μA, referenced to 25 °C<br>ID= 1 mA, referenced to 25 °C|Q1<br>Q2|||15<br>15|||mV/°C|
|IDSS|Zero Gate Voltage Drain Current|VDS= 24 V,   VGS= 0 V|Q1<br>Q2||||1<br>500||μA<br>μA|
|IGSS|Gate to Source Leakage Current|VGS= 20 V, VDS= 0 V<br>VGS= 20 V, VDS= 0 V|Q1<br>Q2||||100<br>100||nA<br>nA|
|**On Characteristics**||||||||||
|VGS(th)|Gate to Source Threshold Voltage|VGS= VDS,  ID= 250μA<br>VGS= VDS,  ID= 1 mA|Q1<br>Q2|1<br>1||1.8<br>1.8|3<br>3||V|
|ΔVGS(th)<br>ΔTJ|Gate to Source Threshold Voltage<br>Temperature Coefficient|ID= 250μA, referenced to 25 °C<br>ID= 1 mA, referenced to 25 °C|Q1<br>Q2|||-6<br>-5|||mV/°C|
|rDS(on)|Drain to Source On Resistance|VGS= 10 V,  ID= 12 A<br>VGS= 4.5 V, ID= 10 A<br>VGS= 10 V,  ID= 12 A , TJ= 125 °C|Q1|||6.0<br>8.5<br>8.3|7.5<br>12<br>12||mΩ|
|||VGS= 10 V,  ID= 17 A<br>VGS= 4.5 V, ID= 14 A<br>VGS= 10 V,  ID= 17 A , TJ= 125 °C|Q2|||4.2<br>5.4<br>4.9|5.0<br>6.8<br>7.2|||
|gFS|Forward Transconductance|VDS= 5 V,  ID= 12 A<br>VDS= 5 V,  ID= 17 A|Q1<br>Q2|||63<br>87|||S|
|**Dynamic Characteristics**||||||||||
|Ciss|Input Capacitance|Q1:<br>VDS= 15 V, VGS= 0 V, f = 1 MHZ<br>Q2:<br>VDS= 15 V, VGS= 0 V, f = 1 MHZ|Q1<br>Q2|||1315<br>2020|1750<br>2690||pF|
|Coss|Output Capacitance||Q1<br>Q2|||445<br>860|600<br>1145||pF|
|Crss|Reverse Transfer Capacitance||Q1<br>Q2|||45<br>95|70<br>145||pF|
|Rg|Gate Resistance||Q1<br>Q2|||0.9<br>0.7|||Ω|
|**Switching Characteristics**||||||||||
|td(on)|Turn-On Delay Time|Q1:<br>VDD= 15 V, ID= 12 A,  RGEN= 6Ω<br>Q2:<br>VDD= 15 V, ID= 17 A,  RGEN= 6Ω|Q1<br>Q2|||8.6<br>11||18<br>20|ns|
|tr|Rise Time||Q1<br>Q2|||2.5<br>3.8||10<br>10|ns|
|td(off)|Turn-Off Delay Time||Q1<br>Q2|||20<br>27||32<br>43|ns|
|tf|Fall Time||Q1<br>Q2|||2.3<br>3.2||10<br>10|ns|
|Qg|Total Gate Charge|VGS= 0  V to 10 V|Q1<br>Q2|||20<br>33||28<br>46|nC|
|Qg|Total Gate Charge|VGS= 0  V to 4.5 V|Q1<br>Q2|||9.3<br>16||13<br>22|nC|
|Qgs|Gate to Source Gate Charge||Q1<br>Q2|||4.3<br>5.8|||nC|
|Qgd|Gate to Drain “Miller” Charge||Q1<br>Q2|||2.2<br>4.6|||nC|



©2010 Fairchild Semiconductor Corporation FDMS7602S Rev.C2 

www.fairchildsemi.com 

## **Electrical Characteristics** TJ = 25 °C unless otherwise noted 

|VSD|Source to Drain Diode  Forward Voltage|VGS= 0 V, IS= 12 A           (Note 2)<br>VGS = 0 V, IS = 17 A(Note 2)|Q1<br>Q2||0.8<br>0.8|1.2<br>1.2|V|
|---|---|---|---|---|---|---|---|
|trr|Reverse Recovery Time|Q1<br>IF= 12 A, di/dt = 100 A/μs<br>Q2<br>IF= 17 A, di/dt = 300 A/μs|Q1<br>Q2||27<br>29|43<br>46|ns|
|Qrr|Reverse Recovery Charge||Q1<br>Q2||10<br>31|18<br>50|nC|



## **Notes:** 

**1:** RθJA is determined with the device mounted on a 1 in[2] pad 2 oz copper pad on a 1.5 x 1.5 in. board of FR-4 material. RθJC is guaranteed by design while RθCA is determined by the user's board design. 

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b. 50 °C/W when mounted on<br>a. 57 °C/W when mounted on a 1 in [2  ]  pad of  2 oz  copper<br>a 1 in [2  ]  pad of  2 oz  copper<br>So000<br>c. 125 °C/W when mounted on  a d. 120 °C/W when mounted on  a<br>minimum pad of 2 oz copper  minimum pad of 2 oz copper<br>**----- End of picture text -----**<br>


- **2:** Pulse Test: Pulse Width < 300 μs, Duty cycle < 2.0%. 

- **3:** As an N-ch device, the negative Vgs rating is for low duty cycle pulse ocurrence only. No continuous rating is implied. 

©2010 Fairchild Semiconductor Corporation FDMS7602S Rev.C2 

www.fairchildsemi.com 

## **Typical Characteristics (Q1 N-Channel)** TJ = 25°C unless otherwise noted 

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40 4<br>VGS = 10 V PULSE DURATION = 80  μ s<br>VGS = 6 V DUTY CYCLE = 0.5% MAX<br>30 3<br>VGS =  4.5 V VGS = 3.5 V<br>VGS =  4 V VGS = 4 V<br>20 2<br>VGS =  4.5 V<br>10 1<br>VGS =  3.5 V PULSE DURATION = 80 DUTY CYCLE = 0.5% MAX μ s VGS = 6 V VGS =  10 V<br>0 0<br>0.0 0.5 1.0 1.5 2.0 0 10 20 30 40<br>VDS, DRAIN TO SOURCE VOLTAGE (V) ID, DRAIN CURRENT (A)<br>Figure 1.  On Region Characteristics Figure 2.      Normalized On-Resistance<br>vs Drain Current and Gate Voltage<br>1.6 40<br>ID = 12 A PULSE DURATION = 80  μ s<br>VGS = 10 V DUTY CYCLE = 0.5% MAX<br>1.4 30<br>ID = 12 A<br>1.2 20<br>TJ = 125 [ o] C<br>1.0 10<br>TJ = 25  [o] C<br>0.8 0<br>-75 -50 -25 0 25 50 75 100 125 150 2 4 6 8 10<br>TJ, JUNCTION TEMPERATURE ( [o] C) VGS, GATE TO SOURCE VOLTAGE (V)<br>Figure 3.  Normalized  On  Resistance                                         Figure 4.   On-Resistance vs  Gate to<br>vs Junction Temperature Source Voltage<br>40 40<br>PULSE DURATION = 80  μ s VGS = 0 V<br>DUTY CYCLE = 0.5% MAX 10<br>30<br>VDS = 5 V 1<br>TJ = 150  [o] C<br>TJ = 150  [o] C<br>20<br>0.1 TJ = 25 [ o] C<br>TJ = 25  [o] C<br>10<br>0.01<br>TJ = -55  [o] C<br>TJ = -55  [o] C<br>0 0.001<br>1.5 2.0 2.5 3.0 3.5 4.0 0.0 0.2 0.4 0.6 0.8 1.0 1.2<br>VGS, GATE TO SOURCE VOLTAGE (V) VSD, BODY DIODE FORWARD VOLTAGE (V)<br>Figure 5.  Transfer Characteristics Figure 6.    Source to Drain  Diode<br>Forward Voltage vs Source Current<br>NORMALIZED<br>, DRAIN CURRENT (A)<br>ID<br>DRAIN TO SOURCE ON-RESISTANCE<br>)<br>Ω<br>m<br>(<br>DRAIN TO<br>NORMALIZED rDS(on),<br>SOURCE ON-RESISTANCE<br> DRAIN TO SOURCE ON-RESISTANCE<br>, DRAIN CURRENT (A)<br>ID<br>, REVERSE DRAIN CURRENT (A)<br>IS<br>**----- End of picture text -----**<br>


©2010 Fairchild Semiconductor Corporation FDMS7602S Rev.C2 

www.fairchildsemi.com 

## **Typical Characteristics (Q1 N-Channel)** TJ = 25°C unless otherwise noted 

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10 2000<br>ID = 12 A<br>1000 Ciss<br>8<br>VDD = 10 V<br>6 Coss<br>VDD = 15 V<br>100<br>4<br>VDD = 20 V<br>2<br>Crss<br>f = 1 MHz<br>VGS = 0 V<br>0 10<br>0 5 10 15 20 0.1 1 10 30<br>Qg, GATE CHARGE (nC) VDS, DRAIN TO SOURCE VOLTAGE (V)<br>Figure 7.  Gate Charge Characteristics Figure 8.     Capacitance   vs   Drain<br>to Source Voltage<br>60 100<br>VGS = 10 V R θ JC = 3.5  [o] C/W 100us<br>10<br>40<br>1 ms<br>VGS = 4.5 V<br>1 10 ms<br>THIS AREA IS<br>LIMITED BY rDS(on) 100 ms<br>20 Limited by Package SINGLE PULSE 1s<br>0.1 TJ = MAX RATED 10s<br>R θ JA = 125  [o] C/W DC<br>T A = 25  [o] C<br>0 0.01<br>25 50 75 100 125 150 0.01 0.1 1 10 100 200<br>TC, CASE TEMPERATURE (oC) VDS, DRAIN to SOURCE VOLTAGE (V)<br>Figure 9.  Maximum  Continuous   Drain   Figure 10.     Forward Bias Safe<br>Current vs Case Temperature  Operating Area<br>1000<br>SINGLE PULSE<br>R θ JA = 125  [o] C/W<br>100 TA = 25  [o] C<br>10<br>1<br>0.5<br>10-4 10-3 10-2 10-1 1 10 100 1000<br>t, PULSE WIDTH (s)<br>Figure 11.  Single Pulse Maximum Power Dissipation<br>CAPACITANCE (pF)<br>, GATE TO SOURCE VOLTAGE (V)<br>GS<br>V<br>DRAIN CURRENT (A)<br>I, D , DRAIN CURRENT (A)ID<br>, PEAK TRANSIENT POWER (W)<br>(PK)<br>P<br>**----- End of picture text -----**<br>


www.fairchildsemi.com 

©2010 Fairchild Semiconductor Corporation FDMS7602S Rev.C2 

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Typical Characteristics (Q1 N-Channel) TJ = 25°C unless otherwise noted<br>2<br>DUTY CYCLE-DESCENDING ORDER<br>1<br>D = 0.5<br>      0.2<br>      0.1<br>0.1       0.05<br>      0.02 PDM<br>      0.01<br>t1<br>0.01 SINGLE PULSE t2<br>R θ JA = 125  [o] C/W NOTES:DUTY FACTOR: D = t1/t2<br>( Note 1c ) PEAK T J  = P DM  x Z θJA  x R θJA  + T A<br>0.001<br>10-4 10-3 10-2 10-1 1 10 100 1000<br>t, RECTANGULAR PULSE DURATION (sec)<br>Z JA θ<br>IMPEDANCE,<br>NORMALIZED THERMAL<br>**----- End of picture text -----**<br>


**Figure 12.  Junction-to-Ambient Transient Thermal Response Curve** 

©2010 Fairchild Semiconductor Corporation FDMS7602S Rev.C2 

www.fairchildsemi.com 

## **Typical Characteristics (Q2 SyncFET)** 

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60 5<br>VGS =  10 V PULSE DURATION = 80DUTY CYCLE = 0.5% MAX  μ s<br>4<br>VGS =  4.5 V VGS = 3 V<br>40<br>VGS = 4 V 3<br>VGS = 3.5 V<br>VGS =  3.5 V 2 V GS  = 4 V<br>20<br>PULSE DURATION = 80  μ s 1<br>DUTY CYCLE = 0.5% MAX<br>VGS =  3 V VGS = 4.5 V VGS =  10 V<br>0 0<br>0.0 0.5 1.0 1.5 2.0 0 20 40 60<br>VDS, DRAIN TO SOURCE VOLTAGE (V) ID, DRAIN CURRENT (A)<br>Figure 13. On-Region Characteristics Figure 14. Normalized on-Resistance vs Drain<br>Current and Gate  Voltage<br>1.6 20<br>ID = 17 A PULSE DURATION = 80  μ s<br>VGS = 10 V DUTY CYCLE = 0.5% MAX<br>1.4<br>15<br>ID = 17 A<br>1.2<br>10<br>1.0 TJ = 125 [ o] C<br>5<br>0.8<br>TJ = 25  [o] C<br>0.6 0<br>-75 -50 -25 0 25 50 75 100 125 150 2 4 6 8 10<br>TJ, JUNCTION TEMPERATURE ( [o] C) VGS, GATE TO SOURCE VOLTAGE (V)<br>Figure 15. Normalized On-Resistance  Figure 16. On-Resistance vs Gate to<br>vs Junction Temperature Source Voltage<br>60<br>60<br>PULSE DURATION = 80 DUTY CYCLE = 0.5% MAX μ s VGS = 0 V<br>VDS = 5 V 10<br>40 TJ = 125  [o] C<br>TJ = 125  [o] C<br>1<br>20 TJ = 25  [o] C TJ = 25 [o] C<br>0.1<br>TJ = -55  [o] C T J  = -55  [o] C<br>0<br>1.5 2.0 2.5 3.0 3.5 0.01<br>0.0 0.2 0.4 0.6 0.8 1.0 1.2<br>VGS, GATE TO SOURCE VOLTAGE (V)<br>VSD, BODY DIODE FORWARD VOLTAGE (V)<br>NORMALIZED<br>, DRAIN CURRENT (A)<br>ID<br>DRAIN TO SOURCE ON-RESISTANCE<br>)<br>Ω<br>m<br>(<br>DRAIN TO<br>NORMALIZED rDS(on),<br>SOURCE ON-RESISTANCE<br> DRAIN TO SOURCE ON-RESISTANCE<br>, DRAIN CURRENT (A)<br>ID<br>, REVERSE DRAIN CURRENT (A)<br>IS<br>**----- End of picture text -----**<br>


**Figure 17. Transfer Characteristics** 

**Figure 18. Source to Drain Diode Forward Voltage vs Source Current** 

©2010 Fairchild Semiconductor Corporation FDMS7602S Rev.C2 

www.fairchildsemi.com 

## **Typical Characteristics  (Q2 SyncFET)** 

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10 3000<br>ID = 17 A<br>8 Ciss<br>VDD = 10 V 1000<br>6<br>C oss<br>VDD = 15 V<br>4<br>VDD = 20 V<br>2<br>100 f = 1 MHz<br>0 60 VGS = 0 V Crss<br>0 10 20 30 40 0.1 1 10 30<br>Qg, GATE CHARGE (nC) VDS, DRAIN TO SOURCE VOLTAGE (V)<br>Figure 19. Gate Charge Characteristics Figure 20. Capacitance vs Drain<br>to Source Voltage<br>100 100<br>VGS = 10 V R θ JC = 2  [o] C/W<br>80 100 us<br>10<br>1 ms<br>60<br>VGS = 4.5 V 1 THIS AREA IS  10 ms<br>40 LIMITED BY rDS(on) 100 ms<br>1 s<br>SINGLE PULSE<br>20 0.1 TJ = MAX RATED 10 s<br>Limited by package R θ JA = 120  [o] C/W DC<br>T A = 25  [o] C<br>0 0.01<br>25 50 75 100 125 150 0.01 0.1 1 10 100 200<br>TC, CASE TEMPERATURE (oC) VDS, DRAIN to SOURCE VOLTAGE (V)<br>Figure 21.   Maximum  Continuous  Drain<br>Current vs Case Temperature  Figure 22. Forward Bias Safe Operating Area<br>1000<br>SINGLE PULSE<br>R θ JA = 120  [o] C/W<br>TA = 25  [o] C<br>100<br>10<br>110-4 10-3 10-2 10-1 1 10 102 103<br>t, PULSE WIDTH (sec)<br>CAPACITANCE (pF)<br>, GATE TO SOURCE VOLTAGE (V)<br>GS<br>V<br>DRAIN CURRENT (A)<br>I, D , DRAIN CURRENT (A)ID<br>PEAK TRANSIENT POWER (W)<br>P)(PK,<br>**----- End of picture text -----**<br>


**Figure 23. Single Pulse Maximum Power Dissipation** 

©2010 Fairchild Semiconductor Corporation FDMS7602S Rev.C2 

www.fairchildsemi.com 

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Typical Characteristics  (Q2 SyncFET)<br>2<br>DUTY CYCLE-DESCENDING ORDER<br>1<br>D = 0.5<br>      0.2<br>      0.1<br>0.1       0.05<br>      0.02      0.01 PDM<br>t1<br>0.01 SINGLE PULSE t2<br>R θ JA = 120  [o] C/W NOTES:DUTY FACTOR: D = t1/t2<br>( Note 1d ) PEAK T J  = P DM  x Z θJA  x R θJA  + T A<br>0.001<br>10-4 10-3 10-2 10-1 1 10 102 103<br>t, RECTANGULAR PULSE DURATION (sec)<br>Figure 24. Junction-to-Ambient Transient Thermal Response Curve<br>Z JA θ<br>IMPEDANCE,<br>NORMALIZED THERMAL<br>**----- End of picture text -----**<br>


www.fairchildsemi.com 

©2010 Fairchild Semiconductor Corporation FDMS7602S Rev.C2 

**Typical Characteristics** (continued) 

## **SyncFET[TM] Schottky body diode Characteristics** 

Fairchild’s SyncFET[TM] process embeds a Schottky diode in parallel with PowerTrench **[®]** MOSFET. This diode exhibits similar characteristics to a discrete external Schottky diode in parallel with a MOSFET. Figure 25 shows the reverse recovery characteristic of the FDMS7602S. 

Schottky barrier diodes exhibit significant leakage at high temperature and high reverse voltage. This will increase the power in the device. 

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20<br>10000<br>TJ = 125  [o] C<br>15<br>1000<br>10 TJ = 100  [o] C<br>di/dt = 300 A/ μ s 100<br>5<br>10<br>0 TJ = 25  [o] C<br>-5 1<br>0 50 100 150 200 0 5 10 15 20 25 30<br>TIME (ns) VDS, REVERSE VOLTAGE (V)<br>CURRENT (A)<br>, REVERSE LEAKAGE CURRENT (uA)<br>IDSS<br>**----- End of picture text -----**<br>


**Figure 25. FDMS7602S SyncFET[TM ] Body Diode Reverse Recovery Characteristic** 

**Figure 26. SyncFET[TM] Body Diode Reverse Leakage  vs. Drain-Source Voltage** 

©2010 Fairchild Semiconductor Corporation FDMS7602S Rev.C2 

www.fairchildsemi.com 

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0.05 C 5.00 A B<br>l 2X a l 1+<br>4.46<br>1.27 0.65<br>8 7  6  5<br>{ ir ct<br>0.63(5X)<br>L 6.00 — U 0.25 c o ed ee l 0.40<br>2.67<br>6.30<br>0.54<br>PIN#1 IDENT 0.05 C 0.66<br>/- MA. So ~ ——<br>2X<br>0.92<br>0.10 C<br>0.08 C 1 2  3  4<br>0.65 (5X)<br>SIDE VIEW C 4.00<br>SEATING<br>RECOMMENDED LAND PATTERN<br>PLANE<br>(OPTION 1 - FUSED LEADS 5,6,7)<br>(0.34)4X<br>1 2  3  4 4.46<br>PIN#1 IDENT 1.27 0.65(8X)<br>8 7  6  5<br>tf _ t r 0.43+0.05(5X) 7 4<br>0.63(8X)<br>(0.66) 0.40<br>[ Rast o orto .0s [ ] ( to Ea<br>2.67<br>7 c ona n<br>6.30<br>0.54<br>0.66<br>py “|<br>0.45<br>0.92<br>8 7  6  5<br>1.27<br>0.10 C A B<br>0.05 C<br>1 2  3  4<br>fa! BOTTOM VIEW Ho 4.00 o<br>RECOMMENDED LAND PATTERN<br>NOTES: (OPTION 2 - ISOLATED LEADS)<br>**----- End of picture text -----**<br>


- A.  PACKAGE DOES NOT FULLY CONFORM TO JEDEC STANDARD. 

- B.  DIMENSIONS ARE IN MILLIMETERS. 

- C.  DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 2009. 

- D.  LAND PATTERN RECOMMENDATION IS EXISTING INDUSTRY LAND PATTERN. 

- E.  DRAWING FILENAME: MKT-MLP08Prev2. 

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