FDMS3606AS

## **Is Now Part of** 

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## **FDMS3606AS** 

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## **PowerTrench[®] Power Stage** 

## **30 V Asymmetric Dual N-Channel MOSFET** 

## **Features** 

Q1: N-Channel 

Max rDS(on) = 8 mΩ at VGS = 10 V, ID = 13 A Max rDS(on) = 11 mΩ at VGS = 4.5 V, ID = 11 A 

Q2: N-Channel 

Max rDS(on) = 1.9 mΩ at VGS = 10 V, ID = 27 A Max rDS(on) = 2.8 mΩ at VGS = 4.5 V, ID = 23 A 

Low inductance packaging shortens rise/fall times, resulting in lower switching losses 

MOSFET integration enables optimum layout for lower circuit inductance and reduced switch node ringing 

RoHS Compliant 

## **General Description** 

This device includes two specialized N-Channel MOSFETs in a dual PQFN package. The switch node has been internally connected to enable easy placement and routing of synchronous buck converters. The control MOSFET (Q1) and synchronous SyncFET (Q2) have been designed to provide optimal power efficiency. 

## **Applications** 

Computing 

Communications 

General Purpose Point of Load 

Notebook VCORE 

Sever 

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G1 D1 D1 D1D1 S2 5 Q2 4 D1<br>PHASE S2 6 PHASE 3 D1<br>(S1/D2)<br>S2 7 2 D1<br>G2S2S2 S2 G2 8 Q1 1 G1<br>Top Power 56 Bottom<br>MOSFET Maximum Ratings TA = 25 °C unless otherwise noted<br>**----- End of picture text -----**<br>


**Symbol Parameter Q1 Q2 Units** VDS Drain to Source Voltage 30 30 V VGS Gate to Source Voltage                                                                                  (Note 3) ±20 ±20 V Drain Current      -Continuous  (Package limited)                                   TC = 25 °C 30 40 ID -Continuous                                                                    T                             -Continuous  (Silicon limited)                                       TCA = 25 °C= 25 °C 1360[1a] 27148[1b] A -Pulsed 40 100 EAS ~~ze~~ Single Pulse Avalanche Energy 40[4] 162[5] mJ PD Power DissiPower Dissippation for Sination for Singgle Ole Opperation                                                  Teration                                                  TA A = 25 °C= 25 °C 2.21.0[1a][1c] 2.51.0[1b][1d] W ~~ee~~ TJ, TSTG Operating and Storage Junction Temperature Range -55 to +150 °C **Thermal Characteristics** RθJA Thermal Resistance, Junction to Ambient 57[1a] 50[1b] RθJA Thermal Resistance, Junction to Ambient 125[1c] 120[1d] °C/W ~~ee~~ RθJC Thermal Resistance, Junction to Case 3.5 2 **Package Marking and Ordering Information Device Marking Device Package Reel Size Tape Width Quantity** 22CA FDMS3606AS Power 56 13 ” 12 mm 3000 units N9CC ~~a~~ ©2011 Fairchild Semiconductor Corporation **1** www.fairchildsemi.com FDMS3606AS Rev.C4 

## **Electrical Characteristics** TJ = 25 °C unless otherwise noted 

|**Electrica**|**l Characteristics**TJ= 25 °C u|nless otherwise noted||||||||
|---|---|---|---|---|---|---|---|---|---|
|**Symbol**|**Parameter**|**Test Conditions**|**Type**|**Min**||**Typ**|**Max**||**Units**|
|**Off Characteristics**||||||||||
|BVDSS|Drain to Source Breakdown Voltage|ID= 250μA, VGS= 0 V<br>ID= 1 mA, VGS= 0 V|Q1<br>Q2|30<br>30|||||V|
|ΔBVDSS<br>ΔTJ|Breakdown Voltage Temperature<br>Coefficient|ID= 250μA, referenced to 25 °C<br>ID= 10 mA, referenced to 25 °C|Q1<br>Q2|||15<br>20|||mV/°C|
|IDSS|Zero Gate Voltage Drain Current|VDS= 24 V,   VGS= 0 V|Q1<br>Q2||||1<br>500||μA<br>μA|
|IGSS|Gate to Source Leakage Current,<br>Forward|VGS= 20 V, VDS= 0 V|Q1<br>Q2||||100<br>100||nA<br>nA|
|**On Characteristics**||||||||||
|VGS(th)|Gate to Source Threshold Voltage|VGS= VDS,  ID= 250μA<br>VGS= VDS,  ID= 1 mA|Q1<br>Q2|1.1<br>1.1||2<br>1.8|2.7<br>3||V|
|ΔVGS(th)<br>ΔTJ|Gate to Source Threshold Voltage<br>Temperature Coefficient|ID= 250μA, referenced to 25 °C<br>ID= 10 mA, referenced to 25 °C|Q1<br>Q2|||-6<br>-5|||mV/°C|
|rDS(on)|Drain to Source On Resistance|VGS= 10 V,  ID= 13 A<br>VGS= 4.5 V,  ID= 11 A<br>VGS= 10 V,  ID= 13 A , TJ= 125 °C|Q1|||5.8<br>8.5<br>7.8|8<br>11<br>10.8||mΩ|
|||VGS= 10 V,  ID= 27 A<br>VGS= 4.5 V,  ID= 23 A<br>VGS= 10 V,  ID= 27 A , TJ= 125 °C|Q2|||1.4<br>2<br>1.9|1.9<br>2.8<br>2.8|||
|gFS|Forward Transconductance|VDS= 5 V,  ID= 13 A<br>VDS= 5 V,  ID= 27 A|Q1<br>Q2|||61<br>154|||S|
|**Dynamic Characteristics**||||||||||
|Ciss|Input Capacitance|Q1:<br>VDS= 15 V, VGS= 0 V, f = 1 MHZ<br>Q2:<br>VDS= 15 V, VGS= 0 V, f = 1 MHZ|Q1<br>Q2|||1273<br>4129|1695<br>5490||pF|
|Coss|Output Capacitance||Q1<br>Q2|||461<br>1527|615<br>2030||pF|
|Crss|Reverse Transfer Capacitance||Q1<br>Q2|||50<br>98|75<br>150||pF|
|Rg|Gate Resistance||Q1<br>Q2|0.2<br>0.2||0.6<br>0.8|2<br>3||Ω|
|**Switching Characteristics**||||||||||
|td(on)|Turn-On Delay Time|Q1:<br>VDD= 15 V, ID= 13 A,  RGEN= 6Ω<br>Q2:<br>VDD= 15 V, ID= 27 A,  RGEN= 6Ω|Q1<br>Q2|||8.2<br>15||16<br>27|ns|
|tr|Rise Time||Q1<br>Q2|||2.5<br>5.5||10<br>11|ns|
|td(off)|Turn-Off Delay Time||Q1<br>Q2|||20<br>36||32<br>58|ns|
|tf|Fall Time||Q1<br>Q2|||2.2<br>3.4||10<br>10|ns|
|Qg|Total Gate Charge|VGS= 0  V to 10 V|Q1<br>Q2|||21<br>59||29<br>83|nC|
|Qg|Total Gate Charge|VGS= 0  V to 4.5 V|Q1<br>Q2|||10<br>27||14<br>38|nC|
|Qgs|Gate to Source Gate Charge||Q1<br>Q2|||3.9<br>12|||nC|
|Qgd|Gate to Drain “Miller” Charge||Q1<br>Q2|||3.1<br>5.7|||nC|



©2011 Fairchild Semiconductor Corporation FDMS3606AS Rev.C4 

www.fairchildsemi.com 

**2** 

|**Electrical Characteristics**TJ= 25 °C unless otherwise noted<br>**Drain-Source Diode Characteristics**<br>**Symbol**<br>**Parameter**<br>**Test Conditions**<br>**Type**<br>**Min**<br>**Typ**<br>**Max**<br>**Units**<br>VSD<br>Source to Drain Diode  Forward Voltage VGS= 0 V, IS= 13 A           (Note 2)<br>VGS = 0 V, IS = 27 A(Note 2)<br>Q1<br>Q2<br>0.8<br>0.8<br>1.2<br>1.2<br>V<br>trr<br>Reverse Recovery Time<br>Q1<br>IF= 13 A, di/dt = 100 A/μs<br>Q2<br>IF= 27 A, di/dt = 300 A/μs<br>Q1<br>Q2<br>25<br>39<br>40<br>62<br>ns<br>Qrr<br>Reverse Recovery Charge<br>Q1<br>Q2<br>9<br>57<br>18<br>91<br>nC<br>**Notes:**<br>**1:** RθJAis determined with the device mounted on a 1 in2pad 2 oz copper pad on a 1.5 x 1.5 in. board of FR-4 material. RθJCis guaranteed by design while RθCAis determined<br>by the user's board design.<br>a. 57 °C/W when mounted on<br>a 1 in2pad of  2 oz  copper<br>b. 50 °C/W when mounted on<br>a 1 in2pad of  2 oz  copper<br>~~a B~~<br>po<br>ooo00**0**<br>oo000<br>0000<br>00000|**Electrical Characteristics**TJ= 25 °C unless otherwise noted<br>**Drain-Source Diode Characteristics**<br>**Symbol**<br>**Parameter**<br>**Test Conditions**<br>**Type**<br>**Min**<br>**Typ**<br>**Max**<br>**Units**<br>VSD<br>Source to Drain Diode  Forward Voltage VGS= 0 V, IS= 13 A           (Note 2)<br>VGS = 0 V, IS = 27 A(Note 2)<br>Q1<br>Q2<br>0.8<br>0.8<br>1.2<br>1.2<br>V<br>trr<br>Reverse Recovery Time<br>Q1<br>IF= 13 A, di/dt = 100 A/μs<br>Q2<br>IF= 27 A, di/dt = 300 A/μs<br>Q1<br>Q2<br>25<br>39<br>40<br>62<br>ns<br>Qrr<br>Reverse Recovery Charge<br>Q1<br>Q2<br>9<br>57<br>18<br>91<br>nC<br>**Notes:**<br>**1:** RθJAis determined with the device mounted on a 1 in2pad 2 oz copper pad on a 1.5 x 1.5 in. board of FR-4 material. RθJCis guaranteed by design while RθCAis determined<br>by the user's board design.<br>a. 57 °C/W when mounted on<br>a 1 in2pad of  2 oz  copper<br>b. 50 °C/W when mounted on<br>a 1 in2pad of  2 oz  copper<br>~~a B~~<br>po<br>ooo00**0**<br>oo000<br>0000<br>00000|**Electrical Characteristics**TJ= 25 °C unless otherwise noted<br>**Drain-Source Diode Characteristics**<br>**Symbol**<br>**Parameter**<br>**Test Conditions**<br>**Type**<br>**Min**<br>**Typ**<br>**Max**<br>**Units**<br>VSD<br>Source to Drain Diode  Forward Voltage VGS= 0 V, IS= 13 A           (Note 2)<br>VGS = 0 V, IS = 27 A(Note 2)<br>Q1<br>Q2<br>0.8<br>0.8<br>1.2<br>1.2<br>V<br>trr<br>Reverse Recovery Time<br>Q1<br>IF= 13 A, di/dt = 100 A/μs<br>Q2<br>IF= 27 A, di/dt = 300 A/μs<br>Q1<br>Q2<br>25<br>39<br>40<br>62<br>ns<br>Qrr<br>Reverse Recovery Charge<br>Q1<br>Q2<br>9<br>57<br>18<br>91<br>nC<br>**Notes:**<br>**1:** RθJAis determined with the device mounted on a 1 in2pad 2 oz copper pad on a 1.5 x 1.5 in. board of FR-4 material. RθJCis guaranteed by design while RθCAis determined<br>by the user's board design.<br>a. 57 °C/W when mounted on<br>a 1 in2pad of  2 oz  copper<br>b. 50 °C/W when mounted on<br>a 1 in2pad of  2 oz  copper<br>~~a B~~<br>po<br>ooo00**0**<br>oo000<br>0000<br>00000|
|---|---|---|
|c. 125 °C/W when mounted on  a<br>d. 120 °C/W when mounted on  a|||
|minimum pad of 2 oz copper<br>minimum pad of 2 oz copper|||
|ooo00<br>00000|||
|**2:** Pulse Test: Pulse Width < 300μs, Duty cycle < 2.0%.|||
|**3:** As an N-ch device, the negative Vgs rating is for low duty cycle pulse ocurrence only. No continuous rating is implied.|||
|**4:** EASof 40 mJ is based on starting TJ= 25oC; N-ch: L = 1 mH, IAS= 9 A, VDD= 27 V, VGS= 10 V. 100% test at L= 0.3 mH, IAS= 14 A.|||
|**5:** EASof 162 mJ is based on starting TJ= 25oC; N-ch: L = 1 mH, IAS= 18 A, VDD= 27 V, VGS= 10 V. 100% test at L= 0.3 mH, IAS= 27 A.|||



©2011 Fairchild Semiconductor Corporation FDMS3606AS Rev.C4 

www.fairchildsemi.com 

**3** 

## **Typical Characteristics (Q1 N-Channel)** TJ = 25 °C unless otherwise noted 

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40 4<br>VGS =  10 V VGS = 3.5 V PULSE DURATION = 80  μ s<br>DUTY CYCLE = 0.5% MAX<br>VGS = 6 V<br>30 3<br>VGS =  4.5 V<br>VGS =  4 V VGS =  4 V<br>20 2<br>VGS = 4.5 V<br>10 1<br>VGS = 3.5 V PULSE DURATION = 80  μ s VGS = 6 V VGS = 10 V<br>DUTY CYCLE = 0.5% MAX<br>0 0<br>0.0 0.2 0.4 0.6 0.8 1.0 0 10 20 30 40<br>VDS, DRAIN TO SOURCE VOLTAGE (V) ID, DRAIN CURRENT (A)<br>Figure 1.  On Region Characteristics Figure 2.      Normalized On-Resistance<br>vs Drain Current and Gate Voltage<br>1.6 20<br>ID = 13 A PULSE DURATION = 80  μ s<br>VGS = 10 V DUTY CYCLE = 0.5% MAX<br>1.4 16<br>ID = 13 A<br>1.2 12<br>TJ = 125 [ o] C<br>1.0 8<br>0.8 4<br>TJ = 25  [o] C<br>0.6 0<br>-75 -50 -25 0 25 50 75 100 125 150 2 4 6 8 10<br>TJ, JUNCTION TEMPERATURE ( [o] C) VGS, GATE TO SOURCE VOLTAGE (V)<br>Figure 3.  Normalized  On  Resistance                                         Figure 4.   On-Resistance vs  Gate to<br>vs Junction Temperature Source Voltage<br>40 40<br>PULSE DURATION = 80  μ s VGS = 0 V<br>DUTY CYCLE = 0.5% MAX 10<br>30<br>VDS = 5 V 1<br>TJ = 150  [o] C TJ = 150  [o] C<br>20 T J  = 25 [ o] C<br>0.1<br>TJ = 25  [o] C<br>10<br>0.01 TJ = -55  [o] C<br>TJ = -55  [o] C<br>0 0.001<br>1.5 2.0 2.5 3.0 3.5 4.0 0.0 0.2 0.4 0.6 0.8 1.0 1.2<br>VGS, GATE TO SOURCE VOLTAGE (V) VSD, BODY DIODE FORWARD VOLTAGE (V)<br>Figure 5.  Transfer Characteristics Figure 6.    Source to Drain  Diode<br>Forward Voltage vs Source Current<br>NORMALIZED<br>, DRAIN CURRENT (A)<br>ID<br>DRAIN TO SOURCE ON-RESISTANCE<br>)<br>Ω<br>m<br>(<br>DRAIN TO<br>NORMALIZED rDS(on),<br>SOURCE ON-RESISTANCE<br> DRAIN TO SOURCE ON-RESISTANCE<br>, DRAIN CURRENT (A)<br>ID<br>, REVERSE DRAIN CURRENT (A)<br>IS<br>**----- End of picture text -----**<br>


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www.fairchildsemi.com 

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Typical Characteristics (Q1 N-Channel)  TJ = 25 °C unless otherwise noted<br>10 2000<br>ID = 13 A VDD = 10 V 1000 Ciss<br>8<br>VDD = 15 V<br>6 Coss<br>VDD = 20 V<br>100<br>4<br>2 Crss<br>f = 1 MHz<br>VGS = 0 V<br>0 10<br>0 5 10 15 20 25 0.1 1 10 30<br>Qg, GATE CHARGE (nC) VDS, DRAIN TO SOURCE VOLTAGE (V)<br>Figure 7.  Gate Charge Characteristics Figure 8.      Capacitance vs Drain<br>to Source Voltage<br>20 100<br>R θ JC = 3.5  [o] C/W<br>80<br>10<br>VGS = 10 V<br>T J  = 25 [ o] C 60<br>VGS = 4.5 V<br>TJ = 100 [ o] C 40<br>20<br>TJ = 125 [o] C Limited by Package<br>1 0<br>0.01 0.1 1 10 100 25 50 75 100 125 150<br>tAV, TIME IN AVALANCHE (ms) TC, CASE TEMPERATURE (oC)<br>Figure 9. Unclamped Inductive                                  Figure 10.  Maximum Continuous Drain<br>Switching Capability Current  vs Case Temperature<br>100 1000<br>SINGLE PULSE<br>100us<br>10 100 R θ JA = 125  [o] C/W<br>TA = 25  [o] C<br>1 ms<br>1 10 ms 10<br>THIS AREA IS<br>LIMITED BY rDS(on) 100 ms<br>SINGLE PULSE 1s<br>0.1 TJ = MAX RATED 10s 1<br>R θ JA = 125  [o] C/W<br>DC<br>T A = 25  [o] C<br>0.01 0.1<br>0.01 0.1 1 10 100 200 10-4 10-3 10-2 10-1 1 10 100 1000<br>VDS, DRAIN to SOURCE VOLTAGE (V) t, PULSE WIDTH (sec)<br>Figure 11.   Forward Bias Safe                                 Figure 12.  Single  Pulse Maximum<br>Operating Area Power  Dissipation<br>CAPACITANCE (pF)<br>FDMS3606AS PowerTrench<br>, GATE TO SOURCE VOLTAGE (V)<br>®<br>GS<br>V<br> Power Stage<br>DRAIN CURRENT (A)<br>,<br>ID<br>, AVALANCHE CURRENT (A)<br>IAS<br>, DRAIN CURRENT (A)<br>ID<br>PEAK TRANSIENT POWER (W)<br>P)(PK,<br>**----- End of picture text -----**<br>


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www.fairchildsemi.com 

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Typical Characteristics (Q1 N-Channel)  TJ = 25 °C unless otherwise noted<br>2<br>DUTY CYCLE-DESCENDING ORDER<br>1<br>D = 0.5<br>      0.2<br>      0.1<br>      0.05<br>0.1<br>      0.02 PDM<br>      0.01<br>t1<br>0.01 SINGLE PULSE t 2<br>NOTES:<br>R θ JA = 125  [o] C/W DUTY FACTOR: D = t1/t2<br>( Note 1c ) PEAK TJ = PDM x Z θJA  x R θJA  + TA<br>0.001<br>10-4 10-3 10-2 10-1 1 10 100 1000<br>t, RECTANGULAR PULSE DURATION (sec)<br>Z JA θ<br>IMPEDANCE,<br>NORMALIZED THERMAL<br>**----- End of picture text -----**<br>


**Figure 13.  Junction-to-Ambient Transient Thermal Response Curve** 

©2011 Fairchild Semiconductor Corporation FDMS3606AS Rev.C4 

www.fairchildsemi.com 

**6** 

## **Typical Characteristics (Q2 N-Channel)** TJ =  25[o] C unlenss otherwise noted 

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100 8<br>VGS = 10 V VGS = 3 V PULSE DURATION = 80DUTY CYCLE = 0.5% MAX  μ s<br>80<br>6<br>VGS =  4.5 V<br>60 VGS = 3.5 V<br>VGS =  4 V<br>4<br>VGS = 3.5 V<br>40<br>2 V GS  = 4 V VGS = 4.5 V<br>20<br>VGS =  3 V PULSE DURATION = 80 DUTY CYCLE = 0.5% MAX μ s VGS =  10 V<br>0 0<br>0.0 0.2 0.4 0.6 0.8 1.0 0 20 40 60 80 100<br>VDS, DRAIN TO SOURCE VOLTAGE (V) ID, DRAIN CURRENT (A)<br>Figure 14. On-Region Characteristics Figure 15. Normalized on-Resistance vs Drain<br>Current and Gate  Voltage<br>1.6 8<br>ID = 27 A PULSE DURATION = 80  μ s<br>VGS = 10 V DUTY CYCLE = 0.5% MAX<br>1.4 6<br>ID = 27 A<br>1.2 4<br>TJ = 125 [ o] C<br>1.0 2<br>TJ = 25  [o] C<br>0.8 0<br>-75 -50 -25 0 25 50 75 100 125 150 2 4 6 8 10<br>TJ, JUNCTION TEMPERATURE ( [o] C) VGS, GATE TO SOURCE VOLTAGE (V)<br>Figure 16. Normalized On-Resistance  Figure 17. On-Resistance vs Gate to<br>vs Junction Temperature Source Voltage<br>100 100<br>PULSE DURATION = 80  μ s VGS = 0 V<br>DUTY CYCLE = 0.5% MAX<br>80 VDS = 5 V 10 TJ = 125  [o] C<br>TJ = 125  [o] C<br>60 1<br>TJ = 25 [ o] C<br>TJ = 25  [o] C<br>40 0.1<br>20 0.01 TJ = -55  [o] C<br>TJ = -55  [o] C<br>0 0.001<br>1.5 2.0 2.5 3.0 3.5 0.0 0.2 0.4 0.6 0.8 1.0 1.2<br>VGS, GATE TO SOURCE VOLTAGE (V) VSD, BODY DIODE FORWARD VOLTAGE (V)<br>NORMALIZED<br>, DRAIN CURRENT (A)<br>ID<br>DRAIN TO SOURCE ON-RESISTANCE<br>)<br>Ω<br>m<br>(<br>DRAIN TO<br>NORMALIZED rDS(on),<br>SOURCE ON-RESISTANCE<br> DRAIN TO SOURCE ON-RESISTANCE<br>, DRAIN CURRENT (A)<br>ID<br>, REVERSE DRAIN CURRENT (A)<br>IS<br>**----- End of picture text -----**<br>


**Figure 18. Transfer Characteristics** 

**Figure 19. Source to Drain Diode Forward Voltage vs Source Current** 

©2011 Fairchild Semiconductor Corporation FDMS3606AS Rev.C4 

www.fairchildsemi.com 

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**Typical Characteristics (Q2 N-Channel)** TJ = 25[o] C unless otherwise noted 

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10 10000<br>ID = 27A<br>8 Ciss<br>VDD = 10 V 1000 Coss<br>6<br>VDD = 15 V<br>4<br>VDD = 20 V 100<br>Crss<br>2<br>f = 1 MHz<br>VGS = 0 V<br>0 10<br>0 10 20 30 40 50 60 0.1 1 10 30<br>Qg, GATE CHARGE (nC) VDS, DRAIN TO SOURCE VOLTAGE (V)<br>Figure 20. Gate Charge Characteristics Figure 21. Capacitance vs Drain<br>to Source Voltage<br>50 200<br>R θ JC = 2  [o] C/W<br>150<br>TJ = 25 [ o] C VGS = 10 V<br>10<br>100<br>T J  = 100 [ o] C VGS = 4.5 V<br>50<br>TJ = 125  [o] C Limited by Package<br>1 0<br>0.01 0.1 1 10 100 1000 25 50 75 100 125 150<br>tAV, TIME IN AVALANCHE (ms) TC, CASE TEMPERATURE (oC)<br>Figure 22. Unclamped Inductive                         Figure 23. Maximun Continuous Drain<br>Switching Capability Current vs Case Temperature<br>200 1000<br>100<br>SINGLE PULSE<br>1 ms 100 R θ JA = 120  [o] C/W<br>10 TA = 25  [o] C<br>10 ms<br>THIS AREA IS  10<br>1 LIMITED BY rDS(on) 100 ms<br>1s<br>SINGLE PULSE<br>0.1 TJ = MAX RATED 10s 1<br>R θ JA = 120  [o] C/W DC<br>T A = 25  [o] C<br>0.01 0.1<br>0.01 0.1 1 10 100200 10-3 10-2 10-1 1 10 100 1000<br>VDS, DRAIN to SOURCE VOLTAGE (V) t, PULSE WIDTH (sec)<br>Figure 24. Forward Bias Safe                                   Figure 25. Single  Pulse Maximum<br>Operating Area Power Dissipation<br>CAPACITANCE (pF)<br>, GATE TO SOURCE VOLTAGE (V)<br>GS<br>V<br>DRAIN CURRENT (A)<br>,<br>ID<br>, AVALANCHE CURRENT (A)<br>IAS<br>, DRAIN CURRENT (A)<br>ID<br>PEAK TRANSIENT POWER (W)<br>P)(PK,<br>**----- End of picture text -----**<br>


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Typical Characteristics (Q2 N-Channel) TJ = 25  [o] C unless otherwise noted<br>2<br>DUTY CYCLE-DESCENDING ORDER<br>1<br>D = 0.5<br>      0.2<br>      0.1<br>0.1 0.05 P DM<br>      0.02<br>0.01<br>t 1<br>t2<br>0.01 SINGLE PULSE NOTES:<br>(Note 1d) R θ JA = 120  [o] C/W DUTY FACTOR: D = tPEAK TJ = PDM x Z θJA 1 x R/t2 θJA  + TA<br>0.00110-3 10-2 10-1 1 10 100 1000<br>t, RECTANGULAR PULSE DURATION (sec)<br>Z JA θ<br>IMPEDANCE,<br>NORMALIZED THERMAL<br>**----- End of picture text -----**<br>


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Figure 26.  Junction-to-Ambient Transient Thermal Response Curve<br>**----- End of picture text -----**<br>


©2011 Fairchild Semiconductor Corporation FDMS3606AS Rev.C4 

www.fairchildsemi.com 

**9** 

## **Typical Characteristics** (continued) 

## **SyncFET Schottky body diode Characteristics** 

Fairchild’s SyncFET process embeds a Schottky diode in parallel with PowerTrench MOSFET. This diode exhibits similar characteristics to a discrete external Schottky diode in parallel with a MOSFET. Figure 27 shows the reverse recovery characteristic of the FDMS3606AS. 

Schottky barrier diodes exhibit significant leakage at high temperature and high reverse voltage. This will increase the power in the device. 

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30 10-2<br>25 TJ = 125  [o] C<br>10-3<br>20 TJ = 100  [o] C<br>didt = 300 A/ μ s<br>15<br>10-4<br>10<br>5 -5<br>10 TJ = 25  [o] C<br>0<br>-5 10-6<br>0 50 100 150 200 250 300 0 5 10 15 20 25 30<br>TIME (ns) VDS, REVERSE VOLTAGE (V)<br>CURRENT (A)<br>, REVERSE LEAKAGE CURRENT (A)<br>IDSS<br>**----- End of picture text -----**<br>


**Figure 27. FDMS3606AS SyncFET body diode reverse recovery characteristic** 

**Figure 28. SyncFET body diode reverse leakage  versus drain-source voltage** 

©2011 Fairchild Semiconductor Corporation FDMS3606AS Rev.C4 

www.fairchildsemi.com 

**10** 

## **Application Information** 

## **1. Switch Node Ringing Suppression** 

Fairchild’s Power Stage products incorporate a proprietary design* that minimizes the peak overshoot, ringing voltage on the switch node (PHASE) without the need of any external snubbing components in a buck converter. As shown in the figure 29, the Power Stage solution rings significantly less than competitor solutions under the same set of test conditions. 

> 1||I }ty | lI | | i[ !| Chl Sov M20.0neS0G54 IT 8.0nehx M20.Onr 5.005% IT B.Opetat AChi + SOY AChI5.0" **Power Stage Device                                                          Competitors solution** 

*Patent Pending 

©2011 Fairchild Semiconductor Corporation FDMS3606AS Rev.C4 

www.fairchildsemi.com 

**11** 

## **2. Recommended PCB Layout Guidelines** 

As a PCB designer, it is necessary to address critical issues in layout to minimize losses and optimize the performance of the power train. Power Stage is a high power density solution and all high current flow paths, such as VIN (D1), PHASE (S1/D2) and GND (S2), should be short and wide for better and stable current flow, heat radiation and system performance. A recommended layout procedure is discussed below to maximize the electrical and thermal performance of the part. 

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©2011 Fairchild Semiconductor Corporation FDMS3606AS Rev.C4 

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www.fairchildsemi.com 

## **Following is a guideline, not a requirement which the PCB designer should consider:** 

1.  Input ceramic bypass capacitors C1 and C2 must be placed close to the D1 and S2 pins of Power Stage to help reduce parasitic inductance and high frequency conduction loss induced by switching operation. C1 and C2 show the bypass capacitors placed close to the part between D1 and S2.  Input capacitors should be connected in parallel close to the part. Multiple input caps can be connected depending upon the application. 

2. The PHASE copper trace serves two purposes; In addition to being the current path from the Power Stage package to the output inductor (L), it also serves as heat sink for the lower FET in the Power Stage package. The trace should be short and wide enough to present a low resistance path for the high current flow between the Power Stage and the inductor. This is done to minimize conduction losses and limit temperature rise. Please note that the PHASE node is a high voltage and high frequency switching node with high noise potential. Care should be taken to minimize coupling to adjacent traces. The reference layout in figure 31 shows a good balance between the thermal and electrical performance of Power Stage. 

3. Output inductor location should be as close as possible to the Power Stage device for lower power loss due to copper trace resistance. A shorter and wider PHASE trace to the inductor reduces the conduction loss. Preferably the Power Stage should be directly in line (as shown in figure 31) with the inductor for space savings and compactness. 

4. The PowerTrench[®] Technology MOSFETs used in the Power Stage are effective at minimizing phase node ringing. It allows the part to operate well within the breakdown voltage limits. This eliminates the need to have an external snubber circuit in most cases. If the designer chooses to use an RC snubber, it should be placed close to the part between the PHASE pad and S2 pins to dampen the high-frequency ringing. 

5. The driver IC should be placed close to the Power Stage part with the shortest possible paths for the High Side gate and Low Side gates through a wide trace connection. This eliminates the effect of parasitic inductance and resistance between the driver and the MOSFET and turns the devices on and off as efficiently as possible. At higher-frequency operation this impedance can limit the gate current trying to charge the MOSFET input capacitance. This will result in slower rise and fall times and additional switching losses. Power Stage has both the gate pins on the same side of the package which allows for back mounting of the driver IC to the board. This provides a very compact path for the drive signals and improves efficiency of the part. 

6. S2 pins should be connected to the GND plane with multiple vias for a low impedance grounding. Poor grounding can create a noise transient offset voltage level between S2 and driver ground. This could lead to faulty operation of the gate driver and MOSFET. 

7. Use multiple vias on each copper area to interconnect top, inner and bottom layers to help smooth current flow and heat conduction. Vias should be relatively large, around 8 mils to 10 mils, and of reasonable inductance. Critical high frequency components such as ceramic bypass caps should be located close to the part and on the same side of the PCB. If not feasible, they should be connected from the backside via a network of low inductance vias. 

©2011 Fairchild Semiconductor Corporation FDMS3606AS Rev.C4 

www.fairchildsemi.com 

**13** 

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5.10<br>0.10 C 4.90 A<br>(2X) PKG B<br>CL<br>8 5<br>PKG CL 6.255.90<br>1 4 0.10 C<br>PIN # 1<br>INDICATOR (2X)<br>TOP VIEW<br>**----- End of picture text -----**<br>


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4.00<br>CL<br>1.27 TYP<br>0.65 TYP<br>8 7  6  5<br>0.63<br>2.52<br>1.60<br>2.15 KEEP OUT AREA<br>0.00 CL<br>4.16<br>1.21<br>2.13<br>2.31<br>3.15<br>1 2  3  4<br>0.63<br>0.59<br>3.18<br>5.10<br>2.00<br>0.00<br>1.18<br>**----- End of picture text -----**<br>


RECOMMENDED LAND PATTERN FOR SAWN / PUNCHED TYPE 

SIDE VIEW 

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0.10 C A B<br>0.05 C<br>0.65 3.16 0.70<br>0.38 2.80 0.36<br>0.45<br>0.25 1 2 3 4 1.34<br>(6X) 1.12<br>0.66±.05<br>2.25<br>4.08 2.05<br>3.70<br>1.02<br>0.65 8 7 6 5 0.82<br>0.38<br>0.44 0.61<br>(8X)<br>0.24 0.31<br>1.27<br>3.81<br>**----- End of picture text -----**<br>


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0.10 C<br>8X<br>0.08 C<br>0.35 0.05 C<br>1.10<br>0.90 0.15 0.00 SEATING<br>  PLANE<br>(SCALE: 2X)<br>**----- End of picture text -----**<br>


BOTTOM VIEW 

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5.10<br>0.10 C<br>4.90<br>(2X) SEE<br>PKG DETAIL B 0.35<br>CL 0.15<br>8 5<br>0.28<br>0.08<br>10°<br>PKG CL 6.25 5.90<br>5.90 5.70<br>1 4 0.10 C (SCALE: 2X)<br>(2X)<br>0.41<br>0.21 [(8X)]<br>TOP VIEW<br>**----- End of picture text -----**<br>


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5.00<br>4.80<br>SEE 0.10 C<br>DETAIL C<br>0.35<br>0.15<br>8X<br>0.08 C<br>C<br>SIDE VIEW<br>1.10 SEATING<br>0.90   PLANE<br>(SCALE: 2X)<br>**----- End of picture text -----**<br>


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0.65 3.16 0.70 0.10 C A B<br>0.38 2.80 0.36 0.05 C<br>0.45<br>0.25<br>1 2 3 4 1.34<br>(6X) 1.12<br>0.66±.05<br>4.08 2.25<br>3.70 2.05<br>1.02<br>0.65 8 7 6 5 0.82<br>0.38<br>0.44 0.61<br>(8X)<br>0.24 0.31<br>1.27<br>3.81<br>BOTTOM VIEW<br>**----- End of picture text -----**<br>


NOTES: UNLESS OTHERWISE SPECIFIED 

A) PACKAGE STANDARD REFERENCE: 

JEDEC REGISTRATION, MO-240, VARIATION AA. 

- B)  ALL DIMENSIONS ARE IN MILLIMETERS. 

- C)  DIMENSIONS DO NOT INCLUDE BURRS OR MOLD FLASH. MOLD FLASH OR BURRS DOES NOT EXCEED 0.10MM. 

- D)  DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994. 

- E)  IT IS RECOMMENDED TO HAVE NO TRACES OR VIAS WITHIN THE KEEP OUT AREA. 

- F)  DRAWING FILE NAME: PQFN08EREV6. 

- G) FAIRCHILD SEMICONDUCTOR 

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