FDMS008G-CA0

# **SD 3.0 Memory Card Specification (UHS-I)** 

**Version 1.7** 

Address: 28 Genting Lane, #09-03/04/05 Platinum 28, Singapore 349585 Tel : +65-6493 5035 Fax : +65-6493 5037 Website: http://www.flexxon.com Email: flexxon@flexxon.com 

ALL RIGHTS ARE STRICTLY RESERVED. ANY PORTION OF THIS PAPER SHALL NOT BE REPRODUCED, COPIED, OR TRANSLATED TO ANY OTHER FORMS WITHOUT PERMISSION FROM FLEXXON. 

## **Table of Contents** 

||**Table of Contents**|
|---|---|
|**1.**|**GENERAL DESCRIPTION ............................................................................. 3**|
|1.1.|Introduction ...................................................................................................................... 3|
|1.2.|Product Overview ............................................................................................................ 3|
|**2.**|**PRODUCT SPECIFICATIONS ........................................................................ 5**|
|2.1.|Performance ..................................................................................................................... 5|
|2.2.|Power ............................................................................................................................... 5|
|2.3.|MTBF ............................................................................................................................... 5|
|2.4.|Data Retention.................................................................................................................. 5|
|**3.**|**Environmental Specifications ..................................................................... 6**|
|**4.**|**Electrical Specifications .............................................................................. 7**|
|4.1.|DC Characteristics ........................................................................................................... 7|
|4.1.1.|Bus Operation Conditions for 3.3V Signaling ..................................................... 7|
|4.1.2.|Bus Signal Line Load ........................................................................................... 8|
|4.1.3.|Power Up Time of Host ....................................................................................... 9|
|4.1.4.|Power Up Time of Card ..................................................................................... 10|
|4.2.|AC Characteristic ........................................................................................................... 10|
|4.2.1.|SD Interface timing (Default) ............................................................................ 11|
|4.2.2.|SD Interface Timing (High-Speed Mode) .......................................................... 12|
|4.2.3.|SD Interface timing (SDR12, SDR25, SDR50 and SDR104 Modes) ............... 13|
|4.2.4.|SD Interface timing (DDR50 Modes) ................................................................ 15|
|**5.**|**pad assignment ......................................................................................... 17**|
|5.1.|Pad Assignment and Descriptions .................................................................................. 17|
|**6.**|**REGISTERS ................................................................................................ 18**|
|**7.**<br>**8.**|**Physical Dimension ................................................................................... 19**<br>**ORDERING INFORMATION ....................................................................... 20**|



## **1. GENERAL DESCRIPTION** 

## **1.1. Introduction** 

FLEXXON SD 3.0 card has high performance, good reliability and wide compatibility. It can alternate communication protocol between SD mode and SPI mode. It’s well adapted for hand-held applications in industrial/medical markets already. 

## **1.2. Product Overview** 

- **Capacity** 

   - ￭ 1GB up to 256GB 

- **Support SD system specification version 3.0** 

- **Support SD SPI mode** 

- **Copyrights Protection Mechanism** 

   - ￭ Compliant with the highest security of SDMI standard 

- **Support CPRM (Content Protection for Recordable Media) of SD Card** 

- **Card removal during read operation will never harm the content** 

- **Password Protection of cards (optional)** 

- **Write Protect feature using mechanical switch** 

- **Built-in write protection features (permanent and temporary)** 

- **Support Dynamic and Static Wear Leveling** 

 **Temperature Range** ￭ Operation: -25°C ~ 85°C ￭ Storage: -40°C ~ 85°C  **RoHS Compliant** 

3 

##  **Bus Speed Mode** 

- ￭ **Non-UHS mode** 

   - Default speed mode: 3.3V signaling, frequency up to 25MHz, up to 12.5MB/sec 

   - High speed mode: 3.3V signaling, frequency up to 50MHz, up to 25MB/sec 

- ￭ **UHS-I mode** 

   - SDR12: SDR up to 25MHz, 1.8V signaling 

   - SDR25: SDR up to 50MHz, 1.8V signaling 

   - SDR50: 1.8V signaling, frequency up to 100MHz, up to 50 MB/sec 

   - SDR104: 1.8V signaling, frequency up to 208MHz, up to 104 MB/sec 

   - DDR50: 1.8V signaling, frequency up to 50MHz, sampled on both clock edges, up to 50 MB/sec 

4 

## **2. PRODUCT SPECIFICATIONS** 

## **2.1. Performance** 

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Table 2-1 Max Performance of SD<br>**----- End of picture text -----**<br>


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Sequential<br>Read (MB/s)  Write (MB/s)<br>100  80<br>—<br>NOTES:<br>1. The performance is obtained from TestMetrix Test (@500MB).<br>**----- End of picture text -----**<br>


2. Performance may vary from flash configuration and platform. 

## **2.2. Power** 

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Table 2-2 Max Power Consumption of SD<br>**----- End of picture text -----**<br>


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Standby<br>Read (mA)  Write (mA)<br>(mA)<br>400  400  1<br>lt<br>2.3. MTBF<br>MTBF, an acronym for Mean Time Between Failures, is a measure of a device’s reliability. Its value represents<br>**----- End of picture text -----**<br>


the average time between a repair and the next failure. The higher the MTBF value, the higher the reliability 

of the device. The predicted result of FLEXXON’s SD is more than 2,000,000 hours. 

## **2.4. Data Retention** 

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 10 years if > 90% life remaining (@25C)<br>**----- End of picture text -----**<br>


- 1 year if < 10% life remaining (@25C) 

5 

## **3. ENVIRONMENTAL SPECIFICATIONS** 

|**Test Items**|**Test Conditions**|
|---|---|
|**Storage Temperature**|-40°C ~ 85°C|
|**Operating Temperature**|-25°C ~ 85°C|
|**Storage Humidity**|40°C, 95% RH|
|**Operating Humidity**|25°C, 95% RH|
|**Shock**|1500G, Half Sin Pulse Duration 0.5ms|
|**Vibration**|80Hz ~ 2000Hz/20G, 20Hz ~ 80Hz/1.52mm, 3 axis/30min|
|**Drop**|150cm free fall, 6 face of each unit|
|**Bending**|≥ 10N, Hold 1 min/5 times|
|**Torque**|0.1N-m or +/-2.5 deg, Hold 30 seconds/5 times|
|**ESD**|Contact: +/- 4KV each item 25 times<br>Air: +/- 8KV 10 times|



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## **4. ELECTRICAL SPECIFICATIONS** 

## **4.1. DC Characteristics** 

## **4.1.1. Bus Operation Conditions for 3.3V Signaling** 

**Table 4-1 Threshold Level for High Voltage Range** 

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|||||||
|---|---|---|---|---|---|
|Parameter|Symbol|Min.|Max|Unit|Condition|
|Supply Voltage|VDD|2.7|3.6|V|
|Output High Voltage|VOH|0.75*VDD|V|IOH=-2mA VDD Min|
|Output Low Voltage|VOL|0.125*VDD|V|IOL=2mA VDD Min|
|Input High Voltage|VIH|0.625*VDD|VDD+0.3|V|
|Input Low Voltage|VIL|VSS-0.3|0.25*VDD|V|
|Power Up Time|250|ms|From 0V to VDD min|
|Parameter|Symbol|Min.|Max|Unit|Condition|
|Supply Voltage|VDD|2.7|3.6|V|
|Regulator Voltage|VDDIO|1.7|1.95|V|Generated by VDD|
|Output High Voltage|VOH|1.4|-|V|IOH=-2mA|
|Output Low Voltage|VOL|-|0.45|V|IOL=2mA|
|Input High Voltage|VIH|1.27|2.00|V|
|Input Low Voltage|VIL|Vss-0.3|0.58|V|
|Parameter|Symbol|Min|Max.|Unit|Remarks|
|Input Leakage Current|-2|2|uA|DAT3 pull-up is|
|disconnected.|

**----- End of picture text -----**<br>


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**Table 4-2 Peak Voltage and Leakage Current** 

|**Parameter**|**Symbol**|**Min**|**Max.**|**Unit**|**Remarks**|
|---|---|---|---|---|---|
|Peak voltage on all lines||-0.3|VDD+0.3|V||
|**All Inputs**||||||
|Input Leakage Current||-10|10|uA||
|**All Outputs**||||||
|Output Leakage Current||-10|10|uA||



## **4.1.2. Bus Signal Line Load** 

## **Bus Operation Conditions – Signal Line’s Load** 

Total Bus Capacitance = CHOST + CBUS + N CCARD 

|**Parameter**|**symbol**|**Min**|**Max**|**Unit**|**Remark**|
|---|---|---|---|---|---|
|Pull-up resistance|RCMD<br>RDAT|10|100|kΩ|to prevent bus floating|
|Total bus capacitance for each signal<br>line|CL||40|pF|1 card<br>CHOST+CBUSshall<br>not exceed 30 pF|
|Card Capacitance for each signal pin|CCARD||101|pF||
|Maximum signal line inductance|||16|nH||
|Pull-up resistance inside card (pin1)|RDAT3|10|90|kΩ|May be used for card<br>detection|
|Capacity Connected to Power Line|CC||5|uF|To prevent inrush current|



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## **4.1.3. Power Up Time of Host** 

Host needs to keep power line level less than 0.5V and more than 1ms before power ramp up. 

- **Power On or Power Cycle** Followings are requirements for Power on and Power cycle to assure a reliable SD Card hard reset. (1) Voltage level shall be below 0.5V (2) Duration shall be at least 1ms. **Power Supply Ramp Up** 

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The power ramp up time is defined from 0.5V threshold level up to the operating supply voltage which is<br>stable between VDD (min.) and VDD (max.) and host can supply SDCLK.<br>Followings are recommendation of Power ramp up:<br>**----- End of picture text -----**<br>


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(1) Voltage of power ramp up should be monotonic as much as possible.<br>**----- End of picture text -----**<br>


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(2) The minimum ramp up time should be 0.1ms.<br>**----- End of picture text -----**<br>


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(3) The maximum ramp up time should be 35ms for 2.7-3.6V power supply.<br>(4) Host shall wait until VDD is stable.<br>(5) After 1ms VDD stable time, host provides at least 74 clocks before issuing the first command.<br>**----- End of picture text -----**<br>


## **Power Down and Power Cycle** 

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• When the host shuts down the power, the card VDD shall be lowered to less than 0.5Volt for a minimum<br>period of 1ms. During power down, DAT, CMD, and CLK should be disconnected or driven to logical 0 by<br>the host to avoid a situation that the operating current is drawn through the signal lines.<br>• If the host needs to change the operating voltage, a power cycle is required. Power cycle means the<br>power is turned off and supplied again. Power cycle is also needed for accessing cards that are already in<br>Inactive State.  To create a power cycle the host shall follow the power down description before power up<br>the card (i.e. the card VDD shall be once lowered to less than 0.5Volt for a minimum period of 1ms).<br>**----- End of picture text -----**<br>


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## **4.1.4. Power Up Time of Card** 

A device shall be ready to accept the first command within 1ms from detecting VDD min. 

Device may use up to 74 clocks for preparation before receiving the first command. 

## **4.2. AC Characteristic** 

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## **4.2.1. SD Interface timing (Default)** 

|**Parameter**|**Symbol**|**Min**|**Max**|**Unit**|**Remark**|
|---|---|---|---|---|---|
|**Clock CLK(All values are referred to min(VIH) and max(VIL)**||||||
|Clock frequency Data<br>Transfer Mode|fPP|0|25|MHz|Ccard≤ 10 pF<br>(1 card)|
|Clock frequency<br>Identification Mode|fOD|0(1)/100|400|KHz|Ccard≤ 10 pF<br> (1 card)|
|Clock low time|tWL|10||ns|Ccard≤ 10 pF<br> (1 card)|
|Clock high time|tWH|10||ns|Ccard≤ 10 pF<br> (1 card)|
|Clock rise time|tTLH||10|ns|Ccard≤ 10 pF<br> (1 card)|
|Clock fall time|tTHL||10|ns|Ccard≤ 10 pF<br> (1 card)|
|**Inputs CMD, DAT(referenced to CLK)**||||||
|Input set-uptime|tISU|5||ns|Ccard≤ 10pF|



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|,<br>™<br>LESON||||||
|---|---|---|---|---|---|
||||||(1 card)|
|Input hold time|tIH|5||ns|Ccard≤ 10 pF<br> (1 card)|
|**Outputs CMD, DAT(referenced to CLK)**||||||
|Output Delay time during<br>Data Transfer Mode|tODLY|0|14|ns|CL≤ 40 pF<br>(1 card)|
|Output Delay time during<br>Identification Mode|tODLY|0|50|ns|CL≤ 40 pF<br>(1 card)|



(1) 0Hz means to stop the clock. The given minimum frequency range is for cases where continues clock is required. 

## **4.2.2. SD Interface Timing (High-Speed Mode)** 

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|**Parameter**<br>~~es~~|**Symbol**<br>~~GG~~|**Min**<br>~~GG~~|**Max**<br>~~GG~~|**Unit**|**Remark**|
|---|---|---|---|---|---|
|**Clock CLK(All values are referred to min(VIH) and max(VIL)**<br>~~es GG~~<br>~~Ct~~||||||
|Clock frequency Data Transfer Mode<br>~~Ct~~|fPP<br>~~Ct~~|0<br>~~Ct~~|50<br>~~Ct~~|MHz<br>~~Ct~~|Ccard≤ 10 pF<br>(1 card)<br>~~Ct~~|
|Clock low time|tWL|7||ns|Ccard≤ 10 pF<br> (1 card)|
|Clock high time|tWH|7||ns|Ccard≤ 10 pF<br> (1 card)|
|Clock rise time|tTLH||3|ns|Ccard≤ 10 pF<br> (1 card)|
|Clock fall time|tTHL||3|ns<br>~~i,~~|Ccard≤ 10 pF<br> (1 card)<br>~~i,Se~~|
|**Inputs CMD, DAT(referenced to CLK)**<br>~~ee,~~<br>~~i,Se~~||||||
|Input set-up time<br>~~ee,~~|tISU<br>~~ee,~~|6<br>~~ee,~~|~~ee,~~|ns<br>~~ee,~~<br>~~i,~~|Ccard≤ 10 pF<br> (1 card)<br>~~ee,~~<br>~~i,Se~~|
|Input hold time|tIH|2|~~OD~~|ns|Ccard≤ 10 pF<br> (1 card)<br>~~ee~~|
|**Outputs CMD, DAT(referenced to CLK)**<br>~~eS,~~<br>~~OD~~<br>~~ee~~||||||
|Output Delay time during Data<br>Transfer Mode<br>~~eS,~~|tODLY<br>~~eS,~~|~~eS,~~|14<br>~~eS,~~<br>~~OD~~|ns<br>~~eS,~~|CL≤ 40 pF<br>(1 card)<br>~~eS,~~<br>~~ee~~|
|Output Hold time|TOH|2.5||ns|CL≤ 15 pF<br>(1 card)|
|Total System capacitance of each<br>line¹|CL||40|pF|CL ≤ 15 pF<br>(1 card)|



(1) In order to satisfy severe timing, the host shall drive only one card. 

## **4.2.3. SD Interface timing (SDR12, SDR25, SDR50 and SDR104 Modes)** 

## _**Input:**_ 

|**Symbol**|**Min**|**Max**|**Unit**|**Remark**|
|---|---|---|---|---|
|tCLK|4.80|-|ns|208MHz(Max.),Between risingedge,VCT= 0.975V|
|tCR, tCF|-|0.2* tCLK|ns|tCR, tCF< 0.96ns (max.) at 208MHz, CCARD=10pF<br>tCR, tCF< 2.00ns (max.) at 100MHz, CCARD=10pF<br>The absolute maximum value of tCR, tCFis 10ns<br>regardless of clock frequency|
|Clock Duty|30|70|%||



13 

## Clock Signal Timing 

## **SDR50 and SDR104 Input Timing:** 

|**Symbol**|**Min**|**Max**|**Unit**|**SDR104 Mode**|
|---|---|---|---|---|
|tIS|1.40|-|ns|CCARD=10pF,VCT= 0.975V|
|tIH|0.8|-|ns|CCARD= 5pF,VCT= 0.975V|
|**Symbol**|**Min**|**Max**|**Unit**|**SDR50 Mode**|
|tIS|3.00|-|ns|CCARD=10pF,VCT= 0.975V|
|tIH|0.8|-|ns|CCARD= 5pF,VCT= 0.975V|



## _**Output**_ **(SDR12, SDR25, SDR50)** _**:**_ 

|**Symbol**|**Min**|**Max**|**Unit**|**Remark**|
|---|---|---|---|---|
|tODLY|-|7.5|ns|tCLK>=10.0ns,CL=30pF,usingdriver Type B,for SDR50|
|tODLY|-|14|ns|tCLK>=20.0ns, CL=40pF, using driver Type B, for SDR25 and<br>SDR12,|
|TOH|1.5|-|ns|Hold time at the tODLY (min.),CL=15pF|



14 

## _**Output (SDR104 Mode):**_ 

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Symbol  Min  Max  Unit  Remark<br>tOP 0  2  Ul  Card Output Phase<br>△ tOP -350  +1550  ps  Delay variable due to temperature change after tuning<br>tODW 0.60  -  Ul  tODW = 2.88ns at 208MHz<br>**----- End of picture text -----**<br>


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4.2.4. SD Interface timing (DDR50 Modes)<br>**----- End of picture text -----**<br>


|**Symbol**|**Min**|**Max**|**Unit**|**Remark**|
|---|---|---|---|---|
|tCLK|20|-|ns|50MHz (Max.), Between rising edge|
|tCR, tCF|-|0.2* tCLK|ns|tCR, tCF< 4.00ns (max.) at 50MHz, CCARD=10pF|
|Clock Duty|45|55|%||



15 

|**Parameter**|**Symbol**|**Min**|**Max**|**Unit**|**Remark**|
|---|---|---|---|---|---|
|**Input CMD**(referenced to CLK risingedge)||||||
|Input set-up time|tISU|6|-|ns|Ccard≤ 10 pF<br> (1 card)|
|Input hold time|tIH|0.8|-|ns|Ccard≤ 10 pF<br> (1 card)|
|**Output CMD**(referenced to CLK risingedge)||||||
|Output Delay time<br>during Data Transfer<br>Mode|tODLY||13.7|ns|CL≤ 30 pF<br>(1 card)|
|Output Hold time|TOH|1.5|-|ns|CL≥ 15 pF<br>(1 card)|
|**Inputs DAT**(referenced to CLK risingand fallingedges)||||||
|Input set-up time|tISU2x|3|-|ns|Ccard≤ 10 pF<br> (1 card)|
|Input hold time|tIH2x|0.8|-|ns|Ccard≤ 10 pF<br> (1 card)|
|**Outputs DAT**(referenced to CLK risingand fallingedges)||||||
|Output Delay time<br>during Data Transfer<br>Mode|tODLY2x|-|7.0|ns|CL≤ 25 pF<br>(1 card)|
|Output Hold time|TOH2x|1.5|-|ns|CL≥ 15 pF<br>(1 card)|



16 

## **5. PAD ASSIGNMENT** 

## **5.1. Pad Assignment and Descriptions** 

**Table 5-1 SD Memory Card Pad Assignment** 

|**pin**|**SD Mode**|**SD Mode**|**SD Mode**|**SPI Mode**|**SPI Mode**|**SPI Mode**|
|---|---|---|---|---|---|---|
||**Name**|**Type1 **|**Description**|**Name**|**Type**|**Description**|
|**1**|CD/DAT3**2**|I/O/PP3|Card Detect/<br>Data Line[bit3]|CS|I3|Chip Select (net true)|
|**2**|CMD|PP|Command/Response|DI|I|Data In|
|**3**|VSS1|S|Supply voltage ground|VSS|S|Supply voltage ground|
|**4**|VDD|S|Supply voltage|VDD|S|Supply voltage|
|**5**|CLK|I|Clock|SCLK|I|Clock|
|**6**|VSS2|S|Supply voltage ground|VSS2|S|Supply voltage ground|
|**7**|DAT0|I/O/PP|Data Line[bit0]|DO|O/PP|Data Out|
|**8**|DAT1|I/O/PP|Data Line[bit1]|RSV|||
|**9**|DAT2|I/O/PP|Data Line[bit2]|RSV|||



- (1)  S: power supply, I: input; O: output using push-pull drivers; PP: I/O using push-pull drivers. 

- (2)  The extended DAT lines (DAT1-DAT3) are input on power up. They start to operate as DAT lines after SET_BUS_WIDTH command. The Host shall keep its own DAT1-DAT3 lines in input mode as well while they are not used. It is defined so in order to keep compatibility to MultiMedia Cards. 

- (3)  At power up, this line has a 50KOhm pull up enabled in the card. This resistor serves two functions: Card detection and Mode Selection. For Mode Selection, the host can drive the line high or let it be pulled high to select SD mode. If the host wants to select SPI mode, it should drive the line low. For Card detection, the host detects that the line is pulled high. This pull-up should be disconnected by the user during regular data transfer with SET_CLR_CARD_DETECT (ACMD42) command. SET_CLR_CARD_DETECT (ACMD42) command. 

17 

## **6. REGISTERS** 

|**Name**|**Width**|**Description**|
|---|---|---|
|CID|128bit|Card identification number; card individual number for identification.|
|RCA|16bit|Relative card address; local system address of a card, dynamically<br>suggested by the card and approved by the host during initialization.|
|DSR|16bit|Driver Stage Register; to configure the card’s output drivers.|
|CSD|128bit|Card Specific Data; Information about the card operation conditions.|
|SCR|64bit|SD Configuration Register; Information about the SD Memory Card's<br>Special Features capabilities|
|OCR|32bit|Operation conditions register.|
|SSR|512bit|SD Status; Information about the card proprietary features.|
|OCR|32bit|Card Status; Information about the card status.|



18 

## **7. PHYSICAL DIMENSION** 

**Dimension: 32mm(L) x 24mm(W) x 2.1mm(H)** 

19 

## **8. ORDERING INFORMATION** 

|**Capacity**|**MPN**|
|---|---|
|1GB|FDMS001G-C60|
|2GB|FDMS002G-C60|
|4GB|FDMS004G-CA0|
|8GB|FDMS008G-CA0|
|16GB|FDMS016G-CA0|
|32GB|FDMS032G-CA0|
|64GB|FDMS064G-CA0|
|128GB|FDMS128G-CA0|
|256GB|FDMS256G-CA0|



20 

## **Revision History** 

|**Revision**|**Release Date**|**Description**|
|---|---|---|
|1.0|2013/12|First release|
|1.1|2014/04|Modify Temperature Range|
|1.2|2014/06|Modify<br>Power<br>Consumption<br>&<br>Add<br>note<br>in<br>Temperature and humidity|
|1.3|2015/03|Add Ordering Information|
|1.4|2016/01|Add 128GB & 256GB|
|1.5|2017/04|Update Environmental Specifications|
|1.6|2020/04|Update ordering information|
|1.7|2020/08|Update Product Specification|



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